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// SPDX-License-Identifier: GPL-2.0
/*
* r8a7791 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2015-2017 Glider bvba
*
* Based on clk-rcar-gen2.c
*
* Copyright (C) 2013 Ideas On Board SPRL
*/
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen2-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A7791_CLK_OSC,
/* External Input Clocks */
CLK_EXTAL,
CLK_USB_EXTAL,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
CLK_PLL3,
CLK_PLL1_DIV2,
/* Module Clocks */
MOD_CLK_BASE
};
static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
/* Core Clock Outputs */
DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
DEF_BASE("qspi", R8A7791_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
DEF_BASE("rcan", R8A7791_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
DEF_FIXED("zg", R8A7791_CLK_ZG, CLK_PLL1, 3, 1),
DEF_FIXED("zx", R8A7791_CLK_ZX, CLK_PLL1, 3, 1),
DEF_FIXED("zs", R8A7791_CLK_ZS, CLK_PLL1, 6, 1),
DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1),
DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1),
DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1),
DEF_FIXED("lb", R8A7791_CLK_LB, CLK_PLL1, 24, 1),
DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1),
DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1),
DEF_FIXED("zb3", R8A7791_CLK_ZB3, CLK_PLL3, 4, 1),
DEF_FIXED("zb3d2", R8A7791_CLK_ZB3D2, CLK_PLL3, 8, 1),
DEF_FIXED("ddr", R8A7791_CLK_DDR, CLK_PLL3, 8, 1),
DEF_FIXED("mp", R8A7791_CLK_MP, CLK_PLL1_DIV2, 15, 1),
DEF_FIXED("cp", R8A7791_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("r", R8A7791_CLK_R, CLK_PLL1, 49152, 1),
DEF_FIXED("osc", R8A7791_CLK_OSC, CLK_PLL1, 12288, 1),
DEF_DIV6P1("sd2", R8A7791_CLK_SD2, CLK_PLL1_DIV2, 0x078),
DEF_DIV6P1("sd3", R8A7791_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
DEF_DIV6P1("mmc0", R8A7791_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
DEF_DIV6P1("ssp", R8A7791_CLK_SSP, CLK_PLL1_DIV2, 0x248),
DEF_DIV6P1("ssprs", R8A7791_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
};
static const struct mssr_mod_clk r8a7791_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7791_CLK_MP),
DEF_MOD("vcp0", 101, R8A7791_CLK_ZS),
DEF_MOD("vpc0", 103, R8A7791_CLK_ZS),
DEF_MOD("jpu", 106, R8A7791_CLK_M2),
DEF_MOD("ssp1", 109, R8A7791_CLK_ZS),
DEF_MOD("tmu1", 111, R8A7791_CLK_P),
DEF_MOD("3dg", 112, R8A7791_CLK_ZG),
DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS),
DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS),
DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS),
DEF_MOD("tmu3", 121, R8A7791_CLK_P),
DEF_MOD("tmu2", 122, R8A7791_CLK_P),
DEF_MOD("cmt0", 124, R8A7791_CLK_R),
DEF_MOD("tmu0", 125, R8A7791_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS),
DEF_MOD("vsps", 131, R8A7791_CLK_ZS),
DEF_MOD("scifa2", 202, R8A7791_CLK_MP),
DEF_MOD("scifa1", 203, R8A7791_CLK_MP),
DEF_MOD("scifa0", 204, R8A7791_CLK_MP),
DEF_MOD("msiof2", 205, R8A7791_CLK_MP),
DEF_MOD("scifb0", 206, R8A7791_CLK_MP),
DEF_MOD("scifb1", 207, R8A7791_CLK_MP),
DEF_MOD("msiof1", 208, R8A7791_CLK_MP),
DEF_MOD("scifb2", 216, R8A7791_CLK_MP),
DEF_MOD("sys-dmac1", 218, R8A7791_CLK_ZS),
DEF_MOD("sys-dmac0", 219, R8A7791_CLK_ZS),
DEF_MOD("tpu0", 304, R8A7791_CLK_CP),
DEF_MOD("sdhi3", 311, R8A7791_CLK_SD3),
DEF_MOD("sdhi2", 312, R8A7791_CLK_SD2),
DEF_MOD("sdhi0", 314, R8A7791_CLK_SD0),
DEF_MOD("mmcif0", 315, R8A7791_CLK_MMC0),
DEF_MOD("iic0", 318, R8A7791_CLK_HP),
DEF_MOD("pciec", 319, R8A7791_CLK_MP),
DEF_MOD("iic1", 323, R8A7791_CLK_HP),
DEF_MOD("usb3.0", 328, R8A7791_CLK_MP),
DEF_MOD("cmt1", 329, R8A7791_CLK_R),
DEF_MOD("usbhs-dmac0", 330, R8A7791_CLK_HP),
DEF_MOD("usbhs-dmac1", 331, R8A7791_CLK_HP),
DEF_MOD("rwdt", 402, R8A7791_CLK_R),
DEF_MOD("irqc", 407, R8A7791_CLK_CP),
DEF_MOD("intc-sys", 408, R8A7791_CLK_ZS),
DEF_MOD("audio-dmac1", 501, R8A7791_CLK_HP),
DEF_MOD("audio-dmac0", 502, R8A7791_CLK_HP),
DEF_MOD("adsp_mod", 506, R8A7791_CLK_ADSP),
DEF_MOD("thermal", 522, CLK_EXTAL),
DEF_MOD("pwm", 523, R8A7791_CLK_P),
DEF_MOD("usb-ehci", 703, R8A7791_CLK_MP),
DEF_MOD("usbhs", 704, R8A7791_CLK_HP),
DEF_MOD("hscif2", 713, R8A7791_CLK_ZS),
DEF_MOD("scif5", 714, R8A7791_CLK_P),
DEF_MOD("scif4", 715, R8A7791_CLK_P),
DEF_MOD("hscif1", 716, R8A7791_CLK_ZS),
DEF_MOD("hscif0", 717, R8A7791_CLK_ZS),
DEF_MOD("scif3", 718, R8A7791_CLK_P),
DEF_MOD("scif2", 719, R8A7791_CLK_P),
DEF_MOD("scif1", 720, R8A7791_CLK_P),
DEF_MOD("scif0", 721, R8A7791_CLK_P),
DEF_MOD("du1", 723, R8A7791_CLK_ZX),
DEF_MOD("du0", 724, R8A7791_CLK_ZX),
DEF_MOD("lvds0", 726, R8A7791_CLK_ZX),
DEF_MOD("ipmmu-sgx", 800, R8A7791_CLK_ZX),
DEF_MOD("mlb", 802, R8A7791_CLK_HP),
DEF_MOD("vin2", 809, R8A7791_CLK_ZG),
DEF_MOD("vin1", 810, R8A7791_CLK_ZG),
DEF_MOD("vin0", 811, R8A7791_CLK_ZG),
DEF_MOD("etheravb", 812, R8A7791_CLK_HP),
DEF_MOD("ether", 813, R8A7791_CLK_P),
DEF_MOD("sata1", 814, R8A7791_CLK_ZS),
DEF_MOD("sata0", 815, R8A7791_CLK_ZS),
DEF_MOD("gyro-adc", 901, R8A7791_CLK_P),
DEF_MOD("gpio7", 904, R8A7791_CLK_CP),
DEF_MOD("gpio6", 905, R8A7791_CLK_CP),
DEF_MOD("gpio5", 907, R8A7791_CLK_CP),
DEF_MOD("gpio4", 908, R8A7791_CLK_CP),
DEF_MOD("gpio3", 909, R8A7791_CLK_CP),
DEF_MOD("gpio2", 910, R8A7791_CLK_CP),
DEF_MOD("gpio1", 911, R8A7791_CLK_CP),
DEF_MOD("gpio0", 912, R8A7791_CLK_CP),
DEF_MOD("can1", 915, R8A7791_CLK_P),
DEF_MOD("can0", 916, R8A7791_CLK_P),
DEF_MOD("qspi_mod", 917, R8A7791_CLK_QSPI),
DEF_MOD("i2c5", 925, R8A7791_CLK_HP),
DEF_MOD("iicdvfs", 926, R8A7791_CLK_CP),
DEF_MOD("i2c4", 927, R8A7791_CLK_HP),
DEF_MOD("i2c3", 928, R8A7791_CLK_HP),
DEF_MOD("i2c2", 929, R8A7791_CLK_HP),
DEF_MOD("i2c1", 930, R8A7791_CLK_HP),
DEF_MOD("i2c0", 931, R8A7791_CLK_HP),
DEF_MOD("ssi-all", 1005, R8A7791_CLK_P),
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
DEF_MOD("scu-all", 1017, R8A7791_CLK_P),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
DEF_MOD("scifa3", 1106, R8A7791_CLK_MP),
DEF_MOD("scifa4", 1107, R8A7791_CLK_MP),
DEF_MOD("scifa5", 1108, R8A7791_CLK_MP),
};
static const unsigned int r8a7791_crit_mod_clks[] __initconst = {
MOD_CLK_ID(402), /* RWDT */
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL3
* 14 13 19 (MHz) *1 *1
*---------------------------------------------------
* 0 0 0 15 x172/2 x208/2 x106
* 0 0 1 15 x172/2 x208/2 x88
* 0 1 0 20 x130/2 x156/2 x80
* 0 1 1 20 x130/2 x156/2 x66
* 1 0 0 26 / 2 x200/2 x240/2 x122
* 1 0 1 26 / 2 x200/2 x240/2 x102
* 1 1 0 30 / 2 x172/2 x208/2 x106
* 1 1 1 30 / 2 x172/2 x208/2 x88
*
* *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
};
static int __init r8a7791_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
struct device_node *np = dev->of_node;
unsigned int i;
u32 cpg_mode;
int error;
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
if (of_device_is_compatible(np, "renesas,r8a7793-cpg-mssr")) {
/* R-Car M2-N uses a 1/5 divider for ZG */
for (i = 0; i < ARRAY_SIZE(r8a7791_core_clks); i++)
if (r8a7791_core_clks[i].id == R8A7791_CLK_ZG) {
r8a7791_core_clks[i].div = 5;
break;
}
}
return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
}
const struct cpg_mssr_info r8a7791_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a7791_core_clks,
.num_core_clks = ARRAY_SIZE(r8a7791_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a7791_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a7791_mod_clks),
.num_hw_mod_clks = 12 * 32,
/* Critical Module Clocks */
.crit_mod_clks = r8a7791_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a7791_crit_mod_clks),
/* Callbacks */
.init = r8a7791_cpg_mssr_init,
.cpg_clk_register = rcar_gen2_cpg_clk_register,
};
| linux-master | drivers/clk/renesas/r8a7791-cpg-mssr.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r8a779a0 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2020 Renesas Electronics Corp.
*
* Based on r8a7795-cpg-mssr.c
*
* Copyright (C) 2015 Glider bvba
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen4-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A779A0_CLK_OSC,
/* External Input Clocks */
CLK_EXTAL,
CLK_EXTALR,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL1,
CLK_PLL20,
CLK_PLL21,
CLK_PLL30,
CLK_PLL31,
CLK_PLL5,
CLK_PLL1_DIV2,
CLK_PLL20_DIV2,
CLK_PLL21_DIV2,
CLK_PLL30_DIV2,
CLK_PLL31_DIV2,
CLK_PLL5_DIV2,
CLK_PLL5_DIV4,
CLK_S1,
CLK_S3,
CLK_SDSRC,
CLK_RPCSRC,
CLK_OCO,
/* Module Clocks */
MOD_CLK_BASE
};
#define DEF_PLL(_name, _id, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
.offset = _offset)
static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
DEF_PLL(".pll20", CLK_PLL20, 0x0834),
DEF_PLL(".pll21", CLK_PLL21, 0x0838),
DEF_PLL(".pll30", CLK_PLL30, 0x083c),
DEF_PLL(".pll31", CLK_PLL31, 0x0840),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1),
DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1),
DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1),
DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1),
DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1),
DEF_RATE(".oco", CLK_OCO, 32768),
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
/* Core Clock Outputs */
DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0),
DEF_GEN4_Z("z1", R8A779A0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL21, 2, 8),
DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1),
DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1),
DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1),
DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1),
DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1),
DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1),
DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1),
DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1),
DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1),
DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1),
DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1),
DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1),
DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1),
DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1),
DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1),
DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1),
DEF_GEN4_SDH("sd0h", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870),
DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870),
DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
R8A779A0_CLK_RPC),
DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884),
DEF_GEN4_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
DEF_GEN4_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
};
static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2),
DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2),
DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2),
DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2),
DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2),
DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2),
DEF_MOD("canfd0", 328, R8A779A0_CLK_CANFD),
DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0),
DEF_MOD("du", 411, R8A779A0_CLK_S3D1),
DEF_MOD("dsi0", 415, R8A779A0_CLK_DSI),
DEF_MOD("dsi1", 416, R8A779A0_CLK_DSI),
DEF_MOD("fcpvd0", 508, R8A779A0_CLK_S3D1),
DEF_MOD("fcpvd1", 509, R8A779A0_CLK_S3D1),
DEF_MOD("hscif0", 514, R8A779A0_CLK_S1D2),
DEF_MOD("hscif1", 515, R8A779A0_CLK_S1D2),
DEF_MOD("hscif2", 516, R8A779A0_CLK_S1D2),
DEF_MOD("hscif3", 517, R8A779A0_CLK_S1D2),
DEF_MOD("i2c0", 518, R8A779A0_CLK_S1D4),
DEF_MOD("i2c1", 519, R8A779A0_CLK_S1D4),
DEF_MOD("i2c2", 520, R8A779A0_CLK_S1D4),
DEF_MOD("i2c3", 521, R8A779A0_CLK_S1D4),
DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4),
DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4),
DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4),
DEF_MOD("ispcs0", 612, R8A779A0_CLK_S1D1),
DEF_MOD("ispcs1", 613, R8A779A0_CLK_S1D1),
DEF_MOD("ispcs2", 614, R8A779A0_CLK_S1D1),
DEF_MOD("ispcs3", 615, R8A779A0_CLK_S1D1),
DEF_MOD("msi0", 618, R8A779A0_CLK_MSO),
DEF_MOD("msi1", 619, R8A779A0_CLK_MSO),
DEF_MOD("msi2", 620, R8A779A0_CLK_MSO),
DEF_MOD("msi3", 621, R8A779A0_CLK_MSO),
DEF_MOD("msi4", 622, R8A779A0_CLK_MSO),
DEF_MOD("msi5", 623, R8A779A0_CLK_MSO),
DEF_MOD("pwm0", 628, R8A779A0_CLK_S1D8),
DEF_MOD("rpc-if", 629, R8A779A0_CLK_RPCD2),
DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8),
DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8),
DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8),
DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8),
DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0),
DEF_MOD("sys-dmac1", 709, R8A779A0_CLK_S1D2),
DEF_MOD("sys-dmac2", 710, R8A779A0_CLK_S1D2),
DEF_MOD("tmu0", 713, R8A779A0_CLK_CL16MCK),
DEF_MOD("tmu1", 714, R8A779A0_CLK_S1D4),
DEF_MOD("tmu2", 715, R8A779A0_CLK_S1D4),
DEF_MOD("tmu3", 716, R8A779A0_CLK_S1D4),
DEF_MOD("tmu4", 717, R8A779A0_CLK_S1D4),
DEF_MOD("tpu0", 718, R8A779A0_CLK_S1D8),
DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1),
DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1),
DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1),
DEF_MOD("vin03", 801, R8A779A0_CLK_S1D1),
DEF_MOD("vin04", 802, R8A779A0_CLK_S1D1),
DEF_MOD("vin05", 803, R8A779A0_CLK_S1D1),
DEF_MOD("vin06", 804, R8A779A0_CLK_S1D1),
DEF_MOD("vin07", 805, R8A779A0_CLK_S1D1),
DEF_MOD("vin10", 806, R8A779A0_CLK_S1D1),
DEF_MOD("vin11", 807, R8A779A0_CLK_S1D1),
DEF_MOD("vin12", 808, R8A779A0_CLK_S1D1),
DEF_MOD("vin13", 809, R8A779A0_CLK_S1D1),
DEF_MOD("vin14", 810, R8A779A0_CLK_S1D1),
DEF_MOD("vin15", 811, R8A779A0_CLK_S1D1),
DEF_MOD("vin16", 812, R8A779A0_CLK_S1D1),
DEF_MOD("vin17", 813, R8A779A0_CLK_S1D1),
DEF_MOD("vin20", 814, R8A779A0_CLK_S1D1),
DEF_MOD("vin21", 815, R8A779A0_CLK_S1D1),
DEF_MOD("vin22", 816, R8A779A0_CLK_S1D1),
DEF_MOD("vin23", 817, R8A779A0_CLK_S1D1),
DEF_MOD("vin24", 818, R8A779A0_CLK_S1D1),
DEF_MOD("vin25", 819, R8A779A0_CLK_S1D1),
DEF_MOD("vin26", 820, R8A779A0_CLK_S1D1),
DEF_MOD("vin27", 821, R8A779A0_CLK_S1D1),
DEF_MOD("vin30", 822, R8A779A0_CLK_S1D1),
DEF_MOD("vin31", 823, R8A779A0_CLK_S1D1),
DEF_MOD("vin32", 824, R8A779A0_CLK_S1D1),
DEF_MOD("vin33", 825, R8A779A0_CLK_S1D1),
DEF_MOD("vin34", 826, R8A779A0_CLK_S1D1),
DEF_MOD("vin35", 827, R8A779A0_CLK_S1D1),
DEF_MOD("vin36", 828, R8A779A0_CLK_S1D1),
DEF_MOD("vin37", 829, R8A779A0_CLK_S1D1),
DEF_MOD("vspd0", 830, R8A779A0_CLK_S3D1),
DEF_MOD("vspd1", 831, R8A779A0_CLK_S3D1),
DEF_MOD("rwdt", 907, R8A779A0_CLK_R),
DEF_MOD("cmt0", 910, R8A779A0_CLK_R),
DEF_MOD("cmt1", 911, R8A779A0_CLK_R),
DEF_MOD("cmt2", 912, R8A779A0_CLK_R),
DEF_MOD("cmt3", 913, R8A779A0_CLK_R),
DEF_MOD("pfc0", 915, R8A779A0_CLK_CP),
DEF_MOD("pfc1", 916, R8A779A0_CLK_CP),
DEF_MOD("pfc2", 917, R8A779A0_CLK_CP),
DEF_MOD("pfc3", 918, R8A779A0_CLK_CP),
DEF_MOD("tsc", 919, R8A779A0_CLK_CL16MCK),
DEF_MOD("vspx0", 1028, R8A779A0_CLK_S1D1),
DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1),
DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1),
DEF_MOD("vspx3", 1031, R8A779A0_CLK_S1D1),
};
static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
MOD_CLK_ID(907), /* RWDT */
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
* 14 13 (MHz) 21 31
* ----------------------------------------------------------------
* 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16
* 0 1 20 x 1 x106 x180 x106 x120 x160 /19
* 1 0 Prohibited setting
* 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
{ 1, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 16, },
{ 1, 106, 1, 0, 0, 0, 0, 120, 1, 160, 1, 0, 0, 19, },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 32, },
};
static int __init r8a779a0_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
u32 cpg_mode;
int error;
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
}
const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a779a0_core_clks,
.num_core_clks = ARRAY_SIZE(r8a779a0_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a779a0_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks),
.num_hw_mod_clks = 15 * 32,
/* Critical Module Clocks */
.crit_mod_clks = r8a779a0_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a779a0_crit_mod_clks),
/* Callbacks */
.init = r8a779a0_cpg_mssr_init,
.cpg_clk_register = rcar_gen4_cpg_clk_register,
.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
};
| linux-master | drivers/clk/renesas/r8a779a0-cpg-mssr.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r8a77990 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* Based on r8a7795-cpg-mssr.c
*
* Copyright (C) 2015 Glider bvba
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A77990_CLK_CPEX,
/* External Input Clocks */
CLK_EXTAL,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
CLK_PLL3,
CLK_PLL0D4,
CLK_PLL0D6,
CLK_PLL0D8,
CLK_PLL0D20,
CLK_PLL0D24,
CLK_PLL1D2,
CLK_PE,
CLK_S0,
CLK_S1,
CLK_S2,
CLK_S3,
CLK_SDSRC,
CLK_RPCSRC,
CLK_RINT,
CLK_OCO,
/* Module Clocks */
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),
DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1),
DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1),
DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1),
DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1),
DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1),
DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1),
DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
/* Core Clock Outputs */
DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8),
DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1),
DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1),
DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1),
DEF_FIXED("s0d1", R8A77990_CLK_S0D1, CLK_S0, 1, 1),
DEF_FIXED("s0d3", R8A77990_CLK_S0D3, CLK_S0, 3, 1),
DEF_FIXED("s0d6", R8A77990_CLK_S0D6, CLK_S0, 6, 1),
DEF_FIXED("s0d12", R8A77990_CLK_S0D12, CLK_S0, 12, 1),
DEF_FIXED("s0d24", R8A77990_CLK_S0D24, CLK_S0, 24, 1),
DEF_FIXED("s1d1", R8A77990_CLK_S1D1, CLK_S1, 1, 1),
DEF_FIXED("s1d2", R8A77990_CLK_S1D2, CLK_S1, 2, 1),
DEF_FIXED("s1d4", R8A77990_CLK_S1D4, CLK_S1, 4, 1),
DEF_FIXED("s2d1", R8A77990_CLK_S2D1, CLK_S2, 1, 1),
DEF_FIXED("s2d2", R8A77990_CLK_S2D2, CLK_S2, 2, 1),
DEF_FIXED("s2d4", R8A77990_CLK_S2D4, CLK_S2, 4, 1),
DEF_FIXED("s3d1", R8A77990_CLK_S3D1, CLK_S3, 1, 1),
DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1),
DEF_GEN3_SDH("sd0h", R8A77990_CLK_SD0H, CLK_SDSRC, 0x0074),
DEF_GEN3_SDH("sd1h", R8A77990_CLK_SD1H, CLK_SDSRC, 0x0078),
DEF_GEN3_SDH("sd3h", R8A77990_CLK_SD3H, CLK_SDSRC, 0x026c),
DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, R8A77990_CLK_SD0H, 0x0074),
DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, R8A77990_CLK_SD1H, 0x0078),
DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, R8A77990_CLK_SD3H, 0x026c),
DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77990_CLK_RPC),
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1),
DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
DEF_DIV6_RO("osc", R8A77990_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014),
DEF_GEN3_RCKSEL("r", R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
};
static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A77990_CLK_S0D6C),
DEF_MOD("tmu3", 122, R8A77990_CLK_S3D2C),
DEF_MOD("tmu2", 123, R8A77990_CLK_S3D2C),
DEF_MOD("tmu1", 124, R8A77990_CLK_S3D2C),
DEF_MOD("tmu0", 125, R8A77990_CLK_CP),
DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C),
DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C),
DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C),
DEF_MOD("scif1", 206, R8A77990_CLK_S3D4C),
DEF_MOD("scif0", 207, R8A77990_CLK_S3D4C),
DEF_MOD("msiof3", 208, R8A77990_CLK_MSO),
DEF_MOD("msiof2", 209, R8A77990_CLK_MSO),
DEF_MOD("msiof1", 210, R8A77990_CLK_MSO),
DEF_MOD("msiof0", 211, R8A77990_CLK_MSO),
DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
DEF_MOD("sceg-pub", 229, R8A77990_CLK_CR),
DEF_MOD("cmt3", 300, R8A77990_CLK_R),
DEF_MOD("cmt2", 301, R8A77990_CLK_R),
DEF_MOD("cmt1", 302, R8A77990_CLK_R),
DEF_MOD("cmt0", 303, R8A77990_CLK_R),
DEF_MOD("scif2", 310, R8A77990_CLK_S3D4C),
DEF_MOD("sdif3", 311, R8A77990_CLK_SD3),
DEF_MOD("sdif1", 313, R8A77990_CLK_SD1),
DEF_MOD("sdif0", 314, R8A77990_CLK_SD0),
DEF_MOD("pcie0", 319, R8A77990_CLK_S3D1),
DEF_MOD("usb3-if0", 328, R8A77990_CLK_S3D1),
DEF_MOD("usb-dmac0", 330, R8A77990_CLK_S3D1),
DEF_MOD("usb-dmac1", 331, R8A77990_CLK_S3D1),
DEF_MOD("rwdt", 402, R8A77990_CLK_R),
DEF_MOD("intc-ex", 407, R8A77990_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
DEF_MOD("audmac0", 502, R8A77990_CLK_S1D2),
DEF_MOD("drif31", 508, R8A77990_CLK_S3D2),
DEF_MOD("drif30", 509, R8A77990_CLK_S3D2),
DEF_MOD("drif21", 510, R8A77990_CLK_S3D2),
DEF_MOD("drif20", 511, R8A77990_CLK_S3D2),
DEF_MOD("drif11", 512, R8A77990_CLK_S3D2),
DEF_MOD("drif10", 513, R8A77990_CLK_S3D2),
DEF_MOD("drif01", 514, R8A77990_CLK_S3D2),
DEF_MOD("drif00", 515, R8A77990_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C),
DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C),
DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C),
DEF_MOD("hscif1", 519, R8A77990_CLK_S3D1C),
DEF_MOD("hscif0", 520, R8A77990_CLK_S3D1C),
DEF_MOD("thermal", 522, R8A77990_CLK_CP),
DEF_MOD("pwm", 523, R8A77990_CLK_S3D4C),
DEF_MOD("fcpvd1", 602, R8A77990_CLK_S1D2),
DEF_MOD("fcpvd0", 603, R8A77990_CLK_S1D2),
DEF_MOD("fcpvb0", 607, R8A77990_CLK_S0D1),
DEF_MOD("fcpvi0", 611, R8A77990_CLK_S0D1),
DEF_MOD("fcpf0", 615, R8A77990_CLK_S0D1),
DEF_MOD("fcpcs", 619, R8A77990_CLK_S0D1),
DEF_MOD("vspd1", 622, R8A77990_CLK_S1D2),
DEF_MOD("vspd0", 623, R8A77990_CLK_S1D2),
DEF_MOD("vspb", 626, R8A77990_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
DEF_MOD("ehci0", 703, R8A77990_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A77990_CLK_S3D2),
DEF_MOD("cmm1", 710, R8A77990_CLK_S1D1),
DEF_MOD("cmm0", 711, R8A77990_CLK_S1D1),
DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
DEF_MOD("lvds", 727, R8A77990_CLK_S2D1),
DEF_MOD("mlp", 802, R8A77990_CLK_S2D1),
DEF_MOD("vin5", 806, R8A77990_CLK_S1D2),
DEF_MOD("vin4", 807, R8A77990_CLK_S1D2),
DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2),
DEF_MOD("gpio6", 906, R8A77990_CLK_S3D4),
DEF_MOD("gpio5", 907, R8A77990_CLK_S3D4),
DEF_MOD("gpio4", 908, R8A77990_CLK_S3D4),
DEF_MOD("gpio3", 909, R8A77990_CLK_S3D4),
DEF_MOD("gpio2", 910, R8A77990_CLK_S3D4),
DEF_MOD("gpio1", 911, R8A77990_CLK_S3D4),
DEF_MOD("gpio0", 912, R8A77990_CLK_S3D4),
DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4),
DEF_MOD("rpc-if", 917, R8A77990_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2),
DEF_MOD("adg", 922, R8A77990_CLK_ZA2),
DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP),
DEF_MOD("i2c4", 927, R8A77990_CLK_S3D2),
DEF_MOD("i2c3", 928, R8A77990_CLK_S3D2),
DEF_MOD("i2c2", 929, R8A77990_CLK_S3D2),
DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2),
DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2),
DEF_MOD("i2c7", 1003, R8A77990_CLK_S3D2),
DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4),
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
DEF_MOD("dab", 1016, R8A77990_CLK_S3D1),
DEF_MOD("scu-all", 1017, R8A77990_CLK_S3D4),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
static const unsigned int r8a77990_crit_mod_clks[] __initconst = {
MOD_CLK_ID(402), /* RWDT */
MOD_CLK_ID(408), /* INTC-AP (GIC) */
};
/*
* CPG Clock Data
*/
/*
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
*--------------------------------------------------------------------
* 0 48 x 1 x100/1 x100/3 x100/3
* 1 48 x 1 x100/1 x100/3 x58/3
*/
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 100, 3, 100, 3, },
{ 1, 100, 3, 58, 3, },
};
static int __init r8a77990_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
u32 cpg_mode;
int error;
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
}
const struct cpg_mssr_info r8a77990_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a77990_core_clks,
.num_core_clks = ARRAY_SIZE(r8a77990_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a77990_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a77990_mod_clks),
.num_hw_mod_clks = 12 * 32,
/* Critical Module Clocks */
.crit_mod_clks = r8a77990_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a77990_crit_mod_clks),
/* Callbacks */
.init = r8a77990_cpg_mssr_init,
.cpg_clk_register = rcar_gen3_cpg_clk_register,
};
| linux-master | drivers/clk/renesas/r8a77990-cpg-mssr.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r8a7740 Core CPG Clocks
*
* Copyright (C) 2014 Ulrich Hecht
*/
#include <linux/clk-provider.h>
#include <linux/clk/renesas.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/spinlock.h>
struct r8a7740_cpg {
struct clk_onecell_data data;
spinlock_t lock;
};
#define CPG_FRQCRA 0x00
#define CPG_FRQCRB 0x04
#define CPG_PLLC2CR 0x2c
#define CPG_USBCKCR 0x8c
#define CPG_FRQCRC 0xe0
#define CLK_ENABLE_ON_INIT BIT(0)
struct div4_clk {
const char *name;
unsigned int reg;
unsigned int shift;
int flags;
};
static struct div4_clk div4_clks[] = {
{ "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT },
{ "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT },
{ "b", CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT },
{ "m1", CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT },
{ "hp", CPG_FRQCRB, 4, 0 },
{ "hpp", CPG_FRQCRC, 20, 0 },
{ "usbp", CPG_FRQCRC, 16, 0 },
{ "s", CPG_FRQCRC, 12, 0 },
{ "zb", CPG_FRQCRC, 8, 0 },
{ "m3", CPG_FRQCRC, 4, 0 },
{ "cp", CPG_FRQCRC, 0, 0 },
{ NULL, 0, 0, 0 },
};
static const struct clk_div_table div4_div_table[] = {
{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
{ 6, 16 }, { 7, 18 }, { 8, 24 }, { 9, 32 }, { 10, 36 }, { 11, 48 },
{ 13, 72 }, { 14, 96 }, { 0, 0 }
};
static u32 cpg_mode __initdata;
static struct clk * __init
r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
void __iomem *base, const char *name)
{
const struct clk_div_table *table = NULL;
const char *parent_name;
unsigned int shift, reg;
unsigned int mult = 1;
unsigned int div = 1;
if (!strcmp(name, "r")) {
switch (cpg_mode & (BIT(2) | BIT(1))) {
case BIT(1) | BIT(2):
/* extal1 */
parent_name = of_clk_get_parent_name(np, 0);
div = 2048;
break;
case BIT(2):
/* extal1 */
parent_name = of_clk_get_parent_name(np, 0);
div = 1024;
break;
default:
/* extalr */
parent_name = of_clk_get_parent_name(np, 2);
break;
}
} else if (!strcmp(name, "system")) {
parent_name = of_clk_get_parent_name(np, 0);
if (cpg_mode & BIT(1))
div = 2;
} else if (!strcmp(name, "pllc0")) {
/* PLLC0/1 are configurable multiplier clocks. Register them as
* fixed factor clocks for now as there's no generic multiplier
* clock implementation and we currently have no need to change
* the multiplier value.
*/
u32 value = readl(base + CPG_FRQCRC);
parent_name = "system";
mult = ((value >> 24) & 0x7f) + 1;
} else if (!strcmp(name, "pllc1")) {
u32 value = readl(base + CPG_FRQCRA);
parent_name = "system";
mult = ((value >> 24) & 0x7f) + 1;
div = 2;
} else if (!strcmp(name, "pllc2")) {
u32 value = readl(base + CPG_PLLC2CR);
parent_name = "system";
mult = ((value >> 24) & 0x3f) + 1;
} else if (!strcmp(name, "usb24s")) {
u32 value = readl(base + CPG_USBCKCR);
if (value & BIT(7))
/* extal2 */
parent_name = of_clk_get_parent_name(np, 1);
else
parent_name = "system";
if (!(value & BIT(6)))
div = 2;
} else {
struct div4_clk *c;
for (c = div4_clks; c->name; c++) {
if (!strcmp(name, c->name)) {
parent_name = "pllc1";
table = div4_div_table;
reg = c->reg;
shift = c->shift;
break;
}
}
if (!c->name)
return ERR_PTR(-EINVAL);
}
if (!table) {
return clk_register_fixed_factor(NULL, name, parent_name, 0,
mult, div);
} else {
return clk_register_divider_table(NULL, name, parent_name, 0,
base + reg, shift, 4, 0,
table, &cpg->lock);
}
}
static void __init r8a7740_cpg_clocks_init(struct device_node *np)
{
struct r8a7740_cpg *cpg;
void __iomem *base;
struct clk **clks;
unsigned int i;
int num_clks;
if (of_property_read_u32(np, "renesas,mode", &cpg_mode))
pr_warn("%s: missing renesas,mode property\n", __func__);
num_clks = of_property_count_strings(np, "clock-output-names");
if (num_clks < 0) {
pr_err("%s: failed to count clocks\n", __func__);
return;
}
cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
if (cpg == NULL || clks == NULL) {
/* We're leaking memory on purpose, there's no point in cleaning
* up as the system won't boot anyway.
*/
return;
}
spin_lock_init(&cpg->lock);
cpg->data.clks = clks;
cpg->data.clk_num = num_clks;
base = of_iomap(np, 0);
if (WARN_ON(base == NULL))
return;
for (i = 0; i < num_clks; ++i) {
const char *name;
struct clk *clk;
of_property_read_string_index(np, "clock-output-names", i,
&name);
clk = r8a7740_cpg_register_clock(np, cpg, base, name);
if (IS_ERR(clk))
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
__func__, np, name, PTR_ERR(clk));
else
cpg->data.clks[i] = clk;
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
}
CLK_OF_DECLARE(r8a7740_cpg_clks, "renesas,r8a7740-cpg-clocks",
r8a7740_cpg_clocks_init);
| linux-master | drivers/clk/renesas/clk-r8a7740.c |
// SPDX-License-Identifier: GPL-2.0
/*
* RZ/A1 Core CPG Clocks
*
* Copyright (C) 2013 Ideas On Board SPRL
* Copyright (C) 2014 Wolfram Sang, Sang Engineering <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/clk/renesas.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#define CPG_FRQCR 0x10
#define CPG_FRQCR2 0x14
#define PPR0 0xFCFE3200
#define PIBC0 0xFCFE7000
#define MD_CLK(x) ((x >> 2) & 1) /* P0_2 */
/* -----------------------------------------------------------------------------
* Initialization
*/
static u16 __init rz_cpg_read_mode_pins(void)
{
void __iomem *ppr0, *pibc0;
u16 modes;
ppr0 = ioremap(PPR0, 2);
pibc0 = ioremap(PIBC0, 2);
BUG_ON(!ppr0 || !pibc0);
iowrite16(4, pibc0); /* enable input buffer */
modes = ioread16(ppr0);
iounmap(ppr0);
iounmap(pibc0);
return modes;
}
static struct clk * __init
rz_cpg_register_clock(struct device_node *np, void __iomem *base,
const char *name)
{
u32 val;
unsigned mult;
static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };
if (strcmp(name, "pll") == 0) {
unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());
const char *parent_name = of_clk_get_parent_name(np, cpg_mode);
mult = cpg_mode ? (32 / 4) : 30;
return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
}
/* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
if (!base)
return ERR_PTR(-ENXIO);
/* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
* and the constraint that always g <= i. To get the rz platform started,
* let them run at fixed current speed and implement the details later.
*/
if (strcmp(name, "i") == 0)
val = (readl(base + CPG_FRQCR) >> 8) & 3;
else if (strcmp(name, "g") == 0)
val = readl(base + CPG_FRQCR2) & 3;
else
return ERR_PTR(-EINVAL);
mult = frqcr_tab[val];
return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3);
}
static void __init rz_cpg_clocks_init(struct device_node *np)
{
struct clk_onecell_data *data;
struct clk **clks;
void __iomem *base;
unsigned i;
int num_clks;
num_clks = of_property_count_strings(np, "clock-output-names");
if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
return;
data = kzalloc(sizeof(*data), GFP_KERNEL);
clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
BUG_ON(!data || !clks);
data->clks = clks;
data->clk_num = num_clks;
base = of_iomap(np, 0);
for (i = 0; i < num_clks; ++i) {
const char *name;
struct clk *clk;
of_property_read_string_index(np, "clock-output-names", i, &name);
clk = rz_cpg_register_clock(np, base, name);
if (IS_ERR(clk))
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
__func__, np, name, PTR_ERR(clk));
else
data->clks[i] = clk;
}
of_clk_add_provider(np, of_clk_src_onecell_get, data);
cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
| linux-master | drivers/clk/renesas/clk-rz.c |
// SPDX-License-Identifier: GPL-2.0
/*
* RZ/G2L Clock Pulse Generator
*
* Copyright (C) 2021 Renesas Electronics Corp.
*
* Based on renesas-cpg-mssr.c
*
* Copyright (C) 2015 Glider bvba
* Copyright (C) 2013 Ideas On Board SPRL
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clk/renesas.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/iopoll.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <linux/units.h>
#include <dt-bindings/clock/renesas-cpg-mssr.h>
#include "rzg2l-cpg.h"
#ifdef DEBUG
#define WARN_DEBUG(x) WARN_ON(x)
#else
#define WARN_DEBUG(x) do { } while (0)
#endif
#define DIV_RSMASK(v, s, m) ((v >> s) & m)
#define GET_SHIFT(val) ((val >> 12) & 0xff)
#define GET_WIDTH(val) ((val >> 8) & 0xf)
#define KDIV(val) DIV_RSMASK(val, 16, 0xffff)
#define MDIV(val) DIV_RSMASK(val, 6, 0x3ff)
#define PDIV(val) DIV_RSMASK(val, 0, 0x3f)
#define SDIV(val) DIV_RSMASK(val, 0, 0x7)
#define CLK_ON_R(reg) (reg)
#define CLK_MON_R(reg) (0x180 + (reg))
#define CLK_RST_R(reg) (reg)
#define CLK_MRST_R(reg) (0x180 + (reg))
#define GET_REG_OFFSET(val) ((val >> 20) & 0xfff)
#define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff)
#define GET_REG_SAMPLL_CLK2(val) ((val >> 12) & 0xfff)
#define MAX_VCLK_FREQ (148500000)
struct sd_hw_data {
struct clk_hw hw;
u32 conf;
struct rzg2l_cpg_priv *priv;
};
#define to_sd_hw_data(_hw) container_of(_hw, struct sd_hw_data, hw)
struct rzg2l_pll5_param {
u32 pl5_fracin;
u8 pl5_refdiv;
u8 pl5_intin;
u8 pl5_postdiv1;
u8 pl5_postdiv2;
u8 pl5_spread;
};
struct rzg2l_pll5_mux_dsi_div_param {
u8 clksrc;
u8 dsi_div_a;
u8 dsi_div_b;
};
/**
* struct rzg2l_cpg_priv - Clock Pulse Generator Private Data
*
* @rcdev: Reset controller entity
* @dev: CPG device
* @base: CPG register block base address
* @rmw_lock: protects register accesses
* @clks: Array containing all Core and Module Clocks
* @num_core_clks: Number of Core Clocks in clks[]
* @num_mod_clks: Number of Module Clocks in clks[]
* @num_resets: Number of Module Resets in info->resets[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
* @info: Pointer to platform data
* @genpd: PM domain
* @mux_dsi_div_params: pll5 mux and dsi div parameters
*/
struct rzg2l_cpg_priv {
struct reset_controller_dev rcdev;
struct device *dev;
void __iomem *base;
spinlock_t rmw_lock;
struct clk **clks;
unsigned int num_core_clks;
unsigned int num_mod_clks;
unsigned int num_resets;
unsigned int last_dt_core_clk;
const struct rzg2l_cpg_info *info;
struct generic_pm_domain genpd;
struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
};
static void rzg2l_cpg_del_clk_provider(void *data)
{
of_clk_del_provider(data);
}
static struct clk * __init
rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core,
struct clk **clks,
void __iomem *base,
struct rzg2l_cpg_priv *priv)
{
struct device *dev = priv->dev;
const struct clk *parent;
const char *parent_name;
struct clk_hw *clk_hw;
parent = clks[core->parent & 0xffff];
if (IS_ERR(parent))
return ERR_CAST(parent);
parent_name = __clk_get_name(parent);
if (core->dtable)
clk_hw = clk_hw_register_divider_table(dev, core->name,
parent_name, 0,
base + GET_REG_OFFSET(core->conf),
GET_SHIFT(core->conf),
GET_WIDTH(core->conf),
core->flag,
core->dtable,
&priv->rmw_lock);
else
clk_hw = clk_hw_register_divider(dev, core->name,
parent_name, 0,
base + GET_REG_OFFSET(core->conf),
GET_SHIFT(core->conf),
GET_WIDTH(core->conf),
core->flag, &priv->rmw_lock);
if (IS_ERR(clk_hw))
return ERR_CAST(clk_hw);
return clk_hw->clk;
}
static struct clk * __init
rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core,
void __iomem *base,
struct rzg2l_cpg_priv *priv)
{
const struct clk_hw *clk_hw;
clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
core->parent_names, core->num_parents,
core->flag,
base + GET_REG_OFFSET(core->conf),
GET_SHIFT(core->conf),
GET_WIDTH(core->conf),
core->mux_flags, &priv->rmw_lock);
if (IS_ERR(clk_hw))
return ERR_CAST(clk_hw);
return clk_hw->clk;
}
static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct sd_hw_data *hwdata = to_sd_hw_data(hw);
struct rzg2l_cpg_priv *priv = hwdata->priv;
u32 off = GET_REG_OFFSET(hwdata->conf);
u32 shift = GET_SHIFT(hwdata->conf);
const u32 clk_src_266 = 2;
u32 bitmask;
/*
* As per the HW manual, we should not directly switch from 533 MHz to
* 400 MHz and vice versa. To change the setting from 2’b01 (533 MHz)
* to 2’b10 (400 MHz) or vice versa, Switch to 2’b11 (266 MHz) first,
* and then switch to the target setting (2’b01 (533 MHz) or 2’b10
* (400 MHz)).
* Setting a value of '0' to the SEL_SDHI0_SET or SEL_SDHI1_SET clock
* switching register is prohibited.
* The clock mux has 3 input clocks(533 MHz, 400 MHz, and 266 MHz), and
* the index to value mapping is done by adding 1 to the index.
*/
bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;
if (index != clk_src_266) {
u32 msk, val;
int ret;
writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off);
msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
!(val & msk), 100,
CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
if (ret) {
dev_err(priv->dev, "failed to switch clk source\n");
return ret;
}
}
writel(bitmask | ((index + 1) << shift), priv->base + off);
return 0;
}
static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)
{
struct sd_hw_data *hwdata = to_sd_hw_data(hw);
struct rzg2l_cpg_priv *priv = hwdata->priv;
u32 val = readl(priv->base + GET_REG_OFFSET(hwdata->conf));
val >>= GET_SHIFT(hwdata->conf);
val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0);
if (val) {
val--;
} else {
/* Prohibited clk source, change it to 533 MHz(reset value) */
rzg2l_cpg_sd_clk_mux_set_parent(hw, 0);
}
return val;
}
static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = {
.determine_rate = __clk_mux_determine_rate_closest,
.set_parent = rzg2l_cpg_sd_clk_mux_set_parent,
.get_parent = rzg2l_cpg_sd_clk_mux_get_parent,
};
static struct clk * __init
rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
void __iomem *base,
struct rzg2l_cpg_priv *priv)
{
struct sd_hw_data *clk_hw_data;
struct clk_init_data init;
struct clk_hw *clk_hw;
int ret;
clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
if (!clk_hw_data)
return ERR_PTR(-ENOMEM);
clk_hw_data->priv = priv;
clk_hw_data->conf = core->conf;
init.name = GET_SHIFT(core->conf) ? "sd1" : "sd0";
init.ops = &rzg2l_cpg_sd_clk_mux_ops;
init.flags = 0;
init.num_parents = core->num_parents;
init.parent_names = core->parent_names;
clk_hw = &clk_hw_data->hw;
clk_hw->init = &init;
ret = devm_clk_hw_register(priv->dev, clk_hw);
if (ret)
return ERR_PTR(ret);
return clk_hw->clk;
}
static unsigned long
rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params,
unsigned long rate)
{
unsigned long foutpostdiv_rate;
params->pl5_intin = rate / MEGA;
params->pl5_fracin = div_u64(((u64)rate % MEGA) << 24, MEGA);
params->pl5_refdiv = 2;
params->pl5_postdiv1 = 1;
params->pl5_postdiv2 = 1;
params->pl5_spread = 0x16;
foutpostdiv_rate =
EXTAL_FREQ_IN_MEGA_HZ * MEGA / params->pl5_refdiv *
((((params->pl5_intin << 24) + params->pl5_fracin)) >> 24) /
(params->pl5_postdiv1 * params->pl5_postdiv2);
return foutpostdiv_rate;
}
struct dsi_div_hw_data {
struct clk_hw hw;
u32 conf;
unsigned long rate;
struct rzg2l_cpg_priv *priv;
};
#define to_dsi_div_hw_data(_hw) container_of(_hw, struct dsi_div_hw_data, hw)
static unsigned long rzg2l_cpg_dsi_div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
unsigned long rate = dsi_div->rate;
if (!rate)
rate = parent_rate;
return rate;
}
static unsigned long rzg2l_cpg_get_vclk_parent_rate(struct clk_hw *hw,
unsigned long rate)
{
struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
struct rzg2l_cpg_priv *priv = dsi_div->priv;
struct rzg2l_pll5_param params;
unsigned long parent_rate;
parent_rate = rzg2l_cpg_get_foutpostdiv_rate(¶ms, rate);
if (priv->mux_dsi_div_params.clksrc)
parent_rate /= 2;
return parent_rate;
}
static int rzg2l_cpg_dsi_div_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
if (req->rate > MAX_VCLK_FREQ)
req->rate = MAX_VCLK_FREQ;
req->best_parent_rate = rzg2l_cpg_get_vclk_parent_rate(hw, req->rate);
return 0;
}
static int rzg2l_cpg_dsi_div_set_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate)
{
struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
struct rzg2l_cpg_priv *priv = dsi_div->priv;
/*
* MUX -->DIV_DSI_{A,B} -->M3 -->VCLK
*
* Based on the dot clock, the DSI divider clock sets the divider value,
* calculates the pll parameters for generating FOUTPOSTDIV and the clk
* source for the MUX and propagates that info to the parents.
*/
if (!rate || rate > MAX_VCLK_FREQ)
return -EINVAL;
dsi_div->rate = rate;
writel(CPG_PL5_SDIV_DIV_DSI_A_WEN | CPG_PL5_SDIV_DIV_DSI_B_WEN |
(priv->mux_dsi_div_params.dsi_div_a << 0) |
(priv->mux_dsi_div_params.dsi_div_b << 8),
priv->base + CPG_PL5_SDIV);
return 0;
}
static const struct clk_ops rzg2l_cpg_dsi_div_ops = {
.recalc_rate = rzg2l_cpg_dsi_div_recalc_rate,
.determine_rate = rzg2l_cpg_dsi_div_determine_rate,
.set_rate = rzg2l_cpg_dsi_div_set_rate,
};
static struct clk * __init
rzg2l_cpg_dsi_div_clk_register(const struct cpg_core_clk *core,
struct clk **clks,
struct rzg2l_cpg_priv *priv)
{
struct dsi_div_hw_data *clk_hw_data;
const struct clk *parent;
const char *parent_name;
struct clk_init_data init;
struct clk_hw *clk_hw;
int ret;
parent = clks[core->parent & 0xffff];
if (IS_ERR(parent))
return ERR_CAST(parent);
clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
if (!clk_hw_data)
return ERR_PTR(-ENOMEM);
clk_hw_data->priv = priv;
parent_name = __clk_get_name(parent);
init.name = core->name;
init.ops = &rzg2l_cpg_dsi_div_ops;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = &parent_name;
init.num_parents = 1;
clk_hw = &clk_hw_data->hw;
clk_hw->init = &init;
ret = devm_clk_hw_register(priv->dev, clk_hw);
if (ret)
return ERR_PTR(ret);
return clk_hw->clk;
}
struct pll5_mux_hw_data {
struct clk_hw hw;
u32 conf;
unsigned long rate;
struct rzg2l_cpg_priv *priv;
};
#define to_pll5_mux_hw_data(_hw) container_of(_hw, struct pll5_mux_hw_data, hw)
static int rzg2l_cpg_pll5_4_clk_mux_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_hw *parent;
struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw);
struct rzg2l_cpg_priv *priv = hwdata->priv;
parent = clk_hw_get_parent_by_index(hw, priv->mux_dsi_div_params.clksrc);
req->best_parent_hw = parent;
req->best_parent_rate = req->rate;
return 0;
}
static int rzg2l_cpg_pll5_4_clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw);
struct rzg2l_cpg_priv *priv = hwdata->priv;
/*
* FOUTPOSTDIV--->|
* | | -->MUX -->DIV_DSIA_B -->M3 -->VCLK
* |--FOUT1PH0-->|
*
* Based on the dot clock, the DSI divider clock calculates the parent
* rate and clk source for the MUX. It propagates that info to
* pll5_4_clk_mux which sets the clock source for DSI divider clock.
*/
writel(CPG_OTHERFUNC1_REG_RES0_ON_WEN | index,
priv->base + CPG_OTHERFUNC1_REG);
return 0;
}
static u8 rzg2l_cpg_pll5_4_clk_mux_get_parent(struct clk_hw *hw)
{
struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw);
struct rzg2l_cpg_priv *priv = hwdata->priv;
return readl(priv->base + GET_REG_OFFSET(hwdata->conf));
}
static const struct clk_ops rzg2l_cpg_pll5_4_clk_mux_ops = {
.determine_rate = rzg2l_cpg_pll5_4_clk_mux_determine_rate,
.set_parent = rzg2l_cpg_pll5_4_clk_mux_set_parent,
.get_parent = rzg2l_cpg_pll5_4_clk_mux_get_parent,
};
static struct clk * __init
rzg2l_cpg_pll5_4_mux_clk_register(const struct cpg_core_clk *core,
struct rzg2l_cpg_priv *priv)
{
struct pll5_mux_hw_data *clk_hw_data;
struct clk_init_data init;
struct clk_hw *clk_hw;
int ret;
clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
if (!clk_hw_data)
return ERR_PTR(-ENOMEM);
clk_hw_data->priv = priv;
clk_hw_data->conf = core->conf;
init.name = core->name;
init.ops = &rzg2l_cpg_pll5_4_clk_mux_ops;
init.flags = CLK_SET_RATE_PARENT;
init.num_parents = core->num_parents;
init.parent_names = core->parent_names;
clk_hw = &clk_hw_data->hw;
clk_hw->init = &init;
ret = devm_clk_hw_register(priv->dev, clk_hw);
if (ret)
return ERR_PTR(ret);
return clk_hw->clk;
}
struct sipll5 {
struct clk_hw hw;
u32 conf;
unsigned long foutpostdiv_rate;
struct rzg2l_cpg_priv *priv;
};
#define to_sipll5(_hw) container_of(_hw, struct sipll5, hw)
static unsigned long rzg2l_cpg_get_vclk_rate(struct clk_hw *hw,
unsigned long rate)
{
struct sipll5 *sipll5 = to_sipll5(hw);
struct rzg2l_cpg_priv *priv = sipll5->priv;
unsigned long vclk;
vclk = rate / ((1 << priv->mux_dsi_div_params.dsi_div_a) *
(priv->mux_dsi_div_params.dsi_div_b + 1));
if (priv->mux_dsi_div_params.clksrc)
vclk /= 2;
return vclk;
}
static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct sipll5 *sipll5 = to_sipll5(hw);
unsigned long pll5_rate = sipll5->foutpostdiv_rate;
if (!pll5_rate)
pll5_rate = parent_rate;
return pll5_rate;
}
static long rzg2l_cpg_sipll5_round_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long *parent_rate)
{
return rate;
}
static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate)
{
struct sipll5 *sipll5 = to_sipll5(hw);
struct rzg2l_cpg_priv *priv = sipll5->priv;
struct rzg2l_pll5_param params;
unsigned long vclk_rate;
int ret;
u32 val;
/*
* OSC --> PLL5 --> FOUTPOSTDIV-->|
* | | -->MUX -->DIV_DSIA_B -->M3 -->VCLK
* |--FOUT1PH0-->|
*
* Based on the dot clock, the DSI divider clock calculates the parent
* rate and the pll5 parameters for generating FOUTPOSTDIV. It propagates
* that info to sipll5 which sets parameters for generating FOUTPOSTDIV.
*
* OSC --> PLL5 --> FOUTPOSTDIV
*/
if (!rate)
return -EINVAL;
vclk_rate = rzg2l_cpg_get_vclk_rate(hw, rate);
sipll5->foutpostdiv_rate =
rzg2l_cpg_get_foutpostdiv_rate(¶ms, vclk_rate);
/* Put PLL5 into standby mode */
writel(CPG_SIPLL5_STBY_RESETB_WEN, priv->base + CPG_SIPLL5_STBY);
ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val,
!(val & CPG_SIPLL5_MON_PLL5_LOCK), 100, 250000);
if (ret) {
dev_err(priv->dev, "failed to release pll5 lock");
return ret;
}
/* Output clock setting 1 */
writel((params.pl5_postdiv1 << 0) | (params.pl5_postdiv2 << 4) |
(params.pl5_refdiv << 8), priv->base + CPG_SIPLL5_CLK1);
/* Output clock setting, SSCG modulation value setting 3 */
writel((params.pl5_fracin << 8), priv->base + CPG_SIPLL5_CLK3);
/* Output clock setting 4 */
writel(CPG_SIPLL5_CLK4_RESV_LSB | (params.pl5_intin << 16),
priv->base + CPG_SIPLL5_CLK4);
/* Output clock setting 5 */
writel(params.pl5_spread, priv->base + CPG_SIPLL5_CLK5);
/* PLL normal mode setting */
writel(CPG_SIPLL5_STBY_DOWNSPREAD_WEN | CPG_SIPLL5_STBY_SSCG_EN_WEN |
CPG_SIPLL5_STBY_RESETB_WEN | CPG_SIPLL5_STBY_RESETB,
priv->base + CPG_SIPLL5_STBY);
/* PLL normal mode transition, output clock stability check */
ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val,
(val & CPG_SIPLL5_MON_PLL5_LOCK), 100, 250000);
if (ret) {
dev_err(priv->dev, "failed to lock pll5");
return ret;
}
return 0;
}
static const struct clk_ops rzg2l_cpg_sipll5_ops = {
.recalc_rate = rzg2l_cpg_sipll5_recalc_rate,
.round_rate = rzg2l_cpg_sipll5_round_rate,
.set_rate = rzg2l_cpg_sipll5_set_rate,
};
static struct clk * __init
rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
struct clk **clks,
struct rzg2l_cpg_priv *priv)
{
const struct clk *parent;
struct clk_init_data init;
const char *parent_name;
struct sipll5 *sipll5;
struct clk_hw *clk_hw;
int ret;
parent = clks[core->parent & 0xffff];
if (IS_ERR(parent))
return ERR_CAST(parent);
sipll5 = devm_kzalloc(priv->dev, sizeof(*sipll5), GFP_KERNEL);
if (!sipll5)
return ERR_PTR(-ENOMEM);
init.name = core->name;
parent_name = __clk_get_name(parent);
init.ops = &rzg2l_cpg_sipll5_ops;
init.flags = 0;
init.parent_names = &parent_name;
init.num_parents = 1;
sipll5->hw.init = &init;
sipll5->conf = core->conf;
sipll5->priv = priv;
writel(CPG_SIPLL5_STBY_SSCG_EN_WEN | CPG_SIPLL5_STBY_RESETB_WEN |
CPG_SIPLL5_STBY_RESETB, priv->base + CPG_SIPLL5_STBY);
clk_hw = &sipll5->hw;
clk_hw->init = &init;
ret = devm_clk_hw_register(priv->dev, clk_hw);
if (ret)
return ERR_PTR(ret);
priv->mux_dsi_div_params.clksrc = 1; /* Use clk src 1 for DSI */
priv->mux_dsi_div_params.dsi_div_a = 1; /* Divided by 2 */
priv->mux_dsi_div_params.dsi_div_b = 2; /* Divided by 3 */
return clk_hw->clk;
}
struct pll_clk {
struct clk_hw hw;
unsigned int conf;
unsigned int type;
void __iomem *base;
struct rzg2l_cpg_priv *priv;
};
#define to_pll(_hw) container_of(_hw, struct pll_clk, hw)
static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct pll_clk *pll_clk = to_pll(hw);
struct rzg2l_cpg_priv *priv = pll_clk->priv;
unsigned int val1, val2;
unsigned int mult = 1;
unsigned int div = 1;
if (pll_clk->type != CLK_TYPE_SAM_PLL)
return parent_rate;
val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));
mult = MDIV(val1) + KDIV(val1) / 65536;
div = PDIV(val1) << SDIV(val2);
return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div);
}
static const struct clk_ops rzg2l_cpg_pll_ops = {
.recalc_rate = rzg2l_cpg_pll_clk_recalc_rate,
};
static struct clk * __init
rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
struct clk **clks,
void __iomem *base,
struct rzg2l_cpg_priv *priv)
{
struct device *dev = priv->dev;
const struct clk *parent;
struct clk_init_data init;
const char *parent_name;
struct pll_clk *pll_clk;
parent = clks[core->parent & 0xffff];
if (IS_ERR(parent))
return ERR_CAST(parent);
pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
if (!pll_clk)
return ERR_PTR(-ENOMEM);
parent_name = __clk_get_name(parent);
init.name = core->name;
init.ops = &rzg2l_cpg_pll_ops;
init.flags = 0;
init.parent_names = &parent_name;
init.num_parents = 1;
pll_clk->hw.init = &init;
pll_clk->conf = core->conf;
pll_clk->base = base;
pll_clk->priv = priv;
pll_clk->type = core->type;
return clk_register(NULL, &pll_clk->hw);
}
static struct clk
*rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
void *data)
{
unsigned int clkidx = clkspec->args[1];
struct rzg2l_cpg_priv *priv = data;
struct device *dev = priv->dev;
const char *type;
struct clk *clk;
switch (clkspec->args[0]) {
case CPG_CORE:
type = "core";
if (clkidx > priv->last_dt_core_clk) {
dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
return ERR_PTR(-EINVAL);
}
clk = priv->clks[clkidx];
break;
case CPG_MOD:
type = "module";
if (clkidx >= priv->num_mod_clks) {
dev_err(dev, "Invalid %s clock index %u\n", type,
clkidx);
return ERR_PTR(-EINVAL);
}
clk = priv->clks[priv->num_core_clks + clkidx];
break;
default:
dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
return ERR_PTR(-EINVAL);
}
if (IS_ERR(clk))
dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
PTR_ERR(clk));
else
dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
clkspec->args[0], clkspec->args[1], clk,
clk_get_rate(clk));
return clk;
}
static void __init
rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
const struct rzg2l_cpg_info *info,
struct rzg2l_cpg_priv *priv)
{
struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent;
struct device *dev = priv->dev;
unsigned int id = core->id, div = core->div;
const char *parent_name;
WARN_DEBUG(id >= priv->num_core_clks);
WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
if (!core->name) {
/* Skip NULLified clock */
return;
}
switch (core->type) {
case CLK_TYPE_IN:
clk = of_clk_get_by_name(priv->dev->of_node, core->name);
break;
case CLK_TYPE_FF:
WARN_DEBUG(core->parent >= priv->num_core_clks);
parent = priv->clks[core->parent];
if (IS_ERR(parent)) {
clk = parent;
goto fail;
}
parent_name = __clk_get_name(parent);
clk = clk_register_fixed_factor(NULL, core->name,
parent_name, CLK_SET_RATE_PARENT,
core->mult, div);
break;
case CLK_TYPE_SAM_PLL:
clk = rzg2l_cpg_pll_clk_register(core, priv->clks,
priv->base, priv);
break;
case CLK_TYPE_SIPLL5:
clk = rzg2l_cpg_sipll5_register(core, priv->clks, priv);
break;
case CLK_TYPE_DIV:
clk = rzg2l_cpg_div_clk_register(core, priv->clks,
priv->base, priv);
break;
case CLK_TYPE_MUX:
clk = rzg2l_cpg_mux_clk_register(core, priv->base, priv);
break;
case CLK_TYPE_SD_MUX:
clk = rzg2l_cpg_sd_mux_clk_register(core, priv->base, priv);
break;
case CLK_TYPE_PLL5_4_MUX:
clk = rzg2l_cpg_pll5_4_mux_clk_register(core, priv);
break;
case CLK_TYPE_DSI_DIV:
clk = rzg2l_cpg_dsi_div_clk_register(core, priv->clks, priv);
break;
default:
goto fail;
}
if (IS_ERR_OR_NULL(clk))
goto fail;
dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
priv->clks[id] = clk;
return;
fail:
dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
core->name, PTR_ERR(clk));
}
/**
* struct mstp_clock - MSTP gating clock
*
* @hw: handle between common and hardware-specific interfaces
* @off: register offset
* @bit: ON/MON bit
* @enabled: soft state of the clock, if it is coupled with another clock
* @priv: CPG/MSTP private data
* @sibling: pointer to the other coupled clock
*/
struct mstp_clock {
struct clk_hw hw;
u16 off;
u8 bit;
bool enabled;
struct rzg2l_cpg_priv *priv;
struct mstp_clock *sibling;
};
#define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw)
static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
{
struct mstp_clock *clock = to_mod_clock(hw);
struct rzg2l_cpg_priv *priv = clock->priv;
unsigned int reg = clock->off;
struct device *dev = priv->dev;
unsigned long flags;
u32 bitmask = BIT(clock->bit);
u32 value;
int error;
if (!clock->off) {
dev_dbg(dev, "%pC does not support ON/OFF\n", hw->clk);
return 0;
}
dev_dbg(dev, "CLK_ON %u/%pC %s\n", CLK_ON_R(reg), hw->clk,
enable ? "ON" : "OFF");
spin_lock_irqsave(&priv->rmw_lock, flags);
if (enable)
value = (bitmask << 16) | bitmask;
else
value = bitmask << 16;
writel(value, priv->base + CLK_ON_R(reg));
spin_unlock_irqrestore(&priv->rmw_lock, flags);
if (!enable)
return 0;
if (!priv->info->has_clk_mon_regs)
return 0;
error = readl_poll_timeout_atomic(priv->base + CLK_MON_R(reg), value,
value & bitmask, 0, 10);
if (error)
dev_err(dev, "Failed to enable CLK_ON %p\n",
priv->base + CLK_ON_R(reg));
return error;
}
static int rzg2l_mod_clock_enable(struct clk_hw *hw)
{
struct mstp_clock *clock = to_mod_clock(hw);
if (clock->sibling) {
struct rzg2l_cpg_priv *priv = clock->priv;
unsigned long flags;
bool enabled;
spin_lock_irqsave(&priv->rmw_lock, flags);
enabled = clock->sibling->enabled;
clock->enabled = true;
spin_unlock_irqrestore(&priv->rmw_lock, flags);
if (enabled)
return 0;
}
return rzg2l_mod_clock_endisable(hw, true);
}
static void rzg2l_mod_clock_disable(struct clk_hw *hw)
{
struct mstp_clock *clock = to_mod_clock(hw);
if (clock->sibling) {
struct rzg2l_cpg_priv *priv = clock->priv;
unsigned long flags;
bool enabled;
spin_lock_irqsave(&priv->rmw_lock, flags);
enabled = clock->sibling->enabled;
clock->enabled = false;
spin_unlock_irqrestore(&priv->rmw_lock, flags);
if (enabled)
return;
}
rzg2l_mod_clock_endisable(hw, false);
}
static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
{
struct mstp_clock *clock = to_mod_clock(hw);
struct rzg2l_cpg_priv *priv = clock->priv;
u32 bitmask = BIT(clock->bit);
u32 value;
if (!clock->off) {
dev_dbg(priv->dev, "%pC does not support ON/OFF\n", hw->clk);
return 1;
}
if (clock->sibling)
return clock->enabled;
if (priv->info->has_clk_mon_regs)
value = readl(priv->base + CLK_MON_R(clock->off));
else
value = readl(priv->base + clock->off);
return value & bitmask;
}
static const struct clk_ops rzg2l_mod_clock_ops = {
.enable = rzg2l_mod_clock_enable,
.disable = rzg2l_mod_clock_disable,
.is_enabled = rzg2l_mod_clock_is_enabled,
};
static struct mstp_clock
*rzg2l_mod_clock_get_sibling(struct mstp_clock *clock,
struct rzg2l_cpg_priv *priv)
{
struct clk_hw *hw;
unsigned int i;
for (i = 0; i < priv->num_mod_clks; i++) {
struct mstp_clock *clk;
if (priv->clks[priv->num_core_clks + i] == ERR_PTR(-ENOENT))
continue;
hw = __clk_get_hw(priv->clks[priv->num_core_clks + i]);
clk = to_mod_clock(hw);
if (clock->off == clk->off && clock->bit == clk->bit)
return clk;
}
return NULL;
}
static void __init
rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
const struct rzg2l_cpg_info *info,
struct rzg2l_cpg_priv *priv)
{
struct mstp_clock *clock = NULL;
struct device *dev = priv->dev;
unsigned int id = mod->id;
struct clk_init_data init;
struct clk *parent, *clk;
const char *parent_name;
unsigned int i;
WARN_DEBUG(id < priv->num_core_clks);
WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
if (!mod->name) {
/* Skip NULLified clock */
return;
}
parent = priv->clks[mod->parent];
if (IS_ERR(parent)) {
clk = parent;
goto fail;
}
clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
if (!clock) {
clk = ERR_PTR(-ENOMEM);
goto fail;
}
init.name = mod->name;
init.ops = &rzg2l_mod_clock_ops;
init.flags = CLK_SET_RATE_PARENT;
for (i = 0; i < info->num_crit_mod_clks; i++)
if (id == info->crit_mod_clks[i]) {
dev_dbg(dev, "CPG %s setting CLK_IS_CRITICAL\n",
mod->name);
init.flags |= CLK_IS_CRITICAL;
break;
}
parent_name = __clk_get_name(parent);
init.parent_names = &parent_name;
init.num_parents = 1;
clock->off = mod->off;
clock->bit = mod->bit;
clock->priv = priv;
clock->hw.init = &init;
clk = clk_register(NULL, &clock->hw);
if (IS_ERR(clk))
goto fail;
dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
priv->clks[id] = clk;
if (mod->is_coupled) {
struct mstp_clock *sibling;
clock->enabled = rzg2l_mod_clock_is_enabled(&clock->hw);
sibling = rzg2l_mod_clock_get_sibling(clock, priv);
if (sibling) {
clock->sibling = sibling;
sibling->sibling = clock;
}
}
return;
fail:
dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
mod->name, PTR_ERR(clk));
}
#define rcdev_to_priv(x) container_of(x, struct rzg2l_cpg_priv, rcdev)
static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
const struct rzg2l_cpg_info *info = priv->info;
unsigned int reg = info->resets[id].off;
u32 dis = BIT(info->resets[id].bit);
u32 we = dis << 16;
dev_dbg(rcdev->dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
/* Reset module */
writel(we, priv->base + CLK_RST_R(reg));
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
udelay(35);
/* Release module from reset state */
writel(we | dis, priv->base + CLK_RST_R(reg));
return 0;
}
static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
const struct rzg2l_cpg_info *info = priv->info;
unsigned int reg = info->resets[id].off;
u32 value = BIT(info->resets[id].bit) << 16;
dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
writel(value, priv->base + CLK_RST_R(reg));
return 0;
}
static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
const struct rzg2l_cpg_info *info = priv->info;
unsigned int reg = info->resets[id].off;
u32 dis = BIT(info->resets[id].bit);
u32 value = (dis << 16) | dis;
dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id,
CLK_RST_R(reg));
writel(value, priv->base + CLK_RST_R(reg));
return 0;
}
static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
const struct rzg2l_cpg_info *info = priv->info;
unsigned int reg = info->resets[id].off;
u32 bitmask = BIT(info->resets[id].bit);
s8 monbit = info->resets[id].monbit;
if (info->has_clk_mon_regs) {
return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
} else if (monbit >= 0) {
u32 monbitmask = BIT(monbit);
return !!(readl(priv->base + CPG_RST_MON) & monbitmask);
}
return -ENOTSUPP;
}
static const struct reset_control_ops rzg2l_cpg_reset_ops = {
.reset = rzg2l_cpg_reset,
.assert = rzg2l_cpg_assert,
.deassert = rzg2l_cpg_deassert,
.status = rzg2l_cpg_status,
};
static int rzg2l_cpg_reset_xlate(struct reset_controller_dev *rcdev,
const struct of_phandle_args *reset_spec)
{
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
const struct rzg2l_cpg_info *info = priv->info;
unsigned int id = reset_spec->args[0];
if (id >= rcdev->nr_resets || !info->resets[id].off) {
dev_err(rcdev->dev, "Invalid reset index %u\n", id);
return -EINVAL;
}
return id;
}
static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
{
priv->rcdev.ops = &rzg2l_cpg_reset_ops;
priv->rcdev.of_node = priv->dev->of_node;
priv->rcdev.dev = priv->dev;
priv->rcdev.of_reset_n_cells = 1;
priv->rcdev.of_xlate = rzg2l_cpg_reset_xlate;
priv->rcdev.nr_resets = priv->num_resets;
return devm_reset_controller_register(priv->dev, &priv->rcdev);
}
static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
const struct of_phandle_args *clkspec)
{
const struct rzg2l_cpg_info *info = priv->info;
unsigned int id;
unsigned int i;
if (clkspec->args_count != 2)
return false;
if (clkspec->args[0] != CPG_MOD)
return false;
id = clkspec->args[1] + info->num_total_core_clks;
for (i = 0; i < info->num_no_pm_mod_clks; i++) {
if (info->no_pm_mod_clks[i] == id)
return false;
}
return true;
}
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
{
struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd);
struct device_node *np = dev->of_node;
struct of_phandle_args clkspec;
bool once = true;
struct clk *clk;
int error;
int i = 0;
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
&clkspec)) {
if (rzg2l_cpg_is_pm_clk(priv, &clkspec)) {
if (once) {
once = false;
error = pm_clk_create(dev);
if (error) {
of_node_put(clkspec.np);
goto err;
}
}
clk = of_clk_get_from_provider(&clkspec);
of_node_put(clkspec.np);
if (IS_ERR(clk)) {
error = PTR_ERR(clk);
goto fail_destroy;
}
error = pm_clk_add_clk(dev, clk);
if (error) {
dev_err(dev, "pm_clk_add_clk failed %d\n",
error);
goto fail_put;
}
} else {
of_node_put(clkspec.np);
}
i++;
}
return 0;
fail_put:
clk_put(clk);
fail_destroy:
pm_clk_destroy(dev);
err:
return error;
}
static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev)
{
if (!pm_clk_no_clocks(dev))
pm_clk_destroy(dev);
}
static void rzg2l_cpg_genpd_remove(void *data)
{
pm_genpd_remove(data);
}
static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
{
struct device *dev = priv->dev;
struct device_node *np = dev->of_node;
struct generic_pm_domain *genpd = &priv->genpd;
int ret;
genpd->name = np->name;
genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
GENPD_FLAG_ACTIVE_WAKEUP;
genpd->attach_dev = rzg2l_cpg_attach_dev;
genpd->detach_dev = rzg2l_cpg_detach_dev;
ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd);
if (ret)
return ret;
return of_genpd_add_provider_simple(np, genpd);
}
static int __init rzg2l_cpg_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
const struct rzg2l_cpg_info *info;
struct rzg2l_cpg_priv *priv;
unsigned int nclks, i;
struct clk **clks;
int error;
info = of_device_get_match_data(dev);
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = dev;
priv->info = info;
spin_lock_init(&priv->rmw_lock);
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
nclks = info->num_total_core_clks + info->num_hw_mod_clks;
clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
if (!clks)
return -ENOMEM;
dev_set_drvdata(dev, priv);
priv->clks = clks;
priv->num_core_clks = info->num_total_core_clks;
priv->num_mod_clks = info->num_hw_mod_clks;
priv->num_resets = info->num_resets;
priv->last_dt_core_clk = info->last_dt_core_clk;
for (i = 0; i < nclks; i++)
clks[i] = ERR_PTR(-ENOENT);
for (i = 0; i < info->num_core_clks; i++)
rzg2l_cpg_register_core_clk(&info->core_clks[i], info, priv);
for (i = 0; i < info->num_mod_clks; i++)
rzg2l_cpg_register_mod_clk(&info->mod_clks[i], info, priv);
error = of_clk_add_provider(np, rzg2l_cpg_clk_src_twocell_get, priv);
if (error)
return error;
error = devm_add_action_or_reset(dev, rzg2l_cpg_del_clk_provider, np);
if (error)
return error;
error = rzg2l_cpg_add_clk_domain(priv);
if (error)
return error;
error = rzg2l_cpg_reset_controller_register(priv);
if (error)
return error;
return 0;
}
static const struct of_device_id rzg2l_cpg_match[] = {
#ifdef CONFIG_CLK_R9A07G043
{
.compatible = "renesas,r9a07g043-cpg",
.data = &r9a07g043_cpg_info,
},
#endif
#ifdef CONFIG_CLK_R9A07G044
{
.compatible = "renesas,r9a07g044-cpg",
.data = &r9a07g044_cpg_info,
},
#endif
#ifdef CONFIG_CLK_R9A07G054
{
.compatible = "renesas,r9a07g054-cpg",
.data = &r9a07g054_cpg_info,
},
#endif
#ifdef CONFIG_CLK_R9A09G011
{
.compatible = "renesas,r9a09g011-cpg",
.data = &r9a09g011_cpg_info,
},
#endif
{ /* sentinel */ }
};
static struct platform_driver rzg2l_cpg_driver = {
.driver = {
.name = "rzg2l-cpg",
.of_match_table = rzg2l_cpg_match,
},
};
static int __init rzg2l_cpg_init(void)
{
return platform_driver_probe(&rzg2l_cpg_driver, rzg2l_cpg_probe);
}
subsys_initcall(rzg2l_cpg_init);
MODULE_DESCRIPTION("Renesas RZ/G2L CPG Driver");
| linux-master | drivers/clk/renesas/rzg2l-cpg.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r8a7792 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2017 Glider bvba
*
* Based on clk-rcar-gen2.c
*
* Copyright (C) 2013 Ideas On Board SPRL
*/
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen2-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A7792_CLK_OSC,
/* External Input Clocks */
CLK_EXTAL,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
CLK_PLL3,
CLK_PLL1_DIV2,
/* Module Clocks */
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
/* Core Clock Outputs */
DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
DEF_FIXED("z", R8A7792_CLK_Z, CLK_PLL0, 1, 1),
DEF_FIXED("zg", R8A7792_CLK_ZG, CLK_PLL1, 5, 1),
DEF_FIXED("zx", R8A7792_CLK_ZX, CLK_PLL1, 3, 1),
DEF_FIXED("zs", R8A7792_CLK_ZS, CLK_PLL1, 6, 1),
DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1),
DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1),
DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1),
DEF_FIXED("lb", R8A7792_CLK_LB, CLK_PLL1, 24, 1),
DEF_FIXED("p", R8A7792_CLK_P, CLK_PLL1, 24, 1),
DEF_FIXED("cl", R8A7792_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("m2", R8A7792_CLK_M2, CLK_PLL1, 8, 1),
DEF_FIXED("imp", R8A7792_CLK_IMP, CLK_PLL1, 4, 1),
DEF_FIXED("zb3", R8A7792_CLK_ZB3, CLK_PLL3, 4, 1),
DEF_FIXED("zb3d2", R8A7792_CLK_ZB3D2, CLK_PLL3, 8, 1),
DEF_FIXED("ddr", R8A7792_CLK_DDR, CLK_PLL3, 8, 1),
DEF_FIXED("sd", R8A7792_CLK_SD, CLK_PLL1_DIV2, 8, 1),
DEF_FIXED("mp", R8A7792_CLK_MP, CLK_PLL1_DIV2, 15, 1),
DEF_FIXED("cp", R8A7792_CLK_CP, CLK_PLL1, 48, 1),
DEF_FIXED("cpex", R8A7792_CLK_CPEX, CLK_EXTAL, 2, 1),
DEF_FIXED("rcan", R8A7792_CLK_RCAN, CLK_PLL1_DIV2, 49, 1),
DEF_FIXED("r", R8A7792_CLK_R, CLK_PLL1, 49152, 1),
DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1),
};
static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
DEF_MOD("jpu", 106, R8A7792_CLK_M2),
DEF_MOD("tmu1", 111, R8A7792_CLK_P),
DEF_MOD("3dg", 112, R8A7792_CLK_ZG),
DEF_MOD("2d-dmac", 115, R8A7792_CLK_ZS),
DEF_MOD("tmu3", 121, R8A7792_CLK_P),
DEF_MOD("tmu2", 122, R8A7792_CLK_P),
DEF_MOD("cmt0", 124, R8A7792_CLK_R),
DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7792_CLK_ZS),
DEF_MOD("vsps", 131, R8A7792_CLK_ZS),
DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS),
DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS),
DEF_MOD("tpu0", 304, R8A7792_CLK_CP),
DEF_MOD("sdhi0", 314, R8A7792_CLK_SD),
DEF_MOD("cmt1", 329, R8A7792_CLK_R),
DEF_MOD("rwdt", 402, R8A7792_CLK_R),
DEF_MOD("irqc", 407, R8A7792_CLK_CP),
DEF_MOD("intc-sys", 408, R8A7792_CLK_ZS),
DEF_MOD("audio-dmac0", 502, R8A7792_CLK_HP),
DEF_MOD("thermal", 522, CLK_EXTAL),
DEF_MOD("pwm", 523, R8A7792_CLK_P),
DEF_MOD("hscif1", 716, R8A7792_CLK_ZS),
DEF_MOD("hscif0", 717, R8A7792_CLK_ZS),
DEF_MOD("scif3", 718, R8A7792_CLK_P),
DEF_MOD("scif2", 719, R8A7792_CLK_P),
DEF_MOD("scif1", 720, R8A7792_CLK_P),
DEF_MOD("scif0", 721, R8A7792_CLK_P),
DEF_MOD("du1", 723, R8A7792_CLK_ZX),
DEF_MOD("du0", 724, R8A7792_CLK_ZX),
DEF_MOD("vin5", 804, R8A7792_CLK_ZG),
DEF_MOD("vin4", 805, R8A7792_CLK_ZG),
DEF_MOD("vin3", 808, R8A7792_CLK_ZG),
DEF_MOD("vin2", 809, R8A7792_CLK_ZG),
DEF_MOD("vin1", 810, R8A7792_CLK_ZG),
DEF_MOD("vin0", 811, R8A7792_CLK_ZG),
DEF_MOD("etheravb", 812, R8A7792_CLK_HP),
DEF_MOD("imr-lx3", 821, R8A7792_CLK_ZG),
DEF_MOD("imr-lsx3-1", 822, R8A7792_CLK_ZG),
DEF_MOD("imr-lsx3-0", 823, R8A7792_CLK_ZG),
DEF_MOD("imr-lsx3-5", 825, R8A7792_CLK_ZG),
DEF_MOD("imr-lsx3-4", 826, R8A7792_CLK_ZG),
DEF_MOD("imr-lsx3-3", 827, R8A7792_CLK_ZG),
DEF_MOD("imr-lsx3-2", 828, R8A7792_CLK_ZG),
DEF_MOD("gyro-adc", 901, R8A7792_CLK_P),
DEF_MOD("gpio7", 904, R8A7792_CLK_CP),
DEF_MOD("gpio6", 905, R8A7792_CLK_CP),
DEF_MOD("gpio5", 907, R8A7792_CLK_CP),
DEF_MOD("gpio4", 908, R8A7792_CLK_CP),
DEF_MOD("gpio3", 909, R8A7792_CLK_CP),
DEF_MOD("gpio2", 910, R8A7792_CLK_CP),
DEF_MOD("gpio1", 911, R8A7792_CLK_CP),
DEF_MOD("gpio0", 912, R8A7792_CLK_CP),
DEF_MOD("gpio11", 913, R8A7792_CLK_CP),
DEF_MOD("gpio10", 914, R8A7792_CLK_CP),
DEF_MOD("can1", 915, R8A7792_CLK_P),
DEF_MOD("can0", 916, R8A7792_CLK_P),
DEF_MOD("qspi_mod", 917, R8A7792_CLK_QSPI),
DEF_MOD("gpio9", 919, R8A7792_CLK_CP),
DEF_MOD("gpio8", 921, R8A7792_CLK_CP),
DEF_MOD("i2c5", 925, R8A7792_CLK_HP),
DEF_MOD("iicdvfs", 926, R8A7792_CLK_CP),
DEF_MOD("i2c4", 927, R8A7792_CLK_HP),
DEF_MOD("i2c3", 928, R8A7792_CLK_HP),
DEF_MOD("i2c2", 929, R8A7792_CLK_HP),
DEF_MOD("i2c1", 930, R8A7792_CLK_HP),
DEF_MOD("i2c0", 931, R8A7792_CLK_HP),
DEF_MOD("ssi-all", 1005, R8A7792_CLK_P),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
};
static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
MOD_CLK_ID(402), /* RWDT */
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL3
* 14 13 19 (MHz) *1 *2
*---------------------------------------------------
* 0 0 0 15 x200/3 x208/2 x106
* 0 0 1 15 x200/3 x208/2 x88
* 0 1 0 20 x150/3 x156/2 x80
* 0 1 1 20 x150/3 x156/2 x66
* 1 0 0 26 / 2 x230/3 x240/2 x122
* 1 0 1 26 / 2 x230/3 x240/2 x102
* 1 1 0 30 / 2 x200/3 x208/2 x106
* 1 1 1 30 / 2 x200/3 x208/2 x88
*
* *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
* *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
{ 1, 208, 106, 200 },
{ 1, 208, 88, 200 },
{ 1, 156, 80, 150 },
{ 1, 156, 66, 150 },
{ 2, 240, 122, 230 },
{ 2, 240, 102, 230 },
{ 2, 208, 106, 200 },
{ 2, 208, 88, 200 },
};
static int __init r8a7792_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
u32 cpg_mode;
int error;
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
return rcar_gen2_cpg_init(cpg_pll_config, 3, cpg_mode);
}
const struct cpg_mssr_info r8a7792_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a7792_core_clks,
.num_core_clks = ARRAY_SIZE(r8a7792_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a7792_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a7792_mod_clks),
.num_hw_mod_clks = 12 * 32,
/* Critical Module Clocks */
.crit_mod_clks = r8a7792_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a7792_crit_mod_clks),
/* Callbacks */
.init = r8a7792_cpg_mssr_init,
.cpg_clk_register = rcar_gen2_cpg_clk_register,
};
| linux-master | drivers/clk/renesas/r8a7792-cpg-mssr.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r8a7743 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2016 Cogent Embedded Inc.
*/
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen2-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A7743_CLK_OSC,
/* External Input Clocks */
CLK_EXTAL,
CLK_USB_EXTAL,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
CLK_PLL3,
CLK_PLL1_DIV2,
/* Module Clocks */
MOD_CLK_BASE
};
static struct cpg_core_clk r8a7743_core_clks[] __initdata = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
/* Core Clock Outputs */
DEF_BASE("z", R8A7743_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
DEF_BASE("sdh", R8A7743_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
DEF_BASE("sd0", R8A7743_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
DEF_BASE("rcan", R8A7743_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
DEF_FIXED("zg", R8A7743_CLK_ZG, CLK_PLL1, 3, 1),
DEF_FIXED("zx", R8A7743_CLK_ZX, CLK_PLL1, 3, 1),
DEF_FIXED("zs", R8A7743_CLK_ZS, CLK_PLL1, 6, 1),
DEF_FIXED("hp", R8A7743_CLK_HP, CLK_PLL1, 12, 1),
DEF_FIXED("b", R8A7743_CLK_B, CLK_PLL1, 12, 1),
DEF_FIXED("lb", R8A7743_CLK_LB, CLK_PLL1, 24, 1),
DEF_FIXED("p", R8A7743_CLK_P, CLK_PLL1, 24, 1),
DEF_FIXED("cl", R8A7743_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("m2", R8A7743_CLK_M2, CLK_PLL1, 8, 1),
DEF_FIXED("zb3", R8A7743_CLK_ZB3, CLK_PLL3, 4, 1),
DEF_FIXED("zb3d2", R8A7743_CLK_ZB3D2, CLK_PLL3, 8, 1),
DEF_FIXED("ddr", R8A7743_CLK_DDR, CLK_PLL3, 8, 1),
DEF_FIXED("mp", R8A7743_CLK_MP, CLK_PLL1_DIV2, 15, 1),
DEF_FIXED("cp", R8A7743_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("r", R8A7743_CLK_R, CLK_PLL1, 49152, 1),
DEF_FIXED("osc", R8A7743_CLK_OSC, CLK_PLL1, 12288, 1),
DEF_DIV6P1("sd2", R8A7743_CLK_SD2, CLK_PLL1_DIV2, 0x078),
DEF_DIV6P1("sd3", R8A7743_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
DEF_DIV6P1("mmc0", R8A7743_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
};
static const struct mssr_mod_clk r8a7743_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7743_CLK_MP),
DEF_MOD("vcp0", 101, R8A7743_CLK_ZS),
DEF_MOD("vpc0", 103, R8A7743_CLK_ZS),
DEF_MOD("tmu1", 111, R8A7743_CLK_P),
DEF_MOD("3dg", 112, R8A7743_CLK_ZG),
DEF_MOD("2d-dmac", 115, R8A7743_CLK_ZS),
DEF_MOD("fdp1-1", 118, R8A7743_CLK_ZS),
DEF_MOD("fdp1-0", 119, R8A7743_CLK_ZS),
DEF_MOD("tmu3", 121, R8A7743_CLK_P),
DEF_MOD("tmu2", 122, R8A7743_CLK_P),
DEF_MOD("cmt0", 124, R8A7743_CLK_R),
DEF_MOD("tmu0", 125, R8A7743_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7743_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7743_CLK_ZS),
DEF_MOD("vsps", 131, R8A7743_CLK_ZS),
DEF_MOD("scifa2", 202, R8A7743_CLK_MP),
DEF_MOD("scifa1", 203, R8A7743_CLK_MP),
DEF_MOD("scifa0", 204, R8A7743_CLK_MP),
DEF_MOD("msiof2", 205, R8A7743_CLK_MP),
DEF_MOD("scifb0", 206, R8A7743_CLK_MP),
DEF_MOD("scifb1", 207, R8A7743_CLK_MP),
DEF_MOD("msiof1", 208, R8A7743_CLK_MP),
DEF_MOD("scifb2", 216, R8A7743_CLK_MP),
DEF_MOD("sys-dmac1", 218, R8A7743_CLK_ZS),
DEF_MOD("sys-dmac0", 219, R8A7743_CLK_ZS),
DEF_MOD("tpu0", 304, R8A7743_CLK_CP),
DEF_MOD("sdhi3", 311, R8A7743_CLK_SD3),
DEF_MOD("sdhi2", 312, R8A7743_CLK_SD2),
DEF_MOD("sdhi0", 314, R8A7743_CLK_SD0),
DEF_MOD("mmcif0", 315, R8A7743_CLK_MMC0),
DEF_MOD("iic0", 318, R8A7743_CLK_HP),
DEF_MOD("pciec", 319, R8A7743_CLK_MP),
DEF_MOD("iic1", 323, R8A7743_CLK_HP),
DEF_MOD("usb3.0", 328, R8A7743_CLK_MP),
DEF_MOD("cmt1", 329, R8A7743_CLK_R),
DEF_MOD("usbhs-dmac0", 330, R8A7743_CLK_HP),
DEF_MOD("usbhs-dmac1", 331, R8A7743_CLK_HP),
DEF_MOD("rwdt", 402, R8A7743_CLK_R),
DEF_MOD("irqc", 407, R8A7743_CLK_CP),
DEF_MOD("intc-sys", 408, R8A7743_CLK_ZS),
DEF_MOD("audio-dmac1", 501, R8A7743_CLK_HP),
DEF_MOD("audio-dmac0", 502, R8A7743_CLK_HP),
DEF_MOD("thermal", 522, CLK_EXTAL),
DEF_MOD("pwm", 523, R8A7743_CLK_P),
DEF_MOD("usb-ehci", 703, R8A7743_CLK_MP),
DEF_MOD("usbhs", 704, R8A7743_CLK_HP),
DEF_MOD("hscif2", 713, R8A7743_CLK_ZS),
DEF_MOD("scif5", 714, R8A7743_CLK_P),
DEF_MOD("scif4", 715, R8A7743_CLK_P),
DEF_MOD("hscif1", 716, R8A7743_CLK_ZS),
DEF_MOD("hscif0", 717, R8A7743_CLK_ZS),
DEF_MOD("scif3", 718, R8A7743_CLK_P),
DEF_MOD("scif2", 719, R8A7743_CLK_P),
DEF_MOD("scif1", 720, R8A7743_CLK_P),
DEF_MOD("scif0", 721, R8A7743_CLK_P),
DEF_MOD("du1", 723, R8A7743_CLK_ZX),
DEF_MOD("du0", 724, R8A7743_CLK_ZX),
DEF_MOD("lvds0", 726, R8A7743_CLK_ZX),
DEF_MOD("ipmmu-sgx", 800, R8A7743_CLK_ZX),
DEF_MOD("vin2", 809, R8A7743_CLK_ZG),
DEF_MOD("vin1", 810, R8A7743_CLK_ZG),
DEF_MOD("vin0", 811, R8A7743_CLK_ZG),
DEF_MOD("etheravb", 812, R8A7743_CLK_HP),
DEF_MOD("ether", 813, R8A7743_CLK_P),
DEF_MOD("sata1", 814, R8A7743_CLK_ZS),
DEF_MOD("sata0", 815, R8A7743_CLK_ZS),
DEF_MOD("gpio7", 904, R8A7743_CLK_CP),
DEF_MOD("gpio6", 905, R8A7743_CLK_CP),
DEF_MOD("gpio5", 907, R8A7743_CLK_CP),
DEF_MOD("gpio4", 908, R8A7743_CLK_CP),
DEF_MOD("gpio3", 909, R8A7743_CLK_CP),
DEF_MOD("gpio2", 910, R8A7743_CLK_CP),
DEF_MOD("gpio1", 911, R8A7743_CLK_CP),
DEF_MOD("gpio0", 912, R8A7743_CLK_CP),
DEF_MOD("can1", 915, R8A7743_CLK_P),
DEF_MOD("can0", 916, R8A7743_CLK_P),
DEF_MOD("qspi_mod", 917, R8A7743_CLK_QSPI),
DEF_MOD("i2c5", 925, R8A7743_CLK_HP),
DEF_MOD("iicdvfs", 926, R8A7743_CLK_CP),
DEF_MOD("i2c4", 927, R8A7743_CLK_HP),
DEF_MOD("i2c3", 928, R8A7743_CLK_HP),
DEF_MOD("i2c2", 929, R8A7743_CLK_HP),
DEF_MOD("i2c1", 930, R8A7743_CLK_HP),
DEF_MOD("i2c0", 931, R8A7743_CLK_HP),
DEF_MOD("ssi-all", 1005, R8A7743_CLK_P),
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
DEF_MOD("scu-all", 1017, R8A7743_CLK_P),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
DEF_MOD("scifa3", 1106, R8A7743_CLK_MP),
DEF_MOD("scifa4", 1107, R8A7743_CLK_MP),
DEF_MOD("scifa5", 1108, R8A7743_CLK_MP),
};
static const unsigned int r8a7743_crit_mod_clks[] __initconst = {
MOD_CLK_ID(402), /* RWDT */
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL3
* 14 13 19 (MHz) *1 *1
*---------------------------------------------------
* 0 0 0 15 x172/2 x208/2 x106
* 0 0 1 15 x172/2 x208/2 x88
* 0 1 0 20 x130/2 x156/2 x80
* 0 1 1 20 x130/2 x156/2 x66
* 1 0 0 26 / 2 x200/2 x240/2 x122
* 1 0 1 26 / 2 x200/2 x240/2 x102
* 1 1 0 30 / 2 x172/2 x208/2 x106
* 1 1 1 30 / 2 x172/2 x208/2 x88
*
* *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
/* EXTAL div PLL1 mult PLL3 mult */
{ 1, 208, 106, },
{ 1, 208, 88, },
{ 1, 156, 80, },
{ 1, 156, 66, },
{ 2, 240, 122, },
{ 2, 240, 102, },
{ 2, 208, 106, },
{ 2, 208, 88, },
};
static int __init r8a7743_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
struct device_node *np = dev->of_node;
unsigned int i;
u32 cpg_mode;
int error;
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
if (of_device_is_compatible(np, "renesas,r8a7744-cpg-mssr")) {
/* RZ/G1N uses a 1/5 divider for ZG */
for (i = 0; i < ARRAY_SIZE(r8a7743_core_clks); i++)
if (r8a7743_core_clks[i].id == R8A7743_CLK_ZG) {
r8a7743_core_clks[i].div = 5;
break;
}
}
return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
}
const struct cpg_mssr_info r8a7743_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a7743_core_clks,
.num_core_clks = ARRAY_SIZE(r8a7743_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a7743_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a7743_mod_clks),
.num_hw_mod_clks = 12 * 32,
/* Critical Module Clocks */
.crit_mod_clks = r8a7743_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a7743_crit_mod_clks),
/* Callbacks */
.init = r8a7743_cpg_mssr_init,
.cpg_clk_register = rcar_gen2_cpg_clk_register,
};
| linux-master | drivers/clk/renesas/r8a7743-cpg-mssr.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r8a77995 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2017 Glider bvba
*
* Based on r8a7795-cpg-mssr.c
*
* Copyright (C) 2015 Glider bvba
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,
/* External Input Clocks */
CLK_EXTAL,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
CLK_PLL3,
CLK_PLL0D2,
CLK_PLL0D3,
CLK_PLL0D5,
CLK_PLL1D2,
CLK_PE,
CLK_S0,
CLK_S1,
CLK_S2,
CLK_S3,
CLK_SDSRC,
CLK_RPCSRC,
CLK_RINT,
CLK_OCO,
/* Module Clocks */
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
DEF_FIXED_RPCSRC_D3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
/* Core Clock Outputs */
DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1),
DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("cr", R8A77995_CLK_CR, CLK_PLL1D2, 2, 1),
DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1),
DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268),
DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77995_CLK_RPC),
DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
};
static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A77995_CLK_S1D4C),
DEF_MOD("tmu3", 122, R8A77995_CLK_S3D2C),
DEF_MOD("tmu2", 123, R8A77995_CLK_S3D2C),
DEF_MOD("tmu1", 124, R8A77995_CLK_S3D2C),
DEF_MOD("tmu0", 125, R8A77995_CLK_CP),
DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
DEF_MOD("cmt3", 300, R8A77995_CLK_R),
DEF_MOD("cmt2", 301, R8A77995_CLK_R),
DEF_MOD("cmt1", 302, R8A77995_CLK_R),
DEF_MOD("cmt0", 303, R8A77995_CLK_R),
DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
DEF_MOD("rwdt", 402, R8A77995_CLK_R),
DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A77995_CLK_S1D2),
DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
DEF_MOD("thermal", 522, R8A77995_CLK_CP),
DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
DEF_MOD("cmm1", 710, R8A77995_CLK_S1D1),
DEF_MOD("cmm0", 711, R8A77995_CLK_S1D1),
DEF_MOD("du1", 723, R8A77995_CLK_S1D1),
DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
DEF_MOD("mlp", 802, R8A77995_CLK_S2D1),
DEF_MOD("vin4", 807, R8A77995_CLK_S3D1),
DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
DEF_MOD("rpc-if", 917, R8A77995_CLK_RPCD2),
DEF_MOD("adg", 922, R8A77995_CLK_ZA2),
DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
};
static const unsigned int r8a77995_crit_mod_clks[] __initconst = {
MOD_CLK_ID(402), /* RWDT */
MOD_CLK_ID(408), /* INTC-AP (GIC) */
};
/*
* CPG Clock Data
*/
/*
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
*--------------------------------------------------------------------
* 0 48 x 1 x250/4 x100/3 x100/3
* 1 48 x 1 x250/4 x100/3 x58/3
*/
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 100, 3, 100, 3, },
{ 1, 100, 3, 58, 3, },
};
static int __init r8a77995_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
u32 cpg_mode;
int error;
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
}
const struct cpg_mssr_info r8a77995_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a77995_core_clks,
.num_core_clks = ARRAY_SIZE(r8a77995_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a77995_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a77995_mod_clks),
.num_hw_mod_clks = 12 * 32,
/* Critical Module Clocks */
.crit_mod_clks = r8a77995_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a77995_crit_mod_clks),
/* Callbacks */
.init = r8a77995_cpg_mssr_init,
.cpg_clk_register = rcar_gen3_cpg_clk_register,
};
| linux-master | drivers/clk/renesas/r8a77995-cpg-mssr.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r8a779g0 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2022 Renesas Electronics Corp.
*
* Based on r8a779f0-cpg-mssr.c
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen4-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A779G0_CLK_R,
/* External Input Clocks */
CLK_EXTAL,
CLK_EXTALR,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL1,
CLK_PLL2,
CLK_PLL3,
CLK_PLL4,
CLK_PLL5,
CLK_PLL6,
CLK_PLL1_DIV2,
CLK_PLL2_DIV2,
CLK_PLL3_DIV2,
CLK_PLL4_DIV2,
CLK_PLL5_DIV2,
CLK_PLL5_DIV4,
CLK_PLL6_DIV2,
CLK_S0,
CLK_S0_VIO,
CLK_S0_VC,
CLK_S0_HSC,
CLK_SASYNCPER,
CLK_SV_VIP,
CLK_SV_IR,
CLK_SDSRC,
CLK_RPCSRC,
CLK_VIO,
CLK_VC,
CLK_OCO,
/* Module Clocks */
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2_VAR, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1),
DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1),
DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1, 5, 1),
DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1, 5, 1),
DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
DEF_RATE(".oco", CLK_OCO, 32768),
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
DEF_FIXED(".vio", CLK_VIO, CLK_PLL5_DIV2, 3, 1),
DEF_FIXED(".vc", CLK_VC, CLK_PLL5_DIV2, 3, 1),
/* Core Clock Outputs */
DEF_GEN4_Z("z0", R8A779G0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0),
DEF_FIXED("s0d2", R8A779G0_CLK_S0D2, CLK_S0, 2, 1),
DEF_FIXED("s0d3", R8A779G0_CLK_S0D3, CLK_S0, 3, 1),
DEF_FIXED("s0d4", R8A779G0_CLK_S0D4, CLK_S0, 4, 1),
DEF_FIXED("cl16m", R8A779G0_CLK_CL16M, CLK_S0, 48, 1),
DEF_FIXED("s0d1_vio", R8A779G0_CLK_S0D1_VIO, CLK_S0_VIO, 1, 1),
DEF_FIXED("s0d2_vio", R8A779G0_CLK_S0D2_VIO, CLK_S0_VIO, 2, 1),
DEF_FIXED("s0d4_vio", R8A779G0_CLK_S0D4_VIO, CLK_S0_VIO, 4, 1),
DEF_FIXED("s0d8_vio", R8A779G0_CLK_S0D8_VIO, CLK_S0_VIO, 8, 1),
DEF_FIXED("s0d1_vc", R8A779G0_CLK_S0D1_VC, CLK_S0_VC, 1, 1),
DEF_FIXED("s0d2_vc", R8A779G0_CLK_S0D2_VC, CLK_S0_VC, 2, 1),
DEF_FIXED("s0d4_vc", R8A779G0_CLK_S0D4_VC, CLK_S0_VC, 4, 1),
DEF_FIXED("s0d2_mm", R8A779G0_CLK_S0D2_MM, CLK_S0, 2, 1),
DEF_FIXED("s0d4_mm", R8A779G0_CLK_S0D4_MM, CLK_S0, 4, 1),
DEF_FIXED("cl16m_mm", R8A779G0_CLK_CL16M_MM, CLK_S0, 48, 1),
DEF_FIXED("s0d2_u3dg", R8A779G0_CLK_S0D2_U3DG, CLK_S0, 2, 1),
DEF_FIXED("s0d4_u3dg", R8A779G0_CLK_S0D4_U3DG, CLK_S0, 4, 1),
DEF_FIXED("s0d2_rt", R8A779G0_CLK_S0D2_RT, CLK_S0, 2, 1),
DEF_FIXED("s0d3_rt", R8A779G0_CLK_S0D3_RT, CLK_S0, 3, 1),
DEF_FIXED("s0d4_rt", R8A779G0_CLK_S0D4_RT, CLK_S0, 4, 1),
DEF_FIXED("s0d6_rt", R8A779G0_CLK_S0D6_RT, CLK_S0, 6, 1),
DEF_FIXED("s0d24_rt", R8A779G0_CLK_S0D24_RT, CLK_S0, 24, 1),
DEF_FIXED("cl16m_rt", R8A779G0_CLK_CL16M_RT, CLK_S0, 48, 1),
DEF_FIXED("s0d2_per", R8A779G0_CLK_S0D2_PER, CLK_S0, 2, 1),
DEF_FIXED("s0d3_per", R8A779G0_CLK_S0D3_PER, CLK_S0, 3, 1),
DEF_FIXED("s0d4_per", R8A779G0_CLK_S0D4_PER, CLK_S0, 4, 1),
DEF_FIXED("s0d6_per", R8A779G0_CLK_S0D6_PER, CLK_S0, 6, 1),
DEF_FIXED("s0d12_per", R8A779G0_CLK_S0D12_PER, CLK_S0, 12, 1),
DEF_FIXED("s0d24_per", R8A779G0_CLK_S0D24_PER, CLK_S0, 24, 1),
DEF_FIXED("cl16m_per", R8A779G0_CLK_CL16M_PER, CLK_S0, 48, 1),
DEF_FIXED("s0d1_hsc", R8A779G0_CLK_S0D1_HSC, CLK_S0_HSC, 1, 1),
DEF_FIXED("s0d2_hsc", R8A779G0_CLK_S0D2_HSC, CLK_S0_HSC, 2, 1),
DEF_FIXED("s0d4_hsc", R8A779G0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1),
DEF_FIXED("cl16m_hsc", R8A779G0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1),
DEF_FIXED("s0d2_cc", R8A779G0_CLK_S0D2_CC, CLK_S0, 2, 1),
DEF_FIXED("sasyncrt", R8A779G0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1),
DEF_FIXED("sasyncperd1",R8A779G0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
DEF_FIXED("sasyncperd2",R8A779G0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
DEF_FIXED("sasyncperd4",R8A779G0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
DEF_FIXED("svd1_ir", R8A779G0_CLK_SVD1_IR, CLK_SV_IR, 1, 1),
DEF_FIXED("svd2_ir", R8A779G0_CLK_SVD2_IR, CLK_SV_IR, 2, 1),
DEF_FIXED("svd1_vip", R8A779G0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1),
DEF_FIXED("svd2_vip", R8A779G0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
DEF_FIXED("cbfusa", R8A779G0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A779G0_CLK_CPEX, CLK_EXTAL, 2, 1),
DEF_FIXED("viobus", R8A779G0_CLK_VIOBUS, CLK_VIO, 1, 1),
DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, 0x880),
DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870),
DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870),
DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
DEF_BASE("rpc", R8A779G0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
DEF_BASE("rpcd2", R8A779G0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC),
DEF_GEN4_OSC("osc", R8A779G0_CLK_OSC, CLK_EXTAL, 8),
DEF_GEN4_MDSEL("r", R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
};
static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("canfd0", 328, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("csi40", 331, R8A779G0_CLK_CSI),
DEF_MOD("csi41", 400, R8A779G0_CLK_CSI),
DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("fcpvd0", 508, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("fcpvd1", 509, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1),
DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1),
DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1),
DEF_MOD("hscif3", 517, R8A779G0_CLK_SASYNCPERD1),
DEF_MOD("i2c0", 518, R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c1", 519, R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c2", 520, R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c3", 521, R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c4", 522, R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c5", 523, R8A779G0_CLK_S0D6_PER),
DEF_MOD("irqc", 611, R8A779G0_CLK_CL16M),
DEF_MOD("ispcs0", 612, R8A779G0_CLK_S0D2_VIO),
DEF_MOD("ispcs1", 613, R8A779G0_CLK_S0D2_VIO),
DEF_MOD("msi0", 618, R8A779G0_CLK_MSO),
DEF_MOD("msi1", 619, R8A779G0_CLK_MSO),
DEF_MOD("msi2", 620, R8A779G0_CLK_MSO),
DEF_MOD("msi3", 621, R8A779G0_CLK_MSO),
DEF_MOD("msi4", 622, R8A779G0_CLK_MSO),
DEF_MOD("msi5", 623, R8A779G0_CLK_MSO),
DEF_MOD("pwm", 628, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("rpc-if", 629, R8A779G0_CLK_RPCD2),
DEF_MOD("scif0", 702, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("scif1", 703, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("scif3", 704, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("scif4", 705, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("sdhi", 706, R8A779G0_CLK_SD0),
DEF_MOD("sys-dmac0", 709, R8A779G0_CLK_S0D6_PER),
DEF_MOD("sys-dmac1", 710, R8A779G0_CLK_S0D6_PER),
DEF_MOD("tmu0", 713, R8A779G0_CLK_SASYNCRT),
DEF_MOD("tmu1", 714, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tmu2", 715, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("vin00", 730, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vin01", 731, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vin02", 800, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vin03", 801, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vin04", 802, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vin05", 803, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vin06", 804, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vin07", 805, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vin10", 806, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vin11", 807, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vin12", 808, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vin13", 809, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vin14", 810, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vin15", 811, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vin16", 812, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vin17", 813, R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vspd0", 830, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("vspd1", 831, R8A779G0_CLK_VIOBUSD2),
DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
DEF_MOD("cmt0", 910, R8A779G0_CLK_R),
DEF_MOD("cmt1", 911, R8A779G0_CLK_R),
DEF_MOD("cmt2", 912, R8A779G0_CLK_R),
DEF_MOD("cmt3", 913, R8A779G0_CLK_R),
DEF_MOD("pfc0", 915, R8A779G0_CLK_CL16M),
DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M),
DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M),
DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M),
DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
* 14 13 (MHz)
* ------------------------------------------------------------------------
* 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
* 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
* 1 0 Prohibited setting
* 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
{ 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 16, },
{ 1, 160, 1, 170, 1, 160, 1, 120, 1, 160, 1, 140, 1, 19, },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 32, },
};
static int __init r8a779g0_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
u32 cpg_mode;
int error;
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
if (!cpg_pll_config->extal_div) {
dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
return -EINVAL;
}
return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
}
const struct cpg_mssr_info r8a779g0_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a779g0_core_clks,
.num_core_clks = ARRAY_SIZE(r8a779g0_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a779g0_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a779g0_mod_clks),
.num_hw_mod_clks = 30 * 32,
/* Callbacks */
.init = r8a779g0_cpg_mssr_init,
.cpg_clk_register = rcar_gen4_cpg_clk_register,
.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
};
| linux-master | drivers/clk/renesas/r8a779g0-cpg-mssr.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas R-Car USB2.0 clock selector
*
* Copyright (C) 2017 Renesas Electronics Corp.
*
* Based on renesas-cpg-mssr.c
*
* Copyright (C) 2015 Glider bvba
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/slab.h>
#define USB20_CLKSET0 0x00
#define CLKSET0_INTCLK_EN BIT(11)
#define CLKSET0_PRIVATE BIT(0)
#define CLKSET0_EXTAL_ONLY (CLKSET0_INTCLK_EN | CLKSET0_PRIVATE)
static const struct clk_bulk_data rcar_usb2_clocks[] = {
{ .id = "ehci_ohci", },
{ .id = "hs-usb-if", },
};
struct usb2_clock_sel_priv {
void __iomem *base;
struct clk_hw hw;
struct clk_bulk_data clks[ARRAY_SIZE(rcar_usb2_clocks)];
struct reset_control *rsts;
bool extal;
bool xtal;
};
#define to_priv(_hw) container_of(_hw, struct usb2_clock_sel_priv, hw)
static void usb2_clock_sel_enable_extal_only(struct usb2_clock_sel_priv *priv)
{
u16 val = readw(priv->base + USB20_CLKSET0);
pr_debug("%s: enter %d %d %x\n", __func__,
priv->extal, priv->xtal, val);
if (priv->extal && !priv->xtal && val != CLKSET0_EXTAL_ONLY)
writew(CLKSET0_EXTAL_ONLY, priv->base + USB20_CLKSET0);
}
static void usb2_clock_sel_disable_extal_only(struct usb2_clock_sel_priv *priv)
{
if (priv->extal && !priv->xtal)
writew(CLKSET0_PRIVATE, priv->base + USB20_CLKSET0);
}
static int usb2_clock_sel_enable(struct clk_hw *hw)
{
struct usb2_clock_sel_priv *priv = to_priv(hw);
int ret;
ret = reset_control_deassert(priv->rsts);
if (ret)
return ret;
ret = clk_bulk_prepare_enable(ARRAY_SIZE(priv->clks), priv->clks);
if (ret) {
reset_control_assert(priv->rsts);
return ret;
}
usb2_clock_sel_enable_extal_only(priv);
return 0;
}
static void usb2_clock_sel_disable(struct clk_hw *hw)
{
struct usb2_clock_sel_priv *priv = to_priv(hw);
usb2_clock_sel_disable_extal_only(priv);
clk_bulk_disable_unprepare(ARRAY_SIZE(priv->clks), priv->clks);
reset_control_assert(priv->rsts);
}
/*
* This module seems a mux, but this driver assumes a gate because
* ehci/ohci platform drivers don't support clk_set_parent() for now.
* If this driver acts as a gate, ehci/ohci-platform drivers don't need
* any modification.
*/
static const struct clk_ops usb2_clock_sel_clock_ops = {
.enable = usb2_clock_sel_enable,
.disable = usb2_clock_sel_disable,
};
static const struct of_device_id rcar_usb2_clock_sel_match[] = {
{ .compatible = "renesas,rcar-gen3-usb2-clock-sel" },
{ }
};
static int rcar_usb2_clock_sel_suspend(struct device *dev)
{
struct usb2_clock_sel_priv *priv = dev_get_drvdata(dev);
usb2_clock_sel_disable_extal_only(priv);
pm_runtime_put(dev);
return 0;
}
static int rcar_usb2_clock_sel_resume(struct device *dev)
{
struct usb2_clock_sel_priv *priv = dev_get_drvdata(dev);
pm_runtime_get_sync(dev);
usb2_clock_sel_enable_extal_only(priv);
return 0;
}
static void rcar_usb2_clock_sel_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
of_clk_del_provider(dev->of_node);
pm_runtime_put(dev);
pm_runtime_disable(dev);
}
static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct usb2_clock_sel_priv *priv;
struct clk *clk;
struct clk_init_data init = {};
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
memcpy(priv->clks, rcar_usb2_clocks, sizeof(priv->clks));
ret = devm_clk_bulk_get(dev, ARRAY_SIZE(priv->clks), priv->clks);
if (ret < 0)
return ret;
priv->rsts = devm_reset_control_array_get_shared(dev);
if (IS_ERR(priv->rsts))
return PTR_ERR(priv->rsts);
clk = devm_clk_get(dev, "usb_extal");
if (!IS_ERR(clk) && !clk_prepare_enable(clk)) {
priv->extal = !!clk_get_rate(clk);
clk_disable_unprepare(clk);
}
clk = devm_clk_get(dev, "usb_xtal");
if (!IS_ERR(clk) && !clk_prepare_enable(clk)) {
priv->xtal = !!clk_get_rate(clk);
clk_disable_unprepare(clk);
}
if (!priv->extal && !priv->xtal) {
dev_err(dev, "This driver needs usb_extal or usb_xtal\n");
return -ENOENT;
}
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
platform_set_drvdata(pdev, priv);
dev_set_drvdata(dev, priv);
init.name = "rcar_usb2_clock_sel";
init.ops = &usb2_clock_sel_clock_ops;
priv->hw.init = &init;
ret = devm_clk_hw_register(dev, &priv->hw);
if (ret)
goto pm_put;
ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &priv->hw);
if (ret)
goto pm_put;
return 0;
pm_put:
pm_runtime_put(dev);
pm_runtime_disable(dev);
return ret;
}
static const struct dev_pm_ops rcar_usb2_clock_sel_pm_ops = {
.suspend = rcar_usb2_clock_sel_suspend,
.resume = rcar_usb2_clock_sel_resume,
};
static struct platform_driver rcar_usb2_clock_sel_driver = {
.driver = {
.name = "rcar-usb2-clock-sel",
.of_match_table = rcar_usb2_clock_sel_match,
.pm = &rcar_usb2_clock_sel_pm_ops,
},
.probe = rcar_usb2_clock_sel_probe,
.remove_new = rcar_usb2_clock_sel_remove,
};
builtin_platform_driver(rcar_usb2_clock_sel_driver);
MODULE_DESCRIPTION("Renesas R-Car USB2 clock selector Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/renesas/rcar-usb2-clock-sel.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r8a774e1 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2020 Renesas Electronics Corp.
*
* Based on r8a7795-cpg-mssr.c
*
* Copyright (C) 2015 Glider bvba
*/
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A774E1_CLK_CANFD,
/* External Input Clocks */
CLK_EXTAL,
CLK_EXTALR,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
CLK_PLL2,
CLK_PLL3,
CLK_PLL4,
CLK_PLL1_DIV2,
CLK_PLL1_DIV4,
CLK_S0,
CLK_S1,
CLK_S2,
CLK_S3,
CLK_SDSRC,
CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A774E1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
DEF_GEN3_Z("zg", R8A774E1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A774E1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A774E1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A774E1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED("zx", R8A774E1_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED("s0d1", R8A774E1_CLK_S0D1, CLK_S0, 1, 1),
DEF_FIXED("s0d2", R8A774E1_CLK_S0D2, CLK_S0, 2, 1),
DEF_FIXED("s0d3", R8A774E1_CLK_S0D3, CLK_S0, 3, 1),
DEF_FIXED("s0d4", R8A774E1_CLK_S0D4, CLK_S0, 4, 1),
DEF_FIXED("s0d6", R8A774E1_CLK_S0D6, CLK_S0, 6, 1),
DEF_FIXED("s0d8", R8A774E1_CLK_S0D8, CLK_S0, 8, 1),
DEF_FIXED("s0d12", R8A774E1_CLK_S0D12, CLK_S0, 12, 1),
DEF_FIXED("s1d2", R8A774E1_CLK_S1D2, CLK_S1, 2, 1),
DEF_FIXED("s1d4", R8A774E1_CLK_S1D4, CLK_S1, 4, 1),
DEF_FIXED("s2d1", R8A774E1_CLK_S2D1, CLK_S2, 1, 1),
DEF_FIXED("s2d2", R8A774E1_CLK_S2D2, CLK_S2, 2, 1),
DEF_FIXED("s2d4", R8A774E1_CLK_S2D4, CLK_S2, 4, 1),
DEF_FIXED("s3d1", R8A774E1_CLK_S3D1, CLK_S3, 1, 1),
DEF_FIXED("s3d2", R8A774E1_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A774E1_CLK_S3D4, CLK_S3, 4, 1),
DEF_GEN3_SDH("sd0h", R8A774E1_CLK_SD0H, CLK_SDSRC, 0x074),
DEF_GEN3_SDH("sd1h", R8A774E1_CLK_SD1H, CLK_SDSRC, 0x078),
DEF_GEN3_SDH("sd2h", R8A774E1_CLK_SD2H, CLK_SDSRC, 0x268),
DEF_GEN3_SDH("sd3h", R8A774E1_CLK_SD3H, CLK_SDSRC, 0x26c),
DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, R8A774E1_CLK_SD0H, 0x074),
DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, R8A774E1_CLK_SD1H, 0x078),
DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268),
DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c),
DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774E1_CLK_RPC),
DEF_FIXED("cl", R8A774E1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cr", R8A774E1_CLK_CR, CLK_PLL1_DIV4, 2, 1),
DEF_FIXED("cp", R8A774E1_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A774E1_CLK_CPEX, CLK_EXTAL, 2, 1),
DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
DEF_DIV6P1("csi0", R8A774E1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
DEF_DIV6P1("mso", R8A774E1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A774E1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
DEF_GEN3_OSC("osc", R8A774E1_CLK_OSC, CLK_EXTAL, 8),
DEF_BASE("r", R8A774E1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {
DEF_MOD("3dge", 112, R8A774E1_CLK_ZG),
DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A774E1_CLK_S3D2),
DEF_MOD("tmu2", 123, R8A774E1_CLK_S3D2),
DEF_MOD("tmu1", 124, R8A774E1_CLK_S3D2),
DEF_MOD("tmu0", 125, R8A774E1_CLK_CP),
DEF_MOD("vcplf", 130, R8A774E1_CLK_S2D1),
DEF_MOD("vdpb", 131, R8A774E1_CLK_S2D1),
DEF_MOD("scif5", 202, R8A774E1_CLK_S3D4),
DEF_MOD("scif4", 203, R8A774E1_CLK_S3D4),
DEF_MOD("scif3", 204, R8A774E1_CLK_S3D4),
DEF_MOD("scif1", 206, R8A774E1_CLK_S3D4),
DEF_MOD("scif0", 207, R8A774E1_CLK_S3D4),
DEF_MOD("msiof3", 208, R8A774E1_CLK_MSO),
DEF_MOD("msiof2", 209, R8A774E1_CLK_MSO),
DEF_MOD("msiof1", 210, R8A774E1_CLK_MSO),
DEF_MOD("msiof0", 211, R8A774E1_CLK_MSO),
DEF_MOD("sys-dmac2", 217, R8A774E1_CLK_S3D1),
DEF_MOD("sys-dmac1", 218, R8A774E1_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A774E1_CLK_S0D3),
DEF_MOD("cmt3", 300, R8A774E1_CLK_R),
DEF_MOD("cmt2", 301, R8A774E1_CLK_R),
DEF_MOD("cmt1", 302, R8A774E1_CLK_R),
DEF_MOD("cmt0", 303, R8A774E1_CLK_R),
DEF_MOD("tpu0", 304, R8A774E1_CLK_S3D4),
DEF_MOD("scif2", 310, R8A774E1_CLK_S3D4),
DEF_MOD("sdif3", 311, R8A774E1_CLK_SD3),
DEF_MOD("sdif2", 312, R8A774E1_CLK_SD2),
DEF_MOD("sdif1", 313, R8A774E1_CLK_SD1),
DEF_MOD("sdif0", 314, R8A774E1_CLK_SD0),
DEF_MOD("pcie1", 318, R8A774E1_CLK_S3D1),
DEF_MOD("pcie0", 319, R8A774E1_CLK_S3D1),
DEF_MOD("usb3-if0", 328, R8A774E1_CLK_S3D1),
DEF_MOD("usb-dmac0", 330, R8A774E1_CLK_S3D1),
DEF_MOD("usb-dmac1", 331, R8A774E1_CLK_S3D1),
DEF_MOD("rwdt", 402, R8A774E1_CLK_R),
DEF_MOD("intc-ex", 407, R8A774E1_CLK_CP),
DEF_MOD("intc-ap", 408, R8A774E1_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A774E1_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A774E1_CLK_S1D2),
DEF_MOD("hscif4", 516, R8A774E1_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A774E1_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A774E1_CLK_S3D1),
DEF_MOD("hscif1", 519, R8A774E1_CLK_S3D1),
DEF_MOD("hscif0", 520, R8A774E1_CLK_S3D1),
DEF_MOD("thermal", 522, R8A774E1_CLK_CP),
DEF_MOD("pwm", 523, R8A774E1_CLK_S0D12),
DEF_MOD("fcpvd1", 602, R8A774E1_CLK_S0D2),
DEF_MOD("fcpvd0", 603, R8A774E1_CLK_S0D2),
DEF_MOD("fcpvb1", 606, R8A774E1_CLK_S0D1),
DEF_MOD("fcpvb0", 607, R8A774E1_CLK_S0D1),
DEF_MOD("fcpvi1", 610, R8A774E1_CLK_S0D1),
DEF_MOD("fcpvi0", 611, R8A774E1_CLK_S0D1),
DEF_MOD("fcpf1", 614, R8A774E1_CLK_S0D1),
DEF_MOD("fcpf0", 615, R8A774E1_CLK_S0D1),
DEF_MOD("fcpcs", 619, R8A774E1_CLK_S0D1),
DEF_MOD("vspd1", 622, R8A774E1_CLK_S0D2),
DEF_MOD("vspd0", 623, R8A774E1_CLK_S0D2),
DEF_MOD("vspbc", 624, R8A774E1_CLK_S0D1),
DEF_MOD("vspbd", 626, R8A774E1_CLK_S0D1),
DEF_MOD("vspi1", 630, R8A774E1_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A774E1_CLK_S0D1),
DEF_MOD("ehci1", 702, R8A774E1_CLK_S3D2),
DEF_MOD("ehci0", 703, R8A774E1_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A774E1_CLK_S3D2),
DEF_MOD("csi20", 714, R8A774E1_CLK_CSI0),
DEF_MOD("csi40", 716, R8A774E1_CLK_CSI0),
DEF_MOD("du3", 721, R8A774E1_CLK_S2D1),
DEF_MOD("du1", 723, R8A774E1_CLK_S2D1),
DEF_MOD("du0", 724, R8A774E1_CLK_S2D1),
DEF_MOD("lvds", 727, R8A774E1_CLK_S0D4),
DEF_MOD("hdmi0", 729, R8A774E1_CLK_HDMI),
DEF_MOD("vin7", 804, R8A774E1_CLK_S0D2),
DEF_MOD("vin6", 805, R8A774E1_CLK_S0D2),
DEF_MOD("vin5", 806, R8A774E1_CLK_S0D2),
DEF_MOD("vin4", 807, R8A774E1_CLK_S0D2),
DEF_MOD("vin3", 808, R8A774E1_CLK_S0D2),
DEF_MOD("vin2", 809, R8A774E1_CLK_S0D2),
DEF_MOD("vin1", 810, R8A774E1_CLK_S0D2),
DEF_MOD("vin0", 811, R8A774E1_CLK_S0D2),
DEF_MOD("etheravb", 812, R8A774E1_CLK_S0D6),
DEF_MOD("sata0", 815, R8A774E1_CLK_S3D2),
DEF_MOD("gpio7", 905, R8A774E1_CLK_S3D4),
DEF_MOD("gpio6", 906, R8A774E1_CLK_S3D4),
DEF_MOD("gpio5", 907, R8A774E1_CLK_S3D4),
DEF_MOD("gpio4", 908, R8A774E1_CLK_S3D4),
DEF_MOD("gpio3", 909, R8A774E1_CLK_S3D4),
DEF_MOD("gpio2", 910, R8A774E1_CLK_S3D4),
DEF_MOD("gpio1", 911, R8A774E1_CLK_S3D4),
DEF_MOD("gpio0", 912, R8A774E1_CLK_S3D4),
DEF_MOD("can-fd", 914, R8A774E1_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774E1_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774E1_CLK_S3D4),
DEF_MOD("rpc-if", 917, R8A774E1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774E1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774E1_CLK_S0D6),
DEF_MOD("adg", 922, R8A774E1_CLK_S0D4),
DEF_MOD("iic-pmic", 926, R8A774E1_CLK_CP),
DEF_MOD("i2c4", 927, R8A774E1_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A774E1_CLK_S0D6),
DEF_MOD("i2c2", 929, R8A774E1_CLK_S3D2),
DEF_MOD("i2c1", 930, R8A774E1_CLK_S3D2),
DEF_MOD("i2c0", 931, R8A774E1_CLK_S3D2),
DEF_MOD("ssi-all", 1005, R8A774E1_CLK_S3D4),
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
DEF_MOD("scu-all", 1017, R8A774E1_CLK_S3D4),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
static const unsigned int r8a774e1_crit_mod_clks[] __initconst = {
MOD_CLK_ID(402), /* RWDT */
MOD_CLK_ID(408), /* INTC-AP (GIC) */
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
* 14 13 19 17 (MHz)
*-------------------------------------------------------------------------
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
* 0 0 1 0 Prohibited setting
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
* 0 1 1 0 Prohibited setting
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
* 1 0 1 0 Prohibited setting
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
* 1 1 1 0 Prohibited setting
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
(((md) & BIT(13)) >> 11) | \
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, 16, },
{ 0, /* Prohibited setting */ },
{ 1, 192, 1, 192, 1, 16, },
{ 1, 160, 1, 160, 1, 19, },
{ 1, 160, 1, 106, 1, 19, },
{ 0, /* Prohibited setting */ },
{ 1, 160, 1, 160, 1, 19, },
{ 1, 128, 1, 128, 1, 24, },
{ 1, 128, 1, 84, 1, 24, },
{ 0, /* Prohibited setting */ },
{ 1, 128, 1, 128, 1, 24, },
{ 2, 192, 1, 192, 1, 32, },
{ 2, 192, 1, 128, 1, 32, },
{ 0, /* Prohibited setting */ },
{ 2, 192, 1, 192, 1, 32, },
};
static int __init r8a774e1_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
u32 cpg_mode;
int error;
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
if (!cpg_pll_config->extal_div) {
dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
return -EINVAL;
}
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
}
const struct cpg_mssr_info r8a774e1_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a774e1_core_clks,
.num_core_clks = ARRAY_SIZE(r8a774e1_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a774e1_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a774e1_mod_clks),
.num_hw_mod_clks = 12 * 32,
/* Critical Module Clocks */
.crit_mod_clks = r8a774e1_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a774e1_crit_mod_clks),
/* Callbacks */
.init = r8a774e1_cpg_mssr_init,
.cpg_clk_register = rcar_gen3_cpg_clk_register,
};
| linux-master | drivers/clk/renesas/r8a774e1-cpg-mssr.c |
// SPDX-License-Identifier: GPL-2.0
/*
* R-Car MSTP clocks
*
* Copyright (C) 2013 Ideas On Board SPRL
* Copyright (C) 2015 Glider bvba
*
* Contact: Laurent Pinchart <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clk/renesas.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
#include <linux/spinlock.h>
/*
* MSTP clocks. We can't use standard gate clocks as we need to poll on the
* status register when enabling the clock.
*/
#define MSTP_MAX_CLOCKS 32
/**
* struct mstp_clock_group - MSTP gating clocks group
*
* @data: clock specifier translation for clocks in this group
* @smstpcr: module stop control register
* @mstpsr: module stop status register (optional)
* @lock: protects writes to SMSTPCR
* @width_8bit: registers are 8-bit, not 32-bit
* @clks: clocks in this group
*/
struct mstp_clock_group {
struct clk_onecell_data data;
void __iomem *smstpcr;
void __iomem *mstpsr;
spinlock_t lock;
bool width_8bit;
struct clk *clks[];
};
/**
* struct mstp_clock - MSTP gating clock
* @hw: handle between common and hardware-specific interfaces
* @bit_index: control bit index
* @group: MSTP clocks group
*/
struct mstp_clock {
struct clk_hw hw;
u32 bit_index;
struct mstp_clock_group *group;
};
#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
u32 __iomem *reg)
{
return group->width_8bit ? readb(reg) : readl(reg);
}
static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
u32 __iomem *reg)
{
group->width_8bit ? writeb(val, reg) : writel(val, reg);
}
static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
{
struct mstp_clock *clock = to_mstp_clock(hw);
struct mstp_clock_group *group = clock->group;
u32 bitmask = BIT(clock->bit_index);
unsigned long flags;
u32 value;
int ret;
spin_lock_irqsave(&group->lock, flags);
value = cpg_mstp_read(group, group->smstpcr);
if (enable)
value &= ~bitmask;
else
value |= bitmask;
cpg_mstp_write(group, value, group->smstpcr);
if (!group->mstpsr) {
/* dummy read to ensure write has completed */
cpg_mstp_read(group, group->smstpcr);
barrier_data(group->smstpcr);
}
spin_unlock_irqrestore(&group->lock, flags);
if (!enable || !group->mstpsr)
return 0;
/* group->width_8bit is always false if group->mstpsr is present */
ret = readl_poll_timeout_atomic(group->mstpsr, value,
!(value & bitmask), 0, 10);
if (ret)
pr_err("%s: failed to enable %p[%d]\n", __func__,
group->smstpcr, clock->bit_index);
return ret;
}
static int cpg_mstp_clock_enable(struct clk_hw *hw)
{
return cpg_mstp_clock_endisable(hw, true);
}
static void cpg_mstp_clock_disable(struct clk_hw *hw)
{
cpg_mstp_clock_endisable(hw, false);
}
static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
{
struct mstp_clock *clock = to_mstp_clock(hw);
struct mstp_clock_group *group = clock->group;
u32 value;
if (group->mstpsr)
value = cpg_mstp_read(group, group->mstpsr);
else
value = cpg_mstp_read(group, group->smstpcr);
return !(value & BIT(clock->bit_index));
}
static const struct clk_ops cpg_mstp_clock_ops = {
.enable = cpg_mstp_clock_enable,
.disable = cpg_mstp_clock_disable,
.is_enabled = cpg_mstp_clock_is_enabled,
};
static struct clk * __init cpg_mstp_clock_register(const char *name,
const char *parent_name, unsigned int index,
struct mstp_clock_group *group)
{
struct clk_init_data init = {};
struct mstp_clock *clock;
struct clk *clk;
clock = kzalloc(sizeof(*clock), GFP_KERNEL);
if (!clock)
return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = &cpg_mstp_clock_ops;
init.flags = CLK_SET_RATE_PARENT;
/* INTC-SYS is the module clock of the GIC, and must not be disabled */
if (!strcmp(name, "intc-sys")) {
pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name);
init.flags |= CLK_IS_CRITICAL;
}
init.parent_names = &parent_name;
init.num_parents = 1;
clock->bit_index = index;
clock->group = group;
clock->hw.init = &init;
clk = clk_register(NULL, &clock->hw);
if (IS_ERR(clk))
kfree(clock);
return clk;
}
static void __init cpg_mstp_clocks_init(struct device_node *np)
{
struct mstp_clock_group *group;
const char *idxname;
struct clk **clks;
unsigned int i;
group = kzalloc(struct_size(group, clks, MSTP_MAX_CLOCKS), GFP_KERNEL);
if (!group)
return;
clks = group->clks;
spin_lock_init(&group->lock);
group->data.clks = clks;
group->smstpcr = of_iomap(np, 0);
group->mstpsr = of_iomap(np, 1);
if (group->smstpcr == NULL) {
pr_err("%s: failed to remap SMSTPCR\n", __func__);
kfree(group);
return;
}
if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))
group->width_8bit = true;
for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
clks[i] = ERR_PTR(-ENOENT);
if (of_find_property(np, "clock-indices", &i))
idxname = "clock-indices";
else
idxname = "renesas,clock-indices";
for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
const char *parent_name;
const char *name;
u32 clkidx;
int ret;
/* Skip clocks with no name. */
ret = of_property_read_string_index(np, "clock-output-names",
i, &name);
if (ret < 0 || strlen(name) == 0)
continue;
parent_name = of_clk_get_parent_name(np, i);
ret = of_property_read_u32_index(np, idxname, i, &clkidx);
if (parent_name == NULL || ret < 0)
break;
if (clkidx >= MSTP_MAX_CLOCKS) {
pr_err("%s: invalid clock %pOFn %s index %u\n",
__func__, np, name, clkidx);
continue;
}
clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
clkidx, group);
if (!IS_ERR(clks[clkidx])) {
group->data.clk_num = max(group->data.clk_num,
clkidx + 1);
/*
* Register a clkdev to let board code retrieve the
* clock by name and register aliases for non-DT
* devices.
*
* FIXME: Remove this when all devices that require a
* clock will be instantiated from DT.
*/
clk_register_clkdev(clks[clkidx], name, NULL);
} else {
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
__func__, np, name, PTR_ERR(clks[clkidx]));
}
}
of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
}
CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev)
{
struct device_node *np = dev->of_node;
struct of_phandle_args clkspec;
struct clk *clk;
int i = 0;
int error;
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
&clkspec)) {
if (of_device_is_compatible(clkspec.np,
"renesas,cpg-mstp-clocks"))
goto found;
/* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */
if (of_node_name_eq(clkspec.np, "zb_clk"))
goto found;
of_node_put(clkspec.np);
i++;
}
return 0;
found:
clk = of_clk_get_from_provider(&clkspec);
of_node_put(clkspec.np);
if (IS_ERR(clk))
return PTR_ERR(clk);
error = pm_clk_create(dev);
if (error)
goto fail_put;
error = pm_clk_add_clk(dev, clk);
if (error)
goto fail_destroy;
return 0;
fail_destroy:
pm_clk_destroy(dev);
fail_put:
clk_put(clk);
return error;
}
void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)
{
if (!pm_clk_no_clocks(dev))
pm_clk_destroy(dev);
}
void __init cpg_mstp_add_clk_domain(struct device_node *np)
{
struct generic_pm_domain *pd;
u32 ncells;
if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
pr_warn("%pOF lacks #power-domain-cells\n", np);
return;
}
pd = kzalloc(sizeof(*pd), GFP_KERNEL);
if (!pd)
return;
pd->name = np->name;
pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
GENPD_FLAG_ACTIVE_WAKEUP;
pd->attach_dev = cpg_mstp_attach_dev;
pd->detach_dev = cpg_mstp_detach_dev;
pm_genpd_init(pd, &pm_domain_always_on_gov, false);
of_genpd_add_provider_simple(np, pd);
}
| linux-master | drivers/clk/renesas/clk-mstp.c |
// SPDX-License-Identifier: GPL-2.0
/*
* EMMA Mobile EV2 common clock framework support
*
* Copyright (C) 2013 Takashi Yoshii <[email protected]>
* Copyright (C) 2012 Magnus Damm
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
/* EMEV2 SMU registers */
#define USIAU0_RSTCTRL 0x094
#define USIBU1_RSTCTRL 0x0ac
#define USIBU2_RSTCTRL 0x0b0
#define USIBU3_RSTCTRL 0x0b4
#define IIC0_RSTCTRL 0x0dc
#define IIC1_RSTCTRL 0x0e0
#define STI_RSTCTRL 0x124
#define STI_CLKSEL 0x688
static DEFINE_SPINLOCK(lock);
/* not pretty, but hey */
static void __iomem *smu_base;
static void __init emev2_smu_write(unsigned long value, int offs)
{
BUG_ON(!smu_base || (offs >= PAGE_SIZE));
writel_relaxed(value, smu_base + offs);
}
static const struct of_device_id smu_id[] __initconst = {
{ .compatible = "renesas,emev2-smu", },
{},
};
static void __init emev2_smu_init(void)
{
struct device_node *np;
np = of_find_matching_node(NULL, smu_id);
BUG_ON(!np);
smu_base = of_iomap(np, 0);
BUG_ON(!smu_base);
of_node_put(np);
/* setup STI timer to run on 32.768 kHz and deassert reset */
emev2_smu_write(0, STI_CLKSEL);
emev2_smu_write(1, STI_RSTCTRL);
/* deassert reset for UART0->UART3 */
emev2_smu_write(2, USIAU0_RSTCTRL);
emev2_smu_write(2, USIBU1_RSTCTRL);
emev2_smu_write(2, USIBU2_RSTCTRL);
emev2_smu_write(2, USIBU3_RSTCTRL);
/* deassert reset for IIC0->IIC1 */
emev2_smu_write(1, IIC0_RSTCTRL);
emev2_smu_write(1, IIC1_RSTCTRL);
}
static void __init emev2_smu_clkdiv_init(struct device_node *np)
{
u32 reg[2];
struct clk *clk;
const char *parent_name = of_clk_get_parent_name(np, 0);
if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
return;
if (!smu_base)
emev2_smu_init();
clk = clk_register_divider(NULL, np->name, parent_name, 0,
smu_base + reg[0], reg[1], 8, 0, &lock);
of_clk_add_provider(np, of_clk_src_simple_get, clk);
pr_debug("## %s %pOFn %p\n", __func__, np, clk);
}
CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv",
emev2_smu_clkdiv_init);
static void __init emev2_smu_gclk_init(struct device_node *np)
{
u32 reg[2];
struct clk *clk;
const char *parent_name = of_clk_get_parent_name(np, 0);
if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
return;
if (!smu_base)
emev2_smu_init();
clk = clk_register_gate(NULL, np->name, parent_name, 0,
smu_base + reg[0], reg[1], 0, &lock);
of_clk_add_provider(np, of_clk_src_simple_get, clk);
pr_debug("## %s %pOFn %p\n", __func__, np, clk);
}
CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);
| linux-master | drivers/clk/renesas/clk-emev2.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r8a7790 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2017 Glider bvba
*
* Based on clk-rcar-gen2.c
*
* Copyright (C) 2013 Ideas On Board SPRL
*/
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen2-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A7790_CLK_OSC,
/* External Input Clocks */
CLK_EXTAL,
CLK_USB_EXTAL,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
CLK_PLL3,
CLK_PLL1_DIV2,
/* Module Clocks */
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a7790_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
/* Core Clock Outputs */
DEF_BASE("z", R8A7790_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
DEF_BASE("lb", R8A7790_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
DEF_BASE("adsp", R8A7790_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
DEF_BASE("sdh", R8A7790_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
DEF_BASE("sd0", R8A7790_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
DEF_BASE("sd1", R8A7790_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
DEF_BASE("qspi", R8A7790_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
DEF_BASE("rcan", R8A7790_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
DEF_FIXED("z2", R8A7790_CLK_Z2, CLK_PLL1, 2, 1),
DEF_FIXED("zg", R8A7790_CLK_ZG, CLK_PLL1, 3, 1),
DEF_FIXED("zx", R8A7790_CLK_ZX, CLK_PLL1, 3, 1),
DEF_FIXED("zs", R8A7790_CLK_ZS, CLK_PLL1, 6, 1),
DEF_FIXED("hp", R8A7790_CLK_HP, CLK_PLL1, 12, 1),
DEF_FIXED("i", R8A7790_CLK_I, CLK_PLL1, 2, 1),
DEF_FIXED("b", R8A7790_CLK_B, CLK_PLL1, 12, 1),
DEF_FIXED("p", R8A7790_CLK_P, CLK_PLL1, 24, 1),
DEF_FIXED("cl", R8A7790_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("m2", R8A7790_CLK_M2, CLK_PLL1, 8, 1),
DEF_FIXED("imp", R8A7790_CLK_IMP, CLK_PLL1, 4, 1),
DEF_FIXED("zb3", R8A7790_CLK_ZB3, CLK_PLL3, 4, 1),
DEF_FIXED("zb3d2", R8A7790_CLK_ZB3D2, CLK_PLL3, 8, 1),
DEF_FIXED("ddr", R8A7790_CLK_DDR, CLK_PLL3, 8, 1),
DEF_FIXED("mp", R8A7790_CLK_MP, CLK_PLL1_DIV2, 15, 1),
DEF_FIXED("cp", R8A7790_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("r", R8A7790_CLK_R, CLK_PLL1, 49152, 1),
DEF_FIXED("osc", R8A7790_CLK_OSC, CLK_PLL1, 12288, 1),
DEF_DIV6P1("sd2", R8A7790_CLK_SD2, CLK_PLL1_DIV2, 0x078),
DEF_DIV6P1("sd3", R8A7790_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
DEF_DIV6P1("mmc0", R8A7790_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
DEF_DIV6P1("mmc1", R8A7790_CLK_MMC1, CLK_PLL1_DIV2, 0x244),
DEF_DIV6P1("ssp", R8A7790_CLK_SSP, CLK_PLL1_DIV2, 0x248),
DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
};
static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7790_CLK_MP),
DEF_MOD("vcp1", 100, R8A7790_CLK_ZS),
DEF_MOD("vcp0", 101, R8A7790_CLK_ZS),
DEF_MOD("vpc1", 102, R8A7790_CLK_ZS),
DEF_MOD("vpc0", 103, R8A7790_CLK_ZS),
DEF_MOD("jpu", 106, R8A7790_CLK_M2),
DEF_MOD("ssp1", 109, R8A7790_CLK_ZS),
DEF_MOD("tmu1", 111, R8A7790_CLK_P),
DEF_MOD("3dg", 112, R8A7790_CLK_ZG),
DEF_MOD("2d-dmac", 115, R8A7790_CLK_ZS),
DEF_MOD("fdp1-2", 117, R8A7790_CLK_ZS),
DEF_MOD("fdp1-1", 118, R8A7790_CLK_ZS),
DEF_MOD("fdp1-0", 119, R8A7790_CLK_ZS),
DEF_MOD("tmu3", 121, R8A7790_CLK_P),
DEF_MOD("tmu2", 122, R8A7790_CLK_P),
DEF_MOD("cmt0", 124, R8A7790_CLK_R),
DEF_MOD("tmu0", 125, R8A7790_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7790_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7790_CLK_ZS),
DEF_MOD("vspr", 130, R8A7790_CLK_ZS),
DEF_MOD("vsps", 131, R8A7790_CLK_ZS),
DEF_MOD("scifa2", 202, R8A7790_CLK_MP),
DEF_MOD("scifa1", 203, R8A7790_CLK_MP),
DEF_MOD("scifa0", 204, R8A7790_CLK_MP),
DEF_MOD("msiof2", 205, R8A7790_CLK_MP),
DEF_MOD("scifb0", 206, R8A7790_CLK_MP),
DEF_MOD("scifb1", 207, R8A7790_CLK_MP),
DEF_MOD("msiof1", 208, R8A7790_CLK_MP),
DEF_MOD("msiof3", 215, R8A7790_CLK_MP),
DEF_MOD("scifb2", 216, R8A7790_CLK_MP),
DEF_MOD("sys-dmac1", 218, R8A7790_CLK_ZS),
DEF_MOD("sys-dmac0", 219, R8A7790_CLK_ZS),
DEF_MOD("iic2", 300, R8A7790_CLK_HP),
DEF_MOD("tpu0", 304, R8A7790_CLK_CP),
DEF_MOD("mmcif1", 305, R8A7790_CLK_MMC1),
DEF_MOD("scif2", 310, R8A7790_CLK_P),
DEF_MOD("sdhi3", 311, R8A7790_CLK_SD3),
DEF_MOD("sdhi2", 312, R8A7790_CLK_SD2),
DEF_MOD("sdhi1", 313, R8A7790_CLK_SD1),
DEF_MOD("sdhi0", 314, R8A7790_CLK_SD0),
DEF_MOD("mmcif0", 315, R8A7790_CLK_MMC0),
DEF_MOD("iic0", 318, R8A7790_CLK_HP),
DEF_MOD("pciec", 319, R8A7790_CLK_MP),
DEF_MOD("iic1", 323, R8A7790_CLK_HP),
DEF_MOD("usb3.0", 328, R8A7790_CLK_MP),
DEF_MOD("cmt1", 329, R8A7790_CLK_R),
DEF_MOD("usbhs-dmac0", 330, R8A7790_CLK_HP),
DEF_MOD("usbhs-dmac1", 331, R8A7790_CLK_HP),
DEF_MOD("rwdt", 402, R8A7790_CLK_R),
DEF_MOD("irqc", 407, R8A7790_CLK_CP),
DEF_MOD("intc-sys", 408, R8A7790_CLK_ZS),
DEF_MOD("audio-dmac1", 501, R8A7790_CLK_HP),
DEF_MOD("audio-dmac0", 502, R8A7790_CLK_HP),
DEF_MOD("adsp_mod", 506, R8A7790_CLK_ADSP),
DEF_MOD("thermal", 522, CLK_EXTAL),
DEF_MOD("pwm", 523, R8A7790_CLK_P),
DEF_MOD("usb-ehci", 703, R8A7790_CLK_MP),
DEF_MOD("usbhs", 704, R8A7790_CLK_HP),
DEF_MOD("hscif1", 716, R8A7790_CLK_ZS),
DEF_MOD("hscif0", 717, R8A7790_CLK_ZS),
DEF_MOD("scif1", 720, R8A7790_CLK_P),
DEF_MOD("scif0", 721, R8A7790_CLK_P),
DEF_MOD("du2", 722, R8A7790_CLK_ZX),
DEF_MOD("du1", 723, R8A7790_CLK_ZX),
DEF_MOD("du0", 724, R8A7790_CLK_ZX),
DEF_MOD("lvds1", 725, R8A7790_CLK_ZX),
DEF_MOD("lvds0", 726, R8A7790_CLK_ZX),
DEF_MOD("mlb", 802, R8A7790_CLK_HP),
DEF_MOD("vin3", 808, R8A7790_CLK_ZG),
DEF_MOD("vin2", 809, R8A7790_CLK_ZG),
DEF_MOD("vin1", 810, R8A7790_CLK_ZG),
DEF_MOD("vin0", 811, R8A7790_CLK_ZG),
DEF_MOD("etheravb", 812, R8A7790_CLK_HP),
DEF_MOD("ether", 813, R8A7790_CLK_P),
DEF_MOD("sata1", 814, R8A7790_CLK_ZS),
DEF_MOD("sata0", 815, R8A7790_CLK_ZS),
DEF_MOD("gyro-adc", 901, R8A7790_CLK_P),
DEF_MOD("gpio5", 907, R8A7790_CLK_CP),
DEF_MOD("gpio4", 908, R8A7790_CLK_CP),
DEF_MOD("gpio3", 909, R8A7790_CLK_CP),
DEF_MOD("gpio2", 910, R8A7790_CLK_CP),
DEF_MOD("gpio1", 911, R8A7790_CLK_CP),
DEF_MOD("gpio0", 912, R8A7790_CLK_CP),
DEF_MOD("can1", 915, R8A7790_CLK_P),
DEF_MOD("can0", 916, R8A7790_CLK_P),
DEF_MOD("qspi_mod", 917, R8A7790_CLK_QSPI),
DEF_MOD("iicdvfs", 926, R8A7790_CLK_CP),
DEF_MOD("i2c3", 928, R8A7790_CLK_HP),
DEF_MOD("i2c2", 929, R8A7790_CLK_HP),
DEF_MOD("i2c1", 930, R8A7790_CLK_HP),
DEF_MOD("i2c0", 931, R8A7790_CLK_HP),
DEF_MOD("ssi-all", 1005, R8A7790_CLK_P),
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
DEF_MOD("scu-all", 1017, R8A7790_CLK_P),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
static const unsigned int r8a7790_crit_mod_clks[] __initconst = {
MOD_CLK_ID(402), /* RWDT */
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL3
* 14 13 19 (MHz) *1 *1
*---------------------------------------------------
* 0 0 0 15 x172/2 x208/2 x106
* 0 0 1 15 x172/2 x208/2 x88
* 0 1 0 20 x130/2 x156/2 x80
* 0 1 1 20 x130/2 x156/2 x66
* 1 0 0 26 / 2 x200/2 x240/2 x122
* 1 0 1 26 / 2 x200/2 x240/2 x102
* 1 1 0 30 / 2 x172/2 x208/2 x106
* 1 1 1 30 / 2 x172/2 x208/2 x88
*
* *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
};
static int __init r8a7790_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
u32 cpg_mode;
int error;
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
}
const struct cpg_mssr_info r8a7790_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a7790_core_clks,
.num_core_clks = ARRAY_SIZE(r8a7790_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a7790_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a7790_mod_clks),
.num_hw_mod_clks = 12 * 32,
/* Critical Module Clocks */
.crit_mod_clks = r8a7790_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a7790_crit_mod_clks),
/* Callbacks */
.init = r8a7790_cpg_mssr_init,
.cpg_clk_register = rcar_gen2_cpg_clk_register,
};
| linux-master | drivers/clk/renesas/r8a7790-cpg-mssr.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r8a7778 Core CPG Clocks
*
* Copyright (C) 2014 Ulrich Hecht
*/
#include <linux/clk-provider.h>
#include <linux/clk/renesas.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/soc/renesas/rcar-rst.h>
/* PLL multipliers per bits 11, 12, and 18 of MODEMR */
static const struct {
unsigned long plla_mult;
unsigned long pllb_mult;
} r8a7778_rates[] __initconst = {
[0] = { 21, 21 },
[1] = { 24, 24 },
[2] = { 28, 28 },
[3] = { 32, 32 },
[5] = { 24, 21 },
[6] = { 28, 21 },
[7] = { 32, 24 },
};
/* Clock dividers per bits 1 and 2 of MODEMR */
static const struct {
const char *name;
unsigned int div[4];
} r8a7778_divs[6] __initconst = {
{ "b", { 12, 12, 16, 18 } },
{ "out", { 12, 12, 16, 18 } },
{ "p", { 16, 12, 16, 12 } },
{ "s", { 4, 3, 4, 3 } },
{ "s1", { 8, 6, 8, 6 } },
};
static u32 cpg_mode_rates __initdata;
static u32 cpg_mode_divs __initdata;
static struct clk * __init
r8a7778_cpg_register_clock(struct device_node *np, const char *name)
{
if (!strcmp(name, "plla")) {
return clk_register_fixed_factor(NULL, "plla",
of_clk_get_parent_name(np, 0), 0,
r8a7778_rates[cpg_mode_rates].plla_mult, 1);
} else if (!strcmp(name, "pllb")) {
return clk_register_fixed_factor(NULL, "pllb",
of_clk_get_parent_name(np, 0), 0,
r8a7778_rates[cpg_mode_rates].pllb_mult, 1);
} else {
unsigned int i;
for (i = 0; i < ARRAY_SIZE(r8a7778_divs); i++) {
if (!strcmp(name, r8a7778_divs[i].name)) {
return clk_register_fixed_factor(NULL,
r8a7778_divs[i].name,
"plla", 0, 1,
r8a7778_divs[i].div[cpg_mode_divs]);
}
}
}
return ERR_PTR(-EINVAL);
}
static void __init r8a7778_cpg_clocks_init(struct device_node *np)
{
struct clk_onecell_data *data;
struct clk **clks;
unsigned int i;
int num_clks;
u32 mode;
if (rcar_rst_read_mode_pins(&mode))
return;
BUG_ON(!(mode & BIT(19)));
cpg_mode_rates = (!!(mode & BIT(18)) << 2) |
(!!(mode & BIT(12)) << 1) |
(!!(mode & BIT(11)));
cpg_mode_divs = (!!(mode & BIT(2)) << 1) |
(!!(mode & BIT(1)));
num_clks = of_property_count_strings(np, "clock-output-names");
if (num_clks < 0) {
pr_err("%s: failed to count clocks\n", __func__);
return;
}
data = kzalloc(sizeof(*data), GFP_KERNEL);
clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
if (data == NULL || clks == NULL) {
/* We're leaking memory on purpose, there's no point in cleaning
* up as the system won't boot anyway.
*/
return;
}
data->clks = clks;
data->clk_num = num_clks;
for (i = 0; i < num_clks; ++i) {
const char *name;
struct clk *clk;
of_property_read_string_index(np, "clock-output-names", i,
&name);
clk = r8a7778_cpg_register_clock(np, name);
if (IS_ERR(clk))
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
__func__, np, name, PTR_ERR(clk));
else
data->clks[i] = clk;
}
of_clk_add_provider(np, of_clk_src_onecell_get, data);
cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
r8a7778_cpg_clocks_init);
| linux-master | drivers/clk/renesas/clk-r8a7778.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r8a77965 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2018 Jacopo Mondi <[email protected]>
* Copyright (C) 2019 Renesas Electronics Corp.
*
* Based on r8a7795-cpg-mssr.c
*
* Copyright (C) 2015 Glider bvba
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a77965-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A77965_CLK_OSC,
/* External Input Clocks */
CLK_EXTAL,
CLK_EXTALR,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
CLK_PLL3,
CLK_PLL4,
CLK_PLL1_DIV2,
CLK_PLL1_DIV4,
CLK_S0,
CLK_S1,
CLK_S2,
CLK_S3,
CLK_SDSRC,
CLK_SSPSRC,
CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("zg", R8A77965_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED("zx", R8A77965_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED("s0d1", R8A77965_CLK_S0D1, CLK_S0, 1, 1),
DEF_FIXED("s0d2", R8A77965_CLK_S0D2, CLK_S0, 2, 1),
DEF_FIXED("s0d3", R8A77965_CLK_S0D3, CLK_S0, 3, 1),
DEF_FIXED("s0d4", R8A77965_CLK_S0D4, CLK_S0, 4, 1),
DEF_FIXED("s0d6", R8A77965_CLK_S0D6, CLK_S0, 6, 1),
DEF_FIXED("s0d8", R8A77965_CLK_S0D8, CLK_S0, 8, 1),
DEF_FIXED("s0d12", R8A77965_CLK_S0D12, CLK_S0, 12, 1),
DEF_FIXED("s1d1", R8A77965_CLK_S1D1, CLK_S1, 1, 1),
DEF_FIXED("s1d2", R8A77965_CLK_S1D2, CLK_S1, 2, 1),
DEF_FIXED("s1d4", R8A77965_CLK_S1D4, CLK_S1, 4, 1),
DEF_FIXED("s2d1", R8A77965_CLK_S2D1, CLK_S2, 1, 1),
DEF_FIXED("s2d2", R8A77965_CLK_S2D2, CLK_S2, 2, 1),
DEF_FIXED("s2d4", R8A77965_CLK_S2D4, CLK_S2, 4, 1),
DEF_FIXED("s3d1", R8A77965_CLK_S3D1, CLK_S3, 1, 1),
DEF_FIXED("s3d2", R8A77965_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A77965_CLK_S3D4, CLK_S3, 4, 1),
DEF_GEN3_SDH("sd0h", R8A77965_CLK_SD0H, CLK_SDSRC, 0x074),
DEF_GEN3_SDH("sd1h", R8A77965_CLK_SD1H, CLK_SDSRC, 0x078),
DEF_GEN3_SDH("sd2h", R8A77965_CLK_SD2H, CLK_SDSRC, 0x268),
DEF_GEN3_SDH("sd3h", R8A77965_CLK_SD3H, CLK_SDSRC, 0x26c),
DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, R8A77965_CLK_SD0H, 0x074),
DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H, 0x078),
DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268),
DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c),
DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77965_CLK_RPC),
DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1),
DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A77965_CLK_CPEX, CLK_EXTAL, 2, 1),
DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
DEF_GEN3_OSC("osc", R8A77965_CLK_OSC, CLK_EXTAL, 8),
DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
DEF_MOD("3dge", 112, R8A77965_CLK_ZG),
DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A77965_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A77965_CLK_S3D2),
DEF_MOD("tmu2", 123, R8A77965_CLK_S3D2),
DEF_MOD("tmu1", 124, R8A77965_CLK_S3D2),
DEF_MOD("tmu0", 125, R8A77965_CLK_CP),
DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
DEF_MOD("scif1", 206, R8A77965_CLK_S3D4),
DEF_MOD("scif0", 207, R8A77965_CLK_S3D4),
DEF_MOD("msiof3", 208, R8A77965_CLK_MSO),
DEF_MOD("msiof2", 209, R8A77965_CLK_MSO),
DEF_MOD("msiof1", 210, R8A77965_CLK_MSO),
DEF_MOD("msiof0", 211, R8A77965_CLK_MSO),
DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),
DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
DEF_MOD("sceg-pub", 229, R8A77965_CLK_CR),
DEF_MOD("cmt3", 300, R8A77965_CLK_R),
DEF_MOD("cmt2", 301, R8A77965_CLK_R),
DEF_MOD("cmt1", 302, R8A77965_CLK_R),
DEF_MOD("cmt0", 303, R8A77965_CLK_R),
DEF_MOD("tpu0", 304, R8A77965_CLK_S3D4),
DEF_MOD("scif2", 310, R8A77965_CLK_S3D4),
DEF_MOD("sdif3", 311, R8A77965_CLK_SD3),
DEF_MOD("sdif2", 312, R8A77965_CLK_SD2),
DEF_MOD("sdif1", 313, R8A77965_CLK_SD1),
DEF_MOD("sdif0", 314, R8A77965_CLK_SD0),
DEF_MOD("pcie1", 318, R8A77965_CLK_S3D1),
DEF_MOD("pcie0", 319, R8A77965_CLK_S3D1),
DEF_MOD("usb3-if0", 328, R8A77965_CLK_S3D1),
DEF_MOD("usb-dmac0", 330, R8A77965_CLK_S3D1),
DEF_MOD("usb-dmac1", 331, R8A77965_CLK_S3D1),
DEF_MOD("rwdt", 402, R8A77965_CLK_R),
DEF_MOD("intc-ex", 407, R8A77965_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A77965_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A77965_CLK_S1D2),
DEF_MOD("drif31", 508, R8A77965_CLK_S3D2),
DEF_MOD("drif30", 509, R8A77965_CLK_S3D2),
DEF_MOD("drif21", 510, R8A77965_CLK_S3D2),
DEF_MOD("drif20", 511, R8A77965_CLK_S3D2),
DEF_MOD("drif11", 512, R8A77965_CLK_S3D2),
DEF_MOD("drif10", 513, R8A77965_CLK_S3D2),
DEF_MOD("drif01", 514, R8A77965_CLK_S3D2),
DEF_MOD("drif00", 515, R8A77965_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1),
DEF_MOD("hscif1", 519, R8A77965_CLK_S3D1),
DEF_MOD("hscif0", 520, R8A77965_CLK_S3D1),
DEF_MOD("thermal", 522, R8A77965_CLK_CP),
DEF_MOD("pwm", 523, R8A77965_CLK_S0D12),
DEF_MOD("fcpvd1", 602, R8A77965_CLK_S0D2),
DEF_MOD("fcpvd0", 603, R8A77965_CLK_S0D2),
DEF_MOD("fcpvb0", 607, R8A77965_CLK_S0D1),
DEF_MOD("fcpvi0", 611, R8A77965_CLK_S0D1),
DEF_MOD("fcpf0", 615, R8A77965_CLK_S0D1),
DEF_MOD("fcpcs", 619, R8A77965_CLK_S0D2),
DEF_MOD("vspd1", 622, R8A77965_CLK_S0D2),
DEF_MOD("vspd0", 623, R8A77965_CLK_S0D2),
DEF_MOD("vspb", 626, R8A77965_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1),
DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2),
DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A77965_CLK_S3D2),
DEF_MOD("cmm3", 708, R8A77965_CLK_S2D1),
DEF_MOD("cmm1", 710, R8A77965_CLK_S2D1),
DEF_MOD("cmm0", 711, R8A77965_CLK_S2D1),
DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
DEF_MOD("du3", 721, R8A77965_CLK_S2D1),
DEF_MOD("du1", 723, R8A77965_CLK_S2D1),
DEF_MOD("du0", 724, R8A77965_CLK_S2D1),
DEF_MOD("lvds", 727, R8A77965_CLK_S2D1),
DEF_MOD("hdmi0", 729, R8A77965_CLK_HDMI),
DEF_MOD("mlp", 802, R8A77965_CLK_S2D1),
DEF_MOD("vin7", 804, R8A77965_CLK_S0D2),
DEF_MOD("vin6", 805, R8A77965_CLK_S0D2),
DEF_MOD("vin5", 806, R8A77965_CLK_S0D2),
DEF_MOD("vin4", 807, R8A77965_CLK_S0D2),
DEF_MOD("vin3", 808, R8A77965_CLK_S0D2),
DEF_MOD("vin2", 809, R8A77965_CLK_S0D2),
DEF_MOD("vin1", 810, R8A77965_CLK_S0D2),
DEF_MOD("vin0", 811, R8A77965_CLK_S0D2),
DEF_MOD("etheravb", 812, R8A77965_CLK_S0D6),
DEF_MOD("sata0", 815, R8A77965_CLK_S3D2),
DEF_MOD("imr1", 822, R8A77965_CLK_S0D2),
DEF_MOD("imr0", 823, R8A77965_CLK_S0D2),
DEF_MOD("gpio7", 905, R8A77965_CLK_S3D4),
DEF_MOD("gpio6", 906, R8A77965_CLK_S3D4),
DEF_MOD("gpio5", 907, R8A77965_CLK_S3D4),
DEF_MOD("gpio4", 908, R8A77965_CLK_S3D4),
DEF_MOD("gpio3", 909, R8A77965_CLK_S3D4),
DEF_MOD("gpio2", 910, R8A77965_CLK_S3D4),
DEF_MOD("gpio1", 911, R8A77965_CLK_S3D4),
DEF_MOD("gpio0", 912, R8A77965_CLK_S3D4),
DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4),
DEF_MOD("rpc-if", 917, R8A77965_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6),
DEF_MOD("adg", 922, R8A77965_CLK_S0D4),
DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP),
DEF_MOD("i2c4", 927, R8A77965_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A77965_CLK_S0D6),
DEF_MOD("i2c2", 929, R8A77965_CLK_S3D2),
DEF_MOD("i2c1", 930, R8A77965_CLK_S3D2),
DEF_MOD("i2c0", 931, R8A77965_CLK_S3D2),
DEF_MOD("ssi-all", 1005, R8A77965_CLK_S3D4),
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
DEF_MOD("dab", 1016, R8A77965_CLK_S0D6),
DEF_MOD("scu-all", 1017, R8A77965_CLK_S3D4),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
static const unsigned int r8a77965_crit_mod_clks[] __initconst = {
MOD_CLK_ID(402), /* RWDT */
MOD_CLK_ID(408), /* INTC-AP (GIC) */
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
* 14 13 19 17 (MHz)
*-----------------------------------------------------------------
* 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
* 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16
* 0 0 1 0 Prohibited setting
* 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16
* 0 1 0 0 20 x 1 x150 x160 x160 x120 /19
* 0 1 0 1 20 x 1 x150 x160 x106 x120 /19
* 0 1 1 0 Prohibited setting
* 0 1 1 1 20 x 1 x150 x160 x160 x120 /19
* 1 0 0 0 25 x 1 x120 x128 x128 x96 /24
* 1 0 0 1 25 x 1 x120 x128 x84 x96 /24
* 1 0 1 0 Prohibited setting
* 1 0 1 1 25 x 1 x120 x128 x128 x96 /24
* 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32
* 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32
* 1 1 1 0 Prohibited setting
* 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
(((md) & BIT(13)) >> 11) | \
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, 16, },
{ 0, /* Prohibited setting */ },
{ 1, 192, 1, 192, 1, 16, },
{ 1, 160, 1, 160, 1, 19, },
{ 1, 160, 1, 106, 1, 19, },
{ 0, /* Prohibited setting */ },
{ 1, 160, 1, 160, 1, 19, },
{ 1, 128, 1, 128, 1, 24, },
{ 1, 128, 1, 84, 1, 24, },
{ 0, /* Prohibited setting */ },
{ 1, 128, 1, 128, 1, 24, },
{ 2, 192, 1, 192, 1, 32, },
{ 2, 192, 1, 128, 1, 32, },
{ 0, /* Prohibited setting */ },
{ 2, 192, 1, 192, 1, 32, },
};
static int __init r8a77965_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
u32 cpg_mode;
int error;
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
if (!cpg_pll_config->extal_div) {
dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
return -EINVAL;
}
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
}
const struct cpg_mssr_info r8a77965_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a77965_core_clks,
.num_core_clks = ARRAY_SIZE(r8a77965_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a77965_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a77965_mod_clks),
.num_hw_mod_clks = 12 * 32,
/* Critical Module Clocks */
.crit_mod_clks = r8a77965_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a77965_crit_mod_clks),
/* Callbacks */
.init = r8a77965_cpg_mssr_init,
.cpg_clk_register = rcar_gen3_cpg_clk_register,
};
| linux-master | drivers/clk/renesas/r8a77965-cpg-mssr.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r8a7795 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2015 Glider bvba
* Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* Based on clk-rcar-gen3.c
*
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <linux/sys_soc.h>
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A7795_CLK_S0D12,
/* External Input Clocks */
CLK_EXTAL,
CLK_EXTALR,
/* Internal Core Clocks */
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
CLK_PLL2,
CLK_PLL3,
CLK_PLL4,
CLK_PLL1_DIV2,
CLK_PLL1_DIV4,
CLK_S0,
CLK_S1,
CLK_S2,
CLK_S3,
CLK_SDSRC,
CLK_SSPSRC,
CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
MOD_CLK_BASE
};
static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
DEF_GEN3_Z("zg", R8A7795_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1),
DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
DEF_GEN3_SDH("sd0h", R8A7795_CLK_SD0H, CLK_SDSRC, 0x074),
DEF_GEN3_SDH("sd1h", R8A7795_CLK_SD1H, CLK_SDSRC, 0x078),
DEF_GEN3_SDH("sd2h", R8A7795_CLK_SD2H, CLK_SDSRC, 0x268),
DEF_GEN3_SDH("sd3h", R8A7795_CLK_SD3H, CLK_SDSRC, 0x26c),
DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, R8A7795_CLK_SD0H, 0x074),
DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, R8A7795_CLK_SD1H, 0x078),
DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268),
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c),
DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7795_CLK_RPC),
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A7795_CLK_CPEX, CLK_EXTAL, 2, 1),
DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8),
DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("3dge", 112, R8A7795_CLK_ZG),
DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A7795_CLK_S3D2),
DEF_MOD("tmu2", 123, R8A7795_CLK_S3D2),
DEF_MOD("tmu1", 124, R8A7795_CLK_S3D2),
DEF_MOD("tmu0", 125, R8A7795_CLK_CP),
DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
DEF_MOD("cmt3", 300, R8A7795_CLK_R),
DEF_MOD("cmt2", 301, R8A7795_CLK_R),
DEF_MOD("cmt1", 302, R8A7795_CLK_R),
DEF_MOD("cmt0", 303, R8A7795_CLK_R),
DEF_MOD("tpu0", 304, R8A7795_CLK_S3D4),
DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
DEF_MOD("sdif1", 313, R8A7795_CLK_SD1),
DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
DEF_MOD("rwdt", 402, R8A7795_CLK_R),
DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2),
DEF_MOD("drif31", 508, R8A7795_CLK_S3D2),
DEF_MOD("drif30", 509, R8A7795_CLK_S3D2),
DEF_MOD("drif21", 510, R8A7795_CLK_S3D2),
DEF_MOD("drif20", 511, R8A7795_CLK_S3D2),
DEF_MOD("drif11", 512, R8A7795_CLK_S3D2),
DEF_MOD("drif10", 513, R8A7795_CLK_S3D2),
DEF_MOD("drif01", 514, R8A7795_CLK_S3D2),
DEF_MOD("drif00", 515, R8A7795_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
DEF_MOD("thermal", 522, R8A7795_CLK_CP),
DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2),
DEF_MOD("ehci2", 701, R8A7795_CLK_S3D2),
DEF_MOD("ehci1", 702, R8A7795_CLK_S3D2),
DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2),
DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2),
DEF_MOD("cmm3", 708, R8A7795_CLK_S2D1),
DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1),
DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1),
DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1),
DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
DEF_MOD("mlp", 802, R8A7795_CLK_S2D1),
DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),
DEF_MOD("vin4", 807, R8A7795_CLK_S0D2),
DEF_MOD("vin3", 808, R8A7795_CLK_S0D2),
DEF_MOD("vin2", 809, R8A7795_CLK_S0D2),
DEF_MOD("vin1", 810, R8A7795_CLK_S0D2),
DEF_MOD("vin0", 811, R8A7795_CLK_S0D2),
DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6),
DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
DEF_MOD("imr3", 820, R8A7795_CLK_S0D2),
DEF_MOD("imr2", 821, R8A7795_CLK_S0D2),
DEF_MOD("imr1", 822, R8A7795_CLK_S0D2),
DEF_MOD("imr0", 823, R8A7795_CLK_S0D2),
DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4),
DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4),
DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4),
DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4),
DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4),
DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4),
DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4),
DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4),
DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
DEF_MOD("rpc-if", 917, R8A7795_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
DEF_MOD("adg", 922, R8A7795_CLK_S0D4),
DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
MOD_CLK_ID(402), /* RWDT */
MOD_CLK_ID(408), /* INTC-AP (GIC) */
};
/*
* CPG Clock Data
*/
/*
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
* 14 13 19 17 (MHz)
*-------------------------------------------------------------------------
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
* 0 0 1 0 Prohibited setting
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
* 0 1 1 0 Prohibited setting
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
* 1 0 1 0 Prohibited setting
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
* 1 1 1 0 Prohibited setting
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
(((md) & BIT(13)) >> 11) | \
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, 16, },
{ 0, /* Prohibited setting */ },
{ 1, 192, 1, 192, 1, 16, },
{ 1, 160, 1, 160, 1, 19, },
{ 1, 160, 1, 106, 1, 19, },
{ 0, /* Prohibited setting */ },
{ 1, 160, 1, 160, 1, 19, },
{ 1, 128, 1, 128, 1, 24, },
{ 1, 128, 1, 84, 1, 24, },
{ 0, /* Prohibited setting */ },
{ 1, 128, 1, 128, 1, 24, },
{ 2, 192, 1, 192, 1, 32, },
{ 2, 192, 1, 128, 1, 32, },
{ 0, /* Prohibited setting */ },
{ 2, 192, 1, 192, 1, 32, },
};
static const struct soc_device_attribute r8a7795_denylist[] __initconst = {
{ .soc_id = "r8a7795", .revision = "ES1.*" },
{ /* sentinel */ }
};
static int __init r8a7795_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
u32 cpg_mode;
int error;
/*
* We panic here to ensure removed SoCs and clk updates are always in
* sync to avoid overclocking damages. The panic can only be seen with
* commandline args 'earlycon keep_bootcon'. But these SoCs were for
* developers only anyhow.
*/
if (soc_device_match(r8a7795_denylist))
panic("SoC not supported anymore!\n");
error = rcar_rst_read_mode_pins(&cpg_mode);
if (error)
return error;
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
if (!cpg_pll_config->extal_div) {
dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
return -EINVAL;
}
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
}
const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a7795_core_clks,
.num_core_clks = ARRAY_SIZE(r8a7795_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r8a7795_mod_clks,
.num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks),
.num_hw_mod_clks = 12 * 32,
/* Critical Module Clocks */
.crit_mod_clks = r8a7795_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks),
/* Callbacks */
.init = r8a7795_cpg_mssr_init,
.cpg_clk_register = rcar_gen3_cpg_clk_register,
};
| linux-master | drivers/clk/renesas/r8a7795-cpg-mssr.c |
// SPDX-License-Identifier: GPL-2.0
/*
* R9A06G032 clock driver
*
* Copyright (C) 2018 Renesas Electronics Europe Limited
*
* Michel Pollet <[email protected]>, <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/math64.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
#include <linux/slab.h>
#include <linux/soc/renesas/r9a06g032-sysctrl.h>
#include <linux/spinlock.h>
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
#define R9A06G032_SYSCTRL_USB 0x00
#define R9A06G032_SYSCTRL_USB_H2MODE (1<<1)
#define R9A06G032_SYSCTRL_DMAMUX 0xA0
/**
* struct regbit - describe one bit in a register
* @reg: offset of register relative to base address,
* expressed in units of 32-bit words (not bytes),
* @bit: which bit (0 to 31) in the register
*
* This structure is used to compactly encode the location
* of a single bit in a register. Five bits are needed to
* encode the bit number. With uint16_t data type, this
* leaves 11 bits to encode a register offset up to 2047.
*
* Since registers are aligned on 32-bit boundaries, the
* offset will be specified in 32-bit words rather than bytes.
* This allows encoding an offset up to 0x1FFC (8188) bytes.
*
* Helper macro RB() takes care of converting the register
* offset from bytes to 32-bit words.
*/
struct regbit {
u16 bit:5;
u16 reg:11;
};
#define RB(_reg, _bit) ((struct regbit) { \
.reg = (_reg) / 4, \
.bit = (_bit) \
})
/**
* struct r9a06g032_gate - clock-related control bits
* @gate: clock enable/disable
* @reset: clock module reset (active low)
* @ready: enables NoC forwarding of read/write requests to device,
* (eg. device is ready to handle read/write requests)
* @midle: request to idle the NoC interconnect
*
* Each of these fields describes a single bit in a register,
* which controls some aspect of clock gating. The @gate field
* is mandatory, this one enables/disables the clock. The
* other fields are optional, with zero indicating "not used".
*
* In most cases there is a @reset bit which needs to be
* de-asserted to bring the module out of reset.
*
* Modules may also need to signal when they are @ready to
* handle requests (read/writes) from the NoC interconnect.
*
* Similarly, the @midle bit is used to idle the master.
*/
struct r9a06g032_gate {
struct regbit gate, reset, ready, midle;
/* Unused fields omitted to save space */
/* struct regbit scon, mirack, mistat */;
};
enum gate_type {
K_GATE = 0, /* gate which enable/disable */
K_FFC, /* fixed factor clock */
K_DIV, /* divisor */
K_BITSEL, /* special for UARTs */
K_DUALGATE /* special for UARTs */
};
/**
* struct r9a06g032_clkdesc - describe a single clock
* @name: string describing this clock
* @managed: boolean indicating if this clock should be
* started/stopped as part of power management
* @type: see enum @gate_type
* @index: the ID of this clock element
* @source: the ID+1 of the parent clock element.
* Root clock uses ID of ~0 (PARENT_ID);
* @gate: clock enable/disable
* @div_min: smallest permitted clock divider
* @div_max: largest permitted clock divider
* @reg: clock divider register offset, in 32-bit words
* @div_table: optional list of fixed clock divider values;
* must be in ascending order, zero for unused
* @div: divisor for fixed-factor clock
* @mul: multiplier for fixed-factor clock
* @group: UART group, 0=UART0/1/2, 1=UART3/4/5/6/7
* @sel: select either g1/r1 or g2/r2 as clock source
* @g1: 1st source gate (clock enable/disable)
* @r1: 1st source reset (module reset)
* @g2: 2nd source gate (clock enable/disable)
* @r2: 2nd source reset (module reset)
*
* Describes a single element in the clock tree hierarchy.
* As there are quite a large number of clock elements, this
* structure is packed tightly to conserve space.
*/
struct r9a06g032_clkdesc {
const char *name;
uint32_t managed:1;
enum gate_type type:3;
uint32_t index:8;
uint32_t source:8; /* source index + 1 (0 == none) */
union {
/* type = K_GATE */
struct r9a06g032_gate gate;
/* type = K_DIV */
struct {
unsigned int div_min:10, div_max:10, reg:10;
u16 div_table[4];
};
/* type = K_FFC */
struct {
u16 div, mul;
};
/* type = K_DUALGATE */
struct {
uint16_t group:1;
struct regbit sel, g1, r1, g2, r2;
} dual;
};
};
/*
* The last three arguments are not currently used,
* but are kept in the r9a06g032_clocks table below.
*/
#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) { \
.gate = _clk, \
.reset = _rst, \
.ready = _rdy, \
.midle = _midle, \
/* .scon = _scon, */ \
/* .mirack = _mirack, */ \
/* .mistat = _mistat */ \
}
#define D_GATE(_idx, _n, _src, ...) { \
.type = K_GATE, \
.index = R9A06G032_##_idx, \
.source = 1 + R9A06G032_##_src, \
.name = _n, \
.gate = I_GATE(__VA_ARGS__) \
}
#define D_MODULE(_idx, _n, _src, ...) { \
.type = K_GATE, \
.index = R9A06G032_##_idx, \
.source = 1 + R9A06G032_##_src, \
.name = _n, \
.managed = 1, \
.gate = I_GATE(__VA_ARGS__) \
}
#define D_ROOT(_idx, _n, _mul, _div) { \
.type = K_FFC, \
.index = R9A06G032_##_idx, \
.name = _n, \
.div = _div, \
.mul = _mul \
}
#define D_FFC(_idx, _n, _src, _div) { \
.type = K_FFC, \
.index = R9A06G032_##_idx, \
.source = 1 + R9A06G032_##_src, \
.name = _n, \
.div = _div, \
.mul = 1 \
}
#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \
.type = K_DIV, \
.index = R9A06G032_##_idx, \
.source = 1 + R9A06G032_##_src, \
.name = _n, \
.reg = _reg, \
.div_min = _min, \
.div_max = _max, \
.div_table = { __VA_ARGS__ } \
}
#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) { \
.type = K_DUALGATE, \
.index = R9A06G032_##_idx, \
.source = 1 + R9A06G032_##_src, \
.name = _n, \
.dual = { \
.group = _g, \
.g1 = _g1, \
.r1 = _r1, \
.g2 = _g2, \
.r2 = _r2 \
}, \
}
/* Internal clock IDs */
#define R9A06G032_CLKOUT 0
#define R9A06G032_CLKOUT_D10 2
#define R9A06G032_CLKOUT_D16 3
#define R9A06G032_CLKOUT_D160 4
#define R9A06G032_CLKOUT_D1OR2 5
#define R9A06G032_CLKOUT_D20 6
#define R9A06G032_CLKOUT_D40 7
#define R9A06G032_CLKOUT_D5 8
#define R9A06G032_CLKOUT_D8 9
#define R9A06G032_DIV_ADC 10
#define R9A06G032_DIV_I2C 11
#define R9A06G032_DIV_NAND 12
#define R9A06G032_DIV_P1_PG 13
#define R9A06G032_DIV_P2_PG 14
#define R9A06G032_DIV_P3_PG 15
#define R9A06G032_DIV_P4_PG 16
#define R9A06G032_DIV_P5_PG 17
#define R9A06G032_DIV_P6_PG 18
#define R9A06G032_DIV_QSPI0 19
#define R9A06G032_DIV_QSPI1 20
#define R9A06G032_DIV_REF_SYNC 21
#define R9A06G032_DIV_SDIO0 22
#define R9A06G032_DIV_SDIO1 23
#define R9A06G032_DIV_SWITCH 24
#define R9A06G032_DIV_UART 25
#define R9A06G032_DIV_MOTOR 64
#define R9A06G032_CLK_DDRPHY_PLLCLK_D4 78
#define R9A06G032_CLK_ECAT100_D4 79
#define R9A06G032_CLK_HSR100_D2 80
#define R9A06G032_CLK_REF_SYNC_D4 81
#define R9A06G032_CLK_REF_SYNC_D8 82
#define R9A06G032_CLK_SERCOS100_D2 83
#define R9A06G032_DIV_CA7 84
#define R9A06G032_UART_GROUP_012 154
#define R9A06G032_UART_GROUP_34567 155
#define R9A06G032_CLOCK_COUNT (R9A06G032_UART_GROUP_34567 + 1)
static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
D_ROOT(CLKOUT, "clkout", 25, 1),
D_ROOT(CLK_PLL_USB, "clk_pll_usb", 12, 10),
D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10),
D_FFC(CLKOUT_D16, "clkout_d16", CLKOUT, 16),
D_FFC(CLKOUT_D160, "clkout_d160", CLKOUT, 160),
D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
D_FFC(CLKOUT_D20, "clkout_d20", CLKOUT, 20),
D_FFC(CLKOUT_D40, "clkout_d40", CLKOUT, 40),
D_FFC(CLKOUT_D5, "clkout_d5", CLKOUT, 5),
D_FFC(CLKOUT_D8, "clkout_d8", CLKOUT, 8),
D_DIV(DIV_ADC, "div_adc", CLKOUT, 77, 50, 250),
D_DIV(DIV_I2C, "div_i2c", CLKOUT, 78, 12, 16),
D_DIV(DIV_NAND, "div_nand", CLKOUT, 82, 12, 32),
D_DIV(DIV_P1_PG, "div_p1_pg", CLKOUT, 68, 12, 200),
D_DIV(DIV_P2_PG, "div_p2_pg", CLKOUT, 62, 12, 128),
D_DIV(DIV_P3_PG, "div_p3_pg", CLKOUT, 64, 8, 128),
D_DIV(DIV_P4_PG, "div_p4_pg", CLKOUT, 66, 8, 128),
D_DIV(DIV_P5_PG, "div_p5_pg", CLKOUT, 71, 10, 40),
D_DIV(DIV_P6_PG, "div_p6_pg", CLKOUT, 18, 12, 64),
D_DIV(DIV_QSPI0, "div_qspi0", CLKOUT, 73, 3, 7),
D_DIV(DIV_QSPI1, "div_qspi1", CLKOUT, 25, 3, 7),
D_DIV(DIV_REF_SYNC, "div_ref_sync", CLKOUT, 56, 2, 16, 2, 4, 8, 16),
D_DIV(DIV_SDIO0, "div_sdio0", CLKOUT, 74, 20, 128),
D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128),
D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40),
D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128),
D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, RB(0xe8, 9),
RB(0xe8, 10), RB(0xe8, 11), RB(0x00, 0),
RB(0x15c, 3), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, RB(0xe8, 12),
RB(0xe8, 13), RB(0xe8, 14), RB(0x00, 0),
RB(0x15c, 4), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, RB(0xe8, 15),
RB(0xe8, 16), RB(0xe8, 17), RB(0x00, 0),
RB(0x15c, 5), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, RB(0xe8, 18),
RB(0xe8, 19), RB(0xe8, 20), RB(0x00, 0),
RB(0x15c, 6), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, RB(0xe8, 21),
RB(0xe8, 22), RB(0xe8, 23), RB(0x00, 0),
RB(0x15c, 7), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_ADC, "clk_adc", DIV_ADC, RB(0x3c, 10),
RB(0x3c, 11), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, RB(0x80, 5),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, RB(0x90, 3),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, RB(0x3c, 6),
RB(0x3c, 7), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, RB(0x3c, 8),
RB(0x3c, 9), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, RB(0x68, 2),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_NAND, "clk_nand", DIV_NAND, RB(0x50, 4),
RB(0x50, 5), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, RB(0xec, 20),
RB(0xec, 21), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, RB(0x10c, 2),
RB(0x10c, 3), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, RB(0x10c, 4),
RB(0x10c, 5), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, RB(0x10c, 6),
RB(0x10c, 7), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, RB(0x104, 4),
RB(0x104, 5), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, RB(0x104, 6),
RB(0x104, 7), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, RB(0x114, 0),
RB(0x114, 1), RB(0x114, 2), RB(0x00, 0),
RB(0x16c, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, RB(0x114, 3),
RB(0x114, 4), RB(0x114, 5), RB(0x00, 0),
RB(0x16c, 1), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, RB(0x114, 6),
RB(0x114, 7), RB(0x114, 8), RB(0x00, 0),
RB(0x16c, 2), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, RB(0x114, 9),
RB(0x114, 10), RB(0x114, 11), RB(0x00, 0),
RB(0x16c, 3), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, RB(0x1c, 6),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, RB(0x54, 4),
RB(0x54, 5), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, RB(0x90, 4),
RB(0x90, 5), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, RB(0x68, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, RB(0x68, 1),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, RB(0x0c, 4),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, RB(0xc8, 4),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, RB(0x84, 5),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, RB(0x10c, 0),
RB(0x10c, 1), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, RB(0xfc, 0),
RB(0xfc, 1), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, RB(0xfc, 2),
RB(0xfc, 3), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, RB(0xfc, 4),
RB(0xfc, 5), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, RB(0xfc, 6),
RB(0xfc, 7), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, RB(0x104, 0),
RB(0x104, 1), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, RB(0x104, 2),
RB(0x104, 3), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, RB(0x130, 2),
RB(0x130, 3), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8),
D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, RB(0x80, 0),
RB(0x80, 1), RB(0x00, 0), RB(0x80, 2),
RB(0x00, 0), RB(0x88, 0), RB(0x88, 1)),
D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, RB(0xe8, 0),
RB(0xe8, 1), RB(0xe8, 2), RB(0x00, 0),
RB(0x15c, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, RB(0x84, 0),
RB(0x84, 2), RB(0x00, 0), RB(0x84, 1),
RB(0x00, 0), RB(0x8c, 0), RB(0x8c, 1)),
D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, RB(0x118, 3),
RB(0x118, 4), RB(0x118, 5), RB(0x00, 0),
RB(0x168, 1), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, RB(0x118, 6),
RB(0x118, 7), RB(0x118, 8), RB(0x00, 0),
RB(0x168, 2), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, RB(0x118, 9),
RB(0x118, 10), RB(0x118, 11), RB(0x00, 0),
RB(0x168, 3), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, RB(0xe8, 3),
RB(0xe8, 4), RB(0xe8, 5), RB(0x00, 0),
RB(0x15c, 1), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, RB(0xe8, 6),
RB(0xe8, 7), RB(0xe8, 8), RB(0x00, 0),
RB(0x15c, 2), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, RB(0x1c, 3),
RB(0x00, 0), RB(0x00, 0), RB(0x1c, 4),
RB(0x00, 0), RB(0x20, 2), RB(0x20, 3)),
D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, RB(0x1c, 0),
RB(0x1c, 1), RB(0x00, 0), RB(0x1c, 2),
RB(0x00, 0), RB(0x20, 0), RB(0x20, 1)),
D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, RB(0x1c, 5),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, RB(0xf0, 12),
RB(0xf0, 13), RB(0x00, 0), RB(0xf0, 14),
RB(0x00, 0), RB(0x160, 4), RB(0x160, 5)),
D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, RB(0xf0, 9),
RB(0xf0, 10), RB(0xf0, 11), RB(0x00, 0),
RB(0x160, 3), RB(0x00, 0), RB(0x00, 0)),
D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4),
D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4),
D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2),
D_FFC(CLK_REF_SYNC_D4, "clk_ref_sync_d4", CLK_REF_SYNC, 4),
D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8),
D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2),
D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4),
D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, RB(0xf0, 3),
RB(0xf0, 4), RB(0xf0, 5), RB(0x00, 0),
RB(0x160, 1), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, RB(0xf0, 6),
RB(0xf0, 7), RB(0xf0, 8), RB(0x00, 0),
RB(0x160, 2), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, RB(0x3c, 15),
RB(0x3c, 16), RB(0x3c, 17), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, RB(0x3c, 12),
RB(0x3c, 13), RB(0x3c, 14), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, RB(0xf0, 0),
RB(0xf0, 1), RB(0xf0, 2), RB(0x00, 0),
RB(0x160, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, RB(0x3c, 0),
RB(0x3c, 1), RB(0x3c, 2), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, RB(0x3c, 3),
RB(0x3c, 4), RB(0x3c, 5), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640),
D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, RB(0x174, 0),
RB(0x174, 1), RB(0x00, 0), RB(0x174, 2),
RB(0x00, 0), RB(0x178, 0), RB(0x178, 1)),
D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, RB(0x64, 3),
RB(0x64, 4), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, RB(0x80, 3),
RB(0x80, 4), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, RB(0x90, 4),
RB(0x90, 5), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, RB(0x18c, 0),
RB(0x18c, 1), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, RB(0x84, 4),
RB(0x84, 3), RB(0x00, 0), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, RB(0x34, 15),
RB(0x34, 16), RB(0x34, 17), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, RB(0x184, 0),
RB(0x184, 1), RB(0x184, 2), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, RB(0x24, 3),
RB(0x24, 4), RB(0x24, 5), RB(0x00, 0),
RB(0x28, 2), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, RB(0x24, 0),
RB(0x24, 1), RB(0x00, 0), RB(0x24, 2),
RB(0x00, 0), RB(0x28, 0), RB(0x28, 1)),
D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, RB(0x64, 0),
RB(0x64, 2), RB(0x00, 0), RB(0x64, 1),
RB(0x00, 0), RB(0x74, 0), RB(0x74, 1)),
D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, RB(0x4c, 0),
RB(0x4c, 1), RB(0x4c, 2), RB(0x4c, 3),
RB(0x58, 0), RB(0x58, 1), RB(0x58, 2)),
D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, RB(0x4c, 4),
RB(0x4c, 5), RB(0x4c, 6), RB(0x4c, 7),
RB(0x58, 3), RB(0x58, 4), RB(0x58, 5)),
D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, RB(0x6c, 0),
RB(0x6c, 1), RB(0x6c, 2), RB(0x6c, 3),
RB(0x78, 0), RB(0x78, 1), RB(0x78, 2)),
D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, RB(0x70, 0),
RB(0x70, 1), RB(0x70, 2), RB(0x70, 3),
RB(0x7c, 0), RB(0x7c, 1), RB(0x7c, 2)),
D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, RB(0x40, 18),
RB(0x40, 19), RB(0x40, 20), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, RB(0x40, 21),
RB(0x40, 22), RB(0x40, 23), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, RB(0x44, 9),
RB(0x44, 10), RB(0x44, 11), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, RB(0x90, 0),
RB(0x90, 2), RB(0x00, 0), RB(0x90, 1),
RB(0x00, 0), RB(0x98, 0), RB(0x98, 1)),
D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, RB(0x34, 9),
RB(0x34, 10), RB(0x34, 11), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, RB(0x34, 12),
RB(0x34, 13), RB(0x34, 14), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, RB(0xf4, 0),
RB(0xf4, 1), RB(0xf4, 2), RB(0x00, 0),
RB(0x164, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, RB(0x2c, 4),
RB(0x2c, 5), RB(0x2c, 6), RB(0x00, 0),
RB(0x30, 3), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, RB(0x2c, 0),
RB(0x2c, 1), RB(0x2c, 2), RB(0x2c, 3),
RB(0x30, 0), RB(0x30, 1), RB(0x30, 2)),
D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, RB(0x50, 0),
RB(0x50, 1), RB(0x50, 2), RB(0x50, 3),
RB(0x5c, 0), RB(0x5c, 1), RB(0x5c, 2)),
D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, RB(0xf4, 12),
RB(0xf4, 13), RB(0x00, 0), RB(0xf4, 14),
RB(0x00, 0), RB(0x164, 4), RB(0x164, 5)),
D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, RB(0x44, 12),
RB(0x44, 13), RB(0x44, 14), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, RB(0x44, 15),
RB(0x44, 16), RB(0x44, 17), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, RB(0xf4, 6),
RB(0xf4, 7), RB(0xf4, 8), RB(0x00, 0),
RB(0x164, 2), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, RB(0xf4, 9),
RB(0xf4, 10), RB(0xf4, 11), RB(0x00, 0),
RB(0x164, 3), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, RB(0x54, 0),
RB(0x54, 1), RB(0x54, 2), RB(0x54, 3),
RB(0x60, 0), RB(0x60, 1), RB(0x60, 2)),
D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, RB(0x90, 0),
RB(0x90, 1), RB(0x90, 2), RB(0x90, 3),
RB(0x98, 0), RB(0x98, 1), RB(0x98, 2)),
D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, RB(0x154, 0),
RB(0x154, 1), RB(0x154, 2), RB(0x00, 0),
RB(0x170, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, RB(0x140, 0),
RB(0x140, 3), RB(0x00, 0), RB(0x140, 2),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, RB(0x0c, 0),
RB(0x0c, 1), RB(0x0c, 2), RB(0x0c, 3),
RB(0x10, 0), RB(0x10, 1), RB(0x10, 2)),
D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, RB(0xc8, 0),
RB(0xc8, 1), RB(0xc8, 2), RB(0xc8, 3),
RB(0xcc, 0), RB(0xcc, 1), RB(0xcc, 2)),
D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, RB(0xf4, 3),
RB(0xf4, 4), RB(0xf4, 5), RB(0x00, 0),
RB(0x164, 1), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, RB(0x40, 0),
RB(0x40, 1), RB(0x40, 2), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, RB(0x40, 3),
RB(0x40, 4), RB(0x40, 5), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, RB(0x40, 6),
RB(0x40, 7), RB(0x40, 8), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, RB(0x40, 9),
RB(0x40, 10), RB(0x40, 11), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, RB(0x40, 12),
RB(0x40, 13), RB(0x40, 14), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, RB(0x40, 15),
RB(0x40, 16), RB(0x40, 17), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, RB(0x130, 0),
RB(0x00, 0), RB(0x130, 1), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, RB(0x188, 0),
RB(0x188, 1), RB(0x188, 2), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, RB(0x34, 0),
RB(0x34, 1), RB(0x34, 2), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, RB(0x34, 3),
RB(0x34, 4), RB(0x34, 5), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, RB(0x34, 6),
RB(0x34, 7), RB(0x34, 8), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, RB(0x40, 24),
RB(0x40, 25), RB(0x40, 26), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, RB(0x40, 27),
RB(0x40, 28), RB(0x40, 29), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, RB(0x44, 0),
RB(0x44, 1), RB(0x44, 2), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, RB(0x44, 3),
RB(0x44, 4), RB(0x44, 5), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, RB(0x44, 6),
RB(0x44, 7), RB(0x44, 8), RB(0x00, 0),
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
/*
* These are not hardware clocks, but are needed to handle the special
* case where we have a 'selector bit' that doesn't just change the
* parent for a clock, but also the gate it's supposed to use.
*/
{
.index = R9A06G032_UART_GROUP_012,
.name = "uart_group_012",
.type = K_BITSEL,
.source = 1 + R9A06G032_DIV_UART,
/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
.dual.sel = RB(0x34, 30),
.dual.group = 0,
},
{
.index = R9A06G032_UART_GROUP_34567,
.name = "uart_group_34567",
.type = K_BITSEL,
.source = 1 + R9A06G032_DIV_P2_PG,
/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
.dual.sel = RB(0xec, 24),
.dual.group = 1,
},
D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0,
RB(0x34, 18), RB(0x34, 19), RB(0x34, 20), RB(0x34, 21)),
D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0,
RB(0x34, 22), RB(0x34, 23), RB(0x34, 24), RB(0x34, 25)),
D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0,
RB(0x34, 26), RB(0x34, 27), RB(0x34, 28), RB(0x34, 29)),
D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1,
RB(0xec, 0), RB(0xec, 1), RB(0xec, 2), RB(0xec, 3)),
D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1,
RB(0xec, 4), RB(0xec, 5), RB(0xec, 6), RB(0xec, 7)),
D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1,
RB(0xec, 8), RB(0xec, 9), RB(0xec, 10), RB(0xec, 11)),
D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1,
RB(0xec, 12), RB(0xec, 13), RB(0xec, 14), RB(0xec, 15)),
D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1,
RB(0xec, 16), RB(0xec, 17), RB(0xec, 18), RB(0xec, 19)),
};
struct r9a06g032_priv {
struct clk_onecell_data data;
spinlock_t lock; /* protects concurrent access to gates */
void __iomem *reg;
};
static struct r9a06g032_priv *sysctrl_priv;
/* Exported helper to access the DMAMUX register */
int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val)
{
unsigned long flags;
u32 dmamux;
if (!sysctrl_priv)
return -EPROBE_DEFER;
spin_lock_irqsave(&sysctrl_priv->lock, flags);
dmamux = readl(sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX);
dmamux &= ~mask;
dmamux |= val & mask;
writel(dmamux, sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX);
spin_unlock_irqrestore(&sysctrl_priv->lock, flags);
return 0;
}
EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_set_dmamux);
static void clk_rdesc_set(struct r9a06g032_priv *clocks,
struct regbit rb, unsigned int on)
{
u32 __iomem *reg = clocks->reg + (rb.reg * 4);
u32 val;
if (!rb.reg && !rb.bit)
return;
val = readl(reg);
val = (val & ~BIT(rb.bit)) | ((!!on) << rb.bit);
writel(val, reg);
}
static int clk_rdesc_get(struct r9a06g032_priv *clocks, struct regbit rb)
{
u32 __iomem *reg = clocks->reg + (rb.reg * 4);
u32 val = readl(reg);
return !!(val & BIT(rb.bit));
}
/*
* This implements the R9A06G032 clock gate 'driver'. We cannot use the system's
* clock gate framework as the gates on the R9A06G032 have a special enabling
* sequence, therefore we use this little proxy.
*/
struct r9a06g032_clk_gate {
struct clk_hw hw;
struct r9a06g032_priv *clocks;
u16 index;
struct r9a06g032_gate gate;
};
#define to_r9a06g032_gate(_hw) container_of(_hw, struct r9a06g032_clk_gate, hw)
static int create_add_module_clock(struct of_phandle_args *clkspec,
struct device *dev)
{
struct clk *clk;
int error;
clk = of_clk_get_from_provider(clkspec);
if (IS_ERR(clk))
return PTR_ERR(clk);
error = pm_clk_create(dev);
if (error) {
clk_put(clk);
return error;
}
error = pm_clk_add_clk(dev, clk);
if (error) {
pm_clk_destroy(dev);
clk_put(clk);
}
return error;
}
static int r9a06g032_attach_dev(struct generic_pm_domain *pd,
struct device *dev)
{
struct device_node *np = dev->of_node;
struct of_phandle_args clkspec;
int i = 0;
int error;
int index;
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i++,
&clkspec)) {
if (clkspec.np != pd->dev.of_node)
continue;
index = clkspec.args[0];
if (index < R9A06G032_CLOCK_COUNT &&
r9a06g032_clocks[index].managed) {
error = create_add_module_clock(&clkspec, dev);
of_node_put(clkspec.np);
if (error)
return error;
}
}
return 0;
}
static void r9a06g032_detach_dev(struct generic_pm_domain *unused, struct device *dev)
{
if (!pm_clk_no_clocks(dev))
pm_clk_destroy(dev);
}
static int r9a06g032_add_clk_domain(struct device *dev)
{
struct device_node *np = dev->of_node;
struct generic_pm_domain *pd;
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
if (!pd)
return -ENOMEM;
pd->name = np->name;
pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
GENPD_FLAG_ACTIVE_WAKEUP;
pd->attach_dev = r9a06g032_attach_dev;
pd->detach_dev = r9a06g032_detach_dev;
pm_genpd_init(pd, &pm_domain_always_on_gov, false);
of_genpd_add_provider_simple(np, pd);
return 0;
}
static void
r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks,
struct r9a06g032_gate *g, int on)
{
unsigned long flags;
WARN_ON(!g->gate.reg && !g->gate.bit);
spin_lock_irqsave(&clocks->lock, flags);
clk_rdesc_set(clocks, g->gate, on);
/* De-assert reset */
clk_rdesc_set(clocks, g->reset, 1);
spin_unlock_irqrestore(&clocks->lock, flags);
/* Hardware manual recommends 5us delay after enabling clock & reset */
udelay(5);
/* If the peripheral is memory mapped (i.e. an AXI slave), there is an
* associated SLVRDY bit in the System Controller that needs to be set
* so that the FlexWAY bus fabric passes on the read/write requests.
*/
spin_lock_irqsave(&clocks->lock, flags);
clk_rdesc_set(clocks, g->ready, on);
/* Clear 'Master Idle Request' bit */
clk_rdesc_set(clocks, g->midle, !on);
spin_unlock_irqrestore(&clocks->lock, flags);
/* Note: We don't wait for FlexWAY Socket Connection signal */
}
static int r9a06g032_clk_gate_enable(struct clk_hw *hw)
{
struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
r9a06g032_clk_gate_set(g->clocks, &g->gate, 1);
return 0;
}
static void r9a06g032_clk_gate_disable(struct clk_hw *hw)
{
struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
r9a06g032_clk_gate_set(g->clocks, &g->gate, 0);
}
static int r9a06g032_clk_gate_is_enabled(struct clk_hw *hw)
{
struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
/* if clock is in reset, the gate might be on, and still not 'be' on */
if (g->gate.reset.reg && !clk_rdesc_get(g->clocks, g->gate.reset))
return 0;
return clk_rdesc_get(g->clocks, g->gate.gate);
}
static const struct clk_ops r9a06g032_clk_gate_ops = {
.enable = r9a06g032_clk_gate_enable,
.disable = r9a06g032_clk_gate_disable,
.is_enabled = r9a06g032_clk_gate_is_enabled,
};
static struct clk *
r9a06g032_register_gate(struct r9a06g032_priv *clocks,
const char *parent_name,
const struct r9a06g032_clkdesc *desc)
{
struct clk *clk;
struct r9a06g032_clk_gate *g;
struct clk_init_data init = {};
g = kzalloc(sizeof(*g), GFP_KERNEL);
if (!g)
return NULL;
init.name = desc->name;
init.ops = &r9a06g032_clk_gate_ops;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = parent_name ? &parent_name : NULL;
init.num_parents = parent_name ? 1 : 0;
g->clocks = clocks;
g->index = desc->index;
g->gate = desc->gate;
g->hw.init = &init;
/*
* important here, some clocks are already in use by the CM3, we
* have to assume they are not Linux's to play with and try to disable
* at the end of the boot!
*/
if (r9a06g032_clk_gate_is_enabled(&g->hw)) {
init.flags |= CLK_IS_CRITICAL;
pr_debug("%s was enabled, making read-only\n", desc->name);
}
clk = clk_register(NULL, &g->hw);
if (IS_ERR(clk)) {
kfree(g);
return NULL;
}
return clk;
}
struct r9a06g032_clk_div {
struct clk_hw hw;
struct r9a06g032_priv *clocks;
u16 index;
u16 reg;
u16 min, max;
u8 table_size;
u16 table[8]; /* we know there are no more than 8 */
};
#define to_r9a06g032_div(_hw) \
container_of(_hw, struct r9a06g032_clk_div, hw)
static unsigned long
r9a06g032_div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
u32 div = readl(reg);
if (div < clk->min)
div = clk->min;
else if (div > clk->max)
div = clk->max;
return DIV_ROUND_UP(parent_rate, div);
}
/*
* Attempts to find a value that is in range of min,max,
* and if a table of set dividers was specified for this
* register, try to find the fixed divider that is the closest
* to the target frequency
*/
static long
r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk,
unsigned long rate, unsigned long prate)
{
/* + 1 to cope with rates that have the remainder dropped */
u32 div = DIV_ROUND_UP(prate, rate + 1);
int i;
if (div <= clk->min)
return clk->min;
if (div >= clk->max)
return clk->max;
for (i = 0; clk->table_size && i < clk->table_size - 1; i++) {
if (div >= clk->table[i] && div <= clk->table[i + 1]) {
unsigned long m = rate -
DIV_ROUND_UP(prate, clk->table[i]);
unsigned long p =
DIV_ROUND_UP(prate, clk->table[i + 1]) -
rate;
/*
* select the divider that generates
* the value closest to the ideal frequency
*/
div = p >= m ? clk->table[i] : clk->table[i + 1];
return div;
}
}
return div;
}
static int
r9a06g032_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
u32 div = DIV_ROUND_UP(req->best_parent_rate, req->rate);
pr_devel("%s %pC %ld (prate %ld) (wanted div %u)\n", __func__,
hw->clk, req->rate, req->best_parent_rate, div);
pr_devel(" min %d (%ld) max %d (%ld)\n",
clk->min, DIV_ROUND_UP(req->best_parent_rate, clk->min),
clk->max, DIV_ROUND_UP(req->best_parent_rate, clk->max));
div = r9a06g032_div_clamp_div(clk, req->rate, req->best_parent_rate);
/*
* this is a hack. Currently the serial driver asks for a clock rate
* that is 16 times the baud rate -- and that is wildly outside the
* range of the UART divider, somehow there is no provision for that
* case of 'let the divider as is if outside range'.
* The serial driver *shouldn't* play with these clocks anyway, there's
* several uarts attached to this divider, and changing this impacts
* everyone.
*/
if (clk->index == R9A06G032_DIV_UART ||
clk->index == R9A06G032_DIV_P2_PG) {
pr_devel("%s div uart hack!\n", __func__);
req->rate = clk_get_rate(hw->clk);
return 0;
}
req->rate = DIV_ROUND_UP(req->best_parent_rate, div);
pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk,
req->best_parent_rate, div, req->rate);
return 0;
}
static int
r9a06g032_div_set_rate(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate)
{
struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
/* + 1 to cope with rates that have the remainder dropped */
u32 div = DIV_ROUND_UP(parent_rate, rate + 1);
u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
pr_devel("%s %pC rate %ld parent %ld div %d\n", __func__, hw->clk,
rate, parent_rate, div);
/*
* Need to write the bit 31 with the divider value to
* latch it. Technically we should wait until it has been
* cleared too.
* TODO: Find whether this callback is sleepable, in case
* the hardware /does/ require some sort of spinloop here.
*/
writel(div | BIT(31), reg);
return 0;
}
static const struct clk_ops r9a06g032_clk_div_ops = {
.recalc_rate = r9a06g032_div_recalc_rate,
.determine_rate = r9a06g032_div_determine_rate,
.set_rate = r9a06g032_div_set_rate,
};
static struct clk *
r9a06g032_register_div(struct r9a06g032_priv *clocks,
const char *parent_name,
const struct r9a06g032_clkdesc *desc)
{
struct r9a06g032_clk_div *div;
struct clk *clk;
struct clk_init_data init = {};
unsigned int i;
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
return NULL;
init.name = desc->name;
init.ops = &r9a06g032_clk_div_ops;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = parent_name ? &parent_name : NULL;
init.num_parents = parent_name ? 1 : 0;
div->clocks = clocks;
div->index = desc->index;
div->reg = desc->reg;
div->hw.init = &init;
div->min = desc->div_min;
div->max = desc->div_max;
/* populate (optional) divider table fixed values */
for (i = 0; i < ARRAY_SIZE(div->table) &&
i < ARRAY_SIZE(desc->div_table) && desc->div_table[i]; i++) {
div->table[div->table_size++] = desc->div_table[i];
}
clk = clk_register(NULL, &div->hw);
if (IS_ERR(clk)) {
kfree(div);
return NULL;
}
return clk;
}
/*
* This clock provider handles the case of the R9A06G032 where you have
* peripherals that have two potential clock source and two gates, one for
* each of the clock source - the used clock source (for all sub clocks)
* is selected by a single bit.
* That single bit affects all sub-clocks, and therefore needs to change the
* active gate (and turn the others off) and force a recalculation of the rates.
*
* This implements two clock providers, one 'bitselect' that
* handles the switch between both parents, and another 'dualgate'
* that knows which gate to poke at, depending on the parent's bit position.
*/
struct r9a06g032_clk_bitsel {
struct clk_hw hw;
struct r9a06g032_priv *clocks;
u16 index;
struct regbit selector; /* selector register + bit */
};
#define to_clk_bitselect(_hw) \
container_of(_hw, struct r9a06g032_clk_bitsel, hw)
static u8 r9a06g032_clk_mux_get_parent(struct clk_hw *hw)
{
struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw);
return clk_rdesc_get(set->clocks, set->selector);
}
static int r9a06g032_clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw);
/* a single bit in the register selects one of two parent clocks */
clk_rdesc_set(set->clocks, set->selector, !!index);
return 0;
}
static const struct clk_ops clk_bitselect_ops = {
.determine_rate = clk_hw_determine_rate_no_reparent,
.get_parent = r9a06g032_clk_mux_get_parent,
.set_parent = r9a06g032_clk_mux_set_parent,
};
static struct clk *
r9a06g032_register_bitsel(struct r9a06g032_priv *clocks,
const char *parent_name,
const struct r9a06g032_clkdesc *desc)
{
struct clk *clk;
struct r9a06g032_clk_bitsel *g;
struct clk_init_data init = {};
const char *names[2];
/* allocate the gate */
g = kzalloc(sizeof(*g), GFP_KERNEL);
if (!g)
return NULL;
names[0] = parent_name;
names[1] = "clk_pll_usb";
init.name = desc->name;
init.ops = &clk_bitselect_ops;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = names;
init.num_parents = 2;
g->clocks = clocks;
g->index = desc->index;
g->selector = desc->dual.sel;
g->hw.init = &init;
clk = clk_register(NULL, &g->hw);
if (IS_ERR(clk)) {
kfree(g);
return NULL;
}
return clk;
}
struct r9a06g032_clk_dualgate {
struct clk_hw hw;
struct r9a06g032_priv *clocks;
u16 index;
struct regbit selector; /* selector register + bit */
struct r9a06g032_gate gate[2];
};
#define to_clk_dualgate(_hw) \
container_of(_hw, struct r9a06g032_clk_dualgate, hw)
static int
r9a06g032_clk_dualgate_setenable(struct r9a06g032_clk_dualgate *g, int enable)
{
u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
/* we always turn off the 'other' gate, regardless */
r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0);
r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable);
return 0;
}
static int r9a06g032_clk_dualgate_enable(struct clk_hw *hw)
{
struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
r9a06g032_clk_dualgate_setenable(gate, 1);
return 0;
}
static void r9a06g032_clk_dualgate_disable(struct clk_hw *hw)
{
struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
r9a06g032_clk_dualgate_setenable(gate, 0);
}
static int r9a06g032_clk_dualgate_is_enabled(struct clk_hw *hw)
{
struct r9a06g032_clk_dualgate *g = to_clk_dualgate(hw);
u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate);
}
static const struct clk_ops r9a06g032_clk_dualgate_ops = {
.enable = r9a06g032_clk_dualgate_enable,
.disable = r9a06g032_clk_dualgate_disable,
.is_enabled = r9a06g032_clk_dualgate_is_enabled,
};
static struct clk *
r9a06g032_register_dualgate(struct r9a06g032_priv *clocks,
const char *parent_name,
const struct r9a06g032_clkdesc *desc,
struct regbit sel)
{
struct r9a06g032_clk_dualgate *g;
struct clk *clk;
struct clk_init_data init = {};
/* allocate the gate */
g = kzalloc(sizeof(*g), GFP_KERNEL);
if (!g)
return NULL;
g->clocks = clocks;
g->index = desc->index;
g->selector = sel;
g->gate[0].gate = desc->dual.g1;
g->gate[0].reset = desc->dual.r1;
g->gate[1].gate = desc->dual.g2;
g->gate[1].reset = desc->dual.r2;
init.name = desc->name;
init.ops = &r9a06g032_clk_dualgate_ops;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = &parent_name;
init.num_parents = 1;
g->hw.init = &init;
/*
* important here, some clocks are already in use by the CM3, we
* have to assume they are not Linux's to play with and try to disable
* at the end of the boot!
*/
if (r9a06g032_clk_dualgate_is_enabled(&g->hw)) {
init.flags |= CLK_IS_CRITICAL;
pr_debug("%s was enabled, making read-only\n", desc->name);
}
clk = clk_register(NULL, &g->hw);
if (IS_ERR(clk)) {
kfree(g);
return NULL;
}
return clk;
}
static void r9a06g032_clocks_del_clk_provider(void *data)
{
of_clk_del_provider(data);
}
static void __init r9a06g032_init_h2mode(struct r9a06g032_priv *clocks)
{
struct device_node *usbf_np = NULL;
u32 usb;
while ((usbf_np = of_find_compatible_node(usbf_np, NULL,
"renesas,rzn1-usbf"))) {
if (of_device_is_available(usbf_np))
break;
}
usb = readl(clocks->reg + R9A06G032_SYSCTRL_USB);
if (usbf_np) {
/* 1 host and 1 device mode */
usb &= ~R9A06G032_SYSCTRL_USB_H2MODE;
of_node_put(usbf_np);
} else {
/* 2 hosts mode */
usb |= R9A06G032_SYSCTRL_USB_H2MODE;
}
writel(usb, clocks->reg + R9A06G032_SYSCTRL_USB);
}
static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct r9a06g032_priv *clocks;
struct clk **clks;
struct clk *mclk;
unsigned int i;
struct regbit uart_group_sel[2];
int error;
clocks = devm_kzalloc(dev, sizeof(*clocks), GFP_KERNEL);
clks = devm_kcalloc(dev, R9A06G032_CLOCK_COUNT, sizeof(struct clk *),
GFP_KERNEL);
if (!clocks || !clks)
return -ENOMEM;
spin_lock_init(&clocks->lock);
clocks->data.clks = clks;
clocks->data.clk_num = R9A06G032_CLOCK_COUNT;
mclk = devm_clk_get(dev, "mclk");
if (IS_ERR(mclk))
return PTR_ERR(mclk);
clocks->reg = of_iomap(np, 0);
if (WARN_ON(!clocks->reg))
return -ENOMEM;
r9a06g032_init_h2mode(clocks);
for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) {
const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i];
const char *parent_name = d->source ?
__clk_get_name(clocks->data.clks[d->source - 1]) :
__clk_get_name(mclk);
struct clk *clk = NULL;
switch (d->type) {
case K_FFC:
clk = clk_register_fixed_factor(NULL, d->name,
parent_name, 0,
d->mul, d->div);
break;
case K_GATE:
clk = r9a06g032_register_gate(clocks, parent_name, d);
break;
case K_DIV:
clk = r9a06g032_register_div(clocks, parent_name, d);
break;
case K_BITSEL:
/* keep that selector register around */
uart_group_sel[d->dual.group] = d->dual.sel;
clk = r9a06g032_register_bitsel(clocks, parent_name, d);
break;
case K_DUALGATE:
clk = r9a06g032_register_dualgate(clocks, parent_name,
d,
uart_group_sel[d->dual.group]);
break;
}
clocks->data.clks[d->index] = clk;
}
error = of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data);
if (error)
return error;
error = devm_add_action_or_reset(dev,
r9a06g032_clocks_del_clk_provider, np);
if (error)
return error;
error = r9a06g032_add_clk_domain(dev);
if (error)
return error;
sysctrl_priv = clocks;
error = of_platform_populate(np, NULL, NULL, dev);
if (error)
dev_err(dev, "Failed to populate children (%d)\n", error);
return 0;
}
static const struct of_device_id r9a06g032_match[] = {
{ .compatible = "renesas,r9a06g032-sysctrl" },
{ }
};
static struct platform_driver r9a06g032_clock_driver = {
.driver = {
.name = "renesas,r9a06g032-sysctrl",
.of_match_table = r9a06g032_match,
},
};
static int __init r9a06g032_clocks_init(void)
{
return platform_driver_probe(&r9a06g032_clock_driver,
r9a06g032_clocks_probe);
}
subsys_initcall(r9a06g032_clocks_init);
| linux-master | drivers/clk/renesas/r9a06g032-clocks.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Daniel Palmer <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
/*
* This IP is not documented outside of the messy vendor driver.
* Below is what we think the registers look like based on looking at
* the vendor code and poking at the hardware:
*
* 0x140 -- LPF low. Seems to store one half of the clock transition
* 0x144 /
* 0x148 -- LPF high. Seems to store one half of the clock transition
* 0x14c /
* 0x150 -- vendor code says "toggle lpf enable"
* 0x154 -- mu?
* 0x15c -- lpf_update_count?
* 0x160 -- vendor code says "switch to LPF". Clock source config? Register bank?
* 0x164 -- vendor code says "from low to high" which seems to mean transition from LPF low to
* LPF high.
* 0x174 -- Seems to be the PLL lock status bit
* 0x180 -- Seems to be the current frequency, this might need to be populated by software?
* 0x184 / The vendor driver uses these to set the initial value of LPF low
*
* Frequency seems to be calculated like this:
* (parent clock (432mhz) / register_magic_value) * 16 * 524288
* Only the lower 24 bits of the resulting value will be used. In addition, the
* PLL doesn't seem to be able to lock on frequencies lower than 220 MHz, as
* divisor 0xfb586f (220 MHz) works but 0xfb7fff locks up.
*
* Vendor values:
* frequency - register value
*
* 400000000 - 0x0067AE14
* 600000000 - 0x00451EB8,
* 800000000 - 0x0033D70A,
* 1000000000 - 0x002978d4,
*/
#define REG_LPF_LOW_L 0x140
#define REG_LPF_LOW_H 0x144
#define REG_LPF_HIGH_BOTTOM 0x148
#define REG_LPF_HIGH_TOP 0x14c
#define REG_LPF_TOGGLE 0x150
#define REG_LPF_MYSTERYTWO 0x154
#define REG_LPF_UPDATE_COUNT 0x15c
#define REG_LPF_MYSTERYONE 0x160
#define REG_LPF_TRANSITIONCTRL 0x164
#define REG_LPF_LOCK 0x174
#define REG_CURRENT 0x180
#define LPF_LOCK_TIMEOUT 100000000
#define MULTIPLIER_1 16
#define MULTIPLIER_2 524288
#define MULTIPLIER (MULTIPLIER_1 * MULTIPLIER_2)
struct msc313_cpupll {
void __iomem *base;
struct clk_hw clk_hw;
};
#define to_cpupll(_hw) container_of(_hw, struct msc313_cpupll, clk_hw)
static u32 msc313_cpupll_reg_read32(struct msc313_cpupll *cpupll, unsigned int reg)
{
u32 value;
value = ioread16(cpupll->base + reg + 4) << 16;
value |= ioread16(cpupll->base + reg);
return value;
}
static void msc313_cpupll_reg_write32(struct msc313_cpupll *cpupll, unsigned int reg, u32 value)
{
u16 l = value & 0xffff, h = (value >> 16) & 0xffff;
iowrite16(l, cpupll->base + reg);
iowrite16(h, cpupll->base + reg + 4);
}
static void msc313_cpupll_setfreq(struct msc313_cpupll *cpupll, u32 regvalue)
{
ktime_t timeout;
msc313_cpupll_reg_write32(cpupll, REG_LPF_HIGH_BOTTOM, regvalue);
iowrite16(0x1, cpupll->base + REG_LPF_MYSTERYONE);
iowrite16(0x6, cpupll->base + REG_LPF_MYSTERYTWO);
iowrite16(0x8, cpupll->base + REG_LPF_UPDATE_COUNT);
iowrite16(BIT(12), cpupll->base + REG_LPF_TRANSITIONCTRL);
iowrite16(0, cpupll->base + REG_LPF_TOGGLE);
iowrite16(1, cpupll->base + REG_LPF_TOGGLE);
timeout = ktime_add_ns(ktime_get(), LPF_LOCK_TIMEOUT);
while (!(ioread16(cpupll->base + REG_LPF_LOCK))) {
if (ktime_after(ktime_get(), timeout)) {
pr_err("timeout waiting for LPF_LOCK\n");
return;
}
cpu_relax();
}
iowrite16(0, cpupll->base + REG_LPF_TOGGLE);
msc313_cpupll_reg_write32(cpupll, REG_LPF_LOW_L, regvalue);
}
static unsigned long msc313_cpupll_frequencyforreg(u32 reg, unsigned long parent_rate)
{
unsigned long long prescaled = ((unsigned long long)parent_rate) * MULTIPLIER;
if (prescaled == 0 || reg == 0)
return 0;
return DIV_ROUND_DOWN_ULL(prescaled, reg);
}
static u32 msc313_cpupll_regforfrequecy(unsigned long rate, unsigned long parent_rate)
{
unsigned long long prescaled = ((unsigned long long)parent_rate) * MULTIPLIER;
if (prescaled == 0 || rate == 0)
return 0;
return DIV_ROUND_UP_ULL(prescaled, rate);
}
static unsigned long msc313_cpupll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct msc313_cpupll *cpupll = to_cpupll(hw);
return msc313_cpupll_frequencyforreg(msc313_cpupll_reg_read32(cpupll, REG_LPF_LOW_L),
parent_rate);
}
static long msc313_cpupll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
u32 reg = msc313_cpupll_regforfrequecy(rate, *parent_rate);
long rounded = msc313_cpupll_frequencyforreg(reg, *parent_rate);
/*
* This is my poor attempt at making sure the resulting
* rate doesn't overshoot the requested rate.
*/
for (; rounded >= rate && reg > 0; reg--)
rounded = msc313_cpupll_frequencyforreg(reg, *parent_rate);
return rounded;
}
static int msc313_cpupll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
{
struct msc313_cpupll *cpupll = to_cpupll(hw);
u32 reg = msc313_cpupll_regforfrequecy(rate, parent_rate);
msc313_cpupll_setfreq(cpupll, reg);
return 0;
}
static const struct clk_ops msc313_cpupll_ops = {
.recalc_rate = msc313_cpupll_recalc_rate,
.round_rate = msc313_cpupll_round_rate,
.set_rate = msc313_cpupll_set_rate,
};
static const struct of_device_id msc313_cpupll_of_match[] = {
{ .compatible = "mstar,msc313-cpupll" },
{}
};
static int msc313_cpupll_probe(struct platform_device *pdev)
{
struct clk_init_data clk_init = {};
struct clk_parent_data cpupll_parent = { .index = 0 };
struct device *dev = &pdev->dev;
struct msc313_cpupll *cpupll;
int ret;
cpupll = devm_kzalloc(&pdev->dev, sizeof(*cpupll), GFP_KERNEL);
if (!cpupll)
return -ENOMEM;
cpupll->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(cpupll->base))
return PTR_ERR(cpupll->base);
/* LPF might not contain the current frequency so fix that up */
msc313_cpupll_reg_write32(cpupll, REG_LPF_LOW_L,
msc313_cpupll_reg_read32(cpupll, REG_CURRENT));
clk_init.name = dev_name(dev);
clk_init.ops = &msc313_cpupll_ops;
clk_init.parent_data = &cpupll_parent;
clk_init.num_parents = 1;
cpupll->clk_hw.init = &clk_init;
ret = devm_clk_hw_register(dev, &cpupll->clk_hw);
if (ret)
return ret;
return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get, &cpupll->clk_hw);
}
static struct platform_driver msc313_cpupll_driver = {
.driver = {
.name = "mstar-msc313-cpupll",
.of_match_table = msc313_cpupll_of_match,
},
.probe = msc313_cpupll_probe,
};
builtin_platform_driver(msc313_cpupll_driver);
| linux-master | drivers/clk/mstar/clk-msc313-cpupll.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MStar MSC313 MPLL driver
*
* Copyright (C) 2020 Daniel Palmer <[email protected]>
*/
#include <linux/platform_device.h>
#include <linux/of_address.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#define REG_CONFIG1 0x8
#define REG_CONFIG2 0xc
static const struct regmap_config msc313_mpll_regmap_config = {
.reg_bits = 16,
.val_bits = 16,
.reg_stride = 4,
};
static const struct reg_field config1_loop_div_first = REG_FIELD(REG_CONFIG1, 8, 9);
static const struct reg_field config1_input_div_first = REG_FIELD(REG_CONFIG1, 4, 5);
static const struct reg_field config2_output_div_first = REG_FIELD(REG_CONFIG2, 12, 13);
static const struct reg_field config2_loop_div_second = REG_FIELD(REG_CONFIG2, 0, 7);
static const unsigned int output_dividers[] = {
2, 3, 4, 5, 6, 7, 10
};
#define NUMOUTPUTS (ARRAY_SIZE(output_dividers) + 1)
struct msc313_mpll {
struct clk_hw clk_hw;
struct regmap_field *input_div;
struct regmap_field *loop_div_first;
struct regmap_field *loop_div_second;
struct regmap_field *output_div;
struct clk_hw_onecell_data *clk_data;
};
#define to_mpll(_hw) container_of(_hw, struct msc313_mpll, clk_hw)
static unsigned long msc313_mpll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct msc313_mpll *mpll = to_mpll(hw);
unsigned int input_div, output_div, loop_first, loop_second;
unsigned long output_rate;
regmap_field_read(mpll->input_div, &input_div);
regmap_field_read(mpll->output_div, &output_div);
regmap_field_read(mpll->loop_div_first, &loop_first);
regmap_field_read(mpll->loop_div_second, &loop_second);
output_rate = parent_rate / (1 << input_div);
output_rate *= (1 << loop_first) * max(loop_second, 1U);
output_rate /= max(output_div, 1U);
return output_rate;
}
static const struct clk_ops msc313_mpll_ops = {
.recalc_rate = msc313_mpll_recalc_rate,
};
static const struct clk_parent_data mpll_parent = {
.index = 0,
};
static int msc313_mpll_probe(struct platform_device *pdev)
{
void __iomem *base;
struct msc313_mpll *mpll;
struct clk_init_data clk_init = { };
struct device *dev = &pdev->dev;
struct regmap *regmap;
char *outputname;
struct clk_hw *divhw;
int ret, i;
mpll = devm_kzalloc(dev, sizeof(*mpll), GFP_KERNEL);
if (!mpll)
return -ENOMEM;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(dev, base, &msc313_mpll_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
mpll->input_div = devm_regmap_field_alloc(dev, regmap, config1_input_div_first);
if (IS_ERR(mpll->input_div))
return PTR_ERR(mpll->input_div);
mpll->output_div = devm_regmap_field_alloc(dev, regmap, config2_output_div_first);
if (IS_ERR(mpll->output_div))
return PTR_ERR(mpll->output_div);
mpll->loop_div_first = devm_regmap_field_alloc(dev, regmap, config1_loop_div_first);
if (IS_ERR(mpll->loop_div_first))
return PTR_ERR(mpll->loop_div_first);
mpll->loop_div_second = devm_regmap_field_alloc(dev, regmap, config2_loop_div_second);
if (IS_ERR(mpll->loop_div_second))
return PTR_ERR(mpll->loop_div_second);
mpll->clk_data = devm_kzalloc(dev, struct_size(mpll->clk_data, hws,
ARRAY_SIZE(output_dividers)), GFP_KERNEL);
if (!mpll->clk_data)
return -ENOMEM;
clk_init.name = dev_name(dev);
clk_init.ops = &msc313_mpll_ops;
clk_init.parent_data = &mpll_parent;
clk_init.num_parents = 1;
mpll->clk_hw.init = &clk_init;
ret = devm_clk_hw_register(dev, &mpll->clk_hw);
if (ret)
return ret;
mpll->clk_data->num = NUMOUTPUTS;
mpll->clk_data->hws[0] = &mpll->clk_hw;
for (i = 0; i < ARRAY_SIZE(output_dividers); i++) {
outputname = devm_kasprintf(dev, GFP_KERNEL, "%s_div_%u",
clk_init.name, output_dividers[i]);
if (!outputname)
return -ENOMEM;
divhw = devm_clk_hw_register_fixed_factor(dev, outputname,
clk_init.name, 0, 1, output_dividers[i]);
if (IS_ERR(divhw))
return PTR_ERR(divhw);
mpll->clk_data->hws[i + 1] = divhw;
}
platform_set_drvdata(pdev, mpll);
return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
mpll->clk_data);
}
static const struct of_device_id msc313_mpll_of_match[] = {
{ .compatible = "mstar,msc313-mpll", },
{}
};
static struct platform_driver msc313_mpll_driver = {
.driver = {
.name = "mstar-msc313-mpll",
.of_match_table = msc313_mpll_of_match,
},
.probe = msc313_mpll_probe,
};
builtin_platform_driver(msc313_mpll_driver);
| linux-master | drivers/clk/mstar/clk-msc313-mpll.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Synopsys AXS10X SDP Generic PLL clock driver
*
* Copyright (C) 2017 Synopsys
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
/* PLL registers addresses */
#define PLL_REG_IDIV 0x0
#define PLL_REG_FBDIV 0x4
#define PLL_REG_ODIV 0x8
/*
* Bit fields of the PLL IDIV/FBDIV/ODIV registers:
* ________________________________________________________________________
* |31 15| 14 | 13 | 12 |11 6|5 0|
* |-------RESRVED------|-NOUPDATE-|-BYPASS-|-EDGE-|--HIGHTIME--|--LOWTIME--|
* |____________________|__________|________|______|____________|___________|
*
* Following macros determine the way of access to these registers
* They should be set up only using the macros.
* reg should be an u32 variable.
*/
#define PLL_REG_GET_LOW(reg) \
(((reg) & (0x3F << 0)) >> 0)
#define PLL_REG_GET_HIGH(reg) \
(((reg) & (0x3F << 6)) >> 6)
#define PLL_REG_GET_EDGE(reg) \
(((reg) & (BIT(12))) ? 1 : 0)
#define PLL_REG_GET_BYPASS(reg) \
(((reg) & (BIT(13))) ? 1 : 0)
#define PLL_REG_GET_NOUPD(reg) \
(((reg) & (BIT(14))) ? 1 : 0)
#define PLL_REG_GET_PAD(reg) \
(((reg) & (0x1FFFF << 15)) >> 15)
#define PLL_REG_SET_LOW(reg, value) \
{ reg |= (((value) & 0x3F) << 0); }
#define PLL_REG_SET_HIGH(reg, value) \
{ reg |= (((value) & 0x3F) << 6); }
#define PLL_REG_SET_EDGE(reg, value) \
{ reg |= (((value) & 0x01) << 12); }
#define PLL_REG_SET_BYPASS(reg, value) \
{ reg |= (((value) & 0x01) << 13); }
#define PLL_REG_SET_NOUPD(reg, value) \
{ reg |= (((value) & 0x01) << 14); }
#define PLL_REG_SET_PAD(reg, value) \
{ reg |= (((value) & 0x1FFFF) << 15); }
#define PLL_LOCK BIT(0)
#define PLL_ERROR BIT(1)
#define PLL_MAX_LOCK_TIME 100 /* 100 us */
struct axs10x_pll_cfg {
u32 rate;
u32 idiv;
u32 fbdiv;
u32 odiv;
};
static const struct axs10x_pll_cfg arc_pll_cfg[] = {
{ 33333333, 1, 1, 1 },
{ 50000000, 1, 30, 20 },
{ 75000000, 2, 45, 10 },
{ 90000000, 2, 54, 10 },
{ 100000000, 1, 30, 10 },
{ 125000000, 2, 45, 6 },
{}
};
static const struct axs10x_pll_cfg pgu_pll_cfg[] = {
{ 25200000, 1, 84, 90 },
{ 50000000, 1, 100, 54 },
{ 74250000, 1, 44, 16 },
{}
};
struct axs10x_pll_clk {
struct clk_hw hw;
void __iomem *base;
void __iomem *lock;
const struct axs10x_pll_cfg *pll_cfg;
struct device *dev;
};
static inline void axs10x_pll_write(struct axs10x_pll_clk *clk, u32 reg,
u32 val)
{
iowrite32(val, clk->base + reg);
}
static inline u32 axs10x_pll_read(struct axs10x_pll_clk *clk, u32 reg)
{
return ioread32(clk->base + reg);
}
static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct clk_hw *hw)
{
return container_of(hw, struct axs10x_pll_clk, hw);
}
static inline u32 axs10x_div_get_value(u32 reg)
{
if (PLL_REG_GET_BYPASS(reg))
return 1;
return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);
}
static inline u32 axs10x_encode_div(unsigned int id, int upd)
{
u32 div = 0;
PLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) + 1);
PLL_REG_SET_HIGH(div, id >> 1);
PLL_REG_SET_EDGE(div, id % 2);
PLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0);
PLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0);
return div;
}
static unsigned long axs10x_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
u64 rate;
u32 idiv, fbdiv, odiv;
struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
idiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_IDIV));
fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV));
odiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_ODIV));
rate = (u64)parent_rate * fbdiv;
do_div(rate, idiv * odiv);
return rate;
}
static long axs10x_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
int i;
long best_rate;
struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
if (pll_cfg[0].rate == 0)
return -EINVAL;
best_rate = pll_cfg[0].rate;
for (i = 1; pll_cfg[i].rate != 0; i++) {
if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
best_rate = pll_cfg[i].rate;
}
return best_rate;
}
static int axs10x_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
int i;
struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
for (i = 0; pll_cfg[i].rate != 0; i++) {
if (pll_cfg[i].rate == rate) {
axs10x_pll_write(clk, PLL_REG_IDIV,
axs10x_encode_div(pll_cfg[i].idiv, 0));
axs10x_pll_write(clk, PLL_REG_FBDIV,
axs10x_encode_div(pll_cfg[i].fbdiv, 0));
axs10x_pll_write(clk, PLL_REG_ODIV,
axs10x_encode_div(pll_cfg[i].odiv, 1));
/*
* Wait until CGU relocks and check error status.
* If after timeout CGU is unlocked yet return error
*/
udelay(PLL_MAX_LOCK_TIME);
if (!(ioread32(clk->lock) & PLL_LOCK))
return -ETIMEDOUT;
if (ioread32(clk->lock) & PLL_ERROR)
return -EINVAL;
return 0;
}
}
dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,
parent_rate);
return -EINVAL;
}
static const struct clk_ops axs10x_pll_ops = {
.recalc_rate = axs10x_pll_recalc_rate,
.round_rate = axs10x_pll_round_rate,
.set_rate = axs10x_pll_set_rate,
};
static int axs10x_pll_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const char *parent_name;
struct axs10x_pll_clk *pll_clk;
struct clk_init_data init = { };
int ret;
pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
if (!pll_clk)
return -ENOMEM;
pll_clk->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pll_clk->base))
return PTR_ERR(pll_clk->base);
pll_clk->lock = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(pll_clk->lock))
return PTR_ERR(pll_clk->lock);
init.name = dev->of_node->name;
init.ops = &axs10x_pll_ops;
parent_name = of_clk_get_parent_name(dev->of_node, 0);
init.parent_names = &parent_name;
init.num_parents = 1;
pll_clk->hw.init = &init;
pll_clk->dev = dev;
pll_clk->pll_cfg = of_device_get_match_data(dev);
if (!pll_clk->pll_cfg) {
dev_err(dev, "No OF match data provided\n");
return -EINVAL;
}
ret = devm_clk_hw_register(dev, &pll_clk->hw);
if (ret) {
dev_err(dev, "failed to register %s clock\n", init.name);
return ret;
}
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
&pll_clk->hw);
}
static void __init of_axs10x_pll_clk_setup(struct device_node *node)
{
const char *parent_name;
struct axs10x_pll_clk *pll_clk;
struct clk_init_data init = { };
int ret;
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
if (!pll_clk)
return;
pll_clk->base = of_iomap(node, 0);
if (!pll_clk->base) {
pr_err("failed to map pll div registers\n");
goto err_free_pll_clk;
}
pll_clk->lock = of_iomap(node, 1);
if (!pll_clk->lock) {
pr_err("failed to map pll lock register\n");
goto err_unmap_base;
}
init.name = node->name;
init.ops = &axs10x_pll_ops;
parent_name = of_clk_get_parent_name(node, 0);
init.parent_names = &parent_name;
init.num_parents = parent_name ? 1 : 0;
pll_clk->hw.init = &init;
pll_clk->pll_cfg = arc_pll_cfg;
ret = clk_hw_register(NULL, &pll_clk->hw);
if (ret) {
pr_err("failed to register %pOFn clock\n", node);
goto err_unmap_lock;
}
ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
if (ret) {
pr_err("failed to add hw provider for %pOFn clock\n", node);
goto err_unregister_clk;
}
return;
err_unregister_clk:
clk_hw_unregister(&pll_clk->hw);
err_unmap_lock:
iounmap(pll_clk->lock);
err_unmap_base:
iounmap(pll_clk->base);
err_free_pll_clk:
kfree(pll_clk);
}
CLK_OF_DECLARE(axs10x_pll_clock, "snps,axs10x-arc-pll-clock",
of_axs10x_pll_clk_setup);
static const struct of_device_id axs10x_pll_clk_id[] = {
{ .compatible = "snps,axs10x-pgu-pll-clock", .data = &pgu_pll_cfg},
{ }
};
MODULE_DEVICE_TABLE(of, axs10x_pll_clk_id);
static struct platform_driver axs10x_pll_clk_driver = {
.driver = {
.name = "axs10x-pll-clock",
.of_match_table = axs10x_pll_clk_id,
},
.probe = axs10x_pll_clk_probe,
};
builtin_platform_driver(axs10x_pll_clk_driver);
MODULE_AUTHOR("Vlad Zakharov <[email protected]>");
MODULE_DESCRIPTION("Synopsys AXS10X SDP Generic PLL Clock Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/axs10x/pll_clock.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Synopsys AXS10X SDP I2S PLL clock driver
*
* Copyright (C) 2016 Synopsys
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/of.h>
/* PLL registers addresses */
#define PLL_IDIV_REG 0x0
#define PLL_FBDIV_REG 0x4
#define PLL_ODIV0_REG 0x8
#define PLL_ODIV1_REG 0xC
struct i2s_pll_cfg {
unsigned int rate;
unsigned int idiv;
unsigned int fbdiv;
unsigned int odiv0;
unsigned int odiv1;
};
static const struct i2s_pll_cfg i2s_pll_cfg_27m[] = {
/* 27 Mhz */
{ 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
{ 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
{ 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
{ 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
{ 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
{ 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
{ 2116800, 0x82, 0x3CF, 0x10C30, 0x2000 },
{ 2304000, 0x104, 0x79E, 0x10B2C, 0x2000 },
{ 0, 0, 0, 0, 0 },
};
static const struct i2s_pll_cfg i2s_pll_cfg_28m[] = {
/* 28.224 Mhz */
{ 1024000, 0x82, 0x105, 0x107DF, 0x2000 },
{ 1411200, 0x28A, 0x1, 0x10001, 0x2000 },
{ 1536000, 0xA28, 0x187, 0x10042, 0x2000 },
{ 2048000, 0x41, 0x105, 0x107DF, 0x2000 },
{ 2822400, 0x145, 0x1, 0x10001, 0x2000 },
{ 3072000, 0x514, 0x187, 0x10042, 0x2000 },
{ 2116800, 0x514, 0x42, 0x10001, 0x2000 },
{ 2304000, 0x619, 0x82, 0x10001, 0x2000 },
{ 0, 0, 0, 0, 0 },
};
struct i2s_pll_clk {
void __iomem *base;
struct clk_hw hw;
struct device *dev;
};
static inline void i2s_pll_write(struct i2s_pll_clk *clk, unsigned int reg,
unsigned int val)
{
writel_relaxed(val, clk->base + reg);
}
static inline unsigned int i2s_pll_read(struct i2s_pll_clk *clk,
unsigned int reg)
{
return readl_relaxed(clk->base + reg);
}
static inline struct i2s_pll_clk *to_i2s_pll_clk(struct clk_hw *hw)
{
return container_of(hw, struct i2s_pll_clk, hw);
}
static inline unsigned int i2s_pll_get_value(unsigned int val)
{
return (val & 0x3F) + ((val >> 6) & 0x3F);
}
static const struct i2s_pll_cfg *i2s_pll_get_cfg(unsigned long prate)
{
switch (prate) {
case 27000000:
return i2s_pll_cfg_27m;
case 28224000:
return i2s_pll_cfg_28m;
default:
return NULL;
}
}
static unsigned long i2s_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct i2s_pll_clk *clk = to_i2s_pll_clk(hw);
unsigned int idiv, fbdiv, odiv;
idiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_IDIV_REG));
fbdiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_FBDIV_REG));
odiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_ODIV0_REG));
return ((parent_rate / idiv) * fbdiv) / odiv;
}
static long i2s_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct i2s_pll_clk *clk = to_i2s_pll_clk(hw);
const struct i2s_pll_cfg *pll_cfg = i2s_pll_get_cfg(*prate);
int i;
if (!pll_cfg) {
dev_err(clk->dev, "invalid parent rate=%ld\n", *prate);
return -EINVAL;
}
for (i = 0; pll_cfg[i].rate != 0; i++)
if (pll_cfg[i].rate == rate)
return rate;
return -EINVAL;
}
static int i2s_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct i2s_pll_clk *clk = to_i2s_pll_clk(hw);
const struct i2s_pll_cfg *pll_cfg = i2s_pll_get_cfg(parent_rate);
int i;
if (!pll_cfg) {
dev_err(clk->dev, "invalid parent rate=%ld\n", parent_rate);
return -EINVAL;
}
for (i = 0; pll_cfg[i].rate != 0; i++) {
if (pll_cfg[i].rate == rate) {
i2s_pll_write(clk, PLL_IDIV_REG, pll_cfg[i].idiv);
i2s_pll_write(clk, PLL_FBDIV_REG, pll_cfg[i].fbdiv);
i2s_pll_write(clk, PLL_ODIV0_REG, pll_cfg[i].odiv0);
i2s_pll_write(clk, PLL_ODIV1_REG, pll_cfg[i].odiv1);
return 0;
}
}
dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,
parent_rate);
return -EINVAL;
}
static const struct clk_ops i2s_pll_ops = {
.recalc_rate = i2s_pll_recalc_rate,
.round_rate = i2s_pll_round_rate,
.set_rate = i2s_pll_set_rate,
};
static int i2s_pll_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
const char *clk_name;
const char *parent_name;
struct clk *clk;
struct i2s_pll_clk *pll_clk;
struct clk_init_data init;
pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
if (!pll_clk)
return -ENOMEM;
pll_clk->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pll_clk->base))
return PTR_ERR(pll_clk->base);
memset(&init, 0, sizeof(init));
clk_name = node->name;
init.name = clk_name;
init.ops = &i2s_pll_ops;
parent_name = of_clk_get_parent_name(node, 0);
init.parent_names = &parent_name;
init.num_parents = 1;
pll_clk->hw.init = &init;
pll_clk->dev = dev;
clk = devm_clk_register(dev, &pll_clk->hw);
if (IS_ERR(clk)) {
dev_err(dev, "failed to register %s clock (%ld)\n",
clk_name, PTR_ERR(clk));
return PTR_ERR(clk);
}
return of_clk_add_provider(node, of_clk_src_simple_get, clk);
}
static void i2s_pll_clk_remove(struct platform_device *pdev)
{
of_clk_del_provider(pdev->dev.of_node);
}
static const struct of_device_id i2s_pll_clk_id[] = {
{ .compatible = "snps,axs10x-i2s-pll-clock", },
{ },
};
MODULE_DEVICE_TABLE(of, i2s_pll_clk_id);
static struct platform_driver i2s_pll_clk_driver = {
.driver = {
.name = "axs10x-i2s-pll-clock",
.of_match_table = i2s_pll_clk_id,
},
.probe = i2s_pll_clk_probe,
.remove_new = i2s_pll_clk_remove,
};
module_platform_driver(i2s_pll_clk_driver);
MODULE_AUTHOR("Jose Abreu <[email protected]>");
MODULE_DESCRIPTION("Synopsys AXS10X SDP I2S PLL Clock Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/axs10x/i2s_pll_clock.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/regmap.h>
#include "clk-uniphier.h"
struct uniphier_clk_gate {
struct clk_hw hw;
struct regmap *regmap;
unsigned int reg;
unsigned int bit;
};
#define to_uniphier_clk_gate(_hw) \
container_of(_hw, struct uniphier_clk_gate, hw)
static int uniphier_clk_gate_endisable(struct clk_hw *hw, int enable)
{
struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit),
enable ? BIT(gate->bit) : 0);
}
static int uniphier_clk_gate_enable(struct clk_hw *hw)
{
return uniphier_clk_gate_endisable(hw, 1);
}
static void uniphier_clk_gate_disable(struct clk_hw *hw)
{
if (uniphier_clk_gate_endisable(hw, 0) < 0)
pr_warn("failed to disable clk\n");
}
static int uniphier_clk_gate_is_enabled(struct clk_hw *hw)
{
struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
unsigned int val;
if (regmap_read(gate->regmap, gate->reg, &val) < 0)
pr_warn("is_enabled() may return wrong result\n");
return !!(val & BIT(gate->bit));
}
static const struct clk_ops uniphier_clk_gate_ops = {
.enable = uniphier_clk_gate_enable,
.disable = uniphier_clk_gate_disable,
.is_enabled = uniphier_clk_gate_is_enabled,
};
struct clk_hw *uniphier_clk_register_gate(struct device *dev,
struct regmap *regmap,
const char *name,
const struct uniphier_clk_gate_data *data)
{
struct uniphier_clk_gate *gate;
struct clk_init_data init;
int ret;
gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
if (!gate)
return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = &uniphier_clk_gate_ops;
init.flags = data->parent_name ? CLK_SET_RATE_PARENT : 0;
init.parent_names = data->parent_name ? &data->parent_name : NULL;
init.num_parents = data->parent_name ? 1 : 0;
gate->regmap = regmap;
gate->reg = data->reg;
gate->bit = data->bit;
gate->hw.init = &init;
ret = devm_clk_hw_register(dev, &gate->hw);
if (ret)
return ERR_PTR(ret);
return &gate->hw;
}
| linux-master | drivers/clk/uniphier/clk-uniphier-gate.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/regmap.h>
#include "clk-uniphier.h"
struct uniphier_clk_mux {
struct clk_hw hw;
struct regmap *regmap;
unsigned int reg;
const unsigned int *masks;
const unsigned int *vals;
};
#define to_uniphier_clk_mux(_hw) container_of(_hw, struct uniphier_clk_mux, hw)
static int uniphier_clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index],
mux->vals[index]);
}
static u8 uniphier_clk_mux_get_parent(struct clk_hw *hw)
{
struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
unsigned int num_parents = clk_hw_get_num_parents(hw);
int ret;
unsigned int val;
unsigned int i;
ret = regmap_read(mux->regmap, mux->reg, &val);
if (ret)
return ret;
for (i = 0; i < num_parents; i++)
if ((mux->masks[i] & val) == mux->vals[i])
return i;
return -EINVAL;
}
static const struct clk_ops uniphier_clk_mux_ops = {
.determine_rate = __clk_mux_determine_rate,
.set_parent = uniphier_clk_mux_set_parent,
.get_parent = uniphier_clk_mux_get_parent,
};
struct clk_hw *uniphier_clk_register_mux(struct device *dev,
struct regmap *regmap,
const char *name,
const struct uniphier_clk_mux_data *data)
{
struct uniphier_clk_mux *mux;
struct clk_init_data init;
int ret;
mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = &uniphier_clk_mux_ops;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = data->parent_names;
init.num_parents = data->num_parents;
mux->regmap = regmap;
mux->reg = data->reg;
mux->masks = data->masks;
mux->vals = data->vals;
mux->hw.init = &init;
ret = devm_clk_hw_register(dev, &mux->hw);
if (ret)
return ERR_PTR(ret);
return &mux->hw;
}
| linux-master | drivers/clk/uniphier/clk-uniphier-mux.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/device.h>
#include "clk-uniphier.h"
struct clk_hw *uniphier_clk_register_fixed_rate(struct device *dev,
const char *name,
const struct uniphier_clk_fixed_rate_data *data)
{
struct clk_fixed_rate *fixed;
struct clk_init_data init;
int ret;
/* allocate fixed-rate clock */
fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
if (!fixed)
return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = &clk_fixed_rate_ops;
init.flags = 0;
init.parent_names = NULL;
init.num_parents = 0;
fixed->fixed_rate = data->fixed_rate;
fixed->hw.init = &init;
ret = devm_clk_hw_register(dev, &fixed->hw);
if (ret)
return ERR_PTR(ret);
return &fixed->hw;
}
| linux-master | drivers/clk/uniphier/clk-uniphier-fixed-rate.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <[email protected]>
*/
#include <linux/stddef.h>
#include "clk-uniphier.h"
#define UNIPHIER_MIO_CLK_SD_FIXED \
UNIPHIER_CLK_FACTOR("sd-44m", -1, "sd-133m", 1, 3), \
UNIPHIER_CLK_FACTOR("sd-33m", -1, "sd-200m", 1, 6), \
UNIPHIER_CLK_FACTOR("sd-50m", -1, "sd-200m", 1, 4), \
UNIPHIER_CLK_FACTOR("sd-67m", -1, "sd-200m", 1, 3), \
UNIPHIER_CLK_FACTOR("sd-100m", -1, "sd-200m", 1, 2), \
UNIPHIER_CLK_FACTOR("sd-40m", -1, "sd-200m", 1, 5), \
UNIPHIER_CLK_FACTOR("sd-25m", -1, "sd-200m", 1, 8), \
UNIPHIER_CLK_FACTOR("sd-22m", -1, "sd-133m", 1, 6)
#define UNIPHIER_MIO_CLK_SD(_idx, ch) \
{ \
.name = "sd" #ch "-sel", \
.type = UNIPHIER_CLK_TYPE_MUX, \
.idx = -1, \
.data.mux = { \
.parent_names = { \
"sd-44m", \
"sd-33m", \
"sd-50m", \
"sd-67m", \
"sd-100m", \
"sd-40m", \
"sd-25m", \
"sd-22m", \
}, \
.num_parents = 8, \
.reg = 0x30 + 0x200 * (ch), \
.masks = { \
0x00031000, \
0x00031000, \
0x00031000, \
0x00031000, \
0x00001300, \
0x00001300, \
0x00001300, \
0x00001300, \
}, \
.vals = { \
0x00000000, \
0x00010000, \
0x00020000, \
0x00030000, \
0x00001000, \
0x00001100, \
0x00001200, \
0x00001300, \
}, \
}, \
}, \
UNIPHIER_CLK_GATE("sd" #ch, (_idx), "sd" #ch "-sel", 0x20 + 0x200 * (ch), 8)
#define UNIPHIER_MIO_CLK_USB2(idx, ch) \
UNIPHIER_CLK_GATE("usb2" #ch, (idx), "usb2", 0x20 + 0x200 * (ch), 28)
#define UNIPHIER_MIO_CLK_USB2_PHY(idx, ch) \
UNIPHIER_CLK_GATE("usb2" #ch "-phy", (idx), "usb2", 0x20 + 0x200 * (ch), 29)
const struct uniphier_clk_data uniphier_ld4_mio_clk_data[] = {
UNIPHIER_MIO_CLK_SD_FIXED,
UNIPHIER_MIO_CLK_SD(0, 0),
UNIPHIER_MIO_CLK_SD(1, 1),
UNIPHIER_MIO_CLK_SD(2, 2),
UNIPHIER_CLK_GATE("miodmac", 7, NULL, 0x20, 25),
UNIPHIER_MIO_CLK_USB2(8, 0),
UNIPHIER_MIO_CLK_USB2(9, 1),
UNIPHIER_MIO_CLK_USB2(10, 2),
UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
{ /* sentinel */ }
};
const struct uniphier_clk_data uniphier_pro5_sd_clk_data[] = {
UNIPHIER_MIO_CLK_SD_FIXED,
UNIPHIER_MIO_CLK_SD(0, 0),
UNIPHIER_MIO_CLK_SD(1, 1),
{ /* sentinel */ }
};
| linux-master | drivers/clk/uniphier/clk-uniphier-mio.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/regmap.h>
#include "clk-uniphier.h"
#define UNIPHIER_CLK_CPUGEAR_STAT 0 /* status */
#define UNIPHIER_CLK_CPUGEAR_SET 4 /* set */
#define UNIPHIER_CLK_CPUGEAR_UPD 8 /* update */
#define UNIPHIER_CLK_CPUGEAR_UPD_BIT BIT(0)
struct uniphier_clk_cpugear {
struct clk_hw hw;
struct regmap *regmap;
unsigned int regbase;
unsigned int mask;
};
#define to_uniphier_clk_cpugear(_hw) \
container_of(_hw, struct uniphier_clk_cpugear, hw)
static int uniphier_clk_cpugear_set_parent(struct clk_hw *hw, u8 index)
{
struct uniphier_clk_cpugear *gear = to_uniphier_clk_cpugear(hw);
int ret;
unsigned int val;
ret = regmap_write_bits(gear->regmap,
gear->regbase + UNIPHIER_CLK_CPUGEAR_SET,
gear->mask, index);
if (ret)
return ret;
ret = regmap_write_bits(gear->regmap,
gear->regbase + UNIPHIER_CLK_CPUGEAR_UPD,
UNIPHIER_CLK_CPUGEAR_UPD_BIT,
UNIPHIER_CLK_CPUGEAR_UPD_BIT);
if (ret)
return ret;
return regmap_read_poll_timeout(gear->regmap,
gear->regbase + UNIPHIER_CLK_CPUGEAR_UPD,
val, !(val & UNIPHIER_CLK_CPUGEAR_UPD_BIT),
0, 1);
}
static u8 uniphier_clk_cpugear_get_parent(struct clk_hw *hw)
{
struct uniphier_clk_cpugear *gear = to_uniphier_clk_cpugear(hw);
int num_parents = clk_hw_get_num_parents(hw);
int ret;
unsigned int val;
ret = regmap_read(gear->regmap,
gear->regbase + UNIPHIER_CLK_CPUGEAR_STAT, &val);
if (ret)
return ret;
val &= gear->mask;
return val < num_parents ? val : -EINVAL;
}
static const struct clk_ops uniphier_clk_cpugear_ops = {
.determine_rate = __clk_mux_determine_rate,
.set_parent = uniphier_clk_cpugear_set_parent,
.get_parent = uniphier_clk_cpugear_get_parent,
};
struct clk_hw *uniphier_clk_register_cpugear(struct device *dev,
struct regmap *regmap,
const char *name,
const struct uniphier_clk_cpugear_data *data)
{
struct uniphier_clk_cpugear *gear;
struct clk_init_data init;
int ret;
gear = devm_kzalloc(dev, sizeof(*gear), GFP_KERNEL);
if (!gear)
return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = &uniphier_clk_cpugear_ops;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = data->parent_names;
init.num_parents = data->num_parents;
gear->regmap = regmap;
gear->regbase = data->regbase;
gear->mask = data->mask;
gear->hw.init = &init;
ret = devm_clk_hw_register(dev, &gear->hw);
if (ret)
return ERR_PTR(ret);
return &gear->hw;
}
| linux-master | drivers/clk/uniphier/clk-uniphier-cpugear.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/device.h>
#include "clk-uniphier.h"
struct clk_hw *uniphier_clk_register_fixed_factor(struct device *dev,
const char *name,
const struct uniphier_clk_fixed_factor_data *data)
{
struct clk_fixed_factor *fix;
struct clk_init_data init;
int ret;
fix = devm_kzalloc(dev, sizeof(*fix), GFP_KERNEL);
if (!fix)
return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = &clk_fixed_factor_ops;
init.flags = data->parent_name ? CLK_SET_RATE_PARENT : 0;
init.parent_names = data->parent_name ? &data->parent_name : NULL;
init.num_parents = data->parent_name ? 1 : 0;
fix->mult = data->mult;
fix->div = data->div;
fix->hw.init = &init;
ret = devm_clk_hw_register(dev, &fix->hw);
if (ret)
return ERR_PTR(ret);
return &fix->hw;
}
| linux-master | drivers/clk/uniphier/clk-uniphier-fixed-factor.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <[email protected]>
*/
#include "clk-uniphier.h"
#define UNIPHIER_PERI_CLK_UART(idx, ch) \
UNIPHIER_CLK_GATE("uart" #ch, (idx), "uart", 0x24, 19 + (ch))
#define UNIPHIER_PERI_CLK_I2C_COMMON \
UNIPHIER_CLK_GATE("i2c-common", -1, "i2c", 0x20, 1)
#define UNIPHIER_PERI_CLK_I2C(idx, ch) \
UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c-common", 0x24, 5 + (ch))
#define UNIPHIER_PERI_CLK_FI2C(idx, ch) \
UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c", 0x24, 24 + (ch))
#define UNIPHIER_PERI_CLK_SCSSI(idx, ch) \
UNIPHIER_CLK_GATE("scssi" #ch, (idx), "spi", 0x20, 17 + (ch))
#define UNIPHIER_PERI_CLK_MCSSI(idx) \
UNIPHIER_CLK_GATE("mcssi", (idx), "spi", 0x24, 14)
const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = {
UNIPHIER_PERI_CLK_UART(0, 0),
UNIPHIER_PERI_CLK_UART(1, 1),
UNIPHIER_PERI_CLK_UART(2, 2),
UNIPHIER_PERI_CLK_UART(3, 3),
UNIPHIER_PERI_CLK_I2C_COMMON,
UNIPHIER_PERI_CLK_I2C(4, 0),
UNIPHIER_PERI_CLK_I2C(5, 1),
UNIPHIER_PERI_CLK_I2C(6, 2),
UNIPHIER_PERI_CLK_I2C(7, 3),
UNIPHIER_PERI_CLK_I2C(8, 4),
UNIPHIER_PERI_CLK_SCSSI(11, 0),
{ /* sentinel */ }
};
const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = {
UNIPHIER_PERI_CLK_UART(0, 0),
UNIPHIER_PERI_CLK_UART(1, 1),
UNIPHIER_PERI_CLK_UART(2, 2),
UNIPHIER_PERI_CLK_UART(3, 3),
UNIPHIER_PERI_CLK_FI2C(4, 0),
UNIPHIER_PERI_CLK_FI2C(5, 1),
UNIPHIER_PERI_CLK_FI2C(6, 2),
UNIPHIER_PERI_CLK_FI2C(7, 3),
UNIPHIER_PERI_CLK_FI2C(8, 4),
UNIPHIER_PERI_CLK_FI2C(9, 5),
UNIPHIER_PERI_CLK_FI2C(10, 6),
UNIPHIER_PERI_CLK_SCSSI(11, 0),
UNIPHIER_PERI_CLK_SCSSI(12, 1),
UNIPHIER_PERI_CLK_SCSSI(13, 2),
UNIPHIER_PERI_CLK_SCSSI(14, 3),
UNIPHIER_PERI_CLK_MCSSI(15),
{ /* sentinel */ }
};
| linux-master | drivers/clk/uniphier/clk-uniphier-peri.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <[email protected]>
*/
#include <linux/stddef.h>
#include "clk-uniphier.h"
#define UNIPHIER_LD4_SYS_CLK_SD \
UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
#define UNIPHIER_PRO5_SYS_CLK_SD \
UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
#define UNIPHIER_LD20_SYS_CLK_SD \
UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
#define UNIPHIER_NX1_SYS_CLK_SD \
UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
#define UNIPHIER_LD4_SYS_CLK_NAND(idx) \
UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
#define UNIPHIER_PRO5_SYS_CLK_NAND(idx) \
UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
#define UNIPHIER_LD11_SYS_CLK_NAND(idx) \
UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
#define UNIPHIER_SYS_CLK_NAND_4X(idx) \
UNIPHIER_CLK_FACTOR("nand-4x", (idx), "nand", 4, 1)
#define UNIPHIER_LD11_SYS_CLK_EMMC(idx) \
UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
#define UNIPHIER_LD4_SYS_CLK_STDMAC(idx) \
UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
#define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \
UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
#define UNIPHIER_LD11_SYS_CLK_HSC(idx) \
UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9)
#define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \
UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
#define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \
UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
#define UNIPHIER_PRO4_SYS_CLK_AIO(idx) \
UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 8), \
UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
#define UNIPHIER_PRO5_SYS_CLK_AIO(idx) \
UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 12), \
UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
#define UNIPHIER_LD11_SYS_CLK_AIO(idx) \
UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10), \
UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
#define UNIPHIER_LD11_SYS_CLK_EVEA(idx) \
UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \
UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
#define UNIPHIER_LD11_SYS_CLK_EXIV(idx) \
UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \
UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
#define UNIPHIER_PRO4_SYS_CLK_ETHER(idx) \
UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12)
#define UNIPHIER_LD11_SYS_CLK_ETHER(idx) \
UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x210c, 6)
const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
UNIPHIER_LD4_SYS_CLK_NAND(2),
UNIPHIER_SYS_CLK_NAND_4X(3),
UNIPHIER_LD4_SYS_CLK_SD,
UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
{ /* sentinel */ }
};
const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
UNIPHIER_CLK_FACTOR("spi", 1, "spll", 1, 32),
UNIPHIER_LD4_SYS_CLK_NAND(2),
UNIPHIER_SYS_CLK_NAND_4X(3),
UNIPHIER_LD4_SYS_CLK_SD,
UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
UNIPHIER_PRO4_SYS_CLK_ETHER(6),
UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5),
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */
UNIPHIER_CLK_GATE("ether-phy", 10, "ref", 0x2260, 0),
UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */
UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
UNIPHIER_CLK_FACTOR("usb30-hsphy0", 16, "upll", 1, 12),
UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1),
UNIPHIER_CLK_FACTOR("usb31-ssphy0", 20, "ref", 1, 1),
UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 18),
UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x2104, 19),
UNIPHIER_PRO4_SYS_CLK_AIO(40),
{ /* sentinel */ }
};
const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
UNIPHIER_LD4_SYS_CLK_NAND(2),
UNIPHIER_SYS_CLK_NAND_4X(3),
UNIPHIER_LD4_SYS_CLK_SD,
UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
{ /* sentinel */ }
};
const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */
UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */
UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */
UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
UNIPHIER_PRO5_SYS_CLK_NAND(2),
UNIPHIER_SYS_CLK_NAND_4X(3),
UNIPHIER_PRO5_SYS_CLK_SD,
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC */
UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */
UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x2108, 2),
UNIPHIER_PRO5_SYS_CLK_AIO(40),
{ /* sentinel */ }
};
const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
UNIPHIER_PRO5_SYS_CLK_NAND(2),
UNIPHIER_SYS_CLK_NAND_4X(3),
UNIPHIER_PRO5_SYS_CLK_SD,
UNIPHIER_PRO4_SYS_CLK_ETHER(6),
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, RLE */
/* GIO is always clock-enabled: no function for 0x2104 bit6 */
UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
/* The document mentions 0x2104 bit 18, but not functional */
UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x2104, 19),
UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1),
UNIPHIER_CLK_FACTOR("usb30-ssphy1", 18, "ref", 1, 1),
UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x2104, 20),
UNIPHIER_CLK_FACTOR("usb31-ssphy0", 21, "ref", 1, 1),
UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 22),
UNIPHIER_PRO5_SYS_CLK_AIO(40),
{ /* sentinel */ }
};
const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 392, 5), /* 1960 MHz */
UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* 1600 MHz */
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1), /* 2000 MHz */
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
UNIPHIER_LD11_SYS_CLK_NAND(2),
UNIPHIER_SYS_CLK_NAND_4X(3),
UNIPHIER_LD11_SYS_CLK_EMMC(4),
/* Index 5 reserved for eMMC PHY */
UNIPHIER_LD11_SYS_CLK_ETHER(6),
UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */
UNIPHIER_LD11_SYS_CLK_HSC(9),
UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
UNIPHIER_LD11_SYS_CLK_AIO(40),
UNIPHIER_LD11_SYS_CLK_EVEA(41),
UNIPHIER_LD11_SYS_CLK_EXIV(42),
/* CPU gears */
UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV3("spll", 3, 4, 8),
/* Note: both gear1 and gear4 are spll/4. This is not a bug. */
UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
"cpll/2", "spll/4", "cpll/3", "spll/3",
"spll/4", "spll/8", "cpll/4", "cpll/8"),
UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
"mpll/2", "spll/4", "mpll/3", "spll/3",
"spll/4", "spll/8", "mpll/4", "mpll/8"),
{ /* sentinel */ }
};
const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 88, 1), /* ARM: 2200 MHz */
UNIPHIER_CLK_FACTOR("gppll", -1, "ref", 52, 1), /* Mali: 1300 MHz */
UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* Codec: 1600 MHz */
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2200 MHz */
UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5), /* 2520 MHz */
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
UNIPHIER_LD11_SYS_CLK_NAND(2),
UNIPHIER_SYS_CLK_NAND_4X(3),
UNIPHIER_LD11_SYS_CLK_EMMC(4),
/* Index 5 reserved for eMMC PHY */
UNIPHIER_LD20_SYS_CLK_SD,
UNIPHIER_LD11_SYS_CLK_ETHER(6),
UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */
UNIPHIER_LD11_SYS_CLK_HSC(9),
/* GIO is always clock-enabled: no function for 0x210c bit5 */
/*
* clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
* We do not use bit 15 here.
*/
UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 12),
UNIPHIER_CLK_GATE("usb30-hsphy1", 17, NULL, 0x210c, 13),
UNIPHIER_CLK_FACTOR("usb30-ssphy0", 18, "ref", 1, 1),
UNIPHIER_CLK_FACTOR("usb30-ssphy1", 19, "ref", 1, 1),
UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 4),
UNIPHIER_LD11_SYS_CLK_AIO(40),
UNIPHIER_LD11_SYS_CLK_EVEA(41),
UNIPHIER_LD11_SYS_CLK_EXIV(42),
/* CPU gears */
UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8,
"cpll/2", "spll/2", "cpll/3", "spll/3",
"spll/4", "spll/8", "cpll/4", "cpll/8"),
UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
"cpll/2", "spll/2", "cpll/3", "spll/3",
"spll/4", "spll/8", "cpll/4", "cpll/8"),
UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
"s2pll/2", "spll/2", "s2pll/3", "spll/3",
"spll/4", "spll/8", "s2pll/4", "s2pll/8"),
{ /* sentinel */ }
};
const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 104, 1), /* ARM: 2600 MHz */
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2400 MHz */
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
UNIPHIER_LD20_SYS_CLK_SD,
UNIPHIER_LD11_SYS_CLK_NAND(2),
UNIPHIER_SYS_CLK_NAND_4X(3),
UNIPHIER_LD11_SYS_CLK_EMMC(4),
UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9),
UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10),
UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4), /* =GIO0 */
UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5), /* =GIO1 */
UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6), /* =GIO1-1 */
UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 16),
UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 18),
UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 20),
UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x210c, 17),
UNIPHIER_CLK_GATE("usb31-ssphy0", 21, NULL, 0x210c, 19),
UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3),
UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),
UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),
UNIPHIER_LD11_SYS_CLK_AIO(40),
UNIPHIER_LD11_SYS_CLK_EXIV(42),
/* CPU gears */
UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
"cpll/2", "spll/2", "cpll/3", "spll/3",
"spll/4", "spll/8", "cpll/4", "cpll/8"),
UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
"s2pll/2", "spll/2", "s2pll/3", "spll/3",
"spll/4", "spll/8", "s2pll/4", "s2pll/8"),
{ /* sentinel */ }
};
const struct uniphier_clk_data uniphier_nx1_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 100, 1), /* ARM: 2500 MHz */
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 32, 1), /* 800 MHz */
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 6),
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
UNIPHIER_NX1_SYS_CLK_SD,
UNIPHIER_CLK_GATE("emmc", 4, NULL, 0x2108, 8),
UNIPHIER_CLK_GATE("ether", 6, NULL, 0x210c, 0),
UNIPHIER_CLK_GATE("usb30-0", 12, NULL, 0x210c, 16), /* =GIO */
UNIPHIER_CLK_GATE("usb30-1", 13, NULL, 0x210c, 20), /* =GIO1P */
UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 24),
UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 25),
UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 26),
UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 8),
UNIPHIER_CLK_GATE("voc", 52, NULL, 0x2110, 0),
UNIPHIER_CLK_GATE("hdmitx", 58, NULL, 0x2110, 8),
/* CPU gears */
UNIPHIER_CLK_DIV5("cpll", 2, 4, 8, 16, 32),
UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 5,
"cpll/2", "cpll/4", "cpll/8", "cpll/16",
"cpll/32"),
{ /* sentinel */ }
};
const struct uniphier_clk_data uniphier_pro4_sg_clk_data[] = {
UNIPHIER_CLK_DIV("gpll", 4),
{
.name = "sata-ref",
.type = UNIPHIER_CLK_TYPE_MUX,
.idx = 0,
.data.mux = {
.parent_names = { "gpll/4", "ref", },
.num_parents = 2,
.reg = 0x1a28,
.masks = { 0x1, 0x1, },
.vals = { 0x0, 0x1, },
},
},
{ /* sentinel */ }
};
| linux-master | drivers/clk/uniphier/clk-uniphier-sys.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk-uniphier.h"
static struct clk_hw *uniphier_clk_register(struct device *dev,
struct regmap *regmap,
const struct uniphier_clk_data *data)
{
switch (data->type) {
case UNIPHIER_CLK_TYPE_CPUGEAR:
return uniphier_clk_register_cpugear(dev, regmap, data->name,
&data->data.cpugear);
case UNIPHIER_CLK_TYPE_FIXED_FACTOR:
return uniphier_clk_register_fixed_factor(dev, data->name,
&data->data.factor);
case UNIPHIER_CLK_TYPE_FIXED_RATE:
return uniphier_clk_register_fixed_rate(dev, data->name,
&data->data.rate);
case UNIPHIER_CLK_TYPE_GATE:
return uniphier_clk_register_gate(dev, regmap, data->name,
&data->data.gate);
case UNIPHIER_CLK_TYPE_MUX:
return uniphier_clk_register_mux(dev, regmap, data->name,
&data->data.mux);
default:
dev_err(dev, "unsupported clock type\n");
return ERR_PTR(-EINVAL);
}
}
static int uniphier_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct clk_hw_onecell_data *hw_data;
const struct uniphier_clk_data *p, *data;
struct regmap *regmap;
struct device_node *parent;
int clk_num = 0;
data = of_device_get_match_data(dev);
if (WARN_ON(!data))
return -EINVAL;
parent = of_get_parent(dev->of_node); /* parent should be syscon node */
regmap = syscon_node_to_regmap(parent);
of_node_put(parent);
if (IS_ERR(regmap)) {
dev_err(dev, "failed to get regmap (error %ld)\n",
PTR_ERR(regmap));
return PTR_ERR(regmap);
}
for (p = data; p->name; p++)
clk_num = max(clk_num, p->idx + 1);
hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, clk_num),
GFP_KERNEL);
if (!hw_data)
return -ENOMEM;
hw_data->num = clk_num;
/* avoid returning NULL for unused idx */
while (--clk_num >= 0)
hw_data->hws[clk_num] = ERR_PTR(-EINVAL);
for (p = data; p->name; p++) {
struct clk_hw *hw;
dev_dbg(dev, "register %s (index=%d)\n", p->name, p->idx);
hw = uniphier_clk_register(dev, regmap, p);
if (WARN(IS_ERR(hw), "failed to register %s", p->name))
continue;
if (p->idx >= 0)
hw_data->hws[p->idx] = hw;
}
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
hw_data);
}
static const struct of_device_id uniphier_clk_match[] = {
/* System clock */
{
.compatible = "socionext,uniphier-ld4-clock",
.data = uniphier_ld4_sys_clk_data,
},
{
.compatible = "socionext,uniphier-pro4-clock",
.data = uniphier_pro4_sys_clk_data,
},
{
.compatible = "socionext,uniphier-sld8-clock",
.data = uniphier_sld8_sys_clk_data,
},
{
.compatible = "socionext,uniphier-pro5-clock",
.data = uniphier_pro5_sys_clk_data,
},
{
.compatible = "socionext,uniphier-pxs2-clock",
.data = uniphier_pxs2_sys_clk_data,
},
{
.compatible = "socionext,uniphier-ld11-clock",
.data = uniphier_ld11_sys_clk_data,
},
{
.compatible = "socionext,uniphier-ld20-clock",
.data = uniphier_ld20_sys_clk_data,
},
{
.compatible = "socionext,uniphier-pxs3-clock",
.data = uniphier_pxs3_sys_clk_data,
},
{
.compatible = "socionext,uniphier-nx1-clock",
.data = uniphier_nx1_sys_clk_data,
},
/* Media I/O clock, SD clock */
{
.compatible = "socionext,uniphier-ld4-mio-clock",
.data = uniphier_ld4_mio_clk_data,
},
{
.compatible = "socionext,uniphier-pro4-mio-clock",
.data = uniphier_ld4_mio_clk_data,
},
{
.compatible = "socionext,uniphier-sld8-mio-clock",
.data = uniphier_ld4_mio_clk_data,
},
{
.compatible = "socionext,uniphier-pro5-sd-clock",
.data = uniphier_pro5_sd_clk_data,
},
{
.compatible = "socionext,uniphier-pxs2-sd-clock",
.data = uniphier_pro5_sd_clk_data,
},
{
.compatible = "socionext,uniphier-ld11-mio-clock",
.data = uniphier_ld4_mio_clk_data,
},
{
.compatible = "socionext,uniphier-ld20-sd-clock",
.data = uniphier_pro5_sd_clk_data,
},
{
.compatible = "socionext,uniphier-pxs3-sd-clock",
.data = uniphier_pro5_sd_clk_data,
},
{
.compatible = "socionext,uniphier-nx1-sd-clock",
.data = uniphier_pro5_sd_clk_data,
},
/* Peripheral clock */
{
.compatible = "socionext,uniphier-ld4-peri-clock",
.data = uniphier_ld4_peri_clk_data,
},
{
.compatible = "socionext,uniphier-pro4-peri-clock",
.data = uniphier_pro4_peri_clk_data,
},
{
.compatible = "socionext,uniphier-sld8-peri-clock",
.data = uniphier_ld4_peri_clk_data,
},
{
.compatible = "socionext,uniphier-pro5-peri-clock",
.data = uniphier_pro4_peri_clk_data,
},
{
.compatible = "socionext,uniphier-pxs2-peri-clock",
.data = uniphier_pro4_peri_clk_data,
},
{
.compatible = "socionext,uniphier-ld11-peri-clock",
.data = uniphier_pro4_peri_clk_data,
},
{
.compatible = "socionext,uniphier-ld20-peri-clock",
.data = uniphier_pro4_peri_clk_data,
},
{
.compatible = "socionext,uniphier-pxs3-peri-clock",
.data = uniphier_pro4_peri_clk_data,
},
{
.compatible = "socionext,uniphier-nx1-peri-clock",
.data = uniphier_pro4_peri_clk_data,
},
/* SoC-glue clock */
{
.compatible = "socionext,uniphier-pro4-sg-clock",
.data = uniphier_pro4_sg_clk_data,
},
{ /* sentinel */ }
};
static struct platform_driver uniphier_clk_driver = {
.probe = uniphier_clk_probe,
.driver = {
.name = "uniphier-clk",
.of_match_table = uniphier_clk_match,
},
};
builtin_platform_driver(uniphier_clk_driver);
| linux-master | drivers/clk/uniphier/clk-uniphier-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP APLL clock support
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* J Keerthy <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/string.h>
#include <linux/log2.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include <linux/delay.h>
#include "clock.h"
#define APLL_FORCE_LOCK 0x1
#define APLL_AUTO_IDLE 0x2
#define MAX_APLL_WAIT_TRIES 1000000
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
static int dra7_apll_enable(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
int r = 0, i = 0;
struct dpll_data *ad;
const char *clk_name;
u8 state = 1;
u32 v;
ad = clk->dpll_data;
if (!ad)
return -EINVAL;
clk_name = clk_hw_get_name(&clk->hw);
state <<= __ffs(ad->idlest_mask);
/* Check is already locked */
v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
if ((v & ad->idlest_mask) == state)
return r;
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
v &= ~ad->enable_mask;
v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
state <<= __ffs(ad->idlest_mask);
while (1) {
v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
if ((v & ad->idlest_mask) == state)
break;
if (i > MAX_APLL_WAIT_TRIES)
break;
i++;
udelay(1);
}
if (i == MAX_APLL_WAIT_TRIES) {
pr_warn("clock: %s failed transition to '%s'\n",
clk_name, (state) ? "locked" : "bypassed");
r = -EBUSY;
} else
pr_debug("clock: %s transition to '%s' in %d loops\n",
clk_name, (state) ? "locked" : "bypassed", i);
return r;
}
static void dra7_apll_disable(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
struct dpll_data *ad;
u8 state = 1;
u32 v;
ad = clk->dpll_data;
state <<= __ffs(ad->idlest_mask);
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
v &= ~ad->enable_mask;
v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
}
static int dra7_apll_is_enabled(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
struct dpll_data *ad;
u32 v;
ad = clk->dpll_data;
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
v &= ad->enable_mask;
v >>= __ffs(ad->enable_mask);
return v == APLL_AUTO_IDLE ? 0 : 1;
}
static u8 dra7_init_apll_parent(struct clk_hw *hw)
{
return 0;
}
static const struct clk_ops apll_ck_ops = {
.enable = &dra7_apll_enable,
.disable = &dra7_apll_disable,
.is_enabled = &dra7_apll_is_enabled,
.get_parent = &dra7_init_apll_parent,
};
static void __init omap_clk_register_apll(void *user,
struct device_node *node)
{
struct clk_hw *hw = user;
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
struct dpll_data *ad = clk_hw->dpll_data;
const char *name;
struct clk *clk;
const struct clk_init_data *init = clk_hw->hw.init;
clk = of_clk_get(node, 0);
if (IS_ERR(clk)) {
pr_debug("clk-ref for %pOFn not ready, retry\n",
node);
if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
return;
goto cleanup;
}
ad->clk_ref = __clk_get_hw(clk);
clk = of_clk_get(node, 1);
if (IS_ERR(clk)) {
pr_debug("clk-bypass for %pOFn not ready, retry\n",
node);
if (!ti_clk_retry_init(node, hw, omap_clk_register_apll))
return;
goto cleanup;
}
ad->clk_bypass = __clk_get_hw(clk);
name = ti_dt_clk_name(node);
clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
kfree(init->parent_names);
kfree(init);
return;
}
cleanup:
kfree(clk_hw->dpll_data);
kfree(init->parent_names);
kfree(init);
kfree(clk_hw);
}
static void __init of_dra7_apll_setup(struct device_node *node)
{
struct dpll_data *ad = NULL;
struct clk_hw_omap *clk_hw = NULL;
struct clk_init_data *init = NULL;
const char **parent_names = NULL;
int ret;
ad = kzalloc(sizeof(*ad), GFP_KERNEL);
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
init = kzalloc(sizeof(*init), GFP_KERNEL);
if (!ad || !clk_hw || !init)
goto cleanup;
clk_hw->dpll_data = ad;
clk_hw->hw.init = init;
init->name = ti_dt_clk_name(node);
init->ops = &apll_ck_ops;
init->num_parents = of_clk_get_parent_count(node);
if (init->num_parents < 1) {
pr_err("dra7 apll %pOFn must have parent(s)\n", node);
goto cleanup;
}
parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);
if (!parent_names)
goto cleanup;
of_clk_parent_fill(node, parent_names, init->num_parents);
init->parent_names = parent_names;
ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);
ret |= ti_clk_get_reg_addr(node, 1, &ad->idlest_reg);
if (ret)
goto cleanup;
ad->idlest_mask = 0x1;
ad->enable_mask = 0x3;
omap_clk_register_apll(&clk_hw->hw, node);
return;
cleanup:
kfree(parent_names);
kfree(ad);
kfree(clk_hw);
kfree(init);
}
CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
#define OMAP2_EN_APLL_LOCKED 0x3
#define OMAP2_EN_APLL_STOPPED 0x0
static int omap2_apll_is_enabled(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
struct dpll_data *ad = clk->dpll_data;
u32 v;
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
v &= ad->enable_mask;
v >>= __ffs(ad->enable_mask);
return v == OMAP2_EN_APLL_LOCKED ? 1 : 0;
}
static unsigned long omap2_apll_recalc(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
if (omap2_apll_is_enabled(hw))
return clk->fixed_rate;
return 0;
}
static int omap2_apll_enable(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
struct dpll_data *ad = clk->dpll_data;
u32 v;
int i = 0;
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
v &= ~ad->enable_mask;
v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask);
ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
while (1) {
v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
if (v & ad->idlest_mask)
break;
if (i > MAX_APLL_WAIT_TRIES)
break;
i++;
udelay(1);
}
if (i == MAX_APLL_WAIT_TRIES) {
pr_warn("%s failed to transition to locked\n",
clk_hw_get_name(&clk->hw));
return -EBUSY;
}
return 0;
}
static void omap2_apll_disable(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
struct dpll_data *ad = clk->dpll_data;
u32 v;
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
v &= ~ad->enable_mask;
v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask);
ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
}
static const struct clk_ops omap2_apll_ops = {
.enable = &omap2_apll_enable,
.disable = &omap2_apll_disable,
.is_enabled = &omap2_apll_is_enabled,
.recalc_rate = &omap2_apll_recalc,
};
static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val)
{
struct dpll_data *ad = clk->dpll_data;
u32 v;
v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg);
v &= ~ad->autoidle_mask;
v |= val << __ffs(ad->autoidle_mask);
ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
}
#define OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
#define OMAP2_APLL_AUTOIDLE_DISABLE 0x0
static void omap2_apll_allow_idle(struct clk_hw_omap *clk)
{
omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP);
}
static void omap2_apll_deny_idle(struct clk_hw_omap *clk)
{
omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_DISABLE);
}
static const struct clk_hw_omap_ops omap2_apll_hwops = {
.allow_idle = &omap2_apll_allow_idle,
.deny_idle = &omap2_apll_deny_idle,
};
static void __init of_omap2_apll_setup(struct device_node *node)
{
struct dpll_data *ad = NULL;
struct clk_hw_omap *clk_hw = NULL;
struct clk_init_data *init = NULL;
const char *name;
struct clk *clk;
const char *parent_name;
u32 val;
int ret;
ad = kzalloc(sizeof(*ad), GFP_KERNEL);
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
init = kzalloc(sizeof(*init), GFP_KERNEL);
if (!ad || !clk_hw || !init)
goto cleanup;
clk_hw->dpll_data = ad;
clk_hw->hw.init = init;
init->ops = &omap2_apll_ops;
name = ti_dt_clk_name(node);
init->name = name;
clk_hw->ops = &omap2_apll_hwops;
init->num_parents = of_clk_get_parent_count(node);
if (init->num_parents != 1) {
pr_err("%pOFn must have one parent\n", node);
goto cleanup;
}
parent_name = of_clk_get_parent_name(node, 0);
init->parent_names = &parent_name;
if (of_property_read_u32(node, "ti,clock-frequency", &val)) {
pr_err("%pOFn missing clock-frequency\n", node);
goto cleanup;
}
clk_hw->fixed_rate = val;
if (of_property_read_u32(node, "ti,bit-shift", &val)) {
pr_err("%pOFn missing bit-shift\n", node);
goto cleanup;
}
clk_hw->enable_bit = val;
ad->enable_mask = 0x3 << val;
ad->autoidle_mask = 0x3 << val;
if (of_property_read_u32(node, "ti,idlest-shift", &val)) {
pr_err("%pOFn missing idlest-shift\n", node);
goto cleanup;
}
ad->idlest_mask = 1 << val;
ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);
ret |= ti_clk_get_reg_addr(node, 1, &ad->autoidle_reg);
ret |= ti_clk_get_reg_addr(node, 2, &ad->idlest_reg);
if (ret)
goto cleanup;
name = ti_dt_clk_name(node);
clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
kfree(init);
return;
}
cleanup:
kfree(ad);
kfree(clk_hw);
kfree(init);
}
CLK_OF_DECLARE(omap2_apll_clock, "ti,omap2-apll-clock",
of_omap2_apll_setup);
| linux-master | drivers/clk/ti/apll.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP5 Clock init
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo ([email protected])
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/clk/ti.h>
#include <dt-bindings/clock/omap5.h>
#include "clock.h"
#define OMAP5_DPLL_ABE_DEFFREQ 98304000
/*
* OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
* states it must be at 960MHz
*/
#define OMAP5_DPLL_USB_DEFFREQ 960000000
static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = {
{ OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
{ OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h11x2_ck" },
{ 0 },
};
static const char * const omap5_aess_fclk_parents[] __initconst = {
"abe_clk",
NULL,
};
static const struct omap_clkctrl_div_data omap5_aess_fclk_data __initconst = {
.max_div = 2,
};
static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = {
{ 24, TI_CLK_DIVIDER, omap5_aess_fclk_parents, &omap5_aess_fclk_data },
{ 0 },
};
static const char * const omap5_dmic_gfclk_parents[] __initconst = {
"abe-clkctrl:0018:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
"abe_24m_fclk",
"dss_syc_gfclk_div",
"func_24m_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
"abe-clkctrl:0028:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
"abe-clkctrl:0030:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
"abe-clkctrl:0038:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = {
"dss_syc_gfclk_div",
"sys_32k_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
{ OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
{ OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
{ OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
{ OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
{ OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
{ OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
{ OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
{ OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
{ OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = {
{ OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = {
{ OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ OMAP5_L3_MAIN_2_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = {
{ OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = {
{ OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = {
{ OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
{ OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = {
{ OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" },
{ OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" },
{ OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = {
{ OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ 0 },
};
static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = {
"sys_clkin",
"sys_32k_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const char * const omap5_gpio2_dbclk_parents[] __initconst = {
"sys_32k_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
{ OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
{ OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
{ OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
{ OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
{ OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
{ OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0030:24" },
{ OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" },
{ OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ 0 },
};
static const struct
omap_clkctrl_reg_data omap5_l4_secure_clkctrl_regs[] __initconst = {
{ OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
{ OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
{ OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = {
{ OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
{ OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
{ 0 },
};
static const char * const omap5_dss_dss_clk_parents[] __initconst = {
"dpll_per_h12x2_ck",
NULL,
};
static const char * const omap5_dss_48mhz_clk_parents[] __initconst = {
"func_48m_fclk",
NULL,
};
static const char * const omap5_dss_sys_clk_parents[] __initconst = {
"dss_syc_gfclk_div",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
{ 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
{ 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
{ 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
{ OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
{ 0 },
};
static const char * const omap5_gpu_core_mux_parents[] __initconst = {
"dpll_core_h14x2_ck",
"dpll_per_h14x2_ck",
NULL,
};
static const char * const omap5_gpu_hyd_mux_parents[] __initconst = {
"dpll_core_h14x2_ck",
"dpll_per_h14x2_ck",
NULL,
};
static const char * const omap5_gpu_sys_clk_parents[] __initconst = {
"sys_clkin",
NULL,
};
static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = {
.max_div = 2,
};
static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
{ 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
{ 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24" },
{ 0 },
};
static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
"func_128m_clk",
"dpll_per_m2x2_ck",
NULL,
};
static const char * const omap5_mmc1_fclk_parents[] __initconst = {
"l3init-clkctrl:0008:24",
NULL,
};
static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = {
.max_div = 2,
};
static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data },
{ 0 },
};
static const char * const omap5_mmc2_fclk_parents[] __initconst = {
"l3init-clkctrl:0010:24",
NULL,
};
static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = {
.max_div = 2,
};
static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data },
{ 0 },
};
static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = {
"l3init_60m_fclk",
NULL,
};
static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = {
"dpll_usb_m2_ck",
NULL,
};
static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
"l3init-clkctrl:0038:24",
NULL,
};
static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
"l3init-clkctrl:0038:25",
NULL,
};
static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = {
"l3init_60m_fclk",
"xclk60mhsp1_ck",
NULL,
};
static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = {
"l3init_60m_fclk",
"xclk60mhsp2_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = {
{ 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
{ 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
{ 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
{ 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
{ 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
{ 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
{ 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 0 },
};
static const char * const omap5_sata_ref_clk_parents[] __initconst = {
"sys_clkin",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
{ 0 },
};
static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = {
"dpll_usb_clkdcoldo",
NULL,
};
static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
{ OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
{ OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
{ OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
{ OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = {
{ OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
{ OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
{ OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ 0 },
};
const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
{ 0x4a004320, omap5_mpu_clkctrl_regs },
{ 0x4a004420, omap5_dsp_clkctrl_regs },
{ 0x4a004520, omap5_abe_clkctrl_regs },
{ 0x4a008720, omap5_l3main1_clkctrl_regs },
{ 0x4a008820, omap5_l3main2_clkctrl_regs },
{ 0x4a008920, omap5_ipu_clkctrl_regs },
{ 0x4a008a20, omap5_dma_clkctrl_regs },
{ 0x4a008b20, omap5_emif_clkctrl_regs },
{ 0x4a008d20, omap5_l4cfg_clkctrl_regs },
{ 0x4a008e20, omap5_l3instr_clkctrl_regs },
{ 0x4a009020, omap5_l4per_clkctrl_regs },
{ 0x4a0091a0, omap5_l4_secure_clkctrl_regs },
{ 0x4a009220, omap5_iva_clkctrl_regs },
{ 0x4a009420, omap5_dss_clkctrl_regs },
{ 0x4a009520, omap5_gpu_clkctrl_regs },
{ 0x4a009620, omap5_l3init_clkctrl_regs },
{ 0x4ae07920, omap5_wkupaon_clkctrl_regs },
{ 0 },
};
static struct ti_dt_clk omap54xx_clks[] = {
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
DT_CLK(NULL, "dmic_gfclk", "abe-clkctrl:0018:24"),
DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
DT_CLK(NULL, "dss_sys_clk", "dss-clkctrl:0000:10"),
DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0040:8"),
DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0048:8"),
DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0050:8"),
DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0058:8"),
DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0060:8"),
DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00f0:8"),
DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f8:8"),
DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"),
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"),
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"),
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
DT_CLK(NULL, "mmc1_32khz_clk", "l3init-clkctrl:0008:8"),
DT_CLK(NULL, "mmc1_fclk", "l3init-clkctrl:0008:25"),
DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
DT_CLK(NULL, "mmc2_fclk", "l3init-clkctrl:0010:25"),
DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"),
DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"),
DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0018:24"),
DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0020:24"),
DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0028:24"),
DT_CLK(NULL, "timer5_gfclk_mux", "abe-clkctrl:0048:24"),
DT_CLK(NULL, "timer6_gfclk_mux", "abe-clkctrl:0050:24"),
DT_CLK(NULL, "timer7_gfclk_mux", "abe-clkctrl:0058:24"),
DT_CLK(NULL, "timer8_gfclk_mux", "abe-clkctrl:0060:24"),
DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0030:24"),
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init-clkctrl:0038:13"),
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init-clkctrl:0038:14"),
DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init-clkctrl:0038:7"),
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init-clkctrl:0038:11"),
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init-clkctrl:0038:12"),
DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init-clkctrl:0038:6"),
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init-clkctrl:0038:8"),
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init-clkctrl:0038:9"),
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init-clkctrl:0038:10"),
DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init-clkctrl:00d0:8"),
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init-clkctrl:0048:8"),
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init-clkctrl:0048:9"),
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init-clkctrl:0048:10"),
DT_CLK(NULL, "utmi_p1_gfclk", "l3init-clkctrl:0038:24"),
DT_CLK(NULL, "utmi_p2_gfclk", "l3init-clkctrl:0038:25"),
{ .node_name = NULL },
};
int __init omap5xxx_dt_clk_init(void)
{
int rc;
struct clk *abe_dpll_ref, *abe_dpll, *abe_dpll_byp, *sys_32k_ck, *usb_dpll;
ti_dt_clocks_register(omap54xx_clks);
omap2_clk_disable_autoidle_all();
ti_clk_add_aliases();
abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
/*
* This must also be set to sys_32k_ck to match or
* the ABE DPLL will not lock on a warm reboot when
* ABE timers are used.
*/
abe_dpll_byp = clk_get_sys(NULL, "abe_dpll_bypass_clk_mux");
if (!rc)
rc = clk_set_parent(abe_dpll_byp, sys_32k_ck);
abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
if (!rc)
rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
if (!rc)
rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2);
if (rc)
pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__);
usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
if (rc)
pr_err("%s: failed to configure USB DPLL!\n", __func__);
usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
if (rc)
pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
return 0;
}
| linux-master | drivers/clk/ti/clk-54xx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP interface clock support
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
static const struct clk_ops ti_interface_clk_ops = {
.init = &omap2_init_clk_clkdm,
.enable = &omap2_dflt_clk_enable,
.disable = &omap2_dflt_clk_disable,
.is_enabled = &omap2_dflt_clk_is_enabled,
};
static struct clk *_register_interface(struct device_node *node,
const char *name,
const char *parent_name,
struct clk_omap_reg *reg, u8 bit_idx,
const struct clk_hw_omap_ops *ops)
{
struct clk_init_data init = { NULL };
struct clk_hw_omap *clk_hw;
struct clk *clk;
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
if (!clk_hw)
return ERR_PTR(-ENOMEM);
clk_hw->hw.init = &init;
clk_hw->ops = ops;
memcpy(&clk_hw->enable_reg, reg, sizeof(*reg));
clk_hw->enable_bit = bit_idx;
init.name = name;
init.ops = &ti_interface_clk_ops;
init.flags = 0;
init.num_parents = 1;
init.parent_names = &parent_name;
clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
if (IS_ERR(clk))
kfree(clk_hw);
return clk;
}
static void __init _of_ti_interface_clk_setup(struct device_node *node,
const struct clk_hw_omap_ops *ops)
{
struct clk *clk;
const char *parent_name;
struct clk_omap_reg reg;
u8 enable_bit = 0;
const char *name;
u32 val;
if (ti_clk_get_reg_addr(node, 0, ®))
return;
if (!of_property_read_u32(node, "ti,bit-shift", &val))
enable_bit = val;
parent_name = of_clk_get_parent_name(node, 0);
if (!parent_name) {
pr_err("%pOFn must have a parent\n", node);
return;
}
name = ti_dt_clk_name(node);
clk = _register_interface(node, name, parent_name, ®,
enable_bit, ops);
if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk);
}
static void __init of_ti_interface_clk_setup(struct device_node *node)
{
_of_ti_interface_clk_setup(node, &clkhwops_iclk_wait);
}
CLK_OF_DECLARE(ti_interface_clk, "ti,omap3-interface-clock",
of_ti_interface_clk_setup);
static void __init of_ti_no_wait_interface_clk_setup(struct device_node *node)
{
_of_ti_interface_clk_setup(node, &clkhwops_iclk);
}
CLK_OF_DECLARE(ti_no_wait_interface_clk, "ti,omap3-no-wait-interface-clock",
of_ti_no_wait_interface_clk_setup);
#ifdef CONFIG_ARCH_OMAP3
static void __init of_ti_hsotgusb_interface_clk_setup(struct device_node *node)
{
_of_ti_interface_clk_setup(node,
&clkhwops_omap3430es2_iclk_hsotgusb_wait);
}
CLK_OF_DECLARE(ti_hsotgusb_interface_clk, "ti,omap3-hsotgusb-interface-clock",
of_ti_hsotgusb_interface_clk_setup);
static void __init of_ti_dss_interface_clk_setup(struct device_node *node)
{
_of_ti_interface_clk_setup(node,
&clkhwops_omap3430es2_iclk_dss_usbhost_wait);
}
CLK_OF_DECLARE(ti_dss_interface_clk, "ti,omap3-dss-interface-clock",
of_ti_dss_interface_clk_setup);
static void __init of_ti_ssi_interface_clk_setup(struct device_node *node)
{
_of_ti_interface_clk_setup(node, &clkhwops_omap3430es2_iclk_ssi_wait);
}
CLK_OF_DECLARE(ti_ssi_interface_clk, "ti,omap3-ssi-interface-clock",
of_ti_ssi_interface_clk_setup);
static void __init of_ti_am35xx_interface_clk_setup(struct device_node *node)
{
_of_ti_interface_clk_setup(node, &clkhwops_am35xx_ipss_wait);
}
CLK_OF_DECLARE(ti_am35xx_interface_clk, "ti,am35xx-interface-clock",
of_ti_am35xx_interface_clk_setup);
#endif
#ifdef CONFIG_SOC_OMAP2430
static void __init of_ti_omap2430_interface_clk_setup(struct device_node *node)
{
_of_ti_interface_clk_setup(node, &clkhwops_omap2430_i2chs_wait);
}
CLK_OF_DECLARE(ti_omap2430_interface_clk, "ti,omap2430-interface-clock",
of_ti_omap2430_interface_clk_setup);
#endif
| linux-master | drivers/clk/ti/interface.c |
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/string.h>
#define ADPLL_PLLSS_MMR_LOCK_OFFSET 0x00 /* Managed by MPPULL */
#define ADPLL_PLLSS_MMR_LOCK_ENABLED 0x1f125B64
#define ADPLL_PLLSS_MMR_UNLOCK_MAGIC 0x1eda4c3d
#define ADPLL_PWRCTRL_OFFSET 0x00
#define ADPLL_PWRCTRL_PONIN 5
#define ADPLL_PWRCTRL_PGOODIN 4
#define ADPLL_PWRCTRL_RET 3
#define ADPLL_PWRCTRL_ISORET 2
#define ADPLL_PWRCTRL_ISOSCAN 1
#define ADPLL_PWRCTRL_OFFMODE 0
#define ADPLL_CLKCTRL_OFFSET 0x04
#define ADPLL_CLKCTRL_CLKDCOLDOEN 29
#define ADPLL_CLKCTRL_IDLE 23
#define ADPLL_CLKCTRL_CLKOUTEN 20
#define ADPLL_CLKINPHIFSEL_ADPLL_S 19 /* REVISIT: which bit? */
#define ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ 19
#define ADPLL_CLKCTRL_ULOWCLKEN 18
#define ADPLL_CLKCTRL_CLKDCOLDOPWDNZ 17
#define ADPLL_CLKCTRL_M2PWDNZ 16
#define ADPLL_CLKCTRL_M3PWDNZ_ADPLL_S 15
#define ADPLL_CLKCTRL_LOWCURRSTDBY_ADPLL_S 13
#define ADPLL_CLKCTRL_LPMODE_ADPLL_S 12
#define ADPLL_CLKCTRL_REGM4XEN_ADPLL_S 10
#define ADPLL_CLKCTRL_SELFREQDCO_ADPLL_LJ 10
#define ADPLL_CLKCTRL_TINITZ 0
#define ADPLL_TENABLE_OFFSET 0x08
#define ADPLL_TENABLEDIV_OFFSET 0x8c
#define ADPLL_M2NDIV_OFFSET 0x10
#define ADPLL_M2NDIV_M2 16
#define ADPLL_M2NDIV_M2_ADPLL_S_WIDTH 5
#define ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH 7
#define ADPLL_MN2DIV_OFFSET 0x14
#define ADPLL_MN2DIV_N2 16
#define ADPLL_FRACDIV_OFFSET 0x18
#define ADPLL_FRACDIV_REGSD 24
#define ADPLL_FRACDIV_FRACTIONALM 0
#define ADPLL_FRACDIV_FRACTIONALM_MASK 0x3ffff
#define ADPLL_BWCTRL_OFFSET 0x1c
#define ADPLL_BWCTRL_BWCONTROL 1
#define ADPLL_BWCTRL_BW_INCR_DECRZ 0
#define ADPLL_RESERVED_OFFSET 0x20
#define ADPLL_STATUS_OFFSET 0x24
#define ADPLL_STATUS_PONOUT 31
#define ADPLL_STATUS_PGOODOUT 30
#define ADPLL_STATUS_LDOPWDN 29
#define ADPLL_STATUS_RECAL_BSTATUS3 28
#define ADPLL_STATUS_RECAL_OPPIN 27
#define ADPLL_STATUS_PHASELOCK 10
#define ADPLL_STATUS_FREQLOCK 9
#define ADPLL_STATUS_BYPASSACK 8
#define ADPLL_STATUS_LOSSREF 6
#define ADPLL_STATUS_CLKOUTENACK 5
#define ADPLL_STATUS_LOCK2 4
#define ADPLL_STATUS_M2CHANGEACK 3
#define ADPLL_STATUS_HIGHJITTER 1
#define ADPLL_STATUS_BYPASS 0
#define ADPLL_STATUS_PREPARED_MASK (BIT(ADPLL_STATUS_PHASELOCK) | \
BIT(ADPLL_STATUS_FREQLOCK))
#define ADPLL_M3DIV_OFFSET 0x28 /* Only on MPUPLL */
#define ADPLL_M3DIV_M3 0
#define ADPLL_M3DIV_M3_WIDTH 5
#define ADPLL_M3DIV_M3_MASK 0x1f
#define ADPLL_RAMPCTRL_OFFSET 0x2c /* Only on MPUPLL */
#define ADPLL_RAMPCTRL_CLKRAMPLEVEL 19
#define ADPLL_RAMPCTRL_CLKRAMPRATE 16
#define ADPLL_RAMPCTRL_RELOCK_RAMP_EN 0
#define MAX_ADPLL_INPUTS 3
#define MAX_ADPLL_OUTPUTS 4
#define ADPLL_MAX_RETRIES 5
#define to_dco(_hw) container_of(_hw, struct ti_adpll_dco_data, hw)
#define to_adpll(_hw) container_of(_hw, struct ti_adpll_data, dco)
#define to_clkout(_hw) container_of(_hw, struct ti_adpll_clkout_data, hw)
enum ti_adpll_clocks {
TI_ADPLL_DCO,
TI_ADPLL_DCO_GATE,
TI_ADPLL_N2,
TI_ADPLL_M2,
TI_ADPLL_M2_GATE,
TI_ADPLL_BYPASS,
TI_ADPLL_HIF,
TI_ADPLL_DIV2,
TI_ADPLL_CLKOUT,
TI_ADPLL_CLKOUT2,
TI_ADPLL_M3,
};
#define TI_ADPLL_NR_CLOCKS (TI_ADPLL_M3 + 1)
enum ti_adpll_inputs {
TI_ADPLL_CLKINP,
TI_ADPLL_CLKINPULOW,
TI_ADPLL_CLKINPHIF,
};
enum ti_adpll_s_outputs {
TI_ADPLL_S_DCOCLKLDO,
TI_ADPLL_S_CLKOUT,
TI_ADPLL_S_CLKOUTX2,
TI_ADPLL_S_CLKOUTHIF,
};
enum ti_adpll_lj_outputs {
TI_ADPLL_LJ_CLKDCOLDO,
TI_ADPLL_LJ_CLKOUT,
TI_ADPLL_LJ_CLKOUTLDO,
};
struct ti_adpll_platform_data {
const bool is_type_s;
const int nr_max_inputs;
const int nr_max_outputs;
const int output_index;
};
struct ti_adpll_clock {
struct clk *clk;
struct clk_lookup *cl;
void (*unregister)(struct clk *clk);
};
struct ti_adpll_dco_data {
struct clk_hw hw;
};
struct ti_adpll_clkout_data {
struct ti_adpll_data *adpll;
struct clk_gate gate;
struct clk_hw hw;
};
struct ti_adpll_data {
struct device *dev;
const struct ti_adpll_platform_data *c;
struct device_node *np;
unsigned long pa;
void __iomem *iobase;
void __iomem *regs;
spinlock_t lock; /* For ADPLL shared register access */
const char *parent_names[MAX_ADPLL_INPUTS];
struct clk *parent_clocks[MAX_ADPLL_INPUTS];
struct ti_adpll_clock *clocks;
struct clk_onecell_data outputs;
struct ti_adpll_dco_data dco;
};
static const char *ti_adpll_clk_get_name(struct ti_adpll_data *d,
int output_index,
const char *postfix)
{
const char *name;
int err;
if (output_index >= 0) {
err = of_property_read_string_index(d->np,
"clock-output-names",
output_index,
&name);
if (err)
return NULL;
} else {
name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s",
d->pa, postfix);
}
return name;
}
#define ADPLL_MAX_CON_ID 16 /* See MAX_CON_ID */
static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock,
int index, int output_index, const char *name,
void (*unregister)(struct clk *clk))
{
struct clk_lookup *cl;
const char *postfix = NULL;
char con_id[ADPLL_MAX_CON_ID];
d->clocks[index].clk = clock;
d->clocks[index].unregister = unregister;
/* Separate con_id in format "pll040dcoclkldo" to fit MAX_CON_ID */
postfix = strrchr(name, '.');
if (postfix && strlen(postfix) > 1) {
if (strlen(postfix) > ADPLL_MAX_CON_ID)
dev_warn(d->dev, "clock %s con_id lookup may fail\n",
name);
snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1);
cl = clkdev_create(clock, con_id, NULL);
if (!cl)
return -ENOMEM;
d->clocks[index].cl = cl;
} else {
dev_warn(d->dev, "no con_id for clock %s\n", name);
}
if (output_index < 0)
return 0;
d->outputs.clks[output_index] = clock;
d->outputs.clk_num++;
return 0;
}
static int ti_adpll_init_divider(struct ti_adpll_data *d,
enum ti_adpll_clocks index,
int output_index, char *name,
struct clk *parent_clock,
void __iomem *reg,
u8 shift, u8 width,
u8 clk_divider_flags)
{
const char *child_name;
const char *parent_name;
struct clk *clock;
child_name = ti_adpll_clk_get_name(d, output_index, name);
if (!child_name)
return -EINVAL;
parent_name = __clk_get_name(parent_clock);
clock = clk_register_divider(d->dev, child_name, parent_name, 0,
reg, shift, width, clk_divider_flags,
&d->lock);
if (IS_ERR(clock)) {
dev_err(d->dev, "failed to register divider %s: %li\n",
name, PTR_ERR(clock));
return PTR_ERR(clock);
}
return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
clk_unregister_divider);
}
static int ti_adpll_init_mux(struct ti_adpll_data *d,
enum ti_adpll_clocks index,
char *name, struct clk *clk0,
struct clk *clk1,
void __iomem *reg,
u8 shift)
{
const char *child_name;
const char *parents[2];
struct clk *clock;
child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
if (!child_name)
return -ENOMEM;
parents[0] = __clk_get_name(clk0);
parents[1] = __clk_get_name(clk1);
clock = clk_register_mux(d->dev, child_name, parents, 2, 0,
reg, shift, 1, 0, &d->lock);
if (IS_ERR(clock)) {
dev_err(d->dev, "failed to register mux %s: %li\n",
name, PTR_ERR(clock));
return PTR_ERR(clock);
}
return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
clk_unregister_mux);
}
static int ti_adpll_init_gate(struct ti_adpll_data *d,
enum ti_adpll_clocks index,
int output_index, char *name,
struct clk *parent_clock,
void __iomem *reg,
u8 bit_idx,
u8 clk_gate_flags)
{
const char *child_name;
const char *parent_name;
struct clk *clock;
child_name = ti_adpll_clk_get_name(d, output_index, name);
if (!child_name)
return -EINVAL;
parent_name = __clk_get_name(parent_clock);
clock = clk_register_gate(d->dev, child_name, parent_name, 0,
reg, bit_idx, clk_gate_flags,
&d->lock);
if (IS_ERR(clock)) {
dev_err(d->dev, "failed to register gate %s: %li\n",
name, PTR_ERR(clock));
return PTR_ERR(clock);
}
return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
clk_unregister_gate);
}
static int ti_adpll_init_fixed_factor(struct ti_adpll_data *d,
enum ti_adpll_clocks index,
char *name,
struct clk *parent_clock,
unsigned int mult,
unsigned int div)
{
const char *child_name;
const char *parent_name;
struct clk *clock;
child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
if (!child_name)
return -ENOMEM;
parent_name = __clk_get_name(parent_clock);
clock = clk_register_fixed_factor(d->dev, child_name, parent_name,
0, mult, div);
if (IS_ERR(clock))
return PTR_ERR(clock);
return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
clk_unregister);
}
static void ti_adpll_set_idle_bypass(struct ti_adpll_data *d)
{
unsigned long flags;
u32 v;
spin_lock_irqsave(&d->lock, flags);
v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
v |= BIT(ADPLL_CLKCTRL_IDLE);
writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
spin_unlock_irqrestore(&d->lock, flags);
}
static void ti_adpll_clear_idle_bypass(struct ti_adpll_data *d)
{
unsigned long flags;
u32 v;
spin_lock_irqsave(&d->lock, flags);
v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
v &= ~BIT(ADPLL_CLKCTRL_IDLE);
writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
spin_unlock_irqrestore(&d->lock, flags);
}
static bool ti_adpll_clock_is_bypass(struct ti_adpll_data *d)
{
u32 v;
v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
return v & BIT(ADPLL_STATUS_BYPASS);
}
/*
* Locked and bypass are not actually mutually exclusive: if you only care
* about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
* the PLL, resulting in status (FREQLOCK | PHASELOCK | BYPASS) after lock.
*/
static bool ti_adpll_is_locked(struct ti_adpll_data *d)
{
u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
return (v & ADPLL_STATUS_PREPARED_MASK) == ADPLL_STATUS_PREPARED_MASK;
}
static int ti_adpll_wait_lock(struct ti_adpll_data *d)
{
int retries = ADPLL_MAX_RETRIES;
do {
if (ti_adpll_is_locked(d))
return 0;
usleep_range(200, 300);
} while (retries--);
dev_err(d->dev, "pll failed to lock\n");
return -ETIMEDOUT;
}
static int ti_adpll_prepare(struct clk_hw *hw)
{
struct ti_adpll_dco_data *dco = to_dco(hw);
struct ti_adpll_data *d = to_adpll(dco);
ti_adpll_clear_idle_bypass(d);
ti_adpll_wait_lock(d);
return 0;
}
static void ti_adpll_unprepare(struct clk_hw *hw)
{
struct ti_adpll_dco_data *dco = to_dco(hw);
struct ti_adpll_data *d = to_adpll(dco);
ti_adpll_set_idle_bypass(d);
}
static int ti_adpll_is_prepared(struct clk_hw *hw)
{
struct ti_adpll_dco_data *dco = to_dco(hw);
struct ti_adpll_data *d = to_adpll(dco);
return ti_adpll_is_locked(d);
}
/*
* Note that the DCO clock is never subject to bypass: if the PLL is off,
* dcoclk is low.
*/
static unsigned long ti_adpll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ti_adpll_dco_data *dco = to_dco(hw);
struct ti_adpll_data *d = to_adpll(dco);
u32 frac_m, divider, v;
u64 rate;
unsigned long flags;
if (ti_adpll_clock_is_bypass(d))
return 0;
spin_lock_irqsave(&d->lock, flags);
frac_m = readl_relaxed(d->regs + ADPLL_FRACDIV_OFFSET);
frac_m &= ADPLL_FRACDIV_FRACTIONALM_MASK;
rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18;
rate += frac_m;
rate *= parent_rate;
divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18;
spin_unlock_irqrestore(&d->lock, flags);
do_div(rate, divider);
if (d->c->is_type_s) {
v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
if (v & BIT(ADPLL_CLKCTRL_REGM4XEN_ADPLL_S))
rate *= 4;
rate *= 2;
}
return rate;
}
/* PLL parent is always clkinp, bypass only affects the children */
static u8 ti_adpll_get_parent(struct clk_hw *hw)
{
return 0;
}
static const struct clk_ops ti_adpll_ops = {
.prepare = ti_adpll_prepare,
.unprepare = ti_adpll_unprepare,
.is_prepared = ti_adpll_is_prepared,
.recalc_rate = ti_adpll_recalc_rate,
.get_parent = ti_adpll_get_parent,
};
static int ti_adpll_init_dco(struct ti_adpll_data *d)
{
struct clk_init_data init;
struct clk *clock;
const char *postfix;
int width, err;
d->outputs.clks = devm_kcalloc(d->dev,
MAX_ADPLL_OUTPUTS,
sizeof(struct clk *),
GFP_KERNEL);
if (!d->outputs.clks)
return -ENOMEM;
if (d->c->output_index < 0)
postfix = "dco";
else
postfix = NULL;
init.name = ti_adpll_clk_get_name(d, d->c->output_index, postfix);
if (!init.name)
return -EINVAL;
init.parent_names = d->parent_names;
init.num_parents = d->c->nr_max_inputs;
init.ops = &ti_adpll_ops;
init.flags = CLK_GET_RATE_NOCACHE;
d->dco.hw.init = &init;
if (d->c->is_type_s)
width = 5;
else
width = 4;
/* Internal input clock divider N2 */
err = ti_adpll_init_divider(d, TI_ADPLL_N2, -ENODEV, "n2",
d->parent_clocks[TI_ADPLL_CLKINP],
d->regs + ADPLL_MN2DIV_OFFSET,
ADPLL_MN2DIV_N2, width, 0);
if (err)
return err;
clock = devm_clk_register(d->dev, &d->dco.hw);
if (IS_ERR(clock))
return PTR_ERR(clock);
return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index,
init.name, NULL);
}
static int ti_adpll_clkout_enable(struct clk_hw *hw)
{
struct ti_adpll_clkout_data *co = to_clkout(hw);
struct clk_hw *gate_hw = &co->gate.hw;
__clk_hw_set_clk(gate_hw, hw);
return clk_gate_ops.enable(gate_hw);
}
static void ti_adpll_clkout_disable(struct clk_hw *hw)
{
struct ti_adpll_clkout_data *co = to_clkout(hw);
struct clk_hw *gate_hw = &co->gate.hw;
__clk_hw_set_clk(gate_hw, hw);
clk_gate_ops.disable(gate_hw);
}
static int ti_adpll_clkout_is_enabled(struct clk_hw *hw)
{
struct ti_adpll_clkout_data *co = to_clkout(hw);
struct clk_hw *gate_hw = &co->gate.hw;
__clk_hw_set_clk(gate_hw, hw);
return clk_gate_ops.is_enabled(gate_hw);
}
/* Setting PLL bypass puts clkout and clkoutx2 into bypass */
static u8 ti_adpll_clkout_get_parent(struct clk_hw *hw)
{
struct ti_adpll_clkout_data *co = to_clkout(hw);
struct ti_adpll_data *d = co->adpll;
return ti_adpll_clock_is_bypass(d);
}
static int ti_adpll_init_clkout(struct ti_adpll_data *d,
enum ti_adpll_clocks index,
int output_index, int gate_bit,
char *name, struct clk *clk0,
struct clk *clk1)
{
struct ti_adpll_clkout_data *co;
struct clk_init_data init;
struct clk_ops *ops;
const char *parent_names[2];
const char *child_name;
struct clk *clock;
int err;
co = devm_kzalloc(d->dev, sizeof(*co), GFP_KERNEL);
if (!co)
return -ENOMEM;
co->adpll = d;
err = of_property_read_string_index(d->np,
"clock-output-names",
output_index,
&child_name);
if (err)
return err;
ops = devm_kzalloc(d->dev, sizeof(*ops), GFP_KERNEL);
if (!ops)
return -ENOMEM;
init.name = child_name;
init.ops = ops;
init.flags = 0;
co->hw.init = &init;
parent_names[0] = __clk_get_name(clk0);
parent_names[1] = __clk_get_name(clk1);
init.parent_names = parent_names;
init.num_parents = 2;
ops->get_parent = ti_adpll_clkout_get_parent;
ops->determine_rate = __clk_mux_determine_rate;
if (gate_bit) {
co->gate.lock = &d->lock;
co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET;
co->gate.bit_idx = gate_bit;
ops->enable = ti_adpll_clkout_enable;
ops->disable = ti_adpll_clkout_disable;
ops->is_enabled = ti_adpll_clkout_is_enabled;
}
clock = devm_clk_register(d->dev, &co->hw);
if (IS_ERR(clock)) {
dev_err(d->dev, "failed to register output %s: %li\n",
name, PTR_ERR(clock));
return PTR_ERR(clock);
}
return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
NULL);
}
static int ti_adpll_init_children_adpll_s(struct ti_adpll_data *d)
{
int err;
if (!d->c->is_type_s)
return 0;
/* Internal mux, sources from divider N2 or clkinpulow */
err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
d->clocks[TI_ADPLL_N2].clk,
d->parent_clocks[TI_ADPLL_CLKINPULOW],
d->regs + ADPLL_CLKCTRL_OFFSET,
ADPLL_CLKCTRL_ULOWCLKEN);
if (err)
return err;
/* Internal divider M2, sources DCO */
err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, "m2",
d->clocks[TI_ADPLL_DCO].clk,
d->regs + ADPLL_M2NDIV_OFFSET,
ADPLL_M2NDIV_M2,
ADPLL_M2NDIV_M2_ADPLL_S_WIDTH,
CLK_DIVIDER_ONE_BASED);
if (err)
return err;
/* Internal fixed divider, after M2 before clkout */
err = ti_adpll_init_fixed_factor(d, TI_ADPLL_DIV2, "div2",
d->clocks[TI_ADPLL_M2].clk,
1, 2);
if (err)
return err;
/* Output clkout with a mux and gate, sources from div2 or bypass */
err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
ADPLL_CLKCTRL_CLKOUTEN, "clkout",
d->clocks[TI_ADPLL_DIV2].clk,
d->clocks[TI_ADPLL_BYPASS].clk);
if (err)
return err;
/* Output clkoutx2 with a mux and gate, sources from M2 or bypass */
err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT2, TI_ADPLL_S_CLKOUTX2, 0,
"clkout2", d->clocks[TI_ADPLL_M2].clk,
d->clocks[TI_ADPLL_BYPASS].clk);
if (err)
return err;
/* Internal mux, sources from DCO and clkinphif */
if (d->parent_clocks[TI_ADPLL_CLKINPHIF]) {
err = ti_adpll_init_mux(d, TI_ADPLL_HIF, "hif",
d->clocks[TI_ADPLL_DCO].clk,
d->parent_clocks[TI_ADPLL_CLKINPHIF],
d->regs + ADPLL_CLKCTRL_OFFSET,
ADPLL_CLKINPHIFSEL_ADPLL_S);
if (err)
return err;
}
/* Output clkouthif with a divider M3, sources from hif */
err = ti_adpll_init_divider(d, TI_ADPLL_M3, TI_ADPLL_S_CLKOUTHIF, "m3",
d->clocks[TI_ADPLL_HIF].clk,
d->regs + ADPLL_M3DIV_OFFSET,
ADPLL_M3DIV_M3,
ADPLL_M3DIV_M3_WIDTH,
CLK_DIVIDER_ONE_BASED);
if (err)
return err;
/* Output clock dcoclkldo is the DCO */
return 0;
}
static int ti_adpll_init_children_adpll_lj(struct ti_adpll_data *d)
{
int err;
if (d->c->is_type_s)
return 0;
/* Output clkdcoldo, gated output of DCO */
err = ti_adpll_init_gate(d, TI_ADPLL_DCO_GATE, TI_ADPLL_LJ_CLKDCOLDO,
"clkdcoldo", d->clocks[TI_ADPLL_DCO].clk,
d->regs + ADPLL_CLKCTRL_OFFSET,
ADPLL_CLKCTRL_CLKDCOLDOEN, 0);
if (err)
return err;
/* Internal divider M2, sources from DCO */
err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV,
"m2", d->clocks[TI_ADPLL_DCO].clk,
d->regs + ADPLL_M2NDIV_OFFSET,
ADPLL_M2NDIV_M2,
ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH,
CLK_DIVIDER_ONE_BASED);
if (err)
return err;
/* Output clkoutldo, gated output of M2 */
err = ti_adpll_init_gate(d, TI_ADPLL_M2_GATE, TI_ADPLL_LJ_CLKOUTLDO,
"clkoutldo", d->clocks[TI_ADPLL_M2].clk,
d->regs + ADPLL_CLKCTRL_OFFSET,
ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ,
0);
if (err)
return err;
/* Internal mux, sources from divider N2 or clkinpulow */
err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
d->clocks[TI_ADPLL_N2].clk,
d->parent_clocks[TI_ADPLL_CLKINPULOW],
d->regs + ADPLL_CLKCTRL_OFFSET,
ADPLL_CLKCTRL_ULOWCLKEN);
if (err)
return err;
/* Output clkout, sources M2 or bypass */
err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
ADPLL_CLKCTRL_CLKOUTEN, "clkout",
d->clocks[TI_ADPLL_M2].clk,
d->clocks[TI_ADPLL_BYPASS].clk);
if (err)
return err;
return 0;
}
static void ti_adpll_free_resources(struct ti_adpll_data *d)
{
int i;
for (i = TI_ADPLL_M3; i >= 0; i--) {
struct ti_adpll_clock *ac = &d->clocks[i];
if (!ac || IS_ERR_OR_NULL(ac->clk))
continue;
if (ac->cl)
clkdev_drop(ac->cl);
if (ac->unregister)
ac->unregister(ac->clk);
}
}
/* MPU PLL manages the lock register for all PLLs */
static void ti_adpll_unlock_all(void __iomem *reg)
{
u32 v;
v = readl_relaxed(reg);
if (v == ADPLL_PLLSS_MMR_LOCK_ENABLED)
writel_relaxed(ADPLL_PLLSS_MMR_UNLOCK_MAGIC, reg);
}
static int ti_adpll_init_registers(struct ti_adpll_data *d)
{
int register_offset = 0;
if (d->c->is_type_s) {
register_offset = 8;
ti_adpll_unlock_all(d->iobase + ADPLL_PLLSS_MMR_LOCK_OFFSET);
}
d->regs = d->iobase + register_offset + ADPLL_PWRCTRL_OFFSET;
return 0;
}
static int ti_adpll_init_inputs(struct ti_adpll_data *d)
{
static const char error[] = "need at least %i inputs";
struct clk *clock;
int nr_inputs;
nr_inputs = of_clk_get_parent_count(d->np);
if (nr_inputs < d->c->nr_max_inputs) {
dev_err(d->dev, error, nr_inputs);
return -EINVAL;
}
of_clk_parent_fill(d->np, d->parent_names, nr_inputs);
clock = devm_clk_get(d->dev, d->parent_names[0]);
if (IS_ERR(clock)) {
dev_err(d->dev, "could not get clkinp\n");
return PTR_ERR(clock);
}
d->parent_clocks[TI_ADPLL_CLKINP] = clock;
clock = devm_clk_get(d->dev, d->parent_names[1]);
if (IS_ERR(clock)) {
dev_err(d->dev, "could not get clkinpulow clock\n");
return PTR_ERR(clock);
}
d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock;
if (d->c->is_type_s) {
clock = devm_clk_get(d->dev, d->parent_names[2]);
if (IS_ERR(clock)) {
dev_err(d->dev, "could not get clkinphif clock\n");
return PTR_ERR(clock);
}
d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock;
}
return 0;
}
static const struct ti_adpll_platform_data ti_adpll_type_s = {
.is_type_s = true,
.nr_max_inputs = MAX_ADPLL_INPUTS,
.nr_max_outputs = MAX_ADPLL_OUTPUTS,
.output_index = TI_ADPLL_S_DCOCLKLDO,
};
static const struct ti_adpll_platform_data ti_adpll_type_lj = {
.is_type_s = false,
.nr_max_inputs = MAX_ADPLL_INPUTS - 1,
.nr_max_outputs = MAX_ADPLL_OUTPUTS - 1,
.output_index = -EINVAL,
};
static const struct of_device_id ti_adpll_match[] = {
{ .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
{ .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
{},
};
MODULE_DEVICE_TABLE(of, ti_adpll_match);
static int ti_adpll_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct device *dev = &pdev->dev;
const struct of_device_id *match;
const struct ti_adpll_platform_data *pdata;
struct ti_adpll_data *d;
struct resource *res;
int err;
match = of_match_device(ti_adpll_match, dev);
if (match)
pdata = match->data;
else
return -ENODEV;
d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
if (!d)
return -ENOMEM;
d->dev = dev;
d->np = node;
d->c = pdata;
dev_set_drvdata(d->dev, d);
spin_lock_init(&d->lock);
d->iobase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(d->iobase))
return PTR_ERR(d->iobase);
d->pa = res->start;
err = ti_adpll_init_registers(d);
if (err)
return err;
err = ti_adpll_init_inputs(d);
if (err)
return err;
d->clocks = devm_kcalloc(d->dev,
TI_ADPLL_NR_CLOCKS,
sizeof(struct ti_adpll_clock),
GFP_KERNEL);
if (!d->clocks)
return -ENOMEM;
err = ti_adpll_init_dco(d);
if (err) {
dev_err(dev, "could not register dco: %i\n", err);
goto free;
}
err = ti_adpll_init_children_adpll_s(d);
if (err)
goto free;
err = ti_adpll_init_children_adpll_lj(d);
if (err)
goto free;
err = of_clk_add_provider(d->np, of_clk_src_onecell_get, &d->outputs);
if (err)
goto free;
return 0;
free:
WARN_ON(1);
ti_adpll_free_resources(d);
return err;
}
static void ti_adpll_remove(struct platform_device *pdev)
{
struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev);
ti_adpll_free_resources(d);
}
static struct platform_driver ti_adpll_driver = {
.driver = {
.name = "ti-adpll",
.of_match_table = ti_adpll_match,
},
.probe = ti_adpll_probe,
.remove_new = ti_adpll_remove,
};
static int __init ti_adpll_init(void)
{
return platform_driver_register(&ti_adpll_driver);
}
core_initcall(ti_adpll_init);
static void __exit ti_adpll_exit(void)
{
platform_driver_unregister(&ti_adpll_driver);
}
module_exit(ti_adpll_exit);
MODULE_DESCRIPTION("Clock driver for dm814x ADPLL");
MODULE_ALIAS("platform:dm814-adpll-clock");
MODULE_AUTHOR("Tony LIndgren <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/ti/adpll.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AM43XX Clock init
*
* Copyright (C) 2013 Texas Instruments, Inc
* Tero Kristo ([email protected])
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
#include <dt-bindings/clock/am4.h>
#include "clock.h"
static const struct omap_clkctrl_reg_data am4_l3s_tsc_clkctrl_regs[] __initconst = {
{ AM4_L3S_TSC_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
{ 0 },
};
static const char * const am4_synctimer_32kclk_parents[] __initconst = {
"mux_synctimer32k_ck",
NULL,
};
static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_l4_wkup_aon_clkctrl_regs[] __initconst = {
{ AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sys_clkin_ck" },
{ AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4-wkup-aon-clkctrl:0008:8" },
{ 0 },
};
static const char * const am4_gpio0_dbclk_parents[] __initconst = {
"gpio0_dbclk_mux_ck",
NULL,
};
static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
{ AM4_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
{ AM4_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
{ AM4_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
{ AM4_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
{ AM4_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
{ AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
{ AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
{ AM4_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
{ AM4_L4_WKUP_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
{ AM4_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
{ AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
{ AM4_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ick" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_l3_clkctrl_regs[] __initconst = {
{ AM4_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
{ AM4_L3_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
{ 0 },
};
static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
"dpll_per_clkdcoldo",
NULL,
};
static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_l3s_clkctrl_regs[] __initconst = {
{ AM4_L3S_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3S_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM4_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
{ AM4_L3S_ADC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
{ AM4_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
{ AM4_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
{ AM4_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM4_L3S_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
{ AM4_L3S_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk" },
{ AM4_L3S_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_pruss_ocp_clkctrl_regs[] __initconst = {
{ AM4_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "pruss_ocp_gclk" },
{ 0 },
};
static const char * const am4_gpio1_dbclk_parents[] __initconst = {
"clkdiv32k_ick",
NULL,
};
static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_l4ls_clkctrl_regs[] __initconst = {
{ AM4_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
{ AM4_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
{ AM4_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
{ AM4_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM4_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM4_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
{ AM4_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
{ AM4_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
{ AM4_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
{ AM4_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
{ AM4_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
{ AM4_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
{ AM4_L4LS_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
{ AM4_L4LS_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
{ AM4_L4LS_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
{ AM4_L4LS_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
{ AM4_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM4_L4LS_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM4_L4LS_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_emif_clkctrl_regs[] __initconst = {
{ AM4_EMIF_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_dss_clkctrl_regs[] __initconst = {
{ AM4_DSS_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am4_cpsw_125mhz_clkctrl_regs[] __initconst = {
{ AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
{ 0 },
};
const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = {
{ 0x44df2920, am4_l3s_tsc_clkctrl_regs },
{ 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
{ 0x44df2a20, am4_l4_wkup_clkctrl_regs },
{ 0x44df8320, am4_mpu_clkctrl_regs },
{ 0x44df8420, am4_gfx_l3_clkctrl_regs },
{ 0x44df8520, am4_l4_rtc_clkctrl_regs },
{ 0x44df8820, am4_l3_clkctrl_regs },
{ 0x44df8868, am4_l3s_clkctrl_regs },
{ 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
{ 0x44df8c20, am4_l4ls_clkctrl_regs },
{ 0x44df8f20, am4_emif_clkctrl_regs },
{ 0x44df9220, am4_dss_clkctrl_regs },
{ 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
{ 0 },
};
const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = {
{ 0x44df2920, am4_l3s_tsc_clkctrl_regs },
{ 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
{ 0x44df2a20, am4_l4_wkup_clkctrl_regs },
{ 0x44df8320, am4_mpu_clkctrl_regs },
{ 0x44df8420, am4_gfx_l3_clkctrl_regs },
{ 0x44df8820, am4_l3_clkctrl_regs },
{ 0x44df8868, am4_l3s_clkctrl_regs },
{ 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
{ 0x44df8c20, am4_l4ls_clkctrl_regs },
{ 0x44df8f20, am4_emif_clkctrl_regs },
{ 0x44df9220, am4_dss_clkctrl_regs },
{ 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
{ 0 },
};
static struct ti_dt_clk am43xx_clks[] = {
DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0148:8"),
DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0058:8"),
DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0060:8"),
DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:0068:8"),
DT_CLK(NULL, "gpio4_dbclk", "l4ls-clkctrl:0070:8"),
DT_CLK(NULL, "gpio5_dbclk", "l4ls-clkctrl:0078:8"),
DT_CLK(NULL, "synctimer_32kclk", "l4-wkup-aon-clkctrl:0008:8"),
DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l3s-clkctrl:01f8:8"),
DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3s-clkctrl:0200:8"),
{ .node_name = NULL },
};
static const char *enable_init_clks[] = {
/* AM4_L3_L3_MAIN_CLKCTRL, needed during suspend */
"l3-clkctrl:0000:0",
};
int __init am43xx_dt_clk_init(void)
{
struct clk *clk1, *clk2;
ti_dt_clocks_register(am43xx_clks);
omap2_clk_disable_autoidle_all();
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
ti_clk_add_aliases();
/*
* cpsw_cpts_rft_clk has got the choice of 3 clocksources
* dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck.
* By default dpll_core_m4_ck is selected, witn this as clock
* source the CPTS doesnot work properly. It gives clockcheck errors
* while running PTP.
* clockcheck: clock jumped backward or running slower than expected!
* By selecting dpll_core_m5_ck as the clocksource fixes this issue.
* In AM335x dpll_core_m5_ck is the default clocksource.
*/
clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk");
clk2 = clk_get_sys(NULL, "dpll_core_m5_ck");
clk_set_parent(clk1, clk2);
return 0;
}
| linux-master | drivers/clk/ti/clk-43xx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP2/3/4 DPLL clock functions
*
* Copyright (C) 2005-2008 Texas Instruments, Inc.
* Copyright (C) 2004-2010 Nokia Corporation
*
* Contacts:
* Richard Woodruff <[email protected]>
* Paul Walmsley
*/
#undef DEBUG
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/clk/ti.h>
#include <asm/div64.h>
#include "clock.h"
/* DPLL rate rounding: minimum DPLL multiplier, divider values */
#define DPLL_MIN_MULTIPLIER 2
#define DPLL_MIN_DIVIDER 1
/* Possible error results from _dpll_test_mult */
#define DPLL_MULT_UNDERFLOW -1
/*
* Scale factor to mitigate roundoff errors in DPLL rate rounding.
* The higher the scale factor, the greater the risk of arithmetic overflow,
* but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
* must be a power of DPLL_SCALE_BASE.
*/
#define DPLL_SCALE_FACTOR 64
#define DPLL_SCALE_BASE 2
#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
(DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
/*
* DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
* From device data manual section 4.3 "DPLL and DLL Specifications".
*/
#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
/* _dpll_test_fint() return codes */
#define DPLL_FINT_UNDERFLOW -1
#define DPLL_FINT_INVALID -2
/* Private functions */
/*
* _dpll_test_fint - test whether an Fint value is valid for the DPLL
* @clk: DPLL struct clk to test
* @n: divider value (N) to test
*
* Tests whether a particular divider @n will result in a valid DPLL
* internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
* Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
* (assuming that it is counting N upwards), or -2 if the enclosing loop
* should skip to the next iteration (again assuming N is increasing).
*/
static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
{
struct dpll_data *dd;
long fint, fint_min, fint_max;
int ret = 0;
dd = clk->dpll_data;
/* DPLL divider must result in a valid jitter correction val */
fint = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)) / n;
if (dd->flags & DPLL_J_TYPE) {
fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
} else {
fint_min = ti_clk_get_features()->fint_min;
fint_max = ti_clk_get_features()->fint_max;
}
if (!fint_min || !fint_max) {
WARN(1, "No fint limits available!\n");
return DPLL_FINT_INVALID;
}
if (fint < ti_clk_get_features()->fint_min) {
pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
n);
dd->max_divider = n;
ret = DPLL_FINT_UNDERFLOW;
} else if (fint > ti_clk_get_features()->fint_max) {
pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
n);
dd->min_divider = n;
ret = DPLL_FINT_INVALID;
} else if (fint > ti_clk_get_features()->fint_band1_max &&
fint < ti_clk_get_features()->fint_band2_min) {
pr_debug("rejecting n=%d due to Fint failure\n", n);
ret = DPLL_FINT_INVALID;
}
return ret;
}
static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
unsigned int m, unsigned int n)
{
unsigned long long num;
num = (unsigned long long)parent_rate * m;
do_div(num, n);
return num;
}
/*
* _dpll_test_mult - test a DPLL multiplier value
* @m: pointer to the DPLL m (multiplier) value under test
* @n: current DPLL n (divider) value under test
* @new_rate: pointer to storage for the resulting rounded rate
* @target_rate: the desired DPLL rate
* @parent_rate: the DPLL's parent clock rate
*
* This code tests a DPLL multiplier value, ensuring that the
* resulting rate will not be higher than the target_rate, and that
* the multiplier value itself is valid for the DPLL. Initially, the
* integer pointed to by the m argument should be prescaled by
* multiplying by DPLL_SCALE_FACTOR. The code will replace this with
* a non-scaled m upon return. This non-scaled m will result in a
* new_rate as close as possible to target_rate (but not greater than
* target_rate) given the current (parent_rate, n, prescaled m)
* triple. Returns DPLL_MULT_UNDERFLOW in the event that the
* non-scaled m attempted to underflow, which can allow the calling
* function to bail out early; or 0 upon success.
*/
static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
unsigned long target_rate,
unsigned long parent_rate)
{
int r = 0, carry = 0;
/* Unscale m and round if necessary */
if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
carry = 1;
*m = (*m / DPLL_SCALE_FACTOR) + carry;
/*
* The new rate must be <= the target rate to avoid programming
* a rate that is impossible for the hardware to handle
*/
*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
if (*new_rate > target_rate) {
(*m)--;
*new_rate = 0;
}
/* Guard against m underflow */
if (*m < DPLL_MIN_MULTIPLIER) {
*m = DPLL_MIN_MULTIPLIER;
*new_rate = 0;
r = DPLL_MULT_UNDERFLOW;
}
if (*new_rate == 0)
*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
return r;
}
/**
* _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
* @v: bitfield value of the DPLL enable
*
* Checks given DPLL enable bitfield to see whether the DPLL is in bypass
* mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
*/
static int _omap2_dpll_is_in_bypass(u32 v)
{
u8 mask, val;
mask = ti_clk_get_features()->dpll_bypass_vals;
/*
* Each set bit in the mask corresponds to a bypass value equal
* to the bitshift. Go through each set-bit in the mask and
* compare against the given register value.
*/
while (mask) {
val = __ffs(mask);
mask ^= (1 << val);
if (v == val)
return 1;
}
return 0;
}
/* Public functions */
u8 omap2_init_dpll_parent(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
u32 v;
struct dpll_data *dd;
dd = clk->dpll_data;
if (!dd)
return -EINVAL;
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
v &= dd->enable_mask;
v >>= __ffs(dd->enable_mask);
/* Reparent the struct clk in case the dpll is in bypass */
if (_omap2_dpll_is_in_bypass(v))
return 1;
return 0;
}
/**
* omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
* @clk: struct clk * of a DPLL
*
* DPLLs can be locked or bypassed - basically, enabled or disabled.
* When locked, the DPLL output depends on the M and N values. When
* bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
* or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
* 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
* (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
* Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
* locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
* if the clock @clk is not a DPLL.
*/
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
{
u64 dpll_clk;
u32 dpll_mult, dpll_div, v;
struct dpll_data *dd;
dd = clk->dpll_data;
if (!dd)
return 0;
/* Return bypass rate if DPLL is bypassed */
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
v &= dd->enable_mask;
v >>= __ffs(dd->enable_mask);
if (_omap2_dpll_is_in_bypass(v))
return clk_hw_get_rate(dd->clk_bypass);
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
dpll_mult = v & dd->mult_mask;
dpll_mult >>= __ffs(dd->mult_mask);
dpll_div = v & dd->div1_mask;
dpll_div >>= __ffs(dd->div1_mask);
dpll_clk = (u64)clk_hw_get_rate(dd->clk_ref) * dpll_mult;
do_div(dpll_clk, dpll_div + 1);
return dpll_clk;
}
/* DPLL rate rounding code */
/**
* omap2_dpll_round_rate - round a target rate for an OMAP DPLL
* @hw: struct clk_hw containing the struct clk * for a DPLL
* @target_rate: desired DPLL clock rate
* @parent_rate: parent's DPLL clock rate
*
* Given a DPLL and a desired target rate, round the target rate to a
* possible, programmable rate for this DPLL. Attempts to select the
* minimum possible n. Stores the computed (m, n) in the DPLL's
* dpll_data structure so set_rate() will not need to call this
* (expensive) function again. Returns ~0 if the target rate cannot
* be rounded, or the rounded rate upon success.
*/
long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
unsigned long *parent_rate)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
int m, n, r, scaled_max_m;
int min_delta_m = INT_MAX, min_delta_n = INT_MAX;
unsigned long scaled_rt_rp;
unsigned long new_rate = 0;
struct dpll_data *dd;
unsigned long ref_rate;
long delta;
long prev_min_delta = LONG_MAX;
const char *clk_name;
if (!clk || !clk->dpll_data)
return ~0;
dd = clk->dpll_data;
if (dd->max_rate && target_rate > dd->max_rate)
target_rate = dd->max_rate;
ref_rate = clk_hw_get_rate(dd->clk_ref);
clk_name = clk_hw_get_name(hw);
pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
clk_name, target_rate);
scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
dd->last_rounded_rate = 0;
for (n = dd->min_divider; n <= dd->max_divider; n++) {
/* Is the (input clk, divider) pair valid for the DPLL? */
r = _dpll_test_fint(clk, n);
if (r == DPLL_FINT_UNDERFLOW)
break;
else if (r == DPLL_FINT_INVALID)
continue;
/* Compute the scaled DPLL multiplier, based on the divider */
m = scaled_rt_rp * n;
/*
* Since we're counting n up, a m overflow means we
* can bail out completely (since as n increases in
* the next iteration, there's no way that m can
* increase beyond the current m)
*/
if (m > scaled_max_m)
break;
r = _dpll_test_mult(&m, n, &new_rate, target_rate,
ref_rate);
/* m can't be set low enough for this n - try with a larger n */
if (r == DPLL_MULT_UNDERFLOW)
continue;
/* skip rates above our target rate */
delta = target_rate - new_rate;
if (delta < 0)
continue;
if (delta < prev_min_delta) {
prev_min_delta = delta;
min_delta_m = m;
min_delta_n = n;
}
pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
clk_name, m, n, new_rate);
if (delta == 0)
break;
}
if (prev_min_delta == LONG_MAX) {
pr_debug("clock: %s: cannot round to rate %lu\n",
clk_name, target_rate);
return ~0;
}
dd->last_rounded_m = min_delta_m;
dd->last_rounded_n = min_delta_n;
dd->last_rounded_rate = target_rate - prev_min_delta;
return dd->last_rounded_rate;
}
| linux-master | drivers/clk/ti/clkt_dpll.c |
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
#include <dt-bindings/clock/dm816.h>
#include "clock.h"
static const struct omap_clkctrl_reg_data dm816_default_clkctrl_regs[] __initconst = {
{ DM816_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dm816_alwon_clkctrl_regs[] __initconst = {
{ DM816_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM816_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM816_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM816_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ DM816_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ DM816_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM816_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM816_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
{ DM816_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
{ DM816_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
{ DM816_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
{ DM816_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
{ DM816_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
{ DM816_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
{ DM816_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
{ DM816_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM816_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ DM816_SPINBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ DM816_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM816_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ DM816_DAVINCI_MDIO_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },
{ DM816_EMAC1_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },
{ DM816_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk2_ck" },
{ DM816_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
{ DM816_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM816_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM816_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM816_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM816_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ 0 },
};
const struct omap_clkctrl_data dm816_clkctrl_data[] __initconst = {
{ 0x48180500, dm816_default_clkctrl_regs },
{ 0x48181400, dm816_alwon_clkctrl_regs },
{ 0 },
};
static struct ti_dt_clk dm816x_clks[] = {
DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"),
DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"),
{ .node_name = NULL },
};
static const char *enable_init_clks[] = {
"ddr_pll_clk1",
"ddr_pll_clk2",
"ddr_pll_clk3",
"sysclk6_ck",
};
int __init dm816x_dt_clk_init(void)
{
ti_dt_clocks_register(dm816x_clks);
omap2_clk_disable_autoidle_all();
ti_clk_add_aliases();
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
return 0;
}
| linux-master | drivers/clk/ti/clk-816x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP4 Clock init
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo ([email protected])
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk/ti.h>
#include <dt-bindings/clock/omap4.h>
#include "clock.h"
/*
* OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
* "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
* must be set to 196.608 MHz" and hence, the DPLL locked frequency is
* half of this value.
*/
#define OMAP4_DPLL_ABE_DEFFREQ 98304000
/*
* OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
* "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
* locked frequency for the USB DPLL is 960MHz.
*/
#define OMAP4_DPLL_USB_DEFFREQ 960000000
static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst = {
{ OMAP4_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_tesla_clkctrl_regs[] __initconst = {
{ OMAP4_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_m4x2_ck" },
{ 0 },
};
static const char * const omap4_aess_fclk_parents[] __initconst = {
"abe_clk",
NULL,
};
static const struct omap_clkctrl_div_data omap4_aess_fclk_data __initconst = {
.max_div = 2,
};
static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
{ 24, TI_CLK_DIVIDER, omap4_aess_fclk_parents, &omap4_aess_fclk_data },
{ 0 },
};
static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
"abe-clkctrl:0018:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
static const char * const omap4_dmic_sync_mux_ck_parents[] __initconst = {
"abe_24m_fclk",
"syc_clk_div_ck",
"func_24m_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_func_dmic_abe_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
"abe-clkctrl:0020:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_func_mcasp_abe_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
"abe-clkctrl:0028:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_func_mcbsp1_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
"abe-clkctrl:0030:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_func_mcbsp2_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
"abe-clkctrl:0038:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_mcbsp3_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_func_mcbsp3_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap4_slimbus1_fclk_0_parents[] __initconst = {
"abe_24m_fclk",
NULL,
};
static const char * const omap4_slimbus1_fclk_1_parents[] __initconst = {
"func_24m_clk",
NULL,
};
static const char * const omap4_slimbus1_fclk_2_parents[] __initconst = {
"pad_clks_ck",
NULL,
};
static const char * const omap4_slimbus1_slimbus_clk_parents[] __initconst = {
"slimbus_clk",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_slimbus1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_slimbus1_fclk_0_parents, NULL },
{ 9, TI_CLK_GATE, omap4_slimbus1_fclk_1_parents, NULL },
{ 10, TI_CLK_GATE, omap4_slimbus1_fclk_2_parents, NULL },
{ 11, TI_CLK_GATE, omap4_slimbus1_slimbus_clk_parents, NULL },
{ 0 },
};
static const char * const omap4_timer5_sync_mux_parents[] __initconst = {
"syc_clk_div_ck",
"sys_32k_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_timer5_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_timer6_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_timer7_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
{ OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
{ OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
{ OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
{ OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
{ OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe-clkctrl:0020:24" },
{ OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
{ OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
{ OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
{ OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0040:8" },
{ OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
{ OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
{ OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
{ OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
{ OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_l4_ao_clkctrl_regs[] __initconst = {
{ OMAP4_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
{ OMAP4_SMARTREFLEX_IVA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
{ OMAP4_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_l3_1_clkctrl_regs[] __initconst = {
{ OMAP4_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_div_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_l3_2_clkctrl_regs[] __initconst = {
{ OMAP4_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_div_ck" },
{ OMAP4_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
{ OMAP4_OCMC_RAM_CLKCTRL, NULL, 0, "l3_div_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_ducati_clkctrl_regs[] __initconst = {
{ OMAP4_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "ducati_clk_mux_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_l3_dma_clkctrl_regs[] __initconst = {
{ OMAP4_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_div_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_l3_emif_clkctrl_regs[] __initconst = {
{ OMAP4_DMM_CLKCTRL, NULL, 0, "l3_div_ck" },
{ OMAP4_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
{ OMAP4_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_d2d_clkctrl_regs[] __initconst = {
{ OMAP4_C2C_CLKCTRL, NULL, 0, "div_core_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_l4_cfg_clkctrl_regs[] __initconst = {
{ OMAP4_L4_CFG_CLKCTRL, NULL, 0, "l4_div_ck" },
{ OMAP4_SPINLOCK_CLKCTRL, NULL, 0, "l4_div_ck" },
{ OMAP4_MAILBOX_CLKCTRL, NULL, 0, "l4_div_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_l3_instr_clkctrl_regs[] __initconst = {
{ OMAP4_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
{ OMAP4_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
{ OMAP4_OCP_WP_NOC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_ivahd_clkctrl_regs[] __initconst = {
{ OMAP4_IVA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_m5x2_ck" },
{ OMAP4_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
{ 0 },
};
static const char * const omap4_iss_ctrlclk_parents[] __initconst = {
"func_96m_fclk",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_iss_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_iss_ctrlclk_parents, NULL },
{ 0 },
};
static const char * const omap4_fdif_fck_parents[] __initconst = {
"dpll_per_m4x2_ck",
NULL,
};
static const struct omap_clkctrl_div_data omap4_fdif_fck_data __initconst = {
.max_div = 4,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
{ 24, TI_CLK_DIVIDER, omap4_fdif_fck_parents, &omap4_fdif_fck_data },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
{ OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
{ OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss-clkctrl:0008:24" },
{ 0 },
};
static const char * const omap4_dss_dss_clk_parents[] __initconst = {
"dpll_per_m5x2_ck",
NULL,
};
static const char * const omap4_dss_48mhz_clk_parents[] __initconst = {
"func_48mc_fclk",
NULL,
};
static const char * const omap4_dss_sys_clk_parents[] __initconst = {
"syc_clk_div_ck",
NULL,
};
static const char * const omap4_dss_tv_clk_parents[] __initconst = {
"extalt_clkin_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_dss_dss_clk_parents, NULL },
{ 9, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
{ 10, TI_CLK_GATE, omap4_dss_sys_clk_parents, NULL },
{ 11, TI_CLK_GATE, omap4_dss_tv_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
{ OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3-dss-clkctrl:0000:8" },
{ 0 },
};
static const char * const omap4_sgx_clk_mux_parents[] __initconst = {
"dpll_core_m7x2_ck",
"dpll_per_m7x2_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_sgx_clk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
{ OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3-gfx-clkctrl:0000:24" },
{ 0 },
};
static const char * const omap4_hsmmc1_fclk_parents[] __initconst = {
"func_64m_fclk",
"func_96m_fclk",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_mmc1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_mmc2_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
{ 0 },
};
static const char * const omap4_hsi_fck_parents[] __initconst = {
"dpll_per_m2x2_ck",
NULL,
};
static const struct omap_clkctrl_div_data omap4_hsi_fck_data __initconst = {
.max_div = 4,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
{ 24, TI_CLK_DIVIDER, omap4_hsi_fck_parents, &omap4_hsi_fck_data },
{ 0 },
};
static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
"l3-init-clkctrl:0038:24",
NULL,
};
static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
"l3-init-clkctrl:0038:25",
NULL,
};
static const char * const omap4_usb_host_hs_utmi_p3_clk_parents[] __initconst = {
"init_60m_fclk",
NULL,
};
static const char * const omap4_usb_host_hs_hsic480m_p1_clk_parents[] __initconst = {
"dpll_usb_m2_ck",
NULL,
};
static const char * const omap4_utmi_p1_gfclk_parents[] __initconst = {
"init_60m_fclk",
"xclk60mhsp1_ck",
NULL,
};
static const char * const omap4_utmi_p2_gfclk_parents[] __initconst = {
"init_60m_fclk",
"xclk60mhsp2_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p1_clk_parents, NULL },
{ 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p2_clk_parents, NULL },
{ 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
{ 11, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
{ 12, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
{ 13, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
{ 14, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
{ 15, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
{ 24, TI_CLK_MUX, omap4_utmi_p1_gfclk_parents, NULL },
{ 25, TI_CLK_MUX, omap4_utmi_p2_gfclk_parents, NULL },
{ 0 },
};
static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
"l3-init-clkctrl:0040:24",
NULL,
};
static const char * const omap4_otg_60m_gfclk_parents[] __initconst = {
"utmi_phy_clkout_ck",
"xclk60motg_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_usb_otg_hs_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_usb_otg_hs_xclk_parents, NULL },
{ 24, TI_CLK_MUX, omap4_otg_60m_gfclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_usb_tll_hs_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
{ 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
{ 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
{ 0 },
};
static const char * const omap4_ocp2scp_usb_phy_phy_48m_parents[] __initconst = {
"func_48m_fclk",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_ocp2scp_usb_phy_phy_48m_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
{ OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0008:24" },
{ OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0010:24" },
{ OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:0018:24" },
{ OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
{ OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
{ OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
{ OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:00c0:8" },
{ 0 },
};
static const char * const omap4_cm2_dm10_mux_parents[] __initconst = {
"sys_clkin_ck",
"sys_32k_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_timer10_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_timer11_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_timer2_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_timer3_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_timer4_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_timer9_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
{ 0 },
};
static const char * const omap4_gpio2_dbclk_parents[] __initconst = {
"sys_32k_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_gpio2_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_gpio3_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_gpio4_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_gpio5_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
"l4-per-clkctrl:00c0:26",
"pad_clks_ck",
NULL,
};
static const char * const omap4_mcbsp4_sync_mux_ck_parents[] __initconst = {
"func_96m_fclk",
"per_abe_nc_fclk",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_mcbsp4_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL },
{ 0 },
};
static const char * const omap4_slimbus2_fclk_0_parents[] __initconst = {
"func_24mc_fclk",
NULL,
};
static const char * const omap4_slimbus2_fclk_1_parents[] __initconst = {
"per_abe_24m_fclk",
NULL,
};
static const char * const omap4_slimbus2_slimbus_clk_parents[] __initconst = {
"pad_slimbus_core_clks_ck",
NULL,
};
static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_slimbus2_fclk_0_parents, NULL },
{ 9, TI_CLK_GATE, omap4_slimbus2_fclk_1_parents, NULL },
{ 10, TI_CLK_GATE, omap4_slimbus2_slimbus_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
{ OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0008:24" },
{ OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0010:24" },
{ OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0018:24" },
{ OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0020:24" },
{ OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0028:24" },
{ OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0030:24" },
{ OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
{ OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
{ OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
{ OMAP4_GPIO4_CLKCTRL, omap4_gpio4_bit_data, CLKF_HW_SUP, "l4_div_ck" },
{ OMAP4_GPIO5_CLKCTRL, omap4_gpio5_bit_data, CLKF_HW_SUP, "l4_div_ck" },
{ OMAP4_GPIO6_CLKCTRL, omap4_gpio6_bit_data, CLKF_HW_SUP, "l4_div_ck" },
{ OMAP4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
{ OMAP4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
{ OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:00c0:24" },
{ OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0118:8" },
{ OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ 0 },
};
static const struct
omap_clkctrl_reg_data omap4_l4_secure_clkctrl_regs[] __initconst = {
{ OMAP4_AES1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" },
{ OMAP4_AES2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" },
{ OMAP4_DES3DES_CLKCTRL, NULL, CLKF_SW_SUP, "l4_div_ck" },
{ OMAP4_PKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_div_ck" },
{ OMAP4_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_div_ck" },
{ OMAP4_SHA2MD5_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" },
{ OMAP4_CRYPTODMA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_div_ck" },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_gpio1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_timer1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initconst = {
{ OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
{ OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
{ OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4-wkup-clkctrl:0020:24" },
{ OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
{ OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ 0 },
};
static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
"sys_clkin_ck",
"dpll_core_m6x2_ck",
"tie_low_clock_ck",
NULL,
};
static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
"emu-sys-clkctrl:0000:22",
NULL,
};
static const int omap4_trace_clk_div_div_ck_divs[] __initconst = {
0,
1,
2,
0,
4,
-1,
};
static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __initconst = {
.dividers = omap4_trace_clk_div_div_ck_divs,
};
static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
"emu-sys-clkctrl:0000:20",
NULL,
};
static const struct omap_clkctrl_div_data omap4_stm_clk_div_ck_data __initconst = {
.max_div = 64,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data omap4_debugss_bit_data[] __initconst = {
{ 20, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
{ 22, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
{ 24, TI_CLK_DIVIDER, omap4_trace_clk_div_div_ck_parents, &omap4_trace_clk_div_div_ck_data },
{ 27, TI_CLK_DIVIDER, omap4_stm_clk_div_ck_parents, &omap4_stm_clk_div_ck_data },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap4_emu_sys_clkctrl_regs[] __initconst = {
{ OMAP4_DEBUGSS_CLKCTRL, omap4_debugss_bit_data, 0, "trace_clk_div_ck" },
{ 0 },
};
const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
{ 0x4a004320, omap4_mpuss_clkctrl_regs },
{ 0x4a004420, omap4_tesla_clkctrl_regs },
{ 0x4a004520, omap4_abe_clkctrl_regs },
{ 0x4a008620, omap4_l4_ao_clkctrl_regs },
{ 0x4a008720, omap4_l3_1_clkctrl_regs },
{ 0x4a008820, omap4_l3_2_clkctrl_regs },
{ 0x4a008920, omap4_ducati_clkctrl_regs },
{ 0x4a008a20, omap4_l3_dma_clkctrl_regs },
{ 0x4a008b20, omap4_l3_emif_clkctrl_regs },
{ 0x4a008c20, omap4_d2d_clkctrl_regs },
{ 0x4a008d20, omap4_l4_cfg_clkctrl_regs },
{ 0x4a008e20, omap4_l3_instr_clkctrl_regs },
{ 0x4a008f20, omap4_ivahd_clkctrl_regs },
{ 0x4a009020, omap4_iss_clkctrl_regs },
{ 0x4a009120, omap4_l3_dss_clkctrl_regs },
{ 0x4a009220, omap4_l3_gfx_clkctrl_regs },
{ 0x4a009320, omap4_l3_init_clkctrl_regs },
{ 0x4a009420, omap4_l4_per_clkctrl_regs },
{ 0x4a0095a0, omap4_l4_secure_clkctrl_regs },
{ 0x4a307820, omap4_l4_wkup_clkctrl_regs },
{ 0x4a307a20, omap4_emu_sys_clkctrl_regs },
{ 0 },
};
static struct ti_dt_clk omap44xx_clks[] = {
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
/*
* XXX: All the clock aliases below are only needed for legacy
* hwmod support. Once hwmod is removed, these can be removed
* also.
*/
DT_CLK(NULL, "aess_fclk", "abe-clkctrl:0008:24"),
DT_CLK(NULL, "cm2_dm10_mux", "l4-per-clkctrl:0008:24"),
DT_CLK(NULL, "cm2_dm11_mux", "l4-per-clkctrl:0010:24"),
DT_CLK(NULL, "cm2_dm2_mux", "l4-per-clkctrl:0018:24"),
DT_CLK(NULL, "cm2_dm3_mux", "l4-per-clkctrl:0020:24"),
DT_CLK(NULL, "cm2_dm4_mux", "l4-per-clkctrl:0028:24"),
DT_CLK(NULL, "cm2_dm9_mux", "l4-per-clkctrl:0030:24"),
DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
DT_CLK(NULL, "dmt1_clk_mux", "l4-wkup-clkctrl:0020:24"),
DT_CLK(NULL, "dss_48mhz_clk", "l3-dss-clkctrl:0000:9"),
DT_CLK(NULL, "dss_dss_clk", "l3-dss-clkctrl:0000:8"),
DT_CLK(NULL, "dss_sys_clk", "l3-dss-clkctrl:0000:10"),
DT_CLK(NULL, "dss_tv_clk", "l3-dss-clkctrl:0000:11"),
DT_CLK(NULL, "fdif_fck", "iss-clkctrl:0008:24"),
DT_CLK(NULL, "func_dmic_abe_gfclk", "abe-clkctrl:0018:24"),
DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe-clkctrl:0020:24"),
DT_CLK(NULL, "func_mcbsp1_gfclk", "abe-clkctrl:0028:24"),
DT_CLK(NULL, "func_mcbsp2_gfclk", "abe-clkctrl:0030:24"),
DT_CLK(NULL, "func_mcbsp3_gfclk", "abe-clkctrl:0038:24"),
DT_CLK(NULL, "gpio1_dbclk", "l4-wkup-clkctrl:0018:8"),
DT_CLK(NULL, "gpio2_dbclk", "l4-per-clkctrl:0040:8"),
DT_CLK(NULL, "gpio3_dbclk", "l4-per-clkctrl:0048:8"),
DT_CLK(NULL, "gpio4_dbclk", "l4-per-clkctrl:0050:8"),
DT_CLK(NULL, "gpio5_dbclk", "l4-per-clkctrl:0058:8"),
DT_CLK(NULL, "gpio6_dbclk", "l4-per-clkctrl:0060:8"),
DT_CLK(NULL, "hsi_fck", "l3-init-clkctrl:0018:24"),
DT_CLK(NULL, "hsmmc1_fclk", "l3-init-clkctrl:0008:24"),
DT_CLK(NULL, "hsmmc2_fclk", "l3-init-clkctrl:0010:24"),
DT_CLK(NULL, "iss_ctrlclk", "iss-clkctrl:0000:8"),
DT_CLK(NULL, "mcasp_sync_mux_ck", "abe-clkctrl:0020:26"),
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"),
DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"),
DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"),
DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"),
DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"),
DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"),
DT_CLK(NULL, "sgx_clk_mux", "l3-gfx-clkctrl:0000:24"),
DT_CLK(NULL, "slimbus1_fclk_0", "abe-clkctrl:0040:8"),
DT_CLK(NULL, "slimbus1_fclk_1", "abe-clkctrl:0040:9"),
DT_CLK(NULL, "slimbus1_fclk_2", "abe-clkctrl:0040:10"),
DT_CLK(NULL, "slimbus1_slimbus_clk", "abe-clkctrl:0040:11"),
DT_CLK(NULL, "slimbus2_fclk_0", "l4-per-clkctrl:0118:8"),
DT_CLK(NULL, "slimbus2_fclk_1", "l4-per-clkctrl:0118:9"),
DT_CLK(NULL, "slimbus2_slimbus_clk", "l4-per-clkctrl:0118:10"),
DT_CLK(NULL, "stm_clk_div_ck", "emu-sys-clkctrl:0000:27"),
DT_CLK(NULL, "timer5_sync_mux", "abe-clkctrl:0048:24"),
DT_CLK(NULL, "timer6_sync_mux", "abe-clkctrl:0050:24"),
DT_CLK(NULL, "timer7_sync_mux", "abe-clkctrl:0058:24"),
DT_CLK(NULL, "timer8_sync_mux", "abe-clkctrl:0060:24"),
DT_CLK(NULL, "trace_clk_div_div_ck", "emu-sys-clkctrl:0000:24"),
DT_CLK(NULL, "usb_host_hs_func48mclk", "l3-init-clkctrl:0038:15"),
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3-init-clkctrl:0038:13"),
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3-init-clkctrl:0038:14"),
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3-init-clkctrl:0038:11"),
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3-init-clkctrl:0038:12"),
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3-init-clkctrl:0038:8"),
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3-init-clkctrl:0038:9"),
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init-clkctrl:0038:10"),
DT_CLK(NULL, "usb_otg_hs_xclk", "l3-init-clkctrl:0040:8"),
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3-init-clkctrl:0048:8"),
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3-init-clkctrl:0048:9"),
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3-init-clkctrl:0048:10"),
DT_CLK(NULL, "utmi_p1_gfclk", "l3-init-clkctrl:0038:24"),
DT_CLK(NULL, "utmi_p2_gfclk", "l3-init-clkctrl:0038:25"),
{ .node_name = NULL },
};
int __init omap4xxx_dt_clk_init(void)
{
int rc;
struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
ti_dt_clocks_register(omap44xx_clks);
omap2_clk_disable_autoidle_all();
ti_clk_add_aliases();
/*
* Lock USB DPLL on OMAP4 devices so that the L3INIT power
* domain can transition to retention state when not in use.
*/
usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
if (rc)
pr_err("%s: failed to configure USB DPLL!\n", __func__);
/*
* On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
* state when turning the ABE clock domain. Workaround this by
* locking the ABE DPLL on boot.
* Lock the ABE DPLL in any case to avoid issues with audio.
*/
abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
if (!rc)
rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
return 0;
}
| linux-master | drivers/clk/ti/clk-44xx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP gate clock support
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
static const struct clk_ops omap_gate_clkdm_clk_ops = {
.init = &omap2_init_clk_clkdm,
.enable = &omap2_clkops_enable_clkdm,
.disable = &omap2_clkops_disable_clkdm,
.restore_context = clk_gate_restore_context,
};
const struct clk_ops omap_gate_clk_ops = {
.init = &omap2_init_clk_clkdm,
.enable = &omap2_dflt_clk_enable,
.disable = &omap2_dflt_clk_disable,
.is_enabled = &omap2_dflt_clk_is_enabled,
.restore_context = clk_gate_restore_context,
};
static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
.init = &omap2_init_clk_clkdm,
.enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
.disable = &omap2_dflt_clk_disable,
.is_enabled = &omap2_dflt_clk_is_enabled,
.restore_context = clk_gate_restore_context,
};
/**
* omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
* from HSDivider PWRDN problem Implements Errata ID: i556.
* @hw: DPLL output struct clk_hw
*
* 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
* dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
* valueafter their respective PWRDN bits are set. Any dummy write
* (Any other value different from the Read value) to the
* corresponding CM_CLKSEL register will refresh the dividers.
*/
static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw)
{
struct clk_omap_divider *parent;
struct clk_hw *parent_hw;
u32 dummy_v, orig_v;
int ret;
/* Clear PWRDN bit of HSDIVIDER */
ret = omap2_dflt_clk_enable(hw);
/* Parent is the x2 node, get parent of parent for the m2 div */
parent_hw = clk_hw_get_parent(clk_hw_get_parent(hw));
parent = to_clk_omap_divider(parent_hw);
/* Restore the dividers */
if (!ret) {
orig_v = ti_clk_ll_ops->clk_readl(&parent->reg);
dummy_v = orig_v;
/* Write any other value different from the Read value */
dummy_v ^= (1 << parent->shift);
ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg);
/* Write the original divider */
ti_clk_ll_ops->clk_writel(orig_v, &parent->reg);
}
return ret;
}
static struct clk *_register_gate(struct device_node *node, const char *name,
const char *parent_name, unsigned long flags,
struct clk_omap_reg *reg, u8 bit_idx,
u8 clk_gate_flags, const struct clk_ops *ops,
const struct clk_hw_omap_ops *hw_ops)
{
struct clk_init_data init = { NULL };
struct clk_hw_omap *clk_hw;
struct clk *clk;
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
if (!clk_hw)
return ERR_PTR(-ENOMEM);
clk_hw->hw.init = &init;
init.name = name;
init.ops = ops;
memcpy(&clk_hw->enable_reg, reg, sizeof(*reg));
clk_hw->enable_bit = bit_idx;
clk_hw->ops = hw_ops;
clk_hw->flags = clk_gate_flags;
init.parent_names = &parent_name;
init.num_parents = 1;
init.flags = flags;
clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
if (IS_ERR(clk))
kfree(clk_hw);
return clk;
}
static void __init _of_ti_gate_clk_setup(struct device_node *node,
const struct clk_ops *ops,
const struct clk_hw_omap_ops *hw_ops)
{
struct clk *clk;
const char *parent_name;
struct clk_omap_reg reg;
const char *name;
u8 enable_bit = 0;
u32 val;
u32 flags = 0;
u8 clk_gate_flags = 0;
if (ops != &omap_gate_clkdm_clk_ops) {
if (ti_clk_get_reg_addr(node, 0, ®))
return;
if (!of_property_read_u32(node, "ti,bit-shift", &val))
enable_bit = val;
}
if (of_clk_get_parent_count(node) != 1) {
pr_err("%pOFn must have 1 parent\n", node);
return;
}
parent_name = of_clk_get_parent_name(node, 0);
if (of_property_read_bool(node, "ti,set-rate-parent"))
flags |= CLK_SET_RATE_PARENT;
if (of_property_read_bool(node, "ti,set-bit-to-disable"))
clk_gate_flags |= INVERT_ENABLE;
name = ti_dt_clk_name(node);
clk = _register_gate(node, name, parent_name, flags, ®,
enable_bit, clk_gate_flags, ops, hw_ops);
if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk);
}
static void __init
_of_ti_composite_gate_clk_setup(struct device_node *node,
const struct clk_hw_omap_ops *hw_ops)
{
struct clk_hw_omap *gate;
u32 val = 0;
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
return;
if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg))
goto cleanup;
of_property_read_u32(node, "ti,bit-shift", &val);
gate->enable_bit = val;
gate->ops = hw_ops;
if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
return;
cleanup:
kfree(gate);
}
static void __init
of_ti_composite_no_wait_gate_clk_setup(struct device_node *node)
{
_of_ti_composite_gate_clk_setup(node, NULL);
}
CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock",
of_ti_composite_no_wait_gate_clk_setup);
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
static void __init of_ti_composite_interface_clk_setup(struct device_node *node)
{
_of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait);
}
CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock",
of_ti_composite_interface_clk_setup);
#endif
static void __init of_ti_composite_gate_clk_setup(struct device_node *node)
{
_of_ti_composite_gate_clk_setup(node, &clkhwops_wait);
}
CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock",
of_ti_composite_gate_clk_setup);
static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
{
_of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL);
}
CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
of_ti_clkdm_gate_clk_setup);
static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
{
_of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops,
&clkhwops_wait);
}
CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
of_ti_hsdiv_gate_clk_setup);
static void __init of_ti_gate_clk_setup(struct device_node *node)
{
_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL);
}
CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup);
static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
{
_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait);
}
CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
of_ti_wait_gate_clk_setup);
#ifdef CONFIG_ARCH_OMAP3
static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
{
_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
&clkhwops_am35xx_ipss_module_wait);
}
CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
of_ti_am35xx_gate_clk_setup);
static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
{
_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
&clkhwops_omap3430es2_dss_usbhost_wait);
}
CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
of_ti_dss_gate_clk_setup);
#endif
| linux-master | drivers/clk/ti/gate.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Default clock type
*
* Copyright (C) 2005-2008, 2015 Texas Instruments, Inc.
* Copyright (C) 2004-2010 Nokia Corporation
*
* Contacts:
* Richard Woodruff <[email protected]>
* Paul Walmsley
* Tero Kristo <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/clk/ti.h>
#include <linux/delay.h>
#include "clock.h"
/*
* MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait
* for a module to indicate that it is no longer in idle
*/
#define MAX_MODULE_ENABLE_WAIT 100000
/*
* CM module register offsets, used for calculating the companion
* register addresses.
*/
#define CM_FCLKEN 0x0000
#define CM_ICLKEN 0x0010
/**
* _wait_idlest_generic - wait for a module to leave the idle state
* @clk: module clock to wait for (needed for register offsets)
* @reg: virtual address of module IDLEST register
* @mask: value to mask against to determine if the module is active
* @idlest: idle state indicator (0 or 1) for the clock
* @name: name of the clock (for printk)
*
* Wait for a module to leave idle, where its idle-status register is
* not inside the CM module. Returns 1 if the module left idle
* promptly, or 0 if the module did not leave idle before the timeout
* elapsed. XXX Deprecated - should be moved into drivers for the
* individual IP block that the IDLEST register exists in.
*/
static int _wait_idlest_generic(struct clk_hw_omap *clk,
struct clk_omap_reg *reg,
u32 mask, u8 idlest, const char *name)
{
int i = 0, ena = 0;
ena = (idlest) ? 0 : mask;
/* Wait until module enters enabled state */
for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) {
if ((ti_clk_ll_ops->clk_readl(reg) & mask) == ena)
break;
udelay(1);
}
if (i < MAX_MODULE_ENABLE_WAIT)
pr_debug("omap clock: module associated with clock %s ready after %d loops\n",
name, i);
else
pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n",
name, MAX_MODULE_ENABLE_WAIT);
return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
}
/**
* _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
* @clk: struct clk * belonging to the module
*
* If the necessary clocks for the OMAP hardware IP block that
* corresponds to clock @clk are enabled, then wait for the module to
* indicate readiness (i.e., to leave IDLE). This code does not
* belong in the clock code and will be moved in the medium term to
* module-dependent code. No return value.
*/
static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
{
struct clk_omap_reg companion_reg, idlest_reg;
u8 other_bit, idlest_bit, idlest_val, idlest_reg_id;
s16 prcm_mod;
int r;
/* Not all modules have multiple clocks that their IDLEST depends on */
if (clk->ops->find_companion) {
clk->ops->find_companion(clk, &companion_reg, &other_bit);
if (!(ti_clk_ll_ops->clk_readl(&companion_reg) &
(1 << other_bit)))
return;
}
clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
r = ti_clk_ll_ops->cm_split_idlest_reg(&idlest_reg, &prcm_mod,
&idlest_reg_id);
if (r) {
/* IDLEST register not in the CM module */
_wait_idlest_generic(clk, &idlest_reg, (1 << idlest_bit),
idlest_val, clk_hw_get_name(&clk->hw));
} else {
ti_clk_ll_ops->cm_wait_module_ready(0, prcm_mod, idlest_reg_id,
idlest_bit);
}
}
/**
* omap2_clk_dflt_find_companion - find companion clock to @clk
* @clk: struct clk * to find the companion clock of
* @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
* @other_bit: u8 ** to return the companion clock bit shift in
*
* Note: We don't need special code here for INVERT_ENABLE for the
* time being since INVERT_ENABLE only applies to clocks enabled by
* CM_CLKEN_PLL
*
* Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
* just a matter of XORing the bits.
*
* Some clocks don't have companion clocks. For example, modules with
* only an interface clock (such as MAILBOXES) don't have a companion
* clock. Right now, this code relies on the hardware exporting a bit
* in the correct companion register that indicates that the
* nonexistent 'companion clock' is active. Future patches will
* associate this type of code with per-module data structures to
* avoid this issue, and remove the casts. No return value.
*/
void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
struct clk_omap_reg *other_reg,
u8 *other_bit)
{
memcpy(other_reg, &clk->enable_reg, sizeof(*other_reg));
/*
* Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
* it's just a matter of XORing the bits.
*/
other_reg->offset ^= (CM_FCLKEN ^ CM_ICLKEN);
*other_bit = clk->enable_bit;
}
/**
* omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
* @clk: struct clk * to find IDLEST info for
* @idlest_reg: void __iomem ** to return the CM_IDLEST va in
* @idlest_bit: u8 * to return the CM_IDLEST bit shift in
* @idlest_val: u8 * to return the idle status indicator
*
* Return the CM_IDLEST register address and bit shift corresponding
* to the module that "owns" this clock. This default code assumes
* that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
* the IDLEST register address ID corresponds to the CM_*CLKEN
* register address ID (e.g., that CM_FCLKEN2 corresponds to
* CM_IDLEST2). This is not true for all modules. No return value.
*/
void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
struct clk_omap_reg *idlest_reg, u8 *idlest_bit,
u8 *idlest_val)
{
memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
idlest_reg->offset &= ~0xf0;
idlest_reg->offset |= 0x20;
*idlest_bit = clk->enable_bit;
/*
* 24xx uses 0 to indicate not ready, and 1 to indicate ready.
* 34xx reverses this, just to keep us on our toes
* AM35xx uses both, depending on the module.
*/
*idlest_val = ti_clk_get_features()->cm_idlest_val;
}
/**
* omap2_dflt_clk_enable - enable a clock in the hardware
* @hw: struct clk_hw * of the clock to enable
*
* Enable the clock @hw in the hardware. We first call into the OMAP
* clockdomain code to "enable" the corresponding clockdomain if this
* is the first enabled user of the clockdomain. Then program the
* hardware to enable the clock. Then wait for the IP block that uses
* this clock to leave idle (if applicable). Returns the error value
* from clkdm_clk_enable() if it terminated with an error, or -EINVAL
* if @hw has a null clock enable_reg, or zero upon success.
*/
int omap2_dflt_clk_enable(struct clk_hw *hw)
{
struct clk_hw_omap *clk;
u32 v;
int ret = 0;
bool clkdm_control;
if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL)
clkdm_control = false;
else
clkdm_control = true;
clk = to_clk_hw_omap(hw);
if (clkdm_control && clk->clkdm) {
ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
if (ret) {
WARN(1,
"%s: could not enable %s's clockdomain %s: %d\n",
__func__, clk_hw_get_name(hw),
clk->clkdm_name, ret);
return ret;
}
}
/* FIXME should not have INVERT_ENABLE bit here */
v = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
if (clk->flags & INVERT_ENABLE)
v &= ~(1 << clk->enable_bit);
else
v |= (1 << clk->enable_bit);
ti_clk_ll_ops->clk_writel(v, &clk->enable_reg);
v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); /* OCP barrier */
if (clk->ops && clk->ops->find_idlest)
_omap2_module_wait_ready(clk);
return 0;
}
/**
* omap2_dflt_clk_disable - disable a clock in the hardware
* @hw: struct clk_hw * of the clock to disable
*
* Disable the clock @hw in the hardware, and call into the OMAP
* clockdomain code to "disable" the corresponding clockdomain if all
* clocks/hwmods in that clockdomain are now disabled. No return
* value.
*/
void omap2_dflt_clk_disable(struct clk_hw *hw)
{
struct clk_hw_omap *clk;
u32 v;
clk = to_clk_hw_omap(hw);
v = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
if (clk->flags & INVERT_ENABLE)
v |= (1 << clk->enable_bit);
else
v &= ~(1 << clk->enable_bit);
ti_clk_ll_ops->clk_writel(v, &clk->enable_reg);
/* No OCP barrier needed here since it is a disable operation */
if (!(ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) &&
clk->clkdm)
ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
}
/**
* omap2_dflt_clk_is_enabled - is clock enabled in the hardware?
* @hw: struct clk_hw * to check
*
* Return 1 if the clock represented by @hw is enabled in the
* hardware, or 0 otherwise. Intended for use in the struct
* clk_ops.is_enabled function pointer.
*/
int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
u32 v;
v = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
if (clk->flags & INVERT_ENABLE)
v ^= BIT(clk->enable_bit);
v &= BIT(clk->enable_bit);
return v ? 1 : 0;
}
const struct clk_hw_omap_ops clkhwops_wait = {
.find_idlest = omap2_clk_dflt_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
| linux-master | drivers/clk/ti/clkt_dflt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP2/3 interface clock control
*
* Copyright (C) 2011 Nokia Corporation
* Paul Walmsley
*/
#undef DEBUG
#include <linux/kernel.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/clk/ti.h>
#include "clock.h"
/* Register offsets */
#define OMAP24XX_CM_FCLKEN2 0x04
#define CM_AUTOIDLE 0x30
#define CM_ICLKEN 0x10
#define CM_IDLEST 0x20
#define OMAP24XX_CM_IDLEST_VAL 0
/* Private functions */
/* XXX */
void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
{
u32 v;
struct clk_omap_reg r;
memcpy(&r, &clk->enable_reg, sizeof(r));
r.offset ^= (CM_AUTOIDLE ^ CM_ICLKEN);
v = ti_clk_ll_ops->clk_readl(&r);
v |= (1 << clk->enable_bit);
ti_clk_ll_ops->clk_writel(v, &r);
}
/* XXX */
void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
{
u32 v;
struct clk_omap_reg r;
memcpy(&r, &clk->enable_reg, sizeof(r));
r.offset ^= (CM_AUTOIDLE ^ CM_ICLKEN);
v = ti_clk_ll_ops->clk_readl(&r);
v &= ~(1 << clk->enable_bit);
ti_clk_ll_ops->clk_writel(v, &r);
}
/**
* omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
* @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
*
* OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
* CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
* passes back the correct CM_IDLEST register address for I2CHS
* modules. No return value.
*/
static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk,
struct clk_omap_reg *idlest_reg,
u8 *idlest_bit,
u8 *idlest_val)
{
memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
idlest_reg->offset ^= (OMAP24XX_CM_FCLKEN2 ^ CM_IDLEST);
*idlest_bit = clk->enable_bit;
*idlest_val = OMAP24XX_CM_IDLEST_VAL;
}
/* Public data */
const struct clk_hw_omap_ops clkhwops_iclk = {
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
};
const struct clk_hw_omap_ops clkhwops_iclk_wait = {
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
.find_idlest = omap2_clk_dflt_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
/* 2430 I2CHS has non-standard IDLEST register */
const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait = {
.find_idlest = omap2430_clk_i2chs_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
| linux-master | drivers/clk/ti/clkt_iclk.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* DRA7 Clock init
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo ([email protected])
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk/ti.h>
#include <dt-bindings/clock/dra7.h>
#include "clock.h"
#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
#define DRA7_DPLL_USB_DEFFREQ 960000000
static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
{ DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {
{ DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
{ 0 },
};
static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
"dpll_abe_m2x2_ck",
"dpll_core_h22x2_ck",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {
{ DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLEST, "ipu1-clkctrl:0000:24" },
{ 0 },
};
static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
"per_abe_x1_gfclk2_div",
"video1_clk2_div",
"video2_clk2_div",
"hdmi_clk2_div",
NULL,
};
static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
"abe_24m_fclk",
"abe_sys_clk_div",
"func_24m_clk",
"atl_clkin3_ck",
"atl_clkin2_ck",
"atl_clkin1_ck",
"atl_clkin0_ck",
"sys_clkin2",
"ref_clkin0_ck",
"ref_clkin1_ck",
"ref_clkin2_ck",
"ref_clkin3_ck",
"mlb_clk",
"mlbp_clk",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
"timer_sys_clk_div",
"sys_32k_ck",
"sys_clkin2",
"ref_clkin0_ck",
"ref_clkin1_ck",
"ref_clkin2_ck",
"ref_clkin3_ck",
"abe_giclk_div",
"video1_div_clk",
"video2_div_clk",
"hdmi_div_clk",
"clkoutmux0_clk_mux",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
"func_48m_fclk",
"dpll_per_m2x2_ck",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
{ DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
{ DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },
{ DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },
{ DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },
{ DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },
{ DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = {
{ DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
{ DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ 0 },
};
static const char * const dra7_cam_gfclk_mux_parents[] __initconst = {
"l3_iclk_div",
"core_iss_main_clk",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_cam_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_cam_clkctrl_regs[] __initconst = {
{ DRA7_CAM_VIP1_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_CAM_VIP2_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_CAM_VIP3_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_vpe_clkctrl_regs[] __initconst = {
{ DRA7_VPE_VPE_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h23x2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
{ DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
{ DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
{ DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = {
{ DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
{ DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
{ DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
"sys_32k_ck",
"video1_clkin_ck",
"video2_clkin_ck",
"hdmi_clkin_ck",
NULL,
};
static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
"l3_iclk_div",
"dpll_abe_m2_ck",
"atl-clkctrl:0000:24",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
{ 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
{ DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
{ DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
{ DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_iva_clkctrl_regs[] __initconst = {
{ DRA7_IVA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h12x2_ck" },
{ DRA7_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
{ 0 },
};
static const char * const dra7_dss_dss_clk_parents[] __initconst = {
"dpll_per_h12x2_ck",
NULL,
};
static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
"func_48m_fclk",
NULL,
};
static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
"hdmi_dpll_clk_mux",
NULL,
};
static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
"sys_32k_ck",
NULL,
};
static const char * const dra7_dss_video1_clk_parents[] __initconst = {
"video1_dpll_clk_mux",
NULL,
};
static const char * const dra7_dss_video2_clk_parents[] __initconst = {
"video2_dpll_clk_mux",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
{ 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
{ 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
{ 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
{ 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
{ DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
{ DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
{ 0 },
};
static const char * const dra7_gpu_core_mux_parents[] __initconst = {
"dpll_core_h14x2_ck",
"dpll_per_h14x2_ck",
"dpll_gpu_m2_ck",
NULL,
};
static const char * const dra7_gpu_hyd_mux_parents[] __initconst = {
"dpll_core_h14x2_ck",
"dpll_per_h14x2_ck",
"dpll_gpu_m2_ck",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_gpu_core_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_gpu_core_mux_parents, NULL, },
{ 26, TI_CLK_MUX, dra7_gpu_hyd_mux_parents, NULL, },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_gpu_clkctrl_regs[] __initconst = {
{ DRA7_GPU_CLKCTRL, dra7_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24", },
{ 0 },
};
static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
"func_128m_clk",
"dpll_per_m2x2_ck",
NULL,
};
static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
"l3init-clkctrl:0008:24",
NULL,
};
static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
.max_div = 4,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
{ 0 },
};
static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
"l3init-clkctrl:0010:24",
NULL,
};
static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
.max_div = 4,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
{ 0 },
};
static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
"l3init_960m_gfclk",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
{ 0 },
};
static const char * const dra7_sata_ref_clk_parents[] __initconst = {
"sys_clkin1",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
{ DRA7_L3INIT_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
{ DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
{ DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },
{ DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
{ DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
{ DRA7_L3INIT_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
{ 0 },
};
static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
"apll_pcie_ck",
NULL,
};
static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
"optfclk_pciephy_div",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = {
{ DRA7_PCIE_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
{ DRA7_PCIE_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
{ 0 },
};
static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
"dpll_gmac_h11x2_ck",
"rmii_clk_ck",
NULL,
};
static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
"video1_clkin_ck",
"video2_clkin_ck",
"dpll_abe_m2_ck",
"hdmi_clkin_ck",
"l3_iclk_div",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
{ 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
{ DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "gmac_main_clk" },
{ 0 },
};
static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
"timer_sys_clk_div",
"sys_32k_ck",
"sys_clkin2",
"ref_clkin0_ck",
"ref_clkin1_ck",
"ref_clkin2_ck",
"ref_clkin3_ck",
"abe_giclk_div",
"video1_div_clk",
"video2_div_clk",
"hdmi_div_clk",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
"l4per-clkctrl:00f8:24",
NULL,
};
static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
.max_div = 4,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
{ 0 },
};
static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
"l4per-clkctrl:0100:24",
NULL,
};
static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
.max_div = 4,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
{ DRA7_L4PER_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0000:24" },
{ DRA7_L4PER_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
{ DRA7_L4PER_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
{ DRA7_L4PER_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
{ DRA7_L4PER_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
{ DRA7_L4PER_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
{ DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4PER_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4PER_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4PER_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4PER_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4PER_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
{ DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ DRA7_L4PER_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4PER_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4PER_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:00f8:25" },
{ DRA7_L4PER_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0100:25" },
{ DRA7_L4PER_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0118:24" },
{ DRA7_L4PER_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0120:24" },
{ DRA7_L4PER_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0128:24" },
{ DRA7_L4PER_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0130:24" },
{ DRA7_L4PER_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0148:24" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = {
{ DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
{ DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ DRA7_L4SEC_SHAM2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
{ 0 },
};
static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
"func_128m_clk",
"dpll_per_h13x2_ck",
NULL,
};
static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
"l4per2-clkctrl:012c:24",
NULL,
};
static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
.max_div = 4,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
{ 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = {
{ DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" },
{ DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" },
{ DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
{ DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
{ DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
{ DRA7_L4PER2_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:012c:25" },
{ DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
{ DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
{ DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
{ DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:22" },
{ DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
{ DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
{ DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
{ DRA7_L4PER2_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01dc:24" },
{ DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" },
{ DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" },
{ DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = {
{ DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" },
{ DRA7_L4PER3_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00b4:24" },
{ DRA7_L4PER3_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00bc:24" },
{ DRA7_L4PER3_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00c4:24" },
{ DRA7_L4PER3_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:011c:24" },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
"sys_clkin1",
"sys_clkin2",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
{ DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
{ DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
{ DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
{ DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },
{ DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },
{ DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SOC_DRA76, "mcan_clk" },
{ 0 },
};
const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
{ 0x4a005320, dra7_mpu_clkctrl_regs },
{ 0x4a005420, dra7_dsp1_clkctrl_regs },
{ 0x4a005520, dra7_ipu1_clkctrl_regs },
{ 0x4a005550, dra7_ipu_clkctrl_regs },
{ 0x4a005620, dra7_dsp2_clkctrl_regs },
{ 0x4a005720, dra7_rtc_clkctrl_regs },
{ 0x4a005760, dra7_vpe_clkctrl_regs },
{ 0x4a008620, dra7_coreaon_clkctrl_regs },
{ 0x4a008720, dra7_l3main1_clkctrl_regs },
{ 0x4a008920, dra7_ipu2_clkctrl_regs },
{ 0x4a008a20, dra7_dma_clkctrl_regs },
{ 0x4a008b20, dra7_emif_clkctrl_regs },
{ 0x4a008c00, dra7_atl_clkctrl_regs },
{ 0x4a008d20, dra7_l4cfg_clkctrl_regs },
{ 0x4a008e20, dra7_l3instr_clkctrl_regs },
{ 0x4a008f20, dra7_iva_clkctrl_regs },
{ 0x4a009020, dra7_cam_clkctrl_regs },
{ 0x4a009120, dra7_dss_clkctrl_regs },
{ 0x4a009220, dra7_gpu_clkctrl_regs },
{ 0x4a009320, dra7_l3init_clkctrl_regs },
{ 0x4a0093b0, dra7_pcie_clkctrl_regs },
{ 0x4a0093d0, dra7_gmac_clkctrl_regs },
{ 0x4a009728, dra7_l4per_clkctrl_regs },
{ 0x4a0098a0, dra7_l4sec_clkctrl_regs },
{ 0x4a00970c, dra7_l4per2_clkctrl_regs },
{ 0x4a009714, dra7_l4per3_clkctrl_regs },
{ 0x4ae07820, dra7_wkupaon_clkctrl_regs },
{ 0 },
};
static struct ti_dt_clk dra7xx_clks[] = {
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"),
DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"),
DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"),
DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"),
DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"),
DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"),
DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"),
DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"),
DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"),
DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"),
DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"),
DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"),
DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"),
DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"),
DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"),
DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"),
DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"),
DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"),
DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"),
DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"),
DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"),
DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"),
DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"),
DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"),
DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"),
DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"),
DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"),
DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"),
DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),
DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"),
DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"),
DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"),
DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"),
DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"),
DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"),
DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"),
DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"),
DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"),
DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"),
DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"),
DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"),
DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"),
DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"),
DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"),
DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"),
DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"),
DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"),
DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"),
DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"),
DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"),
DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"),
DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"),
DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"),
DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"),
DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"),
DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"),
DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"),
DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"),
DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"),
DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"),
DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"),
DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"),
DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"),
DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"),
DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"),
DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"),
DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"),
DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"),
DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"),
DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"),
DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"),
DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"),
{ .node_name = NULL },
};
int __init dra7xx_dt_clk_init(void)
{
int rc;
struct clk *dpll_ck, *hdcp_ck;
ti_dt_clocks_register(dra7xx_clks);
omap2_clk_disable_autoidle_all();
ti_clk_add_aliases();
dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
if (rc)
pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
if (rc)
pr_err("%s: failed to configure USB DPLL!\n", __func__);
dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
if (rc)
pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
rc = clk_prepare_enable(hdcp_ck);
if (rc)
pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
return rc;
}
| linux-master | drivers/clk/ti/clk-7xx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AM33XX Clock init
*
* Copyright (C) 2013 Texas Instruments, Inc
* Tero Kristo ([email protected])
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
#include <dt-bindings/clock/am3.h>
#include "clock.h"
static const char * const am3_gpio1_dbclk_parents[] __initconst = {
"clk-24mhz-clkctrl:0000:0",
NULL,
};
static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst = {
{ AM3_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM3_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
{ AM3_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
{ AM3_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
{ AM3_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
{ AM3_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
{ AM3_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
{ AM3_L4LS_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
{ AM3_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
{ AM3_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
{ AM3_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
{ AM3_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ AM3_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ AM3_L4LS_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l3s_clkctrl_regs[] __initconst = {
{ AM3_L3S_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck" },
{ AM3_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
{ AM3_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
{ AM3_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
{ AM3_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l3_clkctrl_regs[] __initconst = {
{ AM3_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM3_L3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck" },
{ AM3_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM3_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
{ AM3_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM3_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM3_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM3_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM3_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ AM3_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4hs_clkctrl_regs[] __initconst = {
{ AM3_L4HS_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_pruss_ocp_clkctrl_regs[] __initconst = {
{ AM3_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "pruss_ocp_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_cpsw_125mhz_clkctrl_regs[] __initconst = {
{ AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_lcdc_clkctrl_regs[] __initconst = {
{ AM3_LCDC_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_clk_24mhz_clkctrl_regs[] __initconst = {
{ AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck" },
{ 0 },
};
static const char * const am3_gpio0_dbclk_parents[] __initconst = {
"gpio0_dbclk_mux_ck",
NULL,
};
static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
{ 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
{ AM3_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
{ AM3_L4_WKUP_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
{ AM3_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
{ AM3_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
{ AM3_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
{ AM3_L4_WKUP_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
{ AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
{ AM3_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
{ AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
{ AM3_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
{ 0 },
};
static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
"sys_clkin_ck",
NULL,
};
static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
"l3-aon-clkctrl:0000:19",
"l3-aon-clkctrl:0000:30",
NULL,
};
static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
"l3-aon-clkctrl:0000:20",
NULL,
};
static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
.max_div = 64,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
"l3-aon-clkctrl:0000:22",
NULL,
};
static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
.max_div = 64,
.flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const char * const am3_dbg_clka_ck_parents[] __initconst = {
"dpll_core_m4_ck",
NULL,
};
static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
{ 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
{ 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
{ 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
{ 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
{ 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
{ 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l3_aon_clkctrl_regs[] __initconst = {
{ AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4_wkup_aon_clkctrl_regs[] __initconst = {
{ AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
{ AM3_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
{ AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk-24mhz-clkctrl:0000:0" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
{ AM3_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
{ AM3_L4_CEFUSE_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
{ 0 },
};
const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = {
{ 0x44e00038, am3_l4ls_clkctrl_regs },
{ 0x44e0001c, am3_l3s_clkctrl_regs },
{ 0x44e00024, am3_l3_clkctrl_regs },
{ 0x44e00120, am3_l4hs_clkctrl_regs },
{ 0x44e000e8, am3_pruss_ocp_clkctrl_regs },
{ 0x44e00000, am3_cpsw_125mhz_clkctrl_regs },
{ 0x44e00018, am3_lcdc_clkctrl_regs },
{ 0x44e0014c, am3_clk_24mhz_clkctrl_regs },
{ 0x44e00400, am3_l4_wkup_clkctrl_regs },
{ 0x44e00414, am3_l3_aon_clkctrl_regs },
{ 0x44e004b0, am3_l4_wkup_aon_clkctrl_regs },
{ 0x44e00600, am3_mpu_clkctrl_regs },
{ 0x44e00800, am3_l4_rtc_clkctrl_regs },
{ 0x44e00900, am3_gfx_l3_clkctrl_regs },
{ 0x44e00a00, am3_l4_cefuse_clkctrl_regs },
{ 0 },
};
static struct ti_dt_clk am33xx_clks[] = {
DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"),
DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"),
DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0008:18"),
DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0074:18"),
DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0078:18"),
DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:007c:18"),
DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"),
DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"),
DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"),
DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l3-aon-clkctrl:0000:20"),
{ .node_name = NULL },
};
static const char *enable_init_clks[] = {
"dpll_ddr_m2_ck",
"dpll_mpu_m2_ck",
"l3_gclk",
/* AM3_L3_L3_MAIN_CLKCTRL, needed during suspend */
"l3-clkctrl:00bc:0",
"l4hs_gclk",
"l4fw_gclk",
"l4ls_gclk",
/* Required for external peripherals like, Audio codecs */
"clkout2_ck",
};
int __init am33xx_dt_clk_init(void)
{
struct clk *clk1, *clk2;
ti_dt_clocks_register(am33xx_clks);
omap2_clk_disable_autoidle_all();
ti_clk_add_aliases();
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
* physically present, in such a case HWMOD enabling of
* clock would be failure with default parent. And timer
* probe thinks clock is already enabled, this leads to
* crash upon accessing timer 3 & 6 registers in probe.
* Fix by setting parent of both these timers to master
* oscillator clock.
*/
clk1 = clk_get_sys(NULL, "sys_clkin_ck");
clk2 = clk_get_sys(NULL, "timer3_fck");
clk_set_parent(clk2, clk1);
clk2 = clk_get_sys(NULL, "timer6_fck");
clk_set_parent(clk2, clk1);
/*
* The On-Chip 32K RC Osc clock is not an accurate clock-source as per
* the design/spec, so as a result, for example, timer which supposed
* to get expired @60Sec, but will expire somewhere ~@40Sec, which is
* not expected by any use-case, so change WDT1 clock source to PRCM
* 32KHz clock.
*/
clk1 = clk_get_sys(NULL, "wdt1_fck");
clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
clk_set_parent(clk1, clk2);
return 0;
}
| linux-master | drivers/clk/ti/clk-33xx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI Divider Clock
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
static unsigned int _get_table_div(const struct clk_div_table *table,
unsigned int val)
{
const struct clk_div_table *clkt;
for (clkt = table; clkt->div; clkt++)
if (clkt->val == val)
return clkt->div;
return 0;
}
static void _setup_mask(struct clk_omap_divider *divider)
{
u16 mask;
u32 max_val;
const struct clk_div_table *clkt;
if (divider->table) {
max_val = 0;
for (clkt = divider->table; clkt->div; clkt++)
if (clkt->val > max_val)
max_val = clkt->val;
} else {
max_val = divider->max;
if (!(divider->flags & CLK_DIVIDER_ONE_BASED) &&
!(divider->flags & CLK_DIVIDER_POWER_OF_TWO))
max_val--;
}
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
mask = fls(max_val) - 1;
else
mask = max_val;
divider->mask = (1 << fls(mask)) - 1;
}
static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val)
{
if (divider->flags & CLK_DIVIDER_ONE_BASED)
return val;
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
return 1 << val;
if (divider->table)
return _get_table_div(divider->table, val);
return val + 1;
}
static unsigned int _get_table_val(const struct clk_div_table *table,
unsigned int div)
{
const struct clk_div_table *clkt;
for (clkt = table; clkt->div; clkt++)
if (clkt->div == div)
return clkt->val;
return 0;
}
static unsigned int _get_val(struct clk_omap_divider *divider, u8 div)
{
if (divider->flags & CLK_DIVIDER_ONE_BASED)
return div;
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
return __ffs(div);
if (divider->table)
return _get_table_val(divider->table, div);
return div - 1;
}
static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_omap_divider *divider = to_clk_omap_divider(hw);
unsigned int div, val;
val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift;
val &= divider->mask;
div = _get_div(divider, val);
if (!div) {
WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
clk_hw_get_name(hw));
return parent_rate;
}
return DIV_ROUND_UP(parent_rate, div);
}
/*
* The reverse of DIV_ROUND_UP: The maximum number which
* divided by m is r
*/
#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
static bool _is_valid_table_div(const struct clk_div_table *table,
unsigned int div)
{
const struct clk_div_table *clkt;
for (clkt = table; clkt->div; clkt++)
if (clkt->div == div)
return true;
return false;
}
static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div)
{
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
return is_power_of_2(div);
if (divider->table)
return _is_valid_table_div(divider->table, div);
return true;
}
static int _div_round_up(const struct clk_div_table *table,
unsigned long parent_rate, unsigned long rate)
{
const struct clk_div_table *clkt;
int up = INT_MAX;
int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
for (clkt = table; clkt->div; clkt++) {
if (clkt->div == div)
return clkt->div;
else if (clkt->div < div)
continue;
if ((clkt->div - div) < (up - div))
up = clkt->div;
}
return up;
}
static int _div_round(const struct clk_div_table *table,
unsigned long parent_rate, unsigned long rate)
{
if (!table)
return DIV_ROUND_UP(parent_rate, rate);
return _div_round_up(table, parent_rate, rate);
}
static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
unsigned long *best_parent_rate)
{
struct clk_omap_divider *divider = to_clk_omap_divider(hw);
int i, bestdiv = 0;
unsigned long parent_rate, best = 0, now, maxdiv;
unsigned long parent_rate_saved = *best_parent_rate;
if (!rate)
rate = 1;
maxdiv = divider->max;
if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
parent_rate = *best_parent_rate;
bestdiv = _div_round(divider->table, parent_rate, rate);
bestdiv = bestdiv == 0 ? 1 : bestdiv;
bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
return bestdiv;
}
/*
* The maximum divider we can use without overflowing
* unsigned long in rate * i below
*/
maxdiv = min(ULONG_MAX / rate, maxdiv);
for (i = 1; i <= maxdiv; i++) {
if (!_is_valid_div(divider, i))
continue;
if (rate * i == parent_rate_saved) {
/*
* It's the most ideal case if the requested rate can be
* divided from parent clock without needing to change
* parent rate, so return the divider immediately.
*/
*best_parent_rate = parent_rate_saved;
return i;
}
parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
MULT_ROUND_UP(rate, i));
now = DIV_ROUND_UP(parent_rate, i);
if (now <= rate && now > best) {
bestdiv = i;
best = now;
*best_parent_rate = parent_rate;
}
}
if (!bestdiv) {
bestdiv = divider->max;
*best_parent_rate =
clk_hw_round_rate(clk_hw_get_parent(hw), 1);
}
return bestdiv;
}
static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
int div;
div = ti_clk_divider_bestdiv(hw, rate, prate);
return DIV_ROUND_UP(*prate, div);
}
static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_omap_divider *divider;
unsigned int div, value;
u32 val;
if (!hw || !rate)
return -EINVAL;
divider = to_clk_omap_divider(hw);
div = DIV_ROUND_UP(parent_rate, rate);
if (div > divider->max)
div = divider->max;
if (div < divider->min)
div = divider->min;
value = _get_val(divider, div);
val = ti_clk_ll_ops->clk_readl(÷r->reg);
val &= ~(divider->mask << divider->shift);
val |= value << divider->shift;
ti_clk_ll_ops->clk_writel(val, ÷r->reg);
ti_clk_latch(÷r->reg, divider->latch);
return 0;
}
/**
* clk_divider_save_context - Save the divider value
* @hw: pointer struct clk_hw
*
* Save the divider value
*/
static int clk_divider_save_context(struct clk_hw *hw)
{
struct clk_omap_divider *divider = to_clk_omap_divider(hw);
u32 val;
val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift;
divider->context = val & divider->mask;
return 0;
}
/**
* clk_divider_restore_context - restore the saved the divider value
* @hw: pointer struct clk_hw
*
* Restore the saved the divider value
*/
static void clk_divider_restore_context(struct clk_hw *hw)
{
struct clk_omap_divider *divider = to_clk_omap_divider(hw);
u32 val;
val = ti_clk_ll_ops->clk_readl(÷r->reg);
val &= ~(divider->mask << divider->shift);
val |= divider->context << divider->shift;
ti_clk_ll_ops->clk_writel(val, ÷r->reg);
}
const struct clk_ops ti_clk_divider_ops = {
.recalc_rate = ti_clk_divider_recalc_rate,
.round_rate = ti_clk_divider_round_rate,
.set_rate = ti_clk_divider_set_rate,
.save_context = clk_divider_save_context,
.restore_context = clk_divider_restore_context,
};
static struct clk *_register_divider(struct device_node *node,
u32 flags,
struct clk_omap_divider *div)
{
struct clk *clk;
struct clk_init_data init;
const char *parent_name;
const char *name;
parent_name = of_clk_get_parent_name(node, 0);
name = ti_dt_clk_name(node);
init.name = name;
init.ops = &ti_clk_divider_ops;
init.flags = flags;
init.parent_names = (parent_name ? &parent_name : NULL);
init.num_parents = (parent_name ? 1 : 0);
div->hw.init = &init;
/* register the clock */
clk = of_ti_clk_register(node, &div->hw, name);
if (IS_ERR(clk))
kfree(div);
return clk;
}
int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
u8 flags, struct clk_omap_divider *divider)
{
int valid_div = 0;
int i;
struct clk_div_table *tmp;
u16 min_div = 0;
if (!div_table) {
divider->min = 1;
divider->max = max_div;
_setup_mask(divider);
return 0;
}
i = 0;
while (!num_dividers || i < num_dividers) {
if (div_table[i] == -1)
break;
if (div_table[i])
valid_div++;
i++;
}
num_dividers = i;
tmp = kcalloc(valid_div + 1, sizeof(*tmp), GFP_KERNEL);
if (!tmp)
return -ENOMEM;
valid_div = 0;
for (i = 0; i < num_dividers; i++)
if (div_table[i] > 0) {
tmp[valid_div].div = div_table[i];
tmp[valid_div].val = i;
valid_div++;
if (div_table[i] > max_div)
max_div = div_table[i];
if (!min_div || div_table[i] < min_div)
min_div = div_table[i];
}
divider->min = min_div;
divider->max = max_div;
divider->table = tmp;
_setup_mask(divider);
return 0;
}
static int __init ti_clk_get_div_table(struct device_node *node,
struct clk_omap_divider *div)
{
struct clk_div_table *table;
const __be32 *divspec;
u32 val;
u32 num_div;
u32 valid_div;
int i;
divspec = of_get_property(node, "ti,dividers", &num_div);
if (!divspec)
return 0;
num_div /= 4;
valid_div = 0;
/* Determine required size for divider table */
for (i = 0; i < num_div; i++) {
of_property_read_u32_index(node, "ti,dividers", i, &val);
if (val)
valid_div++;
}
if (!valid_div) {
pr_err("no valid dividers for %pOFn table\n", node);
return -EINVAL;
}
table = kcalloc(valid_div + 1, sizeof(*table), GFP_KERNEL);
if (!table)
return -ENOMEM;
valid_div = 0;
for (i = 0; i < num_div; i++) {
of_property_read_u32_index(node, "ti,dividers", i, &val);
if (val) {
table[valid_div].div = val;
table[valid_div].val = i;
valid_div++;
}
}
div->table = table;
return 0;
}
static int _populate_divider_min_max(struct device_node *node,
struct clk_omap_divider *divider)
{
u32 min_div = 0;
u32 max_div = 0;
u32 val;
const struct clk_div_table *clkt;
if (!divider->table) {
/* Clk divider table not provided, determine min/max divs */
if (of_property_read_u32(node, "ti,min-div", &min_div))
min_div = 1;
if (of_property_read_u32(node, "ti,max-div", &max_div)) {
pr_err("no max-div for %pOFn!\n", node);
return -EINVAL;
}
} else {
for (clkt = divider->table; clkt->div; clkt++) {
val = clkt->div;
if (val > max_div)
max_div = val;
if (!min_div || val < min_div)
min_div = val;
}
}
divider->min = min_div;
divider->max = max_div;
_setup_mask(divider);
return 0;
}
static int __init ti_clk_divider_populate(struct device_node *node,
struct clk_omap_divider *div,
u32 *flags)
{
u32 val;
int ret;
ret = ti_clk_get_reg_addr(node, 0, &div->reg);
if (ret)
return ret;
if (!of_property_read_u32(node, "ti,bit-shift", &val))
div->shift = val;
else
div->shift = 0;
if (!of_property_read_u32(node, "ti,latch-bit", &val))
div->latch = val;
else
div->latch = -EINVAL;
*flags = 0;
div->flags = 0;
if (of_property_read_bool(node, "ti,index-starts-at-one"))
div->flags |= CLK_DIVIDER_ONE_BASED;
if (of_property_read_bool(node, "ti,index-power-of-two"))
div->flags |= CLK_DIVIDER_POWER_OF_TWO;
if (of_property_read_bool(node, "ti,set-rate-parent"))
*flags |= CLK_SET_RATE_PARENT;
ret = ti_clk_get_div_table(node, div);
if (ret)
return ret;
return _populate_divider_min_max(node, div);
}
/**
* of_ti_divider_clk_setup - Setup function for simple div rate clock
* @node: device node for this clock
*
* Sets up a basic divider clock.
*/
static void __init of_ti_divider_clk_setup(struct device_node *node)
{
struct clk *clk;
u32 flags = 0;
struct clk_omap_divider *div;
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
return;
if (ti_clk_divider_populate(node, div, &flags))
goto cleanup;
clk = _register_divider(node, flags, div);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
of_ti_clk_autoidle_setup(node);
return;
}
cleanup:
kfree(div->table);
kfree(div);
}
CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
{
struct clk_omap_divider *div;
u32 tmp;
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
return;
if (ti_clk_divider_populate(node, div, &tmp))
goto cleanup;
if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
return;
cleanup:
kfree(div->table);
kfree(div);
}
CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
of_ti_composite_divider_clk_setup);
| linux-master | drivers/clk/ti/divider.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP3/4 - specific DPLL control functions
*
* Copyright (C) 2009-2010 Texas Instruments, Inc.
* Copyright (C) 2009-2010 Nokia Corporation
*
* Written by Paul Walmsley
* Testing and integration fixes by Jouni Högander
*
* 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
* Menon
*
* Parts of this code are based on code written by
* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
*/
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/clkdev.h>
#include <linux/clk/ti.h>
#include "clock.h"
/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
#define DPLL_AUTOIDLE_DISABLE 0x0
#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
#define MAX_DPLL_WAIT_TRIES 1000000
#define OMAP3XXX_EN_DPLL_LOCKED 0x7
/* Forward declarations */
static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
/* Private functions */
/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
{
const struct dpll_data *dd;
u32 v;
dd = clk->dpll_data;
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
v &= ~dd->enable_mask;
v |= clken_bits << __ffs(dd->enable_mask);
ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
}
/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
{
const struct dpll_data *dd;
int i = 0;
int ret = -EINVAL;
const char *clk_name;
dd = clk->dpll_data;
clk_name = clk_hw_get_name(&clk->hw);
state <<= __ffs(dd->idlest_mask);
while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask)
!= state) && i < MAX_DPLL_WAIT_TRIES) {
i++;
udelay(1);
}
if (i == MAX_DPLL_WAIT_TRIES) {
pr_err("clock: %s failed transition to '%s'\n",
clk_name, (state) ? "locked" : "bypassed");
} else {
pr_debug("clock: %s transition to '%s' in %d loops\n",
clk_name, (state) ? "locked" : "bypassed", i);
ret = 0;
}
return ret;
}
/* From 3430 TRM ES2 4.7.6.2 */
static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
{
unsigned long fint;
u16 f = 0;
fint = clk_hw_get_rate(clk->dpll_data->clk_ref) / n;
pr_debug("clock: fint is %lu\n", fint);
if (fint >= 750000 && fint <= 1000000)
f = 0x3;
else if (fint > 1000000 && fint <= 1250000)
f = 0x4;
else if (fint > 1250000 && fint <= 1500000)
f = 0x5;
else if (fint > 1500000 && fint <= 1750000)
f = 0x6;
else if (fint > 1750000 && fint <= 2100000)
f = 0x7;
else if (fint > 7500000 && fint <= 10000000)
f = 0xB;
else if (fint > 10000000 && fint <= 12500000)
f = 0xC;
else if (fint > 12500000 && fint <= 15000000)
f = 0xD;
else if (fint > 15000000 && fint <= 17500000)
f = 0xE;
else if (fint > 17500000 && fint <= 21000000)
f = 0xF;
else
pr_debug("clock: unknown freqsel setting for %d\n", n);
return f;
}
/**
* _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
* @clk: pointer to a DPLL struct clk
*
* Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
* readiness before returning. Will save and restore the DPLL's
* autoidle state across the enable, per the CDP code. If the DPLL
* locked successfully, return 0; if the DPLL did not lock in the time
* allotted, or DPLL3 was passed in, return -EINVAL.
*/
static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
{
const struct dpll_data *dd;
u8 ai;
u8 state = 1;
int r = 0;
pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw));
dd = clk->dpll_data;
state <<= __ffs(dd->idlest_mask);
/* Check if already locked */
if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) ==
state)
goto done;
ai = omap3_dpll_autoidle_read(clk);
if (ai)
omap3_dpll_deny_idle(clk);
_omap3_dpll_write_clken(clk, DPLL_LOCKED);
r = _omap3_wait_dpll_status(clk, 1);
if (ai)
omap3_dpll_allow_idle(clk);
done:
return r;
}
/**
* _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
* @clk: pointer to a DPLL struct clk
*
* Instructs a non-CORE DPLL to enter low-power bypass mode. In
* bypass mode, the DPLL's rate is set equal to its parent clock's
* rate. Waits for the DPLL to report readiness before returning.
* Will save and restore the DPLL's autoidle state across the enable,
* per the CDP code. If the DPLL entered bypass mode successfully,
* return 0; if the DPLL did not enter bypass in the time allotted, or
* DPLL3 was passed in, or the DPLL does not support low-power bypass,
* return -EINVAL.
*/
static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
{
int r;
u8 ai;
if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
return -EINVAL;
pr_debug("clock: configuring DPLL %s for low-power bypass\n",
clk_hw_get_name(&clk->hw));
ai = omap3_dpll_autoidle_read(clk);
_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
r = _omap3_wait_dpll_status(clk, 0);
if (ai)
omap3_dpll_allow_idle(clk);
return r;
}
/**
* _omap3_noncore_dpll_stop - instruct a DPLL to stop
* @clk: pointer to a DPLL struct clk
*
* Instructs a non-CORE DPLL to enter low-power stop. Will save and
* restore the DPLL's autoidle state across the stop, per the CDP
* code. If DPLL3 was passed in, or the DPLL does not support
* low-power stop, return -EINVAL; otherwise, return 0.
*/
static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
{
u8 ai;
if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
return -EINVAL;
pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw));
ai = omap3_dpll_autoidle_read(clk);
_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
if (ai)
omap3_dpll_allow_idle(clk);
return 0;
}
/**
* _lookup_dco - Lookup DCO used by j-type DPLL
* @clk: pointer to a DPLL struct clk
* @dco: digital control oscillator selector
* @m: DPLL multiplier to set
* @n: DPLL divider to set
*
* See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
*
* XXX This code is not needed for 3430/AM35xx; can it be optimized
* out in non-multi-OMAP builds for those chips?
*/
static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
{
unsigned long fint, clkinp; /* watch out for overflow */
clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
fint = (clkinp / n) * m;
if (fint < 1000000000)
*dco = 2;
else
*dco = 4;
}
/**
* _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
* @clk: pointer to a DPLL struct clk
* @sd_div: target sigma-delta divider
* @m: DPLL multiplier to set
* @n: DPLL divider to set
*
* See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
*
* XXX This code is not needed for 3430/AM35xx; can it be optimized
* out in non-multi-OMAP builds for those chips?
*/
static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
{
unsigned long clkinp, sd; /* watch out for overflow */
int mod1, mod2;
clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
/*
* target sigma-delta to near 250MHz
* sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
*/
clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
mod1 = (clkinp * m) % (250 * n);
sd = (clkinp * m) / (250 * n);
mod2 = sd % 10;
sd /= 10;
if (mod1 || mod2)
sd++;
*sd_div = sd;
}
/**
* omap3_noncore_dpll_ssc_program - set spread-spectrum clocking registers
* @clk: struct clk * of DPLL to set
*
* Enable the DPLL spread spectrum clocking if frequency modulation and
* frequency spreading have been set, otherwise disable it.
*/
static void omap3_noncore_dpll_ssc_program(struct clk_hw_omap *clk)
{
struct dpll_data *dd = clk->dpll_data;
unsigned long ref_rate;
u32 v, ctrl, mod_freq_divider, exponent, mantissa;
u32 deltam_step, deltam_ceil;
ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
if (dd->ssc_modfreq && dd->ssc_deltam) {
ctrl |= dd->ssc_enable_mask;
if (dd->ssc_downspread)
ctrl |= dd->ssc_downspread_mask;
else
ctrl &= ~dd->ssc_downspread_mask;
ref_rate = clk_hw_get_rate(dd->clk_ref);
mod_freq_divider =
(ref_rate / dd->last_rounded_n) / (4 * dd->ssc_modfreq);
if (dd->ssc_modfreq > (ref_rate / 70))
pr_warn("clock: SSC modulation frequency of DPLL %s greater than %ld\n",
__clk_get_name(clk->hw.clk), ref_rate / 70);
exponent = 0;
mantissa = mod_freq_divider;
while ((mantissa > 127) && (exponent < 7)) {
exponent++;
mantissa /= 2;
}
if (mantissa > 127)
mantissa = 127;
v = ti_clk_ll_ops->clk_readl(&dd->ssc_modfreq_reg);
v &= ~(dd->ssc_modfreq_mant_mask | dd->ssc_modfreq_exp_mask);
v |= mantissa << __ffs(dd->ssc_modfreq_mant_mask);
v |= exponent << __ffs(dd->ssc_modfreq_exp_mask);
ti_clk_ll_ops->clk_writel(v, &dd->ssc_modfreq_reg);
deltam_step = dd->last_rounded_m * dd->ssc_deltam;
deltam_step /= 10;
if (dd->ssc_downspread)
deltam_step /= 2;
deltam_step <<= __ffs(dd->ssc_deltam_int_mask);
deltam_step /= 100;
deltam_step /= mod_freq_divider;
if (deltam_step > 0xFFFFF)
deltam_step = 0xFFFFF;
deltam_ceil = (deltam_step & dd->ssc_deltam_int_mask) >>
__ffs(dd->ssc_deltam_int_mask);
if (deltam_step & dd->ssc_deltam_frac_mask)
deltam_ceil++;
if ((dd->ssc_downspread &&
((dd->last_rounded_m - (2 * deltam_ceil)) < 20 ||
dd->last_rounded_m > 2045)) ||
((dd->last_rounded_m - deltam_ceil) < 20 ||
(dd->last_rounded_m + deltam_ceil) > 2045))
pr_warn("clock: SSC multiplier of DPLL %s is out of range\n",
__clk_get_name(clk->hw.clk));
v = ti_clk_ll_ops->clk_readl(&dd->ssc_deltam_reg);
v &= ~(dd->ssc_deltam_int_mask | dd->ssc_deltam_frac_mask);
v |= deltam_step << __ffs(dd->ssc_deltam_int_mask |
dd->ssc_deltam_frac_mask);
ti_clk_ll_ops->clk_writel(v, &dd->ssc_deltam_reg);
} else {
ctrl &= ~dd->ssc_enable_mask;
}
ti_clk_ll_ops->clk_writel(ctrl, &dd->control_reg);
}
/**
* omap3_noncore_dpll_program - set non-core DPLL M,N values directly
* @clk: struct clk * of DPLL to set
* @freqsel: FREQSEL value to set
*
* Program the DPLL with the last M, N values calculated, and wait for
* the DPLL to lock. Returns -EINVAL upon error, or 0 upon success.
*/
static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
{
struct dpll_data *dd = clk->dpll_data;
u8 dco, sd_div, ai = 0;
u32 v;
bool errata_i810;
/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
_omap3_noncore_dpll_bypass(clk);
/*
* Set jitter correction. Jitter correction applicable for OMAP343X
* only since freqsel field is no longer present on other devices.
*/
if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
v &= ~dd->freqsel_mask;
v |= freqsel << __ffs(dd->freqsel_mask);
ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
}
/* Set DPLL multiplier, divider */
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
/* Handle Duty Cycle Correction */
if (dd->dcc_mask) {
if (dd->last_rounded_rate >= dd->dcc_rate)
v |= dd->dcc_mask; /* Enable DCC */
else
v &= ~dd->dcc_mask; /* Disable DCC */
}
v &= ~(dd->mult_mask | dd->div1_mask);
v |= dd->last_rounded_m << __ffs(dd->mult_mask);
v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
/* Configure dco and sd_div for dplls that have these fields */
if (dd->dco_mask) {
_lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);
v &= ~(dd->dco_mask);
v |= dco << __ffs(dd->dco_mask);
}
if (dd->sddiv_mask) {
_lookup_sddiv(clk, &sd_div, dd->last_rounded_m,
dd->last_rounded_n);
v &= ~(dd->sddiv_mask);
v |= sd_div << __ffs(dd->sddiv_mask);
}
/*
* Errata i810 - DPLL controller can get stuck while transitioning
* to a power saving state. Software must ensure the DPLL can not
* transition to a low power state while changing M/N values.
* Easiest way to accomplish this is to prevent DPLL autoidle
* before doing the M/N re-program.
*/
errata_i810 = ti_clk_get_features()->flags & TI_CLK_ERRATA_I810;
if (errata_i810) {
ai = omap3_dpll_autoidle_read(clk);
if (ai) {
omap3_dpll_deny_idle(clk);
/* OCP barrier */
omap3_dpll_autoidle_read(clk);
}
}
ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
/* Set 4X multiplier and low-power mode */
if (dd->m4xen_mask || dd->lpmode_mask) {
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
if (dd->m4xen_mask) {
if (dd->last_rounded_m4xen)
v |= dd->m4xen_mask;
else
v &= ~dd->m4xen_mask;
}
if (dd->lpmode_mask) {
if (dd->last_rounded_lpmode)
v |= dd->lpmode_mask;
else
v &= ~dd->lpmode_mask;
}
ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
}
if (dd->ssc_enable_mask)
omap3_noncore_dpll_ssc_program(clk);
/* We let the clock framework set the other output dividers later */
/* REVISIT: Set ramp-up delay? */
_omap3_noncore_dpll_lock(clk);
if (errata_i810 && ai)
omap3_dpll_allow_idle(clk);
return 0;
}
/* Public functions */
/**
* omap3_dpll_recalc - recalculate DPLL rate
* @hw: struct clk_hw containing the DPLL struct clk
* @parent_rate: clock rate of the DPLL parent
*
* Recalculate and propagate the DPLL rate.
*/
unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
return omap2_get_dpll_rate(clk);
}
/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
/**
* omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
* @hw: struct clk_hw containing then pointer to a DPLL struct clk
*
* Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
* The choice of modes depends on the DPLL's programmed rate: if it is
* the same as the DPLL's parent clock, it will enter bypass;
* otherwise, it will enter lock. This code will wait for the DPLL to
* indicate readiness before returning, unless the DPLL takes too long
* to enter the target state. Intended to be used as the struct clk's
* enable function. If DPLL3 was passed in, or the DPLL does not
* support low-power stop, or if the DPLL took too long to enter
* bypass or lock, return -EINVAL; otherwise, return 0.
*/
int omap3_noncore_dpll_enable(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
int r;
struct dpll_data *dd;
struct clk_hw *parent;
dd = clk->dpll_data;
if (!dd)
return -EINVAL;
if (clk->clkdm) {
r = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
if (r) {
WARN(1,
"%s: could not enable %s's clockdomain %s: %d\n",
__func__, clk_hw_get_name(hw),
clk->clkdm_name, r);
return r;
}
}
parent = clk_hw_get_parent(hw);
if (clk_hw_get_rate(hw) == clk_hw_get_rate(dd->clk_bypass)) {
WARN_ON(parent != dd->clk_bypass);
r = _omap3_noncore_dpll_bypass(clk);
} else {
WARN_ON(parent != dd->clk_ref);
r = _omap3_noncore_dpll_lock(clk);
}
return r;
}
/**
* omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
* @hw: struct clk_hw containing then pointer to a DPLL struct clk
*
* Instructs a non-CORE DPLL to enter low-power stop. This function is
* intended for use in struct clkops. No return value.
*/
void omap3_noncore_dpll_disable(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
_omap3_noncore_dpll_stop(clk);
if (clk->clkdm)
ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
}
/* Non-CORE DPLL rate set code */
/**
* omap3_noncore_dpll_determine_rate - determine rate for a DPLL
* @hw: pointer to the clock to determine rate for
* @req: target rate request
*
* Determines which DPLL mode to use for reaching a desired target rate.
* Checks whether the DPLL shall be in bypass or locked mode, and if
* locked, calculates the M,N values for the DPLL via round-rate.
* Returns a 0 on success, negative error value in failure.
*/
int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
struct dpll_data *dd;
if (!req->rate)
return -EINVAL;
dd = clk->dpll_data;
if (!dd)
return -EINVAL;
if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&
(dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
req->best_parent_hw = dd->clk_bypass;
} else {
req->rate = omap2_dpll_round_rate(hw, req->rate,
&req->best_parent_rate);
req->best_parent_hw = dd->clk_ref;
}
req->best_parent_rate = req->rate;
return 0;
}
/**
* omap3_noncore_dpll_set_parent - set parent for a DPLL clock
* @hw: pointer to the clock to set parent for
* @index: parent index to select
*
* Sets parent for a DPLL clock. This sets the DPLL into bypass or
* locked mode. Returns 0 with success, negative error value otherwise.
*/
int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
int ret;
if (!hw)
return -EINVAL;
if (index)
ret = _omap3_noncore_dpll_bypass(clk);
else
ret = _omap3_noncore_dpll_lock(clk);
return ret;
}
/**
* omap3_noncore_dpll_set_rate - set rate for a DPLL clock
* @hw: pointer to the clock to set parent for
* @rate: target rate for the clock
* @parent_rate: rate of the parent clock
*
* Sets rate for a DPLL clock. First checks if the clock parent is
* reference clock (in bypass mode, the rate of the clock can't be
* changed) and proceeds with the rate change operation. Returns 0
* with success, negative error value otherwise.
*/
int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
struct dpll_data *dd;
u16 freqsel = 0;
int ret;
if (!hw || !rate)
return -EINVAL;
dd = clk->dpll_data;
if (!dd)
return -EINVAL;
if (clk_hw_get_parent(hw) != dd->clk_ref)
return -EINVAL;
if (dd->last_rounded_rate == 0)
return -EINVAL;
/* Freqsel is available only on OMAP343X devices */
if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
WARN_ON(!freqsel);
}
pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__,
clk_hw_get_name(hw), rate);
ret = omap3_noncore_dpll_program(clk, freqsel);
return ret;
}
/**
* omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock
* @hw: pointer to the clock to set rate and parent for
* @rate: target rate for the DPLL
* @parent_rate: clock rate of the DPLL parent
* @index: new parent index for the DPLL, 0 - reference, 1 - bypass
*
* Sets rate and parent for a DPLL clock. If new parent is the bypass
* clock, only selects the parent. Otherwise proceeds with a rate
* change, as this will effectively also change the parent as the
* DPLL is put into locked mode. Returns 0 with success, negative error
* value otherwise.
*/
int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate,
u8 index)
{
int ret;
if (!hw || !rate)
return -EINVAL;
/*
* clk-ref at index[0], in which case we only need to set rate,
* the parent will be changed automatically with the lock sequence.
* With clk-bypass case we only need to change parent.
*/
if (index)
ret = omap3_noncore_dpll_set_parent(hw, index);
else
ret = omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
return ret;
}
/* DPLL autoidle read/set code */
/**
* omap3_dpll_autoidle_read - read a DPLL's autoidle bits
* @clk: struct clk * of the DPLL to read
*
* Return the DPLL's autoidle bits, shifted down to bit 0. Returns
* -EINVAL if passed a null pointer or if the struct clk does not
* appear to refer to a DPLL.
*/
static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
{
const struct dpll_data *dd;
u32 v;
if (!clk || !clk->dpll_data)
return -EINVAL;
dd = clk->dpll_data;
if (!dd->autoidle_mask)
return -EINVAL;
v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
v &= dd->autoidle_mask;
v >>= __ffs(dd->autoidle_mask);
return v;
}
/**
* omap3_dpll_allow_idle - enable DPLL autoidle bits
* @clk: struct clk * of the DPLL to operate on
*
* Enable DPLL automatic idle control. This automatic idle mode
* switching takes effect only when the DPLL is locked, at least on
* OMAP3430. The DPLL will enter low-power stop when its downstream
* clocks are gated. No return value.
*/
static void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
{
const struct dpll_data *dd;
u32 v;
if (!clk || !clk->dpll_data)
return;
dd = clk->dpll_data;
if (!dd->autoidle_mask)
return;
/*
* REVISIT: CORE DPLL can optionally enter low-power bypass
* by writing 0x5 instead of 0x1. Add some mechanism to
* optionally enter this mode.
*/
v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
v &= ~dd->autoidle_mask;
v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
}
/**
* omap3_dpll_deny_idle - prevent DPLL from automatically idling
* @clk: struct clk * of the DPLL to operate on
*
* Disable DPLL automatic idle control. No return value.
*/
static void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
{
const struct dpll_data *dd;
u32 v;
if (!clk || !clk->dpll_data)
return;
dd = clk->dpll_data;
if (!dd->autoidle_mask)
return;
v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
v &= ~dd->autoidle_mask;
v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
}
/* Clock control for DPLL outputs */
/* Find the parent DPLL for the given clkoutx2 clock */
static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
{
struct clk_hw_omap *pclk = NULL;
/* Walk up the parents of clk, looking for a DPLL */
do {
do {
hw = clk_hw_get_parent(hw);
} while (hw && (!omap2_clk_is_hw_omap(hw)));
if (!hw)
break;
pclk = to_clk_hw_omap(hw);
} while (pclk && !pclk->dpll_data);
/* clk does not have a DPLL as a parent? error in the clock data */
if (!pclk) {
WARN_ON(1);
return NULL;
}
return pclk;
}
/**
* omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
* @hw: pointer struct clk_hw
* @parent_rate: clock rate of the DPLL parent
*
* Using parent clock DPLL data, look up DPLL state. If locked, set our
* rate to the dpll_clk * 2; otherwise, just use dpll_clk.
*/
unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
unsigned long parent_rate)
{
const struct dpll_data *dd;
unsigned long rate;
u32 v;
struct clk_hw_omap *pclk = NULL;
if (!parent_rate)
return 0;
pclk = omap3_find_clkoutx2_dpll(hw);
if (!pclk)
return 0;
dd = pclk->dpll_data;
WARN_ON(!dd->enable_mask);
v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask;
v >>= __ffs(dd->enable_mask);
if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
rate = parent_rate;
else
rate = parent_rate * 2;
return rate;
}
/**
* omap3_core_dpll_save_context - Save the m and n values of the divider
* @hw: pointer struct clk_hw
*
* Before the dpll registers are lost save the last rounded rate m and n
* and the enable mask.
*/
int omap3_core_dpll_save_context(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
struct dpll_data *dd;
u32 v;
dd = clk->dpll_data;
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
if (clk->context == DPLL_LOCKED) {
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
dd->last_rounded_m = (v & dd->mult_mask) >>
__ffs(dd->mult_mask);
dd->last_rounded_n = ((v & dd->div1_mask) >>
__ffs(dd->div1_mask)) + 1;
}
return 0;
}
/**
* omap3_core_dpll_restore_context - restore the m and n values of the divider
* @hw: pointer struct clk_hw
*
* Restore the last rounded rate m and n
* and the enable mask.
*/
void omap3_core_dpll_restore_context(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
const struct dpll_data *dd;
u32 v;
dd = clk->dpll_data;
if (clk->context == DPLL_LOCKED) {
_omap3_dpll_write_clken(clk, 0x4);
_omap3_wait_dpll_status(clk, 0);
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
v &= ~(dd->mult_mask | dd->div1_mask);
v |= dd->last_rounded_m << __ffs(dd->mult_mask);
v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
_omap3_dpll_write_clken(clk, DPLL_LOCKED);
_omap3_wait_dpll_status(clk, 1);
} else {
_omap3_dpll_write_clken(clk, clk->context);
}
}
/**
* omap3_non_core_dpll_save_context - Save the m and n values of the divider
* @hw: pointer struct clk_hw
*
* Before the dpll registers are lost save the last rounded rate m and n
* and the enable mask.
*/
int omap3_noncore_dpll_save_context(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
struct dpll_data *dd;
u32 v;
dd = clk->dpll_data;
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
if (clk->context == DPLL_LOCKED) {
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
dd->last_rounded_m = (v & dd->mult_mask) >>
__ffs(dd->mult_mask);
dd->last_rounded_n = ((v & dd->div1_mask) >>
__ffs(dd->div1_mask)) + 1;
}
return 0;
}
/**
* omap3_core_dpll_restore_context - restore the m and n values of the divider
* @hw: pointer struct clk_hw
*
* Restore the last rounded rate m and n
* and the enable mask.
*/
void omap3_noncore_dpll_restore_context(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
const struct dpll_data *dd;
u32 ctrl, mult_div1;
dd = clk->dpll_data;
ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
mult_div1 = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
if (clk->context == ((ctrl & dd->enable_mask) >>
__ffs(dd->enable_mask)) &&
dd->last_rounded_m == ((mult_div1 & dd->mult_mask) >>
__ffs(dd->mult_mask)) &&
dd->last_rounded_n == ((mult_div1 & dd->div1_mask) >>
__ffs(dd->div1_mask)) + 1) {
/* nothing to be done */
return;
}
if (clk->context == DPLL_LOCKED)
omap3_noncore_dpll_program(clk, 0);
else
_omap3_dpll_write_clken(clk, clk->context);
}
/* OMAP3/4 non-CORE DPLL clkops */
const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
.allow_idle = omap3_dpll_allow_idle,
.deny_idle = omap3_dpll_deny_idle,
};
/**
* omap3_dpll4_set_rate - set rate for omap3 per-dpll
* @hw: clock to change
* @rate: target rate for clock
* @parent_rate: clock rate of the DPLL parent
*
* Check if the current SoC supports the per-dpll reprogram operation
* or not, and then do the rate change if supported. Returns -EINVAL
* if not supported, 0 for success, and potential error codes from the
* clock rate change.
*/
int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
/*
* According to the 12-5 CDP code from TI, "Limitation 2.5"
* on 3430ES1 prevents us from changing DPLL multipliers or dividers
* on DPLL4.
*/
if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
return -EINVAL;
}
return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
}
/**
* omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll
* @hw: clock to change
* @rate: target rate for clock
* @parent_rate: rate of the parent clock
* @index: parent index, 0 - reference clock, 1 - bypass clock
*
* Check if the current SoC support the per-dpll reprogram operation
* or not, and then do the rate + parent change if supported. Returns
* -EINVAL if not supported, 0 for success, and potential error codes
* from the clock rate change.
*/
int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate, u8 index)
{
if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
return -EINVAL;
}
return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,
index);
}
/* Apply DM3730 errata sprz319 advisory 2.1. */
static bool omap3_dpll5_apply_errata(struct clk_hw *hw,
unsigned long parent_rate)
{
struct omap3_dpll5_settings {
unsigned int rate, m, n;
};
static const struct omap3_dpll5_settings precomputed[] = {
/*
* From DM3730 errata advisory 2.1, table 35 and 36.
* The N value is increased by 1 compared to the tables as the
* errata lists register values while last_rounded_field is the
* real divider value.
*/
{ 12000000, 80, 0 + 1 },
{ 13000000, 443, 5 + 1 },
{ 19200000, 50, 0 + 1 },
{ 26000000, 443, 11 + 1 },
{ 38400000, 25, 0 + 1 }
};
const struct omap3_dpll5_settings *d;
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
struct dpll_data *dd;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(precomputed); ++i) {
if (parent_rate == precomputed[i].rate)
break;
}
if (i == ARRAY_SIZE(precomputed))
return false;
d = &precomputed[i];
/* Update the M, N and rounded rate values and program the DPLL. */
dd = clk->dpll_data;
dd->last_rounded_m = d->m;
dd->last_rounded_n = d->n;
dd->last_rounded_rate = div_u64((u64)parent_rate * d->m, d->n);
omap3_noncore_dpll_program(clk, 0);
return true;
}
/**
* omap3_dpll5_set_rate - set rate for omap3 dpll5
* @hw: clock to change
* @rate: target rate for clock
* @parent_rate: rate of the parent clock
*
* Set rate for the DPLL5 clock. Apply the sprz319 advisory 2.1 on OMAP36xx if
* the DPLL is used for USB host (detected through the requested rate).
*/
int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
if (rate == OMAP3_DPLL5_FREQ_FOR_USBHOST * 8) {
if (omap3_dpll5_apply_errata(hw, parent_rate))
return 0;
}
return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
}
| linux-master | drivers/clk/ti/dpll3xxx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP clkctrl clock support
*
* Copyright (C) 2017 Texas Instruments, Inc.
*
* Tero Kristo <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include <linux/delay.h>
#include <linux/string_helpers.h>
#include <linux/timekeeping.h>
#include "clock.h"
#define NO_IDLEST 0
#define OMAP4_MODULEMODE_MASK 0x3
#define MODULEMODE_HWCTRL 0x1
#define MODULEMODE_SWCTRL 0x2
#define OMAP4_IDLEST_MASK (0x3 << 16)
#define OMAP4_IDLEST_SHIFT 16
#define OMAP4_STBYST_MASK BIT(18)
#define OMAP4_STBYST_SHIFT 18
#define CLKCTRL_IDLEST_FUNCTIONAL 0x0
#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
#define CLKCTRL_IDLEST_DISABLED 0x3
/* These timeouts are in us */
#define OMAP4_MAX_MODULE_READY_TIME 2000
#define OMAP4_MAX_MODULE_DISABLE_TIME 5000
static bool _early_timeout = true;
struct omap_clkctrl_provider {
void __iomem *base;
struct list_head clocks;
char *clkdm_name;
};
struct omap_clkctrl_clk {
struct clk_hw *clk;
u16 reg_offset;
int bit_offset;
struct list_head node;
};
union omap4_timeout {
u32 cycles;
ktime_t start;
};
static const struct omap_clkctrl_data default_clkctrl_data[] __initconst = {
{ 0 },
};
static u32 _omap4_idlest(u32 val)
{
val &= OMAP4_IDLEST_MASK;
val >>= OMAP4_IDLEST_SHIFT;
return val;
}
static bool _omap4_is_idle(u32 val)
{
val = _omap4_idlest(val);
return val == CLKCTRL_IDLEST_DISABLED;
}
static bool _omap4_is_ready(u32 val)
{
val = _omap4_idlest(val);
return val == CLKCTRL_IDLEST_FUNCTIONAL ||
val == CLKCTRL_IDLEST_INTERFACE_IDLE;
}
static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout)
{
/*
* There are two special cases where ktime_to_ns() can't be
* used to track the timeouts. First one is during early boot
* when the timers haven't been initialized yet. The second
* one is during suspend-resume cycle while timekeeping is
* being suspended / resumed. Clocksource for the system
* can be from a timer that requires pm_runtime access, which
* will eventually bring us here with timekeeping_suspended,
* during both suspend entry and resume paths. This happens
* at least on am43xx platform. Account for flakeyness
* with udelay() by multiplying the timeout value by 2.
*/
if (unlikely(_early_timeout || timekeeping_suspended)) {
if (time->cycles++ < timeout) {
udelay(1 * 2);
return false;
}
} else {
if (!ktime_to_ns(time->start)) {
time->start = ktime_get();
return false;
}
if (ktime_us_delta(ktime_get(), time->start) < timeout) {
cpu_relax();
return false;
}
}
return true;
}
static int __init _omap4_disable_early_timeout(void)
{
_early_timeout = false;
return 0;
}
arch_initcall(_omap4_disable_early_timeout);
static int _omap4_clkctrl_clk_enable(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
u32 val;
int ret;
union omap4_timeout timeout = { 0 };
if (clk->clkdm) {
ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
if (ret) {
WARN(1,
"%s: could not enable %s's clockdomain %s: %d\n",
__func__, clk_hw_get_name(hw),
clk->clkdm_name, ret);
return ret;
}
}
if (!clk->enable_bit)
return 0;
val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
val &= ~OMAP4_MODULEMODE_MASK;
val |= clk->enable_bit;
ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
if (test_bit(NO_IDLEST, &clk->flags))
return 0;
/* Wait until module is enabled */
while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
if (_omap4_is_timeout(&timeout, OMAP4_MAX_MODULE_READY_TIME)) {
pr_err("%s: failed to enable\n", clk_hw_get_name(hw));
return -EBUSY;
}
}
return 0;
}
static void _omap4_clkctrl_clk_disable(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
u32 val;
union omap4_timeout timeout = { 0 };
if (!clk->enable_bit)
goto exit;
val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
val &= ~OMAP4_MODULEMODE_MASK;
ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
if (test_bit(NO_IDLEST, &clk->flags))
goto exit;
/* Wait until module is disabled */
while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
if (_omap4_is_timeout(&timeout,
OMAP4_MAX_MODULE_DISABLE_TIME)) {
pr_err("%s: failed to disable\n", clk_hw_get_name(hw));
break;
}
}
exit:
if (clk->clkdm)
ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
}
static int _omap4_clkctrl_clk_is_enabled(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
u32 val;
val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
if (val & clk->enable_bit)
return 1;
return 0;
}
static const struct clk_ops omap4_clkctrl_clk_ops = {
.enable = _omap4_clkctrl_clk_enable,
.disable = _omap4_clkctrl_clk_disable,
.is_enabled = _omap4_clkctrl_clk_is_enabled,
.init = omap2_init_clk_clkdm,
};
static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
void *data)
{
struct omap_clkctrl_provider *provider = data;
struct omap_clkctrl_clk *entry = NULL, *iter;
if (clkspec->args_count != 2)
return ERR_PTR(-EINVAL);
pr_debug("%s: looking for %x:%x\n", __func__,
clkspec->args[0], clkspec->args[1]);
list_for_each_entry(iter, &provider->clocks, node) {
if (iter->reg_offset == clkspec->args[0] &&
iter->bit_offset == clkspec->args[1]) {
entry = iter;
break;
}
}
if (!entry)
return ERR_PTR(-EINVAL);
return entry->clk;
}
/* Get clkctrl clock base name based on clkctrl_name or dts node */
static const char * __init clkctrl_get_clock_name(struct device_node *np,
const char *clkctrl_name,
int offset, int index,
bool legacy_naming)
{
char *clock_name;
/* l4per-clkctrl:1234:0 style naming based on clkctrl_name */
if (clkctrl_name && !legacy_naming) {
clock_name = kasprintf(GFP_KERNEL, "%s-clkctrl:%04x:%d",
clkctrl_name, offset, index);
if (!clock_name)
return NULL;
strreplace(clock_name, '_', '-');
return clock_name;
}
/* l4per:1234:0 old style naming based on clkctrl_name */
if (clkctrl_name)
return kasprintf(GFP_KERNEL, "%s_cm:clk:%04x:%d",
clkctrl_name, offset, index);
/* l4per_cm:1234:0 old style naming based on parent node name */
if (legacy_naming)
return kasprintf(GFP_KERNEL, "%pOFn:clk:%04x:%d",
np->parent, offset, index);
/* l4per-clkctrl:1234:0 style naming based on node name */
return kasprintf(GFP_KERNEL, "%pOFn:%04x:%d", np, offset, index);
}
static int __init
_ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
struct device_node *node, struct clk_hw *clk_hw,
u16 offset, u8 bit, const char * const *parents,
int num_parents, const struct clk_ops *ops,
const char *clkctrl_name)
{
struct clk_init_data init = { NULL };
struct clk *clk;
struct omap_clkctrl_clk *clkctrl_clk;
int ret = 0;
init.name = clkctrl_get_clock_name(node, clkctrl_name, offset, bit,
ti_clk_get_features()->flags &
TI_CLK_CLKCTRL_COMPAT);
clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
if (!init.name || !clkctrl_clk) {
ret = -ENOMEM;
goto cleanup;
}
clk_hw->init = &init;
init.parent_names = parents;
init.num_parents = num_parents;
init.ops = ops;
init.flags = 0;
clk = of_ti_clk_register(node, clk_hw, init.name);
if (IS_ERR_OR_NULL(clk)) {
ret = -EINVAL;
goto cleanup;
}
clkctrl_clk->reg_offset = offset;
clkctrl_clk->bit_offset = bit;
clkctrl_clk->clk = clk_hw;
list_add(&clkctrl_clk->node, &provider->clocks);
return 0;
cleanup:
kfree(init.name);
kfree(clkctrl_clk);
return ret;
}
static void __init
_ti_clkctrl_setup_gate(struct omap_clkctrl_provider *provider,
struct device_node *node, u16 offset,
const struct omap_clkctrl_bit_data *data,
void __iomem *reg, const char *clkctrl_name)
{
struct clk_hw_omap *clk_hw;
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
if (!clk_hw)
return;
clk_hw->enable_bit = data->bit;
clk_hw->enable_reg.ptr = reg;
if (_ti_clkctrl_clk_register(provider, node, &clk_hw->hw, offset,
data->bit, data->parents, 1,
&omap_gate_clk_ops, clkctrl_name))
kfree(clk_hw);
}
static void __init
_ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider,
struct device_node *node, u16 offset,
const struct omap_clkctrl_bit_data *data,
void __iomem *reg, const char *clkctrl_name)
{
struct clk_omap_mux *mux;
int num_parents = 0;
const char * const *pname;
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
return;
pname = data->parents;
while (*pname) {
num_parents++;
pname++;
}
mux->mask = num_parents;
if (!(mux->flags & CLK_MUX_INDEX_ONE))
mux->mask--;
mux->mask = (1 << fls(mux->mask)) - 1;
mux->shift = data->bit;
mux->reg.ptr = reg;
if (_ti_clkctrl_clk_register(provider, node, &mux->hw, offset,
data->bit, data->parents, num_parents,
&ti_clk_mux_ops, clkctrl_name))
kfree(mux);
}
static void __init
_ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
struct device_node *node, u16 offset,
const struct omap_clkctrl_bit_data *data,
void __iomem *reg, const char *clkctrl_name)
{
struct clk_omap_divider *div;
const struct omap_clkctrl_div_data *div_data = data->data;
u8 div_flags = 0;
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
return;
div->reg.ptr = reg;
div->shift = data->bit;
div->flags = div_data->flags;
if (div->flags & CLK_DIVIDER_POWER_OF_TWO)
div_flags |= CLKF_INDEX_POWER_OF_TWO;
if (ti_clk_parse_divider_data((int *)div_data->dividers, 0,
div_data->max_div, div_flags,
div)) {
pr_err("%s: Data parsing for %pOF:%04x:%d failed\n", __func__,
node, offset, data->bit);
kfree(div);
return;
}
if (_ti_clkctrl_clk_register(provider, node, &div->hw, offset,
data->bit, data->parents, 1,
&ti_clk_divider_ops, clkctrl_name))
kfree(div);
}
static void __init
_ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider,
struct device_node *node,
const struct omap_clkctrl_reg_data *data,
void __iomem *reg, const char *clkctrl_name)
{
const struct omap_clkctrl_bit_data *bits = data->bit_data;
if (!bits)
return;
while (bits->bit) {
switch (bits->type) {
case TI_CLK_GATE:
_ti_clkctrl_setup_gate(provider, node, data->offset,
bits, reg, clkctrl_name);
break;
case TI_CLK_DIVIDER:
_ti_clkctrl_setup_div(provider, node, data->offset,
bits, reg, clkctrl_name);
break;
case TI_CLK_MUX:
_ti_clkctrl_setup_mux(provider, node, data->offset,
bits, reg, clkctrl_name);
break;
default:
pr_err("%s: bad subclk type: %d\n", __func__,
bits->type);
return;
}
bits++;
}
}
static void __init _clkctrl_add_provider(void *data,
struct device_node *np)
{
of_clk_add_hw_provider(np, _ti_omap4_clkctrl_xlate, data);
}
/*
* Get clock name based on "clock-output-names" property or the
* compatible property for clkctrl.
*/
static const char * __init clkctrl_get_name(struct device_node *np)
{
struct property *prop;
const int prefix_len = 11;
const char *compat;
const char *output;
const char *end;
char *name;
if (!of_property_read_string_index(np, "clock-output-names", 0,
&output)) {
int len;
len = strlen(output);
end = strstr(output, "_clkctrl");
if (end)
len -= strlen(end);
name = kstrndup(output, len, GFP_KERNEL);
return name;
}
of_property_for_each_string(np, "compatible", prop, compat) {
if (!strncmp("ti,clkctrl-", compat, prefix_len)) {
end = compat + prefix_len;
/* Two letter minimum name length for l3, l4 etc */
if (strnlen(end, 16) < 2)
continue;
name = kstrdup_and_replace(end, '-', '_', GFP_KERNEL);
if (!name)
continue;
return name;
}
}
return NULL;
}
static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
{
struct omap_clkctrl_provider *provider;
const struct omap_clkctrl_data *data = default_clkctrl_data;
const struct omap_clkctrl_reg_data *reg_data;
struct clk_init_data init = { NULL };
struct clk_hw_omap *hw;
struct clk *clk;
struct omap_clkctrl_clk *clkctrl_clk = NULL;
bool legacy_naming;
const char *clkctrl_name;
u32 addr;
int ret;
char *c;
u16 soc_mask = 0;
struct resource res;
of_address_to_resource(node, 0, &res);
addr = (u32)res.start;
#ifdef CONFIG_ARCH_OMAP4
if (of_machine_is_compatible("ti,omap4"))
data = omap4_clkctrl_data;
#endif
#ifdef CONFIG_SOC_OMAP5
if (of_machine_is_compatible("ti,omap5"))
data = omap5_clkctrl_data;
#endif
#ifdef CONFIG_SOC_DRA7XX
if (of_machine_is_compatible("ti,dra7"))
data = dra7_clkctrl_data;
if (of_machine_is_compatible("ti,dra72"))
soc_mask = CLKF_SOC_DRA72;
if (of_machine_is_compatible("ti,dra74"))
soc_mask = CLKF_SOC_DRA74;
if (of_machine_is_compatible("ti,dra76"))
soc_mask = CLKF_SOC_DRA76;
#endif
#ifdef CONFIG_SOC_AM33XX
if (of_machine_is_compatible("ti,am33xx"))
data = am3_clkctrl_data;
#endif
#ifdef CONFIG_SOC_AM43XX
if (of_machine_is_compatible("ti,am4372"))
data = am4_clkctrl_data;
if (of_machine_is_compatible("ti,am438x"))
data = am438x_clkctrl_data;
#endif
#ifdef CONFIG_SOC_TI81XX
if (of_machine_is_compatible("ti,dm814"))
data = dm814_clkctrl_data;
if (of_machine_is_compatible("ti,dm816"))
data = dm816_clkctrl_data;
#endif
if (ti_clk_get_features()->flags & TI_CLK_DEVICE_TYPE_GP)
soc_mask |= CLKF_SOC_NONSEC;
while (data->addr) {
if (addr == data->addr)
break;
data++;
}
if (!data->addr) {
pr_err("%pOF not found from clkctrl data.\n", node);
return;
}
provider = kzalloc(sizeof(*provider), GFP_KERNEL);
if (!provider)
return;
provider->base = of_iomap(node, 0);
legacy_naming = ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT;
clkctrl_name = clkctrl_get_name(node);
if (clkctrl_name) {
provider->clkdm_name = kasprintf(GFP_KERNEL,
"%s_clkdm", clkctrl_name);
if (!provider->clkdm_name) {
kfree(provider);
return;
}
goto clkdm_found;
}
/*
* The code below can be removed when all clkctrl nodes use domain
* specific compatible property and standard clock node naming
*/
if (legacy_naming) {
provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFnxxx", node->parent);
if (!provider->clkdm_name) {
kfree(provider);
return;
}
/*
* Create default clkdm name, replace _cm from end of parent
* node name with _clkdm
*/
provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0;
} else {
provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFn", node);
if (!provider->clkdm_name) {
kfree(provider);
return;
}
/*
* Create default clkdm name, replace _clkctrl from end of
* node name with _clkdm
*/
provider->clkdm_name[strlen(provider->clkdm_name) - 7] = 0;
}
strcat(provider->clkdm_name, "clkdm");
/* Replace any dash from the clkdm name with underscore */
c = provider->clkdm_name;
while (*c) {
if (*c == '-')
*c = '_';
c++;
}
clkdm_found:
INIT_LIST_HEAD(&provider->clocks);
/* Generate clocks */
reg_data = data->regs;
while (reg_data->parent) {
if ((reg_data->flags & CLKF_SOC_MASK) &&
(reg_data->flags & soc_mask) == 0) {
reg_data++;
continue;
}
hw = kzalloc(sizeof(*hw), GFP_KERNEL);
if (!hw)
return;
hw->enable_reg.ptr = provider->base + reg_data->offset;
_ti_clkctrl_setup_subclks(provider, node, reg_data,
hw->enable_reg.ptr, clkctrl_name);
if (reg_data->flags & CLKF_SW_SUP)
hw->enable_bit = MODULEMODE_SWCTRL;
if (reg_data->flags & CLKF_HW_SUP)
hw->enable_bit = MODULEMODE_HWCTRL;
if (reg_data->flags & CLKF_NO_IDLEST)
set_bit(NO_IDLEST, &hw->flags);
if (reg_data->clkdm_name)
hw->clkdm_name = reg_data->clkdm_name;
else
hw->clkdm_name = provider->clkdm_name;
init.parent_names = ®_data->parent;
init.num_parents = 1;
init.flags = 0;
if (reg_data->flags & CLKF_SET_RATE_PARENT)
init.flags |= CLK_SET_RATE_PARENT;
init.name = clkctrl_get_clock_name(node, clkctrl_name,
reg_data->offset, 0,
legacy_naming);
if (!init.name)
goto cleanup;
clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
if (!clkctrl_clk)
goto cleanup;
init.ops = &omap4_clkctrl_clk_ops;
hw->hw.init = &init;
clk = of_ti_clk_register_omap_hw(node, &hw->hw, init.name);
if (IS_ERR_OR_NULL(clk))
goto cleanup;
clkctrl_clk->reg_offset = reg_data->offset;
clkctrl_clk->clk = &hw->hw;
list_add(&clkctrl_clk->node, &provider->clocks);
reg_data++;
}
ret = of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider);
if (ret == -EPROBE_DEFER)
ti_clk_retry_init(node, provider, _clkctrl_add_provider);
kfree(clkctrl_name);
return;
cleanup:
kfree(hw);
kfree(init.name);
kfree(clkctrl_name);
kfree(clkctrl_clk);
}
CLK_OF_DECLARE(ti_omap4_clkctrl_clock, "ti,clkctrl",
_ti_omap4_clkctrl_setup);
/**
* ti_clk_is_in_standby - Check if clkctrl clock is in standby or not
* @clk: clock to check standby status for
*
* Finds whether the provided clock is in standby mode or not. Returns
* true if the provided clock is a clkctrl type clock and it is in standby,
* false otherwise.
*/
bool ti_clk_is_in_standby(struct clk *clk)
{
struct clk_hw *hw;
struct clk_hw_omap *hwclk;
u32 val;
hw = __clk_get_hw(clk);
if (!omap2_clk_is_hw_omap(hw))
return false;
hwclk = to_clk_hw_omap(hw);
val = ti_clk_ll_ops->clk_readl(&hwclk->enable_reg);
if (val & OMAP4_STBYST_MASK)
return true;
return false;
}
EXPORT_SYMBOL_GPL(ti_clk_is_in_standby);
| linux-master | drivers/clk/ti/clkctrl.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI clock autoidle support
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"
struct clk_ti_autoidle {
struct clk_omap_reg reg;
u8 shift;
u8 flags;
const char *name;
struct list_head node;
};
#define AUTOIDLE_LOW 0x1
static LIST_HEAD(autoidle_clks);
/*
* we have some non-atomic read/write
* operations behind it, so lets
* take one lock for handling autoidle
* of all clocks
*/
static DEFINE_SPINLOCK(autoidle_spinlock);
static int _omap2_clk_deny_idle(struct clk_hw_omap *clk)
{
if (clk->ops && clk->ops->deny_idle) {
unsigned long irqflags;
spin_lock_irqsave(&autoidle_spinlock, irqflags);
clk->autoidle_count++;
if (clk->autoidle_count == 1)
clk->ops->deny_idle(clk);
spin_unlock_irqrestore(&autoidle_spinlock, irqflags);
}
return 0;
}
static int _omap2_clk_allow_idle(struct clk_hw_omap *clk)
{
if (clk->ops && clk->ops->allow_idle) {
unsigned long irqflags;
spin_lock_irqsave(&autoidle_spinlock, irqflags);
clk->autoidle_count--;
if (clk->autoidle_count == 0)
clk->ops->allow_idle(clk);
spin_unlock_irqrestore(&autoidle_spinlock, irqflags);
}
return 0;
}
/**
* omap2_clk_deny_idle - disable autoidle on an OMAP clock
* @clk: struct clk * to disable autoidle for
*
* Disable autoidle on an OMAP clock.
*/
int omap2_clk_deny_idle(struct clk *clk)
{
struct clk_hw *hw;
if (!clk)
return -EINVAL;
hw = __clk_get_hw(clk);
if (omap2_clk_is_hw_omap(hw)) {
struct clk_hw_omap *c = to_clk_hw_omap(hw);
return _omap2_clk_deny_idle(c);
}
return -EINVAL;
}
/**
* omap2_clk_allow_idle - enable autoidle on an OMAP clock
* @clk: struct clk * to enable autoidle for
*
* Enable autoidle on an OMAP clock.
*/
int omap2_clk_allow_idle(struct clk *clk)
{
struct clk_hw *hw;
if (!clk)
return -EINVAL;
hw = __clk_get_hw(clk);
if (omap2_clk_is_hw_omap(hw)) {
struct clk_hw_omap *c = to_clk_hw_omap(hw);
return _omap2_clk_allow_idle(c);
}
return -EINVAL;
}
static void _allow_autoidle(struct clk_ti_autoidle *clk)
{
u32 val;
val = ti_clk_ll_ops->clk_readl(&clk->reg);
if (clk->flags & AUTOIDLE_LOW)
val &= ~(1 << clk->shift);
else
val |= (1 << clk->shift);
ti_clk_ll_ops->clk_writel(val, &clk->reg);
}
static void _deny_autoidle(struct clk_ti_autoidle *clk)
{
u32 val;
val = ti_clk_ll_ops->clk_readl(&clk->reg);
if (clk->flags & AUTOIDLE_LOW)
val |= (1 << clk->shift);
else
val &= ~(1 << clk->shift);
ti_clk_ll_ops->clk_writel(val, &clk->reg);
}
/**
* _clk_generic_allow_autoidle_all - enable autoidle for all clocks
*
* Enables hardware autoidle for all registered DT clocks, which have
* the feature.
*/
static void _clk_generic_allow_autoidle_all(void)
{
struct clk_ti_autoidle *c;
list_for_each_entry(c, &autoidle_clks, node)
_allow_autoidle(c);
}
/**
* _clk_generic_deny_autoidle_all - disable autoidle for all clocks
*
* Disables hardware autoidle for all registered DT clocks, which have
* the feature.
*/
static void _clk_generic_deny_autoidle_all(void)
{
struct clk_ti_autoidle *c;
list_for_each_entry(c, &autoidle_clks, node)
_deny_autoidle(c);
}
/**
* of_ti_clk_autoidle_setup - sets up hardware autoidle for a clock
* @node: pointer to the clock device node
*
* Checks if a clock has hardware autoidle support or not (check
* for presence of 'ti,autoidle-shift' property in the device tree
* node) and sets up the hardware autoidle feature for the clock
* if available. If autoidle is available, the clock is also added
* to the autoidle list for later processing. Returns 0 on success,
* negative error value on failure.
*/
int __init of_ti_clk_autoidle_setup(struct device_node *node)
{
u32 shift;
struct clk_ti_autoidle *clk;
int ret;
/* Check if this clock has autoidle support or not */
if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
return 0;
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
if (!clk)
return -ENOMEM;
clk->shift = shift;
clk->name = ti_dt_clk_name(node);
ret = ti_clk_get_reg_addr(node, 0, &clk->reg);
if (ret) {
kfree(clk);
return ret;
}
if (of_property_read_bool(node, "ti,invert-autoidle-bit"))
clk->flags |= AUTOIDLE_LOW;
list_add(&clk->node, &autoidle_clks);
return 0;
}
/**
* omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that
* support it
*
* Enable clock autoidle on all OMAP clocks that have allow_idle
* function pointers associated with them. This function is intended
* to be temporary until support for this is added to the common clock
* code. Returns 0.
*/
int omap2_clk_enable_autoidle_all(void)
{
int ret;
ret = omap2_clk_for_each(_omap2_clk_allow_idle);
if (ret)
return ret;
_clk_generic_allow_autoidle_all();
return 0;
}
/**
* omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that
* support it
*
* Disable clock autoidle on all OMAP clocks that have allow_idle
* function pointers associated with them. This function is intended
* to be temporary until support for this is added to the common clock
* code. Returns 0.
*/
int omap2_clk_disable_autoidle_all(void)
{
int ret;
ret = omap2_clk_for_each(_omap2_clk_deny_idle);
if (ret)
return ret;
_clk_generic_deny_autoidle_all();
return 0;
}
| linux-master | drivers/clk/ti/autoidle.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI composite clock support
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include <linux/list.h>
#include "clock.h"
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
return ti_clk_divider_ops.recalc_rate(hw, parent_rate);
}
static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
return -EINVAL;
}
static int ti_composite_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
return -EINVAL;
}
static const struct clk_ops ti_composite_divider_ops = {
.recalc_rate = &ti_composite_recalc_rate,
.round_rate = &ti_composite_round_rate,
.set_rate = &ti_composite_set_rate,
};
static const struct clk_ops ti_composite_gate_ops = {
.enable = &omap2_dflt_clk_enable,
.disable = &omap2_dflt_clk_disable,
.is_enabled = &omap2_dflt_clk_is_enabled,
};
struct component_clk {
int num_parents;
const char **parent_names;
struct device_node *node;
int type;
struct clk_hw *hw;
struct list_head link;
};
static const char * const component_clk_types[] __initconst = {
"gate", "divider", "mux"
};
static LIST_HEAD(component_clks);
static struct device_node *_get_component_node(struct device_node *node, int i)
{
int rc;
struct of_phandle_args clkspec;
rc = of_parse_phandle_with_args(node, "clocks", "#clock-cells", i,
&clkspec);
if (rc)
return NULL;
return clkspec.np;
}
static struct component_clk *_lookup_component(struct device_node *node)
{
struct component_clk *comp;
list_for_each_entry(comp, &component_clks, link) {
if (comp->node == node)
return comp;
}
return NULL;
}
struct clk_hw_omap_comp {
struct clk_hw hw;
struct device_node *comp_nodes[CLK_COMPONENT_TYPE_MAX];
struct component_clk *comp_clks[CLK_COMPONENT_TYPE_MAX];
};
static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx)
{
if (!clk)
return NULL;
if (!clk->comp_clks[idx])
return NULL;
return clk->comp_clks[idx]->hw;
}
#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw)
static void __init _register_composite(void *user,
struct device_node *node)
{
struct clk_hw *hw = user;
struct clk *clk;
struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
struct component_clk *comp;
int num_parents = 0;
const char **parent_names = NULL;
const char *name;
int i;
int ret;
/* Check for presence of each component clock */
for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
if (!cclk->comp_nodes[i])
continue;
comp = _lookup_component(cclk->comp_nodes[i]);
if (!comp) {
pr_debug("component %s not ready for %pOFn, retry\n",
cclk->comp_nodes[i]->name, node);
if (!ti_clk_retry_init(node, hw,
_register_composite))
return;
goto cleanup;
}
if (cclk->comp_clks[comp->type] != NULL) {
pr_err("duplicate component types for %pOFn (%s)!\n",
node, component_clk_types[comp->type]);
goto cleanup;
}
cclk->comp_clks[comp->type] = comp;
/* Mark this node as found */
cclk->comp_nodes[i] = NULL;
}
/* All components exists, proceed with registration */
for (i = CLK_COMPONENT_TYPE_MAX - 1; i >= 0; i--) {
comp = cclk->comp_clks[i];
if (!comp)
continue;
if (comp->num_parents) {
num_parents = comp->num_parents;
parent_names = comp->parent_names;
break;
}
}
if (!num_parents) {
pr_err("%s: no parents found for %pOFn!\n", __func__, node);
goto cleanup;
}
name = ti_dt_clk_name(node);
clk = clk_register_composite(NULL, name,
parent_names, num_parents,
_get_hw(cclk, CLK_COMPONENT_TYPE_MUX),
&ti_clk_mux_ops,
_get_hw(cclk, CLK_COMPONENT_TYPE_DIVIDER),
&ti_composite_divider_ops,
_get_hw(cclk, CLK_COMPONENT_TYPE_GATE),
&ti_composite_gate_ops, 0);
if (!IS_ERR(clk)) {
ret = ti_clk_add_alias(clk, name);
if (ret) {
clk_unregister(clk);
goto cleanup;
}
of_clk_add_provider(node, of_clk_src_simple_get, clk);
}
cleanup:
/* Free component clock list entries */
for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
if (!cclk->comp_clks[i])
continue;
list_del(&cclk->comp_clks[i]->link);
kfree(cclk->comp_clks[i]->parent_names);
kfree(cclk->comp_clks[i]);
}
kfree(cclk);
}
static void __init of_ti_composite_clk_setup(struct device_node *node)
{
unsigned int num_clks;
int i;
struct clk_hw_omap_comp *cclk;
/* Number of component clocks to be put inside this clock */
num_clks = of_clk_get_parent_count(node);
if (!num_clks) {
pr_err("composite clk %pOFn must have component(s)\n", node);
return;
}
cclk = kzalloc(sizeof(*cclk), GFP_KERNEL);
if (!cclk)
return;
/* Get device node pointers for each component clock */
for (i = 0; i < num_clks; i++)
cclk->comp_nodes[i] = _get_component_node(node, i);
_register_composite(&cclk->hw, node);
}
CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock",
of_ti_composite_clk_setup);
/**
* ti_clk_add_component - add a component clock to the pool
* @node: device node of the component clock
* @hw: hardware clock definition for the component clock
* @type: type of the component clock
*
* Adds a component clock to the list of available components, so that
* it can be registered by a composite clock.
*/
int __init ti_clk_add_component(struct device_node *node, struct clk_hw *hw,
int type)
{
unsigned int num_parents;
const char **parent_names;
struct component_clk *clk;
num_parents = of_clk_get_parent_count(node);
if (!num_parents) {
pr_err("component-clock %pOFn must have parent(s)\n", node);
return -EINVAL;
}
parent_names = kcalloc(num_parents, sizeof(char *), GFP_KERNEL);
if (!parent_names)
return -ENOMEM;
of_clk_parent_fill(node, parent_names, num_parents);
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
if (!clk) {
kfree(parent_names);
return -ENOMEM;
}
clk->num_parents = num_parents;
clk->parent_names = parent_names;
clk->hw = hw;
clk->node = node;
clk->type = type;
list_add(&clk->link, &component_clks);
return 0;
}
| linux-master | drivers/clk/ti/composite.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI clock support
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clk/ti.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/list.h>
#include <linux/regmap.h>
#include <linux/string_helpers.h>
#include <linux/memblock.h>
#include <linux/device.h>
#include "clock.h"
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
static LIST_HEAD(clk_hw_omap_clocks);
struct ti_clk_ll_ops *ti_clk_ll_ops;
static struct device_node *clocks_node_ptr[CLK_MAX_MEMMAPS];
struct ti_clk_features ti_clk_features;
struct clk_iomap {
struct regmap *regmap;
void __iomem *mem;
};
static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS];
static void clk_memmap_writel(u32 val, const struct clk_omap_reg *reg)
{
struct clk_iomap *io = clk_memmaps[reg->index];
if (reg->ptr)
writel_relaxed(val, reg->ptr);
else if (io->regmap)
regmap_write(io->regmap, reg->offset, val);
else
writel_relaxed(val, io->mem + reg->offset);
}
static void _clk_rmw(u32 val, u32 mask, void __iomem *ptr)
{
u32 v;
v = readl_relaxed(ptr);
v &= ~mask;
v |= val;
writel_relaxed(v, ptr);
}
static void clk_memmap_rmw(u32 val, u32 mask, const struct clk_omap_reg *reg)
{
struct clk_iomap *io = clk_memmaps[reg->index];
if (reg->ptr) {
_clk_rmw(val, mask, reg->ptr);
} else if (io->regmap) {
regmap_update_bits(io->regmap, reg->offset, mask, val);
} else {
_clk_rmw(val, mask, io->mem + reg->offset);
}
}
static u32 clk_memmap_readl(const struct clk_omap_reg *reg)
{
u32 val;
struct clk_iomap *io = clk_memmaps[reg->index];
if (reg->ptr)
val = readl_relaxed(reg->ptr);
else if (io->regmap)
regmap_read(io->regmap, reg->offset, &val);
else
val = readl_relaxed(io->mem + reg->offset);
return val;
}
/**
* ti_clk_setup_ll_ops - setup low level clock operations
* @ops: low level clock ops descriptor
*
* Sets up low level clock operations for TI clock driver. This is used
* to provide various callbacks for the clock driver towards platform
* specific code. Returns 0 on success, -EBUSY if ll_ops have been
* registered already.
*/
int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops)
{
if (ti_clk_ll_ops) {
pr_err("Attempt to register ll_ops multiple times.\n");
return -EBUSY;
}
ti_clk_ll_ops = ops;
ops->clk_readl = clk_memmap_readl;
ops->clk_writel = clk_memmap_writel;
ops->clk_rmw = clk_memmap_rmw;
return 0;
}
/*
* Eventually we could standardize to using '_' for clk-*.c files to follow the
* TRM naming and leave out the tmp name here.
*/
static struct device_node *ti_find_clock_provider(struct device_node *from,
const char *name)
{
struct device_node *np;
bool found = false;
const char *n;
char *tmp;
tmp = kstrdup_and_replace(name, '-', '_', GFP_KERNEL);
if (!tmp)
return NULL;
/* Node named "clock" with "clock-output-names" */
for_each_of_allnodes_from(from, np) {
if (of_property_read_string_index(np, "clock-output-names",
0, &n))
continue;
if (!strncmp(n, tmp, strlen(tmp))) {
of_node_get(np);
found = true;
break;
}
}
kfree(tmp);
if (found) {
of_node_put(from);
return np;
}
/* Fall back to using old node name base provider name */
return of_find_node_by_name(from, name);
}
/**
* ti_dt_clocks_register - register DT alias clocks during boot
* @oclks: list of clocks to register
*
* Register alias or non-standard DT clock entries during boot. By
* default, DT clocks are found based on their clock-output-names
* property, or the clock node name for legacy cases. If any
* additional con-id / dev-id -> clock mapping is required, use this
* function to list these.
*/
void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
{
struct ti_dt_clk *c;
struct device_node *node, *parent, *child;
struct clk *clk;
struct of_phandle_args clkspec;
char buf[64];
char *ptr;
char *tags[2];
int i;
int num_args;
int ret;
static bool clkctrl_nodes_missing;
static bool has_clkctrl_data;
static bool compat_mode;
compat_mode = ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT;
for (c = oclks; c->node_name != NULL; c++) {
strcpy(buf, c->node_name);
ptr = buf;
for (i = 0; i < 2; i++)
tags[i] = NULL;
num_args = 0;
while (*ptr) {
if (*ptr == ':') {
if (num_args >= 2) {
pr_warn("Bad number of tags on %s\n",
c->node_name);
return;
}
tags[num_args++] = ptr + 1;
*ptr = 0;
}
ptr++;
}
if (num_args && clkctrl_nodes_missing)
continue;
node = ti_find_clock_provider(NULL, buf);
if (num_args && compat_mode) {
parent = node;
child = of_get_child_by_name(parent, "clock");
if (!child)
child = of_get_child_by_name(parent, "clk");
if (child) {
of_node_put(parent);
node = child;
}
}
clkspec.np = node;
clkspec.args_count = num_args;
for (i = 0; i < num_args; i++) {
ret = kstrtoint(tags[i], i ? 10 : 16, clkspec.args + i);
if (ret) {
pr_warn("Bad tag in %s at %d: %s\n",
c->node_name, i, tags[i]);
of_node_put(node);
return;
}
}
clk = of_clk_get_from_provider(&clkspec);
of_node_put(node);
if (!IS_ERR(clk)) {
c->lk.clk = clk;
clkdev_add(&c->lk);
} else {
if (num_args && !has_clkctrl_data) {
struct device_node *np;
np = of_find_compatible_node(NULL, NULL,
"ti,clkctrl");
if (np) {
has_clkctrl_data = true;
of_node_put(np);
} else {
clkctrl_nodes_missing = true;
pr_warn("missing clkctrl nodes, please update your dts.\n");
continue;
}
}
pr_warn("failed to lookup clock node %s, ret=%ld\n",
c->node_name, PTR_ERR(clk));
}
}
}
struct clk_init_item {
struct device_node *node;
void *user;
ti_of_clk_init_cb_t func;
struct list_head link;
};
static LIST_HEAD(retry_list);
/**
* ti_clk_retry_init - retries a failed clock init at later phase
* @node: device node for the clock
* @user: user data pointer
* @func: init function to be called for the clock
*
* Adds a failed clock init to the retry list. The retry list is parsed
* once all the other clocks have been initialized.
*/
int __init ti_clk_retry_init(struct device_node *node, void *user,
ti_of_clk_init_cb_t func)
{
struct clk_init_item *retry;
pr_debug("%pOFn: adding to retry list...\n", node);
retry = kzalloc(sizeof(*retry), GFP_KERNEL);
if (!retry)
return -ENOMEM;
retry->node = node;
retry->func = func;
retry->user = user;
list_add(&retry->link, &retry_list);
return 0;
}
/**
* ti_clk_get_reg_addr - get register address for a clock register
* @node: device node for the clock
* @index: register index from the clock node
* @reg: pointer to target register struct
*
* Builds clock register address from device tree information, and returns
* the data via the provided output pointer @reg. Returns 0 on success,
* negative error value on failure.
*/
int ti_clk_get_reg_addr(struct device_node *node, int index,
struct clk_omap_reg *reg)
{
u32 val;
int i;
for (i = 0; i < CLK_MAX_MEMMAPS; i++) {
if (clocks_node_ptr[i] == node->parent)
break;
if (clocks_node_ptr[i] == node->parent->parent)
break;
}
if (i == CLK_MAX_MEMMAPS) {
pr_err("clk-provider not found for %pOFn!\n", node);
return -ENOENT;
}
reg->index = i;
if (of_property_read_u32_index(node, "reg", index, &val)) {
if (of_property_read_u32_index(node->parent, "reg",
index, &val)) {
pr_err("%pOFn or parent must have reg[%d]!\n",
node, index);
return -EINVAL;
}
}
reg->offset = val;
reg->ptr = NULL;
return 0;
}
void ti_clk_latch(struct clk_omap_reg *reg, s8 shift)
{
u32 latch;
if (shift < 0)
return;
latch = 1 << shift;
ti_clk_ll_ops->clk_rmw(latch, latch, reg);
ti_clk_ll_ops->clk_rmw(0, latch, reg);
ti_clk_ll_ops->clk_readl(reg); /* OCP barrier */
}
/**
* omap2_clk_provider_init - init master clock provider
* @parent: master node
* @index: internal index for clk_reg_ops
* @syscon: syscon regmap pointer for accessing clock registers
* @mem: iomem pointer for the clock provider memory area, only used if
* syscon is not provided
*
* Initializes a master clock IP block. This basically sets up the
* mapping from clocks node to the memory map index. All the clocks
* are then initialized through the common of_clk_init call, and the
* clocks will access their memory maps based on the node layout.
* Returns 0 in success.
*/
int __init omap2_clk_provider_init(struct device_node *parent, int index,
struct regmap *syscon, void __iomem *mem)
{
struct device_node *clocks;
struct clk_iomap *io;
/* get clocks for this parent */
clocks = of_get_child_by_name(parent, "clocks");
if (!clocks) {
pr_err("%pOFn missing 'clocks' child node.\n", parent);
return -EINVAL;
}
/* add clocks node info */
clocks_node_ptr[index] = clocks;
io = kzalloc(sizeof(*io), GFP_KERNEL);
if (!io)
return -ENOMEM;
io->regmap = syscon;
io->mem = mem;
clk_memmaps[index] = io;
return 0;
}
/**
* omap2_clk_legacy_provider_init - initialize a legacy clock provider
* @index: index for the clock provider
* @mem: iomem pointer for the clock provider memory area
*
* Initializes a legacy clock provider memory mapping.
*/
void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem)
{
struct clk_iomap *io;
io = memblock_alloc(sizeof(*io), SMP_CACHE_BYTES);
if (!io)
panic("%s: Failed to allocate %zu bytes\n", __func__,
sizeof(*io));
io->mem = mem;
clk_memmaps[index] = io;
}
/**
* ti_dt_clk_init_retry_clks - init clocks from the retry list
*
* Initializes any clocks that have failed to initialize before,
* reasons being missing parent node(s) during earlier init. This
* typically happens only for DPLLs which need to have both of their
* parent clocks ready during init.
*/
void ti_dt_clk_init_retry_clks(void)
{
struct clk_init_item *retry;
struct clk_init_item *tmp;
int retries = 5;
while (!list_empty(&retry_list) && retries) {
list_for_each_entry_safe(retry, tmp, &retry_list, link) {
pr_debug("retry-init: %pOFn\n", retry->node);
retry->func(retry->user, retry->node);
list_del(&retry->link);
kfree(retry);
}
retries--;
}
}
static const struct of_device_id simple_clk_match_table[] __initconst = {
{ .compatible = "fixed-clock" },
{ .compatible = "fixed-factor-clock" },
{ }
};
/**
* ti_dt_clk_name - init clock name from first output name or node name
* @np: device node
*
* Use the first clock-output-name for the clock name if found. Fall back
* to legacy naming based on node name.
*/
const char *ti_dt_clk_name(struct device_node *np)
{
const char *name;
if (!of_property_read_string_index(np, "clock-output-names", 0,
&name))
return name;
return np->name;
}
/**
* ti_clk_add_aliases - setup clock aliases
*
* Sets up any missing clock aliases. No return value.
*/
void __init ti_clk_add_aliases(void)
{
struct device_node *np;
struct clk *clk;
for_each_matching_node(np, simple_clk_match_table) {
struct of_phandle_args clkspec;
clkspec.np = np;
clk = of_clk_get_from_provider(&clkspec);
ti_clk_add_alias(clk, ti_dt_clk_name(np));
}
}
/**
* ti_clk_setup_features - setup clock features flags
* @features: features definition to use
*
* Initializes the clock driver features flags based on platform
* provided data. No return value.
*/
void __init ti_clk_setup_features(struct ti_clk_features *features)
{
memcpy(&ti_clk_features, features, sizeof(*features));
}
/**
* ti_clk_get_features - get clock driver features flags
*
* Get TI clock driver features description. Returns a pointer
* to the current feature setup.
*/
const struct ti_clk_features *ti_clk_get_features(void)
{
return &ti_clk_features;
}
/**
* omap2_clk_enable_init_clocks - prepare & enable a list of clocks
* @clk_names: ptr to an array of strings of clock names to enable
* @num_clocks: number of clock names in @clk_names
*
* Prepare and enable a list of clocks, named by @clk_names. No
* return value. XXX Deprecated; only needed until these clocks are
* properly claimed and enabled by the drivers or core code that uses
* them. XXX What code disables & calls clk_put on these clocks?
*/
void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
{
struct clk *init_clk;
int i;
for (i = 0; i < num_clocks; i++) {
init_clk = clk_get(NULL, clk_names[i]);
if (WARN(IS_ERR(init_clk), "could not find init clock %s\n",
clk_names[i]))
continue;
clk_prepare_enable(init_clk);
}
}
/**
* ti_clk_add_alias - add a clock alias for a TI clock
* @clk: clock handle to create alias for
* @con: connection ID for this clock
*
* Creates a clock alias for a TI clock. Allocates the clock lookup entry
* and assigns the data to it. Returns 0 if successful, negative error
* value otherwise.
*/
int ti_clk_add_alias(struct clk *clk, const char *con)
{
struct clk_lookup *cl;
if (!clk)
return 0;
if (IS_ERR(clk))
return PTR_ERR(clk);
cl = kzalloc(sizeof(*cl), GFP_KERNEL);
if (!cl)
return -ENOMEM;
cl->con_id = con;
cl->clk = clk;
clkdev_add(cl);
return 0;
}
/**
* of_ti_clk_register - register a TI clock to the common clock framework
* @node: device node for this clock
* @hw: hardware clock handle
* @con: connection ID for this clock
*
* Registers a TI clock to the common clock framework, and adds a clock
* alias for it. Returns a handle to the registered clock if successful,
* ERR_PTR value in failure.
*/
struct clk *of_ti_clk_register(struct device_node *node, struct clk_hw *hw,
const char *con)
{
struct clk *clk;
int ret;
ret = of_clk_hw_register(node, hw);
if (ret)
return ERR_PTR(ret);
clk = hw->clk;
ret = ti_clk_add_alias(clk, con);
if (ret) {
clk_unregister(clk);
return ERR_PTR(ret);
}
return clk;
}
/**
* of_ti_clk_register_omap_hw - register a clk_hw_omap to the clock framework
* @node: device node for this clock
* @hw: hardware clock handle
* @con: connection ID for this clock
*
* Registers a clk_hw_omap clock to the clock framewor, adds a clock alias
* for it, and adds the list to the available clk_hw_omap type clocks.
* Returns a handle to the registered clock if successful, ERR_PTR value
* in failure.
*/
struct clk *of_ti_clk_register_omap_hw(struct device_node *node,
struct clk_hw *hw, const char *con)
{
struct clk *clk;
struct clk_hw_omap *oclk;
clk = of_ti_clk_register(node, hw, con);
if (IS_ERR(clk))
return clk;
oclk = to_clk_hw_omap(hw);
list_add(&oclk->node, &clk_hw_omap_clocks);
return clk;
}
/**
* omap2_clk_for_each - call function for each registered clk_hw_omap
* @fn: pointer to a callback function
*
* Call @fn for each registered clk_hw_omap, passing @hw to each
* function. @fn must return 0 for success or any other value for
* failure. If @fn returns non-zero, the iteration across clocks
* will stop and the non-zero return value will be passed to the
* caller of omap2_clk_for_each().
*/
int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw))
{
int ret;
struct clk_hw_omap *hw;
list_for_each_entry(hw, &clk_hw_omap_clocks, node) {
ret = (*fn)(hw);
if (ret)
break;
}
return ret;
}
/**
* omap2_clk_is_hw_omap - check if the provided clk_hw is OMAP clock
* @hw: clk_hw to check if it is an omap clock or not
*
* Checks if the provided clk_hw is OMAP clock or not. Returns true if
* it is, false otherwise.
*/
bool omap2_clk_is_hw_omap(struct clk_hw *hw)
{
struct clk_hw_omap *oclk;
list_for_each_entry(oclk, &clk_hw_omap_clocks, node) {
if (&oclk->hw == hw)
return true;
}
return false;
}
| linux-master | drivers/clk/ti/clk.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP2 Clock init
*
* Copyright (C) 2013 Texas Instruments, Inc
* Tero Kristo ([email protected])
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clk/ti.h>
#include "clock.h"
static struct ti_dt_clk omap2xxx_clks[] = {
DT_CLK(NULL, "func_32k_ck", "func_32k_ck"),
DT_CLK(NULL, "secure_32k_ck", "secure_32k_ck"),
DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
DT_CLK(NULL, "virt_26m_ck", "virt_26m_ck"),
DT_CLK(NULL, "aplls_clkin_ck", "aplls_clkin_ck"),
DT_CLK(NULL, "aplls_clkin_x2_ck", "aplls_clkin_x2_ck"),
DT_CLK(NULL, "osc_ck", "osc_ck"),
DT_CLK(NULL, "sys_ck", "sys_ck"),
DT_CLK(NULL, "alt_ck", "alt_ck"),
DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
DT_CLK(NULL, "dpll_ck", "dpll_ck"),
DT_CLK(NULL, "apll96_ck", "apll96_ck"),
DT_CLK(NULL, "apll54_ck", "apll54_ck"),
DT_CLK(NULL, "func_54m_ck", "func_54m_ck"),
DT_CLK(NULL, "core_ck", "core_ck"),
DT_CLK(NULL, "func_96m_ck", "func_96m_ck"),
DT_CLK(NULL, "func_48m_ck", "func_48m_ck"),
DT_CLK(NULL, "func_12m_ck", "func_12m_ck"),
DT_CLK(NULL, "sys_clkout_src", "sys_clkout_src"),
DT_CLK(NULL, "sys_clkout", "sys_clkout"),
DT_CLK(NULL, "emul_ck", "emul_ck"),
DT_CLK(NULL, "mpu_ck", "mpu_ck"),
DT_CLK(NULL, "dsp_fck", "dsp_fck"),
DT_CLK(NULL, "gfx_3d_fck", "gfx_3d_fck"),
DT_CLK(NULL, "gfx_2d_fck", "gfx_2d_fck"),
DT_CLK(NULL, "gfx_ick", "gfx_ick"),
DT_CLK("omapdss_dss", "ick", "dss_ick"),
DT_CLK(NULL, "dss_ick", "dss_ick"),
DT_CLK(NULL, "dss1_fck", "dss1_fck"),
DT_CLK(NULL, "dss2_fck", "dss2_fck"),
DT_CLK(NULL, "dss_54m_fck", "dss_54m_fck"),
DT_CLK(NULL, "core_l3_ck", "core_l3_ck"),
DT_CLK(NULL, "ssi_fck", "ssi_ssr_sst_fck"),
DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
DT_CLK(NULL, "l4_ck", "l4_ck"),
DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"),
DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
DT_CLK(NULL, "uart1_ick", "uart1_ick"),
DT_CLK(NULL, "uart1_fck", "uart1_fck"),
DT_CLK(NULL, "uart2_ick", "uart2_ick"),
DT_CLK(NULL, "uart2_fck", "uart2_fck"),
DT_CLK(NULL, "uart3_ick", "uart3_ick"),
DT_CLK(NULL, "uart3_fck", "uart3_fck"),
DT_CLK(NULL, "gpios_ick", "gpios_ick"),
DT_CLK(NULL, "gpios_fck", "gpios_fck"),
DT_CLK("omap_wdt", "ick", "mpu_wdt_ick"),
DT_CLK(NULL, "mpu_wdt_ick", "mpu_wdt_ick"),
DT_CLK(NULL, "mpu_wdt_fck", "mpu_wdt_fck"),
DT_CLK(NULL, "sync_32k_ick", "sync_32k_ick"),
DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
DT_CLK("omap24xxcam", "fck", "cam_fck"),
DT_CLK(NULL, "cam_fck", "cam_fck"),
DT_CLK("omap24xxcam", "ick", "cam_ick"),
DT_CLK(NULL, "cam_ick", "cam_ick"),
DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
DT_CLK(NULL, "wdt4_ick", "wdt4_ick"),
DT_CLK(NULL, "wdt4_fck", "wdt4_fck"),
DT_CLK(NULL, "mspro_ick", "mspro_ick"),
DT_CLK(NULL, "mspro_fck", "mspro_fck"),
DT_CLK(NULL, "fac_ick", "fac_ick"),
DT_CLK(NULL, "fac_fck", "fac_fck"),
DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
DT_CLK(NULL, "hdq_ick", "hdq_ick"),
DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
DT_CLK(NULL, "hdq_fck", "hdq_fck"),
DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
DT_CLK(NULL, "sdma_fck", "sdma_fck"),
DT_CLK(NULL, "sdma_ick", "sdma_ick"),
DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
DT_CLK(NULL, "des_ick", "des_ick"),
DT_CLK("omap-sham", "ick", "sha_ick"),
DT_CLK(NULL, "sha_ick", "sha_ick"),
DT_CLK("omap_rng", "ick", "rng_ick"),
DT_CLK(NULL, "rng_ick", "rng_ick"),
DT_CLK("omap-aes", "ick", "aes_ick"),
DT_CLK(NULL, "aes_ick", "aes_ick"),
DT_CLK(NULL, "pka_ick", "pka_ick"),
DT_CLK(NULL, "usb_fck", "usb_fck"),
DT_CLK(NULL, "timer_32k_ck", "func_32k_ck"),
DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
DT_CLK(NULL, "timer_ext_ck", "alt_ck"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap2420_clks[] = {
DT_CLK(NULL, "sys_clkout2_src", "sys_clkout2_src"),
DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
DT_CLK(NULL, "dsp_ick", "dsp_ick"),
DT_CLK(NULL, "iva1_ifck", "iva1_ifck"),
DT_CLK(NULL, "iva1_mpu_int_ifck", "iva1_mpu_int_ifck"),
DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
DT_CLK("mmci-omap.0", "ick", "mmc_ick"),
DT_CLK(NULL, "mmc_ick", "mmc_ick"),
DT_CLK("mmci-omap.0", "fck", "mmc_fck"),
DT_CLK(NULL, "mmc_fck", "mmc_fck"),
DT_CLK(NULL, "eac_ick", "eac_ick"),
DT_CLK(NULL, "eac_fck", "eac_fck"),
DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
DT_CLK(NULL, "vlynq_ick", "vlynq_ick"),
DT_CLK(NULL, "vlynq_fck", "vlynq_fck"),
DT_CLK("musb-hdrc", "fck", "osc_ck"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap2430_clks[] = {
DT_CLK("twl", "fck", "osc_ck"),
DT_CLK(NULL, "iva2_1_ick", "iva2_1_ick"),
DT_CLK(NULL, "mdm_ick", "mdm_ick"),
DT_CLK(NULL, "mdm_osc_ck", "mdm_osc_ck"),
DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"),
DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"),
DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
DT_CLK(NULL, "icr_ick", "icr_ick"),
DT_CLK(NULL, "i2chs1_fck", "i2chs1_fck"),
DT_CLK(NULL, "i2chs2_fck", "i2chs2_fck"),
DT_CLK("musb-omap2430", "ick", "usbhs_ick"),
DT_CLK(NULL, "usbhs_ick", "usbhs_ick"),
DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
DT_CLK(NULL, "gpio5_fck", "gpio5_fck"),
DT_CLK(NULL, "mdm_intc_ick", "mdm_intc_ick"),
DT_CLK("omap_hsmmc.0", "mmchsdb_fck", "mmchsdb1_fck"),
DT_CLK(NULL, "mmchsdb1_fck", "mmchsdb1_fck"),
DT_CLK("omap_hsmmc.1", "mmchsdb_fck", "mmchsdb2_fck"),
DT_CLK(NULL, "mmchsdb2_fck", "mmchsdb2_fck"),
{ .node_name = NULL },
};
static const char *enable_init_clks[] = {
"apll96_ck",
"apll54_ck",
"sync_32k_ick",
"omapctrl_ick",
"gpmc_fck",
"sdrc_ick",
};
enum {
OMAP2_SOC_OMAP2420,
OMAP2_SOC_OMAP2430,
};
static int __init omap2xxx_dt_clk_init(int soc_type)
{
ti_dt_clocks_register(omap2xxx_clks);
if (soc_type == OMAP2_SOC_OMAP2420)
ti_dt_clocks_register(omap2420_clks);
else
ti_dt_clocks_register(omap2430_clks);
omap2xxx_clkt_vps_init();
omap2_clk_disable_autoidle_all();
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
(clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 1000000),
(clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 100000) % 10,
(clk_get_rate(clk_get_sys(NULL, "dpll_ck")) / 1000000),
(clk_get_rate(clk_get_sys(NULL, "mpu_ck")) / 1000000));
return 0;
}
int __init omap2420_dt_clk_init(void)
{
return omap2xxx_dt_clk_init(OMAP2_SOC_OMAP2420);
}
int __init omap2430_dt_clk_init(void)
{
return omap2xxx_dt_clk_init(OMAP2_SOC_OMAP2430);
}
| linux-master | drivers/clk/ti/clk-2xxx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP3 Clock init
*
* Copyright (C) 2013 Texas Instruments, Inc
* Tero Kristo ([email protected])
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
#include "clock.h"
#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1
#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5
#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8
#define OMAP34XX_CM_IDLEST_VAL 1
/*
* In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported
* in the same register at a bit offset of 0x8. The EN_ACK for ICK is
* at an offset of 4 from ICK enable bit.
*/
#define AM35XX_IPSS_ICK_MASK 0xF
#define AM35XX_IPSS_ICK_EN_ACK_OFFSET 0x4
#define AM35XX_IPSS_ICK_FCK_OFFSET 0x8
#define AM35XX_IPSS_CLK_IDLEST_VAL 0
#define AM35XX_ST_IPSS_SHIFT 5
/**
* omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
* @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
*
* The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
* from the CM_{I,F}CLKEN bit. Pass back the correct info via
* @idlest_reg and @idlest_bit. No return value.
*/
static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk,
struct clk_omap_reg *idlest_reg,
u8 *idlest_bit,
u8 *idlest_val)
{
memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
idlest_reg->offset &= ~0xf0;
idlest_reg->offset |= 0x20;
*idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
*idlest_val = OMAP34XX_CM_IDLEST_VAL;
}
const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait = {
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
.find_idlest = omap3430es2_clk_ssi_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
/**
* omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
* @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
*
* Some OMAP modules on OMAP3 ES2+ chips have both initiator and
* target IDLEST bits. For our purposes, we are concerned with the
* target IDLEST bits, which exist at a different bit position than
* the *CLKEN bit position for these modules (DSS and USBHOST) (The
* default find_idlest code assumes that they are at the same
* position.) No return value.
*/
static void
omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk,
struct clk_omap_reg *idlest_reg,
u8 *idlest_bit, u8 *idlest_val)
{
memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
idlest_reg->offset &= ~0xf0;
idlest_reg->offset |= 0x20;
/* USBHOST_IDLE has same shift */
*idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
*idlest_val = OMAP34XX_CM_IDLEST_VAL;
}
const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait = {
.find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait = {
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
.find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
/**
* omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
* @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
*
* The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
* shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
* @idlest_reg and @idlest_bit. No return value.
*/
static void
omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk,
struct clk_omap_reg *idlest_reg,
u8 *idlest_bit,
u8 *idlest_val)
{
memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
idlest_reg->offset &= ~0xf0;
idlest_reg->offset |= 0x20;
*idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
*idlest_val = OMAP34XX_CM_IDLEST_VAL;
}
const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait = {
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
.find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
/**
* am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
* @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
*
* The interface clocks on AM35xx IPSS reflects the clock idle status
* in the enable register itsel at a bit offset of 4 from the enable
* bit. A value of 1 indicates that clock is enabled.
*/
static void am35xx_clk_find_idlest(struct clk_hw_omap *clk,
struct clk_omap_reg *idlest_reg,
u8 *idlest_bit,
u8 *idlest_val)
{
memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
*idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET;
*idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL;
}
/**
* am35xx_clk_find_companion - find companion clock to @clk
* @clk: struct clk * to find the companion clock of
* @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
* @other_bit: u8 ** to return the companion clock bit shift in
*
* Some clocks don't have companion clocks. For example, modules with
* only an interface clock (such as HECC) don't have a companion
* clock. Right now, this code relies on the hardware exporting a bit
* in the correct companion register that indicates that the
* nonexistent 'companion clock' is active. Future patches will
* associate this type of code with per-module data structures to
* avoid this issue, and remove the casts. No return value.
*/
static void am35xx_clk_find_companion(struct clk_hw_omap *clk,
struct clk_omap_reg *other_reg,
u8 *other_bit)
{
memcpy(other_reg, &clk->enable_reg, sizeof(*other_reg));
if (clk->enable_bit & AM35XX_IPSS_ICK_MASK)
*other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET;
else
*other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET;
}
const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = {
.find_idlest = am35xx_clk_find_idlest,
.find_companion = am35xx_clk_find_companion,
};
/**
* am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
* @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
*
* The IPSS target CM_IDLEST bit is at a different shift from the
* CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg
* and @idlest_bit. No return value.
*/
static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk,
struct clk_omap_reg *idlest_reg,
u8 *idlest_bit,
u8 *idlest_val)
{
memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
idlest_reg->offset &= ~0xf0;
idlest_reg->offset |= 0x20;
*idlest_bit = AM35XX_ST_IPSS_SHIFT;
*idlest_val = OMAP34XX_CM_IDLEST_VAL;
}
const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = {
.allow_idle = omap2_clkt_iclk_allow_idle,
.deny_idle = omap2_clkt_iclk_deny_idle,
.find_idlest = am35xx_clk_ipss_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
static struct ti_dt_clk omap3xxx_clks[] = {
DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap3430es1_clks[] = {
DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
{ .node_name = NULL },
};
static struct ti_dt_clk am35xx_clks[] = {
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
{ .node_name = NULL },
};
static const char *enable_init_clks[] = {
"sdrc_ick",
"gpmc_fck",
"omapctrl_ick",
};
enum {
OMAP3_SOC_AM35XX,
OMAP3_SOC_OMAP3430_ES1,
OMAP3_SOC_OMAP3430_ES2_PLUS,
OMAP3_SOC_OMAP3630,
};
/**
* omap3_clk_lock_dpll5 - locks DPLL5
*
* Locks DPLL5 to a pre-defined frequency. This is required for proper
* operation of USB.
*/
void __init omap3_clk_lock_dpll5(void)
{
struct clk *dpll5_clk;
struct clk *dpll5_m2_clk;
/*
* Errata sprz319f advisory 2.1 documents a USB host clock drift issue
* that can be worked around using specially crafted dpll5 settings
* with a dpll5_m2 divider set to 8. Set the dpll5 rate to 8x the USB
* host clock rate, its .set_rate handler() will detect that frequency
* and use the errata settings.
*/
dpll5_clk = clk_get(NULL, "dpll5_ck");
clk_set_rate(dpll5_clk, OMAP3_DPLL5_FREQ_FOR_USBHOST * 8);
clk_prepare_enable(dpll5_clk);
/* Program dpll5_m2_clk divider */
dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
clk_prepare_enable(dpll5_m2_clk);
clk_set_rate(dpll5_m2_clk, OMAP3_DPLL5_FREQ_FOR_USBHOST);
clk_disable_unprepare(dpll5_m2_clk);
clk_disable_unprepare(dpll5_clk);
}
static int __init omap3xxx_dt_clk_init(int soc_type)
{
if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
soc_type == OMAP3_SOC_OMAP3430_ES1 ||
soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
ti_dt_clocks_register(omap3xxx_clks);
if (soc_type == OMAP3_SOC_AM35XX)
ti_dt_clocks_register(am35xx_clks);
if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX ||
soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
ti_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks);
if (soc_type == OMAP3_SOC_OMAP3430_ES1)
ti_dt_clocks_register(omap3430es1_clks);
if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
soc_type == OMAP3_SOC_OMAP3630)
ti_dt_clocks_register(omap36xx_omap3430es2plus_clks);
omap2_clk_disable_autoidle_all();
ti_clk_add_aliases();
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
(clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
(clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
(clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
(clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
if (soc_type != OMAP3_SOC_OMAP3430_ES1)
omap3_clk_lock_dpll5();
return 0;
}
int __init omap3430_dt_clk_init(void)
{
return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS);
}
int __init omap3630_dt_clk_init(void)
{
return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3630);
}
int __init am35xx_dt_clk_init(void)
{
return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX);
}
| linux-master | drivers/clk/ti/clk-3xxx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP DPLL clock support
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX)
static const struct clk_ops dpll_m4xen_ck_ops = {
.enable = &omap3_noncore_dpll_enable,
.disable = &omap3_noncore_dpll_disable,
.recalc_rate = &omap4_dpll_regm4xen_recalc,
.round_rate = &omap4_dpll_regm4xen_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
.set_parent = &omap3_noncore_dpll_set_parent,
.set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
.determine_rate = &omap4_dpll_regm4xen_determine_rate,
.get_parent = &omap2_init_dpll_parent,
.save_context = &omap3_core_dpll_save_context,
.restore_context = &omap3_core_dpll_restore_context,
};
#else
static const struct clk_ops dpll_m4xen_ck_ops = {};
#endif
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
static const struct clk_ops dpll_core_ck_ops = {
.recalc_rate = &omap3_dpll_recalc,
.get_parent = &omap2_init_dpll_parent,
};
static const struct clk_ops dpll_ck_ops = {
.enable = &omap3_noncore_dpll_enable,
.disable = &omap3_noncore_dpll_disable,
.recalc_rate = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
.set_parent = &omap3_noncore_dpll_set_parent,
.set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
.determine_rate = &omap3_noncore_dpll_determine_rate,
.get_parent = &omap2_init_dpll_parent,
.save_context = &omap3_noncore_dpll_save_context,
.restore_context = &omap3_noncore_dpll_restore_context,
};
static const struct clk_ops dpll_no_gate_ck_ops = {
.recalc_rate = &omap3_dpll_recalc,
.get_parent = &omap2_init_dpll_parent,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
.set_parent = &omap3_noncore_dpll_set_parent,
.set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
.determine_rate = &omap3_noncore_dpll_determine_rate,
.save_context = &omap3_noncore_dpll_save_context,
.restore_context = &omap3_noncore_dpll_restore_context
};
#else
static const struct clk_ops dpll_core_ck_ops = {};
static const struct clk_ops dpll_ck_ops = {};
static const struct clk_ops dpll_no_gate_ck_ops = {};
const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
#endif
#ifdef CONFIG_ARCH_OMAP2
static const struct clk_ops omap2_dpll_core_ck_ops = {
.get_parent = &omap2_init_dpll_parent,
.recalc_rate = &omap2_dpllcore_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap2_reprogram_dpllcore,
};
#else
static const struct clk_ops omap2_dpll_core_ck_ops = {};
#endif
#ifdef CONFIG_ARCH_OMAP3
static const struct clk_ops omap3_dpll_core_ck_ops = {
.get_parent = &omap2_init_dpll_parent,
.recalc_rate = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
};
#else
static const struct clk_ops omap3_dpll_core_ck_ops = {};
#endif
#ifdef CONFIG_ARCH_OMAP3
static const struct clk_ops omap3_dpll_ck_ops = {
.enable = &omap3_noncore_dpll_enable,
.disable = &omap3_noncore_dpll_disable,
.get_parent = &omap2_init_dpll_parent,
.recalc_rate = &omap3_dpll_recalc,
.set_rate = &omap3_noncore_dpll_set_rate,
.set_parent = &omap3_noncore_dpll_set_parent,
.set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
.determine_rate = &omap3_noncore_dpll_determine_rate,
.round_rate = &omap2_dpll_round_rate,
};
static const struct clk_ops omap3_dpll5_ck_ops = {
.enable = &omap3_noncore_dpll_enable,
.disable = &omap3_noncore_dpll_disable,
.get_parent = &omap2_init_dpll_parent,
.recalc_rate = &omap3_dpll_recalc,
.set_rate = &omap3_dpll5_set_rate,
.set_parent = &omap3_noncore_dpll_set_parent,
.set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
.determine_rate = &omap3_noncore_dpll_determine_rate,
.round_rate = &omap2_dpll_round_rate,
};
static const struct clk_ops omap3_dpll_per_ck_ops = {
.enable = &omap3_noncore_dpll_enable,
.disable = &omap3_noncore_dpll_disable,
.get_parent = &omap2_init_dpll_parent,
.recalc_rate = &omap3_dpll_recalc,
.set_rate = &omap3_dpll4_set_rate,
.set_parent = &omap3_noncore_dpll_set_parent,
.set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
.determine_rate = &omap3_noncore_dpll_determine_rate,
.round_rate = &omap2_dpll_round_rate,
};
#endif
static const struct clk_ops dpll_x2_ck_ops = {
.recalc_rate = &omap3_clkoutx2_recalc,
};
/**
* _register_dpll - low level registration of a DPLL clock
* @user: pointer to the hardware clock definition for the clock
* @node: device node for the clock
*
* Finalizes DPLL registration process. In case a failure (clk-ref or
* clk-bypass is missing), the clock is added to retry list and
* the initialization is retried on later stage.
*/
static void __init _register_dpll(void *user,
struct device_node *node)
{
struct clk_hw *hw = user;
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
struct dpll_data *dd = clk_hw->dpll_data;
const char *name;
struct clk *clk;
const struct clk_init_data *init = hw->init;
clk = of_clk_get(node, 0);
if (IS_ERR(clk)) {
pr_debug("clk-ref missing for %pOFn, retry later\n",
node);
if (!ti_clk_retry_init(node, hw, _register_dpll))
return;
goto cleanup;
}
dd->clk_ref = __clk_get_hw(clk);
clk = of_clk_get(node, 1);
if (IS_ERR(clk)) {
pr_debug("clk-bypass missing for %pOFn, retry later\n",
node);
if (!ti_clk_retry_init(node, hw, _register_dpll))
return;
goto cleanup;
}
dd->clk_bypass = __clk_get_hw(clk);
/* register the clock */
name = ti_dt_clk_name(node);
clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
kfree(init->parent_names);
kfree(init);
return;
}
cleanup:
kfree(clk_hw->dpll_data);
kfree(init->parent_names);
kfree(init);
kfree(clk_hw);
}
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
defined(CONFIG_SOC_AM43XX)
/**
* _register_dpll_x2 - Registers a DPLLx2 clock
* @node: device node for this clock
* @ops: clk_ops for this clock
* @hw_ops: clk_hw_ops for this clock
*
* Initializes a DPLL x 2 clock from device tree data.
*/
static void _register_dpll_x2(struct device_node *node,
const struct clk_ops *ops,
const struct clk_hw_omap_ops *hw_ops)
{
struct clk *clk;
struct clk_init_data init = { NULL };
struct clk_hw_omap *clk_hw;
const char *name = ti_dt_clk_name(node);
const char *parent_name;
parent_name = of_clk_get_parent_name(node, 0);
if (!parent_name) {
pr_err("%pOFn must have parent\n", node);
return;
}
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
if (!clk_hw)
return;
clk_hw->ops = hw_ops;
clk_hw->hw.init = &init;
init.name = name;
init.ops = ops;
init.parent_names = &parent_name;
init.num_parents = 1;
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX)
if (hw_ops == &clkhwops_omap4_dpllmx) {
int ret;
/* Check if register defined, if not, drop hw-ops */
ret = of_property_count_elems_of_size(node, "reg", 1);
if (ret <= 0) {
clk_hw->ops = NULL;
} else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {
kfree(clk_hw);
return;
}
}
#endif
/* register the clock */
clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
if (IS_ERR(clk))
kfree(clk_hw);
else
of_clk_add_provider(node, of_clk_src_simple_get, clk);
}
#endif
/**
* of_ti_dpll_setup - Setup function for OMAP DPLL clocks
* @node: device node containing the DPLL info
* @ops: ops for the DPLL
* @ddt: DPLL data template to use
*
* Initializes a DPLL clock from device tree data.
*/
static void __init of_ti_dpll_setup(struct device_node *node,
const struct clk_ops *ops,
const struct dpll_data *ddt)
{
struct clk_hw_omap *clk_hw = NULL;
struct clk_init_data *init = NULL;
const char **parent_names = NULL;
struct dpll_data *dd = NULL;
int ssc_clk_index;
u8 dpll_mode = 0;
u32 min_div;
dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL);
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
init = kzalloc(sizeof(*init), GFP_KERNEL);
if (!dd || !clk_hw || !init)
goto cleanup;
clk_hw->dpll_data = dd;
clk_hw->ops = &clkhwops_omap3_dpll;
clk_hw->hw.init = init;
init->name = ti_dt_clk_name(node);
init->ops = ops;
init->num_parents = of_clk_get_parent_count(node);
if (!init->num_parents) {
pr_err("%pOFn must have parent(s)\n", node);
goto cleanup;
}
parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);
if (!parent_names)
goto cleanup;
of_clk_parent_fill(node, parent_names, init->num_parents);
init->parent_names = parent_names;
if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))
goto cleanup;
/*
* Special case for OMAP2 DPLL, register order is different due to
* missing idlest_reg, also clkhwops is different. Detected from
* missing idlest_mask.
*/
if (!dd->idlest_mask) {
if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg))
goto cleanup;
#ifdef CONFIG_ARCH_OMAP2
clk_hw->ops = &clkhwops_omap2xxx_dpll;
omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
#endif
} else {
if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg))
goto cleanup;
if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg))
goto cleanup;
}
if (dd->autoidle_mask) {
if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))
goto cleanup;
ssc_clk_index = 4;
} else {
ssc_clk_index = 3;
}
if (dd->ssc_deltam_int_mask && dd->ssc_deltam_frac_mask &&
dd->ssc_modfreq_mant_mask && dd->ssc_modfreq_exp_mask) {
if (ti_clk_get_reg_addr(node, ssc_clk_index++,
&dd->ssc_deltam_reg))
goto cleanup;
if (ti_clk_get_reg_addr(node, ssc_clk_index++,
&dd->ssc_modfreq_reg))
goto cleanup;
of_property_read_u32(node, "ti,ssc-modfreq-hz",
&dd->ssc_modfreq);
of_property_read_u32(node, "ti,ssc-deltam", &dd->ssc_deltam);
dd->ssc_downspread =
of_property_read_bool(node, "ti,ssc-downspread");
}
if (of_property_read_bool(node, "ti,low-power-stop"))
dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
if (of_property_read_bool(node, "ti,low-power-bypass"))
dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
if (of_property_read_bool(node, "ti,lock"))
dpll_mode |= 1 << DPLL_LOCKED;
if (!of_property_read_u32(node, "ti,min-div", &min_div) &&
min_div > dd->min_divider)
dd->min_divider = min_div;
if (dpll_mode)
dd->modes = dpll_mode;
_register_dpll(&clk_hw->hw, node);
return;
cleanup:
kfree(dd);
kfree(parent_names);
kfree(init);
kfree(clk_hw);
}
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX)
static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
{
_register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
}
CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
of_ti_omap4_dpll_x2_setup);
#endif
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
{
_register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
}
CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
of_ti_am3_dpll_x2_setup);
#endif
#ifdef CONFIG_ARCH_OMAP3
static void __init of_ti_omap3_dpll_setup(struct device_node *node)
{
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
.autoidle_mask = 0x7,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
.freqsel_mask = 0xf0,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
if ((of_machine_is_compatible("ti,omap3630") ||
of_machine_is_compatible("ti,omap36xx")) &&
of_node_name_eq(node, "dpll5_ck"))
of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd);
else
of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
of_ti_omap3_dpll_setup);
static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
{
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
.autoidle_mask = 0x7,
.mult_mask = 0x7ff << 16,
.div1_mask = 0x7f << 8,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
.freqsel_mask = 0xf0,
};
of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
of_ti_omap3_core_dpll_setup);
static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
{
const struct dpll_data dd = {
.idlest_mask = 0x1 << 1,
.enable_mask = 0x7 << 16,
.autoidle_mask = 0x7 << 3,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
.freqsel_mask = 0xf00000,
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
};
of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
of_ti_omap3_per_dpll_setup);
static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
{
const struct dpll_data dd = {
.idlest_mask = 0x1 << 1,
.enable_mask = 0x7 << 16,
.autoidle_mask = 0x7 << 3,
.mult_mask = 0xfff << 8,
.div1_mask = 0x7f,
.max_multiplier = 4095,
.max_divider = 128,
.min_divider = 1,
.sddiv_mask = 0xff << 24,
.dco_mask = 0xe << 20,
.flags = DPLL_J_TYPE,
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
};
of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
of_ti_omap3_per_jtype_dpll_setup);
#endif
static void __init of_ti_omap4_dpll_setup(struct device_node *node)
{
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
.autoidle_mask = 0x7,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
of_ti_omap4_dpll_setup);
static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
{
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
.autoidle_mask = 0x7,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.max_multiplier = 2047,
.max_divider = 128,
.dcc_mask = BIT(22),
.dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
.min_divider = 1,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
}
CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
of_ti_omap5_mpu_dpll_setup);
static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
{
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
.autoidle_mask = 0x7,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
of_ti_omap4_core_dpll_setup);
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX)
static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
{
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
.autoidle_mask = 0x7,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
.m4xen_mask = 0x800,
.lpmode_mask = 1 << 10,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
of_ti_omap4_m4xen_dpll_setup);
static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
{
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
.autoidle_mask = 0x7,
.mult_mask = 0xfff << 8,
.div1_mask = 0xff,
.max_multiplier = 4095,
.max_divider = 256,
.min_divider = 1,
.sddiv_mask = 0xff << 24,
.flags = DPLL_J_TYPE,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
of_ti_omap4_jtype_dpll_setup);
#endif
static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
{
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
.ssc_enable_mask = 0x1 << 12,
.ssc_downspread_mask = 0x1 << 14,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.ssc_deltam_int_mask = 0x3 << 18,
.ssc_deltam_frac_mask = 0x3ffff,
.ssc_modfreq_mant_mask = 0x7f,
.ssc_modfreq_exp_mask = 0x7 << 8,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
.max_rate = 1000000000,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
of_ti_am3_no_gate_dpll_setup);
static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
{
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.max_multiplier = 4095,
.max_divider = 256,
.min_divider = 2,
.flags = DPLL_J_TYPE,
.max_rate = 2000000000,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
of_ti_am3_jtype_dpll_setup);
static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
{
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
.max_rate = 2000000000,
.flags = DPLL_J_TYPE,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
"ti,am3-dpll-no-gate-j-type-clock",
of_ti_am3_no_gate_jtype_dpll_setup);
static void __init of_ti_am3_dpll_setup(struct device_node *node)
{
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
.ssc_enable_mask = 0x1 << 12,
.ssc_downspread_mask = 0x1 << 14,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.ssc_deltam_int_mask = 0x3 << 18,
.ssc_deltam_frac_mask = 0x3ffff,
.ssc_modfreq_mant_mask = 0x7f,
.ssc_modfreq_exp_mask = 0x7 << 8,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
.max_rate = 1000000000,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
{
const struct dpll_data dd = {
.idlest_mask = 0x1,
.enable_mask = 0x7,
.mult_mask = 0x7ff << 8,
.div1_mask = 0x7f,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
.max_rate = 1000000000,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
};
of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
of_ti_am3_core_dpll_setup);
static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
{
const struct dpll_data dd = {
.enable_mask = 0x3,
.mult_mask = 0x3ff << 12,
.div1_mask = 0xf << 8,
.max_divider = 16,
.min_divider = 1,
};
of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
}
CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
of_ti_omap2_core_dpll_setup);
| linux-master | drivers/clk/ti/dpll.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI Multiplexer Clock
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
{
struct clk_omap_mux *mux = to_clk_omap_mux(hw);
int num_parents = clk_hw_get_num_parents(hw);
u32 val;
/*
* FIXME need a mux-specific flag to determine if val is bitwise or
* numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
* from 0x1 to 0x7 (index starts at one)
* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
* val = 0x4 really means "bit 2, index starts at bit 0"
*/
val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift;
val &= mux->mask;
if (mux->table) {
int i;
for (i = 0; i < num_parents; i++)
if (mux->table[i] == val)
return i;
return -EINVAL;
}
if (val && (mux->flags & CLK_MUX_INDEX_BIT))
val = ffs(val) - 1;
if (val && (mux->flags & CLK_MUX_INDEX_ONE))
val--;
if (val >= num_parents)
return -EINVAL;
return val;
}
static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_omap_mux *mux = to_clk_omap_mux(hw);
u32 val;
if (mux->table) {
index = mux->table[index];
} else {
if (mux->flags & CLK_MUX_INDEX_BIT)
index = (1 << ffs(index));
if (mux->flags & CLK_MUX_INDEX_ONE)
index++;
}
if (mux->flags & CLK_MUX_HIWORD_MASK) {
val = mux->mask << (mux->shift + 16);
} else {
val = ti_clk_ll_ops->clk_readl(&mux->reg);
val &= ~(mux->mask << mux->shift);
}
val |= index << mux->shift;
ti_clk_ll_ops->clk_writel(val, &mux->reg);
ti_clk_latch(&mux->reg, mux->latch);
return 0;
}
/**
* clk_mux_save_context - Save the parent selcted in the mux
* @hw: pointer struct clk_hw
*
* Save the parent mux value.
*/
static int clk_mux_save_context(struct clk_hw *hw)
{
struct clk_omap_mux *mux = to_clk_omap_mux(hw);
mux->saved_parent = ti_clk_mux_get_parent(hw);
return 0;
}
/**
* clk_mux_restore_context - Restore the parent in the mux
* @hw: pointer struct clk_hw
*
* Restore the saved parent mux value.
*/
static void clk_mux_restore_context(struct clk_hw *hw)
{
struct clk_omap_mux *mux = to_clk_omap_mux(hw);
ti_clk_mux_set_parent(hw, mux->saved_parent);
}
const struct clk_ops ti_clk_mux_ops = {
.get_parent = ti_clk_mux_get_parent,
.set_parent = ti_clk_mux_set_parent,
.determine_rate = __clk_mux_determine_rate,
.save_context = clk_mux_save_context,
.restore_context = clk_mux_restore_context,
};
static struct clk *_register_mux(struct device_node *node, const char *name,
const char * const *parent_names,
u8 num_parents, unsigned long flags,
struct clk_omap_reg *reg, u8 shift, u32 mask,
s8 latch, u8 clk_mux_flags, u32 *table)
{
struct clk_omap_mux *mux;
struct clk *clk;
struct clk_init_data init;
/* allocate the mux */
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = &ti_clk_mux_ops;
init.flags = flags;
init.parent_names = parent_names;
init.num_parents = num_parents;
/* struct clk_mux assignments */
memcpy(&mux->reg, reg, sizeof(*reg));
mux->shift = shift;
mux->mask = mask;
mux->latch = latch;
mux->flags = clk_mux_flags;
mux->table = table;
mux->hw.init = &init;
clk = of_ti_clk_register(node, &mux->hw, name);
if (IS_ERR(clk))
kfree(mux);
return clk;
}
/**
* of_mux_clk_setup - Setup function for simple mux rate clock
* @node: DT node for the clock
*
* Sets up a basic clock multiplexer.
*/
static void of_mux_clk_setup(struct device_node *node)
{
struct clk *clk;
struct clk_omap_reg reg;
unsigned int num_parents;
const char **parent_names;
const char *name;
u8 clk_mux_flags = 0;
u32 mask = 0;
u32 shift = 0;
s32 latch = -EINVAL;
u32 flags = CLK_SET_RATE_NO_REPARENT;
num_parents = of_clk_get_parent_count(node);
if (num_parents < 2) {
pr_err("mux-clock %pOFn must have parents\n", node);
return;
}
parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
if (!parent_names)
goto cleanup;
of_clk_parent_fill(node, parent_names, num_parents);
if (ti_clk_get_reg_addr(node, 0, ®))
goto cleanup;
of_property_read_u32(node, "ti,bit-shift", &shift);
of_property_read_u32(node, "ti,latch-bit", &latch);
if (of_property_read_bool(node, "ti,index-starts-at-one"))
clk_mux_flags |= CLK_MUX_INDEX_ONE;
if (of_property_read_bool(node, "ti,set-rate-parent"))
flags |= CLK_SET_RATE_PARENT;
/* Generate bit-mask based on parent info */
mask = num_parents;
if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
mask--;
mask = (1 << fls(mask)) - 1;
name = ti_dt_clk_name(node);
clk = _register_mux(node, name, parent_names, num_parents,
flags, ®, shift, mask, latch, clk_mux_flags,
NULL);
if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk);
cleanup:
kfree(parent_names);
}
CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
{
struct clk_omap_mux *mux;
int num_parents;
if (!setup)
return NULL;
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
mux->shift = setup->bit_shift;
mux->latch = -EINVAL;
mux->reg.index = setup->module;
mux->reg.offset = setup->reg;
if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
mux->flags |= CLK_MUX_INDEX_ONE;
num_parents = setup->num_parents;
mux->mask = num_parents - 1;
mux->mask = (1 << fls(mux->mask)) - 1;
return &mux->hw;
}
static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
{
struct clk_omap_mux *mux;
unsigned int num_parents;
u32 val;
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
return;
if (ti_clk_get_reg_addr(node, 0, &mux->reg))
goto cleanup;
if (!of_property_read_u32(node, "ti,bit-shift", &val))
mux->shift = val;
if (of_property_read_bool(node, "ti,index-starts-at-one"))
mux->flags |= CLK_MUX_INDEX_ONE;
num_parents = of_clk_get_parent_count(node);
if (num_parents < 2) {
pr_err("%pOFn must have parents\n", node);
goto cleanup;
}
mux->mask = num_parents - 1;
mux->mask = (1 << fls(mux->mask)) - 1;
if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
return;
cleanup:
kfree(mux);
}
CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
of_ti_composite_mux_clk_setup);
| linux-master | drivers/clk/ti/mux.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP clockdomain support
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
/**
* omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw
* @hw: struct clk_hw * of the clock being enabled
*
* Increment the usecount of the clockdomain of the clock pointed to
* by @hw; if the usecount is 1, the clockdomain will be "enabled."
* Only needed for clocks that don't use omap2_dflt_clk_enable() as
* their enable function pointer. Passes along the return value of
* clkdm_clk_enable(), -EINVAL if @hw is not associated with a
* clockdomain, or 0 if clock framework-based clockdomain control is
* not implemented.
*/
int omap2_clkops_enable_clkdm(struct clk_hw *hw)
{
struct clk_hw_omap *clk;
int ret = 0;
clk = to_clk_hw_omap(hw);
if (unlikely(!clk->clkdm)) {
pr_err("%s: %s: no clkdm set ?!\n", __func__,
clk_hw_get_name(hw));
return -EINVAL;
}
if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) {
pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
__func__, clk_hw_get_name(hw));
return 0;
}
ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n",
__func__, clk_hw_get_name(hw), clk->clkdm_name, ret);
return ret;
}
/**
* omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw
* @hw: struct clk_hw * of the clock being disabled
*
* Decrement the usecount of the clockdomain of the clock pointed to
* by @hw; if the usecount is 0, the clockdomain will be "disabled."
* Only needed for clocks that don't use omap2_dflt_clk_disable() as their
* disable function pointer. No return value.
*/
void omap2_clkops_disable_clkdm(struct clk_hw *hw)
{
struct clk_hw_omap *clk;
clk = to_clk_hw_omap(hw);
if (unlikely(!clk->clkdm)) {
pr_err("%s: %s: no clkdm set ?!\n", __func__,
clk_hw_get_name(hw));
return;
}
if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) {
pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
__func__, clk_hw_get_name(hw));
return;
}
ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
}
/**
* omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
* @hw: Pointer to clk_hw_omap used to obtain OMAP clock struct ptr to use
*
* Convert a clockdomain name stored in a struct clk 'clk' into a
* clockdomain pointer, and save it into the struct clk. Intended to be
* called during clk_register(). Returns 0 on success, -EERROR otherwise.
*/
int omap2_init_clk_clkdm(struct clk_hw *hw)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
struct clockdomain *clkdm;
const char *clk_name;
if (!clk->clkdm_name)
return 0;
clk_name = __clk_get_name(hw->clk);
clkdm = ti_clk_ll_ops->clkdm_lookup(clk->clkdm_name);
if (clkdm) {
pr_debug("clock: associated clk %s to clkdm %s\n",
clk_name, clk->clkdm_name);
clk->clkdm = clkdm;
} else {
pr_debug("clock: could not associate clk %s to clkdm %s\n",
clk_name, clk->clkdm_name);
}
return 0;
}
static void __init of_ti_clockdomain_setup(struct device_node *node)
{
struct clk *clk;
struct clk_hw *clk_hw;
const char *clkdm_name = ti_dt_clk_name(node);
int i;
unsigned int num_clks;
num_clks = of_clk_get_parent_count(node);
for (i = 0; i < num_clks; i++) {
clk = of_clk_get(node, i);
if (IS_ERR(clk)) {
pr_err("%s: Failed get %pOF' clock nr %d (%ld)\n",
__func__, node, i, PTR_ERR(clk));
continue;
}
clk_hw = __clk_get_hw(clk);
if (!omap2_clk_is_hw_omap(clk_hw)) {
pr_warn("can't setup clkdm for basic clk %s\n",
__clk_get_name(clk));
clk_put(clk);
continue;
}
to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
omap2_init_clk_clkdm(clk_hw);
clk_put(clk);
}
}
static const struct of_device_id ti_clkdm_match_table[] __initconst = {
{ .compatible = "ti,clockdomain" },
{ }
};
/**
* ti_dt_clockdomains_setup - setup device tree clockdomains
*
* Initializes clockdomain nodes for a SoC. This parses through all the
* nodes with compatible = "ti,clockdomain", and add the clockdomain
* info for all the clocks listed under these. This function shall be
* called after rest of the DT clock init has completed and all
* clock nodes have been registered.
*/
void __init ti_dt_clockdomains_setup(void)
{
struct device_node *np;
for_each_matching_node(np, ti_clkdm_match_table) {
of_ti_clockdomain_setup(np);
}
}
| linux-master | drivers/clk/ti/clockdomain.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* DRA7 ATL (Audio Tracking Logic) clock driver
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Peter Ujfalusi <[email protected]>
*/
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/clk/ti.h>
#include "clock.h"
#define DRA7_ATL_INSTANCES 4
#define DRA7_ATL_PPMR_REG(id) (0x200 + (id * 0x80))
#define DRA7_ATL_BBSR_REG(id) (0x204 + (id * 0x80))
#define DRA7_ATL_ATLCR_REG(id) (0x208 + (id * 0x80))
#define DRA7_ATL_SWEN_REG(id) (0x210 + (id * 0x80))
#define DRA7_ATL_BWSMUX_REG(id) (0x214 + (id * 0x80))
#define DRA7_ATL_AWSMUX_REG(id) (0x218 + (id * 0x80))
#define DRA7_ATL_PCLKMUX_REG(id) (0x21c + (id * 0x80))
#define DRA7_ATL_SWEN BIT(0)
#define DRA7_ATL_DIVIDER_MASK (0x1f)
#define DRA7_ATL_PCLKMUX BIT(0)
struct dra7_atl_clock_info;
struct dra7_atl_desc {
struct clk *clk;
struct clk_hw hw;
struct dra7_atl_clock_info *cinfo;
int id;
bool probed; /* the driver for the IP has been loaded */
bool valid; /* configured */
bool enabled;
u32 bws; /* Baseband Word Select Mux */
u32 aws; /* Audio Word Select Mux */
u32 divider; /* Cached divider value */
};
struct dra7_atl_clock_info {
struct device *dev;
void __iomem *iobase;
struct dra7_atl_desc *cdesc;
};
#define to_atl_desc(_hw) container_of(_hw, struct dra7_atl_desc, hw)
static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg,
u32 val)
{
__raw_writel(val, cinfo->iobase + reg);
}
static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg)
{
return __raw_readl(cinfo->iobase + reg);
}
static int atl_clk_enable(struct clk_hw *hw)
{
struct dra7_atl_desc *cdesc = to_atl_desc(hw);
if (!cdesc->probed)
goto out;
if (unlikely(!cdesc->valid))
dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n",
cdesc->id);
pm_runtime_get_sync(cdesc->cinfo->dev);
atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id),
cdesc->divider - 1);
atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN);
out:
cdesc->enabled = true;
return 0;
}
static void atl_clk_disable(struct clk_hw *hw)
{
struct dra7_atl_desc *cdesc = to_atl_desc(hw);
if (!cdesc->probed)
goto out;
atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0);
pm_runtime_put_sync(cdesc->cinfo->dev);
out:
cdesc->enabled = false;
}
static int atl_clk_is_enabled(struct clk_hw *hw)
{
struct dra7_atl_desc *cdesc = to_atl_desc(hw);
return cdesc->enabled;
}
static unsigned long atl_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct dra7_atl_desc *cdesc = to_atl_desc(hw);
return parent_rate / cdesc->divider;
}
static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
unsigned divider;
divider = (*parent_rate + rate / 2) / rate;
if (divider > DRA7_ATL_DIVIDER_MASK + 1)
divider = DRA7_ATL_DIVIDER_MASK + 1;
return *parent_rate / divider;
}
static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct dra7_atl_desc *cdesc;
u32 divider;
if (!hw || !rate)
return -EINVAL;
cdesc = to_atl_desc(hw);
divider = ((parent_rate + rate / 2) / rate) - 1;
if (divider > DRA7_ATL_DIVIDER_MASK)
divider = DRA7_ATL_DIVIDER_MASK;
cdesc->divider = divider + 1;
return 0;
}
static const struct clk_ops atl_clk_ops = {
.enable = atl_clk_enable,
.disable = atl_clk_disable,
.is_enabled = atl_clk_is_enabled,
.recalc_rate = atl_clk_recalc_rate,
.round_rate = atl_clk_round_rate,
.set_rate = atl_clk_set_rate,
};
static void __init of_dra7_atl_clock_setup(struct device_node *node)
{
struct dra7_atl_desc *clk_hw = NULL;
struct clk_parent_data pdata = { .index = 0 };
struct clk_init_data init = { NULL };
const char *name;
struct clk *clk;
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
if (!clk_hw) {
pr_err("%s: could not allocate dra7_atl_desc\n", __func__);
return;
}
clk_hw->hw.init = &init;
clk_hw->divider = 1;
name = ti_dt_clk_name(node);
init.name = name;
init.ops = &atl_clk_ops;
init.flags = CLK_IGNORE_UNUSED;
init.num_parents = of_clk_get_parent_count(node);
if (init.num_parents != 1) {
pr_err("%s: atl clock %pOFn must have 1 parent\n", __func__,
node);
goto cleanup;
}
init.parent_data = &pdata;
clk = of_ti_clk_register(node, &clk_hw->hw, name);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
return;
}
cleanup:
kfree(clk_hw);
}
CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup);
static int of_dra7_atl_clk_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct dra7_atl_clock_info *cinfo;
int i;
int ret = 0;
if (!node)
return -ENODEV;
cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL);
if (!cinfo)
return -ENOMEM;
cinfo->iobase = of_iomap(node, 0);
cinfo->dev = &pdev->dev;
pm_runtime_enable(cinfo->dev);
pm_runtime_get_sync(cinfo->dev);
atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX);
for (i = 0; i < DRA7_ATL_INSTANCES; i++) {
struct device_node *cfg_node;
char prop[5];
struct dra7_atl_desc *cdesc;
struct of_phandle_args clkspec;
struct clk *clk;
int rc;
rc = of_parse_phandle_with_args(node, "ti,provided-clocks",
NULL, i, &clkspec);
if (rc) {
pr_err("%s: failed to lookup atl clock %d\n", __func__,
i);
ret = -EINVAL;
goto pm_put;
}
clk = of_clk_get_from_provider(&clkspec);
if (IS_ERR(clk)) {
pr_err("%s: failed to get atl clock %d from provider\n",
__func__, i);
ret = PTR_ERR(clk);
goto pm_put;
}
cdesc = to_atl_desc(__clk_get_hw(clk));
cdesc->cinfo = cinfo;
cdesc->id = i;
/* Get configuration for the ATL instances */
snprintf(prop, sizeof(prop), "atl%u", i);
cfg_node = of_get_child_by_name(node, prop);
if (cfg_node) {
ret = of_property_read_u32(cfg_node, "bws",
&cdesc->bws);
ret |= of_property_read_u32(cfg_node, "aws",
&cdesc->aws);
if (!ret) {
cdesc->valid = true;
atl_write(cinfo, DRA7_ATL_BWSMUX_REG(i),
cdesc->bws);
atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i),
cdesc->aws);
}
of_node_put(cfg_node);
}
cdesc->probed = true;
/*
* Enable the clock if it has been asked prior to loading the
* hw driver
*/
if (cdesc->enabled)
atl_clk_enable(__clk_get_hw(clk));
}
pm_put:
pm_runtime_put_sync(cinfo->dev);
return ret;
}
static const struct of_device_id of_dra7_atl_clk_match_tbl[] = {
{ .compatible = "ti,dra7-atl", },
{},
};
static struct platform_driver dra7_atl_clk_driver = {
.driver = {
.name = "dra7-atl",
.suppress_bind_attrs = true,
.of_match_table = of_dra7_atl_clk_match_tbl,
},
.probe = of_dra7_atl_clk_probe,
};
builtin_platform_driver(dra7_atl_clk_driver);
| linux-master | drivers/clk/ti/clk-dra7-atl.c |
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/math64.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"
/* FAPLL Control Register PLL_CTRL */
#define FAPLL_MAIN_MULT_N_SHIFT 16
#define FAPLL_MAIN_DIV_P_SHIFT 8
#define FAPLL_MAIN_LOCK BIT(7)
#define FAPLL_MAIN_PLLEN BIT(3)
#define FAPLL_MAIN_BP BIT(2)
#define FAPLL_MAIN_LOC_CTL BIT(0)
#define FAPLL_MAIN_MAX_MULT_N 0xffff
#define FAPLL_MAIN_MAX_DIV_P 0xff
#define FAPLL_MAIN_CLEAR_MASK \
((FAPLL_MAIN_MAX_MULT_N << FAPLL_MAIN_MULT_N_SHIFT) | \
(FAPLL_MAIN_DIV_P_SHIFT << FAPLL_MAIN_DIV_P_SHIFT) | \
FAPLL_MAIN_LOC_CTL)
/* FAPLL powerdown register PWD */
#define FAPLL_PWD_OFFSET 4
#define MAX_FAPLL_OUTPUTS 7
#define FAPLL_MAX_RETRIES 1000
#define to_fapll(_hw) container_of(_hw, struct fapll_data, hw)
#define to_synth(_hw) container_of(_hw, struct fapll_synth, hw)
/* The bypass bit is inverted on the ddr_pll.. */
#define fapll_is_ddr_pll(va) (((u32)(va) & 0xffff) == 0x0440)
/*
* The audio_pll_clk1 input is hard wired to the 27MHz bypass clock,
* and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output.
*/
#define is_ddr_pll_clk1(va) (((u32)(va) & 0xffff) == 0x044c)
#define is_audio_pll_clk1(va) (((u32)(va) & 0xffff) == 0x04a8)
/* Synthesizer divider register */
#define SYNTH_LDMDIV1 BIT(8)
/* Synthesizer frequency register */
#define SYNTH_LDFREQ BIT(31)
#define SYNTH_PHASE_K 8
#define SYNTH_MAX_INT_DIV 0xf
#define SYNTH_MAX_DIV_M 0xff
struct fapll_data {
struct clk_hw hw;
void __iomem *base;
const char *name;
struct clk *clk_ref;
struct clk *clk_bypass;
struct clk_onecell_data outputs;
bool bypass_bit_inverted;
};
struct fapll_synth {
struct clk_hw hw;
struct fapll_data *fd;
int index;
void __iomem *freq;
void __iomem *div;
const char *name;
struct clk *clk_pll;
};
static bool ti_fapll_clock_is_bypass(struct fapll_data *fd)
{
u32 v = readl_relaxed(fd->base);
if (fd->bypass_bit_inverted)
return !(v & FAPLL_MAIN_BP);
else
return !!(v & FAPLL_MAIN_BP);
}
static void ti_fapll_set_bypass(struct fapll_data *fd)
{
u32 v = readl_relaxed(fd->base);
if (fd->bypass_bit_inverted)
v &= ~FAPLL_MAIN_BP;
else
v |= FAPLL_MAIN_BP;
writel_relaxed(v, fd->base);
}
static void ti_fapll_clear_bypass(struct fapll_data *fd)
{
u32 v = readl_relaxed(fd->base);
if (fd->bypass_bit_inverted)
v |= FAPLL_MAIN_BP;
else
v &= ~FAPLL_MAIN_BP;
writel_relaxed(v, fd->base);
}
static int ti_fapll_wait_lock(struct fapll_data *fd)
{
int retries = FAPLL_MAX_RETRIES;
u32 v;
while ((v = readl_relaxed(fd->base))) {
if (v & FAPLL_MAIN_LOCK)
return 0;
if (retries-- <= 0)
break;
udelay(1);
}
pr_err("%s failed to lock\n", fd->name);
return -ETIMEDOUT;
}
static int ti_fapll_enable(struct clk_hw *hw)
{
struct fapll_data *fd = to_fapll(hw);
u32 v = readl_relaxed(fd->base);
v |= FAPLL_MAIN_PLLEN;
writel_relaxed(v, fd->base);
ti_fapll_wait_lock(fd);
return 0;
}
static void ti_fapll_disable(struct clk_hw *hw)
{
struct fapll_data *fd = to_fapll(hw);
u32 v = readl_relaxed(fd->base);
v &= ~FAPLL_MAIN_PLLEN;
writel_relaxed(v, fd->base);
}
static int ti_fapll_is_enabled(struct clk_hw *hw)
{
struct fapll_data *fd = to_fapll(hw);
u32 v = readl_relaxed(fd->base);
return v & FAPLL_MAIN_PLLEN;
}
static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct fapll_data *fd = to_fapll(hw);
u32 fapll_n, fapll_p, v;
u64 rate;
if (ti_fapll_clock_is_bypass(fd))
return parent_rate;
rate = parent_rate;
/* PLL pre-divider is P and multiplier is N */
v = readl_relaxed(fd->base);
fapll_p = (v >> 8) & 0xff;
if (fapll_p)
do_div(rate, fapll_p);
fapll_n = v >> 16;
if (fapll_n)
rate *= fapll_n;
return rate;
}
static u8 ti_fapll_get_parent(struct clk_hw *hw)
{
struct fapll_data *fd = to_fapll(hw);
if (ti_fapll_clock_is_bypass(fd))
return 1;
return 0;
}
static int ti_fapll_set_div_mult(unsigned long rate,
unsigned long parent_rate,
u32 *pre_div_p, u32 *mult_n)
{
/*
* So far no luck getting decent clock with PLL divider,
* PLL does not seem to lock and the signal does not look
* right. It seems the divider can only be used together
* with the multiplier?
*/
if (rate < parent_rate) {
pr_warn("FAPLL main divider rates unsupported\n");
return -EINVAL;
}
*mult_n = rate / parent_rate;
if (*mult_n > FAPLL_MAIN_MAX_MULT_N)
return -EINVAL;
*pre_div_p = 1;
return 0;
}
static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
u32 pre_div_p, mult_n;
int error;
if (!rate)
return -EINVAL;
error = ti_fapll_set_div_mult(rate, *parent_rate,
&pre_div_p, &mult_n);
if (error)
return error;
rate = *parent_rate / pre_div_p;
rate *= mult_n;
return rate;
}
static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct fapll_data *fd = to_fapll(hw);
u32 pre_div_p, mult_n, v;
int error;
if (!rate)
return -EINVAL;
error = ti_fapll_set_div_mult(rate, parent_rate,
&pre_div_p, &mult_n);
if (error)
return error;
ti_fapll_set_bypass(fd);
v = readl_relaxed(fd->base);
v &= ~FAPLL_MAIN_CLEAR_MASK;
v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT;
v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT;
writel_relaxed(v, fd->base);
if (ti_fapll_is_enabled(hw))
ti_fapll_wait_lock(fd);
ti_fapll_clear_bypass(fd);
return 0;
}
static const struct clk_ops ti_fapll_ops = {
.enable = ti_fapll_enable,
.disable = ti_fapll_disable,
.is_enabled = ti_fapll_is_enabled,
.recalc_rate = ti_fapll_recalc_rate,
.get_parent = ti_fapll_get_parent,
.round_rate = ti_fapll_round_rate,
.set_rate = ti_fapll_set_rate,
};
static int ti_fapll_synth_enable(struct clk_hw *hw)
{
struct fapll_synth *synth = to_synth(hw);
u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
v &= ~(1 << synth->index);
writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
return 0;
}
static void ti_fapll_synth_disable(struct clk_hw *hw)
{
struct fapll_synth *synth = to_synth(hw);
u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
v |= 1 << synth->index;
writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
}
static int ti_fapll_synth_is_enabled(struct clk_hw *hw)
{
struct fapll_synth *synth = to_synth(hw);
u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
return !(v & (1 << synth->index));
}
/*
* See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info
*/
static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct fapll_synth *synth = to_synth(hw);
u32 synth_div_m;
u64 rate;
/* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */
if (!synth->div)
return 32768;
/*
* PLL in bypass sets the synths in bypass mode too. The PLL rate
* can be also be set to 27MHz, so we can't use parent_rate to
* check for bypass mode.
*/
if (ti_fapll_clock_is_bypass(synth->fd))
return parent_rate;
rate = parent_rate;
/*
* Synth frequency integer and fractional divider.
* Note that the phase output K is 8, so the result needs
* to be multiplied by SYNTH_PHASE_K.
*/
if (synth->freq) {
u32 v, synth_int_div, synth_frac_div, synth_div_freq;
v = readl_relaxed(synth->freq);
synth_int_div = (v >> 24) & 0xf;
synth_frac_div = v & 0xffffff;
synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
rate *= 10000000;
do_div(rate, synth_div_freq);
rate *= SYNTH_PHASE_K;
}
/* Synth post-divider M */
synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
return DIV_ROUND_UP_ULL(rate, synth_div_m);
}
static unsigned long ti_fapll_synth_get_frac_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct fapll_synth *synth = to_synth(hw);
unsigned long current_rate, frac_rate;
u32 post_div_m;
current_rate = ti_fapll_synth_recalc_rate(hw, parent_rate);
post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
frac_rate = current_rate * post_div_m;
return frac_rate;
}
static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth,
unsigned long rate,
unsigned long parent_rate)
{
u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v;
post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate);
post_div_m = post_div_m / SYNTH_MAX_INT_DIV;
if (post_div_m > SYNTH_MAX_DIV_M)
return -EINVAL;
if (!post_div_m)
post_div_m = 1;
for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) {
synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate *
SYNTH_PHASE_K *
10000000,
rate * post_div_m);
synth_frac_div = synth_int_div % 10000000;
synth_int_div /= 10000000;
if (synth_int_div <= SYNTH_MAX_INT_DIV)
break;
}
if (synth_int_div > SYNTH_MAX_INT_DIV)
return -EINVAL;
v = readl_relaxed(synth->freq);
v &= ~0x1fffffff;
v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24;
v |= (synth_frac_div & 0xffffff);
v |= SYNTH_LDFREQ;
writel_relaxed(v, synth->freq);
return post_div_m;
}
static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct fapll_synth *synth = to_synth(hw);
struct fapll_data *fd = synth->fd;
unsigned long r;
if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
return -EINVAL;
/* Only post divider m available with no fractional divider? */
if (!synth->freq) {
unsigned long frac_rate;
u32 synth_post_div_m;
frac_rate = ti_fapll_synth_get_frac_rate(hw, *parent_rate);
synth_post_div_m = DIV_ROUND_UP(frac_rate, rate);
r = DIV_ROUND_UP(frac_rate, synth_post_div_m);
goto out;
}
r = *parent_rate * SYNTH_PHASE_K;
if (rate > r)
goto out;
r = DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M);
if (rate < r)
goto out;
r = rate;
out:
return r;
}
static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct fapll_synth *synth = to_synth(hw);
struct fapll_data *fd = synth->fd;
unsigned long frac_rate, post_rate = 0;
u32 post_div_m = 0, v;
if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
return -EINVAL;
/* Produce the rate with just post divider M? */
frac_rate = ti_fapll_synth_get_frac_rate(hw, parent_rate);
if (frac_rate < rate) {
if (!synth->freq)
return -EINVAL;
} else {
post_div_m = DIV_ROUND_UP(frac_rate, rate);
if (post_div_m && (post_div_m <= SYNTH_MAX_DIV_M))
post_rate = DIV_ROUND_UP(frac_rate, post_div_m);
if (!synth->freq && !post_rate)
return -EINVAL;
}
/* Need to recalculate the fractional divider? */
if ((post_rate != rate) && synth->freq)
post_div_m = ti_fapll_synth_set_frac_rate(synth,
rate,
parent_rate);
v = readl_relaxed(synth->div);
v &= ~SYNTH_MAX_DIV_M;
v |= post_div_m;
v |= SYNTH_LDMDIV1;
writel_relaxed(v, synth->div);
return 0;
}
static const struct clk_ops ti_fapll_synt_ops = {
.enable = ti_fapll_synth_enable,
.disable = ti_fapll_synth_disable,
.is_enabled = ti_fapll_synth_is_enabled,
.recalc_rate = ti_fapll_synth_recalc_rate,
.round_rate = ti_fapll_synth_round_rate,
.set_rate = ti_fapll_synth_set_rate,
};
static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd,
void __iomem *freq,
void __iomem *div,
int index,
const char *name,
const char *parent,
struct clk *pll_clk)
{
struct clk_init_data *init;
struct fapll_synth *synth;
struct clk *clk = ERR_PTR(-ENOMEM);
init = kzalloc(sizeof(*init), GFP_KERNEL);
if (!init)
return ERR_PTR(-ENOMEM);
init->ops = &ti_fapll_synt_ops;
init->name = name;
init->parent_names = &parent;
init->num_parents = 1;
synth = kzalloc(sizeof(*synth), GFP_KERNEL);
if (!synth)
goto free;
synth->fd = fd;
synth->index = index;
synth->freq = freq;
synth->div = div;
synth->name = name;
synth->hw.init = init;
synth->clk_pll = pll_clk;
clk = clk_register(NULL, &synth->hw);
if (IS_ERR(clk)) {
pr_err("failed to register clock\n");
goto free;
}
return clk;
free:
kfree(synth);
kfree(init);
return clk;
}
static void __init ti_fapll_setup(struct device_node *node)
{
struct fapll_data *fd;
struct clk_init_data *init = NULL;
const char *parent_name[2];
struct clk *pll_clk;
const char *name;
int i;
fd = kzalloc(sizeof(*fd), GFP_KERNEL);
if (!fd)
return;
fd->outputs.clks = kzalloc(sizeof(struct clk *) *
MAX_FAPLL_OUTPUTS + 1,
GFP_KERNEL);
if (!fd->outputs.clks)
goto free;
init = kzalloc(sizeof(*init), GFP_KERNEL);
if (!init)
goto free;
init->ops = &ti_fapll_ops;
name = ti_dt_clk_name(node);
init->name = name;
init->num_parents = of_clk_get_parent_count(node);
if (init->num_parents != 2) {
pr_err("%pOFn must have two parents\n", node);
goto free;
}
of_clk_parent_fill(node, parent_name, 2);
init->parent_names = parent_name;
fd->clk_ref = of_clk_get(node, 0);
if (IS_ERR(fd->clk_ref)) {
pr_err("%pOFn could not get clk_ref\n", node);
goto free;
}
fd->clk_bypass = of_clk_get(node, 1);
if (IS_ERR(fd->clk_bypass)) {
pr_err("%pOFn could not get clk_bypass\n", node);
goto free;
}
fd->base = of_iomap(node, 0);
if (!fd->base) {
pr_err("%pOFn could not get IO base\n", node);
goto free;
}
if (fapll_is_ddr_pll(fd->base))
fd->bypass_bit_inverted = true;
fd->name = name;
fd->hw.init = init;
/* Register the parent PLL */
pll_clk = clk_register(NULL, &fd->hw);
if (IS_ERR(pll_clk))
goto unmap;
fd->outputs.clks[0] = pll_clk;
fd->outputs.clk_num++;
/*
* Set up the child synthesizers starting at index 1 as the
* PLL output is at index 0. We need to check the clock-indices
* for numbering in case there are holes in the synth mapping,
* and then probe the synth register to see if it has a FREQ
* register available.
*/
for (i = 0; i < MAX_FAPLL_OUTPUTS; i++) {
const char *output_name;
void __iomem *freq, *div;
struct clk *synth_clk;
int output_instance;
u32 v;
if (of_property_read_string_index(node, "clock-output-names",
i, &output_name))
continue;
if (of_property_read_u32_index(node, "clock-indices", i,
&output_instance))
output_instance = i;
freq = fd->base + (output_instance * 8);
div = freq + 4;
/* Check for hardwired audio_pll_clk1 */
if (is_audio_pll_clk1(freq)) {
freq = NULL;
div = NULL;
} else {
/* Does the synthesizer have a FREQ register? */
v = readl_relaxed(freq);
if (!v)
freq = NULL;
}
synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance,
output_name, name, pll_clk);
if (IS_ERR(synth_clk))
continue;
fd->outputs.clks[output_instance] = synth_clk;
fd->outputs.clk_num++;
clk_register_clkdev(synth_clk, output_name, NULL);
}
/* Register the child synthesizers as the FAPLL outputs */
of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs);
/* Add clock alias for the outputs */
kfree(init);
return;
unmap:
iounmap(fd->base);
free:
if (fd->clk_bypass)
clk_put(fd->clk_bypass);
if (fd->clk_ref)
clk_put(fd->clk_ref);
kfree(fd->outputs.clks);
kfree(fd);
kfree(init);
}
CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup);
| linux-master | drivers/clk/ti/fapll.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI Fixed Factor Clock
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include "clock.h"
#undef pr_fmt
#define pr_fmt(fmt) "%s: " fmt, __func__
/**
* of_ti_fixed_factor_clk_setup - Setup function for TI fixed factor clock
* @node: device node for this clock
*
* Sets up a simple fixed factor clock based on device tree info.
*/
static void __init of_ti_fixed_factor_clk_setup(struct device_node *node)
{
struct clk *clk;
const char *clk_name = ti_dt_clk_name(node);
const char *parent_name;
u32 div, mult;
u32 flags = 0;
if (of_property_read_u32(node, "ti,clock-div", &div)) {
pr_err("%pOFn must have a clock-div property\n", node);
return;
}
if (of_property_read_u32(node, "ti,clock-mult", &mult)) {
pr_err("%pOFn must have a clock-mult property\n", node);
return;
}
if (of_property_read_bool(node, "ti,set-rate-parent"))
flags |= CLK_SET_RATE_PARENT;
parent_name = of_clk_get_parent_name(node, 0);
clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
mult, div);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
of_ti_clk_autoidle_setup(node);
ti_clk_add_alias(clk, clk_name);
}
}
CLK_OF_DECLARE(ti_fixed_factor_clk, "ti,fixed-factor-clock",
of_ti_fixed_factor_clk_setup);
| linux-master | drivers/clk/ti/fixed-factor.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP4-specific DPLL control functions
*
* Copyright (C) 2011 Texas Instruments, Inc.
* Rajendra Nayak
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/clk/ti.h>
#include "clock.h"
/*
* Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
* can supported when using the DPLL low-power mode. Frequencies are
* defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control,
* Status, and Low-Power Operation Mode".
*/
#define OMAP4_DPLL_LP_FINT_MAX 1000000
#define OMAP4_DPLL_LP_FOUT_MAX 100000000
/*
* Bitfield declarations
*/
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BIT(8)
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BIT(10)
#define OMAP4430_DPLL_REGM4XEN_MASK BIT(11)
/* Static rate multiplier for OMAP4 REGM4XEN clocks */
#define OMAP4430_REGM4XEN_MULT 4
static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
{
u32 v;
u32 mask;
if (!clk)
return;
mask = clk->flags & CLOCK_CLKOUTX2 ?
OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
/* Clear the bit to allow gatectrl */
v &= ~mask;
ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
}
static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
{
u32 v;
u32 mask;
if (!clk)
return;
mask = clk->flags & CLOCK_CLKOUTX2 ?
OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
/* Set the bit to deny gatectrl */
v |= mask;
ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
}
const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
.allow_idle = omap4_dpllmx_allow_gatectrl,
.deny_idle = omap4_dpllmx_deny_gatectrl,
};
/**
* omap4_dpll_lpmode_recalc - compute DPLL low-power setting
* @dd: pointer to the dpll data structure
*
* Calculates if low-power mode can be enabled based upon the last
* multiplier and divider values calculated. If low-power mode can be
* enabled, then the bit to enable low-power mode is stored in the
* last_rounded_lpmode variable. This implementation is based upon the
* criteria for enabling low-power mode as described in the OMAP4430/60
* Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power
* Operation Mode".
*/
static void omap4_dpll_lpmode_recalc(struct dpll_data *dd)
{
long fint, fout;
fint = clk_hw_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1);
fout = fint * dd->last_rounded_m;
if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX))
dd->last_rounded_lpmode = 1;
else
dd->last_rounded_lpmode = 0;
}
/**
* omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
* @hw: pointer to the clock to compute the rate for
* @parent_rate: clock rate of the DPLL parent
*
* Compute the output rate for the OMAP4 DPLL represented by @clk.
* Takes the REGM4XEN bit into consideration, which is needed for the
* OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
* upon success, or 0 upon error.
*/
unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
u32 v;
unsigned long rate;
struct dpll_data *dd;
if (!clk || !clk->dpll_data)
return 0;
dd = clk->dpll_data;
rate = omap2_get_dpll_rate(clk);
/* regm4xen adds a multiplier of 4 to DPLL calculations */
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
if (v & OMAP4430_DPLL_REGM4XEN_MASK)
rate *= OMAP4430_REGM4XEN_MULT;
return rate;
}
/**
* omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
* @hw: struct hw_clk containing the struct clk * of the DPLL to round a rate for
* @target_rate: the desired rate of the DPLL
* @parent_rate: clock rate of the DPLL parent
*
* Compute the rate that would be programmed into the DPLL hardware
* for @clk if set_rate() were to be provided with the rate
* @target_rate. Takes the REGM4XEN bit into consideration, which is
* needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
* M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
* ~0 if an error occurred in omap2_dpll_round_rate().
*/
long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
unsigned long target_rate,
unsigned long *parent_rate)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
struct dpll_data *dd;
long r;
if (!clk || !clk->dpll_data)
return -EINVAL;
dd = clk->dpll_data;
dd->last_rounded_m4xen = 0;
/*
* First try to compute the DPLL configuration for
* target rate without using the 4X multiplier.
*/
r = omap2_dpll_round_rate(hw, target_rate, NULL);
if (r != ~0)
goto out;
/*
* If we did not find a valid DPLL configuration, try again, but
* this time see if using the 4X multiplier can help. Enabling the
* 4X multiplier is equivalent to dividing the target rate by 4.
*/
r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT,
NULL);
if (r == ~0)
return r;
dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
dd->last_rounded_m4xen = 1;
out:
omap4_dpll_lpmode_recalc(dd);
return dd->last_rounded_rate;
}
/**
* omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
* @hw: pointer to the clock to determine rate for
* @req: target rate request
*
* Determines which DPLL mode to use for reaching a desired rate.
* Checks whether the DPLL shall be in bypass or locked mode, and if
* locked, calculates the M,N values for the DPLL via round-rate.
* Returns 0 on success and a negative error value otherwise.
*/
int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
struct dpll_data *dd;
if (!req->rate)
return -EINVAL;
dd = clk->dpll_data;
if (!dd)
return -EINVAL;
if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&
(dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
req->best_parent_hw = dd->clk_bypass;
} else {
req->rate = omap4_dpll_regm4xen_round_rate(hw, req->rate,
&req->best_parent_rate);
req->best_parent_hw = dd->clk_ref;
}
req->best_parent_rate = req->rate;
return 0;
}
| linux-master | drivers/clk/ti/dpll44xx.c |
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
#include <linux/of_platform.h>
#include <dt-bindings/clock/dm814.h>
#include "clock.h"
static const struct omap_clkctrl_reg_data dm814_default_clkctrl_regs[] __initconst = {
{ DM814_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "pll260dcoclkldo" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst = {
{ DM814_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ DM814_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ DM814_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
{ DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" },
{ DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
{ DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM814_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM814_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM814_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM814_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM814_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
{ DM814_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
{ DM814_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
{ 0 },
};
static const struct
omap_clkctrl_reg_data dm814_alwon_ethernet_clkctrl_regs[] __initconst = {
{ 0, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
};
const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = {
{ 0x48180500, dm814_default_clkctrl_regs },
{ 0x48181400, dm814_alwon_clkctrl_regs },
{ 0x481815d4, dm814_alwon_ethernet_clkctrl_regs },
{ 0 },
};
static struct ti_dt_clk dm814_clks[] = {
DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
{ .node_name = NULL },
};
static bool timer_clocks_initialized;
static int __init dm814x_adpll_early_init(void)
{
struct device_node *np;
if (!timer_clocks_initialized)
return -ENODEV;
np = of_find_node_by_name(NULL, "pllss");
if (!np) {
pr_err("Could not find node for plls\n");
return -ENODEV;
}
of_platform_populate(np, NULL, NULL, NULL);
of_node_put(np);
return 0;
}
core_initcall(dm814x_adpll_early_init);
static const char * const init_clocks[] = {
"pll040clkout", /* MPU 481c5040.adpll.clkout */
"pll290clkout", /* DDR 481c5290.adpll.clkout */
};
static int __init dm814x_adpll_enable_init_clocks(void)
{
int i, err;
if (!timer_clocks_initialized)
return -ENODEV;
for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
struct clk *clock;
clock = clk_get(NULL, init_clocks[i]);
if (WARN(IS_ERR(clock), "could not find init clock %s\n",
init_clocks[i]))
continue;
err = clk_prepare_enable(clock);
if (WARN(err, "could not enable init clock %s\n",
init_clocks[i]))
continue;
}
return 0;
}
postcore_initcall(dm814x_adpll_enable_init_clocks);
int __init dm814x_dt_clk_init(void)
{
ti_dt_clocks_register(dm814_clks);
omap2_clk_disable_autoidle_all();
ti_clk_add_aliases();
omap2_clk_enable_init_clocks(NULL, 0);
timer_clocks_initialized = true;
return 0;
}
| linux-master | drivers/clk/ti/clk-814x.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016-2017 Imagination Technologies
* Author: Paul Burton <[email protected]>
*/
#define pr_fmt(fmt) "clk-boston: " fmt
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/mfd/syscon.h>
#include <dt-bindings/clock/boston-clock.h>
#define BOSTON_PLAT_MMCMDIV 0x30
# define BOSTON_PLAT_MMCMDIV_CLK0DIV (0xff << 0)
# define BOSTON_PLAT_MMCMDIV_INPUT (0xff << 8)
# define BOSTON_PLAT_MMCMDIV_MUL (0xff << 16)
# define BOSTON_PLAT_MMCMDIV_CLK1DIV (0xff << 24)
#define BOSTON_CLK_COUNT 3
static u32 ext_field(u32 val, u32 mask)
{
return (val & mask) >> (ffs(mask) - 1);
}
static void __init clk_boston_setup(struct device_node *np)
{
unsigned long in_freq, cpu_freq, sys_freq;
uint mmcmdiv, mul, cpu_div, sys_div;
struct clk_hw_onecell_data *onecell;
struct regmap *regmap;
struct clk_hw *hw;
int err;
regmap = syscon_node_to_regmap(np->parent);
if (IS_ERR(regmap)) {
pr_err("failed to find regmap\n");
return;
}
err = regmap_read(regmap, BOSTON_PLAT_MMCMDIV, &mmcmdiv);
if (err) {
pr_err("failed to read mmcm_div register: %d\n", err);
return;
}
in_freq = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_INPUT) * 1000000;
mul = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_MUL);
sys_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK0DIV);
sys_freq = mult_frac(in_freq, mul, sys_div);
cpu_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK1DIV);
cpu_freq = mult_frac(in_freq, mul, cpu_div);
onecell = kzalloc(struct_size(onecell, hws, BOSTON_CLK_COUNT),
GFP_KERNEL);
if (!onecell)
return;
onecell->num = BOSTON_CLK_COUNT;
hw = clk_hw_register_fixed_rate(NULL, "input", NULL, 0, in_freq);
if (IS_ERR(hw)) {
pr_err("failed to register input clock: %ld\n", PTR_ERR(hw));
goto fail_input;
}
onecell->hws[BOSTON_CLK_INPUT] = hw;
hw = clk_hw_register_fixed_rate(NULL, "sys", "input", 0, sys_freq);
if (IS_ERR(hw)) {
pr_err("failed to register sys clock: %ld\n", PTR_ERR(hw));
goto fail_sys;
}
onecell->hws[BOSTON_CLK_SYS] = hw;
hw = clk_hw_register_fixed_rate(NULL, "cpu", "input", 0, cpu_freq);
if (IS_ERR(hw)) {
pr_err("failed to register cpu clock: %ld\n", PTR_ERR(hw));
goto fail_cpu;
}
onecell->hws[BOSTON_CLK_CPU] = hw;
err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, onecell);
if (err) {
pr_err("failed to add DT provider: %d\n", err);
goto fail_clk_add;
}
return;
fail_clk_add:
clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_CPU]);
fail_cpu:
clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_SYS]);
fail_sys:
clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_INPUT]);
fail_input:
kfree(onecell);
}
/*
* Use CLK_OF_DECLARE so that this driver is probed early enough to provide the
* CPU frequency for use with the GIC or cop0 counters/timers.
*/
CLK_OF_DECLARE(clk_boston, "img,boston-clock", clk_boston_setup);
| linux-master | drivers/clk/imgtec/clk-boston.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MFD driver for Active-semi ACT8945a PMIC
*
* Copyright (C) 2015 Atmel Corporation.
*
* Author: Wenyou Yang <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
static const struct mfd_cell act8945a_devs[] = {
{
.name = "act8945a-regulator",
},
{
.name = "act8945a-charger",
.of_compatible = "active-semi,act8945a-charger",
},
};
static const struct regmap_config act8945a_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
static int act8945a_i2c_probe(struct i2c_client *i2c)
{
int ret;
struct regmap *regmap;
regmap = devm_regmap_init_i2c(i2c, &act8945a_regmap_config);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
dev_err(&i2c->dev, "regmap init failed: %d\n", ret);
return ret;
}
i2c_set_clientdata(i2c, regmap);
ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_NONE,
act8945a_devs, ARRAY_SIZE(act8945a_devs),
NULL, 0, NULL);
if (ret) {
dev_err(&i2c->dev, "Failed to add sub devices\n");
return ret;
}
return 0;
}
static const struct i2c_device_id act8945a_i2c_id[] = {
{ "act8945a", 0 },
{}
};
MODULE_DEVICE_TABLE(i2c, act8945a_i2c_id);
static const struct of_device_id act8945a_of_match[] = {
{ .compatible = "active-semi,act8945a", },
{},
};
MODULE_DEVICE_TABLE(of, act8945a_of_match);
static struct i2c_driver act8945a_i2c_driver = {
.driver = {
.name = "act8945a",
.of_match_table = act8945a_of_match,
},
.probe = act8945a_i2c_probe,
.id_table = act8945a_i2c_id,
};
static int __init act8945a_i2c_init(void)
{
return i2c_add_driver(&act8945a_i2c_driver);
}
subsys_initcall(act8945a_i2c_init);
static void __exit act8945a_i2c_exit(void)
{
i2c_del_driver(&act8945a_i2c_driver);
}
module_exit(act8945a_i2c_exit);
MODULE_DESCRIPTION("ACT8945A PMIC multi-function driver");
MODULE_AUTHOR("Wenyou Yang <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/act8945a.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm5110-tables.c -- WM5110 data tables
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/module.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/registers.h>
#include <linux/device.h>
#include "arizona.h"
#define WM5110_NUM_AOD_ISR 2
#define WM5110_NUM_ISR 5
static const struct reg_sequence wm5110_reva_patch[] = {
{ 0x80, 0x3 },
{ 0x44, 0x20 },
{ 0x45, 0x40 },
{ 0x46, 0x60 },
{ 0x47, 0x80 },
{ 0x48, 0xa0 },
{ 0x51, 0x13 },
{ 0x52, 0x33 },
{ 0x53, 0x53 },
{ 0x54, 0x73 },
{ 0x55, 0x75 },
{ 0x56, 0xb3 },
{ 0x2ef, 0x124 },
{ 0x2ef, 0x124 },
{ 0x2f0, 0x124 },
{ 0x2f0, 0x124 },
{ 0x2f1, 0x124 },
{ 0x2f1, 0x124 },
{ 0x2f2, 0x124 },
{ 0x2f2, 0x124 },
{ 0x2f3, 0x124 },
{ 0x2f3, 0x124 },
{ 0x2f4, 0x124 },
{ 0x2f4, 0x124 },
{ 0x2eb, 0x60 },
{ 0x2ec, 0x60 },
{ 0x2ed, 0x60 },
{ 0xc30, 0x3e3e },
{ 0xc30, 0x3e3e },
{ 0xc31, 0x3e },
{ 0xc32, 0x3e3e },
{ 0xc32, 0x3e3e },
{ 0xc33, 0x3e3e },
{ 0xc33, 0x3e3e },
{ 0xc34, 0x3e3e },
{ 0xc34, 0x3e3e },
{ 0xc35, 0x3e3e },
{ 0xc35, 0x3e3e },
{ 0xc36, 0x3e3e },
{ 0xc36, 0x3e3e },
{ 0xc37, 0x3e3e },
{ 0xc37, 0x3e3e },
{ 0xc38, 0x3e3e },
{ 0xc38, 0x3e3e },
{ 0xc30, 0x3e3e },
{ 0xc30, 0x3e3e },
{ 0xc39, 0x3e3e },
{ 0xc39, 0x3e3e },
{ 0xc3a, 0x3e3e },
{ 0xc3a, 0x3e3e },
{ 0xc3b, 0x3e3e },
{ 0xc3b, 0x3e3e },
{ 0xc3c, 0x3e },
{ 0x201, 0x18a5 },
{ 0x201, 0x18a5 },
{ 0x201, 0x18a5 },
{ 0x202, 0x4100 },
{ 0x460, 0xc00 },
{ 0x461, 0x8000 },
{ 0x462, 0xc01 },
{ 0x463, 0x50f0 },
{ 0x464, 0xc01 },
{ 0x465, 0x4820 },
{ 0x466, 0xc01 },
{ 0x466, 0xc01 },
{ 0x467, 0x4040 },
{ 0x468, 0xc01 },
{ 0x468, 0xc01 },
{ 0x469, 0x3940 },
{ 0x46a, 0xc01 },
{ 0x46a, 0xc01 },
{ 0x46a, 0xc01 },
{ 0x46b, 0x3310 },
{ 0x46c, 0x801 },
{ 0x46c, 0x801 },
{ 0x46d, 0x2d80 },
{ 0x46e, 0x801 },
{ 0x46e, 0x801 },
{ 0x46f, 0x2890 },
{ 0x470, 0x801 },
{ 0x470, 0x801 },
{ 0x471, 0x1990 },
{ 0x472, 0x801 },
{ 0x472, 0x801 },
{ 0x473, 0x1450 },
{ 0x474, 0x801 },
{ 0x474, 0x801 },
{ 0x474, 0x801 },
{ 0x475, 0x1020 },
{ 0x476, 0x801 },
{ 0x476, 0x801 },
{ 0x476, 0x801 },
{ 0x477, 0xcd0 },
{ 0x478, 0x806 },
{ 0x478, 0x806 },
{ 0x479, 0xa30 },
{ 0x47a, 0x806 },
{ 0x47a, 0x806 },
{ 0x47b, 0x810 },
{ 0x47c, 0x80e },
{ 0x47c, 0x80e },
{ 0x47d, 0x510 },
{ 0x47e, 0x81f },
{ 0x47e, 0x81f },
{ 0x2DB, 0x0A00 },
{ 0x2DD, 0x0023 },
{ 0x2DF, 0x0102 },
{ 0x80, 0x0 },
{ 0xC20, 0x0002 },
{ 0x209, 0x002A },
};
static const struct reg_sequence wm5110_revb_patch[] = {
{ 0x80, 0x3 },
{ 0x36e, 0x0210 },
{ 0x370, 0x0210 },
{ 0x372, 0x0210 },
{ 0x374, 0x0210 },
{ 0x376, 0x0210 },
{ 0x378, 0x0210 },
{ 0x36d, 0x0028 },
{ 0x36f, 0x0028 },
{ 0x371, 0x0028 },
{ 0x373, 0x0028 },
{ 0x375, 0x0028 },
{ 0x377, 0x0028 },
{ 0x280, 0x2002 },
{ 0x44, 0x20 },
{ 0x45, 0x40 },
{ 0x46, 0x60 },
{ 0x47, 0x80 },
{ 0x48, 0xa0 },
{ 0x51, 0x13 },
{ 0x52, 0x33 },
{ 0x53, 0x53 },
{ 0x54, 0x73 },
{ 0x55, 0x93 },
{ 0x56, 0xb3 },
{ 0xc30, 0x3e3e },
{ 0xc31, 0x3e },
{ 0xc32, 0x3e3e },
{ 0xc33, 0x3e3e },
{ 0xc34, 0x3e3e },
{ 0xc35, 0x3e3e },
{ 0xc36, 0x3e3e },
{ 0xc37, 0x3e3e },
{ 0xc38, 0x3e3e },
{ 0xc39, 0x3e3e },
{ 0xc3a, 0x3e3e },
{ 0xc3b, 0x3e3e },
{ 0xc3c, 0x3e },
{ 0x201, 0x18a5 },
{ 0x202, 0x4100 },
{ 0x460, 0x0c40 },
{ 0x461, 0x8000 },
{ 0x462, 0x0c41 },
{ 0x463, 0x4820 },
{ 0x464, 0x0c41 },
{ 0x465, 0x4040 },
{ 0x466, 0x0841 },
{ 0x467, 0x3940 },
{ 0x468, 0x0841 },
{ 0x469, 0x2030 },
{ 0x46a, 0x0842 },
{ 0x46b, 0x1990 },
{ 0x46c, 0x08c2 },
{ 0x46d, 0x1450 },
{ 0x46e, 0x08c6 },
{ 0x46f, 0x1020 },
{ 0x470, 0x08c6 },
{ 0x471, 0x0cd0 },
{ 0x472, 0x08c6 },
{ 0x473, 0x0a30 },
{ 0x474, 0x0442 },
{ 0x475, 0x0660 },
{ 0x476, 0x0446 },
{ 0x477, 0x0510 },
{ 0x478, 0x04c6 },
{ 0x479, 0x0400 },
{ 0x47a, 0x04ce },
{ 0x47b, 0x0330 },
{ 0x47c, 0x05df },
{ 0x47d, 0x0001 },
{ 0x47e, 0x07ff },
{ 0x2db, 0x0a00 },
{ 0x2dd, 0x0023 },
{ 0x2df, 0x0102 },
{ 0x2ef, 0x924 },
{ 0x2f0, 0x924 },
{ 0x2f1, 0x924 },
{ 0x2f2, 0x924 },
{ 0x2f3, 0x924 },
{ 0x2f4, 0x924 },
{ 0x2eb, 0x60 },
{ 0x2ec, 0x60 },
{ 0x2ed, 0x60 },
{ 0x4f2, 0x33e },
{ 0x458, 0x0000 },
{ 0x15a, 0x0003 },
{ 0x80, 0x0 },
};
static const struct reg_sequence wm5110_revd_patch[] = {
{ 0x80, 0x3 },
{ 0x80, 0x3 },
{ 0x393, 0x27 },
{ 0x394, 0x27 },
{ 0x395, 0x27 },
{ 0x396, 0x27 },
{ 0x397, 0x27 },
{ 0x398, 0x26 },
{ 0x221, 0x90 },
{ 0x211, 0x8 },
{ 0x36c, 0x1fb },
{ 0x26e, 0x64 },
{ 0x26f, 0xea },
{ 0x270, 0x1f16 },
{ 0x51b, 0x1 },
{ 0x55b, 0x1 },
{ 0x59b, 0x1 },
{ 0x4f0, 0x633 },
{ 0x441, 0xc059 },
{ 0x209, 0x27 },
{ 0x80, 0x0 },
{ 0x80, 0x0 },
};
/* Add extra headphone write sequence locations */
static const struct reg_sequence wm5110_reve_patch[] = {
{ 0x80, 0x3 },
{ 0x80, 0x3 },
{ 0x4b, 0x138 },
{ 0x4c, 0x13d },
{ 0x80, 0x0 },
{ 0x80, 0x0 },
};
/* We use a function so we can use ARRAY_SIZE() */
int wm5110_patch(struct arizona *arizona)
{
switch (arizona->rev) {
case 0:
return regmap_register_patch(arizona->regmap,
wm5110_reva_patch,
ARRAY_SIZE(wm5110_reva_patch));
case 1:
return regmap_register_patch(arizona->regmap,
wm5110_revb_patch,
ARRAY_SIZE(wm5110_revb_patch));
case 3:
return regmap_register_patch(arizona->regmap,
wm5110_revd_patch,
ARRAY_SIZE(wm5110_revd_patch));
default:
return regmap_register_patch(arizona->regmap,
wm5110_reve_patch,
ARRAY_SIZE(wm5110_reve_patch));
}
}
EXPORT_SYMBOL_GPL(wm5110_patch);
static const struct regmap_irq wm5110_aod_irqs[ARIZONA_NUM_IRQ] = {
[ARIZONA_IRQ_MICD_CLAMP_FALL] = {
.mask = ARIZONA_MICD_CLAMP_FALL_EINT1
},
[ARIZONA_IRQ_MICD_CLAMP_RISE] = {
.mask = ARIZONA_MICD_CLAMP_RISE_EINT1
},
[ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 },
[ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 },
[ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 },
[ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 },
};
const struct regmap_irq_chip wm5110_aod = {
.name = "wm5110 AOD",
.status_base = ARIZONA_AOD_IRQ1,
.mask_base = ARIZONA_AOD_IRQ_MASK_IRQ1,
.ack_base = ARIZONA_AOD_IRQ1,
.wake_base = ARIZONA_WAKE_CONTROL,
.wake_invert = 1,
.num_regs = 1,
.irqs = wm5110_aod_irqs,
.num_irqs = ARRAY_SIZE(wm5110_aod_irqs),
};
EXPORT_SYMBOL_GPL(wm5110_aod);
static const struct regmap_irq wm5110_irqs[ARIZONA_NUM_IRQ] = {
[ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
[ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
[ARIZONA_IRQ_DSP4_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP3_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP2_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP1_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP_IRQ8] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
},
[ARIZONA_IRQ_DSP_IRQ7] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
},
[ARIZONA_IRQ_DSP_IRQ6] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1
},
[ARIZONA_IRQ_DSP_IRQ5] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1
},
[ARIZONA_IRQ_DSP_IRQ4] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1
},
[ARIZONA_IRQ_DSP_IRQ3] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1
},
[ARIZONA_IRQ_DSP_IRQ2] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
},
[ARIZONA_IRQ_DSP_IRQ1] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT_WARN] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
},
[ARIZONA_IRQ_HPDET] = {
.reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
},
[ARIZONA_IRQ_MICDET] = {
.reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
},
[ARIZONA_IRQ_WSEQ_DONE] = {
.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
},
[ARIZONA_IRQ_DRC2_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1
},
[ARIZONA_IRQ_DRC1_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
},
[ARIZONA_IRQ_ASRC2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1
},
[ARIZONA_IRQ_ASRC1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1
},
[ARIZONA_IRQ_UNDERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1
},
[ARIZONA_IRQ_OVERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1
},
[ARIZONA_IRQ_FLL2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
},
[ARIZONA_IRQ_FLL1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1
},
[ARIZONA_IRQ_ASRC_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1
},
[ARIZONA_IRQ_AIF3_ERR] = {
.reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1
},
[ARIZONA_IRQ_AIF2_ERR] = {
.reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1
},
[ARIZONA_IRQ_AIF1_ERR] = {
.reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1
},
[ARIZONA_IRQ_CTRLIF_ERR] = {
.reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1
},
[ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = {
.reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1
},
[ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_SYSCLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_ISRC1_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1
},
[ARIZONA_IRQ_ISRC2_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1
},
[ARIZONA_IRQ_HP3R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP3R_DONE_EINT1
},
[ARIZONA_IRQ_HP3L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP3L_DONE_EINT1
},
[ARIZONA_IRQ_HP2R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP2R_DONE_EINT1
},
[ARIZONA_IRQ_HP2L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP2L_DONE_EINT1
},
[ARIZONA_IRQ_HP1R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1
},
[ARIZONA_IRQ_HP1L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1
},
[ARIZONA_IRQ_BOOT_DONE] = {
.reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1
},
[ARIZONA_IRQ_FLL2_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1
},
[ARIZONA_IRQ_FLL1_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1
},
};
const struct regmap_irq_chip wm5110_irq = {
.name = "wm5110 IRQ",
.status_base = ARIZONA_INTERRUPT_STATUS_1,
.mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK,
.ack_base = ARIZONA_INTERRUPT_STATUS_1,
.num_regs = 5,
.irqs = wm5110_irqs,
.num_irqs = ARRAY_SIZE(wm5110_irqs),
};
EXPORT_SYMBOL_GPL(wm5110_irq);
static const struct regmap_irq wm5110_revd_irqs[ARIZONA_NUM_IRQ] = {
[ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
[ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
[ARIZONA_IRQ_DSP4_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP3_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP2_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP1_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP_IRQ8] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
},
[ARIZONA_IRQ_DSP_IRQ7] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
},
[ARIZONA_IRQ_DSP_IRQ6] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1
},
[ARIZONA_IRQ_DSP_IRQ5] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1
},
[ARIZONA_IRQ_DSP_IRQ4] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1
},
[ARIZONA_IRQ_DSP_IRQ3] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1
},
[ARIZONA_IRQ_DSP_IRQ2] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
},
[ARIZONA_IRQ_DSP_IRQ1] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT_WARN] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
},
[ARIZONA_IRQ_HPDET] = {
.reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
},
[ARIZONA_IRQ_MICDET] = {
.reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
},
[ARIZONA_IRQ_WSEQ_DONE] = {
.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
},
[ARIZONA_IRQ_DRC2_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1
},
[ARIZONA_IRQ_DRC1_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
},
[ARIZONA_IRQ_ASRC2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1
},
[ARIZONA_IRQ_ASRC1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1
},
[ARIZONA_IRQ_UNDERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1
},
[ARIZONA_IRQ_OVERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1
},
[ARIZONA_IRQ_FLL2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
},
[ARIZONA_IRQ_FLL1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1
},
[ARIZONA_IRQ_CTRLIF_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_CTRLIF_ERR_EINT1
},
[ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = {
.reg_offset = 3, .mask = ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1
},
[ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_SYSCLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_V2_SYSCLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_ISRC1_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_ISRC1_CFG_ERR_EINT1
},
[ARIZONA_IRQ_ISRC2_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_ISRC2_CFG_ERR_EINT1
},
[ARIZONA_IRQ_ISRC3_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_ISRC3_CFG_ERR_EINT1
},
[ARIZONA_IRQ_HP3R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP3R_DONE_EINT1
},
[ARIZONA_IRQ_HP3L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP3L_DONE_EINT1
},
[ARIZONA_IRQ_HP2R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP2R_DONE_EINT1
},
[ARIZONA_IRQ_HP2L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP2L_DONE_EINT1
},
[ARIZONA_IRQ_HP1R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1
},
[ARIZONA_IRQ_HP1L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1
},
[ARIZONA_IRQ_BOOT_DONE] = {
.reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1
},
[ARIZONA_IRQ_ASRC_CFG_ERR] = {
.reg_offset = 4, .mask = ARIZONA_V2_ASRC_CFG_ERR_EINT1
},
[ARIZONA_IRQ_FLL2_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1
},
[ARIZONA_IRQ_FLL1_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1
},
[ARIZONA_IRQ_DSP_SHARED_WR_COLL] = {
.reg_offset = 5, .mask = ARIZONA_DSP_SHARED_WR_COLL_EINT1
},
[ARIZONA_IRQ_SPK_SHUTDOWN] = {
.reg_offset = 5, .mask = ARIZONA_SPK_SHUTDOWN_EINT1
},
[ARIZONA_IRQ_SPK1R_SHORT] = {
.reg_offset = 5, .mask = ARIZONA_SPK1R_SHORT_EINT1
},
[ARIZONA_IRQ_SPK1L_SHORT] = {
.reg_offset = 5, .mask = ARIZONA_SPK1L_SHORT_EINT1
},
[ARIZONA_IRQ_HP3R_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP3R_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP3R_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP3R_SC_POS_EINT1
},
[ARIZONA_IRQ_HP3L_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP3L_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP3L_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP3L_SC_POS_EINT1
},
[ARIZONA_IRQ_HP2R_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP2R_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP2R_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP2R_SC_POS_EINT1
},
[ARIZONA_IRQ_HP2L_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP2L_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP2L_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP2L_SC_POS_EINT1
},
[ARIZONA_IRQ_HP1R_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP1R_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP1R_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP1R_SC_POS_EINT1
},
[ARIZONA_IRQ_HP1L_SC_NEG] = {
.reg_offset = 5, .mask = ARIZONA_HP1L_SC_NEG_EINT1
},
[ARIZONA_IRQ_HP1L_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP1L_SC_POS_EINT1
},
};
const struct regmap_irq_chip wm5110_revd_irq = {
.name = "wm5110 IRQ",
.status_base = ARIZONA_INTERRUPT_STATUS_1,
.mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK,
.ack_base = ARIZONA_INTERRUPT_STATUS_1,
.num_regs = 6,
.irqs = wm5110_revd_irqs,
.num_irqs = ARRAY_SIZE(wm5110_revd_irqs),
};
EXPORT_SYMBOL_GPL(wm5110_revd_irq);
static const struct reg_default wm5110_reg_default[] = {
{ 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */
{ 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */
{ 0x0000000A, 0x0001 }, /* R10 - Ctrl IF I2C2 CFG 1 */
{ 0x0000000B, 0x001A }, /* R11 - Ctrl IF I2C1 CFG 2 */
{ 0x0000000C, 0x001A }, /* R12 - Ctrl IF I2C2 CFG 2 */
{ 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */
{ 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */
{ 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */
{ 0x00000023, 0x1000 }, /* R35 - Tone Generator 4 */
{ 0x00000024, 0x0000 }, /* R36 - Tone Generator 5 */
{ 0x00000030, 0x0000 }, /* R48 - PWM Drive 1 */
{ 0x00000031, 0x0100 }, /* R49 - PWM Drive 2 */
{ 0x00000032, 0x0100 }, /* R50 - PWM Drive 3 */
{ 0x00000040, 0x0000 }, /* R64 - Wake control */
{ 0x00000041, 0x0000 }, /* R65 - Sequence control */
{ 0x00000042, 0x0000 }, /* R66 - Spare Triggers */
{ 0x00000061, 0x01FF }, /* R97 - Sample Rate Sequence Select 1 */
{ 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */
{ 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */
{ 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */
{ 0x00000066, 0x01FF }, /* R102 - Always On Triggers Sequence Select 1 */
{ 0x00000067, 0x01FF }, /* R103 - Always On Triggers Sequence Select 2 */
{ 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 3 */
{ 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 4 */
{ 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 5 */
{ 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 6 */
{ 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */
{ 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */
{ 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */
{ 0x00000092, 0x0000 }, /* R146 - Haptics phase 1 intensity */
{ 0x00000093, 0x0000 }, /* R147 - Haptics phase 1 duration */
{ 0x00000094, 0x0000 }, /* R148 - Haptics phase 2 intensity */
{ 0x00000095, 0x0000 }, /* R149 - Haptics phase 2 duration */
{ 0x00000096, 0x0000 }, /* R150 - Haptics phase 3 intensity */
{ 0x00000097, 0x0000 }, /* R151 - Haptics phase 3 duration */
{ 0x00000100, 0x0001 }, /* R256 - Clock 32k 1 */
{ 0x00000101, 0x0504 }, /* R257 - System Clock 1 */
{ 0x00000102, 0x0011 }, /* R258 - Sample rate 1 */
{ 0x00000103, 0x0011 }, /* R259 - Sample rate 2 */
{ 0x00000104, 0x0011 }, /* R260 - Sample rate 3 */
{ 0x00000112, 0x0305 }, /* R274 - Async clock 1 */
{ 0x00000113, 0x0011 }, /* R275 - Async sample rate 1 */
{ 0x00000114, 0x0011 }, /* R276 - Async sample rate 2 */
{ 0x00000149, 0x0000 }, /* R329 - Output system clock */
{ 0x0000014A, 0x0000 }, /* R330 - Output async clock */
{ 0x00000152, 0x0000 }, /* R338 - Rate Estimator 1 */
{ 0x00000153, 0x0000 }, /* R339 - Rate Estimator 2 */
{ 0x00000154, 0x0000 }, /* R340 - Rate Estimator 3 */
{ 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */
{ 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */
{ 0x00000171, 0x0002 }, /* R369 - FLL1 Control 1 */
{ 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */
{ 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */
{ 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */
{ 0x00000175, 0x0006 }, /* R373 - FLL1 Control 5 */
{ 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */
{ 0x00000179, 0x0000 }, /* R376 - FLL1 Control 7 */
{ 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */
{ 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */
{ 0x00000183, 0x0000 }, /* R387 - FLL1 Synchroniser 3 */
{ 0x00000184, 0x0000 }, /* R388 - FLL1 Synchroniser 4 */
{ 0x00000185, 0x0000 }, /* R389 - FLL1 Synchroniser 5 */
{ 0x00000186, 0x0000 }, /* R390 - FLL1 Synchroniser 6 */
{ 0x00000187, 0x0001 }, /* R390 - FLL1 Synchroniser 7 */
{ 0x00000189, 0x0000 }, /* R393 - FLL1 Spread Spectrum */
{ 0x0000018A, 0x000C }, /* R394 - FLL1 GPIO Clock */
{ 0x00000191, 0x0002 }, /* R401 - FLL2 Control 1 */
{ 0x00000192, 0x0008 }, /* R402 - FLL2 Control 2 */
{ 0x00000193, 0x0018 }, /* R403 - FLL2 Control 3 */
{ 0x00000194, 0x007D }, /* R404 - FLL2 Control 4 */
{ 0x00000195, 0x000C }, /* R405 - FLL2 Control 5 */
{ 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */
{ 0x00000199, 0x0000 }, /* R408 - FLL2 Control 7 */
{ 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */
{ 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */
{ 0x000001A3, 0x0000 }, /* R419 - FLL2 Synchroniser 3 */
{ 0x000001A4, 0x0000 }, /* R420 - FLL2 Synchroniser 4 */
{ 0x000001A5, 0x0000 }, /* R421 - FLL2 Synchroniser 5 */
{ 0x000001A6, 0x0000 }, /* R422 - FLL2 Synchroniser 6 */
{ 0x000001A7, 0x0001 }, /* R422 - FLL2 Synchroniser 7 */
{ 0x000001A9, 0x0000 }, /* R425 - FLL2 Spread Spectrum */
{ 0x000001AA, 0x000C }, /* R426 - FLL2 GPIO Clock */
{ 0x00000200, 0x0006 }, /* R512 - Mic Charge Pump 1 */
{ 0x00000210, 0x0184 }, /* R528 - LDO1 Control 1 */
{ 0x00000213, 0x03E4 }, /* R531 - LDO2 Control 1 */
{ 0x00000218, 0x00E6 }, /* R536 - Mic Bias Ctrl 1 */
{ 0x00000219, 0x00E6 }, /* R537 - Mic Bias Ctrl 2 */
{ 0x0000021A, 0x00E6 }, /* R538 - Mic Bias Ctrl 3 */
{ 0x00000293, 0x0000 }, /* R659 - Accessory Detect Mode 1 */
{ 0x0000029B, 0x0028 }, /* R667 - Headphone Detect 1 */
{ 0x000002A2, 0x0000 }, /* R674 - Micd clamp control */
{ 0x000002A3, 0x1102 }, /* R675 - Mic Detect 1 */
{ 0x000002A4, 0x009F }, /* R676 - Mic Detect 2 */
{ 0x000002A6, 0x3737 }, /* R678 - Mic Detect Level 1 */
{ 0x000002A7, 0x2C37 }, /* R679 - Mic Detect Level 2 */
{ 0x000002A8, 0x1422 }, /* R680 - Mic Detect Level 3 */
{ 0x000002A9, 0x030A }, /* R681 - Mic Detect Level 4 */
{ 0x000002C3, 0x0000 }, /* R707 - Mic noise mix control 1 */
{ 0x000002CB, 0x0000 }, /* R715 - Isolation control */
{ 0x000002D3, 0x0000 }, /* R723 - Jack detect analogue */
{ 0x00000300, 0x0000 }, /* R768 - Input Enables */
{ 0x00000308, 0x0000 }, /* R776 - Input Rate */
{ 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */
{ 0x0000030C, 0x0002 }, /* R780 - HPF Control */
{ 0x00000310, 0x2080 }, /* R784 - IN1L Control */
{ 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */
{ 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */
{ 0x00000314, 0x0080 }, /* R788 - IN1R Control */
{ 0x00000315, 0x0180 }, /* R789 - ADC Digital Volume 1R */
{ 0x00000316, 0x0000 }, /* R790 - DMIC1R Control */
{ 0x00000318, 0x2080 }, /* R792 - IN2L Control */
{ 0x00000319, 0x0180 }, /* R793 - ADC Digital Volume 2L */
{ 0x0000031A, 0x0000 }, /* R794 - DMIC2L Control */
{ 0x0000031C, 0x0080 }, /* R796 - IN2R Control */
{ 0x0000031D, 0x0180 }, /* R797 - ADC Digital Volume 2R */
{ 0x0000031E, 0x0000 }, /* R798 - DMIC2R Control */
{ 0x00000320, 0x2080 }, /* R800 - IN3L Control */
{ 0x00000321, 0x0180 }, /* R801 - ADC Digital Volume 3L */
{ 0x00000322, 0x0000 }, /* R802 - DMIC3L Control */
{ 0x00000324, 0x0080 }, /* R804 - IN3R Control */
{ 0x00000325, 0x0180 }, /* R805 - ADC Digital Volume 3R */
{ 0x00000326, 0x0000 }, /* R806 - DMIC3R Control */
{ 0x00000328, 0x2000 }, /* R808 - IN4L Control */
{ 0x00000329, 0x0180 }, /* R809 - ADC Digital Volume 4L */
{ 0x0000032A, 0x0000 }, /* R810 - DMIC4L Control */
{ 0x0000032C, 0x0000 }, /* R812 - IN4R Control */
{ 0x0000032D, 0x0180 }, /* R813 - ADC Digital Volume 4R */
{ 0x0000032E, 0x0000 }, /* R814 - DMIC4R Control */
{ 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */
{ 0x00000408, 0x0000 }, /* R1032 - Output Rate 1 */
{ 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */
{ 0x00000410, 0x0080 }, /* R1040 - Output Path Config 1L */
{ 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */
{ 0x00000412, 0x0081 }, /* R1042 - DAC Volume Limit 1L */
{ 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */
{ 0x00000414, 0x0080 }, /* R1044 - Output Path Config 1R */
{ 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */
{ 0x00000416, 0x0081 }, /* R1046 - DAC Volume Limit 1R */
{ 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */
{ 0x00000418, 0x0080 }, /* R1048 - Output Path Config 2L */
{ 0x00000419, 0x0180 }, /* R1049 - DAC Digital Volume 2L */
{ 0x0000041A, 0x0081 }, /* R1050 - DAC Volume Limit 2L */
{ 0x0000041B, 0x0004 }, /* R1051 - Noise Gate Select 2L */
{ 0x0000041C, 0x0080 }, /* R1052 - Output Path Config 2R */
{ 0x0000041D, 0x0180 }, /* R1053 - DAC Digital Volume 2R */
{ 0x0000041E, 0x0081 }, /* R1054 - DAC Volume Limit 2R */
{ 0x0000041F, 0x0008 }, /* R1055 - Noise Gate Select 2R */
{ 0x00000420, 0x0080 }, /* R1056 - Output Path Config 3L */
{ 0x00000421, 0x0180 }, /* R1057 - DAC Digital Volume 3L */
{ 0x00000422, 0x0081 }, /* R1058 - DAC Volume Limit 3L */
{ 0x00000423, 0x0010 }, /* R1059 - Noise Gate Select 3L */
{ 0x00000424, 0x0080 }, /* R1060 - Output Path Config 3R */
{ 0x00000425, 0x0180 }, /* R1061 - DAC Digital Volume 3R */
{ 0x00000426, 0x0081 }, /* R1062 - DAC Volume Limit 3R */
{ 0x00000427, 0x0020 }, /* R1063 - Noise Gate Select 3R */
{ 0x00000428, 0x0000 }, /* R1064 - Output Path Config 4L */
{ 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */
{ 0x0000042A, 0x0081 }, /* R1066 - Out Volume 4L */
{ 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */
{ 0x0000042C, 0x0000 }, /* R1068 - Output Path Config 4R */
{ 0x0000042D, 0x0180 }, /* R1069 - DAC Digital Volume 4R */
{ 0x0000042E, 0x0081 }, /* R1070 - Out Volume 4R */
{ 0x0000042F, 0x0080 }, /* R1071 - Noise Gate Select 4R */
{ 0x00000430, 0x0000 }, /* R1072 - Output Path Config 5L */
{ 0x00000431, 0x0180 }, /* R1073 - DAC Digital Volume 5L */
{ 0x00000432, 0x0081 }, /* R1074 - DAC Volume Limit 5L */
{ 0x00000433, 0x0100 }, /* R1075 - Noise Gate Select 5L */
{ 0x00000434, 0x0000 }, /* R1076 - Output Path Config 5R */
{ 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */
{ 0x00000436, 0x0081 }, /* R1078 - DAC Volume Limit 5R */
{ 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */
{ 0x00000438, 0x0000 }, /* R1080 - Output Path Config 6L */
{ 0x00000439, 0x0180 }, /* R1081 - DAC Digital Volume 6L */
{ 0x0000043A, 0x0081 }, /* R1082 - DAC Volume Limit 6L */
{ 0x0000043B, 0x0400 }, /* R1083 - Noise Gate Select 6L */
{ 0x0000043C, 0x0000 }, /* R1084 - Output Path Config 6R */
{ 0x0000043D, 0x0180 }, /* R1085 - DAC Digital Volume 6R */
{ 0x0000043E, 0x0081 }, /* R1086 - DAC Volume Limit 6R */
{ 0x0000043F, 0x0800 }, /* R1087 - Noise Gate Select 6R */
{ 0x00000440, 0x003F }, /* R1088 - DRE Enable */
{ 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */
{ 0x00000458, 0x0000 }, /* R1112 - Noise Gate Control */
{ 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */
{ 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */
{ 0x00000492, 0x0069 }, /* R1170 - PDM SPK2 CTRL 1 */
{ 0x00000493, 0x0000 }, /* R1171 - PDM SPK2 CTRL 2 */
{ 0x000004A0, 0x3480 }, /* R1184 - HP1 Short Circuit Ctrl */
{ 0x000004A1, 0x3400 }, /* R1185 - HP2 Short Circuit Ctrl */
{ 0x000004A2, 0x3400 }, /* R1186 - HP3 Short Circuit Ctrl */
{ 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */
{ 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */
{ 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */
{ 0x00000503, 0x0000 }, /* R1283 - AIF1 Rate Ctrl */
{ 0x00000504, 0x0000 }, /* R1284 - AIF1 Format */
{ 0x00000505, 0x0040 }, /* R1285 - AIF1 Tx BCLK Rate */
{ 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */
{ 0x00000507, 0x1818 }, /* R1287 - AIF1 Frame Ctrl 1 */
{ 0x00000508, 0x1818 }, /* R1288 - AIF1 Frame Ctrl 2 */
{ 0x00000509, 0x0000 }, /* R1289 - AIF1 Frame Ctrl 3 */
{ 0x0000050A, 0x0001 }, /* R1290 - AIF1 Frame Ctrl 4 */
{ 0x0000050B, 0x0002 }, /* R1291 - AIF1 Frame Ctrl 5 */
{ 0x0000050C, 0x0003 }, /* R1292 - AIF1 Frame Ctrl 6 */
{ 0x0000050D, 0x0004 }, /* R1293 - AIF1 Frame Ctrl 7 */
{ 0x0000050E, 0x0005 }, /* R1294 - AIF1 Frame Ctrl 8 */
{ 0x0000050F, 0x0006 }, /* R1295 - AIF1 Frame Ctrl 9 */
{ 0x00000510, 0x0007 }, /* R1296 - AIF1 Frame Ctrl 10 */
{ 0x00000511, 0x0000 }, /* R1297 - AIF1 Frame Ctrl 11 */
{ 0x00000512, 0x0001 }, /* R1298 - AIF1 Frame Ctrl 12 */
{ 0x00000513, 0x0002 }, /* R1299 - AIF1 Frame Ctrl 13 */
{ 0x00000514, 0x0003 }, /* R1300 - AIF1 Frame Ctrl 14 */
{ 0x00000515, 0x0004 }, /* R1301 - AIF1 Frame Ctrl 15 */
{ 0x00000516, 0x0005 }, /* R1302 - AIF1 Frame Ctrl 16 */
{ 0x00000517, 0x0006 }, /* R1303 - AIF1 Frame Ctrl 17 */
{ 0x00000518, 0x0007 }, /* R1304 - AIF1 Frame Ctrl 18 */
{ 0x00000519, 0x0000 }, /* R1305 - AIF1 Tx Enables */
{ 0x0000051A, 0x0000 }, /* R1306 - AIF1 Rx Enables */
{ 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */
{ 0x00000541, 0x0008 }, /* R1345 - AIF2 Tx Pin Ctrl */
{ 0x00000542, 0x0000 }, /* R1346 - AIF2 Rx Pin Ctrl */
{ 0x00000543, 0x0000 }, /* R1347 - AIF2 Rate Ctrl */
{ 0x00000544, 0x0000 }, /* R1348 - AIF2 Format */
{ 0x00000545, 0x0040 }, /* R1349 - AIF2 Tx BCLK Rate */
{ 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */
{ 0x00000547, 0x1818 }, /* R1351 - AIF2 Frame Ctrl 1 */
{ 0x00000548, 0x1818 }, /* R1352 - AIF2 Frame Ctrl 2 */
{ 0x00000549, 0x0000 }, /* R1353 - AIF2 Frame Ctrl 3 */
{ 0x0000054A, 0x0001 }, /* R1354 - AIF2 Frame Ctrl 4 */
{ 0x0000054B, 0x0002 }, /* R1355 - AIF2 Frame Ctrl 5 */
{ 0x0000054C, 0x0003 }, /* R1356 - AIF2 Frame Ctrl 6 */
{ 0x0000054D, 0x0004 }, /* R1357 - AIF2 Frame Ctrl 7 */
{ 0x0000054E, 0x0005 }, /* R1358 - AIF2 Frame Ctrl 8 */
{ 0x00000551, 0x0000 }, /* R1361 - AIF2 Frame Ctrl 11 */
{ 0x00000552, 0x0001 }, /* R1362 - AIF2 Frame Ctrl 12 */
{ 0x00000553, 0x0002 }, /* R1363 - AIF2 Frame Ctrl 13 */
{ 0x00000554, 0x0003 }, /* R1364 - AIF2 Frame Ctrl 14 */
{ 0x00000555, 0x0004 }, /* R1365 - AIF2 Frame Ctrl 15 */
{ 0x00000556, 0x0005 }, /* R1366 - AIF2 Frame Ctrl 16 */
{ 0x00000559, 0x0000 }, /* R1369 - AIF2 Tx Enables */
{ 0x0000055A, 0x0000 }, /* R1370 - AIF2 Rx Enables */
{ 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */
{ 0x00000581, 0x0008 }, /* R1409 - AIF3 Tx Pin Ctrl */
{ 0x00000582, 0x0000 }, /* R1410 - AIF3 Rx Pin Ctrl */
{ 0x00000583, 0x0000 }, /* R1411 - AIF3 Rate Ctrl */
{ 0x00000584, 0x0000 }, /* R1412 - AIF3 Format */
{ 0x00000585, 0x0040 }, /* R1413 - AIF3 Tx BCLK Rate */
{ 0x00000586, 0x0040 }, /* R1414 - AIF3 Rx BCLK Rate */
{ 0x00000587, 0x1818 }, /* R1415 - AIF3 Frame Ctrl 1 */
{ 0x00000588, 0x1818 }, /* R1416 - AIF3 Frame Ctrl 2 */
{ 0x00000589, 0x0000 }, /* R1417 - AIF3 Frame Ctrl 3 */
{ 0x0000058A, 0x0001 }, /* R1418 - AIF3 Frame Ctrl 4 */
{ 0x00000591, 0x0000 }, /* R1425 - AIF3 Frame Ctrl 11 */
{ 0x00000592, 0x0001 }, /* R1426 - AIF3 Frame Ctrl 12 */
{ 0x00000599, 0x0000 }, /* R1433 - AIF3 Tx Enables */
{ 0x0000059A, 0x0000 }, /* R1434 - AIF3 Rx Enables */
{ 0x000005E3, 0x0004 }, /* R1507 - SLIMbus Framer Ref Gear */
{ 0x000005E5, 0x0000 }, /* R1509 - SLIMbus Rates 1 */
{ 0x000005E6, 0x0000 }, /* R1510 - SLIMbus Rates 2 */
{ 0x000005E7, 0x0000 }, /* R1511 - SLIMbus Rates 3 */
{ 0x000005E8, 0x0000 }, /* R1512 - SLIMbus Rates 4 */
{ 0x000005E9, 0x0000 }, /* R1513 - SLIMbus Rates 5 */
{ 0x000005EA, 0x0000 }, /* R1514 - SLIMbus Rates 6 */
{ 0x000005EB, 0x0000 }, /* R1515 - SLIMbus Rates 7 */
{ 0x000005EC, 0x0000 }, /* R1516 - SLIMbus Rates 8 */
{ 0x000005F5, 0x0000 }, /* R1525 - SLIMbus RX Channel Enable */
{ 0x000005F6, 0x0000 }, /* R1526 - SLIMbus TX Channel Enable */
{ 0x00000640, 0x0000 }, /* R1600 - PWM1MIX Input 1 Source */
{ 0x00000641, 0x0080 }, /* R1601 - PWM1MIX Input 1 Volume */
{ 0x00000642, 0x0000 }, /* R1602 - PWM1MIX Input 2 Source */
{ 0x00000643, 0x0080 }, /* R1603 - PWM1MIX Input 2 Volume */
{ 0x00000644, 0x0000 }, /* R1604 - PWM1MIX Input 3 Source */
{ 0x00000645, 0x0080 }, /* R1605 - PWM1MIX Input 3 Volume */
{ 0x00000646, 0x0000 }, /* R1606 - PWM1MIX Input 4 Source */
{ 0x00000647, 0x0080 }, /* R1607 - PWM1MIX Input 4 Volume */
{ 0x00000648, 0x0000 }, /* R1608 - PWM2MIX Input 1 Source */
{ 0x00000649, 0x0080 }, /* R1609 - PWM2MIX Input 1 Volume */
{ 0x0000064A, 0x0000 }, /* R1610 - PWM2MIX Input 2 Source */
{ 0x0000064B, 0x0080 }, /* R1611 - PWM2MIX Input 2 Volume */
{ 0x0000064C, 0x0000 }, /* R1612 - PWM2MIX Input 3 Source */
{ 0x0000064D, 0x0080 }, /* R1613 - PWM2MIX Input 3 Volume */
{ 0x0000064E, 0x0000 }, /* R1614 - PWM2MIX Input 4 Source */
{ 0x0000064F, 0x0080 }, /* R1615 - PWM2MIX Input 4 Volume */
{ 0x00000660, 0x0000 }, /* R1632 - MICMIX Input 1 Source */
{ 0x00000661, 0x0080 }, /* R1633 - MICMIX Input 1 Volume */
{ 0x00000662, 0x0000 }, /* R1634 - MICMIX Input 2 Source */
{ 0x00000663, 0x0080 }, /* R1635 - MICMIX Input 2 Volume */
{ 0x00000664, 0x0000 }, /* R1636 - MICMIX Input 3 Source */
{ 0x00000665, 0x0080 }, /* R1637 - MICMIX Input 3 Volume */
{ 0x00000666, 0x0000 }, /* R1638 - MICMIX Input 4 Source */
{ 0x00000667, 0x0080 }, /* R1639 - MICMIX Input 4 Volume */
{ 0x00000668, 0x0000 }, /* R1640 - NOISEMIX Input 1 Source */
{ 0x00000669, 0x0080 }, /* R1641 - NOISEMIX Input 1 Volume */
{ 0x0000066A, 0x0000 }, /* R1642 - NOISEMIX Input 2 Source */
{ 0x0000066B, 0x0080 }, /* R1643 - NOISEMIX Input 2 Volume */
{ 0x0000066C, 0x0000 }, /* R1644 - NOISEMIX Input 3 Source */
{ 0x0000066D, 0x0080 }, /* R1645 - NOISEMIX Input 3 Volume */
{ 0x0000066E, 0x0000 }, /* R1646 - NOISEMIX Input 4 Source */
{ 0x0000066F, 0x0080 }, /* R1647 - NOISEMIX Input 4 Volume */
{ 0x00000680, 0x0000 }, /* R1664 - OUT1LMIX Input 1 Source */
{ 0x00000681, 0x0080 }, /* R1665 - OUT1LMIX Input 1 Volume */
{ 0x00000682, 0x0000 }, /* R1666 - OUT1LMIX Input 2 Source */
{ 0x00000683, 0x0080 }, /* R1667 - OUT1LMIX Input 2 Volume */
{ 0x00000684, 0x0000 }, /* R1668 - OUT1LMIX Input 3 Source */
{ 0x00000685, 0x0080 }, /* R1669 - OUT1LMIX Input 3 Volume */
{ 0x00000686, 0x0000 }, /* R1670 - OUT1LMIX Input 4 Source */
{ 0x00000687, 0x0080 }, /* R1671 - OUT1LMIX Input 4 Volume */
{ 0x00000688, 0x0000 }, /* R1672 - OUT1RMIX Input 1 Source */
{ 0x00000689, 0x0080 }, /* R1673 - OUT1RMIX Input 1 Volume */
{ 0x0000068A, 0x0000 }, /* R1674 - OUT1RMIX Input 2 Source */
{ 0x0000068B, 0x0080 }, /* R1675 - OUT1RMIX Input 2 Volume */
{ 0x0000068C, 0x0000 }, /* R1676 - OUT1RMIX Input 3 Source */
{ 0x0000068D, 0x0080 }, /* R1677 - OUT1RMIX Input 3 Volume */
{ 0x0000068E, 0x0000 }, /* R1678 - OUT1RMIX Input 4 Source */
{ 0x0000068F, 0x0080 }, /* R1679 - OUT1RMIX Input 4 Volume */
{ 0x00000690, 0x0000 }, /* R1680 - OUT2LMIX Input 1 Source */
{ 0x00000691, 0x0080 }, /* R1681 - OUT2LMIX Input 1 Volume */
{ 0x00000692, 0x0000 }, /* R1682 - OUT2LMIX Input 2 Source */
{ 0x00000693, 0x0080 }, /* R1683 - OUT2LMIX Input 2 Volume */
{ 0x00000694, 0x0000 }, /* R1684 - OUT2LMIX Input 3 Source */
{ 0x00000695, 0x0080 }, /* R1685 - OUT2LMIX Input 3 Volume */
{ 0x00000696, 0x0000 }, /* R1686 - OUT2LMIX Input 4 Source */
{ 0x00000697, 0x0080 }, /* R1687 - OUT2LMIX Input 4 Volume */
{ 0x00000698, 0x0000 }, /* R1688 - OUT2RMIX Input 1 Source */
{ 0x00000699, 0x0080 }, /* R1689 - OUT2RMIX Input 1 Volume */
{ 0x0000069A, 0x0000 }, /* R1690 - OUT2RMIX Input 2 Source */
{ 0x0000069B, 0x0080 }, /* R1691 - OUT2RMIX Input 2 Volume */
{ 0x0000069C, 0x0000 }, /* R1692 - OUT2RMIX Input 3 Source */
{ 0x0000069D, 0x0080 }, /* R1693 - OUT2RMIX Input 3 Volume */
{ 0x0000069E, 0x0000 }, /* R1694 - OUT2RMIX Input 4 Source */
{ 0x0000069F, 0x0080 }, /* R1695 - OUT2RMIX Input 4 Volume */
{ 0x000006A0, 0x0000 }, /* R1696 - OUT3LMIX Input 1 Source */
{ 0x000006A1, 0x0080 }, /* R1697 - OUT3LMIX Input 1 Volume */
{ 0x000006A2, 0x0000 }, /* R1698 - OUT3LMIX Input 2 Source */
{ 0x000006A3, 0x0080 }, /* R1699 - OUT3LMIX Input 2 Volume */
{ 0x000006A4, 0x0000 }, /* R1700 - OUT3LMIX Input 3 Source */
{ 0x000006A5, 0x0080 }, /* R1701 - OUT3LMIX Input 3 Volume */
{ 0x000006A6, 0x0000 }, /* R1702 - OUT3LMIX Input 4 Source */
{ 0x000006A7, 0x0080 }, /* R1703 - OUT3LMIX Input 4 Volume */
{ 0x000006A8, 0x0000 }, /* R1704 - OUT3RMIX Input 1 Source */
{ 0x000006A9, 0x0080 }, /* R1705 - OUT3RMIX Input 1 Volume */
{ 0x000006AA, 0x0000 }, /* R1706 - OUT3RMIX Input 2 Source */
{ 0x000006AB, 0x0080 }, /* R1707 - OUT3RMIX Input 2 Volume */
{ 0x000006AC, 0x0000 }, /* R1708 - OUT3RMIX Input 3 Source */
{ 0x000006AD, 0x0080 }, /* R1709 - OUT3RMIX Input 3 Volume */
{ 0x000006AE, 0x0000 }, /* R1710 - OUT3RMIX Input 4 Source */
{ 0x000006AF, 0x0080 }, /* R1711 - OUT3RMIX Input 4 Volume */
{ 0x000006B0, 0x0000 }, /* R1712 - OUT4LMIX Input 1 Source */
{ 0x000006B1, 0x0080 }, /* R1713 - OUT4LMIX Input 1 Volume */
{ 0x000006B2, 0x0000 }, /* R1714 - OUT4LMIX Input 2 Source */
{ 0x000006B3, 0x0080 }, /* R1715 - OUT4LMIX Input 2 Volume */
{ 0x000006B4, 0x0000 }, /* R1716 - OUT4LMIX Input 3 Source */
{ 0x000006B5, 0x0080 }, /* R1717 - OUT4LMIX Input 3 Volume */
{ 0x000006B6, 0x0000 }, /* R1718 - OUT4LMIX Input 4 Source */
{ 0x000006B7, 0x0080 }, /* R1719 - OUT4LMIX Input 4 Volume */
{ 0x000006B8, 0x0000 }, /* R1720 - OUT4RMIX Input 1 Source */
{ 0x000006B9, 0x0080 }, /* R1721 - OUT4RMIX Input 1 Volume */
{ 0x000006BA, 0x0000 }, /* R1722 - OUT4RMIX Input 2 Source */
{ 0x000006BB, 0x0080 }, /* R1723 - OUT4RMIX Input 2 Volume */
{ 0x000006BC, 0x0000 }, /* R1724 - OUT4RMIX Input 3 Source */
{ 0x000006BD, 0x0080 }, /* R1725 - OUT4RMIX Input 3 Volume */
{ 0x000006BE, 0x0000 }, /* R1726 - OUT4RMIX Input 4 Source */
{ 0x000006BF, 0x0080 }, /* R1727 - OUT4RMIX Input 4 Volume */
{ 0x000006C0, 0x0000 }, /* R1728 - OUT5LMIX Input 1 Source */
{ 0x000006C1, 0x0080 }, /* R1729 - OUT5LMIX Input 1 Volume */
{ 0x000006C2, 0x0000 }, /* R1730 - OUT5LMIX Input 2 Source */
{ 0x000006C3, 0x0080 }, /* R1731 - OUT5LMIX Input 2 Volume */
{ 0x000006C4, 0x0000 }, /* R1732 - OUT5LMIX Input 3 Source */
{ 0x000006C5, 0x0080 }, /* R1733 - OUT5LMIX Input 3 Volume */
{ 0x000006C6, 0x0000 }, /* R1734 - OUT5LMIX Input 4 Source */
{ 0x000006C7, 0x0080 }, /* R1735 - OUT5LMIX Input 4 Volume */
{ 0x000006C8, 0x0000 }, /* R1736 - OUT5RMIX Input 1 Source */
{ 0x000006C9, 0x0080 }, /* R1737 - OUT5RMIX Input 1 Volume */
{ 0x000006CA, 0x0000 }, /* R1738 - OUT5RMIX Input 2 Source */
{ 0x000006CB, 0x0080 }, /* R1739 - OUT5RMIX Input 2 Volume */
{ 0x000006CC, 0x0000 }, /* R1740 - OUT5RMIX Input 3 Source */
{ 0x000006CD, 0x0080 }, /* R1741 - OUT5RMIX Input 3 Volume */
{ 0x000006CE, 0x0000 }, /* R1742 - OUT5RMIX Input 4 Source */
{ 0x000006CF, 0x0080 }, /* R1743 - OUT5RMIX Input 4 Volume */
{ 0x000006D0, 0x0000 }, /* R1744 - OUT6LMIX Input 1 Source */
{ 0x000006D1, 0x0080 }, /* R1745 - OUT6LMIX Input 1 Volume */
{ 0x000006D2, 0x0000 }, /* R1746 - OUT6LMIX Input 2 Source */
{ 0x000006D3, 0x0080 }, /* R1747 - OUT6LMIX Input 2 Volume */
{ 0x000006D4, 0x0000 }, /* R1748 - OUT6LMIX Input 3 Source */
{ 0x000006D5, 0x0080 }, /* R1749 - OUT6LMIX Input 3 Volume */
{ 0x000006D6, 0x0000 }, /* R1750 - OUT6LMIX Input 4 Source */
{ 0x000006D7, 0x0080 }, /* R1751 - OUT6LMIX Input 4 Volume */
{ 0x000006D8, 0x0000 }, /* R1752 - OUT6RMIX Input 1 Source */
{ 0x000006D9, 0x0080 }, /* R1753 - OUT6RMIX Input 1 Volume */
{ 0x000006DA, 0x0000 }, /* R1754 - OUT6RMIX Input 2 Source */
{ 0x000006DB, 0x0080 }, /* R1755 - OUT6RMIX Input 2 Volume */
{ 0x000006DC, 0x0000 }, /* R1756 - OUT6RMIX Input 3 Source */
{ 0x000006DD, 0x0080 }, /* R1757 - OUT6RMIX Input 3 Volume */
{ 0x000006DE, 0x0000 }, /* R1758 - OUT6RMIX Input 4 Source */
{ 0x000006DF, 0x0080 }, /* R1759 - OUT6RMIX Input 4 Volume */
{ 0x00000700, 0x0000 }, /* R1792 - AIF1TX1MIX Input 1 Source */
{ 0x00000701, 0x0080 }, /* R1793 - AIF1TX1MIX Input 1 Volume */
{ 0x00000702, 0x0000 }, /* R1794 - AIF1TX1MIX Input 2 Source */
{ 0x00000703, 0x0080 }, /* R1795 - AIF1TX1MIX Input 2 Volume */
{ 0x00000704, 0x0000 }, /* R1796 - AIF1TX1MIX Input 3 Source */
{ 0x00000705, 0x0080 }, /* R1797 - AIF1TX1MIX Input 3 Volume */
{ 0x00000706, 0x0000 }, /* R1798 - AIF1TX1MIX Input 4 Source */
{ 0x00000707, 0x0080 }, /* R1799 - AIF1TX1MIX Input 4 Volume */
{ 0x00000708, 0x0000 }, /* R1800 - AIF1TX2MIX Input 1 Source */
{ 0x00000709, 0x0080 }, /* R1801 - AIF1TX2MIX Input 1 Volume */
{ 0x0000070A, 0x0000 }, /* R1802 - AIF1TX2MIX Input 2 Source */
{ 0x0000070B, 0x0080 }, /* R1803 - AIF1TX2MIX Input 2 Volume */
{ 0x0000070C, 0x0000 }, /* R1804 - AIF1TX2MIX Input 3 Source */
{ 0x0000070D, 0x0080 }, /* R1805 - AIF1TX2MIX Input 3 Volume */
{ 0x0000070E, 0x0000 }, /* R1806 - AIF1TX2MIX Input 4 Source */
{ 0x0000070F, 0x0080 }, /* R1807 - AIF1TX2MIX Input 4 Volume */
{ 0x00000710, 0x0000 }, /* R1808 - AIF1TX3MIX Input 1 Source */
{ 0x00000711, 0x0080 }, /* R1809 - AIF1TX3MIX Input 1 Volume */
{ 0x00000712, 0x0000 }, /* R1810 - AIF1TX3MIX Input 2 Source */
{ 0x00000713, 0x0080 }, /* R1811 - AIF1TX3MIX Input 2 Volume */
{ 0x00000714, 0x0000 }, /* R1812 - AIF1TX3MIX Input 3 Source */
{ 0x00000715, 0x0080 }, /* R1813 - AIF1TX3MIX Input 3 Volume */
{ 0x00000716, 0x0000 }, /* R1814 - AIF1TX3MIX Input 4 Source */
{ 0x00000717, 0x0080 }, /* R1815 - AIF1TX3MIX Input 4 Volume */
{ 0x00000718, 0x0000 }, /* R1816 - AIF1TX4MIX Input 1 Source */
{ 0x00000719, 0x0080 }, /* R1817 - AIF1TX4MIX Input 1 Volume */
{ 0x0000071A, 0x0000 }, /* R1818 - AIF1TX4MIX Input 2 Source */
{ 0x0000071B, 0x0080 }, /* R1819 - AIF1TX4MIX Input 2 Volume */
{ 0x0000071C, 0x0000 }, /* R1820 - AIF1TX4MIX Input 3 Source */
{ 0x0000071D, 0x0080 }, /* R1821 - AIF1TX4MIX Input 3 Volume */
{ 0x0000071E, 0x0000 }, /* R1822 - AIF1TX4MIX Input 4 Source */
{ 0x0000071F, 0x0080 }, /* R1823 - AIF1TX4MIX Input 4 Volume */
{ 0x00000720, 0x0000 }, /* R1824 - AIF1TX5MIX Input 1 Source */
{ 0x00000721, 0x0080 }, /* R1825 - AIF1TX5MIX Input 1 Volume */
{ 0x00000722, 0x0000 }, /* R1826 - AIF1TX5MIX Input 2 Source */
{ 0x00000723, 0x0080 }, /* R1827 - AIF1TX5MIX Input 2 Volume */
{ 0x00000724, 0x0000 }, /* R1828 - AIF1TX5MIX Input 3 Source */
{ 0x00000725, 0x0080 }, /* R1829 - AIF1TX5MIX Input 3 Volume */
{ 0x00000726, 0x0000 }, /* R1830 - AIF1TX5MIX Input 4 Source */
{ 0x00000727, 0x0080 }, /* R1831 - AIF1TX5MIX Input 4 Volume */
{ 0x00000728, 0x0000 }, /* R1832 - AIF1TX6MIX Input 1 Source */
{ 0x00000729, 0x0080 }, /* R1833 - AIF1TX6MIX Input 1 Volume */
{ 0x0000072A, 0x0000 }, /* R1834 - AIF1TX6MIX Input 2 Source */
{ 0x0000072B, 0x0080 }, /* R1835 - AIF1TX6MIX Input 2 Volume */
{ 0x0000072C, 0x0000 }, /* R1836 - AIF1TX6MIX Input 3 Source */
{ 0x0000072D, 0x0080 }, /* R1837 - AIF1TX6MIX Input 3 Volume */
{ 0x0000072E, 0x0000 }, /* R1838 - AIF1TX6MIX Input 4 Source */
{ 0x0000072F, 0x0080 }, /* R1839 - AIF1TX6MIX Input 4 Volume */
{ 0x00000730, 0x0000 }, /* R1840 - AIF1TX7MIX Input 1 Source */
{ 0x00000731, 0x0080 }, /* R1841 - AIF1TX7MIX Input 1 Volume */
{ 0x00000732, 0x0000 }, /* R1842 - AIF1TX7MIX Input 2 Source */
{ 0x00000733, 0x0080 }, /* R1843 - AIF1TX7MIX Input 2 Volume */
{ 0x00000734, 0x0000 }, /* R1844 - AIF1TX7MIX Input 3 Source */
{ 0x00000735, 0x0080 }, /* R1845 - AIF1TX7MIX Input 3 Volume */
{ 0x00000736, 0x0000 }, /* R1846 - AIF1TX7MIX Input 4 Source */
{ 0x00000737, 0x0080 }, /* R1847 - AIF1TX7MIX Input 4 Volume */
{ 0x00000738, 0x0000 }, /* R1848 - AIF1TX8MIX Input 1 Source */
{ 0x00000739, 0x0080 }, /* R1849 - AIF1TX8MIX Input 1 Volume */
{ 0x0000073A, 0x0000 }, /* R1850 - AIF1TX8MIX Input 2 Source */
{ 0x0000073B, 0x0080 }, /* R1851 - AIF1TX8MIX Input 2 Volume */
{ 0x0000073C, 0x0000 }, /* R1852 - AIF1TX8MIX Input 3 Source */
{ 0x0000073D, 0x0080 }, /* R1853 - AIF1TX8MIX Input 3 Volume */
{ 0x0000073E, 0x0000 }, /* R1854 - AIF1TX8MIX Input 4 Source */
{ 0x0000073F, 0x0080 }, /* R1855 - AIF1TX8MIX Input 4 Volume */
{ 0x00000740, 0x0000 }, /* R1856 - AIF2TX1MIX Input 1 Source */
{ 0x00000741, 0x0080 }, /* R1857 - AIF2TX1MIX Input 1 Volume */
{ 0x00000742, 0x0000 }, /* R1858 - AIF2TX1MIX Input 2 Source */
{ 0x00000743, 0x0080 }, /* R1859 - AIF2TX1MIX Input 2 Volume */
{ 0x00000744, 0x0000 }, /* R1860 - AIF2TX1MIX Input 3 Source */
{ 0x00000745, 0x0080 }, /* R1861 - AIF2TX1MIX Input 3 Volume */
{ 0x00000746, 0x0000 }, /* R1862 - AIF2TX1MIX Input 4 Source */
{ 0x00000747, 0x0080 }, /* R1863 - AIF2TX1MIX Input 4 Volume */
{ 0x00000748, 0x0000 }, /* R1864 - AIF2TX2MIX Input 1 Source */
{ 0x00000749, 0x0080 }, /* R1865 - AIF2TX2MIX Input 1 Volume */
{ 0x0000074A, 0x0000 }, /* R1866 - AIF2TX2MIX Input 2 Source */
{ 0x0000074B, 0x0080 }, /* R1867 - AIF2TX2MIX Input 2 Volume */
{ 0x0000074C, 0x0000 }, /* R1868 - AIF2TX2MIX Input 3 Source */
{ 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */
{ 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */
{ 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */
{ 0x00000750, 0x0000 }, /* R1872 - AIF2TX3MIX Input 1 Source */
{ 0x00000751, 0x0080 }, /* R1873 - AIF2TX3MIX Input 1 Volume */
{ 0x00000752, 0x0000 }, /* R1874 - AIF2TX3MIX Input 2 Source */
{ 0x00000753, 0x0080 }, /* R1875 - AIF2TX3MIX Input 2 Volume */
{ 0x00000754, 0x0000 }, /* R1876 - AIF2TX3MIX Input 3 Source */
{ 0x00000755, 0x0080 }, /* R1877 - AIF2TX3MIX Input 3 Volume */
{ 0x00000756, 0x0000 }, /* R1878 - AIF2TX3MIX Input 4 Source */
{ 0x00000757, 0x0080 }, /* R1879 - AIF2TX3MIX Input 4 Volume */
{ 0x00000758, 0x0000 }, /* R1880 - AIF2TX4MIX Input 1 Source */
{ 0x00000759, 0x0080 }, /* R1881 - AIF2TX4MIX Input 1 Volume */
{ 0x0000075A, 0x0000 }, /* R1882 - AIF2TX4MIX Input 2 Source */
{ 0x0000075B, 0x0080 }, /* R1883 - AIF2TX4MIX Input 2 Volume */
{ 0x0000075C, 0x0000 }, /* R1884 - AIF2TX4MIX Input 3 Source */
{ 0x0000075D, 0x0080 }, /* R1885 - AIF2TX4MIX Input 3 Volume */
{ 0x0000075E, 0x0000 }, /* R1886 - AIF2TX4MIX Input 4 Source */
{ 0x0000075F, 0x0080 }, /* R1887 - AIF2TX4MIX Input 4 Volume */
{ 0x00000760, 0x0000 }, /* R1888 - AIF2TX5MIX Input 1 Source */
{ 0x00000761, 0x0080 }, /* R1889 - AIF2TX5MIX Input 1 Volume */
{ 0x00000762, 0x0000 }, /* R1890 - AIF2TX5MIX Input 2 Source */
{ 0x00000763, 0x0080 }, /* R1891 - AIF2TX5MIX Input 2 Volume */
{ 0x00000764, 0x0000 }, /* R1892 - AIF2TX5MIX Input 3 Source */
{ 0x00000765, 0x0080 }, /* R1893 - AIF2TX5MIX Input 3 Volume */
{ 0x00000766, 0x0000 }, /* R1894 - AIF2TX5MIX Input 4 Source */
{ 0x00000767, 0x0080 }, /* R1895 - AIF2TX5MIX Input 4 Volume */
{ 0x00000768, 0x0000 }, /* R1896 - AIF2TX6MIX Input 1 Source */
{ 0x00000769, 0x0080 }, /* R1897 - AIF2TX6MIX Input 1 Volume */
{ 0x0000076A, 0x0000 }, /* R1898 - AIF2TX6MIX Input 2 Source */
{ 0x0000076B, 0x0080 }, /* R1899 - AIF2TX6MIX Input 2 Volume */
{ 0x0000076C, 0x0000 }, /* R1900 - AIF2TX6MIX Input 3 Source */
{ 0x0000076D, 0x0080 }, /* R1901 - AIF2TX6MIX Input 3 Volume */
{ 0x0000076E, 0x0000 }, /* R1902 - AIF2TX6MIX Input 4 Source */
{ 0x0000076F, 0x0080 }, /* R1903 - AIF2TX6MIX Input 4 Volume */
{ 0x00000780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */
{ 0x00000781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */
{ 0x00000782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */
{ 0x00000783, 0x0080 }, /* R1923 - AIF3TX1MIX Input 2 Volume */
{ 0x00000784, 0x0000 }, /* R1924 - AIF3TX1MIX Input 3 Source */
{ 0x00000785, 0x0080 }, /* R1925 - AIF3TX1MIX Input 3 Volume */
{ 0x00000786, 0x0000 }, /* R1926 - AIF3TX1MIX Input 4 Source */
{ 0x00000787, 0x0080 }, /* R1927 - AIF3TX1MIX Input 4 Volume */
{ 0x00000788, 0x0000 }, /* R1928 - AIF3TX2MIX Input 1 Source */
{ 0x00000789, 0x0080 }, /* R1929 - AIF3TX2MIX Input 1 Volume */
{ 0x0000078A, 0x0000 }, /* R1930 - AIF3TX2MIX Input 2 Source */
{ 0x0000078B, 0x0080 }, /* R1931 - AIF3TX2MIX Input 2 Volume */
{ 0x0000078C, 0x0000 }, /* R1932 - AIF3TX2MIX Input 3 Source */
{ 0x0000078D, 0x0080 }, /* R1933 - AIF3TX2MIX Input 3 Volume */
{ 0x0000078E, 0x0000 }, /* R1934 - AIF3TX2MIX Input 4 Source */
{ 0x0000078F, 0x0080 }, /* R1935 - AIF3TX2MIX Input 4 Volume */
{ 0x000007C0, 0x0000 }, /* R1984 - SLIMTX1MIX Input 1 Source */
{ 0x000007C1, 0x0080 }, /* R1985 - SLIMTX1MIX Input 1 Volume */
{ 0x000007C2, 0x0000 }, /* R1986 - SLIMTX1MIX Input 2 Source */
{ 0x000007C3, 0x0080 }, /* R1987 - SLIMTX1MIX Input 2 Volume */
{ 0x000007C4, 0x0000 }, /* R1988 - SLIMTX1MIX Input 3 Source */
{ 0x000007C5, 0x0080 }, /* R1989 - SLIMTX1MIX Input 3 Volume */
{ 0x000007C6, 0x0000 }, /* R1990 - SLIMTX1MIX Input 4 Source */
{ 0x000007C7, 0x0080 }, /* R1991 - SLIMTX1MIX Input 4 Volume */
{ 0x000007C8, 0x0000 }, /* R1992 - SLIMTX2MIX Input 1 Source */
{ 0x000007C9, 0x0080 }, /* R1993 - SLIMTX2MIX Input 1 Volume */
{ 0x000007CA, 0x0000 }, /* R1994 - SLIMTX2MIX Input 2 Source */
{ 0x000007CB, 0x0080 }, /* R1995 - SLIMTX2MIX Input 2 Volume */
{ 0x000007CC, 0x0000 }, /* R1996 - SLIMTX2MIX Input 3 Source */
{ 0x000007CD, 0x0080 }, /* R1997 - SLIMTX2MIX Input 3 Volume */
{ 0x000007CE, 0x0000 }, /* R1998 - SLIMTX2MIX Input 4 Source */
{ 0x000007CF, 0x0080 }, /* R1999 - SLIMTX2MIX Input 4 Volume */
{ 0x000007D0, 0x0000 }, /* R2000 - SLIMTX3MIX Input 1 Source */
{ 0x000007D1, 0x0080 }, /* R2001 - SLIMTX3MIX Input 1 Volume */
{ 0x000007D2, 0x0000 }, /* R2002 - SLIMTX3MIX Input 2 Source */
{ 0x000007D3, 0x0080 }, /* R2003 - SLIMTX3MIX Input 2 Volume */
{ 0x000007D4, 0x0000 }, /* R2004 - SLIMTX3MIX Input 3 Source */
{ 0x000007D5, 0x0080 }, /* R2005 - SLIMTX3MIX Input 3 Volume */
{ 0x000007D6, 0x0000 }, /* R2006 - SLIMTX3MIX Input 4 Source */
{ 0x000007D7, 0x0080 }, /* R2007 - SLIMTX3MIX Input 4 Volume */
{ 0x000007D8, 0x0000 }, /* R2008 - SLIMTX4MIX Input 1 Source */
{ 0x000007D9, 0x0080 }, /* R2009 - SLIMTX4MIX Input 1 Volume */
{ 0x000007DA, 0x0000 }, /* R2010 - SLIMTX4MIX Input 2 Source */
{ 0x000007DB, 0x0080 }, /* R2011 - SLIMTX4MIX Input 2 Volume */
{ 0x000007DC, 0x0000 }, /* R2012 - SLIMTX4MIX Input 3 Source */
{ 0x000007DD, 0x0080 }, /* R2013 - SLIMTX4MIX Input 3 Volume */
{ 0x000007DE, 0x0000 }, /* R2014 - SLIMTX4MIX Input 4 Source */
{ 0x000007DF, 0x0080 }, /* R2015 - SLIMTX4MIX Input 4 Volume */
{ 0x000007E0, 0x0000 }, /* R2016 - SLIMTX5MIX Input 1 Source */
{ 0x000007E1, 0x0080 }, /* R2017 - SLIMTX5MIX Input 1 Volume */
{ 0x000007E2, 0x0000 }, /* R2018 - SLIMTX5MIX Input 2 Source */
{ 0x000007E3, 0x0080 }, /* R2019 - SLIMTX5MIX Input 2 Volume */
{ 0x000007E4, 0x0000 }, /* R2020 - SLIMTX5MIX Input 3 Source */
{ 0x000007E5, 0x0080 }, /* R2021 - SLIMTX5MIX Input 3 Volume */
{ 0x000007E6, 0x0000 }, /* R2022 - SLIMTX5MIX Input 4 Source */
{ 0x000007E7, 0x0080 }, /* R2023 - SLIMTX5MIX Input 4 Volume */
{ 0x000007E8, 0x0000 }, /* R2024 - SLIMTX6MIX Input 1 Source */
{ 0x000007E9, 0x0080 }, /* R2025 - SLIMTX6MIX Input 1 Volume */
{ 0x000007EA, 0x0000 }, /* R2026 - SLIMTX6MIX Input 2 Source */
{ 0x000007EB, 0x0080 }, /* R2027 - SLIMTX6MIX Input 2 Volume */
{ 0x000007EC, 0x0000 }, /* R2028 - SLIMTX6MIX Input 3 Source */
{ 0x000007ED, 0x0080 }, /* R2029 - SLIMTX6MIX Input 3 Volume */
{ 0x000007EE, 0x0000 }, /* R2030 - SLIMTX6MIX Input 4 Source */
{ 0x000007EF, 0x0080 }, /* R2031 - SLIMTX6MIX Input 4 Volume */
{ 0x000007F0, 0x0000 }, /* R2032 - SLIMTX7MIX Input 1 Source */
{ 0x000007F1, 0x0080 }, /* R2033 - SLIMTX7MIX Input 1 Volume */
{ 0x000007F2, 0x0000 }, /* R2034 - SLIMTX7MIX Input 2 Source */
{ 0x000007F3, 0x0080 }, /* R2035 - SLIMTX7MIX Input 2 Volume */
{ 0x000007F4, 0x0000 }, /* R2036 - SLIMTX7MIX Input 3 Source */
{ 0x000007F5, 0x0080 }, /* R2037 - SLIMTX7MIX Input 3 Volume */
{ 0x000007F6, 0x0000 }, /* R2038 - SLIMTX7MIX Input 4 Source */
{ 0x000007F7, 0x0080 }, /* R2039 - SLIMTX7MIX Input 4 Volume */
{ 0x000007F8, 0x0000 }, /* R2040 - SLIMTX8MIX Input 1 Source */
{ 0x000007F9, 0x0080 }, /* R2041 - SLIMTX8MIX Input 1 Volume */
{ 0x000007FA, 0x0000 }, /* R2042 - SLIMTX8MIX Input 2 Source */
{ 0x000007FB, 0x0080 }, /* R2043 - SLIMTX8MIX Input 2 Volume */
{ 0x000007FC, 0x0000 }, /* R2044 - SLIMTX8MIX Input 3 Source */
{ 0x000007FD, 0x0080 }, /* R2045 - SLIMTX8MIX Input 3 Volume */
{ 0x000007FE, 0x0000 }, /* R2046 - SLIMTX8MIX Input 4 Source */
{ 0x000007FF, 0x0080 }, /* R2047 - SLIMTX8MIX Input 4 Volume */
{ 0x00000880, 0x0000 }, /* R2176 - EQ1MIX Input 1 Source */
{ 0x00000881, 0x0080 }, /* R2177 - EQ1MIX Input 1 Volume */
{ 0x00000882, 0x0000 }, /* R2178 - EQ1MIX Input 2 Source */
{ 0x00000883, 0x0080 }, /* R2179 - EQ1MIX Input 2 Volume */
{ 0x00000884, 0x0000 }, /* R2180 - EQ1MIX Input 3 Source */
{ 0x00000885, 0x0080 }, /* R2181 - EQ1MIX Input 3 Volume */
{ 0x00000886, 0x0000 }, /* R2182 - EQ1MIX Input 4 Source */
{ 0x00000887, 0x0080 }, /* R2183 - EQ1MIX Input 4 Volume */
{ 0x00000888, 0x0000 }, /* R2184 - EQ2MIX Input 1 Source */
{ 0x00000889, 0x0080 }, /* R2185 - EQ2MIX Input 1 Volume */
{ 0x0000088A, 0x0000 }, /* R2186 - EQ2MIX Input 2 Source */
{ 0x0000088B, 0x0080 }, /* R2187 - EQ2MIX Input 2 Volume */
{ 0x0000088C, 0x0000 }, /* R2188 - EQ2MIX Input 3 Source */
{ 0x0000088D, 0x0080 }, /* R2189 - EQ2MIX Input 3 Volume */
{ 0x0000088E, 0x0000 }, /* R2190 - EQ2MIX Input 4 Source */
{ 0x0000088F, 0x0080 }, /* R2191 - EQ2MIX Input 4 Volume */
{ 0x00000890, 0x0000 }, /* R2192 - EQ3MIX Input 1 Source */
{ 0x00000891, 0x0080 }, /* R2193 - EQ3MIX Input 1 Volume */
{ 0x00000892, 0x0000 }, /* R2194 - EQ3MIX Input 2 Source */
{ 0x00000893, 0x0080 }, /* R2195 - EQ3MIX Input 2 Volume */
{ 0x00000894, 0x0000 }, /* R2196 - EQ3MIX Input 3 Source */
{ 0x00000895, 0x0080 }, /* R2197 - EQ3MIX Input 3 Volume */
{ 0x00000896, 0x0000 }, /* R2198 - EQ3MIX Input 4 Source */
{ 0x00000897, 0x0080 }, /* R2199 - EQ3MIX Input 4 Volume */
{ 0x00000898, 0x0000 }, /* R2200 - EQ4MIX Input 1 Source */
{ 0x00000899, 0x0080 }, /* R2201 - EQ4MIX Input 1 Volume */
{ 0x0000089A, 0x0000 }, /* R2202 - EQ4MIX Input 2 Source */
{ 0x0000089B, 0x0080 }, /* R2203 - EQ4MIX Input 2 Volume */
{ 0x0000089C, 0x0000 }, /* R2204 - EQ4MIX Input 3 Source */
{ 0x0000089D, 0x0080 }, /* R2205 - EQ4MIX Input 3 Volume */
{ 0x0000089E, 0x0000 }, /* R2206 - EQ4MIX Input 4 Source */
{ 0x0000089F, 0x0080 }, /* R2207 - EQ4MIX Input 4 Volume */
{ 0x000008C0, 0x0000 }, /* R2240 - DRC1LMIX Input 1 Source */
{ 0x000008C1, 0x0080 }, /* R2241 - DRC1LMIX Input 1 Volume */
{ 0x000008C2, 0x0000 }, /* R2242 - DRC1LMIX Input 2 Source */
{ 0x000008C3, 0x0080 }, /* R2243 - DRC1LMIX Input 2 Volume */
{ 0x000008C4, 0x0000 }, /* R2244 - DRC1LMIX Input 3 Source */
{ 0x000008C5, 0x0080 }, /* R2245 - DRC1LMIX Input 3 Volume */
{ 0x000008C6, 0x0000 }, /* R2246 - DRC1LMIX Input 4 Source */
{ 0x000008C7, 0x0080 }, /* R2247 - DRC1LMIX Input 4 Volume */
{ 0x000008C8, 0x0000 }, /* R2248 - DRC1RMIX Input 1 Source */
{ 0x000008C9, 0x0080 }, /* R2249 - DRC1RMIX Input 1 Volume */
{ 0x000008CA, 0x0000 }, /* R2250 - DRC1RMIX Input 2 Source */
{ 0x000008CB, 0x0080 }, /* R2251 - DRC1RMIX Input 2 Volume */
{ 0x000008CC, 0x0000 }, /* R2252 - DRC1RMIX Input 3 Source */
{ 0x000008CD, 0x0080 }, /* R2253 - DRC1RMIX Input 3 Volume */
{ 0x000008CE, 0x0000 }, /* R2254 - DRC1RMIX Input 4 Source */
{ 0x000008CF, 0x0080 }, /* R2255 - DRC1RMIX Input 4 Volume */
{ 0x000008D0, 0x0000 }, /* R2256 - DRC2LMIX Input 1 Source */
{ 0x000008D1, 0x0080 }, /* R2257 - DRC2LMIX Input 1 Volume */
{ 0x000008D2, 0x0000 }, /* R2258 - DRC2LMIX Input 2 Source */
{ 0x000008D3, 0x0080 }, /* R2259 - DRC2LMIX Input 2 Volume */
{ 0x000008D4, 0x0000 }, /* R2260 - DRC2LMIX Input 3 Source */
{ 0x000008D5, 0x0080 }, /* R2261 - DRC2LMIX Input 3 Volume */
{ 0x000008D6, 0x0000 }, /* R2262 - DRC2LMIX Input 4 Source */
{ 0x000008D7, 0x0080 }, /* R2263 - DRC2LMIX Input 4 Volume */
{ 0x000008D8, 0x0000 }, /* R2264 - DRC2RMIX Input 1 Source */
{ 0x000008D9, 0x0080 }, /* R2265 - DRC2RMIX Input 1 Volume */
{ 0x000008DA, 0x0000 }, /* R2266 - DRC2RMIX Input 2 Source */
{ 0x000008DB, 0x0080 }, /* R2267 - DRC2RMIX Input 2 Volume */
{ 0x000008DC, 0x0000 }, /* R2268 - DRC2RMIX Input 3 Source */
{ 0x000008DD, 0x0080 }, /* R2269 - DRC2RMIX Input 3 Volume */
{ 0x000008DE, 0x0000 }, /* R2270 - DRC2RMIX Input 4 Source */
{ 0x000008DF, 0x0080 }, /* R2271 - DRC2RMIX Input 4 Volume */
{ 0x00000900, 0x0000 }, /* R2304 - HPLP1MIX Input 1 Source */
{ 0x00000901, 0x0080 }, /* R2305 - HPLP1MIX Input 1 Volume */
{ 0x00000902, 0x0000 }, /* R2306 - HPLP1MIX Input 2 Source */
{ 0x00000903, 0x0080 }, /* R2307 - HPLP1MIX Input 2 Volume */
{ 0x00000904, 0x0000 }, /* R2308 - HPLP1MIX Input 3 Source */
{ 0x00000905, 0x0080 }, /* R2309 - HPLP1MIX Input 3 Volume */
{ 0x00000906, 0x0000 }, /* R2310 - HPLP1MIX Input 4 Source */
{ 0x00000907, 0x0080 }, /* R2311 - HPLP1MIX Input 4 Volume */
{ 0x00000908, 0x0000 }, /* R2312 - HPLP2MIX Input 1 Source */
{ 0x00000909, 0x0080 }, /* R2313 - HPLP2MIX Input 1 Volume */
{ 0x0000090A, 0x0000 }, /* R2314 - HPLP2MIX Input 2 Source */
{ 0x0000090B, 0x0080 }, /* R2315 - HPLP2MIX Input 2 Volume */
{ 0x0000090C, 0x0000 }, /* R2316 - HPLP2MIX Input 3 Source */
{ 0x0000090D, 0x0080 }, /* R2317 - HPLP2MIX Input 3 Volume */
{ 0x0000090E, 0x0000 }, /* R2318 - HPLP2MIX Input 4 Source */
{ 0x0000090F, 0x0080 }, /* R2319 - HPLP2MIX Input 4 Volume */
{ 0x00000910, 0x0000 }, /* R2320 - HPLP3MIX Input 1 Source */
{ 0x00000911, 0x0080 }, /* R2321 - HPLP3MIX Input 1 Volume */
{ 0x00000912, 0x0000 }, /* R2322 - HPLP3MIX Input 2 Source */
{ 0x00000913, 0x0080 }, /* R2323 - HPLP3MIX Input 2 Volume */
{ 0x00000914, 0x0000 }, /* R2324 - HPLP3MIX Input 3 Source */
{ 0x00000915, 0x0080 }, /* R2325 - HPLP3MIX Input 3 Volume */
{ 0x00000916, 0x0000 }, /* R2326 - HPLP3MIX Input 4 Source */
{ 0x00000917, 0x0080 }, /* R2327 - HPLP3MIX Input 4 Volume */
{ 0x00000918, 0x0000 }, /* R2328 - HPLP4MIX Input 1 Source */
{ 0x00000919, 0x0080 }, /* R2329 - HPLP4MIX Input 1 Volume */
{ 0x0000091A, 0x0000 }, /* R2330 - HPLP4MIX Input 2 Source */
{ 0x0000091B, 0x0080 }, /* R2331 - HPLP4MIX Input 2 Volume */
{ 0x0000091C, 0x0000 }, /* R2332 - HPLP4MIX Input 3 Source */
{ 0x0000091D, 0x0080 }, /* R2333 - HPLP4MIX Input 3 Volume */
{ 0x0000091E, 0x0000 }, /* R2334 - HPLP4MIX Input 4 Source */
{ 0x0000091F, 0x0080 }, /* R2335 - HPLP4MIX Input 4 Volume */
{ 0x00000940, 0x0000 }, /* R2368 - DSP1LMIX Input 1 Source */
{ 0x00000941, 0x0080 }, /* R2369 - DSP1LMIX Input 1 Volume */
{ 0x00000942, 0x0000 }, /* R2370 - DSP1LMIX Input 2 Source */
{ 0x00000943, 0x0080 }, /* R2371 - DSP1LMIX Input 2 Volume */
{ 0x00000944, 0x0000 }, /* R2372 - DSP1LMIX Input 3 Source */
{ 0x00000945, 0x0080 }, /* R2373 - DSP1LMIX Input 3 Volume */
{ 0x00000946, 0x0000 }, /* R2374 - DSP1LMIX Input 4 Source */
{ 0x00000947, 0x0080 }, /* R2375 - DSP1LMIX Input 4 Volume */
{ 0x00000948, 0x0000 }, /* R2376 - DSP1RMIX Input 1 Source */
{ 0x00000949, 0x0080 }, /* R2377 - DSP1RMIX Input 1 Volume */
{ 0x0000094A, 0x0000 }, /* R2378 - DSP1RMIX Input 2 Source */
{ 0x0000094B, 0x0080 }, /* R2379 - DSP1RMIX Input 2 Volume */
{ 0x0000094C, 0x0000 }, /* R2380 - DSP1RMIX Input 3 Source */
{ 0x0000094D, 0x0080 }, /* R2381 - DSP1RMIX Input 3 Volume */
{ 0x0000094E, 0x0000 }, /* R2382 - DSP1RMIX Input 4 Source */
{ 0x0000094F, 0x0080 }, /* R2383 - DSP1RMIX Input 4 Volume */
{ 0x00000950, 0x0000 }, /* R2384 - DSP1AUX1MIX Input 1 Source */
{ 0x00000958, 0x0000 }, /* R2392 - DSP1AUX2MIX Input 1 Source */
{ 0x00000960, 0x0000 }, /* R2400 - DSP1AUX3MIX Input 1 Source */
{ 0x00000968, 0x0000 }, /* R2408 - DSP1AUX4MIX Input 1 Source */
{ 0x00000970, 0x0000 }, /* R2416 - DSP1AUX5MIX Input 1 Source */
{ 0x00000978, 0x0000 }, /* R2424 - DSP1AUX6MIX Input 1 Source */
{ 0x00000980, 0x0000 }, /* R2432 - DSP2LMIX Input 1 Source */
{ 0x00000981, 0x0080 }, /* R2433 - DSP2LMIX Input 1 Volume */
{ 0x00000982, 0x0000 }, /* R2434 - DSP2LMIX Input 2 Source */
{ 0x00000983, 0x0080 }, /* R2435 - DSP2LMIX Input 2 Volume */
{ 0x00000984, 0x0000 }, /* R2436 - DSP2LMIX Input 3 Source */
{ 0x00000985, 0x0080 }, /* R2437 - DSP2LMIX Input 3 Volume */
{ 0x00000986, 0x0000 }, /* R2438 - DSP2LMIX Input 4 Source */
{ 0x00000987, 0x0080 }, /* R2439 - DSP2LMIX Input 4 Volume */
{ 0x00000988, 0x0000 }, /* R2440 - DSP2RMIX Input 1 Source */
{ 0x00000989, 0x0080 }, /* R2441 - DSP2RMIX Input 1 Volume */
{ 0x0000098A, 0x0000 }, /* R2442 - DSP2RMIX Input 2 Source */
{ 0x0000098B, 0x0080 }, /* R2443 - DSP2RMIX Input 2 Volume */
{ 0x0000098C, 0x0000 }, /* R2444 - DSP2RMIX Input 3 Source */
{ 0x0000098D, 0x0080 }, /* R2445 - DSP2RMIX Input 3 Volume */
{ 0x0000098E, 0x0000 }, /* R2446 - DSP2RMIX Input 4 Source */
{ 0x0000098F, 0x0080 }, /* R2447 - DSP2RMIX Input 4 Volume */
{ 0x00000990, 0x0000 }, /* R2448 - DSP2AUX1MIX Input 1 Source */
{ 0x00000998, 0x0000 }, /* R2456 - DSP2AUX2MIX Input 1 Source */
{ 0x000009A0, 0x0000 }, /* R2464 - DSP2AUX3MIX Input 1 Source */
{ 0x000009A8, 0x0000 }, /* R2472 - DSP2AUX4MIX Input 1 Source */
{ 0x000009B0, 0x0000 }, /* R2480 - DSP2AUX5MIX Input 1 Source */
{ 0x000009B8, 0x0000 }, /* R2488 - DSP2AUX6MIX Input 1 Source */
{ 0x000009C0, 0x0000 }, /* R2496 - DSP3LMIX Input 1 Source */
{ 0x000009C1, 0x0080 }, /* R2497 - DSP3LMIX Input 1 Volume */
{ 0x000009C2, 0x0000 }, /* R2498 - DSP3LMIX Input 2 Source */
{ 0x000009C3, 0x0080 }, /* R2499 - DSP3LMIX Input 2 Volume */
{ 0x000009C4, 0x0000 }, /* R2500 - DSP3LMIX Input 3 Source */
{ 0x000009C5, 0x0080 }, /* R2501 - DSP3LMIX Input 3 Volume */
{ 0x000009C6, 0x0000 }, /* R2502 - DSP3LMIX Input 4 Source */
{ 0x000009C7, 0x0080 }, /* R2503 - DSP3LMIX Input 4 Volume */
{ 0x000009C8, 0x0000 }, /* R2504 - DSP3RMIX Input 1 Source */
{ 0x000009C9, 0x0080 }, /* R2505 - DSP3RMIX Input 1 Volume */
{ 0x000009CA, 0x0000 }, /* R2506 - DSP3RMIX Input 2 Source */
{ 0x000009CB, 0x0080 }, /* R2507 - DSP3RMIX Input 2 Volume */
{ 0x000009CC, 0x0000 }, /* R2508 - DSP3RMIX Input 3 Source */
{ 0x000009CD, 0x0080 }, /* R2509 - DSP3RMIX Input 3 Volume */
{ 0x000009CE, 0x0000 }, /* R2510 - DSP3RMIX Input 4 Source */
{ 0x000009CF, 0x0080 }, /* R2511 - DSP3RMIX Input 4 Volume */
{ 0x000009D0, 0x0000 }, /* R2512 - DSP3AUX1MIX Input 1 Source */
{ 0x000009D8, 0x0000 }, /* R2520 - DSP3AUX2MIX Input 1 Source */
{ 0x000009E0, 0x0000 }, /* R2528 - DSP3AUX3MIX Input 1 Source */
{ 0x000009E8, 0x0000 }, /* R2536 - DSP3AUX4MIX Input 1 Source */
{ 0x000009F0, 0x0000 }, /* R2544 - DSP3AUX5MIX Input 1 Source */
{ 0x000009F8, 0x0000 }, /* R2552 - DSP3AUX6MIX Input 1 Source */
{ 0x00000A00, 0x0000 }, /* R2560 - DSP4LMIX Input 1 Source */
{ 0x00000A01, 0x0080 }, /* R2561 - DSP4LMIX Input 1 Volume */
{ 0x00000A02, 0x0000 }, /* R2562 - DSP4LMIX Input 2 Source */
{ 0x00000A03, 0x0080 }, /* R2563 - DSP4LMIX Input 2 Volume */
{ 0x00000A04, 0x0000 }, /* R2564 - DSP4LMIX Input 3 Source */
{ 0x00000A05, 0x0080 }, /* R2565 - DSP4LMIX Input 3 Volume */
{ 0x00000A06, 0x0000 }, /* R2566 - DSP4LMIX Input 4 Source */
{ 0x00000A07, 0x0080 }, /* R2567 - DSP4LMIX Input 4 Volume */
{ 0x00000A08, 0x0000 }, /* R2568 - DSP4RMIX Input 1 Source */
{ 0x00000A09, 0x0080 }, /* R2569 - DSP4RMIX Input 1 Volume */
{ 0x00000A0A, 0x0000 }, /* R2570 - DSP4RMIX Input 2 Source */
{ 0x00000A0B, 0x0080 }, /* R2571 - DSP4RMIX Input 2 Volume */
{ 0x00000A0C, 0x0000 }, /* R2572 - DSP4RMIX Input 3 Source */
{ 0x00000A0D, 0x0080 }, /* R2573 - DSP4RMIX Input 3 Volume */
{ 0x00000A0E, 0x0000 }, /* R2574 - DSP4RMIX Input 4 Source */
{ 0x00000A0F, 0x0080 }, /* R2575 - DSP4RMIX Input 4 Volume */
{ 0x00000A10, 0x0000 }, /* R2576 - DSP4AUX1MIX Input 1 Source */
{ 0x00000A18, 0x0000 }, /* R2584 - DSP4AUX2MIX Input 1 Source */
{ 0x00000A20, 0x0000 }, /* R2592 - DSP4AUX3MIX Input 1 Source */
{ 0x00000A28, 0x0000 }, /* R2600 - DSP4AUX4MIX Input 1 Source */
{ 0x00000A30, 0x0000 }, /* R2608 - DSP4AUX5MIX Input 1 Source */
{ 0x00000A38, 0x0000 }, /* R2616 - DSP4AUX6MIX Input 1 Source */
{ 0x00000A80, 0x0000 }, /* R2688 - ASRC1LMIX Input 1 Source */
{ 0x00000A88, 0x0000 }, /* R2696 - ASRC1RMIX Input 1 Source */
{ 0x00000A90, 0x0000 }, /* R2704 - ASRC2LMIX Input 1 Source */
{ 0x00000A98, 0x0000 }, /* R2712 - ASRC2RMIX Input 1 Source */
{ 0x00000B00, 0x0000 }, /* R2816 - ISRC1DEC1MIX Input 1 Source */
{ 0x00000B08, 0x0000 }, /* R2824 - ISRC1DEC2MIX Input 1 Source */
{ 0x00000B10, 0x0000 }, /* R2832 - ISRC1DEC3MIX Input 1 Source */
{ 0x00000B18, 0x0000 }, /* R2840 - ISRC1DEC4MIX Input 1 Source */
{ 0x00000B20, 0x0000 }, /* R2848 - ISRC1INT1MIX Input 1 Source */
{ 0x00000B28, 0x0000 }, /* R2856 - ISRC1INT2MIX Input 1 Source */
{ 0x00000B30, 0x0000 }, /* R2864 - ISRC1INT3MIX Input 1 Source */
{ 0x00000B38, 0x0000 }, /* R2872 - ISRC1INT4MIX Input 1 Source */
{ 0x00000B40, 0x0000 }, /* R2880 - ISRC2DEC1MIX Input 1 Source */
{ 0x00000B48, 0x0000 }, /* R2888 - ISRC2DEC2MIX Input 1 Source */
{ 0x00000B50, 0x0000 }, /* R2896 - ISRC2DEC3MIX Input 1 Source */
{ 0x00000B58, 0x0000 }, /* R2904 - ISRC2DEC4MIX Input 1 Source */
{ 0x00000B60, 0x0000 }, /* R2912 - ISRC2INT1MIX Input 1 Source */
{ 0x00000B68, 0x0000 }, /* R2920 - ISRC2INT2MIX Input 1 Source */
{ 0x00000B70, 0x0000 }, /* R2928 - ISRC2INT3MIX Input 1 Source */
{ 0x00000B78, 0x0000 }, /* R2936 - ISRC2INT4MIX Input 1 Source */
{ 0x00000B80, 0x0000 }, /* R2944 - ISRC3DEC1MIX Input 1 Source */
{ 0x00000B88, 0x0000 }, /* R2952 - ISRC3DEC2MIX Input 1 Source */
{ 0x00000B90, 0x0000 }, /* R2960 - ISRC3DEC3MIX Input 1 Source */
{ 0x00000B98, 0x0000 }, /* R2968 - ISRC3DEC4MIX Input 1 Source */
{ 0x00000BA0, 0x0000 }, /* R2976 - ISRC3INT1MIX Input 1 Source */
{ 0x00000BA8, 0x0000 }, /* R2984 - ISRC3INT2MIX Input 1 Source */
{ 0x00000BB0, 0x0000 }, /* R2992 - ISRC3INT3MIX Input 1 Source */
{ 0x00000BB8, 0x0000 }, /* R3000 - ISRC3INT4MIX Input 1 Source */
{ 0x00000C00, 0xA101 }, /* R3072 - GPIO1 CTRL */
{ 0x00000C01, 0xA101 }, /* R3073 - GPIO2 CTRL */
{ 0x00000C02, 0xA101 }, /* R3074 - GPIO3 CTRL */
{ 0x00000C03, 0xA101 }, /* R3075 - GPIO4 CTRL */
{ 0x00000C04, 0xA101 }, /* R3076 - GPIO5 CTRL */
{ 0x00000C0F, 0x0400 }, /* R3087 - IRQ CTRL 1 */
{ 0x00000C10, 0x1000 }, /* R3088 - GPIO Debounce Config */
{ 0x00000C18, 0x0000 }, /* R3096 - GP Switch 1 */
{ 0x00000C20, 0x8002 }, /* R3104 - Misc Pad Ctrl 1 */
{ 0x00000C21, 0x0001 }, /* R3105 - Misc Pad Ctrl 2 */
{ 0x00000C22, 0x0000 }, /* R3106 - Misc Pad Ctrl 3 */
{ 0x00000C23, 0x0000 }, /* R3107 - Misc Pad Ctrl 4 */
{ 0x00000C24, 0x0000 }, /* R3108 - Misc Pad Ctrl 5 */
{ 0x00000C25, 0x0000 }, /* R3109 - Misc Pad Ctrl 6 */
{ 0x00000C30, 0x0404 }, /* R3120 - Misc Pad Ctrl 7 */
{ 0x00000C31, 0x0004 }, /* R3121 - Misc Pad Ctrl 8 */
{ 0x00000C32, 0x0404 }, /* R3122 - Misc Pad Ctrl 9 */
{ 0x00000C33, 0x0404 }, /* R3123 - Misc Pad Ctrl 10 */
{ 0x00000C34, 0x0404 }, /* R3124 - Misc Pad Ctrl 11 */
{ 0x00000C35, 0x0404 }, /* R3125 - Misc Pad Ctrl 12 */
{ 0x00000C36, 0x0404 }, /* R3126 - Misc Pad Ctrl 13 */
{ 0x00000C37, 0x0404 }, /* R3127 - Misc Pad Ctrl 14 */
{ 0x00000C38, 0x0004 }, /* R3128 - Misc Pad Ctrl 15 */
{ 0x00000C39, 0x0404 }, /* R3129 - Misc Pad Ctrl 16 */
{ 0x00000C3A, 0x0404 }, /* R3130 - Misc Pad Ctrl 17 */
{ 0x00000C3B, 0x0404 }, /* R3131 - Misc Pad Ctrl 18 */
{ 0x00000D08, 0xFFFF }, /* R3336 - Interrupt Status 1 Mask */
{ 0x00000D09, 0xFFFF }, /* R3337 - Interrupt Status 2 Mask */
{ 0x00000D0A, 0xFFFF }, /* R3338 - Interrupt Status 3 Mask */
{ 0x00000D0B, 0xFFFF }, /* R3339 - Interrupt Status 4 Mask */
{ 0x00000D0C, 0xFEFF }, /* R3340 - Interrupt Status 5 Mask */
{ 0x00000D0D, 0xFFFF }, /* R3341 - Interrupt Status 6 Mask */
{ 0x00000D0F, 0x0000 }, /* R3343 - Interrupt Control */
{ 0x00000D18, 0xFFFF }, /* R3352 - IRQ2 Status 1 Mask */
{ 0x00000D19, 0xFFFF }, /* R3353 - IRQ2 Status 2 Mask */
{ 0x00000D1A, 0xFFFF }, /* R3354 - IRQ2 Status 3 Mask */
{ 0x00000D1B, 0xFFFF }, /* R3355 - IRQ2 Status 4 Mask */
{ 0x00000D1C, 0xFFFF }, /* R3356 - IRQ2 Status 5 Mask */
{ 0x00000D1D, 0xFFFF }, /* R3357 - IRQ2 Status 6 Mask */
{ 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */
{ 0x00000D53, 0xFFFF }, /* R3411 - AOD IRQ Mask IRQ1 */
{ 0x00000D54, 0xFFFF }, /* R3412 - AOD IRQ Mask IRQ2 */
{ 0x00000D56, 0x0000 }, /* R3414 - Jack detect debounce */
{ 0x00000E00, 0x0000 }, /* R3584 - FX_Ctrl1 */
{ 0x00000E10, 0x6318 }, /* R3600 - EQ1_1 */
{ 0x00000E11, 0x6300 }, /* R3601 - EQ1_2 */
{ 0x00000E12, 0x0FC8 }, /* R3602 - EQ1_3 */
{ 0x00000E13, 0x03FE }, /* R3603 - EQ1_4 */
{ 0x00000E14, 0x00E0 }, /* R3604 - EQ1_5 */
{ 0x00000E15, 0x1EC4 }, /* R3605 - EQ1_6 */
{ 0x00000E16, 0xF136 }, /* R3606 - EQ1_7 */
{ 0x00000E17, 0x0409 }, /* R3607 - EQ1_8 */
{ 0x00000E18, 0x04CC }, /* R3608 - EQ1_9 */
{ 0x00000E19, 0x1C9B }, /* R3609 - EQ1_10 */
{ 0x00000E1A, 0xF337 }, /* R3610 - EQ1_11 */
{ 0x00000E1B, 0x040B }, /* R3611 - EQ1_12 */
{ 0x00000E1C, 0x0CBB }, /* R3612 - EQ1_13 */
{ 0x00000E1D, 0x16F8 }, /* R3613 - EQ1_14 */
{ 0x00000E1E, 0xF7D9 }, /* R3614 - EQ1_15 */
{ 0x00000E1F, 0x040A }, /* R3615 - EQ1_16 */
{ 0x00000E20, 0x1F14 }, /* R3616 - EQ1_17 */
{ 0x00000E21, 0x058C }, /* R3617 - EQ1_18 */
{ 0x00000E22, 0x0563 }, /* R3618 - EQ1_19 */
{ 0x00000E23, 0x4000 }, /* R3619 - EQ1_20 */
{ 0x00000E24, 0x0B75 }, /* R3620 - EQ1_21 */
{ 0x00000E26, 0x6318 }, /* R3622 - EQ2_1 */
{ 0x00000E27, 0x6300 }, /* R3623 - EQ2_2 */
{ 0x00000E28, 0x0FC8 }, /* R3624 - EQ2_3 */
{ 0x00000E29, 0x03FE }, /* R3625 - EQ2_4 */
{ 0x00000E2A, 0x00E0 }, /* R3626 - EQ2_5 */
{ 0x00000E2B, 0x1EC4 }, /* R3627 - EQ2_6 */
{ 0x00000E2C, 0xF136 }, /* R3628 - EQ2_7 */
{ 0x00000E2D, 0x0409 }, /* R3629 - EQ2_8 */
{ 0x00000E2E, 0x04CC }, /* R3630 - EQ2_9 */
{ 0x00000E2F, 0x1C9B }, /* R3631 - EQ2_10 */
{ 0x00000E30, 0xF337 }, /* R3632 - EQ2_11 */
{ 0x00000E31, 0x040B }, /* R3633 - EQ2_12 */
{ 0x00000E32, 0x0CBB }, /* R3634 - EQ2_13 */
{ 0x00000E33, 0x16F8 }, /* R3635 - EQ2_14 */
{ 0x00000E34, 0xF7D9 }, /* R3636 - EQ2_15 */
{ 0x00000E35, 0x040A }, /* R3637 - EQ2_16 */
{ 0x00000E36, 0x1F14 }, /* R3638 - EQ2_17 */
{ 0x00000E37, 0x058C }, /* R3639 - EQ2_18 */
{ 0x00000E38, 0x0563 }, /* R3640 - EQ2_19 */
{ 0x00000E39, 0x4000 }, /* R3641 - EQ2_20 */
{ 0x00000E3A, 0x0B75 }, /* R3642 - EQ2_21 */
{ 0x00000E3C, 0x6318 }, /* R3644 - EQ3_1 */
{ 0x00000E3D, 0x6300 }, /* R3645 - EQ3_2 */
{ 0x00000E3E, 0x0FC8 }, /* R3646 - EQ3_3 */
{ 0x00000E3F, 0x03FE }, /* R3647 - EQ3_4 */
{ 0x00000E40, 0x00E0 }, /* R3648 - EQ3_5 */
{ 0x00000E41, 0x1EC4 }, /* R3649 - EQ3_6 */
{ 0x00000E42, 0xF136 }, /* R3650 - EQ3_7 */
{ 0x00000E43, 0x0409 }, /* R3651 - EQ3_8 */
{ 0x00000E44, 0x04CC }, /* R3652 - EQ3_9 */
{ 0x00000E45, 0x1C9B }, /* R3653 - EQ3_10 */
{ 0x00000E46, 0xF337 }, /* R3654 - EQ3_11 */
{ 0x00000E47, 0x040B }, /* R3655 - EQ3_12 */
{ 0x00000E48, 0x0CBB }, /* R3656 - EQ3_13 */
{ 0x00000E49, 0x16F8 }, /* R3657 - EQ3_14 */
{ 0x00000E4A, 0xF7D9 }, /* R3658 - EQ3_15 */
{ 0x00000E4B, 0x040A }, /* R3659 - EQ3_16 */
{ 0x00000E4C, 0x1F14 }, /* R3660 - EQ3_17 */
{ 0x00000E4D, 0x058C }, /* R3661 - EQ3_18 */
{ 0x00000E4E, 0x0563 }, /* R3662 - EQ3_19 */
{ 0x00000E4F, 0x4000 }, /* R3663 - EQ3_20 */
{ 0x00000E50, 0x0B75 }, /* R3664 - EQ3_21 */
{ 0x00000E52, 0x6318 }, /* R3666 - EQ4_1 */
{ 0x00000E53, 0x6300 }, /* R3667 - EQ4_2 */
{ 0x00000E54, 0x0FC8 }, /* R3668 - EQ4_3 */
{ 0x00000E55, 0x03FE }, /* R3669 - EQ4_4 */
{ 0x00000E56, 0x00E0 }, /* R3670 - EQ4_5 */
{ 0x00000E57, 0x1EC4 }, /* R3671 - EQ4_6 */
{ 0x00000E58, 0xF136 }, /* R3672 - EQ4_7 */
{ 0x00000E59, 0x0409 }, /* R3673 - EQ4_8 */
{ 0x00000E5A, 0x04CC }, /* R3674 - EQ4_9 */
{ 0x00000E5B, 0x1C9B }, /* R3675 - EQ4_10 */
{ 0x00000E5C, 0xF337 }, /* R3676 - EQ4_11 */
{ 0x00000E5D, 0x040B }, /* R3677 - EQ4_12 */
{ 0x00000E5E, 0x0CBB }, /* R3678 - EQ4_13 */
{ 0x00000E5F, 0x16F8 }, /* R3679 - EQ4_14 */
{ 0x00000E60, 0xF7D9 }, /* R3680 - EQ4_15 */
{ 0x00000E61, 0x040A }, /* R3681 - EQ4_16 */
{ 0x00000E62, 0x1F14 }, /* R3682 - EQ4_17 */
{ 0x00000E63, 0x058C }, /* R3683 - EQ4_18 */
{ 0x00000E64, 0x0563 }, /* R3684 - EQ4_19 */
{ 0x00000E65, 0x4000 }, /* R3685 - EQ4_20 */
{ 0x00000E66, 0x0B75 }, /* R3686 - EQ4_21 */
{ 0x00000E80, 0x0018 }, /* R3712 - DRC1 ctrl1 */
{ 0x00000E81, 0x0933 }, /* R3713 - DRC1 ctrl2 */
{ 0x00000E82, 0x0018 }, /* R3714 - DRC1 ctrl3 */
{ 0x00000E83, 0x0000 }, /* R3715 - DRC1 ctrl4 */
{ 0x00000E84, 0x0000 }, /* R3716 - DRC1 ctrl5 */
{ 0x00000E89, 0x0018 }, /* R3721 - DRC2 ctrl1 */
{ 0x00000E8A, 0x0933 }, /* R3722 - DRC2 ctrl2 */
{ 0x00000E8B, 0x0018 }, /* R3723 - DRC2 ctrl3 */
{ 0x00000E8C, 0x0000 }, /* R3724 - DRC2 ctrl4 */
{ 0x00000E8D, 0x0000 }, /* R3725 - DRC2 ctrl5 */
{ 0x00000EC0, 0x0000 }, /* R3776 - HPLPF1_1 */
{ 0x00000EC1, 0x0000 }, /* R3777 - HPLPF1_2 */
{ 0x00000EC4, 0x0000 }, /* R3780 - HPLPF2_1 */
{ 0x00000EC5, 0x0000 }, /* R3781 - HPLPF2_2 */
{ 0x00000EC8, 0x0000 }, /* R3784 - HPLPF3_1 */
{ 0x00000EC9, 0x0000 }, /* R3785 - HPLPF3_2 */
{ 0x00000ECC, 0x0000 }, /* R3788 - HPLPF4_1 */
{ 0x00000ECD, 0x0000 }, /* R3789 - HPLPF4_2 */
{ 0x00000EE0, 0x0000 }, /* R3808 - ASRC_ENABLE */
{ 0x00000EE2, 0x0000 }, /* R3810 - ASRC_RATE1 */
{ 0x00000EE3, 0x4000 }, /* R3811 - ASRC_RATE2 */
{ 0x00000EF0, 0x0000 }, /* R3824 - ISRC 1 CTRL 1 */
{ 0x00000EF1, 0x0000 }, /* R3825 - ISRC 1 CTRL 2 */
{ 0x00000EF2, 0x0000 }, /* R3826 - ISRC 1 CTRL 3 */
{ 0x00000EF3, 0x0000 }, /* R3827 - ISRC 2 CTRL 1 */
{ 0x00000EF4, 0x0000 }, /* R3828 - ISRC 2 CTRL 2 */
{ 0x00000EF5, 0x0000 }, /* R3829 - ISRC 2 CTRL 3 */
{ 0x00000EF6, 0x0000 }, /* R3830 - ISRC 3 CTRL 1 */
{ 0x00000EF7, 0x0000 }, /* R3831 - ISRC 3 CTRL 2 */
{ 0x00000EF8, 0x0000 }, /* R3832 - ISRC 3 CTRL 3 */
{ 0x00000F00, 0x0000 }, /* R3840 - Clock Control */
{ 0x00000F01, 0x0000 }, /* R3841 - ANC_SRC */
{ 0x00000F08, 0x001c }, /* R3848 - ANC Coefficient */
{ 0x00000F09, 0x0000 }, /* R3849 - ANC Coefficient */
{ 0x00000F0A, 0x0000 }, /* R3850 - ANC Coefficient */
{ 0x00000F0B, 0x0000 }, /* R3851 - ANC Coefficient */
{ 0x00000F0C, 0x0000 }, /* R3852 - ANC Coefficient */
{ 0x00000F0D, 0x0000 }, /* R3853 - ANC Coefficient */
{ 0x00000F0E, 0x0000 }, /* R3854 - ANC Coefficient */
{ 0x00000F0F, 0x0000 }, /* R3855 - ANC Coefficient */
{ 0x00000F10, 0x0001 }, /* R3856 - ANC Coefficient */
{ 0x00000F11, 0x0000 }, /* R3857 - ANC Coefficient */
{ 0x00000F12, 0x0000 }, /* R3858 - ANC Coefficient */
{ 0x00000F15, 0x0000 }, /* R3861 - FCL Filter Control */
{ 0x00000F17, 0x0004 }, /* R3863 - FCL ADC Reformatter Control */
{ 0x00000F18, 0x0004 }, /* R3864 - ANC Coefficient */
{ 0x00000F19, 0x0002 }, /* R3865 - ANC Coefficient */
{ 0x00000F1A, 0x0000 }, /* R3866 - ANC Coefficient */
{ 0x00000F1B, 0x0010 }, /* R3867 - ANC Coefficient */
{ 0x00000F1C, 0x0000 }, /* R3868 - ANC Coefficient */
{ 0x00000F1D, 0x0000 }, /* R3869 - ANC Coefficient */
{ 0x00000F1E, 0x0000 }, /* R3870 - ANC Coefficient */
{ 0x00000F1F, 0x0000 }, /* R3871 - ANC Coefficient */
{ 0x00000F20, 0x0000 }, /* R3872 - ANC Coefficient */
{ 0x00000F21, 0x0000 }, /* R3873 - ANC Coefficient */
{ 0x00000F22, 0x0000 }, /* R3874 - ANC Coefficient */
{ 0x00000F23, 0x0000 }, /* R3875 - ANC Coefficient */
{ 0x00000F24, 0x0000 }, /* R3876 - ANC Coefficient */
{ 0x00000F25, 0x0000 }, /* R3877 - ANC Coefficient */
{ 0x00000F26, 0x0000 }, /* R3878 - ANC Coefficient */
{ 0x00000F27, 0x0000 }, /* R3879 - ANC Coefficient */
{ 0x00000F28, 0x0000 }, /* R3880 - ANC Coefficient */
{ 0x00000F29, 0x0000 }, /* R3881 - ANC Coefficient */
{ 0x00000F2A, 0x0000 }, /* R3882 - ANC Coefficient */
{ 0x00000F2B, 0x0000 }, /* R3883 - ANC Coefficient */
{ 0x00000F2C, 0x0000 }, /* R3884 - ANC Coefficient */
{ 0x00000F2D, 0x0000 }, /* R3885 - ANC Coefficient */
{ 0x00000F2E, 0x0000 }, /* R3886 - ANC Coefficient */
{ 0x00000F2F, 0x0000 }, /* R3887 - ANC Coefficient */
{ 0x00000F30, 0x0000 }, /* R3888 - ANC Coefficient */
{ 0x00000F31, 0x0000 }, /* R3889 - ANC Coefficient */
{ 0x00000F32, 0x0000 }, /* R3890 - ANC Coefficient */
{ 0x00000F33, 0x0000 }, /* R3891 - ANC Coefficient */
{ 0x00000F34, 0x0000 }, /* R3892 - ANC Coefficient */
{ 0x00000F35, 0x0000 }, /* R3893 - ANC Coefficient */
{ 0x00000F36, 0x0000 }, /* R3894 - ANC Coefficient */
{ 0x00000F37, 0x0000 }, /* R3895 - ANC Coefficient */
{ 0x00000F38, 0x0000 }, /* R3896 - ANC Coefficient */
{ 0x00000F39, 0x0000 }, /* R3897 - ANC Coefficient */
{ 0x00000F3A, 0x0000 }, /* R3898 - ANC Coefficient */
{ 0x00000F3B, 0x0000 }, /* R3899 - ANC Coefficient */
{ 0x00000F3C, 0x0000 }, /* R3900 - ANC Coefficient */
{ 0x00000F3D, 0x0000 }, /* R3901 - ANC Coefficient */
{ 0x00000F3E, 0x0000 }, /* R3902 - ANC Coefficient */
{ 0x00000F3F, 0x0000 }, /* R3903 - ANC Coefficient */
{ 0x00000F40, 0x0000 }, /* R3904 - ANC Coefficient */
{ 0x00000F41, 0x0000 }, /* R3905 - ANC Coefficient */
{ 0x00000F42, 0x0000 }, /* R3906 - ANC Coefficient */
{ 0x00000F43, 0x0000 }, /* R3907 - ANC Coefficient */
{ 0x00000F44, 0x0000 }, /* R3908 - ANC Coefficient */
{ 0x00000F45, 0x0000 }, /* R3909 - ANC Coefficient */
{ 0x00000F46, 0x0000 }, /* R3910 - ANC Coefficient */
{ 0x00000F47, 0x0000 }, /* R3911 - ANC Coefficient */
{ 0x00000F48, 0x0000 }, /* R3912 - ANC Coefficient */
{ 0x00000F49, 0x0000 }, /* R3913 - ANC Coefficient */
{ 0x00000F4A, 0x0000 }, /* R3914 - ANC Coefficient */
{ 0x00000F4B, 0x0000 }, /* R3915 - ANC Coefficient */
{ 0x00000F4C, 0x0000 }, /* R3916 - ANC Coefficient */
{ 0x00000F4D, 0x0000 }, /* R3917 - ANC Coefficient */
{ 0x00000F4E, 0x0000 }, /* R3918 - ANC Coefficient */
{ 0x00000F4F, 0x0000 }, /* R3919 - ANC Coefficient */
{ 0x00000F50, 0x0000 }, /* R3920 - ANC Coefficient */
{ 0x00000F51, 0x0000 }, /* R3921 - ANC Coefficient */
{ 0x00000F52, 0x0000 }, /* R3922 - ANC Coefficient */
{ 0x00000F53, 0x0000 }, /* R3923 - ANC Coefficient */
{ 0x00000F54, 0x0000 }, /* R3924 - ANC Coefficient */
{ 0x00000F55, 0x0000 }, /* R3925 - ANC Coefficient */
{ 0x00000F56, 0x0000 }, /* R3926 - ANC Coefficient */
{ 0x00000F57, 0x0000 }, /* R3927 - ANC Coefficient */
{ 0x00000F58, 0x0000 }, /* R3928 - ANC Coefficient */
{ 0x00000F59, 0x0000 }, /* R3929 - ANC Coefficient */
{ 0x00000F5A, 0x0000 }, /* R3930 - ANC Coefficient */
{ 0x00000F5B, 0x0000 }, /* R3931 - ANC Coefficient */
{ 0x00000F5C, 0x0000 }, /* R3932 - ANC Coefficient */
{ 0x00000F5D, 0x0000 }, /* R3933 - ANC Coefficient */
{ 0x00000F5E, 0x0000 }, /* R3934 - ANC Coefficient */
{ 0x00000F5F, 0x0000 }, /* R3935 - ANC Coefficient */
{ 0x00000F60, 0x0000 }, /* R3936 - ANC Coefficient */
{ 0x00000F61, 0x0000 }, /* R3937 - ANC Coefficient */
{ 0x00000F62, 0x0000 }, /* R3938 - ANC Coefficient */
{ 0x00000F63, 0x0000 }, /* R3939 - ANC Coefficient */
{ 0x00000F64, 0x0000 }, /* R3940 - ANC Coefficient */
{ 0x00000F65, 0x0000 }, /* R3941 - ANC Coefficient */
{ 0x00000F66, 0x0000 }, /* R3942 - ANC Coefficient */
{ 0x00000F67, 0x0000 }, /* R3943 - ANC Coefficient */
{ 0x00000F68, 0x0000 }, /* R3944 - ANC Coefficient */
{ 0x00000F69, 0x0000 }, /* R3945 - ANC Coefficient */
{ 0x00000F70, 0x0000 }, /* R3952 - FCR Filter Control */
{ 0x00000F72, 0x0004 }, /* R3954 - FCR ADC Reformatter Control */
{ 0x00000F73, 0x0004 }, /* R3955 - ANC Coefficient */
{ 0x00000F74, 0x0002 }, /* R3956 - ANC Coefficient */
{ 0x00000F75, 0x0000 }, /* R3957 - ANC Coefficient */
{ 0x00000F76, 0x0010 }, /* R3958 - ANC Coefficient */
{ 0x00000F77, 0x0000 }, /* R3959 - ANC Coefficient */
{ 0x00000F78, 0x0000 }, /* R3960 - ANC Coefficient */
{ 0x00000F79, 0x0000 }, /* R3961 - ANC Coefficient */
{ 0x00000F7A, 0x0000 }, /* R3962 - ANC Coefficient */
{ 0x00000F7B, 0x0000 }, /* R3963 - ANC Coefficient */
{ 0x00000F7C, 0x0000 }, /* R3964 - ANC Coefficient */
{ 0x00000F7D, 0x0000 }, /* R3965 - ANC Coefficient */
{ 0x00000F7E, 0x0000 }, /* R3966 - ANC Coefficient */
{ 0x00000F7F, 0x0000 }, /* R3967 - ANC Coefficient */
{ 0x00000F80, 0x0000 }, /* R3968 - ANC Coefficient */
{ 0x00000F81, 0x0000 }, /* R3969 - ANC Coefficient */
{ 0x00000F82, 0x0000 }, /* R3970 - ANC Coefficient */
{ 0x00000F83, 0x0000 }, /* R3971 - ANC Coefficient */
{ 0x00000F84, 0x0000 }, /* R3972 - ANC Coefficient */
{ 0x00000F85, 0x0000 }, /* R3973 - ANC Coefficient */
{ 0x00000F86, 0x0000 }, /* R3974 - ANC Coefficient */
{ 0x00000F87, 0x0000 }, /* R3975 - ANC Coefficient */
{ 0x00000F88, 0x0000 }, /* R3976 - ANC Coefficient */
{ 0x00000F89, 0x0000 }, /* R3977 - ANC Coefficient */
{ 0x00000F8A, 0x0000 }, /* R3978 - ANC Coefficient */
{ 0x00000F8B, 0x0000 }, /* R3979 - ANC Coefficient */
{ 0x00000F8C, 0x0000 }, /* R3980 - ANC Coefficient */
{ 0x00000F8D, 0x0000 }, /* R3981 - ANC Coefficient */
{ 0x00000F8E, 0x0000 }, /* R3982 - ANC Coefficient */
{ 0x00000F8F, 0x0000 }, /* R3983 - ANC Coefficient */
{ 0x00000F90, 0x0000 }, /* R3984 - ANC Coefficient */
{ 0x00000F91, 0x0000 }, /* R3985 - ANC Coefficient */
{ 0x00000F92, 0x0000 }, /* R3986 - ANC Coefficient */
{ 0x00000F93, 0x0000 }, /* R3987 - ANC Coefficient */
{ 0x00000F94, 0x0000 }, /* R3988 - ANC Coefficient */
{ 0x00000F95, 0x0000 }, /* R3989 - ANC Coefficient */
{ 0x00000F96, 0x0000 }, /* R3990 - ANC Coefficient */
{ 0x00000F97, 0x0000 }, /* R3991 - ANC Coefficient */
{ 0x00000F98, 0x0000 }, /* R3992 - ANC Coefficient */
{ 0x00000F99, 0x0000 }, /* R3993 - ANC Coefficient */
{ 0x00000F9A, 0x0000 }, /* R3994 - ANC Coefficient */
{ 0x00000F9B, 0x0000 }, /* R3995 - ANC Coefficient */
{ 0x00000F9C, 0x0000 }, /* R3996 - ANC Coefficient */
{ 0x00000F9D, 0x0000 }, /* R3997 - ANC Coefficient */
{ 0x00000F9E, 0x0000 }, /* R3998 - ANC Coefficient */
{ 0x00000F9F, 0x0000 }, /* R3999 - ANC Coefficient */
{ 0x00000FA0, 0x0000 }, /* R4000 - ANC Coefficient */
{ 0x00000FA1, 0x0000 }, /* R4001 - ANC Coefficient */
{ 0x00000FA2, 0x0000 }, /* R4002 - ANC Coefficient */
{ 0x00000FA3, 0x0000 }, /* R4003 - ANC Coefficient */
{ 0x00000FA4, 0x0000 }, /* R4004 - ANC Coefficient */
{ 0x00000FA5, 0x0000 }, /* R4005 - ANC Coefficient */
{ 0x00000FA6, 0x0000 }, /* R4006 - ANC Coefficient */
{ 0x00000FA7, 0x0000 }, /* R4007 - ANC Coefficient */
{ 0x00000FA8, 0x0000 }, /* R4008 - ANC Coefficient */
{ 0x00000FA9, 0x0000 }, /* R4009 - ANC Coefficient */
{ 0x00000FAA, 0x0000 }, /* R4010 - ANC Coefficient */
{ 0x00000FAB, 0x0000 }, /* R4011 - ANC Coefficient */
{ 0x00000FAC, 0x0000 }, /* R4012 - ANC Coefficient */
{ 0x00000FAD, 0x0000 }, /* R4013 - ANC Coefficient */
{ 0x00000FAE, 0x0000 }, /* R4014 - ANC Coefficient */
{ 0x00000FAF, 0x0000 }, /* R4015 - ANC Coefficient */
{ 0x00000FB0, 0x0000 }, /* R4016 - ANC Coefficient */
{ 0x00000FB1, 0x0000 }, /* R4017 - ANC Coefficient */
{ 0x00000FB2, 0x0000 }, /* R4018 - ANC Coefficient */
{ 0x00000FB3, 0x0000 }, /* R4019 - ANC Coefficient */
{ 0x00000FB4, 0x0000 }, /* R4020 - ANC Coefficient */
{ 0x00000FB5, 0x0000 }, /* R4021 - ANC Coefficient */
{ 0x00000FB6, 0x0000 }, /* R4022 - ANC Coefficient */
{ 0x00000FB7, 0x0000 }, /* R4023 - ANC Coefficient */
{ 0x00000FB8, 0x0000 }, /* R4024 - ANC Coefficient */
{ 0x00000FB9, 0x0000 }, /* R4025 - ANC Coefficient */
{ 0x00000FBA, 0x0000 }, /* R4026 - ANC Coefficient */
{ 0x00000FBB, 0x0000 }, /* R4027 - ANC Coefficient */
{ 0x00000FBC, 0x0000 }, /* R4028 - ANC Coefficient */
{ 0x00000FBD, 0x0000 }, /* R4029 - ANC Coefficient */
{ 0x00000FBE, 0x0000 }, /* R4030 - ANC Coefficient */
{ 0x00000FBF, 0x0000 }, /* R4031 - ANC Coefficient */
{ 0x00000FC0, 0x0000 }, /* R4032 - ANC Coefficient */
{ 0x00000FC1, 0x0000 }, /* R4033 - ANC Coefficient */
{ 0x00000FC2, 0x0000 }, /* R4034 - ANC Coefficient */
{ 0x00000FC3, 0x0000 }, /* R4035 - ANC Coefficient */
{ 0x00000FC4, 0x0000 }, /* R4036 - ANC Coefficient */
{ 0x00001100, 0x0010 }, /* R4352 - DSP1 Control 1 */
{ 0x00001200, 0x0010 }, /* R4608 - DSP2 Control 1 */
{ 0x00001300, 0x0010 }, /* R4864 - DSP3 Control 1 */
{ 0x00001400, 0x0010 }, /* R5120 - DSP4 Control 1 */
};
static bool wm5110_is_rev_b_adsp_memory(unsigned int reg)
{
if ((reg >= 0x100000 && reg < 0x103000) ||
(reg >= 0x180000 && reg < 0x181000) ||
(reg >= 0x190000 && reg < 0x192000) ||
(reg >= 0x1a8000 && reg < 0x1a9000) ||
(reg >= 0x200000 && reg < 0x209000) ||
(reg >= 0x280000 && reg < 0x281000) ||
(reg >= 0x290000 && reg < 0x29a000) ||
(reg >= 0x2a8000 && reg < 0x2aa000) ||
(reg >= 0x300000 && reg < 0x30f000) ||
(reg >= 0x380000 && reg < 0x382000) ||
(reg >= 0x390000 && reg < 0x39e000) ||
(reg >= 0x3a8000 && reg < 0x3b6000) ||
(reg >= 0x400000 && reg < 0x403000) ||
(reg >= 0x480000 && reg < 0x481000) ||
(reg >= 0x490000 && reg < 0x492000) ||
(reg >= 0x4a8000 && reg < 0x4a9000))
return true;
else
return false;
}
static bool wm5110_is_rev_d_adsp_memory(unsigned int reg)
{
if ((reg >= 0x100000 && reg < 0x106000) ||
(reg >= 0x180000 && reg < 0x182000) ||
(reg >= 0x190000 && reg < 0x198000) ||
(reg >= 0x1a8000 && reg < 0x1aa000) ||
(reg >= 0x200000 && reg < 0x20f000) ||
(reg >= 0x280000 && reg < 0x282000) ||
(reg >= 0x290000 && reg < 0x29c000) ||
(reg >= 0x2a6000 && reg < 0x2b4000) ||
(reg >= 0x300000 && reg < 0x30f000) ||
(reg >= 0x380000 && reg < 0x382000) ||
(reg >= 0x390000 && reg < 0x3a2000) ||
(reg >= 0x3a6000 && reg < 0x3b4000) ||
(reg >= 0x400000 && reg < 0x406000) ||
(reg >= 0x480000 && reg < 0x482000) ||
(reg >= 0x490000 && reg < 0x498000) ||
(reg >= 0x4a8000 && reg < 0x4aa000))
return true;
else
return false;
}
static bool wm5110_is_adsp_memory(struct device *dev, unsigned int reg)
{
struct arizona *arizona = dev_get_drvdata(dev);
switch (arizona->rev) {
case 0 ... 2:
return wm5110_is_rev_b_adsp_memory(reg);
default:
return wm5110_is_rev_d_adsp_memory(reg);
}
}
static bool wm5110_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case ARIZONA_SOFTWARE_RESET:
case ARIZONA_DEVICE_REVISION:
case ARIZONA_CTRL_IF_SPI_CFG_1:
case ARIZONA_CTRL_IF_I2C1_CFG_1:
case ARIZONA_CTRL_IF_I2C2_CFG_1:
case ARIZONA_CTRL_IF_I2C1_CFG_2:
case ARIZONA_CTRL_IF_I2C2_CFG_2:
case ARIZONA_WRITE_SEQUENCER_CTRL_0:
case ARIZONA_WRITE_SEQUENCER_CTRL_1:
case ARIZONA_WRITE_SEQUENCER_CTRL_2:
case ARIZONA_TONE_GENERATOR_1:
case ARIZONA_TONE_GENERATOR_2:
case ARIZONA_TONE_GENERATOR_3:
case ARIZONA_TONE_GENERATOR_4:
case ARIZONA_TONE_GENERATOR_5:
case ARIZONA_PWM_DRIVE_1:
case ARIZONA_PWM_DRIVE_2:
case ARIZONA_PWM_DRIVE_3:
case ARIZONA_WAKE_CONTROL:
case ARIZONA_SEQUENCE_CONTROL:
case ARIZONA_SPARE_TRIGGERS:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6:
case ARIZONA_COMFORT_NOISE_GENERATOR:
case ARIZONA_HAPTICS_CONTROL_1:
case ARIZONA_HAPTICS_CONTROL_2:
case ARIZONA_HAPTICS_PHASE_1_INTENSITY:
case ARIZONA_HAPTICS_PHASE_1_DURATION:
case ARIZONA_HAPTICS_PHASE_2_INTENSITY:
case ARIZONA_HAPTICS_PHASE_2_DURATION:
case ARIZONA_HAPTICS_PHASE_3_INTENSITY:
case ARIZONA_HAPTICS_PHASE_3_DURATION:
case ARIZONA_HAPTICS_STATUS:
case ARIZONA_CLOCK_32K_1:
case ARIZONA_SYSTEM_CLOCK_1:
case ARIZONA_SAMPLE_RATE_1:
case ARIZONA_SAMPLE_RATE_2:
case ARIZONA_SAMPLE_RATE_3:
case ARIZONA_SAMPLE_RATE_1_STATUS:
case ARIZONA_SAMPLE_RATE_2_STATUS:
case ARIZONA_SAMPLE_RATE_3_STATUS:
case ARIZONA_ASYNC_CLOCK_1:
case ARIZONA_ASYNC_SAMPLE_RATE_1:
case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
case ARIZONA_ASYNC_SAMPLE_RATE_2:
case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS:
case ARIZONA_OUTPUT_SYSTEM_CLOCK:
case ARIZONA_OUTPUT_ASYNC_CLOCK:
case ARIZONA_RATE_ESTIMATOR_1:
case ARIZONA_RATE_ESTIMATOR_2:
case ARIZONA_RATE_ESTIMATOR_3:
case ARIZONA_RATE_ESTIMATOR_4:
case ARIZONA_RATE_ESTIMATOR_5:
case ARIZONA_FLL1_CONTROL_1:
case ARIZONA_FLL1_CONTROL_2:
case ARIZONA_FLL1_CONTROL_3:
case ARIZONA_FLL1_CONTROL_4:
case ARIZONA_FLL1_CONTROL_5:
case ARIZONA_FLL1_CONTROL_6:
case ARIZONA_FLL1_CONTROL_7:
case ARIZONA_FLL1_SYNCHRONISER_1:
case ARIZONA_FLL1_SYNCHRONISER_2:
case ARIZONA_FLL1_SYNCHRONISER_3:
case ARIZONA_FLL1_SYNCHRONISER_4:
case ARIZONA_FLL1_SYNCHRONISER_5:
case ARIZONA_FLL1_SYNCHRONISER_6:
case ARIZONA_FLL1_SYNCHRONISER_7:
case ARIZONA_FLL1_SPREAD_SPECTRUM:
case ARIZONA_FLL1_GPIO_CLOCK:
case ARIZONA_FLL2_CONTROL_1:
case ARIZONA_FLL2_CONTROL_2:
case ARIZONA_FLL2_CONTROL_3:
case ARIZONA_FLL2_CONTROL_4:
case ARIZONA_FLL2_CONTROL_5:
case ARIZONA_FLL2_CONTROL_6:
case ARIZONA_FLL2_CONTROL_7:
case ARIZONA_FLL2_SYNCHRONISER_1:
case ARIZONA_FLL2_SYNCHRONISER_2:
case ARIZONA_FLL2_SYNCHRONISER_3:
case ARIZONA_FLL2_SYNCHRONISER_4:
case ARIZONA_FLL2_SYNCHRONISER_5:
case ARIZONA_FLL2_SYNCHRONISER_6:
case ARIZONA_FLL2_SYNCHRONISER_7:
case ARIZONA_FLL2_SPREAD_SPECTRUM:
case ARIZONA_FLL2_GPIO_CLOCK:
case ARIZONA_MIC_CHARGE_PUMP_1:
case ARIZONA_LDO1_CONTROL_1:
case ARIZONA_LDO2_CONTROL_1:
case ARIZONA_MIC_BIAS_CTRL_1:
case ARIZONA_MIC_BIAS_CTRL_2:
case ARIZONA_MIC_BIAS_CTRL_3:
case ARIZONA_HP_CTRL_1L:
case ARIZONA_HP_CTRL_1R:
case ARIZONA_ACCESSORY_DETECT_MODE_1:
case ARIZONA_HEADPHONE_DETECT_1:
case ARIZONA_HEADPHONE_DETECT_2:
case ARIZONA_MICD_CLAMP_CONTROL:
case ARIZONA_MIC_DETECT_1:
case ARIZONA_MIC_DETECT_2:
case ARIZONA_MIC_DETECT_3:
case ARIZONA_MIC_DETECT_4:
case ARIZONA_MIC_DETECT_LEVEL_1:
case ARIZONA_MIC_DETECT_LEVEL_2:
case ARIZONA_MIC_DETECT_LEVEL_3:
case ARIZONA_MIC_DETECT_LEVEL_4:
case ARIZONA_MIC_NOISE_MIX_CONTROL_1:
case ARIZONA_ISOLATION_CONTROL:
case ARIZONA_JACK_DETECT_ANALOGUE:
case ARIZONA_INPUT_ENABLES:
case ARIZONA_INPUT_ENABLES_STATUS:
case ARIZONA_INPUT_RATE:
case ARIZONA_INPUT_VOLUME_RAMP:
case ARIZONA_HPF_CONTROL:
case ARIZONA_IN1L_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_1L:
case ARIZONA_DMIC1L_CONTROL:
case ARIZONA_IN1R_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_1R:
case ARIZONA_DMIC1R_CONTROL:
case ARIZONA_IN2L_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_2L:
case ARIZONA_DMIC2L_CONTROL:
case ARIZONA_IN2R_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_2R:
case ARIZONA_DMIC2R_CONTROL:
case ARIZONA_IN3L_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_3L:
case ARIZONA_DMIC3L_CONTROL:
case ARIZONA_IN3R_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_3R:
case ARIZONA_DMIC3R_CONTROL:
case ARIZONA_IN4L_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_4L:
case ARIZONA_DMIC4L_CONTROL:
case ARIZONA_IN4R_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_4R:
case ARIZONA_DMIC4R_CONTROL:
case ARIZONA_OUTPUT_ENABLES_1:
case ARIZONA_OUTPUT_STATUS_1:
case ARIZONA_RAW_OUTPUT_STATUS_1:
case ARIZONA_OUTPUT_RATE_1:
case ARIZONA_OUTPUT_VOLUME_RAMP:
case ARIZONA_OUTPUT_PATH_CONFIG_1L:
case ARIZONA_DAC_DIGITAL_VOLUME_1L:
case ARIZONA_DAC_VOLUME_LIMIT_1L:
case ARIZONA_NOISE_GATE_SELECT_1L:
case ARIZONA_OUTPUT_PATH_CONFIG_1R:
case ARIZONA_DAC_DIGITAL_VOLUME_1R:
case ARIZONA_DAC_VOLUME_LIMIT_1R:
case ARIZONA_NOISE_GATE_SELECT_1R:
case ARIZONA_OUTPUT_PATH_CONFIG_2L:
case ARIZONA_DAC_DIGITAL_VOLUME_2L:
case ARIZONA_DAC_VOLUME_LIMIT_2L:
case ARIZONA_NOISE_GATE_SELECT_2L:
case ARIZONA_OUTPUT_PATH_CONFIG_2R:
case ARIZONA_DAC_DIGITAL_VOLUME_2R:
case ARIZONA_DAC_VOLUME_LIMIT_2R:
case ARIZONA_NOISE_GATE_SELECT_2R:
case ARIZONA_OUTPUT_PATH_CONFIG_3L:
case ARIZONA_DAC_DIGITAL_VOLUME_3L:
case ARIZONA_DAC_VOLUME_LIMIT_3L:
case ARIZONA_NOISE_GATE_SELECT_3L:
case ARIZONA_OUTPUT_PATH_CONFIG_3R:
case ARIZONA_DAC_DIGITAL_VOLUME_3R:
case ARIZONA_DAC_VOLUME_LIMIT_3R:
case ARIZONA_NOISE_GATE_SELECT_3R:
case ARIZONA_OUTPUT_PATH_CONFIG_4L:
case ARIZONA_DAC_DIGITAL_VOLUME_4L:
case ARIZONA_OUT_VOLUME_4L:
case ARIZONA_NOISE_GATE_SELECT_4L:
case ARIZONA_OUTPUT_PATH_CONFIG_4R:
case ARIZONA_DAC_DIGITAL_VOLUME_4R:
case ARIZONA_OUT_VOLUME_4R:
case ARIZONA_NOISE_GATE_SELECT_4R:
case ARIZONA_OUTPUT_PATH_CONFIG_5L:
case ARIZONA_DAC_DIGITAL_VOLUME_5L:
case ARIZONA_DAC_VOLUME_LIMIT_5L:
case ARIZONA_NOISE_GATE_SELECT_5L:
case ARIZONA_OUTPUT_PATH_CONFIG_5R:
case ARIZONA_DAC_DIGITAL_VOLUME_5R:
case ARIZONA_DAC_VOLUME_LIMIT_5R:
case ARIZONA_NOISE_GATE_SELECT_5R:
case ARIZONA_OUTPUT_PATH_CONFIG_6L:
case ARIZONA_DAC_DIGITAL_VOLUME_6L:
case ARIZONA_DAC_VOLUME_LIMIT_6L:
case ARIZONA_NOISE_GATE_SELECT_6L:
case ARIZONA_OUTPUT_PATH_CONFIG_6R:
case ARIZONA_DAC_DIGITAL_VOLUME_6R:
case ARIZONA_DAC_VOLUME_LIMIT_6R:
case ARIZONA_NOISE_GATE_SELECT_6R:
case ARIZONA_DRE_ENABLE:
case ARIZONA_DAC_AEC_CONTROL_1:
case ARIZONA_NOISE_GATE_CONTROL:
case ARIZONA_PDM_SPK1_CTRL_1:
case ARIZONA_PDM_SPK1_CTRL_2:
case ARIZONA_PDM_SPK2_CTRL_1:
case ARIZONA_PDM_SPK2_CTRL_2:
case ARIZONA_HP1_SHORT_CIRCUIT_CTRL:
case ARIZONA_HP2_SHORT_CIRCUIT_CTRL:
case ARIZONA_HP3_SHORT_CIRCUIT_CTRL:
case ARIZONA_HP_TEST_CTRL_1:
case ARIZONA_AIF1_BCLK_CTRL:
case ARIZONA_AIF1_TX_PIN_CTRL:
case ARIZONA_AIF1_RX_PIN_CTRL:
case ARIZONA_AIF1_RATE_CTRL:
case ARIZONA_AIF1_FORMAT:
case ARIZONA_AIF1_TX_BCLK_RATE:
case ARIZONA_AIF1_RX_BCLK_RATE:
case ARIZONA_AIF1_FRAME_CTRL_1:
case ARIZONA_AIF1_FRAME_CTRL_2:
case ARIZONA_AIF1_FRAME_CTRL_3:
case ARIZONA_AIF1_FRAME_CTRL_4:
case ARIZONA_AIF1_FRAME_CTRL_5:
case ARIZONA_AIF1_FRAME_CTRL_6:
case ARIZONA_AIF1_FRAME_CTRL_7:
case ARIZONA_AIF1_FRAME_CTRL_8:
case ARIZONA_AIF1_FRAME_CTRL_9:
case ARIZONA_AIF1_FRAME_CTRL_10:
case ARIZONA_AIF1_FRAME_CTRL_11:
case ARIZONA_AIF1_FRAME_CTRL_12:
case ARIZONA_AIF1_FRAME_CTRL_13:
case ARIZONA_AIF1_FRAME_CTRL_14:
case ARIZONA_AIF1_FRAME_CTRL_15:
case ARIZONA_AIF1_FRAME_CTRL_16:
case ARIZONA_AIF1_FRAME_CTRL_17:
case ARIZONA_AIF1_FRAME_CTRL_18:
case ARIZONA_AIF1_TX_ENABLES:
case ARIZONA_AIF1_RX_ENABLES:
case ARIZONA_AIF2_BCLK_CTRL:
case ARIZONA_AIF2_TX_PIN_CTRL:
case ARIZONA_AIF2_RX_PIN_CTRL:
case ARIZONA_AIF2_RATE_CTRL:
case ARIZONA_AIF2_FORMAT:
case ARIZONA_AIF2_TX_BCLK_RATE:
case ARIZONA_AIF2_RX_BCLK_RATE:
case ARIZONA_AIF2_FRAME_CTRL_1:
case ARIZONA_AIF2_FRAME_CTRL_2:
case ARIZONA_AIF2_FRAME_CTRL_3:
case ARIZONA_AIF2_FRAME_CTRL_4:
case ARIZONA_AIF2_FRAME_CTRL_5:
case ARIZONA_AIF2_FRAME_CTRL_6:
case ARIZONA_AIF2_FRAME_CTRL_7:
case ARIZONA_AIF2_FRAME_CTRL_8:
case ARIZONA_AIF2_FRAME_CTRL_11:
case ARIZONA_AIF2_FRAME_CTRL_12:
case ARIZONA_AIF2_FRAME_CTRL_13:
case ARIZONA_AIF2_FRAME_CTRL_14:
case ARIZONA_AIF2_FRAME_CTRL_15:
case ARIZONA_AIF2_FRAME_CTRL_16:
case ARIZONA_AIF2_TX_ENABLES:
case ARIZONA_AIF2_RX_ENABLES:
case ARIZONA_AIF3_BCLK_CTRL:
case ARIZONA_AIF3_TX_PIN_CTRL:
case ARIZONA_AIF3_RX_PIN_CTRL:
case ARIZONA_AIF3_RATE_CTRL:
case ARIZONA_AIF3_FORMAT:
case ARIZONA_AIF3_TX_BCLK_RATE:
case ARIZONA_AIF3_RX_BCLK_RATE:
case ARIZONA_AIF3_FRAME_CTRL_1:
case ARIZONA_AIF3_FRAME_CTRL_2:
case ARIZONA_AIF3_FRAME_CTRL_3:
case ARIZONA_AIF3_FRAME_CTRL_4:
case ARIZONA_AIF3_FRAME_CTRL_11:
case ARIZONA_AIF3_FRAME_CTRL_12:
case ARIZONA_AIF3_TX_ENABLES:
case ARIZONA_AIF3_RX_ENABLES:
case ARIZONA_SLIMBUS_FRAMER_REF_GEAR:
case ARIZONA_SLIMBUS_RATES_1:
case ARIZONA_SLIMBUS_RATES_2:
case ARIZONA_SLIMBUS_RATES_3:
case ARIZONA_SLIMBUS_RATES_4:
case ARIZONA_SLIMBUS_RATES_5:
case ARIZONA_SLIMBUS_RATES_6:
case ARIZONA_SLIMBUS_RATES_7:
case ARIZONA_SLIMBUS_RATES_8:
case ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE:
case ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE:
case ARIZONA_SLIMBUS_RX_PORT_STATUS:
case ARIZONA_SLIMBUS_TX_PORT_STATUS:
case ARIZONA_PWM1MIX_INPUT_1_SOURCE:
case ARIZONA_PWM1MIX_INPUT_1_VOLUME:
case ARIZONA_PWM1MIX_INPUT_2_SOURCE:
case ARIZONA_PWM1MIX_INPUT_2_VOLUME:
case ARIZONA_PWM1MIX_INPUT_3_SOURCE:
case ARIZONA_PWM1MIX_INPUT_3_VOLUME:
case ARIZONA_PWM1MIX_INPUT_4_SOURCE:
case ARIZONA_PWM1MIX_INPUT_4_VOLUME:
case ARIZONA_PWM2MIX_INPUT_1_SOURCE:
case ARIZONA_PWM2MIX_INPUT_1_VOLUME:
case ARIZONA_PWM2MIX_INPUT_2_SOURCE:
case ARIZONA_PWM2MIX_INPUT_2_VOLUME:
case ARIZONA_PWM2MIX_INPUT_3_SOURCE:
case ARIZONA_PWM2MIX_INPUT_3_VOLUME:
case ARIZONA_PWM2MIX_INPUT_4_SOURCE:
case ARIZONA_PWM2MIX_INPUT_4_VOLUME:
case ARIZONA_MICMIX_INPUT_1_SOURCE:
case ARIZONA_MICMIX_INPUT_1_VOLUME:
case ARIZONA_MICMIX_INPUT_2_SOURCE:
case ARIZONA_MICMIX_INPUT_2_VOLUME:
case ARIZONA_MICMIX_INPUT_3_SOURCE:
case ARIZONA_MICMIX_INPUT_3_VOLUME:
case ARIZONA_MICMIX_INPUT_4_SOURCE:
case ARIZONA_MICMIX_INPUT_4_VOLUME:
case ARIZONA_NOISEMIX_INPUT_1_SOURCE:
case ARIZONA_NOISEMIX_INPUT_1_VOLUME:
case ARIZONA_NOISEMIX_INPUT_2_SOURCE:
case ARIZONA_NOISEMIX_INPUT_2_VOLUME:
case ARIZONA_NOISEMIX_INPUT_3_SOURCE:
case ARIZONA_NOISEMIX_INPUT_3_VOLUME:
case ARIZONA_NOISEMIX_INPUT_4_SOURCE:
case ARIZONA_NOISEMIX_INPUT_4_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_4_VOLUME:
case ARIZONA_OUT2LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT2LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT2LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT2LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT2LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT2LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT2LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT2LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT2RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT2RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT2RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT2RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT2RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT2RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT2RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT2RMIX_INPUT_4_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT3RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT3RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT3RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT3RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT3RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT3RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT3RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT3RMIX_INPUT_4_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT4RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT4RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT4RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT4RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT4RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT4RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT4RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT4RMIX_INPUT_4_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_4_VOLUME:
case ARIZONA_OUT6LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT6LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT6LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT6LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT6LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT6LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT6LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT6LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT6RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT6RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT6RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT6RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT6RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT6RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT6RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT6RMIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME:
case ARIZONA_EQ1MIX_INPUT_1_SOURCE:
case ARIZONA_EQ1MIX_INPUT_1_VOLUME:
case ARIZONA_EQ1MIX_INPUT_2_SOURCE:
case ARIZONA_EQ1MIX_INPUT_2_VOLUME:
case ARIZONA_EQ1MIX_INPUT_3_SOURCE:
case ARIZONA_EQ1MIX_INPUT_3_VOLUME:
case ARIZONA_EQ1MIX_INPUT_4_SOURCE:
case ARIZONA_EQ1MIX_INPUT_4_VOLUME:
case ARIZONA_EQ2MIX_INPUT_1_SOURCE:
case ARIZONA_EQ2MIX_INPUT_1_VOLUME:
case ARIZONA_EQ2MIX_INPUT_2_SOURCE:
case ARIZONA_EQ2MIX_INPUT_2_VOLUME:
case ARIZONA_EQ2MIX_INPUT_3_SOURCE:
case ARIZONA_EQ2MIX_INPUT_3_VOLUME:
case ARIZONA_EQ2MIX_INPUT_4_SOURCE:
case ARIZONA_EQ2MIX_INPUT_4_VOLUME:
case ARIZONA_EQ3MIX_INPUT_1_SOURCE:
case ARIZONA_EQ3MIX_INPUT_1_VOLUME:
case ARIZONA_EQ3MIX_INPUT_2_SOURCE:
case ARIZONA_EQ3MIX_INPUT_2_VOLUME:
case ARIZONA_EQ3MIX_INPUT_3_SOURCE:
case ARIZONA_EQ3MIX_INPUT_3_VOLUME:
case ARIZONA_EQ3MIX_INPUT_4_SOURCE:
case ARIZONA_EQ3MIX_INPUT_4_VOLUME:
case ARIZONA_EQ4MIX_INPUT_1_SOURCE:
case ARIZONA_EQ4MIX_INPUT_1_VOLUME:
case ARIZONA_EQ4MIX_INPUT_2_SOURCE:
case ARIZONA_EQ4MIX_INPUT_2_VOLUME:
case ARIZONA_EQ4MIX_INPUT_3_SOURCE:
case ARIZONA_EQ4MIX_INPUT_3_VOLUME:
case ARIZONA_EQ4MIX_INPUT_4_SOURCE:
case ARIZONA_EQ4MIX_INPUT_4_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_1_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_1_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_2_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_2_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_3_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_3_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_4_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_4_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_1_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_1_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_2_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_2_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_3_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_3_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_4_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_4_VOLUME:
case ARIZONA_DRC2LMIX_INPUT_1_SOURCE:
case ARIZONA_DRC2LMIX_INPUT_1_VOLUME:
case ARIZONA_DRC2LMIX_INPUT_2_SOURCE:
case ARIZONA_DRC2LMIX_INPUT_2_VOLUME:
case ARIZONA_DRC2LMIX_INPUT_3_SOURCE:
case ARIZONA_DRC2LMIX_INPUT_3_VOLUME:
case ARIZONA_DRC2LMIX_INPUT_4_SOURCE:
case ARIZONA_DRC2LMIX_INPUT_4_VOLUME:
case ARIZONA_DRC2RMIX_INPUT_1_SOURCE:
case ARIZONA_DRC2RMIX_INPUT_1_VOLUME:
case ARIZONA_DRC2RMIX_INPUT_2_SOURCE:
case ARIZONA_DRC2RMIX_INPUT_2_VOLUME:
case ARIZONA_DRC2RMIX_INPUT_3_SOURCE:
case ARIZONA_DRC2RMIX_INPUT_3_VOLUME:
case ARIZONA_DRC2RMIX_INPUT_4_SOURCE:
case ARIZONA_DRC2RMIX_INPUT_4_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_4_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_4_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_4_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_4_VOLUME:
case ARIZONA_DSP1LMIX_INPUT_1_SOURCE:
case ARIZONA_DSP1LMIX_INPUT_1_VOLUME:
case ARIZONA_DSP1LMIX_INPUT_2_SOURCE:
case ARIZONA_DSP1LMIX_INPUT_2_VOLUME:
case ARIZONA_DSP1LMIX_INPUT_3_SOURCE:
case ARIZONA_DSP1LMIX_INPUT_3_VOLUME:
case ARIZONA_DSP1LMIX_INPUT_4_SOURCE:
case ARIZONA_DSP1LMIX_INPUT_4_VOLUME:
case ARIZONA_DSP1RMIX_INPUT_1_SOURCE:
case ARIZONA_DSP1RMIX_INPUT_1_VOLUME:
case ARIZONA_DSP1RMIX_INPUT_2_SOURCE:
case ARIZONA_DSP1RMIX_INPUT_2_VOLUME:
case ARIZONA_DSP1RMIX_INPUT_3_SOURCE:
case ARIZONA_DSP1RMIX_INPUT_3_VOLUME:
case ARIZONA_DSP1RMIX_INPUT_4_SOURCE:
case ARIZONA_DSP1RMIX_INPUT_4_VOLUME:
case ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE:
case ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE:
case ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE:
case ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE:
case ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE:
case ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE:
case ARIZONA_DSP2LMIX_INPUT_1_SOURCE:
case ARIZONA_DSP2LMIX_INPUT_1_VOLUME:
case ARIZONA_DSP2LMIX_INPUT_2_SOURCE:
case ARIZONA_DSP2LMIX_INPUT_2_VOLUME:
case ARIZONA_DSP2LMIX_INPUT_3_SOURCE:
case ARIZONA_DSP2LMIX_INPUT_3_VOLUME:
case ARIZONA_DSP2LMIX_INPUT_4_SOURCE:
case ARIZONA_DSP2LMIX_INPUT_4_VOLUME:
case ARIZONA_DSP2RMIX_INPUT_1_SOURCE:
case ARIZONA_DSP2RMIX_INPUT_1_VOLUME:
case ARIZONA_DSP2RMIX_INPUT_2_SOURCE:
case ARIZONA_DSP2RMIX_INPUT_2_VOLUME:
case ARIZONA_DSP2RMIX_INPUT_3_SOURCE:
case ARIZONA_DSP2RMIX_INPUT_3_VOLUME:
case ARIZONA_DSP2RMIX_INPUT_4_SOURCE:
case ARIZONA_DSP2RMIX_INPUT_4_VOLUME:
case ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE:
case ARIZONA_DSP2AUX2MIX_INPUT_1_SOURCE:
case ARIZONA_DSP2AUX3MIX_INPUT_1_SOURCE:
case ARIZONA_DSP2AUX4MIX_INPUT_1_SOURCE:
case ARIZONA_DSP2AUX5MIX_INPUT_1_SOURCE:
case ARIZONA_DSP2AUX6MIX_INPUT_1_SOURCE:
case ARIZONA_DSP3LMIX_INPUT_1_SOURCE:
case ARIZONA_DSP3LMIX_INPUT_1_VOLUME:
case ARIZONA_DSP3LMIX_INPUT_2_SOURCE:
case ARIZONA_DSP3LMIX_INPUT_2_VOLUME:
case ARIZONA_DSP3LMIX_INPUT_3_SOURCE:
case ARIZONA_DSP3LMIX_INPUT_3_VOLUME:
case ARIZONA_DSP3LMIX_INPUT_4_SOURCE:
case ARIZONA_DSP3LMIX_INPUT_4_VOLUME:
case ARIZONA_DSP3RMIX_INPUT_1_SOURCE:
case ARIZONA_DSP3RMIX_INPUT_1_VOLUME:
case ARIZONA_DSP3RMIX_INPUT_2_SOURCE:
case ARIZONA_DSP3RMIX_INPUT_2_VOLUME:
case ARIZONA_DSP3RMIX_INPUT_3_SOURCE:
case ARIZONA_DSP3RMIX_INPUT_3_VOLUME:
case ARIZONA_DSP3RMIX_INPUT_4_SOURCE:
case ARIZONA_DSP3RMIX_INPUT_4_VOLUME:
case ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE:
case ARIZONA_DSP3AUX2MIX_INPUT_1_SOURCE:
case ARIZONA_DSP3AUX3MIX_INPUT_1_SOURCE:
case ARIZONA_DSP3AUX4MIX_INPUT_1_SOURCE:
case ARIZONA_DSP3AUX5MIX_INPUT_1_SOURCE:
case ARIZONA_DSP3AUX6MIX_INPUT_1_SOURCE:
case ARIZONA_DSP4LMIX_INPUT_1_SOURCE:
case ARIZONA_DSP4LMIX_INPUT_1_VOLUME:
case ARIZONA_DSP4LMIX_INPUT_2_SOURCE:
case ARIZONA_DSP4LMIX_INPUT_2_VOLUME:
case ARIZONA_DSP4LMIX_INPUT_3_SOURCE:
case ARIZONA_DSP4LMIX_INPUT_3_VOLUME:
case ARIZONA_DSP4LMIX_INPUT_4_SOURCE:
case ARIZONA_DSP4LMIX_INPUT_4_VOLUME:
case ARIZONA_DSP4RMIX_INPUT_1_SOURCE:
case ARIZONA_DSP4RMIX_INPUT_1_VOLUME:
case ARIZONA_DSP4RMIX_INPUT_2_SOURCE:
case ARIZONA_DSP4RMIX_INPUT_2_VOLUME:
case ARIZONA_DSP4RMIX_INPUT_3_SOURCE:
case ARIZONA_DSP4RMIX_INPUT_3_VOLUME:
case ARIZONA_DSP4RMIX_INPUT_4_SOURCE:
case ARIZONA_DSP4RMIX_INPUT_4_VOLUME:
case ARIZONA_DSP4AUX1MIX_INPUT_1_SOURCE:
case ARIZONA_DSP4AUX2MIX_INPUT_1_SOURCE:
case ARIZONA_DSP4AUX3MIX_INPUT_1_SOURCE:
case ARIZONA_DSP4AUX4MIX_INPUT_1_SOURCE:
case ARIZONA_DSP4AUX5MIX_INPUT_1_SOURCE:
case ARIZONA_DSP4AUX6MIX_INPUT_1_SOURCE:
case ARIZONA_ASRC1LMIX_INPUT_1_SOURCE:
case ARIZONA_ASRC1RMIX_INPUT_1_SOURCE:
case ARIZONA_ASRC2LMIX_INPUT_1_SOURCE:
case ARIZONA_ASRC2RMIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3DEC3MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3DEC4MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3INT3MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3INT4MIX_INPUT_1_SOURCE:
case ARIZONA_GPIO1_CTRL:
case ARIZONA_GPIO2_CTRL:
case ARIZONA_GPIO3_CTRL:
case ARIZONA_GPIO4_CTRL:
case ARIZONA_GPIO5_CTRL:
case ARIZONA_IRQ_CTRL_1:
case ARIZONA_GPIO_DEBOUNCE_CONFIG:
case ARIZONA_GP_SWITCH_1:
case ARIZONA_MISC_PAD_CTRL_1:
case ARIZONA_MISC_PAD_CTRL_2:
case ARIZONA_MISC_PAD_CTRL_3:
case ARIZONA_MISC_PAD_CTRL_4:
case ARIZONA_MISC_PAD_CTRL_5:
case ARIZONA_MISC_PAD_CTRL_6:
case ARIZONA_MISC_PAD_CTRL_7:
case ARIZONA_MISC_PAD_CTRL_8:
case ARIZONA_MISC_PAD_CTRL_9:
case ARIZONA_MISC_PAD_CTRL_10:
case ARIZONA_MISC_PAD_CTRL_11:
case ARIZONA_MISC_PAD_CTRL_12:
case ARIZONA_MISC_PAD_CTRL_13:
case ARIZONA_MISC_PAD_CTRL_14:
case ARIZONA_MISC_PAD_CTRL_15:
case ARIZONA_MISC_PAD_CTRL_16:
case ARIZONA_MISC_PAD_CTRL_17:
case ARIZONA_MISC_PAD_CTRL_18:
case ARIZONA_INTERRUPT_STATUS_1:
case ARIZONA_INTERRUPT_STATUS_2:
case ARIZONA_INTERRUPT_STATUS_3:
case ARIZONA_INTERRUPT_STATUS_4:
case ARIZONA_INTERRUPT_STATUS_5:
case ARIZONA_INTERRUPT_STATUS_6:
case ARIZONA_INTERRUPT_STATUS_1_MASK:
case ARIZONA_INTERRUPT_STATUS_2_MASK:
case ARIZONA_INTERRUPT_STATUS_3_MASK:
case ARIZONA_INTERRUPT_STATUS_4_MASK:
case ARIZONA_INTERRUPT_STATUS_5_MASK:
case ARIZONA_INTERRUPT_STATUS_6_MASK:
case ARIZONA_INTERRUPT_CONTROL:
case ARIZONA_IRQ2_STATUS_1:
case ARIZONA_IRQ2_STATUS_2:
case ARIZONA_IRQ2_STATUS_3:
case ARIZONA_IRQ2_STATUS_4:
case ARIZONA_IRQ2_STATUS_5:
case ARIZONA_IRQ2_STATUS_6:
case ARIZONA_IRQ2_STATUS_1_MASK:
case ARIZONA_IRQ2_STATUS_2_MASK:
case ARIZONA_IRQ2_STATUS_3_MASK:
case ARIZONA_IRQ2_STATUS_4_MASK:
case ARIZONA_IRQ2_STATUS_5_MASK:
case ARIZONA_IRQ2_STATUS_6_MASK:
case ARIZONA_IRQ2_CONTROL:
case ARIZONA_INTERRUPT_RAW_STATUS_2:
case ARIZONA_INTERRUPT_RAW_STATUS_3:
case ARIZONA_INTERRUPT_RAW_STATUS_4:
case ARIZONA_INTERRUPT_RAW_STATUS_5:
case ARIZONA_INTERRUPT_RAW_STATUS_6:
case ARIZONA_INTERRUPT_RAW_STATUS_7:
case ARIZONA_INTERRUPT_RAW_STATUS_8:
case ARIZONA_INTERRUPT_RAW_STATUS_9:
case ARIZONA_IRQ_PIN_STATUS:
case ARIZONA_AOD_WKUP_AND_TRIG:
case ARIZONA_AOD_IRQ1:
case ARIZONA_AOD_IRQ2:
case ARIZONA_AOD_IRQ_MASK_IRQ1:
case ARIZONA_AOD_IRQ_MASK_IRQ2:
case ARIZONA_AOD_IRQ_RAW_STATUS:
case ARIZONA_JACK_DETECT_DEBOUNCE:
case ARIZONA_FX_CTRL1:
case ARIZONA_FX_CTRL2:
case ARIZONA_EQ1_1:
case ARIZONA_EQ1_2:
case ARIZONA_EQ1_3:
case ARIZONA_EQ1_4:
case ARIZONA_EQ1_5:
case ARIZONA_EQ1_6:
case ARIZONA_EQ1_7:
case ARIZONA_EQ1_8:
case ARIZONA_EQ1_9:
case ARIZONA_EQ1_10:
case ARIZONA_EQ1_11:
case ARIZONA_EQ1_12:
case ARIZONA_EQ1_13:
case ARIZONA_EQ1_14:
case ARIZONA_EQ1_15:
case ARIZONA_EQ1_16:
case ARIZONA_EQ1_17:
case ARIZONA_EQ1_18:
case ARIZONA_EQ1_19:
case ARIZONA_EQ1_20:
case ARIZONA_EQ1_21:
case ARIZONA_EQ2_1:
case ARIZONA_EQ2_2:
case ARIZONA_EQ2_3:
case ARIZONA_EQ2_4:
case ARIZONA_EQ2_5:
case ARIZONA_EQ2_6:
case ARIZONA_EQ2_7:
case ARIZONA_EQ2_8:
case ARIZONA_EQ2_9:
case ARIZONA_EQ2_10:
case ARIZONA_EQ2_11:
case ARIZONA_EQ2_12:
case ARIZONA_EQ2_13:
case ARIZONA_EQ2_14:
case ARIZONA_EQ2_15:
case ARIZONA_EQ2_16:
case ARIZONA_EQ2_17:
case ARIZONA_EQ2_18:
case ARIZONA_EQ2_19:
case ARIZONA_EQ2_20:
case ARIZONA_EQ2_21:
case ARIZONA_EQ3_1:
case ARIZONA_EQ3_2:
case ARIZONA_EQ3_3:
case ARIZONA_EQ3_4:
case ARIZONA_EQ3_5:
case ARIZONA_EQ3_6:
case ARIZONA_EQ3_7:
case ARIZONA_EQ3_8:
case ARIZONA_EQ3_9:
case ARIZONA_EQ3_10:
case ARIZONA_EQ3_11:
case ARIZONA_EQ3_12:
case ARIZONA_EQ3_13:
case ARIZONA_EQ3_14:
case ARIZONA_EQ3_15:
case ARIZONA_EQ3_16:
case ARIZONA_EQ3_17:
case ARIZONA_EQ3_18:
case ARIZONA_EQ3_19:
case ARIZONA_EQ3_20:
case ARIZONA_EQ3_21:
case ARIZONA_EQ4_1:
case ARIZONA_EQ4_2:
case ARIZONA_EQ4_3:
case ARIZONA_EQ4_4:
case ARIZONA_EQ4_5:
case ARIZONA_EQ4_6:
case ARIZONA_EQ4_7:
case ARIZONA_EQ4_8:
case ARIZONA_EQ4_9:
case ARIZONA_EQ4_10:
case ARIZONA_EQ4_11:
case ARIZONA_EQ4_12:
case ARIZONA_EQ4_13:
case ARIZONA_EQ4_14:
case ARIZONA_EQ4_15:
case ARIZONA_EQ4_16:
case ARIZONA_EQ4_17:
case ARIZONA_EQ4_18:
case ARIZONA_EQ4_19:
case ARIZONA_EQ4_20:
case ARIZONA_EQ4_21:
case ARIZONA_DRC1_CTRL1:
case ARIZONA_DRC1_CTRL2:
case ARIZONA_DRC1_CTRL3:
case ARIZONA_DRC1_CTRL4:
case ARIZONA_DRC1_CTRL5:
case ARIZONA_DRC2_CTRL1:
case ARIZONA_DRC2_CTRL2:
case ARIZONA_DRC2_CTRL3:
case ARIZONA_DRC2_CTRL4:
case ARIZONA_DRC2_CTRL5:
case ARIZONA_HPLPF1_1:
case ARIZONA_HPLPF1_2:
case ARIZONA_HPLPF2_1:
case ARIZONA_HPLPF2_2:
case ARIZONA_HPLPF3_1:
case ARIZONA_HPLPF3_2:
case ARIZONA_HPLPF4_1:
case ARIZONA_HPLPF4_2:
case ARIZONA_ASRC_ENABLE:
case ARIZONA_ASRC_STATUS:
case ARIZONA_ASRC_RATE1:
case ARIZONA_ASRC_RATE2:
case ARIZONA_ISRC_1_CTRL_1:
case ARIZONA_ISRC_1_CTRL_2:
case ARIZONA_ISRC_1_CTRL_3:
case ARIZONA_ISRC_2_CTRL_1:
case ARIZONA_ISRC_2_CTRL_2:
case ARIZONA_ISRC_2_CTRL_3:
case ARIZONA_ISRC_3_CTRL_1:
case ARIZONA_ISRC_3_CTRL_2:
case ARIZONA_ISRC_3_CTRL_3:
case ARIZONA_CLOCK_CONTROL:
case ARIZONA_ANC_SRC:
case ARIZONA_DSP_STATUS:
case ARIZONA_ANC_COEFF_START ... ARIZONA_ANC_COEFF_END:
case ARIZONA_FCL_FILTER_CONTROL:
case ARIZONA_FCL_ADC_REFORMATTER_CONTROL:
case ARIZONA_FCL_COEFF_START ... ARIZONA_FCL_COEFF_END:
case ARIZONA_FCR_FILTER_CONTROL:
case ARIZONA_FCR_ADC_REFORMATTER_CONTROL:
case ARIZONA_FCR_COEFF_START ... ARIZONA_FCR_COEFF_END:
case ARIZONA_DSP1_CONTROL_1:
case ARIZONA_DSP1_CLOCKING_1:
case ARIZONA_DSP1_STATUS_1:
case ARIZONA_DSP1_STATUS_2:
case ARIZONA_DSP1_STATUS_3:
case ARIZONA_DSP1_STATUS_4:
case ARIZONA_DSP1_WDMA_BUFFER_1:
case ARIZONA_DSP1_WDMA_BUFFER_2:
case ARIZONA_DSP1_WDMA_BUFFER_3:
case ARIZONA_DSP1_WDMA_BUFFER_4:
case ARIZONA_DSP1_WDMA_BUFFER_5:
case ARIZONA_DSP1_WDMA_BUFFER_6:
case ARIZONA_DSP1_WDMA_BUFFER_7:
case ARIZONA_DSP1_WDMA_BUFFER_8:
case ARIZONA_DSP1_RDMA_BUFFER_1:
case ARIZONA_DSP1_RDMA_BUFFER_2:
case ARIZONA_DSP1_RDMA_BUFFER_3:
case ARIZONA_DSP1_RDMA_BUFFER_4:
case ARIZONA_DSP1_RDMA_BUFFER_5:
case ARIZONA_DSP1_RDMA_BUFFER_6:
case ARIZONA_DSP1_WDMA_CONFIG_1:
case ARIZONA_DSP1_WDMA_CONFIG_2:
case ARIZONA_DSP1_WDMA_OFFSET_1:
case ARIZONA_DSP1_RDMA_CONFIG_1:
case ARIZONA_DSP1_RDMA_OFFSET_1:
case ARIZONA_DSP1_EXTERNAL_START_SELECT_1:
case ARIZONA_DSP1_SCRATCH_0:
case ARIZONA_DSP1_SCRATCH_1:
case ARIZONA_DSP1_SCRATCH_2:
case ARIZONA_DSP1_SCRATCH_3:
case ARIZONA_DSP2_CONTROL_1:
case ARIZONA_DSP2_CLOCKING_1:
case ARIZONA_DSP2_STATUS_1:
case ARIZONA_DSP2_STATUS_2:
case ARIZONA_DSP2_STATUS_3:
case ARIZONA_DSP2_STATUS_4:
case ARIZONA_DSP2_WDMA_BUFFER_1:
case ARIZONA_DSP2_WDMA_BUFFER_2:
case ARIZONA_DSP2_WDMA_BUFFER_3:
case ARIZONA_DSP2_WDMA_BUFFER_4:
case ARIZONA_DSP2_WDMA_BUFFER_5:
case ARIZONA_DSP2_WDMA_BUFFER_6:
case ARIZONA_DSP2_WDMA_BUFFER_7:
case ARIZONA_DSP2_WDMA_BUFFER_8:
case ARIZONA_DSP2_RDMA_BUFFER_1:
case ARIZONA_DSP2_RDMA_BUFFER_2:
case ARIZONA_DSP2_RDMA_BUFFER_3:
case ARIZONA_DSP2_RDMA_BUFFER_4:
case ARIZONA_DSP2_RDMA_BUFFER_5:
case ARIZONA_DSP2_RDMA_BUFFER_6:
case ARIZONA_DSP2_WDMA_CONFIG_1:
case ARIZONA_DSP2_WDMA_CONFIG_2:
case ARIZONA_DSP2_WDMA_OFFSET_1:
case ARIZONA_DSP2_RDMA_CONFIG_1:
case ARIZONA_DSP2_RDMA_OFFSET_1:
case ARIZONA_DSP2_EXTERNAL_START_SELECT_1:
case ARIZONA_DSP2_SCRATCH_0:
case ARIZONA_DSP2_SCRATCH_1:
case ARIZONA_DSP2_SCRATCH_2:
case ARIZONA_DSP2_SCRATCH_3:
case ARIZONA_DSP3_CONTROL_1:
case ARIZONA_DSP3_CLOCKING_1:
case ARIZONA_DSP3_STATUS_1:
case ARIZONA_DSP3_STATUS_2:
case ARIZONA_DSP3_STATUS_3:
case ARIZONA_DSP3_STATUS_4:
case ARIZONA_DSP3_WDMA_BUFFER_1:
case ARIZONA_DSP3_WDMA_BUFFER_2:
case ARIZONA_DSP3_WDMA_BUFFER_3:
case ARIZONA_DSP3_WDMA_BUFFER_4:
case ARIZONA_DSP3_WDMA_BUFFER_5:
case ARIZONA_DSP3_WDMA_BUFFER_6:
case ARIZONA_DSP3_WDMA_BUFFER_7:
case ARIZONA_DSP3_WDMA_BUFFER_8:
case ARIZONA_DSP3_RDMA_BUFFER_1:
case ARIZONA_DSP3_RDMA_BUFFER_2:
case ARIZONA_DSP3_RDMA_BUFFER_3:
case ARIZONA_DSP3_RDMA_BUFFER_4:
case ARIZONA_DSP3_RDMA_BUFFER_5:
case ARIZONA_DSP3_RDMA_BUFFER_6:
case ARIZONA_DSP3_WDMA_CONFIG_1:
case ARIZONA_DSP3_WDMA_CONFIG_2:
case ARIZONA_DSP3_WDMA_OFFSET_1:
case ARIZONA_DSP3_RDMA_CONFIG_1:
case ARIZONA_DSP3_RDMA_OFFSET_1:
case ARIZONA_DSP3_EXTERNAL_START_SELECT_1:
case ARIZONA_DSP3_SCRATCH_0:
case ARIZONA_DSP3_SCRATCH_1:
case ARIZONA_DSP3_SCRATCH_2:
case ARIZONA_DSP3_SCRATCH_3:
case ARIZONA_DSP4_CONTROL_1:
case ARIZONA_DSP4_CLOCKING_1:
case ARIZONA_DSP4_STATUS_1:
case ARIZONA_DSP4_STATUS_2:
case ARIZONA_DSP4_STATUS_3:
case ARIZONA_DSP4_STATUS_4:
case ARIZONA_DSP4_WDMA_BUFFER_1:
case ARIZONA_DSP4_WDMA_BUFFER_2:
case ARIZONA_DSP4_WDMA_BUFFER_3:
case ARIZONA_DSP4_WDMA_BUFFER_4:
case ARIZONA_DSP4_WDMA_BUFFER_5:
case ARIZONA_DSP4_WDMA_BUFFER_6:
case ARIZONA_DSP4_WDMA_BUFFER_7:
case ARIZONA_DSP4_WDMA_BUFFER_8:
case ARIZONA_DSP4_RDMA_BUFFER_1:
case ARIZONA_DSP4_RDMA_BUFFER_2:
case ARIZONA_DSP4_RDMA_BUFFER_3:
case ARIZONA_DSP4_RDMA_BUFFER_4:
case ARIZONA_DSP4_RDMA_BUFFER_5:
case ARIZONA_DSP4_RDMA_BUFFER_6:
case ARIZONA_DSP4_WDMA_CONFIG_1:
case ARIZONA_DSP4_WDMA_CONFIG_2:
case ARIZONA_DSP4_WDMA_OFFSET_1:
case ARIZONA_DSP4_RDMA_CONFIG_1:
case ARIZONA_DSP4_RDMA_OFFSET_1:
case ARIZONA_DSP4_EXTERNAL_START_SELECT_1:
case ARIZONA_DSP4_SCRATCH_0:
case ARIZONA_DSP4_SCRATCH_1:
case ARIZONA_DSP4_SCRATCH_2:
case ARIZONA_DSP4_SCRATCH_3:
return true;
default:
return wm5110_is_adsp_memory(dev, reg);
}
}
static bool wm5110_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case ARIZONA_SOFTWARE_RESET:
case ARIZONA_DEVICE_REVISION:
case ARIZONA_WRITE_SEQUENCER_CTRL_0:
case ARIZONA_WRITE_SEQUENCER_CTRL_1:
case ARIZONA_WRITE_SEQUENCER_CTRL_2:
case ARIZONA_HAPTICS_STATUS:
case ARIZONA_SAMPLE_RATE_1_STATUS:
case ARIZONA_SAMPLE_RATE_2_STATUS:
case ARIZONA_SAMPLE_RATE_3_STATUS:
case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS:
case ARIZONA_MIC_DETECT_3:
case ARIZONA_MIC_DETECT_4:
case ARIZONA_HP_CTRL_1L:
case ARIZONA_HP_CTRL_1R:
case ARIZONA_HEADPHONE_DETECT_2:
case ARIZONA_INPUT_ENABLES_STATUS:
case ARIZONA_OUTPUT_STATUS_1:
case ARIZONA_RAW_OUTPUT_STATUS_1:
case ARIZONA_HP_TEST_CTRL_1:
case ARIZONA_SLIMBUS_RX_PORT_STATUS:
case ARIZONA_SLIMBUS_TX_PORT_STATUS:
case ARIZONA_INTERRUPT_STATUS_1:
case ARIZONA_INTERRUPT_STATUS_2:
case ARIZONA_INTERRUPT_STATUS_3:
case ARIZONA_INTERRUPT_STATUS_4:
case ARIZONA_INTERRUPT_STATUS_5:
case ARIZONA_INTERRUPT_STATUS_6:
case ARIZONA_IRQ2_STATUS_1:
case ARIZONA_IRQ2_STATUS_2:
case ARIZONA_IRQ2_STATUS_3:
case ARIZONA_IRQ2_STATUS_4:
case ARIZONA_IRQ2_STATUS_5:
case ARIZONA_IRQ2_STATUS_6:
case ARIZONA_INTERRUPT_RAW_STATUS_2:
case ARIZONA_INTERRUPT_RAW_STATUS_3:
case ARIZONA_INTERRUPT_RAW_STATUS_4:
case ARIZONA_INTERRUPT_RAW_STATUS_5:
case ARIZONA_INTERRUPT_RAW_STATUS_6:
case ARIZONA_INTERRUPT_RAW_STATUS_7:
case ARIZONA_INTERRUPT_RAW_STATUS_8:
case ARIZONA_INTERRUPT_RAW_STATUS_9:
case ARIZONA_IRQ_PIN_STATUS:
case ARIZONA_AOD_WKUP_AND_TRIG:
case ARIZONA_AOD_IRQ1:
case ARIZONA_AOD_IRQ2:
case ARIZONA_AOD_IRQ_RAW_STATUS:
case ARIZONA_FX_CTRL2:
case ARIZONA_ASRC_STATUS:
case ARIZONA_CLOCK_CONTROL:
case ARIZONA_DSP_STATUS:
case ARIZONA_DSP1_STATUS_1:
case ARIZONA_DSP1_STATUS_2:
case ARIZONA_DSP1_STATUS_3:
case ARIZONA_DSP1_STATUS_4:
case ARIZONA_DSP1_WDMA_BUFFER_1:
case ARIZONA_DSP1_WDMA_BUFFER_2:
case ARIZONA_DSP1_WDMA_BUFFER_3:
case ARIZONA_DSP1_WDMA_BUFFER_4:
case ARIZONA_DSP1_WDMA_BUFFER_5:
case ARIZONA_DSP1_WDMA_BUFFER_6:
case ARIZONA_DSP1_WDMA_BUFFER_7:
case ARIZONA_DSP1_WDMA_BUFFER_8:
case ARIZONA_DSP1_RDMA_BUFFER_1:
case ARIZONA_DSP1_RDMA_BUFFER_2:
case ARIZONA_DSP1_RDMA_BUFFER_3:
case ARIZONA_DSP1_RDMA_BUFFER_4:
case ARIZONA_DSP1_RDMA_BUFFER_5:
case ARIZONA_DSP1_RDMA_BUFFER_6:
case ARIZONA_DSP1_WDMA_CONFIG_1:
case ARIZONA_DSP1_WDMA_CONFIG_2:
case ARIZONA_DSP1_WDMA_OFFSET_1:
case ARIZONA_DSP1_RDMA_CONFIG_1:
case ARIZONA_DSP1_RDMA_OFFSET_1:
case ARIZONA_DSP1_EXTERNAL_START_SELECT_1:
case ARIZONA_DSP1_SCRATCH_0:
case ARIZONA_DSP1_SCRATCH_1:
case ARIZONA_DSP1_SCRATCH_2:
case ARIZONA_DSP1_SCRATCH_3:
case ARIZONA_DSP1_CLOCKING_1:
case ARIZONA_DSP2_STATUS_1:
case ARIZONA_DSP2_STATUS_2:
case ARIZONA_DSP2_STATUS_3:
case ARIZONA_DSP2_STATUS_4:
case ARIZONA_DSP2_WDMA_BUFFER_1:
case ARIZONA_DSP2_WDMA_BUFFER_2:
case ARIZONA_DSP2_WDMA_BUFFER_3:
case ARIZONA_DSP2_WDMA_BUFFER_4:
case ARIZONA_DSP2_WDMA_BUFFER_5:
case ARIZONA_DSP2_WDMA_BUFFER_6:
case ARIZONA_DSP2_WDMA_BUFFER_7:
case ARIZONA_DSP2_WDMA_BUFFER_8:
case ARIZONA_DSP2_RDMA_BUFFER_1:
case ARIZONA_DSP2_RDMA_BUFFER_2:
case ARIZONA_DSP2_RDMA_BUFFER_3:
case ARIZONA_DSP2_RDMA_BUFFER_4:
case ARIZONA_DSP2_RDMA_BUFFER_5:
case ARIZONA_DSP2_RDMA_BUFFER_6:
case ARIZONA_DSP2_WDMA_CONFIG_1:
case ARIZONA_DSP2_WDMA_CONFIG_2:
case ARIZONA_DSP2_WDMA_OFFSET_1:
case ARIZONA_DSP2_RDMA_CONFIG_1:
case ARIZONA_DSP2_RDMA_OFFSET_1:
case ARIZONA_DSP2_EXTERNAL_START_SELECT_1:
case ARIZONA_DSP2_SCRATCH_0:
case ARIZONA_DSP2_SCRATCH_1:
case ARIZONA_DSP2_SCRATCH_2:
case ARIZONA_DSP2_SCRATCH_3:
case ARIZONA_DSP2_CLOCKING_1:
case ARIZONA_DSP3_STATUS_1:
case ARIZONA_DSP3_STATUS_2:
case ARIZONA_DSP3_STATUS_3:
case ARIZONA_DSP3_STATUS_4:
case ARIZONA_DSP3_WDMA_BUFFER_1:
case ARIZONA_DSP3_WDMA_BUFFER_2:
case ARIZONA_DSP3_WDMA_BUFFER_3:
case ARIZONA_DSP3_WDMA_BUFFER_4:
case ARIZONA_DSP3_WDMA_BUFFER_5:
case ARIZONA_DSP3_WDMA_BUFFER_6:
case ARIZONA_DSP3_WDMA_BUFFER_7:
case ARIZONA_DSP3_WDMA_BUFFER_8:
case ARIZONA_DSP3_RDMA_BUFFER_1:
case ARIZONA_DSP3_RDMA_BUFFER_2:
case ARIZONA_DSP3_RDMA_BUFFER_3:
case ARIZONA_DSP3_RDMA_BUFFER_4:
case ARIZONA_DSP3_RDMA_BUFFER_5:
case ARIZONA_DSP3_RDMA_BUFFER_6:
case ARIZONA_DSP3_WDMA_CONFIG_1:
case ARIZONA_DSP3_WDMA_CONFIG_2:
case ARIZONA_DSP3_WDMA_OFFSET_1:
case ARIZONA_DSP3_RDMA_CONFIG_1:
case ARIZONA_DSP3_RDMA_OFFSET_1:
case ARIZONA_DSP3_EXTERNAL_START_SELECT_1:
case ARIZONA_DSP3_SCRATCH_0:
case ARIZONA_DSP3_SCRATCH_1:
case ARIZONA_DSP3_SCRATCH_2:
case ARIZONA_DSP3_SCRATCH_3:
case ARIZONA_DSP3_CLOCKING_1:
case ARIZONA_DSP4_STATUS_1:
case ARIZONA_DSP4_STATUS_2:
case ARIZONA_DSP4_STATUS_3:
case ARIZONA_DSP4_STATUS_4:
case ARIZONA_DSP4_WDMA_BUFFER_1:
case ARIZONA_DSP4_WDMA_BUFFER_2:
case ARIZONA_DSP4_WDMA_BUFFER_3:
case ARIZONA_DSP4_WDMA_BUFFER_4:
case ARIZONA_DSP4_WDMA_BUFFER_5:
case ARIZONA_DSP4_WDMA_BUFFER_6:
case ARIZONA_DSP4_WDMA_BUFFER_7:
case ARIZONA_DSP4_WDMA_BUFFER_8:
case ARIZONA_DSP4_RDMA_BUFFER_1:
case ARIZONA_DSP4_RDMA_BUFFER_2:
case ARIZONA_DSP4_RDMA_BUFFER_3:
case ARIZONA_DSP4_RDMA_BUFFER_4:
case ARIZONA_DSP4_RDMA_BUFFER_5:
case ARIZONA_DSP4_RDMA_BUFFER_6:
case ARIZONA_DSP4_WDMA_CONFIG_1:
case ARIZONA_DSP4_WDMA_CONFIG_2:
case ARIZONA_DSP4_WDMA_OFFSET_1:
case ARIZONA_DSP4_RDMA_CONFIG_1:
case ARIZONA_DSP4_RDMA_OFFSET_1:
case ARIZONA_DSP4_EXTERNAL_START_SELECT_1:
case ARIZONA_DSP4_SCRATCH_0:
case ARIZONA_DSP4_SCRATCH_1:
case ARIZONA_DSP4_SCRATCH_2:
case ARIZONA_DSP4_SCRATCH_3:
case ARIZONA_DSP4_CLOCKING_1:
return true;
default:
return wm5110_is_adsp_memory(dev, reg);
}
}
#define WM5110_MAX_REGISTER 0x4a9fff
const struct regmap_config wm5110_spi_regmap = {
.reg_bits = 32,
.pad_bits = 16,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = WM5110_MAX_REGISTER,
.readable_reg = wm5110_readable_register,
.volatile_reg = wm5110_volatile_register,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = wm5110_reg_default,
.num_reg_defaults = ARRAY_SIZE(wm5110_reg_default),
};
EXPORT_SYMBOL_GPL(wm5110_spi_regmap);
const struct regmap_config wm5110_i2c_regmap = {
.reg_bits = 32,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = WM5110_MAX_REGISTER,
.readable_reg = wm5110_readable_register,
.volatile_reg = wm5110_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm5110_reg_default,
.num_reg_defaults = ARRAY_SIZE(wm5110_reg_default),
};
EXPORT_SYMBOL_GPL(wm5110_i2c_regmap);
| linux-master | drivers/mfd/wm5110-tables.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Device access for Basin Cove PMIC
*
* Copyright (c) 2019, Intel Corporation.
* Author: Andy Shevchenko <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/mfd/intel_soc_pmic_mrfld.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <asm/intel_scu_ipc.h>
/*
* Level 2 IRQs
*
* Firmware on the systems with Basin Cove PMIC services Level 1 IRQs
* without an assistance. Thus, each of the Level 1 IRQ is represented
* as a separate RTE in IOAPIC.
*/
static struct resource irq_level2_resources[] = {
DEFINE_RES_IRQ(0), /* power button */
DEFINE_RES_IRQ(0), /* TMU */
DEFINE_RES_IRQ(0), /* thermal */
DEFINE_RES_IRQ(0), /* BCU */
DEFINE_RES_IRQ(0), /* ADC */
DEFINE_RES_IRQ(0), /* charger */
DEFINE_RES_IRQ(0), /* GPIO */
};
static const struct mfd_cell bcove_dev[] = {
{
.name = "mrfld_bcove_pwrbtn",
.num_resources = 1,
.resources = &irq_level2_resources[0],
}, {
.name = "mrfld_bcove_tmu",
.num_resources = 1,
.resources = &irq_level2_resources[1],
}, {
.name = "mrfld_bcove_thermal",
.num_resources = 1,
.resources = &irq_level2_resources[2],
}, {
.name = "mrfld_bcove_bcu",
.num_resources = 1,
.resources = &irq_level2_resources[3],
}, {
.name = "mrfld_bcove_adc",
.num_resources = 1,
.resources = &irq_level2_resources[4],
}, {
.name = "mrfld_bcove_charger",
.num_resources = 1,
.resources = &irq_level2_resources[5],
}, {
.name = "mrfld_bcove_pwrsrc",
.num_resources = 1,
.resources = &irq_level2_resources[5],
}, {
.name = "mrfld_bcove_gpio",
.num_resources = 1,
.resources = &irq_level2_resources[6],
},
{ .name = "mrfld_bcove_region", },
};
static int bcove_ipc_byte_reg_read(void *context, unsigned int reg,
unsigned int *val)
{
struct intel_soc_pmic *pmic = context;
u8 ipc_out;
int ret;
ret = intel_scu_ipc_dev_ioread8(pmic->scu, reg, &ipc_out);
if (ret)
return ret;
*val = ipc_out;
return 0;
}
static int bcove_ipc_byte_reg_write(void *context, unsigned int reg,
unsigned int val)
{
struct intel_soc_pmic *pmic = context;
u8 ipc_in = val;
return intel_scu_ipc_dev_iowrite8(pmic->scu, reg, ipc_in);
}
static const struct regmap_config bcove_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.max_register = 0xff,
.reg_write = bcove_ipc_byte_reg_write,
.reg_read = bcove_ipc_byte_reg_read,
};
static int bcove_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct intel_soc_pmic *pmic;
unsigned int i;
int ret;
pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
if (!pmic)
return -ENOMEM;
pmic->scu = devm_intel_scu_ipc_dev_get(dev);
if (!pmic->scu)
return -ENOMEM;
platform_set_drvdata(pdev, pmic);
pmic->dev = &pdev->dev;
pmic->regmap = devm_regmap_init(dev, NULL, pmic, &bcove_regmap_config);
if (IS_ERR(pmic->regmap))
return PTR_ERR(pmic->regmap);
for (i = 0; i < ARRAY_SIZE(irq_level2_resources); i++) {
ret = platform_get_irq(pdev, i);
if (ret < 0)
return ret;
irq_level2_resources[i].start = ret;
irq_level2_resources[i].end = ret;
}
return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
bcove_dev, ARRAY_SIZE(bcove_dev),
NULL, 0, NULL);
}
static const struct acpi_device_id bcove_acpi_ids[] = {
{ "INTC100E" },
{}
};
MODULE_DEVICE_TABLE(acpi, bcove_acpi_ids);
static struct platform_driver bcove_driver = {
.driver = {
.name = "intel_soc_pmic_mrfld",
.acpi_match_table = bcove_acpi_ids,
},
.probe = bcove_probe,
};
module_platform_driver(bcove_driver);
MODULE_DESCRIPTION("IPC driver for Intel SoC Basin Cove PMIC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/intel_soc_pmic_mrfld.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI LP8788 MFD - interrupt handler
*
* Copyright 2012 Texas Instruments
*
* Author: Milo(Woogyom) Kim <[email protected]>
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/device.h>
#include <linux/mfd/lp8788.h>
#include <linux/module.h>
#include <linux/slab.h>
/* register address */
#define LP8788_INT_1 0x00
#define LP8788_INTEN_1 0x03
#define BASE_INTEN_ADDR LP8788_INTEN_1
#define SIZE_REG 8
#define NUM_REGS 3
/*
* struct lp8788_irq_data
* @lp : used for accessing to lp8788 registers
* @irq_lock : mutex for enabling/disabling the interrupt
* @domain : IRQ domain for handling nested interrupt
* @enabled : status of enabled interrupt
*/
struct lp8788_irq_data {
struct lp8788 *lp;
struct mutex irq_lock;
struct irq_domain *domain;
int enabled[LP8788_INT_MAX];
};
static inline u8 _irq_to_addr(enum lp8788_int_id id)
{
return id / SIZE_REG;
}
static inline u8 _irq_to_enable_addr(enum lp8788_int_id id)
{
return _irq_to_addr(id) + BASE_INTEN_ADDR;
}
static inline u8 _irq_to_mask(enum lp8788_int_id id)
{
return 1 << (id % SIZE_REG);
}
static inline u8 _irq_to_val(enum lp8788_int_id id, int enable)
{
return enable << (id % SIZE_REG);
}
static void lp8788_irq_enable(struct irq_data *data)
{
struct lp8788_irq_data *irqd = irq_data_get_irq_chip_data(data);
irqd->enabled[data->hwirq] = 1;
}
static void lp8788_irq_disable(struct irq_data *data)
{
struct lp8788_irq_data *irqd = irq_data_get_irq_chip_data(data);
irqd->enabled[data->hwirq] = 0;
}
static void lp8788_irq_bus_lock(struct irq_data *data)
{
struct lp8788_irq_data *irqd = irq_data_get_irq_chip_data(data);
mutex_lock(&irqd->irq_lock);
}
static void lp8788_irq_bus_sync_unlock(struct irq_data *data)
{
struct lp8788_irq_data *irqd = irq_data_get_irq_chip_data(data);
enum lp8788_int_id irq = data->hwirq;
u8 addr, mask, val;
addr = _irq_to_enable_addr(irq);
mask = _irq_to_mask(irq);
val = _irq_to_val(irq, irqd->enabled[irq]);
lp8788_update_bits(irqd->lp, addr, mask, val);
mutex_unlock(&irqd->irq_lock);
}
static struct irq_chip lp8788_irq_chip = {
.name = "lp8788",
.irq_enable = lp8788_irq_enable,
.irq_disable = lp8788_irq_disable,
.irq_bus_lock = lp8788_irq_bus_lock,
.irq_bus_sync_unlock = lp8788_irq_bus_sync_unlock,
};
static irqreturn_t lp8788_irq_handler(int irq, void *ptr)
{
struct lp8788_irq_data *irqd = ptr;
struct lp8788 *lp = irqd->lp;
u8 status[NUM_REGS], addr, mask;
bool handled = false;
int i;
if (lp8788_read_multi_bytes(lp, LP8788_INT_1, status, NUM_REGS))
return IRQ_NONE;
for (i = 0 ; i < LP8788_INT_MAX ; i++) {
addr = _irq_to_addr(i);
mask = _irq_to_mask(i);
/* reporting only if the irq is enabled */
if (status[addr] & mask) {
handle_nested_irq(irq_find_mapping(irqd->domain, i));
handled = true;
}
}
return handled ? IRQ_HANDLED : IRQ_NONE;
}
static int lp8788_irq_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hwirq)
{
struct lp8788_irq_data *irqd = d->host_data;
struct irq_chip *chip = &lp8788_irq_chip;
irq_set_chip_data(virq, irqd);
irq_set_chip_and_handler(virq, chip, handle_edge_irq);
irq_set_nested_thread(virq, 1);
irq_set_noprobe(virq);
return 0;
}
static const struct irq_domain_ops lp8788_domain_ops = {
.map = lp8788_irq_map,
};
int lp8788_irq_init(struct lp8788 *lp, int irq)
{
struct lp8788_irq_data *irqd;
int ret;
if (irq <= 0) {
dev_warn(lp->dev, "invalid irq number: %d\n", irq);
return 0;
}
irqd = devm_kzalloc(lp->dev, sizeof(*irqd), GFP_KERNEL);
if (!irqd)
return -ENOMEM;
irqd->lp = lp;
irqd->domain = irq_domain_add_linear(lp->dev->of_node, LP8788_INT_MAX,
&lp8788_domain_ops, irqd);
if (!irqd->domain) {
dev_err(lp->dev, "failed to add irq domain err\n");
return -EINVAL;
}
lp->irqdm = irqd->domain;
mutex_init(&irqd->irq_lock);
ret = request_threaded_irq(irq, NULL, lp8788_irq_handler,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"lp8788-irq", irqd);
if (ret) {
irq_domain_remove(lp->irqdm);
dev_err(lp->dev, "failed to create a thread for IRQ_N\n");
return ret;
}
lp->irq = irq;
return 0;
}
void lp8788_irq_exit(struct lp8788 *lp)
{
if (lp->irq)
free_irq(lp->irq, lp->irqdm);
if (lp->irqdm)
irq_domain_remove(lp->irqdm);
}
| linux-master | drivers/mfd/lp8788-irq.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Simple MFD - I2C
*
* Author(s):
* Michael Walle <[email protected]>
* Lee Jones <[email protected]>
*
* This driver creates a single register map with the intention for it to be
* shared by all sub-devices. Children can use their parent's device structure
* (dev.parent) in order to reference it.
*
* Once the register map has been successfully initialised, any sub-devices
* represented by child nodes in Device Tree or via the MFD cells in this file
* will be subsequently registered.
*/
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
#include "simple-mfd-i2c.h"
static const struct regmap_config regmap_config_8r_8v = {
.reg_bits = 8,
.val_bits = 8,
};
static int simple_mfd_i2c_probe(struct i2c_client *i2c)
{
const struct simple_mfd_data *simple_mfd_data;
const struct regmap_config *regmap_config;
struct regmap *regmap;
int ret;
simple_mfd_data = device_get_match_data(&i2c->dev);
/* If no regmap_config is specified, use the default 8reg and 8val bits */
if (!simple_mfd_data || !simple_mfd_data->regmap_config)
regmap_config = ®map_config_8r_8v;
else
regmap_config = simple_mfd_data->regmap_config;
regmap = devm_regmap_init_i2c(i2c, regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* If no MFD cells are specified, register using the DT child nodes instead */
if (!simple_mfd_data || !simple_mfd_data->mfd_cell)
return devm_of_platform_populate(&i2c->dev);
ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
simple_mfd_data->mfd_cell,
simple_mfd_data->mfd_cell_size,
NULL, 0, NULL);
if (ret)
dev_err(&i2c->dev, "Failed to add child devices\n");
return ret;
}
static const struct mfd_cell sy7636a_cells[] = {
{ .name = "sy7636a-regulator", },
{ .name = "sy7636a-temperature", },
};
static const struct simple_mfd_data silergy_sy7636a = {
.mfd_cell = sy7636a_cells,
.mfd_cell_size = ARRAY_SIZE(sy7636a_cells),
};
static const struct mfd_cell max5970_cells[] = {
{ .name = "max5970-regulator", },
{ .name = "max5970-iio", },
{ .name = "max5970-led", },
};
static const struct simple_mfd_data maxim_max5970 = {
.mfd_cell = max5970_cells,
.mfd_cell_size = ARRAY_SIZE(max5970_cells),
};
static const struct of_device_id simple_mfd_i2c_of_match[] = {
{ .compatible = "kontron,sl28cpld" },
{ .compatible = "silergy,sy7636a", .data = &silergy_sy7636a},
{ .compatible = "maxim,max5970", .data = &maxim_max5970},
{ .compatible = "maxim,max5978", .data = &maxim_max5970},
{}
};
MODULE_DEVICE_TABLE(of, simple_mfd_i2c_of_match);
static struct i2c_driver simple_mfd_i2c_driver = {
.probe = simple_mfd_i2c_probe,
.driver = {
.name = "simple-mfd-i2c",
.of_match_table = simple_mfd_i2c_of_match,
},
};
module_i2c_driver(simple_mfd_i2c_driver);
MODULE_AUTHOR("Michael Walle <[email protected]>");
MODULE_DESCRIPTION("Simple MFD - I2C driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/simple-mfd-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Regmap tables for CS47L90 codec
*
* Copyright (C) 2015-2017 Cirrus Logic
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/mfd/madera/core.h>
#include <linux/mfd/madera/registers.h>
#include "madera.h"
static const struct reg_sequence cs47l90_reva_16_patch[] = {
{ 0x8A, 0x5555 },
{ 0x8A, 0xAAAA },
{ 0x4CF, 0x0700 },
{ 0x171, 0x0003 },
{ 0x101, 0x0444 },
{ 0x159, 0x0002 },
{ 0x120, 0x0444 },
{ 0x1D1, 0x0004 },
{ 0x1E0, 0xC084 },
{ 0x159, 0x0000 },
{ 0x120, 0x0404 },
{ 0x101, 0x0404 },
{ 0x171, 0x0002 },
{ 0x17A, 0x2906 },
{ 0x19A, 0x2906 },
{ 0x441, 0xC750 },
{ 0x340, 0x0001 },
{ 0x112, 0x0405 },
{ 0x124, 0x0C49 },
{ 0x1300, 0x050E },
{ 0x1302, 0x0101 },
{ 0x1380, 0x0425 },
{ 0x1381, 0xF6D8 },
{ 0x1382, 0x0632 },
{ 0x1383, 0xFEC8 },
{ 0x1390, 0x042F },
{ 0x1391, 0xF6CA },
{ 0x1392, 0x0637 },
{ 0x1393, 0xFEC8 },
{ 0x281, 0x0000 },
{ 0x282, 0x0000 },
{ 0x4EA, 0x0100 },
{ 0x8A, 0xCCCC },
{ 0x8A, 0x3333 },
};
int cs47l90_patch(struct madera *madera)
{
int ret;
ret = regmap_register_patch(madera->regmap,
cs47l90_reva_16_patch,
ARRAY_SIZE(cs47l90_reva_16_patch));
if (ret < 0) {
dev_err(madera->dev,
"Error in applying 16-bit patch: %d\n", ret);
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(cs47l90_patch);
static const struct reg_default cs47l90_reg_default[] = {
{ 0x00000020, 0x0000 }, /* R32 (0x20) - Tone Generator 1 */
{ 0x00000021, 0x1000 }, /* R33 (0x21) - Tone Generator 2 */
{ 0x00000022, 0x0000 }, /* R34 (0x22) - Tone Generator 3 */
{ 0x00000023, 0x1000 }, /* R35 (0x23) - Tone Generator 4 */
{ 0x00000024, 0x0000 }, /* R36 (0x24) - Tone Generator 5 */
{ 0x00000030, 0x0000 }, /* R48 (0x30) - PWM Drive 1 */
{ 0x00000031, 0x0100 }, /* R49 (0x31) - PWM Drive 2 */
{ 0x00000032, 0x0100 }, /* R50 (0x32) - PWM Drive 3 */
{ 0x00000061, 0x01ff }, /* R97 (0x61) - Sample Rate Sequence Select 1 */
{ 0x00000062, 0x01ff }, /* R98 (0x62) - Sample Rate Sequence Select 2 */
{ 0x00000063, 0x01ff }, /* R99 (0x63) - Sample Rate Sequence Select 3 */
{ 0x00000064, 0x01ff }, /* R100 (0x64) - Sample Rate Sequence Select 4 */
{ 0x00000066, 0x01ff }, /* R102 (0x66) - Always On Triggers Sequence Select 1 */
{ 0x00000067, 0x01ff }, /* R103 (0x67) - Always On Triggers Sequence Select 2 */
{ 0x00000090, 0x0000 }, /* R144 (0x90) - Haptics Control 1 */
{ 0x00000091, 0x7fff }, /* R145 (0x91) - Haptics Control 2 */
{ 0x00000092, 0x0000 }, /* R146 (0x92) - Haptics phase 1 intensity */
{ 0x00000093, 0x0000 }, /* R147 (0x93) - Haptics phase 1 duration */
{ 0x00000094, 0x0000 }, /* R148 (0x94) - Haptics phase 2 intensity */
{ 0x00000095, 0x0000 }, /* R149 (0x95) - Haptics phase 2 duration */
{ 0x00000096, 0x0000 }, /* R150 (0x96) - Haptics phase 3 intensity */
{ 0x00000097, 0x0000 }, /* R151 (0x97) - Haptics phase 3 duration */
{ 0x000000a0, 0x0000 }, /* R160 (0xa0) - Comfort Noise Generator */
{ 0x00000100, 0x0002 }, /* R256 (0x100) - Clock 32k 1 */
{ 0x00000101, 0x0404 }, /* R257 (0x101) - System Clock 1 */
{ 0x00000102, 0x0011 }, /* R258 (0x102) - Sample rate 1 */
{ 0x00000103, 0x0011 }, /* R259 (0x103) - Sample rate 2 */
{ 0x00000104, 0x0011 }, /* R260 (0x104) - Sample rate 3 */
{ 0x00000112, 0x0405 }, /* R274 (0x112) - Async clock 1 */
{ 0x00000113, 0x0011 }, /* R275 (0x113) - Async sample rate 1 */
{ 0x00000114, 0x0011 }, /* R276 (0x114) - Async sample rate 2 */
{ 0x00000120, 0x0404 }, /* R288 (0x120) - DSP Clock 1 */
{ 0x00000122, 0x0000 }, /* R290 (0x122) - DSP Clock 2 */
{ 0x00000149, 0x0000 }, /* R329 (0x149) - Output system clock */
{ 0x0000014a, 0x0000 }, /* R330 (0x14a) - Output async clock */
{ 0x00000152, 0x0000 }, /* R338 (0x152) - Rate Estimator 1 */
{ 0x00000153, 0x0000 }, /* R339 (0x153) - Rate Estimator 2 */
{ 0x00000154, 0x0000 }, /* R340 (0x154) - Rate Estimator 3 */
{ 0x00000155, 0x0000 }, /* R341 (0x155) - Rate Estimator 4 */
{ 0x00000156, 0x0000 }, /* R342 (0x156) - Rate Estimator 5 */
{ 0x00000171, 0x0002 }, /* R369 (0x171) - FLL1 Control 1 */
{ 0x00000172, 0x0008 }, /* R370 (0x172) - FLL1 Control 2 */
{ 0x00000173, 0x0018 }, /* R371 (0x173) - FLL1 Control 3 */
{ 0x00000174, 0x007d }, /* R372 (0x174) - FLL1 Control 4 */
{ 0x00000175, 0x0000 }, /* R373 (0x175) - FLL1 Control 5 */
{ 0x00000176, 0x0000 }, /* R374 (0x176) - FLL1 Control 6 */
{ 0x00000179, 0x0000 }, /* R377 (0x179) - FLL1 Control 7 */
{ 0x0000017a, 0x2906 }, /* R377 (0x17a) - FLL1 Efs 2 */
{ 0x00000181, 0x0000 }, /* R385 (0x181) - FLL1 Synchroniser 1 */
{ 0x00000182, 0x0000 }, /* R386 (0x182) - FLL1 Synchroniser 2 */
{ 0x00000183, 0x0000 }, /* R387 (0x183) - FLL1 Synchroniser 3 */
{ 0x00000184, 0x0000 }, /* R388 (0x184) - FLL1 Synchroniser 4 */
{ 0x00000185, 0x0000 }, /* R389 (0x185) - FLL1 Synchroniser 5 */
{ 0x00000186, 0x0000 }, /* R390 (0x186) - FLL1 Synchroniser 6 */
{ 0x00000187, 0x0001 }, /* R391 (0x187) - FLL1 Synchroniser 7 */
{ 0x00000189, 0x0000 }, /* R393 (0x189) - FLL1 Spread Spectrum */
{ 0x0000018a, 0x0004 }, /* R394 (0x18a) - FLL1 GPIO Clock */
{ 0x00000191, 0x0002 }, /* R401 (0x191) - FLL2 Control 1 */
{ 0x00000192, 0x0008 }, /* R402 (0x192) - FLL2 Control 2 */
{ 0x00000193, 0x0018 }, /* R403 (0x193) - FLL2 Control 3 */
{ 0x00000194, 0x007d }, /* R404 (0x194) - FLL2 Control 4 */
{ 0x00000195, 0x0000 }, /* R405 (0x195) - FLL2 Control 5 */
{ 0x00000196, 0x0000 }, /* R406 (0x196) - FLL2 Control 6 */
{ 0x00000199, 0x0000 }, /* R409 (0x199) - FLL2 Control 7 */
{ 0x0000019a, 0x2906 }, /* R410 (0x19a) - FLL2 Efs 2 */
{ 0x000001a1, 0x0000 }, /* R417 (0x1a1) - FLL2 Synchroniser 1 */
{ 0x000001a2, 0x0000 }, /* R418 (0x1a2) - FLL2 Synchroniser 2 */
{ 0x000001a3, 0x0000 }, /* R419 (0x1a3) - FLL2 Synchroniser 3 */
{ 0x000001a4, 0x0000 }, /* R420 (0x1a4) - FLL2 Synchroniser 4 */
{ 0x000001a5, 0x0000 }, /* R421 (0x1a5) - FLL2 Synchroniser 5 */
{ 0x000001a6, 0x0000 }, /* R422 (0x1a6) - FLL2 Synchroniser 6 */
{ 0x000001a7, 0x0001 }, /* R423 (0x1a7) - FLL2 Synchroniser 7 */
{ 0x000001a9, 0x0000 }, /* R425 (0x1a9) - FLL2 Spread Spectrum */
{ 0x000001aa, 0x0004 }, /* R426 (0x1aa) - FLL2 GPIO Clock */
{ 0x000001d1, 0x0004 }, /* R465 (0x1d1) - FLLAO_CONTROL_1 */
{ 0x000001d2, 0x0004 }, /* R466 (0x1d2) - FLLAO_CONTROL_2 */
{ 0x000001d3, 0x0000 }, /* R467 (0x1d3) - FLLAO_CONTROL_3 */
{ 0x000001d4, 0x0000 }, /* R468 (0x1d4) - FLLAO_CONTROL_4 */
{ 0x000001d5, 0x0001 }, /* R469 (0x1d5) - FLLAO_CONTROL_5 */
{ 0x000001d6, 0x8004 }, /* R470 (0x1d6) - FLLAO_CONTROL_6 */
{ 0x000001d8, 0x0000 }, /* R472 (0x1d8) - FLLAO_CONTROL_7 */
{ 0x000001da, 0x0070 }, /* R474 (0x1da) - FLLAO_CONTROL_8 */
{ 0x000001db, 0x0000 }, /* R475 (0x1db) - FLLAO_CONTROL_9 */
{ 0x000001dc, 0x06da }, /* R476 (0x1dc) - FLLAO_CONTROL_10 */
{ 0x000001dd, 0x0011 }, /* R477 (0x1dd) - FLLAO_CONTROL_11 */
{ 0x00000200, 0x0006 }, /* R512 (0x200) - Mic Charge Pump 1 */
{ 0x00000213, 0x03e4 }, /* R531 (0x213) - LDO2 Control 1 */
{ 0x00000218, 0x00e6 }, /* R536 (0x218) - Mic Bias Ctrl 1 */
{ 0x00000219, 0x00e6 }, /* R537 (0x219) - Mic Bias Ctrl 2 */
{ 0x0000021c, 0x2222 }, /* R540 (0x21c) - Mic Bias Ctrl 5 */
{ 0x0000021e, 0x2222 }, /* R542 (0x21e) - Mic Bias Ctrl 6 */
{ 0x0000027e, 0x0000 }, /* R638 (0x27e) - EDRE HP stereo control */
{ 0x00000293, 0x0080 }, /* R659 (0x293) - Accessory Detect Mode 1 */
{ 0x00000299, 0x0000 }, /* R665 (0x299) - Headphone Detect 0 */
{ 0x0000029b, 0x0000 }, /* R667 (0x29b) - Headphone Detect 1 */
{ 0x000002a2, 0x0010 }, /* R674 (0x2a2) - Mic Detect 1 Control 0 */
{ 0x000002a3, 0x1102 }, /* R675 (0x2a3) - Mic Detect 1 Control 1 */
{ 0x000002a4, 0x009f }, /* R676 (0x2a4) - Mic Detect 1 Control 2 */
{ 0x000002a6, 0x3d3d }, /* R678 (0x2a6) - Mic Detect 1 Level 1 */
{ 0x000002a7, 0x3d3d }, /* R679 (0x2a7) - Mic Detect 1 Level 2 */
{ 0x000002a8, 0x333d }, /* R680 (0x2a8) - Mic Detect 1 Level 3 */
{ 0x000002a9, 0x202d }, /* R681 (0x2a9) - Mic Detect 1 Level 4 */
{ 0x000002b2, 0x0010 }, /* R690 (0x2b2) - Mic Detect 2 Control 0 */
{ 0x000002b3, 0x1102 }, /* R691 (0x2b3) - Mic Detect 2 Control 1 */
{ 0x000002b4, 0x009f }, /* R692 (0x2b4) - Mic Detect 2 Control 2 */
{ 0x000002b6, 0x3d3d }, /* R694 (0x2b6) - Mic Detect 2 Level 1 */
{ 0x000002b7, 0x3d3d }, /* R695 (0x2b7) - Mic Detect 2 Level 2 */
{ 0x000002b8, 0x333d }, /* R696 (0x2b8) - Mic Detect 2 Level 3 */
{ 0x000002b9, 0x202d }, /* R697 (0x2b9) - Mic Detect 2 Level 4 */
{ 0x000002c6, 0x0010 }, /* R710 (0x2c6) - Mic Clamp control */
{ 0x000002c8, 0x0000 }, /* R712 (0x2c8) - GP switch 1 */
{ 0x000002d3, 0x0000 }, /* R723 (0x2d3) - Jack detect analogue */
{ 0x00000300, 0x0000 }, /* R768 (0x300) - Input Enables */
{ 0x00000308, 0x0400 }, /* R776 (0x308) - Input Rate */
{ 0x00000309, 0x0022 }, /* R777 (0x309) - Input Volume Ramp */
{ 0x0000030c, 0x0002 }, /* R780 (0x30C) - HPF Control */
{ 0x00000310, 0x0080 }, /* R784 (0x310) - IN1L Control */
{ 0x00000311, 0x0180 }, /* R785 (0x311) - ADC Digital Volume 1L */
{ 0x00000312, 0x0500 }, /* R786 (0x312) - DMIC1L Control */
{ 0x00000313, 0x0000 }, /* R787 (0x313) - IN1L Rate Control */
{ 0x00000314, 0x0080 }, /* R788 (0x314) - IN1R Control */
{ 0x00000315, 0x0180 }, /* R789 (0x315) - ADC Digital Volume 1R */
{ 0x00000316, 0x0000 }, /* R790 (0x316) - DMIC1R Control */
{ 0x00000317, 0x0000 }, /* R791 (0x317) - IN1R Rate Control */
{ 0x00000318, 0x0080 }, /* R792 (0x318) - IN2L Control */
{ 0x00000319, 0x0180 }, /* R793 (0x319) - ADC Digital Volume 2L */
{ 0x0000031a, 0x0500 }, /* R794 (0x31a) - DMIC2L Control */
{ 0x0000031b, 0x0000 }, /* R795 (0x31b) - IN2L Rate Control */
{ 0x0000031c, 0x0080 }, /* R796 (0x31c) - IN2R Control */
{ 0x0000031d, 0x0180 }, /* R797 (0x31d) - ADC Digital Volume 2R */
{ 0x0000031e, 0x0000 }, /* R798 (0x31e) - DMIC2R Control */
{ 0x0000031f, 0x0000 }, /* R799 (0x31f) - IN2R Rate Control */
{ 0x00000320, 0x0000 }, /* R800 (0x320) - IN3L Control */
{ 0x00000321, 0x0180 }, /* R801 (0x321) - ADC Digital Volume 3L */
{ 0x00000322, 0x0500 }, /* R802 (0x322) - DMIC3L Control */
{ 0x00000323, 0x0000 }, /* R803 (0x323) - IN3L Rate Control */
{ 0x00000324, 0x0000 }, /* R804 (0x324) - IN3R Control */
{ 0x00000325, 0x0180 }, /* R805 (0x325) - ADC Digital Volume 3R */
{ 0x00000326, 0x0000 }, /* R806 (0x326) - DMIC3R Control */
{ 0x00000327, 0x0000 }, /* R807 (0x327) - IN3R Rate Control */
{ 0x00000328, 0x0000 }, /* R808 (0x328) - IN4 Control */
{ 0x00000329, 0x0180 }, /* R809 (0x329) - ADC Digital Volume 4L */
{ 0x0000032a, 0x0500 }, /* R810 (0x32a) - DMIC4L Control */
{ 0x0000032b, 0x0000 }, /* R811 (0x32b) - IN4L Rate Control */
{ 0x0000032c, 0x0000 }, /* R812 (0x32c) - IN4R Control */
{ 0x0000032d, 0x0180 }, /* R813 (0x32d) - ADC Digital Volume 4R */
{ 0x0000032e, 0x0000 }, /* R814 (0x32e) - DMIC4R Control */
{ 0x0000032f, 0x0000 }, /* R815 (0x32f) - IN4R Rate Control */
{ 0x00000330, 0x0000 }, /* R816 (0x330) - IN5L Control */
{ 0x00000331, 0x0180 }, /* R817 (0x331) - ADC Digital Volume 5L */
{ 0x00000332, 0x0500 }, /* R818 (0x332) - DMIC5L Control */
{ 0x00000333, 0x0000 }, /* R819 (0x333) - IN5L Rate Control */
{ 0x00000334, 0x0000 }, /* R820 (0x334) - IN5R Control */
{ 0x00000335, 0x0180 }, /* R821 (0x335) - ADC Digital Volume 5R */
{ 0x00000336, 0x0000 }, /* R822 (0x336) - DMIC5R Control */
{ 0x00000337, 0x0000 }, /* R823 (0x337) - IN5R Rate Control */
{ 0x00000400, 0x0000 }, /* R1024 (0x400) - Output Enables 1 */
{ 0x00000408, 0x0000 }, /* R1032 (0x408) - Output Rate 1 */
{ 0x00000409, 0x0022 }, /* R1033 (0x409) - Output Volume Ramp */
{ 0x00000410, 0x0080 }, /* R1040 (0x410) - Output Path Config 1L */
{ 0x00000411, 0x0180 }, /* R1041 (0x411) - DAC Digital Volume 1L */
{ 0x00000412, 0x0000 }, /* R1042 (0x412) - Output Path Config 1 */
{ 0x00000413, 0x0001 }, /* R1043 (0x413) - Noise Gate Select 1L */
{ 0x00000414, 0x0080 }, /* R1044 (0x414) - Output Path Config 1R */
{ 0x00000415, 0x0180 }, /* R1045 (0x415) - DAC Digital Volume 1R */
{ 0x00000417, 0x0002 }, /* R1047 (0x417) - Noise Gate Select 1R */
{ 0x00000418, 0x0080 }, /* R1048 (0x418) - Output Path Config 2L */
{ 0x00000419, 0x0180 }, /* R1049 (0x419) - DAC Digital Volume 2L */
{ 0x0000041a, 0x0002 }, /* R1050 (0x41a) - Output Path Config 2 */
{ 0x0000041b, 0x0004 }, /* R1051 (0x41b) - Noise Gate Select 2L */
{ 0x0000041c, 0x0080 }, /* R1052 (0x41c) - Output Path Config 2R */
{ 0x0000041d, 0x0180 }, /* R1053 (0x41d) - DAC Digital Volume 2R */
{ 0x0000041f, 0x0008 }, /* R1055 (0x41f) - Noise Gate Select 2R */
{ 0x00000420, 0x0080 }, /* R1056 (0x420) - Output Path Config 3L */
{ 0x00000421, 0x0180 }, /* R1057 (0x421) - DAC Digital Volume 3L */
{ 0x00000423, 0x0010 }, /* R1059 (0x423) - Noise Gate Select 3L */
{ 0x00000424, 0x0080 }, /* R1060 (0x424) - Output Path Config 3R */
{ 0x00000425, 0x0180 }, /* R1061 (0x425) - DAC Digital Volume 3R */
{ 0x00000427, 0x0020 }, /* R1063 (0x427) - Noise Gate Select 3R */
{ 0x00000430, 0x0000 }, /* R1072 (0x430) - Output Path Config 5L */
{ 0x00000431, 0x0180 }, /* R1073 (0x431) - DAC Digital Volume 5L */
{ 0x00000433, 0x0100 }, /* R1075 (0x433) - Noise Gate Select 5L */
{ 0x00000434, 0x0000 }, /* R1076 (0x434) - Output Path Config 5R */
{ 0x00000435, 0x0180 }, /* R1077 (0x435) - DAC Digital Volume 5R */
{ 0x00000437, 0x0200 }, /* R1079 (0x437) - Noise Gate Select 5R */
{ 0x00000450, 0x0000 }, /* R1104 (0x450) - DAC AEC Control 1 */
{ 0x00000451, 0x0000 }, /* R1104 (0x450) - DAC AEC Control 2 */
{ 0x00000458, 0x0000 }, /* R1112 (0x458) - Noise Gate Control */
{ 0x00000490, 0x0069 }, /* R1168 (0x490) - PDM SPK1 CTRL 1 */
{ 0x00000491, 0x0000 }, /* R1169 (0x491) - PDM SPK1 CTRL 2 */
{ 0x000004a0, 0x3080 }, /* R1184 (0x4a0) - HP1 Short Circuit Ctrl */
{ 0x000004a1, 0x3000 }, /* R1185 (0x4a1) - HP2 Short Circuit Ctrl */
{ 0x000004a2, 0x3000 }, /* R1186 (0x4a2) - HP3 Short Circuit Ctrl */
{ 0x00000500, 0x000c }, /* R1280 (0x500) - AIF1 BCLK Ctrl */
{ 0x00000501, 0x0000 }, /* R1281 (0x501) - AIF1 Tx Pin Ctrl */
{ 0x00000502, 0x0000 }, /* R1282 (0x502) - AIF1 Rx Pin Ctrl */
{ 0x00000503, 0x0000 }, /* R1283 (0x503) - AIF1 Rate Ctrl */
{ 0x00000504, 0x0000 }, /* R1284 (0x504) - AIF1 Format */
{ 0x00000506, 0x0040 }, /* R1286 (0x506) - AIF1 Rx BCLK Rate */
{ 0x00000507, 0x1818 }, /* R1287 (0x507) - AIF1 Frame Ctrl 1 */
{ 0x00000508, 0x1818 }, /* R1288 (0x508) - AIF1 Frame Ctrl 2 */
{ 0x00000509, 0x0000 }, /* R1289 (0x509) - AIF1 Frame Ctrl 3 */
{ 0x0000050a, 0x0001 }, /* R1290 (0x50a) - AIF1 Frame Ctrl 4 */
{ 0x0000050b, 0x0002 }, /* R1291 (0x50b) - AIF1 Frame Ctrl 5 */
{ 0x0000050c, 0x0003 }, /* R1292 (0x50c) - AIF1 Frame Ctrl 6 */
{ 0x0000050d, 0x0004 }, /* R1293 (0x50d) - AIF1 Frame Ctrl 7 */
{ 0x0000050e, 0x0005 }, /* R1294 (0x50e) - AIF1 Frame Ctrl 8 */
{ 0x0000050f, 0x0006 }, /* R1295 (0x50f) - AIF1 Frame Ctrl 9 */
{ 0x00000510, 0x0007 }, /* R1296 (0x510) - AIF1 Frame Ctrl 10 */
{ 0x00000511, 0x0000 }, /* R1297 (0x511) - AIF1 Frame Ctrl 11 */
{ 0x00000512, 0x0001 }, /* R1298 (0x512) - AIF1 Frame Ctrl 12 */
{ 0x00000513, 0x0002 }, /* R1299 (0x513) - AIF1 Frame Ctrl 13 */
{ 0x00000514, 0x0003 }, /* R1300 (0x514) - AIF1 Frame Ctrl 14 */
{ 0x00000515, 0x0004 }, /* R1301 (0x515) - AIF1 Frame Ctrl 15 */
{ 0x00000516, 0x0005 }, /* R1302 (0x516) - AIF1 Frame Ctrl 16 */
{ 0x00000517, 0x0006 }, /* R1303 (0x517) - AIF1 Frame Ctrl 17 */
{ 0x00000518, 0x0007 }, /* R1304 (0x518) - AIF1 Frame Ctrl 18 */
{ 0x00000519, 0x0000 }, /* R1305 (0x519) - AIF1 Tx Enables */
{ 0x0000051a, 0x0000 }, /* R1306 (0x51a) - AIF1 Rx Enables */
{ 0x00000540, 0x000c }, /* R1344 (0x540) - AIF2 BCLK Ctrl */
{ 0x00000541, 0x0000 }, /* R1345 (0x541) - AIF2 Tx Pin Ctrl */
{ 0x00000542, 0x0000 }, /* R1346 (0x542) - AIF2 Rx Pin Ctrl */
{ 0x00000543, 0x0000 }, /* R1347 (0x543) - AIF2 Rate Ctrl */
{ 0x00000544, 0x0000 }, /* R1348 (0x544) - AIF2 Format */
{ 0x00000546, 0x0040 }, /* R1350 (0x546) - AIF2 Rx BCLK Rate */
{ 0x00000547, 0x1818 }, /* R1351 (0x547) - AIF2 Frame Ctrl 1 */
{ 0x00000548, 0x1818 }, /* R1352 (0x548) - AIF2 Frame Ctrl 2 */
{ 0x00000549, 0x0000 }, /* R1353 (0x549) - AIF2 Frame Ctrl 3 */
{ 0x0000054a, 0x0001 }, /* R1354 (0x54a) - AIF2 Frame Ctrl 4 */
{ 0x0000054b, 0x0002 }, /* R1355 (0x54b) - AIF2 Frame Ctrl 5 */
{ 0x0000054c, 0x0003 }, /* R1356 (0x54c) - AIF2 Frame Ctrl 6 */
{ 0x0000054d, 0x0004 }, /* R1357 (0x54d) - AIF2 Frame Ctrl 7 */
{ 0x0000054e, 0x0005 }, /* R1358 (0x54e) - AIF2 Frame Ctrl 8 */
{ 0x0000054f, 0x0006 }, /* R1359 (0x54f) - AIF2 Frame Ctrl 9 */
{ 0x00000550, 0x0007 }, /* R1360 (0x550) - AIF2 Frame Ctrl 10 */
{ 0x00000551, 0x0000 }, /* R1361 (0x551) - AIF2 Frame Ctrl 11 */
{ 0x00000552, 0x0001 }, /* R1362 (0x552) - AIF2 Frame Ctrl 12 */
{ 0x00000553, 0x0002 }, /* R1363 (0x553) - AIF2 Frame Ctrl 13 */
{ 0x00000554, 0x0003 }, /* R1364 (0x554) - AIF2 Frame Ctrl 14 */
{ 0x00000555, 0x0004 }, /* R1365 (0x555) - AIF2 Frame Ctrl 15 */
{ 0x00000556, 0x0005 }, /* R1366 (0x556) - AIF2 Frame Ctrl 16 */
{ 0x00000557, 0x0006 }, /* R1367 (0x557) - AIF2 Frame Ctrl 17 */
{ 0x00000558, 0x0007 }, /* R1368 (0x558) - AIF2 Frame Ctrl 18 */
{ 0x00000559, 0x0000 }, /* R1369 (0x559) - AIF2 Tx Enables */
{ 0x0000055a, 0x0000 }, /* R1370 (0x55a) - AIF2 Rx Enables */
{ 0x00000580, 0x000c }, /* R1408 (0x580) - AIF3 BCLK Ctrl */
{ 0x00000581, 0x0000 }, /* R1409 (0x581) - AIF3 Tx Pin Ctrl */
{ 0x00000582, 0x0000 }, /* R1410 (0x582) - AIF3 Rx Pin Ctrl */
{ 0x00000583, 0x0000 }, /* R1411 (0x583) - AIF3 Rate Ctrl */
{ 0x00000584, 0x0000 }, /* R1412 (0x584) - AIF3 Format */
{ 0x00000586, 0x0040 }, /* R1414 (0x586) - AIF3 Rx BCLK Rate */
{ 0x00000587, 0x1818 }, /* R1415 (0x587) - AIF3 Frame Ctrl 1 */
{ 0x00000588, 0x1818 }, /* R1416 (0x588) - AIF3 Frame Ctrl 2 */
{ 0x00000589, 0x0000 }, /* R1417 (0x589) - AIF3 Frame Ctrl 3 */
{ 0x0000058a, 0x0001 }, /* R1418 (0x58a) - AIF3 Frame Ctrl 4 */
{ 0x00000591, 0x0000 }, /* R1425 (0x591) - AIF3 Frame Ctrl 11 */
{ 0x00000592, 0x0001 }, /* R1426 (0x592) - AIF3 Frame Ctrl 12 */
{ 0x00000599, 0x0000 }, /* R1433 (0x599) - AIF3 Tx Enables */
{ 0x0000059a, 0x0000 }, /* R1434 (0x59a) - AIF3 Rx Enables */
{ 0x000005a0, 0x000c }, /* R1440 (0x5a0) - AIF4 BCLK Ctrl */
{ 0x000005a1, 0x0000 }, /* R1441 (0x5a1) - AIF4 Tx Pin Ctrl */
{ 0x000005a2, 0x0000 }, /* R1442 (0x5a2) - AIF4 Rx Pin Ctrl */
{ 0x000005a3, 0x0000 }, /* R1443 (0x5a3) - AIF4 Rate Ctrl */
{ 0x000005a4, 0x0000 }, /* R1444 (0x5a4) - AIF4 Format */
{ 0x000005a6, 0x0040 }, /* R1446 (0x5a6) - AIF4 Rx BCLK Rate */
{ 0x000005a7, 0x1818 }, /* R1447 (0x5a7) - AIF4 Frame Ctrl 1 */
{ 0x000005a8, 0x1818 }, /* R1448 (0x5a8) - AIF4 Frame Ctrl 2 */
{ 0x000005a9, 0x0000 }, /* R1449 (0x5a9) - AIF4 Frame Ctrl 3 */
{ 0x000005aa, 0x0001 }, /* R1450 (0x5aa) - AIF4 Frame Ctrl 4 */
{ 0x000005b1, 0x0000 }, /* R1457 (0x5b1) - AIF4 Frame Ctrl 11 */
{ 0x000005b2, 0x0001 }, /* R1458 (0x5b2) - AIF4 Frame Ctrl 12 */
{ 0x000005b9, 0x0000 }, /* R1465 (0x5b9) - AIF4 Tx Enables */
{ 0x000005ba, 0x0000 }, /* R1466 (0x5ba) - AIF4 Rx Enables */
{ 0x000005c2, 0x0000 }, /* R1474 (0x5c2) - SPD1 TX Control */
{ 0x000005e3, 0x0000 }, /* R1507 (0x5e3) - SLIMbus Framer Ref Gear */
{ 0x000005e5, 0x0000 }, /* R1509 (0x5e5) - SLIMbus Rates 1 */
{ 0x000005e6, 0x0000 }, /* R1510 (0x5e6) - SLIMbus Rates 2 */
{ 0x000005e7, 0x0000 }, /* R1511 (0x5e7) - SLIMbus Rates 3 */
{ 0x000005e8, 0x0000 }, /* R1512 (0x5e8) - SLIMbus Rates 4 */
{ 0x000005e9, 0x0000 }, /* R1513 (0x5e9) - SLIMbus Rates 5 */
{ 0x000005ea, 0x0000 }, /* R1514 (0x5ea) - SLIMbus Rates 6 */
{ 0x000005eb, 0x0000 }, /* R1515 (0x5eb) - SLIMbus Rates 7 */
{ 0x000005ec, 0x0000 }, /* R1516 (0x5ec) - SLIMbus Rates 8 */
{ 0x000005f5, 0x0000 }, /* R1525 (0x5f5) - SLIMbus RX Channel Enable */
{ 0x000005f6, 0x0000 }, /* R1526 (0x5F6) - SLIMbus TX Channel Enable */
{ 0x00000640, 0x0000 }, /* R1600 (0x640) - PWM1MIX Input 1 Source */
{ 0x00000641, 0x0080 }, /* R1601 (0x641) - PWM1MIX Input 1 Volume */
{ 0x00000642, 0x0000 }, /* R1602 (0x642) - PWM1MIX Input 2 Source */
{ 0x00000643, 0x0080 }, /* R1603 (0x643) - PWM1MIX Input 2 Volume */
{ 0x00000644, 0x0000 }, /* R1604 (0x644) - PWM1MIX Input 3 Source */
{ 0x00000645, 0x0080 }, /* R1605 (0x645) - PWM1MIX Input 3 Volume */
{ 0x00000646, 0x0000 }, /* R1606 (0x646) - PWM1MIX Input 4 Source */
{ 0x00000647, 0x0080 }, /* R1607 (0x647) - PWM1MIX Input 4 Volume */
{ 0x00000648, 0x0000 }, /* R1608 (0x648) - PWM2MIX Input 1 Source */
{ 0x00000649, 0x0080 }, /* R1609 (0x649) - PWM2MIX Input 1 Volume */
{ 0x0000064a, 0x0000 }, /* R1610 (0x64a) - PWM2MIX Input 2 Source */
{ 0x0000064b, 0x0080 }, /* R1611 (0x64b) - PWM2MIX Input 2 Volume */
{ 0x0000064c, 0x0000 }, /* R1612 (0x64c) - PWM2MIX Input 3 Source */
{ 0x0000064d, 0x0080 }, /* R1613 (0x64d) - PWM2MIX Input 3 Volume */
{ 0x0000064e, 0x0000 }, /* R1614 (0x64e) - PWM2MIX Input 4 Source */
{ 0x0000064f, 0x0080 }, /* R1615 (0x64f) - PWM2MIX Input 4 Volume */
{ 0x00000680, 0x0000 }, /* R1664 (0x680) - OUT1LMIX Input 1 Source */
{ 0x00000681, 0x0080 }, /* R1665 (0x681) - OUT1LMIX Input 1 Volume */
{ 0x00000682, 0x0000 }, /* R1666 (0x682) - OUT1LMIX Input 2 Source */
{ 0x00000683, 0x0080 }, /* R1667 (0x683) - OUT1LMIX Input 2 Volume */
{ 0x00000684, 0x0000 }, /* R1668 (0x684) - OUT1LMIX Input 3 Source */
{ 0x00000685, 0x0080 }, /* R1669 (0x685) - OUT1LMIX Input 3 Volume */
{ 0x00000686, 0x0000 }, /* R1670 (0x686) - OUT1LMIX Input 4 Source */
{ 0x00000687, 0x0080 }, /* R1671 (0x687) - OUT1LMIX Input 4 Volume */
{ 0x00000688, 0x0000 }, /* R1672 (0x688) - OUT1RMIX Input 1 Source */
{ 0x00000689, 0x0080 }, /* R1673 (0x689) - OUT1RMIX Input 1 Volume */
{ 0x0000068a, 0x0000 }, /* R1674 (0x68a) - OUT1RMIX Input 2 Source */
{ 0x0000068b, 0x0080 }, /* R1675 (0x68b) - OUT1RMIX Input 2 Volume */
{ 0x0000068c, 0x0000 }, /* R1672 (0x68c) - OUT1RMIX Input 3 Source */
{ 0x0000068d, 0x0080 }, /* R1673 (0x68d) - OUT1RMIX Input 3 Volume */
{ 0x0000068e, 0x0000 }, /* R1674 (0x68e) - OUT1RMIX Input 4 Source */
{ 0x0000068f, 0x0080 }, /* R1675 (0x68f) - OUT1RMIX Input 4 Volume */
{ 0x00000690, 0x0000 }, /* R1680 (0x690) - OUT2LMIX Input 1 Source */
{ 0x00000691, 0x0080 }, /* R1681 (0x691) - OUT2LMIX Input 1 Volume */
{ 0x00000692, 0x0000 }, /* R1682 (0x692) - OUT2LMIX Input 2 Source */
{ 0x00000693, 0x0080 }, /* R1683 (0x693) - OUT2LMIX Input 2 Volume */
{ 0x00000694, 0x0000 }, /* R1684 (0x694) - OUT2LMIX Input 3 Source */
{ 0x00000695, 0x0080 }, /* R1685 (0x695) - OUT2LMIX Input 3 Volume */
{ 0x00000696, 0x0000 }, /* R1686 (0x696) - OUT2LMIX Input 4 Source */
{ 0x00000697, 0x0080 }, /* R1687 (0x697) - OUT2LMIX Input 4 Volume */
{ 0x00000698, 0x0000 }, /* R1688 (0x698) - OUT2RMIX Input 1 Source */
{ 0x00000699, 0x0080 }, /* R1689 (0x699) - OUT2RMIX Input 1 Volume */
{ 0x0000069a, 0x0000 }, /* R1690 (0x69a) - OUT2RMIX Input 2 Source */
{ 0x0000069b, 0x0080 }, /* R1691 (0x69b) - OUT2RMIX Input 2 Volume */
{ 0x0000069c, 0x0000 }, /* R1692 (0x69c) - OUT2RMIX Input 3 Source */
{ 0x0000069d, 0x0080 }, /* R1693 (0x69d) - OUT2RMIX Input 3 Volume */
{ 0x0000069e, 0x0000 }, /* R1694 (0x69e) - OUT2RMIX Input 4 Source */
{ 0x0000069f, 0x0080 }, /* R1695 (0x69f) - OUT2RMIX Input 4 Volume */
{ 0x000006a0, 0x0000 }, /* R1696 (0x6a0) - OUT3LMIX Input 1 Source */
{ 0x000006a1, 0x0080 }, /* R1697 (0x6a1) - OUT3LMIX Input 1 Volume */
{ 0x000006a2, 0x0000 }, /* R1698 (0x6a2) - OUT3LMIX Input 2 Source */
{ 0x000006a3, 0x0080 }, /* R1699 (0x6a3) - OUT3LMIX Input 2 Volume */
{ 0x000006a4, 0x0000 }, /* R1700 (0x6a4) - OUT3LMIX Input 3 Source */
{ 0x000006a5, 0x0080 }, /* R1701 (0x6a5) - OUT3LMIX Input 3 Volume */
{ 0x000006a6, 0x0000 }, /* R1702 (0x6a6) - OUT3LMIX Input 4 Source */
{ 0x000006a7, 0x0080 }, /* R1703 (0x6a7) - OUT3LMIX Input 4 Volume */
{ 0x000006a8, 0x0000 }, /* R1704 (0x6a8) - OUT3RMIX Input 1 Source */
{ 0x000006a9, 0x0080 }, /* R1705 (0x6a9) - OUT3RMIX Input 1 Volume */
{ 0x000006aa, 0x0000 }, /* R1706 (0x6aa) - OUT3RMIX Input 2 Source */
{ 0x000006ab, 0x0080 }, /* R1707 (0x6ab) - OUT3RMIX Input 2 Volume */
{ 0x000006ac, 0x0000 }, /* R1708 (0x6ac) - OUT3RMIX Input 3 Source */
{ 0x000006ad, 0x0080 }, /* R1709 (0x6ad) - OUT3RMIX Input 3 Volume */
{ 0x000006ae, 0x0000 }, /* R1710 (0x6ae) - OUT3RMIX Input 4 Source */
{ 0x000006af, 0x0080 }, /* R1711 (0x6af) - OUT3RMIX Input 4 Volume */
{ 0x000006c0, 0x0000 }, /* R1728 (0x6c0) - OUT5LMIX Input 1 Source */
{ 0x000006c1, 0x0080 }, /* R1729 (0x6c1) - OUT5LMIX Input 1 Volume */
{ 0x000006c2, 0x0000 }, /* R1730 (0x6c2) - OUT5LMIX Input 2 Source */
{ 0x000006c3, 0x0080 }, /* R1731 (0x6c3) - OUT5LMIX Input 2 Volume */
{ 0x000006c4, 0x0000 }, /* R1732 (0x6c4) - OUT5LMIX Input 3 Source */
{ 0x000006c5, 0x0080 }, /* R1733 (0x6c5) - OUT5LMIX Input 3 Volume */
{ 0x000006c6, 0x0000 }, /* R1734 (0x6c6) - OUT5LMIX Input 4 Source */
{ 0x000006c7, 0x0080 }, /* R1735 (0x6c7) - OUT5LMIX Input 4 Volume */
{ 0x000006c8, 0x0000 }, /* R1736 (0x6c8) - OUT5RMIX Input 1 Source */
{ 0x000006c9, 0x0080 }, /* R1737 (0x6c9) - OUT5RMIX Input 1 Volume */
{ 0x000006ca, 0x0000 }, /* R1738 (0x6ca) - OUT5RMIX Input 2 Source */
{ 0x000006cb, 0x0080 }, /* R1739 (0x6cb) - OUT5RMIX Input 2 Volume */
{ 0x000006cc, 0x0000 }, /* R1740 (0x6cc) - OUT5RMIX Input 3 Source */
{ 0x000006cd, 0x0080 }, /* R1741 (0x6cd) - OUT5RMIX Input 3 Volume */
{ 0x000006ce, 0x0000 }, /* R1742 (0x6ce) - OUT5RMIX Input 4 Source */
{ 0x000006cf, 0x0080 }, /* R1743 (0x6cf) - OUT5RMIX Input 4 Volume */
{ 0x00000700, 0x0000 }, /* R1792 (0x700) - AIF1TX1MIX Input 1 Source */
{ 0x00000701, 0x0080 }, /* R1793 (0x701) - AIF1TX1MIX Input 1 Volume */
{ 0x00000702, 0x0000 }, /* R1794 (0x702) - AIF1TX1MIX Input 2 Source */
{ 0x00000703, 0x0080 }, /* R1795 (0x703) - AIF1TX1MIX Input 2 Volume */
{ 0x00000704, 0x0000 }, /* R1796 (0x704) - AIF1TX1MIX Input 3 Source */
{ 0x00000705, 0x0080 }, /* R1797 (0x705) - AIF1TX1MIX Input 3 Volume */
{ 0x00000706, 0x0000 }, /* R1798 (0x706) - AIF1TX1MIX Input 4 Source */
{ 0x00000707, 0x0080 }, /* R1799 (0x707) - AIF1TX1MIX Input 4 Volume */
{ 0x00000708, 0x0000 }, /* R1800 (0x708) - AIF1TX2MIX Input 1 Source */
{ 0x00000709, 0x0080 }, /* R1801 (0x709) - AIF1TX2MIX Input 1 Volume */
{ 0x0000070a, 0x0000 }, /* R1802 (0x70a) - AIF1TX2MIX Input 2 Source */
{ 0x0000070b, 0x0080 }, /* R1803 (0x70b) - AIF1TX2MIX Input 2 Volume */
{ 0x0000070c, 0x0000 }, /* R1804 (0x70c) - AIF1TX2MIX Input 3 Source */
{ 0x0000070d, 0x0080 }, /* R1805 (0x70d) - AIF1TX2MIX Input 3 Volume */
{ 0x0000070e, 0x0000 }, /* R1806 (0x70e) - AIF1TX2MIX Input 4 Source */
{ 0x0000070f, 0x0080 }, /* R1807 (0x70f) - AIF1TX2MIX Input 4 Volume */
{ 0x00000710, 0x0000 }, /* R1808 (0x710) - AIF1TX3MIX Input 1 Source */
{ 0x00000711, 0x0080 }, /* R1809 (0x711) - AIF1TX3MIX Input 1 Volume */
{ 0x00000712, 0x0000 }, /* R1810 (0x712) - AIF1TX3MIX Input 2 Source */
{ 0x00000713, 0x0080 }, /* R1811 (0x713) - AIF1TX3MIX Input 2 Volume */
{ 0x00000714, 0x0000 }, /* R1812 (0x714) - AIF1TX3MIX Input 3 Source */
{ 0x00000715, 0x0080 }, /* R1813 (0x715) - AIF1TX3MIX Input 3 Volume */
{ 0x00000716, 0x0000 }, /* R1814 (0x716) - AIF1TX3MIX Input 4 Source */
{ 0x00000717, 0x0080 }, /* R1815 (0x717) - AIF1TX3MIX Input 4 Volume */
{ 0x00000718, 0x0000 }, /* R1816 (0x718) - AIF1TX4MIX Input 1 Source */
{ 0x00000719, 0x0080 }, /* R1817 (0x719) - AIF1TX4MIX Input 1 Volume */
{ 0x0000071a, 0x0000 }, /* R1818 (0x71a) - AIF1TX4MIX Input 2 Source */
{ 0x0000071b, 0x0080 }, /* R1819 (0x71b) - AIF1TX4MIX Input 2 Volume */
{ 0x0000071c, 0x0000 }, /* R1820 (0x71c) - AIF1TX4MIX Input 3 Source */
{ 0x0000071d, 0x0080 }, /* R1821 (0x71d) - AIF1TX4MIX Input 3 Volume */
{ 0x0000071e, 0x0000 }, /* R1822 (0x71e) - AIF1TX4MIX Input 4 Source */
{ 0x0000071f, 0x0080 }, /* R1823 (0x71f) - AIF1TX4MIX Input 4 Volume */
{ 0x00000720, 0x0000 }, /* R1824 (0x720) - AIF1TX5MIX Input 1 Source */
{ 0x00000721, 0x0080 }, /* R1825 (0x721) - AIF1TX5MIX Input 1 Volume */
{ 0x00000722, 0x0000 }, /* R1826 (0x722) - AIF1TX5MIX Input 2 Source */
{ 0x00000723, 0x0080 }, /* R1827 (0x723) - AIF1TX5MIX Input 2 Volume */
{ 0x00000724, 0x0000 }, /* R1828 (0x724) - AIF1TX5MIX Input 3 Source */
{ 0x00000725, 0x0080 }, /* R1829 (0x725) - AIF1TX5MIX Input 3 Volume */
{ 0x00000726, 0x0000 }, /* R1830 (0x726) - AIF1TX5MIX Input 4 Source */
{ 0x00000727, 0x0080 }, /* R1831 (0x727) - AIF1TX5MIX Input 4 Volume */
{ 0x00000728, 0x0000 }, /* R1832 (0x728) - AIF1TX6MIX Input 1 Source */
{ 0x00000729, 0x0080 }, /* R1833 (0x729) - AIF1TX6MIX Input 1 Volume */
{ 0x0000072a, 0x0000 }, /* R1834 (0x72a) - AIF1TX6MIX Input 2 Source */
{ 0x0000072b, 0x0080 }, /* R1835 (0x72b) - AIF1TX6MIX Input 2 Volume */
{ 0x0000072c, 0x0000 }, /* R1836 (0x72c) - AIF1TX6MIX Input 3 Source */
{ 0x0000072d, 0x0080 }, /* R1837 (0x72d) - AIF1TX6MIX Input 3 Volume */
{ 0x0000072e, 0x0000 }, /* R1838 (0x72e) - AIF1TX6MIX Input 4 Source */
{ 0x0000072f, 0x0080 }, /* R1839 (0x72f) - AIF1TX6MIX Input 4 Volume */
{ 0x00000730, 0x0000 }, /* R1840 (0x730) - AIF1TX7MIX Input 1 Source */
{ 0x00000731, 0x0080 }, /* R1841 (0x731) - AIF1TX7MIX Input 1 Volume */
{ 0x00000732, 0x0000 }, /* R1842 (0x732) - AIF1TX7MIX Input 2 Source */
{ 0x00000733, 0x0080 }, /* R1843 (0x733) - AIF1TX7MIX Input 2 Volume */
{ 0x00000734, 0x0000 }, /* R1844 (0x734) - AIF1TX7MIX Input 3 Source */
{ 0x00000735, 0x0080 }, /* R1845 (0x735) - AIF1TX7MIX Input 3 Volume */
{ 0x00000736, 0x0000 }, /* R1846 (0x736) - AIF1TX7MIX Input 4 Source */
{ 0x00000737, 0x0080 }, /* R1847 (0x737) - AIF1TX7MIX Input 4 Volume */
{ 0x00000738, 0x0000 }, /* R1848 (0x738) - AIF1TX8MIX Input 1 Source */
{ 0x00000739, 0x0080 }, /* R1849 (0x739) - AIF1TX8MIX Input 1 Volume */
{ 0x0000073a, 0x0000 }, /* R1850 (0x73a) - AIF1TX8MIX Input 2 Source */
{ 0x0000073b, 0x0080 }, /* R1851 (0x73b) - AIF1TX8MIX Input 2 Volume */
{ 0x0000073c, 0x0000 }, /* R1852 (0x73c) - AIF1TX8MIX Input 3 Source */
{ 0x0000073d, 0x0080 }, /* R1853 (0x73d) - AIF1TX8MIX Input 3 Volume */
{ 0x0000073e, 0x0000 }, /* R1854 (0x73e) - AIF1TX8MIX Input 4 Source */
{ 0x0000073f, 0x0080 }, /* R1855 (0x73f) - AIF1TX8MIX Input 4 Volume */
{ 0x00000740, 0x0000 }, /* R1856 (0x740) - AIF2TX1MIX Input 1 Source */
{ 0x00000741, 0x0080 }, /* R1857 (0x741) - AIF2TX1MIX Input 1 Volume */
{ 0x00000742, 0x0000 }, /* R1858 (0x742) - AIF2TX1MIX Input 2 Source */
{ 0x00000743, 0x0080 }, /* R1859 (0x743) - AIF2TX1MIX Input 2 Volume */
{ 0x00000744, 0x0000 }, /* R1860 (0x744) - AIF2TX1MIX Input 3 Source */
{ 0x00000745, 0x0080 }, /* R1861 (0x745) - AIF2TX1MIX Input 3 Volume */
{ 0x00000746, 0x0000 }, /* R1862 (0x746) - AIF2TX1MIX Input 4 Source */
{ 0x00000747, 0x0080 }, /* R1863 (0x747) - AIF2TX1MIX Input 4 Volume */
{ 0x00000748, 0x0000 }, /* R1864 (0x748) - AIF2TX2MIX Input 1 Source */
{ 0x00000749, 0x0080 }, /* R1865 (0x749) - AIF2TX2MIX Input 1 Volume */
{ 0x0000074a, 0x0000 }, /* R1866 (0x74a) - AIF2TX2MIX Input 2 Source */
{ 0x0000074b, 0x0080 }, /* R1867 (0x74b) - AIF2TX2MIX Input 2 Volume */
{ 0x0000074c, 0x0000 }, /* R1868 (0x74c) - AIF2TX2MIX Input 3 Source */
{ 0x0000074d, 0x0080 }, /* R1869 (0x74d) - AIF2TX2MIX Input 3 Volume */
{ 0x0000074e, 0x0000 }, /* R1870 (0x74e) - AIF2TX2MIX Input 4 Source */
{ 0x0000074f, 0x0080 }, /* R1871 (0x74f) - AIF2TX2MIX Input 4 Volume */
{ 0x00000750, 0x0000 }, /* R1872 (0x750) - AIF2TX3MIX Input 1 Source */
{ 0x00000751, 0x0080 }, /* R1873 (0x751) - AIF2TX3MIX Input 1 Volume */
{ 0x00000752, 0x0000 }, /* R1874 (0x752) - AIF2TX3MIX Input 2 Source */
{ 0x00000753, 0x0080 }, /* R1875 (0x753) - AIF2TX3MIX Input 2 Volume */
{ 0x00000754, 0x0000 }, /* R1876 (0x754) - AIF2TX3MIX Input 3 Source */
{ 0x00000755, 0x0080 }, /* R1877 (0x755) - AIF2TX3MIX Input 3 Volume */
{ 0x00000756, 0x0000 }, /* R1878 (0x756) - AIF2TX3MIX Input 4 Source */
{ 0x00000757, 0x0080 }, /* R1879 (0x757) - AIF2TX3MIX Input 4 Volume */
{ 0x00000758, 0x0000 }, /* R1880 (0x758) - AIF2TX4MIX Input 1 Source */
{ 0x00000759, 0x0080 }, /* R1881 (0x759) - AIF2TX4MIX Input 1 Volume */
{ 0x0000075a, 0x0000 }, /* R1882 (0x75a) - AIF2TX4MIX Input 2 Source */
{ 0x0000075b, 0x0080 }, /* R1883 (0x75b) - AIF2TX4MIX Input 2 Volume */
{ 0x0000075c, 0x0000 }, /* R1884 (0x75c) - AIF2TX4MIX Input 3 Source */
{ 0x0000075d, 0x0080 }, /* R1885 (0x75d) - AIF2TX4MIX Input 3 Volume */
{ 0x0000075e, 0x0000 }, /* R1886 (0x75e) - AIF2TX4MIX Input 4 Source */
{ 0x0000075f, 0x0080 }, /* R1887 (0x75f) - AIF2TX4MIX Input 4 Volume */
{ 0x00000760, 0x0000 }, /* R1888 (0x760) - AIF2TX5MIX Input 1 Source */
{ 0x00000761, 0x0080 }, /* R1889 (0x761) - AIF2TX5MIX Input 1 Volume */
{ 0x00000762, 0x0000 }, /* R1890 (0x762) - AIF2TX5MIX Input 2 Source */
{ 0x00000763, 0x0080 }, /* R1891 (0x763) - AIF2TX5MIX Input 2 Volume */
{ 0x00000764, 0x0000 }, /* R1892 (0x764) - AIF2TX5MIX Input 3 Source */
{ 0x00000765, 0x0080 }, /* R1893 (0x765) - AIF2TX5MIX Input 3 Volume */
{ 0x00000766, 0x0000 }, /* R1894 (0x766) - AIF2TX5MIX Input 4 Source */
{ 0x00000767, 0x0080 }, /* R1895 (0x767) - AIF2TX5MIX Input 4 Volume */
{ 0x00000768, 0x0000 }, /* R1896 (0x768) - AIF2TX6MIX Input 1 Source */
{ 0x00000769, 0x0080 }, /* R1897 (0x769) - AIF2TX6MIX Input 1 Volume */
{ 0x0000076a, 0x0000 }, /* R1898 (0x76a) - AIF2TX6MIX Input 2 Source */
{ 0x0000076b, 0x0080 }, /* R1899 (0x76b) - AIF2TX6MIX Input 2 Volume */
{ 0x0000076c, 0x0000 }, /* R1900 (0x76c) - AIF2TX6MIX Input 3 Source */
{ 0x0000076d, 0x0080 }, /* R1901 (0x76d) - AIF2TX6MIX Input 3 Volume */
{ 0x0000076e, 0x0000 }, /* R1902 (0x76e) - AIF2TX6MIX Input 4 Source */
{ 0x0000076f, 0x0080 }, /* R1903 (0x76f) - AIF2TX6MIX Input 4 Volume */
{ 0x00000770, 0x0000 }, /* R1904 (0x770) - AIF2TX7MIX Input 1 Source */
{ 0x00000771, 0x0080 }, /* R1905 (0x771) - AIF2TX7MIX Input 1 Volume */
{ 0x00000772, 0x0000 }, /* R1906 (0x772) - AIF2TX7MIX Input 2 Source */
{ 0x00000773, 0x0080 }, /* R1907 (0x773) - AIF2TX7MIX Input 2 Volume */
{ 0x00000774, 0x0000 }, /* R1908 (0x774) - AIF2TX7MIX Input 3 Source */
{ 0x00000775, 0x0080 }, /* R1909 (0x775) - AIF2TX7MIX Input 3 Volume */
{ 0x00000776, 0x0000 }, /* R1910 (0x776) - AIF2TX7MIX Input 4 Source */
{ 0x00000777, 0x0080 }, /* R1911 (0x777) - AIF2TX7MIX Input 4 Volume */
{ 0x00000778, 0x0000 }, /* R1912 (0x778) - AIF2TX8MIX Input 1 Source */
{ 0x00000779, 0x0080 }, /* R1913 (0x779) - AIF2TX8MIX Input 1 Volume */
{ 0x0000077a, 0x0000 }, /* R1914 (0x77a) - AIF2TX8MIX Input 2 Source */
{ 0x0000077b, 0x0080 }, /* R1915 (0x77b) - AIF2TX8MIX Input 2 Volume */
{ 0x0000077c, 0x0000 }, /* R1916 (0x77c) - AIF2TX8MIX Input 3 Source */
{ 0x0000077d, 0x0080 }, /* R1917 (0x77d) - AIF2TX8MIX Input 3 Volume */
{ 0x0000077e, 0x0000 }, /* R1918 (0x77e) - AIF2TX8MIX Input 4 Source */
{ 0x0000077f, 0x0080 }, /* R1919 (0x77f) - AIF2TX8MIX Input 4 Volume */
{ 0x00000780, 0x0000 }, /* R1920 (0x780) - AIF3TX1MIX Input 1 Source */
{ 0x00000781, 0x0080 }, /* R1921 (0x781) - AIF3TX1MIX Input 1 Volume */
{ 0x00000782, 0x0000 }, /* R1922 (0x782) - AIF3TX1MIX Input 2 Source */
{ 0x00000783, 0x0080 }, /* R1923 (0x783) - AIF3TX1MIX Input 2 Volume */
{ 0x00000784, 0x0000 }, /* R1924 (0x784) - AIF3TX1MIX Input 3 Source */
{ 0x00000785, 0x0080 }, /* R1925 (0x785) - AIF3TX1MIX Input 3 Volume */
{ 0x00000786, 0x0000 }, /* R1926 (0x786) - AIF3TX1MIX Input 4 Source */
{ 0x00000787, 0x0080 }, /* R1927 (0x787) - AIF3TX1MIX Input 4 Volume */
{ 0x00000788, 0x0000 }, /* R1928 (0x788) - AIF3TX2MIX Input 1 Source */
{ 0x00000789, 0x0080 }, /* R1929 (0x789) - AIF3TX2MIX Input 1 Volume */
{ 0x0000078a, 0x0000 }, /* R1930 (0x78a) - AIF3TX2MIX Input 2 Source */
{ 0x0000078b, 0x0080 }, /* R1931 (0x78b) - AIF3TX2MIX Input 2 Volume */
{ 0x0000078c, 0x0000 }, /* R1932 (0x78c) - AIF3TX2MIX Input 3 Source */
{ 0x0000078d, 0x0080 }, /* R1933 (0x78d) - AIF3TX2MIX Input 3 Volume */
{ 0x0000078e, 0x0000 }, /* R1934 (0x78e) - AIF3TX2MIX Input 4 Source */
{ 0x0000078f, 0x0080 }, /* R1935 (0x78f) - AIF3TX2MIX Input 4 Volume */
{ 0x000007a0, 0x0000 }, /* R1952 (0x7a0) - AIF4TX1MIX Input 1 Source */
{ 0x000007a1, 0x0080 }, /* R1953 (0x7a1) - AIF4TX1MIX Input 1 Volume */
{ 0x000007a2, 0x0000 }, /* R1954 (0x7a2) - AIF4TX1MIX Input 2 Source */
{ 0x000007a3, 0x0080 }, /* R1955 (0x7a3) - AIF4TX1MIX Input 2 Volume */
{ 0x000007a4, 0x0000 }, /* R1956 (0x7a4) - AIF4TX1MIX Input 3 Source */
{ 0x000007a5, 0x0080 }, /* R1957 (0x7a5) - AIF4TX1MIX Input 3 Volume */
{ 0x000007a6, 0x0000 }, /* R1958 (0x7a6) - AIF4TX1MIX Input 4 Source */
{ 0x000007a7, 0x0080 }, /* R1959 (0x7a7) - AIF4TX1MIX Input 4 Volume */
{ 0x000007a8, 0x0000 }, /* R1960 (0x7a8) - AIF4TX2MIX Input 1 Source */
{ 0x000007a9, 0x0080 }, /* R1961 (0x7a9) - AIF4TX2MIX Input 1 Volume */
{ 0x000007aa, 0x0000 }, /* R1962 (0x7aa) - AIF4TX2MIX Input 2 Source */
{ 0x000007ab, 0x0080 }, /* R1963 (0x7ab) - AIF4TX2MIX Input 2 Volume */
{ 0x000007ac, 0x0000 }, /* R1964 (0x7ac) - AIF4TX2MIX Input 3 Source */
{ 0x000007ad, 0x0080 }, /* R1965 (0x7ad) - AIF4TX2MIX Input 3 Volume */
{ 0x000007ae, 0x0000 }, /* R1966 (0x7ae) - AIF4TX2MIX Input 4 Source */
{ 0x000007af, 0x0080 }, /* R1967 (0x7af) - AIF4TX2MIX Input 4 Volume */
{ 0x000007c0, 0x0000 }, /* R1984 (0x7c0) - SLIMTX1MIX Input 1 Source */
{ 0x000007c1, 0x0080 }, /* R1985 (0x7c1) - SLIMTX1MIX Input 1 Volume */
{ 0x000007c2, 0x0000 }, /* R1986 (0x7c2) - SLIMTX1MIX Input 2 Source */
{ 0x000007c3, 0x0080 }, /* R1987 (0x7c3) - SLIMTX1MIX Input 2 Volume */
{ 0x000007c4, 0x0000 }, /* R1988 (0x7c4) - SLIMTX1MIX Input 3 Source */
{ 0x000007c5, 0x0080 }, /* R1989 (0x7c5) - SLIMTX1MIX Input 3 Volume */
{ 0x000007c6, 0x0000 }, /* R1990 (0x7c6) - SLIMTX1MIX Input 4 Source */
{ 0x000007c7, 0x0080 }, /* R1991 (0x7c7) - SLIMTX1MIX Input 4 Volume */
{ 0x000007c8, 0x0000 }, /* R1992 (0x7c8) - SLIMTX2MIX Input 1 Source */
{ 0x000007c9, 0x0080 }, /* R1993 (0x7c9) - SLIMTX2MIX Input 1 Volume */
{ 0x000007ca, 0x0000 }, /* R1994 (0x7ca) - SLIMTX2MIX Input 2 Source */
{ 0x000007cb, 0x0080 }, /* R1995 (0x7cb) - SLIMTX2MIX Input 2 Volume */
{ 0x000007cc, 0x0000 }, /* R1996 (0x7cc) - SLIMTX2MIX Input 3 Source */
{ 0x000007cd, 0x0080 }, /* R1997 (0x7cd) - SLIMTX2MIX Input 3 Volume */
{ 0x000007ce, 0x0000 }, /* R1998 (0x7ce) - SLIMTX2MIX Input 4 Source */
{ 0x000007cf, 0x0080 }, /* R1999 (0x7cf) - SLIMTX2MIX Input 4 Volume */
{ 0x000007d0, 0x0000 }, /* R2000 (0x7d0) - SLIMTX3MIX Input 1 Source */
{ 0x000007d1, 0x0080 }, /* R2001 (0x7d1) - SLIMTX3MIX Input 1 Volume */
{ 0x000007d2, 0x0000 }, /* R2002 (0x7d2) - SLIMTX3MIX Input 2 Source */
{ 0x000007d3, 0x0080 }, /* R2003 (0x7d3) - SLIMTX3MIX Input 2 Volume */
{ 0x000007d4, 0x0000 }, /* R2004 (0x7d4) - SLIMTX3MIX Input 3 Source */
{ 0x000007d5, 0x0080 }, /* R2005 (0x7d5) - SLIMTX3MIX Input 3 Volume */
{ 0x000007d6, 0x0000 }, /* R2006 (0x7d6) - SLIMTX3MIX Input 4 Source */
{ 0x000007d7, 0x0080 }, /* R2007 (0x7d7) - SLIMTX3MIX Input 4 Volume */
{ 0x000007d8, 0x0000 }, /* R2008 (0x7d8) - SLIMTX4MIX Input 1 Source */
{ 0x000007d9, 0x0080 }, /* R2009 (0x7d9) - SLIMTX4MIX Input 1 Volume */
{ 0x000007da, 0x0000 }, /* R2010 (0x7da) - SLIMTX4MIX Input 2 Source */
{ 0x000007db, 0x0080 }, /* R2011 (0x7db) - SLIMTX4MIX Input 2 Volume */
{ 0x000007dc, 0x0000 }, /* R2012 (0x7dc) - SLIMTX4MIX Input 3 Source */
{ 0x000007dd, 0x0080 }, /* R2013 (0x7dd) - SLIMTX4MIX Input 3 Volume */
{ 0x000007de, 0x0000 }, /* R2014 (0x7de) - SLIMTX4MIX Input 4 Source */
{ 0x000007df, 0x0080 }, /* R2015 (0x7df) - SLIMTX4MIX Input 4 Volume */
{ 0x000007e0, 0x0000 }, /* R2016 (0x7e0) - SLIMTX5MIX Input 1 Source */
{ 0x000007e1, 0x0080 }, /* R2017 (0x7e1) - SLIMTX5MIX Input 1 Volume */
{ 0x000007e2, 0x0000 }, /* R2018 (0x7e2) - SLIMTX5MIX Input 2 Source */
{ 0x000007e3, 0x0080 }, /* R2019 (0x7e3) - SLIMTX5MIX Input 2 Volume */
{ 0x000007e4, 0x0000 }, /* R2020 (0x7e4) - SLIMTX5MIX Input 3 Source */
{ 0x000007e5, 0x0080 }, /* R2021 (0x7e5) - SLIMTX5MIX Input 3 Volume */
{ 0x000007e6, 0x0000 }, /* R2022 (0x7e6) - SLIMTX5MIX Input 4 Source */
{ 0x000007e7, 0x0080 }, /* R2023 (0x7e7) - SLIMTX5MIX Input 4 Volume */
{ 0x000007e8, 0x0000 }, /* R2024 (0x7e8) - SLIMTX6MIX Input 1 Source */
{ 0x000007e9, 0x0080 }, /* R2025 (0x7e9) - SLIMTX6MIX Input 1 Volume */
{ 0x000007ea, 0x0000 }, /* R2026 (0x7ea) - SLIMTX6MIX Input 2 Source */
{ 0x000007eb, 0x0080 }, /* R2027 (0x7eb) - SLIMTX6MIX Input 2 Volume */
{ 0x000007ec, 0x0000 }, /* R2028 (0x7ec) - SLIMTX6MIX Input 3 Source */
{ 0x000007ed, 0x0080 }, /* R2029 (0x7ed) - SLIMTX6MIX Input 3 Volume */
{ 0x000007ee, 0x0000 }, /* R2030 (0x7ee) - SLIMTX6MIX Input 4 Source */
{ 0x000007ef, 0x0080 }, /* R2031 (0x7ef) - SLIMTX6MIX Input 4 Volume */
{ 0x000007f0, 0x0000 }, /* R2032 (0x7f0) - SLIMTX7MIX Input 1 Source */
{ 0x000007f1, 0x0080 }, /* R2033 (0x7f1) - SLIMTX7MIX Input 1 Volume */
{ 0x000007f2, 0x0000 }, /* R2034 (0x7f2) - SLIMTX7MIX Input 2 Source */
{ 0x000007f3, 0x0080 }, /* R2035 (0x7f3) - SLIMTX7MIX Input 2 Volume */
{ 0x000007f4, 0x0000 }, /* R2036 (0x7f4) - SLIMTX7MIX Input 3 Source */
{ 0x000007f5, 0x0080 }, /* R2037 (0x7f5) - SLIMTX7MIX Input 3 Volume */
{ 0x000007f6, 0x0000 }, /* R2038 (0x7f6) - SLIMTX7MIX Input 4 Source */
{ 0x000007f7, 0x0080 }, /* R2039 (0x7f7) - SLIMTX7MIX Input 4 Volume */
{ 0x000007f8, 0x0000 }, /* R2040 (0x7f8) - SLIMTX8MIX Input 1 Source */
{ 0x000007f9, 0x0080 }, /* R2041 (0x7f9) - SLIMTX8MIX Input 1 Volume */
{ 0x000007fa, 0x0000 }, /* R2042 (0x7fa) - SLIMTX8MIX Input 2 Source */
{ 0x000007fb, 0x0080 }, /* R2043 (0x7fb) - SLIMTX8MIX Input 2 Volume */
{ 0x000007fc, 0x0000 }, /* R2044 (0x7fc) - SLIMTX8MIX Input 3 Source */
{ 0x000007fd, 0x0080 }, /* R2045 (0x7fd) - SLIMTX8MIX Input 3 Volume */
{ 0x000007fe, 0x0000 }, /* R2046 (0x7fe) - SLIMTX8MIX Input 4 Source */
{ 0x000007ff, 0x0080 }, /* R2047 (0x7ff) - SLIMTX8MIX Input 4 Volume */
{ 0x00000800, 0x0000 }, /* R2048 (0x800) - SPDIF1TX1MIX Input 1 Source */
{ 0x00000801, 0x0080 }, /* R2049 (0x801) - SPDIF1TX1MIX Input 1 Volume */
{ 0x00000808, 0x0000 }, /* R2056 (0x808) - SPDIF1TX2MIX Input 1 Source */
{ 0x00000809, 0x0080 }, /* R2057 (0x809) - SPDIF1TX2MIX Input 1 Volume */
{ 0x00000880, 0x0000 }, /* R2176 (0x880) - EQ1MIX Input 1 Source */
{ 0x00000881, 0x0080 }, /* R2177 (0x881) - EQ1MIX Input 1 Volume */
{ 0x00000882, 0x0000 }, /* R2178 (0x882) - EQ1MIX Input 2 Source */
{ 0x00000883, 0x0080 }, /* R2179 (0x883) - EQ1MIX Input 2 Volume */
{ 0x00000884, 0x0000 }, /* R2180 (0x884) - EQ1MIX Input 3 Source */
{ 0x00000885, 0x0080 }, /* R2181 (0x885) - EQ1MIX Input 3 Volume */
{ 0x00000886, 0x0000 }, /* R2182 (0x886) - EQ1MIX Input 4 Source */
{ 0x00000887, 0x0080 }, /* R2183 (0x887) - EQ1MIX Input 4 Volume */
{ 0x00000888, 0x0000 }, /* R2184 (0x888) - EQ2MIX Input 1 Source */
{ 0x00000889, 0x0080 }, /* R2185 (0x889) - EQ2MIX Input 1 Volume */
{ 0x0000088a, 0x0000 }, /* R2186 (0x88a) - EQ2MIX Input 2 Source */
{ 0x0000088b, 0x0080 }, /* R2187 (0x88b) - EQ2MIX Input 2 Volume */
{ 0x0000088c, 0x0000 }, /* R2188 (0x88c) - EQ2MIX Input 3 Source */
{ 0x0000088d, 0x0080 }, /* R2189 (0x88d) - EQ2MIX Input 3 Volume */
{ 0x0000088e, 0x0000 }, /* R2190 (0x88e) - EQ2MIX Input 4 Source */
{ 0x0000088f, 0x0080 }, /* R2191 (0x88f) - EQ2MIX Input 4 Volume */
{ 0x00000890, 0x0000 }, /* R2192 (0x890) - EQ3MIX Input 1 Source */
{ 0x00000891, 0x0080 }, /* R2193 (0x891) - EQ3MIX Input 1 Volume */
{ 0x00000892, 0x0000 }, /* R2194 (0x892) - EQ3MIX Input 2 Source */
{ 0x00000893, 0x0080 }, /* R2195 (0x893) - EQ3MIX Input 2 Volume */
{ 0x00000894, 0x0000 }, /* R2196 (0x894) - EQ3MIX Input 3 Source */
{ 0x00000895, 0x0080 }, /* R2197 (0x895) - EQ3MIX Input 3 Volume */
{ 0x00000896, 0x0000 }, /* R2198 (0x896) - EQ3MIX Input 4 Source */
{ 0x00000897, 0x0080 }, /* R2199 (0x897) - EQ3MIX Input 4 Volume */
{ 0x00000898, 0x0000 }, /* R2200 (0x898) - EQ4MIX Input 1 Source */
{ 0x00000899, 0x0080 }, /* R2201 (0x899) - EQ4MIX Input 1 Volume */
{ 0x0000089a, 0x0000 }, /* R2202 (0x89a) - EQ4MIX Input 2 Source */
{ 0x0000089b, 0x0080 }, /* R2203 (0x89b) - EQ4MIX Input 2 Volume */
{ 0x0000089c, 0x0000 }, /* R2204 (0x89c) - EQ4MIX Input 3 Source */
{ 0x0000089d, 0x0080 }, /* R2205 (0x89d) - EQ4MIX Input 3 Volume */
{ 0x0000089e, 0x0000 }, /* R2206 (0x89e) - EQ4MIX Input 4 Source */
{ 0x0000089f, 0x0080 }, /* R2207 (0x89f) - EQ4MIX Input 4 Volume */
{ 0x000008c0, 0x0000 }, /* R2240 (0x8c0) - DRC1LMIX Input 1 Source */
{ 0x000008c1, 0x0080 }, /* R2241 (0x8c1) - DRC1LMIX Input 1 Volume */
{ 0x000008c2, 0x0000 }, /* R2242 (0x8c2) - DRC1LMIX Input 2 Source */
{ 0x000008c3, 0x0080 }, /* R2243 (0x8c3) - DRC1LMIX Input 2 Volume */
{ 0x000008c4, 0x0000 }, /* R2244 (0x8c4) - DRC1LMIX Input 3 Source */
{ 0x000008c5, 0x0080 }, /* R2245 (0x8c5) - DRC1LMIX Input 3 Volume */
{ 0x000008c6, 0x0000 }, /* R2246 (0x8c6) - DRC1LMIX Input 4 Source */
{ 0x000008c7, 0x0080 }, /* R2247 (0x8c7) - DRC1LMIX Input 4 Volume */
{ 0x000008c8, 0x0000 }, /* R2248 (0x8c8) - DRC1RMIX Input 1 Source */
{ 0x000008c9, 0x0080 }, /* R2249 (0x8c9) - DRC1RMIX Input 1 Volume */
{ 0x000008ca, 0x0000 }, /* R2250 (0x8ca) - DRC1RMIX Input 2 Source */
{ 0x000008cb, 0x0080 }, /* R2251 (0x8cb) - DRC1RMIX Input 2 Volume */
{ 0x000008cc, 0x0000 }, /* R2252 (0x8cc) - DRC1RMIX Input 3 Source */
{ 0x000008cd, 0x0080 }, /* R2253 (0x8cd) - DRC1RMIX Input 3 Volume */
{ 0x000008ce, 0x0000 }, /* R2254 (0x8ce) - DRC1RMIX Input 4 Source */
{ 0x000008cf, 0x0080 }, /* R2255 (0x8cf) - DRC1RMIX Input 4 Volume */
{ 0x000008d0, 0x0000 }, /* R2256 (0x8d0) - DRC2LMIX Input 1 Source */
{ 0x000008d1, 0x0080 }, /* R2257 (0x8d1) - DRC2LMIX Input 1 Volume */
{ 0x000008d2, 0x0000 }, /* R2258 (0x8d2) - DRC2LMIX Input 2 Source */
{ 0x000008d3, 0x0080 }, /* R2259 (0x8d3) - DRC2LMIX Input 2 Volume */
{ 0x000008d4, 0x0000 }, /* R2260 (0x8d4) - DRC2LMIX Input 3 Source */
{ 0x000008d5, 0x0080 }, /* R2261 (0x8d5) - DRC2LMIX Input 3 Volume */
{ 0x000008d6, 0x0000 }, /* R2262 (0x8d6) - DRC2LMIX Input 4 Source */
{ 0x000008d7, 0x0080 }, /* R2263 (0x8d7) - DRC2LMIX Input 4 Volume */
{ 0x000008d8, 0x0000 }, /* R2264 (0x8d8) - DRC2RMIX Input 1 Source */
{ 0x000008d9, 0x0080 }, /* R2265 (0x8d9) - DRC2RMIX Input 1 Volume */
{ 0x000008da, 0x0000 }, /* R2266 (0x8da) - DRC2RMIX Input 2 Source */
{ 0x000008db, 0x0080 }, /* R2267 (0x8db) - DRC2RMIX Input 2 Volume */
{ 0x000008dc, 0x0000 }, /* R2268 (0x8dc) - DRC2RMIX Input 3 Source */
{ 0x000008dd, 0x0080 }, /* R2269 (0x8dd) - DRC2RMIX Input 3 Volume */
{ 0x000008de, 0x0000 }, /* R2270 (0x8de) - DRC2RMIX Input 4 Source */
{ 0x000008df, 0x0080 }, /* R2271 (0x8df) - DRC2RMIX Input 4 Volume */
{ 0x00000900, 0x0000 }, /* R2304 (0x900) - HPLP1MIX Input 1 Source */
{ 0x00000901, 0x0080 }, /* R2305 (0x901) - HPLP1MIX Input 1 Volume */
{ 0x00000902, 0x0000 }, /* R2306 (0x902) - HPLP1MIX Input 2 Source */
{ 0x00000903, 0x0080 }, /* R2307 (0x903) - HPLP1MIX Input 2 Volume */
{ 0x00000904, 0x0000 }, /* R2308 (0x904) - HPLP1MIX Input 3 Source */
{ 0x00000905, 0x0080 }, /* R2309 (0x905) - HPLP1MIX Input 3 Volume */
{ 0x00000906, 0x0000 }, /* R2310 (0x906) - HPLP1MIX Input 4 Source */
{ 0x00000907, 0x0080 }, /* R2311 (0x907) - HPLP1MIX Input 4 Volume */
{ 0x00000908, 0x0000 }, /* R2312 (0x908) - HPLP2MIX Input 1 Source */
{ 0x00000909, 0x0080 }, /* R2313 (0x909) - HPLP2MIX Input 1 Volume */
{ 0x0000090a, 0x0000 }, /* R2314 (0x90a) - HPLP2MIX Input 2 Source */
{ 0x0000090b, 0x0080 }, /* R2315 (0x90b) - HPLP2MIX Input 2 Volume */
{ 0x0000090c, 0x0000 }, /* R2316 (0x90c) - HPLP2MIX Input 3 Source */
{ 0x0000090d, 0x0080 }, /* R2317 (0x90d) - HPLP2MIX Input 3 Volume */
{ 0x0000090e, 0x0000 }, /* R2318 (0x90e) - HPLP2MIX Input 4 Source */
{ 0x0000090f, 0x0080 }, /* R2319 (0x90f) - HPLP2MIX Input 4 Volume */
{ 0x00000910, 0x0000 }, /* R2320 (0x910) - HPLP3MIX Input 1 Source */
{ 0x00000911, 0x0080 }, /* R2321 (0x911) - HPLP3MIX Input 1 Volume */
{ 0x00000912, 0x0000 }, /* R2322 (0x912) - HPLP3MIX Input 2 Source */
{ 0x00000913, 0x0080 }, /* R2323 (0x913) - HPLP3MIX Input 2 Volume */
{ 0x00000914, 0x0000 }, /* R2324 (0x914) - HPLP3MIX Input 3 Source */
{ 0x00000915, 0x0080 }, /* R2325 (0x915) - HPLP3MIX Input 3 Volume */
{ 0x00000916, 0x0000 }, /* R2326 (0x916) - HPLP3MIX Input 4 Source */
{ 0x00000917, 0x0080 }, /* R2327 (0x917) - HPLP3MIX Input 4 Volume */
{ 0x00000918, 0x0000 }, /* R2328 (0x918) - HPLP4MIX Input 1 Source */
{ 0x00000919, 0x0080 }, /* R2329 (0x919) - HPLP4MIX Input 1 Volume */
{ 0x0000091a, 0x0000 }, /* R2330 (0x91a) - HPLP4MIX Input 2 Source */
{ 0x0000091b, 0x0080 }, /* R2331 (0x91b) - HPLP4MIX Input 2 Volume */
{ 0x0000091c, 0x0000 }, /* R2332 (0x91c) - HPLP4MIX Input 3 Source */
{ 0x0000091d, 0x0080 }, /* R2333 (0x91d) - HPLP4MIX Input 3 Volume */
{ 0x0000091e, 0x0000 }, /* R2334 (0x91e) - HPLP4MIX Input 4 Source */
{ 0x0000091f, 0x0080 }, /* R2335 (0x91f) - HPLP4MIX Input 4 Volume */
{ 0x00000940, 0x0000 }, /* R2368 (0x940) - DSP1LMIX Input 1 Source */
{ 0x00000941, 0x0080 }, /* R2369 (0x941) - DSP1LMIX Input 1 Volume */
{ 0x00000942, 0x0000 }, /* R2370 (0x942) - DSP1LMIX Input 2 Source */
{ 0x00000943, 0x0080 }, /* R2371 (0x943) - DSP1LMIX Input 2 Volume */
{ 0x00000944, 0x0000 }, /* R2372 (0x944) - DSP1LMIX Input 3 Source */
{ 0x00000945, 0x0080 }, /* R2373 (0x945) - DSP1LMIX Input 3 Volume */
{ 0x00000946, 0x0000 }, /* R2374 (0x946) - DSP1LMIX Input 4 Source */
{ 0x00000947, 0x0080 }, /* R2375 (0x947) - DSP1LMIX Input 4 Volume */
{ 0x00000948, 0x0000 }, /* R2376 (0x948) - DSP1RMIX Input 1 Source */
{ 0x00000949, 0x0080 }, /* R2377 (0x949) - DSP1RMIX Input 1 Volume */
{ 0x0000094a, 0x0000 }, /* R2378 (0x94a) - DSP1RMIX Input 2 Source */
{ 0x0000094b, 0x0080 }, /* R2379 (0x94b) - DSP1RMIX Input 2 Volume */
{ 0x0000094c, 0x0000 }, /* R2380 (0x94c) - DSP1RMIX Input 3 Source */
{ 0x0000094d, 0x0080 }, /* R2381 (0x94d) - DSP1RMIX Input 3 Volume */
{ 0x0000094e, 0x0000 }, /* R2382 (0x94e) - DSP1RMIX Input 4 Source */
{ 0x0000094f, 0x0080 }, /* R2383 (0x94f) - DSP1RMIX Input 4 Volume */
{ 0x00000950, 0x0000 }, /* R2384 (0x950) - DSP1AUX1MIX Input 1 Source */
{ 0x00000958, 0x0000 }, /* R2392 (0x958) - DSP1AUX2MIX Input 1 Source */
{ 0x00000960, 0x0000 }, /* R2400 (0x960) - DSP1AUX3MIX Input 1 Source */
{ 0x00000968, 0x0000 }, /* R2408 (0x968) - DSP1AUX4MIX Input 1 Source */
{ 0x00000970, 0x0000 }, /* R2416 (0x970) - DSP1AUX5MIX Input 1 Source */
{ 0x00000978, 0x0000 }, /* R2424 (0x978) - DSP1AUX6MIX Input 1 Source */
{ 0x00000980, 0x0000 }, /* R2432 (0x980) - DSP2LMIX Input 1 Source */
{ 0x00000981, 0x0080 }, /* R2433 (0x981) - DSP2LMIX Input 1 Volume */
{ 0x00000982, 0x0000 }, /* R2434 (0x982) - DSP2LMIX Input 2 Source */
{ 0x00000983, 0x0080 }, /* R2435 (0x983) - DSP2LMIX Input 2 Volume */
{ 0x00000984, 0x0000 }, /* R2436 (0x984) - DSP2LMIX Input 3 Source */
{ 0x00000985, 0x0080 }, /* R2437 (0x985) - DSP2LMIX Input 3 Volume */
{ 0x00000986, 0x0000 }, /* R2438 (0x986) - DSP2LMIX Input 4 Source */
{ 0x00000987, 0x0080 }, /* R2439 (0x987) - DSP2LMIX Input 4 Volume */
{ 0x00000988, 0x0000 }, /* R2440 (0x988) - DSP2RMIX Input 1 Source */
{ 0x00000989, 0x0080 }, /* R2441 (0x989) - DSP2RMIX Input 1 Volume */
{ 0x0000098a, 0x0000 }, /* R2442 (0x98a) - DSP2RMIX Input 2 Source */
{ 0x0000098b, 0x0080 }, /* R2443 (0x98b) - DSP2RMIX Input 2 Volume */
{ 0x0000098c, 0x0000 }, /* R2444 (0x98c) - DSP2RMIX Input 3 Source */
{ 0x0000098d, 0x0080 }, /* R2445 (0x98d) - DSP2RMIX Input 3 Volume */
{ 0x0000098e, 0x0000 }, /* R2446 (0x98e) - DSP2RMIX Input 4 Source */
{ 0x0000098f, 0x0080 }, /* R2447 (0x98f) - DSP2RMIX Input 4 Volume */
{ 0x00000990, 0x0000 }, /* R2448 (0x990) - DSP2AUX1MIX Input 1 Source */
{ 0x00000998, 0x0000 }, /* R2456 (0x998) - DSP2AUX2MIX Input 1 Source */
{ 0x000009a0, 0x0000 }, /* R2464 (0x9a0) - DSP2AUX3MIX Input 1 Source */
{ 0x000009a8, 0x0000 }, /* R2472 (0x9a8) - DSP2AUX4MIX Input 1 Source */
{ 0x000009b0, 0x0000 }, /* R2480 (0x9b0) - DSP2AUX5MIX Input 1 Source */
{ 0x000009b8, 0x0000 }, /* R2488 (0x9b8) - DSP2AUX6MIX Input 1 Source */
{ 0x000009c0, 0x0000 }, /* R2496 (0x9c0) - DSP3LMIX Input 1 Source */
{ 0x000009c1, 0x0080 }, /* R2497 (0x9c1) - DSP3LMIX Input 1 Volume */
{ 0x000009c2, 0x0000 }, /* R2498 (0x9c2) - DSP3LMIX Input 2 Source */
{ 0x000009c3, 0x0080 }, /* R2499 (0x9c3) - DSP3LMIX Input 2 Volume */
{ 0x000009c4, 0x0000 }, /* R2500 (0x9c4) - DSP3LMIX Input 3 Source */
{ 0x000009c5, 0x0080 }, /* R2501 (0x9c5) - DSP3LMIX Input 3 Volume */
{ 0x000009c6, 0x0000 }, /* R2502 (0x9c6) - DSP3LMIX Input 4 Source */
{ 0x000009c7, 0x0080 }, /* R2503 (0x9c7) - DSP3LMIX Input 4 Volume */
{ 0x000009c8, 0x0000 }, /* R2504 (0x9c8) - DSP3RMIX Input 1 Source */
{ 0x000009c9, 0x0080 }, /* R2505 (0x9c9) - DSP3RMIX Input 1 Volume */
{ 0x000009ca, 0x0000 }, /* R2506 (0x9ca) - DSP3RMIX Input 2 Source */
{ 0x000009cb, 0x0080 }, /* R2507 (0x9cb) - DSP3RMIX Input 2 Volume */
{ 0x000009cc, 0x0000 }, /* R2508 (0x9cc) - DSP3RMIX Input 3 Source */
{ 0x000009cd, 0x0080 }, /* R2509 (0x9cd) - DSP3RMIX Input 3 Volume */
{ 0x000009ce, 0x0000 }, /* R2510 (0x9ce) - DSP3RMIX Input 4 Source */
{ 0x000009cf, 0x0080 }, /* R2511 (0x9cf) - DSP3RMIX Input 4 Volume */
{ 0x000009d0, 0x0000 }, /* R2512 (0x9d0) - DSP3AUX1MIX Input 1 Source */
{ 0x000009d8, 0x0000 }, /* R2520 (0x9d8) - DSP3AUX2MIX Input 1 Source */
{ 0x000009e0, 0x0000 }, /* R2528 (0x9e0) - DSP3AUX3MIX Input 1 Source */
{ 0x000009e8, 0x0000 }, /* R2536 (0x9e8) - DSP3AUX4MIX Input 1 Source */
{ 0x000009f0, 0x0000 }, /* R2544 (0x9f0) - DSP3AUX5MIX Input 1 Source */
{ 0x000009f8, 0x0000 }, /* R2552 (0x9f8) - DSP3AUX6MIX Input 1 Source */
{ 0x00000a00, 0x0000 }, /* R2560 (0xa00) - DSP4LMIX Input 1 Source */
{ 0x00000a01, 0x0080 }, /* R2561 (0xa01) - DSP4LMIX Input 1 Volume */
{ 0x00000a02, 0x0000 }, /* R2562 (0xa02) - DSP4LMIX Input 2 Source */
{ 0x00000a03, 0x0080 }, /* R2563 (0xa03) - DSP4LMIX Input 2 Volume */
{ 0x00000a04, 0x0000 }, /* R2564 (0xa04) - DSP4LMIX Input 3 Source */
{ 0x00000a05, 0x0080 }, /* R2565 (0xa05) - DSP4LMIX Input 3 Volume */
{ 0x00000a06, 0x0000 }, /* R2566 (0xa06) - DSP4LMIX Input 4 Source */
{ 0x00000a07, 0x0080 }, /* R2567 (0xa07) - DSP4LMIX Input 4 Volume */
{ 0x00000a08, 0x0000 }, /* R2568 (0xa08) - DSP4RMIX Input 1 Source */
{ 0x00000a09, 0x0080 }, /* R2569 (0xa09) - DSP4RMIX Input 1 Volume */
{ 0x00000a0a, 0x0000 }, /* R2570 (0xa0a) - DSP4RMIX Input 2 Source */
{ 0x00000a0b, 0x0080 }, /* R2571 (0xa0b) - DSP4RMIX Input 2 Volume */
{ 0x00000a0c, 0x0000 }, /* R2572 (0xa0c) - DSP4RMIX Input 3 Source */
{ 0x00000a0d, 0x0080 }, /* R2573 (0xa0d) - DSP4RMIX Input 3 Volume */
{ 0x00000a0e, 0x0000 }, /* R2574 (0xa0e) - DSP4RMIX Input 4 Source */
{ 0x00000a0f, 0x0080 }, /* R2575 (0xa0f) - DSP4RMIX Input 4 Volume */
{ 0x00000a10, 0x0000 }, /* R2576 (0xa10) - DSP4AUX1MIX Input 1 Source */
{ 0x00000a18, 0x0000 }, /* R2584 (0xa18) - DSP4AUX2MIX Input 1 Source */
{ 0x00000a20, 0x0000 }, /* R2592 (0xa20) - DSP4AUX3MIX Input 1 Source */
{ 0x00000a28, 0x0000 }, /* R2600 (0xa28) - DSP4AUX4MIX Input 1 Source */
{ 0x00000a30, 0x0000 }, /* R2608 (0xa30) - DSP4AUX5MIX Input 1 Source */
{ 0x00000a38, 0x0000 }, /* R2616 (0xa38) - DSP4AUX6MIX Input 1 Source */
{ 0x00000a40, 0x0000 }, /* R2624 (0xa40) - DSP5LMIX Input 1 Source */
{ 0x00000a41, 0x0080 }, /* R2625 (0xa41) - DSP5LMIX Input 1 Volume */
{ 0x00000a42, 0x0000 }, /* R2626 (0xa42) - DSP5LMIX Input 2 Source */
{ 0x00000a43, 0x0080 }, /* R2627 (0xa43) - DSP5LMIX Input 2 Volume */
{ 0x00000a44, 0x0000 }, /* R2628 (0xa44) - DSP5LMIX Input 3 Source */
{ 0x00000a45, 0x0080 }, /* R2629 (0xa45) - DSP5LMIX Input 3 Volume */
{ 0x00000a46, 0x0000 }, /* R2630 (0xa46) - DSP5LMIX Input 4 Source */
{ 0x00000a47, 0x0080 }, /* R2631 (0xa47) - DSP5LMIX Input 4 Volume */
{ 0x00000a48, 0x0000 }, /* R2632 (0xa48) - DSP5RMIX Input 1 Source */
{ 0x00000a49, 0x0080 }, /* R2633 (0xa49) - DSP5RMIX Input 1 Volume */
{ 0x00000a4a, 0x0000 }, /* R2634 (0xa4a) - DSP5RMIX Input 2 Source */
{ 0x00000a4b, 0x0080 }, /* R2635 (0xa4b) - DSP5RMIX Input 2 Volume */
{ 0x00000a4c, 0x0000 }, /* R2636 (0xa4c) - DSP5RMIX Input 3 Source */
{ 0x00000a4d, 0x0080 }, /* R2637 (0xa4d) - DSP5RMIX Input 3 Volume */
{ 0x00000a4e, 0x0000 }, /* R2638 (0xa4e) - DSP5RMIX Input 4 Source */
{ 0x00000a4f, 0x0080 }, /* R2639 (0xa4f) - DSP5RMIX Input 4 Volume */
{ 0x00000a50, 0x0000 }, /* R2640 (0xa50) - DSP5AUX1MIX Input 1 Source */
{ 0x00000a58, 0x0000 }, /* R2658 (0xa58) - DSP5AUX2MIX Input 1 Source */
{ 0x00000a60, 0x0000 }, /* R2656 (0xa60) - DSP5AUX3MIX Input 1 Source */
{ 0x00000a68, 0x0000 }, /* R2664 (0xa68) - DSP5AUX4MIX Input 1 Source */
{ 0x00000a70, 0x0000 }, /* R2672 (0xa70) - DSP5AUX5MIX Input 1 Source */
{ 0x00000a78, 0x0000 }, /* R2680 (0xa78) - DSP5AUX6MIX Input 1 Source */
{ 0x00000a80, 0x0000 }, /* R2688 (0xa80) - ASRC1_1LMIX Input 1 Source */
{ 0x00000a88, 0x0000 }, /* R2696 (0xa88) - ASRC1_1RMIX Input 1 Source */
{ 0x00000a90, 0x0000 }, /* R2704 (0xa90) - ASRC1_2LMIX Input 1 Source */
{ 0x00000a98, 0x0000 }, /* R2712 (0xa98) - ASRC1_2RMIX Input 1 Source */
{ 0x00000aa0, 0x0000 }, /* R2720 (0xaa0) - ASRC2_1LMIX Input 1 Source */
{ 0x00000aa8, 0x0000 }, /* R2728 (0xaa8) - ASRC2_1RMIX Input 1 Source */
{ 0x00000ab0, 0x0000 }, /* R2736 (0xab0) - ASRC2_2LMIX Input 1 Source */
{ 0x00000ab8, 0x0000 }, /* R2744 (0xab8) - ASRC2_2RMIX Input 1 Source */
{ 0x00000b00, 0x0000 }, /* R2816 (0xb00) - ISRC1DEC1MIX Input 1 Source*/
{ 0x00000b08, 0x0000 }, /* R2824 (0xb08) - ISRC1DEC2MIX Input 1 Source*/
{ 0x00000b10, 0x0000 }, /* R2832 (0xb10) - ISRC1DEC3MIX Input 1 Source*/
{ 0x00000b18, 0x0000 }, /* R2840 (0xb18) - ISRC1DEC4MIX Input 1 Source*/
{ 0x00000b20, 0x0000 }, /* R2848 (0xb20) - ISRC1INT1MIX Input 1 Source*/
{ 0x00000b28, 0x0000 }, /* R2856 (0xb28) - ISRC1INT2MIX Input 1 Source*/
{ 0x00000b30, 0x0000 }, /* R2864 (0xb30) - ISRC1INT3MIX Input 1 Source*/
{ 0x00000b38, 0x0000 }, /* R2872 (0xb38) - ISRC1INT4MIX Input 1 Source*/
{ 0x00000b40, 0x0000 }, /* R2880 (0xb40) - ISRC2DEC1MIX Input 1 Source*/
{ 0x00000b48, 0x0000 }, /* R2888 (0xb48) - ISRC2DEC2MIX Input 1 Source*/
{ 0x00000b50, 0x0000 }, /* R2896 (0xb50) - ISRC2DEC3MIX Input 1 Source*/
{ 0x00000b58, 0x0000 }, /* R2904 (0xb58) - ISRC2DEC4MIX Input 1 Source*/
{ 0x00000b60, 0x0000 }, /* R2912 (0xb60) - ISRC2INT1MIX Input 1 Source*/
{ 0x00000b68, 0x0000 }, /* R2920 (0xb68) - ISRC2INT2MIX Input 1 Source*/
{ 0x00000b70, 0x0000 }, /* R2928 (0xb70) - ISRC2INT3MIX Input 1 Source*/
{ 0x00000b78, 0x0000 }, /* R2936 (0xb78) - ISRC2INT4MIX Input 1 Source*/
{ 0x00000b80, 0x0000 }, /* R2944 (0xb80) - ISRC3DEC1MIX Input 1 Source*/
{ 0x00000b88, 0x0000 }, /* R2952 (0xb88) - ISRC3DEC2MIX Input 1 Source*/
{ 0x00000ba0, 0x0000 }, /* R2976 (0xb80) - ISRC3INT1MIX Input 1 Source*/
{ 0x00000ba8, 0x0000 }, /* R2984 (0xb88) - ISRC3INT2MIX Input 1 Source*/
{ 0x00000bc0, 0x0000 }, /* R3008 (0xbc0) - ISRC4DEC1MIX Input 1 Source */
{ 0x00000bc8, 0x0000 }, /* R3016 (0xbc8) - ISRC4DEC2MIX Input 1 Source */
{ 0x00000be0, 0x0000 }, /* R3040 (0xbe0) - ISRC4INT1MIX Input 1 Source */
{ 0x00000be8, 0x0000 }, /* R3048 (0xbe8) - ISRC4INT2MIX Input 1 Source */
{ 0x00000c00, 0x0000 }, /* R3072 (0xc00) - DSP6LMIX Input 1 Source */
{ 0x00000c01, 0x0080 }, /* R3073 (0xc01) - DSP6LMIX Input 1 Volume */
{ 0x00000c02, 0x0000 }, /* R3074 (0xc02) - DSP6LMIX Input 2 Source */
{ 0x00000c03, 0x0080 }, /* R3075 (0xc03) - DSP6LMIX Input 2 Volume */
{ 0x00000c04, 0x0000 }, /* R3076 (0xc04) - DSP6LMIX Input 3 Source */
{ 0x00000c05, 0x0080 }, /* R3077 (0xc05) - DSP6LMIX Input 3 Volume */
{ 0x00000c06, 0x0000 }, /* R3078 (0xc06) - DSP6LMIX Input 4 Source */
{ 0x00000c07, 0x0080 }, /* R3079 (0xc07) - DSP6LMIX Input 4 Volume */
{ 0x00000c08, 0x0000 }, /* R3080 (0xc08) - DSP6RMIX Input 1 Source */
{ 0x00000c09, 0x0080 }, /* R3081 (0xc09) - DSP6RMIX Input 1 Volume */
{ 0x00000c0a, 0x0000 }, /* R3082 (0xc0a) - DSP6RMIX Input 2 Source */
{ 0x00000c0b, 0x0080 }, /* R3083 (0xc0b) - DSP6RMIX Input 2 Volume */
{ 0x00000c0c, 0x0000 }, /* R3084 (0xc0c) - DSP6RMIX Input 3 Source */
{ 0x00000c0d, 0x0080 }, /* R3085 (0xc0d) - DSP6RMIX Input 3 Volume */
{ 0x00000c0e, 0x0000 }, /* R3086 (0xc0e) - DSP6RMIX Input 4 Source */
{ 0x00000c0f, 0x0080 }, /* R3087 (0xc0f) - DSP6RMIX Input 4 Volume */
{ 0x00000c10, 0x0000 }, /* R3088 (0xc10) - DSP6AUX1MIX Input 1 Source */
{ 0x00000c18, 0x0000 }, /* R3088 (0xc18) - DSP6AUX2MIX Input 1 Source */
{ 0x00000c20, 0x0000 }, /* R3088 (0xc20) - DSP6AUX3MIX Input 1 Source */
{ 0x00000c28, 0x0000 }, /* R3088 (0xc28) - DSP6AUX4MIX Input 1 Source */
{ 0x00000c30, 0x0000 }, /* R3088 (0xc30) - DSP6AUX5MIX Input 1 Source */
{ 0x00000c38, 0x0000 }, /* R3088 (0xc38) - DSP6AUX6MIX Input 1 Source */
{ 0x00000c40, 0x0000 }, /* R3136 (0xc40) - DSP7LMIX Input 1 Source */
{ 0x00000c41, 0x0080 }, /* R3137 (0xc41) - DSP7LMIX Input 1 Volume */
{ 0x00000c42, 0x0000 }, /* R3138 (0xc42) - DSP7LMIX Input 2 Source */
{ 0x00000c43, 0x0080 }, /* R3139 (0xc43) - DSP7LMIX Input 2 Volume */
{ 0x00000c44, 0x0000 }, /* R3140 (0xc44) - DSP7LMIX Input 3 Source */
{ 0x00000c45, 0x0080 }, /* R3141 (0xc45) - DSP7lMIX Input 3 Volume */
{ 0x00000c46, 0x0000 }, /* R3142 (0xc46) - DSP7lMIX Input 4 Source */
{ 0x00000c47, 0x0080 }, /* R3143 (0xc47) - DSP7LMIX Input 4 Volume */
{ 0x00000c48, 0x0000 }, /* R3144 (0xc48) - DSP7RMIX Input 1 Source */
{ 0x00000c49, 0x0080 }, /* R3145 (0xc49) - DSP7RMIX Input 1 Volume */
{ 0x00000c4a, 0x0000 }, /* R3146 (0xc4a) - DSP7RMIX Input 2 Source */
{ 0x00000c4b, 0x0080 }, /* R3147 (0xc4b) - DSP7RMIX Input 2 Volume */
{ 0x00000c4c, 0x0000 }, /* R3148 (0xc4c) - DSP7RMIX Input 3 Source */
{ 0x00000c4d, 0x0080 }, /* R3159 (0xc4d) - DSP7RMIX Input 3 Volume */
{ 0x00000c4e, 0x0000 }, /* R3150 (0xc4e) - DSP7RMIX Input 4 Source */
{ 0x00000c4f, 0x0080 }, /* R3151 (0xc4f) - DSP7RMIX Input 4 Volume */
{ 0x00000c50, 0x0000 }, /* R3152 (0xc50) - DSP7AUX1MIX Input 1 Source */
{ 0x00000c58, 0x0000 }, /* R3160 (0xc58) - DSP7AUX2MIX Input 1 Source */
{ 0x00000c60, 0x0000 }, /* R3168 (0xc60) - DSP7AUX3MIX Input 1 Source */
{ 0x00000c68, 0x0000 }, /* R3176 (0xc68) - DSP7AUX4MIX Input 1 Source */
{ 0x00000c70, 0x0000 }, /* R3184 (0xc70) - DSP7AUX5MIX Input 1 Source */
{ 0x00000c78, 0x0000 }, /* R3192 (0xc78) - DSP7AUX6MIX Input 1 Source */
{ 0x00000dc0, 0x0000 }, /* R3520 (0xdc0) - DFC1MIX Input 1 Source */
{ 0x00000dc8, 0x0000 }, /* R3528 (0xdc8) - DFC2MIX Input 1 Source */
{ 0x00000dd0, 0x0000 }, /* R3536 (0xdd0) - DFC3MIX Input 1 Source */
{ 0x00000dd8, 0x0000 }, /* R3544 (0xdd8) - DFC4MIX Input 1 Source */
{ 0x00000de0, 0x0000 }, /* R3552 (0xde0) - DFC5MIX Input 1 Source */
{ 0x00000de8, 0x0000 }, /* R3560 (0xde8) - DFC6MIX Input 1 Source */
{ 0x00000df0, 0x0000 }, /* R3568 (0xdf0) - DFC7MIX Input 1 Source */
{ 0x00000df8, 0x0000 }, /* R3576 (0xdf8) - DFC8MIX Input 1 Source */
{ 0x00000e00, 0x0000 }, /* R3584 (0xe00) - FX_Ctrl1 */
{ 0x00000e10, 0x6318 }, /* R3600 (0xe10) - EQ1_1 */
{ 0x00000e11, 0x6300 }, /* R3601 (0xe11) - EQ1_2 */
{ 0x00000e12, 0x0fc8 }, /* R3602 (0xe12) - EQ1_3 */
{ 0x00000e13, 0x03fe }, /* R3603 (0xe13) - EQ1_4 */
{ 0x00000e14, 0x00e0 }, /* R3604 (0xe14) - EQ1_5 */
{ 0x00000e15, 0x1ec4 }, /* R3605 (0xe15) - EQ1_6 */
{ 0x00000e16, 0xf136 }, /* R3606 (0xe16) - EQ1_7 */
{ 0x00000e17, 0x0409 }, /* R3607 (0xe17) - EQ1_8 */
{ 0x00000e18, 0x04cc }, /* R3608 (0xe18) - EQ1_9 */
{ 0x00000e19, 0x1c9b }, /* R3609 (0xe19) - EQ1_10 */
{ 0x00000e1a, 0xf337 }, /* R3610 (0xe1a) - EQ1_11 */
{ 0x00000e1b, 0x040b }, /* R3611 (0xe1b) - EQ1_12 */
{ 0x00000e1c, 0x0cbb }, /* R3612 (0xe1c) - EQ1_13 */
{ 0x00000e1d, 0x16f8 }, /* R3613 (0xe1d) - EQ1_14 */
{ 0x00000e1e, 0xf7d9 }, /* R3614 (0xe1e) - EQ1_15 */
{ 0x00000e1f, 0x040a }, /* R3615 (0xe1f) - EQ1_16 */
{ 0x00000e20, 0x1f14 }, /* R3616 (0xe20) - EQ1_17 */
{ 0x00000e21, 0x058c }, /* R3617 (0xe21) - EQ1_18 */
{ 0x00000e22, 0x0563 }, /* R3618 (0xe22) - EQ1_19 */
{ 0x00000e23, 0x4000 }, /* R3619 (0xe23) - EQ1_20 */
{ 0x00000e24, 0x0b75 }, /* R3620 (0xe24) - EQ1_21 */
{ 0x00000e26, 0x6318 }, /* R3622 (0xe26) - EQ2_1 */
{ 0x00000e27, 0x6300 }, /* R3623 (0xe27) - EQ2_2 */
{ 0x00000e28, 0x0fc8 }, /* R3624 (0xe28) - EQ2_3 */
{ 0x00000e29, 0x03fe }, /* R3625 (0xe29) - EQ2_4 */
{ 0x00000e2a, 0x00e0 }, /* R3626 (0xe2a) - EQ2_5 */
{ 0x00000e2b, 0x1ec4 }, /* R3627 (0xe2b) - EQ2_6 */
{ 0x00000e2c, 0xf136 }, /* R3628 (0xe2c) - EQ2_7 */
{ 0x00000e2d, 0x0409 }, /* R3629 (0xe2d) - EQ2_8 */
{ 0x00000e2e, 0x04cc }, /* R3630 (0xe2e) - EQ2_9 */
{ 0x00000e2f, 0x1c9b }, /* R3631 (0xe2f) - EQ2_10 */
{ 0x00000e30, 0xf337 }, /* R3632 (0xe30) - EQ2_11 */
{ 0x00000e31, 0x040b }, /* R3633 (0xe31) - EQ2_12 */
{ 0x00000e32, 0x0cbb }, /* R3634 (0xe32) - EQ2_13 */
{ 0x00000e33, 0x16f8 }, /* R3635 (0xe33) - EQ2_14 */
{ 0x00000e34, 0xf7d9 }, /* R3636 (0xe34) - EQ2_15 */
{ 0x00000e35, 0x040a }, /* R3637 (0xe35) - EQ2_16 */
{ 0x00000e36, 0x1f14 }, /* R3638 (0xe36) - EQ2_17 */
{ 0x00000e37, 0x058c }, /* R3639 (0xe37) - EQ2_18 */
{ 0x00000e38, 0x0563 }, /* R3640 (0xe38) - EQ2_19 */
{ 0x00000e39, 0x4000 }, /* R3641 (0xe39) - EQ2_20 */
{ 0x00000e3a, 0x0b75 }, /* R3642 (0xe3a) - EQ2_21 */
{ 0x00000e3c, 0x6318 }, /* R3644 (0xe3c) - EQ3_1 */
{ 0x00000e3d, 0x6300 }, /* R3645 (0xe3d) - EQ3_2 */
{ 0x00000e3e, 0x0fc8 }, /* R3646 (0xe3e) - EQ3_3 */
{ 0x00000e3f, 0x03fe }, /* R3647 (0xe3f) - EQ3_4 */
{ 0x00000e40, 0x00e0 }, /* R3648 (0xe40) - EQ3_5 */
{ 0x00000e41, 0x1ec4 }, /* R3649 (0xe41) - EQ3_6 */
{ 0x00000e42, 0xf136 }, /* R3650 (0xe42) - EQ3_7 */
{ 0x00000e43, 0x0409 }, /* R3651 (0xe43) - EQ3_8 */
{ 0x00000e44, 0x04cc }, /* R3652 (0xe44) - EQ3_9 */
{ 0x00000e45, 0x1c9b }, /* R3653 (0xe45) - EQ3_10 */
{ 0x00000e46, 0xf337 }, /* R3654 (0xe46) - EQ3_11 */
{ 0x00000e47, 0x040b }, /* R3655 (0xe47) - EQ3_12 */
{ 0x00000e48, 0x0cbb }, /* R3656 (0xe48) - EQ3_13 */
{ 0x00000e49, 0x16f8 }, /* R3657 (0xe49) - EQ3_14 */
{ 0x00000e4a, 0xf7d9 }, /* R3658 (0xe4a) - EQ3_15 */
{ 0x00000e4b, 0x040a }, /* R3659 (0xe4b) - EQ3_16 */
{ 0x00000e4c, 0x1f14 }, /* R3660 (0xe4c) - EQ3_17 */
{ 0x00000e4d, 0x058c }, /* R3661 (0xe4d) - EQ3_18 */
{ 0x00000e4e, 0x0563 }, /* R3662 (0xe4e) - EQ3_19 */
{ 0x00000e4f, 0x4000 }, /* R3663 (0xe4f) - EQ3_20 */
{ 0x00000e50, 0x0b75 }, /* R3664 (0xe50) - EQ3_21 */
{ 0x00000e52, 0x6318 }, /* R3666 (0xe52) - EQ4_1 */
{ 0x00000e53, 0x6300 }, /* R3667 (0xe53) - EQ4_2 */
{ 0x00000e54, 0x0fc8 }, /* R3668 (0xe54) - EQ4_3 */
{ 0x00000e55, 0x03fe }, /* R3669 (0xe55) - EQ4_4 */
{ 0x00000e56, 0x00e0 }, /* R3670 (0xe56) - EQ4_5 */
{ 0x00000e57, 0x1ec4 }, /* R3671 (0xe57) - EQ4_6 */
{ 0x00000e58, 0xf136 }, /* R3672 (0xe58) - EQ4_7 */
{ 0x00000e59, 0x0409 }, /* R3673 (0xe59) - EQ4_8 */
{ 0x00000e5a, 0x04cc }, /* R3674 (0xe5a) - EQ4_9 */
{ 0x00000e5b, 0x1c9b }, /* R3675 (0xe5b) - EQ4_10 */
{ 0x00000e5c, 0xf337 }, /* R3676 (0xe5c) - EQ4_11 */
{ 0x00000e5d, 0x040b }, /* R3677 (0xe5d) - EQ4_12 */
{ 0x00000e5e, 0x0cbb }, /* R3678 (0xe5e) - EQ4_13 */
{ 0x00000e5f, 0x16f8 }, /* R3679 (0xe5f) - EQ4_14 */
{ 0x00000e60, 0xf7d9 }, /* R3680 (0xe60) - EQ4_15 */
{ 0x00000e61, 0x040a }, /* R3681 (0xe61) - EQ4_16 */
{ 0x00000e62, 0x1f14 }, /* R3682 (0xe62) - EQ4_17 */
{ 0x00000e63, 0x058c }, /* R3683 (0xe63) - EQ4_18 */
{ 0x00000e64, 0x0563 }, /* R3684 (0xe64) - EQ4_19 */
{ 0x00000e65, 0x4000 }, /* R3685 (0xe65) - EQ4_20 */
{ 0x00000e66, 0x0b75 }, /* R3686 (0xe66) - EQ4_21 */
{ 0x00000e80, 0x0018 }, /* R3712 (0xe80) - DRC1 ctrl1 */
{ 0x00000e81, 0x0933 }, /* R3713 (0xe81) - DRC1 ctrl2 */
{ 0x00000e82, 0x0018 }, /* R3714 (0xe82) - DRC1 ctrl3 */
{ 0x00000e83, 0x0000 }, /* R3715 (0xe83) - DRC1 ctrl4 */
{ 0x00000e84, 0x0000 }, /* R3716 (0xe84) - DRC1 ctrl5 */
{ 0x00000e88, 0x0018 }, /* R3720 (0xe88) - DRC2 ctrl1 */
{ 0x00000e89, 0x0933 }, /* R3721 (0xe89) - DRC2 ctrl2 */
{ 0x00000e8a, 0x0018 }, /* R3722 (0xe8a) - DRC2 ctrl3 */
{ 0x00000e8b, 0x0000 }, /* R3723 (0xe8b) - DRC2 ctrl4 */
{ 0x00000e8c, 0x0000 }, /* R3724 (0xe8c) - DRC2 ctrl5 */
{ 0x00000ec0, 0x0000 }, /* R3776 (0xec0) - HPLPF1_1 */
{ 0x00000ec1, 0x0000 }, /* R3777 (0xec1) - HPLPF1_2 */
{ 0x00000ec4, 0x0000 }, /* R3780 (0xec4) - HPLPF2_1 */
{ 0x00000ec5, 0x0000 }, /* R3781 (0xec5) - HPLPF2_2 */
{ 0x00000ec8, 0x0000 }, /* R3784 (0xec8) - HPLPF3_1 */
{ 0x00000ec9, 0x0000 }, /* R3785 (0xec9) - HPLPF3_2 */
{ 0x00000ecc, 0x0000 }, /* R3788 (0xecc) - HPLPF4_1 */
{ 0x00000ecd, 0x0000 }, /* R3789 (0xecd) - HPLPF4_2 */
{ 0x00000ed0, 0x0000 }, /* R3792 (0xed0) - ASRC2_ENABLE */
{ 0x00000ed2, 0x0000 }, /* R3794 (0xed2) - ASRC2_RATE1 */
{ 0x00000ed3, 0x4000 }, /* R3795 (0xed3) - ASRC2_RATE2 */
{ 0x00000ee0, 0x0000 }, /* R3808 (0xee0) - ASRC1_ENABLE */
{ 0x00000ee2, 0x0000 }, /* R3810 (0xee2) - ASRC1_RATE1 */
{ 0x00000ee3, 0x4000 }, /* R3811 (0xee3) - ASRC1_RATE2 */
{ 0x00000ef0, 0x0000 }, /* R3824 (0xef0) - ISRC 1 CTRL 1 */
{ 0x00000ef1, 0x0001 }, /* R3825 (0xef1) - ISRC 1 CTRL 2 */
{ 0x00000ef2, 0x0000 }, /* R3826 (0xef2) - ISRC 1 CTRL 3 */
{ 0x00000ef3, 0x0000 }, /* R3827 (0xef3) - ISRC 2 CTRL 1 */
{ 0x00000ef4, 0x0001 }, /* R3828 (0xef4) - ISRC 2 CTRL 2 */
{ 0x00000ef5, 0x0000 }, /* R3829 (0xef5) - ISRC 2 CTRL 3 */
{ 0x00000ef6, 0x0000 }, /* R3830 (0xef6) - ISRC 3 CTRL 1 */
{ 0x00000ef7, 0x0001 }, /* R3831 (0xef7) - ISRC 3 CTRL 2 */
{ 0x00000ef8, 0x0000 }, /* R3832 (0xef8) - ISRC 3 CTRL 3 */
{ 0x00000ef9, 0x0000 }, /* R3833 (0xef9) - ISRC 4 CTRL 1 */
{ 0x00000efa, 0x0001 }, /* R3834 (0xefa) - ISRC 4 CTRL 2 */
{ 0x00000efb, 0x0000 }, /* R3835 (0xefb) - ISRC 4 CTRL 3 */
{ 0x00000f01, 0x0000 }, /* R3841 (0xf01) - ANC_SRC */
{ 0x00000f02, 0x0000 }, /* R3842 (0xf02) - DSP Status */
{ 0x00000f08, 0x001c }, /* R3848 (0xf08) - ANC Coefficient */
{ 0x00000f09, 0x0000 }, /* R3849 (0xf09) - ANC Coefficient */
{ 0x00000f0a, 0x0000 }, /* R3850 (0xf0a) - ANC Coefficient */
{ 0x00000f0b, 0x0000 }, /* R3851 (0xf0b) - ANC Coefficient */
{ 0x00000f0c, 0x0000 }, /* R3852 (0xf0c) - ANC Coefficient */
{ 0x00000f0d, 0x0000 }, /* R3853 (0xf0d) - ANC Coefficient */
{ 0x00000f0e, 0x0000 }, /* R3854 (0xf0e) - ANC Coefficient */
{ 0x00000f0f, 0x0000 }, /* R3855 (0xf0f) - ANC Coefficient */
{ 0x00000f10, 0x0000 }, /* R3856 (0xf10) - ANC Coefficient */
{ 0x00000f11, 0x0000 }, /* R3857 (0xf11) - ANC Coefficient */
{ 0x00000f12, 0x0000 }, /* R3858 (0xf12) - ANC Coefficient */
{ 0x00000f15, 0x0000 }, /* R3861 (0xf15) - FCL Filter Control */
{ 0x00000f17, 0x0004 }, /* R3863 (0xf17) - FCL ADC Reformatter Control */
{ 0x00000f18, 0x0004 }, /* R3864 (0xf18) - ANC Coefficient */
{ 0x00000f19, 0x0002 }, /* R3865 (0xf19) - ANC Coefficient */
{ 0x00000f1a, 0x0000 }, /* R3866 (0xf1a) - ANC Coefficient */
{ 0x00000f1b, 0x0010 }, /* R3867 (0xf1b) - ANC Coefficient */
{ 0x00000f1c, 0x0000 }, /* R3868 (0xf1c) - ANC Coefficient */
{ 0x00000f1d, 0x0000 }, /* R3869 (0xf1d) - ANC Coefficient */
{ 0x00000f1e, 0x0000 }, /* R3870 (0xf1e) - ANC Coefficient */
{ 0x00000f1f, 0x0000 }, /* R3871 (0xf1f) - ANC Coefficient */
{ 0x00000f20, 0x0000 }, /* R3872 (0xf20) - ANC Coefficient */
{ 0x00000f21, 0x0000 }, /* R3873 (0xf21) - ANC Coefficient */
{ 0x00000f22, 0x0000 }, /* R3874 (0xf22) - ANC Coefficient */
{ 0x00000f23, 0x0000 }, /* R3875 (0xf23) - ANC Coefficient */
{ 0x00000f24, 0x0000 }, /* R3876 (0xf24) - ANC Coefficient */
{ 0x00000f25, 0x0000 }, /* R3877 (0xf25) - ANC Coefficient */
{ 0x00000f26, 0x0000 }, /* R3878 (0xf26) - ANC Coefficient */
{ 0x00000f27, 0x0000 }, /* R3879 (0xf27) - ANC Coefficient */
{ 0x00000f28, 0x0000 }, /* R3880 (0xf28) - ANC Coefficient */
{ 0x00000f29, 0x0000 }, /* R3881 (0xf29) - ANC Coefficient */
{ 0x00000f2a, 0x0000 }, /* R3882 (0xf2a) - ANC Coefficient */
{ 0x00000f2b, 0x0000 }, /* R3883 (0xf2b) - ANC Coefficient */
{ 0x00000f2c, 0x0000 }, /* R3884 (0xf2c) - ANC Coefficient */
{ 0x00000f2d, 0x0000 }, /* R3885 (0xf2d) - ANC Coefficient */
{ 0x00000f2e, 0x0000 }, /* R3886 (0xf2e) - ANC Coefficient */
{ 0x00000f2f, 0x0000 }, /* R3887 (0xf2f) - ANC Coefficient */
{ 0x00000f30, 0x0000 }, /* R3888 (0xf30) - ANC Coefficient */
{ 0x00000f31, 0x0000 }, /* R3889 (0xf31) - ANC Coefficient */
{ 0x00000f32, 0x0000 }, /* R3890 (0xf32) - ANC Coefficient */
{ 0x00000f33, 0x0000 }, /* R3891 (0xf33) - ANC Coefficient */
{ 0x00000f34, 0x0000 }, /* R3892 (0xf34) - ANC Coefficient */
{ 0x00000f35, 0x0000 }, /* R3893 (0xf35) - ANC Coefficient */
{ 0x00000f36, 0x0000 }, /* R3894 (0xf36) - ANC Coefficient */
{ 0x00000f37, 0x0000 }, /* R3895 (0xf37) - ANC Coefficient */
{ 0x00000f38, 0x0000 }, /* R3896 (0xf38) - ANC Coefficient */
{ 0x00000f39, 0x0000 }, /* R3897 (0xf39) - ANC Coefficient */
{ 0x00000f3a, 0x0000 }, /* R3898 (0xf3a) - ANC Coefficient */
{ 0x00000f3b, 0x0000 }, /* R3899 (0xf3b) - ANC Coefficient */
{ 0x00000f3c, 0x0000 }, /* R3900 (0xf3c) - ANC Coefficient */
{ 0x00000f3d, 0x0000 }, /* R3901 (0xf3d) - ANC Coefficient */
{ 0x00000f3e, 0x0000 }, /* R3902 (0xf3e) - ANC Coefficient */
{ 0x00000f3f, 0x0000 }, /* R3903 (0xf3f) - ANC Coefficient */
{ 0x00000f40, 0x0000 }, /* R3904 (0xf40) - ANC Coefficient */
{ 0x00000f41, 0x0000 }, /* R3905 (0xf41) - ANC Coefficient */
{ 0x00000f42, 0x0000 }, /* R3906 (0xf42) - ANC Coefficient */
{ 0x00000f43, 0x0000 }, /* R3907 (0xf43) - ANC Coefficient */
{ 0x00000f44, 0x0000 }, /* R3908 (0xf44) - ANC Coefficient */
{ 0x00000f45, 0x0000 }, /* R3909 (0xf45) - ANC Coefficient */
{ 0x00000f46, 0x0000 }, /* R3910 (0xf46) - ANC Coefficient */
{ 0x00000f47, 0x0000 }, /* R3911 (0xf47) - ANC Coefficient */
{ 0x00000f48, 0x0000 }, /* R3912 (0xf48) - ANC Coefficient */
{ 0x00000f49, 0x0000 }, /* R3913 (0xf49) - ANC Coefficient */
{ 0x00000f4a, 0x0000 }, /* R3914 (0xf4a) - ANC Coefficient */
{ 0x00000f4b, 0x0000 }, /* R3915 (0xf4b) - ANC Coefficient */
{ 0x00000f4c, 0x0000 }, /* R3916 (0xf4c) - ANC Coefficient */
{ 0x00000f4d, 0x0000 }, /* R3917 (0xf4d) - ANC Coefficient */
{ 0x00000f4e, 0x0000 }, /* R3918 (0xf4e) - ANC Coefficient */
{ 0x00000f4f, 0x0000 }, /* R3919 (0xf4f) - ANC Coefficient */
{ 0x00000f50, 0x0000 }, /* R3920 (0xf50) - ANC Coefficient */
{ 0x00000f51, 0x0000 }, /* R3921 (0xf51) - ANC Coefficient */
{ 0x00000f52, 0x0000 }, /* R3922 (0xf52) - ANC Coefficient */
{ 0x00000f53, 0x0000 }, /* R3923 (0xf53) - ANC Coefficient */
{ 0x00000f54, 0x0000 }, /* R3924 (0xf54) - ANC Coefficient */
{ 0x00000f55, 0x0000 }, /* R3925 (0xf55) - ANC Coefficient */
{ 0x00000f56, 0x0000 }, /* R3926 (0xf56) - ANC Coefficient */
{ 0x00000f57, 0x0000 }, /* R3927 (0xf57) - ANC Coefficient */
{ 0x00000f58, 0x0000 }, /* R3928 (0xf58) - ANC Coefficient */
{ 0x00000f59, 0x0000 }, /* R3929 (0xf59) - ANC Coefficient */
{ 0x00000f5a, 0x0000 }, /* R3930 (0xf5a) - ANC Coefficient */
{ 0x00000f5b, 0x0000 }, /* R3931 (0xf5b) - ANC Coefficient */
{ 0x00000f5c, 0x0000 }, /* R3932 (0xf5c) - ANC Coefficient */
{ 0x00000f5d, 0x0000 }, /* R3933 (0xf5d) - ANC Coefficient */
{ 0x00000f5e, 0x0000 }, /* R3934 (0xf5e) - ANC Coefficient */
{ 0x00000f5f, 0x0000 }, /* R3935 (0xf5f) - ANC Coefficient */
{ 0x00000f60, 0x0000 }, /* R3936 (0xf60) - ANC Coefficient */
{ 0x00000f61, 0x0000 }, /* R3937 (0xf61) - ANC Coefficient */
{ 0x00000f62, 0x0000 }, /* R3938 (0xf62) - ANC Coefficient */
{ 0x00000f63, 0x0000 }, /* R3939 (0xf63) - ANC Coefficient */
{ 0x00000f64, 0x0000 }, /* R3940 (0xf64) - ANC Coefficient */
{ 0x00000f65, 0x0000 }, /* R3941 (0xf65) - ANC Coefficient */
{ 0x00000f66, 0x0000 }, /* R3942 (0xf66) - ANC Coefficient */
{ 0x00000f67, 0x0000 }, /* R3943 (0xf67) - ANC Coefficient */
{ 0x00000f68, 0x0000 }, /* R3944 (0xf68) - ANC Coefficient */
{ 0x00000f69, 0x0000 }, /* R3945 (0xf69) - ANC Coefficient */
{ 0x00000f71, 0x0000 }, /* R3953 (0xf71) - FCR Filter Control */
{ 0x00000f73, 0x0004 }, /* R3955 (0xf73) - FCR ADC Reformatter Control */
{ 0x00000f74, 0x0004 }, /* R3956 (0xf74) - ANC Coefficient */
{ 0x00000f75, 0x0002 }, /* R3957 (0xf75) - ANC Coefficient */
{ 0x00000f76, 0x0000 }, /* R3958 (0xf76) - ANC Coefficient */
{ 0x00000f77, 0x0010 }, /* R3959 (0xf77) - ANC Coefficient */
{ 0x00000f78, 0x0000 }, /* R3960 (0xf78) - ANC Coefficient */
{ 0x00000f79, 0x0000 }, /* R3961 (0xf79) - ANC Coefficient */
{ 0x00000f7a, 0x0000 }, /* R3962 (0xf7a) - ANC Coefficient */
{ 0x00000f7b, 0x0000 }, /* R3963 (0xf7b) - ANC Coefficient */
{ 0x00000f7c, 0x0000 }, /* R3964 (0xf7c) - ANC Coefficient */
{ 0x00000f7d, 0x0000 }, /* R3965 (0xf7d) - ANC Coefficient */
{ 0x00000f7e, 0x0000 }, /* R3966 (0xf7e) - ANC Coefficient */
{ 0x00000f7f, 0x0000 }, /* R3967 (0xf7f) - ANC Coefficient */
{ 0x00000f80, 0x0000 }, /* R3968 (0xf80) - ANC Coefficient */
{ 0x00000f81, 0x0000 }, /* R3969 (0xf81) - ANC Coefficient */
{ 0x00000f82, 0x0000 }, /* R3970 (0xf82) - ANC Coefficient */
{ 0x00000f83, 0x0000 }, /* R3971 (0xf83) - ANC Coefficient */
{ 0x00000f84, 0x0000 }, /* R3972 (0xf84) - ANC Coefficient */
{ 0x00000f85, 0x0000 }, /* R3973 (0xf85) - ANC Coefficient */
{ 0x00000f86, 0x0000 }, /* R3974 (0xf86) - ANC Coefficient */
{ 0x00000f87, 0x0000 }, /* R3975 (0xf87) - ANC Coefficient */
{ 0x00000f88, 0x0000 }, /* R3976 (0xf88) - ANC Coefficient */
{ 0x00000f89, 0x0000 }, /* R3977 (0xf89) - ANC Coefficient */
{ 0x00000f8a, 0x0000 }, /* R3978 (0xf8a) - ANC Coefficient */
{ 0x00000f8b, 0x0000 }, /* R3979 (0xf8b) - ANC Coefficient */
{ 0x00000f8c, 0x0000 }, /* R3980 (0xf8c) - ANC Coefficient */
{ 0x00000f8d, 0x0000 }, /* R3981 (0xf8d) - ANC Coefficient */
{ 0x00000f8e, 0x0000 }, /* R3982 (0xf8e) - ANC Coefficient */
{ 0x00000f8f, 0x0000 }, /* R3983 (0xf8f) - ANC Coefficient */
{ 0x00000f90, 0x0000 }, /* R3984 (0xf90) - ANC Coefficient */
{ 0x00000f91, 0x0000 }, /* R3985 (0xf91) - ANC Coefficient */
{ 0x00000f92, 0x0000 }, /* R3986 (0xf92) - ANC Coefficient */
{ 0x00000f93, 0x0000 }, /* R3987 (0xf93) - ANC Coefficient */
{ 0x00000f94, 0x0000 }, /* R3988 (0xf94) - ANC Coefficient */
{ 0x00000f95, 0x0000 }, /* R3989 (0xf95) - ANC Coefficient */
{ 0x00000f96, 0x0000 }, /* R3990 (0xf96) - ANC Coefficient */
{ 0x00000f97, 0x0000 }, /* R3991 (0xf97) - ANC Coefficient */
{ 0x00000f98, 0x0000 }, /* R3992 (0xf98) - ANC Coefficient */
{ 0x00000f99, 0x0000 }, /* R3993 (0xf99) - ANC Coefficient */
{ 0x00000f9a, 0x0000 }, /* R3994 (0xf9a) - ANC Coefficient */
{ 0x00000f9b, 0x0000 }, /* R3995 (0xf9b) - ANC Coefficient */
{ 0x00000f9c, 0x0000 }, /* R3996 (0xf9c) - ANC Coefficient */
{ 0x00000f9d, 0x0000 }, /* R3997 (0xf9d) - ANC Coefficient */
{ 0x00000f9e, 0x0000 }, /* R3998 (0xf9e) - ANC Coefficient */
{ 0x00000f9f, 0x0000 }, /* R3999 (0xf9f) - ANC Coefficient */
{ 0x00000fa0, 0x0000 }, /* R4000 (0xfa0) - ANC Coefficient */
{ 0x00000fa1, 0x0000 }, /* R4001 (0xfa1) - ANC Coefficient */
{ 0x00000fa2, 0x0000 }, /* R4002 (0xfa2) - ANC Coefficient */
{ 0x00000fa3, 0x0000 }, /* R4003 (0xfa3) - ANC Coefficient */
{ 0x00000fa4, 0x0000 }, /* R4004 (0xfa4) - ANC Coefficient */
{ 0x00000fa5, 0x0000 }, /* R4005 (0xfa5) - ANC Coefficient */
{ 0x00000fa6, 0x0000 }, /* R4006 (0xfa6) - ANC Coefficient */
{ 0x00000fa7, 0x0000 }, /* R4007 (0xfa7) - ANC Coefficient */
{ 0x00000fa8, 0x0000 }, /* R4008 (0xfa8) - ANC Coefficient */
{ 0x00000fa9, 0x0000 }, /* R4009 (0xfa9) - ANC Coefficient */
{ 0x00000faa, 0x0000 }, /* R4010 (0xfaa) - ANC Coefficient */
{ 0x00000fab, 0x0000 }, /* R4011 (0xfab) - ANC Coefficient */
{ 0x00000fac, 0x0000 }, /* R4012 (0xfac) - ANC Coefficient */
{ 0x00000fad, 0x0000 }, /* R4013 (0xfad) - ANC Coefficient */
{ 0x00000fae, 0x0000 }, /* R4014 (0xfae) - ANC Coefficient */
{ 0x00000faf, 0x0000 }, /* R4015 (0xfaf) - ANC Coefficient */
{ 0x00000fb0, 0x0000 }, /* R4016 (0xfb0) - ANC Coefficient */
{ 0x00000fb1, 0x0000 }, /* R4017 (0xfb1) - ANC Coefficient */
{ 0x00000fb2, 0x0000 }, /* R4018 (0xfb2) - ANC Coefficient */
{ 0x00000fb3, 0x0000 }, /* R4019 (0xfb3) - ANC Coefficient */
{ 0x00000fb4, 0x0000 }, /* R4020 (0xfb4) - ANC Coefficient */
{ 0x00000fb5, 0x0000 }, /* R4021 (0xfb5) - ANC Coefficient */
{ 0x00000fb6, 0x0000 }, /* R4022 (0xfb6) - ANC Coefficient */
{ 0x00000fb7, 0x0000 }, /* R4023 (0xfb7) - ANC Coefficient */
{ 0x00000fb8, 0x0000 }, /* R4024 (0xfb8) - ANC Coefficient */
{ 0x00000fb9, 0x0000 }, /* R4025 (0xfb9) - ANC Coefficient */
{ 0x00000fba, 0x0000 }, /* R4026 (0xfba) - ANC Coefficient */
{ 0x00000fbb, 0x0000 }, /* R4027 (0xfbb) - ANC Coefficient */
{ 0x00000fbc, 0x0000 }, /* R4028 (0xfbc) - ANC Coefficient */
{ 0x00000fbd, 0x0000 }, /* R4029 (0xfbd) - ANC Coefficient */
{ 0x00000fbe, 0x0000 }, /* R4030 (0xfbe) - ANC Coefficient */
{ 0x00000fbf, 0x0000 }, /* R4031 (0xfbf) - ANC Coefficient */
{ 0x00000fc0, 0x0000 }, /* R4032 (0xfc0) - ANC Coefficient */
{ 0x00000fc1, 0x0000 }, /* R4033 (0xfc1) - ANC Coefficient */
{ 0x00000fc2, 0x0000 }, /* R4034 (0xfc2) - ANC Coefficient */
{ 0x00000fc3, 0x0000 }, /* R4035 (0xfc3) - ANC Coefficient */
{ 0x00000fc4, 0x0000 }, /* R4036 (0xfc4) - ANC Coefficient */
{ 0x00000fc5, 0x0000 }, /* R4037 (0xfc5) - ANC Coefficient */
{ 0x00001480, 0x0000 }, /* R5248 (0x1480) - DFC1_CTRL */
{ 0x00001482, 0x1f00 }, /* R5250 (0x1482) - DFC1_RX */
{ 0x00001484, 0x1f00 }, /* R5252 (0x1486) - DFC1_TX */
{ 0x00001486, 0x0000 }, /* R5254 (0x1486) - DFC2_CTRL */
{ 0x00001488, 0x1f00 }, /* R5256 (0x1488) - DFC2_RX */
{ 0x0000148a, 0x1f00 }, /* R5258 (0x148a) - DFC2_TX */
{ 0x0000148c, 0x0000 }, /* R5260 (0x148c) - DFC3_CTRL */
{ 0x0000148e, 0x1f00 }, /* R5262 (0x148e) - DFC3_RX */
{ 0x00001490, 0x1f00 }, /* R5264 (0x1490) - DFC3_TX */
{ 0x00001492, 0x0000 }, /* R5266 (0x1492) - DFC4_CTRL */
{ 0x00001494, 0x1f00 }, /* R5268 (0x1494) - DFC4_RX */
{ 0x00001496, 0x1f00 }, /* R5270 (0x1496) - DFC4_TX */
{ 0x00001498, 0x0000 }, /* R5272 (0x1498) - DFC5_CTRL */
{ 0x0000149a, 0x1f00 }, /* R5274 (0x149a) - DFC5_RX */
{ 0x0000149c, 0x1f00 }, /* R5276 (0x149c) - DFC5_TX */
{ 0x0000149e, 0x0000 }, /* R5278 (0x149e) - DFC6_CTRL */
{ 0x000014a0, 0x1f00 }, /* R5280 (0x14a0) - DFC6_RX */
{ 0x000014a2, 0x1f00 }, /* R5282 (0x14a2) - DFC6_TX */
{ 0x000014a4, 0x0000 }, /* R5284 (0x14a4) - DFC7_CTRL */
{ 0x000014a6, 0x1f00 }, /* R5286 (0x14a6) - DFC7_RX */
{ 0x000014a8, 0x1f00 }, /* R5288 (0x14a8) - DFC7_TX */
{ 0x000014aa, 0x0000 }, /* R5290 (0x14aa) - DFC8_CTRL */
{ 0x000014ac, 0x1f00 }, /* R5292 (0x14ac) - DFC8_RX */
{ 0x000014ae, 0x1f00 }, /* R5294 (0x14ae) - DFC8_TX */
{ 0x00001700, 0x2001 }, /* R5888 (0x1700) - GPIO1 Control 1 */
{ 0x00001701, 0xf000 }, /* R5889 (0x1701) - GPIO1 Control 2 */
{ 0x00001702, 0x2001 }, /* R5890 (0x1702) - GPIO2 Control 1 */
{ 0x00001703, 0xf000 }, /* R5891 (0x1702) - GPIO2 Control 2 */
{ 0x00001704, 0x2001 }, /* R5892 (0x1704) - GPIO3 Control 1 */
{ 0x00001705, 0xf000 }, /* R5893 (0x1705) - GPIO3 Control 2 */
{ 0x00001706, 0x2001 }, /* R5894 (0x1706) - GPIO4 Control 1 */
{ 0x00001707, 0xf000 }, /* R5895 (0x1707) - GPIO4 Control 2 */
{ 0x00001708, 0x2001 }, /* R5896 (0x1708) - GPIO5 Control 1 */
{ 0x00001709, 0xf000 }, /* R5897 (0x1709) - GPIO5 Control 2 */
{ 0x0000170a, 0x2001 }, /* R5898 (0x170a) - GPIO6 Control 1 */
{ 0x0000170b, 0xf000 }, /* R5899 (0x170b) - GPIO6 Control 2 */
{ 0x0000170c, 0x2001 }, /* R5900 (0x170c) - GPIO7 Control 1 */
{ 0x0000170d, 0xf000 }, /* R5901 (0x170d) - GPIO7 Control 2 */
{ 0x0000170e, 0x2001 }, /* R5902 (0x170e) - GPIO8 Control 1 */
{ 0x0000170f, 0xf000 }, /* R5903 (0x170f) - GPIO8 Control 2 */
{ 0x00001710, 0x2001 }, /* R5904 (0x1710) - GPIO9 Control 1 */
{ 0x00001711, 0xf000 }, /* R5905 (0x1711) - GPIO9 Control 2 */
{ 0x00001712, 0x2001 }, /* R5906 (0x1712) - GPIO10 Control 1 */
{ 0x00001713, 0xf000 }, /* R5907 (0x1713) - GPIO10 Control 2 */
{ 0x00001714, 0x2001 }, /* R5908 (0x1714) - GPIO11 Control 1 */
{ 0x00001715, 0xf000 }, /* R5909 (0x1715) - GPIO11 Control 2 */
{ 0x00001716, 0x2001 }, /* R5910 (0x1716) - GPIO12 Control 1 */
{ 0x00001717, 0xf000 }, /* R5911 (0x1717) - GPIO12 Control 2 */
{ 0x00001718, 0x2001 }, /* R5912 (0x1718) - GPIO13 Control 1 */
{ 0x00001719, 0xf000 }, /* R5913 (0x1719) - GPIO13 Control 2 */
{ 0x0000171a, 0x2001 }, /* R5914 (0x171a) - GPIO14 Control 1 */
{ 0x0000171b, 0xf000 }, /* R5915 (0x171b) - GPIO14 Control 2 */
{ 0x0000171c, 0x2001 }, /* R5916 (0x171c) - GPIO15 Control 1 */
{ 0x0000171d, 0xf000 }, /* R5917 (0x171d) - GPIO15 Control 2 */
{ 0x0000171e, 0x2001 }, /* R5918 (0x171e) - GPIO16 Control 1 */
{ 0x0000171f, 0xf000 }, /* R5919 (0x171f) - GPIO16 Control 2 */
{ 0x00001720, 0x2001 }, /* R5920 (0x1720) - GPIO17 Control 1 */
{ 0x00001721, 0xf000 }, /* R5921 (0x1721) - GPIO17 Control 2 */
{ 0x00001722, 0x2001 }, /* R5922 (0x1722) - GPIO18 Control 1 */
{ 0x00001723, 0xf000 }, /* R5923 (0x1723) - GPIO18 Control 2 */
{ 0x00001724, 0x2001 }, /* R5924 (0x1724) - GPIO19 Control 1 */
{ 0x00001725, 0xf000 }, /* R5925 (0x1725) - GPIO19 Control 2 */
{ 0x00001726, 0x2001 }, /* R5926 (0x1726) - GPIO20 Control 1 */
{ 0x00001727, 0xf000 }, /* R5927 (0x1727) - GPIO20 Control 2 */
{ 0x00001728, 0x2001 }, /* R5928 (0x1728) - GPIO21 Control 1 */
{ 0x00001729, 0xf000 }, /* R5929 (0x1729) - GPIO21 Control 2 */
{ 0x0000172a, 0x2001 }, /* R5930 (0x172a) - GPIO22 Control 1 */
{ 0x0000172b, 0xf000 }, /* R5931 (0x172b) - GPIO22 Control 2 */
{ 0x0000172c, 0x2001 }, /* R5932 (0x172c) - GPIO23 Control 1 */
{ 0x0000172d, 0xf000 }, /* R5933 (0x172d) - GPIO23 Control 2 */
{ 0x0000172e, 0x2001 }, /* R5934 (0x172e) - GPIO24 Control 1 */
{ 0x0000172f, 0xf000 }, /* R5935 (0x172f) - GPIO24 Control 2 */
{ 0x00001730, 0x2001 }, /* R5936 (0x1730) - GPIO25 Control 1 */
{ 0x00001731, 0xf000 }, /* R5937 (0x1731) - GPIO25 Control 2 */
{ 0x00001732, 0x2001 }, /* R5938 (0x1732) - GPIO26 Control 1 */
{ 0x00001733, 0xf000 }, /* R5939 (0x1733) - GPIO26 Control 2 */
{ 0x00001734, 0x2001 }, /* R5940 (0x1734) - GPIO27 Control 1 */
{ 0x00001735, 0xf000 }, /* R5941 (0x1735) - GPIO27 Control 2 */
{ 0x00001736, 0x2001 }, /* R5942 (0x1736) - GPIO28 Control 1 */
{ 0x00001737, 0xf000 }, /* R5943 (0x1737) - GPIO28 Control 2 */
{ 0x00001738, 0x2001 }, /* R5944 (0x1738) - GPIO29 Control 1 */
{ 0x00001739, 0xf000 }, /* R5945 (0x1739) - GPIO29 Control 2 */
{ 0x0000173a, 0x2001 }, /* R5946 (0x173a) - GPIO30 Control 1 */
{ 0x0000173b, 0xf000 }, /* R5947 (0x173b) - GPIO30 Control 2 */
{ 0x0000173c, 0x2001 }, /* R5948 (0x173c) - GPIO31 Control 1 */
{ 0x0000173d, 0xf000 }, /* R5949 (0x173d) - GPIO31 Control 2 */
{ 0x0000173e, 0x2001 }, /* R5950 (0x173e) - GPIO32 Control 1 */
{ 0x0000173f, 0xf000 }, /* R5951 (0x173f) - GPIO32 Control 2 */
{ 0x00001740, 0x2001 }, /* R5952 (0x1740) - GPIO33 Control 1 */
{ 0x00001741, 0xf000 }, /* R5953 (0x1741) - GPIO33 Control 2 */
{ 0x00001742, 0x2001 }, /* R5954 (0x1742) - GPIO34 Control 1 */
{ 0x00001743, 0xf000 }, /* R5955 (0x1743) - GPIO34 Control 2 */
{ 0x00001744, 0x2001 }, /* R5956 (0x1744) - GPIO35 Control 1 */
{ 0x00001745, 0xf000 }, /* R5957 (0x1745) - GPIO35 Control 2 */
{ 0x00001746, 0x2001 }, /* R5958 (0x1746) - GPIO36 Control 1 */
{ 0x00001747, 0xf000 }, /* R5959 (0x1747) - GPIO36 Control 2 */
{ 0x00001748, 0x2001 }, /* R5960 (0x1748) - GPIO37 Control 1 */
{ 0x00001749, 0xf000 }, /* R5961 (0x1749) - GPIO37 Control 2 */
{ 0x0000174a, 0x2001 }, /* R5962 (0x174a) - GPIO38 Control 1 */
{ 0x0000174b, 0xf000 }, /* R5963 (0x174b) - GPIO38 Control 2 */
{ 0x00001840, 0xffff }, /* R6208 (0x1840) - IRQ1 Mask 1 */
{ 0x00001841, 0xffff }, /* R6209 (0x1841) - IRQ1 Mask 2 */
{ 0x00001842, 0xffff }, /* R6210 (0x1842) - IRQ1 Mask 3 */
{ 0x00001843, 0xffff }, /* R6211 (0x1843) - IRQ1 Mask 4 */
{ 0x00001844, 0xffff }, /* R6212 (0x1844) - IRQ1 Mask 5 */
{ 0x00001845, 0xffff }, /* R6213 (0x1845) - IRQ1 Mask 6 */
{ 0x00001846, 0xffff }, /* R6214 (0x1846) - IRQ1 Mask 7 */
{ 0x00001847, 0xffff }, /* R6215 (0x1847) - IRQ1 Mask 8 */
{ 0x00001848, 0xffff }, /* R6216 (0x1848) - IRQ1 Mask 9 */
{ 0x00001849, 0xffff }, /* R6217 (0x1849) - IRQ1 Mask 10 */
{ 0x0000184a, 0xffff }, /* R6218 (0x184a) - IRQ1 Mask 11 */
{ 0x0000184b, 0xffff }, /* R6219 (0x184b) - IRQ1 Mask 12 */
{ 0x0000184c, 0xffff }, /* R6220 (0x184c) - IRQ1 Mask 13 */
{ 0x0000184d, 0xffff }, /* R6221 (0x184d) - IRQ1 Mask 14 */
{ 0x0000184e, 0xffff }, /* R6222 (0x184e) - IRQ1 Mask 15 */
{ 0x0000184f, 0xffff }, /* R6223 (0x184f) - IRQ1 Mask 16 */
{ 0x00001850, 0xffff }, /* R6224 (0x1850) - IRQ1 Mask 17 */
{ 0x00001851, 0xffff }, /* R6225 (0x1851) - IRQ1 Mask 18 */
{ 0x00001852, 0xffff }, /* R6226 (0x1852) - IRQ1 Mask 19 */
{ 0x00001853, 0xffff }, /* R6227 (0x1853) - IRQ1 Mask 20 */
{ 0x00001854, 0xffff }, /* R6228 (0x1854) - IRQ1 Mask 21 */
{ 0x00001855, 0xffff }, /* R6229 (0x1855) - IRQ1 Mask 22 */
{ 0x00001856, 0xffff }, /* R6230 (0x1856) - IRQ1 Mask 23 */
{ 0x00001857, 0xffff }, /* R6231 (0x1857) - IRQ1 Mask 24 */
{ 0x00001858, 0xffff }, /* R6232 (0x1858) - IRQ1 Mask 25 */
{ 0x00001859, 0xffff }, /* R6233 (0x1859) - IRQ1 Mask 26 */
{ 0x0000185a, 0xffff }, /* R6234 (0x185a) - IRQ1 Mask 27 */
{ 0x0000185b, 0xffff }, /* R6235 (0x185b) - IRQ1 Mask 28 */
{ 0x0000185c, 0xffff }, /* R6236 (0x185c) - IRQ1 Mask 29 */
{ 0x0000185d, 0xffff }, /* R6237 (0x185d) - IRQ1 Mask 30 */
{ 0x0000185e, 0xffff }, /* R6238 (0x185e) - IRQ1 Mask 31 */
{ 0x0000185f, 0xffff }, /* R6239 (0x185f) - IRQ1 Mask 32 */
{ 0x00001860, 0xffff }, /* R6240 (0x1860) - IRQ1 Mask 33 */
{ 0x00001a06, 0x0000 }, /* R6662 (0x1a06) - Interrupt Debounce 7 */
{ 0x00001a80, 0x4400 }, /* R6784 (0x1a80) - IRQ1 CTRL */
};
static bool cs47l90_is_adsp_memory(unsigned int reg)
{
switch (reg) {
case 0x080000 ... 0x088ffe:
case 0x0a0000 ... 0x0a9ffe:
case 0x0c0000 ... 0x0c3ffe:
case 0x0e0000 ... 0x0e1ffe:
case 0x100000 ... 0x10effe:
case 0x120000 ... 0x12bffe:
case 0x136000 ... 0x137ffe:
case 0x140000 ... 0x14bffe:
case 0x160000 ... 0x161ffe:
case 0x180000 ... 0x18effe:
case 0x1a0000 ... 0x1b1ffe:
case 0x1b6000 ... 0x1b7ffe:
case 0x1c0000 ... 0x1cbffe:
case 0x1e0000 ... 0x1e1ffe:
case 0x200000 ... 0x208ffe:
case 0x220000 ... 0x229ffe:
case 0x240000 ... 0x243ffe:
case 0x260000 ... 0x261ffe:
case 0x280000 ... 0x288ffe:
case 0x2a0000 ... 0x2a9ffe:
case 0x2c0000 ... 0x2c3ffe:
case 0x2e0000 ... 0x2e1ffe:
case 0x300000 ... 0x308ffe:
case 0x320000 ... 0x333ffe:
case 0x340000 ... 0x353ffe:
case 0x360000 ... 0x361ffe:
case 0x380000 ... 0x388ffe:
case 0x3a0000 ... 0x3b3ffe:
case 0x3c0000 ... 0x3d3ffe:
case 0x3e0000 ... 0x3e1ffe:
return true;
default:
return false;
}
}
static bool cs47l90_16bit_readable_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_SOFTWARE_RESET:
case MADERA_HARDWARE_REVISION:
case MADERA_WRITE_SEQUENCER_CTRL_0:
case MADERA_WRITE_SEQUENCER_CTRL_1:
case MADERA_WRITE_SEQUENCER_CTRL_2:
case MADERA_TONE_GENERATOR_1:
case MADERA_TONE_GENERATOR_2:
case MADERA_TONE_GENERATOR_3:
case MADERA_TONE_GENERATOR_4:
case MADERA_TONE_GENERATOR_5:
case MADERA_PWM_DRIVE_1:
case MADERA_PWM_DRIVE_2:
case MADERA_PWM_DRIVE_3:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_1:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_2:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_3:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_4:
case MADERA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1:
case MADERA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2:
case MADERA_HAPTICS_CONTROL_1:
case MADERA_HAPTICS_CONTROL_2:
case MADERA_HAPTICS_PHASE_1_INTENSITY:
case MADERA_HAPTICS_PHASE_1_DURATION:
case MADERA_HAPTICS_PHASE_2_INTENSITY:
case MADERA_HAPTICS_PHASE_2_DURATION:
case MADERA_HAPTICS_PHASE_3_INTENSITY:
case MADERA_HAPTICS_PHASE_3_DURATION:
case MADERA_HAPTICS_STATUS:
case MADERA_COMFORT_NOISE_GENERATOR:
case MADERA_CLOCK_32K_1:
case MADERA_SYSTEM_CLOCK_1:
case MADERA_SAMPLE_RATE_1:
case MADERA_SAMPLE_RATE_2:
case MADERA_SAMPLE_RATE_3:
case MADERA_SAMPLE_RATE_1_STATUS:
case MADERA_SAMPLE_RATE_2_STATUS:
case MADERA_SAMPLE_RATE_3_STATUS:
case MADERA_ASYNC_CLOCK_1:
case MADERA_ASYNC_SAMPLE_RATE_1:
case MADERA_ASYNC_SAMPLE_RATE_1_STATUS:
case MADERA_ASYNC_SAMPLE_RATE_2:
case MADERA_ASYNC_SAMPLE_RATE_2_STATUS:
case MADERA_DSP_CLOCK_1:
case MADERA_DSP_CLOCK_2:
case MADERA_OUTPUT_SYSTEM_CLOCK:
case MADERA_OUTPUT_ASYNC_CLOCK:
case MADERA_RATE_ESTIMATOR_1:
case MADERA_RATE_ESTIMATOR_2:
case MADERA_RATE_ESTIMATOR_3:
case MADERA_RATE_ESTIMATOR_4:
case MADERA_RATE_ESTIMATOR_5:
case MADERA_FLL1_CONTROL_1:
case MADERA_FLL1_CONTROL_2:
case MADERA_FLL1_CONTROL_3:
case MADERA_FLL1_CONTROL_4:
case MADERA_FLL1_CONTROL_5:
case MADERA_FLL1_CONTROL_6:
case MADERA_FLL1_CONTROL_7:
case MADERA_FLL1_EFS_2:
case MADERA_FLL1_SYNCHRONISER_1:
case MADERA_FLL1_SYNCHRONISER_2:
case MADERA_FLL1_SYNCHRONISER_3:
case MADERA_FLL1_SYNCHRONISER_4:
case MADERA_FLL1_SYNCHRONISER_5:
case MADERA_FLL1_SYNCHRONISER_6:
case MADERA_FLL1_SYNCHRONISER_7:
case MADERA_FLL1_SPREAD_SPECTRUM:
case MADERA_FLL1_GPIO_CLOCK:
case MADERA_FLL2_CONTROL_1:
case MADERA_FLL2_CONTROL_2:
case MADERA_FLL2_CONTROL_3:
case MADERA_FLL2_CONTROL_4:
case MADERA_FLL2_CONTROL_5:
case MADERA_FLL2_CONTROL_6:
case MADERA_FLL2_CONTROL_7:
case MADERA_FLL2_EFS_2:
case MADERA_FLL2_SYNCHRONISER_1:
case MADERA_FLL2_SYNCHRONISER_2:
case MADERA_FLL2_SYNCHRONISER_3:
case MADERA_FLL2_SYNCHRONISER_4:
case MADERA_FLL2_SYNCHRONISER_5:
case MADERA_FLL2_SYNCHRONISER_6:
case MADERA_FLL2_SYNCHRONISER_7:
case MADERA_FLL2_SPREAD_SPECTRUM:
case MADERA_FLL2_GPIO_CLOCK:
case MADERA_FLLAO_CONTROL_1:
case MADERA_FLLAO_CONTROL_2:
case MADERA_FLLAO_CONTROL_3:
case MADERA_FLLAO_CONTROL_4:
case MADERA_FLLAO_CONTROL_5:
case MADERA_FLLAO_CONTROL_6:
case MADERA_FLLAO_CONTROL_7:
case MADERA_FLLAO_CONTROL_8:
case MADERA_FLLAO_CONTROL_9:
case MADERA_FLLAO_CONTROL_10:
case MADERA_FLLAO_CONTROL_11:
case MADERA_MIC_CHARGE_PUMP_1:
case MADERA_LDO2_CONTROL_1:
case MADERA_MIC_BIAS_CTRL_1:
case MADERA_MIC_BIAS_CTRL_2:
case MADERA_MIC_BIAS_CTRL_5:
case MADERA_MIC_BIAS_CTRL_6:
case MADERA_HP_CTRL_1L:
case MADERA_HP_CTRL_1R:
case MADERA_HP_CTRL_2L:
case MADERA_HP_CTRL_2R:
case MADERA_HP_CTRL_3L:
case MADERA_HP_CTRL_3R:
case MADERA_EDRE_HP_STEREO_CONTROL:
case MADERA_ACCESSORY_DETECT_MODE_1:
case MADERA_HEADPHONE_DETECT_0:
case MADERA_HEADPHONE_DETECT_1:
case MADERA_HEADPHONE_DETECT_2:
case MADERA_HEADPHONE_DETECT_3:
case MADERA_HEADPHONE_DETECT_5:
case MADERA_MICD_CLAMP_CONTROL:
case MADERA_MIC_DETECT_1_CONTROL_0:
case MADERA_MIC_DETECT_1_CONTROL_1:
case MADERA_MIC_DETECT_1_CONTROL_2:
case MADERA_MIC_DETECT_1_CONTROL_3:
case MADERA_MIC_DETECT_1_LEVEL_1:
case MADERA_MIC_DETECT_1_LEVEL_2:
case MADERA_MIC_DETECT_1_LEVEL_3:
case MADERA_MIC_DETECT_1_LEVEL_4:
case MADERA_MIC_DETECT_1_CONTROL_4:
case MADERA_MIC_DETECT_2_CONTROL_0:
case MADERA_MIC_DETECT_2_CONTROL_1:
case MADERA_MIC_DETECT_2_CONTROL_2:
case MADERA_MIC_DETECT_2_CONTROL_3:
case MADERA_MIC_DETECT_2_LEVEL_1:
case MADERA_MIC_DETECT_2_LEVEL_2:
case MADERA_MIC_DETECT_2_LEVEL_3:
case MADERA_MIC_DETECT_2_LEVEL_4:
case MADERA_MIC_DETECT_2_CONTROL_4:
case MADERA_GP_SWITCH_1:
case MADERA_JACK_DETECT_ANALOGUE:
case MADERA_INPUT_ENABLES:
case MADERA_INPUT_ENABLES_STATUS:
case MADERA_INPUT_RATE:
case MADERA_INPUT_VOLUME_RAMP:
case MADERA_HPF_CONTROL:
case MADERA_IN1L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_1L:
case MADERA_DMIC1L_CONTROL:
case MADERA_IN1L_RATE_CONTROL:
case MADERA_IN1R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_1R:
case MADERA_DMIC1R_CONTROL:
case MADERA_IN1R_RATE_CONTROL:
case MADERA_IN2L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_2L:
case MADERA_DMIC2L_CONTROL:
case MADERA_IN2L_RATE_CONTROL:
case MADERA_IN2R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_2R:
case MADERA_DMIC2R_CONTROL:
case MADERA_IN2R_RATE_CONTROL:
case MADERA_IN3L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_3L:
case MADERA_DMIC3L_CONTROL:
case MADERA_IN3L_RATE_CONTROL:
case MADERA_IN3R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_3R:
case MADERA_DMIC3R_CONTROL:
case MADERA_IN3R_RATE_CONTROL:
case MADERA_IN4L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_4L:
case MADERA_DMIC4L_CONTROL:
case MADERA_IN4L_RATE_CONTROL:
case MADERA_IN4R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_4R:
case MADERA_DMIC4R_CONTROL:
case MADERA_IN4R_RATE_CONTROL:
case MADERA_IN5L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_5L:
case MADERA_DMIC5L_CONTROL:
case MADERA_IN5L_RATE_CONTROL:
case MADERA_IN5R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_5R:
case MADERA_DMIC5R_CONTROL:
case MADERA_IN5R_RATE_CONTROL:
case MADERA_OUTPUT_ENABLES_1:
case MADERA_OUTPUT_STATUS_1:
case MADERA_RAW_OUTPUT_STATUS_1:
case MADERA_OUTPUT_RATE_1:
case MADERA_OUTPUT_VOLUME_RAMP:
case MADERA_OUTPUT_PATH_CONFIG_1L:
case MADERA_DAC_DIGITAL_VOLUME_1L:
case MADERA_OUTPUT_PATH_CONFIG_1:
case MADERA_NOISE_GATE_SELECT_1L:
case MADERA_OUTPUT_PATH_CONFIG_1R:
case MADERA_DAC_DIGITAL_VOLUME_1R:
case MADERA_NOISE_GATE_SELECT_1R:
case MADERA_OUTPUT_PATH_CONFIG_2L:
case MADERA_DAC_DIGITAL_VOLUME_2L:
case MADERA_OUTPUT_PATH_CONFIG_2:
case MADERA_NOISE_GATE_SELECT_2L:
case MADERA_OUTPUT_PATH_CONFIG_2R:
case MADERA_DAC_DIGITAL_VOLUME_2R:
case MADERA_NOISE_GATE_SELECT_2R:
case MADERA_OUTPUT_PATH_CONFIG_3L:
case MADERA_DAC_DIGITAL_VOLUME_3L:
case MADERA_NOISE_GATE_SELECT_3L:
case MADERA_OUTPUT_PATH_CONFIG_3R:
case MADERA_DAC_DIGITAL_VOLUME_3R:
case MADERA_NOISE_GATE_SELECT_3R:
case MADERA_OUTPUT_PATH_CONFIG_5L:
case MADERA_DAC_DIGITAL_VOLUME_5L:
case MADERA_NOISE_GATE_SELECT_5L:
case MADERA_OUTPUT_PATH_CONFIG_5R:
case MADERA_DAC_DIGITAL_VOLUME_5R:
case MADERA_NOISE_GATE_SELECT_5R:
case MADERA_DAC_AEC_CONTROL_1:
case MADERA_DAC_AEC_CONTROL_2:
case MADERA_NOISE_GATE_CONTROL:
case MADERA_PDM_SPK1_CTRL_1:
case MADERA_PDM_SPK1_CTRL_2:
case MADERA_HP1_SHORT_CIRCUIT_CTRL:
case MADERA_HP2_SHORT_CIRCUIT_CTRL:
case MADERA_HP3_SHORT_CIRCUIT_CTRL:
case MADERA_AIF1_BCLK_CTRL:
case MADERA_AIF1_TX_PIN_CTRL:
case MADERA_AIF1_RX_PIN_CTRL:
case MADERA_AIF1_RATE_CTRL:
case MADERA_AIF1_FORMAT:
case MADERA_AIF1_RX_BCLK_RATE:
case MADERA_AIF1_FRAME_CTRL_1:
case MADERA_AIF1_FRAME_CTRL_2:
case MADERA_AIF1_FRAME_CTRL_3:
case MADERA_AIF1_FRAME_CTRL_4:
case MADERA_AIF1_FRAME_CTRL_5:
case MADERA_AIF1_FRAME_CTRL_6:
case MADERA_AIF1_FRAME_CTRL_7:
case MADERA_AIF1_FRAME_CTRL_8:
case MADERA_AIF1_FRAME_CTRL_9:
case MADERA_AIF1_FRAME_CTRL_10:
case MADERA_AIF1_FRAME_CTRL_11:
case MADERA_AIF1_FRAME_CTRL_12:
case MADERA_AIF1_FRAME_CTRL_13:
case MADERA_AIF1_FRAME_CTRL_14:
case MADERA_AIF1_FRAME_CTRL_15:
case MADERA_AIF1_FRAME_CTRL_16:
case MADERA_AIF1_FRAME_CTRL_17:
case MADERA_AIF1_FRAME_CTRL_18:
case MADERA_AIF1_TX_ENABLES:
case MADERA_AIF1_RX_ENABLES:
case MADERA_AIF2_BCLK_CTRL:
case MADERA_AIF2_TX_PIN_CTRL:
case MADERA_AIF2_RX_PIN_CTRL:
case MADERA_AIF2_RATE_CTRL:
case MADERA_AIF2_FORMAT:
case MADERA_AIF2_RX_BCLK_RATE:
case MADERA_AIF2_FRAME_CTRL_1:
case MADERA_AIF2_FRAME_CTRL_2:
case MADERA_AIF2_FRAME_CTRL_3:
case MADERA_AIF2_FRAME_CTRL_4:
case MADERA_AIF2_FRAME_CTRL_5:
case MADERA_AIF2_FRAME_CTRL_6:
case MADERA_AIF2_FRAME_CTRL_7:
case MADERA_AIF2_FRAME_CTRL_8:
case MADERA_AIF2_FRAME_CTRL_9:
case MADERA_AIF2_FRAME_CTRL_10:
case MADERA_AIF2_FRAME_CTRL_11:
case MADERA_AIF2_FRAME_CTRL_12:
case MADERA_AIF2_FRAME_CTRL_13:
case MADERA_AIF2_FRAME_CTRL_14:
case MADERA_AIF2_FRAME_CTRL_15:
case MADERA_AIF2_FRAME_CTRL_16:
case MADERA_AIF2_FRAME_CTRL_17:
case MADERA_AIF2_FRAME_CTRL_18:
case MADERA_AIF2_TX_ENABLES:
case MADERA_AIF2_RX_ENABLES:
case MADERA_AIF3_BCLK_CTRL:
case MADERA_AIF3_TX_PIN_CTRL:
case MADERA_AIF3_RX_PIN_CTRL:
case MADERA_AIF3_RATE_CTRL:
case MADERA_AIF3_FORMAT:
case MADERA_AIF3_RX_BCLK_RATE:
case MADERA_AIF3_FRAME_CTRL_1:
case MADERA_AIF3_FRAME_CTRL_2:
case MADERA_AIF3_FRAME_CTRL_3:
case MADERA_AIF3_FRAME_CTRL_4:
case MADERA_AIF3_FRAME_CTRL_11:
case MADERA_AIF3_FRAME_CTRL_12:
case MADERA_AIF3_TX_ENABLES:
case MADERA_AIF3_RX_ENABLES:
case MADERA_AIF4_BCLK_CTRL:
case MADERA_AIF4_TX_PIN_CTRL:
case MADERA_AIF4_RX_PIN_CTRL:
case MADERA_AIF4_RATE_CTRL:
case MADERA_AIF4_FORMAT:
case MADERA_AIF4_RX_BCLK_RATE:
case MADERA_AIF4_FRAME_CTRL_1:
case MADERA_AIF4_FRAME_CTRL_2:
case MADERA_AIF4_FRAME_CTRL_3:
case MADERA_AIF4_FRAME_CTRL_4:
case MADERA_AIF4_FRAME_CTRL_11:
case MADERA_AIF4_FRAME_CTRL_12:
case MADERA_AIF4_TX_ENABLES:
case MADERA_AIF4_RX_ENABLES:
case MADERA_SPD1_TX_CONTROL:
case MADERA_SPD1_TX_CHANNEL_STATUS_1:
case MADERA_SPD1_TX_CHANNEL_STATUS_2:
case MADERA_SPD1_TX_CHANNEL_STATUS_3:
case MADERA_SLIMBUS_FRAMER_REF_GEAR:
case MADERA_SLIMBUS_RATES_1:
case MADERA_SLIMBUS_RATES_2:
case MADERA_SLIMBUS_RATES_3:
case MADERA_SLIMBUS_RATES_4:
case MADERA_SLIMBUS_RATES_5:
case MADERA_SLIMBUS_RATES_6:
case MADERA_SLIMBUS_RATES_7:
case MADERA_SLIMBUS_RATES_8:
case MADERA_SLIMBUS_RX_CHANNEL_ENABLE:
case MADERA_SLIMBUS_TX_CHANNEL_ENABLE:
case MADERA_SLIMBUS_RX_PORT_STATUS:
case MADERA_SLIMBUS_TX_PORT_STATUS:
case MADERA_PWM1MIX_INPUT_1_SOURCE:
case MADERA_PWM1MIX_INPUT_1_VOLUME:
case MADERA_PWM1MIX_INPUT_2_SOURCE:
case MADERA_PWM1MIX_INPUT_2_VOLUME:
case MADERA_PWM1MIX_INPUT_3_SOURCE:
case MADERA_PWM1MIX_INPUT_3_VOLUME:
case MADERA_PWM1MIX_INPUT_4_SOURCE:
case MADERA_PWM1MIX_INPUT_4_VOLUME:
case MADERA_PWM2MIX_INPUT_1_SOURCE:
case MADERA_PWM2MIX_INPUT_1_VOLUME:
case MADERA_PWM2MIX_INPUT_2_SOURCE:
case MADERA_PWM2MIX_INPUT_2_VOLUME:
case MADERA_PWM2MIX_INPUT_3_SOURCE:
case MADERA_PWM2MIX_INPUT_3_VOLUME:
case MADERA_PWM2MIX_INPUT_4_SOURCE:
case MADERA_PWM2MIX_INPUT_4_VOLUME:
case MADERA_OUT1LMIX_INPUT_1_SOURCE:
case MADERA_OUT1LMIX_INPUT_1_VOLUME:
case MADERA_OUT1LMIX_INPUT_2_SOURCE:
case MADERA_OUT1LMIX_INPUT_2_VOLUME:
case MADERA_OUT1LMIX_INPUT_3_SOURCE:
case MADERA_OUT1LMIX_INPUT_3_VOLUME:
case MADERA_OUT1LMIX_INPUT_4_SOURCE:
case MADERA_OUT1LMIX_INPUT_4_VOLUME:
case MADERA_OUT1RMIX_INPUT_1_SOURCE:
case MADERA_OUT1RMIX_INPUT_1_VOLUME:
case MADERA_OUT1RMIX_INPUT_2_SOURCE:
case MADERA_OUT1RMIX_INPUT_2_VOLUME:
case MADERA_OUT1RMIX_INPUT_3_SOURCE:
case MADERA_OUT1RMIX_INPUT_3_VOLUME:
case MADERA_OUT1RMIX_INPUT_4_SOURCE:
case MADERA_OUT1RMIX_INPUT_4_VOLUME:
case MADERA_OUT2LMIX_INPUT_1_SOURCE:
case MADERA_OUT2LMIX_INPUT_1_VOLUME:
case MADERA_OUT2LMIX_INPUT_2_SOURCE:
case MADERA_OUT2LMIX_INPUT_2_VOLUME:
case MADERA_OUT2LMIX_INPUT_3_SOURCE:
case MADERA_OUT2LMIX_INPUT_3_VOLUME:
case MADERA_OUT2LMIX_INPUT_4_SOURCE:
case MADERA_OUT2LMIX_INPUT_4_VOLUME:
case MADERA_OUT2RMIX_INPUT_1_SOURCE:
case MADERA_OUT2RMIX_INPUT_1_VOLUME:
case MADERA_OUT2RMIX_INPUT_2_SOURCE:
case MADERA_OUT2RMIX_INPUT_2_VOLUME:
case MADERA_OUT2RMIX_INPUT_3_SOURCE:
case MADERA_OUT2RMIX_INPUT_3_VOLUME:
case MADERA_OUT2RMIX_INPUT_4_SOURCE:
case MADERA_OUT2RMIX_INPUT_4_VOLUME:
case MADERA_OUT3LMIX_INPUT_1_SOURCE:
case MADERA_OUT3LMIX_INPUT_1_VOLUME:
case MADERA_OUT3LMIX_INPUT_2_SOURCE:
case MADERA_OUT3LMIX_INPUT_2_VOLUME:
case MADERA_OUT3LMIX_INPUT_3_SOURCE:
case MADERA_OUT3LMIX_INPUT_3_VOLUME:
case MADERA_OUT3LMIX_INPUT_4_SOURCE:
case MADERA_OUT3LMIX_INPUT_4_VOLUME:
case MADERA_OUT3RMIX_INPUT_1_SOURCE:
case MADERA_OUT3RMIX_INPUT_1_VOLUME:
case MADERA_OUT3RMIX_INPUT_2_SOURCE:
case MADERA_OUT3RMIX_INPUT_2_VOLUME:
case MADERA_OUT3RMIX_INPUT_3_SOURCE:
case MADERA_OUT3RMIX_INPUT_3_VOLUME:
case MADERA_OUT3RMIX_INPUT_4_SOURCE:
case MADERA_OUT3RMIX_INPUT_4_VOLUME:
case MADERA_OUT5LMIX_INPUT_1_SOURCE:
case MADERA_OUT5LMIX_INPUT_1_VOLUME:
case MADERA_OUT5LMIX_INPUT_2_SOURCE:
case MADERA_OUT5LMIX_INPUT_2_VOLUME:
case MADERA_OUT5LMIX_INPUT_3_SOURCE:
case MADERA_OUT5LMIX_INPUT_3_VOLUME:
case MADERA_OUT5LMIX_INPUT_4_SOURCE:
case MADERA_OUT5LMIX_INPUT_4_VOLUME:
case MADERA_OUT5RMIX_INPUT_1_SOURCE:
case MADERA_OUT5RMIX_INPUT_1_VOLUME:
case MADERA_OUT5RMIX_INPUT_2_SOURCE:
case MADERA_OUT5RMIX_INPUT_2_VOLUME:
case MADERA_OUT5RMIX_INPUT_3_SOURCE:
case MADERA_OUT5RMIX_INPUT_3_VOLUME:
case MADERA_OUT5RMIX_INPUT_4_SOURCE:
case MADERA_OUT5RMIX_INPUT_4_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX7MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX7MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX7MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX7MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX7MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX7MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX7MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX7MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX8MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX8MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX8MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX8MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX8MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX8MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX8MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX8MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX5MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX5MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX5MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX5MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX5MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX5MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX5MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX5MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX6MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX6MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX6MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX6MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX6MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX6MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX6MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX6MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX7MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX7MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX7MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX7MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX7MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX7MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX7MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX7MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX8MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX8MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX8MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX8MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX8MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX8MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX8MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX8MIX_INPUT_4_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_4_VOLUME:
case MADERA_AIF4TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF4TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF4TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF4TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF4TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF4TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF4TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF4TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF4TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF4TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF4TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF4TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF4TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF4TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF4TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF4TX2MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX7MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX7MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX7MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX7MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX7MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX7MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX7MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX7MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX8MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX8MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX8MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX8MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX8MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX8MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX8MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX8MIX_INPUT_4_VOLUME:
case MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE:
case MADERA_SPDIF1TX1MIX_INPUT_1_VOLUME:
case MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE:
case MADERA_SPDIF1TX2MIX_INPUT_1_VOLUME:
case MADERA_EQ1MIX_INPUT_1_SOURCE:
case MADERA_EQ1MIX_INPUT_1_VOLUME:
case MADERA_EQ1MIX_INPUT_2_SOURCE:
case MADERA_EQ1MIX_INPUT_2_VOLUME:
case MADERA_EQ1MIX_INPUT_3_SOURCE:
case MADERA_EQ1MIX_INPUT_3_VOLUME:
case MADERA_EQ1MIX_INPUT_4_SOURCE:
case MADERA_EQ1MIX_INPUT_4_VOLUME:
case MADERA_EQ2MIX_INPUT_1_SOURCE:
case MADERA_EQ2MIX_INPUT_1_VOLUME:
case MADERA_EQ2MIX_INPUT_2_SOURCE:
case MADERA_EQ2MIX_INPUT_2_VOLUME:
case MADERA_EQ2MIX_INPUT_3_SOURCE:
case MADERA_EQ2MIX_INPUT_3_VOLUME:
case MADERA_EQ2MIX_INPUT_4_SOURCE:
case MADERA_EQ2MIX_INPUT_4_VOLUME:
case MADERA_EQ3MIX_INPUT_1_SOURCE:
case MADERA_EQ3MIX_INPUT_1_VOLUME:
case MADERA_EQ3MIX_INPUT_2_SOURCE:
case MADERA_EQ3MIX_INPUT_2_VOLUME:
case MADERA_EQ3MIX_INPUT_3_SOURCE:
case MADERA_EQ3MIX_INPUT_3_VOLUME:
case MADERA_EQ3MIX_INPUT_4_SOURCE:
case MADERA_EQ3MIX_INPUT_4_VOLUME:
case MADERA_EQ4MIX_INPUT_1_SOURCE:
case MADERA_EQ4MIX_INPUT_1_VOLUME:
case MADERA_EQ4MIX_INPUT_2_SOURCE:
case MADERA_EQ4MIX_INPUT_2_VOLUME:
case MADERA_EQ4MIX_INPUT_3_SOURCE:
case MADERA_EQ4MIX_INPUT_3_VOLUME:
case MADERA_EQ4MIX_INPUT_4_SOURCE:
case MADERA_EQ4MIX_INPUT_4_VOLUME:
case MADERA_DRC1LMIX_INPUT_1_SOURCE:
case MADERA_DRC1LMIX_INPUT_1_VOLUME:
case MADERA_DRC1LMIX_INPUT_2_SOURCE:
case MADERA_DRC1LMIX_INPUT_2_VOLUME:
case MADERA_DRC1LMIX_INPUT_3_SOURCE:
case MADERA_DRC1LMIX_INPUT_3_VOLUME:
case MADERA_DRC1LMIX_INPUT_4_SOURCE:
case MADERA_DRC1LMIX_INPUT_4_VOLUME:
case MADERA_DRC1RMIX_INPUT_1_SOURCE:
case MADERA_DRC1RMIX_INPUT_1_VOLUME:
case MADERA_DRC1RMIX_INPUT_2_SOURCE:
case MADERA_DRC1RMIX_INPUT_2_VOLUME:
case MADERA_DRC1RMIX_INPUT_3_SOURCE:
case MADERA_DRC1RMIX_INPUT_3_VOLUME:
case MADERA_DRC1RMIX_INPUT_4_SOURCE:
case MADERA_DRC1RMIX_INPUT_4_VOLUME:
case MADERA_DRC2LMIX_INPUT_1_SOURCE:
case MADERA_DRC2LMIX_INPUT_1_VOLUME:
case MADERA_DRC2LMIX_INPUT_2_SOURCE:
case MADERA_DRC2LMIX_INPUT_2_VOLUME:
case MADERA_DRC2LMIX_INPUT_3_SOURCE:
case MADERA_DRC2LMIX_INPUT_3_VOLUME:
case MADERA_DRC2LMIX_INPUT_4_SOURCE:
case MADERA_DRC2LMIX_INPUT_4_VOLUME:
case MADERA_DRC2RMIX_INPUT_1_SOURCE:
case MADERA_DRC2RMIX_INPUT_1_VOLUME:
case MADERA_DRC2RMIX_INPUT_2_SOURCE:
case MADERA_DRC2RMIX_INPUT_2_VOLUME:
case MADERA_DRC2RMIX_INPUT_3_SOURCE:
case MADERA_DRC2RMIX_INPUT_3_VOLUME:
case MADERA_DRC2RMIX_INPUT_4_SOURCE:
case MADERA_DRC2RMIX_INPUT_4_VOLUME:
case MADERA_HPLP1MIX_INPUT_1_SOURCE:
case MADERA_HPLP1MIX_INPUT_1_VOLUME:
case MADERA_HPLP1MIX_INPUT_2_SOURCE:
case MADERA_HPLP1MIX_INPUT_2_VOLUME:
case MADERA_HPLP1MIX_INPUT_3_SOURCE:
case MADERA_HPLP1MIX_INPUT_3_VOLUME:
case MADERA_HPLP1MIX_INPUT_4_SOURCE:
case MADERA_HPLP1MIX_INPUT_4_VOLUME:
case MADERA_HPLP2MIX_INPUT_1_SOURCE:
case MADERA_HPLP2MIX_INPUT_1_VOLUME:
case MADERA_HPLP2MIX_INPUT_2_SOURCE:
case MADERA_HPLP2MIX_INPUT_2_VOLUME:
case MADERA_HPLP2MIX_INPUT_3_SOURCE:
case MADERA_HPLP2MIX_INPUT_3_VOLUME:
case MADERA_HPLP2MIX_INPUT_4_SOURCE:
case MADERA_HPLP2MIX_INPUT_4_VOLUME:
case MADERA_HPLP3MIX_INPUT_1_SOURCE:
case MADERA_HPLP3MIX_INPUT_1_VOLUME:
case MADERA_HPLP3MIX_INPUT_2_SOURCE:
case MADERA_HPLP3MIX_INPUT_2_VOLUME:
case MADERA_HPLP3MIX_INPUT_3_SOURCE:
case MADERA_HPLP3MIX_INPUT_3_VOLUME:
case MADERA_HPLP3MIX_INPUT_4_SOURCE:
case MADERA_HPLP3MIX_INPUT_4_VOLUME:
case MADERA_HPLP4MIX_INPUT_1_SOURCE:
case MADERA_HPLP4MIX_INPUT_1_VOLUME:
case MADERA_HPLP4MIX_INPUT_2_SOURCE:
case MADERA_HPLP4MIX_INPUT_2_VOLUME:
case MADERA_HPLP4MIX_INPUT_3_SOURCE:
case MADERA_HPLP4MIX_INPUT_3_VOLUME:
case MADERA_HPLP4MIX_INPUT_4_SOURCE:
case MADERA_HPLP4MIX_INPUT_4_VOLUME:
case MADERA_DSP1LMIX_INPUT_1_SOURCE:
case MADERA_DSP1LMIX_INPUT_1_VOLUME:
case MADERA_DSP1LMIX_INPUT_2_SOURCE:
case MADERA_DSP1LMIX_INPUT_2_VOLUME:
case MADERA_DSP1LMIX_INPUT_3_SOURCE:
case MADERA_DSP1LMIX_INPUT_3_VOLUME:
case MADERA_DSP1LMIX_INPUT_4_SOURCE:
case MADERA_DSP1LMIX_INPUT_4_VOLUME:
case MADERA_DSP1RMIX_INPUT_1_SOURCE:
case MADERA_DSP1RMIX_INPUT_1_VOLUME:
case MADERA_DSP1RMIX_INPUT_2_SOURCE:
case MADERA_DSP1RMIX_INPUT_2_VOLUME:
case MADERA_DSP1RMIX_INPUT_3_SOURCE:
case MADERA_DSP1RMIX_INPUT_3_VOLUME:
case MADERA_DSP1RMIX_INPUT_4_SOURCE:
case MADERA_DSP1RMIX_INPUT_4_VOLUME:
case MADERA_DSP1AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX6MIX_INPUT_1_SOURCE:
case MADERA_DSP2LMIX_INPUT_1_SOURCE:
case MADERA_DSP2LMIX_INPUT_1_VOLUME:
case MADERA_DSP2LMIX_INPUT_2_SOURCE:
case MADERA_DSP2LMIX_INPUT_2_VOLUME:
case MADERA_DSP2LMIX_INPUT_3_SOURCE:
case MADERA_DSP2LMIX_INPUT_3_VOLUME:
case MADERA_DSP2LMIX_INPUT_4_SOURCE:
case MADERA_DSP2LMIX_INPUT_4_VOLUME:
case MADERA_DSP2RMIX_INPUT_1_SOURCE:
case MADERA_DSP2RMIX_INPUT_1_VOLUME:
case MADERA_DSP2RMIX_INPUT_2_SOURCE:
case MADERA_DSP2RMIX_INPUT_2_VOLUME:
case MADERA_DSP2RMIX_INPUT_3_SOURCE:
case MADERA_DSP2RMIX_INPUT_3_VOLUME:
case MADERA_DSP2RMIX_INPUT_4_SOURCE:
case MADERA_DSP2RMIX_INPUT_4_VOLUME:
case MADERA_DSP2AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP2AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP2AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP2AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP2AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP2AUX6MIX_INPUT_1_SOURCE:
case MADERA_DSP3LMIX_INPUT_1_SOURCE:
case MADERA_DSP3LMIX_INPUT_1_VOLUME:
case MADERA_DSP3LMIX_INPUT_2_SOURCE:
case MADERA_DSP3LMIX_INPUT_2_VOLUME:
case MADERA_DSP3LMIX_INPUT_3_SOURCE:
case MADERA_DSP3LMIX_INPUT_3_VOLUME:
case MADERA_DSP3LMIX_INPUT_4_SOURCE:
case MADERA_DSP3LMIX_INPUT_4_VOLUME:
case MADERA_DSP3RMIX_INPUT_1_SOURCE:
case MADERA_DSP3RMIX_INPUT_1_VOLUME:
case MADERA_DSP3RMIX_INPUT_2_SOURCE:
case MADERA_DSP3RMIX_INPUT_2_VOLUME:
case MADERA_DSP3RMIX_INPUT_3_SOURCE:
case MADERA_DSP3RMIX_INPUT_3_VOLUME:
case MADERA_DSP3RMIX_INPUT_4_SOURCE:
case MADERA_DSP3RMIX_INPUT_4_VOLUME:
case MADERA_DSP3AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP3AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP3AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP3AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP3AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP3AUX6MIX_INPUT_1_SOURCE:
case MADERA_DSP4LMIX_INPUT_1_SOURCE:
case MADERA_DSP4LMIX_INPUT_1_VOLUME:
case MADERA_DSP4LMIX_INPUT_2_SOURCE:
case MADERA_DSP4LMIX_INPUT_2_VOLUME:
case MADERA_DSP4LMIX_INPUT_3_SOURCE:
case MADERA_DSP4LMIX_INPUT_3_VOLUME:
case MADERA_DSP4LMIX_INPUT_4_SOURCE:
case MADERA_DSP4LMIX_INPUT_4_VOLUME:
case MADERA_DSP4RMIX_INPUT_1_SOURCE:
case MADERA_DSP4RMIX_INPUT_1_VOLUME:
case MADERA_DSP4RMIX_INPUT_2_SOURCE:
case MADERA_DSP4RMIX_INPUT_2_VOLUME:
case MADERA_DSP4RMIX_INPUT_3_SOURCE:
case MADERA_DSP4RMIX_INPUT_3_VOLUME:
case MADERA_DSP4RMIX_INPUT_4_SOURCE:
case MADERA_DSP4RMIX_INPUT_4_VOLUME:
case MADERA_DSP4AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP4AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP4AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP4AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP4AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP4AUX6MIX_INPUT_1_SOURCE:
case MADERA_DSP5LMIX_INPUT_1_SOURCE:
case MADERA_DSP5LMIX_INPUT_1_VOLUME:
case MADERA_DSP5LMIX_INPUT_2_SOURCE:
case MADERA_DSP5LMIX_INPUT_2_VOLUME:
case MADERA_DSP5LMIX_INPUT_3_SOURCE:
case MADERA_DSP5LMIX_INPUT_3_VOLUME:
case MADERA_DSP5LMIX_INPUT_4_SOURCE:
case MADERA_DSP5LMIX_INPUT_4_VOLUME:
case MADERA_DSP5RMIX_INPUT_1_SOURCE:
case MADERA_DSP5RMIX_INPUT_1_VOLUME:
case MADERA_DSP5RMIX_INPUT_2_SOURCE:
case MADERA_DSP5RMIX_INPUT_2_VOLUME:
case MADERA_DSP5RMIX_INPUT_3_SOURCE:
case MADERA_DSP5RMIX_INPUT_3_VOLUME:
case MADERA_DSP5RMIX_INPUT_4_SOURCE:
case MADERA_DSP5RMIX_INPUT_4_VOLUME:
case MADERA_DSP5AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP5AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP5AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP5AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP5AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP5AUX6MIX_INPUT_1_SOURCE:
case MADERA_ASRC1_1LMIX_INPUT_1_SOURCE:
case MADERA_ASRC1_1RMIX_INPUT_1_SOURCE:
case MADERA_ASRC1_2LMIX_INPUT_1_SOURCE:
case MADERA_ASRC1_2RMIX_INPUT_1_SOURCE:
case MADERA_ASRC2_1LMIX_INPUT_1_SOURCE:
case MADERA_ASRC2_1RMIX_INPUT_1_SOURCE:
case MADERA_ASRC2_2LMIX_INPUT_1_SOURCE:
case MADERA_ASRC2_2RMIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC3MIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC4MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT1MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT2MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT3MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT4MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC3MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC4MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT1MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT2MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT3MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT4MIX_INPUT_1_SOURCE:
case MADERA_ISRC3DEC1MIX_INPUT_1_SOURCE:
case MADERA_ISRC3DEC2MIX_INPUT_1_SOURCE:
case MADERA_ISRC3INT1MIX_INPUT_1_SOURCE:
case MADERA_ISRC3INT2MIX_INPUT_1_SOURCE:
case MADERA_ISRC4DEC1MIX_INPUT_1_SOURCE:
case MADERA_ISRC4DEC2MIX_INPUT_1_SOURCE:
case MADERA_ISRC4INT1MIX_INPUT_1_SOURCE:
case MADERA_ISRC4INT2MIX_INPUT_1_SOURCE:
case MADERA_DSP6LMIX_INPUT_1_SOURCE:
case MADERA_DSP6LMIX_INPUT_1_VOLUME:
case MADERA_DSP6LMIX_INPUT_2_SOURCE:
case MADERA_DSP6LMIX_INPUT_2_VOLUME:
case MADERA_DSP6LMIX_INPUT_3_SOURCE:
case MADERA_DSP6LMIX_INPUT_3_VOLUME:
case MADERA_DSP6LMIX_INPUT_4_SOURCE:
case MADERA_DSP6LMIX_INPUT_4_VOLUME:
case MADERA_DSP6RMIX_INPUT_1_SOURCE:
case MADERA_DSP6RMIX_INPUT_1_VOLUME:
case MADERA_DSP6RMIX_INPUT_2_SOURCE:
case MADERA_DSP6RMIX_INPUT_2_VOLUME:
case MADERA_DSP6RMIX_INPUT_3_SOURCE:
case MADERA_DSP6RMIX_INPUT_3_VOLUME:
case MADERA_DSP6RMIX_INPUT_4_SOURCE:
case MADERA_DSP6RMIX_INPUT_4_VOLUME:
case MADERA_DSP6AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP6AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP6AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP6AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP6AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP6AUX6MIX_INPUT_1_SOURCE:
case MADERA_DSP7LMIX_INPUT_1_SOURCE:
case MADERA_DSP7LMIX_INPUT_1_VOLUME:
case MADERA_DSP7LMIX_INPUT_2_SOURCE:
case MADERA_DSP7LMIX_INPUT_2_VOLUME:
case MADERA_DSP7LMIX_INPUT_3_SOURCE:
case MADERA_DSP7LMIX_INPUT_3_VOLUME:
case MADERA_DSP7LMIX_INPUT_4_SOURCE:
case MADERA_DSP7LMIX_INPUT_4_VOLUME:
case MADERA_DSP7RMIX_INPUT_1_SOURCE:
case MADERA_DSP7RMIX_INPUT_1_VOLUME:
case MADERA_DSP7RMIX_INPUT_2_SOURCE:
case MADERA_DSP7RMIX_INPUT_2_VOLUME:
case MADERA_DSP7RMIX_INPUT_3_SOURCE:
case MADERA_DSP7RMIX_INPUT_3_VOLUME:
case MADERA_DSP7RMIX_INPUT_4_SOURCE:
case MADERA_DSP7RMIX_INPUT_4_VOLUME:
case MADERA_DSP7AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP7AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP7AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP7AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP7AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP7AUX6MIX_INPUT_1_SOURCE:
case MADERA_DFC1MIX_INPUT_1_SOURCE:
case MADERA_DFC2MIX_INPUT_1_SOURCE:
case MADERA_DFC3MIX_INPUT_1_SOURCE:
case MADERA_DFC4MIX_INPUT_1_SOURCE:
case MADERA_DFC5MIX_INPUT_1_SOURCE:
case MADERA_DFC6MIX_INPUT_1_SOURCE:
case MADERA_DFC7MIX_INPUT_1_SOURCE:
case MADERA_DFC8MIX_INPUT_1_SOURCE:
case MADERA_FX_CTRL1:
case MADERA_FX_CTRL2:
case MADERA_EQ1_1 ... MADERA_EQ1_21:
case MADERA_EQ2_1 ... MADERA_EQ2_21:
case MADERA_EQ3_1 ... MADERA_EQ3_21:
case MADERA_EQ4_1 ... MADERA_EQ4_21:
case MADERA_DRC1_CTRL1:
case MADERA_DRC1_CTRL2:
case MADERA_DRC1_CTRL3:
case MADERA_DRC1_CTRL4:
case MADERA_DRC1_CTRL5:
case MADERA_DRC2_CTRL1:
case MADERA_DRC2_CTRL2:
case MADERA_DRC2_CTRL3:
case MADERA_DRC2_CTRL4:
case MADERA_DRC2_CTRL5:
case MADERA_HPLPF1_1:
case MADERA_HPLPF1_2:
case MADERA_HPLPF2_1:
case MADERA_HPLPF2_2:
case MADERA_HPLPF3_1:
case MADERA_HPLPF3_2:
case MADERA_HPLPF4_1:
case MADERA_HPLPF4_2:
case MADERA_ASRC1_ENABLE:
case MADERA_ASRC1_STATUS:
case MADERA_ASRC1_RATE1:
case MADERA_ASRC1_RATE2:
case MADERA_ASRC2_ENABLE:
case MADERA_ASRC2_STATUS:
case MADERA_ASRC2_RATE1:
case MADERA_ASRC2_RATE2:
case MADERA_ISRC_1_CTRL_1:
case MADERA_ISRC_1_CTRL_2:
case MADERA_ISRC_1_CTRL_3:
case MADERA_ISRC_2_CTRL_1:
case MADERA_ISRC_2_CTRL_2:
case MADERA_ISRC_2_CTRL_3:
case MADERA_ISRC_3_CTRL_1:
case MADERA_ISRC_3_CTRL_2:
case MADERA_ISRC_3_CTRL_3:
case MADERA_ISRC_4_CTRL_1:
case MADERA_ISRC_4_CTRL_2:
case MADERA_ISRC_4_CTRL_3:
case MADERA_CLOCK_CONTROL:
case MADERA_ANC_SRC:
case MADERA_DSP_STATUS:
case MADERA_ANC_COEFF_START ... MADERA_ANC_COEFF_END:
case MADERA_FCL_FILTER_CONTROL:
case MADERA_FCL_ADC_REFORMATTER_CONTROL:
case MADERA_FCL_COEFF_START ... MADERA_FCL_COEFF_END:
case MADERA_FCR_FILTER_CONTROL:
case MADERA_FCR_ADC_REFORMATTER_CONTROL:
case MADERA_FCR_COEFF_START ... MADERA_FCR_COEFF_END:
case MADERA_DFC1_CTRL:
case MADERA_DFC1_RX:
case MADERA_DFC1_TX:
case MADERA_DFC2_CTRL:
case MADERA_DFC2_RX:
case MADERA_DFC2_TX:
case MADERA_DFC3_CTRL:
case MADERA_DFC3_RX:
case MADERA_DFC3_TX:
case MADERA_DFC4_CTRL:
case MADERA_DFC4_RX:
case MADERA_DFC4_TX:
case MADERA_DFC5_CTRL:
case MADERA_DFC5_RX:
case MADERA_DFC5_TX:
case MADERA_DFC6_CTRL:
case MADERA_DFC6_RX:
case MADERA_DFC6_TX:
case MADERA_DFC7_CTRL:
case MADERA_DFC7_RX:
case MADERA_DFC7_TX:
case MADERA_DFC8_CTRL:
case MADERA_DFC8_RX:
case MADERA_DFC8_TX:
case MADERA_DFC_STATUS:
case MADERA_GPIO1_CTRL_1 ... MADERA_GPIO38_CTRL_2:
case MADERA_IRQ1_STATUS_1 ... MADERA_IRQ1_STATUS_33:
case MADERA_IRQ1_MASK_1 ... MADERA_IRQ1_MASK_33:
case MADERA_IRQ1_RAW_STATUS_1 ... MADERA_IRQ1_RAW_STATUS_33:
case MADERA_INTERRUPT_DEBOUNCE_7:
case MADERA_IRQ1_CTRL:
return true;
default:
return false;
}
}
static bool cs47l90_16bit_volatile_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_SOFTWARE_RESET:
case MADERA_HARDWARE_REVISION:
case MADERA_WRITE_SEQUENCER_CTRL_0:
case MADERA_WRITE_SEQUENCER_CTRL_1:
case MADERA_WRITE_SEQUENCER_CTRL_2:
case MADERA_HAPTICS_STATUS:
case MADERA_SAMPLE_RATE_1_STATUS:
case MADERA_SAMPLE_RATE_2_STATUS:
case MADERA_SAMPLE_RATE_3_STATUS:
case MADERA_ASYNC_SAMPLE_RATE_1_STATUS:
case MADERA_ASYNC_SAMPLE_RATE_2_STATUS:
case MADERA_HP_CTRL_1L:
case MADERA_HP_CTRL_1R:
case MADERA_HP_CTRL_2L:
case MADERA_HP_CTRL_2R:
case MADERA_HP_CTRL_3L:
case MADERA_HP_CTRL_3R:
case MADERA_MIC_DETECT_1_CONTROL_3:
case MADERA_MIC_DETECT_1_CONTROL_4:
case MADERA_MIC_DETECT_2_CONTROL_3:
case MADERA_MIC_DETECT_2_CONTROL_4:
case MADERA_HEADPHONE_DETECT_2:
case MADERA_HEADPHONE_DETECT_3:
case MADERA_HEADPHONE_DETECT_5:
case MADERA_INPUT_ENABLES_STATUS:
case MADERA_OUTPUT_STATUS_1:
case MADERA_RAW_OUTPUT_STATUS_1:
case MADERA_SPD1_TX_CHANNEL_STATUS_1:
case MADERA_SPD1_TX_CHANNEL_STATUS_2:
case MADERA_SPD1_TX_CHANNEL_STATUS_3:
case MADERA_SLIMBUS_RX_PORT_STATUS:
case MADERA_SLIMBUS_TX_PORT_STATUS:
case MADERA_FX_CTRL2:
case MADERA_ASRC2_STATUS:
case MADERA_ASRC1_STATUS:
case MADERA_CLOCK_CONTROL:
case MADERA_DFC_STATUS:
case MADERA_IRQ1_STATUS_1 ... MADERA_IRQ1_STATUS_33:
case MADERA_IRQ1_RAW_STATUS_1 ... MADERA_IRQ1_RAW_STATUS_33:
return true;
default:
return false;
}
}
static bool cs47l90_32bit_readable_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_WSEQ_SEQUENCE_1 ... MADERA_WSEQ_SEQUENCE_508:
case MADERA_OTP_HPDET_CAL_1 ... MADERA_OTP_HPDET_CAL_2:
case MADERA_DSP1_CONFIG_1 ... MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
case MADERA_DSP2_CONFIG_1 ... MADERA_DSP2_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
case MADERA_DSP3_CONFIG_1 ... MADERA_DSP3_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
case MADERA_DSP4_CONFIG_1 ... MADERA_DSP4_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
case MADERA_DSP5_CONFIG_1 ... MADERA_DSP5_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
case MADERA_DSP6_CONFIG_1 ... MADERA_DSP6_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
case MADERA_DSP7_CONFIG_1 ... MADERA_DSP7_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
return true;
default:
return cs47l90_is_adsp_memory(reg);
}
}
static bool cs47l90_32bit_volatile_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_WSEQ_SEQUENCE_1 ... MADERA_WSEQ_SEQUENCE_508:
case MADERA_OTP_HPDET_CAL_1 ... MADERA_OTP_HPDET_CAL_2:
case MADERA_DSP1_CONFIG_1 ... MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
case MADERA_DSP2_CONFIG_1 ... MADERA_DSP2_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
case MADERA_DSP3_CONFIG_1 ... MADERA_DSP3_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
case MADERA_DSP4_CONFIG_1 ... MADERA_DSP4_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
case MADERA_DSP5_CONFIG_1 ... MADERA_DSP5_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
case MADERA_DSP6_CONFIG_1 ... MADERA_DSP6_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
case MADERA_DSP7_CONFIG_1 ... MADERA_DSP7_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
return true;
default:
return cs47l90_is_adsp_memory(reg);
}
}
const struct regmap_config cs47l90_16bit_spi_regmap = {
.name = "cs47l90_16bit",
.reg_bits = 32,
.pad_bits = 16,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = MADERA_INTERRUPT_RAW_STATUS_1,
.readable_reg = cs47l90_16bit_readable_register,
.volatile_reg = cs47l90_16bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = cs47l90_reg_default,
.num_reg_defaults = ARRAY_SIZE(cs47l90_reg_default),
};
EXPORT_SYMBOL_GPL(cs47l90_16bit_spi_regmap);
const struct regmap_config cs47l90_16bit_i2c_regmap = {
.name = "cs47l90_16bit",
.reg_bits = 32,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = MADERA_INTERRUPT_RAW_STATUS_1,
.readable_reg = cs47l90_16bit_readable_register,
.volatile_reg = cs47l90_16bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = cs47l90_reg_default,
.num_reg_defaults = ARRAY_SIZE(cs47l90_reg_default),
};
EXPORT_SYMBOL_GPL(cs47l90_16bit_i2c_regmap);
const struct regmap_config cs47l90_32bit_spi_regmap = {
.name = "cs47l90_32bit",
.reg_bits = 32,
.reg_stride = 2,
.pad_bits = 16,
.val_bits = 32,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = MADERA_DSP7_PMEM_ERR_ADDR___XMEM_ERR_ADDR,
.readable_reg = cs47l90_32bit_readable_register,
.volatile_reg = cs47l90_32bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(cs47l90_32bit_spi_regmap);
const struct regmap_config cs47l90_32bit_i2c_regmap = {
.name = "cs47l90_32bit",
.reg_bits = 32,
.reg_stride = 2,
.val_bits = 32,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = MADERA_DSP7_PMEM_ERR_ADDR___XMEM_ERR_ADDR,
.readable_reg = cs47l90_32bit_readable_register,
.volatile_reg = cs47l90_32bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(cs47l90_32bit_i2c_regmap);
| linux-master | drivers/mfd/cs47l90-tables.c |
// SPDX-License-Identifier: GPL-2.0+
//
// MFD core driver for the Maxim MAX77843
//
// Copyright (C) 2015 Samsung Electronics
// Author: Jaewon Kim <[email protected]>
// Author: Beomho Seo <[email protected]>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mfd/max77693-common.h>
#include <linux/mfd/max77843-private.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
static const struct mfd_cell max77843_devs[] = {
{
.name = "max77843-muic",
.of_compatible = "maxim,max77843-muic",
}, {
.name = "max77843-regulator",
.of_compatible = "maxim,max77843-regulator",
}, {
.name = "max77843-charger",
.of_compatible = "maxim,max77843-charger"
}, {
.name = "max77843-fuelgauge",
.of_compatible = "maxim,max77843-fuelgauge",
}, {
.name = "max77843-haptic",
.of_compatible = "maxim,max77843-haptic",
},
};
static const struct regmap_config max77843_charger_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX77843_CHG_REG_END,
};
static const struct regmap_config max77843_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX77843_SYS_REG_END,
};
static const struct regmap_irq max77843_irqs[] = {
/* TOPSYS interrupts */
{ .reg_offset = 0, .mask = MAX77843_SYS_IRQ_SYSUVLO_INT, },
{ .reg_offset = 0, .mask = MAX77843_SYS_IRQ_SYSOVLO_INT, },
{ .reg_offset = 0, .mask = MAX77843_SYS_IRQ_TSHDN_INT, },
{ .reg_offset = 0, .mask = MAX77843_SYS_IRQ_TM_INT, },
};
static const struct regmap_irq_chip max77843_irq_chip = {
.name = "max77843",
.status_base = MAX77843_SYS_REG_SYSINTSRC,
.mask_base = MAX77843_SYS_REG_SYSINTMASK,
.num_regs = 1,
.irqs = max77843_irqs,
.num_irqs = ARRAY_SIZE(max77843_irqs),
};
/* Charger and Charger regulator use same regmap. */
static int max77843_chg_init(struct max77693_dev *max77843)
{
int ret;
max77843->i2c_chg = i2c_new_dummy_device(max77843->i2c->adapter, I2C_ADDR_CHG);
if (IS_ERR(max77843->i2c_chg)) {
dev_err(&max77843->i2c->dev,
"Cannot allocate I2C device for Charger\n");
return PTR_ERR(max77843->i2c_chg);
}
i2c_set_clientdata(max77843->i2c_chg, max77843);
max77843->regmap_chg = devm_regmap_init_i2c(max77843->i2c_chg,
&max77843_charger_regmap_config);
if (IS_ERR(max77843->regmap_chg)) {
ret = PTR_ERR(max77843->regmap_chg);
goto err_chg_i2c;
}
return 0;
err_chg_i2c:
i2c_unregister_device(max77843->i2c_chg);
return ret;
}
static int max77843_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
struct max77693_dev *max77843;
unsigned int reg_data;
int ret;
max77843 = devm_kzalloc(&i2c->dev, sizeof(*max77843), GFP_KERNEL);
if (!max77843)
return -ENOMEM;
i2c_set_clientdata(i2c, max77843);
max77843->dev = &i2c->dev;
max77843->i2c = i2c;
max77843->irq = i2c->irq;
max77843->type = id->driver_data;
max77843->regmap = devm_regmap_init_i2c(i2c,
&max77843_regmap_config);
if (IS_ERR(max77843->regmap)) {
dev_err(&i2c->dev, "Failed to allocate topsys register map\n");
return PTR_ERR(max77843->regmap);
}
ret = regmap_add_irq_chip(max77843->regmap, max77843->irq,
IRQF_TRIGGER_LOW | IRQF_ONESHOT | IRQF_SHARED,
0, &max77843_irq_chip, &max77843->irq_data_topsys);
if (ret) {
dev_err(&i2c->dev, "Failed to add TOPSYS IRQ chip\n");
return ret;
}
ret = regmap_read(max77843->regmap,
MAX77843_SYS_REG_PMICID, ®_data);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read PMIC ID\n");
goto err_pmic_id;
}
dev_info(&i2c->dev, "device ID: 0x%x\n", reg_data);
ret = max77843_chg_init(max77843);
if (ret) {
dev_err(&i2c->dev, "Failed to init Charger\n");
goto err_pmic_id;
}
ret = regmap_update_bits(max77843->regmap,
MAX77843_SYS_REG_INTSRCMASK,
MAX77843_INTSRC_MASK_MASK,
(unsigned int)~MAX77843_INTSRC_MASK_MASK);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to unmask interrupt source\n");
goto err_pmic_id;
}
ret = mfd_add_devices(max77843->dev, -1, max77843_devs,
ARRAY_SIZE(max77843_devs), NULL, 0, NULL);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to add mfd device\n");
goto err_pmic_id;
}
device_init_wakeup(max77843->dev, true);
return 0;
err_pmic_id:
regmap_del_irq_chip(max77843->irq, max77843->irq_data_topsys);
return ret;
}
static const struct of_device_id max77843_dt_match[] = {
{ .compatible = "maxim,max77843", },
{ },
};
static const struct i2c_device_id max77843_id[] = {
{ "max77843", TYPE_MAX77843, },
{ },
};
static int __maybe_unused max77843_suspend(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct max77693_dev *max77843 = i2c_get_clientdata(i2c);
disable_irq(max77843->irq);
if (device_may_wakeup(dev))
enable_irq_wake(max77843->irq);
return 0;
}
static int __maybe_unused max77843_resume(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct max77693_dev *max77843 = i2c_get_clientdata(i2c);
if (device_may_wakeup(dev))
disable_irq_wake(max77843->irq);
enable_irq(max77843->irq);
return 0;
}
static SIMPLE_DEV_PM_OPS(max77843_pm, max77843_suspend, max77843_resume);
static struct i2c_driver max77843_i2c_driver = {
.driver = {
.name = "max77843",
.pm = &max77843_pm,
.of_match_table = max77843_dt_match,
.suppress_bind_attrs = true,
},
.probe = max77843_probe,
.id_table = max77843_id,
};
static int __init max77843_i2c_init(void)
{
return i2c_add_driver(&max77843_i2c_driver);
}
subsys_initcall(max77843_i2c_init);
| linux-master | drivers/mfd/max77843.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* lm3533-core.c -- LM3533 Core
*
* Copyright (C) 2011-2012 Texas Instruments
*
* Author: Johan Hovold <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/mfd/lm3533.h>
#define LM3533_BOOST_OVP_MASK 0x06
#define LM3533_BOOST_OVP_SHIFT 1
#define LM3533_BOOST_FREQ_MASK 0x01
#define LM3533_BOOST_FREQ_SHIFT 0
#define LM3533_BL_ID_MASK 1
#define LM3533_LED_ID_MASK 3
#define LM3533_BL_ID_MAX 1
#define LM3533_LED_ID_MAX 3
#define LM3533_HVLED_ID_MAX 2
#define LM3533_LVLED_ID_MAX 5
#define LM3533_REG_OUTPUT_CONF1 0x10
#define LM3533_REG_OUTPUT_CONF2 0x11
#define LM3533_REG_BOOST_PWM 0x2c
#define LM3533_REG_MAX 0xb2
static struct mfd_cell lm3533_als_devs[] = {
{
.name = "lm3533-als",
.id = -1,
},
};
static struct mfd_cell lm3533_bl_devs[] = {
{
.name = "lm3533-backlight",
.id = 0,
},
{
.name = "lm3533-backlight",
.id = 1,
},
};
static struct mfd_cell lm3533_led_devs[] = {
{
.name = "lm3533-leds",
.id = 0,
},
{
.name = "lm3533-leds",
.id = 1,
},
{
.name = "lm3533-leds",
.id = 2,
},
{
.name = "lm3533-leds",
.id = 3,
},
};
int lm3533_read(struct lm3533 *lm3533, u8 reg, u8 *val)
{
int tmp;
int ret;
ret = regmap_read(lm3533->regmap, reg, &tmp);
if (ret < 0) {
dev_err(lm3533->dev, "failed to read register %02x: %d\n",
reg, ret);
return ret;
}
*val = tmp;
dev_dbg(lm3533->dev, "read [%02x]: %02x\n", reg, *val);
return ret;
}
EXPORT_SYMBOL_GPL(lm3533_read);
int lm3533_write(struct lm3533 *lm3533, u8 reg, u8 val)
{
int ret;
dev_dbg(lm3533->dev, "write [%02x]: %02x\n", reg, val);
ret = regmap_write(lm3533->regmap, reg, val);
if (ret < 0) {
dev_err(lm3533->dev, "failed to write register %02x: %d\n",
reg, ret);
}
return ret;
}
EXPORT_SYMBOL_GPL(lm3533_write);
int lm3533_update(struct lm3533 *lm3533, u8 reg, u8 val, u8 mask)
{
int ret;
dev_dbg(lm3533->dev, "update [%02x]: %02x/%02x\n", reg, val, mask);
ret = regmap_update_bits(lm3533->regmap, reg, mask, val);
if (ret < 0) {
dev_err(lm3533->dev, "failed to update register %02x: %d\n",
reg, ret);
}
return ret;
}
EXPORT_SYMBOL_GPL(lm3533_update);
static int lm3533_set_boost_freq(struct lm3533 *lm3533,
enum lm3533_boost_freq freq)
{
int ret;
ret = lm3533_update(lm3533, LM3533_REG_BOOST_PWM,
freq << LM3533_BOOST_FREQ_SHIFT,
LM3533_BOOST_FREQ_MASK);
if (ret)
dev_err(lm3533->dev, "failed to set boost frequency\n");
return ret;
}
static int lm3533_set_boost_ovp(struct lm3533 *lm3533,
enum lm3533_boost_ovp ovp)
{
int ret;
ret = lm3533_update(lm3533, LM3533_REG_BOOST_PWM,
ovp << LM3533_BOOST_OVP_SHIFT,
LM3533_BOOST_OVP_MASK);
if (ret)
dev_err(lm3533->dev, "failed to set boost ovp\n");
return ret;
}
/*
* HVLED output config -- output hvled controlled by backlight bl
*/
static int lm3533_set_hvled_config(struct lm3533 *lm3533, u8 hvled, u8 bl)
{
u8 val;
u8 mask;
int shift;
int ret;
if (hvled == 0 || hvled > LM3533_HVLED_ID_MAX)
return -EINVAL;
if (bl > LM3533_BL_ID_MAX)
return -EINVAL;
shift = hvled - 1;
mask = LM3533_BL_ID_MASK << shift;
val = bl << shift;
ret = lm3533_update(lm3533, LM3533_REG_OUTPUT_CONF1, val, mask);
if (ret)
dev_err(lm3533->dev, "failed to set hvled config\n");
return ret;
}
/*
* LVLED output config -- output lvled controlled by LED led
*/
static int lm3533_set_lvled_config(struct lm3533 *lm3533, u8 lvled, u8 led)
{
u8 reg;
u8 val;
u8 mask;
int shift;
int ret;
if (lvled == 0 || lvled > LM3533_LVLED_ID_MAX)
return -EINVAL;
if (led > LM3533_LED_ID_MAX)
return -EINVAL;
if (lvled < 4) {
reg = LM3533_REG_OUTPUT_CONF1;
shift = 2 * lvled;
} else {
reg = LM3533_REG_OUTPUT_CONF2;
shift = 2 * (lvled - 4);
}
mask = LM3533_LED_ID_MASK << shift;
val = led << shift;
ret = lm3533_update(lm3533, reg, val, mask);
if (ret)
dev_err(lm3533->dev, "failed to set lvled config\n");
return ret;
}
static void lm3533_enable(struct lm3533 *lm3533)
{
if (gpio_is_valid(lm3533->gpio_hwen))
gpio_set_value(lm3533->gpio_hwen, 1);
}
static void lm3533_disable(struct lm3533 *lm3533)
{
if (gpio_is_valid(lm3533->gpio_hwen))
gpio_set_value(lm3533->gpio_hwen, 0);
}
enum lm3533_attribute_type {
LM3533_ATTR_TYPE_BACKLIGHT,
LM3533_ATTR_TYPE_LED,
};
struct lm3533_device_attribute {
struct device_attribute dev_attr;
enum lm3533_attribute_type type;
union {
struct {
u8 id;
} output;
} u;
};
#define to_lm3533_dev_attr(_attr) \
container_of(_attr, struct lm3533_device_attribute, dev_attr)
static ssize_t show_output(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct lm3533 *lm3533 = dev_get_drvdata(dev);
struct lm3533_device_attribute *lattr = to_lm3533_dev_attr(attr);
int id = lattr->u.output.id;
u8 reg;
u8 val;
u8 mask;
int shift;
int ret;
if (lattr->type == LM3533_ATTR_TYPE_BACKLIGHT) {
reg = LM3533_REG_OUTPUT_CONF1;
shift = id - 1;
mask = LM3533_BL_ID_MASK << shift;
} else {
if (id < 4) {
reg = LM3533_REG_OUTPUT_CONF1;
shift = 2 * id;
} else {
reg = LM3533_REG_OUTPUT_CONF2;
shift = 2 * (id - 4);
}
mask = LM3533_LED_ID_MASK << shift;
}
ret = lm3533_read(lm3533, reg, &val);
if (ret)
return ret;
val = (val & mask) >> shift;
return sysfs_emit(buf, "%u\n", val);
}
static ssize_t store_output(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct lm3533 *lm3533 = dev_get_drvdata(dev);
struct lm3533_device_attribute *lattr = to_lm3533_dev_attr(attr);
int id = lattr->u.output.id;
u8 val;
int ret;
if (kstrtou8(buf, 0, &val))
return -EINVAL;
if (lattr->type == LM3533_ATTR_TYPE_BACKLIGHT)
ret = lm3533_set_hvled_config(lm3533, id, val);
else
ret = lm3533_set_lvled_config(lm3533, id, val);
if (ret)
return ret;
return len;
}
#define LM3533_OUTPUT_ATTR(_name, _mode, _show, _store, _type, _id) \
struct lm3533_device_attribute lm3533_dev_attr_##_name = \
{ .dev_attr = __ATTR(_name, _mode, _show, _store), \
.type = _type, \
.u.output = { .id = _id }, }
#define LM3533_OUTPUT_ATTR_RW(_name, _type, _id) \
LM3533_OUTPUT_ATTR(output_##_name, S_IRUGO | S_IWUSR, \
show_output, store_output, _type, _id)
#define LM3533_OUTPUT_HVLED_ATTR_RW(_nr) \
LM3533_OUTPUT_ATTR_RW(hvled##_nr, LM3533_ATTR_TYPE_BACKLIGHT, _nr)
#define LM3533_OUTPUT_LVLED_ATTR_RW(_nr) \
LM3533_OUTPUT_ATTR_RW(lvled##_nr, LM3533_ATTR_TYPE_LED, _nr)
/*
* Output config:
*
* output_hvled<nr> 0-1
* output_lvled<nr> 0-3
*/
static LM3533_OUTPUT_HVLED_ATTR_RW(1);
static LM3533_OUTPUT_HVLED_ATTR_RW(2);
static LM3533_OUTPUT_LVLED_ATTR_RW(1);
static LM3533_OUTPUT_LVLED_ATTR_RW(2);
static LM3533_OUTPUT_LVLED_ATTR_RW(3);
static LM3533_OUTPUT_LVLED_ATTR_RW(4);
static LM3533_OUTPUT_LVLED_ATTR_RW(5);
static struct attribute *lm3533_attributes[] = {
&lm3533_dev_attr_output_hvled1.dev_attr.attr,
&lm3533_dev_attr_output_hvled2.dev_attr.attr,
&lm3533_dev_attr_output_lvled1.dev_attr.attr,
&lm3533_dev_attr_output_lvled2.dev_attr.attr,
&lm3533_dev_attr_output_lvled3.dev_attr.attr,
&lm3533_dev_attr_output_lvled4.dev_attr.attr,
&lm3533_dev_attr_output_lvled5.dev_attr.attr,
NULL,
};
#define to_dev_attr(_attr) \
container_of(_attr, struct device_attribute, attr)
static umode_t lm3533_attr_is_visible(struct kobject *kobj,
struct attribute *attr, int n)
{
struct device *dev = kobj_to_dev(kobj);
struct lm3533 *lm3533 = dev_get_drvdata(dev);
struct device_attribute *dattr = to_dev_attr(attr);
struct lm3533_device_attribute *lattr = to_lm3533_dev_attr(dattr);
enum lm3533_attribute_type type = lattr->type;
umode_t mode = attr->mode;
if (!lm3533->have_backlights && type == LM3533_ATTR_TYPE_BACKLIGHT)
mode = 0;
else if (!lm3533->have_leds && type == LM3533_ATTR_TYPE_LED)
mode = 0;
return mode;
};
static struct attribute_group lm3533_attribute_group = {
.is_visible = lm3533_attr_is_visible,
.attrs = lm3533_attributes
};
static int lm3533_device_als_init(struct lm3533 *lm3533)
{
struct lm3533_platform_data *pdata = dev_get_platdata(lm3533->dev);
int ret;
if (!pdata->als)
return 0;
lm3533_als_devs[0].platform_data = pdata->als;
lm3533_als_devs[0].pdata_size = sizeof(*pdata->als);
ret = mfd_add_devices(lm3533->dev, 0, lm3533_als_devs, 1, NULL,
0, NULL);
if (ret) {
dev_err(lm3533->dev, "failed to add ALS device\n");
return ret;
}
lm3533->have_als = 1;
return 0;
}
static int lm3533_device_bl_init(struct lm3533 *lm3533)
{
struct lm3533_platform_data *pdata = dev_get_platdata(lm3533->dev);
int i;
int ret;
if (!pdata->backlights || pdata->num_backlights == 0)
return 0;
if (pdata->num_backlights > ARRAY_SIZE(lm3533_bl_devs))
pdata->num_backlights = ARRAY_SIZE(lm3533_bl_devs);
for (i = 0; i < pdata->num_backlights; ++i) {
lm3533_bl_devs[i].platform_data = &pdata->backlights[i];
lm3533_bl_devs[i].pdata_size = sizeof(pdata->backlights[i]);
}
ret = mfd_add_devices(lm3533->dev, 0, lm3533_bl_devs,
pdata->num_backlights, NULL, 0, NULL);
if (ret) {
dev_err(lm3533->dev, "failed to add backlight devices\n");
return ret;
}
lm3533->have_backlights = 1;
return 0;
}
static int lm3533_device_led_init(struct lm3533 *lm3533)
{
struct lm3533_platform_data *pdata = dev_get_platdata(lm3533->dev);
int i;
int ret;
if (!pdata->leds || pdata->num_leds == 0)
return 0;
if (pdata->num_leds > ARRAY_SIZE(lm3533_led_devs))
pdata->num_leds = ARRAY_SIZE(lm3533_led_devs);
for (i = 0; i < pdata->num_leds; ++i) {
lm3533_led_devs[i].platform_data = &pdata->leds[i];
lm3533_led_devs[i].pdata_size = sizeof(pdata->leds[i]);
}
ret = mfd_add_devices(lm3533->dev, 0, lm3533_led_devs,
pdata->num_leds, NULL, 0, NULL);
if (ret) {
dev_err(lm3533->dev, "failed to add LED devices\n");
return ret;
}
lm3533->have_leds = 1;
return 0;
}
static int lm3533_device_setup(struct lm3533 *lm3533,
struct lm3533_platform_data *pdata)
{
int ret;
ret = lm3533_set_boost_freq(lm3533, pdata->boost_freq);
if (ret)
return ret;
return lm3533_set_boost_ovp(lm3533, pdata->boost_ovp);
}
static int lm3533_device_init(struct lm3533 *lm3533)
{
struct lm3533_platform_data *pdata = dev_get_platdata(lm3533->dev);
int ret;
dev_dbg(lm3533->dev, "%s\n", __func__);
if (!pdata) {
dev_err(lm3533->dev, "no platform data\n");
return -EINVAL;
}
lm3533->gpio_hwen = pdata->gpio_hwen;
if (gpio_is_valid(lm3533->gpio_hwen)) {
ret = devm_gpio_request_one(lm3533->dev, lm3533->gpio_hwen,
GPIOF_OUT_INIT_LOW, "lm3533-hwen");
if (ret < 0) {
dev_err(lm3533->dev,
"failed to request HWEN GPIO %d\n",
lm3533->gpio_hwen);
return ret;
}
}
lm3533_enable(lm3533);
ret = lm3533_device_setup(lm3533, pdata);
if (ret)
goto err_disable;
lm3533_device_als_init(lm3533);
lm3533_device_bl_init(lm3533);
lm3533_device_led_init(lm3533);
ret = sysfs_create_group(&lm3533->dev->kobj, &lm3533_attribute_group);
if (ret < 0) {
dev_err(lm3533->dev, "failed to create sysfs attributes\n");
goto err_unregister;
}
return 0;
err_unregister:
mfd_remove_devices(lm3533->dev);
err_disable:
lm3533_disable(lm3533);
return ret;
}
static void lm3533_device_exit(struct lm3533 *lm3533)
{
dev_dbg(lm3533->dev, "%s\n", __func__);
sysfs_remove_group(&lm3533->dev->kobj, &lm3533_attribute_group);
mfd_remove_devices(lm3533->dev);
lm3533_disable(lm3533);
}
static bool lm3533_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x10 ... 0x2c:
case 0x30 ... 0x38:
case 0x40 ... 0x45:
case 0x50 ... 0x57:
case 0x60 ... 0x6e:
case 0x70 ... 0x75:
case 0x80 ... 0x85:
case 0x90 ... 0x95:
case 0xa0 ... 0xa5:
case 0xb0 ... 0xb2:
return true;
default:
return false;
}
}
static bool lm3533_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x34 ... 0x36: /* zone */
case 0x37 ... 0x38: /* adc */
case 0xb0 ... 0xb1: /* fault */
return true;
default:
return false;
}
}
static bool lm3533_precious_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x34: /* zone */
return true;
default:
return false;
}
}
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = LM3533_REG_MAX,
.readable_reg = lm3533_readable_register,
.volatile_reg = lm3533_volatile_register,
.precious_reg = lm3533_precious_register,
};
static int lm3533_i2c_probe(struct i2c_client *i2c)
{
struct lm3533 *lm3533;
dev_dbg(&i2c->dev, "%s\n", __func__);
lm3533 = devm_kzalloc(&i2c->dev, sizeof(*lm3533), GFP_KERNEL);
if (!lm3533)
return -ENOMEM;
i2c_set_clientdata(i2c, lm3533);
lm3533->regmap = devm_regmap_init_i2c(i2c, ®map_config);
if (IS_ERR(lm3533->regmap))
return PTR_ERR(lm3533->regmap);
lm3533->dev = &i2c->dev;
lm3533->irq = i2c->irq;
return lm3533_device_init(lm3533);
}
static void lm3533_i2c_remove(struct i2c_client *i2c)
{
struct lm3533 *lm3533 = i2c_get_clientdata(i2c);
dev_dbg(&i2c->dev, "%s\n", __func__);
lm3533_device_exit(lm3533);
}
static const struct i2c_device_id lm3533_i2c_ids[] = {
{ "lm3533", 0 },
{ },
};
MODULE_DEVICE_TABLE(i2c, lm3533_i2c_ids);
static struct i2c_driver lm3533_i2c_driver = {
.driver = {
.name = "lm3533",
},
.id_table = lm3533_i2c_ids,
.probe = lm3533_i2c_probe,
.remove = lm3533_i2c_remove,
};
static int __init lm3533_i2c_init(void)
{
return i2c_add_driver(&lm3533_i2c_driver);
}
subsys_initcall(lm3533_i2c_init);
static void __exit lm3533_i2c_exit(void)
{
i2c_del_driver(&lm3533_i2c_driver);
}
module_exit(lm3533_i2c_exit);
MODULE_AUTHOR("Johan Hovold <[email protected]>");
MODULE_DESCRIPTION("LM3533 Core");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/lm3533-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Srinidhi Kasagar <[email protected]>
* Author: Rabin Vincent <[email protected]>
* Author: Mattias Wallin <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/abx500.h>
#include <linux/mfd/abx500/ab8500.h>
#include <linux/mfd/dbx500-prcmu.h>
#include <linux/of.h>
/*
* Interrupt register offsets
* Bank : 0x0E
*/
#define AB8500_IT_SOURCE1_REG 0x00
#define AB8500_IT_SOURCE2_REG 0x01
#define AB8500_IT_SOURCE3_REG 0x02
#define AB8500_IT_SOURCE4_REG 0x03
#define AB8500_IT_SOURCE5_REG 0x04
#define AB8500_IT_SOURCE6_REG 0x05
#define AB8500_IT_SOURCE7_REG 0x06
#define AB8500_IT_SOURCE8_REG 0x07
#define AB9540_IT_SOURCE13_REG 0x0C
#define AB8500_IT_SOURCE19_REG 0x12
#define AB8500_IT_SOURCE20_REG 0x13
#define AB8500_IT_SOURCE21_REG 0x14
#define AB8500_IT_SOURCE22_REG 0x15
#define AB8500_IT_SOURCE23_REG 0x16
#define AB8500_IT_SOURCE24_REG 0x17
/*
* latch registers
*/
#define AB8500_IT_LATCH1_REG 0x20
#define AB8500_IT_LATCH2_REG 0x21
#define AB8500_IT_LATCH3_REG 0x22
#define AB8500_IT_LATCH4_REG 0x23
#define AB8500_IT_LATCH5_REG 0x24
#define AB8500_IT_LATCH6_REG 0x25
#define AB8500_IT_LATCH7_REG 0x26
#define AB8500_IT_LATCH8_REG 0x27
#define AB8500_IT_LATCH9_REG 0x28
#define AB8500_IT_LATCH10_REG 0x29
#define AB8500_IT_LATCH12_REG 0x2B
#define AB9540_IT_LATCH13_REG 0x2C
#define AB8500_IT_LATCH19_REG 0x32
#define AB8500_IT_LATCH20_REG 0x33
#define AB8500_IT_LATCH21_REG 0x34
#define AB8500_IT_LATCH22_REG 0x35
#define AB8500_IT_LATCH23_REG 0x36
#define AB8500_IT_LATCH24_REG 0x37
/*
* mask registers
*/
#define AB8500_IT_MASK1_REG 0x40
#define AB8500_IT_MASK2_REG 0x41
#define AB8500_IT_MASK3_REG 0x42
#define AB8500_IT_MASK4_REG 0x43
#define AB8500_IT_MASK5_REG 0x44
#define AB8500_IT_MASK6_REG 0x45
#define AB8500_IT_MASK7_REG 0x46
#define AB8500_IT_MASK8_REG 0x47
#define AB8500_IT_MASK9_REG 0x48
#define AB8500_IT_MASK10_REG 0x49
#define AB8500_IT_MASK11_REG 0x4A
#define AB8500_IT_MASK12_REG 0x4B
#define AB8500_IT_MASK13_REG 0x4C
#define AB8500_IT_MASK14_REG 0x4D
#define AB8500_IT_MASK15_REG 0x4E
#define AB8500_IT_MASK16_REG 0x4F
#define AB8500_IT_MASK17_REG 0x50
#define AB8500_IT_MASK18_REG 0x51
#define AB8500_IT_MASK19_REG 0x52
#define AB8500_IT_MASK20_REG 0x53
#define AB8500_IT_MASK21_REG 0x54
#define AB8500_IT_MASK22_REG 0x55
#define AB8500_IT_MASK23_REG 0x56
#define AB8500_IT_MASK24_REG 0x57
#define AB8500_IT_MASK25_REG 0x58
/*
* latch hierarchy registers
*/
#define AB8500_IT_LATCHHIER1_REG 0x60
#define AB8500_IT_LATCHHIER2_REG 0x61
#define AB8500_IT_LATCHHIER3_REG 0x62
#define AB8540_IT_LATCHHIER4_REG 0x63
#define AB8500_IT_LATCHHIER_NUM 3
#define AB8540_IT_LATCHHIER_NUM 4
#define AB8500_REV_REG 0x80
#define AB8500_IC_NAME_REG 0x82
#define AB8500_SWITCH_OFF_STATUS 0x00
#define AB8500_TURN_ON_STATUS 0x00
#define AB8505_TURN_ON_STATUS_2 0x04
#define AB8500_CH_USBCH_STAT1_REG 0x02
#define VBUS_DET_DBNC100 0x02
#define VBUS_DET_DBNC1 0x01
static DEFINE_SPINLOCK(on_stat_lock);
static u8 turn_on_stat_mask = 0xFF;
static u8 turn_on_stat_set;
#define AB9540_MODEM_CTRL2_REG 0x23
#define AB9540_MODEM_CTRL2_SWDBBRSTN_BIT BIT(2)
/*
* Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
* numbers are indexed into this array with (num / 8). The interupts are
* defined in linux/mfd/ab8500.h
*
* This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at
* offset 0.
*/
/* AB8500 support */
static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = {
0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21,
};
/* AB9540 / AB8505 support */
static const int ab9540_irq_regoffset[AB9540_NUM_IRQ_REGS] = {
0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21, 12, 13, 24, 5, 22, 23
};
/* AB8540 support */
static const int ab8540_irq_regoffset[AB8540_NUM_IRQ_REGS] = {
0, 1, 2, 3, 4, -1, -1, -1, -1, 11, 18, 19, 20, 21, 12, 13, 24, 5, 22,
23, 25, 26, 27, 28, 29, 30, 31,
};
static const char ab8500_version_str[][7] = {
[AB8500_VERSION_AB8500] = "AB8500",
[AB8500_VERSION_AB8505] = "AB8505",
[AB8500_VERSION_AB9540] = "AB9540",
[AB8500_VERSION_AB8540] = "AB8540",
};
static int ab8500_prcmu_write(struct ab8500 *ab8500, u16 addr, u8 data)
{
int ret;
ret = prcmu_abb_write((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
if (ret < 0)
dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
return ret;
}
static int ab8500_prcmu_write_masked(struct ab8500 *ab8500, u16 addr, u8 mask,
u8 data)
{
int ret;
ret = prcmu_abb_write_masked((u8)(addr >> 8), (u8)(addr & 0xFF), &data,
&mask, 1);
if (ret < 0)
dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
return ret;
}
static int ab8500_prcmu_read(struct ab8500 *ab8500, u16 addr)
{
int ret;
u8 data;
ret = prcmu_abb_read((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
if (ret < 0) {
dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
return ret;
}
return (int)data;
}
static int ab8500_get_chip_id(struct device *dev)
{
struct ab8500 *ab8500;
if (!dev)
return -EINVAL;
ab8500 = dev_get_drvdata(dev->parent);
return ab8500 ? (int)ab8500->chip_id : -EINVAL;
}
static int set_register_interruptible(struct ab8500 *ab8500, u8 bank,
u8 reg, u8 data)
{
int ret;
/*
* Put the u8 bank and u8 register together into a an u16.
* The bank on higher 8 bits and register in lower 8 bits.
*/
u16 addr = ((u16)bank) << 8 | reg;
dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data);
mutex_lock(&ab8500->lock);
ret = ab8500->write(ab8500, addr, data);
if (ret < 0)
dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
addr, ret);
mutex_unlock(&ab8500->lock);
return ret;
}
static int ab8500_set_register(struct device *dev, u8 bank,
u8 reg, u8 value)
{
int ret;
struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
atomic_inc(&ab8500->transfer_ongoing);
ret = set_register_interruptible(ab8500, bank, reg, value);
atomic_dec(&ab8500->transfer_ongoing);
return ret;
}
static int get_register_interruptible(struct ab8500 *ab8500, u8 bank,
u8 reg, u8 *value)
{
int ret;
u16 addr = ((u16)bank) << 8 | reg;
mutex_lock(&ab8500->lock);
ret = ab8500->read(ab8500, addr);
if (ret < 0)
dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
addr, ret);
else
*value = ret;
mutex_unlock(&ab8500->lock);
dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);
return (ret < 0) ? ret : 0;
}
static int ab8500_get_register(struct device *dev, u8 bank,
u8 reg, u8 *value)
{
int ret;
struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
atomic_inc(&ab8500->transfer_ongoing);
ret = get_register_interruptible(ab8500, bank, reg, value);
atomic_dec(&ab8500->transfer_ongoing);
return ret;
}
static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank,
u8 reg, u8 bitmask, u8 bitvalues)
{
int ret;
u16 addr = ((u16)bank) << 8 | reg;
mutex_lock(&ab8500->lock);
if (ab8500->write_masked == NULL) {
u8 data;
ret = ab8500->read(ab8500, addr);
if (ret < 0) {
dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
addr, ret);
goto out;
}
data = (u8)ret;
data = (~bitmask & data) | (bitmask & bitvalues);
ret = ab8500->write(ab8500, addr, data);
if (ret < 0)
dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
addr, ret);
dev_vdbg(ab8500->dev, "mask: addr %#x => data %#x\n", addr,
data);
goto out;
}
ret = ab8500->write_masked(ab8500, addr, bitmask, bitvalues);
if (ret < 0)
dev_err(ab8500->dev, "failed to modify reg %#x: %d\n", addr,
ret);
out:
mutex_unlock(&ab8500->lock);
return ret;
}
static int ab8500_mask_and_set_register(struct device *dev,
u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
{
int ret;
struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
atomic_inc(&ab8500->transfer_ongoing);
ret = mask_and_set_register_interruptible(ab8500, bank, reg,
bitmask, bitvalues);
atomic_dec(&ab8500->transfer_ongoing);
return ret;
}
static struct abx500_ops ab8500_ops = {
.get_chip_id = ab8500_get_chip_id,
.get_register = ab8500_get_register,
.set_register = ab8500_set_register,
.get_register_page = NULL,
.set_register_page = NULL,
.mask_and_set_register = ab8500_mask_and_set_register,
.event_registers_startup_state_get = NULL,
.startup_irq_enabled = NULL,
.dump_all_banks = ab8500_dump_all_banks,
};
static void ab8500_irq_lock(struct irq_data *data)
{
struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
mutex_lock(&ab8500->irq_lock);
atomic_inc(&ab8500->transfer_ongoing);
}
static void ab8500_irq_sync_unlock(struct irq_data *data)
{
struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
int i;
for (i = 0; i < ab8500->mask_size; i++) {
u8 old = ab8500->oldmask[i];
u8 new = ab8500->mask[i];
int reg;
if (new == old)
continue;
/*
* Interrupt register 12 doesn't exist prior to AB8500 version
* 2.0
*/
if (ab8500->irq_reg_offset[i] == 11 &&
is_ab8500_1p1_or_earlier(ab8500))
continue;
if (ab8500->irq_reg_offset[i] < 0)
continue;
ab8500->oldmask[i] = new;
reg = AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i];
set_register_interruptible(ab8500, AB8500_INTERRUPT, reg, new);
}
atomic_dec(&ab8500->transfer_ongoing);
mutex_unlock(&ab8500->irq_lock);
}
static void ab8500_irq_mask(struct irq_data *data)
{
struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
int offset = data->hwirq;
int index = offset / 8;
int mask = 1 << (offset % 8);
ab8500->mask[index] |= mask;
/* The AB8500 GPIOs have two interrupts each (rising & falling). */
if (offset >= AB8500_INT_GPIO6R && offset <= AB8500_INT_GPIO41R)
ab8500->mask[index + 2] |= mask;
if (offset >= AB9540_INT_GPIO50R && offset <= AB9540_INT_GPIO54R)
ab8500->mask[index + 1] |= mask;
if (offset == AB8540_INT_GPIO43R || offset == AB8540_INT_GPIO44R)
/* Here the falling IRQ is one bit lower */
ab8500->mask[index] |= (mask << 1);
}
static void ab8500_irq_unmask(struct irq_data *data)
{
struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
unsigned int type = irqd_get_trigger_type(data);
int offset = data->hwirq;
int index = offset / 8;
int mask = 1 << (offset % 8);
if (type & IRQ_TYPE_EDGE_RISING)
ab8500->mask[index] &= ~mask;
/* The AB8500 GPIOs have two interrupts each (rising & falling). */
if (type & IRQ_TYPE_EDGE_FALLING) {
if (offset >= AB8500_INT_GPIO6R && offset <= AB8500_INT_GPIO41R)
ab8500->mask[index + 2] &= ~mask;
else if (offset >= AB9540_INT_GPIO50R &&
offset <= AB9540_INT_GPIO54R)
ab8500->mask[index + 1] &= ~mask;
else if (offset == AB8540_INT_GPIO43R ||
offset == AB8540_INT_GPIO44R)
/* Here the falling IRQ is one bit lower */
ab8500->mask[index] &= ~(mask << 1);
else
ab8500->mask[index] &= ~mask;
} else {
/* Satisfies the case where type is not set. */
ab8500->mask[index] &= ~mask;
}
}
static int ab8500_irq_set_type(struct irq_data *data, unsigned int type)
{
return 0;
}
static struct irq_chip ab8500_irq_chip = {
.name = "ab8500",
.irq_bus_lock = ab8500_irq_lock,
.irq_bus_sync_unlock = ab8500_irq_sync_unlock,
.irq_mask = ab8500_irq_mask,
.irq_disable = ab8500_irq_mask,
.irq_unmask = ab8500_irq_unmask,
.irq_set_type = ab8500_irq_set_type,
};
static void update_latch_offset(u8 *offset, int i)
{
/* Fix inconsistent ITFromLatch25 bit mapping... */
if (unlikely(*offset == 17))
*offset = 24;
/* Fix inconsistent ab8540 bit mapping... */
if (unlikely(*offset == 16))
*offset = 25;
if ((i == 3) && (*offset >= 24))
*offset += 2;
}
static int ab8500_handle_hierarchical_line(struct ab8500 *ab8500,
int latch_offset, u8 latch_val)
{
int int_bit, line, i;
for (i = 0; i < ab8500->mask_size; i++)
if (ab8500->irq_reg_offset[i] == latch_offset)
break;
if (i >= ab8500->mask_size) {
dev_err(ab8500->dev, "Register offset 0x%2x not declared\n",
latch_offset);
return -ENXIO;
}
/* ignore masked out interrupts */
latch_val &= ~ab8500->mask[i];
while (latch_val) {
int_bit = __ffs(latch_val);
line = (i << 3) + int_bit;
latch_val &= ~(1 << int_bit);
/*
* This handles the falling edge hwirqs from the GPIO
* lines. Route them back to the line registered for the
* rising IRQ, as this is merely a flag for the same IRQ
* in linux terms.
*/
if (line >= AB8500_INT_GPIO6F && line <= AB8500_INT_GPIO41F)
line -= 16;
if (line >= AB9540_INT_GPIO50F && line <= AB9540_INT_GPIO54F)
line -= 8;
if (line == AB8540_INT_GPIO43F || line == AB8540_INT_GPIO44F)
line += 1;
handle_nested_irq(irq_find_mapping(ab8500->domain, line));
}
return 0;
}
static int ab8500_handle_hierarchical_latch(struct ab8500 *ab8500,
int hier_offset, u8 hier_val)
{
int latch_bit, status;
u8 latch_offset, latch_val;
do {
latch_bit = __ffs(hier_val);
latch_offset = (hier_offset << 3) + latch_bit;
update_latch_offset(&latch_offset, hier_offset);
status = get_register_interruptible(ab8500,
AB8500_INTERRUPT,
AB8500_IT_LATCH1_REG + latch_offset,
&latch_val);
if (status < 0 || latch_val == 0)
goto discard;
status = ab8500_handle_hierarchical_line(ab8500,
latch_offset, latch_val);
if (status < 0)
return status;
discard:
hier_val &= ~(1 << latch_bit);
} while (hier_val);
return 0;
}
static irqreturn_t ab8500_hierarchical_irq(int irq, void *dev)
{
struct ab8500 *ab8500 = dev;
u8 i;
dev_vdbg(ab8500->dev, "interrupt\n");
/* Hierarchical interrupt version */
for (i = 0; i < (ab8500->it_latchhier_num); i++) {
int status;
u8 hier_val;
status = get_register_interruptible(ab8500, AB8500_INTERRUPT,
AB8500_IT_LATCHHIER1_REG + i, &hier_val);
if (status < 0 || hier_val == 0)
continue;
status = ab8500_handle_hierarchical_latch(ab8500, i, hier_val);
if (status < 0)
break;
}
return IRQ_HANDLED;
}
static int ab8500_irq_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hwirq)
{
struct ab8500 *ab8500 = d->host_data;
if (!ab8500)
return -EINVAL;
irq_set_chip_data(virq, ab8500);
irq_set_chip_and_handler(virq, &ab8500_irq_chip,
handle_simple_irq);
irq_set_nested_thread(virq, 1);
irq_set_noprobe(virq);
return 0;
}
static const struct irq_domain_ops ab8500_irq_ops = {
.map = ab8500_irq_map,
.xlate = irq_domain_xlate_twocell,
};
static int ab8500_irq_init(struct ab8500 *ab8500, struct device_node *np)
{
int num_irqs;
if (is_ab8540(ab8500))
num_irqs = AB8540_NR_IRQS;
else if (is_ab9540(ab8500))
num_irqs = AB9540_NR_IRQS;
else if (is_ab8505(ab8500))
num_irqs = AB8505_NR_IRQS;
else
num_irqs = AB8500_NR_IRQS;
/* If ->irq_base is zero this will give a linear mapping */
ab8500->domain = irq_domain_add_simple(ab8500->dev->of_node,
num_irqs, 0,
&ab8500_irq_ops, ab8500);
if (!ab8500->domain) {
dev_err(ab8500->dev, "Failed to create irqdomain\n");
return -ENODEV;
}
return 0;
}
int ab8500_suspend(struct ab8500 *ab8500)
{
if (atomic_read(&ab8500->transfer_ongoing))
return -EINVAL;
return 0;
}
static const struct mfd_cell ab8500_bm_devs[] = {
MFD_CELL_OF("ab8500-charger", NULL, NULL, 0, 0,
"stericsson,ab8500-charger"),
MFD_CELL_OF("ab8500-btemp", NULL, NULL, 0, 0,
"stericsson,ab8500-btemp"),
MFD_CELL_OF("ab8500-fg", NULL, NULL, 0, 0,
"stericsson,ab8500-fg"),
MFD_CELL_OF("ab8500-chargalg", NULL, NULL, 0, 0,
"stericsson,ab8500-chargalg"),
};
static const struct mfd_cell ab8500_devs[] = {
MFD_CELL_OF("ab8500-sysctrl",
NULL, NULL, 0, 0, "stericsson,ab8500-sysctrl"),
MFD_CELL_OF("ab8500-ext-regulator",
NULL, NULL, 0, 0, "stericsson,ab8500-ext-regulator"),
MFD_CELL_OF("ab8500-regulator",
NULL, NULL, 0, 0, "stericsson,ab8500-regulator"),
MFD_CELL_OF("ab8500-clk",
NULL, NULL, 0, 0, "stericsson,ab8500-clk"),
MFD_CELL_OF("ab8500-gpadc",
NULL, NULL, 0, 0, "stericsson,ab8500-gpadc"),
MFD_CELL_OF("ab8500-rtc",
NULL, NULL, 0, 0, "stericsson,ab8500-rtc"),
MFD_CELL_OF("ab8500-acc-det",
NULL, NULL, 0, 0, "stericsson,ab8500-acc-det"),
MFD_CELL_OF("ab8500-poweron-key",
NULL, NULL, 0, 0, "stericsson,ab8500-poweron-key"),
MFD_CELL_OF("ab8500-pwm",
NULL, NULL, 0, 1, "stericsson,ab8500-pwm"),
MFD_CELL_OF("ab8500-pwm",
NULL, NULL, 0, 2, "stericsson,ab8500-pwm"),
MFD_CELL_OF("ab8500-pwm",
NULL, NULL, 0, 3, "stericsson,ab8500-pwm"),
MFD_CELL_OF("ab8500-denc",
NULL, NULL, 0, 0, "stericsson,ab8500-denc"),
MFD_CELL_OF("pinctrl-ab8500",
NULL, NULL, 0, 0, "stericsson,ab8500-gpio"),
MFD_CELL_OF("abx500-temp",
NULL, NULL, 0, 0, "stericsson,abx500-temp"),
MFD_CELL_OF("ab8500-usb",
NULL, NULL, 0, 0, "stericsson,ab8500-usb"),
MFD_CELL_OF("ab8500-codec",
NULL, NULL, 0, 0, "stericsson,ab8500-codec"),
};
static const struct mfd_cell ab9540_devs[] = {
{
.name = "ab8500-sysctrl",
},
{
.name = "ab8500-ext-regulator",
},
{
.name = "ab8500-regulator",
},
{
.name = "abx500-clk",
.of_compatible = "stericsson,abx500-clk",
},
{
.name = "ab8500-gpadc",
.of_compatible = "stericsson,ab8500-gpadc",
},
{
.name = "ab8500-rtc",
},
{
.name = "ab8500-acc-det",
},
{
.name = "ab8500-poweron-key",
},
{
.name = "ab8500-pwm",
.id = 1,
},
{
.name = "abx500-temp",
},
{
.name = "pinctrl-ab9540",
.of_compatible = "stericsson,ab9540-gpio",
},
{
.name = "ab9540-usb",
},
{
.name = "ab9540-codec",
},
{
.name = "ab-iddet",
},
};
/* Device list for ab8505 */
static const struct mfd_cell ab8505_devs[] = {
{
.name = "ab8500-sysctrl",
.of_compatible = "stericsson,ab8500-sysctrl",
},
{
.name = "ab8500-regulator",
.of_compatible = "stericsson,ab8505-regulator",
},
{
.name = "abx500-clk",
.of_compatible = "stericsson,ab8500-clk",
},
{
.name = "ab8500-gpadc",
.of_compatible = "stericsson,ab8500-gpadc",
},
{
.name = "ab8500-rtc",
.of_compatible = "stericsson,ab8500-rtc",
},
{
.name = "ab8500-acc-det",
.of_compatible = "stericsson,ab8500-acc-det",
},
{
.name = "ab8500-poweron-key",
.of_compatible = "stericsson,ab8500-poweron-key",
},
{
.name = "ab8500-pwm",
.of_compatible = "stericsson,ab8500-pwm",
.id = 1,
},
{
.name = "pinctrl-ab8505",
.of_compatible = "stericsson,ab8505-gpio",
},
{
.name = "ab8500-usb",
.of_compatible = "stericsson,ab8500-usb",
},
{
.name = "ab8500-codec",
.of_compatible = "stericsson,ab8500-codec",
},
{
.name = "ab-iddet",
},
};
static const struct mfd_cell ab8540_devs[] = {
{
.name = "ab8500-sysctrl",
},
{
.name = "ab8500-ext-regulator",
},
{
.name = "ab8500-regulator",
},
{
.name = "abx500-clk",
.of_compatible = "stericsson,abx500-clk",
},
{
.name = "ab8500-gpadc",
.of_compatible = "stericsson,ab8500-gpadc",
},
{
.name = "ab8500-acc-det",
},
{
.name = "ab8500-poweron-key",
},
{
.name = "ab8500-pwm",
.id = 1,
},
{
.name = "abx500-temp",
},
{
.name = "pinctrl-ab8540",
},
{
.name = "ab8540-usb",
},
{
.name = "ab8540-codec",
},
{
.name = "ab-iddet",
},
};
static const struct mfd_cell ab8540_cut1_devs[] = {
{
.name = "ab8500-rtc",
.of_compatible = "stericsson,ab8500-rtc",
},
};
static const struct mfd_cell ab8540_cut2_devs[] = {
{
.name = "ab8540-rtc",
.of_compatible = "stericsson,ab8540-rtc",
},
};
static ssize_t chip_id_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct ab8500 *ab8500;
ab8500 = dev_get_drvdata(dev);
return sprintf(buf, "%#x\n", ab8500 ? ab8500->chip_id : -EINVAL);
}
/*
* ab8500 has switched off due to (SWITCH_OFF_STATUS):
* 0x01 Swoff bit programming
* 0x02 Thermal protection activation
* 0x04 Vbat lower then BattOk falling threshold
* 0x08 Watchdog expired
* 0x10 Non presence of 32kHz clock
* 0x20 Battery level lower than power on reset threshold
* 0x40 Power on key 1 pressed longer than 10 seconds
* 0x80 DB8500 thermal shutdown
*/
static ssize_t switch_off_status_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int ret;
u8 value;
struct ab8500 *ab8500;
ab8500 = dev_get_drvdata(dev);
ret = get_register_interruptible(ab8500, AB8500_RTC,
AB8500_SWITCH_OFF_STATUS, &value);
if (ret < 0)
return ret;
return sprintf(buf, "%#x\n", value);
}
/* use mask and set to override the register turn_on_stat value */
void ab8500_override_turn_on_stat(u8 mask, u8 set)
{
spin_lock(&on_stat_lock);
turn_on_stat_mask = mask;
turn_on_stat_set = set;
spin_unlock(&on_stat_lock);
}
/*
* ab8500 has turned on due to (TURN_ON_STATUS):
* 0x01 PORnVbat
* 0x02 PonKey1dbF
* 0x04 PonKey2dbF
* 0x08 RTCAlarm
* 0x10 MainChDet
* 0x20 VbusDet
* 0x40 UsbIDDetect
* 0x80 Reserved
*/
static ssize_t turn_on_status_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int ret;
u8 value;
struct ab8500 *ab8500;
ab8500 = dev_get_drvdata(dev);
ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK,
AB8500_TURN_ON_STATUS, &value);
if (ret < 0)
return ret;
/*
* In L9540, turn_on_status register is not updated correctly if
* the device is rebooted with AC/USB charger connected. Due to
* this, the device boots android instead of entering into charge
* only mode. Read the AC/USB status register to detect the charger
* presence and update the turn on status manually.
*/
if (is_ab9540(ab8500)) {
spin_lock(&on_stat_lock);
value = (value & turn_on_stat_mask) | turn_on_stat_set;
spin_unlock(&on_stat_lock);
}
return sprintf(buf, "%#x\n", value);
}
static ssize_t turn_on_status_2_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int ret;
u8 value;
struct ab8500 *ab8500;
ab8500 = dev_get_drvdata(dev);
ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK,
AB8505_TURN_ON_STATUS_2, &value);
if (ret < 0)
return ret;
return sprintf(buf, "%#x\n", (value & 0x1));
}
static ssize_t dbbrstn_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct ab8500 *ab8500;
int ret;
u8 value;
ab8500 = dev_get_drvdata(dev);
ret = get_register_interruptible(ab8500, AB8500_REGU_CTRL2,
AB9540_MODEM_CTRL2_REG, &value);
if (ret < 0)
return ret;
return sprintf(buf, "%d\n",
(value & AB9540_MODEM_CTRL2_SWDBBRSTN_BIT) ? 1 : 0);
}
static ssize_t dbbrstn_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct ab8500 *ab8500;
int ret = count;
int err;
u8 bitvalues;
ab8500 = dev_get_drvdata(dev);
if (count > 0) {
switch (buf[0]) {
case '0':
bitvalues = 0;
break;
case '1':
bitvalues = AB9540_MODEM_CTRL2_SWDBBRSTN_BIT;
break;
default:
goto exit;
}
err = mask_and_set_register_interruptible(ab8500,
AB8500_REGU_CTRL2, AB9540_MODEM_CTRL2_REG,
AB9540_MODEM_CTRL2_SWDBBRSTN_BIT, bitvalues);
if (err)
dev_info(ab8500->dev,
"Failed to set DBBRSTN %c, err %#x\n",
buf[0], err);
}
exit:
return ret;
}
static DEVICE_ATTR_RO(chip_id);
static DEVICE_ATTR_RO(switch_off_status);
static DEVICE_ATTR_RO(turn_on_status);
static DEVICE_ATTR_RO(turn_on_status_2);
static DEVICE_ATTR_RW(dbbrstn);
static struct attribute *ab8500_sysfs_entries[] = {
&dev_attr_chip_id.attr,
&dev_attr_switch_off_status.attr,
&dev_attr_turn_on_status.attr,
NULL,
};
static struct attribute *ab8505_sysfs_entries[] = {
&dev_attr_turn_on_status_2.attr,
NULL,
};
static struct attribute *ab9540_sysfs_entries[] = {
&dev_attr_chip_id.attr,
&dev_attr_switch_off_status.attr,
&dev_attr_turn_on_status.attr,
&dev_attr_dbbrstn.attr,
NULL,
};
static const struct attribute_group ab8500_attr_group = {
.attrs = ab8500_sysfs_entries,
};
static const struct attribute_group ab8505_attr_group = {
.attrs = ab8505_sysfs_entries,
};
static const struct attribute_group ab9540_attr_group = {
.attrs = ab9540_sysfs_entries,
};
static int ab8500_probe(struct platform_device *pdev)
{
static const char * const switch_off_status[] = {
"Swoff bit programming",
"Thermal protection activation",
"Vbat lower then BattOk falling threshold",
"Watchdog expired",
"Non presence of 32kHz clock",
"Battery level lower than power on reset threshold",
"Power on key 1 pressed longer than 10 seconds",
"DB8500 thermal shutdown"};
static const char * const turn_on_status[] = {
"Battery rising (Vbat)",
"Power On Key 1 dbF",
"Power On Key 2 dbF",
"RTC Alarm",
"Main Charger Detect",
"Vbus Detect (USB)",
"USB ID Detect",
"UART Factory Mode Detect"};
const struct platform_device_id *platid = platform_get_device_id(pdev);
enum ab8500_version version = AB8500_VERSION_UNDEFINED;
struct device_node *np = pdev->dev.of_node;
struct ab8500 *ab8500;
int ret;
int i;
int irq;
u8 value;
ab8500 = devm_kzalloc(&pdev->dev, sizeof(*ab8500), GFP_KERNEL);
if (!ab8500)
return -ENOMEM;
ab8500->dev = &pdev->dev;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ab8500->irq = irq;
ab8500->read = ab8500_prcmu_read;
ab8500->write = ab8500_prcmu_write;
ab8500->write_masked = ab8500_prcmu_write_masked;
mutex_init(&ab8500->lock);
mutex_init(&ab8500->irq_lock);
atomic_set(&ab8500->transfer_ongoing, 0);
platform_set_drvdata(pdev, ab8500);
if (platid)
version = platid->driver_data;
if (version != AB8500_VERSION_UNDEFINED)
ab8500->version = version;
else {
ret = get_register_interruptible(ab8500, AB8500_MISC,
AB8500_IC_NAME_REG, &value);
if (ret < 0) {
dev_err(&pdev->dev, "could not probe HW\n");
return ret;
}
ab8500->version = value;
}
ret = get_register_interruptible(ab8500, AB8500_MISC,
AB8500_REV_REG, &value);
if (ret < 0)
return ret;
ab8500->chip_id = value;
dev_info(ab8500->dev, "detected chip, %s rev. %1x.%1x\n",
ab8500_version_str[ab8500->version],
ab8500->chip_id >> 4,
ab8500->chip_id & 0x0F);
/* Configure AB8540 */
if (is_ab8540(ab8500)) {
ab8500->mask_size = AB8540_NUM_IRQ_REGS;
ab8500->irq_reg_offset = ab8540_irq_regoffset;
ab8500->it_latchhier_num = AB8540_IT_LATCHHIER_NUM;
} /* Configure AB8500 or AB9540 IRQ */
else if (is_ab9540(ab8500) || is_ab8505(ab8500)) {
ab8500->mask_size = AB9540_NUM_IRQ_REGS;
ab8500->irq_reg_offset = ab9540_irq_regoffset;
ab8500->it_latchhier_num = AB8500_IT_LATCHHIER_NUM;
} else {
ab8500->mask_size = AB8500_NUM_IRQ_REGS;
ab8500->irq_reg_offset = ab8500_irq_regoffset;
ab8500->it_latchhier_num = AB8500_IT_LATCHHIER_NUM;
}
ab8500->mask = devm_kzalloc(&pdev->dev, ab8500->mask_size,
GFP_KERNEL);
if (!ab8500->mask)
return -ENOMEM;
ab8500->oldmask = devm_kzalloc(&pdev->dev, ab8500->mask_size,
GFP_KERNEL);
if (!ab8500->oldmask)
return -ENOMEM;
/*
* ab8500 has switched off due to (SWITCH_OFF_STATUS):
* 0x01 Swoff bit programming
* 0x02 Thermal protection activation
* 0x04 Vbat lower then BattOk falling threshold
* 0x08 Watchdog expired
* 0x10 Non presence of 32kHz clock
* 0x20 Battery level lower than power on reset threshold
* 0x40 Power on key 1 pressed longer than 10 seconds
* 0x80 DB8500 thermal shutdown
*/
ret = get_register_interruptible(ab8500, AB8500_RTC,
AB8500_SWITCH_OFF_STATUS, &value);
if (ret < 0)
return ret;
dev_info(ab8500->dev, "switch off cause(s) (%#x): ", value);
if (value) {
for (i = 0; i < ARRAY_SIZE(switch_off_status); i++) {
if (value & 1)
pr_cont(" \"%s\"", switch_off_status[i]);
value = value >> 1;
}
pr_cont("\n");
} else {
pr_cont(" None\n");
}
ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK,
AB8500_TURN_ON_STATUS, &value);
if (ret < 0)
return ret;
dev_info(ab8500->dev, "turn on reason(s) (%#x): ", value);
if (value) {
for (i = 0; i < ARRAY_SIZE(turn_on_status); i++) {
if (value & 1)
pr_cont("\"%s\" ", turn_on_status[i]);
value = value >> 1;
}
pr_cont("\n");
} else {
pr_cont("None\n");
}
if (is_ab9540(ab8500)) {
ret = get_register_interruptible(ab8500, AB8500_CHARGER,
AB8500_CH_USBCH_STAT1_REG, &value);
if (ret < 0)
return ret;
if ((value & VBUS_DET_DBNC1) && (value & VBUS_DET_DBNC100))
ab8500_override_turn_on_stat(~AB8500_POW_KEY_1_ON,
AB8500_VBUS_DET);
}
/* Clear and mask all interrupts */
for (i = 0; i < ab8500->mask_size; i++) {
/*
* Interrupt register 12 doesn't exist prior to AB8500 version
* 2.0
*/
if (ab8500->irq_reg_offset[i] == 11 &&
is_ab8500_1p1_or_earlier(ab8500))
continue;
if (ab8500->irq_reg_offset[i] < 0)
continue;
get_register_interruptible(ab8500, AB8500_INTERRUPT,
AB8500_IT_LATCH1_REG + ab8500->irq_reg_offset[i],
&value);
set_register_interruptible(ab8500, AB8500_INTERRUPT,
AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i], 0xff);
}
ret = abx500_register_ops(ab8500->dev, &ab8500_ops);
if (ret)
return ret;
for (i = 0; i < ab8500->mask_size; i++)
ab8500->mask[i] = ab8500->oldmask[i] = 0xff;
ret = ab8500_irq_init(ab8500, np);
if (ret)
return ret;
ret = devm_request_threaded_irq(&pdev->dev, ab8500->irq, NULL,
ab8500_hierarchical_irq,
IRQF_ONESHOT | IRQF_NO_SUSPEND,
"ab8500", ab8500);
if (ret)
return ret;
if (is_ab9540(ab8500))
ret = mfd_add_devices(ab8500->dev, 0, ab9540_devs,
ARRAY_SIZE(ab9540_devs), NULL,
0, ab8500->domain);
else if (is_ab8540(ab8500)) {
ret = mfd_add_devices(ab8500->dev, 0, ab8540_devs,
ARRAY_SIZE(ab8540_devs), NULL,
0, ab8500->domain);
if (ret)
return ret;
if (is_ab8540_1p2_or_earlier(ab8500))
ret = mfd_add_devices(ab8500->dev, 0, ab8540_cut1_devs,
ARRAY_SIZE(ab8540_cut1_devs), NULL,
0, ab8500->domain);
else /* ab8540 >= cut2 */
ret = mfd_add_devices(ab8500->dev, 0, ab8540_cut2_devs,
ARRAY_SIZE(ab8540_cut2_devs), NULL,
0, ab8500->domain);
} else if (is_ab8505(ab8500))
ret = mfd_add_devices(ab8500->dev, 0, ab8505_devs,
ARRAY_SIZE(ab8505_devs), NULL,
0, ab8500->domain);
else
ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
ARRAY_SIZE(ab8500_devs), NULL,
0, ab8500->domain);
if (ret)
return ret;
/* Add battery management devices */
ret = mfd_add_devices(ab8500->dev, 0, ab8500_bm_devs,
ARRAY_SIZE(ab8500_bm_devs), NULL,
0, ab8500->domain);
if (ret)
dev_err(ab8500->dev, "error adding bm devices\n");
if (((is_ab8505(ab8500) || is_ab9540(ab8500)) &&
ab8500->chip_id >= AB8500_CUT2P0) || is_ab8540(ab8500))
ret = sysfs_create_group(&ab8500->dev->kobj,
&ab9540_attr_group);
else
ret = sysfs_create_group(&ab8500->dev->kobj,
&ab8500_attr_group);
if ((is_ab8505(ab8500) || is_ab9540(ab8500)) &&
ab8500->chip_id >= AB8500_CUT2P0)
ret = sysfs_create_group(&ab8500->dev->kobj,
&ab8505_attr_group);
if (ret)
dev_err(ab8500->dev, "error creating sysfs entries\n");
return ret;
}
static const struct platform_device_id ab8500_id[] = {
{ "ab8500-core", AB8500_VERSION_AB8500 },
{ "ab8505-core", AB8500_VERSION_AB8505 },
{ "ab9540-i2c", AB8500_VERSION_AB9540 },
{ "ab8540-i2c", AB8500_VERSION_AB8540 },
{ }
};
static struct platform_driver ab8500_core_driver = {
.driver = {
.name = "ab8500-core",
.suppress_bind_attrs = true,
},
.probe = ab8500_probe,
.id_table = ab8500_id,
};
static int __init ab8500_core_init(void)
{
return platform_driver_register(&ab8500_core_driver);
}
core_initcall(ab8500_core_init);
| linux-master | drivers/mfd/ab8500-core.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for STMicroelectronics Multi-Function eXpander (STMFX) core
*
* Copyright (C) 2019 STMicroelectronics
* Author(s): Amelie Delaunay <[email protected]>.
*/
#include <linux/bitfield.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/mfd/stmfx.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>
static bool stmfx_reg_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case STMFX_REG_SYS_CTRL:
case STMFX_REG_IRQ_SRC_EN:
case STMFX_REG_IRQ_PENDING:
case STMFX_REG_IRQ_GPI_PENDING1:
case STMFX_REG_IRQ_GPI_PENDING2:
case STMFX_REG_IRQ_GPI_PENDING3:
case STMFX_REG_GPIO_STATE1:
case STMFX_REG_GPIO_STATE2:
case STMFX_REG_GPIO_STATE3:
case STMFX_REG_IRQ_GPI_SRC1:
case STMFX_REG_IRQ_GPI_SRC2:
case STMFX_REG_IRQ_GPI_SRC3:
case STMFX_REG_GPO_SET1:
case STMFX_REG_GPO_SET2:
case STMFX_REG_GPO_SET3:
case STMFX_REG_GPO_CLR1:
case STMFX_REG_GPO_CLR2:
case STMFX_REG_GPO_CLR3:
return true;
default:
return false;
}
}
static bool stmfx_reg_writeable(struct device *dev, unsigned int reg)
{
return (reg >= STMFX_REG_SYS_CTRL);
}
static const struct regmap_config stmfx_regmap_config = {
.reg_bits = 8,
.reg_stride = 1,
.val_bits = 8,
.max_register = STMFX_REG_MAX,
.volatile_reg = stmfx_reg_volatile,
.writeable_reg = stmfx_reg_writeable,
.cache_type = REGCACHE_RBTREE,
};
static const struct resource stmfx_pinctrl_resources[] = {
DEFINE_RES_IRQ(STMFX_REG_IRQ_SRC_EN_GPIO),
};
static const struct resource stmfx_idd_resources[] = {
DEFINE_RES_IRQ(STMFX_REG_IRQ_SRC_EN_IDD),
DEFINE_RES_IRQ(STMFX_REG_IRQ_SRC_EN_ERROR),
};
static const struct resource stmfx_ts_resources[] = {
DEFINE_RES_IRQ(STMFX_REG_IRQ_SRC_EN_TS_DET),
DEFINE_RES_IRQ(STMFX_REG_IRQ_SRC_EN_TS_NE),
DEFINE_RES_IRQ(STMFX_REG_IRQ_SRC_EN_TS_TH),
DEFINE_RES_IRQ(STMFX_REG_IRQ_SRC_EN_TS_FULL),
DEFINE_RES_IRQ(STMFX_REG_IRQ_SRC_EN_TS_OVF),
};
static struct mfd_cell stmfx_cells[] = {
{
.of_compatible = "st,stmfx-0300-pinctrl",
.name = "stmfx-pinctrl",
.resources = stmfx_pinctrl_resources,
.num_resources = ARRAY_SIZE(stmfx_pinctrl_resources),
},
{
.of_compatible = "st,stmfx-0300-idd",
.name = "stmfx-idd",
.resources = stmfx_idd_resources,
.num_resources = ARRAY_SIZE(stmfx_idd_resources),
},
{
.of_compatible = "st,stmfx-0300-ts",
.name = "stmfx-ts",
.resources = stmfx_ts_resources,
.num_resources = ARRAY_SIZE(stmfx_ts_resources),
},
};
static u8 stmfx_func_to_mask(u32 func)
{
u8 mask = 0;
if (func & STMFX_FUNC_GPIO)
mask |= STMFX_REG_SYS_CTRL_GPIO_EN;
if ((func & STMFX_FUNC_ALTGPIO_LOW) || (func & STMFX_FUNC_ALTGPIO_HIGH))
mask |= STMFX_REG_SYS_CTRL_ALTGPIO_EN;
if (func & STMFX_FUNC_TS)
mask |= STMFX_REG_SYS_CTRL_TS_EN;
if (func & STMFX_FUNC_IDD)
mask |= STMFX_REG_SYS_CTRL_IDD_EN;
return mask;
}
int stmfx_function_enable(struct stmfx *stmfx, u32 func)
{
u32 sys_ctrl;
u8 mask;
int ret;
ret = regmap_read(stmfx->map, STMFX_REG_SYS_CTRL, &sys_ctrl);
if (ret)
return ret;
/*
* IDD and TS have priority in STMFX FW, so if IDD and TS are enabled,
* ALTGPIO function is disabled by STMFX FW. If IDD or TS is enabled,
* the number of aGPIO available decreases. To avoid GPIO management
* disturbance, abort IDD or TS function enable in this case.
*/
if (((func & STMFX_FUNC_IDD) || (func & STMFX_FUNC_TS)) &&
(sys_ctrl & STMFX_REG_SYS_CTRL_ALTGPIO_EN)) {
dev_err(stmfx->dev, "ALTGPIO function already enabled\n");
return -EBUSY;
}
/* If TS is enabled, aGPIO[3:0] cannot be used */
if ((func & STMFX_FUNC_ALTGPIO_LOW) &&
(sys_ctrl & STMFX_REG_SYS_CTRL_TS_EN)) {
dev_err(stmfx->dev, "TS in use, aGPIO[3:0] unavailable\n");
return -EBUSY;
}
/* If IDD is enabled, aGPIO[7:4] cannot be used */
if ((func & STMFX_FUNC_ALTGPIO_HIGH) &&
(sys_ctrl & STMFX_REG_SYS_CTRL_IDD_EN)) {
dev_err(stmfx->dev, "IDD in use, aGPIO[7:4] unavailable\n");
return -EBUSY;
}
mask = stmfx_func_to_mask(func);
return regmap_update_bits(stmfx->map, STMFX_REG_SYS_CTRL, mask, mask);
}
EXPORT_SYMBOL_GPL(stmfx_function_enable);
int stmfx_function_disable(struct stmfx *stmfx, u32 func)
{
u8 mask = stmfx_func_to_mask(func);
return regmap_update_bits(stmfx->map, STMFX_REG_SYS_CTRL, mask, 0);
}
EXPORT_SYMBOL_GPL(stmfx_function_disable);
static void stmfx_irq_bus_lock(struct irq_data *data)
{
struct stmfx *stmfx = irq_data_get_irq_chip_data(data);
mutex_lock(&stmfx->lock);
}
static void stmfx_irq_bus_sync_unlock(struct irq_data *data)
{
struct stmfx *stmfx = irq_data_get_irq_chip_data(data);
regmap_write(stmfx->map, STMFX_REG_IRQ_SRC_EN, stmfx->irq_src);
mutex_unlock(&stmfx->lock);
}
static void stmfx_irq_mask(struct irq_data *data)
{
struct stmfx *stmfx = irq_data_get_irq_chip_data(data);
stmfx->irq_src &= ~BIT(data->hwirq % 8);
}
static void stmfx_irq_unmask(struct irq_data *data)
{
struct stmfx *stmfx = irq_data_get_irq_chip_data(data);
stmfx->irq_src |= BIT(data->hwirq % 8);
}
static struct irq_chip stmfx_irq_chip = {
.name = "stmfx-core",
.irq_bus_lock = stmfx_irq_bus_lock,
.irq_bus_sync_unlock = stmfx_irq_bus_sync_unlock,
.irq_mask = stmfx_irq_mask,
.irq_unmask = stmfx_irq_unmask,
};
static irqreturn_t stmfx_irq_handler(int irq, void *data)
{
struct stmfx *stmfx = data;
unsigned long bits;
u32 pending, ack;
int n, ret;
ret = regmap_read(stmfx->map, STMFX_REG_IRQ_PENDING, &pending);
if (ret)
return IRQ_NONE;
/*
* There is no ACK for GPIO, MFX_REG_IRQ_PENDING_GPIO is a logical OR
* of MFX_REG_IRQ_GPI _PENDING1/_PENDING2/_PENDING3
*/
ack = pending & ~BIT(STMFX_REG_IRQ_SRC_EN_GPIO);
if (ack) {
ret = regmap_write(stmfx->map, STMFX_REG_IRQ_ACK, ack);
if (ret)
return IRQ_NONE;
}
bits = pending;
for_each_set_bit(n, &bits, STMFX_REG_IRQ_SRC_MAX)
handle_nested_irq(irq_find_mapping(stmfx->irq_domain, n));
return IRQ_HANDLED;
}
static int stmfx_irq_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hwirq)
{
irq_set_chip_data(virq, d->host_data);
irq_set_chip_and_handler(virq, &stmfx_irq_chip, handle_simple_irq);
irq_set_nested_thread(virq, 1);
irq_set_noprobe(virq);
return 0;
}
static void stmfx_irq_unmap(struct irq_domain *d, unsigned int virq)
{
irq_set_chip_and_handler(virq, NULL, NULL);
irq_set_chip_data(virq, NULL);
}
static const struct irq_domain_ops stmfx_irq_ops = {
.map = stmfx_irq_map,
.unmap = stmfx_irq_unmap,
};
static void stmfx_irq_exit(struct i2c_client *client)
{
struct stmfx *stmfx = i2c_get_clientdata(client);
int hwirq;
for (hwirq = 0; hwirq < STMFX_REG_IRQ_SRC_MAX; hwirq++)
irq_dispose_mapping(irq_find_mapping(stmfx->irq_domain, hwirq));
irq_domain_remove(stmfx->irq_domain);
}
static int stmfx_irq_init(struct i2c_client *client)
{
struct stmfx *stmfx = i2c_get_clientdata(client);
u32 irqoutpin = 0, irqtrigger;
int ret;
stmfx->irq_domain = irq_domain_add_simple(stmfx->dev->of_node,
STMFX_REG_IRQ_SRC_MAX, 0,
&stmfx_irq_ops, stmfx);
if (!stmfx->irq_domain) {
dev_err(stmfx->dev, "Failed to create IRQ domain\n");
return -EINVAL;
}
if (!of_property_read_bool(stmfx->dev->of_node, "drive-open-drain"))
irqoutpin |= STMFX_REG_IRQ_OUT_PIN_TYPE;
irqtrigger = irq_get_trigger_type(client->irq);
if ((irqtrigger & IRQ_TYPE_EDGE_RISING) ||
(irqtrigger & IRQ_TYPE_LEVEL_HIGH))
irqoutpin |= STMFX_REG_IRQ_OUT_PIN_POL;
ret = regmap_write(stmfx->map, STMFX_REG_IRQ_OUT_PIN, irqoutpin);
if (ret)
goto irq_exit;
ret = devm_request_threaded_irq(stmfx->dev, client->irq,
NULL, stmfx_irq_handler,
irqtrigger | IRQF_ONESHOT,
"stmfx", stmfx);
if (ret)
goto irq_exit;
stmfx->irq = client->irq;
return 0;
irq_exit:
stmfx_irq_exit(client);
return ret;
}
static int stmfx_chip_reset(struct stmfx *stmfx)
{
int ret;
ret = regmap_write(stmfx->map, STMFX_REG_SYS_CTRL,
STMFX_REG_SYS_CTRL_SWRST);
if (ret)
return ret;
msleep(STMFX_BOOT_TIME_MS);
return ret;
}
static int stmfx_chip_init(struct i2c_client *client)
{
struct stmfx *stmfx = i2c_get_clientdata(client);
u32 id;
u8 version[2];
int ret;
stmfx->vdd = devm_regulator_get_optional(&client->dev, "vdd");
ret = PTR_ERR_OR_ZERO(stmfx->vdd);
if (ret) {
stmfx->vdd = NULL;
if (ret != -ENODEV)
return dev_err_probe(&client->dev, ret, "Failed to get VDD regulator\n");
}
if (stmfx->vdd) {
ret = regulator_enable(stmfx->vdd);
if (ret) {
dev_err(&client->dev, "VDD enable failed: %d\n", ret);
return ret;
}
}
ret = regmap_read(stmfx->map, STMFX_REG_CHIP_ID, &id);
if (ret) {
dev_err(&client->dev, "Error reading chip ID: %d\n", ret);
goto err;
}
/*
* Check that ID is the complement of the I2C address:
* STMFX I2C address follows the 7-bit format (MSB), that's why
* client->addr is shifted.
*
* STMFX_I2C_ADDR| STMFX | Linux
* input pin | I2C device address | I2C device address
*---------------------------------------------------------
* 0 | b: 1000 010x h:0x84 | 0x42
* 1 | b: 1000 011x h:0x86 | 0x43
*/
if (FIELD_GET(STMFX_REG_CHIP_ID_MASK, ~id) != (client->addr << 1)) {
dev_err(&client->dev, "Unknown chip ID: %#x\n", id);
ret = -EINVAL;
goto err;
}
ret = regmap_bulk_read(stmfx->map, STMFX_REG_FW_VERSION_MSB,
version, ARRAY_SIZE(version));
if (ret) {
dev_err(&client->dev, "Error reading FW version: %d\n", ret);
goto err;
}
dev_info(&client->dev, "STMFX id: %#x, fw version: %x.%02x\n",
id, version[0], version[1]);
ret = stmfx_chip_reset(stmfx);
if (ret) {
dev_err(&client->dev, "Failed to reset chip: %d\n", ret);
goto err;
}
return 0;
err:
if (stmfx->vdd)
regulator_disable(stmfx->vdd);
return ret;
}
static void stmfx_chip_exit(struct i2c_client *client)
{
struct stmfx *stmfx = i2c_get_clientdata(client);
regmap_write(stmfx->map, STMFX_REG_IRQ_SRC_EN, 0);
regmap_write(stmfx->map, STMFX_REG_SYS_CTRL, 0);
if (stmfx->vdd) {
int ret;
ret = regulator_disable(stmfx->vdd);
if (ret)
dev_err(&client->dev,
"Failed to disable vdd regulator: %pe\n",
ERR_PTR(ret));
}
}
static int stmfx_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct stmfx *stmfx;
int ret;
stmfx = devm_kzalloc(dev, sizeof(*stmfx), GFP_KERNEL);
if (!stmfx)
return -ENOMEM;
i2c_set_clientdata(client, stmfx);
stmfx->dev = dev;
stmfx->map = devm_regmap_init_i2c(client, &stmfx_regmap_config);
if (IS_ERR(stmfx->map)) {
ret = PTR_ERR(stmfx->map);
dev_err(dev, "Failed to allocate register map: %d\n", ret);
return ret;
}
mutex_init(&stmfx->lock);
ret = stmfx_chip_init(client);
if (ret) {
if (ret == -ETIMEDOUT)
return -EPROBE_DEFER;
return ret;
}
if (client->irq < 0) {
dev_err(dev, "Failed to get IRQ: %d\n", client->irq);
ret = client->irq;
goto err_chip_exit;
}
ret = stmfx_irq_init(client);
if (ret)
goto err_chip_exit;
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
stmfx_cells, ARRAY_SIZE(stmfx_cells), NULL,
0, stmfx->irq_domain);
if (ret)
goto err_irq_exit;
return 0;
err_irq_exit:
stmfx_irq_exit(client);
err_chip_exit:
stmfx_chip_exit(client);
return ret;
}
static void stmfx_remove(struct i2c_client *client)
{
stmfx_irq_exit(client);
stmfx_chip_exit(client);
}
static int stmfx_suspend(struct device *dev)
{
struct stmfx *stmfx = dev_get_drvdata(dev);
int ret;
ret = regmap_raw_read(stmfx->map, STMFX_REG_SYS_CTRL,
&stmfx->bkp_sysctrl, sizeof(stmfx->bkp_sysctrl));
if (ret)
return ret;
ret = regmap_raw_read(stmfx->map, STMFX_REG_IRQ_OUT_PIN,
&stmfx->bkp_irqoutpin,
sizeof(stmfx->bkp_irqoutpin));
if (ret)
return ret;
disable_irq(stmfx->irq);
if (stmfx->vdd)
return regulator_disable(stmfx->vdd);
return 0;
}
static int stmfx_resume(struct device *dev)
{
struct stmfx *stmfx = dev_get_drvdata(dev);
int ret;
if (stmfx->vdd) {
ret = regulator_enable(stmfx->vdd);
if (ret) {
dev_err(stmfx->dev,
"VDD enable failed: %d\n", ret);
return ret;
}
}
/* Reset STMFX - supply has been stopped during suspend */
ret = stmfx_chip_reset(stmfx);
if (ret) {
dev_err(stmfx->dev, "Failed to reset chip: %d\n", ret);
return ret;
}
ret = regmap_raw_write(stmfx->map, STMFX_REG_SYS_CTRL,
&stmfx->bkp_sysctrl, sizeof(stmfx->bkp_sysctrl));
if (ret)
return ret;
ret = regmap_raw_write(stmfx->map, STMFX_REG_IRQ_OUT_PIN,
&stmfx->bkp_irqoutpin,
sizeof(stmfx->bkp_irqoutpin));
if (ret)
return ret;
ret = regmap_raw_write(stmfx->map, STMFX_REG_IRQ_SRC_EN,
&stmfx->irq_src, sizeof(stmfx->irq_src));
if (ret)
return ret;
enable_irq(stmfx->irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(stmfx_dev_pm_ops, stmfx_suspend, stmfx_resume);
static const struct of_device_id stmfx_of_match[] = {
{ .compatible = "st,stmfx-0300", },
{},
};
MODULE_DEVICE_TABLE(of, stmfx_of_match);
static struct i2c_driver stmfx_driver = {
.driver = {
.name = "stmfx-core",
.of_match_table = stmfx_of_match,
.pm = pm_sleep_ptr(&stmfx_dev_pm_ops),
},
.probe = stmfx_probe,
.remove = stmfx_remove,
};
module_i2c_driver(stmfx_driver);
MODULE_DESCRIPTION("STMFX core driver");
MODULE_AUTHOR("Amelie Delaunay <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/stmfx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* sky81452.c SKY81452 MFD driver
*
* Copyright 2014 Skyworks Solutions Inc.
* Author : Gyungoh Yoo <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/mfd/sky81452.h>
static const struct regmap_config sky81452_config = {
.reg_bits = 8,
.val_bits = 8,
};
static int sky81452_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
const struct sky81452_platform_data *pdata = dev_get_platdata(dev);
struct mfd_cell cells[2];
struct regmap *regmap;
int ret;
if (!pdata) {
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
}
regmap = devm_regmap_init_i2c(client, &sky81452_config);
if (IS_ERR(regmap)) {
dev_err(dev, "failed to initialize.err=%ld\n", PTR_ERR(regmap));
return PTR_ERR(regmap);
}
i2c_set_clientdata(client, regmap);
memset(cells, 0, sizeof(cells));
cells[0].name = "sky81452-backlight";
cells[0].of_compatible = "skyworks,sky81452-backlight";
cells[1].name = "sky81452-regulator";
cells[1].platform_data = pdata->regulator_init_data;
cells[1].pdata_size = sizeof(*pdata->regulator_init_data);
ret = devm_mfd_add_devices(dev, -1, cells, ARRAY_SIZE(cells),
NULL, 0, NULL);
if (ret)
dev_err(dev, "failed to add child devices. err=%d\n", ret);
return ret;
}
static const struct i2c_device_id sky81452_ids[] = {
{ "sky81452" },
{ }
};
MODULE_DEVICE_TABLE(i2c, sky81452_ids);
#ifdef CONFIG_OF
static const struct of_device_id sky81452_of_match[] = {
{ .compatible = "skyworks,sky81452", },
{ }
};
MODULE_DEVICE_TABLE(of, sky81452_of_match);
#endif
static struct i2c_driver sky81452_driver = {
.driver = {
.name = "sky81452",
.of_match_table = of_match_ptr(sky81452_of_match),
},
.probe = sky81452_probe,
.id_table = sky81452_ids,
};
module_i2c_driver(sky81452_driver);
MODULE_DESCRIPTION("Skyworks SKY81452 MFD driver");
MODULE_AUTHOR("Gyungoh Yoo <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/sky81452.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* MFD driver for wl1273 FM radio and audio codec submodules.
*
* Copyright (C) 2011 Nokia Corporation
* Author: Matti Aaltonen <[email protected]>
*/
#include <linux/mfd/wl1273-core.h>
#include <linux/slab.h>
#include <linux/module.h>
#define DRIVER_DESC "WL1273 FM Radio Core"
static const struct i2c_device_id wl1273_driver_id_table[] = {
{ WL1273_FM_DRIVER_NAME, 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, wl1273_driver_id_table);
static int wl1273_fm_read_reg(struct wl1273_core *core, u8 reg, u16 *value)
{
struct i2c_client *client = core->client;
u8 b[2];
int r;
r = i2c_smbus_read_i2c_block_data(client, reg, sizeof(b), b);
if (r != 2) {
dev_err(&client->dev, "%s: Read: %d fails.\n", __func__, reg);
return -EREMOTEIO;
}
*value = (u16)b[0] << 8 | b[1];
return 0;
}
static int wl1273_fm_write_cmd(struct wl1273_core *core, u8 cmd, u16 param)
{
struct i2c_client *client = core->client;
u8 buf[] = { (param >> 8) & 0xff, param & 0xff };
int r;
r = i2c_smbus_write_i2c_block_data(client, cmd, sizeof(buf), buf);
if (r) {
dev_err(&client->dev, "%s: Cmd: %d fails.\n", __func__, cmd);
return r;
}
return 0;
}
static int wl1273_fm_write_data(struct wl1273_core *core, u8 *data, u16 len)
{
struct i2c_client *client = core->client;
struct i2c_msg msg;
int r;
msg.addr = client->addr;
msg.flags = 0;
msg.buf = data;
msg.len = len;
r = i2c_transfer(client->adapter, &msg, 1);
if (r != 1) {
dev_err(&client->dev, "%s: write error.\n", __func__);
return -EREMOTEIO;
}
return 0;
}
/**
* wl1273_fm_set_audio() - Set audio mode.
* @core: A pointer to the device struct.
* @new_mode: The new audio mode.
*
* Audio modes are WL1273_AUDIO_DIGITAL and WL1273_AUDIO_ANALOG.
*/
static int wl1273_fm_set_audio(struct wl1273_core *core, unsigned int new_mode)
{
int r = 0;
if (core->mode == WL1273_MODE_OFF ||
core->mode == WL1273_MODE_SUSPENDED)
return -EPERM;
if (core->mode == WL1273_MODE_RX && new_mode == WL1273_AUDIO_DIGITAL) {
r = wl1273_fm_write_cmd(core, WL1273_PCM_MODE_SET,
WL1273_PCM_DEF_MODE);
if (r)
goto out;
r = wl1273_fm_write_cmd(core, WL1273_I2S_MODE_CONFIG_SET,
core->i2s_mode);
if (r)
goto out;
r = wl1273_fm_write_cmd(core, WL1273_AUDIO_ENABLE,
WL1273_AUDIO_ENABLE_I2S);
if (r)
goto out;
} else if (core->mode == WL1273_MODE_RX &&
new_mode == WL1273_AUDIO_ANALOG) {
r = wl1273_fm_write_cmd(core, WL1273_AUDIO_ENABLE,
WL1273_AUDIO_ENABLE_ANALOG);
if (r)
goto out;
} else if (core->mode == WL1273_MODE_TX &&
new_mode == WL1273_AUDIO_DIGITAL) {
r = wl1273_fm_write_cmd(core, WL1273_I2S_MODE_CONFIG_SET,
core->i2s_mode);
if (r)
goto out;
r = wl1273_fm_write_cmd(core, WL1273_AUDIO_IO_SET,
WL1273_AUDIO_IO_SET_I2S);
if (r)
goto out;
} else if (core->mode == WL1273_MODE_TX &&
new_mode == WL1273_AUDIO_ANALOG) {
r = wl1273_fm_write_cmd(core, WL1273_AUDIO_IO_SET,
WL1273_AUDIO_IO_SET_ANALOG);
if (r)
goto out;
}
core->audio_mode = new_mode;
out:
return r;
}
/**
* wl1273_fm_set_volume() - Set volume.
* @core: A pointer to the device struct.
* @volume: The new volume value.
*/
static int wl1273_fm_set_volume(struct wl1273_core *core, unsigned int volume)
{
int r;
if (volume > WL1273_MAX_VOLUME)
return -EINVAL;
if (core->volume == volume)
return 0;
r = wl1273_fm_write_cmd(core, WL1273_VOLUME_SET, volume);
if (r)
return r;
core->volume = volume;
return 0;
}
static int wl1273_core_probe(struct i2c_client *client)
{
struct wl1273_fm_platform_data *pdata = dev_get_platdata(&client->dev);
struct wl1273_core *core;
struct mfd_cell *cell;
int children = 0;
int r = 0;
dev_dbg(&client->dev, "%s\n", __func__);
if (!pdata) {
dev_err(&client->dev, "No platform data.\n");
return -EINVAL;
}
if (!(pdata->children & WL1273_RADIO_CHILD)) {
dev_err(&client->dev, "Cannot function without radio child.\n");
return -EINVAL;
}
core = devm_kzalloc(&client->dev, sizeof(*core), GFP_KERNEL);
if (!core)
return -ENOMEM;
core->pdata = pdata;
core->client = client;
mutex_init(&core->lock);
i2c_set_clientdata(client, core);
dev_dbg(&client->dev, "%s: Have V4L2.\n", __func__);
cell = &core->cells[children];
cell->name = "wl1273_fm_radio";
cell->platform_data = &core;
cell->pdata_size = sizeof(core);
children++;
core->read = wl1273_fm_read_reg;
core->write = wl1273_fm_write_cmd;
core->write_data = wl1273_fm_write_data;
core->set_audio = wl1273_fm_set_audio;
core->set_volume = wl1273_fm_set_volume;
if (pdata->children & WL1273_CODEC_CHILD) {
cell = &core->cells[children];
dev_dbg(&client->dev, "%s: Have codec.\n", __func__);
cell->name = "wl1273-codec";
cell->platform_data = &core;
cell->pdata_size = sizeof(core);
children++;
}
dev_dbg(&client->dev, "%s: number of children: %d.\n",
__func__, children);
r = devm_mfd_add_devices(&client->dev, -1, core->cells,
children, NULL, 0, NULL);
if (r)
goto err;
return 0;
err:
pdata->free_resources();
dev_dbg(&client->dev, "%s\n", __func__);
return r;
}
static struct i2c_driver wl1273_core_driver = {
.driver = {
.name = WL1273_FM_DRIVER_NAME,
},
.probe = wl1273_core_probe,
.id_table = wl1273_driver_id_table,
};
static int __init wl1273_core_init(void)
{
int r;
r = i2c_add_driver(&wl1273_core_driver);
if (r) {
pr_err(WL1273_FM_DRIVER_NAME
": driver registration failed\n");
return r;
}
return r;
}
static void __exit wl1273_core_exit(void)
{
i2c_del_driver(&wl1273_core_driver);
}
late_initcall(wl1273_core_init);
module_exit(wl1273_core_exit);
MODULE_AUTHOR("Matti Aaltonen <[email protected]>");
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/wl1273-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2017 Spreadtrum Communications Inc.
*/
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mfd/core.h>
#include <linux/mfd/sc27xx-pmic.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <uapi/linux/usb/charger.h>
#define SPRD_PMIC_INT_MASK_STATUS 0x0
#define SPRD_PMIC_INT_RAW_STATUS 0x4
#define SPRD_PMIC_INT_EN 0x8
#define SPRD_SC2730_IRQ_BASE 0x80
#define SPRD_SC2730_IRQ_NUMS 10
#define SPRD_SC2730_CHG_DET 0x1b9c
#define SPRD_SC2731_IRQ_BASE 0x140
#define SPRD_SC2731_IRQ_NUMS 16
#define SPRD_SC2731_CHG_DET 0xedc
/* PMIC charger detection definition */
#define SPRD_PMIC_CHG_DET_DELAY_US 200000
#define SPRD_PMIC_CHG_DET_TIMEOUT 2000000
#define SPRD_PMIC_CHG_DET_DONE BIT(11)
#define SPRD_PMIC_SDP_TYPE BIT(7)
#define SPRD_PMIC_DCP_TYPE BIT(6)
#define SPRD_PMIC_CDP_TYPE BIT(5)
#define SPRD_PMIC_CHG_TYPE_MASK GENMASK(7, 5)
struct sprd_pmic {
struct regmap *regmap;
struct device *dev;
struct regmap_irq *irqs;
struct regmap_irq_chip irq_chip;
struct regmap_irq_chip_data *irq_data;
const struct sprd_pmic_data *pdata;
int irq;
};
struct sprd_pmic_data {
u32 irq_base;
u32 num_irqs;
u32 charger_det;
};
/*
* Since different PMICs of SC27xx series can have different interrupt
* base address and irq number, we should save irq number and irq base
* in the device data structure.
*/
static const struct sprd_pmic_data sc2730_data = {
.irq_base = SPRD_SC2730_IRQ_BASE,
.num_irqs = SPRD_SC2730_IRQ_NUMS,
.charger_det = SPRD_SC2730_CHG_DET,
};
static const struct sprd_pmic_data sc2731_data = {
.irq_base = SPRD_SC2731_IRQ_BASE,
.num_irqs = SPRD_SC2731_IRQ_NUMS,
.charger_det = SPRD_SC2731_CHG_DET,
};
enum usb_charger_type sprd_pmic_detect_charger_type(struct device *dev)
{
struct spi_device *spi = to_spi_device(dev);
struct sprd_pmic *ddata = spi_get_drvdata(spi);
const struct sprd_pmic_data *pdata = ddata->pdata;
enum usb_charger_type type;
u32 val;
int ret;
ret = regmap_read_poll_timeout(ddata->regmap, pdata->charger_det, val,
(val & SPRD_PMIC_CHG_DET_DONE),
SPRD_PMIC_CHG_DET_DELAY_US,
SPRD_PMIC_CHG_DET_TIMEOUT);
if (ret) {
dev_err(&spi->dev, "failed to detect charger type\n");
return UNKNOWN_TYPE;
}
switch (val & SPRD_PMIC_CHG_TYPE_MASK) {
case SPRD_PMIC_CDP_TYPE:
type = CDP_TYPE;
break;
case SPRD_PMIC_DCP_TYPE:
type = DCP_TYPE;
break;
case SPRD_PMIC_SDP_TYPE:
type = SDP_TYPE;
break;
default:
type = UNKNOWN_TYPE;
break;
}
return type;
}
EXPORT_SYMBOL_GPL(sprd_pmic_detect_charger_type);
static int sprd_pmic_spi_write(void *context, const void *data, size_t count)
{
struct device *dev = context;
struct spi_device *spi = to_spi_device(dev);
return spi_write(spi, data, count);
}
static int sprd_pmic_spi_read(void *context,
const void *reg, size_t reg_size,
void *val, size_t val_size)
{
struct device *dev = context;
struct spi_device *spi = to_spi_device(dev);
u32 rx_buf[2] = { 0 };
int ret;
/* Now we only support one PMIC register to read every time. */
if (reg_size != sizeof(u32) || val_size != sizeof(u32))
return -EINVAL;
/* Copy address to read from into first element of SPI buffer. */
memcpy(rx_buf, reg, sizeof(u32));
ret = spi_read(spi, rx_buf, 1);
if (ret < 0)
return ret;
memcpy(val, rx_buf, val_size);
return 0;
}
static struct regmap_bus sprd_pmic_regmap = {
.write = sprd_pmic_spi_write,
.read = sprd_pmic_spi_read,
.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
};
static const struct regmap_config sprd_pmic_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = 0xffff,
};
static int sprd_pmic_probe(struct spi_device *spi)
{
struct sprd_pmic *ddata;
const struct sprd_pmic_data *pdata;
int ret, i;
pdata = of_device_get_match_data(&spi->dev);
if (!pdata) {
dev_err(&spi->dev, "No matching driver data found\n");
return -EINVAL;
}
ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
ddata->regmap = devm_regmap_init(&spi->dev, &sprd_pmic_regmap,
&spi->dev, &sprd_pmic_config);
if (IS_ERR(ddata->regmap)) {
ret = PTR_ERR(ddata->regmap);
dev_err(&spi->dev, "Failed to allocate register map %d\n", ret);
return ret;
}
spi_set_drvdata(spi, ddata);
ddata->dev = &spi->dev;
ddata->irq = spi->irq;
ddata->pdata = pdata;
ddata->irq_chip.name = dev_name(&spi->dev);
ddata->irq_chip.status_base =
pdata->irq_base + SPRD_PMIC_INT_MASK_STATUS;
ddata->irq_chip.unmask_base = pdata->irq_base + SPRD_PMIC_INT_EN;
ddata->irq_chip.ack_base = 0;
ddata->irq_chip.num_regs = 1;
ddata->irq_chip.num_irqs = pdata->num_irqs;
ddata->irqs = devm_kcalloc(&spi->dev,
pdata->num_irqs, sizeof(struct regmap_irq),
GFP_KERNEL);
if (!ddata->irqs)
return -ENOMEM;
ddata->irq_chip.irqs = ddata->irqs;
for (i = 0; i < pdata->num_irqs; i++)
ddata->irqs[i].mask = BIT(i);
ret = devm_regmap_add_irq_chip(&spi->dev, ddata->regmap, ddata->irq,
IRQF_ONESHOT, 0,
&ddata->irq_chip, &ddata->irq_data);
if (ret) {
dev_err(&spi->dev, "Failed to add PMIC irq chip %d\n", ret);
return ret;
}
ret = devm_of_platform_populate(&spi->dev);
if (ret) {
dev_err(&spi->dev, "Failed to populate sub-devices %d\n", ret);
return ret;
}
device_init_wakeup(&spi->dev, true);
return 0;
}
static int sprd_pmic_suspend(struct device *dev)
{
struct sprd_pmic *ddata = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
enable_irq_wake(ddata->irq);
return 0;
}
static int sprd_pmic_resume(struct device *dev)
{
struct sprd_pmic *ddata = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
disable_irq_wake(ddata->irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(sprd_pmic_pm_ops,
sprd_pmic_suspend, sprd_pmic_resume);
static const struct of_device_id sprd_pmic_match[] = {
{ .compatible = "sprd,sc2730", .data = &sc2730_data },
{ .compatible = "sprd,sc2731", .data = &sc2731_data },
{},
};
MODULE_DEVICE_TABLE(of, sprd_pmic_match);
static const struct spi_device_id sprd_pmic_spi_ids[] = {
{ .name = "sc2730", .driver_data = (unsigned long)&sc2730_data },
{ .name = "sc2731", .driver_data = (unsigned long)&sc2731_data },
{},
};
MODULE_DEVICE_TABLE(spi, sprd_pmic_spi_ids);
static struct spi_driver sprd_pmic_driver = {
.driver = {
.name = "sc27xx-pmic",
.of_match_table = sprd_pmic_match,
.pm = pm_sleep_ptr(&sprd_pmic_pm_ops),
},
.probe = sprd_pmic_probe,
.id_table = sprd_pmic_spi_ids,
};
static int __init sprd_pmic_init(void)
{
return spi_register_driver(&sprd_pmic_driver);
}
subsys_initcall(sprd_pmic_init);
static void __exit sprd_pmic_exit(void)
{
spi_unregister_driver(&sprd_pmic_driver);
}
module_exit(sprd_pmic_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Spreadtrum SC27xx PMICs driver");
MODULE_AUTHOR("Baolin Wang <[email protected]>");
| linux-master | drivers/mfd/sprd-sc27xx-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*/
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/gfp.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spmi.h>
#include <linux/types.h>
#include <linux/regmap.h>
#include <linux/of_platform.h>
#include <soc/qcom/qcom-spmi-pmic.h>
#define PMIC_REV2 0x101
#define PMIC_REV3 0x102
#define PMIC_REV4 0x103
#define PMIC_TYPE 0x104
#define PMIC_SUBTYPE 0x105
#define PMIC_FAB_ID 0x1f2
#define PMIC_TYPE_VALUE 0x51
#define PMIC_REV4_V2 0x02
struct qcom_spmi_dev {
int num_usids;
struct qcom_spmi_pmic pmic;
};
#define N_USIDS(n) ((void *)n)
static const struct of_device_id pmic_spmi_id_table[] = {
{ .compatible = "qcom,pm660", .data = N_USIDS(2) },
{ .compatible = "qcom,pm660l", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8004", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8005", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8019", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8028", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8110", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8150", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8150b", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8150c", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8150l", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8226", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8841", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8901", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8909", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8916", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8941", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8950", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8994", .data = N_USIDS(2) },
{ .compatible = "qcom,pm8998", .data = N_USIDS(2) },
{ .compatible = "qcom,pma8084", .data = N_USIDS(2) },
{ .compatible = "qcom,pmd9635", .data = N_USIDS(2) },
{ .compatible = "qcom,pmi8950", .data = N_USIDS(2) },
{ .compatible = "qcom,pmi8962", .data = N_USIDS(2) },
{ .compatible = "qcom,pmi8994", .data = N_USIDS(2) },
{ .compatible = "qcom,pmi8998", .data = N_USIDS(2) },
{ .compatible = "qcom,pmk8002", .data = N_USIDS(2) },
{ .compatible = "qcom,pmp8074", .data = N_USIDS(2) },
{ .compatible = "qcom,smb2351", .data = N_USIDS(2) },
{ .compatible = "qcom,spmi-pmic", .data = N_USIDS(1) },
{ }
};
/*
* A PMIC can be represented by multiple SPMI devices, but
* only the base PMIC device will contain a reference to
* the revision information.
*
* This function takes a pointer to a pmic device and
* returns a pointer to the base PMIC device.
*
* This only supports PMICs with 1 or 2 USIDs.
*/
static struct spmi_device *qcom_pmic_get_base_usid(struct device *dev)
{
struct spmi_device *sdev;
struct qcom_spmi_dev *ctx;
struct device_node *spmi_bus;
struct device_node *other_usid = NULL;
int function_parent_usid, ret;
u32 pmic_addr;
sdev = to_spmi_device(dev);
ctx = dev_get_drvdata(&sdev->dev);
/*
* Quick return if the function device is already in the base
* USID. This will always be hit for PMICs with only 1 USID.
*/
if (sdev->usid % ctx->num_usids == 0)
return sdev;
function_parent_usid = sdev->usid;
/*
* Walk through the list of PMICs until we find the sibling USID.
* The goal is to find the first USID which is less than the
* number of USIDs in the PMIC array, e.g. for a PMIC with 2 USIDs
* where the function device is under USID 3, we want to find the
* device for USID 2.
*/
spmi_bus = of_get_parent(sdev->dev.of_node);
do {
other_usid = of_get_next_child(spmi_bus, other_usid);
ret = of_property_read_u32_index(other_usid, "reg", 0, &pmic_addr);
if (ret)
return ERR_PTR(ret);
sdev = spmi_device_from_of(other_usid);
if (pmic_addr == function_parent_usid - (ctx->num_usids - 1)) {
if (!sdev)
/*
* If the base USID for this PMIC hasn't probed yet
* but the secondary USID has, then we need to defer
* the function driver so that it will attempt to
* probe again when the base USID is ready.
*/
return ERR_PTR(-EPROBE_DEFER);
return sdev;
}
} while (other_usid->sibling);
return ERR_PTR(-ENODATA);
}
static int pmic_spmi_load_revid(struct regmap *map, struct device *dev,
struct qcom_spmi_pmic *pmic)
{
int ret;
ret = regmap_read(map, PMIC_TYPE, &pmic->type);
if (ret < 0)
return ret;
if (pmic->type != PMIC_TYPE_VALUE)
return ret;
ret = regmap_read(map, PMIC_SUBTYPE, &pmic->subtype);
if (ret < 0)
return ret;
pmic->name = of_match_device(pmic_spmi_id_table, dev)->compatible;
ret = regmap_read(map, PMIC_REV2, &pmic->rev2);
if (ret < 0)
return ret;
ret = regmap_read(map, PMIC_REV3, &pmic->minor);
if (ret < 0)
return ret;
ret = regmap_read(map, PMIC_REV4, &pmic->major);
if (ret < 0)
return ret;
if (pmic->subtype == PMI8998_SUBTYPE || pmic->subtype == PM660_SUBTYPE) {
ret = regmap_read(map, PMIC_FAB_ID, &pmic->fab_id);
if (ret < 0)
return ret;
}
/*
* In early versions of PM8941 and PM8226, the major revision number
* started incrementing from 0 (eg 0 = v1.0, 1 = v2.0).
* Increment the major revision number here if the chip is an early
* version of PM8941 or PM8226.
*/
if ((pmic->subtype == PM8941_SUBTYPE || pmic->subtype == PM8226_SUBTYPE) &&
pmic->major < PMIC_REV4_V2)
pmic->major++;
if (pmic->subtype == PM8110_SUBTYPE)
pmic->minor = pmic->rev2;
dev_dbg(dev, "%x: %s v%d.%d\n",
pmic->subtype, pmic->name, pmic->major, pmic->minor);
return 0;
}
/**
* qcom_pmic_get() - Get a pointer to the base PMIC device
*
* This function takes a struct device for a driver which is a child of a PMIC.
* And locates the PMIC revision information for it.
*
* @dev: the pmic function device
* @return: the struct qcom_spmi_pmic* pointer associated with the function device
*/
const struct qcom_spmi_pmic *qcom_pmic_get(struct device *dev)
{
struct spmi_device *sdev;
struct qcom_spmi_dev *spmi;
/*
* Make sure the device is actually a child of a PMIC
*/
if (!of_match_device(pmic_spmi_id_table, dev->parent))
return ERR_PTR(-EINVAL);
sdev = qcom_pmic_get_base_usid(dev->parent);
if (IS_ERR(sdev))
return ERR_CAST(sdev);
spmi = dev_get_drvdata(&sdev->dev);
return &spmi->pmic;
}
EXPORT_SYMBOL(qcom_pmic_get);
static const struct regmap_config spmi_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.max_register = 0xffff,
.fast_io = true,
};
static int pmic_spmi_probe(struct spmi_device *sdev)
{
struct regmap *regmap;
struct qcom_spmi_dev *ctx;
int ret;
regmap = devm_regmap_init_spmi_ext(sdev, &spmi_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ctx = devm_kzalloc(&sdev->dev, sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
ctx->num_usids = (uintptr_t)of_device_get_match_data(&sdev->dev);
/* Only the first slave id for a PMIC contains this information */
if (sdev->usid % ctx->num_usids == 0) {
ret = pmic_spmi_load_revid(regmap, &sdev->dev, &ctx->pmic);
if (ret < 0)
return ret;
}
spmi_device_set_drvdata(sdev, ctx);
return devm_of_platform_populate(&sdev->dev);
}
MODULE_DEVICE_TABLE(of, pmic_spmi_id_table);
static struct spmi_driver pmic_spmi_driver = {
.probe = pmic_spmi_probe,
.driver = {
.name = "pmic-spmi",
.of_match_table = pmic_spmi_id_table,
},
};
module_spmi_driver(pmic_spmi_driver);
MODULE_DESCRIPTION("Qualcomm SPMI PMIC driver");
MODULE_ALIAS("spmi:spmi-pmic");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Josh Cartwright <[email protected]>");
MODULE_AUTHOR("Stanimir Varbanov <[email protected]>");
| linux-master | drivers/mfd/qcom-spmi-pmic.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8994-regmap.c -- Register map data for WM8994 series devices
*
* Copyright 2011 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/mfd/wm8994/core.h>
#include <linux/mfd/wm8994/registers.h>
#include <linux/regmap.h>
#include <linux/device.h>
#include "wm8994.h"
static const struct reg_default wm1811_defaults[] = {
{ 0x0001, 0x0000 }, /* R1 - Power Management (1) */
{ 0x0002, 0x6000 }, /* R2 - Power Management (2) */
{ 0x0003, 0x0000 }, /* R3 - Power Management (3) */
{ 0x0004, 0x0000 }, /* R4 - Power Management (4) */
{ 0x0005, 0x0000 }, /* R5 - Power Management (5) */
{ 0x0006, 0x0000 }, /* R6 - Power Management (6) */
{ 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
{ 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
{ 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
{ 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
{ 0x001B, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
{ 0x001C, 0x006D }, /* R28 - Left Output Volume */
{ 0x001D, 0x006D }, /* R29 - Right Output Volume */
{ 0x001E, 0x0066 }, /* R30 - Line Outputs Volume */
{ 0x001F, 0x0020 }, /* R31 - HPOUT2 Volume */
{ 0x0020, 0x0079 }, /* R32 - Left OPGA Volume */
{ 0x0021, 0x0079 }, /* R33 - Right OPGA Volume */
{ 0x0022, 0x0003 }, /* R34 - SPKMIXL Attenuation */
{ 0x0023, 0x0003 }, /* R35 - SPKMIXR Attenuation */
{ 0x0024, 0x0011 }, /* R36 - SPKOUT Mixers */
{ 0x0025, 0x0140 }, /* R37 - ClassD */
{ 0x0026, 0x0079 }, /* R38 - Speaker Volume Left */
{ 0x0027, 0x0079 }, /* R39 - Speaker Volume Right */
{ 0x0028, 0x0000 }, /* R40 - Input Mixer (2) */
{ 0x0029, 0x0000 }, /* R41 - Input Mixer (3) */
{ 0x002A, 0x0000 }, /* R42 - Input Mixer (4) */
{ 0x002B, 0x0000 }, /* R43 - Input Mixer (5) */
{ 0x002C, 0x0000 }, /* R44 - Input Mixer (6) */
{ 0x002D, 0x0000 }, /* R45 - Output Mixer (1) */
{ 0x002E, 0x0000 }, /* R46 - Output Mixer (2) */
{ 0x002F, 0x0000 }, /* R47 - Output Mixer (3) */
{ 0x0030, 0x0000 }, /* R48 - Output Mixer (4) */
{ 0x0031, 0x0000 }, /* R49 - Output Mixer (5) */
{ 0x0032, 0x0000 }, /* R50 - Output Mixer (6) */
{ 0x0033, 0x0000 }, /* R51 - HPOUT2 Mixer */
{ 0x0034, 0x0000 }, /* R52 - Line Mixer (1) */
{ 0x0035, 0x0000 }, /* R53 - Line Mixer (2) */
{ 0x0036, 0x0000 }, /* R54 - Speaker Mixer */
{ 0x0037, 0x0000 }, /* R55 - Additional Control */
{ 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */
{ 0x0039, 0x0000 }, /* R57 - AntiPOP (2) */
{ 0x003B, 0x000D }, /* R59 - LDO 1 */
{ 0x003C, 0x0003 }, /* R60 - LDO 2 */
{ 0x003D, 0x0039 }, /* R61 - MICBIAS1 */
{ 0x003E, 0x0039 }, /* R62 - MICBIAS2 */
{ 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */
{ 0x004D, 0xAB19 }, /* R77 - Charge Pump (2) */
{ 0x0051, 0x0004 }, /* R81 - Class W (1) */
{ 0x0055, 0x054A }, /* R85 - DC Servo (2) */
{ 0x0059, 0x0000 }, /* R89 - DC Servo (4) */
{ 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */
{ 0x00C5, 0x0000 }, /* R197 - Class D Test (5) */
{ 0x00D0, 0x7600 }, /* R208 - Mic Detect 1 */
{ 0x00D1, 0x007F }, /* R209 - Mic Detect 2 */
{ 0x0101, 0x8004 }, /* R257 - Control Interface */
{ 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */
{ 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */
{ 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */
{ 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */
{ 0x0208, 0x0000 }, /* R520 - Clocking (1) */
{ 0x0209, 0x0000 }, /* R521 - Clocking (2) */
{ 0x0210, 0x0083 }, /* R528 - AIF1 Rate */
{ 0x0211, 0x0083 }, /* R529 - AIF2 Rate */
{ 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */
{ 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */
{ 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */
{ 0x0223, 0x0000 }, /* R547 - FLL1 Control (4) */
{ 0x0224, 0x0C80 }, /* R548 - FLL1 Control (5) */
{ 0x0226, 0x0000 }, /* R550 - FLL1 EFS 1 */
{ 0x0227, 0x0006 }, /* R551 - FLL1 EFS 2 */
{ 0x0240, 0x0000 }, /* R576 - FLL2Control (1) */
{ 0x0241, 0x0000 }, /* R577 - FLL2Control (2) */
{ 0x0242, 0x0000 }, /* R578 - FLL2Control (3) */
{ 0x0243, 0x0000 }, /* R579 - FLL2 Control (4) */
{ 0x0244, 0x0C80 }, /* R580 - FLL2Control (5) */
{ 0x0246, 0x0000 }, /* R582 - FLL2 EFS 1 */
{ 0x0247, 0x0006 }, /* R583 - FLL2 EFS 2 */
{ 0x0300, 0x4050 }, /* R768 - AIF1 Control (1) */
{ 0x0301, 0x4000 }, /* R769 - AIF1 Control (2) */
{ 0x0302, 0x0000 }, /* R770 - AIF1 Master/Slave */
{ 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */
{ 0x0304, 0x0040 }, /* R772 - AIF1ADC LRCLK */
{ 0x0305, 0x0040 }, /* R773 - AIF1DAC LRCLK */
{ 0x0306, 0x0004 }, /* R774 - AIF1DAC Data */
{ 0x0307, 0x0100 }, /* R775 - AIF1ADC Data */
{ 0x0310, 0x4050 }, /* R784 - AIF2 Control (1) */
{ 0x0311, 0x4000 }, /* R785 - AIF2 Control (2) */
{ 0x0312, 0x0000 }, /* R786 - AIF2 Master/Slave */
{ 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */
{ 0x0314, 0x0040 }, /* R788 - AIF2ADC LRCLK */
{ 0x0315, 0x0040 }, /* R789 - AIF2DAC LRCLK */
{ 0x0316, 0x0000 }, /* R790 - AIF2DAC Data */
{ 0x0317, 0x0000 }, /* R791 - AIF2ADC Data */
{ 0x0318, 0x0003 }, /* R792 - AIF2TX Control */
{ 0x0320, 0x0040 }, /* R800 - AIF3 Control (1) */
{ 0x0321, 0x0000 }, /* R801 - AIF3 Control (2) */
{ 0x0322, 0x0000 }, /* R802 - AIF3DAC Data */
{ 0x0323, 0x0000 }, /* R803 - AIF3ADC Data */
{ 0x0400, 0x00C0 }, /* R1024 - AIF1 ADC1 Left Volume */
{ 0x0401, 0x00C0 }, /* R1025 - AIF1 ADC1 Right Volume */
{ 0x0402, 0x00C0 }, /* R1026 - AIF1 DAC1 Left Volume */
{ 0x0403, 0x00C0 }, /* R1027 - AIF1 DAC1 Right Volume */
{ 0x0410, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */
{ 0x0411, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */
{ 0x0420, 0x0200 }, /* R1056 - AIF1 DAC1 Filters (1) */
{ 0x0421, 0x0010 }, /* R1057 - AIF1 DAC1 Filters (2) */
{ 0x0422, 0x0200 }, /* R1058 - AIF1 DAC2 Filters (1) */
{ 0x0423, 0x0010 }, /* R1059 - AIF1 DAC2 Filters (2) */
{ 0x0430, 0x0068 }, /* R1072 - AIF1 DAC1 Noise Gate */
{ 0x0431, 0x0068 }, /* R1073 - AIF1 DAC2 Noise Gate */
{ 0x0440, 0x0098 }, /* R1088 - AIF1 DRC1 (1) */
{ 0x0441, 0x0845 }, /* R1089 - AIF1 DRC1 (2) */
{ 0x0442, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */
{ 0x0443, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */
{ 0x0444, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */
{ 0x0450, 0x0098 }, /* R1104 - AIF1 DRC2 (1) */
{ 0x0451, 0x0845 }, /* R1105 - AIF1 DRC2 (2) */
{ 0x0452, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */
{ 0x0453, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */
{ 0x0454, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */
{ 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
{ 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
{ 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
{ 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
{ 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
{ 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
{ 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
{ 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
{ 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
{ 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
{ 0x048A, 0xF373 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
{ 0x048B, 0x0A54 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
{ 0x048C, 0x0558 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
{ 0x048D, 0x168E }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
{ 0x048E, 0xF829 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
{ 0x048F, 0x07AD }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
{ 0x0490, 0x1103 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
{ 0x0491, 0x0564 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
{ 0x0492, 0x0559 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
{ 0x0493, 0x4000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
{ 0x0494, 0x0000 }, /* R1172 - AIF1 DAC1 EQ Band 1 C */
{ 0x04A0, 0x6318 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
{ 0x04A1, 0x6300 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
{ 0x04A2, 0x0FCA }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
{ 0x04A3, 0x0400 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
{ 0x04A4, 0x00D8 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
{ 0x04A5, 0x1EB5 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
{ 0x04A6, 0xF145 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
{ 0x04A7, 0x0B75 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
{ 0x04A8, 0x01C5 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
{ 0x04A9, 0x1C58 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
{ 0x04AA, 0xF373 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
{ 0x04AB, 0x0A54 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
{ 0x04AC, 0x0558 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
{ 0x04AD, 0x168E }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
{ 0x04AE, 0xF829 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
{ 0x04AF, 0x07AD }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
{ 0x04B0, 0x1103 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
{ 0x04B1, 0x0564 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
{ 0x04B2, 0x0559 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
{ 0x04B3, 0x4000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
{ 0x04B4, 0x0000 }, /* R1204 - AIF1 DAC2 EQ Band 1 C */
{ 0x0500, 0x00C0 }, /* R1280 - AIF2 ADC Left Volume */
{ 0x0501, 0x00C0 }, /* R1281 - AIF2 ADC Right Volume */
{ 0x0502, 0x00C0 }, /* R1282 - AIF2 DAC Left Volume */
{ 0x0503, 0x00C0 }, /* R1283 - AIF2 DAC Right Volume */
{ 0x0510, 0x0000 }, /* R1296 - AIF2 ADC Filters */
{ 0x0520, 0x0200 }, /* R1312 - AIF2 DAC Filters (1) */
{ 0x0521, 0x0010 }, /* R1313 - AIF2 DAC Filters (2) */
{ 0x0530, 0x0068 }, /* R1328 - AIF2 DAC Noise Gate */
{ 0x0540, 0x0098 }, /* R1344 - AIF2 DRC (1) */
{ 0x0541, 0x0845 }, /* R1345 - AIF2 DRC (2) */
{ 0x0542, 0x0000 }, /* R1346 - AIF2 DRC (3) */
{ 0x0543, 0x0000 }, /* R1347 - AIF2 DRC (4) */
{ 0x0544, 0x0000 }, /* R1348 - AIF2 DRC (5) */
{ 0x0580, 0x6318 }, /* R1408 - AIF2 EQ Gains (1) */
{ 0x0581, 0x6300 }, /* R1409 - AIF2 EQ Gains (2) */
{ 0x0582, 0x0FCA }, /* R1410 - AIF2 EQ Band 1 A */
{ 0x0583, 0x0400 }, /* R1411 - AIF2 EQ Band 1 B */
{ 0x0584, 0x00D8 }, /* R1412 - AIF2 EQ Band 1 PG */
{ 0x0585, 0x1EB5 }, /* R1413 - AIF2 EQ Band 2 A */
{ 0x0586, 0xF145 }, /* R1414 - AIF2 EQ Band 2 B */
{ 0x0587, 0x0B75 }, /* R1415 - AIF2 EQ Band 2 C */
{ 0x0588, 0x01C5 }, /* R1416 - AIF2 EQ Band 2 PG */
{ 0x0589, 0x1C58 }, /* R1417 - AIF2 EQ Band 3 A */
{ 0x058A, 0xF373 }, /* R1418 - AIF2 EQ Band 3 B */
{ 0x058B, 0x0A54 }, /* R1419 - AIF2 EQ Band 3 C */
{ 0x058C, 0x0558 }, /* R1420 - AIF2 EQ Band 3 PG */
{ 0x058D, 0x168E }, /* R1421 - AIF2 EQ Band 4 A */
{ 0x058E, 0xF829 }, /* R1422 - AIF2 EQ Band 4 B */
{ 0x058F, 0x07AD }, /* R1423 - AIF2 EQ Band 4 C */
{ 0x0590, 0x1103 }, /* R1424 - AIF2 EQ Band 4 PG */
{ 0x0591, 0x0564 }, /* R1425 - AIF2 EQ Band 5 A */
{ 0x0592, 0x0559 }, /* R1426 - AIF2 EQ Band 5 B */
{ 0x0593, 0x4000 }, /* R1427 - AIF2 EQ Band 5 PG */
{ 0x0594, 0x0000 }, /* R1428 - AIF2 EQ Band 1 C */
{ 0x0600, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */
{ 0x0601, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */
{ 0x0602, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */
{ 0x0603, 0x0000 }, /* R1539 - AIF2ADC Mixer Volumes */
{ 0x0604, 0x0000 }, /* R1540 - AIF2ADC Left Mixer Routing */
{ 0x0605, 0x0000 }, /* R1541 - AIF2ADC Right Mixer Routing */
{ 0x0606, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
{ 0x0607, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
{ 0x0608, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
{ 0x0609, 0x0000 }, /* R1545 - AIF1 ADC2 Right Mixer Routing */
{ 0x0610, 0x02C0 }, /* R1552 - DAC1 Left Volume */
{ 0x0611, 0x02C0 }, /* R1553 - DAC1 Right Volume */
{ 0x0612, 0x02C0 }, /* R1554 - AIF2TX Left Volume */
{ 0x0613, 0x02C0 }, /* R1555 - AIF2TX Right Volume */
{ 0x0614, 0x0000 }, /* R1556 - DAC Softmute */
{ 0x0620, 0x0002 }, /* R1568 - Oversampling */
{ 0x0621, 0x0000 }, /* R1569 - Sidetone */
{ 0x0700, 0x8100 }, /* R1792 - GPIO 1 */
{ 0x0701, 0xA101 }, /* R1793 - Pull Control (MCLK2) */
{ 0x0702, 0xA101 }, /* R1794 - Pull Control (BCLK2) */
{ 0x0703, 0xA101 }, /* R1795 - Pull Control (DACLRCLK2) */
{ 0x0704, 0xA101 }, /* R1796 - Pull Control (DACDAT2) */
{ 0x0707, 0xA101 }, /* R1799 - GPIO 8 */
{ 0x0708, 0xA101 }, /* R1800 - GPIO 9 */
{ 0x0709, 0xA101 }, /* R1801 - GPIO 10 */
{ 0x070A, 0xA101 }, /* R1802 - GPIO 11 */
{ 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */
{ 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */
{ 0x0732, 0x0000 }, /* R1842 - Interrupt Raw Status 2 */
{ 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */
{ 0x0739, 0xDFEF }, /* R1849 - Interrupt Status 2 Mask */
{ 0x0740, 0x0000 }, /* R1856 - Interrupt Control */
{ 0x0748, 0x003F }, /* R1864 - IRQ Debounce */
};
static const struct reg_default wm8994_defaults[] = {
{ 0x0001, 0x0000 }, /* R1 - Power Management (1) */
{ 0x0002, 0x6000 }, /* R2 - Power Management (2) */
{ 0x0003, 0x0000 }, /* R3 - Power Management (3) */
{ 0x0004, 0x0000 }, /* R4 - Power Management (4) */
{ 0x0005, 0x0000 }, /* R5 - Power Management (5) */
{ 0x0006, 0x0000 }, /* R6 - Power Management (6) */
{ 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
{ 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
{ 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
{ 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
{ 0x001B, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
{ 0x001C, 0x006D }, /* R28 - Left Output Volume */
{ 0x001D, 0x006D }, /* R29 - Right Output Volume */
{ 0x001E, 0x0066 }, /* R30 - Line Outputs Volume */
{ 0x001F, 0x0020 }, /* R31 - HPOUT2 Volume */
{ 0x0020, 0x0079 }, /* R32 - Left OPGA Volume */
{ 0x0021, 0x0079 }, /* R33 - Right OPGA Volume */
{ 0x0022, 0x0003 }, /* R34 - SPKMIXL Attenuation */
{ 0x0023, 0x0003 }, /* R35 - SPKMIXR Attenuation */
{ 0x0024, 0x0011 }, /* R36 - SPKOUT Mixers */
{ 0x0025, 0x0140 }, /* R37 - ClassD */
{ 0x0026, 0x0079 }, /* R38 - Speaker Volume Left */
{ 0x0027, 0x0079 }, /* R39 - Speaker Volume Right */
{ 0x0028, 0x0000 }, /* R40 - Input Mixer (2) */
{ 0x0029, 0x0000 }, /* R41 - Input Mixer (3) */
{ 0x002A, 0x0000 }, /* R42 - Input Mixer (4) */
{ 0x002B, 0x0000 }, /* R43 - Input Mixer (5) */
{ 0x002C, 0x0000 }, /* R44 - Input Mixer (6) */
{ 0x002D, 0x0000 }, /* R45 - Output Mixer (1) */
{ 0x002E, 0x0000 }, /* R46 - Output Mixer (2) */
{ 0x002F, 0x0000 }, /* R47 - Output Mixer (3) */
{ 0x0030, 0x0000 }, /* R48 - Output Mixer (4) */
{ 0x0031, 0x0000 }, /* R49 - Output Mixer (5) */
{ 0x0032, 0x0000 }, /* R50 - Output Mixer (6) */
{ 0x0033, 0x0000 }, /* R51 - HPOUT2 Mixer */
{ 0x0034, 0x0000 }, /* R52 - Line Mixer (1) */
{ 0x0035, 0x0000 }, /* R53 - Line Mixer (2) */
{ 0x0036, 0x0000 }, /* R54 - Speaker Mixer */
{ 0x0037, 0x0000 }, /* R55 - Additional Control */
{ 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */
{ 0x0039, 0x0000 }, /* R57 - AntiPOP (2) */
{ 0x003A, 0x0000 }, /* R58 - MICBIAS */
{ 0x003B, 0x000D }, /* R59 - LDO 1 */
{ 0x003C, 0x0003 }, /* R60 - LDO 2 */
{ 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */
{ 0x0051, 0x0004 }, /* R81 - Class W (1) */
{ 0x0055, 0x054A }, /* R85 - DC Servo (2) */
{ 0x0057, 0x0000 }, /* R87 - DC Servo (4) */
{ 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */
{ 0x0101, 0x8004 }, /* R257 - Control Interface */
{ 0x0110, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */
{ 0x0111, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
{ 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */
{ 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */
{ 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */
{ 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */
{ 0x0208, 0x0000 }, /* R520 - Clocking (1) */
{ 0x0209, 0x0000 }, /* R521 - Clocking (2) */
{ 0x0210, 0x0083 }, /* R528 - AIF1 Rate */
{ 0x0211, 0x0083 }, /* R529 - AIF2 Rate */
{ 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */
{ 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */
{ 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */
{ 0x0223, 0x0000 }, /* R547 - FLL1 Control (4) */
{ 0x0224, 0x0C80 }, /* R548 - FLL1 Control (5) */
{ 0x0240, 0x0000 }, /* R576 - FLL2 Control (1) */
{ 0x0241, 0x0000 }, /* R577 - FLL2 Control (2) */
{ 0x0242, 0x0000 }, /* R578 - FLL2 Control (3) */
{ 0x0243, 0x0000 }, /* R579 - FLL2 Control (4) */
{ 0x0244, 0x0C80 }, /* R580 - FLL2 Control (5) */
{ 0x0300, 0x4050 }, /* R768 - AIF1 Control (1) */
{ 0x0301, 0x4000 }, /* R769 - AIF1 Control (2) */
{ 0x0302, 0x0000 }, /* R770 - AIF1 Master/Slave */
{ 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */
{ 0x0304, 0x0040 }, /* R772 - AIF1ADC LRCLK */
{ 0x0305, 0x0040 }, /* R773 - AIF1DAC LRCLK */
{ 0x0306, 0x0004 }, /* R774 - AIF1DAC Data */
{ 0x0307, 0x0100 }, /* R775 - AIF1ADC Data */
{ 0x0310, 0x4050 }, /* R784 - AIF2 Control (1) */
{ 0x0311, 0x4000 }, /* R785 - AIF2 Control (2) */
{ 0x0312, 0x0000 }, /* R786 - AIF2 Master/Slave */
{ 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */
{ 0x0314, 0x0040 }, /* R788 - AIF2ADC LRCLK */
{ 0x0315, 0x0040 }, /* R789 - AIF2DAC LRCLK */
{ 0x0316, 0x0000 }, /* R790 - AIF2DAC Data */
{ 0x0317, 0x0000 }, /* R791 - AIF2ADC Data */
{ 0x0400, 0x00C0 }, /* R1024 - AIF1 ADC1 Left Volume */
{ 0x0401, 0x00C0 }, /* R1025 - AIF1 ADC1 Right Volume */
{ 0x0402, 0x00C0 }, /* R1026 - AIF1 DAC1 Left Volume */
{ 0x0403, 0x00C0 }, /* R1027 - AIF1 DAC1 Right Volume */
{ 0x0404, 0x00C0 }, /* R1028 - AIF1 ADC2 Left Volume */
{ 0x0405, 0x00C0 }, /* R1029 - AIF1 ADC2 Right Volume */
{ 0x0406, 0x00C0 }, /* R1030 - AIF1 DAC2 Left Volume */
{ 0x0407, 0x00C0 }, /* R1031 - AIF1 DAC2 Right Volume */
{ 0x0410, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */
{ 0x0411, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */
{ 0x0420, 0x0200 }, /* R1056 - AIF1 DAC1 Filters (1) */
{ 0x0421, 0x0010 }, /* R1057 - AIF1 DAC1 Filters (2) */
{ 0x0422, 0x0200 }, /* R1058 - AIF1 DAC2 Filters (1) */
{ 0x0423, 0x0010 }, /* R1059 - AIF1 DAC2 Filters (2) */
{ 0x0440, 0x0098 }, /* R1088 - AIF1 DRC1 (1) */
{ 0x0441, 0x0845 }, /* R1089 - AIF1 DRC1 (2) */
{ 0x0442, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */
{ 0x0443, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */
{ 0x0444, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */
{ 0x0450, 0x0098 }, /* R1104 - AIF1 DRC2 (1) */
{ 0x0451, 0x0845 }, /* R1105 - AIF1 DRC2 (2) */
{ 0x0452, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */
{ 0x0453, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */
{ 0x0454, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */
{ 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
{ 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
{ 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
{ 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
{ 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
{ 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
{ 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
{ 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
{ 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
{ 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
{ 0x048A, 0xF373 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
{ 0x048B, 0x0A54 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
{ 0x048C, 0x0558 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
{ 0x048D, 0x168E }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
{ 0x048E, 0xF829 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
{ 0x048F, 0x07AD }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
{ 0x0490, 0x1103 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
{ 0x0491, 0x0564 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
{ 0x0492, 0x0559 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
{ 0x0493, 0x4000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
{ 0x04A0, 0x6318 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
{ 0x04A1, 0x6300 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
{ 0x04A2, 0x0FCA }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
{ 0x04A3, 0x0400 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
{ 0x04A4, 0x00D8 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
{ 0x04A5, 0x1EB5 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
{ 0x04A6, 0xF145 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
{ 0x04A7, 0x0B75 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
{ 0x04A8, 0x01C5 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
{ 0x04A9, 0x1C58 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
{ 0x04AA, 0xF373 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
{ 0x04AB, 0x0A54 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
{ 0x04AC, 0x0558 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
{ 0x04AD, 0x168E }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
{ 0x04AE, 0xF829 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
{ 0x04AF, 0x07AD }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
{ 0x04B0, 0x1103 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
{ 0x04B1, 0x0564 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
{ 0x04B2, 0x0559 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
{ 0x04B3, 0x4000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
{ 0x0500, 0x00C0 }, /* R1280 - AIF2 ADC Left Volume */
{ 0x0501, 0x00C0 }, /* R1281 - AIF2 ADC Right Volume */
{ 0x0502, 0x00C0 }, /* R1282 - AIF2 DAC Left Volume */
{ 0x0503, 0x00C0 }, /* R1283 - AIF2 DAC Right Volume */
{ 0x0510, 0x0000 }, /* R1296 - AIF2 ADC Filters */
{ 0x0520, 0x0200 }, /* R1312 - AIF2 DAC Filters (1) */
{ 0x0521, 0x0010 }, /* R1313 - AIF2 DAC Filters (2) */
{ 0x0540, 0x0098 }, /* R1344 - AIF2 DRC (1) */
{ 0x0541, 0x0845 }, /* R1345 - AIF2 DRC (2) */
{ 0x0542, 0x0000 }, /* R1346 - AIF2 DRC (3) */
{ 0x0543, 0x0000 }, /* R1347 - AIF2 DRC (4) */
{ 0x0544, 0x0000 }, /* R1348 - AIF2 DRC (5) */
{ 0x0580, 0x6318 }, /* R1408 - AIF2 EQ Gains (1) */
{ 0x0581, 0x6300 }, /* R1409 - AIF2 EQ Gains (2) */
{ 0x0582, 0x0FCA }, /* R1410 - AIF2 EQ Band 1 A */
{ 0x0583, 0x0400 }, /* R1411 - AIF2 EQ Band 1 B */
{ 0x0584, 0x00D8 }, /* R1412 - AIF2 EQ Band 1 PG */
{ 0x0585, 0x1EB5 }, /* R1413 - AIF2 EQ Band 2 A */
{ 0x0586, 0xF145 }, /* R1414 - AIF2 EQ Band 2 B */
{ 0x0587, 0x0B75 }, /* R1415 - AIF2 EQ Band 2 C */
{ 0x0588, 0x01C5 }, /* R1416 - AIF2 EQ Band 2 PG */
{ 0x0589, 0x1C58 }, /* R1417 - AIF2 EQ Band 3 A */
{ 0x058A, 0xF373 }, /* R1418 - AIF2 EQ Band 3 B */
{ 0x058B, 0x0A54 }, /* R1419 - AIF2 EQ Band 3 C */
{ 0x058C, 0x0558 }, /* R1420 - AIF2 EQ Band 3 PG */
{ 0x058D, 0x168E }, /* R1421 - AIF2 EQ Band 4 A */
{ 0x058E, 0xF829 }, /* R1422 - AIF2 EQ Band 4 B */
{ 0x058F, 0x07AD }, /* R1423 - AIF2 EQ Band 4 C */
{ 0x0590, 0x1103 }, /* R1424 - AIF2 EQ Band 4 PG */
{ 0x0591, 0x0564 }, /* R1425 - AIF2 EQ Band 5 A */
{ 0x0592, 0x0559 }, /* R1426 - AIF2 EQ Band 5 B */
{ 0x0593, 0x4000 }, /* R1427 - AIF2 EQ Band 5 PG */
{ 0x0600, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */
{ 0x0601, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */
{ 0x0602, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */
{ 0x0603, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */
{ 0x0604, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */
{ 0x0605, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */
{ 0x0606, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
{ 0x0607, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
{ 0x0608, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
{ 0x0609, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
{ 0x0610, 0x02C0 }, /* R1552 - DAC1 Left Volume */
{ 0x0611, 0x02C0 }, /* R1553 - DAC1 Right Volume */
{ 0x0612, 0x02C0 }, /* R1554 - DAC2 Left Volume */
{ 0x0613, 0x02C0 }, /* R1555 - DAC2 Right Volume */
{ 0x0614, 0x0000 }, /* R1556 - DAC Softmute */
{ 0x0620, 0x0002 }, /* R1568 - Oversampling */
{ 0x0621, 0x0000 }, /* R1569 - Sidetone */
{ 0x0700, 0x8100 }, /* R1792 - GPIO 1 */
{ 0x0701, 0xA101 }, /* R1793 - GPIO 2 */
{ 0x0702, 0xA101 }, /* R1794 - GPIO 3 */
{ 0x0703, 0xA101 }, /* R1795 - GPIO 4 */
{ 0x0704, 0xA101 }, /* R1796 - GPIO 5 */
{ 0x0705, 0xA101 }, /* R1797 - GPIO 6 */
{ 0x0706, 0xA101 }, /* R1798 - GPIO 7 */
{ 0x0707, 0xA101 }, /* R1799 - GPIO 8 */
{ 0x0708, 0xA101 }, /* R1800 - GPIO 9 */
{ 0x0709, 0xA101 }, /* R1801 - GPIO 10 */
{ 0x070A, 0xA101 }, /* R1802 - GPIO 11 */
{ 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */
{ 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */
{ 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */
{ 0x0739, 0xFFFF }, /* R1849 - Interrupt Status 2 Mask */
{ 0x0740, 0x0000 }, /* R1856 - Interrupt Control */
{ 0x0748, 0x003F }, /* R1864 - IRQ Debounce */
};
static const struct reg_default wm8958_defaults[] = {
{ 0x0001, 0x0000 }, /* R1 - Power Management (1) */
{ 0x0002, 0x6000 }, /* R2 - Power Management (2) */
{ 0x0003, 0x0000 }, /* R3 - Power Management (3) */
{ 0x0004, 0x0000 }, /* R4 - Power Management (4) */
{ 0x0005, 0x0000 }, /* R5 - Power Management (5) */
{ 0x0006, 0x0000 }, /* R6 - Power Management (6) */
{ 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
{ 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
{ 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
{ 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
{ 0x001B, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
{ 0x001C, 0x006D }, /* R28 - Left Output Volume */
{ 0x001D, 0x006D }, /* R29 - Right Output Volume */
{ 0x001E, 0x0066 }, /* R30 - Line Outputs Volume */
{ 0x001F, 0x0020 }, /* R31 - HPOUT2 Volume */
{ 0x0020, 0x0079 }, /* R32 - Left OPGA Volume */
{ 0x0021, 0x0079 }, /* R33 - Right OPGA Volume */
{ 0x0022, 0x0003 }, /* R34 - SPKMIXL Attenuation */
{ 0x0023, 0x0003 }, /* R35 - SPKMIXR Attenuation */
{ 0x0024, 0x0011 }, /* R36 - SPKOUT Mixers */
{ 0x0025, 0x0140 }, /* R37 - ClassD */
{ 0x0026, 0x0079 }, /* R38 - Speaker Volume Left */
{ 0x0027, 0x0079 }, /* R39 - Speaker Volume Right */
{ 0x0028, 0x0000 }, /* R40 - Input Mixer (2) */
{ 0x0029, 0x0000 }, /* R41 - Input Mixer (3) */
{ 0x002A, 0x0000 }, /* R42 - Input Mixer (4) */
{ 0x002B, 0x0000 }, /* R43 - Input Mixer (5) */
{ 0x002C, 0x0000 }, /* R44 - Input Mixer (6) */
{ 0x002D, 0x0000 }, /* R45 - Output Mixer (1) */
{ 0x002E, 0x0000 }, /* R46 - Output Mixer (2) */
{ 0x002F, 0x0000 }, /* R47 - Output Mixer (3) */
{ 0x0030, 0x0000 }, /* R48 - Output Mixer (4) */
{ 0x0031, 0x0000 }, /* R49 - Output Mixer (5) */
{ 0x0032, 0x0000 }, /* R50 - Output Mixer (6) */
{ 0x0033, 0x0000 }, /* R51 - HPOUT2 Mixer */
{ 0x0034, 0x0000 }, /* R52 - Line Mixer (1) */
{ 0x0035, 0x0000 }, /* R53 - Line Mixer (2) */
{ 0x0036, 0x0000 }, /* R54 - Speaker Mixer */
{ 0x0037, 0x0000 }, /* R55 - Additional Control */
{ 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */
{ 0x0039, 0x0180 }, /* R57 - AntiPOP (2) */
{ 0x003B, 0x000D }, /* R59 - LDO 1 */
{ 0x003C, 0x0005 }, /* R60 - LDO 2 */
{ 0x003D, 0x0039 }, /* R61 - MICBIAS1 */
{ 0x003E, 0x0039 }, /* R62 - MICBIAS2 */
{ 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */
{ 0x004D, 0xAB19 }, /* R77 - Charge Pump (2) */
{ 0x0051, 0x0004 }, /* R81 - Class W (1) */
{ 0x0055, 0x054A }, /* R85 - DC Servo (2) */
{ 0x0057, 0x0000 }, /* R87 - DC Servo (4) */
{ 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */
{ 0x00C5, 0x0000 }, /* R197 - Class D Test (5) */
{ 0x00D0, 0x5600 }, /* R208 - Mic Detect 1 */
{ 0x00D1, 0x007F }, /* R209 - Mic Detect 2 */
{ 0x0101, 0x8004 }, /* R257 - Control Interface */
{ 0x0110, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */
{ 0x0111, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
{ 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */
{ 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */
{ 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */
{ 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */
{ 0x0208, 0x0000 }, /* R520 - Clocking (1) */
{ 0x0209, 0x0000 }, /* R521 - Clocking (2) */
{ 0x0210, 0x0083 }, /* R528 - AIF1 Rate */
{ 0x0211, 0x0083 }, /* R529 - AIF2 Rate */
{ 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */
{ 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */
{ 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */
{ 0x0223, 0x0000 }, /* R547 - FLL1 Control (4) */
{ 0x0224, 0x0C80 }, /* R548 - FLL1 Control (5) */
{ 0x0226, 0x0000 }, /* R550 - FLL1 EFS 1 */
{ 0x0227, 0x0006 }, /* R551 - FLL1 EFS 2 */
{ 0x0240, 0x0000 }, /* R576 - FLL2Control (1) */
{ 0x0241, 0x0000 }, /* R577 - FLL2Control (2) */
{ 0x0242, 0x0000 }, /* R578 - FLL2Control (3) */
{ 0x0243, 0x0000 }, /* R579 - FLL2 Control (4) */
{ 0x0244, 0x0C80 }, /* R580 - FLL2Control (5) */
{ 0x0246, 0x0000 }, /* R582 - FLL2 EFS 1 */
{ 0x0247, 0x0006 }, /* R583 - FLL2 EFS 2 */
{ 0x0300, 0x4050 }, /* R768 - AIF1 Control (1) */
{ 0x0301, 0x4000 }, /* R769 - AIF1 Control (2) */
{ 0x0302, 0x0000 }, /* R770 - AIF1 Master/Slave */
{ 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */
{ 0x0304, 0x0040 }, /* R772 - AIF1ADC LRCLK */
{ 0x0305, 0x0040 }, /* R773 - AIF1DAC LRCLK */
{ 0x0306, 0x0004 }, /* R774 - AIF1DAC Data */
{ 0x0307, 0x0100 }, /* R775 - AIF1ADC Data */
{ 0x0310, 0x4053 }, /* R784 - AIF2 Control (1) */
{ 0x0311, 0x4000 }, /* R785 - AIF2 Control (2) */
{ 0x0312, 0x0000 }, /* R786 - AIF2 Master/Slave */
{ 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */
{ 0x0314, 0x0040 }, /* R788 - AIF2ADC LRCLK */
{ 0x0315, 0x0040 }, /* R789 - AIF2DAC LRCLK */
{ 0x0316, 0x0000 }, /* R790 - AIF2DAC Data */
{ 0x0317, 0x0000 }, /* R791 - AIF2ADC Data */
{ 0x0320, 0x0040 }, /* R800 - AIF3 Control (1) */
{ 0x0321, 0x0000 }, /* R801 - AIF3 Control (2) */
{ 0x0322, 0x0000 }, /* R802 - AIF3DAC Data */
{ 0x0323, 0x0000 }, /* R803 - AIF3ADC Data */
{ 0x0400, 0x00C0 }, /* R1024 - AIF1 ADC1 Left Volume */
{ 0x0401, 0x00C0 }, /* R1025 - AIF1 ADC1 Right Volume */
{ 0x0402, 0x00C0 }, /* R1026 - AIF1 DAC1 Left Volume */
{ 0x0403, 0x00C0 }, /* R1027 - AIF1 DAC1 Right Volume */
{ 0x0404, 0x00C0 }, /* R1028 - AIF1 ADC2 Left Volume */
{ 0x0405, 0x00C0 }, /* R1029 - AIF1 ADC2 Right Volume */
{ 0x0406, 0x00C0 }, /* R1030 - AIF1 DAC2 Left Volume */
{ 0x0407, 0x00C0 }, /* R1031 - AIF1 DAC2 Right Volume */
{ 0x0410, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */
{ 0x0411, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */
{ 0x0420, 0x0200 }, /* R1056 - AIF1 DAC1 Filters (1) */
{ 0x0421, 0x0010 }, /* R1057 - AIF1 DAC1 Filters (2) */
{ 0x0422, 0x0200 }, /* R1058 - AIF1 DAC2 Filters (1) */
{ 0x0423, 0x0010 }, /* R1059 - AIF1 DAC2 Filters (2) */
{ 0x0430, 0x0068 }, /* R1072 - AIF1 DAC1 Noise Gate */
{ 0x0431, 0x0068 }, /* R1073 - AIF1 DAC2 Noise Gate */
{ 0x0440, 0x0098 }, /* R1088 - AIF1 DRC1 (1) */
{ 0x0441, 0x0845 }, /* R1089 - AIF1 DRC1 (2) */
{ 0x0442, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */
{ 0x0443, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */
{ 0x0444, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */
{ 0x0450, 0x0098 }, /* R1104 - AIF1 DRC2 (1) */
{ 0x0451, 0x0845 }, /* R1105 - AIF1 DRC2 (2) */
{ 0x0452, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */
{ 0x0453, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */
{ 0x0454, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */
{ 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
{ 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
{ 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
{ 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
{ 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
{ 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
{ 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
{ 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
{ 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
{ 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
{ 0x048A, 0xF373 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
{ 0x048B, 0x0A54 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
{ 0x048C, 0x0558 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
{ 0x048D, 0x168E }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
{ 0x048E, 0xF829 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
{ 0x048F, 0x07AD }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
{ 0x0490, 0x1103 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
{ 0x0491, 0x0564 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
{ 0x0492, 0x0559 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
{ 0x0493, 0x4000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
{ 0x0494, 0x0000 }, /* R1172 - AIF1 DAC1 EQ Band 1 C */
{ 0x04A0, 0x6318 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
{ 0x04A1, 0x6300 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
{ 0x04A2, 0x0FCA }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
{ 0x04A3, 0x0400 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
{ 0x04A4, 0x00D8 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
{ 0x04A5, 0x1EB5 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
{ 0x04A6, 0xF145 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
{ 0x04A7, 0x0B75 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
{ 0x04A8, 0x01C5 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
{ 0x04A9, 0x1C58 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
{ 0x04AA, 0xF373 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
{ 0x04AB, 0x0A54 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
{ 0x04AC, 0x0558 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
{ 0x04AD, 0x168E }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
{ 0x04AE, 0xF829 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
{ 0x04AF, 0x07AD }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
{ 0x04B0, 0x1103 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
{ 0x04B1, 0x0564 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
{ 0x04B2, 0x0559 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
{ 0x04B3, 0x4000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
{ 0x04B4, 0x0000 }, /* R1204 - AIF1 DAC2EQ Band 1 C */
{ 0x0500, 0x00C0 }, /* R1280 - AIF2 ADC Left Volume */
{ 0x0501, 0x00C0 }, /* R1281 - AIF2 ADC Right Volume */
{ 0x0502, 0x00C0 }, /* R1282 - AIF2 DAC Left Volume */
{ 0x0503, 0x00C0 }, /* R1283 - AIF2 DAC Right Volume */
{ 0x0510, 0x0000 }, /* R1296 - AIF2 ADC Filters */
{ 0x0520, 0x0200 }, /* R1312 - AIF2 DAC Filters (1) */
{ 0x0521, 0x0010 }, /* R1313 - AIF2 DAC Filters (2) */
{ 0x0530, 0x0068 }, /* R1328 - AIF2 DAC Noise Gate */
{ 0x0540, 0x0098 }, /* R1344 - AIF2 DRC (1) */
{ 0x0541, 0x0845 }, /* R1345 - AIF2 DRC (2) */
{ 0x0542, 0x0000 }, /* R1346 - AIF2 DRC (3) */
{ 0x0543, 0x0000 }, /* R1347 - AIF2 DRC (4) */
{ 0x0544, 0x0000 }, /* R1348 - AIF2 DRC (5) */
{ 0x0580, 0x6318 }, /* R1408 - AIF2 EQ Gains (1) */
{ 0x0581, 0x6300 }, /* R1409 - AIF2 EQ Gains (2) */
{ 0x0582, 0x0FCA }, /* R1410 - AIF2 EQ Band 1 A */
{ 0x0583, 0x0400 }, /* R1411 - AIF2 EQ Band 1 B */
{ 0x0584, 0x00D8 }, /* R1412 - AIF2 EQ Band 1 PG */
{ 0x0585, 0x1EB5 }, /* R1413 - AIF2 EQ Band 2 A */
{ 0x0586, 0xF145 }, /* R1414 - AIF2 EQ Band 2 B */
{ 0x0587, 0x0B75 }, /* R1415 - AIF2 EQ Band 2 C */
{ 0x0588, 0x01C5 }, /* R1416 - AIF2 EQ Band 2 PG */
{ 0x0589, 0x1C58 }, /* R1417 - AIF2 EQ Band 3 A */
{ 0x058A, 0xF373 }, /* R1418 - AIF2 EQ Band 3 B */
{ 0x058B, 0x0A54 }, /* R1419 - AIF2 EQ Band 3 C */
{ 0x058C, 0x0558 }, /* R1420 - AIF2 EQ Band 3 PG */
{ 0x058D, 0x168E }, /* R1421 - AIF2 EQ Band 4 A */
{ 0x058E, 0xF829 }, /* R1422 - AIF2 EQ Band 4 B */
{ 0x058F, 0x07AD }, /* R1423 - AIF2 EQ Band 4 C */
{ 0x0590, 0x1103 }, /* R1424 - AIF2 EQ Band 4 PG */
{ 0x0591, 0x0564 }, /* R1425 - AIF2 EQ Band 5 A */
{ 0x0592, 0x0559 }, /* R1426 - AIF2 EQ Band 5 B */
{ 0x0593, 0x4000 }, /* R1427 - AIF2 EQ Band 5 PG */
{ 0x0594, 0x0000 }, /* R1428 - AIF2 EQ Band 1 C */
{ 0x0600, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */
{ 0x0601, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */
{ 0x0602, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */
{ 0x0603, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */
{ 0x0604, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */
{ 0x0605, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */
{ 0x0606, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
{ 0x0607, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
{ 0x0608, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
{ 0x0609, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
{ 0x0610, 0x02C0 }, /* R1552 - DAC1 Left Volume */
{ 0x0611, 0x02C0 }, /* R1553 - DAC1 Right Volume */
{ 0x0612, 0x02C0 }, /* R1554 - DAC2 Left Volume */
{ 0x0613, 0x02C0 }, /* R1555 - DAC2 Right Volume */
{ 0x0614, 0x0000 }, /* R1556 - DAC Softmute */
{ 0x0620, 0x0002 }, /* R1568 - Oversampling */
{ 0x0621, 0x0000 }, /* R1569 - Sidetone */
{ 0x0700, 0x8100 }, /* R1792 - GPIO 1 */
{ 0x0701, 0xA101 }, /* R1793 - Pull Control (MCLK2) */
{ 0x0702, 0xA101 }, /* R1794 - Pull Control (BCLK2) */
{ 0x0703, 0xA101 }, /* R1795 - Pull Control (DACLRCLK2) */
{ 0x0704, 0xA101 }, /* R1796 - Pull Control (DACDAT2) */
{ 0x0705, 0xA101 }, /* R1797 - GPIO 6 */
{ 0x0707, 0xA101 }, /* R1799 - GPIO 8 */
{ 0x0708, 0xA101 }, /* R1800 - GPIO 9 */
{ 0x0709, 0xA101 }, /* R1801 - GPIO 10 */
{ 0x070A, 0xA101 }, /* R1802 - GPIO 11 */
{ 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */
{ 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */
{ 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */
{ 0x0739, 0xFFEF }, /* R1849 - Interrupt Status 2 Mask */
{ 0x0740, 0x0000 }, /* R1856 - Interrupt Control */
{ 0x0748, 0x003F }, /* R1864 - IRQ Debounce */
{ 0x0900, 0x1C00 }, /* R2304 - DSP2_Program */
{ 0x0901, 0x0000 }, /* R2305 - DSP2_Config */
{ 0x0A0D, 0x0000 }, /* R2573 - DSP2_ExecControl */
{ 0x2400, 0x003F }, /* R9216 - MBC Band 1 K (1) */
{ 0x2401, 0x8BD8 }, /* R9217 - MBC Band 1 K (2) */
{ 0x2402, 0x0032 }, /* R9218 - MBC Band 1 N1 (1) */
{ 0x2403, 0xF52D }, /* R9219 - MBC Band 1 N1 (2) */
{ 0x2404, 0x0065 }, /* R9220 - MBC Band 1 N2 (1) */
{ 0x2405, 0xAC8C }, /* R9221 - MBC Band 1 N2 (2) */
{ 0x2406, 0x006B }, /* R9222 - MBC Band 1 N3 (1) */
{ 0x2407, 0xE087 }, /* R9223 - MBC Band 1 N3 (2) */
{ 0x2408, 0x0072 }, /* R9224 - MBC Band 1 N4 (1) */
{ 0x2409, 0x1483 }, /* R9225 - MBC Band 1 N4 (2) */
{ 0x240A, 0x0072 }, /* R9226 - MBC Band 1 N5 (1) */
{ 0x240B, 0x1483 }, /* R9227 - MBC Band 1 N5 (2) */
{ 0x240C, 0x0043 }, /* R9228 - MBC Band 1 X1 (1) */
{ 0x240D, 0x3525 }, /* R9229 - MBC Band 1 X1 (2) */
{ 0x240E, 0x0006 }, /* R9230 - MBC Band 1 X2 (1) */
{ 0x240F, 0x6A4A }, /* R9231 - MBC Band 1 X2 (2) */
{ 0x2410, 0x0043 }, /* R9232 - MBC Band 1 X3 (1) */
{ 0x2411, 0x6079 }, /* R9233 - MBC Band 1 X3 (2) */
{ 0x2412, 0x000C }, /* R9234 - MBC Band 1 Attack (1) */
{ 0x2413, 0xCCCD }, /* R9235 - MBC Band 1 Attack (2) */
{ 0x2414, 0x0000 }, /* R9236 - MBC Band 1 Decay (1) */
{ 0x2415, 0x0800 }, /* R9237 - MBC Band 1 Decay (2) */
{ 0x2416, 0x003F }, /* R9238 - MBC Band 2 K (1) */
{ 0x2417, 0x8BD8 }, /* R9239 - MBC Band 2 K (2) */
{ 0x2418, 0x0032 }, /* R9240 - MBC Band 2 N1 (1) */
{ 0x2419, 0xF52D }, /* R9241 - MBC Band 2 N1 (2) */
{ 0x241A, 0x0065 }, /* R9242 - MBC Band 2 N2 (1) */
{ 0x241B, 0xAC8C }, /* R9243 - MBC Band 2 N2 (2) */
{ 0x241C, 0x006B }, /* R9244 - MBC Band 2 N3 (1) */
{ 0x241D, 0xE087 }, /* R9245 - MBC Band 2 N3 (2) */
{ 0x241E, 0x0072 }, /* R9246 - MBC Band 2 N4 (1) */
{ 0x241F, 0x1483 }, /* R9247 - MBC Band 2 N4 (2) */
{ 0x2420, 0x0072 }, /* R9248 - MBC Band 2 N5 (1) */
{ 0x2421, 0x1483 }, /* R9249 - MBC Band 2 N5 (2) */
{ 0x2422, 0x0043 }, /* R9250 - MBC Band 2 X1 (1) */
{ 0x2423, 0x3525 }, /* R9251 - MBC Band 2 X1 (2) */
{ 0x2424, 0x0006 }, /* R9252 - MBC Band 2 X2 (1) */
{ 0x2425, 0x6A4A }, /* R9253 - MBC Band 2 X2 (2) */
{ 0x2426, 0x0043 }, /* R9254 - MBC Band 2 X3 (1) */
{ 0x2427, 0x6079 }, /* R9255 - MBC Band 2 X3 (2) */
{ 0x2428, 0x000C }, /* R9256 - MBC Band 2 Attack (1) */
{ 0x2429, 0xCCCD }, /* R9257 - MBC Band 2 Attack (2) */
{ 0x242A, 0x0000 }, /* R9258 - MBC Band 2 Decay (1) */
{ 0x242B, 0x0800 }, /* R9259 - MBC Band 2 Decay (2) */
{ 0x242C, 0x005A }, /* R9260 - MBC_B2_PG2 (1) */
{ 0x242D, 0x7EFA }, /* R9261 - MBC_B2_PG2 (2) */
{ 0x242E, 0x005A }, /* R9262 - MBC_B1_PG2 (1) */
{ 0x242F, 0x7EFA }, /* R9263 - MBC_B1_PG2 (2) */
{ 0x2600, 0x00A7 }, /* R9728 - MBC Crossover (1) */
{ 0x2601, 0x0D1C }, /* R9729 - MBC Crossover (2) */
{ 0x2602, 0x0083 }, /* R9730 - MBC HPF (1) */
{ 0x2603, 0x98AD }, /* R9731 - MBC HPF (2) */
{ 0x2606, 0x0008 }, /* R9734 - MBC LPF (1) */
{ 0x2607, 0xE7A2 }, /* R9735 - MBC LPF (2) */
{ 0x260A, 0x0055 }, /* R9738 - MBC RMS Limit (1) */
{ 0x260B, 0x8C4B }, /* R9739 - MBC RMS Limit (2) */
};
static bool wm1811_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8994_SOFTWARE_RESET:
case WM8994_POWER_MANAGEMENT_1:
case WM8994_POWER_MANAGEMENT_2:
case WM8994_POWER_MANAGEMENT_3:
case WM8994_POWER_MANAGEMENT_4:
case WM8994_POWER_MANAGEMENT_5:
case WM8994_POWER_MANAGEMENT_6:
case WM8994_INPUT_MIXER_1:
case WM8994_LEFT_LINE_INPUT_1_2_VOLUME:
case WM8994_LEFT_LINE_INPUT_3_4_VOLUME:
case WM8994_RIGHT_LINE_INPUT_1_2_VOLUME:
case WM8994_RIGHT_LINE_INPUT_3_4_VOLUME:
case WM8994_LEFT_OUTPUT_VOLUME:
case WM8994_RIGHT_OUTPUT_VOLUME:
case WM8994_LINE_OUTPUTS_VOLUME:
case WM8994_HPOUT2_VOLUME:
case WM8994_LEFT_OPGA_VOLUME:
case WM8994_RIGHT_OPGA_VOLUME:
case WM8994_SPKMIXL_ATTENUATION:
case WM8994_SPKMIXR_ATTENUATION:
case WM8994_SPKOUT_MIXERS:
case WM8994_CLASSD:
case WM8994_SPEAKER_VOLUME_LEFT:
case WM8994_SPEAKER_VOLUME_RIGHT:
case WM8994_INPUT_MIXER_2:
case WM8994_INPUT_MIXER_3:
case WM8994_INPUT_MIXER_4:
case WM8994_INPUT_MIXER_5:
case WM8994_INPUT_MIXER_6:
case WM8994_OUTPUT_MIXER_1:
case WM8994_OUTPUT_MIXER_2:
case WM8994_OUTPUT_MIXER_3:
case WM8994_OUTPUT_MIXER_4:
case WM8994_OUTPUT_MIXER_5:
case WM8994_OUTPUT_MIXER_6:
case WM8994_HPOUT2_MIXER:
case WM8994_LINE_MIXER_1:
case WM8994_LINE_MIXER_2:
case WM8994_SPEAKER_MIXER:
case WM8994_ADDITIONAL_CONTROL:
case WM8994_ANTIPOP_1:
case WM8994_ANTIPOP_2:
case WM8994_LDO_1:
case WM8994_LDO_2:
case WM8958_MICBIAS1:
case WM8958_MICBIAS2:
case WM8994_CHARGE_PUMP_1:
case WM8958_CHARGE_PUMP_2:
case WM8994_CLASS_W_1:
case WM8994_DC_SERVO_1:
case WM8994_DC_SERVO_2:
case WM8994_DC_SERVO_READBACK:
case WM8994_DC_SERVO_4:
case WM8994_DC_SERVO_4E:
case WM8994_ANALOGUE_HP_1:
case WM8958_MIC_DETECT_1:
case WM8958_MIC_DETECT_2:
case WM8958_MIC_DETECT_3:
case WM8994_CHIP_REVISION:
case WM8994_CONTROL_INTERFACE:
case WM8994_AIF1_CLOCKING_1:
case WM8994_AIF1_CLOCKING_2:
case WM8994_AIF2_CLOCKING_1:
case WM8994_AIF2_CLOCKING_2:
case WM8994_CLOCKING_1:
case WM8994_CLOCKING_2:
case WM8994_AIF1_RATE:
case WM8994_AIF2_RATE:
case WM8994_RATE_STATUS:
case WM8994_FLL1_CONTROL_1:
case WM8994_FLL1_CONTROL_2:
case WM8994_FLL1_CONTROL_3:
case WM8994_FLL1_CONTROL_4:
case WM8994_FLL1_CONTROL_5:
case WM8958_FLL1_EFS_1:
case WM8958_FLL1_EFS_2:
case WM8994_FLL2_CONTROL_1:
case WM8994_FLL2_CONTROL_2:
case WM8994_FLL2_CONTROL_3:
case WM8994_FLL2_CONTROL_4:
case WM8994_FLL2_CONTROL_5:
case WM8958_FLL2_EFS_1:
case WM8958_FLL2_EFS_2:
case WM8994_AIF1_CONTROL_1:
case WM8994_AIF1_CONTROL_2:
case WM8994_AIF1_MASTER_SLAVE:
case WM8994_AIF1_BCLK:
case WM8994_AIF1ADC_LRCLK:
case WM8994_AIF1DAC_LRCLK:
case WM8994_AIF1DAC_DATA:
case WM8994_AIF1ADC_DATA:
case WM8994_AIF2_CONTROL_1:
case WM8994_AIF2_CONTROL_2:
case WM8994_AIF2_MASTER_SLAVE:
case WM8994_AIF2_BCLK:
case WM8994_AIF2ADC_LRCLK:
case WM8994_AIF2DAC_LRCLK:
case WM8994_AIF2DAC_DATA:
case WM8994_AIF2ADC_DATA:
case WM1811_AIF2TX_CONTROL:
case WM8958_AIF3_CONTROL_1:
case WM8958_AIF3_CONTROL_2:
case WM8958_AIF3DAC_DATA:
case WM8958_AIF3ADC_DATA:
case WM8994_AIF1_ADC1_LEFT_VOLUME:
case WM8994_AIF1_ADC1_RIGHT_VOLUME:
case WM8994_AIF1_DAC1_LEFT_VOLUME:
case WM8994_AIF1_DAC1_RIGHT_VOLUME:
case WM8994_AIF1_ADC1_FILTERS:
case WM8994_AIF1_ADC2_FILTERS:
case WM8994_AIF1_DAC1_FILTERS_1:
case WM8994_AIF1_DAC1_FILTERS_2:
case WM8994_AIF1_DAC2_FILTERS_1:
case WM8994_AIF1_DAC2_FILTERS_2:
case WM8958_AIF1_DAC1_NOISE_GATE:
case WM8958_AIF1_DAC2_NOISE_GATE:
case WM8994_AIF1_DRC1_1:
case WM8994_AIF1_DRC1_2:
case WM8994_AIF1_DRC1_3:
case WM8994_AIF1_DRC1_4:
case WM8994_AIF1_DRC1_5:
case WM8994_AIF1_DRC2_1:
case WM8994_AIF1_DRC2_2:
case WM8994_AIF1_DRC2_3:
case WM8994_AIF1_DRC2_4:
case WM8994_AIF1_DRC2_5:
case WM8994_AIF1_DAC1_EQ_GAINS_1:
case WM8994_AIF1_DAC1_EQ_GAINS_2:
case WM8994_AIF1_DAC1_EQ_BAND_1_A:
case WM8994_AIF1_DAC1_EQ_BAND_1_B:
case WM8994_AIF1_DAC1_EQ_BAND_1_PG:
case WM8994_AIF1_DAC1_EQ_BAND_2_A:
case WM8994_AIF1_DAC1_EQ_BAND_2_B:
case WM8994_AIF1_DAC1_EQ_BAND_2_C:
case WM8994_AIF1_DAC1_EQ_BAND_2_PG:
case WM8994_AIF1_DAC1_EQ_BAND_3_A:
case WM8994_AIF1_DAC1_EQ_BAND_3_B:
case WM8994_AIF1_DAC1_EQ_BAND_3_C:
case WM8994_AIF1_DAC1_EQ_BAND_3_PG:
case WM8994_AIF1_DAC1_EQ_BAND_4_A:
case WM8994_AIF1_DAC1_EQ_BAND_4_B:
case WM8994_AIF1_DAC1_EQ_BAND_4_C:
case WM8994_AIF1_DAC1_EQ_BAND_4_PG:
case WM8994_AIF1_DAC1_EQ_BAND_5_A:
case WM8994_AIF1_DAC1_EQ_BAND_5_B:
case WM8994_AIF1_DAC1_EQ_BAND_5_PG:
case WM8994_AIF1_DAC1_EQ_BAND_1_C:
case WM8994_AIF1_DAC2_EQ_GAINS_1:
case WM8994_AIF1_DAC2_EQ_GAINS_2:
case WM8994_AIF1_DAC2_EQ_BAND_1_A:
case WM8994_AIF1_DAC2_EQ_BAND_1_B:
case WM8994_AIF1_DAC2_EQ_BAND_1_PG:
case WM8994_AIF1_DAC2_EQ_BAND_2_A:
case WM8994_AIF1_DAC2_EQ_BAND_2_B:
case WM8994_AIF1_DAC2_EQ_BAND_2_C:
case WM8994_AIF1_DAC2_EQ_BAND_2_PG:
case WM8994_AIF1_DAC2_EQ_BAND_3_A:
case WM8994_AIF1_DAC2_EQ_BAND_3_B:
case WM8994_AIF1_DAC2_EQ_BAND_3_C:
case WM8994_AIF1_DAC2_EQ_BAND_3_PG:
case WM8994_AIF1_DAC2_EQ_BAND_4_A:
case WM8994_AIF1_DAC2_EQ_BAND_4_B:
case WM8994_AIF1_DAC2_EQ_BAND_4_C:
case WM8994_AIF1_DAC2_EQ_BAND_4_PG:
case WM8994_AIF1_DAC2_EQ_BAND_5_A:
case WM8994_AIF1_DAC2_EQ_BAND_5_B:
case WM8994_AIF1_DAC2_EQ_BAND_5_PG:
case WM8994_AIF1_DAC2_EQ_BAND_1_C:
case WM8994_AIF2_ADC_LEFT_VOLUME:
case WM8994_AIF2_ADC_RIGHT_VOLUME:
case WM8994_AIF2_DAC_LEFT_VOLUME:
case WM8994_AIF2_DAC_RIGHT_VOLUME:
case WM8994_AIF2_ADC_FILTERS:
case WM8994_AIF2_DAC_FILTERS_1:
case WM8994_AIF2_DAC_FILTERS_2:
case WM8958_AIF2_DAC_NOISE_GATE:
case WM8994_AIF2_DRC_1:
case WM8994_AIF2_DRC_2:
case WM8994_AIF2_DRC_3:
case WM8994_AIF2_DRC_4:
case WM8994_AIF2_DRC_5:
case WM8994_AIF2_EQ_GAINS_1:
case WM8994_AIF2_EQ_GAINS_2:
case WM8994_AIF2_EQ_BAND_1_A:
case WM8994_AIF2_EQ_BAND_1_B:
case WM8994_AIF2_EQ_BAND_1_PG:
case WM8994_AIF2_EQ_BAND_2_A:
case WM8994_AIF2_EQ_BAND_2_B:
case WM8994_AIF2_EQ_BAND_2_C:
case WM8994_AIF2_EQ_BAND_2_PG:
case WM8994_AIF2_EQ_BAND_3_A:
case WM8994_AIF2_EQ_BAND_3_B:
case WM8994_AIF2_EQ_BAND_3_C:
case WM8994_AIF2_EQ_BAND_3_PG:
case WM8994_AIF2_EQ_BAND_4_A:
case WM8994_AIF2_EQ_BAND_4_B:
case WM8994_AIF2_EQ_BAND_4_C:
case WM8994_AIF2_EQ_BAND_4_PG:
case WM8994_AIF2_EQ_BAND_5_A:
case WM8994_AIF2_EQ_BAND_5_B:
case WM8994_AIF2_EQ_BAND_5_PG:
case WM8994_AIF2_EQ_BAND_1_C:
case WM8994_DAC1_MIXER_VOLUMES:
case WM8994_DAC1_LEFT_MIXER_ROUTING:
case WM8994_DAC1_RIGHT_MIXER_ROUTING:
case WM8994_DAC2_MIXER_VOLUMES:
case WM8994_DAC2_LEFT_MIXER_ROUTING:
case WM8994_DAC2_RIGHT_MIXER_ROUTING:
case WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING:
case WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING:
case WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING:
case WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING:
case WM8994_DAC1_LEFT_VOLUME:
case WM8994_DAC1_RIGHT_VOLUME:
case WM8994_DAC2_LEFT_VOLUME:
case WM8994_DAC2_RIGHT_VOLUME:
case WM8994_DAC_SOFTMUTE:
case WM8994_OVERSAMPLING:
case WM8994_SIDETONE:
case WM8994_GPIO_1:
case WM8994_GPIO_2:
case WM8994_GPIO_3:
case WM8994_GPIO_4:
case WM8994_GPIO_5:
case WM8994_GPIO_6:
case WM8994_GPIO_8:
case WM8994_GPIO_9:
case WM8994_GPIO_10:
case WM8994_GPIO_11:
case WM8994_PULL_CONTROL_1:
case WM8994_PULL_CONTROL_2:
case WM8994_INTERRUPT_STATUS_1:
case WM8994_INTERRUPT_STATUS_2:
case WM8994_INTERRUPT_RAW_STATUS_2:
case WM8994_INTERRUPT_STATUS_1_MASK:
case WM8994_INTERRUPT_STATUS_2_MASK:
case WM8994_INTERRUPT_CONTROL:
case WM8994_IRQ_DEBOUNCE:
return true;
default:
return false;
}
}
static bool wm8994_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8994_DC_SERVO_READBACK:
case WM8994_MICBIAS:
case WM8994_WRITE_SEQUENCER_CTRL_1:
case WM8994_WRITE_SEQUENCER_CTRL_2:
case WM8994_AIF1_ADC2_LEFT_VOLUME:
case WM8994_AIF1_ADC2_RIGHT_VOLUME:
case WM8994_AIF1_DAC2_LEFT_VOLUME:
case WM8994_AIF1_DAC2_RIGHT_VOLUME:
case WM8994_AIF1_ADC2_FILTERS:
case WM8994_AIF1_DAC2_FILTERS_1:
case WM8994_AIF1_DAC2_FILTERS_2:
case WM8958_AIF1_DAC2_NOISE_GATE:
case WM8994_AIF1_DRC2_1:
case WM8994_AIF1_DRC2_2:
case WM8994_AIF1_DRC2_3:
case WM8994_AIF1_DRC2_4:
case WM8994_AIF1_DRC2_5:
case WM8994_AIF1_DAC2_EQ_GAINS_1:
case WM8994_AIF1_DAC2_EQ_GAINS_2:
case WM8994_AIF1_DAC2_EQ_BAND_1_A:
case WM8994_AIF1_DAC2_EQ_BAND_1_B:
case WM8994_AIF1_DAC2_EQ_BAND_1_PG:
case WM8994_AIF1_DAC2_EQ_BAND_2_A:
case WM8994_AIF1_DAC2_EQ_BAND_2_B:
case WM8994_AIF1_DAC2_EQ_BAND_2_C:
case WM8994_AIF1_DAC2_EQ_BAND_2_PG:
case WM8994_AIF1_DAC2_EQ_BAND_3_A:
case WM8994_AIF1_DAC2_EQ_BAND_3_B:
case WM8994_AIF1_DAC2_EQ_BAND_3_C:
case WM8994_AIF1_DAC2_EQ_BAND_3_PG:
case WM8994_AIF1_DAC2_EQ_BAND_4_A:
case WM8994_AIF1_DAC2_EQ_BAND_4_B:
case WM8994_AIF1_DAC2_EQ_BAND_4_C:
case WM8994_AIF1_DAC2_EQ_BAND_4_PG:
case WM8994_AIF1_DAC2_EQ_BAND_5_A:
case WM8994_AIF1_DAC2_EQ_BAND_5_B:
case WM8994_AIF1_DAC2_EQ_BAND_5_PG:
case WM8994_AIF1_DAC2_EQ_BAND_1_C:
case WM8994_DAC2_MIXER_VOLUMES:
case WM8994_DAC2_LEFT_MIXER_ROUTING:
case WM8994_DAC2_RIGHT_MIXER_ROUTING:
case WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING:
case WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING:
case WM8994_DAC2_LEFT_VOLUME:
case WM8994_DAC2_RIGHT_VOLUME:
return true;
default:
return wm1811_readable_register(dev, reg);
}
}
static bool wm8958_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8958_DSP2_PROGRAM:
case WM8958_DSP2_CONFIG:
case WM8958_DSP2_MAGICNUM:
case WM8958_DSP2_RELEASEYEAR:
case WM8958_DSP2_RELEASEMONTHDAY:
case WM8958_DSP2_RELEASETIME:
case WM8958_DSP2_VERMAJMIN:
case WM8958_DSP2_VERBUILD:
case WM8958_DSP2_TESTREG:
case WM8958_DSP2_XORREG:
case WM8958_DSP2_SHIFTMAXX:
case WM8958_DSP2_SHIFTMAXY:
case WM8958_DSP2_SHIFTMAXZ:
case WM8958_DSP2_SHIFTMAXEXTLO:
case WM8958_DSP2_AESSELECT:
case WM8958_DSP2_EXECCONTROL:
case WM8958_DSP2_SAMPLEBREAK:
case WM8958_DSP2_COUNTBREAK:
case WM8958_DSP2_INTSTATUS:
case WM8958_DSP2_EVENTSTATUS:
case WM8958_DSP2_INTMASK:
case WM8958_DSP2_CONFIGDWIDTH:
case WM8958_DSP2_CONFIGINSTR:
case WM8958_DSP2_CONFIGDMEM:
case WM8958_DSP2_CONFIGDELAYS:
case WM8958_DSP2_CONFIGNUMIO:
case WM8958_DSP2_CONFIGEXTDEPTH:
case WM8958_DSP2_CONFIGMULTIPLIER:
case WM8958_DSP2_CONFIGCTRLDWIDTH:
case WM8958_DSP2_CONFIGPIPELINE:
case WM8958_DSP2_SHIFTMAXEXTHI:
case WM8958_DSP2_SWVERSIONREG:
case WM8958_DSP2_CONFIGXMEM:
case WM8958_DSP2_CONFIGYMEM:
case WM8958_DSP2_CONFIGZMEM:
case WM8958_FW_BUILD_1:
case WM8958_FW_BUILD_0:
case WM8958_FW_ID_1:
case WM8958_FW_ID_0:
case WM8958_FW_MAJOR_1:
case WM8958_FW_MAJOR_0:
case WM8958_FW_MINOR_1:
case WM8958_FW_MINOR_0:
case WM8958_FW_PATCH_1:
case WM8958_FW_PATCH_0:
case WM8958_MBC_BAND_1_K_1:
case WM8958_MBC_BAND_1_K_2:
case WM8958_MBC_BAND_1_N1_1:
case WM8958_MBC_BAND_1_N1_2:
case WM8958_MBC_BAND_1_N2_1:
case WM8958_MBC_BAND_1_N2_2:
case WM8958_MBC_BAND_1_N3_1:
case WM8958_MBC_BAND_1_N3_2:
case WM8958_MBC_BAND_1_N4_1:
case WM8958_MBC_BAND_1_N4_2:
case WM8958_MBC_BAND_1_N5_1:
case WM8958_MBC_BAND_1_N5_2:
case WM8958_MBC_BAND_1_X1_1:
case WM8958_MBC_BAND_1_X1_2:
case WM8958_MBC_BAND_1_X2_1:
case WM8958_MBC_BAND_1_X2_2:
case WM8958_MBC_BAND_1_X3_1:
case WM8958_MBC_BAND_1_X3_2:
case WM8958_MBC_BAND_1_ATTACK_1:
case WM8958_MBC_BAND_1_ATTACK_2:
case WM8958_MBC_BAND_1_DECAY_1:
case WM8958_MBC_BAND_1_DECAY_2:
case WM8958_MBC_BAND_2_K_1:
case WM8958_MBC_BAND_2_K_2:
case WM8958_MBC_BAND_2_N1_1:
case WM8958_MBC_BAND_2_N1_2:
case WM8958_MBC_BAND_2_N2_1:
case WM8958_MBC_BAND_2_N2_2:
case WM8958_MBC_BAND_2_N3_1:
case WM8958_MBC_BAND_2_N3_2:
case WM8958_MBC_BAND_2_N4_1:
case WM8958_MBC_BAND_2_N4_2:
case WM8958_MBC_BAND_2_N5_1:
case WM8958_MBC_BAND_2_N5_2:
case WM8958_MBC_BAND_2_X1_1:
case WM8958_MBC_BAND_2_X1_2:
case WM8958_MBC_BAND_2_X2_1:
case WM8958_MBC_BAND_2_X2_2:
case WM8958_MBC_BAND_2_X3_1:
case WM8958_MBC_BAND_2_X3_2:
case WM8958_MBC_BAND_2_ATTACK_1:
case WM8958_MBC_BAND_2_ATTACK_2:
case WM8958_MBC_BAND_2_DECAY_1:
case WM8958_MBC_BAND_2_DECAY_2:
case WM8958_MBC_B2_PG2_1:
case WM8958_MBC_B2_PG2_2:
case WM8958_MBC_B1_PG2_1:
case WM8958_MBC_B1_PG2_2:
case WM8958_MBC_CROSSOVER_1:
case WM8958_MBC_CROSSOVER_2:
case WM8958_MBC_HPF_1:
case WM8958_MBC_HPF_2:
case WM8958_MBC_LPF_1:
case WM8958_MBC_LPF_2:
case WM8958_MBC_RMS_LIMIT_1:
case WM8958_MBC_RMS_LIMIT_2:
return true;
default:
return wm8994_readable_register(dev, reg);
}
}
static bool wm8994_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8994_SOFTWARE_RESET:
case WM8994_DC_SERVO_1:
case WM8994_DC_SERVO_READBACK:
case WM8994_RATE_STATUS:
case WM8958_MIC_DETECT_3:
case WM8994_DC_SERVO_4E:
case WM8994_INTERRUPT_STATUS_1:
case WM8994_INTERRUPT_STATUS_2:
return true;
default:
return false;
}
}
static bool wm1811_volatile_register(struct device *dev, unsigned int reg)
{
struct wm8994 *wm8994 = dev_get_drvdata(dev);
switch (reg) {
case WM8994_GPIO_6:
if (wm8994->cust_id > 1 || wm8994->revision > 1)
return true;
else
return false;
default:
return wm8994_volatile_register(dev, reg);
}
}
static bool wm8958_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8958_DSP2_MAGICNUM:
case WM8958_DSP2_RELEASEYEAR:
case WM8958_DSP2_RELEASEMONTHDAY:
case WM8958_DSP2_RELEASETIME:
case WM8958_DSP2_VERMAJMIN:
case WM8958_DSP2_VERBUILD:
case WM8958_DSP2_EXECCONTROL:
case WM8958_DSP2_SWVERSIONREG:
case WM8958_DSP2_CONFIGXMEM:
case WM8958_DSP2_CONFIGYMEM:
case WM8958_DSP2_CONFIGZMEM:
case WM8958_FW_BUILD_1:
case WM8958_FW_BUILD_0:
case WM8958_FW_ID_1:
case WM8958_FW_ID_0:
case WM8958_FW_MAJOR_1:
case WM8958_FW_MAJOR_0:
case WM8958_FW_MINOR_1:
case WM8958_FW_MINOR_0:
case WM8958_FW_PATCH_1:
case WM8958_FW_PATCH_0:
return true;
default:
return wm8994_volatile_register(dev, reg);
}
}
struct regmap_config wm1811_regmap_config = {
.reg_bits = 16,
.val_bits = 16,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm1811_defaults,
.num_reg_defaults = ARRAY_SIZE(wm1811_defaults),
.max_register = WM8994_MAX_REGISTER,
.volatile_reg = wm1811_volatile_register,
.readable_reg = wm1811_readable_register,
};
EXPORT_SYMBOL(wm1811_regmap_config);
struct regmap_config wm8994_regmap_config = {
.reg_bits = 16,
.val_bits = 16,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm8994_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8994_defaults),
.max_register = WM8994_MAX_REGISTER,
.volatile_reg = wm8994_volatile_register,
.readable_reg = wm8994_readable_register,
};
EXPORT_SYMBOL(wm8994_regmap_config);
struct regmap_config wm8958_regmap_config = {
.reg_bits = 16,
.val_bits = 16,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm8958_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8958_defaults),
.max_register = WM8994_MAX_REGISTER,
.volatile_reg = wm8958_volatile_register,
.readable_reg = wm8958_readable_register,
};
EXPORT_SYMBOL(wm8958_regmap_config);
struct regmap_config wm8994_base_regmap_config = {
.reg_bits = 16,
.val_bits = 16,
};
EXPORT_SYMBOL(wm8994_base_regmap_config);
| linux-master | drivers/mfd/wm8994-regmap.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/* NXP PCF50633 GPIO Driver
*
* (C) 2006-2008 by Openmoko, Inc.
* Author: Balaji Rao <[email protected]>
* All rights reserved.
*
* Broken down from monstrous PCF50633 driver mainly by
* Harald Welte, Andy Green and Werner Almesberger
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mfd/pcf50633/core.h>
#include <linux/mfd/pcf50633/gpio.h>
#include <linux/mfd/pcf50633/pmic.h>
static const u8 pcf50633_regulator_registers[PCF50633_NUM_REGULATORS] = {
[PCF50633_REGULATOR_AUTO] = PCF50633_REG_AUTOOUT,
[PCF50633_REGULATOR_DOWN1] = PCF50633_REG_DOWN1OUT,
[PCF50633_REGULATOR_DOWN2] = PCF50633_REG_DOWN2OUT,
[PCF50633_REGULATOR_MEMLDO] = PCF50633_REG_MEMLDOOUT,
[PCF50633_REGULATOR_LDO1] = PCF50633_REG_LDO1OUT,
[PCF50633_REGULATOR_LDO2] = PCF50633_REG_LDO2OUT,
[PCF50633_REGULATOR_LDO3] = PCF50633_REG_LDO3OUT,
[PCF50633_REGULATOR_LDO4] = PCF50633_REG_LDO4OUT,
[PCF50633_REGULATOR_LDO5] = PCF50633_REG_LDO5OUT,
[PCF50633_REGULATOR_LDO6] = PCF50633_REG_LDO6OUT,
[PCF50633_REGULATOR_HCLDO] = PCF50633_REG_HCLDOOUT,
};
int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val)
{
u8 reg;
reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
return pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val);
}
EXPORT_SYMBOL_GPL(pcf50633_gpio_set);
u8 pcf50633_gpio_get(struct pcf50633 *pcf, int gpio)
{
u8 reg, val;
reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
val = pcf50633_reg_read(pcf, reg) & 0x07;
return val;
}
EXPORT_SYMBOL_GPL(pcf50633_gpio_get);
int pcf50633_gpio_invert_set(struct pcf50633 *pcf, int gpio, int invert)
{
u8 val, reg;
reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
val = !!invert << 3;
return pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val);
}
EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_set);
int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio)
{
u8 reg, val;
reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
val = pcf50633_reg_read(pcf, reg);
return val & (1 << 3);
}
EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_get);
int pcf50633_gpio_power_supply_set(struct pcf50633 *pcf,
int gpio, int regulator, int on)
{
u8 reg, val, mask;
/* the *ENA register is always one after the *OUT register */
reg = pcf50633_regulator_registers[regulator] + 1;
val = !!on << (gpio - PCF50633_GPIO1);
mask = 1 << (gpio - PCF50633_GPIO1);
return pcf50633_reg_set_bit_mask(pcf, reg, mask, val);
}
EXPORT_SYMBOL_GPL(pcf50633_gpio_power_supply_set);
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/pcf50633-gpio.c |
// SPDX-License-Identifier: GPL-2.0-only
/* linux/drivers/mfd/sm501.c
*
* Copyright (C) 2006 Simtec Electronics
* Ben Dooks <[email protected]>
* Vincent Sanders <[email protected]>
*
* SM501 MFD driver
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/platform_data/i2c-gpio.h>
#include <linux/gpio/driver.h>
#include <linux/gpio/machine.h>
#include <linux/slab.h>
#include <linux/sm501.h>
#include <linux/sm501-regs.h>
#include <linux/serial_8250.h>
#include <linux/io.h>
struct sm501_device {
struct list_head list;
struct platform_device pdev;
};
struct sm501_gpio;
#ifdef CONFIG_MFD_SM501_GPIO
#include <linux/gpio.h>
struct sm501_gpio_chip {
struct gpio_chip gpio;
struct sm501_gpio *ourgpio; /* to get back to parent. */
void __iomem *regbase;
void __iomem *control; /* address of control reg. */
};
struct sm501_gpio {
struct sm501_gpio_chip low;
struct sm501_gpio_chip high;
spinlock_t lock;
unsigned int registered : 1;
void __iomem *regs;
struct resource *regs_res;
};
#else
struct sm501_gpio {
/* no gpio support, empty definition for sm501_devdata. */
};
#endif
struct sm501_devdata {
spinlock_t reg_lock;
struct mutex clock_lock;
struct list_head devices;
struct sm501_gpio gpio;
struct device *dev;
struct resource *io_res;
struct resource *mem_res;
struct resource *regs_claim;
struct sm501_platdata *platdata;
unsigned int in_suspend;
unsigned long pm_misc;
int unit_power[20];
unsigned int pdev_id;
unsigned int irq;
void __iomem *regs;
unsigned int rev;
};
#define MHZ (1000 * 1000)
#ifdef DEBUG
static const unsigned int div_tab[] = {
[0] = 1,
[1] = 2,
[2] = 4,
[3] = 8,
[4] = 16,
[5] = 32,
[6] = 64,
[7] = 128,
[8] = 3,
[9] = 6,
[10] = 12,
[11] = 24,
[12] = 48,
[13] = 96,
[14] = 192,
[15] = 384,
[16] = 5,
[17] = 10,
[18] = 20,
[19] = 40,
[20] = 80,
[21] = 160,
[22] = 320,
[23] = 604,
};
static unsigned long decode_div(unsigned long pll2, unsigned long val,
unsigned int lshft, unsigned int selbit,
unsigned long mask)
{
if (val & selbit)
pll2 = 288 * MHZ;
return pll2 / div_tab[(val >> lshft) & mask];
}
#define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
/* sm501_dump_clk
*
* Print out the current clock configuration for the device
*/
static void sm501_dump_clk(struct sm501_devdata *sm)
{
unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING);
unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
unsigned long sdclk0, sdclk1;
unsigned long pll2 = 0;
switch (misct & 0x30) {
case 0x00:
pll2 = 336 * MHZ;
break;
case 0x10:
pll2 = 288 * MHZ;
break;
case 0x20:
pll2 = 240 * MHZ;
break;
case 0x30:
pll2 = 192 * MHZ;
break;
}
sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
sdclk0 /= div_tab[((misct >> 8) & 0xf)];
sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
sdclk1 /= div_tab[((misct >> 16) & 0xf)];
dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
misct, pm0, pm1);
dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
fmt_freq(pll2), sdclk0, sdclk1);
dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
dev_dbg(sm->dev, "PM0[%c]: "
"P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
"M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
(pmc & 3 ) == 0 ? '*' : '-',
fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)),
fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15)));
dev_dbg(sm->dev, "PM1[%c]: "
"P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
"M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
(pmc & 3 ) == 1 ? '*' : '-',
fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)),
fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15)));
}
static void sm501_dump_regs(struct sm501_devdata *sm)
{
void __iomem *regs = sm->regs;
dev_info(sm->dev, "System Control %08x\n",
smc501_readl(regs + SM501_SYSTEM_CONTROL));
dev_info(sm->dev, "Misc Control %08x\n",
smc501_readl(regs + SM501_MISC_CONTROL));
dev_info(sm->dev, "GPIO Control Low %08x\n",
smc501_readl(regs + SM501_GPIO31_0_CONTROL));
dev_info(sm->dev, "GPIO Control Hi %08x\n",
smc501_readl(regs + SM501_GPIO63_32_CONTROL));
dev_info(sm->dev, "DRAM Control %08x\n",
smc501_readl(regs + SM501_DRAM_CONTROL));
dev_info(sm->dev, "Arbitration Ctrl %08x\n",
smc501_readl(regs + SM501_ARBTRTN_CONTROL));
dev_info(sm->dev, "Misc Timing %08x\n",
smc501_readl(regs + SM501_MISC_TIMING));
}
static void sm501_dump_gate(struct sm501_devdata *sm)
{
dev_info(sm->dev, "CurrentGate %08x\n",
smc501_readl(sm->regs + SM501_CURRENT_GATE));
dev_info(sm->dev, "CurrentClock %08x\n",
smc501_readl(sm->regs + SM501_CURRENT_CLOCK));
dev_info(sm->dev, "PowerModeControl %08x\n",
smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL));
}
#else
static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
#endif
/* sm501_sync_regs
*
* ensure the
*/
static void sm501_sync_regs(struct sm501_devdata *sm)
{
smc501_readl(sm->regs);
}
static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
{
/* during suspend/resume, we are currently not allowed to sleep,
* so change to using mdelay() instead of msleep() if we
* are in one of these paths */
if (sm->in_suspend)
mdelay(delay);
else
msleep(delay);
}
/* sm501_misc_control
*
* alters the miscellaneous control parameters
*/
int sm501_misc_control(struct device *dev,
unsigned long set, unsigned long clear)
{
struct sm501_devdata *sm = dev_get_drvdata(dev);
unsigned long misc;
unsigned long save;
unsigned long to;
spin_lock_irqsave(&sm->reg_lock, save);
misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
to = (misc & ~clear) | set;
if (to != misc) {
smc501_writel(to, sm->regs + SM501_MISC_CONTROL);
sm501_sync_regs(sm);
dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
}
spin_unlock_irqrestore(&sm->reg_lock, save);
return to;
}
EXPORT_SYMBOL_GPL(sm501_misc_control);
/* sm501_modify_reg
*
* Modify a register in the SM501 which may be shared with other
* drivers.
*/
unsigned long sm501_modify_reg(struct device *dev,
unsigned long reg,
unsigned long set,
unsigned long clear)
{
struct sm501_devdata *sm = dev_get_drvdata(dev);
unsigned long data;
unsigned long save;
spin_lock_irqsave(&sm->reg_lock, save);
data = smc501_readl(sm->regs + reg);
data |= set;
data &= ~clear;
smc501_writel(data, sm->regs + reg);
sm501_sync_regs(sm);
spin_unlock_irqrestore(&sm->reg_lock, save);
return data;
}
EXPORT_SYMBOL_GPL(sm501_modify_reg);
/* sm501_unit_power
*
* alters the power active gate to set specific units on or off
*/
int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
{
struct sm501_devdata *sm = dev_get_drvdata(dev);
unsigned long mode;
unsigned long gate;
unsigned long clock;
mutex_lock(&sm->clock_lock);
mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
mode &= 3; /* get current power mode */
if (unit >= ARRAY_SIZE(sm->unit_power)) {
dev_err(dev, "%s: bad unit %d\n", __func__, unit);
goto already;
}
dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
sm->unit_power[unit], to);
if (to == 0 && sm->unit_power[unit] == 0) {
dev_err(sm->dev, "unit %d is already shutdown\n", unit);
goto already;
}
sm->unit_power[unit] += to ? 1 : -1;
to = sm->unit_power[unit] ? 1 : 0;
if (to) {
if (gate & (1 << unit))
goto already;
gate |= (1 << unit);
} else {
if (!(gate & (1 << unit)))
goto already;
gate &= ~(1 << unit);
}
switch (mode) {
case 1:
smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
mode = 0;
break;
case 2:
case 0:
smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
mode = 1;
break;
default:
gate = -1;
goto already;
}
smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
sm501_sync_regs(sm);
dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
gate, clock, mode);
sm501_mdelay(sm, 16);
already:
mutex_unlock(&sm->clock_lock);
return gate;
}
EXPORT_SYMBOL_GPL(sm501_unit_power);
/* clock value structure. */
struct sm501_clock {
unsigned long mclk;
int divider;
int shift;
unsigned int m, n, k;
};
/* sm501_calc_clock
*
* Calculates the nearest discrete clock frequency that
* can be achieved with the specified input clock.
* the maximum divisor is 3 or 5
*/
static int sm501_calc_clock(unsigned long freq,
struct sm501_clock *clock,
int max_div,
unsigned long mclk,
long *best_diff)
{
int ret = 0;
int divider;
int shift;
long diff;
/* try dividers 1 and 3 for CRT and for panel,
try divider 5 for panel only.*/
for (divider = 1; divider <= max_div; divider += 2) {
/* try all 8 shift values.*/
for (shift = 0; shift < 8; shift++) {
/* Calculate difference to requested clock */
diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
if (diff < 0)
diff = -diff;
/* If it is less than the current, use it */
if (diff < *best_diff) {
*best_diff = diff;
clock->mclk = mclk;
clock->divider = divider;
clock->shift = shift;
ret = 1;
}
}
}
return ret;
}
/* sm501_calc_pll
*
* Calculates the nearest discrete clock frequency that can be
* achieved using the programmable PLL.
* the maximum divisor is 3 or 5
*/
static unsigned long sm501_calc_pll(unsigned long freq,
struct sm501_clock *clock,
int max_div)
{
unsigned long mclk;
unsigned int m, n, k;
long best_diff = 999999999;
/*
* The SM502 datasheet doesn't specify the min/max values for M and N.
* N = 1 at least doesn't work in practice.
*/
for (m = 2; m <= 255; m++) {
for (n = 2; n <= 127; n++) {
for (k = 0; k <= 1; k++) {
mclk = (24000000UL * m / n) >> k;
if (sm501_calc_clock(freq, clock, max_div,
mclk, &best_diff)) {
clock->m = m;
clock->n = n;
clock->k = k;
}
}
}
}
/* Return best clock. */
return clock->mclk / (clock->divider << clock->shift);
}
/* sm501_select_clock
*
* Calculates the nearest discrete clock frequency that can be
* achieved using the 288MHz and 336MHz PLLs.
* the maximum divisor is 3 or 5
*/
static unsigned long sm501_select_clock(unsigned long freq,
struct sm501_clock *clock,
int max_div)
{
unsigned long mclk;
long best_diff = 999999999;
/* Try 288MHz and 336MHz clocks. */
for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
}
/* Return best clock. */
return clock->mclk / (clock->divider << clock->shift);
}
/* sm501_set_clock
*
* set one of the four clock sources to the closest available frequency to
* the one specified
*/
unsigned long sm501_set_clock(struct device *dev,
int clksrc,
unsigned long req_freq)
{
struct sm501_devdata *sm = dev_get_drvdata(dev);
unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
unsigned int pll_reg = 0;
unsigned long sm501_freq; /* the actual frequency achieved */
u64 reg;
struct sm501_clock to;
/* find achivable discrete frequency and setup register value
* accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
* has an extra bit for the divider */
switch (clksrc) {
case SM501_CLOCK_P2XCLK:
/* This clock is divided in half so to achieve the
* requested frequency the value must be multiplied by
* 2. This clock also has an additional pre divisor */
if (sm->rev >= 0xC0) {
/* SM502 -> use the programmable PLL */
sm501_freq = (sm501_calc_pll(2 * req_freq,
&to, 5) / 2);
reg = to.shift & 0x07;/* bottom 3 bits are shift */
if (to.divider == 3)
reg |= 0x08; /* /3 divider required */
else if (to.divider == 5)
reg |= 0x10; /* /5 divider required */
reg |= 0x40; /* select the programmable PLL */
pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
} else {
sm501_freq = (sm501_select_clock(2 * req_freq,
&to, 5) / 2);
reg = to.shift & 0x07;/* bottom 3 bits are shift */
if (to.divider == 3)
reg |= 0x08; /* /3 divider required */
else if (to.divider == 5)
reg |= 0x10; /* /5 divider required */
if (to.mclk != 288000000)
reg |= 0x20; /* which mclk pll is source */
}
break;
case SM501_CLOCK_V2XCLK:
/* This clock is divided in half so to achieve the
* requested frequency the value must be multiplied by 2. */
sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
reg=to.shift & 0x07; /* bottom 3 bits are shift */
if (to.divider == 3)
reg |= 0x08; /* /3 divider required */
if (to.mclk != 288000000)
reg |= 0x10; /* which mclk pll is source */
break;
case SM501_CLOCK_MCLK:
case SM501_CLOCK_M1XCLK:
/* These clocks are the same and not further divided */
sm501_freq = sm501_select_clock( req_freq, &to, 3);
reg=to.shift & 0x07; /* bottom 3 bits are shift */
if (to.divider == 3)
reg |= 0x08; /* /3 divider required */
if (to.mclk != 288000000)
reg |= 0x10; /* which mclk pll is source */
break;
default:
return 0; /* this is bad */
}
mutex_lock(&sm->clock_lock);
mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
clock = clock & ~(0xFF << clksrc);
clock |= reg<<clksrc;
mode &= 3; /* find current mode */
switch (mode) {
case 1:
smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
mode = 0;
break;
case 2:
case 0:
smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
mode = 1;
break;
default:
mutex_unlock(&sm->clock_lock);
return -1;
}
smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
if (pll_reg)
smc501_writel(pll_reg,
sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
sm501_sync_regs(sm);
dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
gate, clock, mode);
sm501_mdelay(sm, 16);
mutex_unlock(&sm->clock_lock);
sm501_dump_clk(sm);
return sm501_freq;
}
EXPORT_SYMBOL_GPL(sm501_set_clock);
/* sm501_find_clock
*
* finds the closest available frequency for a given clock
*/
unsigned long sm501_find_clock(struct device *dev,
int clksrc,
unsigned long req_freq)
{
struct sm501_devdata *sm = dev_get_drvdata(dev);
unsigned long sm501_freq; /* the frequency achieveable by the 501 */
struct sm501_clock to;
switch (clksrc) {
case SM501_CLOCK_P2XCLK:
if (sm->rev >= 0xC0) {
/* SM502 -> use the programmable PLL */
sm501_freq = (sm501_calc_pll(2 * req_freq,
&to, 5) / 2);
} else {
sm501_freq = (sm501_select_clock(2 * req_freq,
&to, 5) / 2);
}
break;
case SM501_CLOCK_V2XCLK:
sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
break;
case SM501_CLOCK_MCLK:
case SM501_CLOCK_M1XCLK:
sm501_freq = sm501_select_clock(req_freq, &to, 3);
break;
default:
sm501_freq = 0; /* error */
}
return sm501_freq;
}
EXPORT_SYMBOL_GPL(sm501_find_clock);
static struct sm501_device *to_sm_device(struct platform_device *pdev)
{
return container_of(pdev, struct sm501_device, pdev);
}
/* sm501_device_release
*
* A release function for the platform devices we create to allow us to
* free any items we allocated
*/
static void sm501_device_release(struct device *dev)
{
kfree(to_sm_device(to_platform_device(dev)));
}
/* sm501_create_subdev
*
* Create a skeleton platform device with resources for passing to a
* sub-driver
*/
static struct platform_device *
sm501_create_subdev(struct sm501_devdata *sm, char *name,
unsigned int res_count, unsigned int platform_data_size)
{
struct sm501_device *smdev;
smdev = kzalloc(sizeof(struct sm501_device) +
(sizeof(struct resource) * res_count) +
platform_data_size, GFP_KERNEL);
if (!smdev)
return NULL;
smdev->pdev.dev.release = sm501_device_release;
smdev->pdev.name = name;
smdev->pdev.id = sm->pdev_id;
smdev->pdev.dev.parent = sm->dev;
smdev->pdev.dev.coherent_dma_mask = 0xffffffff;
if (res_count) {
smdev->pdev.resource = (struct resource *)(smdev+1);
smdev->pdev.num_resources = res_count;
}
if (platform_data_size)
smdev->pdev.dev.platform_data = (void *)(smdev+1);
return &smdev->pdev;
}
/* sm501_register_device
*
* Register a platform device created with sm501_create_subdev()
*/
static int sm501_register_device(struct sm501_devdata *sm,
struct platform_device *pdev)
{
struct sm501_device *smdev = to_sm_device(pdev);
int ptr;
int ret;
for (ptr = 0; ptr < pdev->num_resources; ptr++) {
printk(KERN_DEBUG "%s[%d] %pR\n",
pdev->name, ptr, &pdev->resource[ptr]);
}
ret = platform_device_register(pdev);
if (ret >= 0) {
dev_dbg(sm->dev, "registered %s\n", pdev->name);
list_add_tail(&smdev->list, &sm->devices);
} else
dev_err(sm->dev, "error registering %s (%d)\n",
pdev->name, ret);
return ret;
}
/* sm501_create_subio
*
* Fill in an IO resource for a sub device
*/
static void sm501_create_subio(struct sm501_devdata *sm,
struct resource *res,
resource_size_t offs,
resource_size_t size)
{
res->flags = IORESOURCE_MEM;
res->parent = sm->io_res;
res->start = sm->io_res->start + offs;
res->end = res->start + size - 1;
}
/* sm501_create_mem
*
* Fill in an MEM resource for a sub device
*/
static void sm501_create_mem(struct sm501_devdata *sm,
struct resource *res,
resource_size_t *offs,
resource_size_t size)
{
*offs -= size; /* adjust memory size */
res->flags = IORESOURCE_MEM;
res->parent = sm->mem_res;
res->start = sm->mem_res->start + *offs;
res->end = res->start + size - 1;
}
/* sm501_create_irq
*
* Fill in an IRQ resource for a sub device
*/
static void sm501_create_irq(struct sm501_devdata *sm,
struct resource *res)
{
res->flags = IORESOURCE_IRQ;
res->parent = NULL;
res->start = res->end = sm->irq;
}
static int sm501_register_usbhost(struct sm501_devdata *sm,
resource_size_t *mem_avail)
{
struct platform_device *pdev;
pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
if (!pdev)
return -ENOMEM;
sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
sm501_create_irq(sm, &pdev->resource[2]);
return sm501_register_device(sm, pdev);
}
static void sm501_setup_uart_data(struct sm501_devdata *sm,
struct plat_serial8250_port *uart_data,
unsigned int offset)
{
uart_data->membase = sm->regs + offset;
uart_data->mapbase = sm->io_res->start + offset;
uart_data->iotype = UPIO_MEM;
uart_data->irq = sm->irq;
uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
uart_data->regshift = 2;
uart_data->uartclk = (9600 * 16);
}
static int sm501_register_uart(struct sm501_devdata *sm, int devices)
{
struct platform_device *pdev;
struct plat_serial8250_port *uart_data;
pdev = sm501_create_subdev(sm, "serial8250", 0,
sizeof(struct plat_serial8250_port) * 3);
if (!pdev)
return -ENOMEM;
uart_data = dev_get_platdata(&pdev->dev);
if (devices & SM501_USE_UART0) {
sm501_setup_uart_data(sm, uart_data++, 0x30000);
sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
}
if (devices & SM501_USE_UART1) {
sm501_setup_uart_data(sm, uart_data++, 0x30020);
sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
}
pdev->id = PLAT8250_DEV_SM501;
return sm501_register_device(sm, pdev);
}
static int sm501_register_display(struct sm501_devdata *sm,
resource_size_t *mem_avail)
{
struct platform_device *pdev;
pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
if (!pdev)
return -ENOMEM;
sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
sm501_create_irq(sm, &pdev->resource[3]);
return sm501_register_device(sm, pdev);
}
#ifdef CONFIG_MFD_SM501_GPIO
static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
{
return container_of(gpio, struct sm501_devdata, gpio);
}
static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct sm501_gpio_chip *smgpio = gpiochip_get_data(chip);
unsigned long result;
result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
result >>= offset;
return result & 1UL;
}
static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip,
unsigned long bit)
{
unsigned long ctrl;
/* check and modify if this pin is not set as gpio. */
if (smc501_readl(smchip->control) & bit) {
dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,
"changing mode of gpio, bit %08lx\n", bit);
ctrl = smc501_readl(smchip->control);
ctrl &= ~bit;
smc501_writel(ctrl, smchip->control);
sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));
}
}
static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
struct sm501_gpio *smgpio = smchip->ourgpio;
unsigned long bit = 1 << offset;
void __iomem *regs = smchip->regbase;
unsigned long save;
unsigned long val;
dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
__func__, chip, offset);
spin_lock_irqsave(&smgpio->lock, save);
val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
if (value)
val |= bit;
smc501_writel(val, regs);
sm501_sync_regs(sm501_gpio_to_dev(smgpio));
sm501_gpio_ensure_gpio(smchip, bit);
spin_unlock_irqrestore(&smgpio->lock, save);
}
static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
{
struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
struct sm501_gpio *smgpio = smchip->ourgpio;
void __iomem *regs = smchip->regbase;
unsigned long bit = 1 << offset;
unsigned long save;
unsigned long ddr;
dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
__func__, chip, offset);
spin_lock_irqsave(&smgpio->lock, save);
ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
sm501_sync_regs(sm501_gpio_to_dev(smgpio));
sm501_gpio_ensure_gpio(smchip, bit);
spin_unlock_irqrestore(&smgpio->lock, save);
return 0;
}
static int sm501_gpio_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
struct sm501_gpio *smgpio = smchip->ourgpio;
unsigned long bit = 1 << offset;
void __iomem *regs = smchip->regbase;
unsigned long save;
unsigned long val;
unsigned long ddr;
dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
__func__, chip, offset, value);
spin_lock_irqsave(&smgpio->lock, save);
val = smc501_readl(regs + SM501_GPIO_DATA_LOW);
if (value)
val |= bit;
else
val &= ~bit;
smc501_writel(val, regs);
ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
sm501_sync_regs(sm501_gpio_to_dev(smgpio));
smc501_writel(val, regs + SM501_GPIO_DATA_LOW);
sm501_sync_regs(sm501_gpio_to_dev(smgpio));
spin_unlock_irqrestore(&smgpio->lock, save);
return 0;
}
static const struct gpio_chip gpio_chip_template = {
.ngpio = 32,
.direction_input = sm501_gpio_input,
.direction_output = sm501_gpio_output,
.set = sm501_gpio_set,
.get = sm501_gpio_get,
};
static int sm501_gpio_register_chip(struct sm501_devdata *sm,
struct sm501_gpio *gpio,
struct sm501_gpio_chip *chip)
{
struct sm501_platdata *pdata = sm->platdata;
struct gpio_chip *gchip = &chip->gpio;
int base = pdata->gpio_base;
chip->gpio = gpio_chip_template;
if (chip == &gpio->high) {
if (base > 0)
base += 32;
chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
gchip->label = "SM501-HIGH";
} else {
chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
gchip->label = "SM501-LOW";
}
gchip->base = base;
chip->ourgpio = gpio;
return gpiochip_add_data(gchip, chip);
}
static int sm501_register_gpio(struct sm501_devdata *sm)
{
struct sm501_gpio *gpio = &sm->gpio;
resource_size_t iobase = sm->io_res->start + SM501_GPIO;
int ret;
dev_dbg(sm->dev, "registering gpio block %08llx\n",
(unsigned long long)iobase);
spin_lock_init(&gpio->lock);
gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
if (!gpio->regs_res) {
dev_err(sm->dev, "gpio: failed to request region\n");
return -ENXIO;
}
gpio->regs = ioremap(iobase, 0x20);
if (!gpio->regs) {
dev_err(sm->dev, "gpio: failed to remap registers\n");
ret = -ENXIO;
goto err_claimed;
}
/* Register both our chips. */
ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
if (ret) {
dev_err(sm->dev, "failed to add low chip\n");
goto err_mapped;
}
ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
if (ret) {
dev_err(sm->dev, "failed to add high chip\n");
goto err_low_chip;
}
gpio->registered = 1;
return 0;
err_low_chip:
gpiochip_remove(&gpio->low.gpio);
err_mapped:
iounmap(gpio->regs);
err_claimed:
release_mem_region(iobase, 0x20);
return ret;
}
static void sm501_gpio_remove(struct sm501_devdata *sm)
{
struct sm501_gpio *gpio = &sm->gpio;
resource_size_t iobase = sm->io_res->start + SM501_GPIO;
if (!sm->gpio.registered)
return;
gpiochip_remove(&gpio->low.gpio);
gpiochip_remove(&gpio->high.gpio);
iounmap(gpio->regs);
release_mem_region(iobase, 0x20);
}
static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
{
return sm->gpio.registered;
}
#else
static inline int sm501_register_gpio(struct sm501_devdata *sm)
{
return 0;
}
static inline void sm501_gpio_remove(struct sm501_devdata *sm)
{
}
static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
{
return 0;
}
#endif
static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
struct sm501_platdata_gpio_i2c *iic)
{
struct i2c_gpio_platform_data *icd;
struct platform_device *pdev;
struct gpiod_lookup_table *lookup;
pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
sizeof(struct i2c_gpio_platform_data));
if (!pdev)
return -ENOMEM;
/* Create a gpiod lookup using gpiochip-local offsets */
lookup = devm_kzalloc(&pdev->dev, struct_size(lookup, table, 3),
GFP_KERNEL);
if (!lookup)
return -ENOMEM;
lookup->dev_id = "i2c-gpio";
lookup->table[0] = (struct gpiod_lookup)
GPIO_LOOKUP_IDX(iic->pin_sda < 32 ? "SM501-LOW" : "SM501-HIGH",
iic->pin_sda % 32, NULL, 0,
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN);
lookup->table[1] = (struct gpiod_lookup)
GPIO_LOOKUP_IDX(iic->pin_scl < 32 ? "SM501-LOW" : "SM501-HIGH",
iic->pin_scl % 32, NULL, 1,
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN);
gpiod_add_lookup_table(lookup);
icd = dev_get_platdata(&pdev->dev);
icd->timeout = iic->timeout;
icd->udelay = iic->udelay;
/* note, we can't use either of the pin numbers, as the i2c-gpio
* driver uses the platform.id field to generate the bus number
* to register with the i2c core; The i2c core doesn't have enough
* entries to deal with anything we currently use.
*/
pdev->id = iic->bus_num;
dev_info(sm->dev, "registering i2c-%d: sda=%d, scl=%d\n",
iic->bus_num,
iic->pin_sda, iic->pin_scl);
return sm501_register_device(sm, pdev);
}
static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
struct sm501_platdata *pdata)
{
struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
int index;
int ret;
for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
ret = sm501_register_gpio_i2c_instance(sm, iic);
if (ret < 0)
return ret;
}
return 0;
}
/* dbg_regs_show
*
* Debug attribute to attach to parent device to show core registers
*/
static ssize_t dbg_regs_show(struct device *dev,
struct device_attribute *attr, char *buff)
{
struct sm501_devdata *sm = dev_get_drvdata(dev) ;
unsigned int reg;
char *ptr = buff;
int ret;
for (reg = 0x00; reg < 0x70; reg += 4) {
ret = sprintf(ptr, "%08x = %08x\n",
reg, smc501_readl(sm->regs + reg));
ptr += ret;
}
return ptr - buff;
}
static DEVICE_ATTR_RO(dbg_regs);
/* sm501_init_reg
*
* Helper function for the init code to setup a register
*
* clear the bits which are set in r->mask, and then set
* the bits set in r->set.
*/
static inline void sm501_init_reg(struct sm501_devdata *sm,
unsigned long reg,
struct sm501_reg_init *r)
{
unsigned long tmp;
tmp = smc501_readl(sm->regs + reg);
tmp &= ~r->mask;
tmp |= r->set;
smc501_writel(tmp, sm->regs + reg);
}
/* sm501_init_regs
*
* Setup core register values
*/
static void sm501_init_regs(struct sm501_devdata *sm,
struct sm501_initdata *init)
{
sm501_misc_control(sm->dev,
init->misc_control.set,
init->misc_control.mask);
sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
if (init->m1xclk) {
dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
}
if (init->mclk) {
dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
}
}
/* Check the PLL sources for the M1CLK and M1XCLK
*
* If the M1CLK and M1XCLKs are not sourced from the same PLL, then
* there is a risk (see errata AB-5) that the SM501 will cease proper
* function. If this happens, then it is likely the SM501 will
* hang the system.
*/
static int sm501_check_clocks(struct sm501_devdata *sm)
{
unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
}
static unsigned int sm501_mem_local[] = {
[0] = 4*1024*1024,
[1] = 8*1024*1024,
[2] = 16*1024*1024,
[3] = 32*1024*1024,
[4] = 64*1024*1024,
[5] = 2*1024*1024,
};
/* sm501_init_dev
*
* Common init code for an SM501
*/
static int sm501_init_dev(struct sm501_devdata *sm)
{
struct sm501_initdata *idata;
struct sm501_platdata *pdata;
resource_size_t mem_avail;
unsigned long dramctrl;
unsigned long devid;
int ret;
mutex_init(&sm->clock_lock);
spin_lock_init(&sm->reg_lock);
INIT_LIST_HEAD(&sm->devices);
devid = smc501_readl(sm->regs + SM501_DEVICEID);
if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
dev_err(sm->dev, "incorrect device id %08lx\n", devid);
return -EINVAL;
}
/* disable irqs */
smc501_writel(0, sm->regs + SM501_IRQ_MASK);
dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL);
mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
sm->rev = devid & SM501_DEVICEID_REVMASK;
sm501_dump_gate(sm);
ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
if (ret)
dev_err(sm->dev, "failed to create debug regs file\n");
sm501_dump_clk(sm);
/* check to see if we have some device initialisation */
pdata = sm->platdata;
idata = pdata ? pdata->init : NULL;
if (idata) {
sm501_init_regs(sm, idata);
if (idata->devices & SM501_USE_USB_HOST)
sm501_register_usbhost(sm, &mem_avail);
if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
sm501_register_uart(sm, idata->devices);
if (idata->devices & SM501_USE_GPIO)
sm501_register_gpio(sm);
}
if (pdata && pdata->gpio_i2c && pdata->gpio_i2c_nr > 0) {
if (!sm501_gpio_isregistered(sm))
dev_err(sm->dev, "no gpio available for i2c gpio.\n");
else
sm501_register_gpio_i2c(sm, pdata);
}
ret = sm501_check_clocks(sm);
if (ret) {
dev_err(sm->dev, "M1X and M clocks sourced from different "
"PLLs\n");
return -EINVAL;
}
/* always create a framebuffer */
sm501_register_display(sm, &mem_avail);
return 0;
}
static int sm501_plat_probe(struct platform_device *dev)
{
struct sm501_devdata *sm;
int ret;
sm = kzalloc(sizeof(*sm), GFP_KERNEL);
if (!sm) {
ret = -ENOMEM;
goto err1;
}
sm->dev = &dev->dev;
sm->pdev_id = dev->id;
sm->platdata = dev_get_platdata(&dev->dev);
ret = platform_get_irq(dev, 0);
if (ret < 0)
goto err_res;
sm->irq = ret;
sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
if (!sm->io_res || !sm->mem_res) {
dev_err(&dev->dev, "failed to get IO resource\n");
ret = -ENOENT;
goto err_res;
}
sm->regs_claim = request_mem_region(sm->io_res->start,
0x100, "sm501");
if (!sm->regs_claim) {
dev_err(&dev->dev, "cannot claim registers\n");
ret = -EBUSY;
goto err_res;
}
platform_set_drvdata(dev, sm);
sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
if (!sm->regs) {
dev_err(&dev->dev, "cannot remap registers\n");
ret = -EIO;
goto err_claim;
}
ret = sm501_init_dev(sm);
if (ret)
goto err_unmap;
return 0;
err_unmap:
iounmap(sm->regs);
err_claim:
release_mem_region(sm->io_res->start, 0x100);
err_res:
kfree(sm);
err1:
return ret;
}
/* power management support */
static void sm501_set_power(struct sm501_devdata *sm, int on)
{
struct sm501_platdata *pd = sm->platdata;
if (!pd)
return;
if (pd->get_power) {
if (pd->get_power(sm->dev) == on) {
dev_dbg(sm->dev, "is already %d\n", on);
return;
}
}
if (pd->set_power) {
dev_dbg(sm->dev, "setting power to %d\n", on);
pd->set_power(sm->dev, on);
sm501_mdelay(sm, 10);
}
}
static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
{
struct sm501_devdata *sm = platform_get_drvdata(pdev);
sm->in_suspend = 1;
sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
sm501_dump_regs(sm);
if (sm->platdata) {
if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
sm501_set_power(sm, 0);
}
return 0;
}
static int sm501_plat_resume(struct platform_device *pdev)
{
struct sm501_devdata *sm = platform_get_drvdata(pdev);
sm501_set_power(sm, 1);
sm501_dump_regs(sm);
sm501_dump_gate(sm);
sm501_dump_clk(sm);
/* check to see if we are in the same state as when suspended */
if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
/* our suspend causes the controller state to change,
* either by something attempting setup, power loss,
* or an external reset event on power change */
if (sm->platdata && sm->platdata->init) {
sm501_init_regs(sm, sm->platdata->init);
}
}
/* dump our state from resume */
sm501_dump_regs(sm);
sm501_dump_clk(sm);
sm->in_suspend = 0;
return 0;
}
/* Initialisation data for PCI devices */
static struct sm501_initdata sm501_pci_initdata = {
.gpio_high = {
.set = 0x3F000000, /* 24bit panel */
.mask = 0x0,
},
.misc_timing = {
.set = 0x010100, /* SDRAM timing */
.mask = 0x1F1F00,
},
.misc_control = {
.set = SM501_MISC_PNL_24BIT,
.mask = 0,
},
.devices = SM501_USE_ALL,
/* Errata AB-3 says that 72MHz is the fastest available
* for 33MHZ PCI with proper bus-mastering operation */
.mclk = 72 * MHZ,
.m1xclk = 144 * MHZ,
};
static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
.flags = (SM501FB_FLAG_USE_INIT_MODE |
SM501FB_FLAG_USE_HWCURSOR |
SM501FB_FLAG_USE_HWACCEL |
SM501FB_FLAG_DISABLE_AT_EXIT),
};
static struct sm501_platdata_fb sm501_fb_pdata = {
.fb_route = SM501_FB_OWN,
.fb_crt = &sm501_pdata_fbsub,
.fb_pnl = &sm501_pdata_fbsub,
};
static struct sm501_platdata sm501_pci_platdata = {
.init = &sm501_pci_initdata,
.fb = &sm501_fb_pdata,
.gpio_base = -1,
};
static int sm501_pci_probe(struct pci_dev *dev,
const struct pci_device_id *id)
{
struct sm501_devdata *sm;
int err;
sm = kzalloc(sizeof(*sm), GFP_KERNEL);
if (!sm) {
err = -ENOMEM;
goto err1;
}
/* set a default set of platform data */
dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
/* set a hopefully unique id for our child platform devices */
sm->pdev_id = 32 + dev->devfn;
pci_set_drvdata(dev, sm);
err = pci_enable_device(dev);
if (err) {
dev_err(&dev->dev, "cannot enable device\n");
goto err2;
}
sm->dev = &dev->dev;
sm->irq = dev->irq;
#ifdef __BIG_ENDIAN
/* if the system is big-endian, we most probably have a
* translation in the IO layer making the PCI bus little endian
* so make the framebuffer swapped pixels */
sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
#endif
/* check our resources */
if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
dev_err(&dev->dev, "region #0 is not memory?\n");
err = -EINVAL;
goto err3;
}
if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
dev_err(&dev->dev, "region #1 is not memory?\n");
err = -EINVAL;
goto err3;
}
/* make our resources ready for sharing */
sm->io_res = &dev->resource[1];
sm->mem_res = &dev->resource[0];
sm->regs_claim = request_mem_region(sm->io_res->start,
0x100, "sm501");
if (!sm->regs_claim) {
dev_err(&dev->dev, "cannot claim registers\n");
err= -EBUSY;
goto err3;
}
sm->regs = pci_ioremap_bar(dev, 1);
if (!sm->regs) {
dev_err(&dev->dev, "cannot remap registers\n");
err = -EIO;
goto err4;
}
sm501_init_dev(sm);
return 0;
err4:
release_mem_region(sm->io_res->start, 0x100);
err3:
pci_disable_device(dev);
err2:
kfree(sm);
err1:
return err;
}
static void sm501_remove_sub(struct sm501_devdata *sm,
struct sm501_device *smdev)
{
list_del(&smdev->list);
platform_device_unregister(&smdev->pdev);
}
static void sm501_dev_remove(struct sm501_devdata *sm)
{
struct sm501_device *smdev, *tmp;
list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
sm501_remove_sub(sm, smdev);
device_remove_file(sm->dev, &dev_attr_dbg_regs);
sm501_gpio_remove(sm);
}
static void sm501_pci_remove(struct pci_dev *dev)
{
struct sm501_devdata *sm = pci_get_drvdata(dev);
sm501_dev_remove(sm);
iounmap(sm->regs);
release_mem_region(sm->io_res->start, 0x100);
pci_disable_device(dev);
}
static int sm501_plat_remove(struct platform_device *dev)
{
struct sm501_devdata *sm = platform_get_drvdata(dev);
sm501_dev_remove(sm);
iounmap(sm->regs);
release_mem_region(sm->io_res->start, 0x100);
return 0;
}
static const struct pci_device_id sm501_pci_tbl[] = {
{ 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
static struct pci_driver sm501_pci_driver = {
.name = "sm501",
.id_table = sm501_pci_tbl,
.probe = sm501_pci_probe,
.remove = sm501_pci_remove,
};
MODULE_ALIAS("platform:sm501");
static const struct of_device_id of_sm501_match_tbl[] = {
{ .compatible = "smi,sm501", },
{ /* end */ }
};
MODULE_DEVICE_TABLE(of, of_sm501_match_tbl);
static struct platform_driver sm501_plat_driver = {
.driver = {
.name = "sm501",
.of_match_table = of_sm501_match_tbl,
},
.probe = sm501_plat_probe,
.remove = sm501_plat_remove,
.suspend = pm_sleep_ptr(sm501_plat_suspend),
.resume = pm_sleep_ptr(sm501_plat_resume),
};
static int __init sm501_base_init(void)
{
int ret;
ret = platform_driver_register(&sm501_plat_driver);
if (ret < 0)
return ret;
return pci_register_driver(&sm501_pci_driver);
}
static void __exit sm501_base_exit(void)
{
platform_driver_unregister(&sm501_plat_driver);
pci_unregister_driver(&sm501_pci_driver);
}
module_init(sm501_base_init);
module_exit(sm501_base_exit);
MODULE_DESCRIPTION("SM501 Core Driver");
MODULE_AUTHOR("Ben Dooks <[email protected]>, Vincent Sanders");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/sm501.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI LP8788 MFD - core interface
*
* Copyright 2012 Texas Instruments
*
* Author: Milo(Woogyom) Kim <[email protected]>
*/
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#include <linux/mfd/lp8788.h>
#include <linux/module.h>
#include <linux/slab.h>
#define MAX_LP8788_REGISTERS 0xA2
#define MFD_DEV_SIMPLE(_name) \
{ \
.name = LP8788_DEV_##_name, \
}
#define MFD_DEV_WITH_ID(_name, _id) \
{ \
.name = LP8788_DEV_##_name, \
.id = _id, \
}
#define MFD_DEV_WITH_RESOURCE(_name, _resource, num_resource) \
{ \
.name = LP8788_DEV_##_name, \
.resources = _resource, \
.num_resources = num_resource, \
}
static const struct resource chg_irqs[] = {
/* Charger Interrupts */
{
.start = LP8788_INT_CHG_INPUT_STATE,
.end = LP8788_INT_PRECHG_TIMEOUT,
.name = LP8788_CHG_IRQ,
.flags = IORESOURCE_IRQ,
},
/* Power Routing Switch Interrupts */
{
.start = LP8788_INT_ENTER_SYS_SUPPORT,
.end = LP8788_INT_EXIT_SYS_SUPPORT,
.name = LP8788_PRSW_IRQ,
.flags = IORESOURCE_IRQ,
},
/* Battery Interrupts */
{
.start = LP8788_INT_BATT_LOW,
.end = LP8788_INT_NO_BATT,
.name = LP8788_BATT_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static const struct resource rtc_irqs[] = {
{
.start = LP8788_INT_RTC_ALARM1,
.end = LP8788_INT_RTC_ALARM2,
.name = LP8788_ALM_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static const struct mfd_cell lp8788_devs[] = {
/* 4 bucks */
MFD_DEV_WITH_ID(BUCK, 1),
MFD_DEV_WITH_ID(BUCK, 2),
MFD_DEV_WITH_ID(BUCK, 3),
MFD_DEV_WITH_ID(BUCK, 4),
/* 12 digital ldos */
MFD_DEV_WITH_ID(DLDO, 1),
MFD_DEV_WITH_ID(DLDO, 2),
MFD_DEV_WITH_ID(DLDO, 3),
MFD_DEV_WITH_ID(DLDO, 4),
MFD_DEV_WITH_ID(DLDO, 5),
MFD_DEV_WITH_ID(DLDO, 6),
MFD_DEV_WITH_ID(DLDO, 7),
MFD_DEV_WITH_ID(DLDO, 8),
MFD_DEV_WITH_ID(DLDO, 9),
MFD_DEV_WITH_ID(DLDO, 10),
MFD_DEV_WITH_ID(DLDO, 11),
MFD_DEV_WITH_ID(DLDO, 12),
/* 10 analog ldos */
MFD_DEV_WITH_ID(ALDO, 1),
MFD_DEV_WITH_ID(ALDO, 2),
MFD_DEV_WITH_ID(ALDO, 3),
MFD_DEV_WITH_ID(ALDO, 4),
MFD_DEV_WITH_ID(ALDO, 5),
MFD_DEV_WITH_ID(ALDO, 6),
MFD_DEV_WITH_ID(ALDO, 7),
MFD_DEV_WITH_ID(ALDO, 8),
MFD_DEV_WITH_ID(ALDO, 9),
MFD_DEV_WITH_ID(ALDO, 10),
/* ADC */
MFD_DEV_SIMPLE(ADC),
/* battery charger */
MFD_DEV_WITH_RESOURCE(CHARGER, chg_irqs, ARRAY_SIZE(chg_irqs)),
/* rtc */
MFD_DEV_WITH_RESOURCE(RTC, rtc_irqs, ARRAY_SIZE(rtc_irqs)),
/* backlight */
MFD_DEV_SIMPLE(BACKLIGHT),
/* current sink for vibrator */
MFD_DEV_SIMPLE(VIBRATOR),
/* current sink for keypad LED */
MFD_DEV_SIMPLE(KEYLED),
};
int lp8788_read_byte(struct lp8788 *lp, u8 reg, u8 *data)
{
int ret;
unsigned int val;
ret = regmap_read(lp->regmap, reg, &val);
if (ret < 0) {
dev_err(lp->dev, "failed to read 0x%.2x\n", reg);
return ret;
}
*data = (u8)val;
return 0;
}
EXPORT_SYMBOL_GPL(lp8788_read_byte);
int lp8788_read_multi_bytes(struct lp8788 *lp, u8 reg, u8 *data, size_t count)
{
return regmap_bulk_read(lp->regmap, reg, data, count);
}
EXPORT_SYMBOL_GPL(lp8788_read_multi_bytes);
int lp8788_write_byte(struct lp8788 *lp, u8 reg, u8 data)
{
return regmap_write(lp->regmap, reg, data);
}
EXPORT_SYMBOL_GPL(lp8788_write_byte);
int lp8788_update_bits(struct lp8788 *lp, u8 reg, u8 mask, u8 data)
{
return regmap_update_bits(lp->regmap, reg, mask, data);
}
EXPORT_SYMBOL_GPL(lp8788_update_bits);
static int lp8788_platform_init(struct lp8788 *lp)
{
struct lp8788_platform_data *pdata = lp->pdata;
return (pdata && pdata->init_func) ? pdata->init_func(lp) : 0;
}
static const struct regmap_config lp8788_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = MAX_LP8788_REGISTERS,
};
static int lp8788_probe(struct i2c_client *cl)
{
struct lp8788 *lp;
struct lp8788_platform_data *pdata = dev_get_platdata(&cl->dev);
int ret;
lp = devm_kzalloc(&cl->dev, sizeof(struct lp8788), GFP_KERNEL);
if (!lp)
return -ENOMEM;
lp->regmap = devm_regmap_init_i2c(cl, &lp8788_regmap_config);
if (IS_ERR(lp->regmap)) {
ret = PTR_ERR(lp->regmap);
dev_err(&cl->dev, "regmap init i2c err: %d\n", ret);
return ret;
}
lp->pdata = pdata;
lp->dev = &cl->dev;
i2c_set_clientdata(cl, lp);
ret = lp8788_platform_init(lp);
if (ret)
return ret;
ret = lp8788_irq_init(lp, cl->irq);
if (ret)
return ret;
ret = mfd_add_devices(lp->dev, -1, lp8788_devs,
ARRAY_SIZE(lp8788_devs), NULL, 0, NULL);
if (ret)
goto err_exit_irq;
return 0;
err_exit_irq:
lp8788_irq_exit(lp);
return ret;
}
static void lp8788_remove(struct i2c_client *cl)
{
struct lp8788 *lp = i2c_get_clientdata(cl);
mfd_remove_devices(lp->dev);
lp8788_irq_exit(lp);
}
static const struct i2c_device_id lp8788_ids[] = {
{"lp8788", 0},
{ }
};
MODULE_DEVICE_TABLE(i2c, lp8788_ids);
static struct i2c_driver lp8788_driver = {
.driver = {
.name = "lp8788",
},
.probe = lp8788_probe,
.remove = lp8788_remove,
.id_table = lp8788_ids,
};
static int __init lp8788_init(void)
{
return i2c_add_driver(&lp8788_driver);
}
subsys_initcall(lp8788_init);
static void __exit lp8788_exit(void)
{
i2c_del_driver(&lp8788_driver);
}
module_exit(lp8788_exit);
MODULE_DESCRIPTION("TI LP8788 MFD Driver");
MODULE_AUTHOR("Milo Kim");
| linux-master | drivers/mfd/lp8788.c |
// SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0-or-later
/*
* ENE KB3930 Embedded Controller Driver
*
* Copyright (C) 2020 Lubomir Rintel
*/
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
/* I2C registers that are multiplexing access to the EC RAM. */
enum {
EC_DATA_IN = 0x00,
EC_RAM_OUT = 0x80,
EC_RAM_IN = 0x81,
};
/* EC RAM registers. */
enum {
EC_MODEL = 0x30,
EC_VERSION_MAJ = 0x31,
EC_VERSION_MIN = 0x32,
};
struct kb3930 {
struct i2c_client *client;
struct regmap *ram_regmap;
struct gpio_descs *off_gpios;
};
static struct kb3930 *kb3930_power_off;
#define EC_GPIO_WAVE 0
#define EC_GPIO_OFF_MODE 1
#define EC_OFF_MODE_REBOOT 0
#define EC_OFF_MODE_POWER 1
static void kb3930_off(struct kb3930 *ddata, int off_mode)
{
gpiod_direction_output(ddata->off_gpios->desc[EC_GPIO_OFF_MODE],
off_mode);
/*
* This creates a 10 Hz wave on EC_GPIO_WAVE that signals a
* shutdown request to the EC. Once the EC detects it, it will
* proceed to turn the power off or reset the board depending on
* the value of EC_GPIO_OFF_MODE.
*/
while (1) {
mdelay(50);
gpiod_direction_output(ddata->off_gpios->desc[EC_GPIO_WAVE], 0);
mdelay(50);
gpiod_direction_output(ddata->off_gpios->desc[EC_GPIO_WAVE], 1);
}
}
static int kb3930_restart(struct notifier_block *this,
unsigned long mode, void *cmd)
{
kb3930_off(kb3930_power_off, EC_OFF_MODE_REBOOT);
return NOTIFY_DONE;
}
static void kb3930_pm_power_off(void)
{
kb3930_off(kb3930_power_off, EC_OFF_MODE_POWER);
}
static struct notifier_block kb3930_restart_nb = {
.notifier_call = kb3930_restart,
};
static const struct mfd_cell ariel_ec_cells[] = {
{ .name = "dell-wyse-ariel-led", },
{ .name = "dell-wyse-ariel-power", },
};
static int kb3930_ec_ram_reg_write(void *context, unsigned int reg,
unsigned int val)
{
struct kb3930 *ddata = context;
return i2c_smbus_write_word_data(ddata->client, EC_RAM_OUT,
(val << 8) | reg);
}
static int kb3930_ec_ram_reg_read(void *context, unsigned int reg,
unsigned int *val)
{
struct kb3930 *ddata = context;
int ret;
ret = i2c_smbus_write_word_data(ddata->client, EC_RAM_IN, reg);
if (ret < 0)
return ret;
ret = i2c_smbus_read_word_data(ddata->client, EC_DATA_IN);
if (ret < 0)
return ret;
*val = ret >> 8;
return 0;
}
static const struct regmap_config kb3930_ram_regmap_config = {
.name = "ec_ram",
.reg_bits = 8,
.val_bits = 8,
.reg_stride = 1,
.max_register = 0xff,
.reg_write = kb3930_ec_ram_reg_write,
.reg_read = kb3930_ec_ram_reg_read,
.fast_io = false,
};
static int kb3930_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct device_node *np = dev->of_node;
struct kb3930 *ddata;
unsigned int model;
int ret;
ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
kb3930_power_off = ddata;
ddata->client = client;
i2c_set_clientdata(client, ddata);
ddata->ram_regmap = devm_regmap_init(dev, NULL, ddata,
&kb3930_ram_regmap_config);
if (IS_ERR(ddata->ram_regmap))
return PTR_ERR(ddata->ram_regmap);
ret = regmap_read(ddata->ram_regmap, EC_MODEL, &model);
if (ret < 0)
return ret;
/* Currently we only support the cells present on Dell Ariel model. */
if (model != 'J') {
dev_err(dev, "unknown board model: %02x\n", model);
return -ENODEV;
}
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO,
ariel_ec_cells,
ARRAY_SIZE(ariel_ec_cells),
NULL, 0, NULL);
if (ret)
return ret;
if (of_property_read_bool(np, "system-power-controller")) {
ddata->off_gpios =
devm_gpiod_get_array_optional(dev, "off", GPIOD_IN);
if (IS_ERR(ddata->off_gpios))
return PTR_ERR(ddata->off_gpios);
if (ddata->off_gpios->ndescs < 2) {
dev_err(dev, "invalid off-gpios property\n");
return -EINVAL;
}
}
if (ddata->off_gpios) {
register_restart_handler(&kb3930_restart_nb);
if (!pm_power_off)
pm_power_off = kb3930_pm_power_off;
}
return 0;
}
static void kb3930_remove(struct i2c_client *client)
{
struct kb3930 *ddata = i2c_get_clientdata(client);
if (ddata->off_gpios) {
if (pm_power_off == kb3930_pm_power_off)
pm_power_off = NULL;
unregister_restart_handler(&kb3930_restart_nb);
}
kb3930_power_off = NULL;
}
static const struct of_device_id kb3930_dt_ids[] = {
{ .compatible = "ene,kb3930" },
{ }
};
MODULE_DEVICE_TABLE(of, kb3930_dt_ids);
static struct i2c_driver kb3930_driver = {
.probe = kb3930_probe,
.remove = kb3930_remove,
.driver = {
.name = "ene-kb3930",
.of_match_table = kb3930_dt_ids,
},
};
module_i2c_driver(kb3930_driver);
MODULE_AUTHOR("Lubomir Rintel <[email protected]>");
MODULE_DESCRIPTION("ENE KB3930 Embedded Controller Driver");
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | drivers/mfd/ene-kb3930.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 MediaTek Inc.
*
* Author: Gene Chen <[email protected]>
*/
#include <linux/crc8.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
enum {
MT6360_SLAVE_TCPC = 0,
MT6360_SLAVE_PMIC,
MT6360_SLAVE_LDO,
MT6360_SLAVE_PMU,
MT6360_SLAVE_MAX,
};
struct mt6360_ddata {
struct i2c_client *i2c[MT6360_SLAVE_MAX];
struct device *dev;
struct regmap *regmap;
struct regmap_irq_chip_data *irq_data;
unsigned int chip_rev;
u8 crc8_tbl[CRC8_TABLE_SIZE];
};
#define MT6360_TCPC_SLAVEID 0x4E
#define MT6360_PMIC_SLAVEID 0x1A
#define MT6360_LDO_SLAVEID 0x64
#define MT6360_PMU_SLAVEID 0x34
#define MT6360_REG_TCPCSTART 0x00
#define MT6360_REG_TCPCEND 0xFF
#define MT6360_REG_PMICSTART 0x100
#define MT6360_REG_PMICEND 0x13B
#define MT6360_REG_LDOSTART 0x200
#define MT6360_REG_LDOEND 0x21C
#define MT6360_REG_PMUSTART 0x300
#define MT6360_PMU_DEV_INFO 0x300
#define MT6360_PMU_CHG_IRQ1 0x3D0
#define MT6360_PMU_CHG_MASK1 0x3F0
#define MT6360_REG_PMUEND 0x3FF
#define MT6360_PMU_IRQ_REGNUM 16
#define CHIP_VEN_MASK 0xF0
#define CHIP_VEN_MT6360 0x50
#define CHIP_REV_MASK 0x0F
#define MT6360_ADDRESS_MASK 0x3F
#define MT6360_DATA_SIZE_1_BYTE 0x00
#define MT6360_DATA_SIZE_2_BYTES 0x40
#define MT6360_DATA_SIZE_3_BYTES 0x80
#define MT6360_DATA_SIZE_4_BYTES 0xC0
#define MT6360_CRC8_POLYNOMIAL 0x7
#define MT6360_CRC_I2C_ADDR_SIZE 1
#define MT6360_CRC_REG_ADDR_SIZE 1
/* prealloca read size = i2c device addr + i2c reg addr + val ... + crc8 */
#define MT6360_ALLOC_READ_SIZE(_size) (_size + 3)
/* prealloca write size = i2c device addr + i2c reg addr + val ... + crc8 + dummy byte */
#define MT6360_ALLOC_WRITE_SIZE(_size) (_size + 4)
#define MT6360_CRC_PREDATA_OFFSET (MT6360_CRC_I2C_ADDR_SIZE + MT6360_CRC_REG_ADDR_SIZE)
#define MT6360_CRC_CRC8_SIZE 1
#define MT6360_CRC_DUMMY_BYTE_SIZE 1
#define MT6360_REGMAP_REG_BYTE_SIZE 2
#define I2C_ADDR_XLATE_8BIT(_addr, _rw) (((_addr & 0x7F) << 1) + _rw)
/* reg 0 -> 0 ~ 7 */
#define MT6360_CHG_TREG_EVT 4
#define MT6360_CHG_AICR_EVT 5
#define MT6360_CHG_MIVR_EVT 6
#define MT6360_PWR_RDY_EVT 7
/* REG 1 -> 8 ~ 15 */
#define MT6360_CHG_BATSYSUV_EVT 9
#define MT6360_FLED_CHG_VINOVP_EVT 11
#define MT6360_CHG_VSYSUV_EVT 12
#define MT6360_CHG_VSYSOV_EVT 13
#define MT6360_CHG_VBATOV_EVT 14
#define MT6360_CHG_VBUSOV_EVT 15
/* REG 2 -> 16 ~ 23 */
/* REG 3 -> 24 ~ 31 */
#define MT6360_WD_PMU_DET 25
#define MT6360_WD_PMU_DONE 26
#define MT6360_CHG_TMRI 27
#define MT6360_CHG_ADPBADI 29
#define MT6360_CHG_RVPI 30
#define MT6360_OTPI 31
/* REG 4 -> 32 ~ 39 */
#define MT6360_CHG_AICCMEASL 32
#define MT6360_CHGDET_DONEI 34
#define MT6360_WDTMRI 35
#define MT6360_SSFINISHI 36
#define MT6360_CHG_RECHGI 37
#define MT6360_CHG_TERMI 38
#define MT6360_CHG_IEOCI 39
/* REG 5 -> 40 ~ 47 */
#define MT6360_PUMPX_DONEI 40
#define MT6360_BAT_OVP_ADC_EVT 41
#define MT6360_TYPEC_OTP_EVT 42
#define MT6360_ADC_WAKEUP_EVT 43
#define MT6360_ADC_DONEI 44
#define MT6360_BST_BATUVI 45
#define MT6360_BST_VBUSOVI 46
#define MT6360_BST_OLPI 47
/* REG 6 -> 48 ~ 55 */
#define MT6360_ATTACH_I 48
#define MT6360_DETACH_I 49
#define MT6360_QC30_STPDONE 51
#define MT6360_QC_VBUSDET_DONE 52
#define MT6360_HVDCP_DET 53
#define MT6360_CHGDETI 54
#define MT6360_DCDTI 55
/* REG 7 -> 56 ~ 63 */
#define MT6360_FOD_DONE_EVT 56
#define MT6360_FOD_OV_EVT 57
#define MT6360_CHRDET_UVP_EVT 58
#define MT6360_CHRDET_OVP_EVT 59
#define MT6360_CHRDET_EXT_EVT 60
#define MT6360_FOD_LR_EVT 61
#define MT6360_FOD_HR_EVT 62
#define MT6360_FOD_DISCHG_FAIL_EVT 63
/* REG 8 -> 64 ~ 71 */
#define MT6360_USBID_EVT 64
#define MT6360_APWDTRST_EVT 65
#define MT6360_EN_EVT 66
#define MT6360_QONB_RST_EVT 67
#define MT6360_MRSTB_EVT 68
#define MT6360_OTP_EVT 69
#define MT6360_VDDAOV_EVT 70
#define MT6360_SYSUV_EVT 71
/* REG 9 -> 72 ~ 79 */
#define MT6360_FLED_STRBPIN_EVT 72
#define MT6360_FLED_TORPIN_EVT 73
#define MT6360_FLED_TX_EVT 74
#define MT6360_FLED_LVF_EVT 75
#define MT6360_FLED2_SHORT_EVT 78
#define MT6360_FLED1_SHORT_EVT 79
/* REG 10 -> 80 ~ 87 */
#define MT6360_FLED2_STRB_EVT 80
#define MT6360_FLED1_STRB_EVT 81
#define MT6360_FLED2_STRB_TO_EVT 82
#define MT6360_FLED1_STRB_TO_EVT 83
#define MT6360_FLED2_TOR_EVT 84
#define MT6360_FLED1_TOR_EVT 85
/* REG 11 -> 88 ~ 95 */
/* REG 12 -> 96 ~ 103 */
#define MT6360_BUCK1_PGB_EVT 96
#define MT6360_BUCK1_OC_EVT 100
#define MT6360_BUCK1_OV_EVT 101
#define MT6360_BUCK1_UV_EVT 102
/* REG 13 -> 104 ~ 111 */
#define MT6360_BUCK2_PGB_EVT 104
#define MT6360_BUCK2_OC_EVT 108
#define MT6360_BUCK2_OV_EVT 109
#define MT6360_BUCK2_UV_EVT 110
/* REG 14 -> 112 ~ 119 */
#define MT6360_LDO1_OC_EVT 113
#define MT6360_LDO2_OC_EVT 114
#define MT6360_LDO3_OC_EVT 115
#define MT6360_LDO5_OC_EVT 117
#define MT6360_LDO6_OC_EVT 118
#define MT6360_LDO7_OC_EVT 119
/* REG 15 -> 120 ~ 127 */
#define MT6360_LDO1_PGB_EVT 121
#define MT6360_LDO2_PGB_EVT 122
#define MT6360_LDO3_PGB_EVT 123
#define MT6360_LDO5_PGB_EVT 125
#define MT6360_LDO6_PGB_EVT 126
#define MT6360_LDO7_PGB_EVT 127
static const struct regmap_irq mt6360_irqs[] = {
REGMAP_IRQ_REG_LINE(MT6360_CHG_TREG_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHG_AICR_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHG_MIVR_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_PWR_RDY_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHG_BATSYSUV_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FLED_CHG_VINOVP_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHG_VSYSUV_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHG_VSYSOV_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHG_VBATOV_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHG_VBUSOV_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_WD_PMU_DET, 8),
REGMAP_IRQ_REG_LINE(MT6360_WD_PMU_DONE, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHG_TMRI, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHG_ADPBADI, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHG_RVPI, 8),
REGMAP_IRQ_REG_LINE(MT6360_OTPI, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHG_AICCMEASL, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHGDET_DONEI, 8),
REGMAP_IRQ_REG_LINE(MT6360_WDTMRI, 8),
REGMAP_IRQ_REG_LINE(MT6360_SSFINISHI, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHG_RECHGI, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHG_TERMI, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHG_IEOCI, 8),
REGMAP_IRQ_REG_LINE(MT6360_PUMPX_DONEI, 8),
REGMAP_IRQ_REG_LINE(MT6360_BAT_OVP_ADC_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_TYPEC_OTP_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_ADC_WAKEUP_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_ADC_DONEI, 8),
REGMAP_IRQ_REG_LINE(MT6360_BST_BATUVI, 8),
REGMAP_IRQ_REG_LINE(MT6360_BST_VBUSOVI, 8),
REGMAP_IRQ_REG_LINE(MT6360_BST_OLPI, 8),
REGMAP_IRQ_REG_LINE(MT6360_ATTACH_I, 8),
REGMAP_IRQ_REG_LINE(MT6360_DETACH_I, 8),
REGMAP_IRQ_REG_LINE(MT6360_QC30_STPDONE, 8),
REGMAP_IRQ_REG_LINE(MT6360_QC_VBUSDET_DONE, 8),
REGMAP_IRQ_REG_LINE(MT6360_HVDCP_DET, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHGDETI, 8),
REGMAP_IRQ_REG_LINE(MT6360_DCDTI, 8),
REGMAP_IRQ_REG_LINE(MT6360_FOD_DONE_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FOD_OV_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHRDET_UVP_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHRDET_OVP_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_CHRDET_EXT_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FOD_LR_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FOD_HR_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FOD_DISCHG_FAIL_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_USBID_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_APWDTRST_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_EN_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_QONB_RST_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_MRSTB_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_OTP_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_VDDAOV_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_SYSUV_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FLED_STRBPIN_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FLED_TORPIN_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FLED_TX_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FLED_LVF_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FLED2_SHORT_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FLED1_SHORT_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FLED2_STRB_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FLED1_STRB_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FLED2_STRB_TO_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FLED1_STRB_TO_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FLED2_TOR_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_FLED1_TOR_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_BUCK1_PGB_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_BUCK1_OC_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_BUCK1_OV_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_BUCK1_UV_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_BUCK2_PGB_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_BUCK2_OC_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_BUCK2_OV_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_BUCK2_UV_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_LDO1_OC_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_LDO2_OC_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_LDO3_OC_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_LDO5_OC_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_LDO6_OC_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_LDO7_OC_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_LDO1_PGB_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_LDO2_PGB_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_LDO3_PGB_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_LDO5_PGB_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_LDO6_PGB_EVT, 8),
REGMAP_IRQ_REG_LINE(MT6360_LDO7_PGB_EVT, 8),
};
static const struct regmap_irq_chip mt6360_irq_chip = {
.name = "mt6360_irqs",
.irqs = mt6360_irqs,
.num_irqs = ARRAY_SIZE(mt6360_irqs),
.num_regs = MT6360_PMU_IRQ_REGNUM,
.mask_base = MT6360_PMU_CHG_MASK1,
.status_base = MT6360_PMU_CHG_IRQ1,
.ack_base = MT6360_PMU_CHG_IRQ1,
.init_ack_masked = true,
.use_ack = true,
};
static const struct resource mt6360_adc_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6360_ADC_DONEI, "adc_donei"),
};
static const struct resource mt6360_chg_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6360_CHG_TREG_EVT, "chg_treg_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_PWR_RDY_EVT, "pwr_rdy_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_CHG_BATSYSUV_EVT, "chg_batsysuv_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSUV_EVT, "chg_vsysuv_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSOV_EVT, "chg_vsysov_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBATOV_EVT, "chg_vbatov_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBUSOV_EVT, "chg_vbusov_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_CHG_AICCMEASL, "chg_aiccmeasl"),
DEFINE_RES_IRQ_NAMED(MT6360_WDTMRI, "wdtmri"),
DEFINE_RES_IRQ_NAMED(MT6360_CHG_RECHGI, "chg_rechgi"),
DEFINE_RES_IRQ_NAMED(MT6360_CHG_TERMI, "chg_termi"),
DEFINE_RES_IRQ_NAMED(MT6360_CHG_IEOCI, "chg_ieoci"),
DEFINE_RES_IRQ_NAMED(MT6360_PUMPX_DONEI, "pumpx_donei"),
DEFINE_RES_IRQ_NAMED(MT6360_ATTACH_I, "attach_i"),
DEFINE_RES_IRQ_NAMED(MT6360_CHRDET_EXT_EVT, "chrdet_ext_evt"),
};
static const struct resource mt6360_led_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6360_FLED_CHG_VINOVP_EVT, "fled_chg_vinovp_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_FLED_LVF_EVT, "fled_lvf_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_FLED2_SHORT_EVT, "fled2_short_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_FLED1_SHORT_EVT, "fled1_short_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_FLED2_STRB_TO_EVT, "fled2_strb_to_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_FLED1_STRB_TO_EVT, "fled1_strb_to_evt"),
};
static const struct resource mt6360_regulator_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_PGB_EVT, "buck1_pgb_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OC_EVT, "buck1_oc_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OV_EVT, "buck1_ov_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_UV_EVT, "buck1_uv_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_PGB_EVT, "buck2_pgb_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OC_EVT, "buck2_oc_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OV_EVT, "buck2_ov_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_UV_EVT, "buck2_uv_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_LDO1_OC_EVT, "ldo1_oc_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_LDO2_OC_EVT, "ldo2_oc_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_LDO3_OC_EVT, "ldo3_oc_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_LDO5_OC_EVT, "ldo5_oc_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_LDO6_OC_EVT, "ldo6_oc_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_LDO7_OC_EVT, "ldo7_oc_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_LDO1_PGB_EVT, "ldo1_pgb_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_LDO2_PGB_EVT, "ldo2_pgb_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_LDO3_PGB_EVT, "ldo3_pgb_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_LDO5_PGB_EVT, "ldo5_pgb_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_LDO6_PGB_EVT, "ldo6_pgb_evt"),
DEFINE_RES_IRQ_NAMED(MT6360_LDO7_PGB_EVT, "ldo7_pgb_evt"),
};
static const struct mfd_cell mt6360_devs[] = {
MFD_CELL_OF("mt6360-adc", mt6360_adc_resources,
NULL, 0, 0, "mediatek,mt6360-adc"),
MFD_CELL_OF("mt6360-chg", mt6360_chg_resources,
NULL, 0, 0, "mediatek,mt6360-chg"),
MFD_CELL_OF("mt6360-led", mt6360_led_resources,
NULL, 0, 0, "mediatek,mt6360-led"),
MFD_CELL_RES("mt6360-regulator", mt6360_regulator_resources),
MFD_CELL_OF("mt6360-tcpc", NULL,
NULL, 0, 0, "mediatek,mt6360-tcpc"),
};
static int mt6360_check_vendor_info(struct mt6360_ddata *ddata)
{
u32 info;
int ret;
ret = regmap_read(ddata->regmap, MT6360_PMU_DEV_INFO, &info);
if (ret < 0)
return ret;
if ((info & CHIP_VEN_MASK) != CHIP_VEN_MT6360) {
dev_err(ddata->dev, "Device not supported\n");
return -ENODEV;
}
ddata->chip_rev = info & CHIP_REV_MASK;
return 0;
}
static const unsigned short mt6360_slave_addr[MT6360_SLAVE_MAX] = {
MT6360_TCPC_SLAVEID,
MT6360_PMIC_SLAVEID,
MT6360_LDO_SLAVEID,
MT6360_PMU_SLAVEID,
};
static int mt6360_xlate_pmicldo_addr(u8 *addr, int rw_size)
{
/* Address is already in encoded [5:0] */
*addr &= MT6360_ADDRESS_MASK;
switch (rw_size) {
case 1:
*addr |= MT6360_DATA_SIZE_1_BYTE;
break;
case 2:
*addr |= MT6360_DATA_SIZE_2_BYTES;
break;
case 3:
*addr |= MT6360_DATA_SIZE_3_BYTES;
break;
case 4:
*addr |= MT6360_DATA_SIZE_4_BYTES;
break;
default:
return -EINVAL;
}
return 0;
}
static int mt6360_regmap_read(void *context, const void *reg, size_t reg_size,
void *val, size_t val_size)
{
struct mt6360_ddata *ddata = context;
u8 bank = *(u8 *)reg;
u8 reg_addr = *(u8 *)(reg + 1);
struct i2c_client *i2c;
bool crc_needed = false;
u8 *buf;
int buf_len = MT6360_ALLOC_READ_SIZE(val_size);
int read_size = val_size;
u8 crc;
int ret;
if (bank >= MT6360_SLAVE_MAX)
return -EINVAL;
i2c = ddata->i2c[bank];
if (bank == MT6360_SLAVE_PMIC || bank == MT6360_SLAVE_LDO) {
crc_needed = true;
ret = mt6360_xlate_pmicldo_addr(®_addr, val_size);
if (ret < 0)
return ret;
read_size += MT6360_CRC_CRC8_SIZE;
}
buf = kzalloc(buf_len, GFP_KERNEL);
if (!buf)
return -ENOMEM;
buf[0] = I2C_ADDR_XLATE_8BIT(i2c->addr, I2C_SMBUS_READ);
buf[1] = reg_addr;
ret = i2c_smbus_read_i2c_block_data(i2c, reg_addr, read_size,
buf + MT6360_CRC_PREDATA_OFFSET);
if (ret < 0)
goto out;
else if (ret != read_size) {
ret = -EIO;
goto out;
}
if (crc_needed) {
crc = crc8(ddata->crc8_tbl, buf, val_size + MT6360_CRC_PREDATA_OFFSET, 0);
if (crc != buf[val_size + MT6360_CRC_PREDATA_OFFSET]) {
ret = -EIO;
goto out;
}
}
memcpy(val, buf + MT6360_CRC_PREDATA_OFFSET, val_size);
out:
kfree(buf);
return (ret < 0) ? ret : 0;
}
static int mt6360_regmap_write(void *context, const void *val, size_t val_size)
{
struct mt6360_ddata *ddata = context;
u8 bank = *(u8 *)val;
u8 reg_addr = *(u8 *)(val + 1);
struct i2c_client *i2c;
bool crc_needed = false;
u8 *buf;
int buf_len = MT6360_ALLOC_WRITE_SIZE(val_size);
int write_size = val_size - MT6360_REGMAP_REG_BYTE_SIZE;
int ret;
if (bank >= MT6360_SLAVE_MAX)
return -EINVAL;
i2c = ddata->i2c[bank];
if (bank == MT6360_SLAVE_PMIC || bank == MT6360_SLAVE_LDO) {
crc_needed = true;
ret = mt6360_xlate_pmicldo_addr(®_addr, val_size - MT6360_REGMAP_REG_BYTE_SIZE);
if (ret < 0)
return ret;
}
buf = kzalloc(buf_len, GFP_KERNEL);
if (!buf)
return -ENOMEM;
buf[0] = I2C_ADDR_XLATE_8BIT(i2c->addr, I2C_SMBUS_WRITE);
buf[1] = reg_addr;
memcpy(buf + MT6360_CRC_PREDATA_OFFSET, val + MT6360_REGMAP_REG_BYTE_SIZE, write_size);
if (crc_needed) {
buf[val_size] = crc8(ddata->crc8_tbl, buf, val_size, 0);
write_size += (MT6360_CRC_CRC8_SIZE + MT6360_CRC_DUMMY_BYTE_SIZE);
}
ret = i2c_smbus_write_i2c_block_data(i2c, reg_addr, write_size,
buf + MT6360_CRC_PREDATA_OFFSET);
kfree(buf);
return ret;
}
static const struct regmap_bus mt6360_regmap_bus = {
.read = mt6360_regmap_read,
.write = mt6360_regmap_write,
/* Due to PMIC and LDO CRC access size limit */
.max_raw_read = 4,
.max_raw_write = 4,
};
static bool mt6360_is_readwrite_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MT6360_REG_TCPCSTART ... MT6360_REG_TCPCEND:
fallthrough;
case MT6360_REG_PMICSTART ... MT6360_REG_PMICEND:
fallthrough;
case MT6360_REG_LDOSTART ... MT6360_REG_LDOEND:
fallthrough;
case MT6360_REG_PMUSTART ... MT6360_REG_PMUEND:
return true;
}
return false;
}
static const struct regmap_config mt6360_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.max_register = MT6360_REG_PMUEND,
.writeable_reg = mt6360_is_readwrite_reg,
.readable_reg = mt6360_is_readwrite_reg,
};
static int mt6360_probe(struct i2c_client *client)
{
struct mt6360_ddata *ddata;
int i, ret;
ddata = devm_kzalloc(&client->dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
ddata->dev = &client->dev;
i2c_set_clientdata(client, ddata);
for (i = 0; i < MT6360_SLAVE_MAX - 1; i++) {
ddata->i2c[i] = devm_i2c_new_dummy_device(&client->dev,
client->adapter,
mt6360_slave_addr[i]);
if (IS_ERR(ddata->i2c[i])) {
dev_err(&client->dev,
"Failed to get new dummy I2C device for address 0x%x",
mt6360_slave_addr[i]);
return PTR_ERR(ddata->i2c[i]);
}
}
ddata->i2c[MT6360_SLAVE_MAX - 1] = client;
crc8_populate_msb(ddata->crc8_tbl, MT6360_CRC8_POLYNOMIAL);
ddata->regmap = devm_regmap_init(ddata->dev, &mt6360_regmap_bus, ddata,
&mt6360_regmap_config);
if (IS_ERR(ddata->regmap)) {
dev_err(&client->dev, "Failed to register regmap\n");
return PTR_ERR(ddata->regmap);
}
ret = mt6360_check_vendor_info(ddata);
if (ret)
return ret;
ret = devm_regmap_add_irq_chip(&client->dev, ddata->regmap, client->irq,
0, 0, &mt6360_irq_chip,
&ddata->irq_data);
if (ret) {
dev_err(&client->dev, "Failed to add Regmap IRQ Chip\n");
return ret;
}
ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO,
mt6360_devs, ARRAY_SIZE(mt6360_devs), NULL,
0, regmap_irq_get_domain(ddata->irq_data));
if (ret) {
dev_err(&client->dev,
"Failed to register subordinate devices\n");
return ret;
}
return 0;
}
static int __maybe_unused mt6360_suspend(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
if (device_may_wakeup(dev))
enable_irq_wake(i2c->irq);
return 0;
}
static int __maybe_unused mt6360_resume(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
if (device_may_wakeup(dev))
disable_irq_wake(i2c->irq);
return 0;
}
static SIMPLE_DEV_PM_OPS(mt6360_pm_ops, mt6360_suspend, mt6360_resume);
static const struct of_device_id __maybe_unused mt6360_of_id[] = {
{ .compatible = "mediatek,mt6360", },
{},
};
MODULE_DEVICE_TABLE(of, mt6360_of_id);
static struct i2c_driver mt6360_driver = {
.driver = {
.name = "mt6360",
.pm = &mt6360_pm_ops,
.of_match_table = of_match_ptr(mt6360_of_id),
},
.probe = mt6360_probe,
};
module_i2c_driver(mt6360_driver);
MODULE_AUTHOR("Gene Chen <[email protected]>");
MODULE_DESCRIPTION("MT6360 I2C Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/mt6360-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014, Sony Mobile Communications AB.
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
* Author: Bjorn Andersson <[email protected]>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/mfd/qcom_rpm.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/clk.h>
#include <dt-bindings/mfd/qcom-rpm.h>
struct qcom_rpm_resource {
unsigned target_id;
unsigned status_id;
unsigned select_id;
unsigned size;
};
struct qcom_rpm_data {
u32 version;
const struct qcom_rpm_resource *resource_table;
unsigned int n_resources;
unsigned int req_ctx_off;
unsigned int req_sel_off;
unsigned int ack_ctx_off;
unsigned int ack_sel_off;
unsigned int req_sel_size;
unsigned int ack_sel_size;
};
struct qcom_rpm {
struct device *dev;
struct regmap *ipc_regmap;
unsigned ipc_offset;
unsigned ipc_bit;
struct clk *ramclk;
struct completion ack;
struct mutex lock;
void __iomem *status_regs;
void __iomem *ctrl_regs;
void __iomem *req_regs;
u32 ack_status;
const struct qcom_rpm_data *data;
};
#define RPM_STATUS_REG(rpm, i) ((rpm)->status_regs + (i) * 4)
#define RPM_CTRL_REG(rpm, i) ((rpm)->ctrl_regs + (i) * 4)
#define RPM_REQ_REG(rpm, i) ((rpm)->req_regs + (i) * 4)
#define RPM_REQUEST_TIMEOUT (5 * HZ)
#define RPM_MAX_SEL_SIZE 7
#define RPM_NOTIFICATION BIT(30)
#define RPM_REJECTED BIT(31)
static const struct qcom_rpm_resource apq8064_rpm_resource_table[] = {
[QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
[QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 },
[QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 },
[QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 },
[QCOM_RPM_MM_FABRIC_CLK] = { 29, 13, 10, 1 },
[QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 },
[QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 },
[QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 },
[QCOM_RPM_MMFPB_CLK] = { 33, 17, 14, 1 },
[QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 },
[QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 1 },
[QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 1 },
[QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 },
[QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 },
[QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 1 },
[QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 1 },
[QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 },
[QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 30 },
[QCOM_RPM_MM_FABRIC_HALT] = { 89, 27, 26, 1 },
[QCOM_RPM_MM_FABRIC_MODE] = { 91, 28, 27, 1 },
[QCOM_RPM_MM_FABRIC_IOCTL] = { 94, 29, 28, 1 },
[QCOM_RPM_MM_FABRIC_ARB] = { 95, 30, 29, 21 },
[QCOM_RPM_PM8921_SMPS1] = { 116, 31, 30, 2 },
[QCOM_RPM_PM8921_SMPS2] = { 118, 33, 31, 2 },
[QCOM_RPM_PM8921_SMPS3] = { 120, 35, 32, 2 },
[QCOM_RPM_PM8921_SMPS4] = { 122, 37, 33, 2 },
[QCOM_RPM_PM8921_SMPS5] = { 124, 39, 34, 2 },
[QCOM_RPM_PM8921_SMPS6] = { 126, 41, 35, 2 },
[QCOM_RPM_PM8921_SMPS7] = { 128, 43, 36, 2 },
[QCOM_RPM_PM8921_SMPS8] = { 130, 45, 37, 2 },
[QCOM_RPM_PM8921_LDO1] = { 132, 47, 38, 2 },
[QCOM_RPM_PM8921_LDO2] = { 134, 49, 39, 2 },
[QCOM_RPM_PM8921_LDO3] = { 136, 51, 40, 2 },
[QCOM_RPM_PM8921_LDO4] = { 138, 53, 41, 2 },
[QCOM_RPM_PM8921_LDO5] = { 140, 55, 42, 2 },
[QCOM_RPM_PM8921_LDO6] = { 142, 57, 43, 2 },
[QCOM_RPM_PM8921_LDO7] = { 144, 59, 44, 2 },
[QCOM_RPM_PM8921_LDO8] = { 146, 61, 45, 2 },
[QCOM_RPM_PM8921_LDO9] = { 148, 63, 46, 2 },
[QCOM_RPM_PM8921_LDO10] = { 150, 65, 47, 2 },
[QCOM_RPM_PM8921_LDO11] = { 152, 67, 48, 2 },
[QCOM_RPM_PM8921_LDO12] = { 154, 69, 49, 2 },
[QCOM_RPM_PM8921_LDO13] = { 156, 71, 50, 2 },
[QCOM_RPM_PM8921_LDO14] = { 158, 73, 51, 2 },
[QCOM_RPM_PM8921_LDO15] = { 160, 75, 52, 2 },
[QCOM_RPM_PM8921_LDO16] = { 162, 77, 53, 2 },
[QCOM_RPM_PM8921_LDO17] = { 164, 79, 54, 2 },
[QCOM_RPM_PM8921_LDO18] = { 166, 81, 55, 2 },
[QCOM_RPM_PM8921_LDO19] = { 168, 83, 56, 2 },
[QCOM_RPM_PM8921_LDO20] = { 170, 85, 57, 2 },
[QCOM_RPM_PM8921_LDO21] = { 172, 87, 58, 2 },
[QCOM_RPM_PM8921_LDO22] = { 174, 89, 59, 2 },
[QCOM_RPM_PM8921_LDO23] = { 176, 91, 60, 2 },
[QCOM_RPM_PM8921_LDO24] = { 178, 93, 61, 2 },
[QCOM_RPM_PM8921_LDO25] = { 180, 95, 62, 2 },
[QCOM_RPM_PM8921_LDO26] = { 182, 97, 63, 2 },
[QCOM_RPM_PM8921_LDO27] = { 184, 99, 64, 2 },
[QCOM_RPM_PM8921_LDO28] = { 186, 101, 65, 2 },
[QCOM_RPM_PM8921_LDO29] = { 188, 103, 66, 2 },
[QCOM_RPM_PM8921_CLK1] = { 190, 105, 67, 2 },
[QCOM_RPM_PM8921_CLK2] = { 192, 107, 68, 2 },
[QCOM_RPM_PM8921_LVS1] = { 194, 109, 69, 1 },
[QCOM_RPM_PM8921_LVS2] = { 195, 110, 70, 1 },
[QCOM_RPM_PM8921_LVS3] = { 196, 111, 71, 1 },
[QCOM_RPM_PM8921_LVS4] = { 197, 112, 72, 1 },
[QCOM_RPM_PM8921_LVS5] = { 198, 113, 73, 1 },
[QCOM_RPM_PM8921_LVS6] = { 199, 114, 74, 1 },
[QCOM_RPM_PM8921_LVS7] = { 200, 115, 75, 1 },
[QCOM_RPM_PM8821_SMPS1] = { 201, 116, 76, 2 },
[QCOM_RPM_PM8821_SMPS2] = { 203, 118, 77, 2 },
[QCOM_RPM_PM8821_LDO1] = { 205, 120, 78, 2 },
[QCOM_RPM_PM8921_NCP] = { 207, 122, 80, 2 },
[QCOM_RPM_CXO_BUFFERS] = { 209, 124, 81, 1 },
[QCOM_RPM_USB_OTG_SWITCH] = { 210, 125, 82, 1 },
[QCOM_RPM_HDMI_SWITCH] = { 211, 126, 83, 1 },
[QCOM_RPM_DDR_DMM] = { 212, 127, 84, 2 },
[QCOM_RPM_QDSS_CLK] = { 214, ~0, 7, 1 },
[QCOM_RPM_VDDMIN_GPIO] = { 215, 131, 89, 1 },
};
static const struct qcom_rpm_data apq8064_template = {
.version = 3,
.resource_table = apq8064_rpm_resource_table,
.n_resources = ARRAY_SIZE(apq8064_rpm_resource_table),
.req_ctx_off = 3,
.req_sel_off = 11,
.ack_ctx_off = 15,
.ack_sel_off = 23,
.req_sel_size = 4,
.ack_sel_size = 7,
};
static const struct qcom_rpm_resource msm8660_rpm_resource_table[] = {
[QCOM_RPM_CXO_CLK] = { 32, 12, 5, 1 },
[QCOM_RPM_PXO_CLK] = { 33, 13, 6, 1 },
[QCOM_RPM_PLL_4] = { 34, 14, 7, 1 },
[QCOM_RPM_APPS_FABRIC_CLK] = { 35, 15, 8, 1 },
[QCOM_RPM_SYS_FABRIC_CLK] = { 36, 16, 9, 1 },
[QCOM_RPM_MM_FABRIC_CLK] = { 37, 17, 10, 1 },
[QCOM_RPM_DAYTONA_FABRIC_CLK] = { 38, 18, 11, 1 },
[QCOM_RPM_SFPB_CLK] = { 39, 19, 12, 1 },
[QCOM_RPM_CFPB_CLK] = { 40, 20, 13, 1 },
[QCOM_RPM_MMFPB_CLK] = { 41, 21, 14, 1 },
[QCOM_RPM_SMI_CLK] = { 42, 22, 15, 1 },
[QCOM_RPM_EBI1_CLK] = { 43, 23, 16, 1 },
[QCOM_RPM_APPS_L2_CACHE_CTL] = { 44, 24, 17, 1 },
[QCOM_RPM_APPS_FABRIC_HALT] = { 45, 25, 18, 2 },
[QCOM_RPM_APPS_FABRIC_MODE] = { 47, 26, 19, 3 },
[QCOM_RPM_APPS_FABRIC_ARB] = { 51, 28, 21, 6 },
[QCOM_RPM_SYS_FABRIC_HALT] = { 63, 29, 22, 2 },
[QCOM_RPM_SYS_FABRIC_MODE] = { 65, 30, 23, 3 },
[QCOM_RPM_SYS_FABRIC_ARB] = { 69, 32, 25, 22 },
[QCOM_RPM_MM_FABRIC_HALT] = { 105, 33, 26, 2 },
[QCOM_RPM_MM_FABRIC_MODE] = { 107, 34, 27, 3 },
[QCOM_RPM_MM_FABRIC_ARB] = { 111, 36, 29, 23 },
[QCOM_RPM_PM8901_SMPS0] = { 134, 37, 30, 2 },
[QCOM_RPM_PM8901_SMPS1] = { 136, 39, 31, 2 },
[QCOM_RPM_PM8901_SMPS2] = { 138, 41, 32, 2 },
[QCOM_RPM_PM8901_SMPS3] = { 140, 43, 33, 2 },
[QCOM_RPM_PM8901_SMPS4] = { 142, 45, 34, 2 },
[QCOM_RPM_PM8901_LDO0] = { 144, 47, 35, 2 },
[QCOM_RPM_PM8901_LDO1] = { 146, 49, 36, 2 },
[QCOM_RPM_PM8901_LDO2] = { 148, 51, 37, 2 },
[QCOM_RPM_PM8901_LDO3] = { 150, 53, 38, 2 },
[QCOM_RPM_PM8901_LDO4] = { 152, 55, 39, 2 },
[QCOM_RPM_PM8901_LDO5] = { 154, 57, 40, 2 },
[QCOM_RPM_PM8901_LDO6] = { 156, 59, 41, 2 },
[QCOM_RPM_PM8901_LVS0] = { 158, 61, 42, 1 },
[QCOM_RPM_PM8901_LVS1] = { 159, 62, 43, 1 },
[QCOM_RPM_PM8901_LVS2] = { 160, 63, 44, 1 },
[QCOM_RPM_PM8901_LVS3] = { 161, 64, 45, 1 },
[QCOM_RPM_PM8901_MVS] = { 162, 65, 46, 1 },
[QCOM_RPM_PM8058_SMPS0] = { 163, 66, 47, 2 },
[QCOM_RPM_PM8058_SMPS1] = { 165, 68, 48, 2 },
[QCOM_RPM_PM8058_SMPS2] = { 167, 70, 49, 2 },
[QCOM_RPM_PM8058_SMPS3] = { 169, 72, 50, 2 },
[QCOM_RPM_PM8058_SMPS4] = { 171, 74, 51, 2 },
[QCOM_RPM_PM8058_LDO0] = { 173, 76, 52, 2 },
[QCOM_RPM_PM8058_LDO1] = { 175, 78, 53, 2 },
[QCOM_RPM_PM8058_LDO2] = { 177, 80, 54, 2 },
[QCOM_RPM_PM8058_LDO3] = { 179, 82, 55, 2 },
[QCOM_RPM_PM8058_LDO4] = { 181, 84, 56, 2 },
[QCOM_RPM_PM8058_LDO5] = { 183, 86, 57, 2 },
[QCOM_RPM_PM8058_LDO6] = { 185, 88, 58, 2 },
[QCOM_RPM_PM8058_LDO7] = { 187, 90, 59, 2 },
[QCOM_RPM_PM8058_LDO8] = { 189, 92, 60, 2 },
[QCOM_RPM_PM8058_LDO9] = { 191, 94, 61, 2 },
[QCOM_RPM_PM8058_LDO10] = { 193, 96, 62, 2 },
[QCOM_RPM_PM8058_LDO11] = { 195, 98, 63, 2 },
[QCOM_RPM_PM8058_LDO12] = { 197, 100, 64, 2 },
[QCOM_RPM_PM8058_LDO13] = { 199, 102, 65, 2 },
[QCOM_RPM_PM8058_LDO14] = { 201, 104, 66, 2 },
[QCOM_RPM_PM8058_LDO15] = { 203, 106, 67, 2 },
[QCOM_RPM_PM8058_LDO16] = { 205, 108, 68, 2 },
[QCOM_RPM_PM8058_LDO17] = { 207, 110, 69, 2 },
[QCOM_RPM_PM8058_LDO18] = { 209, 112, 70, 2 },
[QCOM_RPM_PM8058_LDO19] = { 211, 114, 71, 2 },
[QCOM_RPM_PM8058_LDO20] = { 213, 116, 72, 2 },
[QCOM_RPM_PM8058_LDO21] = { 215, 118, 73, 2 },
[QCOM_RPM_PM8058_LDO22] = { 217, 120, 74, 2 },
[QCOM_RPM_PM8058_LDO23] = { 219, 122, 75, 2 },
[QCOM_RPM_PM8058_LDO24] = { 221, 124, 76, 2 },
[QCOM_RPM_PM8058_LDO25] = { 223, 126, 77, 2 },
[QCOM_RPM_PM8058_LVS0] = { 225, 128, 78, 1 },
[QCOM_RPM_PM8058_LVS1] = { 226, 129, 79, 1 },
[QCOM_RPM_PM8058_NCP] = { 227, 130, 80, 2 },
[QCOM_RPM_CXO_BUFFERS] = { 229, 132, 81, 1 },
};
static const struct qcom_rpm_data msm8660_template = {
.version = 2,
.resource_table = msm8660_rpm_resource_table,
.n_resources = ARRAY_SIZE(msm8660_rpm_resource_table),
.req_ctx_off = 3,
.req_sel_off = 11,
.ack_ctx_off = 19,
.ack_sel_off = 27,
.req_sel_size = 7,
.ack_sel_size = 7,
};
static const struct qcom_rpm_resource msm8960_rpm_resource_table[] = {
[QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
[QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 },
[QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 },
[QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 },
[QCOM_RPM_MM_FABRIC_CLK] = { 29, 13, 10, 1 },
[QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 },
[QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 },
[QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 },
[QCOM_RPM_MMFPB_CLK] = { 33, 17, 14, 1 },
[QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 },
[QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 1 },
[QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 1 },
[QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 },
[QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 },
[QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 1 },
[QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 1 },
[QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 },
[QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 29 },
[QCOM_RPM_MM_FABRIC_HALT] = { 88, 27, 26, 1 },
[QCOM_RPM_MM_FABRIC_MODE] = { 90, 28, 27, 1 },
[QCOM_RPM_MM_FABRIC_IOCTL] = { 93, 29, 28, 1 },
[QCOM_RPM_MM_FABRIC_ARB] = { 94, 30, 29, 23 },
[QCOM_RPM_PM8921_SMPS1] = { 117, 31, 30, 2 },
[QCOM_RPM_PM8921_SMPS2] = { 119, 33, 31, 2 },
[QCOM_RPM_PM8921_SMPS3] = { 121, 35, 32, 2 },
[QCOM_RPM_PM8921_SMPS4] = { 123, 37, 33, 2 },
[QCOM_RPM_PM8921_SMPS5] = { 125, 39, 34, 2 },
[QCOM_RPM_PM8921_SMPS6] = { 127, 41, 35, 2 },
[QCOM_RPM_PM8921_SMPS7] = { 129, 43, 36, 2 },
[QCOM_RPM_PM8921_SMPS8] = { 131, 45, 37, 2 },
[QCOM_RPM_PM8921_LDO1] = { 133, 47, 38, 2 },
[QCOM_RPM_PM8921_LDO2] = { 135, 49, 39, 2 },
[QCOM_RPM_PM8921_LDO3] = { 137, 51, 40, 2 },
[QCOM_RPM_PM8921_LDO4] = { 139, 53, 41, 2 },
[QCOM_RPM_PM8921_LDO5] = { 141, 55, 42, 2 },
[QCOM_RPM_PM8921_LDO6] = { 143, 57, 43, 2 },
[QCOM_RPM_PM8921_LDO7] = { 145, 59, 44, 2 },
[QCOM_RPM_PM8921_LDO8] = { 147, 61, 45, 2 },
[QCOM_RPM_PM8921_LDO9] = { 149, 63, 46, 2 },
[QCOM_RPM_PM8921_LDO10] = { 151, 65, 47, 2 },
[QCOM_RPM_PM8921_LDO11] = { 153, 67, 48, 2 },
[QCOM_RPM_PM8921_LDO12] = { 155, 69, 49, 2 },
[QCOM_RPM_PM8921_LDO13] = { 157, 71, 50, 2 },
[QCOM_RPM_PM8921_LDO14] = { 159, 73, 51, 2 },
[QCOM_RPM_PM8921_LDO15] = { 161, 75, 52, 2 },
[QCOM_RPM_PM8921_LDO16] = { 163, 77, 53, 2 },
[QCOM_RPM_PM8921_LDO17] = { 165, 79, 54, 2 },
[QCOM_RPM_PM8921_LDO18] = { 167, 81, 55, 2 },
[QCOM_RPM_PM8921_LDO19] = { 169, 83, 56, 2 },
[QCOM_RPM_PM8921_LDO20] = { 171, 85, 57, 2 },
[QCOM_RPM_PM8921_LDO21] = { 173, 87, 58, 2 },
[QCOM_RPM_PM8921_LDO22] = { 175, 89, 59, 2 },
[QCOM_RPM_PM8921_LDO23] = { 177, 91, 60, 2 },
[QCOM_RPM_PM8921_LDO24] = { 179, 93, 61, 2 },
[QCOM_RPM_PM8921_LDO25] = { 181, 95, 62, 2 },
[QCOM_RPM_PM8921_LDO26] = { 183, 97, 63, 2 },
[QCOM_RPM_PM8921_LDO27] = { 185, 99, 64, 2 },
[QCOM_RPM_PM8921_LDO28] = { 187, 101, 65, 2 },
[QCOM_RPM_PM8921_LDO29] = { 189, 103, 66, 2 },
[QCOM_RPM_PM8921_CLK1] = { 191, 105, 67, 2 },
[QCOM_RPM_PM8921_CLK2] = { 193, 107, 68, 2 },
[QCOM_RPM_PM8921_LVS1] = { 195, 109, 69, 1 },
[QCOM_RPM_PM8921_LVS2] = { 196, 110, 70, 1 },
[QCOM_RPM_PM8921_LVS3] = { 197, 111, 71, 1 },
[QCOM_RPM_PM8921_LVS4] = { 198, 112, 72, 1 },
[QCOM_RPM_PM8921_LVS5] = { 199, 113, 73, 1 },
[QCOM_RPM_PM8921_LVS6] = { 200, 114, 74, 1 },
[QCOM_RPM_PM8921_LVS7] = { 201, 115, 75, 1 },
[QCOM_RPM_PM8921_NCP] = { 202, 116, 80, 2 },
[QCOM_RPM_CXO_BUFFERS] = { 204, 118, 81, 1 },
[QCOM_RPM_USB_OTG_SWITCH] = { 205, 119, 82, 1 },
[QCOM_RPM_HDMI_SWITCH] = { 206, 120, 83, 1 },
[QCOM_RPM_DDR_DMM] = { 207, 121, 84, 2 },
};
static const struct qcom_rpm_data msm8960_template = {
.version = 3,
.resource_table = msm8960_rpm_resource_table,
.n_resources = ARRAY_SIZE(msm8960_rpm_resource_table),
.req_ctx_off = 3,
.req_sel_off = 11,
.ack_ctx_off = 15,
.ack_sel_off = 23,
.req_sel_size = 4,
.ack_sel_size = 7,
};
static const struct qcom_rpm_resource ipq806x_rpm_resource_table[] = {
[QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
[QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 },
[QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 },
[QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 },
[QCOM_RPM_NSS_FABRIC_0_CLK] = { 29, 13, 10, 1 },
[QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 },
[QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 },
[QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 },
[QCOM_RPM_NSS_FABRIC_1_CLK] = { 33, 17, 14, 1 },
[QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 },
[QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 2 },
[QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 3 },
[QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 },
[QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 },
[QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 2 },
[QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 3 },
[QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 },
[QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 30 },
[QCOM_RPM_MM_FABRIC_HALT] = { 89, 27, 26, 2 },
[QCOM_RPM_MM_FABRIC_MODE] = { 91, 28, 27, 3 },
[QCOM_RPM_MM_FABRIC_IOCTL] = { 94, 29, 28, 1 },
[QCOM_RPM_MM_FABRIC_ARB] = { 95, 30, 29, 2 },
[QCOM_RPM_CXO_BUFFERS] = { 209, 33, 31, 1 },
[QCOM_RPM_USB_OTG_SWITCH] = { 210, 34, 32, 1 },
[QCOM_RPM_HDMI_SWITCH] = { 211, 35, 33, 1 },
[QCOM_RPM_DDR_DMM] = { 212, 36, 34, 2 },
[QCOM_RPM_VDDMIN_GPIO] = { 215, 40, 39, 1 },
[QCOM_RPM_SMB208_S1a] = { 216, 41, 90, 2 },
[QCOM_RPM_SMB208_S1b] = { 218, 43, 91, 2 },
[QCOM_RPM_SMB208_S2a] = { 220, 45, 92, 2 },
[QCOM_RPM_SMB208_S2b] = { 222, 47, 93, 2 },
};
static const struct qcom_rpm_data ipq806x_template = {
.version = 3,
.resource_table = ipq806x_rpm_resource_table,
.n_resources = ARRAY_SIZE(ipq806x_rpm_resource_table),
.req_ctx_off = 3,
.req_sel_off = 11,
.ack_ctx_off = 15,
.ack_sel_off = 23,
.req_sel_size = 4,
.ack_sel_size = 7,
};
static const struct qcom_rpm_resource mdm9615_rpm_resource_table[] = {
[QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
[QCOM_RPM_SYS_FABRIC_CLK] = { 26, 10, 9, 1 },
[QCOM_RPM_DAYTONA_FABRIC_CLK] = { 27, 11, 11, 1 },
[QCOM_RPM_SFPB_CLK] = { 28, 12, 12, 1 },
[QCOM_RPM_CFPB_CLK] = { 29, 13, 13, 1 },
[QCOM_RPM_EBI1_CLK] = { 30, 14, 16, 1 },
[QCOM_RPM_APPS_FABRIC_HALT] = { 31, 15, 22, 2 },
[QCOM_RPM_APPS_FABRIC_MODE] = { 33, 16, 23, 3 },
[QCOM_RPM_APPS_FABRIC_IOCTL] = { 36, 17, 24, 1 },
[QCOM_RPM_APPS_FABRIC_ARB] = { 37, 18, 25, 27 },
[QCOM_RPM_PM8018_SMPS1] = { 64, 19, 30, 2 },
[QCOM_RPM_PM8018_SMPS2] = { 66, 21, 31, 2 },
[QCOM_RPM_PM8018_SMPS3] = { 68, 23, 32, 2 },
[QCOM_RPM_PM8018_SMPS4] = { 70, 25, 33, 2 },
[QCOM_RPM_PM8018_SMPS5] = { 72, 27, 34, 2 },
[QCOM_RPM_PM8018_LDO1] = { 74, 29, 35, 2 },
[QCOM_RPM_PM8018_LDO2] = { 76, 31, 36, 2 },
[QCOM_RPM_PM8018_LDO3] = { 78, 33, 37, 2 },
[QCOM_RPM_PM8018_LDO4] = { 80, 35, 38, 2 },
[QCOM_RPM_PM8018_LDO5] = { 82, 37, 39, 2 },
[QCOM_RPM_PM8018_LDO6] = { 84, 39, 40, 2 },
[QCOM_RPM_PM8018_LDO7] = { 86, 41, 41, 2 },
[QCOM_RPM_PM8018_LDO8] = { 88, 43, 42, 2 },
[QCOM_RPM_PM8018_LDO9] = { 90, 45, 43, 2 },
[QCOM_RPM_PM8018_LDO10] = { 92, 47, 44, 2 },
[QCOM_RPM_PM8018_LDO11] = { 94, 49, 45, 2 },
[QCOM_RPM_PM8018_LDO12] = { 96, 51, 46, 2 },
[QCOM_RPM_PM8018_LDO13] = { 98, 53, 47, 2 },
[QCOM_RPM_PM8018_LDO14] = { 100, 55, 48, 2 },
[QCOM_RPM_PM8018_LVS1] = { 102, 57, 49, 1 },
[QCOM_RPM_PM8018_NCP] = { 103, 58, 80, 2 },
[QCOM_RPM_CXO_BUFFERS] = { 105, 60, 81, 1 },
[QCOM_RPM_USB_OTG_SWITCH] = { 106, 61, 82, 1 },
[QCOM_RPM_HDMI_SWITCH] = { 107, 62, 83, 1 },
[QCOM_RPM_VOLTAGE_CORNER] = { 109, 64, 87, 1 },
};
static const struct qcom_rpm_data mdm9615_template = {
.version = 3,
.resource_table = mdm9615_rpm_resource_table,
.n_resources = ARRAY_SIZE(mdm9615_rpm_resource_table),
.req_ctx_off = 3,
.req_sel_off = 11,
.ack_ctx_off = 15,
.ack_sel_off = 23,
.req_sel_size = 4,
.ack_sel_size = 7,
};
static const struct of_device_id qcom_rpm_of_match[] = {
{ .compatible = "qcom,rpm-apq8064", .data = &apq8064_template },
{ .compatible = "qcom,rpm-msm8660", .data = &msm8660_template },
{ .compatible = "qcom,rpm-msm8960", .data = &msm8960_template },
{ .compatible = "qcom,rpm-ipq8064", .data = &ipq806x_template },
{ .compatible = "qcom,rpm-mdm9615", .data = &mdm9615_template },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_rpm_of_match);
int qcom_rpm_write(struct qcom_rpm *rpm,
int state,
int resource,
u32 *buf, size_t count)
{
const struct qcom_rpm_resource *res;
const struct qcom_rpm_data *data = rpm->data;
u32 sel_mask[RPM_MAX_SEL_SIZE] = { 0 };
int left;
int ret = 0;
int i;
if (WARN_ON(resource < 0 || resource >= data->n_resources))
return -EINVAL;
res = &data->resource_table[resource];
if (WARN_ON(res->size != count))
return -EINVAL;
mutex_lock(&rpm->lock);
for (i = 0; i < res->size; i++)
writel_relaxed(buf[i], RPM_REQ_REG(rpm, res->target_id + i));
bitmap_set((unsigned long *)sel_mask, res->select_id, 1);
for (i = 0; i < rpm->data->req_sel_size; i++) {
writel_relaxed(sel_mask[i],
RPM_CTRL_REG(rpm, rpm->data->req_sel_off + i));
}
writel_relaxed(BIT(state), RPM_CTRL_REG(rpm, rpm->data->req_ctx_off));
reinit_completion(&rpm->ack);
regmap_write(rpm->ipc_regmap, rpm->ipc_offset, BIT(rpm->ipc_bit));
left = wait_for_completion_timeout(&rpm->ack, RPM_REQUEST_TIMEOUT);
if (!left)
ret = -ETIMEDOUT;
else if (rpm->ack_status & RPM_REJECTED)
ret = -EIO;
mutex_unlock(&rpm->lock);
return ret;
}
EXPORT_SYMBOL(qcom_rpm_write);
static irqreturn_t qcom_rpm_ack_interrupt(int irq, void *dev)
{
struct qcom_rpm *rpm = dev;
u32 ack;
int i;
ack = readl_relaxed(RPM_CTRL_REG(rpm, rpm->data->ack_ctx_off));
for (i = 0; i < rpm->data->ack_sel_size; i++)
writel_relaxed(0,
RPM_CTRL_REG(rpm, rpm->data->ack_sel_off + i));
writel(0, RPM_CTRL_REG(rpm, rpm->data->ack_ctx_off));
if (ack & RPM_NOTIFICATION) {
dev_warn(rpm->dev, "ignoring notification!\n");
} else {
rpm->ack_status = ack;
complete(&rpm->ack);
}
return IRQ_HANDLED;
}
static irqreturn_t qcom_rpm_err_interrupt(int irq, void *dev)
{
struct qcom_rpm *rpm = dev;
regmap_write(rpm->ipc_regmap, rpm->ipc_offset, BIT(rpm->ipc_bit));
dev_err(rpm->dev, "RPM triggered fatal error\n");
return IRQ_HANDLED;
}
static irqreturn_t qcom_rpm_wakeup_interrupt(int irq, void *dev)
{
return IRQ_HANDLED;
}
static int qcom_rpm_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
struct device_node *syscon_np;
struct qcom_rpm *rpm;
u32 fw_version[3];
int irq_wakeup;
int irq_ack;
int irq_err;
int ret;
rpm = devm_kzalloc(&pdev->dev, sizeof(*rpm), GFP_KERNEL);
if (!rpm)
return -ENOMEM;
rpm->dev = &pdev->dev;
mutex_init(&rpm->lock);
init_completion(&rpm->ack);
/* Enable message RAM clock */
rpm->ramclk = devm_clk_get_enabled(&pdev->dev, "ram");
if (IS_ERR(rpm->ramclk)) {
ret = PTR_ERR(rpm->ramclk);
if (ret == -EPROBE_DEFER)
return ret;
/*
* Fall through in all other cases, as the clock is
* optional. (Does not exist on all platforms.)
*/
rpm->ramclk = NULL;
}
irq_ack = platform_get_irq_byname(pdev, "ack");
if (irq_ack < 0)
return irq_ack;
irq_err = platform_get_irq_byname(pdev, "err");
if (irq_err < 0)
return irq_err;
irq_wakeup = platform_get_irq_byname(pdev, "wakeup");
if (irq_wakeup < 0)
return irq_wakeup;
match = of_match_device(qcom_rpm_of_match, &pdev->dev);
if (!match)
return -ENODEV;
rpm->data = match->data;
rpm->status_regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(rpm->status_regs))
return PTR_ERR(rpm->status_regs);
rpm->ctrl_regs = rpm->status_regs + 0x400;
rpm->req_regs = rpm->status_regs + 0x600;
syscon_np = of_parse_phandle(pdev->dev.of_node, "qcom,ipc", 0);
if (!syscon_np) {
dev_err(&pdev->dev, "no qcom,ipc node\n");
return -ENODEV;
}
rpm->ipc_regmap = syscon_node_to_regmap(syscon_np);
of_node_put(syscon_np);
if (IS_ERR(rpm->ipc_regmap))
return PTR_ERR(rpm->ipc_regmap);
ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,ipc", 1,
&rpm->ipc_offset);
if (ret < 0) {
dev_err(&pdev->dev, "no offset in qcom,ipc\n");
return -EINVAL;
}
ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,ipc", 2,
&rpm->ipc_bit);
if (ret < 0) {
dev_err(&pdev->dev, "no bit in qcom,ipc\n");
return -EINVAL;
}
dev_set_drvdata(&pdev->dev, rpm);
fw_version[0] = readl(RPM_STATUS_REG(rpm, 0));
fw_version[1] = readl(RPM_STATUS_REG(rpm, 1));
fw_version[2] = readl(RPM_STATUS_REG(rpm, 2));
if (fw_version[0] != rpm->data->version) {
dev_err(&pdev->dev,
"RPM version %u.%u.%u incompatible with driver version %u",
fw_version[0],
fw_version[1],
fw_version[2],
rpm->data->version);
return -EFAULT;
}
writel(fw_version[0], RPM_CTRL_REG(rpm, 0));
writel(fw_version[1], RPM_CTRL_REG(rpm, 1));
writel(fw_version[2], RPM_CTRL_REG(rpm, 2));
dev_info(&pdev->dev, "RPM firmware %u.%u.%u\n", fw_version[0],
fw_version[1],
fw_version[2]);
ret = devm_request_irq(&pdev->dev,
irq_ack,
qcom_rpm_ack_interrupt,
IRQF_TRIGGER_RISING,
"qcom_rpm_ack",
rpm);
if (ret) {
dev_err(&pdev->dev, "failed to request ack interrupt\n");
return ret;
}
ret = irq_set_irq_wake(irq_ack, 1);
if (ret)
dev_warn(&pdev->dev, "failed to mark ack irq as wakeup\n");
ret = devm_request_irq(&pdev->dev,
irq_err,
qcom_rpm_err_interrupt,
IRQF_TRIGGER_RISING,
"qcom_rpm_err",
rpm);
if (ret) {
dev_err(&pdev->dev, "failed to request err interrupt\n");
return ret;
}
ret = devm_request_irq(&pdev->dev,
irq_wakeup,
qcom_rpm_wakeup_interrupt,
IRQF_TRIGGER_RISING,
"qcom_rpm_wakeup",
rpm);
if (ret) {
dev_err(&pdev->dev, "failed to request wakeup interrupt\n");
return ret;
}
ret = irq_set_irq_wake(irq_wakeup, 1);
if (ret)
dev_warn(&pdev->dev, "failed to mark wakeup irq as wakeup\n");
return devm_of_platform_populate(&pdev->dev);
}
static struct platform_driver qcom_rpm_driver = {
.probe = qcom_rpm_probe,
.driver = {
.name = "qcom_rpm",
.of_match_table = qcom_rpm_of_match,
},
};
static int __init qcom_rpm_init(void)
{
return platform_driver_register(&qcom_rpm_driver);
}
arch_initcall(qcom_rpm_init);
static void __exit qcom_rpm_exit(void)
{
platform_driver_unregister(&qcom_rpm_driver);
}
module_exit(qcom_rpm_exit)
MODULE_DESCRIPTION("Qualcomm Resource Power Manager driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Bjorn Andersson <[email protected]>");
| linux-master | drivers/mfd/qcom_rpm.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (C) 2019 ROHM Semiconductors
//
// ROHM BD71828/BD71815 PMIC driver
#include <linux/gpio_keys.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/mfd/rohm-bd71815.h>
#include <linux/mfd/rohm-bd71828.h>
#include <linux/mfd/rohm-generic.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/types.h>
static struct gpio_keys_button button = {
.code = KEY_POWER,
.gpio = -1,
.type = EV_KEY,
};
static struct gpio_keys_platform_data bd71828_powerkey_data = {
.buttons = &button,
.nbuttons = 1,
.name = "bd71828-pwrkey",
};
static const struct resource bd71815_rtc_irqs[] = {
DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC0, "bd71815-rtc-alm-0"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC1, "bd71815-rtc-alm-1"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC2, "bd71815-rtc-alm-2"),
};
static const struct resource bd71828_rtc_irqs[] = {
DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd71828-rtc-alm-0"),
DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd71828-rtc-alm-1"),
DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd71828-rtc-alm-2"),
};
static struct resource bd71815_power_irqs[] = {
DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-clps-out"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-clps-in"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_RES, "bd71815-dcin-ovp-res"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_DET, "bd71815-dcin-ovp-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_RES, "bd71815-dcin-mon-res"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_DET, "bd71815-dcin-mon-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_RES, "bd71815-vsys-uv-res"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_DET, "bd71815-vsys-uv-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_RES, "bd71815-vsys-low-res"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_DET, "bd71815-vsys-low-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-res"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TEMP, "bd71815-chg-wdg-temp"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TIME, "bd71815-chg-wdg"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_RES, "bd71815-rechg-res"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_DET, "bd71815-rechg-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, "bd71815-ranged-temp-transit"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_STATE_TRANSITION, "bd71815-chg-state-change"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_NORMAL, "bd71815-bat-temp-normal"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_ERANGE, "bd71815-bat-temp-erange"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_REMOVED, "bd71815-bat-rmv"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DETECTED, "bd71815-bat-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_REMOVED, "bd71815-therm-rmv"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_DETECTED, "bd71815-therm-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DEAD, "bd71815-bat-dead"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_RES, "bd71815-bat-short-res"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_DET, "bd71815-bat-short-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_RES, "bd71815-bat-low-res"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_DET, "bd71815-bat-low-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_RES, "bd71815-bat-over-res"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_DET, "bd71815-bat-over-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_RES, "bd71815-bat-mon-res"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_DET, "bd71815-bat-mon-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON1, "bd71815-bat-cc-mon1"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON2, "bd71815-bat-cc-mon2"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON3, "bd71815-bat-cc-mon3"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_RES, "bd71815-bat-oc1-res"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_DET, "bd71815-bat-oc1-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_RES, "bd71815-bat-oc2-res"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_DET, "bd71815-bat-oc2-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_RES, "bd71815-bat-oc3-res"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_DET, "bd71815-bat-oc3-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-bat-low-res"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-bat-low-det"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-bat-hi-res"),
DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-bat-hi-det"),
};
static struct mfd_cell bd71815_mfd_cells[] = {
{ .name = "bd71815-pmic", },
{ .name = "bd71815-clk", },
{ .name = "bd71815-gpo", },
{
.name = "bd71815-power",
.num_resources = ARRAY_SIZE(bd71815_power_irqs),
.resources = &bd71815_power_irqs[0],
},
{
.name = "bd71815-rtc",
.num_resources = ARRAY_SIZE(bd71815_rtc_irqs),
.resources = &bd71815_rtc_irqs[0],
},
};
static struct mfd_cell bd71828_mfd_cells[] = {
{ .name = "bd71828-pmic", },
{ .name = "bd71828-gpio", },
{ .name = "bd71828-led", .of_compatible = "rohm,bd71828-leds" },
/*
* We use BD71837 driver to drive the clock block. Only differences to
* BD70528 clock gate are the register address and mask.
*/
{ .name = "bd71828-clk", },
{ .name = "bd71827-power", },
{
.name = "bd71828-rtc",
.resources = bd71828_rtc_irqs,
.num_resources = ARRAY_SIZE(bd71828_rtc_irqs),
}, {
.name = "gpio-keys",
.platform_data = &bd71828_powerkey_data,
.pdata_size = sizeof(bd71828_powerkey_data),
},
};
static const struct regmap_range bd71815_volatile_ranges[] = {
{
.range_min = BD71815_REG_SEC,
.range_max = BD71815_REG_YEAR,
}, {
.range_min = BD71815_REG_CONF,
.range_max = BD71815_REG_BAT_TEMP,
}, {
.range_min = BD71815_REG_VM_IBAT_U,
.range_max = BD71815_REG_CC_CTRL,
}, {
.range_min = BD71815_REG_CC_STAT,
.range_max = BD71815_REG_CC_CURCD_L,
}, {
.range_min = BD71815_REG_VM_BTMP_MON,
.range_max = BD71815_REG_VM_BTMP_MON,
}, {
.range_min = BD71815_REG_INT_STAT,
.range_max = BD71815_REG_INT_UPDATE,
}, {
.range_min = BD71815_REG_VM_VSYS_U,
.range_max = BD71815_REG_REX_CTRL_1,
}, {
.range_min = BD71815_REG_FULL_CCNTD_3,
.range_max = BD71815_REG_CCNTD_CHG_2,
},
};
static const struct regmap_range bd71828_volatile_ranges[] = {
{
.range_min = BD71828_REG_PS_CTRL_1,
.range_max = BD71828_REG_PS_CTRL_1,
}, {
.range_min = BD71828_REG_PS_CTRL_3,
.range_max = BD71828_REG_PS_CTRL_3,
}, {
.range_min = BD71828_REG_RTC_SEC,
.range_max = BD71828_REG_RTC_YEAR,
}, {
/*
* For now make all charger registers volatile because many
* needs to be and because the charger block is not that
* performance critical.
*/
.range_min = BD71828_REG_CHG_STATE,
.range_max = BD71828_REG_CHG_FULL,
}, {
.range_min = BD71828_REG_INT_MAIN,
.range_max = BD71828_REG_IO_STAT,
},
};
static const struct regmap_access_table bd71815_volatile_regs = {
.yes_ranges = &bd71815_volatile_ranges[0],
.n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ranges),
};
static const struct regmap_access_table bd71828_volatile_regs = {
.yes_ranges = &bd71828_volatile_ranges[0],
.n_yes_ranges = ARRAY_SIZE(bd71828_volatile_ranges),
};
static const struct regmap_config bd71815_regmap = {
.reg_bits = 8,
.val_bits = 8,
.volatile_table = &bd71815_volatile_regs,
.max_register = BD71815_MAX_REGISTER - 1,
.cache_type = REGCACHE_RBTREE,
};
static const struct regmap_config bd71828_regmap = {
.reg_bits = 8,
.val_bits = 8,
.volatile_table = &bd71828_volatile_regs,
.max_register = BD71828_MAX_REGISTER,
.cache_type = REGCACHE_RBTREE,
};
/*
* Mapping of main IRQ register bits to sub-IRQ register offsets so that we can
* access corect sub-IRQ registers based on bits that are set in main IRQ
* register. BD71815 and BD71828 have same sub-register-block offests.
*/
static unsigned int bit0_offsets[] = {11}; /* RTC IRQ */
static unsigned int bit1_offsets[] = {10}; /* TEMP IRQ */
static unsigned int bit2_offsets[] = {6, 7, 8, 9}; /* BAT MON IRQ */
static unsigned int bit3_offsets[] = {5}; /* BAT IRQ */
static unsigned int bit4_offsets[] = {4}; /* CHG IRQ */
static unsigned int bit5_offsets[] = {3}; /* VSYS IRQ */
static unsigned int bit6_offsets[] = {1, 2}; /* DCIN IRQ */
static unsigned int bit7_offsets[] = {0}; /* BUCK IRQ */
static struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = {
REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
};
static const struct regmap_irq bd71815_irqs[] = {
REGMAP_IRQ_REG(BD71815_INT_BUCK1_OCP, 0, BD71815_INT_BUCK1_OCP_MASK),
REGMAP_IRQ_REG(BD71815_INT_BUCK2_OCP, 0, BD71815_INT_BUCK2_OCP_MASK),
REGMAP_IRQ_REG(BD71815_INT_BUCK3_OCP, 0, BD71815_INT_BUCK3_OCP_MASK),
REGMAP_IRQ_REG(BD71815_INT_BUCK4_OCP, 0, BD71815_INT_BUCK4_OCP_MASK),
REGMAP_IRQ_REG(BD71815_INT_BUCK5_OCP, 0, BD71815_INT_BUCK5_OCP_MASK),
REGMAP_IRQ_REG(BD71815_INT_LED_OVP, 0, BD71815_INT_LED_OVP_MASK),
REGMAP_IRQ_REG(BD71815_INT_LED_OCP, 0, BD71815_INT_LED_OCP_MASK),
REGMAP_IRQ_REG(BD71815_INT_LED_SCP, 0, BD71815_INT_LED_SCP_MASK),
/* DCIN1 interrupts */
REGMAP_IRQ_REG(BD71815_INT_DCIN_RMV, 1, BD71815_INT_DCIN_RMV_MASK),
REGMAP_IRQ_REG(BD71815_INT_CLPS_OUT, 1, BD71815_INT_CLPS_OUT_MASK),
REGMAP_IRQ_REG(BD71815_INT_CLPS_IN, 1, BD71815_INT_CLPS_IN_MASK),
REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_RES, 1, BD71815_INT_DCIN_OVP_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_DET, 1, BD71815_INT_DCIN_OVP_DET_MASK),
/* DCIN2 interrupts */
REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_RES, 2, BD71815_INT_DCIN_MON_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_DET, 2, BD71815_INT_DCIN_MON_DET_MASK),
REGMAP_IRQ_REG(BD71815_INT_WDOG, 2, BD71815_INT_WDOG_MASK),
/* Vsys */
REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_RES, 3, BD71815_INT_VSYS_UV_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_DET, 3, BD71815_INT_VSYS_UV_DET_MASK),
REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_RES, 3, BD71815_INT_VSYS_LOW_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_DET, 3, BD71815_INT_VSYS_LOW_DET_MASK),
REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_RES, 3, BD71815_INT_VSYS_MON_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_DET, 3, BD71815_INT_VSYS_MON_DET_MASK),
/* Charger */
REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TEMP, 4, BD71815_INT_CHG_WDG_TEMP_MASK),
REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TIME, 4, BD71815_INT_CHG_WDG_TIME_MASK),
REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_RES, 4, BD71815_INT_CHG_RECHARGE_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_DET, 4, BD71815_INT_CHG_RECHARGE_DET_MASK),
REGMAP_IRQ_REG(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, 4,
BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK),
REGMAP_IRQ_REG(BD71815_INT_CHG_STATE_TRANSITION, 4, BD71815_INT_CHG_STATE_TRANSITION_MASK),
/* Battery */
REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_NORMAL, 5, BD71815_INT_BAT_TEMP_NORMAL_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_ERANGE, 5, BD71815_INT_BAT_TEMP_ERANGE_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_REMOVED, 5, BD71815_INT_BAT_REMOVED_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_DETECTED, 5, BD71815_INT_BAT_DETECTED_MASK),
REGMAP_IRQ_REG(BD71815_INT_THERM_REMOVED, 5, BD71815_INT_THERM_REMOVED_MASK),
REGMAP_IRQ_REG(BD71815_INT_THERM_DETECTED, 5, BD71815_INT_THERM_DETECTED_MASK),
/* Battery Mon 1 */
REGMAP_IRQ_REG(BD71815_INT_BAT_DEAD, 6, BD71815_INT_BAT_DEAD_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_RES, 6, BD71815_INT_BAT_SHORTC_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_DET, 6, BD71815_INT_BAT_SHORTC_DET_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_RES, 6, BD71815_INT_BAT_LOW_VOLT_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_DET, 6, BD71815_INT_BAT_LOW_VOLT_DET_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_RES, 6, BD71815_INT_BAT_OVER_VOLT_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_DET, 6, BD71815_INT_BAT_OVER_VOLT_DET_MASK),
/* Battery Mon 2 */
REGMAP_IRQ_REG(BD71815_INT_BAT_MON_RES, 7, BD71815_INT_BAT_MON_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_MON_DET, 7, BD71815_INT_BAT_MON_DET_MASK),
/* Battery Mon 3 (Coulomb counter) */
REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON1, 8, BD71815_INT_BAT_CC_MON1_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON2, 8, BD71815_INT_BAT_CC_MON2_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON3, 8, BD71815_INT_BAT_CC_MON3_MASK),
/* Battery Mon 4 */
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_RES, 9, BD71815_INT_BAT_OVER_CURR_1_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_DET, 9, BD71815_INT_BAT_OVER_CURR_1_DET_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_RES, 9, BD71815_INT_BAT_OVER_CURR_2_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_DET, 9, BD71815_INT_BAT_OVER_CURR_2_DET_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_RES, 9, BD71815_INT_BAT_OVER_CURR_3_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_DET, 9, BD71815_INT_BAT_OVER_CURR_3_DET_MASK),
/* Temperature */
REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_RES, 10, BD71815_INT_TEMP_BAT_LOW_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_DET, 10, BD71815_INT_TEMP_BAT_LOW_DET_MASK),
REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_RES, 10, BD71815_INT_TEMP_BAT_HI_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_DET, 10, BD71815_INT_TEMP_BAT_HI_DET_MASK),
REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_RES, 10,
BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_DET, 10,
BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK),
REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_RES, 10,
BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK),
REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_DET, 10,
BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK),
/* RTC Alarm */
REGMAP_IRQ_REG(BD71815_INT_RTC0, 11, BD71815_INT_RTC0_MASK),
REGMAP_IRQ_REG(BD71815_INT_RTC1, 11, BD71815_INT_RTC1_MASK),
REGMAP_IRQ_REG(BD71815_INT_RTC2, 11, BD71815_INT_RTC2_MASK),
};
static struct regmap_irq bd71828_irqs[] = {
REGMAP_IRQ_REG(BD71828_INT_BUCK1_OCP, 0, BD71828_INT_BUCK1_OCP_MASK),
REGMAP_IRQ_REG(BD71828_INT_BUCK2_OCP, 0, BD71828_INT_BUCK2_OCP_MASK),
REGMAP_IRQ_REG(BD71828_INT_BUCK3_OCP, 0, BD71828_INT_BUCK3_OCP_MASK),
REGMAP_IRQ_REG(BD71828_INT_BUCK4_OCP, 0, BD71828_INT_BUCK4_OCP_MASK),
REGMAP_IRQ_REG(BD71828_INT_BUCK5_OCP, 0, BD71828_INT_BUCK5_OCP_MASK),
REGMAP_IRQ_REG(BD71828_INT_BUCK6_OCP, 0, BD71828_INT_BUCK6_OCP_MASK),
REGMAP_IRQ_REG(BD71828_INT_BUCK7_OCP, 0, BD71828_INT_BUCK7_OCP_MASK),
REGMAP_IRQ_REG(BD71828_INT_PGFAULT, 0, BD71828_INT_PGFAULT_MASK),
/* DCIN1 interrupts */
REGMAP_IRQ_REG(BD71828_INT_DCIN_DET, 1, BD71828_INT_DCIN_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_DCIN_RMV, 1, BD71828_INT_DCIN_RMV_MASK),
REGMAP_IRQ_REG(BD71828_INT_CLPS_OUT, 1, BD71828_INT_CLPS_OUT_MASK),
REGMAP_IRQ_REG(BD71828_INT_CLPS_IN, 1, BD71828_INT_CLPS_IN_MASK),
/* DCIN2 interrupts */
REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_RES, 2, BD71828_INT_DCIN_MON_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_DET, 2, BD71828_INT_DCIN_MON_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_LONGPUSH, 2, BD71828_INT_LONGPUSH_MASK),
REGMAP_IRQ_REG(BD71828_INT_MIDPUSH, 2, BD71828_INT_MIDPUSH_MASK),
REGMAP_IRQ_REG(BD71828_INT_SHORTPUSH, 2, BD71828_INT_SHORTPUSH_MASK),
REGMAP_IRQ_REG(BD71828_INT_PUSH, 2, BD71828_INT_PUSH_MASK),
REGMAP_IRQ_REG(BD71828_INT_WDOG, 2, BD71828_INT_WDOG_MASK),
REGMAP_IRQ_REG(BD71828_INT_SWRESET, 2, BD71828_INT_SWRESET_MASK),
/* Vsys */
REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_RES, 3, BD71828_INT_VSYS_UV_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_DET, 3, BD71828_INT_VSYS_UV_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_RES, 3, BD71828_INT_VSYS_LOW_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_DET, 3, BD71828_INT_VSYS_LOW_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_IN, 3, BD71828_INT_VSYS_HALL_IN_MASK),
REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_TOGGLE, 3, BD71828_INT_VSYS_HALL_TOGGLE_MASK),
REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_RES, 3, BD71828_INT_VSYS_MON_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_DET, 3, BD71828_INT_VSYS_MON_DET_MASK),
/* Charger */
REGMAP_IRQ_REG(BD71828_INT_CHG_DCIN_ILIM, 4, BD71828_INT_CHG_DCIN_ILIM_MASK),
REGMAP_IRQ_REG(BD71828_INT_CHG_TOPOFF_TO_DONE, 4, BD71828_INT_CHG_TOPOFF_TO_DONE_MASK),
REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TEMP, 4, BD71828_INT_CHG_WDG_TEMP_MASK),
REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TIME, 4, BD71828_INT_CHG_WDG_TIME_MASK),
REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_RES, 4, BD71828_INT_CHG_RECHARGE_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_DET, 4, BD71828_INT_CHG_RECHARGE_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_CHG_RANGED_TEMP_TRANSITION, 4,
BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK),
REGMAP_IRQ_REG(BD71828_INT_CHG_STATE_TRANSITION, 4, BD71828_INT_CHG_STATE_TRANSITION_MASK),
/* Battery */
REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_NORMAL, 5, BD71828_INT_BAT_TEMP_NORMAL_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_ERANGE, 5, BD71828_INT_BAT_TEMP_ERANGE_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_WARN, 5, BD71828_INT_BAT_TEMP_WARN_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_REMOVED, 5, BD71828_INT_BAT_REMOVED_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_DETECTED, 5, BD71828_INT_BAT_DETECTED_MASK),
REGMAP_IRQ_REG(BD71828_INT_THERM_REMOVED, 5, BD71828_INT_THERM_REMOVED_MASK),
REGMAP_IRQ_REG(BD71828_INT_THERM_DETECTED, 5, BD71828_INT_THERM_DETECTED_MASK),
/* Battery Mon 1 */
REGMAP_IRQ_REG(BD71828_INT_BAT_DEAD, 6, BD71828_INT_BAT_DEAD_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_RES, 6, BD71828_INT_BAT_SHORTC_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_DET, 6, BD71828_INT_BAT_SHORTC_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_RES, 6, BD71828_INT_BAT_LOW_VOLT_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_DET, 6, BD71828_INT_BAT_LOW_VOLT_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_RES, 6, BD71828_INT_BAT_OVER_VOLT_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_DET, 6, BD71828_INT_BAT_OVER_VOLT_DET_MASK),
/* Battery Mon 2 */
REGMAP_IRQ_REG(BD71828_INT_BAT_MON_RES, 7, BD71828_INT_BAT_MON_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_MON_DET, 7, BD71828_INT_BAT_MON_DET_MASK),
/* Battery Mon 3 (Coulomb counter) */
REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON1, 8, BD71828_INT_BAT_CC_MON1_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON2, 8, BD71828_INT_BAT_CC_MON2_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON3, 8, BD71828_INT_BAT_CC_MON3_MASK),
/* Battery Mon 4 */
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_RES, 9, BD71828_INT_BAT_OVER_CURR_1_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_DET, 9, BD71828_INT_BAT_OVER_CURR_1_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_RES, 9, BD71828_INT_BAT_OVER_CURR_2_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_DET, 9, BD71828_INT_BAT_OVER_CURR_2_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_RES, 9, BD71828_INT_BAT_OVER_CURR_3_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_DET, 9, BD71828_INT_BAT_OVER_CURR_3_DET_MASK),
/* Temperature */
REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_RES, 10, BD71828_INT_TEMP_BAT_LOW_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_DET, 10, BD71828_INT_TEMP_BAT_LOW_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_RES, 10, BD71828_INT_TEMP_BAT_HI_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_DET, 10, BD71828_INT_TEMP_BAT_HI_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_RES, 10,
BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_DET, 10,
BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_DET, 10,
BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_RES, 10,
BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK),
/* RTC Alarm */
REGMAP_IRQ_REG(BD71828_INT_RTC0, 11, BD71828_INT_RTC0_MASK),
REGMAP_IRQ_REG(BD71828_INT_RTC1, 11, BD71828_INT_RTC1_MASK),
REGMAP_IRQ_REG(BD71828_INT_RTC2, 11, BD71828_INT_RTC2_MASK),
};
static struct regmap_irq_chip bd71828_irq_chip = {
.name = "bd71828_irq",
.main_status = BD71828_REG_INT_MAIN,
.irqs = &bd71828_irqs[0],
.num_irqs = ARRAY_SIZE(bd71828_irqs),
.status_base = BD71828_REG_INT_BUCK,
.unmask_base = BD71828_REG_INT_MASK_BUCK,
.ack_base = BD71828_REG_INT_BUCK,
.init_ack_masked = true,
.num_regs = 12,
.num_main_regs = 1,
.sub_reg_offsets = &bd718xx_sub_irq_offsets[0],
.num_main_status_bits = 8,
.irq_reg_stride = 1,
};
static struct regmap_irq_chip bd71815_irq_chip = {
.name = "bd71815_irq",
.main_status = BD71815_REG_INT_STAT,
.irqs = &bd71815_irqs[0],
.num_irqs = ARRAY_SIZE(bd71815_irqs),
.status_base = BD71815_REG_INT_STAT_01,
.unmask_base = BD71815_REG_INT_EN_01,
.ack_base = BD71815_REG_INT_STAT_01,
.init_ack_masked = true,
.num_regs = 12,
.num_main_regs = 1,
.sub_reg_offsets = &bd718xx_sub_irq_offsets[0],
.num_main_status_bits = 8,
.irq_reg_stride = 1,
};
static int set_clk_mode(struct device *dev, struct regmap *regmap,
int clkmode_reg)
{
int ret;
unsigned int open_drain;
ret = of_property_read_u32(dev->of_node, "rohm,clkout-open-drain", &open_drain);
if (ret) {
if (ret == -EINVAL)
return 0;
return ret;
}
if (open_drain > 1) {
dev_err(dev, "bad clk32kout mode configuration");
return -EINVAL;
}
if (open_drain)
return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE,
OUT32K_MODE_OPEN_DRAIN);
return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE,
OUT32K_MODE_CMOS);
}
static int bd71828_i2c_probe(struct i2c_client *i2c)
{
struct regmap_irq_chip_data *irq_data;
int ret;
struct regmap *regmap;
const struct regmap_config *regmap_config;
struct regmap_irq_chip *irqchip;
unsigned int chip_type;
struct mfd_cell *mfd;
int cells;
int button_irq;
int clkmode_reg;
if (!i2c->irq) {
dev_err(&i2c->dev, "No IRQ configured\n");
return -EINVAL;
}
chip_type = (unsigned int)(uintptr_t)
of_device_get_match_data(&i2c->dev);
switch (chip_type) {
case ROHM_CHIP_TYPE_BD71828:
mfd = bd71828_mfd_cells;
cells = ARRAY_SIZE(bd71828_mfd_cells);
regmap_config = &bd71828_regmap;
irqchip = &bd71828_irq_chip;
clkmode_reg = BD71828_REG_OUT32K;
button_irq = BD71828_INT_SHORTPUSH;
break;
case ROHM_CHIP_TYPE_BD71815:
mfd = bd71815_mfd_cells;
cells = ARRAY_SIZE(bd71815_mfd_cells);
regmap_config = &bd71815_regmap;
irqchip = &bd71815_irq_chip;
clkmode_reg = BD71815_REG_OUT32K;
/*
* If BD71817 support is needed we should be able to handle it
* with proper DT configs + BD71815 drivers + power-button.
* BD71815 data-sheet does not list the power-button IRQ so we
* don't use it.
*/
button_irq = 0;
break;
default:
dev_err(&i2c->dev, "Unknown device type");
return -EINVAL;
}
regmap = devm_regmap_init_i2c(i2c, regmap_config);
if (IS_ERR(regmap))
return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
"Failed to initialize Regmap\n");
ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq,
IRQF_ONESHOT, 0, irqchip, &irq_data);
if (ret)
return dev_err_probe(&i2c->dev, ret,
"Failed to add IRQ chip\n");
dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n",
irqchip->num_irqs);
if (button_irq) {
ret = regmap_irq_get_virq(irq_data, button_irq);
if (ret < 0)
return dev_err_probe(&i2c->dev, ret,
"Failed to get the power-key IRQ\n");
button.irq = ret;
}
ret = set_clk_mode(&i2c->dev, regmap, clkmode_reg);
if (ret)
return ret;
ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, mfd, cells,
NULL, 0, regmap_irq_get_domain(irq_data));
if (ret)
dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n");
return ret;
}
static const struct of_device_id bd71828_of_match[] = {
{
.compatible = "rohm,bd71828",
.data = (void *)ROHM_CHIP_TYPE_BD71828,
}, {
.compatible = "rohm,bd71815",
.data = (void *)ROHM_CHIP_TYPE_BD71815,
},
{ },
};
MODULE_DEVICE_TABLE(of, bd71828_of_match);
static struct i2c_driver bd71828_drv = {
.driver = {
.name = "rohm-bd71828",
.of_match_table = bd71828_of_match,
},
.probe = bd71828_i2c_probe,
};
module_i2c_driver(bd71828_drv);
MODULE_AUTHOR("Matti Vaittinen <[email protected]>");
MODULE_DESCRIPTION("ROHM BD71828 Power Management IC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/rohm-bd71828.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8350-i2c.c -- Generic I2C driver for Wolfson WM8350 PMIC
*
* Copyright 2007, 2008 Wolfson Microelectronics PLC.
*
* Author: Liam Girdwood
* [email protected]
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/mfd/wm8350/core.h>
#include <linux/regmap.h>
#include <linux/slab.h>
static int wm8350_i2c_probe(struct i2c_client *i2c)
{
struct wm8350 *wm8350;
struct wm8350_platform_data *pdata = dev_get_platdata(&i2c->dev);
int ret = 0;
wm8350 = devm_kzalloc(&i2c->dev, sizeof(struct wm8350), GFP_KERNEL);
if (wm8350 == NULL)
return -ENOMEM;
wm8350->regmap = devm_regmap_init_i2c(i2c, &wm8350_regmap);
if (IS_ERR(wm8350->regmap)) {
ret = PTR_ERR(wm8350->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
i2c_set_clientdata(i2c, wm8350);
wm8350->dev = &i2c->dev;
return wm8350_device_init(wm8350, i2c->irq, pdata);
}
static const struct i2c_device_id wm8350_i2c_id[] = {
{ "wm8350", 0 },
{ "wm8351", 0 },
{ "wm8352", 0 },
{ }
};
static struct i2c_driver wm8350_i2c_driver = {
.driver = {
.name = "wm8350",
.suppress_bind_attrs = true,
},
.probe = wm8350_i2c_probe,
.id_table = wm8350_i2c_id,
};
static int __init wm8350_i2c_init(void)
{
return i2c_add_driver(&wm8350_i2c_driver);
}
/* init early so consumer devices can complete system boot */
subsys_initcall(wm8350_i2c_init);
| linux-master | drivers/mfd/wm8350-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/* ADC MFD core driver for sunxi platforms
*
* Copyright (c) 2016 Quentin Schulz <[email protected]>
*/
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/sun4i-gpadc.h>
#define ARCH_SUN4I_A10 0
#define ARCH_SUN5I_A13 1
#define ARCH_SUN6I_A31 2
static const struct resource adc_resources[] = {
DEFINE_RES_IRQ_NAMED(SUN4I_GPADC_IRQ_FIFO_DATA, "FIFO_DATA_PENDING"),
DEFINE_RES_IRQ_NAMED(SUN4I_GPADC_IRQ_TEMP_DATA, "TEMP_DATA_PENDING"),
};
static const struct regmap_irq sun4i_gpadc_regmap_irq[] = {
REGMAP_IRQ_REG(SUN4I_GPADC_IRQ_FIFO_DATA, 0,
SUN4I_GPADC_INT_FIFOC_TP_DATA_IRQ_EN),
REGMAP_IRQ_REG(SUN4I_GPADC_IRQ_TEMP_DATA, 0,
SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN),
};
static const struct regmap_irq_chip sun4i_gpadc_regmap_irq_chip = {
.name = "sun4i_gpadc_irq_chip",
.status_base = SUN4I_GPADC_INT_FIFOS,
.ack_base = SUN4I_GPADC_INT_FIFOS,
.unmask_base = SUN4I_GPADC_INT_FIFOC,
.init_ack_masked = true,
.irqs = sun4i_gpadc_regmap_irq,
.num_irqs = ARRAY_SIZE(sun4i_gpadc_regmap_irq),
.num_regs = 1,
};
static struct mfd_cell sun4i_gpadc_cells[] = {
{
.name = "sun4i-a10-gpadc-iio",
.resources = adc_resources,
.num_resources = ARRAY_SIZE(adc_resources),
},
{ .name = "iio_hwmon" }
};
static struct mfd_cell sun5i_gpadc_cells[] = {
{
.name = "sun5i-a13-gpadc-iio",
.resources = adc_resources,
.num_resources = ARRAY_SIZE(adc_resources),
},
{ .name = "iio_hwmon" },
};
static struct mfd_cell sun6i_gpadc_cells[] = {
{
.name = "sun6i-a31-gpadc-iio",
.resources = adc_resources,
.num_resources = ARRAY_SIZE(adc_resources),
},
{ .name = "iio_hwmon" },
};
static const struct regmap_config sun4i_gpadc_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.fast_io = true,
};
static const struct of_device_id sun4i_gpadc_of_match[] = {
{
.compatible = "allwinner,sun4i-a10-ts",
.data = (void *)ARCH_SUN4I_A10,
}, {
.compatible = "allwinner,sun5i-a13-ts",
.data = (void *)ARCH_SUN5I_A13,
}, {
.compatible = "allwinner,sun6i-a31-ts",
.data = (void *)ARCH_SUN6I_A31,
}, { /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sun4i_gpadc_of_match);
static int sun4i_gpadc_probe(struct platform_device *pdev)
{
struct sun4i_gpadc_dev *dev;
const struct of_device_id *of_id;
const struct mfd_cell *cells;
unsigned int irq, size;
int ret;
of_id = of_match_node(sun4i_gpadc_of_match, pdev->dev.of_node);
if (!of_id)
return -EINVAL;
switch ((long)of_id->data) {
case ARCH_SUN4I_A10:
cells = sun4i_gpadc_cells;
size = ARRAY_SIZE(sun4i_gpadc_cells);
break;
case ARCH_SUN5I_A13:
cells = sun5i_gpadc_cells;
size = ARRAY_SIZE(sun5i_gpadc_cells);
break;
case ARCH_SUN6I_A31:
cells = sun6i_gpadc_cells;
size = ARRAY_SIZE(sun6i_gpadc_cells);
break;
default:
return -EINVAL;
}
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
if (!dev)
return -ENOMEM;
dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(dev->base))
return PTR_ERR(dev->base);
dev->dev = &pdev->dev;
dev_set_drvdata(dev->dev, dev);
dev->regmap = devm_regmap_init_mmio(dev->dev, dev->base,
&sun4i_gpadc_regmap_config);
if (IS_ERR(dev->regmap)) {
ret = PTR_ERR(dev->regmap);
dev_err(&pdev->dev, "failed to init regmap: %d\n", ret);
return ret;
}
/* Disable all interrupts */
regmap_write(dev->regmap, SUN4I_GPADC_INT_FIFOC, 0);
irq = platform_get_irq(pdev, 0);
ret = devm_regmap_add_irq_chip(&pdev->dev, dev->regmap, irq,
IRQF_ONESHOT, 0,
&sun4i_gpadc_regmap_irq_chip,
&dev->regmap_irqc);
if (ret) {
dev_err(&pdev->dev, "failed to add irq chip: %d\n", ret);
return ret;
}
ret = devm_mfd_add_devices(dev->dev, 0, cells, size, NULL, 0, NULL);
if (ret) {
dev_err(&pdev->dev, "failed to add MFD devices: %d\n", ret);
return ret;
}
return 0;
}
static struct platform_driver sun4i_gpadc_driver = {
.driver = {
.name = "sun4i-gpadc",
.of_match_table = sun4i_gpadc_of_match,
},
.probe = sun4i_gpadc_probe,
};
module_platform_driver(sun4i_gpadc_driver);
MODULE_DESCRIPTION("Allwinner sunxi platforms' GPADC MFD core driver");
MODULE_AUTHOR("Quentin Schulz <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/sun4i-gpadc.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Janz CMOD-IO MODULbus Carrier Board PCI Driver
*
* Copyright (c) 2010 Ira W. Snyder <[email protected]>
*
* Lots of inspiration and code was copied from drivers/mfd/sm501.c
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/mfd/core.h>
#include <linux/mfd/janz.h>
#define DRV_NAME "janz-cmodio"
/* Size of each MODULbus module in PCI BAR4 */
#define CMODIO_MODULBUS_SIZE 0x200
/* Maximum number of MODULbus modules on a CMOD-IO carrier board */
#define CMODIO_MAX_MODULES 4
/* Module Parameters */
static unsigned int num_modules = CMODIO_MAX_MODULES;
static char *modules[CMODIO_MAX_MODULES] = {
"empty", "empty", "empty", "empty",
};
module_param_array(modules, charp, &num_modules, S_IRUGO);
MODULE_PARM_DESC(modules, "MODULbus modules attached to the carrier board");
/* Unique Device Id */
static unsigned int cmodio_id;
struct cmodio_device {
/* Parent PCI device */
struct pci_dev *pdev;
/* PLX control registers */
struct janz_cmodio_onboard_regs __iomem *ctrl;
/* hex switch position */
u8 hex;
/* mfd-core API */
struct mfd_cell cells[CMODIO_MAX_MODULES];
struct resource resources[3 * CMODIO_MAX_MODULES];
struct janz_platform_data pdata[CMODIO_MAX_MODULES];
};
/*
* Subdevices using the mfd-core API
*/
static int cmodio_setup_subdevice(struct cmodio_device *priv,
char *name, unsigned int devno,
unsigned int modno)
{
struct janz_platform_data *pdata;
struct mfd_cell *cell;
struct resource *res;
struct pci_dev *pci;
pci = priv->pdev;
cell = &priv->cells[devno];
res = &priv->resources[devno * 3];
pdata = &priv->pdata[devno];
cell->name = name;
cell->resources = res;
cell->num_resources = 3;
/* Setup the subdevice ID -- must be unique */
cell->id = cmodio_id++;
/* Add platform data */
pdata->modno = modno;
cell->platform_data = pdata;
cell->pdata_size = sizeof(*pdata);
/* MODULbus registers -- PCI BAR3 is big-endian MODULbus access */
res->flags = IORESOURCE_MEM;
res->parent = &pci->resource[3];
res->start = pci->resource[3].start + (CMODIO_MODULBUS_SIZE * modno);
res->end = res->start + CMODIO_MODULBUS_SIZE - 1;
res++;
/* PLX Control Registers -- PCI BAR4 is interrupt and other registers */
res->flags = IORESOURCE_MEM;
res->parent = &pci->resource[4];
res->start = pci->resource[4].start;
res->end = pci->resource[4].end;
res++;
/*
* IRQ
*
* The start and end fields are used as an offset to the irq_base
* parameter passed into the mfd_add_devices() function call. All
* devices share the same IRQ.
*/
res->flags = IORESOURCE_IRQ;
res->parent = NULL;
res->start = 0;
res->end = 0;
res++;
return 0;
}
/* Probe each submodule using kernel parameters */
static int cmodio_probe_submodules(struct cmodio_device *priv)
{
struct pci_dev *pdev = priv->pdev;
unsigned int num_probed = 0;
char *name;
int i;
for (i = 0; i < num_modules; i++) {
name = modules[i];
if (!strcmp(name, "") || !strcmp(name, "empty"))
continue;
dev_dbg(&priv->pdev->dev, "MODULbus %d: name %s\n", i, name);
cmodio_setup_subdevice(priv, name, num_probed, i);
num_probed++;
}
/* print an error message if no modules were probed */
if (num_probed == 0) {
dev_err(&priv->pdev->dev, "no MODULbus modules specified, "
"please set the ``modules'' kernel "
"parameter according to your "
"hardware configuration\n");
return -ENODEV;
}
return mfd_add_devices(&pdev->dev, 0, priv->cells,
num_probed, NULL, pdev->irq, NULL);
}
/*
* SYSFS Attributes
*/
static ssize_t modulbus_number_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct cmodio_device *priv = dev_get_drvdata(dev);
return sysfs_emit(buf, "%x\n", priv->hex);
}
static DEVICE_ATTR_RO(modulbus_number);
static struct attribute *cmodio_sysfs_attrs[] = {
&dev_attr_modulbus_number.attr,
NULL,
};
static const struct attribute_group cmodio_sysfs_attr_group = {
.attrs = cmodio_sysfs_attrs,
};
/*
* PCI Driver
*/
static int cmodio_pci_probe(struct pci_dev *dev,
const struct pci_device_id *id)
{
struct cmodio_device *priv;
int ret;
priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
pci_set_drvdata(dev, priv);
priv->pdev = dev;
/* Hardware Initialization */
ret = pci_enable_device(dev);
if (ret) {
dev_err(&dev->dev, "unable to enable device\n");
return ret;
}
pci_set_master(dev);
ret = pci_request_regions(dev, DRV_NAME);
if (ret) {
dev_err(&dev->dev, "unable to request regions\n");
goto out_pci_disable_device;
}
/* Onboard configuration registers */
priv->ctrl = pci_ioremap_bar(dev, 4);
if (!priv->ctrl) {
dev_err(&dev->dev, "unable to remap onboard regs\n");
ret = -ENOMEM;
goto out_pci_release_regions;
}
/* Read the hex switch on the carrier board */
priv->hex = ioread8(&priv->ctrl->int_enable);
/* Add the MODULbus number (hex switch value) to the device's sysfs */
ret = sysfs_create_group(&dev->dev.kobj, &cmodio_sysfs_attr_group);
if (ret) {
dev_err(&dev->dev, "unable to create sysfs attributes\n");
goto out_unmap_ctrl;
}
/*
* Disable all interrupt lines, each submodule will enable its
* own interrupt line if needed
*/
iowrite8(0xf, &priv->ctrl->int_disable);
/* Register drivers for all submodules */
ret = cmodio_probe_submodules(priv);
if (ret) {
dev_err(&dev->dev, "unable to probe submodules\n");
goto out_sysfs_remove_group;
}
return 0;
out_sysfs_remove_group:
sysfs_remove_group(&dev->dev.kobj, &cmodio_sysfs_attr_group);
out_unmap_ctrl:
iounmap(priv->ctrl);
out_pci_release_regions:
pci_release_regions(dev);
out_pci_disable_device:
pci_disable_device(dev);
return ret;
}
static void cmodio_pci_remove(struct pci_dev *dev)
{
struct cmodio_device *priv = pci_get_drvdata(dev);
mfd_remove_devices(&dev->dev);
sysfs_remove_group(&dev->dev.kobj, &cmodio_sysfs_attr_group);
iounmap(priv->ctrl);
pci_release_regions(dev);
pci_disable_device(dev);
}
#define PCI_VENDOR_ID_JANZ 0x13c3
/* The list of devices that this module will support */
static const struct pci_device_id cmodio_pci_ids[] = {
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_JANZ, 0x0101 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_JANZ, 0x0100 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_JANZ, 0x0201 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_JANZ, 0x0202 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_JANZ, 0x0201 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_JANZ, 0x0202 },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, cmodio_pci_ids);
static struct pci_driver cmodio_pci_driver = {
.name = DRV_NAME,
.id_table = cmodio_pci_ids,
.probe = cmodio_pci_probe,
.remove = cmodio_pci_remove,
};
module_pci_driver(cmodio_pci_driver);
MODULE_AUTHOR("Ira W. Snyder <[email protected]>");
MODULE_DESCRIPTION("Janz CMOD-IO PCI MODULbus Carrier Board Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/janz-cmodio.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Rockchip RK808/RK818 Core (I2C) driver
*
* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
* Copyright (C) 2016 PHYTEC Messtechnik GmbH
*
* Author: Chris Zhong <[email protected]>
* Author: Zhang Qing <[email protected]>
* Author: Wadim Egorov <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/mfd/rk808.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
struct rk8xx_i2c_platform_data {
const struct regmap_config *regmap_cfg;
int variant;
};
static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg)
{
/*
* Notes:
* - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but
* we don't use that feature. It's better to cache.
* - It's unlikely we care that RK808_DEVCTRL_REG is volatile since
* bits are cleared in case when we shutoff anyway, but better safe.
*/
switch (reg) {
case RK808_SECONDS_REG ... RK808_WEEKS_REG:
case RK808_RTC_STATUS_REG:
case RK808_VB_MON_REG:
case RK808_THERMAL_REG:
case RK808_DCDC_UV_STS_REG:
case RK808_LDO_UV_STS_REG:
case RK808_DCDC_PG_REG:
case RK808_LDO_PG_REG:
case RK808_DEVCTRL_REG:
case RK808_INT_STS_REG1:
case RK808_INT_STS_REG2:
return true;
}
return false;
}
static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg)
{
/*
* Notes:
* - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but
* we don't use that feature. It's better to cache.
*/
switch (reg) {
case RK817_SECONDS_REG ... RK817_WEEKS_REG:
case RK817_RTC_STATUS_REG:
case RK817_CODEC_DTOP_LPT_SRST:
case RK817_GAS_GAUGE_ADC_CONFIG0 ... RK817_GAS_GAUGE_CUR_ADC_K0:
case RK817_PMIC_CHRG_STS:
case RK817_PMIC_CHRG_OUT:
case RK817_PMIC_CHRG_IN:
case RK817_INT_STS_REG0:
case RK817_INT_STS_REG1:
case RK817_INT_STS_REG2:
case RK817_SYS_STS:
return true;
}
return false;
}
static const struct regmap_config rk818_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = RK818_USB_CTRL_REG,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = rk808_is_volatile_reg,
};
static const struct regmap_config rk805_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = RK805_OFF_SOURCE_REG,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = rk808_is_volatile_reg,
};
static const struct regmap_config rk808_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = RK808_IO_POL_REG,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = rk808_is_volatile_reg,
};
static const struct regmap_config rk817_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = RK817_GPIO_INT_CFG,
.cache_type = REGCACHE_NONE,
.volatile_reg = rk817_is_volatile_reg,
};
static const struct rk8xx_i2c_platform_data rk805_data = {
.regmap_cfg = &rk805_regmap_config,
.variant = RK805_ID,
};
static const struct rk8xx_i2c_platform_data rk808_data = {
.regmap_cfg = &rk808_regmap_config,
.variant = RK808_ID,
};
static const struct rk8xx_i2c_platform_data rk809_data = {
.regmap_cfg = &rk817_regmap_config,
.variant = RK809_ID,
};
static const struct rk8xx_i2c_platform_data rk817_data = {
.regmap_cfg = &rk817_regmap_config,
.variant = RK817_ID,
};
static const struct rk8xx_i2c_platform_data rk818_data = {
.regmap_cfg = &rk818_regmap_config,
.variant = RK818_ID,
};
static int rk8xx_i2c_probe(struct i2c_client *client)
{
const struct rk8xx_i2c_platform_data *data;
struct regmap *regmap;
data = device_get_match_data(&client->dev);
if (!data)
return -ENODEV;
regmap = devm_regmap_init_i2c(client, data->regmap_cfg);
if (IS_ERR(regmap))
return dev_err_probe(&client->dev, PTR_ERR(regmap),
"regmap initialization failed\n");
return rk8xx_probe(&client->dev, data->variant, client->irq, regmap);
}
static void rk8xx_i2c_shutdown(struct i2c_client *client)
{
rk8xx_shutdown(&client->dev);
}
static SIMPLE_DEV_PM_OPS(rk8xx_i2c_pm_ops, rk8xx_suspend, rk8xx_resume);
static const struct of_device_id rk8xx_i2c_of_match[] = {
{ .compatible = "rockchip,rk805", .data = &rk805_data },
{ .compatible = "rockchip,rk808", .data = &rk808_data },
{ .compatible = "rockchip,rk809", .data = &rk809_data },
{ .compatible = "rockchip,rk817", .data = &rk817_data },
{ .compatible = "rockchip,rk818", .data = &rk818_data },
{ },
};
MODULE_DEVICE_TABLE(of, rk8xx_i2c_of_match);
static struct i2c_driver rk8xx_i2c_driver = {
.driver = {
.name = "rk8xx-i2c",
.of_match_table = rk8xx_i2c_of_match,
.pm = &rk8xx_i2c_pm_ops,
},
.probe = rk8xx_i2c_probe,
.shutdown = rk8xx_i2c_shutdown,
};
module_i2c_driver(rk8xx_i2c_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Chris Zhong <[email protected]>");
MODULE_AUTHOR("Zhang Qing <[email protected]>");
MODULE_AUTHOR("Wadim Egorov <[email protected]>");
MODULE_DESCRIPTION("RK8xx I2C PMIC driver");
| linux-master | drivers/mfd/rk8xx-i2c.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* I2C access for DA9052 PMICs.
*
* Copyright(c) 2011 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <[email protected]>
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/input.h>
#include <linux/mfd/core.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/mfd/da9052/da9052.h>
#include <linux/mfd/da9052/reg.h>
/* I2C safe register check */
static inline bool i2c_safe_reg(unsigned char reg)
{
switch (reg) {
case DA9052_STATUS_A_REG:
case DA9052_STATUS_B_REG:
case DA9052_STATUS_C_REG:
case DA9052_STATUS_D_REG:
case DA9052_ADC_RES_L_REG:
case DA9052_ADC_RES_H_REG:
case DA9052_VDD_RES_REG:
case DA9052_ICHG_AV_REG:
case DA9052_TBAT_RES_REG:
case DA9052_ADCIN4_RES_REG:
case DA9052_ADCIN5_RES_REG:
case DA9052_ADCIN6_RES_REG:
case DA9052_TJUNC_RES_REG:
case DA9052_TSI_X_MSB_REG:
case DA9052_TSI_Y_MSB_REG:
case DA9052_TSI_LSB_REG:
case DA9052_TSI_Z_MSB_REG:
return true;
default:
return false;
}
}
/*
* There is an issue with DA9052 and DA9053_AA/BA/BB PMIC where the PMIC
* gets lockup up or fails to respond following a system reset.
* This fix is to follow any read or write with a dummy read to a safe
* register.
*/
static int da9052_i2c_fix(struct da9052 *da9052, unsigned char reg)
{
int val;
switch (da9052->chip_id) {
case DA9052:
case DA9053_AA:
case DA9053_BA:
case DA9053_BB:
/* A dummy read to a safe register address. */
if (!i2c_safe_reg(reg))
return regmap_read(da9052->regmap,
DA9052_PARK_REGISTER,
&val);
break;
case DA9053_BC:
default:
/*
* For other chips parking of I2C register
* to a safe place is not required.
*/
break;
}
return 0;
}
/*
* According to errata item 24, multiwrite mode should be avoided
* in order to prevent register data corruption after power-down.
*/
static int da9052_i2c_disable_multiwrite(struct da9052 *da9052)
{
int reg_val, ret;
ret = regmap_read(da9052->regmap, DA9052_CONTROL_B_REG, ®_val);
if (ret < 0)
return ret;
if (!(reg_val & DA9052_CONTROL_B_WRITEMODE)) {
reg_val |= DA9052_CONTROL_B_WRITEMODE;
ret = regmap_write(da9052->regmap, DA9052_CONTROL_B_REG,
reg_val);
if (ret < 0)
return ret;
}
return 0;
}
static const struct i2c_device_id da9052_i2c_id[] = {
{"da9052", DA9052},
{"da9053-aa", DA9053_AA},
{"da9053-ba", DA9053_BA},
{"da9053-bb", DA9053_BB},
{"da9053-bc", DA9053_BC},
{}
};
MODULE_DEVICE_TABLE(i2c, da9052_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id dialog_dt_ids[] = {
{ .compatible = "dlg,da9052", .data = &da9052_i2c_id[0] },
{ .compatible = "dlg,da9053-aa", .data = &da9052_i2c_id[1] },
{ .compatible = "dlg,da9053-ba", .data = &da9052_i2c_id[2] },
{ .compatible = "dlg,da9053-bb", .data = &da9052_i2c_id[3] },
{ .compatible = "dlg,da9053-bc", .data = &da9052_i2c_id[4] },
{ /* sentinel */ }
};
#endif
static int da9052_i2c_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct da9052 *da9052;
int ret;
da9052 = devm_kzalloc(&client->dev, sizeof(struct da9052), GFP_KERNEL);
if (!da9052)
return -ENOMEM;
da9052->dev = &client->dev;
da9052->chip_irq = client->irq;
da9052->fix_io = da9052_i2c_fix;
i2c_set_clientdata(client, da9052);
da9052->regmap = devm_regmap_init_i2c(client, &da9052_regmap_config);
if (IS_ERR(da9052->regmap)) {
ret = PTR_ERR(da9052->regmap);
dev_err(&client->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
ret = da9052_i2c_disable_multiwrite(da9052);
if (ret < 0)
return ret;
#ifdef CONFIG_OF
if (!id)
id = of_device_get_match_data(&client->dev);
#endif
if (!id) {
ret = -ENODEV;
dev_err(&client->dev, "id is null.\n");
return ret;
}
return da9052_device_init(da9052, id->driver_data);
}
static void da9052_i2c_remove(struct i2c_client *client)
{
struct da9052 *da9052 = i2c_get_clientdata(client);
da9052_device_exit(da9052);
}
static struct i2c_driver da9052_i2c_driver = {
.probe = da9052_i2c_probe,
.remove = da9052_i2c_remove,
.id_table = da9052_i2c_id,
.driver = {
.name = "da9052",
#ifdef CONFIG_OF
.of_match_table = dialog_dt_ids,
#endif
},
};
static int __init da9052_i2c_init(void)
{
int ret;
ret = i2c_add_driver(&da9052_i2c_driver);
if (ret != 0) {
pr_err("DA9052 I2C registration failed %d\n", ret);
return ret;
}
return 0;
}
subsys_initcall(da9052_i2c_init);
static void __exit da9052_i2c_exit(void)
{
i2c_del_driver(&da9052_i2c_driver);
}
module_exit(da9052_i2c_exit);
MODULE_AUTHOR("David Dajun Chen <[email protected]>");
MODULE_DESCRIPTION("I2C driver for Dialog DA9052 PMIC");
| linux-master | drivers/mfd/da9052-i2c.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Device driver for regulators in HISI PMIC IC
*
* Copyright (c) 2013 Linaro Ltd.
* Copyright (c) 2011 Hisilicon.
* Copyright (c) 2020-2021 Huawei Technologies Co., Ltd.
*/
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/spmi.h>
static const struct mfd_cell hi6421v600_devs[] = {
{ .name = "hi6421v600-irq", },
{ .name = "hi6421v600-regulator", },
};
static const struct regmap_config regmap_config = {
.reg_bits = 16,
.val_bits = BITS_PER_BYTE,
.max_register = 0xffff,
.fast_io = true
};
static int hi6421_spmi_pmic_probe(struct spmi_device *sdev)
{
struct device *dev = &sdev->dev;
struct regmap *regmap;
int ret;
regmap = devm_regmap_init_spmi_ext(sdev, ®map_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
dev_set_drvdata(&sdev->dev, regmap);
ret = devm_mfd_add_devices(&sdev->dev, PLATFORM_DEVID_NONE,
hi6421v600_devs, ARRAY_SIZE(hi6421v600_devs),
NULL, 0, NULL);
if (ret < 0)
dev_err(dev, "Failed to add child devices: %d\n", ret);
return ret;
}
static const struct of_device_id pmic_spmi_id_table[] = {
{ .compatible = "hisilicon,hi6421-spmi" },
{ }
};
MODULE_DEVICE_TABLE(of, pmic_spmi_id_table);
static struct spmi_driver hi6421_spmi_pmic_driver = {
.driver = {
.name = "hi6421-spmi-pmic",
.of_match_table = pmic_spmi_id_table,
},
.probe = hi6421_spmi_pmic_probe,
};
module_spmi_driver(hi6421_spmi_pmic_driver);
MODULE_DESCRIPTION("HiSilicon Hi6421v600 SPMI PMIC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/hi6421-spmi-pmic.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for the Intel Broxton PMC
*
* (C) Copyright 2014 - 2020 Intel Corporation
*
* This driver is based on Intel SCU IPC driver (intel_scu_ipc.c) by
* Sreedhara DS <[email protected]>
*
* The PMC (Power Management Controller) running on the ARC processor
* communicates with another entity running in the IA (Intel Architecture)
* core through an IPC (Intel Processor Communications) mechanism which in
* turn sends messages between the IA and the PMC.
*/
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel_pmc_bxt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/platform_data/itco_wdt.h>
#include <asm/intel_scu_ipc.h>
/* Residency with clock rate at 19.2MHz to usecs */
#define S0IX_RESIDENCY_IN_USECS(d, s) \
({ \
u64 result = 10ull * ((d) + (s)); \
do_div(result, 192); \
result; \
})
/* Resources exported from IFWI */
#define PLAT_RESOURCE_IPC_INDEX 0
#define PLAT_RESOURCE_IPC_SIZE 0x1000
#define PLAT_RESOURCE_GCR_OFFSET 0x1000
#define PLAT_RESOURCE_GCR_SIZE 0x1000
#define PLAT_RESOURCE_BIOS_DATA_INDEX 1
#define PLAT_RESOURCE_BIOS_IFACE_INDEX 2
#define PLAT_RESOURCE_TELEM_SSRAM_INDEX 3
#define PLAT_RESOURCE_ISP_DATA_INDEX 4
#define PLAT_RESOURCE_ISP_IFACE_INDEX 5
#define PLAT_RESOURCE_GTD_DATA_INDEX 6
#define PLAT_RESOURCE_GTD_IFACE_INDEX 7
#define PLAT_RESOURCE_ACPI_IO_INDEX 0
/*
* BIOS does not create an ACPI device for each PMC function, but
* exports multiple resources from one ACPI device (IPC) for multiple
* functions. This driver is responsible for creating a child device and
* to export resources for those functions.
*/
#define SMI_EN_OFFSET 0x0040
#define SMI_EN_SIZE 4
#define TCO_BASE_OFFSET 0x0060
#define TCO_REGS_SIZE 16
#define TELEM_SSRAM_SIZE 240
#define TELEM_PMC_SSRAM_OFFSET 0x1b00
#define TELEM_PUNIT_SSRAM_OFFSET 0x1a00
/* Commands */
#define PMC_NORTHPEAK_CTRL 0xed
static inline bool is_gcr_valid(u32 offset)
{
return offset < PLAT_RESOURCE_GCR_SIZE - 8;
}
/**
* intel_pmc_gcr_read64() - Read a 64-bit PMC GCR register
* @pmc: PMC device pointer
* @offset: offset of GCR register from GCR address base
* @data: data pointer for storing the register output
*
* Reads the 64-bit PMC GCR register at given offset.
*
* Return: Negative value on error or 0 on success.
*/
int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset, u64 *data)
{
if (!is_gcr_valid(offset))
return -EINVAL;
spin_lock(&pmc->gcr_lock);
*data = readq(pmc->gcr_mem_base + offset);
spin_unlock(&pmc->gcr_lock);
return 0;
}
EXPORT_SYMBOL_GPL(intel_pmc_gcr_read64);
/**
* intel_pmc_gcr_update() - Update PMC GCR register bits
* @pmc: PMC device pointer
* @offset: offset of GCR register from GCR address base
* @mask: bit mask for update operation
* @val: update value
*
* Updates the bits of given GCR register as specified by
* @mask and @val.
*
* Return: Negative value on error or 0 on success.
*/
int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset, u32 mask, u32 val)
{
u32 new_val;
if (!is_gcr_valid(offset))
return -EINVAL;
spin_lock(&pmc->gcr_lock);
new_val = readl(pmc->gcr_mem_base + offset);
new_val = (new_val & ~mask) | (val & mask);
writel(new_val, pmc->gcr_mem_base + offset);
new_val = readl(pmc->gcr_mem_base + offset);
spin_unlock(&pmc->gcr_lock);
/* Check whether the bit update is successful */
return (new_val & mask) != (val & mask) ? -EIO : 0;
}
EXPORT_SYMBOL_GPL(intel_pmc_gcr_update);
/**
* intel_pmc_s0ix_counter_read() - Read S0ix residency
* @pmc: PMC device pointer
* @data: Out param that contains current S0ix residency count.
*
* Writes to @data how many usecs the system has been in low-power S0ix
* state.
*
* Return: An error code or 0 on success.
*/
int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data)
{
u64 deep, shlw;
spin_lock(&pmc->gcr_lock);
deep = readq(pmc->gcr_mem_base + PMC_GCR_TELEM_DEEP_S0IX_REG);
shlw = readq(pmc->gcr_mem_base + PMC_GCR_TELEM_SHLW_S0IX_REG);
spin_unlock(&pmc->gcr_lock);
*data = S0IX_RESIDENCY_IN_USECS(deep, shlw);
return 0;
}
EXPORT_SYMBOL_GPL(intel_pmc_s0ix_counter_read);
/**
* simplecmd_store() - Send a simple IPC command
* @dev: Device under the attribute is
* @attr: Attribute in question
* @buf: Buffer holding data to be stored to the attribute
* @count: Number of bytes in @buf
*
* Expects a string with two integers separated with space. These two
* values hold command and subcommand that is send to PMC.
*
* Return: Number number of bytes written (@count) or negative errno in
* case of error.
*/
static ssize_t simplecmd_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct intel_pmc_dev *pmc = dev_get_drvdata(dev);
struct intel_scu_ipc_dev *scu = pmc->scu;
int subcmd;
int cmd;
int ret;
ret = sscanf(buf, "%d %d", &cmd, &subcmd);
if (ret != 2) {
dev_err(dev, "Invalid values, expected: cmd subcmd\n");
return -EINVAL;
}
ret = intel_scu_ipc_dev_simple_command(scu, cmd, subcmd);
if (ret)
return ret;
return count;
}
static DEVICE_ATTR_WO(simplecmd);
/**
* northpeak_store() - Enable or disable Northpeak
* @dev: Device under the attribute is
* @attr: Attribute in question
* @buf: Buffer holding data to be stored to the attribute
* @count: Number of bytes in @buf
*
* Expects an unsigned integer. Non-zero enables Northpeak and zero
* disables it.
*
* Return: Number number of bytes written (@count) or negative errno in
* case of error.
*/
static ssize_t northpeak_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct intel_pmc_dev *pmc = dev_get_drvdata(dev);
struct intel_scu_ipc_dev *scu = pmc->scu;
unsigned long val;
int subcmd;
int ret;
ret = kstrtoul(buf, 0, &val);
if (ret)
return ret;
/* Northpeak is enabled if subcmd == 1 and disabled if it is 0 */
if (val)
subcmd = 1;
else
subcmd = 0;
ret = intel_scu_ipc_dev_simple_command(scu, PMC_NORTHPEAK_CTRL, subcmd);
if (ret)
return ret;
return count;
}
static DEVICE_ATTR_WO(northpeak);
static struct attribute *intel_pmc_attrs[] = {
&dev_attr_northpeak.attr,
&dev_attr_simplecmd.attr,
NULL
};
static const struct attribute_group intel_pmc_group = {
.attrs = intel_pmc_attrs,
};
static const struct attribute_group *intel_pmc_groups[] = {
&intel_pmc_group,
NULL
};
static struct resource punit_res[6];
static struct mfd_cell punit = {
.name = "intel_punit_ipc",
.resources = punit_res,
};
static struct itco_wdt_platform_data tco_pdata = {
.name = "Apollo Lake SoC",
.version = 5,
.no_reboot_use_pmc = true,
};
static struct resource tco_res[2];
static const struct mfd_cell tco = {
.name = "iTCO_wdt",
.ignore_resource_conflicts = true,
.resources = tco_res,
.num_resources = ARRAY_SIZE(tco_res),
.platform_data = &tco_pdata,
.pdata_size = sizeof(tco_pdata),
};
static const struct resource telem_res[] = {
DEFINE_RES_MEM(TELEM_PUNIT_SSRAM_OFFSET, TELEM_SSRAM_SIZE),
DEFINE_RES_MEM(TELEM_PMC_SSRAM_OFFSET, TELEM_SSRAM_SIZE),
};
static const struct mfd_cell telem = {
.name = "intel_telemetry",
.resources = telem_res,
.num_resources = ARRAY_SIZE(telem_res),
};
static int intel_pmc_get_tco_resources(struct platform_device *pdev)
{
struct resource *res;
if (acpi_has_watchdog())
return 0;
res = platform_get_resource(pdev, IORESOURCE_IO,
PLAT_RESOURCE_ACPI_IO_INDEX);
if (!res) {
dev_err(&pdev->dev, "Failed to get IO resource\n");
return -EINVAL;
}
tco_res[0].flags = IORESOURCE_IO;
tco_res[0].start = res->start + TCO_BASE_OFFSET;
tco_res[0].end = tco_res[0].start + TCO_REGS_SIZE - 1;
tco_res[1].flags = IORESOURCE_IO;
tco_res[1].start = res->start + SMI_EN_OFFSET;
tco_res[1].end = tco_res[1].start + SMI_EN_SIZE - 1;
return 0;
}
static int intel_pmc_get_resources(struct platform_device *pdev,
struct intel_pmc_dev *pmc,
struct intel_scu_ipc_data *scu_data)
{
struct resource gcr_res;
size_t npunit_res = 0;
struct resource *res;
int ret;
scu_data->irq = platform_get_irq_optional(pdev, 0);
res = platform_get_resource(pdev, IORESOURCE_MEM,
PLAT_RESOURCE_IPC_INDEX);
if (!res) {
dev_err(&pdev->dev, "Failed to get IPC resource\n");
return -EINVAL;
}
/* IPC registers */
scu_data->mem.flags = res->flags;
scu_data->mem.start = res->start;
scu_data->mem.end = res->start + PLAT_RESOURCE_IPC_SIZE - 1;
/* GCR registers */
gcr_res.flags = res->flags;
gcr_res.start = res->start + PLAT_RESOURCE_GCR_OFFSET;
gcr_res.end = gcr_res.start + PLAT_RESOURCE_GCR_SIZE - 1;
pmc->gcr_mem_base = devm_ioremap_resource(&pdev->dev, &gcr_res);
if (IS_ERR(pmc->gcr_mem_base))
return PTR_ERR(pmc->gcr_mem_base);
/* Only register iTCO watchdog if there is no WDAT ACPI table */
ret = intel_pmc_get_tco_resources(pdev);
if (ret)
return ret;
/* BIOS data register */
res = platform_get_resource(pdev, IORESOURCE_MEM,
PLAT_RESOURCE_BIOS_DATA_INDEX);
if (!res) {
dev_err(&pdev->dev, "Failed to get resource of P-unit BIOS data\n");
return -EINVAL;
}
punit_res[npunit_res++] = *res;
/* BIOS interface register */
res = platform_get_resource(pdev, IORESOURCE_MEM,
PLAT_RESOURCE_BIOS_IFACE_INDEX);
if (!res) {
dev_err(&pdev->dev, "Failed to get resource of P-unit BIOS interface\n");
return -EINVAL;
}
punit_res[npunit_res++] = *res;
/* ISP data register, optional */
res = platform_get_resource(pdev, IORESOURCE_MEM,
PLAT_RESOURCE_ISP_DATA_INDEX);
if (res)
punit_res[npunit_res++] = *res;
/* ISP interface register, optional */
res = platform_get_resource(pdev, IORESOURCE_MEM,
PLAT_RESOURCE_ISP_IFACE_INDEX);
if (res)
punit_res[npunit_res++] = *res;
/* GTD data register, optional */
res = platform_get_resource(pdev, IORESOURCE_MEM,
PLAT_RESOURCE_GTD_DATA_INDEX);
if (res)
punit_res[npunit_res++] = *res;
/* GTD interface register, optional */
res = platform_get_resource(pdev, IORESOURCE_MEM,
PLAT_RESOURCE_GTD_IFACE_INDEX);
if (res)
punit_res[npunit_res++] = *res;
punit.num_resources = npunit_res;
/* Telemetry SSRAM is optional */
res = platform_get_resource(pdev, IORESOURCE_MEM,
PLAT_RESOURCE_TELEM_SSRAM_INDEX);
if (res)
pmc->telem_base = res;
return 0;
}
static int intel_pmc_create_devices(struct intel_pmc_dev *pmc)
{
int ret;
if (!acpi_has_watchdog()) {
ret = devm_mfd_add_devices(pmc->dev, PLATFORM_DEVID_AUTO, &tco,
1, NULL, 0, NULL);
if (ret)
return ret;
}
ret = devm_mfd_add_devices(pmc->dev, PLATFORM_DEVID_AUTO, &punit, 1,
NULL, 0, NULL);
if (ret)
return ret;
if (pmc->telem_base) {
ret = devm_mfd_add_devices(pmc->dev, PLATFORM_DEVID_AUTO,
&telem, 1, pmc->telem_base, 0, NULL);
}
return ret;
}
static const struct acpi_device_id intel_pmc_acpi_ids[] = {
{ "INT34D2" },
{ }
};
MODULE_DEVICE_TABLE(acpi, intel_pmc_acpi_ids);
static int intel_pmc_probe(struct platform_device *pdev)
{
struct intel_scu_ipc_data scu_data = {};
struct intel_pmc_dev *pmc;
int ret;
pmc = devm_kzalloc(&pdev->dev, sizeof(*pmc), GFP_KERNEL);
if (!pmc)
return -ENOMEM;
pmc->dev = &pdev->dev;
spin_lock_init(&pmc->gcr_lock);
ret = intel_pmc_get_resources(pdev, pmc, &scu_data);
if (ret) {
dev_err(&pdev->dev, "Failed to request resources\n");
return ret;
}
pmc->scu = devm_intel_scu_ipc_register(&pdev->dev, &scu_data);
if (IS_ERR(pmc->scu))
return PTR_ERR(pmc->scu);
platform_set_drvdata(pdev, pmc);
ret = intel_pmc_create_devices(pmc);
if (ret)
dev_err(&pdev->dev, "Failed to create PMC devices\n");
return ret;
}
static struct platform_driver intel_pmc_driver = {
.probe = intel_pmc_probe,
.driver = {
.name = "intel_pmc_bxt",
.acpi_match_table = intel_pmc_acpi_ids,
.dev_groups = intel_pmc_groups,
},
};
module_platform_driver(intel_pmc_driver);
MODULE_AUTHOR("Mika Westerberg <[email protected]>");
MODULE_AUTHOR("Zha Qipeng <[email protected]>");
MODULE_DESCRIPTION("Intel Broxton PMC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/intel_pmc_bxt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs5535-mfd.c - core MFD driver for CS5535/CS5536 southbridges
*
* The CS5535 and CS5536 has an ISA bridge on the PCI bus that is
* used for accessing GPIOs, MFGPTs, ACPI, etc. Each subdevice has
* an IO range that's specified in a single BAR. The BAR order is
* hardcoded in the CS553x specifications.
*
* Copyright (c) 2010 Andres Salomon <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <asm/olpc.h>
#define DRV_NAME "cs5535-mfd"
enum cs5535_mfd_bars {
SMB_BAR = 0,
GPIO_BAR = 1,
MFGPT_BAR = 2,
PMS_BAR = 4,
ACPI_BAR = 5,
NR_BARS,
};
static struct resource cs5535_mfd_resources[NR_BARS];
static struct mfd_cell cs5535_mfd_cells[] = {
{
.name = "cs5535-smb",
.num_resources = 1,
.resources = &cs5535_mfd_resources[SMB_BAR],
},
{
.name = "cs5535-gpio",
.num_resources = 1,
.resources = &cs5535_mfd_resources[GPIO_BAR],
},
{
.name = "cs5535-mfgpt",
.num_resources = 1,
.resources = &cs5535_mfd_resources[MFGPT_BAR],
},
{
.name = "cs5535-pms",
.num_resources = 1,
.resources = &cs5535_mfd_resources[PMS_BAR],
},
};
static struct mfd_cell cs5535_olpc_mfd_cells[] = {
{
.name = "olpc-xo1-pm-acpi",
.num_resources = 1,
.resources = &cs5535_mfd_resources[ACPI_BAR],
},
{
.name = "olpc-xo1-sci-acpi",
.num_resources = 1,
.resources = &cs5535_mfd_resources[ACPI_BAR],
},
};
static int cs5535_mfd_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
int err, bar;
err = pci_enable_device(pdev);
if (err)
return err;
for (bar = 0; bar < NR_BARS; bar++) {
struct resource *r = &cs5535_mfd_resources[bar];
r->flags = IORESOURCE_IO;
r->start = pci_resource_start(pdev, bar);
r->end = pci_resource_end(pdev, bar);
}
err = pci_request_region(pdev, PMS_BAR, DRV_NAME);
if (err) {
dev_err(&pdev->dev, "Failed to request PMS_BAR's IO region\n");
goto err_disable;
}
err = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, cs5535_mfd_cells,
ARRAY_SIZE(cs5535_mfd_cells), NULL, 0, NULL);
if (err) {
dev_err(&pdev->dev,
"Failed to add CS5535 sub-devices: %d\n", err);
goto err_release_pms;
}
if (machine_is_olpc()) {
err = pci_request_region(pdev, ACPI_BAR, DRV_NAME);
if (err) {
dev_err(&pdev->dev,
"Failed to request ACPI_BAR's IO region\n");
goto err_remove_devices;
}
err = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE,
cs5535_olpc_mfd_cells,
ARRAY_SIZE(cs5535_olpc_mfd_cells),
NULL, 0, NULL);
if (err) {
dev_err(&pdev->dev,
"Failed to add CS5535 OLPC sub-devices: %d\n",
err);
goto err_release_acpi;
}
}
dev_info(&pdev->dev, "%zu devices registered.\n",
ARRAY_SIZE(cs5535_mfd_cells));
return 0;
err_release_acpi:
pci_release_region(pdev, ACPI_BAR);
err_remove_devices:
mfd_remove_devices(&pdev->dev);
err_release_pms:
pci_release_region(pdev, PMS_BAR);
err_disable:
pci_disable_device(pdev);
return err;
}
static void cs5535_mfd_remove(struct pci_dev *pdev)
{
mfd_remove_devices(&pdev->dev);
if (machine_is_olpc())
pci_release_region(pdev, ACPI_BAR);
pci_release_region(pdev, PMS_BAR);
pci_disable_device(pdev);
}
static const struct pci_device_id cs5535_mfd_pci_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA) },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, cs5535_mfd_pci_tbl);
static struct pci_driver cs5535_mfd_driver = {
.name = DRV_NAME,
.id_table = cs5535_mfd_pci_tbl,
.probe = cs5535_mfd_probe,
.remove = cs5535_mfd_remove,
};
module_pci_driver(cs5535_mfd_driver);
MODULE_AUTHOR("Andres Salomon <[email protected]>");
MODULE_DESCRIPTION("MFD driver for CS5535/CS5536 southbridge's ISA PCI device");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/cs5535-mfd.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI Touch Screen / ADC MFD driver
*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/mfd/ti_am335x_tscadc.h>
static const struct regmap_config tscadc_regmap_config = {
.name = "ti_tscadc",
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
};
void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tscadc, u32 val)
{
unsigned long flags;
spin_lock_irqsave(&tscadc->reg_lock, flags);
tscadc->reg_se_cache |= val;
if (tscadc->adc_waiting)
wake_up(&tscadc->reg_se_wait);
else if (!tscadc->adc_in_use)
regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
spin_unlock_irqrestore(&tscadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);
static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tscadc)
{
DEFINE_WAIT(wait);
u32 reg;
regmap_read(tscadc->regmap, REG_ADCFSM, ®);
if (reg & SEQ_STATUS) {
tscadc->adc_waiting = true;
prepare_to_wait(&tscadc->reg_se_wait, &wait,
TASK_UNINTERRUPTIBLE);
spin_unlock_irq(&tscadc->reg_lock);
schedule();
spin_lock_irq(&tscadc->reg_lock);
finish_wait(&tscadc->reg_se_wait, &wait);
/*
* Sequencer should either be idle or
* busy applying the charge step.
*/
regmap_read(tscadc->regmap, REG_ADCFSM, ®);
WARN_ON((reg & SEQ_STATUS) && !(reg & CHARGE_STEP));
tscadc->adc_waiting = false;
}
tscadc->adc_in_use = true;
}
void am335x_tsc_se_set_once(struct ti_tscadc_dev *tscadc, u32 val)
{
spin_lock_irq(&tscadc->reg_lock);
am335x_tscadc_need_adc(tscadc);
regmap_write(tscadc->regmap, REG_SE, val);
spin_unlock_irq(&tscadc->reg_lock);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);
void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tscadc)
{
unsigned long flags;
spin_lock_irqsave(&tscadc->reg_lock, flags);
tscadc->adc_in_use = false;
regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
spin_unlock_irqrestore(&tscadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done);
void am335x_tsc_se_clr(struct ti_tscadc_dev *tscadc, u32 val)
{
unsigned long flags;
spin_lock_irqsave(&tscadc->reg_lock, flags);
tscadc->reg_se_cache &= ~val;
regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
spin_unlock_irqrestore(&tscadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);
static void tscadc_idle_config(struct ti_tscadc_dev *tscadc)
{
unsigned int idleconfig;
idleconfig = STEPCONFIG_INM_ADCREFM | STEPCONFIG_INP_ADCREFM;
if (ti_adc_with_touchscreen(tscadc))
idleconfig |= STEPCONFIG_YNN | STEPCONFIG_YPN;
regmap_write(tscadc->regmap, REG_IDLECONFIG, idleconfig);
}
static int ti_tscadc_probe(struct platform_device *pdev)
{
struct ti_tscadc_dev *tscadc;
struct resource *res;
struct clk *clk;
struct device_node *node;
struct mfd_cell *cell;
struct property *prop;
const __be32 *cur;
bool use_tsc = false, use_mag = false;
u32 val;
int err;
int tscmag_wires = 0, adc_channels = 0, cell_idx = 0, total_channels;
int readouts = 0, mag_tracks = 0;
/* Allocate memory for device */
tscadc = devm_kzalloc(&pdev->dev, sizeof(*tscadc), GFP_KERNEL);
if (!tscadc)
return -ENOMEM;
tscadc->dev = &pdev->dev;
if (!pdev->dev.of_node) {
dev_err(&pdev->dev, "Could not find valid DT data.\n");
return -EINVAL;
}
tscadc->data = of_device_get_match_data(&pdev->dev);
if (ti_adc_with_touchscreen(tscadc)) {
node = of_get_child_by_name(pdev->dev.of_node, "tsc");
of_property_read_u32(node, "ti,wires", &tscmag_wires);
err = of_property_read_u32(node, "ti,coordinate-readouts",
&readouts);
if (err < 0)
of_property_read_u32(node, "ti,coordiante-readouts",
&readouts);
of_node_put(node);
if (tscmag_wires)
use_tsc = true;
} else {
/*
* When adding support for the magnetic stripe reader, here is
* the place to look for the number of tracks used from device
* tree. Let's default to 0 for now.
*/
mag_tracks = 0;
tscmag_wires = mag_tracks * 2;
if (tscmag_wires)
use_mag = true;
}
node = of_get_child_by_name(pdev->dev.of_node, "adc");
of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
adc_channels++;
if (val > 7) {
dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
val);
of_node_put(node);
return -EINVAL;
}
}
of_node_put(node);
total_channels = tscmag_wires + adc_channels;
if (total_channels > 8) {
dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
return -EINVAL;
}
if (total_channels == 0) {
dev_err(&pdev->dev, "Need at least one channel.\n");
return -EINVAL;
}
if (use_tsc && (readouts * 2 + 2 + adc_channels > 16)) {
dev_err(&pdev->dev, "Too many step configurations requested\n");
return -EINVAL;
}
err = platform_get_irq(pdev, 0);
if (err < 0)
return err;
else
tscadc->irq = err;
tscadc->tscadc_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(tscadc->tscadc_base))
return PTR_ERR(tscadc->tscadc_base);
tscadc->tscadc_phys_base = res->start;
tscadc->regmap = devm_regmap_init_mmio(&pdev->dev,
tscadc->tscadc_base,
&tscadc_regmap_config);
if (IS_ERR(tscadc->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
return PTR_ERR(tscadc->regmap);
}
spin_lock_init(&tscadc->reg_lock);
init_waitqueue_head(&tscadc->reg_se_wait);
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
/*
* The TSC_ADC_Subsystem has 2 clock domains: OCP_CLK and ADC_CLK.
* ADCs produce a 12-bit sample every 15 ADC_CLK cycles.
* am33xx ADCs expect to capture 200ksps.
* am47xx ADCs expect to capture 867ksps.
* We need ADC clocks respectively running at 3MHz and 13MHz.
* These frequencies are valid since TSC_ADC_SS controller design
* assumes the OCP clock is at least 6x faster than the ADC clock.
*/
clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(clk)) {
dev_err(&pdev->dev, "failed to get fck\n");
err = PTR_ERR(clk);
goto err_disable_clk;
}
tscadc->clk_div = (clk_get_rate(clk) / tscadc->data->target_clk_rate) - 1;
regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);
/*
* Set the control register bits. tscadc->ctrl stores the configuration
* of the CTRL register but not the subsystem enable bit which must be
* added manually when timely.
*/
tscadc->ctrl = CNTRLREG_STEPID;
if (ti_adc_with_touchscreen(tscadc)) {
tscadc->ctrl |= CNTRLREG_TSC_STEPCONFIGWRT;
if (use_tsc) {
tscadc->ctrl |= CNTRLREG_TSC_ENB;
if (tscmag_wires == 5)
tscadc->ctrl |= CNTRLREG_TSC_5WIRE;
else
tscadc->ctrl |= CNTRLREG_TSC_4WIRE;
}
} else {
tscadc->ctrl |= CNTRLREG_MAG_PREAMP_PWRDOWN |
CNTRLREG_MAG_PREAMP_BYPASS;
}
regmap_write(tscadc->regmap, REG_CTRL, tscadc->ctrl);
tscadc_idle_config(tscadc);
/* Enable the TSC module enable bit */
regmap_write(tscadc->regmap, REG_CTRL, tscadc->ctrl | CNTRLREG_SSENB);
/* TSC or MAG Cell */
if (use_tsc || use_mag) {
cell = &tscadc->cells[cell_idx++];
cell->name = tscadc->data->secondary_feature_name;
cell->of_compatible = tscadc->data->secondary_feature_compatible;
cell->platform_data = &tscadc;
cell->pdata_size = sizeof(tscadc);
}
/* ADC Cell */
if (adc_channels > 0) {
cell = &tscadc->cells[cell_idx++];
cell->name = tscadc->data->adc_feature_name;
cell->of_compatible = tscadc->data->adc_feature_compatible;
cell->platform_data = &tscadc;
cell->pdata_size = sizeof(tscadc);
}
err = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO,
tscadc->cells, cell_idx, NULL, 0, NULL);
if (err < 0)
goto err_disable_clk;
platform_set_drvdata(pdev, tscadc);
return 0;
err_disable_clk:
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
return err;
}
static int ti_tscadc_remove(struct platform_device *pdev)
{
struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev);
regmap_write(tscadc->regmap, REG_SE, 0x00);
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
mfd_remove_devices(tscadc->dev);
return 0;
}
static int __maybe_unused ti_tscadc_can_wakeup(struct device *dev, void *data)
{
return device_may_wakeup(dev);
}
static int __maybe_unused tscadc_suspend(struct device *dev)
{
struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev);
regmap_write(tscadc->regmap, REG_SE, 0x00);
if (device_for_each_child(dev, NULL, ti_tscadc_can_wakeup)) {
u32 ctrl;
regmap_read(tscadc->regmap, REG_CTRL, &ctrl);
ctrl &= ~(CNTRLREG_POWERDOWN);
ctrl |= CNTRLREG_SSENB;
regmap_write(tscadc->regmap, REG_CTRL, ctrl);
}
pm_runtime_put_sync(dev);
return 0;
}
static int __maybe_unused tscadc_resume(struct device *dev)
{
struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev);
pm_runtime_get_sync(dev);
regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);
regmap_write(tscadc->regmap, REG_CTRL, tscadc->ctrl);
tscadc_idle_config(tscadc);
regmap_write(tscadc->regmap, REG_CTRL, tscadc->ctrl | CNTRLREG_SSENB);
return 0;
}
static SIMPLE_DEV_PM_OPS(tscadc_pm_ops, tscadc_suspend, tscadc_resume);
static const struct ti_tscadc_data tscdata = {
.adc_feature_name = "TI-am335x-adc",
.adc_feature_compatible = "ti,am3359-adc",
.secondary_feature_name = "TI-am335x-tsc",
.secondary_feature_compatible = "ti,am3359-tsc",
.target_clk_rate = TSC_ADC_CLK,
};
static const struct ti_tscadc_data magdata = {
.adc_feature_name = "TI-am43xx-adc",
.adc_feature_compatible = "ti,am4372-adc",
.secondary_feature_name = "TI-am43xx-mag",
.secondary_feature_compatible = "ti,am4372-mag",
.target_clk_rate = MAG_ADC_CLK,
};
static const struct of_device_id ti_tscadc_dt_ids[] = {
{ .compatible = "ti,am3359-tscadc", .data = &tscdata },
{ .compatible = "ti,am4372-magadc", .data = &magdata },
{ }
};
MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);
static struct platform_driver ti_tscadc_driver = {
.driver = {
.name = "ti_am3359-tscadc",
.pm = &tscadc_pm_ops,
.of_match_table = ti_tscadc_dt_ids,
},
.probe = ti_tscadc_probe,
.remove = ti_tscadc_remove,
};
module_platform_driver(ti_tscadc_driver);
MODULE_DESCRIPTION("TI touchscreen/magnetic stripe reader/ADC MFD controller driver");
MODULE_AUTHOR("Rachna Patil <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/ti_am335x_tscadc.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2019 MediaTek Inc.
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/suspend.h>
#include <linux/mfd/mt6323/core.h>
#include <linux/mfd/mt6323/registers.h>
#include <linux/mfd/mt6331/core.h>
#include <linux/mfd/mt6331/registers.h>
#include <linux/mfd/mt6397/core.h>
#include <linux/mfd/mt6397/registers.h>
static void mt6397_irq_lock(struct irq_data *data)
{
struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
mutex_lock(&mt6397->irqlock);
}
static void mt6397_irq_sync_unlock(struct irq_data *data)
{
struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
regmap_write(mt6397->regmap, mt6397->int_con[0],
mt6397->irq_masks_cur[0]);
regmap_write(mt6397->regmap, mt6397->int_con[1],
mt6397->irq_masks_cur[1]);
mutex_unlock(&mt6397->irqlock);
}
static void mt6397_irq_disable(struct irq_data *data)
{
struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
int shift = data->hwirq & 0xf;
int reg = data->hwirq >> 4;
mt6397->irq_masks_cur[reg] &= ~BIT(shift);
}
static void mt6397_irq_enable(struct irq_data *data)
{
struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
int shift = data->hwirq & 0xf;
int reg = data->hwirq >> 4;
mt6397->irq_masks_cur[reg] |= BIT(shift);
}
static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
{
struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
int shift = irq_data->hwirq & 0xf;
int reg = irq_data->hwirq >> 4;
if (on)
mt6397->wake_mask[reg] |= BIT(shift);
else
mt6397->wake_mask[reg] &= ~BIT(shift);
return 0;
}
static struct irq_chip mt6397_irq_chip = {
.name = "mt6397-irq",
.irq_bus_lock = mt6397_irq_lock,
.irq_bus_sync_unlock = mt6397_irq_sync_unlock,
.irq_enable = mt6397_irq_enable,
.irq_disable = mt6397_irq_disable,
.irq_set_wake = pm_sleep_ptr(mt6397_irq_set_wake),
};
static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
int irqbase)
{
unsigned int status = 0;
int i, irq, ret;
ret = regmap_read(mt6397->regmap, reg, &status);
if (ret) {
dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
return;
}
for (i = 0; i < 16; i++) {
if (status & BIT(i)) {
irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
if (irq)
handle_nested_irq(irq);
}
}
regmap_write(mt6397->regmap, reg, status);
}
static irqreturn_t mt6397_irq_thread(int irq, void *data)
{
struct mt6397_chip *mt6397 = data;
mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
return IRQ_HANDLED;
}
static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
struct mt6397_chip *mt6397 = d->host_data;
irq_set_chip_data(irq, mt6397);
irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
irq_set_nested_thread(irq, 1);
irq_set_noprobe(irq);
return 0;
}
static const struct irq_domain_ops mt6397_irq_domain_ops = {
.map = mt6397_irq_domain_map,
};
static int mt6397_irq_pm_notifier(struct notifier_block *notifier,
unsigned long pm_event, void *unused)
{
struct mt6397_chip *chip =
container_of(notifier, struct mt6397_chip, pm_nb);
switch (pm_event) {
case PM_SUSPEND_PREPARE:
regmap_write(chip->regmap,
chip->int_con[0], chip->wake_mask[0]);
regmap_write(chip->regmap,
chip->int_con[1], chip->wake_mask[1]);
enable_irq_wake(chip->irq);
break;
case PM_POST_SUSPEND:
regmap_write(chip->regmap,
chip->int_con[0], chip->irq_masks_cur[0]);
regmap_write(chip->regmap,
chip->int_con[1], chip->irq_masks_cur[1]);
disable_irq_wake(chip->irq);
break;
default:
break;
}
return NOTIFY_DONE;
}
int mt6397_irq_init(struct mt6397_chip *chip)
{
int ret;
mutex_init(&chip->irqlock);
switch (chip->chip_id) {
case MT6323_CHIP_ID:
chip->int_con[0] = MT6323_INT_CON0;
chip->int_con[1] = MT6323_INT_CON1;
chip->int_status[0] = MT6323_INT_STATUS0;
chip->int_status[1] = MT6323_INT_STATUS1;
break;
case MT6331_CHIP_ID:
chip->int_con[0] = MT6331_INT_CON0;
chip->int_con[1] = MT6331_INT_CON1;
chip->int_status[0] = MT6331_INT_STATUS_CON0;
chip->int_status[1] = MT6331_INT_STATUS_CON1;
break;
case MT6391_CHIP_ID:
case MT6397_CHIP_ID:
chip->int_con[0] = MT6397_INT_CON0;
chip->int_con[1] = MT6397_INT_CON1;
chip->int_status[0] = MT6397_INT_STATUS0;
chip->int_status[1] = MT6397_INT_STATUS1;
break;
default:
dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
return -ENODEV;
}
/* Mask all interrupt sources */
regmap_write(chip->regmap, chip->int_con[0], 0x0);
regmap_write(chip->regmap, chip->int_con[1], 0x0);
chip->pm_nb.notifier_call = mt6397_irq_pm_notifier;
chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
MT6397_IRQ_NR,
&mt6397_irq_domain_ops,
chip);
if (!chip->irq_domain) {
dev_err(chip->dev, "could not create irq domain\n");
return -ENOMEM;
}
ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
mt6397_irq_thread, IRQF_ONESHOT,
"mt6397-pmic", chip);
if (ret) {
dev_err(chip->dev, "failed to register irq=%d; err: %d\n",
chip->irq, ret);
return ret;
}
register_pm_notifier(&chip->pm_nb);
return 0;
}
| linux-master | drivers/mfd/mt6397-irq.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Intel Sunrisepoint LPSS core support.
*
* Copyright (C) 2015, Intel Corporation
*
* Authors: Andy Shevchenko <[email protected]>
* Mika Westerberg <[email protected]>
* Heikki Krogerus <[email protected]>
* Jarkko Nikula <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/debugfs.h>
#include <linux/idr.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mfd/core.h>
#include <linux/pm_qos.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/seq_file.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/dma/idma64.h>
#include "intel-lpss.h"
#define LPSS_DEV_OFFSET 0x000
#define LPSS_DEV_SIZE 0x200
#define LPSS_PRIV_OFFSET 0x200
#define LPSS_PRIV_SIZE 0x100
#define LPSS_PRIV_REG_COUNT (LPSS_PRIV_SIZE / 4)
#define LPSS_IDMA64_OFFSET 0x800
#define LPSS_IDMA64_SIZE 0x800
/* Offsets from lpss->priv */
#define LPSS_PRIV_RESETS 0x04
#define LPSS_PRIV_RESETS_IDMA BIT(2)
#define LPSS_PRIV_RESETS_FUNC 0x3
#define LPSS_PRIV_ACTIVELTR 0x10
#define LPSS_PRIV_IDLELTR 0x14
#define LPSS_PRIV_LTR_REQ BIT(15)
#define LPSS_PRIV_LTR_SCALE_MASK GENMASK(11, 10)
#define LPSS_PRIV_LTR_SCALE_1US (2 << 10)
#define LPSS_PRIV_LTR_SCALE_32US (3 << 10)
#define LPSS_PRIV_LTR_VALUE_MASK GENMASK(9, 0)
#define LPSS_PRIV_SSP_REG 0x20
#define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
#define LPSS_PRIV_REMAP_ADDR 0x40
#define LPSS_PRIV_CAPS 0xfc
#define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
#define LPSS_PRIV_CAPS_TYPE_MASK GENMASK(7, 4)
#define LPSS_PRIV_CAPS_TYPE_SHIFT 4
/* This matches the type field in CAPS register */
enum intel_lpss_dev_type {
LPSS_DEV_I2C = 0,
LPSS_DEV_UART,
LPSS_DEV_SPI,
};
struct intel_lpss {
const struct intel_lpss_platform_info *info;
enum intel_lpss_dev_type type;
struct clk *clk;
struct clk_lookup *clock;
struct mfd_cell *cell;
struct device *dev;
void __iomem *priv;
u32 priv_ctx[LPSS_PRIV_REG_COUNT];
int devid;
u32 caps;
u32 active_ltr;
u32 idle_ltr;
struct dentry *debugfs;
};
static const struct resource intel_lpss_dev_resources[] = {
DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
DEFINE_RES_IRQ(0),
};
static const struct resource intel_lpss_idma64_resources[] = {
DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
DEFINE_RES_IRQ(0),
};
/*
* Cells needs to be ordered so that the iDMA is created first. This is
* because we need to be sure the DMA is available when the host controller
* driver is probed.
*/
static const struct mfd_cell intel_lpss_idma64_cell = {
.name = LPSS_IDMA64_DRIVER_NAME,
.num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
.resources = intel_lpss_idma64_resources,
};
static const struct mfd_cell intel_lpss_i2c_cell = {
.name = "i2c_designware",
.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
.resources = intel_lpss_dev_resources,
};
static const struct mfd_cell intel_lpss_uart_cell = {
.name = "dw-apb-uart",
.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
.resources = intel_lpss_dev_resources,
};
static const struct mfd_cell intel_lpss_spi_cell = {
.name = "pxa2xx-spi",
.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
.resources = intel_lpss_dev_resources,
};
static DEFINE_IDA(intel_lpss_devid_ida);
static struct dentry *intel_lpss_debugfs;
static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
{
lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
}
static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
{
struct dentry *dir;
dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
if (IS_ERR(dir))
return PTR_ERR(dir);
/* Cache the values into lpss structure */
intel_lpss_cache_ltr(lpss);
debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
lpss->debugfs = dir;
return 0;
}
static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
{
debugfs_remove_recursive(lpss->debugfs);
}
static void intel_lpss_ltr_set(struct device *dev, s32 val)
{
struct intel_lpss *lpss = dev_get_drvdata(dev);
u32 ltr;
/*
* Program latency tolerance (LTR) accordingly what has been asked
* by the PM QoS layer or disable it in case we were passed
* negative value or PM_QOS_LATENCY_ANY.
*/
ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
if (val == PM_QOS_LATENCY_ANY || val < 0) {
ltr &= ~LPSS_PRIV_LTR_REQ;
} else {
ltr |= LPSS_PRIV_LTR_REQ;
ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
if (val > LPSS_PRIV_LTR_VALUE_MASK)
ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
else
ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
}
if (ltr == lpss->active_ltr)
return;
writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
/* Cache the values into lpss structure */
intel_lpss_cache_ltr(lpss);
}
static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
{
lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
dev_pm_qos_expose_latency_tolerance(lpss->dev);
}
static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
{
dev_pm_qos_hide_latency_tolerance(lpss->dev);
lpss->dev->power.set_latency_tolerance = NULL;
}
static int intel_lpss_assign_devs(struct intel_lpss *lpss)
{
const struct mfd_cell *cell;
unsigned int type;
type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
switch (type) {
case LPSS_DEV_I2C:
cell = &intel_lpss_i2c_cell;
break;
case LPSS_DEV_UART:
cell = &intel_lpss_uart_cell;
break;
case LPSS_DEV_SPI:
cell = &intel_lpss_spi_cell;
break;
default:
return -ENODEV;
}
lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
if (!lpss->cell)
return -ENOMEM;
lpss->type = type;
return 0;
}
static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
{
return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
}
static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
{
resource_size_t addr = lpss->info->mem->start;
lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
}
static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
{
u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;
/* Bring out the device from reset */
writel(value, lpss->priv + LPSS_PRIV_RESETS);
}
static void intel_lpss_init_dev(const struct intel_lpss *lpss)
{
u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
/* Set the device in reset state */
writel(0, lpss->priv + LPSS_PRIV_RESETS);
intel_lpss_deassert_reset(lpss);
intel_lpss_set_remap_addr(lpss);
if (!intel_lpss_has_idma(lpss))
return;
/* Make sure that SPI multiblock DMA transfers are re-enabled */
if (lpss->type == LPSS_DEV_SPI)
writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
}
static void intel_lpss_unregister_clock_tree(struct clk *clk)
{
struct clk *parent;
while (clk) {
parent = clk_get_parent(clk);
clk_unregister(clk);
clk = parent;
}
}
static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
const char *devname,
struct clk **clk)
{
char name[32];
struct clk *tmp = *clk;
snprintf(name, sizeof(name), "%s-enable", devname);
tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
lpss->priv, 0, 0, NULL);
if (IS_ERR(tmp))
return PTR_ERR(tmp);
snprintf(name, sizeof(name), "%s-div", devname);
tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
CLK_FRAC_DIVIDER_POWER_OF_TWO_PS,
lpss->priv, 1, 15, 16, 15, 0,
NULL);
if (IS_ERR(tmp))
return PTR_ERR(tmp);
*clk = tmp;
snprintf(name, sizeof(name), "%s-update", devname);
tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
if (IS_ERR(tmp))
return PTR_ERR(tmp);
*clk = tmp;
return 0;
}
static int intel_lpss_register_clock(struct intel_lpss *lpss)
{
const struct mfd_cell *cell = lpss->cell;
struct clk *clk;
char devname[24];
int ret;
if (!lpss->info->clk_rate)
return 0;
/* Root clock */
clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0,
lpss->info->clk_rate);
if (IS_ERR(clk))
return PTR_ERR(clk);
snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
/*
* Support for clock divider only if it has some preset value.
* Otherwise we assume that the divider is not used.
*/
if (lpss->type != LPSS_DEV_I2C) {
ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
if (ret)
goto err_clk_register;
}
ret = -ENOMEM;
/* Clock for the host controller */
lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
if (!lpss->clock)
goto err_clk_register;
lpss->clk = clk;
return 0;
err_clk_register:
intel_lpss_unregister_clock_tree(clk);
return ret;
}
static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
{
if (IS_ERR_OR_NULL(lpss->clk))
return;
clkdev_drop(lpss->clock);
intel_lpss_unregister_clock_tree(lpss->clk);
}
int intel_lpss_probe(struct device *dev,
const struct intel_lpss_platform_info *info)
{
struct intel_lpss *lpss;
int ret;
if (!info || !info->mem || info->irq <= 0)
return -EINVAL;
lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
if (!lpss)
return -ENOMEM;
lpss->priv = devm_ioremap_uc(dev, info->mem->start + LPSS_PRIV_OFFSET,
LPSS_PRIV_SIZE);
if (!lpss->priv)
return -ENOMEM;
lpss->info = info;
lpss->dev = dev;
lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
dev_set_drvdata(dev, lpss);
ret = intel_lpss_assign_devs(lpss);
if (ret)
return ret;
lpss->cell->swnode = info->swnode;
lpss->cell->ignore_resource_conflicts = info->ignore_resource_conflicts;
intel_lpss_init_dev(lpss);
lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
if (lpss->devid < 0)
return lpss->devid;
ret = intel_lpss_register_clock(lpss);
if (ret)
goto err_clk_register;
intel_lpss_ltr_expose(lpss);
ret = intel_lpss_debugfs_add(lpss);
if (ret)
dev_warn(dev, "Failed to create debugfs entries\n");
if (intel_lpss_has_idma(lpss)) {
ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
1, info->mem, info->irq, NULL);
if (ret)
dev_warn(dev, "Failed to add %s, fallback to PIO\n",
LPSS_IDMA64_DRIVER_NAME);
}
ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
1, info->mem, info->irq, NULL);
if (ret)
goto err_remove_ltr;
dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND);
return 0;
err_remove_ltr:
intel_lpss_debugfs_remove(lpss);
intel_lpss_ltr_hide(lpss);
intel_lpss_unregister_clock(lpss);
err_clk_register:
ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
return ret;
}
EXPORT_SYMBOL_GPL(intel_lpss_probe);
void intel_lpss_remove(struct device *dev)
{
struct intel_lpss *lpss = dev_get_drvdata(dev);
mfd_remove_devices(dev);
intel_lpss_debugfs_remove(lpss);
intel_lpss_ltr_hide(lpss);
intel_lpss_unregister_clock(lpss);
ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
}
EXPORT_SYMBOL_GPL(intel_lpss_remove);
#ifdef CONFIG_PM
static int resume_lpss_device(struct device *dev, void *data)
{
if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND))
pm_runtime_resume(dev);
return 0;
}
int intel_lpss_prepare(struct device *dev)
{
/*
* Resume both child devices before entering system sleep. This
* ensures that they are in proper state before they get suspended.
*/
device_for_each_child_reverse(dev, NULL, resume_lpss_device);
return 0;
}
EXPORT_SYMBOL_GPL(intel_lpss_prepare);
int intel_lpss_suspend(struct device *dev)
{
struct intel_lpss *lpss = dev_get_drvdata(dev);
unsigned int i;
/* Save device context */
for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
lpss->priv_ctx[i] = readl(lpss->priv + i * 4);
/*
* If the device type is not UART, then put the controller into
* reset. UART cannot be put into reset since S3/S0ix fail when
* no_console_suspend flag is enabled.
*/
if (lpss->type != LPSS_DEV_UART)
writel(0, lpss->priv + LPSS_PRIV_RESETS);
return 0;
}
EXPORT_SYMBOL_GPL(intel_lpss_suspend);
int intel_lpss_resume(struct device *dev)
{
struct intel_lpss *lpss = dev_get_drvdata(dev);
unsigned int i;
intel_lpss_deassert_reset(lpss);
/* Restore device context */
for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
writel(lpss->priv_ctx[i], lpss->priv + i * 4);
return 0;
}
EXPORT_SYMBOL_GPL(intel_lpss_resume);
#endif
static int __init intel_lpss_init(void)
{
intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
return 0;
}
module_init(intel_lpss_init);
static void __exit intel_lpss_exit(void)
{
ida_destroy(&intel_lpss_devid_ida);
debugfs_remove(intel_lpss_debugfs);
}
module_exit(intel_lpss_exit);
MODULE_AUTHOR("Andy Shevchenko <[email protected]>");
MODULE_AUTHOR("Mika Westerberg <[email protected]>");
MODULE_AUTHOR("Heikki Krogerus <[email protected]>");
MODULE_AUTHOR("Jarkko Nikula <[email protected]>");
MODULE_DESCRIPTION("Intel LPSS core driver");
MODULE_LICENSE("GPL v2");
/*
* Ensure the DMA driver is loaded before the host controller device appears,
* so that the host controller driver can request its DMA channels as early
* as possible.
*
* If the DMA module is not there that's OK as well.
*/
MODULE_SOFTDEP("pre: platform:" LPSS_IDMA64_DRIVER_NAME);
| linux-master | drivers/mfd/intel-lpss.c |
// SPDX-License-Identifier: GPL-2.0
/*
* I2C access driver for TI TPS6594/TPS6593/LP8764 PMICs
*
* Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
*/
#include <linux/crc8.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/mfd/tps6594.h>
static bool enable_crc;
module_param(enable_crc, bool, 0444);
MODULE_PARM_DESC(enable_crc, "Enable CRC feature for I2C interface");
DECLARE_CRC8_TABLE(tps6594_i2c_crc_table);
static int tps6594_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
int ret = i2c_transfer(adap, msgs, num);
if (ret == num)
return 0;
else if (ret < 0)
return ret;
else
return -EIO;
}
static int tps6594_i2c_reg_read_with_crc(struct i2c_client *client, u8 page, u8 reg, u8 *val)
{
struct i2c_msg msgs[2];
u8 buf_rx[] = { 0, 0 };
/* I2C address = I2C base address + Page index */
const u8 addr = client->addr + page;
/*
* CRC is calculated from every bit included in the protocol
* except the ACK bits from the target. Byte stream is:
* - B0: (I2C_addr_7bits << 1) | WR_bit, with WR_bit = 0
* - B1: reg
* - B2: (I2C_addr_7bits << 1) | RD_bit, with RD_bit = 1
* - B3: val
* - B4: CRC from B0-B1-B2-B3
*/
u8 crc_data[] = { addr << 1, reg, addr << 1 | 1, 0 };
int ret;
/* Write register */
msgs[0].addr = addr;
msgs[0].flags = 0;
msgs[0].len = 1;
msgs[0].buf = ®
/* Read data and CRC */
msgs[1].addr = msgs[0].addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = 2;
msgs[1].buf = buf_rx;
ret = tps6594_i2c_transfer(client->adapter, msgs, 2);
if (ret < 0)
return ret;
crc_data[sizeof(crc_data) - 1] = *val = buf_rx[0];
if (buf_rx[1] != crc8(tps6594_i2c_crc_table, crc_data, sizeof(crc_data), CRC8_INIT_VALUE))
return -EIO;
return ret;
}
static int tps6594_i2c_reg_write_with_crc(struct i2c_client *client, u8 page, u8 reg, u8 val)
{
struct i2c_msg msg;
u8 buf[] = { reg, val, 0 };
/* I2C address = I2C base address + Page index */
const u8 addr = client->addr + page;
/*
* CRC is calculated from every bit included in the protocol
* except the ACK bits from the target. Byte stream is:
* - B0: (I2C_addr_7bits << 1) | WR_bit, with WR_bit = 0
* - B1: reg
* - B2: val
* - B3: CRC from B0-B1-B2
*/
const u8 crc_data[] = { addr << 1, reg, val };
/* Write register, data and CRC */
msg.addr = addr;
msg.flags = client->flags & I2C_M_TEN;
msg.len = sizeof(buf);
msg.buf = buf;
buf[msg.len - 1] = crc8(tps6594_i2c_crc_table, crc_data, sizeof(crc_data), CRC8_INIT_VALUE);
return tps6594_i2c_transfer(client->adapter, &msg, 1);
}
static int tps6594_i2c_read(void *context, const void *reg_buf, size_t reg_size,
void *val_buf, size_t val_size)
{
struct i2c_client *client = context;
struct tps6594 *tps = i2c_get_clientdata(client);
struct i2c_msg msgs[2];
const u8 *reg_bytes = reg_buf;
u8 *val_bytes = val_buf;
const u8 page = reg_bytes[1];
u8 reg = reg_bytes[0];
int ret = 0;
int i;
if (tps->use_crc) {
/*
* Auto-increment feature does not support CRC protocol.
* Converts the bulk read operation into a series of single read operations.
*/
for (i = 0 ; ret == 0 && i < val_size ; i++)
ret = tps6594_i2c_reg_read_with_crc(client, page, reg + i, val_bytes + i);
return ret;
}
/* Write register: I2C address = I2C base address + Page index */
msgs[0].addr = client->addr + page;
msgs[0].flags = 0;
msgs[0].len = 1;
msgs[0].buf = ®
/* Read data */
msgs[1].addr = msgs[0].addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = val_size;
msgs[1].buf = val_bytes;
return tps6594_i2c_transfer(client->adapter, msgs, 2);
}
static int tps6594_i2c_write(void *context, const void *data, size_t count)
{
struct i2c_client *client = context;
struct tps6594 *tps = i2c_get_clientdata(client);
struct i2c_msg msg;
const u8 *bytes = data;
u8 *buf;
const u8 page = bytes[1];
const u8 reg = bytes[0];
int ret = 0;
int i;
if (tps->use_crc) {
/*
* Auto-increment feature does not support CRC protocol.
* Converts the bulk write operation into a series of single write operations.
*/
for (i = 0 ; ret == 0 && i < count - 2 ; i++)
ret = tps6594_i2c_reg_write_with_crc(client, page, reg + i, bytes[i + 2]);
return ret;
}
/* Setup buffer: page byte is not sent */
buf = kzalloc(--count, GFP_KERNEL);
if (!buf)
return -ENOMEM;
buf[0] = reg;
for (i = 0 ; i < count - 1 ; i++)
buf[i + 1] = bytes[i + 2];
/* Write register and data: I2C address = I2C base address + Page index */
msg.addr = client->addr + page;
msg.flags = client->flags & I2C_M_TEN;
msg.len = count;
msg.buf = buf;
ret = tps6594_i2c_transfer(client->adapter, &msg, 1);
kfree(buf);
return ret;
}
static const struct regmap_config tps6594_i2c_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.max_register = TPS6594_REG_DWD_FAIL_CNT_REG,
.volatile_reg = tps6594_is_volatile_reg,
.read = tps6594_i2c_read,
.write = tps6594_i2c_write,
};
static const struct of_device_id tps6594_i2c_of_match_table[] = {
{ .compatible = "ti,tps6594-q1", .data = (void *)TPS6594, },
{ .compatible = "ti,tps6593-q1", .data = (void *)TPS6593, },
{ .compatible = "ti,lp8764-q1", .data = (void *)LP8764, },
{}
};
MODULE_DEVICE_TABLE(of, tps6594_i2c_of_match_table);
static int tps6594_i2c_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct tps6594 *tps;
const struct of_device_id *match;
tps = devm_kzalloc(dev, sizeof(*tps), GFP_KERNEL);
if (!tps)
return -ENOMEM;
i2c_set_clientdata(client, tps);
tps->dev = dev;
tps->reg = client->addr;
tps->irq = client->irq;
tps->regmap = devm_regmap_init(dev, NULL, client, &tps6594_i2c_regmap_config);
if (IS_ERR(tps->regmap))
return dev_err_probe(dev, PTR_ERR(tps->regmap), "Failed to init regmap\n");
match = of_match_device(tps6594_i2c_of_match_table, dev);
if (!match)
return dev_err_probe(dev, -EINVAL, "Failed to find matching chip ID\n");
tps->chip_id = (unsigned long)match->data;
crc8_populate_msb(tps6594_i2c_crc_table, TPS6594_CRC8_POLYNOMIAL);
return tps6594_device_init(tps, enable_crc);
}
static struct i2c_driver tps6594_i2c_driver = {
.driver = {
.name = "tps6594",
.of_match_table = tps6594_i2c_of_match_table,
},
.probe = tps6594_i2c_probe,
};
module_i2c_driver(tps6594_i2c_driver);
MODULE_AUTHOR("Julien Panis <[email protected]>");
MODULE_DESCRIPTION("TPS6594 I2C Interface Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/tps6594-i2c.c |
// SPDX-License-Identifier: GPL-2.0+
//
// max8997-irq.c - Interrupt controller support for MAX8997
//
// Copyright (C) 2011 Samsung Electronics Co.Ltd
// MyungJoo Ham <[email protected]>
//
// This driver is based on max8998-irq.c
#include <linux/err.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/mfd/max8997.h>
#include <linux/mfd/max8997-private.h>
static const u8 max8997_mask_reg[] = {
[PMIC_INT1] = MAX8997_REG_INT1MSK,
[PMIC_INT2] = MAX8997_REG_INT2MSK,
[PMIC_INT3] = MAX8997_REG_INT3MSK,
[PMIC_INT4] = MAX8997_REG_INT4MSK,
[FUEL_GAUGE] = MAX8997_REG_INVALID,
[MUIC_INT1] = MAX8997_MUIC_REG_INTMASK1,
[MUIC_INT2] = MAX8997_MUIC_REG_INTMASK2,
[MUIC_INT3] = MAX8997_MUIC_REG_INTMASK3,
[GPIO_LOW] = MAX8997_REG_INVALID,
[GPIO_HI] = MAX8997_REG_INVALID,
[FLASH_STATUS] = MAX8997_REG_INVALID,
};
static struct i2c_client *get_i2c(struct max8997_dev *max8997,
enum max8997_irq_source src)
{
switch (src) {
case PMIC_INT1 ... PMIC_INT4:
return max8997->i2c;
case FUEL_GAUGE:
return NULL;
case MUIC_INT1 ... MUIC_INT3:
return max8997->muic;
case GPIO_LOW ... GPIO_HI:
return max8997->i2c;
case FLASH_STATUS:
return max8997->i2c;
default:
return ERR_PTR(-EINVAL);
}
}
struct max8997_irq_data {
int mask;
enum max8997_irq_source group;
};
#define DECLARE_IRQ(idx, _group, _mask) \
[(idx)] = { .group = (_group), .mask = (_mask) }
static const struct max8997_irq_data max8997_irqs[] = {
DECLARE_IRQ(MAX8997_PMICIRQ_PWRONR, PMIC_INT1, 1 << 0),
DECLARE_IRQ(MAX8997_PMICIRQ_PWRONF, PMIC_INT1, 1 << 1),
DECLARE_IRQ(MAX8997_PMICIRQ_PWRON1SEC, PMIC_INT1, 1 << 3),
DECLARE_IRQ(MAX8997_PMICIRQ_JIGONR, PMIC_INT1, 1 << 4),
DECLARE_IRQ(MAX8997_PMICIRQ_JIGONF, PMIC_INT1, 1 << 5),
DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT2, PMIC_INT1, 1 << 6),
DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT1, PMIC_INT1, 1 << 7),
DECLARE_IRQ(MAX8997_PMICIRQ_JIGR, PMIC_INT2, 1 << 0),
DECLARE_IRQ(MAX8997_PMICIRQ_JIGF, PMIC_INT2, 1 << 1),
DECLARE_IRQ(MAX8997_PMICIRQ_MR, PMIC_INT2, 1 << 2),
DECLARE_IRQ(MAX8997_PMICIRQ_DVS1OK, PMIC_INT2, 1 << 3),
DECLARE_IRQ(MAX8997_PMICIRQ_DVS2OK, PMIC_INT2, 1 << 4),
DECLARE_IRQ(MAX8997_PMICIRQ_DVS3OK, PMIC_INT2, 1 << 5),
DECLARE_IRQ(MAX8997_PMICIRQ_DVS4OK, PMIC_INT2, 1 << 6),
DECLARE_IRQ(MAX8997_PMICIRQ_CHGINS, PMIC_INT3, 1 << 0),
DECLARE_IRQ(MAX8997_PMICIRQ_CHGRM, PMIC_INT3, 1 << 1),
DECLARE_IRQ(MAX8997_PMICIRQ_DCINOVP, PMIC_INT3, 1 << 2),
DECLARE_IRQ(MAX8997_PMICIRQ_TOPOFFR, PMIC_INT3, 1 << 3),
DECLARE_IRQ(MAX8997_PMICIRQ_CHGRSTF, PMIC_INT3, 1 << 5),
DECLARE_IRQ(MAX8997_PMICIRQ_MBCHGTMEXPD, PMIC_INT3, 1 << 7),
DECLARE_IRQ(MAX8997_PMICIRQ_RTC60S, PMIC_INT4, 1 << 0),
DECLARE_IRQ(MAX8997_PMICIRQ_RTCA1, PMIC_INT4, 1 << 1),
DECLARE_IRQ(MAX8997_PMICIRQ_RTCA2, PMIC_INT4, 1 << 2),
DECLARE_IRQ(MAX8997_PMICIRQ_SMPL_INT, PMIC_INT4, 1 << 3),
DECLARE_IRQ(MAX8997_PMICIRQ_RTC1S, PMIC_INT4, 1 << 4),
DECLARE_IRQ(MAX8997_PMICIRQ_WTSR, PMIC_INT4, 1 << 5),
DECLARE_IRQ(MAX8997_MUICIRQ_ADCError, MUIC_INT1, 1 << 2),
DECLARE_IRQ(MAX8997_MUICIRQ_ADCLow, MUIC_INT1, 1 << 1),
DECLARE_IRQ(MAX8997_MUICIRQ_ADC, MUIC_INT1, 1 << 0),
DECLARE_IRQ(MAX8997_MUICIRQ_VBVolt, MUIC_INT2, 1 << 4),
DECLARE_IRQ(MAX8997_MUICIRQ_DBChg, MUIC_INT2, 1 << 3),
DECLARE_IRQ(MAX8997_MUICIRQ_DCDTmr, MUIC_INT2, 1 << 2),
DECLARE_IRQ(MAX8997_MUICIRQ_ChgDetRun, MUIC_INT2, 1 << 1),
DECLARE_IRQ(MAX8997_MUICIRQ_ChgTyp, MUIC_INT2, 1 << 0),
DECLARE_IRQ(MAX8997_MUICIRQ_OVP, MUIC_INT3, 1 << 2),
};
static void max8997_irq_lock(struct irq_data *data)
{
struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
mutex_lock(&max8997->irqlock);
}
static void max8997_irq_sync_unlock(struct irq_data *data)
{
struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
int i;
for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) {
u8 mask_reg = max8997_mask_reg[i];
struct i2c_client *i2c = get_i2c(max8997, i);
if (mask_reg == MAX8997_REG_INVALID ||
IS_ERR_OR_NULL(i2c))
continue;
max8997->irq_masks_cache[i] = max8997->irq_masks_cur[i];
max8997_write_reg(i2c, max8997_mask_reg[i],
max8997->irq_masks_cur[i]);
}
mutex_unlock(&max8997->irqlock);
}
inline static const struct max8997_irq_data *
irq_to_max8997_irq(struct max8997_dev *max8997, struct irq_data *data)
{
return &max8997_irqs[data->hwirq];
}
static void max8997_irq_mask(struct irq_data *data)
{
struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997,
data);
max8997->irq_masks_cur[irq_data->group] |= irq_data->mask;
}
static void max8997_irq_unmask(struct irq_data *data)
{
struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997,
data);
max8997->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
}
static struct irq_chip max8997_irq_chip = {
.name = "max8997",
.irq_bus_lock = max8997_irq_lock,
.irq_bus_sync_unlock = max8997_irq_sync_unlock,
.irq_mask = max8997_irq_mask,
.irq_unmask = max8997_irq_unmask,
};
#define MAX8997_IRQSRC_PMIC (1 << 1)
#define MAX8997_IRQSRC_FUELGAUGE (1 << 2)
#define MAX8997_IRQSRC_MUIC (1 << 3)
#define MAX8997_IRQSRC_GPIO (1 << 4)
#define MAX8997_IRQSRC_FLASH (1 << 5)
static irqreturn_t max8997_irq_thread(int irq, void *data)
{
struct max8997_dev *max8997 = data;
u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {};
u8 irq_src;
int ret;
int i, cur_irq;
ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src);
if (ret < 0) {
dev_err(max8997->dev, "Failed to read interrupt source: %d\n",
ret);
return IRQ_NONE;
}
if (irq_src & MAX8997_IRQSRC_PMIC) {
/* PMIC INT1 ~ INT4 */
max8997_bulk_read(max8997->i2c, MAX8997_REG_INT1, 4,
&irq_reg[PMIC_INT1]);
}
if (irq_src & MAX8997_IRQSRC_FUELGAUGE) {
/*
* TODO: FUEL GAUGE
*
* This is to be supported by Max17042 driver. When
* an interrupt incurs here, it should be relayed to a
* Max17042 device that is connected (probably by
* platform-data). However, we do not have interrupt
* handling in Max17042 driver currently. The Max17042 IRQ
* driver should be ready to be used as a stand-alone device and
* a Max8997-dependent device. Because it is not ready in
* Max17042-side and it is not too critical in operating
* Max8997, we do not implement this in initial releases.
*/
irq_reg[FUEL_GAUGE] = 0;
}
if (irq_src & MAX8997_IRQSRC_MUIC) {
/* MUIC INT1 ~ INT3 */
max8997_bulk_read(max8997->muic, MAX8997_MUIC_REG_INT1, 3,
&irq_reg[MUIC_INT1]);
}
if (irq_src & MAX8997_IRQSRC_GPIO) {
/* GPIO Interrupt */
u8 gpio_info[MAX8997_NUM_GPIO];
irq_reg[GPIO_LOW] = 0;
irq_reg[GPIO_HI] = 0;
max8997_bulk_read(max8997->i2c, MAX8997_REG_GPIOCNTL1,
MAX8997_NUM_GPIO, gpio_info);
for (i = 0; i < MAX8997_NUM_GPIO; i++) {
bool interrupt = false;
switch (gpio_info[i] & MAX8997_GPIO_INT_MASK) {
case MAX8997_GPIO_INT_BOTH:
if (max8997->gpio_status[i] != gpio_info[i])
interrupt = true;
break;
case MAX8997_GPIO_INT_RISE:
if ((max8997->gpio_status[i] != gpio_info[i]) &&
(gpio_info[i] & MAX8997_GPIO_DATA_MASK))
interrupt = true;
break;
case MAX8997_GPIO_INT_FALL:
if ((max8997->gpio_status[i] != gpio_info[i]) &&
!(gpio_info[i] & MAX8997_GPIO_DATA_MASK))
interrupt = true;
break;
default:
break;
}
if (interrupt) {
if (i < 8)
irq_reg[GPIO_LOW] |= (1 << i);
else
irq_reg[GPIO_HI] |= (1 << (i - 8));
}
}
}
if (irq_src & MAX8997_IRQSRC_FLASH) {
/* Flash Status Interrupt */
ret = max8997_read_reg(max8997->i2c, MAX8997_REG_FLASHSTATUS,
&irq_reg[FLASH_STATUS]);
}
/* Apply masking */
for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++)
irq_reg[i] &= ~max8997->irq_masks_cur[i];
/* Report */
for (i = 0; i < MAX8997_IRQ_NR; i++) {
if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) {
cur_irq = irq_find_mapping(max8997->irq_domain, i);
if (cur_irq)
handle_nested_irq(cur_irq);
}
}
return IRQ_HANDLED;
}
int max8997_irq_resume(struct max8997_dev *max8997)
{
if (max8997->irq && max8997->irq_domain)
max8997_irq_thread(0, max8997);
return 0;
}
static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
struct max8997_dev *max8997 = d->host_data;
irq_set_chip_data(irq, max8997);
irq_set_chip_and_handler(irq, &max8997_irq_chip, handle_edge_irq);
irq_set_nested_thread(irq, 1);
irq_set_noprobe(irq);
return 0;
}
static const struct irq_domain_ops max8997_irq_domain_ops = {
.map = max8997_irq_domain_map,
};
int max8997_irq_init(struct max8997_dev *max8997)
{
struct irq_domain *domain;
int i;
int ret;
u8 val;
if (!max8997->irq) {
dev_warn(max8997->dev, "No interrupt specified.\n");
return 0;
}
mutex_init(&max8997->irqlock);
/* Mask individual interrupt sources */
for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) {
struct i2c_client *i2c;
max8997->irq_masks_cur[i] = 0xff;
max8997->irq_masks_cache[i] = 0xff;
i2c = get_i2c(max8997, i);
if (IS_ERR_OR_NULL(i2c))
continue;
if (max8997_mask_reg[i] == MAX8997_REG_INVALID)
continue;
max8997_write_reg(i2c, max8997_mask_reg[i], 0xff);
}
for (i = 0; i < MAX8997_NUM_GPIO; i++) {
max8997->gpio_status[i] = (max8997_read_reg(max8997->i2c,
MAX8997_REG_GPIOCNTL1 + i,
&val)
& MAX8997_GPIO_DATA_MASK) ?
true : false;
}
domain = irq_domain_add_linear(NULL, MAX8997_IRQ_NR,
&max8997_irq_domain_ops, max8997);
if (!domain) {
dev_err(max8997->dev, "could not create irq domain\n");
return -ENODEV;
}
max8997->irq_domain = domain;
ret = request_threaded_irq(max8997->irq, NULL, max8997_irq_thread,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"max8997-irq", max8997);
if (ret) {
dev_err(max8997->dev, "Failed to request IRQ %d: %d\n",
max8997->irq, ret);
return ret;
}
if (!max8997->ono)
return 0;
ret = request_threaded_irq(max8997->ono, NULL, max8997_irq_thread,
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
IRQF_ONESHOT, "max8997-ono", max8997);
if (ret)
dev_err(max8997->dev, "Failed to request ono-IRQ %d: %d\n",
max8997->ono, ret);
return 0;
}
void max8997_irq_exit(struct max8997_dev *max8997)
{
if (max8997->ono)
free_irq(max8997->ono, max8997);
if (max8997->irq)
free_irq(max8997->irq, max8997);
}
| linux-master | drivers/mfd/max8997-irq.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8997-tables.c -- WM8997 data tables
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Charles Keepax <[email protected]>
*/
#include <linux/module.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/registers.h>
#include "arizona.h"
static const struct reg_sequence wm8997_reva_patch[] = {
{ 0x80, 0x0003 },
{ 0x214, 0x0008 },
{ 0x458, 0x0000 },
{ 0x0081, 0xE022 },
{ 0x294, 0x0000 },
{ 0x80, 0x0000 },
{ 0x171, 0x0000 },
};
/* We use a function so we can use ARRAY_SIZE() */
int wm8997_patch(struct arizona *arizona)
{
switch (arizona->rev) {
case 0:
return regmap_register_patch(arizona->regmap,
wm8997_reva_patch,
ARRAY_SIZE(wm8997_reva_patch));
default:
return 0;
}
}
EXPORT_SYMBOL_GPL(wm8997_patch);
static const struct regmap_irq wm8997_aod_irqs[ARIZONA_NUM_IRQ] = {
[ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 },
[ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 },
[ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 },
[ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 },
};
const struct regmap_irq_chip wm8997_aod = {
.name = "wm8997 AOD",
.status_base = ARIZONA_AOD_IRQ1,
.mask_base = ARIZONA_AOD_IRQ_MASK_IRQ1,
.ack_base = ARIZONA_AOD_IRQ1,
.num_regs = 1,
.irqs = wm8997_aod_irqs,
.num_irqs = ARRAY_SIZE(wm8997_aod_irqs),
};
EXPORT_SYMBOL_GPL(wm8997_aod);
static const struct regmap_irq wm8997_irqs[ARIZONA_NUM_IRQ] = {
[ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
[ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
[ARIZONA_IRQ_SPK_OVERHEAT_WARN] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
},
[ARIZONA_IRQ_HPDET] = {
.reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
},
[ARIZONA_IRQ_MICDET] = {
.reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
},
[ARIZONA_IRQ_WSEQ_DONE] = {
.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
},
[ARIZONA_IRQ_DRC1_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
},
[ARIZONA_IRQ_UNDERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1
},
[ARIZONA_IRQ_OVERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1
},
[ARIZONA_IRQ_FLL2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
},
[ARIZONA_IRQ_FLL1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1
},
[ARIZONA_IRQ_AIF2_ERR] = {
.reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1
},
[ARIZONA_IRQ_AIF1_ERR] = {
.reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1
},
[ARIZONA_IRQ_CTRLIF_ERR] = {
.reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1
},
[ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = {
.reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1
},
[ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_SYSCLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_ISRC1_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1
},
[ARIZONA_IRQ_ISRC2_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1
},
[ARIZONA_IRQ_BOOT_DONE] = {
.reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1
},
[ARIZONA_IRQ_DCS_DAC_DONE] = {
.reg_offset = 4, .mask = ARIZONA_DCS_DAC_DONE_EINT1
},
[ARIZONA_IRQ_DCS_HP_DONE] = {
.reg_offset = 4, .mask = ARIZONA_DCS_HP_DONE_EINT1
},
[ARIZONA_IRQ_FLL2_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1
},
[ARIZONA_IRQ_FLL1_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1
},
};
const struct regmap_irq_chip wm8997_irq = {
.name = "wm8997 IRQ",
.status_base = ARIZONA_INTERRUPT_STATUS_1,
.mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK,
.ack_base = ARIZONA_INTERRUPT_STATUS_1,
.num_regs = 5,
.irqs = wm8997_irqs,
.num_irqs = ARRAY_SIZE(wm8997_irqs),
};
EXPORT_SYMBOL_GPL(wm8997_irq);
static const struct reg_default wm8997_reg_default[] = {
{ 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */
{ 0x00000016, 0x0000 }, /* R22 - Write Sequencer Ctrl 0 */
{ 0x00000017, 0x0000 }, /* R23 - Write Sequencer Ctrl 1 */
{ 0x00000018, 0x0000 }, /* R24 - Write Sequencer Ctrl 2 */
{ 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */
{ 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */
{ 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */
{ 0x00000023, 0x1000 }, /* R35 - Tone Generator 4 */
{ 0x00000024, 0x0000 }, /* R36 - Tone Generator 5 */
{ 0x00000030, 0x0000 }, /* R48 - PWM Drive 1 */
{ 0x00000031, 0x0100 }, /* R49 - PWM Drive 2 */
{ 0x00000032, 0x0100 }, /* R50 - PWM Drive 3 */
{ 0x00000040, 0x0000 }, /* R64 - Wake control */
{ 0x00000041, 0x0000 }, /* R65 - Sequence control */
{ 0x00000061, 0x01FF }, /* R97 - Sample Rate Sequence Select 1 */
{ 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */
{ 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */
{ 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */
{ 0x00000068, 0x01FF }, /* R104 - AlwaysOn Triggers Seq Select 3 */
{ 0x00000069, 0x01FF }, /* R105 - AlwaysOn Triggers Seq Select 4 */
{ 0x0000006A, 0x01FF }, /* R106 - AlwaysOn Triggers Seq Select 5 */
{ 0x0000006B, 0x01FF }, /* R107 - AlwaysOn Triggers Seq Select 6 */
{ 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */
{ 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */
{ 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */
{ 0x00000092, 0x0000 }, /* R146 - Haptics phase 1 intensity */
{ 0x00000093, 0x0000 }, /* R147 - Haptics phase 1 duration */
{ 0x00000094, 0x0000 }, /* R148 - Haptics phase 2 intensity */
{ 0x00000095, 0x0000 }, /* R149 - Haptics phase 2 duration */
{ 0x00000096, 0x0000 }, /* R150 - Haptics phase 3 intensity */
{ 0x00000097, 0x0000 }, /* R151 - Haptics phase 3 duration */
{ 0x00000100, 0x0002 }, /* R256 - Clock 32k 1 */
{ 0x00000101, 0x0304 }, /* R257 - System Clock 1 */
{ 0x00000102, 0x0011 }, /* R258 - Sample rate 1 */
{ 0x00000103, 0x0011 }, /* R259 - Sample rate 2 */
{ 0x00000104, 0x0011 }, /* R260 - Sample rate 3 */
{ 0x00000112, 0x0305 }, /* R274 - Async clock 1 */
{ 0x00000113, 0x0011 }, /* R275 - Async sample rate 1 */
{ 0x00000149, 0x0000 }, /* R329 - Output system clock */
{ 0x0000014A, 0x0000 }, /* R330 - Output async clock */
{ 0x00000152, 0x0000 }, /* R338 - Rate Estimator 1 */
{ 0x00000153, 0x0000 }, /* R339 - Rate Estimator 2 */
{ 0x00000154, 0x0000 }, /* R340 - Rate Estimator 3 */
{ 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */
{ 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */
{ 0x00000161, 0x0000 }, /* R353 - Dynamic Frequency Scaling 1 */
{ 0x00000171, 0x0000 }, /* R369 - FLL1 Control 1 */
{ 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */
{ 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */
{ 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */
{ 0x00000175, 0x0004 }, /* R373 - FLL1 Control 5 */
{ 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */
{ 0x00000177, 0x0181 }, /* R375 - FLL1 Loop Filter Test 1 */
{ 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */
{ 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */
{ 0x00000183, 0x0000 }, /* R387 - FLL1 Synchroniser 3 */
{ 0x00000184, 0x0000 }, /* R388 - FLL1 Synchroniser 4 */
{ 0x00000185, 0x0000 }, /* R389 - FLL1 Synchroniser 5 */
{ 0x00000186, 0x0000 }, /* R390 - FLL1 Synchroniser 6 */
{ 0x00000189, 0x0000 }, /* R393 - FLL1 Spread Spectrum */
{ 0x0000018A, 0x0004 }, /* R394 - FLL1 GPIO Clock */
{ 0x00000191, 0x0000 }, /* R401 - FLL2 Control 1 */
{ 0x00000192, 0x0008 }, /* R402 - FLL2 Control 2 */
{ 0x00000193, 0x0018 }, /* R403 - FLL2 Control 3 */
{ 0x00000194, 0x007D }, /* R404 - FLL2 Control 4 */
{ 0x00000195, 0x0004 }, /* R405 - FLL2 Control 5 */
{ 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */
{ 0x00000197, 0x0000 }, /* R407 - FLL2 Loop Filter Test 1 */
{ 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */
{ 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */
{ 0x000001A3, 0x0000 }, /* R419 - FLL2 Synchroniser 3 */
{ 0x000001A4, 0x0000 }, /* R420 - FLL2 Synchroniser 4 */
{ 0x000001A5, 0x0000 }, /* R421 - FLL2 Synchroniser 5 */
{ 0x000001A6, 0x0000 }, /* R422 - FLL2 Synchroniser 6 */
{ 0x000001A9, 0x0000 }, /* R425 - FLL2 Spread Spectrum */
{ 0x000001AA, 0x0004 }, /* R426 - FLL2 GPIO Clock */
{ 0x00000200, 0x0006 }, /* R512 - Mic Charge Pump 1 */
{ 0x00000210, 0x00D4 }, /* R528 - LDO1 Control 1 */
{ 0x00000212, 0x0000 }, /* R530 - LDO1 Control 2 */
{ 0x00000213, 0x0344 }, /* R531 - LDO2 Control 1 */
{ 0x00000218, 0x01A6 }, /* R536 - Mic Bias Ctrl 1 */
{ 0x00000219, 0x01A6 }, /* R537 - Mic Bias Ctrl 2 */
{ 0x0000021A, 0x01A6 }, /* R538 - Mic Bias Ctrl 3 */
{ 0x00000293, 0x0000 }, /* R659 - Accessory Detect Mode 1 */
{ 0x0000029B, 0x0020 }, /* R667 - Headphone Detect 1 */
{ 0x000002A3, 0x1102 }, /* R675 - Mic Detect 1 */
{ 0x000002A4, 0x009F }, /* R676 - Mic Detect 2 */
{ 0x000002C3, 0x0000 }, /* R707 - Mic noise mix control 1 */
{ 0x000002CB, 0x0000 }, /* R715 - Isolation control */
{ 0x000002D3, 0x0000 }, /* R723 - Jack detect analogue */
{ 0x00000300, 0x0000 }, /* R768 - Input Enables */
{ 0x00000308, 0x0000 }, /* R776 - Input Rate */
{ 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */
{ 0x00000310, 0x2080 }, /* R784 - IN1L Control */
{ 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */
{ 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */
{ 0x00000314, 0x0080 }, /* R788 - IN1R Control */
{ 0x00000315, 0x0180 }, /* R789 - ADC Digital Volume 1R */
{ 0x00000316, 0x0000 }, /* R790 - DMIC1R Control */
{ 0x00000318, 0x2080 }, /* R792 - IN2L Control */
{ 0x00000319, 0x0180 }, /* R793 - ADC Digital Volume 2L */
{ 0x0000031A, 0x0000 }, /* R794 - DMIC2L Control */
{ 0x0000031C, 0x0080 }, /* R796 - IN2R Control */
{ 0x0000031D, 0x0180 }, /* R797 - ADC Digital Volume 2R */
{ 0x0000031E, 0x0000 }, /* R798 - DMIC2R Control */
{ 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */
{ 0x00000408, 0x0000 }, /* R1032 - Output Rate 1 */
{ 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */
{ 0x00000410, 0x0080 }, /* R1040 - Output Path Config 1L */
{ 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */
{ 0x00000412, 0x0080 }, /* R1042 - DAC Volume Limit 1L */
{ 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */
{ 0x00000414, 0x0080 }, /* R1044 - Output Path Config 1R */
{ 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */
{ 0x00000416, 0x0080 }, /* R1046 - DAC Volume Limit 1R */
{ 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */
{ 0x00000420, 0x0080 }, /* R1056 - Output Path Config 3L */
{ 0x00000421, 0x0180 }, /* R1057 - DAC Digital Volume 3L */
{ 0x00000422, 0x0080 }, /* R1058 - DAC Volume Limit 3L */
{ 0x00000423, 0x0010 }, /* R1059 - Noise Gate Select 3L */
{ 0x00000428, 0x0000 }, /* R1064 - Output Path Config 4L */
{ 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */
{ 0x0000042A, 0x0080 }, /* R1066 - Out Volume 4L */
{ 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */
{ 0x00000430, 0x0000 }, /* R1072 - Output Path Config 5L */
{ 0x00000431, 0x0180 }, /* R1073 - DAC Digital Volume 5L */
{ 0x00000432, 0x0080 }, /* R1074 - DAC Volume Limit 5L */
{ 0x00000433, 0x0100 }, /* R1075 - Noise Gate Select 5L */
{ 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */
{ 0x00000436, 0x0080 }, /* R1078 - DAC Volume Limit 5R */
{ 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */
{ 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */
{ 0x00000458, 0x0000 }, /* R1112 - Noise Gate Control */
{ 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */
{ 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */
{ 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */
{ 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */
{ 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */
{ 0x00000503, 0x0000 }, /* R1283 - AIF1 Rate Ctrl */
{ 0x00000504, 0x0000 }, /* R1284 - AIF1 Format */
{ 0x00000505, 0x0040 }, /* R1285 - AIF1 Tx BCLK Rate */
{ 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */
{ 0x00000507, 0x1818 }, /* R1287 - AIF1 Frame Ctrl 1 */
{ 0x00000508, 0x1818 }, /* R1288 - AIF1 Frame Ctrl 2 */
{ 0x00000509, 0x0000 }, /* R1289 - AIF1 Frame Ctrl 3 */
{ 0x0000050A, 0x0001 }, /* R1290 - AIF1 Frame Ctrl 4 */
{ 0x0000050B, 0x0002 }, /* R1291 - AIF1 Frame Ctrl 5 */
{ 0x0000050C, 0x0003 }, /* R1292 - AIF1 Frame Ctrl 6 */
{ 0x0000050D, 0x0004 }, /* R1293 - AIF1 Frame Ctrl 7 */
{ 0x0000050E, 0x0005 }, /* R1294 - AIF1 Frame Ctrl 8 */
{ 0x0000050F, 0x0006 }, /* R1295 - AIF1 Frame Ctrl 9 */
{ 0x00000510, 0x0007 }, /* R1296 - AIF1 Frame Ctrl 10 */
{ 0x00000511, 0x0000 }, /* R1297 - AIF1 Frame Ctrl 11 */
{ 0x00000512, 0x0001 }, /* R1298 - AIF1 Frame Ctrl 12 */
{ 0x00000513, 0x0002 }, /* R1299 - AIF1 Frame Ctrl 13 */
{ 0x00000514, 0x0003 }, /* R1300 - AIF1 Frame Ctrl 14 */
{ 0x00000515, 0x0004 }, /* R1301 - AIF1 Frame Ctrl 15 */
{ 0x00000516, 0x0005 }, /* R1302 - AIF1 Frame Ctrl 16 */
{ 0x00000517, 0x0006 }, /* R1303 - AIF1 Frame Ctrl 17 */
{ 0x00000518, 0x0007 }, /* R1304 - AIF1 Frame Ctrl 18 */
{ 0x00000519, 0x0000 }, /* R1305 - AIF1 Tx Enables */
{ 0x0000051A, 0x0000 }, /* R1306 - AIF1 Rx Enables */
{ 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */
{ 0x00000541, 0x0008 }, /* R1345 - AIF2 Tx Pin Ctrl */
{ 0x00000542, 0x0000 }, /* R1346 - AIF2 Rx Pin Ctrl */
{ 0x00000543, 0x0000 }, /* R1347 - AIF2 Rate Ctrl */
{ 0x00000544, 0x0000 }, /* R1348 - AIF2 Format */
{ 0x00000545, 0x0040 }, /* R1349 - AIF2 Tx BCLK Rate */
{ 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */
{ 0x00000547, 0x1818 }, /* R1351 - AIF2 Frame Ctrl 1 */
{ 0x00000548, 0x1818 }, /* R1352 - AIF2 Frame Ctrl 2 */
{ 0x00000549, 0x0000 }, /* R1353 - AIF2 Frame Ctrl 3 */
{ 0x0000054A, 0x0001 }, /* R1354 - AIF2 Frame Ctrl 4 */
{ 0x00000551, 0x0000 }, /* R1361 - AIF2 Frame Ctrl 11 */
{ 0x00000552, 0x0001 }, /* R1362 - AIF2 Frame Ctrl 12 */
{ 0x00000559, 0x0000 }, /* R1369 - AIF2 Tx Enables */
{ 0x0000055A, 0x0000 }, /* R1370 - AIF2 Rx Enables */
{ 0x000005E3, 0x0004 }, /* R1507 - SLIMbus Framer Ref Gear */
{ 0x000005E5, 0x0000 }, /* R1509 - SLIMbus Rates 1 */
{ 0x000005E6, 0x0000 }, /* R1510 - SLIMbus Rates 2 */
{ 0x000005E7, 0x0000 }, /* R1511 - SLIMbus Rates 3 */
{ 0x000005E8, 0x0000 }, /* R1512 - SLIMbus Rates 4 */
{ 0x000005E9, 0x0000 }, /* R1513 - SLIMbus Rates 5 */
{ 0x000005EA, 0x0000 }, /* R1514 - SLIMbus Rates 6 */
{ 0x000005EB, 0x0000 }, /* R1515 - SLIMbus Rates 7 */
{ 0x000005EC, 0x0000 }, /* R1516 - SLIMbus Rates 8 */
{ 0x000005F5, 0x0000 }, /* R1525 - SLIMbus RX Channel Enable */
{ 0x000005F6, 0x0000 }, /* R1526 - SLIMbus TX Channel Enable */
{ 0x00000640, 0x0000 }, /* R1600 - PWM1MIX Input 1 Source */
{ 0x00000641, 0x0080 }, /* R1601 - PWM1MIX Input 1 Volume */
{ 0x00000642, 0x0000 }, /* R1602 - PWM1MIX Input 2 Source */
{ 0x00000643, 0x0080 }, /* R1603 - PWM1MIX Input 2 Volume */
{ 0x00000644, 0x0000 }, /* R1604 - PWM1MIX Input 3 Source */
{ 0x00000645, 0x0080 }, /* R1605 - PWM1MIX Input 3 Volume */
{ 0x00000646, 0x0000 }, /* R1606 - PWM1MIX Input 4 Source */
{ 0x00000647, 0x0080 }, /* R1607 - PWM1MIX Input 4 Volume */
{ 0x00000648, 0x0000 }, /* R1608 - PWM2MIX Input 1 Source */
{ 0x00000649, 0x0080 }, /* R1609 - PWM2MIX Input 1 Volume */
{ 0x0000064A, 0x0000 }, /* R1610 - PWM2MIX Input 2 Source */
{ 0x0000064B, 0x0080 }, /* R1611 - PWM2MIX Input 2 Volume */
{ 0x0000064C, 0x0000 }, /* R1612 - PWM2MIX Input 3 Source */
{ 0x0000064D, 0x0080 }, /* R1613 - PWM2MIX Input 3 Volume */
{ 0x0000064E, 0x0000 }, /* R1614 - PWM2MIX Input 4 Source */
{ 0x0000064F, 0x0080 }, /* R1615 - PWM2MIX Input 4 Volume */
{ 0x00000660, 0x0000 }, /* R1632 - MICMIX Input 1 Source */
{ 0x00000661, 0x0080 }, /* R1633 - MICMIX Input 1 Volume */
{ 0x00000662, 0x0000 }, /* R1634 - MICMIX Input 2 Source */
{ 0x00000663, 0x0080 }, /* R1635 - MICMIX Input 2 Volume */
{ 0x00000664, 0x0000 }, /* R1636 - MICMIX Input 3 Source */
{ 0x00000665, 0x0080 }, /* R1637 - MICMIX Input 3 Volume */
{ 0x00000666, 0x0000 }, /* R1638 - MICMIX Input 4 Source */
{ 0x00000667, 0x0080 }, /* R1639 - MICMIX Input 4 Volume */
{ 0x00000668, 0x0000 }, /* R1640 - NOISEMIX Input 1 Source */
{ 0x00000669, 0x0080 }, /* R1641 - NOISEMIX Input 1 Volume */
{ 0x0000066A, 0x0000 }, /* R1642 - NOISEMIX Input 2 Source */
{ 0x0000066B, 0x0080 }, /* R1643 - NOISEMIX Input 2 Volume */
{ 0x0000066C, 0x0000 }, /* R1644 - NOISEMIX Input 3 Source */
{ 0x0000066D, 0x0080 }, /* R1645 - NOISEMIX Input 3 Volume */
{ 0x0000066E, 0x0000 }, /* R1646 - NOISEMIX Input 4 Source */
{ 0x0000066F, 0x0080 }, /* R1647 - NOISEMIX Input 4 Volume */
{ 0x00000680, 0x0000 }, /* R1664 - OUT1LMIX Input 1 Source */
{ 0x00000681, 0x0080 }, /* R1665 - OUT1LMIX Input 1 Volume */
{ 0x00000682, 0x0000 }, /* R1666 - OUT1LMIX Input 2 Source */
{ 0x00000683, 0x0080 }, /* R1667 - OUT1LMIX Input 2 Volume */
{ 0x00000684, 0x0000 }, /* R1668 - OUT1LMIX Input 3 Source */
{ 0x00000685, 0x0080 }, /* R1669 - OUT1LMIX Input 3 Volume */
{ 0x00000686, 0x0000 }, /* R1670 - OUT1LMIX Input 4 Source */
{ 0x00000687, 0x0080 }, /* R1671 - OUT1LMIX Input 4 Volume */
{ 0x00000688, 0x0000 }, /* R1672 - OUT1RMIX Input 1 Source */
{ 0x00000689, 0x0080 }, /* R1673 - OUT1RMIX Input 1 Volume */
{ 0x0000068A, 0x0000 }, /* R1674 - OUT1RMIX Input 2 Source */
{ 0x0000068B, 0x0080 }, /* R1675 - OUT1RMIX Input 2 Volume */
{ 0x0000068C, 0x0000 }, /* R1676 - OUT1RMIX Input 3 Source */
{ 0x0000068D, 0x0080 }, /* R1677 - OUT1RMIX Input 3 Volume */
{ 0x0000068E, 0x0000 }, /* R1678 - OUT1RMIX Input 4 Source */
{ 0x0000068F, 0x0080 }, /* R1679 - OUT1RMIX Input 4 Volume */
{ 0x000006A0, 0x0000 }, /* R1696 - OUT3LMIX Input 1 Source */
{ 0x000006A1, 0x0080 }, /* R1697 - OUT3LMIX Input 1 Volume */
{ 0x000006A2, 0x0000 }, /* R1698 - OUT3LMIX Input 2 Source */
{ 0x000006A3, 0x0080 }, /* R1699 - OUT3LMIX Input 2 Volume */
{ 0x000006A4, 0x0000 }, /* R1700 - OUT3LMIX Input 3 Source */
{ 0x000006A5, 0x0080 }, /* R1701 - OUT3LMIX Input 3 Volume */
{ 0x000006A6, 0x0000 }, /* R1702 - OUT3LMIX Input 4 Source */
{ 0x000006A7, 0x0080 }, /* R1703 - OUT3LMIX Input 4 Volume */
{ 0x000006B0, 0x0000 }, /* R1712 - OUT4LMIX Input 1 Source */
{ 0x000006B1, 0x0080 }, /* R1713 - OUT4LMIX Input 1 Volume */
{ 0x000006B2, 0x0000 }, /* R1714 - OUT4LMIX Input 2 Source */
{ 0x000006B3, 0x0080 }, /* R1715 - OUT4LMIX Input 2 Volume */
{ 0x000006B4, 0x0000 }, /* R1716 - OUT4LMIX Input 3 Source */
{ 0x000006B5, 0x0080 }, /* R1717 - OUT4LMIX Input 3 Volume */
{ 0x000006B6, 0x0000 }, /* R1718 - OUT4LMIX Input 4 Source */
{ 0x000006B7, 0x0080 }, /* R1719 - OUT4LMIX Input 4 Volume */
{ 0x000006C0, 0x0000 }, /* R1728 - OUT5LMIX Input 1 Source */
{ 0x000006C1, 0x0080 }, /* R1729 - OUT5LMIX Input 1 Volume */
{ 0x000006C2, 0x0000 }, /* R1730 - OUT5LMIX Input 2 Source */
{ 0x000006C3, 0x0080 }, /* R1731 - OUT5LMIX Input 2 Volume */
{ 0x000006C4, 0x0000 }, /* R1732 - OUT5LMIX Input 3 Source */
{ 0x000006C5, 0x0080 }, /* R1733 - OUT5LMIX Input 3 Volume */
{ 0x000006C6, 0x0000 }, /* R1734 - OUT5LMIX Input 4 Source */
{ 0x000006C7, 0x0080 }, /* R1735 - OUT5LMIX Input 4 Volume */
{ 0x000006C8, 0x0000 }, /* R1736 - OUT5RMIX Input 1 Source */
{ 0x000006C9, 0x0080 }, /* R1737 - OUT5RMIX Input 1 Volume */
{ 0x000006CA, 0x0000 }, /* R1738 - OUT5RMIX Input 2 Source */
{ 0x000006CB, 0x0080 }, /* R1739 - OUT5RMIX Input 2 Volume */
{ 0x000006CC, 0x0000 }, /* R1740 - OUT5RMIX Input 3 Source */
{ 0x000006CD, 0x0080 }, /* R1741 - OUT5RMIX Input 3 Volume */
{ 0x000006CE, 0x0000 }, /* R1742 - OUT5RMIX Input 4 Source */
{ 0x000006CF, 0x0080 }, /* R1743 - OUT5RMIX Input 4 Volume */
{ 0x00000700, 0x0000 }, /* R1792 - AIF1TX1MIX Input 1 Source */
{ 0x00000701, 0x0080 }, /* R1793 - AIF1TX1MIX Input 1 Volume */
{ 0x00000702, 0x0000 }, /* R1794 - AIF1TX1MIX Input 2 Source */
{ 0x00000703, 0x0080 }, /* R1795 - AIF1TX1MIX Input 2 Volume */
{ 0x00000704, 0x0000 }, /* R1796 - AIF1TX1MIX Input 3 Source */
{ 0x00000705, 0x0080 }, /* R1797 - AIF1TX1MIX Input 3 Volume */
{ 0x00000706, 0x0000 }, /* R1798 - AIF1TX1MIX Input 4 Source */
{ 0x00000707, 0x0080 }, /* R1799 - AIF1TX1MIX Input 4 Volume */
{ 0x00000708, 0x0000 }, /* R1800 - AIF1TX2MIX Input 1 Source */
{ 0x00000709, 0x0080 }, /* R1801 - AIF1TX2MIX Input 1 Volume */
{ 0x0000070A, 0x0000 }, /* R1802 - AIF1TX2MIX Input 2 Source */
{ 0x0000070B, 0x0080 }, /* R1803 - AIF1TX2MIX Input 2 Volume */
{ 0x0000070C, 0x0000 }, /* R1804 - AIF1TX2MIX Input 3 Source */
{ 0x0000070D, 0x0080 }, /* R1805 - AIF1TX2MIX Input 3 Volume */
{ 0x0000070E, 0x0000 }, /* R1806 - AIF1TX2MIX Input 4 Source */
{ 0x0000070F, 0x0080 }, /* R1807 - AIF1TX2MIX Input 4 Volume */
{ 0x00000710, 0x0000 }, /* R1808 - AIF1TX3MIX Input 1 Source */
{ 0x00000711, 0x0080 }, /* R1809 - AIF1TX3MIX Input 1 Volume */
{ 0x00000712, 0x0000 }, /* R1810 - AIF1TX3MIX Input 2 Source */
{ 0x00000713, 0x0080 }, /* R1811 - AIF1TX3MIX Input 2 Volume */
{ 0x00000714, 0x0000 }, /* R1812 - AIF1TX3MIX Input 3 Source */
{ 0x00000715, 0x0080 }, /* R1813 - AIF1TX3MIX Input 3 Volume */
{ 0x00000716, 0x0000 }, /* R1814 - AIF1TX3MIX Input 4 Source */
{ 0x00000717, 0x0080 }, /* R1815 - AIF1TX3MIX Input 4 Volume */
{ 0x00000718, 0x0000 }, /* R1816 - AIF1TX4MIX Input 1 Source */
{ 0x00000719, 0x0080 }, /* R1817 - AIF1TX4MIX Input 1 Volume */
{ 0x0000071A, 0x0000 }, /* R1818 - AIF1TX4MIX Input 2 Source */
{ 0x0000071B, 0x0080 }, /* R1819 - AIF1TX4MIX Input 2 Volume */
{ 0x0000071C, 0x0000 }, /* R1820 - AIF1TX4MIX Input 3 Source */
{ 0x0000071D, 0x0080 }, /* R1821 - AIF1TX4MIX Input 3 Volume */
{ 0x0000071E, 0x0000 }, /* R1822 - AIF1TX4MIX Input 4 Source */
{ 0x0000071F, 0x0080 }, /* R1823 - AIF1TX4MIX Input 4 Volume */
{ 0x00000720, 0x0000 }, /* R1824 - AIF1TX5MIX Input 1 Source */
{ 0x00000721, 0x0080 }, /* R1825 - AIF1TX5MIX Input 1 Volume */
{ 0x00000722, 0x0000 }, /* R1826 - AIF1TX5MIX Input 2 Source */
{ 0x00000723, 0x0080 }, /* R1827 - AIF1TX5MIX Input 2 Volume */
{ 0x00000724, 0x0000 }, /* R1828 - AIF1TX5MIX Input 3 Source */
{ 0x00000725, 0x0080 }, /* R1829 - AIF1TX5MIX Input 3 Volume */
{ 0x00000726, 0x0000 }, /* R1830 - AIF1TX5MIX Input 4 Source */
{ 0x00000727, 0x0080 }, /* R1831 - AIF1TX5MIX Input 4 Volume */
{ 0x00000728, 0x0000 }, /* R1832 - AIF1TX6MIX Input 1 Source */
{ 0x00000729, 0x0080 }, /* R1833 - AIF1TX6MIX Input 1 Volume */
{ 0x0000072A, 0x0000 }, /* R1834 - AIF1TX6MIX Input 2 Source */
{ 0x0000072B, 0x0080 }, /* R1835 - AIF1TX6MIX Input 2 Volume */
{ 0x0000072C, 0x0000 }, /* R1836 - AIF1TX6MIX Input 3 Source */
{ 0x0000072D, 0x0080 }, /* R1837 - AIF1TX6MIX Input 3 Volume */
{ 0x0000072E, 0x0000 }, /* R1838 - AIF1TX6MIX Input 4 Source */
{ 0x0000072F, 0x0080 }, /* R1839 - AIF1TX6MIX Input 4 Volume */
{ 0x00000730, 0x0000 }, /* R1840 - AIF1TX7MIX Input 1 Source */
{ 0x00000731, 0x0080 }, /* R1841 - AIF1TX7MIX Input 1 Volume */
{ 0x00000732, 0x0000 }, /* R1842 - AIF1TX7MIX Input 2 Source */
{ 0x00000733, 0x0080 }, /* R1843 - AIF1TX7MIX Input 2 Volume */
{ 0x00000734, 0x0000 }, /* R1844 - AIF1TX7MIX Input 3 Source */
{ 0x00000735, 0x0080 }, /* R1845 - AIF1TX7MIX Input 3 Volume */
{ 0x00000736, 0x0000 }, /* R1846 - AIF1TX7MIX Input 4 Source */
{ 0x00000737, 0x0080 }, /* R1847 - AIF1TX7MIX Input 4 Volume */
{ 0x00000738, 0x0000 }, /* R1848 - AIF1TX8MIX Input 1 Source */
{ 0x00000739, 0x0080 }, /* R1849 - AIF1TX8MIX Input 1 Volume */
{ 0x0000073A, 0x0000 }, /* R1850 - AIF1TX8MIX Input 2 Source */
{ 0x0000073B, 0x0080 }, /* R1851 - AIF1TX8MIX Input 2 Volume */
{ 0x0000073C, 0x0000 }, /* R1852 - AIF1TX8MIX Input 3 Source */
{ 0x0000073D, 0x0080 }, /* R1853 - AIF1TX8MIX Input 3 Volume */
{ 0x0000073E, 0x0000 }, /* R1854 - AIF1TX8MIX Input 4 Source */
{ 0x0000073F, 0x0080 }, /* R1855 - AIF1TX8MIX Input 4 Volume */
{ 0x00000740, 0x0000 }, /* R1856 - AIF2TX1MIX Input 1 Source */
{ 0x00000741, 0x0080 }, /* R1857 - AIF2TX1MIX Input 1 Volume */
{ 0x00000742, 0x0000 }, /* R1858 - AIF2TX1MIX Input 2 Source */
{ 0x00000743, 0x0080 }, /* R1859 - AIF2TX1MIX Input 2 Volume */
{ 0x00000744, 0x0000 }, /* R1860 - AIF2TX1MIX Input 3 Source */
{ 0x00000745, 0x0080 }, /* R1861 - AIF2TX1MIX Input 3 Volume */
{ 0x00000746, 0x0000 }, /* R1862 - AIF2TX1MIX Input 4 Source */
{ 0x00000747, 0x0080 }, /* R1863 - AIF2TX1MIX Input 4 Volume */
{ 0x00000748, 0x0000 }, /* R1864 - AIF2TX2MIX Input 1 Source */
{ 0x00000749, 0x0080 }, /* R1865 - AIF2TX2MIX Input 1 Volume */
{ 0x0000074A, 0x0000 }, /* R1866 - AIF2TX2MIX Input 2 Source */
{ 0x0000074B, 0x0080 }, /* R1867 - AIF2TX2MIX Input 2 Volume */
{ 0x0000074C, 0x0000 }, /* R1868 - AIF2TX2MIX Input 3 Source */
{ 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */
{ 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */
{ 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */
{ 0x000007C0, 0x0000 }, /* R1984 - SLIMTX1MIX Input 1 Source */
{ 0x000007C1, 0x0080 }, /* R1985 - SLIMTX1MIX Input 1 Volume */
{ 0x000007C2, 0x0000 }, /* R1986 - SLIMTX1MIX Input 2 Source */
{ 0x000007C3, 0x0080 }, /* R1987 - SLIMTX1MIX Input 2 Volume */
{ 0x000007C4, 0x0000 }, /* R1988 - SLIMTX1MIX Input 3 Source */
{ 0x000007C5, 0x0080 }, /* R1989 - SLIMTX1MIX Input 3 Volume */
{ 0x000007C6, 0x0000 }, /* R1990 - SLIMTX1MIX Input 4 Source */
{ 0x000007C7, 0x0080 }, /* R1991 - SLIMTX1MIX Input 4 Volume */
{ 0x000007C8, 0x0000 }, /* R1992 - SLIMTX2MIX Input 1 Source */
{ 0x000007C9, 0x0080 }, /* R1993 - SLIMTX2MIX Input 1 Volume */
{ 0x000007CA, 0x0000 }, /* R1994 - SLIMTX2MIX Input 2 Source */
{ 0x000007CB, 0x0080 }, /* R1995 - SLIMTX2MIX Input 2 Volume */
{ 0x000007CC, 0x0000 }, /* R1996 - SLIMTX2MIX Input 3 Source */
{ 0x000007CD, 0x0080 }, /* R1997 - SLIMTX2MIX Input 3 Volume */
{ 0x000007CE, 0x0000 }, /* R1998 - SLIMTX2MIX Input 4 Source */
{ 0x000007CF, 0x0080 }, /* R1999 - SLIMTX2MIX Input 4 Volume */
{ 0x000007D0, 0x0000 }, /* R2000 - SLIMTX3MIX Input 1 Source */
{ 0x000007D1, 0x0080 }, /* R2001 - SLIMTX3MIX Input 1 Volume */
{ 0x000007D2, 0x0000 }, /* R2002 - SLIMTX3MIX Input 2 Source */
{ 0x000007D3, 0x0080 }, /* R2003 - SLIMTX3MIX Input 2 Volume */
{ 0x000007D4, 0x0000 }, /* R2004 - SLIMTX3MIX Input 3 Source */
{ 0x000007D5, 0x0080 }, /* R2005 - SLIMTX3MIX Input 3 Volume */
{ 0x000007D6, 0x0000 }, /* R2006 - SLIMTX3MIX Input 4 Source */
{ 0x000007D7, 0x0080 }, /* R2007 - SLIMTX3MIX Input 4 Volume */
{ 0x000007D8, 0x0000 }, /* R2008 - SLIMTX4MIX Input 1 Source */
{ 0x000007D9, 0x0080 }, /* R2009 - SLIMTX4MIX Input 1 Volume */
{ 0x000007DA, 0x0000 }, /* R2010 - SLIMTX4MIX Input 2 Source */
{ 0x000007DB, 0x0080 }, /* R2011 - SLIMTX4MIX Input 2 Volume */
{ 0x000007DC, 0x0000 }, /* R2012 - SLIMTX4MIX Input 3 Source */
{ 0x000007DD, 0x0080 }, /* R2013 - SLIMTX4MIX Input 3 Volume */
{ 0x000007DE, 0x0000 }, /* R2014 - SLIMTX4MIX Input 4 Source */
{ 0x000007DF, 0x0080 }, /* R2015 - SLIMTX4MIX Input 4 Volume */
{ 0x000007E0, 0x0000 }, /* R2016 - SLIMTX5MIX Input 1 Source */
{ 0x000007E1, 0x0080 }, /* R2017 - SLIMTX5MIX Input 1 Volume */
{ 0x000007E2, 0x0000 }, /* R2018 - SLIMTX5MIX Input 2 Source */
{ 0x000007E3, 0x0080 }, /* R2019 - SLIMTX5MIX Input 2 Volume */
{ 0x000007E4, 0x0000 }, /* R2020 - SLIMTX5MIX Input 3 Source */
{ 0x000007E5, 0x0080 }, /* R2021 - SLIMTX5MIX Input 3 Volume */
{ 0x000007E6, 0x0000 }, /* R2022 - SLIMTX5MIX Input 4 Source */
{ 0x000007E7, 0x0080 }, /* R2023 - SLIMTX5MIX Input 4 Volume */
{ 0x000007E8, 0x0000 }, /* R2024 - SLIMTX6MIX Input 1 Source */
{ 0x000007E9, 0x0080 }, /* R2025 - SLIMTX6MIX Input 1 Volume */
{ 0x000007EA, 0x0000 }, /* R2026 - SLIMTX6MIX Input 2 Source */
{ 0x000007EB, 0x0080 }, /* R2027 - SLIMTX6MIX Input 2 Volume */
{ 0x000007EC, 0x0000 }, /* R2028 - SLIMTX6MIX Input 3 Source */
{ 0x000007ED, 0x0080 }, /* R2029 - SLIMTX6MIX Input 3 Volume */
{ 0x000007EE, 0x0000 }, /* R2030 - SLIMTX6MIX Input 4 Source */
{ 0x000007EF, 0x0080 }, /* R2031 - SLIMTX6MIX Input 4 Volume */
{ 0x000007F0, 0x0000 }, /* R2032 - SLIMTX7MIX Input 1 Source */
{ 0x000007F1, 0x0080 }, /* R2033 - SLIMTX7MIX Input 1 Volume */
{ 0x000007F2, 0x0000 }, /* R2034 - SLIMTX7MIX Input 2 Source */
{ 0x000007F3, 0x0080 }, /* R2035 - SLIMTX7MIX Input 2 Volume */
{ 0x000007F4, 0x0000 }, /* R2036 - SLIMTX7MIX Input 3 Source */
{ 0x000007F5, 0x0080 }, /* R2037 - SLIMTX7MIX Input 3 Volume */
{ 0x000007F6, 0x0000 }, /* R2038 - SLIMTX7MIX Input 4 Source */
{ 0x000007F7, 0x0080 }, /* R2039 - SLIMTX7MIX Input 4 Volume */
{ 0x000007F8, 0x0000 }, /* R2040 - SLIMTX8MIX Input 1 Source */
{ 0x000007F9, 0x0080 }, /* R2041 - SLIMTX8MIX Input 1 Volume */
{ 0x000007FA, 0x0000 }, /* R2042 - SLIMTX8MIX Input 2 Source */
{ 0x000007FB, 0x0080 }, /* R2043 - SLIMTX8MIX Input 2 Volume */
{ 0x000007FC, 0x0000 }, /* R2044 - SLIMTX8MIX Input 3 Source */
{ 0x000007FD, 0x0080 }, /* R2045 - SLIMTX8MIX Input 3 Volume */
{ 0x000007FE, 0x0000 }, /* R2046 - SLIMTX8MIX Input 4 Source */
{ 0x000007FF, 0x0080 }, /* R2047 - SLIMTX8MIX Input 4 Volume */
{ 0x00000880, 0x0000 }, /* R2176 - EQ1MIX Input 1 Source */
{ 0x00000881, 0x0080 }, /* R2177 - EQ1MIX Input 1 Volume */
{ 0x00000882, 0x0000 }, /* R2178 - EQ1MIX Input 2 Source */
{ 0x00000883, 0x0080 }, /* R2179 - EQ1MIX Input 2 Volume */
{ 0x00000884, 0x0000 }, /* R2180 - EQ1MIX Input 3 Source */
{ 0x00000885, 0x0080 }, /* R2181 - EQ1MIX Input 3 Volume */
{ 0x00000886, 0x0000 }, /* R2182 - EQ1MIX Input 4 Source */
{ 0x00000887, 0x0080 }, /* R2183 - EQ1MIX Input 4 Volume */
{ 0x00000888, 0x0000 }, /* R2184 - EQ2MIX Input 1 Source */
{ 0x00000889, 0x0080 }, /* R2185 - EQ2MIX Input 1 Volume */
{ 0x0000088A, 0x0000 }, /* R2186 - EQ2MIX Input 2 Source */
{ 0x0000088B, 0x0080 }, /* R2187 - EQ2MIX Input 2 Volume */
{ 0x0000088C, 0x0000 }, /* R2188 - EQ2MIX Input 3 Source */
{ 0x0000088D, 0x0080 }, /* R2189 - EQ2MIX Input 3 Volume */
{ 0x0000088E, 0x0000 }, /* R2190 - EQ2MIX Input 4 Source */
{ 0x0000088F, 0x0080 }, /* R2191 - EQ2MIX Input 4 Volume */
{ 0x00000890, 0x0000 }, /* R2192 - EQ3MIX Input 1 Source */
{ 0x00000891, 0x0080 }, /* R2193 - EQ3MIX Input 1 Volume */
{ 0x00000892, 0x0000 }, /* R2194 - EQ3MIX Input 2 Source */
{ 0x00000893, 0x0080 }, /* R2195 - EQ3MIX Input 2 Volume */
{ 0x00000894, 0x0000 }, /* R2196 - EQ3MIX Input 3 Source */
{ 0x00000895, 0x0080 }, /* R2197 - EQ3MIX Input 3 Volume */
{ 0x00000896, 0x0000 }, /* R2198 - EQ3MIX Input 4 Source */
{ 0x00000897, 0x0080 }, /* R2199 - EQ3MIX Input 4 Volume */
{ 0x00000898, 0x0000 }, /* R2200 - EQ4MIX Input 1 Source */
{ 0x00000899, 0x0080 }, /* R2201 - EQ4MIX Input 1 Volume */
{ 0x0000089A, 0x0000 }, /* R2202 - EQ4MIX Input 2 Source */
{ 0x0000089B, 0x0080 }, /* R2203 - EQ4MIX Input 2 Volume */
{ 0x0000089C, 0x0000 }, /* R2204 - EQ4MIX Input 3 Source */
{ 0x0000089D, 0x0080 }, /* R2205 - EQ4MIX Input 3 Volume */
{ 0x0000089E, 0x0000 }, /* R2206 - EQ4MIX Input 4 Source */
{ 0x0000089F, 0x0080 }, /* R2207 - EQ4MIX Input 4 Volume */
{ 0x000008C0, 0x0000 }, /* R2240 - DRC1LMIX Input 1 Source */
{ 0x000008C1, 0x0080 }, /* R2241 - DRC1LMIX Input 1 Volume */
{ 0x000008C2, 0x0000 }, /* R2242 - DRC1LMIX Input 2 Source */
{ 0x000008C3, 0x0080 }, /* R2243 - DRC1LMIX Input 2 Volume */
{ 0x000008C4, 0x0000 }, /* R2244 - DRC1LMIX Input 3 Source */
{ 0x000008C5, 0x0080 }, /* R2245 - DRC1LMIX Input 3 Volume */
{ 0x000008C6, 0x0000 }, /* R2246 - DRC1LMIX Input 4 Source */
{ 0x000008C7, 0x0080 }, /* R2247 - DRC1LMIX Input 4 Volume */
{ 0x000008C8, 0x0000 }, /* R2248 - DRC1RMIX Input 1 Source */
{ 0x000008C9, 0x0080 }, /* R2249 - DRC1RMIX Input 1 Volume */
{ 0x000008CA, 0x0000 }, /* R2250 - DRC1RMIX Input 2 Source */
{ 0x000008CB, 0x0080 }, /* R2251 - DRC1RMIX Input 2 Volume */
{ 0x000008CC, 0x0000 }, /* R2252 - DRC1RMIX Input 3 Source */
{ 0x000008CD, 0x0080 }, /* R2253 - DRC1RMIX Input 3 Volume */
{ 0x000008CE, 0x0000 }, /* R2254 - DRC1RMIX Input 4 Source */
{ 0x000008CF, 0x0080 }, /* R2255 - DRC1RMIX Input 4 Volume */
{ 0x00000900, 0x0000 }, /* R2304 - HPLP1MIX Input 1 Source */
{ 0x00000901, 0x0080 }, /* R2305 - HPLP1MIX Input 1 Volume */
{ 0x00000902, 0x0000 }, /* R2306 - HPLP1MIX Input 2 Source */
{ 0x00000903, 0x0080 }, /* R2307 - HPLP1MIX Input 2 Volume */
{ 0x00000904, 0x0000 }, /* R2308 - HPLP1MIX Input 3 Source */
{ 0x00000905, 0x0080 }, /* R2309 - HPLP1MIX Input 3 Volume */
{ 0x00000906, 0x0000 }, /* R2310 - HPLP1MIX Input 4 Source */
{ 0x00000907, 0x0080 }, /* R2311 - HPLP1MIX Input 4 Volume */
{ 0x00000908, 0x0000 }, /* R2312 - HPLP2MIX Input 1 Source */
{ 0x00000909, 0x0080 }, /* R2313 - HPLP2MIX Input 1 Volume */
{ 0x0000090A, 0x0000 }, /* R2314 - HPLP2MIX Input 2 Source */
{ 0x0000090B, 0x0080 }, /* R2315 - HPLP2MIX Input 2 Volume */
{ 0x0000090C, 0x0000 }, /* R2316 - HPLP2MIX Input 3 Source */
{ 0x0000090D, 0x0080 }, /* R2317 - HPLP2MIX Input 3 Volume */
{ 0x0000090E, 0x0000 }, /* R2318 - HPLP2MIX Input 4 Source */
{ 0x0000090F, 0x0080 }, /* R2319 - HPLP2MIX Input 4 Volume */
{ 0x00000910, 0x0000 }, /* R2320 - HPLP3MIX Input 1 Source */
{ 0x00000911, 0x0080 }, /* R2321 - HPLP3MIX Input 1 Volume */
{ 0x00000912, 0x0000 }, /* R2322 - HPLP3MIX Input 2 Source */
{ 0x00000913, 0x0080 }, /* R2323 - HPLP3MIX Input 2 Volume */
{ 0x00000914, 0x0000 }, /* R2324 - HPLP3MIX Input 3 Source */
{ 0x00000915, 0x0080 }, /* R2325 - HPLP3MIX Input 3 Volume */
{ 0x00000916, 0x0000 }, /* R2326 - HPLP3MIX Input 4 Source */
{ 0x00000917, 0x0080 }, /* R2327 - HPLP3MIX Input 4 Volume */
{ 0x00000918, 0x0000 }, /* R2328 - HPLP4MIX Input 1 Source */
{ 0x00000919, 0x0080 }, /* R2329 - HPLP4MIX Input 1 Volume */
{ 0x0000091A, 0x0000 }, /* R2330 - HPLP4MIX Input 2 Source */
{ 0x0000091B, 0x0080 }, /* R2331 - HPLP4MIX Input 2 Volume */
{ 0x0000091C, 0x0000 }, /* R2332 - HPLP4MIX Input 3 Source */
{ 0x0000091D, 0x0080 }, /* R2333 - HPLP4MIX Input 3 Volume */
{ 0x0000091E, 0x0000 }, /* R2334 - HPLP4MIX Input 4 Source */
{ 0x0000091F, 0x0080 }, /* R2335 - HPLP4MIX Input 4 Volume */
{ 0x00000B00, 0x0000 }, /* R2816 - ISRC1DEC1MIX Input 1 Source */
{ 0x00000B08, 0x0000 }, /* R2824 - ISRC1DEC2MIX Input 1 Source */
{ 0x00000B20, 0x0000 }, /* R2848 - ISRC1INT1MIX Input 1 Source */
{ 0x00000B28, 0x0000 }, /* R2856 - ISRC1INT2MIX Input 1 Source */
{ 0x00000B40, 0x0000 }, /* R2880 - ISRC2DEC1MIX Input 1 Source */
{ 0x00000B48, 0x0000 }, /* R2888 - ISRC2DEC2MIX Input 1 Source */
{ 0x00000B60, 0x0000 }, /* R2912 - ISRC2INT1MIX Input 1 Source */
{ 0x00000B68, 0x0000 }, /* R2920 - ISRC2INT2MIX Input 1 Source */
{ 0x00000C00, 0xA101 }, /* R3072 - GPIO1 CTRL */
{ 0x00000C01, 0xA101 }, /* R3073 - GPIO2 CTRL */
{ 0x00000C02, 0xA101 }, /* R3074 - GPIO3 CTRL */
{ 0x00000C03, 0xA101 }, /* R3075 - GPIO4 CTRL */
{ 0x00000C04, 0xA101 }, /* R3076 - GPIO5 CTRL */
{ 0x00000C0F, 0x0400 }, /* R3087 - IRQ CTRL 1 */
{ 0x00000C10, 0x1000 }, /* R3088 - GPIO Debounce Config */
{ 0x00000C20, 0x8002 }, /* R3104 - Misc Pad Ctrl 1 */
{ 0x00000C21, 0x0001 }, /* R3105 - Misc Pad Ctrl 2 */
{ 0x00000C22, 0x0000 }, /* R3106 - Misc Pad Ctrl 3 */
{ 0x00000C23, 0x0000 }, /* R3107 - Misc Pad Ctrl 4 */
{ 0x00000C24, 0x0000 }, /* R3108 - Misc Pad Ctrl 5 */
{ 0x00000D08, 0xFFFF }, /* R3336 - Interrupt Status 1 Mask */
{ 0x00000D09, 0xFFFF }, /* R3337 - Interrupt Status 2 Mask */
{ 0x00000D0A, 0xFFFF }, /* R3338 - Interrupt Status 3 Mask */
{ 0x00000D0B, 0xFFFF }, /* R3339 - Interrupt Status 4 Mask */
{ 0x00000D0C, 0xFEFF }, /* R3340 - Interrupt Status 5 Mask */
{ 0x00000D0F, 0x0000 }, /* R3343 - Interrupt Control */
{ 0x00000D18, 0xFFFF }, /* R3352 - IRQ2 Status 1 Mask */
{ 0x00000D1A, 0xFFFF }, /* R3354 - IRQ2 Status 3 Mask */
{ 0x00000D1B, 0xFFFF }, /* R3355 - IRQ2 Status 4 Mask */
{ 0x00000D1C, 0xFFFF }, /* R3356 - IRQ2 Status 5 Mask */
{ 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */
{ 0x00000D53, 0xFFFF }, /* R3411 - AOD IRQ Mask IRQ1 */
{ 0x00000D54, 0xFFFF }, /* R3412 - AOD IRQ Mask IRQ2 */
{ 0x00000D56, 0x0000 }, /* R3414 - Jack detect debounce */
{ 0x00000E00, 0x0000 }, /* R3584 - FX_Ctrl1 */
{ 0x00000E10, 0x6318 }, /* R3600 - EQ1_1 */
{ 0x00000E11, 0x6300 }, /* R3601 - EQ1_2 */
{ 0x00000E12, 0x0FC8 }, /* R3602 - EQ1_3 */
{ 0x00000E13, 0x03FE }, /* R3603 - EQ1_4 */
{ 0x00000E14, 0x00E0 }, /* R3604 - EQ1_5 */
{ 0x00000E15, 0x1EC4 }, /* R3605 - EQ1_6 */
{ 0x00000E16, 0xF136 }, /* R3606 - EQ1_7 */
{ 0x00000E17, 0x0409 }, /* R3607 - EQ1_8 */
{ 0x00000E18, 0x04CC }, /* R3608 - EQ1_9 */
{ 0x00000E19, 0x1C9B }, /* R3609 - EQ1_10 */
{ 0x00000E1A, 0xF337 }, /* R3610 - EQ1_11 */
{ 0x00000E1B, 0x040B }, /* R3611 - EQ1_12 */
{ 0x00000E1C, 0x0CBB }, /* R3612 - EQ1_13 */
{ 0x00000E1D, 0x16F8 }, /* R3613 - EQ1_14 */
{ 0x00000E1E, 0xF7D9 }, /* R3614 - EQ1_15 */
{ 0x00000E1F, 0x040A }, /* R3615 - EQ1_16 */
{ 0x00000E20, 0x1F14 }, /* R3616 - EQ1_17 */
{ 0x00000E21, 0x058C }, /* R3617 - EQ1_18 */
{ 0x00000E22, 0x0563 }, /* R3618 - EQ1_19 */
{ 0x00000E23, 0x4000 }, /* R3619 - EQ1_20 */
{ 0x00000E24, 0x0B75 }, /* R3620 - EQ1_21 */
{ 0x00000E26, 0x6318 }, /* R3622 - EQ2_1 */
{ 0x00000E27, 0x6300 }, /* R3623 - EQ2_2 */
{ 0x00000E28, 0x0FC8 }, /* R3624 - EQ2_3 */
{ 0x00000E29, 0x03FE }, /* R3625 - EQ2_4 */
{ 0x00000E2A, 0x00E0 }, /* R3626 - EQ2_5 */
{ 0x00000E2B, 0x1EC4 }, /* R3627 - EQ2_6 */
{ 0x00000E2C, 0xF136 }, /* R3628 - EQ2_7 */
{ 0x00000E2D, 0x0409 }, /* R3629 - EQ2_8 */
{ 0x00000E2E, 0x04CC }, /* R3630 - EQ2_9 */
{ 0x00000E2F, 0x1C9B }, /* R3631 - EQ2_10 */
{ 0x00000E30, 0xF337 }, /* R3632 - EQ2_11 */
{ 0x00000E31, 0x040B }, /* R3633 - EQ2_12 */
{ 0x00000E32, 0x0CBB }, /* R3634 - EQ2_13 */
{ 0x00000E33, 0x16F8 }, /* R3635 - EQ2_14 */
{ 0x00000E34, 0xF7D9 }, /* R3636 - EQ2_15 */
{ 0x00000E35, 0x040A }, /* R3637 - EQ2_16 */
{ 0x00000E36, 0x1F14 }, /* R3638 - EQ2_17 */
{ 0x00000E37, 0x058C }, /* R3639 - EQ2_18 */
{ 0x00000E38, 0x0563 }, /* R3640 - EQ2_19 */
{ 0x00000E39, 0x4000 }, /* R3641 - EQ2_20 */
{ 0x00000E3A, 0x0B75 }, /* R3642 - EQ2_21 */
{ 0x00000E3C, 0x6318 }, /* R3644 - EQ3_1 */
{ 0x00000E3D, 0x6300 }, /* R3645 - EQ3_2 */
{ 0x00000E3E, 0x0FC8 }, /* R3646 - EQ3_3 */
{ 0x00000E3F, 0x03FE }, /* R3647 - EQ3_4 */
{ 0x00000E40, 0x00E0 }, /* R3648 - EQ3_5 */
{ 0x00000E41, 0x1EC4 }, /* R3649 - EQ3_6 */
{ 0x00000E42, 0xF136 }, /* R3650 - EQ3_7 */
{ 0x00000E43, 0x0409 }, /* R3651 - EQ3_8 */
{ 0x00000E44, 0x04CC }, /* R3652 - EQ3_9 */
{ 0x00000E45, 0x1C9B }, /* R3653 - EQ3_10 */
{ 0x00000E46, 0xF337 }, /* R3654 - EQ3_11 */
{ 0x00000E47, 0x040B }, /* R3655 - EQ3_12 */
{ 0x00000E48, 0x0CBB }, /* R3656 - EQ3_13 */
{ 0x00000E49, 0x16F8 }, /* R3657 - EQ3_14 */
{ 0x00000E4A, 0xF7D9 }, /* R3658 - EQ3_15 */
{ 0x00000E4B, 0x040A }, /* R3659 - EQ3_16 */
{ 0x00000E4C, 0x1F14 }, /* R3660 - EQ3_17 */
{ 0x00000E4D, 0x058C }, /* R3661 - EQ3_18 */
{ 0x00000E4E, 0x0563 }, /* R3662 - EQ3_19 */
{ 0x00000E4F, 0x4000 }, /* R3663 - EQ3_20 */
{ 0x00000E50, 0x0B75 }, /* R3664 - EQ3_21 */
{ 0x00000E52, 0x6318 }, /* R3666 - EQ4_1 */
{ 0x00000E53, 0x6300 }, /* R3667 - EQ4_2 */
{ 0x00000E54, 0x0FC8 }, /* R3668 - EQ4_3 */
{ 0x00000E55, 0x03FE }, /* R3669 - EQ4_4 */
{ 0x00000E56, 0x00E0 }, /* R3670 - EQ4_5 */
{ 0x00000E57, 0x1EC4 }, /* R3671 - EQ4_6 */
{ 0x00000E58, 0xF136 }, /* R3672 - EQ4_7 */
{ 0x00000E59, 0x0409 }, /* R3673 - EQ4_8 */
{ 0x00000E5A, 0x04CC }, /* R3674 - EQ4_9 */
{ 0x00000E5B, 0x1C9B }, /* R3675 - EQ4_10 */
{ 0x00000E5C, 0xF337 }, /* R3676 - EQ4_11 */
{ 0x00000E5D, 0x040B }, /* R3677 - EQ4_12 */
{ 0x00000E5E, 0x0CBB }, /* R3678 - EQ4_13 */
{ 0x00000E5F, 0x16F8 }, /* R3679 - EQ4_14 */
{ 0x00000E60, 0xF7D9 }, /* R3680 - EQ4_15 */
{ 0x00000E61, 0x040A }, /* R3681 - EQ4_16 */
{ 0x00000E62, 0x1F14 }, /* R3682 - EQ4_17 */
{ 0x00000E63, 0x058C }, /* R3683 - EQ4_18 */
{ 0x00000E64, 0x0563 }, /* R3684 - EQ4_19 */
{ 0x00000E65, 0x4000 }, /* R3685 - EQ4_20 */
{ 0x00000E66, 0x0B75 }, /* R3686 - EQ4_21 */
{ 0x00000E80, 0x0018 }, /* R3712 - DRC1 ctrl1 */
{ 0x00000E81, 0x0933 }, /* R3713 - DRC1 ctrl2 */
{ 0x00000E82, 0x0018 }, /* R3714 - DRC1 ctrl3 */
{ 0x00000E83, 0x0000 }, /* R3715 - DRC1 ctrl4 */
{ 0x00000E84, 0x0000 }, /* R3716 - DRC1 ctrl5 */
{ 0x00000EC0, 0x0000 }, /* R3776 - HPLPF1_1 */
{ 0x00000EC1, 0x0000 }, /* R3777 - HPLPF1_2 */
{ 0x00000EC4, 0x0000 }, /* R3780 - HPLPF2_1 */
{ 0x00000EC5, 0x0000 }, /* R3781 - HPLPF2_2 */
{ 0x00000EC8, 0x0000 }, /* R3784 - HPLPF3_1 */
{ 0x00000EC9, 0x0000 }, /* R3785 - HPLPF3_2 */
{ 0x00000ECC, 0x0000 }, /* R3788 - HPLPF4_1 */
{ 0x00000ECD, 0x0000 }, /* R3789 - HPLPF4_2 */
{ 0x00000EF0, 0x0000 }, /* R3824 - ISRC 1 CTRL 1 */
{ 0x00000EF1, 0x0000 }, /* R3825 - ISRC 1 CTRL 2 */
{ 0x00000EF2, 0x0000 }, /* R3826 - ISRC 1 CTRL 3 */
{ 0x00000EF3, 0x0000 }, /* R3827 - ISRC 2 CTRL 1 */
{ 0x00000EF4, 0x0000 }, /* R3828 - ISRC 2 CTRL 2 */
{ 0x00000EF5, 0x0000 }, /* R3829 - ISRC 2 CTRL 3 */
};
static bool wm8997_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case ARIZONA_SOFTWARE_RESET:
case ARIZONA_DEVICE_REVISION:
case ARIZONA_CTRL_IF_I2C1_CFG_1:
case ARIZONA_WRITE_SEQUENCER_CTRL_0:
case ARIZONA_WRITE_SEQUENCER_CTRL_1:
case ARIZONA_WRITE_SEQUENCER_CTRL_2:
case ARIZONA_TONE_GENERATOR_1:
case ARIZONA_TONE_GENERATOR_2:
case ARIZONA_TONE_GENERATOR_3:
case ARIZONA_TONE_GENERATOR_4:
case ARIZONA_TONE_GENERATOR_5:
case ARIZONA_PWM_DRIVE_1:
case ARIZONA_PWM_DRIVE_2:
case ARIZONA_PWM_DRIVE_3:
case ARIZONA_WAKE_CONTROL:
case ARIZONA_SEQUENCE_CONTROL:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6:
case ARIZONA_COMFORT_NOISE_GENERATOR:
case ARIZONA_HAPTICS_CONTROL_1:
case ARIZONA_HAPTICS_CONTROL_2:
case ARIZONA_HAPTICS_PHASE_1_INTENSITY:
case ARIZONA_HAPTICS_PHASE_1_DURATION:
case ARIZONA_HAPTICS_PHASE_2_INTENSITY:
case ARIZONA_HAPTICS_PHASE_2_DURATION:
case ARIZONA_HAPTICS_PHASE_3_INTENSITY:
case ARIZONA_HAPTICS_PHASE_3_DURATION:
case ARIZONA_HAPTICS_STATUS:
case ARIZONA_CLOCK_32K_1:
case ARIZONA_SYSTEM_CLOCK_1:
case ARIZONA_SAMPLE_RATE_1:
case ARIZONA_SAMPLE_RATE_2:
case ARIZONA_SAMPLE_RATE_3:
case ARIZONA_SAMPLE_RATE_1_STATUS:
case ARIZONA_SAMPLE_RATE_2_STATUS:
case ARIZONA_SAMPLE_RATE_3_STATUS:
case ARIZONA_ASYNC_CLOCK_1:
case ARIZONA_ASYNC_SAMPLE_RATE_1:
case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
case ARIZONA_OUTPUT_SYSTEM_CLOCK:
case ARIZONA_OUTPUT_ASYNC_CLOCK:
case ARIZONA_RATE_ESTIMATOR_1:
case ARIZONA_RATE_ESTIMATOR_2:
case ARIZONA_RATE_ESTIMATOR_3:
case ARIZONA_RATE_ESTIMATOR_4:
case ARIZONA_RATE_ESTIMATOR_5:
case ARIZONA_DYNAMIC_FREQUENCY_SCALING_1:
case ARIZONA_FLL1_CONTROL_1:
case ARIZONA_FLL1_CONTROL_2:
case ARIZONA_FLL1_CONTROL_3:
case ARIZONA_FLL1_CONTROL_4:
case ARIZONA_FLL1_CONTROL_5:
case ARIZONA_FLL1_CONTROL_6:
case ARIZONA_FLL1_LOOP_FILTER_TEST_1:
case ARIZONA_FLL1_NCO_TEST_0:
case ARIZONA_FLL1_SYNCHRONISER_1:
case ARIZONA_FLL1_SYNCHRONISER_2:
case ARIZONA_FLL1_SYNCHRONISER_3:
case ARIZONA_FLL1_SYNCHRONISER_4:
case ARIZONA_FLL1_SYNCHRONISER_5:
case ARIZONA_FLL1_SYNCHRONISER_6:
case ARIZONA_FLL1_SPREAD_SPECTRUM:
case ARIZONA_FLL1_GPIO_CLOCK:
case ARIZONA_FLL2_CONTROL_1:
case ARIZONA_FLL2_CONTROL_2:
case ARIZONA_FLL2_CONTROL_3:
case ARIZONA_FLL2_CONTROL_4:
case ARIZONA_FLL2_CONTROL_5:
case ARIZONA_FLL2_CONTROL_6:
case ARIZONA_FLL2_LOOP_FILTER_TEST_1:
case ARIZONA_FLL2_NCO_TEST_0:
case ARIZONA_FLL2_SYNCHRONISER_1:
case ARIZONA_FLL2_SYNCHRONISER_2:
case ARIZONA_FLL2_SYNCHRONISER_3:
case ARIZONA_FLL2_SYNCHRONISER_4:
case ARIZONA_FLL2_SYNCHRONISER_5:
case ARIZONA_FLL2_SYNCHRONISER_6:
case ARIZONA_FLL2_SPREAD_SPECTRUM:
case ARIZONA_FLL2_GPIO_CLOCK:
case ARIZONA_MIC_CHARGE_PUMP_1:
case ARIZONA_LDO1_CONTROL_1:
case ARIZONA_LDO1_CONTROL_2:
case ARIZONA_LDO2_CONTROL_1:
case ARIZONA_MIC_BIAS_CTRL_1:
case ARIZONA_MIC_BIAS_CTRL_2:
case ARIZONA_MIC_BIAS_CTRL_3:
case ARIZONA_HP_CTRL_1L:
case ARIZONA_HP_CTRL_1R:
case ARIZONA_ACCESSORY_DETECT_MODE_1:
case ARIZONA_HEADPHONE_DETECT_1:
case ARIZONA_HEADPHONE_DETECT_2:
case ARIZONA_MIC_DETECT_1:
case ARIZONA_MIC_DETECT_2:
case ARIZONA_MIC_DETECT_3:
case ARIZONA_MIC_NOISE_MIX_CONTROL_1:
case ARIZONA_ISOLATION_CONTROL:
case ARIZONA_JACK_DETECT_ANALOGUE:
case ARIZONA_INPUT_ENABLES:
case ARIZONA_INPUT_ENABLES_STATUS:
case ARIZONA_INPUT_RATE:
case ARIZONA_INPUT_VOLUME_RAMP:
case ARIZONA_IN1L_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_1L:
case ARIZONA_DMIC1L_CONTROL:
case ARIZONA_IN1R_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_1R:
case ARIZONA_DMIC1R_CONTROL:
case ARIZONA_IN2L_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_2L:
case ARIZONA_DMIC2L_CONTROL:
case ARIZONA_IN2R_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_2R:
case ARIZONA_DMIC2R_CONTROL:
case ARIZONA_OUTPUT_ENABLES_1:
case ARIZONA_OUTPUT_STATUS_1:
case ARIZONA_RAW_OUTPUT_STATUS_1:
case ARIZONA_OUTPUT_RATE_1:
case ARIZONA_OUTPUT_VOLUME_RAMP:
case ARIZONA_OUTPUT_PATH_CONFIG_1L:
case ARIZONA_DAC_DIGITAL_VOLUME_1L:
case ARIZONA_DAC_VOLUME_LIMIT_1L:
case ARIZONA_NOISE_GATE_SELECT_1L:
case ARIZONA_OUTPUT_PATH_CONFIG_1R:
case ARIZONA_DAC_DIGITAL_VOLUME_1R:
case ARIZONA_DAC_VOLUME_LIMIT_1R:
case ARIZONA_NOISE_GATE_SELECT_1R:
case ARIZONA_OUTPUT_PATH_CONFIG_3L:
case ARIZONA_DAC_DIGITAL_VOLUME_3L:
case ARIZONA_DAC_VOLUME_LIMIT_3L:
case ARIZONA_NOISE_GATE_SELECT_3L:
case ARIZONA_OUTPUT_PATH_CONFIG_4L:
case ARIZONA_DAC_DIGITAL_VOLUME_4L:
case ARIZONA_OUT_VOLUME_4L:
case ARIZONA_NOISE_GATE_SELECT_4L:
case ARIZONA_OUTPUT_PATH_CONFIG_5L:
case ARIZONA_DAC_DIGITAL_VOLUME_5L:
case ARIZONA_DAC_VOLUME_LIMIT_5L:
case ARIZONA_NOISE_GATE_SELECT_5L:
case ARIZONA_DAC_DIGITAL_VOLUME_5R:
case ARIZONA_DAC_VOLUME_LIMIT_5R:
case ARIZONA_NOISE_GATE_SELECT_5R:
case ARIZONA_DAC_AEC_CONTROL_1:
case ARIZONA_NOISE_GATE_CONTROL:
case ARIZONA_PDM_SPK1_CTRL_1:
case ARIZONA_PDM_SPK1_CTRL_2:
case ARIZONA_AIF1_BCLK_CTRL:
case ARIZONA_AIF1_TX_PIN_CTRL:
case ARIZONA_AIF1_RX_PIN_CTRL:
case ARIZONA_AIF1_RATE_CTRL:
case ARIZONA_AIF1_FORMAT:
case ARIZONA_AIF1_TX_BCLK_RATE:
case ARIZONA_AIF1_RX_BCLK_RATE:
case ARIZONA_AIF1_FRAME_CTRL_1:
case ARIZONA_AIF1_FRAME_CTRL_2:
case ARIZONA_AIF1_FRAME_CTRL_3:
case ARIZONA_AIF1_FRAME_CTRL_4:
case ARIZONA_AIF1_FRAME_CTRL_5:
case ARIZONA_AIF1_FRAME_CTRL_6:
case ARIZONA_AIF1_FRAME_CTRL_7:
case ARIZONA_AIF1_FRAME_CTRL_8:
case ARIZONA_AIF1_FRAME_CTRL_9:
case ARIZONA_AIF1_FRAME_CTRL_10:
case ARIZONA_AIF1_FRAME_CTRL_11:
case ARIZONA_AIF1_FRAME_CTRL_12:
case ARIZONA_AIF1_FRAME_CTRL_13:
case ARIZONA_AIF1_FRAME_CTRL_14:
case ARIZONA_AIF1_FRAME_CTRL_15:
case ARIZONA_AIF1_FRAME_CTRL_16:
case ARIZONA_AIF1_FRAME_CTRL_17:
case ARIZONA_AIF1_FRAME_CTRL_18:
case ARIZONA_AIF1_TX_ENABLES:
case ARIZONA_AIF1_RX_ENABLES:
case ARIZONA_AIF2_BCLK_CTRL:
case ARIZONA_AIF2_TX_PIN_CTRL:
case ARIZONA_AIF2_RX_PIN_CTRL:
case ARIZONA_AIF2_RATE_CTRL:
case ARIZONA_AIF2_FORMAT:
case ARIZONA_AIF2_TX_BCLK_RATE:
case ARIZONA_AIF2_RX_BCLK_RATE:
case ARIZONA_AIF2_FRAME_CTRL_1:
case ARIZONA_AIF2_FRAME_CTRL_2:
case ARIZONA_AIF2_FRAME_CTRL_3:
case ARIZONA_AIF2_FRAME_CTRL_4:
case ARIZONA_AIF2_FRAME_CTRL_11:
case ARIZONA_AIF2_FRAME_CTRL_12:
case ARIZONA_AIF2_TX_ENABLES:
case ARIZONA_AIF2_RX_ENABLES:
case ARIZONA_SLIMBUS_FRAMER_REF_GEAR:
case ARIZONA_SLIMBUS_RATES_1:
case ARIZONA_SLIMBUS_RATES_2:
case ARIZONA_SLIMBUS_RATES_3:
case ARIZONA_SLIMBUS_RATES_4:
case ARIZONA_SLIMBUS_RATES_5:
case ARIZONA_SLIMBUS_RATES_6:
case ARIZONA_SLIMBUS_RATES_7:
case ARIZONA_SLIMBUS_RATES_8:
case ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE:
case ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE:
case ARIZONA_SLIMBUS_RX_PORT_STATUS:
case ARIZONA_SLIMBUS_TX_PORT_STATUS:
case ARIZONA_PWM1MIX_INPUT_1_SOURCE:
case ARIZONA_PWM1MIX_INPUT_1_VOLUME:
case ARIZONA_PWM1MIX_INPUT_2_SOURCE:
case ARIZONA_PWM1MIX_INPUT_2_VOLUME:
case ARIZONA_PWM1MIX_INPUT_3_SOURCE:
case ARIZONA_PWM1MIX_INPUT_3_VOLUME:
case ARIZONA_PWM1MIX_INPUT_4_SOURCE:
case ARIZONA_PWM1MIX_INPUT_4_VOLUME:
case ARIZONA_PWM2MIX_INPUT_1_SOURCE:
case ARIZONA_PWM2MIX_INPUT_1_VOLUME:
case ARIZONA_PWM2MIX_INPUT_2_SOURCE:
case ARIZONA_PWM2MIX_INPUT_2_VOLUME:
case ARIZONA_PWM2MIX_INPUT_3_SOURCE:
case ARIZONA_PWM2MIX_INPUT_3_VOLUME:
case ARIZONA_PWM2MIX_INPUT_4_SOURCE:
case ARIZONA_PWM2MIX_INPUT_4_VOLUME:
case ARIZONA_MICMIX_INPUT_1_SOURCE:
case ARIZONA_MICMIX_INPUT_1_VOLUME:
case ARIZONA_MICMIX_INPUT_2_SOURCE:
case ARIZONA_MICMIX_INPUT_2_VOLUME:
case ARIZONA_MICMIX_INPUT_3_SOURCE:
case ARIZONA_MICMIX_INPUT_3_VOLUME:
case ARIZONA_MICMIX_INPUT_4_SOURCE:
case ARIZONA_MICMIX_INPUT_4_VOLUME:
case ARIZONA_NOISEMIX_INPUT_1_SOURCE:
case ARIZONA_NOISEMIX_INPUT_1_VOLUME:
case ARIZONA_NOISEMIX_INPUT_2_SOURCE:
case ARIZONA_NOISEMIX_INPUT_2_VOLUME:
case ARIZONA_NOISEMIX_INPUT_3_SOURCE:
case ARIZONA_NOISEMIX_INPUT_3_VOLUME:
case ARIZONA_NOISEMIX_INPUT_4_SOURCE:
case ARIZONA_NOISEMIX_INPUT_4_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_4_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME:
case ARIZONA_EQ1MIX_INPUT_1_SOURCE:
case ARIZONA_EQ1MIX_INPUT_1_VOLUME:
case ARIZONA_EQ1MIX_INPUT_2_SOURCE:
case ARIZONA_EQ1MIX_INPUT_2_VOLUME:
case ARIZONA_EQ1MIX_INPUT_3_SOURCE:
case ARIZONA_EQ1MIX_INPUT_3_VOLUME:
case ARIZONA_EQ1MIX_INPUT_4_SOURCE:
case ARIZONA_EQ1MIX_INPUT_4_VOLUME:
case ARIZONA_EQ2MIX_INPUT_1_SOURCE:
case ARIZONA_EQ2MIX_INPUT_1_VOLUME:
case ARIZONA_EQ2MIX_INPUT_2_SOURCE:
case ARIZONA_EQ2MIX_INPUT_2_VOLUME:
case ARIZONA_EQ2MIX_INPUT_3_SOURCE:
case ARIZONA_EQ2MIX_INPUT_3_VOLUME:
case ARIZONA_EQ2MIX_INPUT_4_SOURCE:
case ARIZONA_EQ2MIX_INPUT_4_VOLUME:
case ARIZONA_EQ3MIX_INPUT_1_SOURCE:
case ARIZONA_EQ3MIX_INPUT_1_VOLUME:
case ARIZONA_EQ3MIX_INPUT_2_SOURCE:
case ARIZONA_EQ3MIX_INPUT_2_VOLUME:
case ARIZONA_EQ3MIX_INPUT_3_SOURCE:
case ARIZONA_EQ3MIX_INPUT_3_VOLUME:
case ARIZONA_EQ3MIX_INPUT_4_SOURCE:
case ARIZONA_EQ3MIX_INPUT_4_VOLUME:
case ARIZONA_EQ4MIX_INPUT_1_SOURCE:
case ARIZONA_EQ4MIX_INPUT_1_VOLUME:
case ARIZONA_EQ4MIX_INPUT_2_SOURCE:
case ARIZONA_EQ4MIX_INPUT_2_VOLUME:
case ARIZONA_EQ4MIX_INPUT_3_SOURCE:
case ARIZONA_EQ4MIX_INPUT_3_VOLUME:
case ARIZONA_EQ4MIX_INPUT_4_SOURCE:
case ARIZONA_EQ4MIX_INPUT_4_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_1_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_1_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_2_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_2_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_3_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_3_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_4_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_4_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_1_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_1_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_2_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_2_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_3_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_3_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_4_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_4_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_4_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_4_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_4_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_4_VOLUME:
case ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE:
case ARIZONA_GPIO1_CTRL:
case ARIZONA_GPIO2_CTRL:
case ARIZONA_GPIO3_CTRL:
case ARIZONA_GPIO4_CTRL:
case ARIZONA_GPIO5_CTRL:
case ARIZONA_IRQ_CTRL_1:
case ARIZONA_GPIO_DEBOUNCE_CONFIG:
case ARIZONA_MISC_PAD_CTRL_1:
case ARIZONA_MISC_PAD_CTRL_2:
case ARIZONA_MISC_PAD_CTRL_3:
case ARIZONA_MISC_PAD_CTRL_4:
case ARIZONA_MISC_PAD_CTRL_5:
case ARIZONA_INTERRUPT_STATUS_1:
case ARIZONA_INTERRUPT_STATUS_2:
case ARIZONA_INTERRUPT_STATUS_3:
case ARIZONA_INTERRUPT_STATUS_4:
case ARIZONA_INTERRUPT_STATUS_5:
case ARIZONA_INTERRUPT_STATUS_1_MASK:
case ARIZONA_INTERRUPT_STATUS_2_MASK:
case ARIZONA_INTERRUPT_STATUS_3_MASK:
case ARIZONA_INTERRUPT_STATUS_4_MASK:
case ARIZONA_INTERRUPT_STATUS_5_MASK:
case ARIZONA_INTERRUPT_CONTROL:
case ARIZONA_IRQ2_STATUS_1:
case ARIZONA_IRQ2_STATUS_3:
case ARIZONA_IRQ2_STATUS_4:
case ARIZONA_IRQ2_STATUS_5:
case ARIZONA_IRQ2_STATUS_1_MASK:
case ARIZONA_IRQ2_STATUS_3_MASK:
case ARIZONA_IRQ2_STATUS_4_MASK:
case ARIZONA_IRQ2_STATUS_5_MASK:
case ARIZONA_IRQ2_CONTROL:
case ARIZONA_INTERRUPT_RAW_STATUS_3:
case ARIZONA_INTERRUPT_RAW_STATUS_4:
case ARIZONA_INTERRUPT_RAW_STATUS_5:
case ARIZONA_INTERRUPT_RAW_STATUS_6:
case ARIZONA_INTERRUPT_RAW_STATUS_7:
case ARIZONA_INTERRUPT_RAW_STATUS_8:
case ARIZONA_IRQ_PIN_STATUS:
case ARIZONA_AOD_WKUP_AND_TRIG:
case ARIZONA_AOD_IRQ1:
case ARIZONA_AOD_IRQ2:
case ARIZONA_AOD_IRQ_MASK_IRQ1:
case ARIZONA_AOD_IRQ_MASK_IRQ2:
case ARIZONA_AOD_IRQ_RAW_STATUS:
case ARIZONA_JACK_DETECT_DEBOUNCE:
case ARIZONA_FX_CTRL1:
case ARIZONA_FX_CTRL2:
case ARIZONA_EQ1_1:
case ARIZONA_EQ1_2:
case ARIZONA_EQ1_3:
case ARIZONA_EQ1_4:
case ARIZONA_EQ1_5:
case ARIZONA_EQ1_6:
case ARIZONA_EQ1_7:
case ARIZONA_EQ1_8:
case ARIZONA_EQ1_9:
case ARIZONA_EQ1_10:
case ARIZONA_EQ1_11:
case ARIZONA_EQ1_12:
case ARIZONA_EQ1_13:
case ARIZONA_EQ1_14:
case ARIZONA_EQ1_15:
case ARIZONA_EQ1_16:
case ARIZONA_EQ1_17:
case ARIZONA_EQ1_18:
case ARIZONA_EQ1_19:
case ARIZONA_EQ1_20:
case ARIZONA_EQ1_21:
case ARIZONA_EQ2_1:
case ARIZONA_EQ2_2:
case ARIZONA_EQ2_3:
case ARIZONA_EQ2_4:
case ARIZONA_EQ2_5:
case ARIZONA_EQ2_6:
case ARIZONA_EQ2_7:
case ARIZONA_EQ2_8:
case ARIZONA_EQ2_9:
case ARIZONA_EQ2_10:
case ARIZONA_EQ2_11:
case ARIZONA_EQ2_12:
case ARIZONA_EQ2_13:
case ARIZONA_EQ2_14:
case ARIZONA_EQ2_15:
case ARIZONA_EQ2_16:
case ARIZONA_EQ2_17:
case ARIZONA_EQ2_18:
case ARIZONA_EQ2_19:
case ARIZONA_EQ2_20:
case ARIZONA_EQ2_21:
case ARIZONA_EQ3_1:
case ARIZONA_EQ3_2:
case ARIZONA_EQ3_3:
case ARIZONA_EQ3_4:
case ARIZONA_EQ3_5:
case ARIZONA_EQ3_6:
case ARIZONA_EQ3_7:
case ARIZONA_EQ3_8:
case ARIZONA_EQ3_9:
case ARIZONA_EQ3_10:
case ARIZONA_EQ3_11:
case ARIZONA_EQ3_12:
case ARIZONA_EQ3_13:
case ARIZONA_EQ3_14:
case ARIZONA_EQ3_15:
case ARIZONA_EQ3_16:
case ARIZONA_EQ3_17:
case ARIZONA_EQ3_18:
case ARIZONA_EQ3_19:
case ARIZONA_EQ3_20:
case ARIZONA_EQ3_21:
case ARIZONA_EQ4_1:
case ARIZONA_EQ4_2:
case ARIZONA_EQ4_3:
case ARIZONA_EQ4_4:
case ARIZONA_EQ4_5:
case ARIZONA_EQ4_6:
case ARIZONA_EQ4_7:
case ARIZONA_EQ4_8:
case ARIZONA_EQ4_9:
case ARIZONA_EQ4_10:
case ARIZONA_EQ4_11:
case ARIZONA_EQ4_12:
case ARIZONA_EQ4_13:
case ARIZONA_EQ4_14:
case ARIZONA_EQ4_15:
case ARIZONA_EQ4_16:
case ARIZONA_EQ4_17:
case ARIZONA_EQ4_18:
case ARIZONA_EQ4_19:
case ARIZONA_EQ4_20:
case ARIZONA_EQ4_21:
case ARIZONA_DRC1_CTRL1:
case ARIZONA_DRC1_CTRL2:
case ARIZONA_DRC1_CTRL3:
case ARIZONA_DRC1_CTRL4:
case ARIZONA_DRC1_CTRL5:
case ARIZONA_HPLPF1_1:
case ARIZONA_HPLPF1_2:
case ARIZONA_HPLPF2_1:
case ARIZONA_HPLPF2_2:
case ARIZONA_HPLPF3_1:
case ARIZONA_HPLPF3_2:
case ARIZONA_HPLPF4_1:
case ARIZONA_HPLPF4_2:
case ARIZONA_ISRC_1_CTRL_1:
case ARIZONA_ISRC_1_CTRL_2:
case ARIZONA_ISRC_1_CTRL_3:
case ARIZONA_ISRC_2_CTRL_1:
case ARIZONA_ISRC_2_CTRL_2:
case ARIZONA_ISRC_2_CTRL_3:
return true;
default:
return false;
}
}
static bool wm8997_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case ARIZONA_SOFTWARE_RESET:
case ARIZONA_DEVICE_REVISION:
case ARIZONA_HAPTICS_STATUS:
case ARIZONA_SAMPLE_RATE_1_STATUS:
case ARIZONA_SAMPLE_RATE_2_STATUS:
case ARIZONA_SAMPLE_RATE_3_STATUS:
case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
case ARIZONA_FLL1_NCO_TEST_0:
case ARIZONA_FLL2_NCO_TEST_0:
case ARIZONA_MIC_DETECT_3:
case ARIZONA_HP_CTRL_1L:
case ARIZONA_HP_CTRL_1R:
case ARIZONA_HEADPHONE_DETECT_2:
case ARIZONA_INPUT_ENABLES_STATUS:
case ARIZONA_OUTPUT_STATUS_1:
case ARIZONA_RAW_OUTPUT_STATUS_1:
case ARIZONA_SLIMBUS_RX_PORT_STATUS:
case ARIZONA_SLIMBUS_TX_PORT_STATUS:
case ARIZONA_INTERRUPT_STATUS_1:
case ARIZONA_INTERRUPT_STATUS_2:
case ARIZONA_INTERRUPT_STATUS_3:
case ARIZONA_INTERRUPT_STATUS_4:
case ARIZONA_INTERRUPT_STATUS_5:
case ARIZONA_IRQ2_STATUS_1:
case ARIZONA_IRQ2_STATUS_3:
case ARIZONA_IRQ2_STATUS_4:
case ARIZONA_IRQ2_STATUS_5:
case ARIZONA_INTERRUPT_RAW_STATUS_3:
case ARIZONA_INTERRUPT_RAW_STATUS_4:
case ARIZONA_INTERRUPT_RAW_STATUS_5:
case ARIZONA_INTERRUPT_RAW_STATUS_6:
case ARIZONA_INTERRUPT_RAW_STATUS_7:
case ARIZONA_INTERRUPT_RAW_STATUS_8:
case ARIZONA_IRQ_PIN_STATUS:
case ARIZONA_AOD_WKUP_AND_TRIG:
case ARIZONA_AOD_IRQ1:
case ARIZONA_AOD_IRQ2:
case ARIZONA_AOD_IRQ_RAW_STATUS:
case ARIZONA_FX_CTRL2:
return true;
default:
return false;
}
}
#define WM8997_MAX_REGISTER 0x31ff
const struct regmap_config wm8997_i2c_regmap = {
.reg_bits = 32,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = WM8997_MAX_REGISTER,
.readable_reg = wm8997_readable_register,
.volatile_reg = wm8997_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm8997_reg_default,
.num_reg_defaults = ARRAY_SIZE(wm8997_reg_default),
};
EXPORT_SYMBOL_GPL(wm8997_i2c_regmap);
| linux-master | drivers/mfd/wm8997-tables.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Regmap tables for CS47L15 codec
*
* Copyright (C) 2016-2019 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/mfd/madera/core.h>
#include <linux/mfd/madera/registers.h>
#include "madera.h"
static const struct reg_sequence cs47l15_reva_16_patch[] = {
{ 0x8C, 0x5555 },
{ 0x8C, 0xAAAA },
{ 0x314, 0x0080 },
{ 0x4A8, 0x6023 },
{ 0x4A9, 0x6023 },
{ 0x4D4, 0x0008 },
{ 0x4CF, 0x0F00 },
{ 0x4D7, 0x1B2B },
{ 0x8C, 0xCCCC },
{ 0x8C, 0x3333 },
};
int cs47l15_patch(struct madera *madera)
{
int ret;
ret = regmap_register_patch(madera->regmap,
cs47l15_reva_16_patch,
ARRAY_SIZE(cs47l15_reva_16_patch));
if (ret < 0) {
dev_err(madera->dev,
"Error in applying 16-bit patch: %d\n", ret);
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(cs47l15_patch);
static const struct reg_default cs47l15_reg_default[] = {
{ 0x00000020, 0x0000 }, /* R32 (0x20) - Tone Generator 1 */
{ 0x00000021, 0x1000 }, /* R33 (0x21) - Tone Generator 2 */
{ 0x00000022, 0x0000 }, /* R34 (0x22) - Tone Generator 3 */
{ 0x00000023, 0x1000 }, /* R35 (0x23) - Tone Generator 4 */
{ 0x00000024, 0x0000 }, /* R36 (0x24) - Tone Generator 5 */
{ 0x00000030, 0x0000 }, /* R48 (0x30) - PWM Drive 1 */
{ 0x00000031, 0x0100 }, /* R49 (0x31) - PWM Drive 2 */
{ 0x00000032, 0x0100 }, /* R50 (0x32) - PWM Drive 3 */
{ 0x00000061, 0x01ff }, /* R97 (0x61) - Sample Rate Sequence Select 1 */
{ 0x00000062, 0x01ff }, /* R98 (0x62) - Sample Rate Sequence Select 2 */
{ 0x00000063, 0x01ff }, /* R99 (0x63) - Sample Rate Sequence Select 3 */
{ 0x00000064, 0x01ff }, /* R100 (0x64) - Sample Rate Sequence Select 4 */
{ 0x00000066, 0x01ff }, /* R102 (0x66) - Always On Triggers Sequence Select 1 */
{ 0x00000067, 0x01ff }, /* R103 (0x67) - Always On Triggers Sequence Select 2 */
{ 0x00000090, 0x0000 }, /* R144 (0x90) - Haptics Control 1 */
{ 0x00000091, 0x7fff }, /* R145 (0x91) - Haptics Control 2 */
{ 0x00000092, 0x0000 }, /* R146 (0x92) - Haptics Phase 1 Intensity */
{ 0x00000093, 0x0000 }, /* R147 (0x93) - Haptics Phase 1 Duration */
{ 0x00000094, 0x0000 }, /* R148 (0x94) - Haptics Phase 2 Intensity */
{ 0x00000095, 0x0000 }, /* R149 (0x95) - Haptics Phase 2 Duration */
{ 0x00000096, 0x0000 }, /* R150 (0x96) - Haptics Phase 3 Intensity */
{ 0x00000097, 0x0000 }, /* R151 (0x97) - Haptics Phase 3 Duration */
{ 0x000000a0, 0x0000 }, /* R160 (0xA0) - Comfort Noise Generator */
{ 0x00000100, 0x0002 }, /* R256 (0x100) - Clock 32K 1 */
{ 0x00000101, 0x0404 }, /* R257 (0x101) - System Clock 1 */
{ 0x00000102, 0x0011 }, /* R258 (0x102) - Sample Rate 1 */
{ 0x00000103, 0x0011 }, /* R259 (0x103) - Sample Rate 2 */
{ 0x00000104, 0x0011 }, /* R260 (0x104) - Sample Rate 3 */
{ 0x00000120, 0x0304 }, /* R288 (0x120) - DSP Clock 1 */
{ 0x00000122, 0x0000 }, /* R290 (0x122) - DSP Clock 2 */
{ 0x00000149, 0x0000 }, /* R329 (0x149) - Output System Clock */
{ 0x00000152, 0x0000 }, /* R338 (0x152) - Rate Estimator 1 */
{ 0x00000153, 0x0000 }, /* R339 (0x153) - Rate Estimator 2 */
{ 0x00000154, 0x0000 }, /* R340 (0x154) - Rate Estimator 3 */
{ 0x00000155, 0x0000 }, /* R341 (0x155) - Rate Estimator 4 */
{ 0x00000156, 0x0000 }, /* R342 (0x156) - Rate Estimator 5 */
{ 0x00000171, 0x0002 }, /* R369 (0x171) - FLL1 Control 1 */
{ 0x00000172, 0x0008 }, /* R370 (0x172) - FLL1 Control 2 */
{ 0x00000173, 0x0018 }, /* R371 (0x173) - FLL1 Control 3 */
{ 0x00000174, 0x007d }, /* R372 (0x174) - FLL1 Control 4 */
{ 0x00000175, 0x0000 }, /* R373 (0x175) - FLL1 Control 5 */
{ 0x00000176, 0x0000 }, /* R374 (0x176) - FLL1 Control 6 */
{ 0x00000179, 0x0000 }, /* R377 (0x179) - FLL1 Control 7 */
{ 0x0000017a, 0x2906 }, /* R378 (0x17A) - FLL1 EFS 2 */
{ 0x00000181, 0x0000 }, /* R385 (0x181) - FLL1 Synchroniser 1 */
{ 0x00000182, 0x0000 }, /* R386 (0x182) - FLL1 Synchroniser 2 */
{ 0x00000183, 0x0000 }, /* R387 (0x183) - FLL1 Synchroniser 3 */
{ 0x00000184, 0x0000 }, /* R388 (0x184) - FLL1 Synchroniser 4 */
{ 0x00000185, 0x0000 }, /* R389 (0x185) - FLL1 Synchroniser 5 */
{ 0x00000186, 0x0000 }, /* R390 (0x186) - FLL1 Synchroniser 6 */
{ 0x00000187, 0x0001 }, /* R391 (0x187) - FLL1 Synchroniser 7 */
{ 0x00000189, 0x0000 }, /* R393 (0x189) - FLL1 Spread Spectrum */
{ 0x0000018a, 0x0004 }, /* R394 (0x18A) - FLL1 GPIO Clock */
{ 0x000001d1, 0x0004 }, /* R465 (0x1D1) - FLL AO Control 1 */
{ 0x000001d2, 0x0004 }, /* R466 (0x1D2) - FLL AO Control 2 */
{ 0x000001d3, 0x0000 }, /* R467 (0x1D3) - FLL AO Control 3 */
{ 0x000001d4, 0x0000 }, /* R468 (0x1D4) - FLL AO Control 4 */
{ 0x000001d5, 0x0001 }, /* R469 (0x1D5) - FLL AO Control 5 */
{ 0x000001d6, 0x8004 }, /* R470 (0x1D6) - FLL AO Control 6 */
{ 0x000001d8, 0x0000 }, /* R472 (0x1D8) - FLL AO Control 7 */
{ 0x000001da, 0x0077 }, /* R474 (0x1DA) - FLL AO Control 8 */
{ 0x000001db, 0x0000 }, /* R475 (0x1DB) - FLL AO Control 9 */
{ 0x000001dc, 0x06da }, /* R476 (0x1DC) - FLL AO Control 10 */
{ 0x000001dd, 0x0011 }, /* R477 (0x1DD) - FLL AO Control 11 */
{ 0x00000218, 0x00e6 }, /* R536 (0x218) - Mic Bias Ctrl 1 */
{ 0x0000021c, 0x0222 }, /* R540 (0x21C) - Mic Bias Ctrl 5 */
{ 0x00000293, 0x0080 }, /* R659 (0x293) - Accessory Detect Mode 1 */
{ 0x00000299, 0x0000 }, /* R665 (0x299) - Headphone Detect 0 */
{ 0x0000029b, 0x0000 }, /* R667 (0x29B) - Headphone Detect 1 */
{ 0x000002a2, 0x0010 }, /* R674 (0x2A2) - Mic Detect 1 Control 0 */
{ 0x000002a3, 0x1102 }, /* R675 (0x2A3) - Mic Detect 1 Control 1 */
{ 0x000002a4, 0x009f }, /* R676 (0x2A4) - Mic Detect 1 Control 2 */
{ 0x000002a6, 0x3d3d }, /* R678 (0x2A6) - Mic Detect 1 Level 1 */
{ 0x000002a7, 0x3d3d }, /* R679 (0x2A7) - Mic Detect 1 Level 2 */
{ 0x000002a8, 0x333d }, /* R680 (0x2A8) - Mic Detect 1 Level 3 */
{ 0x000002a9, 0x202d }, /* R681 (0x2A9) - Mic Detect 1 Level 4 */
{ 0x000002c6, 0x0010 }, /* R710 (0x2C6) - Micd Clamp Control */
{ 0x000002c8, 0x0000 }, /* R712 (0x2C8) - GP Switch 1 */
{ 0x000002d3, 0x0000 }, /* R723 (0x2D3) - Jack Detect Analogue */
{ 0x00000300, 0x0000 }, /* R768 (0x300) - Input Enables */
{ 0x00000308, 0x0000 }, /* R776 (0x308) - Input Rate */
{ 0x00000309, 0x0022 }, /* R777 (0x309) - Input Volume Ramp */
{ 0x0000030c, 0x0002 }, /* R780 (0x30C) - HPF Control */
{ 0x00000310, 0x0080 }, /* R784 (0x310) - IN1L Control */
{ 0x00000311, 0x0180 }, /* R785 (0x311) - ADC Digital Volume 1L */
{ 0x00000312, 0x0500 }, /* R786 (0x312) - DMIC1L Control */
{ 0x00000313, 0x0000 }, /* R787 (0x313) - IN1L Rate Control */
{ 0x00000314, 0x0080 }, /* R788 (0x314) - IN1R Control */
{ 0x00000315, 0x0180 }, /* R789 (0x315) - ADC Digital Volume 1R */
{ 0x00000316, 0x0000 }, /* R790 (0x316) - DMIC1R Control */
{ 0x00000317, 0x0000 }, /* R791 (0x317) - IN1R Rate Control */
{ 0x00000318, 0x0000 }, /* R792 (0x318) - IN2L Control */
{ 0x00000319, 0x0180 }, /* R793 (0x319) - ADC Digital Volume 2L */
{ 0x0000031a, 0x0500 }, /* R794 (0x31A) - DMIC2L Control */
{ 0x0000031b, 0x0000 }, /* R795 (0x31B) - IN2L Rate Control */
{ 0x0000031c, 0x0800 }, /* R796 (0x31C) - IN2R Control */
{ 0x0000031d, 0x0180 }, /* R797 (0x31D) - ADC Digital Volume 2R */
{ 0x0000031e, 0x0000 }, /* R798 (0x31E) - DMIC2R Control */
{ 0x0000031f, 0x0000 }, /* R799 (0x31F) - IN2R Rate Control */
{ 0x000003a8, 0x2000 }, /* R936 (0x3A8) - CS47L15 ADC Int Bias */
{ 0x000003c4, 0x0000 }, /* R964 (0x3C4) - CS47L15 PGA Bias Sel */
{ 0x00000400, 0x0000 }, /* R1024 (0x400) - Output Enables 1 */
{ 0x00000408, 0x0000 }, /* R1032 (0x408) - Output Rate 1 */
{ 0x00000409, 0x0022 }, /* R1033 (0x409) - Output Volume Ramp */
{ 0x00000410, 0x0080 }, /* R1040 (0x410) - Output Path Config 1L */
{ 0x00000411, 0x0180 }, /* R1041 (0x411) - DAC Digital Volume 1L */
{ 0x00000412, 0x0000 }, /* R1042 (0x412) - Output Path Config 1 */
{ 0x00000413, 0x0001 }, /* R1043 (0x413) - Noise Gate Select 1L */
{ 0x00000414, 0x0080 }, /* R1044 (0x414) - Output Path Config 1R */
{ 0x00000415, 0x0180 }, /* R1045 (0x415) - DAC Digital Volume 1R */
{ 0x00000417, 0x0002 }, /* R1047 (0x417) - Noise Gate Select 1R */
{ 0x0000041a, 0x0600 }, /* R1050 (0x41A) - Output Path Config 2 */
{ 0x00000428, 0x0000 }, /* R1064 (0x428) - Output Path Config 4L */
{ 0x00000429, 0x0180 }, /* R1065 (0x429) - DAC Digital Volume 4L */
{ 0x0000042b, 0x0040 }, /* R1067 (0x42B) - Noise Gate Select 4L */
{ 0x00000430, 0x0000 }, /* R1072 (0x430) - Output Path Config 5L */
{ 0x00000431, 0x0180 }, /* R1073 (0x431) - DAC Digital Volume 5L */
{ 0x00000433, 0x0100 }, /* R1075 (0x433) - Noise Gate Select 5L */
{ 0x00000434, 0x0000 }, /* R1076 (0x434) - Output Path Config 5R */
{ 0x00000435, 0x0180 }, /* R1077 (0x435) - DAC Digital Volume 5R */
{ 0x00000437, 0x0200 }, /* R1079 (0x437) - Noise Gate Select 5R */
{ 0x00000450, 0x0000 }, /* R1104 (0x450) - DAC AEC Control 1 */
{ 0x00000451, 0x0000 }, /* R1105 (0x451) - DAC AEC Control 2 */
{ 0x00000458, 0x0000 }, /* R1112 (0x458) - Noise Gate Control */
{ 0x00000490, 0x0069 }, /* R1168 (0x490) - PDM SPK1 Ctrl 1 */
{ 0x00000491, 0x0000 }, /* R1169 (0x491) - PDM SPK1 Ctrl 2 */
{ 0x000004a0, 0x3080 }, /* R1184 (0x4A0) - HP1 Short Circuit Ctrl */
{ 0x000004a8, 0x6023 }, /* R1192 (0x4A8) - HP Test Ctrl 5 */
{ 0x000004a9, 0x6023 }, /* R1193 (0x4A9) - HP Test Ctrl 6 */
{ 0x00000500, 0x000c }, /* R1280 (0x500) - AIF1 BCLK Ctrl */
{ 0x00000501, 0x0000 }, /* R1281 (0x501) - AIF1 Tx Pin Ctrl */
{ 0x00000502, 0x0000 }, /* R1282 (0x502) - AIF1 Rx Pin Ctrl */
{ 0x00000503, 0x0000 }, /* R1283 (0x503) - AIF1 Rate Ctrl */
{ 0x00000504, 0x0000 }, /* R1284 (0x504) - AIF1 Format */
{ 0x00000506, 0x0040 }, /* R1286 (0x506) - AIF1 Rx BCLK Rate */
{ 0x00000507, 0x1818 }, /* R1287 (0x507) - AIF1 Frame Ctrl 1 */
{ 0x00000508, 0x1818 }, /* R1288 (0x508) - AIF1 Frame Ctrl 2 */
{ 0x00000509, 0x0000 }, /* R1289 (0x509) - AIF1 Frame Ctrl 3 */
{ 0x0000050a, 0x0001 }, /* R1290 (0x50A) - AIF1 Frame Ctrl 4 */
{ 0x0000050b, 0x0002 }, /* R1291 (0x50B) - AIF1 Frame Ctrl 5 */
{ 0x0000050c, 0x0003 }, /* R1292 (0x50C) - AIF1 Frame Ctrl 6 */
{ 0x0000050d, 0x0004 }, /* R1293 (0x50D) - AIF1 Frame Ctrl 7 */
{ 0x0000050e, 0x0005 }, /* R1294 (0x50E) - AIF1 Frame Ctrl 8 */
{ 0x00000511, 0x0000 }, /* R1297 (0x511) - AIF1 Frame Ctrl 11 */
{ 0x00000512, 0x0001 }, /* R1298 (0x512) - AIF1 Frame Ctrl 12 */
{ 0x00000513, 0x0002 }, /* R1299 (0x513) - AIF1 Frame Ctrl 13 */
{ 0x00000514, 0x0003 }, /* R1300 (0x514) - AIF1 Frame Ctrl 14 */
{ 0x00000515, 0x0004 }, /* R1301 (0x515) - AIF1 Frame Ctrl 15 */
{ 0x00000516, 0x0005 }, /* R1302 (0x516) - AIF1 Frame Ctrl 16 */
{ 0x00000519, 0x0000 }, /* R1305 (0x519) - AIF1 Tx Enables */
{ 0x0000051a, 0x0000 }, /* R1306 (0x51A) - AIF1 Rx Enables */
{ 0x00000540, 0x000c }, /* R1344 (0x540) - AIF2 BCLK Ctrl */
{ 0x00000541, 0x0000 }, /* R1345 (0x541) - AIF2 Tx Pin Ctrl */
{ 0x00000542, 0x0000 }, /* R1346 (0x542) - AIF2 Rx Pin Ctrl */
{ 0x00000543, 0x0000 }, /* R1347 (0x543) - AIF2 Rate Ctrl */
{ 0x00000544, 0x0000 }, /* R1348 (0x544) - AIF2 Format */
{ 0x00000546, 0x0040 }, /* R1350 (0x546) - AIF2 Rx BCLK Rate */
{ 0x00000547, 0x1818 }, /* R1351 (0x547) - AIF2 Frame Ctrl 1 */
{ 0x00000548, 0x1818 }, /* R1352 (0x548) - AIF2 Frame Ctrl 2 */
{ 0x00000549, 0x0000 }, /* R1353 (0x549) - AIF2 Frame Ctrl 3 */
{ 0x0000054a, 0x0001 }, /* R1354 (0x54A) - AIF2 Frame Ctrl 4 */
{ 0x0000054b, 0x0002 }, /* R1355 (0x54B) - AIF2 Frame Ctrl 5 */
{ 0x0000054c, 0x0003 }, /* R1356 (0x54C) - AIF2 Frame Ctrl 6 */
{ 0x00000551, 0x0000 }, /* R1361 (0x551) - AIF2 Frame Ctrl 11 */
{ 0x00000552, 0x0001 }, /* R1362 (0x552) - AIF2 Frame Ctrl 12 */
{ 0x00000553, 0x0002 }, /* R1363 (0x553) - AIF2 Frame Ctrl 13 */
{ 0x00000554, 0x0003 }, /* R1364 (0x554) - AIF2 Frame Ctrl 14 */
{ 0x00000559, 0x0000 }, /* R1369 (0x559) - AIF2 Tx Enables */
{ 0x0000055a, 0x0000 }, /* R1370 (0x55A) - AIF2 Rx Enables */
{ 0x00000580, 0x000c }, /* R1408 (0x580) - AIF3 BCLK Ctrl */
{ 0x00000581, 0x0000 }, /* R1409 (0x581) - AIF3 Tx Pin Ctrl */
{ 0x00000582, 0x0000 }, /* R1410 (0x582) - AIF3 Rx Pin Ctrl */
{ 0x00000583, 0x0000 }, /* R1411 (0x583) - AIF3 Rate Ctrl */
{ 0x00000584, 0x0000 }, /* R1412 (0x584) - AIF3 Format */
{ 0x00000586, 0x0040 }, /* R1414 (0x586) - AIF3 Rx BCLK Rate */
{ 0x00000587, 0x1818 }, /* R1415 (0x587) - AIF3 Frame Ctrl 1 */
{ 0x00000588, 0x1818 }, /* R1416 (0x588) - AIF3 Frame Ctrl 2 */
{ 0x00000589, 0x0000 }, /* R1417 (0x589) - AIF3 Frame Ctrl 3 */
{ 0x0000058a, 0x0001 }, /* R1418 (0x58A) - AIF3 Frame Ctrl 4 */
{ 0x00000591, 0x0000 }, /* R1425 (0x591) - AIF3 Frame Ctrl 11 */
{ 0x00000592, 0x0001 }, /* R1426 (0x592) - AIF3 Frame Ctrl 12 */
{ 0x00000599, 0x0000 }, /* R1433 (0x599) - AIF3 Tx Enables */
{ 0x0000059a, 0x0000 }, /* R1434 (0x59A) - AIF3 Rx Enables */
{ 0x000005c2, 0x0000 }, /* R1474 (0x5C2) - SPD1 Tx Control */
{ 0x00000640, 0x0000 }, /* R1600 (0x640) - PWM1MIX Input 1 Source */
{ 0x00000641, 0x0080 }, /* R1601 (0x641) - PWM1MIX Input 1 Volume */
{ 0x00000642, 0x0000 }, /* R1602 (0x642) - PWM1MIX Input 2 Source */
{ 0x00000643, 0x0080 }, /* R1603 (0x643) - PWM1MIX Input 2 Volume */
{ 0x00000644, 0x0000 }, /* R1604 (0x644) - PWM1MIX Input 3 Source */
{ 0x00000645, 0x0080 }, /* R1605 (0x645) - PWM1MIX Input 3 Volume */
{ 0x00000646, 0x0000 }, /* R1606 (0x646) - PWM1MIX Input 4 Source */
{ 0x00000647, 0x0080 }, /* R1607 (0x647) - PWM1MIX Input 4 Volume */
{ 0x00000648, 0x0000 }, /* R1608 (0x648) - PWM2MIX Input 1 Source */
{ 0x00000649, 0x0080 }, /* R1609 (0x649) - PWM2MIX Input 1 Volume */
{ 0x0000064a, 0x0000 }, /* R1610 (0x64A) - PWM2MIX Input 2 Source */
{ 0x0000064b, 0x0080 }, /* R1611 (0x64B) - PWM2MIX Input 2 Volume */
{ 0x0000064c, 0x0000 }, /* R1612 (0x64C) - PWM2MIX Input 3 Source */
{ 0x0000064d, 0x0080 }, /* R1613 (0x64D) - PWM2MIX Input 3 Volume */
{ 0x0000064e, 0x0000 }, /* R1614 (0x64E) - PWM2MIX Input 4 Source */
{ 0x0000064f, 0x0080 }, /* R1615 (0x64F) - PWM2MIX Input 4 Volume */
{ 0x00000680, 0x0000 }, /* R1664 (0x680) - OUT1LMIX Input 1 Source */
{ 0x00000681, 0x0080 }, /* R1665 (0x681) - OUT1LMIX Input 1 Volume */
{ 0x00000682, 0x0000 }, /* R1666 (0x682) - OUT1LMIX Input 2 Source */
{ 0x00000683, 0x0080 }, /* R1667 (0x683) - OUT1LMIX Input 2 Volume */
{ 0x00000684, 0x0000 }, /* R1668 (0x684) - OUT1LMIX Input 3 Source */
{ 0x00000685, 0x0080 }, /* R1669 (0x685) - OUT1LMIX Input 3 Volume */
{ 0x00000686, 0x0000 }, /* R1670 (0x686) - OUT1LMIX Input 4 Source */
{ 0x00000687, 0x0080 }, /* R1671 (0x687) - OUT1LMIX Input 4 Volume */
{ 0x00000688, 0x0000 }, /* R1672 (0x688) - OUT1RMIX Input 1 Source */
{ 0x00000689, 0x0080 }, /* R1673 (0x689) - OUT1RMIX Input 1 Volume */
{ 0x0000068a, 0x0000 }, /* R1674 (0x68A) - OUT1RMIX Input 2 Source */
{ 0x0000068b, 0x0080 }, /* R1675 (0x68B) - OUT1RMIX Input 2 Volume */
{ 0x0000068c, 0x0000 }, /* R1676 (0x68C) - OUT1RMIX Input 3 Source */
{ 0x0000068d, 0x0080 }, /* R1677 (0x68D) - OUT1RMIX Input 3 Volume */
{ 0x0000068e, 0x0000 }, /* R1678 (0x68E) - OUT1RMIX Input 4 Source */
{ 0x0000068f, 0x0080 }, /* R1679 (0x68F) - OUT1RMIX Input 4 Volume */
{ 0x000006b0, 0x0000 }, /* R1712 (0x6B0) - OUT4LMIX Input 1 Source */
{ 0x000006b1, 0x0080 }, /* R1713 (0x6B1) - OUT4LMIX Input 1 Volume */
{ 0x000006b2, 0x0000 }, /* R1714 (0x6B2) - OUT4LMIX Input 2 Source */
{ 0x000006b3, 0x0080 }, /* R1715 (0x6B3) - OUT4LMIX Input 2 Volume */
{ 0x000006b4, 0x0000 }, /* R1716 (0x6B4) - OUT4LMIX Input 3 Source */
{ 0x000006b5, 0x0080 }, /* R1717 (0x6B5) - OUT4LMIX Input 3 Volume */
{ 0x000006b6, 0x0000 }, /* R1718 (0x6B6) - OUT4LMIX Input 4 Source */
{ 0x000006b7, 0x0080 }, /* R1719 (0x6B7) - OUT4LMIX Input 4 Volume */
{ 0x000006c0, 0x0000 }, /* R1728 (0x6C0) - OUT5LMIX Input 1 Source */
{ 0x000006c1, 0x0080 }, /* R1729 (0x6C1) - OUT5LMIX Input 1 Volume */
{ 0x000006c2, 0x0000 }, /* R1730 (0x6C2) - OUT5LMIX Input 2 Source */
{ 0x000006c3, 0x0080 }, /* R1731 (0x6C3) - OUT5LMIX Input 2 Volume */
{ 0x000006c4, 0x0000 }, /* R1732 (0x6C4) - OUT5LMIX Input 3 Source */
{ 0x000006c5, 0x0080 }, /* R1733 (0x6C5) - OUT5LMIX Input 3 Volume */
{ 0x000006c6, 0x0000 }, /* R1734 (0x6C6) - OUT5LMIX Input 4 Source */
{ 0x000006c7, 0x0080 }, /* R1735 (0x6C7) - OUT5LMIX Input 4 Volume */
{ 0x000006c8, 0x0000 }, /* R1736 (0x6C8) - OUT5RMIX Input 1 Source */
{ 0x000006c9, 0x0080 }, /* R1737 (0x6C9) - OUT5RMIX Input 1 Volume */
{ 0x000006ca, 0x0000 }, /* R1738 (0x6CA) - OUT5RMIX Input 2 Source */
{ 0x000006cb, 0x0080 }, /* R1739 (0x6CB) - OUT5RMIX Input 2 Volume */
{ 0x000006cc, 0x0000 }, /* R1740 (0x6CC) - OUT5RMIX Input 3 Source */
{ 0x000006cd, 0x0080 }, /* R1741 (0x6CD) - OUT5RMIX Input 3 Volume */
{ 0x000006ce, 0x0000 }, /* R1742 (0x6CE) - OUT5RMIX Input 4 Source */
{ 0x000006cf, 0x0080 }, /* R1743 (0x6CF) - OUT5RMIX Input 4 Volume */
{ 0x00000700, 0x0000 }, /* R1792 (0x700) - AIF1TX1MIX Input 1 Source */
{ 0x00000701, 0x0080 }, /* R1793 (0x701) - AIF1TX1MIX Input 1 Volume */
{ 0x00000702, 0x0000 }, /* R1794 (0x702) - AIF1TX1MIX Input 2 Source */
{ 0x00000703, 0x0080 }, /* R1795 (0x703) - AIF1TX1MIX Input 2 Volume */
{ 0x00000704, 0x0000 }, /* R1796 (0x704) - AIF1TX1MIX Input 3 Source */
{ 0x00000705, 0x0080 }, /* R1797 (0x705) - AIF1TX1MIX Input 3 Volume */
{ 0x00000706, 0x0000 }, /* R1798 (0x706) - AIF1TX1MIX Input 4 Source */
{ 0x00000707, 0x0080 }, /* R1799 (0x707) - AIF1TX1MIX Input 4 Volume */
{ 0x00000708, 0x0000 }, /* R1800 (0x708) - AIF1TX2MIX Input 1 Source */
{ 0x00000709, 0x0080 }, /* R1801 (0x709) - AIF1TX2MIX Input 1 Volume */
{ 0x0000070a, 0x0000 }, /* R1802 (0x70A) - AIF1TX2MIX Input 2 Source */
{ 0x0000070b, 0x0080 }, /* R1803 (0x70B) - AIF1TX2MIX Input 2 Volume */
{ 0x0000070c, 0x0000 }, /* R1804 (0x70C) - AIF1TX2MIX Input 3 Source */
{ 0x0000070d, 0x0080 }, /* R1805 (0x70D) - AIF1TX2MIX Input 3 Volume */
{ 0x0000070e, 0x0000 }, /* R1806 (0x70E) - AIF1TX2MIX Input 4 Source */
{ 0x0000070f, 0x0080 }, /* R1807 (0x70F) - AIF1TX2MIX Input 4 Volume */
{ 0x00000710, 0x0000 }, /* R1808 (0x710) - AIF1TX3MIX Input 1 Source */
{ 0x00000711, 0x0080 }, /* R1809 (0x711) - AIF1TX3MIX Input 1 Volume */
{ 0x00000712, 0x0000 }, /* R1810 (0x712) - AIF1TX3MIX Input 2 Source */
{ 0x00000713, 0x0080 }, /* R1811 (0x713) - AIF1TX3MIX Input 2 Volume */
{ 0x00000714, 0x0000 }, /* R1812 (0x714) - AIF1TX3MIX Input 3 Source */
{ 0x00000715, 0x0080 }, /* R1813 (0x715) - AIF1TX3MIX Input 3 Volume */
{ 0x00000716, 0x0000 }, /* R1814 (0x716) - AIF1TX3MIX Input 4 Source */
{ 0x00000717, 0x0080 }, /* R1815 (0x717) - AIF1TX3MIX Input 4 Volume */
{ 0x00000718, 0x0000 }, /* R1816 (0x718) - AIF1TX4MIX Input 1 Source */
{ 0x00000719, 0x0080 }, /* R1817 (0x719) - AIF1TX4MIX Input 1 Volume */
{ 0x0000071a, 0x0000 }, /* R1818 (0x71A) - AIF1TX4MIX Input 2 Source */
{ 0x0000071b, 0x0080 }, /* R1819 (0x71B) - AIF1TX4MIX Input 2 Volume */
{ 0x0000071c, 0x0000 }, /* R1820 (0x71C) - AIF1TX4MIX Input 3 Source */
{ 0x0000071d, 0x0080 }, /* R1821 (0x71D) - AIF1TX4MIX Input 3 Volume */
{ 0x0000071e, 0x0000 }, /* R1822 (0x71E) - AIF1TX4MIX Input 4 Source */
{ 0x0000071f, 0x0080 }, /* R1823 (0x71F) - AIF1TX4MIX Input 4 Volume */
{ 0x00000720, 0x0000 }, /* R1824 (0x720) - AIF1TX5MIX Input 1 Source */
{ 0x00000721, 0x0080 }, /* R1825 (0x721) - AIF1TX5MIX Input 1 Volume */
{ 0x00000722, 0x0000 }, /* R1826 (0x722) - AIF1TX5MIX Input 2 Source */
{ 0x00000723, 0x0080 }, /* R1827 (0x723) - AIF1TX5MIX Input 2 Volume */
{ 0x00000724, 0x0000 }, /* R1828 (0x724) - AIF1TX5MIX Input 3 Source */
{ 0x00000725, 0x0080 }, /* R1829 (0x725) - AIF1TX5MIX Input 3 Volume */
{ 0x00000726, 0x0000 }, /* R1830 (0x726) - AIF1TX5MIX Input 4 Source */
{ 0x00000727, 0x0080 }, /* R1831 (0x727) - AIF1TX5MIX Input 4 Volume */
{ 0x00000728, 0x0000 }, /* R1832 (0x728) - AIF1TX6MIX Input 1 Source */
{ 0x00000729, 0x0080 }, /* R1833 (0x729) - AIF1TX6MIX Input 1 Volume */
{ 0x0000072a, 0x0000 }, /* R1834 (0x72A) - AIF1TX6MIX Input 2 Source */
{ 0x0000072b, 0x0080 }, /* R1835 (0x72B) - AIF1TX6MIX Input 2 Volume */
{ 0x0000072c, 0x0000 }, /* R1836 (0x72C) - AIF1TX6MIX Input 3 Source */
{ 0x0000072d, 0x0080 }, /* R1837 (0x72D) - AIF1TX6MIX Input 3 Volume */
{ 0x0000072e, 0x0000 }, /* R1838 (0x72E) - AIF1TX6MIX Input 4 Source */
{ 0x0000072f, 0x0080 }, /* R1839 (0x72F) - AIF1TX6MIX Input 4 Volume */
{ 0x00000740, 0x0000 }, /* R1856 (0x740) - AIF2TX1MIX Input 1 Source */
{ 0x00000741, 0x0080 }, /* R1857 (0x741) - AIF2TX1MIX Input 1 Volume */
{ 0x00000742, 0x0000 }, /* R1858 (0x742) - AIF2TX1MIX Input 2 Source */
{ 0x00000743, 0x0080 }, /* R1859 (0x743) - AIF2TX1MIX Input 2 Volume */
{ 0x00000744, 0x0000 }, /* R1860 (0x744) - AIF2TX1MIX Input 3 Source */
{ 0x00000745, 0x0080 }, /* R1861 (0x745) - AIF2TX1MIX Input 3 Volume */
{ 0x00000746, 0x0000 }, /* R1862 (0x746) - AIF2TX1MIX Input 4 Source */
{ 0x00000747, 0x0080 }, /* R1863 (0x747) - AIF2TX1MIX Input 4 Volume */
{ 0x00000748, 0x0000 }, /* R1864 (0x748) - AIF2TX2MIX Input 1 Source */
{ 0x00000749, 0x0080 }, /* R1865 (0x749) - AIF2TX2MIX Input 1 Volume */
{ 0x0000074a, 0x0000 }, /* R1866 (0x74A) - AIF2TX2MIX Input 2 Source */
{ 0x0000074b, 0x0080 }, /* R1867 (0x74B) - AIF2TX2MIX Input 2 Volume */
{ 0x0000074c, 0x0000 }, /* R1868 (0x74C) - AIF2TX2MIX Input 3 Source */
{ 0x0000074d, 0x0080 }, /* R1869 (0x74D) - AIF2TX2MIX Input 3 Volume */
{ 0x0000074e, 0x0000 }, /* R1870 (0x74E) - AIF2TX2MIX Input 4 Source */
{ 0x0000074f, 0x0080 }, /* R1871 (0x74F) - AIF2TX2MIX Input 4 Volume */
{ 0x00000750, 0x0000 }, /* R1872 (0x750) - AIF2TX3MIX Input 1 Source */
{ 0x00000751, 0x0080 }, /* R1873 (0x751) - AIF2TX3MIX Input 1 Volume */
{ 0x00000752, 0x0000 }, /* R1874 (0x752) - AIF2TX3MIX Input 2 Source */
{ 0x00000753, 0x0080 }, /* R1875 (0x753) - AIF2TX3MIX Input 2 Volume */
{ 0x00000754, 0x0000 }, /* R1876 (0x754) - AIF2TX3MIX Input 3 Source */
{ 0x00000755, 0x0080 }, /* R1877 (0x755) - AIF2TX3MIX Input 3 Volume */
{ 0x00000756, 0x0000 }, /* R1878 (0x756) - AIF2TX3MIX Input 4 Source */
{ 0x00000757, 0x0080 }, /* R1879 (0x757) - AIF2TX3MIX Input 4 Volume */
{ 0x00000758, 0x0000 }, /* R1880 (0x758) - AIF2TX4MIX Input 1 Source */
{ 0x00000759, 0x0080 }, /* R1881 (0x759) - AIF2TX4MIX Input 1 Volume */
{ 0x0000075a, 0x0000 }, /* R1882 (0x75A) - AIF2TX4MIX Input 2 Source */
{ 0x0000075b, 0x0080 }, /* R1883 (0x75B) - AIF2TX4MIX Input 2 Volume */
{ 0x0000075c, 0x0000 }, /* R1884 (0x75C) - AIF2TX4MIX Input 3 Source */
{ 0x0000075d, 0x0080 }, /* R1885 (0x75D) - AIF2TX4MIX Input 3 Volume */
{ 0x0000075e, 0x0000 }, /* R1886 (0x75E) - AIF2TX4MIX Input 4 Source */
{ 0x0000075f, 0x0080 }, /* R1887 (0x75F) - AIF2TX4MIX Input 4 Volume */
{ 0x00000780, 0x0000 }, /* R1920 (0x780) - AIF3TX1MIX Input 1 Source */
{ 0x00000781, 0x0080 }, /* R1921 (0x781) - AIF3TX1MIX Input 1 Volume */
{ 0x00000782, 0x0000 }, /* R1922 (0x782) - AIF3TX1MIX Input 2 Source */
{ 0x00000783, 0x0080 }, /* R1923 (0x783) - AIF3TX1MIX Input 2 Volume */
{ 0x00000784, 0x0000 }, /* R1924 (0x784) - AIF3TX1MIX Input 3 Source */
{ 0x00000785, 0x0080 }, /* R1925 (0x785) - AIF3TX1MIX Input 3 Volume */
{ 0x00000786, 0x0000 }, /* R1926 (0x786) - AIF3TX1MIX Input 4 Source */
{ 0x00000787, 0x0080 }, /* R1927 (0x787) - AIF3TX1MIX Input 4 Volume */
{ 0x00000788, 0x0000 }, /* R1928 (0x788) - AIF3TX2MIX Input 1 Source */
{ 0x00000789, 0x0080 }, /* R1929 (0x789) - AIF3TX2MIX Input 1 Volume */
{ 0x0000078a, 0x0000 }, /* R1930 (0x78A) - AIF3TX2MIX Input 2 Source */
{ 0x0000078b, 0x0080 }, /* R1931 (0x78B) - AIF3TX2MIX Input 2 Volume */
{ 0x0000078c, 0x0000 }, /* R1932 (0x78C) - AIF3TX2MIX Input 3 Source */
{ 0x0000078d, 0x0080 }, /* R1933 (0x78D) - AIF3TX2MIX Input 3 Volume */
{ 0x0000078e, 0x0000 }, /* R1934 (0x78E) - AIF3TX2MIX Input 4 Source */
{ 0x0000078f, 0x0080 }, /* R1935 (0x78F) - AIF3TX2MIX Input 4 Volume */
{ 0x00000800, 0x0000 }, /* R2048 (0x800) - SPDIF1TX1MIX Input 1 Source */
{ 0x00000801, 0x0080 }, /* R2049 (0x801) - SPDIF1TX1MIX Input 1 Volume */
{ 0x00000808, 0x0000 }, /* R2056 (0x808) - SPDIF1TX2MIX Input 1 Source */
{ 0x00000809, 0x0080 }, /* R2057 (0x809) - SPDIF1TX2MIX Input 1 Volume */
{ 0x00000880, 0x0000 }, /* R2176 (0x880) - EQ1MIX Input 1 Source */
{ 0x00000881, 0x0080 }, /* R2177 (0x881) - EQ1MIX Input 1 Volume */
{ 0x00000882, 0x0000 }, /* R2178 (0x882) - EQ1MIX Input 2 Source */
{ 0x00000883, 0x0080 }, /* R2179 (0x883) - EQ1MIX Input 2 Volume */
{ 0x00000884, 0x0000 }, /* R2180 (0x884) - EQ1MIX Input 3 Source */
{ 0x00000885, 0x0080 }, /* R2181 (0x885) - EQ1MIX Input 3 Volume */
{ 0x00000886, 0x0000 }, /* R2182 (0x886) - EQ1MIX Input 4 Source */
{ 0x00000887, 0x0080 }, /* R2183 (0x887) - EQ1MIX Input 4 Volume */
{ 0x00000888, 0x0000 }, /* R2184 (0x888) - EQ2MIX Input 1 Source */
{ 0x00000889, 0x0080 }, /* R2185 (0x889) - EQ2MIX Input 1 Volume */
{ 0x0000088a, 0x0000 }, /* R2186 (0x88A) - EQ2MIX Input 2 Source */
{ 0x0000088b, 0x0080 }, /* R2187 (0x88B) - EQ2MIX Input 2 Volume */
{ 0x0000088c, 0x0000 }, /* R2188 (0x88C) - EQ2MIX Input 3 Source */
{ 0x0000088d, 0x0080 }, /* R2189 (0x88D) - EQ2MIX Input 3 Volume */
{ 0x0000088e, 0x0000 }, /* R2190 (0x88E) - EQ2MIX Input 4 Source */
{ 0x0000088f, 0x0080 }, /* R2191 (0x88F) - EQ2MIX Input 4 Volume */
{ 0x00000890, 0x0000 }, /* R2192 (0x890) - EQ3MIX Input 1 Source */
{ 0x00000891, 0x0080 }, /* R2193 (0x891) - EQ3MIX Input 1 Volume */
{ 0x00000892, 0x0000 }, /* R2194 (0x892) - EQ3MIX Input 2 Source */
{ 0x00000893, 0x0080 }, /* R2195 (0x893) - EQ3MIX Input 2 Volume */
{ 0x00000894, 0x0000 }, /* R2196 (0x894) - EQ3MIX Input 3 Source */
{ 0x00000895, 0x0080 }, /* R2197 (0x895) - EQ3MIX Input 3 Volume */
{ 0x00000896, 0x0000 }, /* R2198 (0x896) - EQ3MIX Input 4 Source */
{ 0x00000897, 0x0080 }, /* R2199 (0x897) - EQ3MIX Input 4 Volume */
{ 0x00000898, 0x0000 }, /* R2200 (0x898) - EQ4MIX Input 1 Source */
{ 0x00000899, 0x0080 }, /* R2201 (0x899) - EQ4MIX Input 1 Volume */
{ 0x0000089a, 0x0000 }, /* R2202 (0x89A) - EQ4MIX Input 2 Source */
{ 0x0000089b, 0x0080 }, /* R2203 (0x89B) - EQ4MIX Input 2 Volume */
{ 0x0000089c, 0x0000 }, /* R2204 (0x89C) - EQ4MIX Input 3 Source */
{ 0x0000089d, 0x0080 }, /* R2205 (0x89D) - EQ4MIX Input 3 Volume */
{ 0x0000089e, 0x0000 }, /* R2206 (0x89E) - EQ4MIX Input 4 Source */
{ 0x0000089f, 0x0080 }, /* R2207 (0x89F) - EQ4MIX Input 4 Volume */
{ 0x000008c0, 0x0000 }, /* R2240 (0x8C0) - DRC1LMIX Input 1 Source */
{ 0x000008c1, 0x0080 }, /* R2241 (0x8C1) - DRC1LMIX Input 1 Volume */
{ 0x000008c2, 0x0000 }, /* R2242 (0x8C2) - DRC1LMIX Input 2 Source */
{ 0x000008c3, 0x0080 }, /* R2243 (0x8C3) - DRC1LMIX Input 2 Volume */
{ 0x000008c4, 0x0000 }, /* R2244 (0x8C4) - DRC1LMIX Input 3 Source */
{ 0x000008c5, 0x0080 }, /* R2245 (0x8C5) - DRC1LMIX Input 3 Volume */
{ 0x000008c6, 0x0000 }, /* R2246 (0x8C6) - DRC1LMIX Input 4 Source */
{ 0x000008c7, 0x0080 }, /* R2247 (0x8C7) - DRC1LMIX Input 4 Volume */
{ 0x000008c8, 0x0000 }, /* R2248 (0x8C8) - DRC1RMIX Input 1 Source */
{ 0x000008c9, 0x0080 }, /* R2249 (0x8C9) - DRC1RMIX Input 1 Volume */
{ 0x000008ca, 0x0000 }, /* R2250 (0x8CA) - DRC1RMIX Input 2 Source */
{ 0x000008cb, 0x0080 }, /* R2251 (0x8CB) - DRC1RMIX Input 2 Volume */
{ 0x000008cc, 0x0000 }, /* R2252 (0x8CC) - DRC1RMIX Input 3 Source */
{ 0x000008cd, 0x0080 }, /* R2253 (0x8CD) - DRC1RMIX Input 3 Volume */
{ 0x000008ce, 0x0000 }, /* R2254 (0x8CE) - DRC1RMIX Input 4 Source */
{ 0x000008cf, 0x0080 }, /* R2255 (0x8CF) - DRC1RMIX Input 4 Volume */
{ 0x000008d0, 0x0000 }, /* R2256 (0x8D0) - DRC2LMIX Input 1 Source */
{ 0x000008d1, 0x0080 }, /* R2257 (0x8D1) - DRC2LMIX Input 1 Volume */
{ 0x000008d2, 0x0000 }, /* R2258 (0x8D2) - DRC2LMIX Input 2 Source */
{ 0x000008d3, 0x0080 }, /* R2259 (0x8D3) - DRC2LMIX Input 2 Volume */
{ 0x000008d4, 0x0000 }, /* R2260 (0x8D4) - DRC2LMIX Input 3 Source */
{ 0x000008d5, 0x0080 }, /* R2261 (0x8D5) - DRC2LMIX Input 3 Volume */
{ 0x000008d6, 0x0000 }, /* R2262 (0x8D6) - DRC2LMIX Input 4 Source */
{ 0x000008d7, 0x0080 }, /* R2263 (0x8D7) - DRC2LMIX Input 4 Volume */
{ 0x000008d8, 0x0000 }, /* R2264 (0x8D8) - DRC2RMIX Input 1 Source */
{ 0x000008d9, 0x0080 }, /* R2265 (0x8D9) - DRC2RMIX Input 1 Volume */
{ 0x000008da, 0x0000 }, /* R2266 (0x8DA) - DRC2RMIX Input 2 Source */
{ 0x000008db, 0x0080 }, /* R2267 (0x8DB) - DRC2RMIX Input 2 Volume */
{ 0x000008dc, 0x0000 }, /* R2268 (0x8DC) - DRC2RMIX Input 3 Source */
{ 0x000008dd, 0x0080 }, /* R2269 (0x8DD) - DRC2RMIX Input 3 Volume */
{ 0x000008de, 0x0000 }, /* R2270 (0x8DE) - DRC2RMIX Input 4 Source */
{ 0x000008df, 0x0080 }, /* R2271 (0x8DF) - DRC2RMIX Input 4 Volume */
{ 0x00000900, 0x0000 }, /* R2304 (0x900) - HPLP1MIX Input 1 Source */
{ 0x00000901, 0x0080 }, /* R2305 (0x901) - HPLP1MIX Input 1 Volume */
{ 0x00000902, 0x0000 }, /* R2306 (0x902) - HPLP1MIX Input 2 Source */
{ 0x00000903, 0x0080 }, /* R2307 (0x903) - HPLP1MIX Input 2 Volume */
{ 0x00000904, 0x0000 }, /* R2308 (0x904) - HPLP1MIX Input 3 Source */
{ 0x00000905, 0x0080 }, /* R2309 (0x905) - HPLP1MIX Input 3 Volume */
{ 0x00000906, 0x0000 }, /* R2310 (0x906) - HPLP1MIX Input 4 Source */
{ 0x00000907, 0x0080 }, /* R2311 (0x907) - HPLP1MIX Input 4 Volume */
{ 0x00000908, 0x0000 }, /* R2312 (0x908) - HPLP2MIX Input 1 Source */
{ 0x00000909, 0x0080 }, /* R2313 (0x909) - HPLP2MIX Input 1 Volume */
{ 0x0000090a, 0x0000 }, /* R2314 (0x90A) - HPLP2MIX Input 2 Source */
{ 0x0000090b, 0x0080 }, /* R2315 (0x90B) - HPLP2MIX Input 2 Volume */
{ 0x0000090c, 0x0000 }, /* R2316 (0x90C) - HPLP2MIX Input 3 Source */
{ 0x0000090d, 0x0080 }, /* R2317 (0x90D) - HPLP2MIX Input 3 Volume */
{ 0x0000090e, 0x0000 }, /* R2318 (0x90E) - HPLP2MIX Input 4 Source */
{ 0x0000090f, 0x0080 }, /* R2319 (0x90F) - HPLP2MIX Input 4 Volume */
{ 0x00000910, 0x0000 }, /* R2320 (0x910) - HPLP3MIX Input 1 Source */
{ 0x00000911, 0x0080 }, /* R2321 (0x911) - HPLP3MIX Input 1 Volume */
{ 0x00000912, 0x0000 }, /* R2322 (0x912) - HPLP3MIX Input 2 Source */
{ 0x00000913, 0x0080 }, /* R2323 (0x913) - HPLP3MIX Input 2 Volume */
{ 0x00000914, 0x0000 }, /* R2324 (0x914) - HPLP3MIX Input 3 Source */
{ 0x00000915, 0x0080 }, /* R2325 (0x915) - HPLP3MIX Input 3 Volume */
{ 0x00000916, 0x0000 }, /* R2326 (0x916) - HPLP3MIX Input 4 Source */
{ 0x00000917, 0x0080 }, /* R2327 (0x917) - HPLP3MIX Input 4 Volume */
{ 0x00000918, 0x0000 }, /* R2328 (0x918) - HPLP4MIX Input 1 Source */
{ 0x00000919, 0x0080 }, /* R2329 (0x919) - HPLP4MIX Input 1 Volume */
{ 0x0000091a, 0x0000 }, /* R2330 (0x91A) - HPLP4MIX Input 2 Source */
{ 0x0000091b, 0x0080 }, /* R2331 (0x91B) - HPLP4MIX Input 2 Volume */
{ 0x0000091c, 0x0000 }, /* R2332 (0x91C) - HPLP4MIX Input 3 Source */
{ 0x0000091d, 0x0080 }, /* R2333 (0x91D) - HPLP4MIX Input 3 Volume */
{ 0x0000091e, 0x0000 }, /* R2334 (0x91E) - HPLP4MIX Input 4 Source */
{ 0x0000091f, 0x0080 }, /* R2335 (0x91F) - HPLP4MIX Input 4 Volume */
{ 0x00000940, 0x0000 }, /* R2368 (0x940) - DSP1LMIX Input 1 Source */
{ 0x00000941, 0x0080 }, /* R2369 (0x941) - DSP1LMIX Input 1 Volume */
{ 0x00000942, 0x0000 }, /* R2370 (0x942) - DSP1LMIX Input 2 Source */
{ 0x00000943, 0x0080 }, /* R2371 (0x943) - DSP1LMIX Input 2 Volume */
{ 0x00000944, 0x0000 }, /* R2372 (0x944) - DSP1LMIX Input 3 Source */
{ 0x00000945, 0x0080 }, /* R2373 (0x945) - DSP1LMIX Input 3 Volume */
{ 0x00000946, 0x0000 }, /* R2374 (0x946) - DSP1LMIX Input 4 Source */
{ 0x00000947, 0x0080 }, /* R2375 (0x947) - DSP1LMIX Input 4 Volume */
{ 0x00000948, 0x0000 }, /* R2376 (0x948) - DSP1RMIX Input 1 Source */
{ 0x00000949, 0x0080 }, /* R2377 (0x949) - DSP1RMIX Input 1 Volume */
{ 0x0000094a, 0x0000 }, /* R2378 (0x94A) - DSP1RMIX Input 2 Source */
{ 0x0000094b, 0x0080 }, /* R2379 (0x94B) - DSP1RMIX Input 2 Volume */
{ 0x0000094c, 0x0000 }, /* R2380 (0x94C) - DSP1RMIX Input 3 Source */
{ 0x0000094d, 0x0080 }, /* R2381 (0x94D) - DSP1RMIX Input 3 Volume */
{ 0x0000094e, 0x0000 }, /* R2382 (0x94E) - DSP1RMIX Input 4 Source */
{ 0x0000094f, 0x0080 }, /* R2383 (0x94F) - DSP1RMIX Input 4 Volume */
{ 0x00000950, 0x0000 }, /* R2384 (0x950) - DSP1AUX1MIX Input 1 Source */
{ 0x00000958, 0x0000 }, /* R2392 (0x958) - DSP1AUX2MIX Input 1 Source */
{ 0x00000960, 0x0000 }, /* R2400 (0x960) - DSP1AUX3MIX Input 1 Source */
{ 0x00000968, 0x0000 }, /* R2408 (0x968) - DSP1AUX4MIX Input 1 Source */
{ 0x00000970, 0x0000 }, /* R2416 (0x970) - DSP1AUX5MIX Input 1 Source */
{ 0x00000978, 0x0000 }, /* R2424 (0x978) - DSP1AUX6MIX Input 1 Source */
{ 0x00000b00, 0x0000 }, /* R2816 (0xB00) - ISRC1DEC1MIX Input 1 Source */
{ 0x00000b08, 0x0000 }, /* R2824 (0xB08) - ISRC1DEC2MIX Input 1 Source */
{ 0x00000b10, 0x0000 }, /* R2832 (0xB10) - ISRC1DEC3MIX Input 1 Source */
{ 0x00000b18, 0x0000 }, /* R2840 (0xB18) - ISRC1DEC4MIX Input 1 Source */
{ 0x00000b20, 0x0000 }, /* R2848 (0xB20) - ISRC1INT1MIX Input 1 Source */
{ 0x00000b28, 0x0000 }, /* R2856 (0xB28) - ISRC1INT2MIX Input 1 Source */
{ 0x00000b30, 0x0000 }, /* R2864 (0xB30) - ISRC1INT3MIX Input 1 Source */
{ 0x00000b38, 0x0000 }, /* R2872 (0xB38) - ISRC1INT4MIX Input 1 Source */
{ 0x00000b40, 0x0000 }, /* R2880 (0xB40) - ISRC2DEC1MIX Input 1 Source */
{ 0x00000b48, 0x0000 }, /* R2888 (0xB48) - ISRC2DEC2MIX Input 1 Source */
{ 0x00000b50, 0x0000 }, /* R2896 (0xB50) - ISRC2DEC3MIX Input 1 Source */
{ 0x00000b58, 0x0000 }, /* R2904 (0xB58) - ISRC2DEC4MIX Input 1 Source */
{ 0x00000b60, 0x0000 }, /* R2912 (0xB60) - ISRC2INT1MIX Input 1 Source */
{ 0x00000b68, 0x0000 }, /* R2920 (0xB68) - ISRC2INT2MIX Input 1 Source */
{ 0x00000b70, 0x0000 }, /* R2928 (0xB70) - ISRC2INT3MIX Input 1 Source */
{ 0x00000b78, 0x0000 }, /* R2936 (0xB78) - ISRC2INT4MIX Input 1 Source */
{ 0x00000e00, 0x0000 }, /* R3584 (0xE00) - FX Ctrl 1 */
{ 0x00000e10, 0x6318 }, /* R3600 (0xE10) - EQ1 1 */
{ 0x00000e11, 0x6300 }, /* R3601 (0xE11) - EQ1 2 */
{ 0x00000e12, 0x0fc8 }, /* R3602 (0xE12) - EQ1 3 */
{ 0x00000e13, 0x03fe }, /* R3603 (0xE13) - EQ1 4 */
{ 0x00000e14, 0x00e0 }, /* R3604 (0xE14) - EQ1 5 */
{ 0x00000e15, 0x1ec4 }, /* R3605 (0xE15) - EQ1 6 */
{ 0x00000e16, 0xf136 }, /* R3606 (0xE16) - EQ1 7 */
{ 0x00000e17, 0x0409 }, /* R3607 (0xE17) - EQ1 8 */
{ 0x00000e18, 0x04cc }, /* R3608 (0xE18) - EQ1 9 */
{ 0x00000e19, 0x1c9b }, /* R3609 (0xE19) - EQ1 10 */
{ 0x00000e1a, 0xf337 }, /* R3610 (0xE1A) - EQ1 11 */
{ 0x00000e1b, 0x040b }, /* R3611 (0xE1B) - EQ1 12 */
{ 0x00000e1c, 0x0cbb }, /* R3612 (0xE1C) - EQ1 13 */
{ 0x00000e1d, 0x16f8 }, /* R3613 (0xE1D) - EQ1 14 */
{ 0x00000e1e, 0xf7d9 }, /* R3614 (0xE1E) - EQ1 15 */
{ 0x00000e1f, 0x040a }, /* R3615 (0xE1F) - EQ1 16 */
{ 0x00000e20, 0x1f14 }, /* R3616 (0xE20) - EQ1 17 */
{ 0x00000e21, 0x058c }, /* R3617 (0xE21) - EQ1 18 */
{ 0x00000e22, 0x0563 }, /* R3618 (0xE22) - EQ1 19 */
{ 0x00000e23, 0x4000 }, /* R3619 (0xE23) - EQ1 20 */
{ 0x00000e24, 0x0b75 }, /* R3620 (0xE24) - EQ1 21 */
{ 0x00000e26, 0x6318 }, /* R3622 (0xE26) - EQ2 1 */
{ 0x00000e27, 0x6300 }, /* R3623 (0xE27) - EQ2 2 */
{ 0x00000e28, 0x0fc8 }, /* R3624 (0xE28) - EQ2 3 */
{ 0x00000e29, 0x03fe }, /* R3625 (0xE29) - EQ2 4 */
{ 0x00000e2a, 0x00e0 }, /* R3626 (0xE2A) - EQ2 5 */
{ 0x00000e2b, 0x1ec4 }, /* R3627 (0xE2B) - EQ2 6 */
{ 0x00000e2c, 0xf136 }, /* R3628 (0xE2C) - EQ2 7 */
{ 0x00000e2d, 0x0409 }, /* R3629 (0xE2D) - EQ2 8 */
{ 0x00000e2e, 0x04cc }, /* R3630 (0xE2E) - EQ2 9 */
{ 0x00000e2f, 0x1c9b }, /* R3631 (0xE2F) - EQ2 10 */
{ 0x00000e30, 0xf337 }, /* R3632 (0xE30) - EQ2 11 */
{ 0x00000e31, 0x040b }, /* R3633 (0xE31) - EQ2 12 */
{ 0x00000e32, 0x0cbb }, /* R3634 (0xE32) - EQ2 13 */
{ 0x00000e33, 0x16f8 }, /* R3635 (0xE33) - EQ2 14 */
{ 0x00000e34, 0xf7d9 }, /* R3636 (0xE34) - EQ2 15 */
{ 0x00000e35, 0x040a }, /* R3637 (0xE35) - EQ2 16 */
{ 0x00000e36, 0x1f14 }, /* R3638 (0xE36) - EQ2 17 */
{ 0x00000e37, 0x058c }, /* R3639 (0xE37) - EQ2 18 */
{ 0x00000e38, 0x0563 }, /* R3640 (0xE38) - EQ2 19 */
{ 0x00000e39, 0x4000 }, /* R3641 (0xE39) - EQ2 20 */
{ 0x00000e3a, 0x0b75 }, /* R3642 (0xE3A) - EQ2 21 */
{ 0x00000e3c, 0x6318 }, /* R3644 (0xE3C) - EQ3 1 */
{ 0x00000e3d, 0x6300 }, /* R3645 (0xE3D) - EQ3 2 */
{ 0x00000e3e, 0x0fc8 }, /* R3646 (0xE3E) - EQ3 3 */
{ 0x00000e3f, 0x03fe }, /* R3647 (0xE3F) - EQ3 4 */
{ 0x00000e40, 0x00e0 }, /* R3648 (0xE40) - EQ3 5 */
{ 0x00000e41, 0x1ec4 }, /* R3649 (0xE41) - EQ3 6 */
{ 0x00000e42, 0xf136 }, /* R3650 (0xE42) - EQ3 7 */
{ 0x00000e43, 0x0409 }, /* R3651 (0xE43) - EQ3 8 */
{ 0x00000e44, 0x04cc }, /* R3652 (0xE44) - EQ3 9 */
{ 0x00000e45, 0x1c9b }, /* R3653 (0xE45) - EQ3 10 */
{ 0x00000e46, 0xf337 }, /* R3654 (0xE46) - EQ3 11 */
{ 0x00000e47, 0x040b }, /* R3655 (0xE47) - EQ3 12 */
{ 0x00000e48, 0x0cbb }, /* R3656 (0xE48) - EQ3 13 */
{ 0x00000e49, 0x16f8 }, /* R3657 (0xE49) - EQ3 14 */
{ 0x00000e4a, 0xf7d9 }, /* R3658 (0xE4A) - EQ3 15 */
{ 0x00000e4b, 0x040a }, /* R3659 (0xE4B) - EQ3 16 */
{ 0x00000e4c, 0x1f14 }, /* R3660 (0xE4C) - EQ3 17 */
{ 0x00000e4d, 0x058c }, /* R3661 (0xE4D) - EQ3 18 */
{ 0x00000e4e, 0x0563 }, /* R3662 (0xE4E) - EQ3 19 */
{ 0x00000e4f, 0x4000 }, /* R3663 (0xE4F) - EQ3 20 */
{ 0x00000e50, 0x0b75 }, /* R3664 (0xE50) - EQ3 21 */
{ 0x00000e52, 0x6318 }, /* R3666 (0xE52) - EQ4 1 */
{ 0x00000e53, 0x6300 }, /* R3667 (0xE53) - EQ4 2 */
{ 0x00000e54, 0x0fc8 }, /* R3668 (0xE54) - EQ4 3 */
{ 0x00000e55, 0x03fe }, /* R3669 (0xE55) - EQ4 4 */
{ 0x00000e56, 0x00e0 }, /* R3670 (0xE56) - EQ4 5 */
{ 0x00000e57, 0x1ec4 }, /* R3671 (0xE57) - EQ4 6 */
{ 0x00000e58, 0xf136 }, /* R3672 (0xE58) - EQ4 7 */
{ 0x00000e59, 0x0409 }, /* R3673 (0xE59) - EQ4 8 */
{ 0x00000e5a, 0x04cc }, /* R3674 (0xE5A) - EQ4 9 */
{ 0x00000e5b, 0x1c9b }, /* R3675 (0xE5B) - EQ4 10 */
{ 0x00000e5c, 0xf337 }, /* R3676 (0xE5C) - EQ4 11 */
{ 0x00000e5d, 0x040b }, /* R3677 (0xE5D) - EQ4 12 */
{ 0x00000e5e, 0x0cbb }, /* R3678 (0xE5E) - EQ4 13 */
{ 0x00000e5f, 0x16f8 }, /* R3679 (0xE5F) - EQ4 14 */
{ 0x00000e60, 0xf7d9 }, /* R3680 (0xE60) - EQ4 15 */
{ 0x00000e61, 0x040a }, /* R3681 (0xE61) - EQ4 16 */
{ 0x00000e62, 0x1f14 }, /* R3682 (0xE62) - EQ4 17 */
{ 0x00000e63, 0x058c }, /* R3683 (0xE63) - EQ4 18 */
{ 0x00000e64, 0x0563 }, /* R3684 (0xE64) - EQ4 19 */
{ 0x00000e65, 0x4000 }, /* R3685 (0xE65) - EQ4 20 */
{ 0x00000e66, 0x0b75 }, /* R3686 (0xE66) - EQ4 21 */
{ 0x00000e80, 0x0018 }, /* R3712 (0xE80) - DRC1 Ctrl 1 */
{ 0x00000e81, 0x0933 }, /* R3713 (0xE81) - DRC1 Ctrl 2 */
{ 0x00000e82, 0x0018 }, /* R3714 (0xE82) - DRC1 Ctrl 3 */
{ 0x00000e83, 0x0000 }, /* R3715 (0xE83) - DRC1 Ctrl 4 */
{ 0x00000e84, 0x0000 }, /* R3716 (0xE84) - DRC1 Ctrl 5 */
{ 0x00000e88, 0x0018 }, /* R3720 (0xE88) - DRC2 Ctrl 1 */
{ 0x00000e89, 0x0933 }, /* R3721 (0xE89) - DRC2 Ctrl 2 */
{ 0x00000e8a, 0x0018 }, /* R3722 (0xE8A) - DRC2 Ctrl 3 */
{ 0x00000e8b, 0x0000 }, /* R3723 (0xE8B) - DRC2 Ctrl 4 */
{ 0x00000e8c, 0x0000 }, /* R3724 (0xE8C) - DRC2 Ctrl 5 */
{ 0x00000ec0, 0x0000 }, /* R3776 (0xEC0) - HPLPF1 1 */
{ 0x00000ec1, 0x0000 }, /* R3777 (0xEC1) - HPLPF1 2 */
{ 0x00000ec4, 0x0000 }, /* R3780 (0xEC4) - HPLPF2 1 */
{ 0x00000ec5, 0x0000 }, /* R3781 (0xEC5) - HPLPF2 2 */
{ 0x00000ec8, 0x0000 }, /* R3784 (0xEC8) - HPLPF3 1 */
{ 0x00000ec9, 0x0000 }, /* R3785 (0xEC9) - HPLPF3 2 */
{ 0x00000ecc, 0x0000 }, /* R3788 (0xECC) - HPLPF4 1 */
{ 0x00000ecd, 0x0000 }, /* R3789 (0xECD) - HPLPF4 2 */
{ 0x00000ef0, 0x0000 }, /* R3824 (0xEF0) - ISRC1 Ctrl 1 */
{ 0x00000ef1, 0x0001 }, /* R3825 (0xEF1) - ISRC1 Ctrl 2 */
{ 0x00000ef2, 0x0000 }, /* R3826 (0xEF2) - ISRC1 Ctrl 3 */
{ 0x00000ef3, 0x0000 }, /* R3827 (0xEF3) - ISRC2 Ctrl 1 */
{ 0x00000ef4, 0x0001 }, /* R3828 (0xEF4) - ISRC2 Ctrl 2 */
{ 0x00000ef5, 0x0000 }, /* R3829 (0xEF5) - ISRC2 Ctrl 3 */
{ 0x00001700, 0x2801 }, /* R5888 (0x1700) - GPIO1 Ctrl 1 */
{ 0x00001701, 0xe800 }, /* R5889 (0x1701) - GPIO1 Ctrl 2 */
{ 0x00001702, 0x2801 }, /* R5890 (0x1702) - GPIO2 Ctrl 1 */
{ 0x00001703, 0xe800 }, /* R5891 (0x1703) - GPIO2 Ctrl 2 */
{ 0x00001704, 0x2801 }, /* R5892 (0x1704) - GPIO3 Ctrl 1 */
{ 0x00001705, 0xe800 }, /* R5893 (0x1705) - GPIO3 Ctrl 2 */
{ 0x00001706, 0x2801 }, /* R5894 (0x1706) - GPIO4 Ctrl 1 */
{ 0x00001707, 0xe800 }, /* R5895 (0x1707) - GPIO4 Ctrl 2 */
{ 0x00001708, 0x2801 }, /* R5896 (0x1708) - GPIO5 Ctrl 1 */
{ 0x00001709, 0xe800 }, /* R5897 (0x1709) - GPIO5 Ctrl 2 */
{ 0x0000170a, 0x2801 }, /* R5898 (0x170A) - GPIO6 Ctrl 1 */
{ 0x0000170b, 0xe800 }, /* R5899 (0x170B) - GPIO6 Ctrl 2 */
{ 0x0000170c, 0x2801 }, /* R5900 (0x170C) - GPIO7 Ctrl 1 */
{ 0x0000170d, 0xe800 }, /* R5901 (0x170D) - GPIO7 Ctrl 2 */
{ 0x0000170e, 0x2801 }, /* R5902 (0x170E) - GPIO8 Ctrl 1 */
{ 0x0000170f, 0xe800 }, /* R5903 (0x170F) - GPIO8 Ctrl 2 */
{ 0x00001710, 0x2801 }, /* R5904 (0x1710) - GPIO9 Ctrl 1 */
{ 0x00001711, 0xe800 }, /* R5905 (0x1711) - GPIO9 Ctrl 2 */
{ 0x00001712, 0x2801 }, /* R5906 (0x1712) - GPIO10 Ctrl 1 */
{ 0x00001713, 0xe800 }, /* R5907 (0x1713) - GPIO10 Ctrl 2 */
{ 0x00001714, 0x2801 }, /* R5908 (0x1714) - GPIO11 Ctrl 1 */
{ 0x00001715, 0xe800 }, /* R5909 (0x1715) - GPIO11 Ctrl 2 */
{ 0x00001716, 0x2801 }, /* R5910 (0x1716) - GPIO12 Ctrl 1 */
{ 0x00001717, 0xe800 }, /* R5911 (0x1717) - GPIO12 Ctrl 2 */
{ 0x00001718, 0x2801 }, /* R5912 (0x1718) - GPIO13 Ctrl 1 */
{ 0x00001719, 0xe800 }, /* R5913 (0x1719) - GPIO13 Ctrl 2 */
{ 0x0000171a, 0x2801 }, /* R5914 (0x171A) - GPIO14 Ctrl 1 */
{ 0x0000171b, 0xe800 }, /* R5915 (0x171B) - GPIO14 Ctrl 2 */
{ 0x0000171c, 0x2801 }, /* R5916 (0x171C) - GPIO15 Ctrl 1 */
{ 0x0000171d, 0xe800 }, /* R5917 (0x171D) - GPIO15 Ctrl 2 */
{ 0x00001840, 0xffff }, /* R6208 (0x1840) - IRQ1 Mask 1 */
{ 0x00001841, 0xffff }, /* R6209 (0x1841) - IRQ1 Mask 2 */
{ 0x00001842, 0xffff }, /* R6210 (0x1842) - IRQ1 Mask 3 */
{ 0x00001843, 0xffff }, /* R6211 (0x1843) - IRQ1 Mask 4 */
{ 0x00001844, 0xffff }, /* R6212 (0x1844) - IRQ1 Mask 5 */
{ 0x00001845, 0xffff }, /* R6213 (0x1845) - IRQ1 Mask 6 */
{ 0x00001846, 0xffff }, /* R6214 (0x1846) - IRQ1 Mask 7 */
{ 0x00001847, 0xffff }, /* R6215 (0x1847) - IRQ1 Mask 8 */
{ 0x00001848, 0xffff }, /* R6216 (0x1848) - IRQ1 Mask 9 */
{ 0x00001849, 0xffff }, /* R6217 (0x1849) - IRQ1 Mask 10 */
{ 0x0000184a, 0xffff }, /* R6218 (0x184A) - IRQ1 Mask 11 */
{ 0x0000184b, 0xffff }, /* R6219 (0x184B) - IRQ1 Mask 12 */
{ 0x0000184c, 0xffff }, /* R6220 (0x184C) - IRQ1 Mask 13 */
{ 0x0000184d, 0xffff }, /* R6221 (0x184D) - IRQ1 Mask 14 */
{ 0x0000184e, 0xffff }, /* R6222 (0x184E) - IRQ1 Mask 15 */
{ 0x0000184f, 0xffff }, /* R6223 (0x184F) - IRQ1 Mask 16 */
{ 0x00001850, 0xffff }, /* R6224 (0x1850) - IRQ1 Mask 17 */
{ 0x00001851, 0xffff }, /* R6225 (0x1851) - IRQ1 Mask 18 */
{ 0x00001852, 0xffff }, /* R6226 (0x1852) - IRQ1 Mask 19 */
{ 0x00001853, 0xffff }, /* R6227 (0x1853) - IRQ1 Mask 20 */
{ 0x00001854, 0xffff }, /* R6228 (0x1854) - IRQ1 Mask 21 */
{ 0x00001855, 0xffff }, /* R6229 (0x1855) - IRQ1 Mask 22 */
{ 0x00001856, 0xffff }, /* R6230 (0x1856) - IRQ1 Mask 23 */
{ 0x00001857, 0xffff }, /* R6231 (0x1857) - IRQ1 Mask 24 */
{ 0x00001858, 0xffff }, /* R6232 (0x1858) - IRQ1 Mask 25 */
{ 0x00001859, 0xffff }, /* R6233 (0x1859) - IRQ1 Mask 26 */
{ 0x0000185a, 0xffff }, /* R6234 (0x185A) - IRQ1 Mask 27 */
{ 0x0000185b, 0xffff }, /* R6235 (0x185B) - IRQ1 Mask 28 */
{ 0x0000185c, 0xffff }, /* R6236 (0x185C) - IRQ1 Mask 29 */
{ 0x0000185d, 0xffff }, /* R6237 (0x185D) - IRQ1 Mask 30 */
{ 0x0000185e, 0xffff }, /* R6238 (0x185E) - IRQ1 Mask 31 */
{ 0x0000185f, 0xffff }, /* R6239 (0x185F) - IRQ1 Mask 32 */
{ 0x00001860, 0xffff }, /* R6240 (0x1860) - IRQ1 Mask 33 */
{ 0x00001a06, 0x0000 }, /* R6662 (0x1A06) - Interrupt Debounce 7 */
{ 0x00001a80, 0x4400 }, /* R6784 (0x1A80) - IRQ1 Ctrl */
};
static bool cs47l15_is_adsp_memory(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x080000 ... 0x088ffe:
case 0x0a0000 ... 0x0a9ffe:
case 0x0c0000 ... 0x0c1ffe:
case 0x0e0000 ... 0x0e1ffe:
return true;
default:
return false;
}
}
static bool cs47l15_16bit_readable_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_SOFTWARE_RESET:
case MADERA_HARDWARE_REVISION:
case MADERA_WRITE_SEQUENCER_CTRL_0 ... MADERA_WRITE_SEQUENCER_CTRL_2:
case MADERA_TONE_GENERATOR_1 ... MADERA_TONE_GENERATOR_5:
case MADERA_PWM_DRIVE_1 ... MADERA_PWM_DRIVE_3:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_1:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_2:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_3:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_4:
case MADERA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1:
case MADERA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2:
case MADERA_HAPTICS_CONTROL_1 ... MADERA_HAPTICS_CONTROL_2:
case MADERA_HAPTICS_PHASE_1_INTENSITY:
case MADERA_HAPTICS_PHASE_1_DURATION:
case MADERA_HAPTICS_PHASE_2_INTENSITY:
case MADERA_HAPTICS_PHASE_2_DURATION:
case MADERA_HAPTICS_PHASE_3_INTENSITY:
case MADERA_HAPTICS_PHASE_3_DURATION:
case MADERA_HAPTICS_STATUS:
case MADERA_COMFORT_NOISE_GENERATOR:
case MADERA_CLOCK_32K_1:
case MADERA_SYSTEM_CLOCK_1:
case MADERA_SAMPLE_RATE_1 ... MADERA_SAMPLE_RATE_3:
case MADERA_SAMPLE_RATE_1_STATUS:
case MADERA_SAMPLE_RATE_2_STATUS:
case MADERA_SAMPLE_RATE_3_STATUS:
case MADERA_DSP_CLOCK_1:
case MADERA_DSP_CLOCK_2:
case MADERA_OUTPUT_SYSTEM_CLOCK:
case MADERA_RATE_ESTIMATOR_1 ... MADERA_RATE_ESTIMATOR_5:
case MADERA_FLL1_CONTROL_1 ... MADERA_FLL1_CONTROL_6:
case MADERA_FLL1_CONTROL_7:
case MADERA_FLL1_EFS_2:
case MADERA_FLL1_SYNCHRONISER_1 ... MADERA_FLL1_SYNCHRONISER_7:
case MADERA_FLL1_SPREAD_SPECTRUM:
case MADERA_FLL1_GPIO_CLOCK:
case MADERA_FLLAO_CONTROL_1:
case MADERA_FLLAO_CONTROL_2:
case MADERA_FLLAO_CONTROL_3:
case MADERA_FLLAO_CONTROL_4:
case MADERA_FLLAO_CONTROL_5:
case MADERA_FLLAO_CONTROL_6:
case MADERA_FLLAO_CONTROL_7:
case MADERA_FLLAO_CONTROL_8:
case MADERA_FLLAO_CONTROL_9:
case MADERA_FLLAO_CONTROL_10:
case MADERA_FLLAO_CONTROL_11:
case MADERA_MIC_BIAS_CTRL_1:
case MADERA_MIC_BIAS_CTRL_5:
case MADERA_HP_CTRL_1L:
case MADERA_HP_CTRL_1R:
case MADERA_ACCESSORY_DETECT_MODE_1:
case MADERA_HEADPHONE_DETECT_0:
case MADERA_HEADPHONE_DETECT_1:
case MADERA_HEADPHONE_DETECT_2:
case MADERA_HEADPHONE_DETECT_3:
case MADERA_HEADPHONE_DETECT_5:
case MADERA_MICD_CLAMP_CONTROL:
case MADERA_MIC_DETECT_1_CONTROL_0:
case MADERA_MIC_DETECT_1_CONTROL_1:
case MADERA_MIC_DETECT_1_CONTROL_2:
case MADERA_MIC_DETECT_1_CONTROL_3:
case MADERA_MIC_DETECT_1_LEVEL_1 ... MADERA_MIC_DETECT_1_LEVEL_4:
case MADERA_MIC_DETECT_1_CONTROL_4:
case MADERA_GP_SWITCH_1:
case MADERA_JACK_DETECT_ANALOGUE:
case MADERA_INPUT_ENABLES:
case MADERA_INPUT_ENABLES_STATUS:
case MADERA_INPUT_RATE:
case MADERA_INPUT_VOLUME_RAMP:
case MADERA_HPF_CONTROL:
case MADERA_IN1L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_1L:
case MADERA_DMIC1L_CONTROL:
case MADERA_IN1L_RATE_CONTROL:
case MADERA_IN1R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_1R:
case MADERA_DMIC1R_CONTROL:
case MADERA_IN1R_RATE_CONTROL:
case MADERA_IN2L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_2L:
case MADERA_DMIC2L_CONTROL:
case MADERA_IN2L_RATE_CONTROL:
case MADERA_IN2R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_2R:
case MADERA_DMIC2R_CONTROL:
case MADERA_IN2R_RATE_CONTROL:
case CS47L15_ADC_INT_BIAS:
case CS47L15_PGA_BIAS_SEL:
case MADERA_OUTPUT_ENABLES_1:
case MADERA_OUTPUT_STATUS_1:
case MADERA_RAW_OUTPUT_STATUS_1:
case MADERA_OUTPUT_RATE_1:
case MADERA_OUTPUT_VOLUME_RAMP:
case MADERA_OUTPUT_PATH_CONFIG_1L:
case MADERA_DAC_DIGITAL_VOLUME_1L:
case MADERA_OUTPUT_PATH_CONFIG_1:
case MADERA_NOISE_GATE_SELECT_1L:
case MADERA_OUTPUT_PATH_CONFIG_1R:
case MADERA_DAC_DIGITAL_VOLUME_1R:
case MADERA_NOISE_GATE_SELECT_1R:
case MADERA_OUTPUT_PATH_CONFIG_2:
case MADERA_OUTPUT_PATH_CONFIG_4L:
case MADERA_DAC_DIGITAL_VOLUME_4L:
case MADERA_NOISE_GATE_SELECT_4L:
case MADERA_OUTPUT_PATH_CONFIG_5L:
case MADERA_DAC_DIGITAL_VOLUME_5L:
case MADERA_NOISE_GATE_SELECT_5L:
case MADERA_OUTPUT_PATH_CONFIG_5R:
case MADERA_DAC_DIGITAL_VOLUME_5R:
case MADERA_NOISE_GATE_SELECT_5R:
case MADERA_DAC_AEC_CONTROL_1:
case MADERA_DAC_AEC_CONTROL_2:
case MADERA_NOISE_GATE_CONTROL:
case MADERA_PDM_SPK1_CTRL_1 ... MADERA_PDM_SPK1_CTRL_2:
case MADERA_HP1_SHORT_CIRCUIT_CTRL:
case MADERA_HP_TEST_CTRL_5:
case MADERA_HP_TEST_CTRL_6:
case MADERA_AIF1_BCLK_CTRL:
case MADERA_AIF1_TX_PIN_CTRL:
case MADERA_AIF1_RX_PIN_CTRL:
case MADERA_AIF1_RATE_CTRL:
case MADERA_AIF1_FORMAT:
case MADERA_AIF1_RX_BCLK_RATE:
case MADERA_AIF1_FRAME_CTRL_1 ... MADERA_AIF1_FRAME_CTRL_8:
case MADERA_AIF1_FRAME_CTRL_11 ... MADERA_AIF1_FRAME_CTRL_16:
case MADERA_AIF1_TX_ENABLES:
case MADERA_AIF1_RX_ENABLES:
case MADERA_AIF2_BCLK_CTRL:
case MADERA_AIF2_TX_PIN_CTRL:
case MADERA_AIF2_RX_PIN_CTRL:
case MADERA_AIF2_RATE_CTRL:
case MADERA_AIF2_FORMAT:
case MADERA_AIF2_RX_BCLK_RATE:
case MADERA_AIF2_FRAME_CTRL_1 ... MADERA_AIF2_FRAME_CTRL_6:
case MADERA_AIF2_FRAME_CTRL_11 ... MADERA_AIF2_FRAME_CTRL_14:
case MADERA_AIF2_TX_ENABLES:
case MADERA_AIF2_RX_ENABLES:
case MADERA_AIF3_BCLK_CTRL:
case MADERA_AIF3_TX_PIN_CTRL:
case MADERA_AIF3_RX_PIN_CTRL:
case MADERA_AIF3_RATE_CTRL:
case MADERA_AIF3_FORMAT:
case MADERA_AIF3_RX_BCLK_RATE:
case MADERA_AIF3_FRAME_CTRL_1 ... MADERA_AIF3_FRAME_CTRL_4:
case MADERA_AIF3_FRAME_CTRL_11 ... MADERA_AIF3_FRAME_CTRL_12:
case MADERA_AIF3_TX_ENABLES:
case MADERA_AIF3_RX_ENABLES:
case MADERA_SPD1_TX_CONTROL:
case MADERA_SPD1_TX_CHANNEL_STATUS_1:
case MADERA_SPD1_TX_CHANNEL_STATUS_2:
case MADERA_SPD1_TX_CHANNEL_STATUS_3:
case MADERA_PWM1MIX_INPUT_1_SOURCE:
case MADERA_PWM1MIX_INPUT_1_VOLUME:
case MADERA_PWM1MIX_INPUT_2_SOURCE:
case MADERA_PWM1MIX_INPUT_2_VOLUME:
case MADERA_PWM1MIX_INPUT_3_SOURCE:
case MADERA_PWM1MIX_INPUT_3_VOLUME:
case MADERA_PWM1MIX_INPUT_4_SOURCE:
case MADERA_PWM1MIX_INPUT_4_VOLUME:
case MADERA_PWM2MIX_INPUT_1_SOURCE:
case MADERA_PWM2MIX_INPUT_1_VOLUME:
case MADERA_PWM2MIX_INPUT_2_SOURCE:
case MADERA_PWM2MIX_INPUT_2_VOLUME:
case MADERA_PWM2MIX_INPUT_3_SOURCE:
case MADERA_PWM2MIX_INPUT_3_VOLUME:
case MADERA_PWM2MIX_INPUT_4_SOURCE:
case MADERA_PWM2MIX_INPUT_4_VOLUME:
case MADERA_OUT1LMIX_INPUT_1_SOURCE:
case MADERA_OUT1LMIX_INPUT_1_VOLUME:
case MADERA_OUT1LMIX_INPUT_2_SOURCE:
case MADERA_OUT1LMIX_INPUT_2_VOLUME:
case MADERA_OUT1LMIX_INPUT_3_SOURCE:
case MADERA_OUT1LMIX_INPUT_3_VOLUME:
case MADERA_OUT1LMIX_INPUT_4_SOURCE:
case MADERA_OUT1LMIX_INPUT_4_VOLUME:
case MADERA_OUT1RMIX_INPUT_1_SOURCE:
case MADERA_OUT1RMIX_INPUT_1_VOLUME:
case MADERA_OUT1RMIX_INPUT_2_SOURCE:
case MADERA_OUT1RMIX_INPUT_2_VOLUME:
case MADERA_OUT1RMIX_INPUT_3_SOURCE:
case MADERA_OUT1RMIX_INPUT_3_VOLUME:
case MADERA_OUT1RMIX_INPUT_4_SOURCE:
case MADERA_OUT1RMIX_INPUT_4_VOLUME:
case MADERA_OUT4LMIX_INPUT_1_SOURCE:
case MADERA_OUT4LMIX_INPUT_1_VOLUME:
case MADERA_OUT4LMIX_INPUT_2_SOURCE:
case MADERA_OUT4LMIX_INPUT_2_VOLUME:
case MADERA_OUT4LMIX_INPUT_3_SOURCE:
case MADERA_OUT4LMIX_INPUT_3_VOLUME:
case MADERA_OUT4LMIX_INPUT_4_SOURCE:
case MADERA_OUT4LMIX_INPUT_4_VOLUME:
case MADERA_OUT5LMIX_INPUT_1_SOURCE:
case MADERA_OUT5LMIX_INPUT_1_VOLUME:
case MADERA_OUT5LMIX_INPUT_2_SOURCE:
case MADERA_OUT5LMIX_INPUT_2_VOLUME:
case MADERA_OUT5LMIX_INPUT_3_SOURCE:
case MADERA_OUT5LMIX_INPUT_3_VOLUME:
case MADERA_OUT5LMIX_INPUT_4_SOURCE:
case MADERA_OUT5LMIX_INPUT_4_VOLUME:
case MADERA_OUT5RMIX_INPUT_1_SOURCE:
case MADERA_OUT5RMIX_INPUT_1_VOLUME:
case MADERA_OUT5RMIX_INPUT_2_SOURCE:
case MADERA_OUT5RMIX_INPUT_2_VOLUME:
case MADERA_OUT5RMIX_INPUT_3_SOURCE:
case MADERA_OUT5RMIX_INPUT_3_VOLUME:
case MADERA_OUT5RMIX_INPUT_4_SOURCE:
case MADERA_OUT5RMIX_INPUT_4_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_4_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_4_VOLUME:
case MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE:
case MADERA_SPDIF1TX1MIX_INPUT_1_VOLUME:
case MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE:
case MADERA_SPDIF1TX2MIX_INPUT_1_VOLUME:
case MADERA_EQ1MIX_INPUT_1_SOURCE:
case MADERA_EQ1MIX_INPUT_1_VOLUME:
case MADERA_EQ1MIX_INPUT_2_SOURCE:
case MADERA_EQ1MIX_INPUT_2_VOLUME:
case MADERA_EQ1MIX_INPUT_3_SOURCE:
case MADERA_EQ1MIX_INPUT_3_VOLUME:
case MADERA_EQ1MIX_INPUT_4_SOURCE:
case MADERA_EQ1MIX_INPUT_4_VOLUME:
case MADERA_EQ2MIX_INPUT_1_SOURCE:
case MADERA_EQ2MIX_INPUT_1_VOLUME:
case MADERA_EQ2MIX_INPUT_2_SOURCE:
case MADERA_EQ2MIX_INPUT_2_VOLUME:
case MADERA_EQ2MIX_INPUT_3_SOURCE:
case MADERA_EQ2MIX_INPUT_3_VOLUME:
case MADERA_EQ2MIX_INPUT_4_SOURCE:
case MADERA_EQ2MIX_INPUT_4_VOLUME:
case MADERA_EQ3MIX_INPUT_1_SOURCE:
case MADERA_EQ3MIX_INPUT_1_VOLUME:
case MADERA_EQ3MIX_INPUT_2_SOURCE:
case MADERA_EQ3MIX_INPUT_2_VOLUME:
case MADERA_EQ3MIX_INPUT_3_SOURCE:
case MADERA_EQ3MIX_INPUT_3_VOLUME:
case MADERA_EQ3MIX_INPUT_4_SOURCE:
case MADERA_EQ3MIX_INPUT_4_VOLUME:
case MADERA_EQ4MIX_INPUT_1_SOURCE:
case MADERA_EQ4MIX_INPUT_1_VOLUME:
case MADERA_EQ4MIX_INPUT_2_SOURCE:
case MADERA_EQ4MIX_INPUT_2_VOLUME:
case MADERA_EQ4MIX_INPUT_3_SOURCE:
case MADERA_EQ4MIX_INPUT_3_VOLUME:
case MADERA_EQ4MIX_INPUT_4_SOURCE:
case MADERA_EQ4MIX_INPUT_4_VOLUME:
case MADERA_DRC1LMIX_INPUT_1_SOURCE:
case MADERA_DRC1LMIX_INPUT_1_VOLUME:
case MADERA_DRC1LMIX_INPUT_2_SOURCE:
case MADERA_DRC1LMIX_INPUT_2_VOLUME:
case MADERA_DRC1LMIX_INPUT_3_SOURCE:
case MADERA_DRC1LMIX_INPUT_3_VOLUME:
case MADERA_DRC1LMIX_INPUT_4_SOURCE:
case MADERA_DRC1LMIX_INPUT_4_VOLUME:
case MADERA_DRC1RMIX_INPUT_1_SOURCE:
case MADERA_DRC1RMIX_INPUT_1_VOLUME:
case MADERA_DRC1RMIX_INPUT_2_SOURCE:
case MADERA_DRC1RMIX_INPUT_2_VOLUME:
case MADERA_DRC1RMIX_INPUT_3_SOURCE:
case MADERA_DRC1RMIX_INPUT_3_VOLUME:
case MADERA_DRC1RMIX_INPUT_4_SOURCE:
case MADERA_DRC1RMIX_INPUT_4_VOLUME:
case MADERA_DRC2LMIX_INPUT_1_SOURCE:
case MADERA_DRC2LMIX_INPUT_1_VOLUME:
case MADERA_DRC2LMIX_INPUT_2_SOURCE:
case MADERA_DRC2LMIX_INPUT_2_VOLUME:
case MADERA_DRC2LMIX_INPUT_3_SOURCE:
case MADERA_DRC2LMIX_INPUT_3_VOLUME:
case MADERA_DRC2LMIX_INPUT_4_SOURCE:
case MADERA_DRC2LMIX_INPUT_4_VOLUME:
case MADERA_DRC2RMIX_INPUT_1_SOURCE:
case MADERA_DRC2RMIX_INPUT_1_VOLUME:
case MADERA_DRC2RMIX_INPUT_2_SOURCE:
case MADERA_DRC2RMIX_INPUT_2_VOLUME:
case MADERA_DRC2RMIX_INPUT_3_SOURCE:
case MADERA_DRC2RMIX_INPUT_3_VOLUME:
case MADERA_DRC2RMIX_INPUT_4_SOURCE:
case MADERA_DRC2RMIX_INPUT_4_VOLUME:
case MADERA_HPLP1MIX_INPUT_1_SOURCE:
case MADERA_HPLP1MIX_INPUT_1_VOLUME:
case MADERA_HPLP1MIX_INPUT_2_SOURCE:
case MADERA_HPLP1MIX_INPUT_2_VOLUME:
case MADERA_HPLP1MIX_INPUT_3_SOURCE:
case MADERA_HPLP1MIX_INPUT_3_VOLUME:
case MADERA_HPLP1MIX_INPUT_4_SOURCE:
case MADERA_HPLP1MIX_INPUT_4_VOLUME:
case MADERA_HPLP2MIX_INPUT_1_SOURCE:
case MADERA_HPLP2MIX_INPUT_1_VOLUME:
case MADERA_HPLP2MIX_INPUT_2_SOURCE:
case MADERA_HPLP2MIX_INPUT_2_VOLUME:
case MADERA_HPLP2MIX_INPUT_3_SOURCE:
case MADERA_HPLP2MIX_INPUT_3_VOLUME:
case MADERA_HPLP2MIX_INPUT_4_SOURCE:
case MADERA_HPLP2MIX_INPUT_4_VOLUME:
case MADERA_HPLP3MIX_INPUT_1_SOURCE:
case MADERA_HPLP3MIX_INPUT_1_VOLUME:
case MADERA_HPLP3MIX_INPUT_2_SOURCE:
case MADERA_HPLP3MIX_INPUT_2_VOLUME:
case MADERA_HPLP3MIX_INPUT_3_SOURCE:
case MADERA_HPLP3MIX_INPUT_3_VOLUME:
case MADERA_HPLP3MIX_INPUT_4_SOURCE:
case MADERA_HPLP3MIX_INPUT_4_VOLUME:
case MADERA_HPLP4MIX_INPUT_1_SOURCE:
case MADERA_HPLP4MIX_INPUT_1_VOLUME:
case MADERA_HPLP4MIX_INPUT_2_SOURCE:
case MADERA_HPLP4MIX_INPUT_2_VOLUME:
case MADERA_HPLP4MIX_INPUT_3_SOURCE:
case MADERA_HPLP4MIX_INPUT_3_VOLUME:
case MADERA_HPLP4MIX_INPUT_4_SOURCE:
case MADERA_HPLP4MIX_INPUT_4_VOLUME:
case MADERA_DSP1LMIX_INPUT_1_SOURCE:
case MADERA_DSP1LMIX_INPUT_1_VOLUME:
case MADERA_DSP1LMIX_INPUT_2_SOURCE:
case MADERA_DSP1LMIX_INPUT_2_VOLUME:
case MADERA_DSP1LMIX_INPUT_3_SOURCE:
case MADERA_DSP1LMIX_INPUT_3_VOLUME:
case MADERA_DSP1LMIX_INPUT_4_SOURCE:
case MADERA_DSP1LMIX_INPUT_4_VOLUME:
case MADERA_DSP1RMIX_INPUT_1_SOURCE:
case MADERA_DSP1RMIX_INPUT_1_VOLUME:
case MADERA_DSP1RMIX_INPUT_2_SOURCE:
case MADERA_DSP1RMIX_INPUT_2_VOLUME:
case MADERA_DSP1RMIX_INPUT_3_SOURCE:
case MADERA_DSP1RMIX_INPUT_3_VOLUME:
case MADERA_DSP1RMIX_INPUT_4_SOURCE:
case MADERA_DSP1RMIX_INPUT_4_VOLUME:
case MADERA_DSP1AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX6MIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC3MIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC4MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT1MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT2MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT3MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT4MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC3MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC4MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT1MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT2MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT3MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT4MIX_INPUT_1_SOURCE:
case MADERA_FX_CTRL1 ... MADERA_FX_CTRL2:
case MADERA_EQ1_1 ... MADERA_EQ1_21:
case MADERA_EQ2_1 ... MADERA_EQ2_21:
case MADERA_EQ3_1 ... MADERA_EQ3_21:
case MADERA_EQ4_1 ... MADERA_EQ4_21:
case MADERA_DRC1_CTRL1 ... MADERA_DRC1_CTRL5:
case MADERA_DRC2_CTRL1 ... MADERA_DRC2_CTRL5:
case MADERA_HPLPF1_1 ... MADERA_HPLPF1_2:
case MADERA_HPLPF2_1 ... MADERA_HPLPF2_2:
case MADERA_HPLPF3_1 ... MADERA_HPLPF3_2:
case MADERA_HPLPF4_1 ... MADERA_HPLPF4_2:
case MADERA_ISRC_1_CTRL_1 ... MADERA_ISRC_1_CTRL_3:
case MADERA_ISRC_2_CTRL_1 ... MADERA_ISRC_2_CTRL_3:
case MADERA_GPIO1_CTRL_1 ... MADERA_GPIO15_CTRL_2:
case MADERA_IRQ1_STATUS_1 ... MADERA_IRQ1_STATUS_33:
case MADERA_IRQ1_MASK_1 ... MADERA_IRQ1_MASK_33:
case MADERA_IRQ1_RAW_STATUS_1 ... MADERA_IRQ1_RAW_STATUS_33:
case MADERA_INTERRUPT_DEBOUNCE_7:
case MADERA_IRQ1_CTRL:
return true;
default:
return false;
}
}
static bool cs47l15_16bit_volatile_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_SOFTWARE_RESET:
case MADERA_HARDWARE_REVISION:
case MADERA_WRITE_SEQUENCER_CTRL_0 ... MADERA_WRITE_SEQUENCER_CTRL_2:
case MADERA_HAPTICS_STATUS:
case MADERA_SAMPLE_RATE_1_STATUS:
case MADERA_SAMPLE_RATE_2_STATUS:
case MADERA_SAMPLE_RATE_3_STATUS:
case MADERA_HP_CTRL_1L:
case MADERA_HP_CTRL_1R:
case MADERA_MIC_DETECT_1_CONTROL_3:
case MADERA_MIC_DETECT_1_CONTROL_4:
case MADERA_HEADPHONE_DETECT_2:
case MADERA_HEADPHONE_DETECT_3:
case MADERA_HEADPHONE_DETECT_5:
case MADERA_INPUT_ENABLES_STATUS:
case MADERA_OUTPUT_STATUS_1:
case MADERA_RAW_OUTPUT_STATUS_1:
case MADERA_SPD1_TX_CHANNEL_STATUS_1:
case MADERA_SPD1_TX_CHANNEL_STATUS_2:
case MADERA_SPD1_TX_CHANNEL_STATUS_3:
case MADERA_FX_CTRL2:
case MADERA_IRQ1_STATUS_1 ... MADERA_IRQ1_STATUS_33:
case MADERA_IRQ1_RAW_STATUS_1 ... MADERA_IRQ1_RAW_STATUS_33:
return true;
default:
return false;
}
}
static bool cs47l15_32bit_readable_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_WSEQ_SEQUENCE_1 ... MADERA_WSEQ_SEQUENCE_225:
case MADERA_OTP_HPDET_CAL_1 ... MADERA_OTP_HPDET_CAL_2:
case MADERA_DSP1_CONFIG_1 ... MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
return true;
default:
return cs47l15_is_adsp_memory(dev, reg);
}
}
static bool cs47l15_32bit_volatile_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_WSEQ_SEQUENCE_1 ... MADERA_WSEQ_SEQUENCE_225:
case MADERA_OTP_HPDET_CAL_1 ... MADERA_OTP_HPDET_CAL_2:
case MADERA_DSP1_CONFIG_1 ... MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
return true;
default:
return cs47l15_is_adsp_memory(dev, reg);
}
}
const struct regmap_config cs47l15_16bit_spi_regmap = {
.name = "cs47l15_16bit",
.reg_bits = 32,
.pad_bits = 16,
.val_bits = 16,
.max_register = MADERA_INTERRUPT_RAW_STATUS_1,
.readable_reg = &cs47l15_16bit_readable_register,
.volatile_reg = &cs47l15_16bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = cs47l15_reg_default,
.num_reg_defaults = ARRAY_SIZE(cs47l15_reg_default),
};
EXPORT_SYMBOL_GPL(cs47l15_16bit_spi_regmap);
const struct regmap_config cs47l15_16bit_i2c_regmap = {
.name = "cs47l15_16bit",
.reg_bits = 32,
.val_bits = 16,
.max_register = MADERA_INTERRUPT_RAW_STATUS_1,
.readable_reg = &cs47l15_16bit_readable_register,
.volatile_reg = &cs47l15_16bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = cs47l15_reg_default,
.num_reg_defaults = ARRAY_SIZE(cs47l15_reg_default),
};
EXPORT_SYMBOL_GPL(cs47l15_16bit_i2c_regmap);
const struct regmap_config cs47l15_32bit_spi_regmap = {
.name = "cs47l15_32bit",
.reg_bits = 32,
.reg_stride = 2,
.pad_bits = 16,
.val_bits = 32,
.max_register = MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR,
.readable_reg = &cs47l15_32bit_readable_register,
.volatile_reg = &cs47l15_32bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(cs47l15_32bit_spi_regmap);
const struct regmap_config cs47l15_32bit_i2c_regmap = {
.name = "cs47l15_32bit",
.reg_bits = 32,
.reg_stride = 2,
.val_bits = 32,
.max_register = MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR,
.readable_reg = &cs47l15_32bit_readable_register,
.volatile_reg = &cs47l15_32bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(cs47l15_32bit_i2c_regmap);
| linux-master | drivers/mfd/cs47l15-tables.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8994-irq.c -- Interrupt controller support for Wolfson WM8994
*
* Copyright 2010 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/regmap.h>
#include <linux/mfd/wm8994/core.h>
#include <linux/mfd/wm8994/pdata.h>
#include <linux/mfd/wm8994/registers.h>
#include <linux/delay.h>
static const struct regmap_irq wm8994_irqs[] = {
[WM8994_IRQ_TEMP_SHUT] = {
.reg_offset = 1,
.mask = WM8994_TEMP_SHUT_EINT,
},
[WM8994_IRQ_MIC1_DET] = {
.reg_offset = 1,
.mask = WM8994_MIC1_DET_EINT,
},
[WM8994_IRQ_MIC1_SHRT] = {
.reg_offset = 1,
.mask = WM8994_MIC1_SHRT_EINT,
},
[WM8994_IRQ_MIC2_DET] = {
.reg_offset = 1,
.mask = WM8994_MIC2_DET_EINT,
},
[WM8994_IRQ_MIC2_SHRT] = {
.reg_offset = 1,
.mask = WM8994_MIC2_SHRT_EINT,
},
[WM8994_IRQ_FLL1_LOCK] = {
.reg_offset = 1,
.mask = WM8994_FLL1_LOCK_EINT,
},
[WM8994_IRQ_FLL2_LOCK] = {
.reg_offset = 1,
.mask = WM8994_FLL2_LOCK_EINT,
},
[WM8994_IRQ_SRC1_LOCK] = {
.reg_offset = 1,
.mask = WM8994_SRC1_LOCK_EINT,
},
[WM8994_IRQ_SRC2_LOCK] = {
.reg_offset = 1,
.mask = WM8994_SRC2_LOCK_EINT,
},
[WM8994_IRQ_AIF1DRC1_SIG_DET] = {
.reg_offset = 1,
.mask = WM8994_AIF1DRC1_SIG_DET,
},
[WM8994_IRQ_AIF1DRC2_SIG_DET] = {
.reg_offset = 1,
.mask = WM8994_AIF1DRC2_SIG_DET_EINT,
},
[WM8994_IRQ_AIF2DRC_SIG_DET] = {
.reg_offset = 1,
.mask = WM8994_AIF2DRC_SIG_DET_EINT,
},
[WM8994_IRQ_FIFOS_ERR] = {
.reg_offset = 1,
.mask = WM8994_FIFOS_ERR_EINT,
},
[WM8994_IRQ_WSEQ_DONE] = {
.reg_offset = 1,
.mask = WM8994_WSEQ_DONE_EINT,
},
[WM8994_IRQ_DCS_DONE] = {
.reg_offset = 1,
.mask = WM8994_DCS_DONE_EINT,
},
[WM8994_IRQ_TEMP_WARN] = {
.reg_offset = 1,
.mask = WM8994_TEMP_WARN_EINT,
},
[WM8994_IRQ_GPIO(1)] = {
.mask = WM8994_GP1_EINT,
},
[WM8994_IRQ_GPIO(2)] = {
.mask = WM8994_GP2_EINT,
},
[WM8994_IRQ_GPIO(3)] = {
.mask = WM8994_GP3_EINT,
},
[WM8994_IRQ_GPIO(4)] = {
.mask = WM8994_GP4_EINT,
},
[WM8994_IRQ_GPIO(5)] = {
.mask = WM8994_GP5_EINT,
},
[WM8994_IRQ_GPIO(6)] = {
.mask = WM8994_GP6_EINT,
},
[WM8994_IRQ_GPIO(7)] = {
.mask = WM8994_GP7_EINT,
},
[WM8994_IRQ_GPIO(8)] = {
.mask = WM8994_GP8_EINT,
},
[WM8994_IRQ_GPIO(9)] = {
.mask = WM8994_GP8_EINT,
},
[WM8994_IRQ_GPIO(10)] = {
.mask = WM8994_GP10_EINT,
},
[WM8994_IRQ_GPIO(11)] = {
.mask = WM8994_GP11_EINT,
},
};
static const struct regmap_irq_chip wm8994_irq_chip = {
.name = "wm8994",
.irqs = wm8994_irqs,
.num_irqs = ARRAY_SIZE(wm8994_irqs),
.num_regs = 2,
.status_base = WM8994_INTERRUPT_STATUS_1,
.mask_base = WM8994_INTERRUPT_STATUS_1_MASK,
.ack_base = WM8994_INTERRUPT_STATUS_1,
.runtime_pm = true,
};
static void wm8994_edge_irq_enable(struct irq_data *data)
{
}
static void wm8994_edge_irq_disable(struct irq_data *data)
{
}
static struct irq_chip wm8994_edge_irq_chip = {
.name = "wm8994_edge",
.irq_disable = wm8994_edge_irq_disable,
.irq_enable = wm8994_edge_irq_enable,
};
static irqreturn_t wm8994_edge_irq(int irq, void *data)
{
struct wm8994 *wm8994 = data;
while (gpio_get_value_cansleep(wm8994->pdata.irq_gpio))
handle_nested_irq(irq_find_mapping(wm8994->edge_irq, 0));
return IRQ_HANDLED;
}
static int wm8994_edge_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct wm8994 *wm8994 = h->host_data;
irq_set_chip_data(virq, wm8994);
irq_set_chip_and_handler(virq, &wm8994_edge_irq_chip, handle_edge_irq);
irq_set_nested_thread(virq, 1);
irq_set_noprobe(virq);
return 0;
}
static const struct irq_domain_ops wm8994_edge_irq_ops = {
.map = wm8994_edge_irq_map,
.xlate = irq_domain_xlate_twocell,
};
int wm8994_irq_init(struct wm8994 *wm8994)
{
int ret;
unsigned long irqflags;
struct wm8994_pdata *pdata = &wm8994->pdata;
if (!wm8994->irq) {
dev_warn(wm8994->dev,
"No interrupt specified, no interrupts\n");
wm8994->irq_base = 0;
return 0;
}
/* select user or default irq flags */
irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT;
if (pdata->irq_flags)
irqflags = pdata->irq_flags;
/* use a GPIO for edge triggered controllers */
if (irqflags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
if (gpio_to_irq(pdata->irq_gpio) != wm8994->irq) {
dev_warn(wm8994->dev, "IRQ %d is not GPIO %d (%d)\n",
wm8994->irq, pdata->irq_gpio,
gpio_to_irq(pdata->irq_gpio));
wm8994->irq = gpio_to_irq(pdata->irq_gpio);
}
ret = devm_gpio_request_one(wm8994->dev, pdata->irq_gpio,
GPIOF_IN, "WM8994 IRQ");
if (ret != 0) {
dev_err(wm8994->dev, "Failed to get IRQ GPIO: %d\n",
ret);
return ret;
}
wm8994->edge_irq = irq_domain_add_linear(NULL, 1,
&wm8994_edge_irq_ops,
wm8994);
ret = regmap_add_irq_chip(wm8994->regmap,
irq_create_mapping(wm8994->edge_irq,
0),
IRQF_ONESHOT,
wm8994->irq_base, &wm8994_irq_chip,
&wm8994->irq_data);
if (ret != 0) {
dev_err(wm8994->dev, "Failed to get IRQ: %d\n",
ret);
return ret;
}
ret = request_threaded_irq(wm8994->irq,
NULL, wm8994_edge_irq,
irqflags,
"WM8994 edge", wm8994);
} else {
ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq,
irqflags,
wm8994->irq_base, &wm8994_irq_chip,
&wm8994->irq_data);
}
if (ret != 0) {
dev_err(wm8994->dev, "Failed to register IRQ chip: %d\n", ret);
return ret;
}
/* Enable top level interrupt if it was masked */
wm8994_reg_write(wm8994, WM8994_INTERRUPT_CONTROL, 0);
return 0;
}
EXPORT_SYMBOL(wm8994_irq_init);
void wm8994_irq_exit(struct wm8994 *wm8994)
{
regmap_del_irq_chip(wm8994->irq, wm8994->irq_data);
}
EXPORT_SYMBOL(wm8994_irq_exit);
| linux-master | drivers/mfd/wm8994-irq.c |
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