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// SPDX-License-Identifier: GPL-2.0-only
/*
* ST Microelectronics MFD: stmpe's driver
*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Rabin Vincent <[email protected]> for ST-Ericsson
*/
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/pm.h>
#include <linux/slab.h>
#include <linux/mfd/core.h>
#include <linux/delay.h>
#include <linux/regulator/consumer.h>
#include "stmpe.h"
/**
* struct stmpe_platform_data - STMPE platform data
* @id: device id to distinguish between multiple STMPEs on the same board
* @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
* @irq_trigger: IRQ trigger to use for the interrupt to the host
* @autosleep: bool to enable/disable stmpe autosleep
* @autosleep_timeout: inactivity timeout in milliseconds for autosleep
*/
struct stmpe_platform_data {
int id;
unsigned int blocks;
unsigned int irq_trigger;
bool autosleep;
int autosleep_timeout;
};
static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
{
return stmpe->variant->enable(stmpe, blocks, true);
}
static int __stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
{
return stmpe->variant->enable(stmpe, blocks, false);
}
static int __stmpe_reg_read(struct stmpe *stmpe, u8 reg)
{
int ret;
ret = stmpe->ci->read_byte(stmpe, reg);
if (ret < 0)
dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret);
dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret);
return ret;
}
static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
{
int ret;
dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val);
ret = stmpe->ci->write_byte(stmpe, reg, val);
if (ret < 0)
dev_err(stmpe->dev, "failed to write reg %#x: %d\n", reg, ret);
return ret;
}
static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
{
int ret;
ret = __stmpe_reg_read(stmpe, reg);
if (ret < 0)
return ret;
ret &= ~mask;
ret |= val;
return __stmpe_reg_write(stmpe, reg, ret);
}
static int __stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length,
u8 *values)
{
int ret;
ret = stmpe->ci->read_block(stmpe, reg, length, values);
if (ret < 0)
dev_err(stmpe->dev, "failed to read regs %#x: %d\n", reg, ret);
dev_vdbg(stmpe->dev, "rd: reg %#x (%d) => ret %#x\n", reg, length, ret);
stmpe_dump_bytes("stmpe rd: ", values, length);
return ret;
}
static int __stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
const u8 *values)
{
int ret;
dev_vdbg(stmpe->dev, "wr: regs %#x (%d)\n", reg, length);
stmpe_dump_bytes("stmpe wr: ", values, length);
ret = stmpe->ci->write_block(stmpe, reg, length, values);
if (ret < 0)
dev_err(stmpe->dev, "failed to write regs %#x: %d\n", reg, ret);
return ret;
}
/**
* stmpe_enable - enable blocks on an STMPE device
* @stmpe: Device to work on
* @blocks: Mask of blocks (enum stmpe_block values) to enable
*/
int stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
{
int ret;
mutex_lock(&stmpe->lock);
ret = __stmpe_enable(stmpe, blocks);
mutex_unlock(&stmpe->lock);
return ret;
}
EXPORT_SYMBOL_GPL(stmpe_enable);
/**
* stmpe_disable - disable blocks on an STMPE device
* @stmpe: Device to work on
* @blocks: Mask of blocks (enum stmpe_block values) to enable
*/
int stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
{
int ret;
mutex_lock(&stmpe->lock);
ret = __stmpe_disable(stmpe, blocks);
mutex_unlock(&stmpe->lock);
return ret;
}
EXPORT_SYMBOL_GPL(stmpe_disable);
/**
* stmpe_reg_read() - read a single STMPE register
* @stmpe: Device to read from
* @reg: Register to read
*/
int stmpe_reg_read(struct stmpe *stmpe, u8 reg)
{
int ret;
mutex_lock(&stmpe->lock);
ret = __stmpe_reg_read(stmpe, reg);
mutex_unlock(&stmpe->lock);
return ret;
}
EXPORT_SYMBOL_GPL(stmpe_reg_read);
/**
* stmpe_reg_write() - write a single STMPE register
* @stmpe: Device to write to
* @reg: Register to write
* @val: Value to write
*/
int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
{
int ret;
mutex_lock(&stmpe->lock);
ret = __stmpe_reg_write(stmpe, reg, val);
mutex_unlock(&stmpe->lock);
return ret;
}
EXPORT_SYMBOL_GPL(stmpe_reg_write);
/**
* stmpe_set_bits() - set the value of a bitfield in a STMPE register
* @stmpe: Device to write to
* @reg: Register to write
* @mask: Mask of bits to set
* @val: Value to set
*/
int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
{
int ret;
mutex_lock(&stmpe->lock);
ret = __stmpe_set_bits(stmpe, reg, mask, val);
mutex_unlock(&stmpe->lock);
return ret;
}
EXPORT_SYMBOL_GPL(stmpe_set_bits);
/**
* stmpe_block_read() - read multiple STMPE registers
* @stmpe: Device to read from
* @reg: First register
* @length: Number of registers
* @values: Buffer to write to
*/
int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values)
{
int ret;
mutex_lock(&stmpe->lock);
ret = __stmpe_block_read(stmpe, reg, length, values);
mutex_unlock(&stmpe->lock);
return ret;
}
EXPORT_SYMBOL_GPL(stmpe_block_read);
/**
* stmpe_block_write() - write multiple STMPE registers
* @stmpe: Device to write to
* @reg: First register
* @length: Number of registers
* @values: Values to write
*/
int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
const u8 *values)
{
int ret;
mutex_lock(&stmpe->lock);
ret = __stmpe_block_write(stmpe, reg, length, values);
mutex_unlock(&stmpe->lock);
return ret;
}
EXPORT_SYMBOL_GPL(stmpe_block_write);
/**
* stmpe_set_altfunc()- set the alternate function for STMPE pins
* @stmpe: Device to configure
* @pins: Bitmask of pins to affect
* @block: block to enable alternate functions for
*
* @pins is assumed to have a bit set for each of the bits whose alternate
* function is to be changed, numbered according to the GPIOXY numbers.
*
* If the GPIO module is not enabled, this function automatically enables it in
* order to perform the change.
*/
int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, enum stmpe_block block)
{
struct stmpe_variant_info *variant = stmpe->variant;
u8 regaddr = stmpe->regs[STMPE_IDX_GPAFR_U_MSB];
int af_bits = variant->af_bits;
int numregs = DIV_ROUND_UP(stmpe->num_gpios * af_bits, 8);
int mask = (1 << af_bits) - 1;
u8 regs[8];
int af, afperreg, ret;
if (!variant->get_altfunc)
return 0;
afperreg = 8 / af_bits;
mutex_lock(&stmpe->lock);
ret = __stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
if (ret < 0)
goto out;
ret = __stmpe_block_read(stmpe, regaddr, numregs, regs);
if (ret < 0)
goto out;
af = variant->get_altfunc(stmpe, block);
while (pins) {
int pin = __ffs(pins);
int regoffset = numregs - (pin / afperreg) - 1;
int pos = (pin % afperreg) * (8 / afperreg);
regs[regoffset] &= ~(mask << pos);
regs[regoffset] |= af << pos;
pins &= ~(1 << pin);
}
ret = __stmpe_block_write(stmpe, regaddr, numregs, regs);
out:
mutex_unlock(&stmpe->lock);
return ret;
}
EXPORT_SYMBOL_GPL(stmpe_set_altfunc);
/*
* GPIO (all variants)
*/
static struct resource stmpe_gpio_resources[] = {
/* Start and end filled dynamically */
{
.flags = IORESOURCE_IRQ,
},
};
static const struct mfd_cell stmpe_gpio_cell = {
.name = "stmpe-gpio",
.of_compatible = "st,stmpe-gpio",
.resources = stmpe_gpio_resources,
.num_resources = ARRAY_SIZE(stmpe_gpio_resources),
};
static const struct mfd_cell stmpe_gpio_cell_noirq = {
.name = "stmpe-gpio",
.of_compatible = "st,stmpe-gpio",
/* gpio cell resources consist of an irq only so no resources here */
};
/*
* Keypad (1601, 2401, 2403)
*/
static struct resource stmpe_keypad_resources[] = {
/* Start and end filled dynamically */
{
.name = "KEYPAD",
.flags = IORESOURCE_IRQ,
},
{
.name = "KEYPAD_OVER",
.flags = IORESOURCE_IRQ,
},
};
static const struct mfd_cell stmpe_keypad_cell = {
.name = "stmpe-keypad",
.of_compatible = "st,stmpe-keypad",
.resources = stmpe_keypad_resources,
.num_resources = ARRAY_SIZE(stmpe_keypad_resources),
};
/*
* PWM (1601, 2401, 2403)
*/
static struct resource stmpe_pwm_resources[] = {
/* Start and end filled dynamically */
{
.name = "PWM0",
.flags = IORESOURCE_IRQ,
},
{
.name = "PWM1",
.flags = IORESOURCE_IRQ,
},
{
.name = "PWM2",
.flags = IORESOURCE_IRQ,
},
};
static const struct mfd_cell stmpe_pwm_cell = {
.name = "stmpe-pwm",
.of_compatible = "st,stmpe-pwm",
.resources = stmpe_pwm_resources,
.num_resources = ARRAY_SIZE(stmpe_pwm_resources),
};
/*
* STMPE801
*/
static const u8 stmpe801_regs[] = {
[STMPE_IDX_CHIP_ID] = STMPE801_REG_CHIP_ID,
[STMPE_IDX_ICR_LSB] = STMPE801_REG_SYS_CTRL,
[STMPE_IDX_GPMR_LSB] = STMPE801_REG_GPIO_MP_STA,
[STMPE_IDX_GPSR_LSB] = STMPE801_REG_GPIO_SET_PIN,
[STMPE_IDX_GPCR_LSB] = STMPE801_REG_GPIO_SET_PIN,
[STMPE_IDX_GPDR_LSB] = STMPE801_REG_GPIO_DIR,
[STMPE_IDX_IEGPIOR_LSB] = STMPE801_REG_GPIO_INT_EN,
[STMPE_IDX_ISGPIOR_MSB] = STMPE801_REG_GPIO_INT_STA,
};
static struct stmpe_variant_block stmpe801_blocks[] = {
{
.cell = &stmpe_gpio_cell,
.irq = 0,
.block = STMPE_BLOCK_GPIO,
},
};
static struct stmpe_variant_block stmpe801_blocks_noirq[] = {
{
.cell = &stmpe_gpio_cell_noirq,
.block = STMPE_BLOCK_GPIO,
},
};
static int stmpe801_enable(struct stmpe *stmpe, unsigned int blocks,
bool enable)
{
if (blocks & STMPE_BLOCK_GPIO)
return 0;
else
return -EINVAL;
}
static struct stmpe_variant_info stmpe801 = {
.name = "stmpe801",
.id_val = STMPE801_ID,
.id_mask = 0xffff,
.num_gpios = 8,
.regs = stmpe801_regs,
.blocks = stmpe801_blocks,
.num_blocks = ARRAY_SIZE(stmpe801_blocks),
.num_irqs = STMPE801_NR_INTERNAL_IRQS,
.enable = stmpe801_enable,
};
static struct stmpe_variant_info stmpe801_noirq = {
.name = "stmpe801",
.id_val = STMPE801_ID,
.id_mask = 0xffff,
.num_gpios = 8,
.regs = stmpe801_regs,
.blocks = stmpe801_blocks_noirq,
.num_blocks = ARRAY_SIZE(stmpe801_blocks_noirq),
.enable = stmpe801_enable,
};
/*
* Touchscreen (STMPE811 or STMPE610)
*/
static struct resource stmpe_ts_resources[] = {
/* Start and end filled dynamically */
{
.name = "TOUCH_DET",
.flags = IORESOURCE_IRQ,
},
{
.name = "FIFO_TH",
.flags = IORESOURCE_IRQ,
},
};
static const struct mfd_cell stmpe_ts_cell = {
.name = "stmpe-ts",
.of_compatible = "st,stmpe-ts",
.resources = stmpe_ts_resources,
.num_resources = ARRAY_SIZE(stmpe_ts_resources),
};
/*
* ADC (STMPE811)
*/
static struct resource stmpe_adc_resources[] = {
/* Start and end filled dynamically */
{
.name = "STMPE_TEMP_SENS",
.flags = IORESOURCE_IRQ,
},
{
.name = "STMPE_ADC",
.flags = IORESOURCE_IRQ,
},
};
static const struct mfd_cell stmpe_adc_cell = {
.name = "stmpe-adc",
.of_compatible = "st,stmpe-adc",
.resources = stmpe_adc_resources,
.num_resources = ARRAY_SIZE(stmpe_adc_resources),
};
/*
* STMPE811 or STMPE610
*/
static const u8 stmpe811_regs[] = {
[STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID,
[STMPE_IDX_SYS_CTRL] = STMPE811_REG_SYS_CTRL,
[STMPE_IDX_SYS_CTRL2] = STMPE811_REG_SYS_CTRL2,
[STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL,
[STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN,
[STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA,
[STMPE_IDX_GPMR_LSB] = STMPE811_REG_GPIO_MP_STA,
[STMPE_IDX_GPSR_LSB] = STMPE811_REG_GPIO_SET_PIN,
[STMPE_IDX_GPCR_LSB] = STMPE811_REG_GPIO_CLR_PIN,
[STMPE_IDX_GPDR_LSB] = STMPE811_REG_GPIO_DIR,
[STMPE_IDX_GPRER_LSB] = STMPE811_REG_GPIO_RE,
[STMPE_IDX_GPFER_LSB] = STMPE811_REG_GPIO_FE,
[STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF,
[STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN,
[STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA,
[STMPE_IDX_GPEDR_LSB] = STMPE811_REG_GPIO_ED,
};
static struct stmpe_variant_block stmpe811_blocks[] = {
{
.cell = &stmpe_gpio_cell,
.irq = STMPE811_IRQ_GPIOC,
.block = STMPE_BLOCK_GPIO,
},
{
.cell = &stmpe_ts_cell,
.irq = STMPE811_IRQ_TOUCH_DET,
.block = STMPE_BLOCK_TOUCHSCREEN,
},
{
.cell = &stmpe_adc_cell,
.irq = STMPE811_IRQ_TEMP_SENS,
.block = STMPE_BLOCK_ADC,
},
};
static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks,
bool enable)
{
unsigned int mask = 0;
if (blocks & STMPE_BLOCK_GPIO)
mask |= STMPE811_SYS_CTRL2_GPIO_OFF;
if (blocks & STMPE_BLOCK_ADC)
mask |= STMPE811_SYS_CTRL2_ADC_OFF;
if (blocks & STMPE_BLOCK_TOUCHSCREEN)
mask |= STMPE811_SYS_CTRL2_TSC_OFF;
return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask,
enable ? 0 : mask);
}
int stmpe811_adc_common_init(struct stmpe *stmpe)
{
int ret;
u8 adc_ctrl1, adc_ctrl1_mask;
adc_ctrl1 = STMPE_SAMPLE_TIME(stmpe->sample_time) |
STMPE_MOD_12B(stmpe->mod_12b) |
STMPE_REF_SEL(stmpe->ref_sel);
adc_ctrl1_mask = STMPE_SAMPLE_TIME(0xff) | STMPE_MOD_12B(0xff) |
STMPE_REF_SEL(0xff);
ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL1,
adc_ctrl1_mask, adc_ctrl1);
if (ret) {
dev_err(stmpe->dev, "Could not setup ADC\n");
return ret;
}
ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL2,
STMPE_ADC_FREQ(0xff), STMPE_ADC_FREQ(stmpe->adc_freq));
if (ret) {
dev_err(stmpe->dev, "Could not setup ADC\n");
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(stmpe811_adc_common_init);
static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
{
/* 0 for touchscreen, 1 for GPIO */
return block != STMPE_BLOCK_TOUCHSCREEN;
}
static struct stmpe_variant_info stmpe811 = {
.name = "stmpe811",
.id_val = 0x0811,
.id_mask = 0xffff,
.num_gpios = 8,
.af_bits = 1,
.regs = stmpe811_regs,
.blocks = stmpe811_blocks,
.num_blocks = ARRAY_SIZE(stmpe811_blocks),
.num_irqs = STMPE811_NR_INTERNAL_IRQS,
.enable = stmpe811_enable,
.get_altfunc = stmpe811_get_altfunc,
};
/* Similar to 811, except number of gpios */
static struct stmpe_variant_info stmpe610 = {
.name = "stmpe610",
.id_val = 0x0811,
.id_mask = 0xffff,
.num_gpios = 6,
.af_bits = 1,
.regs = stmpe811_regs,
.blocks = stmpe811_blocks,
.num_blocks = ARRAY_SIZE(stmpe811_blocks),
.num_irqs = STMPE811_NR_INTERNAL_IRQS,
.enable = stmpe811_enable,
.get_altfunc = stmpe811_get_altfunc,
};
/*
* STMPE1600
* Compared to all others STMPE variant, LSB and MSB regs are located in this
* order : LSB addr
* MSB addr + 1
* As there is only 2 * 8bits registers for GPMR/GPSR/IEGPIOPR, CSB index is MSB registers
*/
static const u8 stmpe1600_regs[] = {
[STMPE_IDX_CHIP_ID] = STMPE1600_REG_CHIP_ID,
[STMPE_IDX_SYS_CTRL] = STMPE1600_REG_SYS_CTRL,
[STMPE_IDX_ICR_LSB] = STMPE1600_REG_SYS_CTRL,
[STMPE_IDX_GPMR_LSB] = STMPE1600_REG_GPMR_LSB,
[STMPE_IDX_GPMR_CSB] = STMPE1600_REG_GPMR_MSB,
[STMPE_IDX_GPSR_LSB] = STMPE1600_REG_GPSR_LSB,
[STMPE_IDX_GPSR_CSB] = STMPE1600_REG_GPSR_MSB,
[STMPE_IDX_GPCR_LSB] = STMPE1600_REG_GPSR_LSB,
[STMPE_IDX_GPCR_CSB] = STMPE1600_REG_GPSR_MSB,
[STMPE_IDX_GPDR_LSB] = STMPE1600_REG_GPDR_LSB,
[STMPE_IDX_GPDR_CSB] = STMPE1600_REG_GPDR_MSB,
[STMPE_IDX_IEGPIOR_LSB] = STMPE1600_REG_IEGPIOR_LSB,
[STMPE_IDX_IEGPIOR_CSB] = STMPE1600_REG_IEGPIOR_MSB,
[STMPE_IDX_ISGPIOR_LSB] = STMPE1600_REG_ISGPIOR_LSB,
};
static struct stmpe_variant_block stmpe1600_blocks[] = {
{
.cell = &stmpe_gpio_cell,
.irq = 0,
.block = STMPE_BLOCK_GPIO,
},
};
static int stmpe1600_enable(struct stmpe *stmpe, unsigned int blocks,
bool enable)
{
if (blocks & STMPE_BLOCK_GPIO)
return 0;
else
return -EINVAL;
}
static struct stmpe_variant_info stmpe1600 = {
.name = "stmpe1600",
.id_val = STMPE1600_ID,
.id_mask = 0xffff,
.num_gpios = 16,
.af_bits = 0,
.regs = stmpe1600_regs,
.blocks = stmpe1600_blocks,
.num_blocks = ARRAY_SIZE(stmpe1600_blocks),
.num_irqs = STMPE1600_NR_INTERNAL_IRQS,
.enable = stmpe1600_enable,
};
/*
* STMPE1601
*/
static const u8 stmpe1601_regs[] = {
[STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID,
[STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL,
[STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2,
[STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB,
[STMPE_IDX_IER_MSB] = STMPE1601_REG_IER_MSB,
[STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB,
[STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB,
[STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB,
[STMPE_IDX_GPMR_CSB] = STMPE1601_REG_GPIO_MP_MSB,
[STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB,
[STMPE_IDX_GPSR_CSB] = STMPE1601_REG_GPIO_SET_MSB,
[STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB,
[STMPE_IDX_GPCR_CSB] = STMPE1601_REG_GPIO_CLR_MSB,
[STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB,
[STMPE_IDX_GPDR_CSB] = STMPE1601_REG_GPIO_SET_DIR_MSB,
[STMPE_IDX_GPEDR_LSB] = STMPE1601_REG_GPIO_ED_LSB,
[STMPE_IDX_GPEDR_CSB] = STMPE1601_REG_GPIO_ED_MSB,
[STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB,
[STMPE_IDX_GPRER_CSB] = STMPE1601_REG_GPIO_RE_MSB,
[STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB,
[STMPE_IDX_GPFER_CSB] = STMPE1601_REG_GPIO_FE_MSB,
[STMPE_IDX_GPPUR_LSB] = STMPE1601_REG_GPIO_PU_LSB,
[STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB,
[STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB,
[STMPE_IDX_IEGPIOR_CSB] = STMPE1601_REG_INT_EN_GPIO_MASK_MSB,
[STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB,
};
static struct stmpe_variant_block stmpe1601_blocks[] = {
{
.cell = &stmpe_gpio_cell,
.irq = STMPE1601_IRQ_GPIOC,
.block = STMPE_BLOCK_GPIO,
},
{
.cell = &stmpe_keypad_cell,
.irq = STMPE1601_IRQ_KEYPAD,
.block = STMPE_BLOCK_KEYPAD,
},
{
.cell = &stmpe_pwm_cell,
.irq = STMPE1601_IRQ_PWM0,
.block = STMPE_BLOCK_PWM,
},
};
/* supported autosleep timeout delay (in msecs) */
static const int stmpe_autosleep_delay[] = {
4, 16, 32, 64, 128, 256, 512, 1024,
};
static int stmpe_round_timeout(int timeout)
{
int i;
for (i = 0; i < ARRAY_SIZE(stmpe_autosleep_delay); i++) {
if (stmpe_autosleep_delay[i] >= timeout)
return i;
}
/*
* requests for delays longer than supported should not return the
* longest supported delay
*/
return -EINVAL;
}
static int stmpe_autosleep(struct stmpe *stmpe, int autosleep_timeout)
{
int ret;
if (!stmpe->variant->enable_autosleep)
return -ENOSYS;
mutex_lock(&stmpe->lock);
ret = stmpe->variant->enable_autosleep(stmpe, autosleep_timeout);
mutex_unlock(&stmpe->lock);
return ret;
}
/*
* Both stmpe 1601/2403 support same layout for autosleep
*/
static int stmpe1601_autosleep(struct stmpe *stmpe,
int autosleep_timeout)
{
int ret, timeout;
/* choose the best available timeout */
timeout = stmpe_round_timeout(autosleep_timeout);
if (timeout < 0) {
dev_err(stmpe->dev, "invalid timeout\n");
return timeout;
}
ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
STMPE1601_AUTOSLEEP_TIMEOUT_MASK,
timeout);
if (ret < 0)
return ret;
return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
STPME1601_AUTOSLEEP_ENABLE,
STPME1601_AUTOSLEEP_ENABLE);
}
static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks,
bool enable)
{
unsigned int mask = 0;
if (blocks & STMPE_BLOCK_GPIO)
mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO;
else
mask &= ~STMPE1601_SYS_CTRL_ENABLE_GPIO;
if (blocks & STMPE_BLOCK_KEYPAD)
mask |= STMPE1601_SYS_CTRL_ENABLE_KPC;
else
mask &= ~STMPE1601_SYS_CTRL_ENABLE_KPC;
if (blocks & STMPE_BLOCK_PWM)
mask |= STMPE1601_SYS_CTRL_ENABLE_SPWM;
else
mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM;
return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
enable ? mask : 0);
}
static int stmpe1601_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
{
switch (block) {
case STMPE_BLOCK_PWM:
return 2;
case STMPE_BLOCK_KEYPAD:
return 1;
case STMPE_BLOCK_GPIO:
default:
return 0;
}
}
static struct stmpe_variant_info stmpe1601 = {
.name = "stmpe1601",
.id_val = 0x0210,
.id_mask = 0xfff0, /* at least 0x0210 and 0x0212 */
.num_gpios = 16,
.af_bits = 2,
.regs = stmpe1601_regs,
.blocks = stmpe1601_blocks,
.num_blocks = ARRAY_SIZE(stmpe1601_blocks),
.num_irqs = STMPE1601_NR_INTERNAL_IRQS,
.enable = stmpe1601_enable,
.get_altfunc = stmpe1601_get_altfunc,
.enable_autosleep = stmpe1601_autosleep,
};
/*
* STMPE1801
*/
static const u8 stmpe1801_regs[] = {
[STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID,
[STMPE_IDX_SYS_CTRL] = STMPE1801_REG_SYS_CTRL,
[STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW,
[STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW,
[STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW,
[STMPE_IDX_GPMR_LSB] = STMPE1801_REG_GPIO_MP_LOW,
[STMPE_IDX_GPMR_CSB] = STMPE1801_REG_GPIO_MP_MID,
[STMPE_IDX_GPMR_MSB] = STMPE1801_REG_GPIO_MP_HIGH,
[STMPE_IDX_GPSR_LSB] = STMPE1801_REG_GPIO_SET_LOW,
[STMPE_IDX_GPSR_CSB] = STMPE1801_REG_GPIO_SET_MID,
[STMPE_IDX_GPSR_MSB] = STMPE1801_REG_GPIO_SET_HIGH,
[STMPE_IDX_GPCR_LSB] = STMPE1801_REG_GPIO_CLR_LOW,
[STMPE_IDX_GPCR_CSB] = STMPE1801_REG_GPIO_CLR_MID,
[STMPE_IDX_GPCR_MSB] = STMPE1801_REG_GPIO_CLR_HIGH,
[STMPE_IDX_GPDR_LSB] = STMPE1801_REG_GPIO_SET_DIR_LOW,
[STMPE_IDX_GPDR_CSB] = STMPE1801_REG_GPIO_SET_DIR_MID,
[STMPE_IDX_GPDR_MSB] = STMPE1801_REG_GPIO_SET_DIR_HIGH,
[STMPE_IDX_GPRER_LSB] = STMPE1801_REG_GPIO_RE_LOW,
[STMPE_IDX_GPRER_CSB] = STMPE1801_REG_GPIO_RE_MID,
[STMPE_IDX_GPRER_MSB] = STMPE1801_REG_GPIO_RE_HIGH,
[STMPE_IDX_GPFER_LSB] = STMPE1801_REG_GPIO_FE_LOW,
[STMPE_IDX_GPFER_CSB] = STMPE1801_REG_GPIO_FE_MID,
[STMPE_IDX_GPFER_MSB] = STMPE1801_REG_GPIO_FE_HIGH,
[STMPE_IDX_GPPUR_LSB] = STMPE1801_REG_GPIO_PULL_UP_LOW,
[STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW,
[STMPE_IDX_IEGPIOR_CSB] = STMPE1801_REG_INT_EN_GPIO_MASK_MID,
[STMPE_IDX_IEGPIOR_MSB] = STMPE1801_REG_INT_EN_GPIO_MASK_HIGH,
[STMPE_IDX_ISGPIOR_MSB] = STMPE1801_REG_INT_STA_GPIO_HIGH,
};
static struct stmpe_variant_block stmpe1801_blocks[] = {
{
.cell = &stmpe_gpio_cell,
.irq = STMPE1801_IRQ_GPIOC,
.block = STMPE_BLOCK_GPIO,
},
{
.cell = &stmpe_keypad_cell,
.irq = STMPE1801_IRQ_KEYPAD,
.block = STMPE_BLOCK_KEYPAD,
},
};
static int stmpe1801_enable(struct stmpe *stmpe, unsigned int blocks,
bool enable)
{
unsigned int mask = 0;
if (blocks & STMPE_BLOCK_GPIO)
mask |= STMPE1801_MSK_INT_EN_GPIO;
if (blocks & STMPE_BLOCK_KEYPAD)
mask |= STMPE1801_MSK_INT_EN_KPC;
return __stmpe_set_bits(stmpe, STMPE1801_REG_INT_EN_MASK_LOW, mask,
enable ? mask : 0);
}
static int stmpe_reset(struct stmpe *stmpe)
{
u16 id_val = stmpe->variant->id_val;
unsigned long timeout;
int ret = 0;
u8 reset_bit;
if (id_val == STMPE811_ID)
/* STMPE801 and STMPE610 use bit 1 of SYS_CTRL register */
reset_bit = STMPE811_SYS_CTRL_RESET;
else
/* all other STMPE variant use bit 7 of SYS_CTRL register */
reset_bit = STMPE_SYS_CTRL_RESET;
ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL],
reset_bit, reset_bit);
if (ret < 0)
return ret;
msleep(10);
timeout = jiffies + msecs_to_jiffies(100);
while (time_before(jiffies, timeout)) {
ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]);
if (ret < 0)
return ret;
if (!(ret & reset_bit))
return 0;
usleep_range(100, 200);
}
return -EIO;
}
static struct stmpe_variant_info stmpe1801 = {
.name = "stmpe1801",
.id_val = STMPE1801_ID,
.id_mask = 0xfff0,
.num_gpios = 18,
.af_bits = 0,
.regs = stmpe1801_regs,
.blocks = stmpe1801_blocks,
.num_blocks = ARRAY_SIZE(stmpe1801_blocks),
.num_irqs = STMPE1801_NR_INTERNAL_IRQS,
.enable = stmpe1801_enable,
/* stmpe1801 do not have any gpio alternate function */
.get_altfunc = NULL,
};
/*
* STMPE24XX
*/
static const u8 stmpe24xx_regs[] = {
[STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID,
[STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL,
[STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2,
[STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB,
[STMPE_IDX_IER_MSB] = STMPE24XX_REG_IER_MSB,
[STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB,
[STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB,
[STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB,
[STMPE_IDX_GPMR_CSB] = STMPE24XX_REG_GPMR_CSB,
[STMPE_IDX_GPMR_MSB] = STMPE24XX_REG_GPMR_MSB,
[STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB,
[STMPE_IDX_GPSR_CSB] = STMPE24XX_REG_GPSR_CSB,
[STMPE_IDX_GPSR_MSB] = STMPE24XX_REG_GPSR_MSB,
[STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB,
[STMPE_IDX_GPCR_CSB] = STMPE24XX_REG_GPCR_CSB,
[STMPE_IDX_GPCR_MSB] = STMPE24XX_REG_GPCR_MSB,
[STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB,
[STMPE_IDX_GPDR_CSB] = STMPE24XX_REG_GPDR_CSB,
[STMPE_IDX_GPDR_MSB] = STMPE24XX_REG_GPDR_MSB,
[STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB,
[STMPE_IDX_GPRER_CSB] = STMPE24XX_REG_GPRER_CSB,
[STMPE_IDX_GPRER_MSB] = STMPE24XX_REG_GPRER_MSB,
[STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB,
[STMPE_IDX_GPFER_CSB] = STMPE24XX_REG_GPFER_CSB,
[STMPE_IDX_GPFER_MSB] = STMPE24XX_REG_GPFER_MSB,
[STMPE_IDX_GPPUR_LSB] = STMPE24XX_REG_GPPUR_LSB,
[STMPE_IDX_GPPDR_LSB] = STMPE24XX_REG_GPPDR_LSB,
[STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB,
[STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB,
[STMPE_IDX_IEGPIOR_CSB] = STMPE24XX_REG_IEGPIOR_CSB,
[STMPE_IDX_IEGPIOR_MSB] = STMPE24XX_REG_IEGPIOR_MSB,
[STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB,
[STMPE_IDX_GPEDR_LSB] = STMPE24XX_REG_GPEDR_LSB,
[STMPE_IDX_GPEDR_CSB] = STMPE24XX_REG_GPEDR_CSB,
[STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB,
};
static struct stmpe_variant_block stmpe24xx_blocks[] = {
{
.cell = &stmpe_gpio_cell,
.irq = STMPE24XX_IRQ_GPIOC,
.block = STMPE_BLOCK_GPIO,
},
{
.cell = &stmpe_keypad_cell,
.irq = STMPE24XX_IRQ_KEYPAD,
.block = STMPE_BLOCK_KEYPAD,
},
{
.cell = &stmpe_pwm_cell,
.irq = STMPE24XX_IRQ_PWM0,
.block = STMPE_BLOCK_PWM,
},
};
static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks,
bool enable)
{
unsigned int mask = 0;
if (blocks & STMPE_BLOCK_GPIO)
mask |= STMPE24XX_SYS_CTRL_ENABLE_GPIO;
if (blocks & STMPE_BLOCK_KEYPAD)
mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC;
return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
enable ? mask : 0);
}
static int stmpe24xx_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
{
switch (block) {
case STMPE_BLOCK_ROTATOR:
return 2;
case STMPE_BLOCK_KEYPAD:
case STMPE_BLOCK_PWM:
return 1;
case STMPE_BLOCK_GPIO:
default:
return 0;
}
}
static struct stmpe_variant_info stmpe2401 = {
.name = "stmpe2401",
.id_val = 0x0101,
.id_mask = 0xffff,
.num_gpios = 24,
.af_bits = 2,
.regs = stmpe24xx_regs,
.blocks = stmpe24xx_blocks,
.num_blocks = ARRAY_SIZE(stmpe24xx_blocks),
.num_irqs = STMPE24XX_NR_INTERNAL_IRQS,
.enable = stmpe24xx_enable,
.get_altfunc = stmpe24xx_get_altfunc,
};
static struct stmpe_variant_info stmpe2403 = {
.name = "stmpe2403",
.id_val = 0x0120,
.id_mask = 0xffff,
.num_gpios = 24,
.af_bits = 2,
.regs = stmpe24xx_regs,
.blocks = stmpe24xx_blocks,
.num_blocks = ARRAY_SIZE(stmpe24xx_blocks),
.num_irqs = STMPE24XX_NR_INTERNAL_IRQS,
.enable = stmpe24xx_enable,
.get_altfunc = stmpe24xx_get_altfunc,
.enable_autosleep = stmpe1601_autosleep, /* same as stmpe1601 */
};
static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = {
[STMPE610] = &stmpe610,
[STMPE801] = &stmpe801,
[STMPE811] = &stmpe811,
[STMPE1600] = &stmpe1600,
[STMPE1601] = &stmpe1601,
[STMPE1801] = &stmpe1801,
[STMPE2401] = &stmpe2401,
[STMPE2403] = &stmpe2403,
};
/*
* These devices can be connected in a 'no-irq' configuration - the irq pin
* is not used and the device cannot interrupt the CPU. Here we only list
* devices which support this configuration - the driver will fail probing
* for any devices not listed here which are configured in this way.
*/
static struct stmpe_variant_info *stmpe_noirq_variant_info[STMPE_NBR_PARTS] = {
[STMPE801] = &stmpe801_noirq,
};
static irqreturn_t stmpe_irq(int irq, void *data)
{
struct stmpe *stmpe = data;
struct stmpe_variant_info *variant = stmpe->variant;
int num = DIV_ROUND_UP(variant->num_irqs, 8);
u8 israddr;
u8 isr[3];
int ret;
int i;
if (variant->id_val == STMPE801_ID ||
variant->id_val == STMPE1600_ID) {
int base = irq_find_mapping(stmpe->domain, 0);
handle_nested_irq(base);
return IRQ_HANDLED;
}
if (variant->id_val == STMPE1801_ID)
israddr = stmpe->regs[STMPE_IDX_ISR_LSB];
else
israddr = stmpe->regs[STMPE_IDX_ISR_MSB];
ret = stmpe_block_read(stmpe, israddr, num, isr);
if (ret < 0)
return IRQ_NONE;
for (i = 0; i < num; i++) {
int bank = num - i - 1;
u8 status = isr[i];
u8 clear;
status &= stmpe->ier[bank];
if (!status)
continue;
clear = status;
while (status) {
int bit = __ffs(status);
int line = bank * 8 + bit;
int nestedirq = irq_find_mapping(stmpe->domain, line);
handle_nested_irq(nestedirq);
status &= ~(1 << bit);
}
stmpe_reg_write(stmpe, israddr + i, clear);
}
return IRQ_HANDLED;
}
static void stmpe_irq_lock(struct irq_data *data)
{
struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
mutex_lock(&stmpe->irq_lock);
}
static void stmpe_irq_sync_unlock(struct irq_data *data)
{
struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
struct stmpe_variant_info *variant = stmpe->variant;
int num = DIV_ROUND_UP(variant->num_irqs, 8);
int i;
for (i = 0; i < num; i++) {
u8 new = stmpe->ier[i];
u8 old = stmpe->oldier[i];
if (new == old)
continue;
stmpe->oldier[i] = new;
stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB + i], new);
}
mutex_unlock(&stmpe->irq_lock);
}
static void stmpe_irq_mask(struct irq_data *data)
{
struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
int offset = data->hwirq;
int regoffset = offset / 8;
int mask = 1 << (offset % 8);
stmpe->ier[regoffset] &= ~mask;
}
static void stmpe_irq_unmask(struct irq_data *data)
{
struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
int offset = data->hwirq;
int regoffset = offset / 8;
int mask = 1 << (offset % 8);
stmpe->ier[regoffset] |= mask;
}
static struct irq_chip stmpe_irq_chip = {
.name = "stmpe",
.irq_bus_lock = stmpe_irq_lock,
.irq_bus_sync_unlock = stmpe_irq_sync_unlock,
.irq_mask = stmpe_irq_mask,
.irq_unmask = stmpe_irq_unmask,
};
static int stmpe_irq_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hwirq)
{
struct stmpe *stmpe = d->host_data;
struct irq_chip *chip = NULL;
if (stmpe->variant->id_val != STMPE801_ID)
chip = &stmpe_irq_chip;
irq_set_chip_data(virq, stmpe);
irq_set_chip_and_handler(virq, chip, handle_edge_irq);
irq_set_nested_thread(virq, 1);
irq_set_noprobe(virq);
return 0;
}
static void stmpe_irq_unmap(struct irq_domain *d, unsigned int virq)
{
irq_set_chip_and_handler(virq, NULL, NULL);
irq_set_chip_data(virq, NULL);
}
static const struct irq_domain_ops stmpe_irq_ops = {
.map = stmpe_irq_map,
.unmap = stmpe_irq_unmap,
.xlate = irq_domain_xlate_twocell,
};
static int stmpe_irq_init(struct stmpe *stmpe, struct device_node *np)
{
int base = 0;
int num_irqs = stmpe->variant->num_irqs;
stmpe->domain = irq_domain_add_simple(np, num_irqs, base,
&stmpe_irq_ops, stmpe);
if (!stmpe->domain) {
dev_err(stmpe->dev, "Failed to create irqdomain\n");
return -ENOSYS;
}
return 0;
}
static int stmpe_chip_init(struct stmpe *stmpe)
{
unsigned int irq_trigger = stmpe->pdata->irq_trigger;
int autosleep_timeout = stmpe->pdata->autosleep_timeout;
struct stmpe_variant_info *variant = stmpe->variant;
u8 icr = 0;
unsigned int id;
u8 data[2];
int ret;
ret = stmpe_block_read(stmpe, stmpe->regs[STMPE_IDX_CHIP_ID],
ARRAY_SIZE(data), data);
if (ret < 0)
return ret;
id = (data[0] << 8) | data[1];
if ((id & variant->id_mask) != variant->id_val) {
dev_err(stmpe->dev, "unknown chip id: %#x\n", id);
return -EINVAL;
}
dev_info(stmpe->dev, "%s detected, chip id: %#x\n", variant->name, id);
/* Disable all modules -- subdrivers should enable what they need. */
ret = stmpe_disable(stmpe, ~0);
if (ret)
return ret;
ret = stmpe_reset(stmpe);
if (ret < 0)
return ret;
if (stmpe->irq >= 0) {
if (id == STMPE801_ID || id == STMPE1600_ID)
icr = STMPE_SYS_CTRL_INT_EN;
else
icr = STMPE_ICR_LSB_GIM;
/* STMPE801 and STMPE1600 don't support Edge interrupts */
if (id != STMPE801_ID && id != STMPE1600_ID) {
if (irq_trigger == IRQF_TRIGGER_FALLING ||
irq_trigger == IRQF_TRIGGER_RISING)
icr |= STMPE_ICR_LSB_EDGE;
}
if (irq_trigger == IRQF_TRIGGER_RISING ||
irq_trigger == IRQF_TRIGGER_HIGH) {
if (id == STMPE801_ID || id == STMPE1600_ID)
icr |= STMPE_SYS_CTRL_INT_HI;
else
icr |= STMPE_ICR_LSB_HIGH;
}
}
if (stmpe->pdata->autosleep) {
ret = stmpe_autosleep(stmpe, autosleep_timeout);
if (ret)
return ret;
}
return stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_ICR_LSB], icr);
}
static int stmpe_add_device(struct stmpe *stmpe, const struct mfd_cell *cell)
{
return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1,
NULL, 0, stmpe->domain);
}
static int stmpe_devices_init(struct stmpe *stmpe)
{
struct stmpe_variant_info *variant = stmpe->variant;
unsigned int platform_blocks = stmpe->pdata->blocks;
int ret = -EINVAL;
int i, j;
for (i = 0; i < variant->num_blocks; i++) {
struct stmpe_variant_block *block = &variant->blocks[i];
if (!(platform_blocks & block->block))
continue;
for (j = 0; j < block->cell->num_resources; j++) {
struct resource *res =
(struct resource *) &block->cell->resources[j];
/* Dynamically fill in a variant's IRQ. */
if (res->flags & IORESOURCE_IRQ)
res->start = res->end = block->irq + j;
}
platform_blocks &= ~block->block;
ret = stmpe_add_device(stmpe, block->cell);
if (ret)
return ret;
}
if (platform_blocks)
dev_warn(stmpe->dev,
"platform wants blocks (%#x) not present on variant",
platform_blocks);
return ret;
}
static void stmpe_of_probe(struct stmpe_platform_data *pdata,
struct device_node *np)
{
struct device_node *child;
pdata->id = of_alias_get_id(np, "stmpe-i2c");
if (pdata->id < 0)
pdata->id = -1;
of_property_read_u32(np, "st,autosleep-timeout",
&pdata->autosleep_timeout);
pdata->autosleep = (pdata->autosleep_timeout) ? true : false;
for_each_available_child_of_node(np, child) {
if (of_device_is_compatible(child, stmpe_gpio_cell.of_compatible))
pdata->blocks |= STMPE_BLOCK_GPIO;
else if (of_device_is_compatible(child, stmpe_keypad_cell.of_compatible))
pdata->blocks |= STMPE_BLOCK_KEYPAD;
else if (of_device_is_compatible(child, stmpe_ts_cell.of_compatible))
pdata->blocks |= STMPE_BLOCK_TOUCHSCREEN;
else if (of_device_is_compatible(child, stmpe_adc_cell.of_compatible))
pdata->blocks |= STMPE_BLOCK_ADC;
else if (of_device_is_compatible(child, stmpe_pwm_cell.of_compatible))
pdata->blocks |= STMPE_BLOCK_PWM;
}
}
/* Called from client specific probe routines */
int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum)
{
struct stmpe_platform_data *pdata;
struct device_node *np = ci->dev->of_node;
struct stmpe *stmpe;
struct gpio_desc *irq_gpio;
int ret;
u32 val;
pdata = devm_kzalloc(ci->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
stmpe_of_probe(pdata, np);
if (!of_property_present(np, "interrupts"))
ci->irq = -1;
stmpe = devm_kzalloc(ci->dev, sizeof(struct stmpe), GFP_KERNEL);
if (!stmpe)
return -ENOMEM;
mutex_init(&stmpe->irq_lock);
mutex_init(&stmpe->lock);
if (!of_property_read_u32(np, "st,sample-time", &val))
stmpe->sample_time = val;
if (!of_property_read_u32(np, "st,mod-12b", &val))
stmpe->mod_12b = val;
if (!of_property_read_u32(np, "st,ref-sel", &val))
stmpe->ref_sel = val;
if (!of_property_read_u32(np, "st,adc-freq", &val))
stmpe->adc_freq = val;
stmpe->dev = ci->dev;
stmpe->client = ci->client;
stmpe->pdata = pdata;
stmpe->ci = ci;
stmpe->partnum = partnum;
stmpe->variant = stmpe_variant_info[partnum];
stmpe->regs = stmpe->variant->regs;
stmpe->num_gpios = stmpe->variant->num_gpios;
stmpe->vcc = devm_regulator_get_optional(ci->dev, "vcc");
if (!IS_ERR(stmpe->vcc)) {
ret = regulator_enable(stmpe->vcc);
if (ret)
dev_warn(ci->dev, "failed to enable VCC supply\n");
}
stmpe->vio = devm_regulator_get_optional(ci->dev, "vio");
if (!IS_ERR(stmpe->vio)) {
ret = regulator_enable(stmpe->vio);
if (ret)
dev_warn(ci->dev, "failed to enable VIO supply\n");
}
dev_set_drvdata(stmpe->dev, stmpe);
if (ci->init)
ci->init(stmpe);
irq_gpio = devm_gpiod_get_optional(ci->dev, "irq", GPIOD_ASIS);
ret = PTR_ERR_OR_ZERO(irq_gpio);
if (ret) {
dev_err(stmpe->dev, "failed to request IRQ GPIO: %d\n", ret);
return ret;
}
if (irq_gpio) {
stmpe->irq = gpiod_to_irq(irq_gpio);
pdata->irq_trigger = gpiod_is_active_low(irq_gpio) ?
IRQF_TRIGGER_LOW : IRQF_TRIGGER_HIGH;
} else {
stmpe->irq = ci->irq;
pdata->irq_trigger = IRQF_TRIGGER_NONE;
}
if (stmpe->irq < 0) {
/* use alternate variant info for no-irq mode, if supported */
dev_info(stmpe->dev,
"%s configured in no-irq mode by platform data\n",
stmpe->variant->name);
if (!stmpe_noirq_variant_info[stmpe->partnum]) {
dev_err(stmpe->dev,
"%s does not support no-irq mode!\n",
stmpe->variant->name);
return -ENODEV;
}
stmpe->variant = stmpe_noirq_variant_info[stmpe->partnum];
} else if (pdata->irq_trigger == IRQF_TRIGGER_NONE) {
pdata->irq_trigger = irq_get_trigger_type(stmpe->irq);
}
ret = stmpe_chip_init(stmpe);
if (ret)
return ret;
if (stmpe->irq >= 0) {
ret = stmpe_irq_init(stmpe, np);
if (ret)
return ret;
ret = devm_request_threaded_irq(ci->dev, stmpe->irq, NULL,
stmpe_irq, pdata->irq_trigger | IRQF_ONESHOT,
"stmpe", stmpe);
if (ret) {
dev_err(stmpe->dev, "failed to request IRQ: %d\n",
ret);
return ret;
}
}
ret = stmpe_devices_init(stmpe);
if (!ret)
return 0;
dev_err(stmpe->dev, "failed to add children\n");
mfd_remove_devices(stmpe->dev);
return ret;
}
void stmpe_remove(struct stmpe *stmpe)
{
if (!IS_ERR(stmpe->vio) && regulator_is_enabled(stmpe->vio))
regulator_disable(stmpe->vio);
if (!IS_ERR(stmpe->vcc) && regulator_is_enabled(stmpe->vcc))
regulator_disable(stmpe->vcc);
__stmpe_disable(stmpe, STMPE_BLOCK_ADC);
mfd_remove_devices(stmpe->dev);
}
static int stmpe_suspend(struct device *dev)
{
struct stmpe *stmpe = dev_get_drvdata(dev);
if (stmpe->irq >= 0 && device_may_wakeup(dev))
enable_irq_wake(stmpe->irq);
return 0;
}
static int stmpe_resume(struct device *dev)
{
struct stmpe *stmpe = dev_get_drvdata(dev);
if (stmpe->irq >= 0 && device_may_wakeup(dev))
disable_irq_wake(stmpe->irq);
return 0;
}
EXPORT_GPL_SIMPLE_DEV_PM_OPS(stmpe_dev_pm_ops,
stmpe_suspend, stmpe_resume);
| linux-master | drivers/mfd/stmpe.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Freescale MXS Low Resolution Analog-to-Digital Converter driver
*
* Copyright (c) 2012 DENX Software Engineering, GmbH.
* Copyright (c) 2017 Ksenija Stanojevic <[email protected]>
*
* Authors:
* Marek Vasut <[email protected]>
* Ksenija Stanojevic <[email protected]>
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/mxs-lradc.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#define ADC_CELL 0
#define TSC_CELL 1
#define RES_MEM 0
enum mx23_lradc_irqs {
MX23_LRADC_TS_IRQ = 0,
MX23_LRADC_CH0_IRQ,
MX23_LRADC_CH1_IRQ,
MX23_LRADC_CH2_IRQ,
MX23_LRADC_CH3_IRQ,
MX23_LRADC_CH4_IRQ,
MX23_LRADC_CH5_IRQ,
MX23_LRADC_CH6_IRQ,
MX23_LRADC_CH7_IRQ,
};
enum mx28_lradc_irqs {
MX28_LRADC_TS_IRQ = 0,
MX28_LRADC_TRESH0_IRQ,
MX28_LRADC_TRESH1_IRQ,
MX28_LRADC_CH0_IRQ,
MX28_LRADC_CH1_IRQ,
MX28_LRADC_CH2_IRQ,
MX28_LRADC_CH3_IRQ,
MX28_LRADC_CH4_IRQ,
MX28_LRADC_CH5_IRQ,
MX28_LRADC_CH6_IRQ,
MX28_LRADC_CH7_IRQ,
MX28_LRADC_BUTTON0_IRQ,
MX28_LRADC_BUTTON1_IRQ,
};
static struct resource mx23_adc_resources[] = {
DEFINE_RES_MEM(0x0, 0x0),
DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH0_IRQ, "mxs-lradc-channel0"),
DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH1_IRQ, "mxs-lradc-channel1"),
DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH2_IRQ, "mxs-lradc-channel2"),
DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH3_IRQ, "mxs-lradc-channel3"),
DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH4_IRQ, "mxs-lradc-channel4"),
DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH5_IRQ, "mxs-lradc-channel5"),
};
static struct resource mx23_touchscreen_resources[] = {
DEFINE_RES_MEM(0x0, 0x0),
DEFINE_RES_IRQ_NAMED(MX23_LRADC_TS_IRQ, "mxs-lradc-touchscreen"),
DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH6_IRQ, "mxs-lradc-channel6"),
DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH7_IRQ, "mxs-lradc-channel7"),
};
static struct resource mx28_adc_resources[] = {
DEFINE_RES_MEM(0x0, 0x0),
DEFINE_RES_IRQ_NAMED(MX28_LRADC_TRESH0_IRQ, "mxs-lradc-thresh0"),
DEFINE_RES_IRQ_NAMED(MX28_LRADC_TRESH1_IRQ, "mxs-lradc-thresh1"),
DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH0_IRQ, "mxs-lradc-channel0"),
DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH1_IRQ, "mxs-lradc-channel1"),
DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH2_IRQ, "mxs-lradc-channel2"),
DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH3_IRQ, "mxs-lradc-channel3"),
DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH4_IRQ, "mxs-lradc-channel4"),
DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH5_IRQ, "mxs-lradc-channel5"),
DEFINE_RES_IRQ_NAMED(MX28_LRADC_BUTTON0_IRQ, "mxs-lradc-button0"),
DEFINE_RES_IRQ_NAMED(MX28_LRADC_BUTTON1_IRQ, "mxs-lradc-button1"),
};
static struct resource mx28_touchscreen_resources[] = {
DEFINE_RES_MEM(0x0, 0x0),
DEFINE_RES_IRQ_NAMED(MX28_LRADC_TS_IRQ, "mxs-lradc-touchscreen"),
DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH6_IRQ, "mxs-lradc-channel6"),
DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH7_IRQ, "mxs-lradc-channel7"),
};
static struct mfd_cell mx23_cells[] = {
{
.name = "mxs-lradc-adc",
.resources = mx23_adc_resources,
.num_resources = ARRAY_SIZE(mx23_adc_resources),
},
{
.name = "mxs-lradc-ts",
.resources = mx23_touchscreen_resources,
.num_resources = ARRAY_SIZE(mx23_touchscreen_resources),
},
};
static struct mfd_cell mx28_cells[] = {
{
.name = "mxs-lradc-adc",
.resources = mx28_adc_resources,
.num_resources = ARRAY_SIZE(mx28_adc_resources),
},
{
.name = "mxs-lradc-ts",
.resources = mx28_touchscreen_resources,
.num_resources = ARRAY_SIZE(mx28_touchscreen_resources),
}
};
static const struct of_device_id mxs_lradc_dt_ids[] = {
{ .compatible = "fsl,imx23-lradc", .data = (void *)IMX23_LRADC, },
{ .compatible = "fsl,imx28-lradc", .data = (void *)IMX28_LRADC, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
static int mxs_lradc_probe(struct platform_device *pdev)
{
const struct of_device_id *of_id;
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
struct mxs_lradc *lradc;
struct mfd_cell *cells = NULL;
struct resource *res;
int ret = 0;
u32 ts_wires = 0;
lradc = devm_kzalloc(&pdev->dev, sizeof(*lradc), GFP_KERNEL);
if (!lradc)
return -ENOMEM;
of_id = of_match_device(mxs_lradc_dt_ids, &pdev->dev);
if (!of_id)
return -EINVAL;
lradc->soc = (uintptr_t)of_id->data;
lradc->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(lradc->clk)) {
dev_err(dev, "Failed to get the delay unit clock\n");
return PTR_ERR(lradc->clk);
}
ret = clk_prepare_enable(lradc->clk);
if (ret) {
dev_err(dev, "Failed to enable the delay unit clock\n");
return ret;
}
ret = of_property_read_u32(node, "fsl,lradc-touchscreen-wires",
&ts_wires);
if (!ret) {
lradc->buffer_vchans = BUFFER_VCHANS_LIMITED;
switch (ts_wires) {
case 4:
lradc->touchscreen_wire = MXS_LRADC_TOUCHSCREEN_4WIRE;
break;
case 5:
if (lradc->soc == IMX28_LRADC) {
lradc->touchscreen_wire =
MXS_LRADC_TOUCHSCREEN_5WIRE;
break;
}
fallthrough; /* to an error message for i.MX23 */
default:
dev_err(&pdev->dev,
"Unsupported number of touchscreen wires (%d)\n"
, ts_wires);
ret = -EINVAL;
goto err_clk;
}
} else {
lradc->buffer_vchans = BUFFER_VCHANS_ALL;
}
platform_set_drvdata(pdev, lradc);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
ret = -ENOMEM;
goto err_clk;
}
switch (lradc->soc) {
case IMX23_LRADC:
mx23_adc_resources[RES_MEM] = *res;
mx23_touchscreen_resources[RES_MEM] = *res;
cells = mx23_cells;
break;
case IMX28_LRADC:
mx28_adc_resources[RES_MEM] = *res;
mx28_touchscreen_resources[RES_MEM] = *res;
cells = mx28_cells;
break;
default:
dev_err(dev, "Unsupported SoC\n");
ret = -ENODEV;
goto err_clk;
}
ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE,
&cells[ADC_CELL], 1, NULL, 0, NULL);
if (ret) {
dev_err(&pdev->dev, "Failed to add the ADC subdevice\n");
goto err_clk;
}
if (!lradc->touchscreen_wire)
return 0;
ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE,
&cells[TSC_CELL], 1, NULL, 0, NULL);
if (ret) {
dev_err(&pdev->dev,
"Failed to add the touchscreen subdevice\n");
goto err_clk;
}
return 0;
err_clk:
clk_disable_unprepare(lradc->clk);
return ret;
}
static int mxs_lradc_remove(struct platform_device *pdev)
{
struct mxs_lradc *lradc = platform_get_drvdata(pdev);
clk_disable_unprepare(lradc->clk);
return 0;
}
static struct platform_driver mxs_lradc_driver = {
.driver = {
.name = "mxs-lradc",
.of_match_table = mxs_lradc_dt_ids,
},
.probe = mxs_lradc_probe,
.remove = mxs_lradc_remove,
};
module_platform_driver(mxs_lradc_driver);
MODULE_AUTHOR("Ksenija Stanojevic <[email protected]>");
MODULE_DESCRIPTION("Freescale i.MX23/i.MX28 LRADC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mxs-lradc");
| linux-master | drivers/mfd/mxs-lradc.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/* NXP PCF50633 Power Management Unit (PMU) driver
*
* (C) 2006-2008 by Openmoko, Inc.
* Author: Harald Welte <[email protected]>
* Balaji Rao <[email protected]>
* All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/pm.h>
#include <linux/slab.h>
#include <linux/regmap.h>
#include <linux/err.h>
#include <linux/mfd/pcf50633/core.h>
/* Read a block of up to 32 regs */
int pcf50633_read_block(struct pcf50633 *pcf, u8 reg,
int nr_regs, u8 *data)
{
int ret;
ret = regmap_raw_read(pcf->regmap, reg, data, nr_regs);
if (ret != 0)
return ret;
return nr_regs;
}
EXPORT_SYMBOL_GPL(pcf50633_read_block);
/* Write a block of up to 32 regs */
int pcf50633_write_block(struct pcf50633 *pcf , u8 reg,
int nr_regs, u8 *data)
{
return regmap_raw_write(pcf->regmap, reg, data, nr_regs);
}
EXPORT_SYMBOL_GPL(pcf50633_write_block);
u8 pcf50633_reg_read(struct pcf50633 *pcf, u8 reg)
{
unsigned int val;
int ret;
ret = regmap_read(pcf->regmap, reg, &val);
if (ret < 0)
return -1;
return val;
}
EXPORT_SYMBOL_GPL(pcf50633_reg_read);
int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val)
{
return regmap_write(pcf->regmap, reg, val);
}
EXPORT_SYMBOL_GPL(pcf50633_reg_write);
int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val)
{
return regmap_update_bits(pcf->regmap, reg, mask, val);
}
EXPORT_SYMBOL_GPL(pcf50633_reg_set_bit_mask);
int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 val)
{
return regmap_update_bits(pcf->regmap, reg, val, 0);
}
EXPORT_SYMBOL_GPL(pcf50633_reg_clear_bits);
/* sysfs attributes */
static ssize_t dump_regs_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct pcf50633 *pcf = dev_get_drvdata(dev);
u8 dump[16];
int n, n1, idx = 0;
char *buf1 = buf;
static u8 address_no_read[] = { /* must be ascending */
PCF50633_REG_INT1,
PCF50633_REG_INT2,
PCF50633_REG_INT3,
PCF50633_REG_INT4,
PCF50633_REG_INT5,
0 /* terminator */
};
for (n = 0; n < 256; n += sizeof(dump)) {
for (n1 = 0; n1 < sizeof(dump); n1++)
if (n == address_no_read[idx]) {
idx++;
dump[n1] = 0x00;
} else
dump[n1] = pcf50633_reg_read(pcf, n + n1);
buf1 += sprintf(buf1, "%*ph\n", (int)sizeof(dump), dump);
}
return buf1 - buf;
}
static DEVICE_ATTR_ADMIN_RO(dump_regs);
static ssize_t resume_reason_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct pcf50633 *pcf = dev_get_drvdata(dev);
int n;
n = sprintf(buf, "%02x%02x%02x%02x%02x\n",
pcf->resume_reason[0],
pcf->resume_reason[1],
pcf->resume_reason[2],
pcf->resume_reason[3],
pcf->resume_reason[4]);
return n;
}
static DEVICE_ATTR_ADMIN_RO(resume_reason);
static struct attribute *pcf_sysfs_entries[] = {
&dev_attr_dump_regs.attr,
&dev_attr_resume_reason.attr,
NULL,
};
static struct attribute_group pcf_attr_group = {
.name = NULL, /* put in device directory */
.attrs = pcf_sysfs_entries,
};
static void
pcf50633_client_dev_register(struct pcf50633 *pcf, const char *name,
struct platform_device **pdev)
{
int ret;
*pdev = platform_device_alloc(name, -1);
if (!*pdev) {
dev_err(pcf->dev, "Failed to allocate %s\n", name);
return;
}
(*pdev)->dev.parent = pcf->dev;
ret = platform_device_add(*pdev);
if (ret) {
dev_err(pcf->dev, "Failed to register %s: %d\n", name, ret);
platform_device_put(*pdev);
*pdev = NULL;
}
}
static const struct regmap_config pcf50633_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
static int pcf50633_probe(struct i2c_client *client)
{
struct pcf50633 *pcf;
struct platform_device *pdev;
struct pcf50633_platform_data *pdata = dev_get_platdata(&client->dev);
int i, j, ret;
int version, variant;
if (!client->irq) {
dev_err(&client->dev, "Missing IRQ\n");
return -ENOENT;
}
pcf = devm_kzalloc(&client->dev, sizeof(*pcf), GFP_KERNEL);
if (!pcf)
return -ENOMEM;
i2c_set_clientdata(client, pcf);
pcf->dev = &client->dev;
pcf->pdata = pdata;
mutex_init(&pcf->lock);
pcf->regmap = devm_regmap_init_i2c(client, &pcf50633_regmap_config);
if (IS_ERR(pcf->regmap)) {
ret = PTR_ERR(pcf->regmap);
dev_err(pcf->dev, "Failed to allocate register map: %d\n", ret);
return ret;
}
version = pcf50633_reg_read(pcf, 0);
variant = pcf50633_reg_read(pcf, 1);
if (version < 0 || variant < 0) {
dev_err(pcf->dev, "Unable to probe pcf50633\n");
ret = -ENODEV;
return ret;
}
dev_info(pcf->dev, "Probed device version %d variant %d\n",
version, variant);
pcf50633_irq_init(pcf, client->irq);
/* Create sub devices */
pcf50633_client_dev_register(pcf, "pcf50633-input", &pcf->input_pdev);
pcf50633_client_dev_register(pcf, "pcf50633-rtc", &pcf->rtc_pdev);
pcf50633_client_dev_register(pcf, "pcf50633-mbc", &pcf->mbc_pdev);
pcf50633_client_dev_register(pcf, "pcf50633-adc", &pcf->adc_pdev);
pcf50633_client_dev_register(pcf, "pcf50633-backlight", &pcf->bl_pdev);
for (i = 0; i < PCF50633_NUM_REGULATORS; i++) {
pdev = platform_device_alloc("pcf50633-regulator", i);
if (!pdev) {
ret = -ENOMEM;
goto err2;
}
pdev->dev.parent = pcf->dev;
ret = platform_device_add_data(pdev, &pdata->reg_init_data[i],
sizeof(pdata->reg_init_data[i]));
if (ret)
goto err;
ret = platform_device_add(pdev);
if (ret)
goto err;
pcf->regulator_pdev[i] = pdev;
}
ret = sysfs_create_group(&client->dev.kobj, &pcf_attr_group);
if (ret)
dev_warn(pcf->dev, "error creating sysfs entries\n");
if (pdata->probe_done)
pdata->probe_done(pcf);
return 0;
err:
platform_device_put(pdev);
err2:
for (j = 0; j < i; j++)
platform_device_put(pcf->regulator_pdev[j]);
return ret;
}
static void pcf50633_remove(struct i2c_client *client)
{
struct pcf50633 *pcf = i2c_get_clientdata(client);
int i;
sysfs_remove_group(&client->dev.kobj, &pcf_attr_group);
pcf50633_irq_free(pcf);
platform_device_unregister(pcf->input_pdev);
platform_device_unregister(pcf->rtc_pdev);
platform_device_unregister(pcf->mbc_pdev);
platform_device_unregister(pcf->adc_pdev);
platform_device_unregister(pcf->bl_pdev);
for (i = 0; i < PCF50633_NUM_REGULATORS; i++)
platform_device_unregister(pcf->regulator_pdev[i]);
}
static const struct i2c_device_id pcf50633_id_table[] = {
{"pcf50633", 0x73},
{/* end of list */}
};
MODULE_DEVICE_TABLE(i2c, pcf50633_id_table);
static struct i2c_driver pcf50633_driver = {
.driver = {
.name = "pcf50633",
.pm = pm_sleep_ptr(&pcf50633_pm),
},
.id_table = pcf50633_id_table,
.probe = pcf50633_probe,
.remove = pcf50633_remove,
};
static int __init pcf50633_init(void)
{
return i2c_add_driver(&pcf50633_driver);
}
static void __exit pcf50633_exit(void)
{
i2c_del_driver(&pcf50633_driver);
}
MODULE_DESCRIPTION("I2C chip driver for NXP PCF50633 PMU");
MODULE_AUTHOR("Harald Welte <[email protected]>");
MODULE_LICENSE("GPL");
subsys_initcall(pcf50633_init);
module_exit(pcf50633_exit);
| linux-master | drivers/mfd/pcf50633-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* MFD core driver for Rockchip RK8XX
*
* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
* Copyright (C) 2016 PHYTEC Messtechnik GmbH
*
* Author: Chris Zhong <[email protected]>
* Author: Zhang Qing <[email protected]>
* Author: Wadim Egorov <[email protected]>
*/
#include <linux/interrupt.h>
#include <linux/mfd/rk808.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/reboot.h>
struct rk808_reg_data {
int addr;
int mask;
int value;
};
static const struct resource rtc_resources[] = {
DEFINE_RES_IRQ(RK808_IRQ_RTC_ALARM),
};
static const struct resource rk817_rtc_resources[] = {
DEFINE_RES_IRQ(RK817_IRQ_RTC_ALARM),
};
static const struct resource rk805_key_resources[] = {
DEFINE_RES_IRQ(RK805_IRQ_PWRON_RISE),
DEFINE_RES_IRQ(RK805_IRQ_PWRON_FALL),
};
static struct resource rk806_pwrkey_resources[] = {
DEFINE_RES_IRQ(RK806_IRQ_PWRON_FALL),
DEFINE_RES_IRQ(RK806_IRQ_PWRON_RISE),
};
static const struct resource rk817_pwrkey_resources[] = {
DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE),
DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL),
};
static const struct resource rk817_charger_resources[] = {
DEFINE_RES_IRQ(RK817_IRQ_PLUG_IN),
DEFINE_RES_IRQ(RK817_IRQ_PLUG_OUT),
};
static const struct mfd_cell rk805s[] = {
{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
{ .name = "rk805-pinctrl", .id = PLATFORM_DEVID_NONE, },
{
.name = "rk808-rtc",
.num_resources = ARRAY_SIZE(rtc_resources),
.resources = &rtc_resources[0],
.id = PLATFORM_DEVID_NONE,
},
{ .name = "rk805-pwrkey",
.num_resources = ARRAY_SIZE(rk805_key_resources),
.resources = &rk805_key_resources[0],
.id = PLATFORM_DEVID_NONE,
},
};
static const struct mfd_cell rk806s[] = {
{ .name = "rk805-pinctrl", .id = PLATFORM_DEVID_AUTO, },
{ .name = "rk808-regulator", .id = PLATFORM_DEVID_AUTO, },
{
.name = "rk805-pwrkey",
.resources = rk806_pwrkey_resources,
.num_resources = ARRAY_SIZE(rk806_pwrkey_resources),
.id = PLATFORM_DEVID_AUTO,
},
};
static const struct mfd_cell rk808s[] = {
{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
{
.name = "rk808-rtc",
.num_resources = ARRAY_SIZE(rtc_resources),
.resources = rtc_resources,
.id = PLATFORM_DEVID_NONE,
},
};
static const struct mfd_cell rk817s[] = {
{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
{
.name = "rk805-pwrkey",
.num_resources = ARRAY_SIZE(rk817_pwrkey_resources),
.resources = &rk817_pwrkey_resources[0],
.id = PLATFORM_DEVID_NONE,
},
{
.name = "rk808-rtc",
.num_resources = ARRAY_SIZE(rk817_rtc_resources),
.resources = &rk817_rtc_resources[0],
.id = PLATFORM_DEVID_NONE,
},
{ .name = "rk817-codec", .id = PLATFORM_DEVID_NONE, },
{
.name = "rk817-charger",
.num_resources = ARRAY_SIZE(rk817_charger_resources),
.resources = &rk817_charger_resources[0],
.id = PLATFORM_DEVID_NONE,
},
};
static const struct mfd_cell rk818s[] = {
{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
{
.name = "rk808-rtc",
.num_resources = ARRAY_SIZE(rtc_resources),
.resources = rtc_resources,
.id = PLATFORM_DEVID_NONE,
},
};
static const struct rk808_reg_data rk805_pre_init_reg[] = {
{RK805_BUCK1_CONFIG_REG, RK805_BUCK1_2_ILMAX_MASK,
RK805_BUCK1_2_ILMAX_4000MA},
{RK805_BUCK2_CONFIG_REG, RK805_BUCK1_2_ILMAX_MASK,
RK805_BUCK1_2_ILMAX_4000MA},
{RK805_BUCK3_CONFIG_REG, RK805_BUCK3_4_ILMAX_MASK,
RK805_BUCK3_ILMAX_3000MA},
{RK805_BUCK4_CONFIG_REG, RK805_BUCK3_4_ILMAX_MASK,
RK805_BUCK4_ILMAX_3500MA},
{RK805_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_400MA},
{RK805_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP115C},
};
static const struct rk808_reg_data rk806_pre_init_reg[] = {
{ RK806_GPIO_INT_CONFIG, RK806_INT_POL_MSK, RK806_INT_POL_L },
{ RK806_SYS_CFG3, RK806_SLAVE_RESTART_FUN_MSK, RK806_SLAVE_RESTART_FUN_EN },
{ RK806_SYS_OPTION, RK806_SYS_ENB2_2M_MSK, RK806_SYS_ENB2_2M_EN },
};
static const struct rk808_reg_data rk808_pre_init_reg[] = {
{ RK808_BUCK3_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_150MA },
{ RK808_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_200MA },
{ RK808_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA },
{ RK808_BUCK1_CONFIG_REG, BUCK1_RATE_MASK, BUCK_ILMIN_200MA },
{ RK808_BUCK2_CONFIG_REG, BUCK2_RATE_MASK, BUCK_ILMIN_200MA },
{ RK808_DCDC_UV_ACT_REG, BUCK_UV_ACT_MASK, BUCK_UV_ACT_DISABLE},
{ RK808_VB_MON_REG, MASK_ALL, VB_LO_ACT |
VB_LO_SEL_3500MV },
};
static const struct rk808_reg_data rk817_pre_init_reg[] = {
{RK817_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
/* Codec specific registers */
{ RK817_CODEC_DTOP_VUCTL, MASK_ALL, 0x03 },
{ RK817_CODEC_DTOP_VUCTIME, MASK_ALL, 0x00 },
{ RK817_CODEC_DTOP_LPT_SRST, MASK_ALL, 0x00 },
{ RK817_CODEC_DTOP_DIGEN_CLKE, MASK_ALL, 0x00 },
/* from vendor driver, CODEC_AREF_RTCFG0 not defined in data sheet */
{ RK817_CODEC_AREF_RTCFG0, MASK_ALL, 0x00 },
{ RK817_CODEC_AREF_RTCFG1, MASK_ALL, 0x06 },
{ RK817_CODEC_AADC_CFG0, MASK_ALL, 0xc8 },
/* from vendor driver, CODEC_AADC_CFG1 not defined in data sheet */
{ RK817_CODEC_AADC_CFG1, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_VOLL, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_VOLR, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_SR_ACL0, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_ALC1, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_ALC2, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_NG, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_HPF, MASK_ALL, 0x00 },
{ RK817_CODEC_DADC_RVOLL, MASK_ALL, 0xff },
{ RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff },
{ RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 },
{ RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 },
{ RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 },
/* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */
{ RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 },
{ RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 },
{ RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 },
{ RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 },
{ RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff },
{ RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff },
{ RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 },
{ RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 },
{ RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 },
{ RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 },
/* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */
{ RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 },
{ RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 },
{ RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 },
{ RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 },
{ RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 },
{ RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff },
{ RK817_CODEC_DDAC_RVOLR, MASK_ALL, 0xff },
{ RK817_CODEC_AHP_ANTI0, MASK_ALL, 0x00 },
{ RK817_CODEC_AHP_ANTI1, MASK_ALL, 0x00 },
{ RK817_CODEC_AHP_CFG0, MASK_ALL, 0xe0 },
{ RK817_CODEC_AHP_CFG1, MASK_ALL, 0x1f },
{ RK817_CODEC_AHP_CP, MASK_ALL, 0x09 },
{ RK817_CODEC_ACLASSD_CFG1, MASK_ALL, 0x69 },
{ RK817_CODEC_ACLASSD_CFG2, MASK_ALL, 0x44 },
{ RK817_CODEC_APLL_CFG0, MASK_ALL, 0x04 },
{ RK817_CODEC_APLL_CFG1, MASK_ALL, 0x00 },
{ RK817_CODEC_APLL_CFG2, MASK_ALL, 0x30 },
{ RK817_CODEC_APLL_CFG3, MASK_ALL, 0x19 },
{ RK817_CODEC_APLL_CFG4, MASK_ALL, 0x65 },
{ RK817_CODEC_APLL_CFG5, MASK_ALL, 0x01 },
{ RK817_CODEC_DI2S_CKM, MASK_ALL, 0x01 },
{ RK817_CODEC_DI2S_RSD, MASK_ALL, 0x00 },
{ RK817_CODEC_DI2S_RXCR1, MASK_ALL, 0x00 },
{ RK817_CODEC_DI2S_RXCR2, MASK_ALL, 0x17 },
{ RK817_CODEC_DI2S_RXCMD_TSD, MASK_ALL, 0x00 },
{ RK817_CODEC_DI2S_TXCR1, MASK_ALL, 0x00 },
{ RK817_CODEC_DI2S_TXCR2, MASK_ALL, 0x17 },
{ RK817_CODEC_DI2S_TXCR3_TXCMD, MASK_ALL, 0x00 },
{RK817_GPIO_INT_CFG, RK817_INT_POL_MSK, RK817_INT_POL_L},
{RK817_SYS_CFG(1), RK817_HOTDIE_TEMP_MSK | RK817_TSD_TEMP_MSK,
RK817_HOTDIE_105 | RK817_TSD_140},
};
static const struct rk808_reg_data rk818_pre_init_reg[] = {
/* improve efficiency */
{ RK818_BUCK2_CONFIG_REG, BUCK2_RATE_MASK, BUCK_ILMIN_250MA },
{ RK818_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_250MA },
{ RK818_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA },
{ RK818_USB_CTRL_REG, RK818_USB_ILIM_SEL_MASK,
RK818_USB_ILMIN_2000MA },
/* close charger when usb lower then 3.4V */
{ RK818_USB_CTRL_REG, RK818_USB_CHG_SD_VSEL_MASK,
(0x7 << 4) },
/* no action when vref */
{ RK818_H5V_EN_REG, BIT(1), RK818_REF_RDY_CTRL },
/* enable HDMI 5V */
{ RK818_H5V_EN_REG, BIT(0), RK818_H5V_EN },
{ RK808_VB_MON_REG, MASK_ALL, VB_LO_ACT |
VB_LO_SEL_3500MV },
};
static const struct regmap_irq rk805_irqs[] = {
[RK805_IRQ_PWRON_RISE] = {
.mask = RK805_IRQ_PWRON_RISE_MSK,
.reg_offset = 0,
},
[RK805_IRQ_VB_LOW] = {
.mask = RK805_IRQ_VB_LOW_MSK,
.reg_offset = 0,
},
[RK805_IRQ_PWRON] = {
.mask = RK805_IRQ_PWRON_MSK,
.reg_offset = 0,
},
[RK805_IRQ_PWRON_LP] = {
.mask = RK805_IRQ_PWRON_LP_MSK,
.reg_offset = 0,
},
[RK805_IRQ_HOTDIE] = {
.mask = RK805_IRQ_HOTDIE_MSK,
.reg_offset = 0,
},
[RK805_IRQ_RTC_ALARM] = {
.mask = RK805_IRQ_RTC_ALARM_MSK,
.reg_offset = 0,
},
[RK805_IRQ_RTC_PERIOD] = {
.mask = RK805_IRQ_RTC_PERIOD_MSK,
.reg_offset = 0,
},
[RK805_IRQ_PWRON_FALL] = {
.mask = RK805_IRQ_PWRON_FALL_MSK,
.reg_offset = 0,
},
};
static const struct regmap_irq rk806_irqs[] = {
/* INT_STS0 IRQs */
REGMAP_IRQ_REG(RK806_IRQ_PWRON_FALL, 0, RK806_INT_STS_PWRON_FALL),
REGMAP_IRQ_REG(RK806_IRQ_PWRON_RISE, 0, RK806_INT_STS_PWRON_RISE),
REGMAP_IRQ_REG(RK806_IRQ_PWRON, 0, RK806_INT_STS_PWRON),
REGMAP_IRQ_REG(RK806_IRQ_PWRON_LP, 0, RK806_INT_STS_PWRON_LP),
REGMAP_IRQ_REG(RK806_IRQ_HOTDIE, 0, RK806_INT_STS_HOTDIE),
REGMAP_IRQ_REG(RK806_IRQ_VDC_RISE, 0, RK806_INT_STS_VDC_RISE),
REGMAP_IRQ_REG(RK806_IRQ_VDC_FALL, 0, RK806_INT_STS_VDC_FALL),
REGMAP_IRQ_REG(RK806_IRQ_VB_LO, 0, RK806_INT_STS_VB_LO),
/* INT_STS1 IRQs */
REGMAP_IRQ_REG(RK806_IRQ_REV0, 1, RK806_INT_STS_REV0),
REGMAP_IRQ_REG(RK806_IRQ_REV1, 1, RK806_INT_STS_REV1),
REGMAP_IRQ_REG(RK806_IRQ_REV2, 1, RK806_INT_STS_REV2),
REGMAP_IRQ_REG(RK806_IRQ_CRC_ERROR, 1, RK806_INT_STS_CRC_ERROR),
REGMAP_IRQ_REG(RK806_IRQ_SLP3_GPIO, 1, RK806_INT_STS_SLP3_GPIO),
REGMAP_IRQ_REG(RK806_IRQ_SLP2_GPIO, 1, RK806_INT_STS_SLP2_GPIO),
REGMAP_IRQ_REG(RK806_IRQ_SLP1_GPIO, 1, RK806_INT_STS_SLP1_GPIO),
REGMAP_IRQ_REG(RK806_IRQ_WDT, 1, RK806_INT_STS_WDT),
};
static const struct regmap_irq rk808_irqs[] = {
/* INT_STS */
[RK808_IRQ_VOUT_LO] = {
.mask = RK808_IRQ_VOUT_LO_MSK,
.reg_offset = 0,
},
[RK808_IRQ_VB_LO] = {
.mask = RK808_IRQ_VB_LO_MSK,
.reg_offset = 0,
},
[RK808_IRQ_PWRON] = {
.mask = RK808_IRQ_PWRON_MSK,
.reg_offset = 0,
},
[RK808_IRQ_PWRON_LP] = {
.mask = RK808_IRQ_PWRON_LP_MSK,
.reg_offset = 0,
},
[RK808_IRQ_HOTDIE] = {
.mask = RK808_IRQ_HOTDIE_MSK,
.reg_offset = 0,
},
[RK808_IRQ_RTC_ALARM] = {
.mask = RK808_IRQ_RTC_ALARM_MSK,
.reg_offset = 0,
},
[RK808_IRQ_RTC_PERIOD] = {
.mask = RK808_IRQ_RTC_PERIOD_MSK,
.reg_offset = 0,
},
/* INT_STS2 */
[RK808_IRQ_PLUG_IN_INT] = {
.mask = RK808_IRQ_PLUG_IN_INT_MSK,
.reg_offset = 1,
},
[RK808_IRQ_PLUG_OUT_INT] = {
.mask = RK808_IRQ_PLUG_OUT_INT_MSK,
.reg_offset = 1,
},
};
static const struct regmap_irq rk818_irqs[] = {
/* INT_STS */
[RK818_IRQ_VOUT_LO] = {
.mask = RK818_IRQ_VOUT_LO_MSK,
.reg_offset = 0,
},
[RK818_IRQ_VB_LO] = {
.mask = RK818_IRQ_VB_LO_MSK,
.reg_offset = 0,
},
[RK818_IRQ_PWRON] = {
.mask = RK818_IRQ_PWRON_MSK,
.reg_offset = 0,
},
[RK818_IRQ_PWRON_LP] = {
.mask = RK818_IRQ_PWRON_LP_MSK,
.reg_offset = 0,
},
[RK818_IRQ_HOTDIE] = {
.mask = RK818_IRQ_HOTDIE_MSK,
.reg_offset = 0,
},
[RK818_IRQ_RTC_ALARM] = {
.mask = RK818_IRQ_RTC_ALARM_MSK,
.reg_offset = 0,
},
[RK818_IRQ_RTC_PERIOD] = {
.mask = RK818_IRQ_RTC_PERIOD_MSK,
.reg_offset = 0,
},
[RK818_IRQ_USB_OV] = {
.mask = RK818_IRQ_USB_OV_MSK,
.reg_offset = 0,
},
/* INT_STS2 */
[RK818_IRQ_PLUG_IN] = {
.mask = RK818_IRQ_PLUG_IN_MSK,
.reg_offset = 1,
},
[RK818_IRQ_PLUG_OUT] = {
.mask = RK818_IRQ_PLUG_OUT_MSK,
.reg_offset = 1,
},
[RK818_IRQ_CHG_OK] = {
.mask = RK818_IRQ_CHG_OK_MSK,
.reg_offset = 1,
},
[RK818_IRQ_CHG_TE] = {
.mask = RK818_IRQ_CHG_TE_MSK,
.reg_offset = 1,
},
[RK818_IRQ_CHG_TS1] = {
.mask = RK818_IRQ_CHG_TS1_MSK,
.reg_offset = 1,
},
[RK818_IRQ_TS2] = {
.mask = RK818_IRQ_TS2_MSK,
.reg_offset = 1,
},
[RK818_IRQ_CHG_CVTLIM] = {
.mask = RK818_IRQ_CHG_CVTLIM_MSK,
.reg_offset = 1,
},
[RK818_IRQ_DISCHG_ILIM] = {
.mask = RK818_IRQ_DISCHG_ILIM_MSK,
.reg_offset = 1,
},
};
static const struct regmap_irq rk817_irqs[RK817_IRQ_END] = {
REGMAP_IRQ_REG_LINE(0, 8),
REGMAP_IRQ_REG_LINE(1, 8),
REGMAP_IRQ_REG_LINE(2, 8),
REGMAP_IRQ_REG_LINE(3, 8),
REGMAP_IRQ_REG_LINE(4, 8),
REGMAP_IRQ_REG_LINE(5, 8),
REGMAP_IRQ_REG_LINE(6, 8),
REGMAP_IRQ_REG_LINE(7, 8),
REGMAP_IRQ_REG_LINE(8, 8),
REGMAP_IRQ_REG_LINE(9, 8),
REGMAP_IRQ_REG_LINE(10, 8),
REGMAP_IRQ_REG_LINE(11, 8),
REGMAP_IRQ_REG_LINE(12, 8),
REGMAP_IRQ_REG_LINE(13, 8),
REGMAP_IRQ_REG_LINE(14, 8),
REGMAP_IRQ_REG_LINE(15, 8),
REGMAP_IRQ_REG_LINE(16, 8),
REGMAP_IRQ_REG_LINE(17, 8),
REGMAP_IRQ_REG_LINE(18, 8),
REGMAP_IRQ_REG_LINE(19, 8),
REGMAP_IRQ_REG_LINE(20, 8),
REGMAP_IRQ_REG_LINE(21, 8),
REGMAP_IRQ_REG_LINE(22, 8),
REGMAP_IRQ_REG_LINE(23, 8)
};
static struct regmap_irq_chip rk805_irq_chip = {
.name = "rk805",
.irqs = rk805_irqs,
.num_irqs = ARRAY_SIZE(rk805_irqs),
.num_regs = 1,
.status_base = RK805_INT_STS_REG,
.mask_base = RK805_INT_STS_MSK_REG,
.ack_base = RK805_INT_STS_REG,
.init_ack_masked = true,
};
static struct regmap_irq_chip rk806_irq_chip = {
.name = "rk806",
.irqs = rk806_irqs,
.num_irqs = ARRAY_SIZE(rk806_irqs),
.num_regs = 2,
.irq_reg_stride = 2,
.mask_base = RK806_INT_MSK0,
.status_base = RK806_INT_STS0,
.ack_base = RK806_INT_STS0,
.init_ack_masked = true,
};
static const struct regmap_irq_chip rk808_irq_chip = {
.name = "rk808",
.irqs = rk808_irqs,
.num_irqs = ARRAY_SIZE(rk808_irqs),
.num_regs = 2,
.irq_reg_stride = 2,
.status_base = RK808_INT_STS_REG1,
.mask_base = RK808_INT_STS_MSK_REG1,
.ack_base = RK808_INT_STS_REG1,
.init_ack_masked = true,
};
static struct regmap_irq_chip rk817_irq_chip = {
.name = "rk817",
.irqs = rk817_irqs,
.num_irqs = ARRAY_SIZE(rk817_irqs),
.num_regs = 3,
.irq_reg_stride = 2,
.status_base = RK817_INT_STS_REG0,
.mask_base = RK817_INT_STS_MSK_REG0,
.ack_base = RK817_INT_STS_REG0,
.init_ack_masked = true,
};
static const struct regmap_irq_chip rk818_irq_chip = {
.name = "rk818",
.irqs = rk818_irqs,
.num_irqs = ARRAY_SIZE(rk818_irqs),
.num_regs = 2,
.irq_reg_stride = 2,
.status_base = RK818_INT_STS_REG1,
.mask_base = RK818_INT_STS_MSK_REG1,
.ack_base = RK818_INT_STS_REG1,
.init_ack_masked = true,
};
static int rk808_power_off(struct sys_off_data *data)
{
struct rk808 *rk808 = data->cb_data;
int ret;
unsigned int reg, bit;
switch (rk808->variant) {
case RK805_ID:
reg = RK805_DEV_CTRL_REG;
bit = DEV_OFF;
break;
case RK808_ID:
reg = RK808_DEVCTRL_REG,
bit = DEV_OFF_RST;
break;
case RK809_ID:
case RK817_ID:
reg = RK817_SYS_CFG(3);
bit = DEV_OFF;
break;
case RK818_ID:
reg = RK818_DEVCTRL_REG;
bit = DEV_OFF;
break;
default:
return NOTIFY_DONE;
}
ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
if (ret)
dev_err(rk808->dev, "Failed to shutdown device!\n");
return NOTIFY_DONE;
}
static int rk808_restart(struct sys_off_data *data)
{
struct rk808 *rk808 = data->cb_data;
unsigned int reg, bit;
int ret;
switch (rk808->variant) {
case RK809_ID:
case RK817_ID:
reg = RK817_SYS_CFG(3);
bit = DEV_RST;
break;
default:
return NOTIFY_DONE;
}
ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
if (ret)
dev_err(rk808->dev, "Failed to restart device!\n");
return NOTIFY_DONE;
}
void rk8xx_shutdown(struct device *dev)
{
struct rk808 *rk808 = dev_get_drvdata(dev);
int ret;
switch (rk808->variant) {
case RK805_ID:
ret = regmap_update_bits(rk808->regmap,
RK805_GPIO_IO_POL_REG,
SLP_SD_MSK,
SHUTDOWN_FUN);
break;
case RK809_ID:
case RK817_ID:
ret = regmap_update_bits(rk808->regmap,
RK817_SYS_CFG(3),
RK817_SLPPIN_FUNC_MSK,
SLPPIN_DN_FUN);
break;
default:
return;
}
if (ret)
dev_warn(dev,
"Cannot switch to power down function\n");
}
EXPORT_SYMBOL_GPL(rk8xx_shutdown);
int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap *regmap)
{
struct rk808 *rk808;
const struct rk808_reg_data *pre_init_reg;
const struct mfd_cell *cells;
int dual_support = 0;
int nr_pre_init_regs;
int nr_cells;
int ret;
int i;
rk808 = devm_kzalloc(dev, sizeof(*rk808), GFP_KERNEL);
if (!rk808)
return -ENOMEM;
rk808->dev = dev;
rk808->variant = variant;
rk808->regmap = regmap;
dev_set_drvdata(dev, rk808);
switch (rk808->variant) {
case RK805_ID:
rk808->regmap_irq_chip = &rk805_irq_chip;
pre_init_reg = rk805_pre_init_reg;
nr_pre_init_regs = ARRAY_SIZE(rk805_pre_init_reg);
cells = rk805s;
nr_cells = ARRAY_SIZE(rk805s);
break;
case RK806_ID:
rk808->regmap_irq_chip = &rk806_irq_chip;
pre_init_reg = rk806_pre_init_reg;
nr_pre_init_regs = ARRAY_SIZE(rk806_pre_init_reg);
cells = rk806s;
nr_cells = ARRAY_SIZE(rk806s);
dual_support = IRQF_SHARED;
break;
case RK808_ID:
rk808->regmap_irq_chip = &rk808_irq_chip;
pre_init_reg = rk808_pre_init_reg;
nr_pre_init_regs = ARRAY_SIZE(rk808_pre_init_reg);
cells = rk808s;
nr_cells = ARRAY_SIZE(rk808s);
break;
case RK818_ID:
rk808->regmap_irq_chip = &rk818_irq_chip;
pre_init_reg = rk818_pre_init_reg;
nr_pre_init_regs = ARRAY_SIZE(rk818_pre_init_reg);
cells = rk818s;
nr_cells = ARRAY_SIZE(rk818s);
break;
case RK809_ID:
case RK817_ID:
rk808->regmap_irq_chip = &rk817_irq_chip;
pre_init_reg = rk817_pre_init_reg;
nr_pre_init_regs = ARRAY_SIZE(rk817_pre_init_reg);
cells = rk817s;
nr_cells = ARRAY_SIZE(rk817s);
break;
default:
dev_err(dev, "Unsupported RK8XX ID %lu\n", rk808->variant);
return -EINVAL;
}
if (!irq)
return dev_err_probe(dev, -EINVAL, "No interrupt support, no core IRQ\n");
ret = devm_regmap_add_irq_chip(dev, rk808->regmap, irq,
IRQF_ONESHOT | dual_support, -1,
rk808->regmap_irq_chip, &rk808->irq_data);
if (ret)
return dev_err_probe(dev, ret, "Failed to add irq_chip\n");
for (i = 0; i < nr_pre_init_regs; i++) {
ret = regmap_update_bits(rk808->regmap,
pre_init_reg[i].addr,
pre_init_reg[i].mask,
pre_init_reg[i].value);
if (ret)
return dev_err_probe(dev, ret, "0x%x write err\n",
pre_init_reg[i].addr);
}
ret = devm_mfd_add_devices(dev, 0, cells, nr_cells, NULL, 0,
regmap_irq_get_domain(rk808->irq_data));
if (ret)
return dev_err_probe(dev, ret, "failed to add MFD devices\n");
if (device_property_read_bool(dev, "rockchip,system-power-controller")) {
ret = devm_register_sys_off_handler(dev,
SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH,
&rk808_power_off, rk808);
if (ret)
return dev_err_probe(dev, ret,
"failed to register poweroff handler\n");
switch (rk808->variant) {
case RK809_ID:
case RK817_ID:
ret = devm_register_sys_off_handler(dev,
SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,
&rk808_restart, rk808);
if (ret)
dev_warn(dev, "failed to register rst handler, %d\n", ret);
break;
default:
dev_dbg(dev, "pmic controlled board reset not supported\n");
break;
}
}
return 0;
}
EXPORT_SYMBOL_GPL(rk8xx_probe);
int rk8xx_suspend(struct device *dev)
{
struct rk808 *rk808 = dev_get_drvdata(dev);
int ret = 0;
switch (rk808->variant) {
case RK805_ID:
ret = regmap_update_bits(rk808->regmap,
RK805_GPIO_IO_POL_REG,
SLP_SD_MSK,
SLEEP_FUN);
break;
case RK809_ID:
case RK817_ID:
ret = regmap_update_bits(rk808->regmap,
RK817_SYS_CFG(3),
RK817_SLPPIN_FUNC_MSK,
SLPPIN_SLP_FUN);
break;
default:
break;
}
return ret;
}
EXPORT_SYMBOL_GPL(rk8xx_suspend);
int rk8xx_resume(struct device *dev)
{
struct rk808 *rk808 = dev_get_drvdata(dev);
int ret = 0;
switch (rk808->variant) {
case RK809_ID:
case RK817_ID:
ret = regmap_update_bits(rk808->regmap,
RK817_SYS_CFG(3),
RK817_SLPPIN_FUNC_MSK,
SLPPIN_NULL_FUN);
break;
default:
break;
}
return ret;
}
EXPORT_SYMBOL_GPL(rk8xx_resume);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Chris Zhong <[email protected]>");
MODULE_AUTHOR("Zhang Qing <[email protected]>");
MODULE_AUTHOR("Wadim Egorov <[email protected]>");
MODULE_DESCRIPTION("RK8xx PMIC core");
| linux-master | drivers/mfd/rk8xx-core.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for AT91 USART
*
* Copyright (C) 2018 Microchip Technology
*
* Author: Radu Pirea <[email protected]>
*
*/
#include <dt-bindings/mfd/at91-usart.h>
#include <linux/module.h>
#include <linux/mfd/core.h>
#include <linux/of.h>
#include <linux/property.h>
static const struct mfd_cell at91_usart_spi_subdev =
MFD_CELL_NAME("at91_usart_spi");
static const struct mfd_cell at91_usart_serial_subdev =
MFD_CELL_NAME("atmel_usart_serial");
static int at91_usart_mode_probe(struct platform_device *pdev)
{
const struct mfd_cell *cell;
u32 opmode = AT91_USART_MODE_SERIAL;
device_property_read_u32(&pdev->dev, "atmel,usart-mode", &opmode);
switch (opmode) {
case AT91_USART_MODE_SPI:
cell = &at91_usart_spi_subdev;
break;
case AT91_USART_MODE_SERIAL:
cell = &at91_usart_serial_subdev;
break;
default:
dev_err(&pdev->dev, "atmel,usart-mode has an invalid value %u\n",
opmode);
return -EINVAL;
}
return devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO, cell, 1,
NULL, 0, NULL);
}
static const struct of_device_id at91_usart_mode_of_match[] = {
{ .compatible = "atmel,at91rm9200-usart" },
{ .compatible = "atmel,at91sam9260-usart" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, at91_usart_mode_of_match);
static struct platform_driver at91_usart_mfd = {
.probe = at91_usart_mode_probe,
.driver = {
.name = "at91_usart_mode",
.of_match_table = at91_usart_mode_of_match,
},
};
module_platform_driver(at91_usart_mfd);
MODULE_AUTHOR("Radu Pirea <[email protected]>");
MODULE_DESCRIPTION("AT91 USART MFD driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/at91-usart.c |
// SPDX-License-Identifier: GPL-2.0+
/* Interrupt support for Dialog DA9063
*
* Copyright 2012 Dialog Semiconductor Ltd.
* Copyright 2013 Philipp Zabel, Pengutronix
*
* Author: Michal Hajduk, Dialog Semiconductor
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/interrupt.h>
#include <linux/regmap.h>
#include <linux/mfd/da9063/core.h>
#define DA9063_REG_EVENT_A_OFFSET 0
#define DA9063_REG_EVENT_B_OFFSET 1
#define DA9063_REG_EVENT_C_OFFSET 2
#define DA9063_REG_EVENT_D_OFFSET 3
static const struct regmap_irq da9063_irqs[] = {
/* DA9063 event A register */
REGMAP_IRQ_REG(DA9063_IRQ_ONKEY,
DA9063_REG_EVENT_A_OFFSET, DA9063_M_ONKEY),
REGMAP_IRQ_REG(DA9063_IRQ_ALARM,
DA9063_REG_EVENT_A_OFFSET, DA9063_M_ALARM),
REGMAP_IRQ_REG(DA9063_IRQ_TICK,
DA9063_REG_EVENT_A_OFFSET, DA9063_M_TICK),
REGMAP_IRQ_REG(DA9063_IRQ_ADC_RDY,
DA9063_REG_EVENT_A_OFFSET, DA9063_M_ADC_RDY),
REGMAP_IRQ_REG(DA9063_IRQ_SEQ_RDY,
DA9063_REG_EVENT_A_OFFSET, DA9063_M_SEQ_RDY),
/* DA9063 event B register */
REGMAP_IRQ_REG(DA9063_IRQ_WAKE,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_WAKE),
REGMAP_IRQ_REG(DA9063_IRQ_TEMP,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_TEMP),
REGMAP_IRQ_REG(DA9063_IRQ_COMP_1V2,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_COMP_1V2),
REGMAP_IRQ_REG(DA9063_IRQ_LDO_LIM,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_LDO_LIM),
REGMAP_IRQ_REG(DA9063_IRQ_REG_UVOV,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_UVOV),
REGMAP_IRQ_REG(DA9063_IRQ_DVC_RDY,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_DVC_RDY),
REGMAP_IRQ_REG(DA9063_IRQ_VDD_MON,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_VDD_MON),
REGMAP_IRQ_REG(DA9063_IRQ_WARN,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_VDD_WARN),
/* DA9063 event C register */
REGMAP_IRQ_REG(DA9063_IRQ_GPI0,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI0),
REGMAP_IRQ_REG(DA9063_IRQ_GPI1,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI1),
REGMAP_IRQ_REG(DA9063_IRQ_GPI2,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI2),
REGMAP_IRQ_REG(DA9063_IRQ_GPI3,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI3),
REGMAP_IRQ_REG(DA9063_IRQ_GPI4,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI4),
REGMAP_IRQ_REG(DA9063_IRQ_GPI5,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI5),
REGMAP_IRQ_REG(DA9063_IRQ_GPI6,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI6),
REGMAP_IRQ_REG(DA9063_IRQ_GPI7,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI7),
/* DA9063 event D register */
REGMAP_IRQ_REG(DA9063_IRQ_GPI8,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI8),
REGMAP_IRQ_REG(DA9063_IRQ_GPI9,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI9),
REGMAP_IRQ_REG(DA9063_IRQ_GPI10,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI10),
REGMAP_IRQ_REG(DA9063_IRQ_GPI11,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI11),
REGMAP_IRQ_REG(DA9063_IRQ_GPI12,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI12),
REGMAP_IRQ_REG(DA9063_IRQ_GPI13,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI13),
REGMAP_IRQ_REG(DA9063_IRQ_GPI14,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI14),
REGMAP_IRQ_REG(DA9063_IRQ_GPI15,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI15),
};
static const struct regmap_irq_chip da9063_irq_chip = {
.name = "da9063-irq",
.irqs = da9063_irqs,
.num_irqs = ARRAY_SIZE(da9063_irqs),
.num_regs = 4,
.status_base = DA9063_REG_EVENT_A,
.mask_base = DA9063_REG_IRQ_MASK_A,
.ack_base = DA9063_REG_EVENT_A,
.init_ack_masked = true,
};
static const struct regmap_irq da9063l_irqs[] = {
/* DA9063 event A register */
REGMAP_IRQ_REG(DA9063_IRQ_ONKEY,
DA9063_REG_EVENT_A_OFFSET, DA9063_M_ONKEY),
REGMAP_IRQ_REG(DA9063_IRQ_ADC_RDY,
DA9063_REG_EVENT_A_OFFSET, DA9063_M_ADC_RDY),
REGMAP_IRQ_REG(DA9063_IRQ_SEQ_RDY,
DA9063_REG_EVENT_A_OFFSET, DA9063_M_SEQ_RDY),
/* DA9063 event B register */
REGMAP_IRQ_REG(DA9063_IRQ_WAKE,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_WAKE),
REGMAP_IRQ_REG(DA9063_IRQ_TEMP,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_TEMP),
REGMAP_IRQ_REG(DA9063_IRQ_COMP_1V2,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_COMP_1V2),
REGMAP_IRQ_REG(DA9063_IRQ_LDO_LIM,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_LDO_LIM),
REGMAP_IRQ_REG(DA9063_IRQ_REG_UVOV,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_UVOV),
REGMAP_IRQ_REG(DA9063_IRQ_DVC_RDY,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_DVC_RDY),
REGMAP_IRQ_REG(DA9063_IRQ_VDD_MON,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_VDD_MON),
REGMAP_IRQ_REG(DA9063_IRQ_WARN,
DA9063_REG_EVENT_B_OFFSET, DA9063_M_VDD_WARN),
/* DA9063 event C register */
REGMAP_IRQ_REG(DA9063_IRQ_GPI0,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI0),
REGMAP_IRQ_REG(DA9063_IRQ_GPI1,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI1),
REGMAP_IRQ_REG(DA9063_IRQ_GPI2,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI2),
REGMAP_IRQ_REG(DA9063_IRQ_GPI3,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI3),
REGMAP_IRQ_REG(DA9063_IRQ_GPI4,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI4),
REGMAP_IRQ_REG(DA9063_IRQ_GPI5,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI5),
REGMAP_IRQ_REG(DA9063_IRQ_GPI6,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI6),
REGMAP_IRQ_REG(DA9063_IRQ_GPI7,
DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI7),
/* DA9063 event D register */
REGMAP_IRQ_REG(DA9063_IRQ_GPI8,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI8),
REGMAP_IRQ_REG(DA9063_IRQ_GPI9,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI9),
REGMAP_IRQ_REG(DA9063_IRQ_GPI10,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI10),
REGMAP_IRQ_REG(DA9063_IRQ_GPI11,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI11),
REGMAP_IRQ_REG(DA9063_IRQ_GPI12,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI12),
REGMAP_IRQ_REG(DA9063_IRQ_GPI13,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI13),
REGMAP_IRQ_REG(DA9063_IRQ_GPI14,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI14),
REGMAP_IRQ_REG(DA9063_IRQ_GPI15,
DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI15),
};
static const struct regmap_irq_chip da9063l_irq_chip = {
.name = "da9063l-irq",
.irqs = da9063l_irqs,
.num_irqs = ARRAY_SIZE(da9063l_irqs),
.num_regs = 4,
.status_base = DA9063_REG_EVENT_A,
.mask_base = DA9063_REG_IRQ_MASK_A,
.ack_base = DA9063_REG_EVENT_A,
.init_ack_masked = true,
};
int da9063_irq_init(struct da9063 *da9063)
{
const struct regmap_irq_chip *irq_chip;
int ret;
if (!da9063->chip_irq) {
dev_err(da9063->dev, "No IRQ configured\n");
return -EINVAL;
}
if (da9063->type == PMIC_TYPE_DA9063)
irq_chip = &da9063_irq_chip;
else
irq_chip = &da9063l_irq_chip;
ret = devm_regmap_add_irq_chip(da9063->dev, da9063->regmap,
da9063->chip_irq,
IRQF_TRIGGER_LOW | IRQF_ONESHOT | IRQF_SHARED,
da9063->irq_base, irq_chip, &da9063->regmap_irq);
if (ret) {
dev_err(da9063->dev, "Failed to reguest IRQ %d: %d\n",
da9063->chip_irq, ret);
return ret;
}
return 0;
}
| linux-master | drivers/mfd/da9063-irq.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2009-2010 Creative Product Design
* Marc Reilly [email protected]
*/
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/mc13xxx.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include "mc13xxx.h"
static const struct i2c_device_id mc13xxx_i2c_device_id[] = {
{
.name = "mc13892",
.driver_data = (kernel_ulong_t)&mc13xxx_variant_mc13892,
}, {
.name = "mc34708",
.driver_data = (kernel_ulong_t)&mc13xxx_variant_mc34708,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(i2c, mc13xxx_i2c_device_id);
static const struct of_device_id mc13xxx_dt_ids[] = {
{
.compatible = "fsl,mc13892",
.data = &mc13xxx_variant_mc13892,
}, {
.compatible = "fsl,mc34708",
.data = &mc13xxx_variant_mc34708,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
static const struct regmap_config mc13xxx_regmap_i2c_config = {
.reg_bits = 8,
.val_bits = 24,
.max_register = MC13XXX_NUMREGS,
.cache_type = REGCACHE_NONE,
};
static int mc13xxx_i2c_probe(struct i2c_client *client)
{
struct mc13xxx *mc13xxx;
int ret;
mc13xxx = devm_kzalloc(&client->dev, sizeof(*mc13xxx), GFP_KERNEL);
if (!mc13xxx)
return -ENOMEM;
dev_set_drvdata(&client->dev, mc13xxx);
mc13xxx->irq = client->irq;
mc13xxx->regmap = devm_regmap_init_i2c(client,
&mc13xxx_regmap_i2c_config);
if (IS_ERR(mc13xxx->regmap)) {
ret = PTR_ERR(mc13xxx->regmap);
dev_err(&client->dev, "Failed to initialize regmap: %d\n", ret);
return ret;
}
mc13xxx->variant = i2c_get_match_data(client);
return mc13xxx_common_init(&client->dev);
}
static void mc13xxx_i2c_remove(struct i2c_client *client)
{
mc13xxx_common_exit(&client->dev);
}
static struct i2c_driver mc13xxx_i2c_driver = {
.id_table = mc13xxx_i2c_device_id,
.driver = {
.name = "mc13xxx",
.of_match_table = mc13xxx_dt_ids,
},
.probe = mc13xxx_i2c_probe,
.remove = mc13xxx_i2c_remove,
};
static int __init mc13xxx_i2c_init(void)
{
return i2c_add_driver(&mc13xxx_i2c_driver);
}
subsys_initcall(mc13xxx_i2c_init);
static void __exit mc13xxx_i2c_exit(void)
{
i2c_del_driver(&mc13xxx_i2c_driver);
}
module_exit(mc13xxx_i2c_exit);
MODULE_DESCRIPTION("i2c driver for Freescale MC13XXX PMIC");
MODULE_AUTHOR("Marc Reilly <[email protected]");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/mc13xxx-i2c.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas RZ/G2L Multi-Function Timer Pulse Unit 3(MTU3a) Core driver
*
* Copyright (C) 2023 Renesas Electronics Corporation
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/mfd/rz-mtu3.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/spinlock.h>
#include "rz-mtu3.h"
struct rz_mtu3_priv {
void __iomem *mmio;
struct reset_control *rstc;
spinlock_t lock;
};
/******* MTU3 registers (original offset is +0x1200) *******/
static const unsigned long rz_mtu3_8bit_ch_reg_offs[][13] = {
[RZ_MTU3_CHAN_0] = MTU_8BIT_CH_0(0x104, 0x090, 0x100, 0x128, 0x101, 0x102, 0x103, 0x126),
[RZ_MTU3_CHAN_1] = MTU_8BIT_CH_1_2(0x184, 0x091, 0x185, 0x180, 0x194, 0x181, 0x182),
[RZ_MTU3_CHAN_2] = MTU_8BIT_CH_1_2(0x204, 0x092, 0x205, 0x200, 0x20c, 0x201, 0x202),
[RZ_MTU3_CHAN_3] = MTU_8BIT_CH_3_4_6_7(0x008, 0x093, 0x02c, 0x000, 0x04c, 0x002, 0x004, 0x005, 0x038),
[RZ_MTU3_CHAN_4] = MTU_8BIT_CH_3_4_6_7(0x009, 0x094, 0x02d, 0x001, 0x04d, 0x003, 0x006, 0x007, 0x039),
[RZ_MTU3_CHAN_5] = MTU_8BIT_CH_5(0xab2, 0x1eb, 0xab4, 0xab6, 0xa84, 0xa85, 0xa86, 0xa94, 0xa95, 0xa96, 0xaa4, 0xaa5, 0xaa6),
[RZ_MTU3_CHAN_6] = MTU_8BIT_CH_3_4_6_7(0x808, 0x893, 0x82c, 0x800, 0x84c, 0x802, 0x804, 0x805, 0x838),
[RZ_MTU3_CHAN_7] = MTU_8BIT_CH_3_4_6_7(0x809, 0x894, 0x82d, 0x801, 0x84d, 0x803, 0x806, 0x807, 0x839),
[RZ_MTU3_CHAN_8] = MTU_8BIT_CH_8(0x404, 0x098, 0x400, 0x406, 0x401, 0x402, 0x403)
};
static const unsigned long rz_mtu3_16bit_ch_reg_offs[][12] = {
[RZ_MTU3_CHAN_0] = MTU_16BIT_CH_0(0x106, 0x108, 0x10a, 0x10c, 0x10e, 0x120, 0x122),
[RZ_MTU3_CHAN_1] = MTU_16BIT_CH_1_2(0x186, 0x188, 0x18a),
[RZ_MTU3_CHAN_2] = MTU_16BIT_CH_1_2(0x206, 0x208, 0x20a),
[RZ_MTU3_CHAN_3] = MTU_16BIT_CH_3_6(0x010, 0x018, 0x01a, 0x024, 0x026, 0x072),
[RZ_MTU3_CHAN_4] = MTU_16BIT_CH_4_7(0x012, 0x01c, 0x01e, 0x028, 0x2a, 0x074, 0x076, 0x040, 0x044, 0x046, 0x048, 0x04a),
[RZ_MTU3_CHAN_5] = MTU_16BIT_CH_5(0xa80, 0xa82, 0xa90, 0xa92, 0xaa0, 0xaa2),
[RZ_MTU3_CHAN_6] = MTU_16BIT_CH_3_6(0x810, 0x818, 0x81a, 0x824, 0x826, 0x872),
[RZ_MTU3_CHAN_7] = MTU_16BIT_CH_4_7(0x812, 0x81c, 0x81e, 0x828, 0x82a, 0x874, 0x876, 0x840, 0x844, 0x846, 0x848, 0x84a)
};
static const unsigned long rz_mtu3_32bit_ch_reg_offs[][5] = {
[RZ_MTU3_CHAN_1] = MTU_32BIT_CH_1(0x1a0, 0x1a4, 0x1a8),
[RZ_MTU3_CHAN_8] = MTU_32BIT_CH_8(0x408, 0x40c, 0x410, 0x414, 0x418)
};
static bool rz_mtu3_is_16bit_shared_reg(u16 offset)
{
return (offset == RZ_MTU3_TDDRA || offset == RZ_MTU3_TDDRB ||
offset == RZ_MTU3_TCDRA || offset == RZ_MTU3_TCDRB ||
offset == RZ_MTU3_TCBRA || offset == RZ_MTU3_TCBRB ||
offset == RZ_MTU3_TCNTSA || offset == RZ_MTU3_TCNTSB);
}
u16 rz_mtu3_shared_reg_read(struct rz_mtu3_channel *ch, u16 offset)
{
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
struct rz_mtu3_priv *priv = mtu->priv_data;
if (rz_mtu3_is_16bit_shared_reg(offset))
return readw(priv->mmio + offset);
else
return readb(priv->mmio + offset);
}
EXPORT_SYMBOL_GPL(rz_mtu3_shared_reg_read);
u8 rz_mtu3_8bit_ch_read(struct rz_mtu3_channel *ch, u16 offset)
{
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
struct rz_mtu3_priv *priv = mtu->priv_data;
u16 ch_offs;
ch_offs = rz_mtu3_8bit_ch_reg_offs[ch->channel_number][offset];
return readb(priv->mmio + ch_offs);
}
EXPORT_SYMBOL_GPL(rz_mtu3_8bit_ch_read);
u16 rz_mtu3_16bit_ch_read(struct rz_mtu3_channel *ch, u16 offset)
{
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
struct rz_mtu3_priv *priv = mtu->priv_data;
u16 ch_offs;
/* MTU8 doesn't have 16-bit registers */
if (ch->channel_number == RZ_MTU3_CHAN_8)
return 0;
ch_offs = rz_mtu3_16bit_ch_reg_offs[ch->channel_number][offset];
return readw(priv->mmio + ch_offs);
}
EXPORT_SYMBOL_GPL(rz_mtu3_16bit_ch_read);
u32 rz_mtu3_32bit_ch_read(struct rz_mtu3_channel *ch, u16 offset)
{
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
struct rz_mtu3_priv *priv = mtu->priv_data;
u16 ch_offs;
if (ch->channel_number != RZ_MTU3_CHAN_1 && ch->channel_number != RZ_MTU3_CHAN_8)
return 0;
ch_offs = rz_mtu3_32bit_ch_reg_offs[ch->channel_number][offset];
return readl(priv->mmio + ch_offs);
}
EXPORT_SYMBOL_GPL(rz_mtu3_32bit_ch_read);
void rz_mtu3_8bit_ch_write(struct rz_mtu3_channel *ch, u16 offset, u8 val)
{
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
struct rz_mtu3_priv *priv = mtu->priv_data;
u16 ch_offs;
ch_offs = rz_mtu3_8bit_ch_reg_offs[ch->channel_number][offset];
writeb(val, priv->mmio + ch_offs);
}
EXPORT_SYMBOL_GPL(rz_mtu3_8bit_ch_write);
void rz_mtu3_16bit_ch_write(struct rz_mtu3_channel *ch, u16 offset, u16 val)
{
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
struct rz_mtu3_priv *priv = mtu->priv_data;
u16 ch_offs;
/* MTU8 doesn't have 16-bit registers */
if (ch->channel_number == RZ_MTU3_CHAN_8)
return;
ch_offs = rz_mtu3_16bit_ch_reg_offs[ch->channel_number][offset];
writew(val, priv->mmio + ch_offs);
}
EXPORT_SYMBOL_GPL(rz_mtu3_16bit_ch_write);
void rz_mtu3_32bit_ch_write(struct rz_mtu3_channel *ch, u16 offset, u32 val)
{
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
struct rz_mtu3_priv *priv = mtu->priv_data;
u16 ch_offs;
if (ch->channel_number != RZ_MTU3_CHAN_1 && ch->channel_number != RZ_MTU3_CHAN_8)
return;
ch_offs = rz_mtu3_32bit_ch_reg_offs[ch->channel_number][offset];
writel(val, priv->mmio + ch_offs);
}
EXPORT_SYMBOL_GPL(rz_mtu3_32bit_ch_write);
void rz_mtu3_shared_reg_write(struct rz_mtu3_channel *ch, u16 offset, u16 value)
{
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
struct rz_mtu3_priv *priv = mtu->priv_data;
if (rz_mtu3_is_16bit_shared_reg(offset))
writew(value, priv->mmio + offset);
else
writeb((u8)value, priv->mmio + offset);
}
EXPORT_SYMBOL_GPL(rz_mtu3_shared_reg_write);
void rz_mtu3_shared_reg_update_bit(struct rz_mtu3_channel *ch, u16 offset,
u16 pos, u8 val)
{
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
struct rz_mtu3_priv *priv = mtu->priv_data;
unsigned long tmdr, flags;
spin_lock_irqsave(&priv->lock, flags);
tmdr = rz_mtu3_shared_reg_read(ch, offset);
__assign_bit(pos, &tmdr, !!val);
rz_mtu3_shared_reg_write(ch, offset, tmdr);
spin_unlock_irqrestore(&priv->lock, flags);
}
EXPORT_SYMBOL_GPL(rz_mtu3_shared_reg_update_bit);
static u16 rz_mtu3_get_tstr_offset(struct rz_mtu3_channel *ch)
{
u16 offset;
switch (ch->channel_number) {
case RZ_MTU3_CHAN_0:
case RZ_MTU3_CHAN_1:
case RZ_MTU3_CHAN_2:
case RZ_MTU3_CHAN_3:
case RZ_MTU3_CHAN_4:
case RZ_MTU3_CHAN_8:
offset = RZ_MTU3_TSTRA;
break;
case RZ_MTU3_CHAN_5:
offset = RZ_MTU3_TSTR;
break;
case RZ_MTU3_CHAN_6:
case RZ_MTU3_CHAN_7:
offset = RZ_MTU3_TSTRB;
break;
default:
offset = 0;
break;
}
return offset;
}
static u8 rz_mtu3_get_tstr_bit_pos(struct rz_mtu3_channel *ch)
{
u8 bitpos;
switch (ch->channel_number) {
case RZ_MTU3_CHAN_0:
case RZ_MTU3_CHAN_1:
case RZ_MTU3_CHAN_2:
case RZ_MTU3_CHAN_6:
case RZ_MTU3_CHAN_7:
bitpos = ch->channel_number;
break;
case RZ_MTU3_CHAN_3:
bitpos = 6;
break;
case RZ_MTU3_CHAN_4:
bitpos = 7;
break;
case RZ_MTU3_CHAN_5:
bitpos = 2;
break;
case RZ_MTU3_CHAN_8:
bitpos = 3;
break;
default:
bitpos = 0;
break;
}
return bitpos;
}
static void rz_mtu3_start_stop_ch(struct rz_mtu3_channel *ch, bool start)
{
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
struct rz_mtu3_priv *priv = mtu->priv_data;
unsigned long flags, tstr;
u16 offset;
u8 bitpos;
offset = rz_mtu3_get_tstr_offset(ch);
bitpos = rz_mtu3_get_tstr_bit_pos(ch);
/* start stop register shared by multiple timer channels */
spin_lock_irqsave(&priv->lock, flags);
tstr = rz_mtu3_shared_reg_read(ch, offset);
__assign_bit(bitpos, &tstr, start);
rz_mtu3_shared_reg_write(ch, offset, tstr);
spin_unlock_irqrestore(&priv->lock, flags);
}
bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch)
{
struct rz_mtu3 *mtu = dev_get_drvdata(ch->dev->parent);
struct rz_mtu3_priv *priv = mtu->priv_data;
unsigned long flags, tstr;
u16 offset;
u8 bitpos;
offset = rz_mtu3_get_tstr_offset(ch);
bitpos = rz_mtu3_get_tstr_bit_pos(ch);
/* start stop register shared by multiple timer channels */
spin_lock_irqsave(&priv->lock, flags);
tstr = rz_mtu3_shared_reg_read(ch, offset);
spin_unlock_irqrestore(&priv->lock, flags);
return tstr & BIT(bitpos);
}
EXPORT_SYMBOL_GPL(rz_mtu3_is_enabled);
int rz_mtu3_enable(struct rz_mtu3_channel *ch)
{
/* enable channel */
rz_mtu3_start_stop_ch(ch, true);
return 0;
}
EXPORT_SYMBOL_GPL(rz_mtu3_enable);
void rz_mtu3_disable(struct rz_mtu3_channel *ch)
{
/* disable channel */
rz_mtu3_start_stop_ch(ch, false);
}
EXPORT_SYMBOL_GPL(rz_mtu3_disable);
static void rz_mtu3_reset_assert(void *data)
{
struct rz_mtu3 *mtu = dev_get_drvdata(data);
struct rz_mtu3_priv *priv = mtu->priv_data;
mfd_remove_devices(data);
reset_control_assert(priv->rstc);
}
static const struct mfd_cell rz_mtu3_devs[] = {
{
.name = "rz-mtu3-counter",
},
{
.name = "pwm-rz-mtu3",
},
};
static int rz_mtu3_probe(struct platform_device *pdev)
{
struct rz_mtu3_priv *priv;
struct rz_mtu3 *ddata;
unsigned int i;
int ret;
ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
ddata->priv_data = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!ddata->priv_data)
return -ENOMEM;
priv = ddata->priv_data;
priv->mmio = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->mmio))
return PTR_ERR(priv->mmio);
priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(priv->rstc))
return PTR_ERR(priv->rstc);
ddata->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(ddata->clk))
return PTR_ERR(ddata->clk);
reset_control_deassert(priv->rstc);
spin_lock_init(&priv->lock);
platform_set_drvdata(pdev, ddata);
for (i = 0; i < RZ_MTU_NUM_CHANNELS; i++) {
ddata->channels[i].channel_number = i;
ddata->channels[i].is_busy = false;
mutex_init(&ddata->channels[i].lock);
}
ret = mfd_add_devices(&pdev->dev, 0, rz_mtu3_devs,
ARRAY_SIZE(rz_mtu3_devs), NULL, 0, NULL);
if (ret < 0)
goto err_assert;
return devm_add_action_or_reset(&pdev->dev, rz_mtu3_reset_assert,
&pdev->dev);
err_assert:
reset_control_assert(priv->rstc);
return ret;
}
static const struct of_device_id rz_mtu3_of_match[] = {
{ .compatible = "renesas,rz-mtu3", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rz_mtu3_of_match);
static struct platform_driver rz_mtu3_driver = {
.probe = rz_mtu3_probe,
.driver = {
.name = "rz-mtu3",
.of_match_table = rz_mtu3_of_match,
},
};
module_platform_driver(rz_mtu3_driver);
MODULE_AUTHOR("Biju Das <[email protected]>");
MODULE_DESCRIPTION("Renesas RZ/G2L MTU3a Core Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/rz-mtu3.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Free Electrons
*
* Author: Boris BREZILLON <[email protected]>
*
* Allwinner PRCM (Power/Reset/Clock Management) driver
*/
#include <linux/mfd/core.h>
#include <linux/init.h>
#include <linux/of.h>
#define SUN8I_CODEC_ANALOG_BASE 0x1c0
#define SUN8I_CODEC_ANALOG_SIZE 0x4
struct prcm_data {
int nsubdevs;
const struct mfd_cell *subdevs;
};
static const struct resource sun6i_a31_ar100_clk_res[] = {
DEFINE_RES_MEM(0x0, 4)
};
static const struct resource sun6i_a31_apb0_clk_res[] = {
DEFINE_RES_MEM(0xc, 4)
};
static const struct resource sun6i_a31_apb0_gates_clk_res[] = {
DEFINE_RES_MEM(0x28, 4)
};
static const struct resource sun6i_a31_ir_clk_res[] = {
DEFINE_RES_MEM(0x54, 4)
};
static const struct resource sun6i_a31_apb0_rstc_res[] = {
DEFINE_RES_MEM(0xb0, 4)
};
static const struct resource sun8i_codec_analog_res[] = {
DEFINE_RES_MEM(SUN8I_CODEC_ANALOG_BASE, SUN8I_CODEC_ANALOG_SIZE),
};
static const struct mfd_cell sun6i_a31_prcm_subdevs[] = {
{
.name = "sun6i-a31-ar100-clk",
.of_compatible = "allwinner,sun6i-a31-ar100-clk",
.num_resources = ARRAY_SIZE(sun6i_a31_ar100_clk_res),
.resources = sun6i_a31_ar100_clk_res,
},
{
.name = "sun6i-a31-apb0-clk",
.of_compatible = "allwinner,sun6i-a31-apb0-clk",
.num_resources = ARRAY_SIZE(sun6i_a31_apb0_clk_res),
.resources = sun6i_a31_apb0_clk_res,
},
{
.name = "sun6i-a31-apb0-gates-clk",
.of_compatible = "allwinner,sun6i-a31-apb0-gates-clk",
.num_resources = ARRAY_SIZE(sun6i_a31_apb0_gates_clk_res),
.resources = sun6i_a31_apb0_gates_clk_res,
},
{
.name = "sun6i-a31-ir-clk",
.of_compatible = "allwinner,sun4i-a10-mod0-clk",
.num_resources = ARRAY_SIZE(sun6i_a31_ir_clk_res),
.resources = sun6i_a31_ir_clk_res,
},
{
.name = "sun6i-a31-apb0-clock-reset",
.of_compatible = "allwinner,sun6i-a31-clock-reset",
.num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res),
.resources = sun6i_a31_apb0_rstc_res,
},
};
static const struct mfd_cell sun8i_a23_prcm_subdevs[] = {
{
.name = "sun8i-a23-apb0-clk",
.of_compatible = "allwinner,sun8i-a23-apb0-clk",
.num_resources = ARRAY_SIZE(sun6i_a31_apb0_clk_res),
.resources = sun6i_a31_apb0_clk_res,
},
{
.name = "sun6i-a31-apb0-gates-clk",
.of_compatible = "allwinner,sun8i-a23-apb0-gates-clk",
.num_resources = ARRAY_SIZE(sun6i_a31_apb0_gates_clk_res),
.resources = sun6i_a31_apb0_gates_clk_res,
},
{
.name = "sun6i-a31-apb0-clock-reset",
.of_compatible = "allwinner,sun6i-a31-clock-reset",
.num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res),
.resources = sun6i_a31_apb0_rstc_res,
},
{
.name = "sun8i-codec-analog",
.of_compatible = "allwinner,sun8i-a23-codec-analog",
.num_resources = ARRAY_SIZE(sun8i_codec_analog_res),
.resources = sun8i_codec_analog_res,
},
};
static const struct prcm_data sun6i_a31_prcm_data = {
.nsubdevs = ARRAY_SIZE(sun6i_a31_prcm_subdevs),
.subdevs = sun6i_a31_prcm_subdevs,
};
static const struct prcm_data sun8i_a23_prcm_data = {
.nsubdevs = ARRAY_SIZE(sun8i_a23_prcm_subdevs),
.subdevs = sun8i_a23_prcm_subdevs,
};
static const struct of_device_id sun6i_prcm_dt_ids[] = {
{
.compatible = "allwinner,sun6i-a31-prcm",
.data = &sun6i_a31_prcm_data,
},
{
.compatible = "allwinner,sun8i-a23-prcm",
.data = &sun8i_a23_prcm_data,
},
{ /* sentinel */ },
};
static int sun6i_prcm_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
const struct prcm_data *data;
struct resource *res;
int ret;
match = of_match_node(sun6i_prcm_dt_ids, pdev->dev.of_node);
if (!match)
return -EINVAL;
data = match->data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "no prcm memory region provided\n");
return -ENOENT;
}
ret = mfd_add_devices(&pdev->dev, 0, data->subdevs, data->nsubdevs,
res, -1, NULL);
if (ret) {
dev_err(&pdev->dev, "failed to add subdevices\n");
return ret;
}
return 0;
}
static struct platform_driver sun6i_prcm_driver = {
.driver = {
.name = "sun6i-prcm",
.of_match_table = sun6i_prcm_dt_ids,
},
.probe = sun6i_prcm_probe,
};
builtin_platform_driver(sun6i_prcm_driver);
| linux-master | drivers/mfd/sun6i-prcm.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Linux multi-function-device driver (MFD) for the integrated peripherals
* of the VIA VX855 chipset
*
* Copyright (C) 2009 VIA Technologies, Inc.
* Copyright (C) 2010 One Laptop per Child
* Author: Harald Welte <[email protected]>
* All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/mfd/core.h>
/* offset into pci config space indicating the 16bit register containing
* the power management IO space base */
#define VX855_CFG_PMIO_OFFSET 0x88
/* ACPI I/O Space registers */
#define VX855_PMIO_ACPI 0x00
#define VX855_PMIO_ACPI_LEN 0x0b
/* Processor Power Management */
#define VX855_PMIO_PPM 0x10
#define VX855_PMIO_PPM_LEN 0x08
/* General Purpose Power Management */
#define VX855_PMIO_GPPM 0x20
#define VX855_PMIO_R_GPI 0x48
#define VX855_PMIO_R_GPO 0x4c
#define VX855_PMIO_GPPM_LEN 0x33
#define VSPIC_MMIO_SIZE 0x1000
static struct resource vx855_gpio_resources[] = {
{
.flags = IORESOURCE_IO,
},
{
.flags = IORESOURCE_IO,
},
};
static const struct mfd_cell vx855_cells[] = {
{
.name = "vx855_gpio",
.num_resources = ARRAY_SIZE(vx855_gpio_resources),
.resources = vx855_gpio_resources,
/* we must ignore resource conflicts, for reasons outlined in
* the vx855_gpio driver */
.ignore_resource_conflicts = true,
},
};
static int vx855_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
int ret;
u16 gpio_io_offset;
ret = pci_enable_device(pdev);
if (ret)
return -ENODEV;
pci_read_config_word(pdev, VX855_CFG_PMIO_OFFSET, &gpio_io_offset);
if (!gpio_io_offset) {
dev_warn(&pdev->dev,
"BIOS did not assign PMIO base offset?!?\n");
ret = -ENODEV;
goto out;
}
/* mask out the lowest seven bits, as they are always zero, but
* hardware returns them as 0x01 */
gpio_io_offset &= 0xff80;
/* As the region identified here includes many non-GPIO things, we
* only work with the specific registers that concern us. */
vx855_gpio_resources[0].start = gpio_io_offset + VX855_PMIO_R_GPI;
vx855_gpio_resources[0].end = vx855_gpio_resources[0].start + 3;
vx855_gpio_resources[1].start = gpio_io_offset + VX855_PMIO_R_GPO;
vx855_gpio_resources[1].end = vx855_gpio_resources[1].start + 3;
ret = mfd_add_devices(&pdev->dev, -1, vx855_cells, ARRAY_SIZE(vx855_cells),
NULL, 0, NULL);
/* we always return -ENODEV here in order to enable other
* drivers like old, not-yet-platform_device ported i2c-viapro */
return -ENODEV;
out:
pci_disable_device(pdev);
return ret;
}
static void vx855_remove(struct pci_dev *pdev)
{
mfd_remove_devices(&pdev->dev);
pci_disable_device(pdev);
}
static const struct pci_device_id vx855_pci_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855) },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, vx855_pci_tbl);
static struct pci_driver vx855_pci_driver = {
.name = "vx855",
.id_table = vx855_pci_tbl,
.probe = vx855_probe,
.remove = vx855_remove,
};
module_pci_driver(vx855_pci_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Harald Welte <[email protected]>");
MODULE_DESCRIPTION("Driver for the VIA VX855 chipset");
| linux-master | drivers/mfd/vx855.c |
/*
* tps6507x.c -- TPS6507x chip family multi-function driver
*
* Copyright (c) 2010 RidgeRun ([email protected])
*
* Author: Todd Fischer
* [email protected]
*
* Credits:
*
* Using code from wm831x-*.c, wm8400-core, Wolfson Microelectronics PLC.
*
* For licencing details see kernel-base/COPYING
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/of.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tps6507x.h>
static const struct mfd_cell tps6507x_devs[] = {
{
.name = "tps6507x-pmic",
},
{
.name = "tps6507x-ts",
},
};
static int tps6507x_i2c_read_device(struct tps6507x_dev *tps6507x, char reg,
int bytes, void *dest)
{
struct i2c_client *i2c = tps6507x->i2c_client;
struct i2c_msg xfer[2];
int ret;
/* Write register */
xfer[0].addr = i2c->addr;
xfer[0].flags = 0;
xfer[0].len = 1;
xfer[0].buf = ®
/* Read data */
xfer[1].addr = i2c->addr;
xfer[1].flags = I2C_M_RD;
xfer[1].len = bytes;
xfer[1].buf = dest;
ret = i2c_transfer(i2c->adapter, xfer, 2);
if (ret == 2)
ret = 0;
else if (ret >= 0)
ret = -EIO;
return ret;
}
static int tps6507x_i2c_write_device(struct tps6507x_dev *tps6507x, char reg,
int bytes, void *src)
{
struct i2c_client *i2c = tps6507x->i2c_client;
/* we add 1 byte for device register */
u8 msg[TPS6507X_MAX_REGISTER + 1];
int ret;
if (bytes > TPS6507X_MAX_REGISTER)
return -EINVAL;
msg[0] = reg;
memcpy(&msg[1], src, bytes);
ret = i2c_master_send(i2c, msg, bytes + 1);
if (ret < 0)
return ret;
if (ret != bytes + 1)
return -EIO;
return 0;
}
static int tps6507x_i2c_probe(struct i2c_client *i2c)
{
struct tps6507x_dev *tps6507x;
tps6507x = devm_kzalloc(&i2c->dev, sizeof(struct tps6507x_dev),
GFP_KERNEL);
if (tps6507x == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, tps6507x);
tps6507x->dev = &i2c->dev;
tps6507x->i2c_client = i2c;
tps6507x->read_dev = tps6507x_i2c_read_device;
tps6507x->write_dev = tps6507x_i2c_write_device;
return devm_mfd_add_devices(tps6507x->dev, -1, tps6507x_devs,
ARRAY_SIZE(tps6507x_devs), NULL, 0, NULL);
}
static const struct i2c_device_id tps6507x_i2c_id[] = {
{ "tps6507x", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tps6507x_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id tps6507x_of_match[] = {
{.compatible = "ti,tps6507x", },
{},
};
MODULE_DEVICE_TABLE(of, tps6507x_of_match);
#endif
static struct i2c_driver tps6507x_i2c_driver = {
.driver = {
.name = "tps6507x",
.of_match_table = of_match_ptr(tps6507x_of_match),
},
.probe = tps6507x_i2c_probe,
.id_table = tps6507x_i2c_id,
};
static int __init tps6507x_i2c_init(void)
{
return i2c_add_driver(&tps6507x_i2c_driver);
}
/* init early so consumer devices can complete system boot */
subsys_initcall(tps6507x_i2c_init);
static void __exit tps6507x_i2c_exit(void)
{
i2c_del_driver(&tps6507x_i2c_driver);
}
module_exit(tps6507x_i2c_exit);
MODULE_DESCRIPTION("TPS6507x chip family multi-function driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/tps6507x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Core functions for TI TPS65912x PMICs
*
* Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/
* Andrew F. Davis <[email protected]>
*
* Based on the TPS65218 driver and the previous TPS65912 driver by
* Margarita Olaya Cabrera <[email protected]>
*/
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/mfd/tps65912.h>
static const struct mfd_cell tps65912_cells[] = {
{ .name = "tps65912-regulator", },
{ .name = "tps65912-gpio", },
};
static const struct regmap_irq tps65912_irqs[] = {
/* INT_STS IRQs */
REGMAP_IRQ_REG(TPS65912_IRQ_PWRHOLD_F, 0, TPS65912_INT_STS_PWRHOLD_F),
REGMAP_IRQ_REG(TPS65912_IRQ_VMON, 0, TPS65912_INT_STS_VMON),
REGMAP_IRQ_REG(TPS65912_IRQ_PWRON, 0, TPS65912_INT_STS_PWRON),
REGMAP_IRQ_REG(TPS65912_IRQ_PWRON_LP, 0, TPS65912_INT_STS_PWRON_LP),
REGMAP_IRQ_REG(TPS65912_IRQ_PWRHOLD_R, 0, TPS65912_INT_STS_PWRHOLD_R),
REGMAP_IRQ_REG(TPS65912_IRQ_HOTDIE, 0, TPS65912_INT_STS_HOTDIE),
REGMAP_IRQ_REG(TPS65912_IRQ_GPIO1_R, 0, TPS65912_INT_STS_GPIO1_R),
REGMAP_IRQ_REG(TPS65912_IRQ_GPIO1_F, 0, TPS65912_INT_STS_GPIO1_F),
/* INT_STS2 IRQs */
REGMAP_IRQ_REG(TPS65912_IRQ_GPIO2_R, 1, TPS65912_INT_STS2_GPIO2_R),
REGMAP_IRQ_REG(TPS65912_IRQ_GPIO2_F, 1, TPS65912_INT_STS2_GPIO2_F),
REGMAP_IRQ_REG(TPS65912_IRQ_GPIO3_R, 1, TPS65912_INT_STS2_GPIO3_R),
REGMAP_IRQ_REG(TPS65912_IRQ_GPIO3_F, 1, TPS65912_INT_STS2_GPIO3_F),
REGMAP_IRQ_REG(TPS65912_IRQ_GPIO4_R, 1, TPS65912_INT_STS2_GPIO4_R),
REGMAP_IRQ_REG(TPS65912_IRQ_GPIO4_F, 1, TPS65912_INT_STS2_GPIO4_F),
REGMAP_IRQ_REG(TPS65912_IRQ_GPIO5_R, 1, TPS65912_INT_STS2_GPIO5_R),
REGMAP_IRQ_REG(TPS65912_IRQ_GPIO5_F, 1, TPS65912_INT_STS2_GPIO5_F),
/* INT_STS3 IRQs */
REGMAP_IRQ_REG(TPS65912_IRQ_PGOOD_DCDC1, 2, TPS65912_INT_STS3_PGOOD_DCDC1),
REGMAP_IRQ_REG(TPS65912_IRQ_PGOOD_DCDC2, 2, TPS65912_INT_STS3_PGOOD_DCDC2),
REGMAP_IRQ_REG(TPS65912_IRQ_PGOOD_DCDC3, 2, TPS65912_INT_STS3_PGOOD_DCDC3),
REGMAP_IRQ_REG(TPS65912_IRQ_PGOOD_DCDC4, 2, TPS65912_INT_STS3_PGOOD_DCDC4),
REGMAP_IRQ_REG(TPS65912_IRQ_PGOOD_LDO1, 2, TPS65912_INT_STS3_PGOOD_LDO1),
REGMAP_IRQ_REG(TPS65912_IRQ_PGOOD_LDO2, 2, TPS65912_INT_STS3_PGOOD_LDO2),
REGMAP_IRQ_REG(TPS65912_IRQ_PGOOD_LDO3, 2, TPS65912_INT_STS3_PGOOD_LDO3),
REGMAP_IRQ_REG(TPS65912_IRQ_PGOOD_LDO4, 2, TPS65912_INT_STS3_PGOOD_LDO4),
/* INT_STS4 IRQs */
REGMAP_IRQ_REG(TPS65912_IRQ_PGOOD_LDO5, 3, TPS65912_INT_STS4_PGOOD_LDO5),
REGMAP_IRQ_REG(TPS65912_IRQ_PGOOD_LDO6, 3, TPS65912_INT_STS4_PGOOD_LDO6),
REGMAP_IRQ_REG(TPS65912_IRQ_PGOOD_LDO7, 3, TPS65912_INT_STS4_PGOOD_LDO7),
REGMAP_IRQ_REG(TPS65912_IRQ_PGOOD_LDO8, 3, TPS65912_INT_STS4_PGOOD_LDO8),
REGMAP_IRQ_REG(TPS65912_IRQ_PGOOD_LDO9, 3, TPS65912_INT_STS4_PGOOD_LDO9),
REGMAP_IRQ_REG(TPS65912_IRQ_PGOOD_LDO10, 3, TPS65912_INT_STS4_PGOOD_LDO10),
};
static struct regmap_irq_chip tps65912_irq_chip = {
.name = "tps65912",
.irqs = tps65912_irqs,
.num_irqs = ARRAY_SIZE(tps65912_irqs),
.num_regs = 4,
.irq_reg_stride = 2,
.mask_base = TPS65912_INT_MSK,
.status_base = TPS65912_INT_STS,
.ack_base = TPS65912_INT_STS,
.init_ack_masked = true,
};
static const struct regmap_range tps65912_yes_ranges[] = {
regmap_reg_range(TPS65912_INT_STS, TPS65912_GPIO5),
};
static const struct regmap_access_table tps65912_volatile_table = {
.yes_ranges = tps65912_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(tps65912_yes_ranges),
};
const struct regmap_config tps65912_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.volatile_table = &tps65912_volatile_table,
};
EXPORT_SYMBOL_GPL(tps65912_regmap_config);
int tps65912_device_init(struct tps65912 *tps)
{
int ret;
ret = regmap_add_irq_chip(tps->regmap, tps->irq, IRQF_ONESHOT, 0,
&tps65912_irq_chip, &tps->irq_data);
if (ret)
return ret;
ret = mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO, tps65912_cells,
ARRAY_SIZE(tps65912_cells), NULL, 0,
regmap_irq_get_domain(tps->irq_data));
if (ret) {
regmap_del_irq_chip(tps->irq, tps->irq_data);
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(tps65912_device_init);
void tps65912_device_exit(struct tps65912 *tps)
{
regmap_del_irq_chip(tps->irq, tps->irq_data);
}
EXPORT_SYMBOL_GPL(tps65912_device_exit);
MODULE_AUTHOR("Andrew F. Davis <[email protected]>");
MODULE_DESCRIPTION("TPS65912x MFD Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/tps65912-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
*
* Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com
* Author: Keshava Munegowda <[email protected]>
* Author: Roger Quadros <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/platform_data/usb-omap.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/err.h>
#include "omap-usb.h"
#define USBHS_DRIVER_NAME "usbhs_omap"
#define OMAP_EHCI_DEVICE "ehci-omap"
#define OMAP_OHCI_DEVICE "ohci-omap3"
/* OMAP USBHOST Register addresses */
/* UHH Register Set */
#define OMAP_UHH_REVISION (0x00)
#define OMAP_UHH_SYSCONFIG (0x10)
#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
#define OMAP_UHH_SYSSTATUS (0x14)
#define OMAP_UHH_HOSTCONFIG (0x40)
#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
/* OMAP4-specific defines */
#define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
#define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
#define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
#define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
#define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
#define OMAP4_P1_MODE_CLEAR (3 << 16)
#define OMAP4_P1_MODE_TLL (1 << 16)
#define OMAP4_P1_MODE_HSIC (3 << 16)
#define OMAP4_P2_MODE_CLEAR (3 << 18)
#define OMAP4_P2_MODE_TLL (1 << 18)
#define OMAP4_P2_MODE_HSIC (3 << 18)
#define OMAP_UHH_DEBUG_CSR (0x44)
/* Values of UHH_REVISION - Note: these are not given in the TRM */
#define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
#define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
#define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
#define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
#define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
#define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
#define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
struct usbhs_hcd_omap {
int nports;
struct clk **utmi_clk;
struct clk **hsic60m_clk;
struct clk **hsic480m_clk;
struct clk *xclk60mhsp1_ck;
struct clk *xclk60mhsp2_ck;
struct clk *utmi_p1_gfclk;
struct clk *utmi_p2_gfclk;
struct clk *init_60m_fclk;
struct clk *ehci_logic_fck;
void __iomem *uhh_base;
struct usbhs_omap_platform_data *pdata;
u32 usbhs_rev;
};
/*-------------------------------------------------------------------------*/
static const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
static u64 usbhs_dmamask = DMA_BIT_MASK(32);
/*-------------------------------------------------------------------------*/
static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
{
writel_relaxed(val, base + reg);
}
static inline u32 usbhs_read(void __iomem *base, u32 reg)
{
return readl_relaxed(base + reg);
}
/*-------------------------------------------------------------------------*/
/*
* Map 'enum usbhs_omap_port_mode' found in <linux/platform_data/usb-omap.h>
* to the device tree binding portN-mode found in
* 'Documentation/devicetree/bindings/mfd/omap-usb-host.txt'
*/
static const char * const port_modes[] = {
[OMAP_USBHS_PORT_MODE_UNUSED] = "",
[OMAP_EHCI_PORT_MODE_PHY] = "ehci-phy",
[OMAP_EHCI_PORT_MODE_TLL] = "ehci-tll",
[OMAP_EHCI_PORT_MODE_HSIC] = "ehci-hsic",
[OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0] = "ohci-phy-6pin-datse0",
[OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM] = "ohci-phy-6pin-dpdm",
[OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0] = "ohci-phy-3pin-datse0",
[OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM] = "ohci-phy-4pin-dpdm",
[OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0] = "ohci-tll-6pin-datse0",
[OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM] = "ohci-tll-6pin-dpdm",
[OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0] = "ohci-tll-3pin-datse0",
[OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM] = "ohci-tll-4pin-dpdm",
[OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0] = "ohci-tll-2pin-datse0",
[OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM] = "ohci-tll-2pin-dpdm",
};
static struct platform_device *omap_usbhs_alloc_child(const char *name,
struct resource *res, int num_resources, void *pdata,
size_t pdata_size, struct device *dev)
{
struct platform_device *child;
int ret;
child = platform_device_alloc(name, 0);
if (!child) {
dev_err(dev, "platform_device_alloc %s failed\n", name);
goto err_end;
}
ret = platform_device_add_resources(child, res, num_resources);
if (ret) {
dev_err(dev, "platform_device_add_resources failed\n");
goto err_alloc;
}
ret = platform_device_add_data(child, pdata, pdata_size);
if (ret) {
dev_err(dev, "platform_device_add_data failed\n");
goto err_alloc;
}
child->dev.dma_mask = &usbhs_dmamask;
dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
child->dev.parent = dev;
ret = platform_device_add(child);
if (ret) {
dev_err(dev, "platform_device_add failed\n");
goto err_alloc;
}
return child;
err_alloc:
platform_device_put(child);
err_end:
return NULL;
}
static int omap_usbhs_alloc_children(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct usbhs_omap_platform_data *pdata = dev_get_platdata(dev);
struct platform_device *ehci;
struct platform_device *ohci;
struct resource *res;
struct resource resources[2];
int ret;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
if (!res) {
dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
ret = -ENODEV;
goto err_end;
}
resources[0] = *res;
res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
if (!res) {
dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
ret = -ENODEV;
goto err_end;
}
resources[1] = *res;
ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, pdata,
sizeof(*pdata), dev);
if (!ehci) {
dev_err(dev, "omap_usbhs_alloc_child failed\n");
ret = -ENOMEM;
goto err_end;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
if (!res) {
dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
ret = -ENODEV;
goto err_ehci;
}
resources[0] = *res;
res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
if (!res) {
dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
ret = -ENODEV;
goto err_ehci;
}
resources[1] = *res;
ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, pdata,
sizeof(*pdata), dev);
if (!ohci) {
dev_err(dev, "omap_usbhs_alloc_child failed\n");
ret = -ENOMEM;
goto err_ehci;
}
return 0;
err_ehci:
platform_device_unregister(ehci);
err_end:
return ret;
}
static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
{
switch (pmode) {
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
return true;
default:
return false;
}
}
static int usbhs_runtime_resume(struct device *dev)
{
struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
struct usbhs_omap_platform_data *pdata = omap->pdata;
int i, r;
dev_dbg(dev, "usbhs_runtime_resume\n");
omap_tll_enable(pdata);
if (!IS_ERR(omap->ehci_logic_fck))
clk_prepare_enable(omap->ehci_logic_fck);
for (i = 0; i < omap->nports; i++) {
switch (pdata->port_mode[i]) {
case OMAP_EHCI_PORT_MODE_HSIC:
if (!IS_ERR(omap->hsic60m_clk[i])) {
r = clk_prepare_enable(omap->hsic60m_clk[i]);
if (r) {
dev_err(dev,
"Can't enable port %d hsic60m clk:%d\n",
i, r);
}
}
if (!IS_ERR(omap->hsic480m_clk[i])) {
r = clk_prepare_enable(omap->hsic480m_clk[i]);
if (r) {
dev_err(dev,
"Can't enable port %d hsic480m clk:%d\n",
i, r);
}
}
fallthrough; /* as HSIC mode needs utmi_clk */
case OMAP_EHCI_PORT_MODE_TLL:
if (!IS_ERR(omap->utmi_clk[i])) {
r = clk_prepare_enable(omap->utmi_clk[i]);
if (r) {
dev_err(dev,
"Can't enable port %d clk : %d\n",
i, r);
}
}
break;
default:
break;
}
}
return 0;
}
static int usbhs_runtime_suspend(struct device *dev)
{
struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
struct usbhs_omap_platform_data *pdata = omap->pdata;
int i;
dev_dbg(dev, "usbhs_runtime_suspend\n");
for (i = 0; i < omap->nports; i++) {
switch (pdata->port_mode[i]) {
case OMAP_EHCI_PORT_MODE_HSIC:
if (!IS_ERR(omap->hsic60m_clk[i]))
clk_disable_unprepare(omap->hsic60m_clk[i]);
if (!IS_ERR(omap->hsic480m_clk[i]))
clk_disable_unprepare(omap->hsic480m_clk[i]);
fallthrough; /* as utmi_clks were used in HSIC mode */
case OMAP_EHCI_PORT_MODE_TLL:
if (!IS_ERR(omap->utmi_clk[i]))
clk_disable_unprepare(omap->utmi_clk[i]);
break;
default:
break;
}
}
if (!IS_ERR(omap->ehci_logic_fck))
clk_disable_unprepare(omap->ehci_logic_fck);
omap_tll_disable(pdata);
return 0;
}
static unsigned omap_usbhs_rev1_hostconfig(struct usbhs_hcd_omap *omap,
unsigned reg)
{
struct usbhs_omap_platform_data *pdata = omap->pdata;
int i;
for (i = 0; i < omap->nports; i++) {
switch (pdata->port_mode[i]) {
case OMAP_USBHS_PORT_MODE_UNUSED:
reg &= ~(OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS << i);
break;
case OMAP_EHCI_PORT_MODE_PHY:
if (pdata->single_ulpi_bypass)
break;
if (i == 0)
reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
else
reg &= ~(OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
<< (i-1));
break;
default:
if (pdata->single_ulpi_bypass)
break;
if (i == 0)
reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
else
reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
<< (i-1);
break;
}
}
if (pdata->single_ulpi_bypass) {
/* bypass ULPI only if none of the ports use PHY mode */
reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
for (i = 0; i < omap->nports; i++) {
if (is_ehci_phy_mode(pdata->port_mode[i])) {
reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
break;
}
}
}
return reg;
}
static unsigned omap_usbhs_rev2_hostconfig(struct usbhs_hcd_omap *omap,
unsigned reg)
{
struct usbhs_omap_platform_data *pdata = omap->pdata;
int i;
for (i = 0; i < omap->nports; i++) {
/* Clear port mode fields for PHY mode */
reg &= ~(OMAP4_P1_MODE_CLEAR << 2 * i);
if (is_ehci_tll_mode(pdata->port_mode[i]) ||
(is_ohci_port(pdata->port_mode[i])))
reg |= OMAP4_P1_MODE_TLL << 2 * i;
else if (is_ehci_hsic_mode(pdata->port_mode[i]))
reg |= OMAP4_P1_MODE_HSIC << 2 * i;
}
return reg;
}
static void omap_usbhs_init(struct device *dev)
{
struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
unsigned reg;
dev_dbg(dev, "starting TI HSUSB Controller\n");
pm_runtime_get_sync(dev);
reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
/* setup ULPI bypass and burst configurations */
reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
| OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
| OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
switch (omap->usbhs_rev) {
case OMAP_USBHS_REV1:
reg = omap_usbhs_rev1_hostconfig(omap, reg);
break;
case OMAP_USBHS_REV2:
reg = omap_usbhs_rev2_hostconfig(omap, reg);
break;
default: /* newer revisions */
reg = omap_usbhs_rev2_hostconfig(omap, reg);
break;
}
usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
pm_runtime_put_sync(dev);
}
static int usbhs_omap_get_dt_pdata(struct device *dev,
struct usbhs_omap_platform_data *pdata)
{
int ret, i;
struct device_node *node = dev->of_node;
ret = of_property_read_u32(node, "num-ports", &pdata->nports);
if (ret)
pdata->nports = 0;
if (pdata->nports > OMAP3_HS_USB_PORTS) {
dev_warn(dev, "Too many num_ports <%d> in device tree. Max %d\n",
pdata->nports, OMAP3_HS_USB_PORTS);
return -ENODEV;
}
/* get port modes */
for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
char prop[11];
const char *mode;
pdata->port_mode[i] = OMAP_USBHS_PORT_MODE_UNUSED;
snprintf(prop, sizeof(prop), "port%d-mode", i + 1);
ret = of_property_read_string(node, prop, &mode);
if (ret < 0)
continue;
/* get 'enum usbhs_omap_port_mode' from port mode string */
ret = match_string(port_modes, ARRAY_SIZE(port_modes), mode);
if (ret < 0) {
dev_warn(dev, "Invalid port%d-mode \"%s\" in device tree\n",
i, mode);
return -ENODEV;
}
dev_dbg(dev, "port%d-mode: %s -> %d\n", i, mode, ret);
pdata->port_mode[i] = ret;
}
/* get flags */
pdata->single_ulpi_bypass = of_property_read_bool(node,
"single-ulpi-bypass");
return 0;
}
static const struct of_device_id usbhs_child_match_table[] = {
{ .compatible = "ti,ehci-omap", },
{ .compatible = "ti,ohci-omap3", },
{ }
};
/**
* usbhs_omap_probe - initialize TI-based HCDs
*
* Allocates basic resources for this USB host controller.
*
* @pdev: Pointer to this device's platform device structure
*/
static int usbhs_omap_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct usbhs_omap_platform_data *pdata = dev_get_platdata(dev);
struct usbhs_hcd_omap *omap;
int ret = 0;
int i;
bool need_logic_fck;
if (dev->of_node) {
/* For DT boot we populate platform data from OF node */
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
ret = usbhs_omap_get_dt_pdata(dev, pdata);
if (ret)
return ret;
dev->platform_data = pdata;
}
if (!pdata) {
dev_err(dev, "Missing platform data\n");
return -ENODEV;
}
if (pdata->nports > OMAP3_HS_USB_PORTS) {
dev_info(dev, "Too many num_ports <%d> in platform_data. Max %d\n",
pdata->nports, OMAP3_HS_USB_PORTS);
return -ENODEV;
}
omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
if (!omap) {
dev_err(dev, "Memory allocation failed\n");
return -ENOMEM;
}
omap->uhh_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(omap->uhh_base))
return PTR_ERR(omap->uhh_base);
omap->pdata = pdata;
/* Initialize the TLL subsystem */
omap_tll_init(pdata);
pm_runtime_enable(dev);
platform_set_drvdata(pdev, omap);
pm_runtime_get_sync(dev);
omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
/* we need to call runtime suspend before we update omap->nports
* to prevent unbalanced clk_disable()
*/
pm_runtime_put_sync(dev);
/*
* If platform data contains nports then use that
* else make out number of ports from USBHS revision
*/
if (pdata->nports) {
omap->nports = pdata->nports;
} else {
switch (omap->usbhs_rev) {
case OMAP_USBHS_REV1:
omap->nports = 3;
break;
case OMAP_USBHS_REV2:
omap->nports = 2;
break;
default:
omap->nports = OMAP3_HS_USB_PORTS;
dev_dbg(dev,
"USB HOST Rev:0x%x not recognized, assuming %d ports\n",
omap->usbhs_rev, omap->nports);
break;
}
pdata->nports = omap->nports;
}
i = sizeof(struct clk *) * omap->nports;
omap->utmi_clk = devm_kzalloc(dev, i, GFP_KERNEL);
omap->hsic480m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
omap->hsic60m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
if (!omap->utmi_clk || !omap->hsic480m_clk || !omap->hsic60m_clk) {
dev_err(dev, "Memory allocation failed\n");
ret = -ENOMEM;
goto err_mem;
}
/* Set all clocks as invalid to begin with */
omap->ehci_logic_fck = ERR_PTR(-ENODEV);
omap->init_60m_fclk = ERR_PTR(-ENODEV);
omap->utmi_p1_gfclk = ERR_PTR(-ENODEV);
omap->utmi_p2_gfclk = ERR_PTR(-ENODEV);
omap->xclk60mhsp1_ck = ERR_PTR(-ENODEV);
omap->xclk60mhsp2_ck = ERR_PTR(-ENODEV);
for (i = 0; i < omap->nports; i++) {
omap->utmi_clk[i] = ERR_PTR(-ENODEV);
omap->hsic480m_clk[i] = ERR_PTR(-ENODEV);
omap->hsic60m_clk[i] = ERR_PTR(-ENODEV);
}
/* for OMAP3 i.e. USBHS REV1 */
if (omap->usbhs_rev == OMAP_USBHS_REV1) {
need_logic_fck = false;
for (i = 0; i < omap->nports; i++) {
if (is_ehci_phy_mode(pdata->port_mode[i]) ||
is_ehci_tll_mode(pdata->port_mode[i]) ||
is_ehci_hsic_mode(pdata->port_mode[i]))
need_logic_fck |= true;
}
if (need_logic_fck) {
omap->ehci_logic_fck = devm_clk_get(dev,
"usbhost_120m_fck");
if (IS_ERR(omap->ehci_logic_fck)) {
ret = PTR_ERR(omap->ehci_logic_fck);
dev_err(dev, "usbhost_120m_fck failed:%d\n",
ret);
goto err_mem;
}
}
goto initialize;
}
/* for OMAP4+ i.e. USBHS REV2+ */
omap->utmi_p1_gfclk = devm_clk_get(dev, "utmi_p1_gfclk");
if (IS_ERR(omap->utmi_p1_gfclk)) {
ret = PTR_ERR(omap->utmi_p1_gfclk);
dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
goto err_mem;
}
omap->utmi_p2_gfclk = devm_clk_get(dev, "utmi_p2_gfclk");
if (IS_ERR(omap->utmi_p2_gfclk)) {
ret = PTR_ERR(omap->utmi_p2_gfclk);
dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
goto err_mem;
}
omap->xclk60mhsp1_ck = devm_clk_get(dev, "refclk_60m_ext_p1");
if (IS_ERR(omap->xclk60mhsp1_ck)) {
ret = PTR_ERR(omap->xclk60mhsp1_ck);
dev_err(dev, "refclk_60m_ext_p1 failed error:%d\n", ret);
goto err_mem;
}
omap->xclk60mhsp2_ck = devm_clk_get(dev, "refclk_60m_ext_p2");
if (IS_ERR(omap->xclk60mhsp2_ck)) {
ret = PTR_ERR(omap->xclk60mhsp2_ck);
dev_err(dev, "refclk_60m_ext_p2 failed error:%d\n", ret);
goto err_mem;
}
omap->init_60m_fclk = devm_clk_get(dev, "refclk_60m_int");
if (IS_ERR(omap->init_60m_fclk)) {
ret = PTR_ERR(omap->init_60m_fclk);
dev_err(dev, "refclk_60m_int failed error:%d\n", ret);
goto err_mem;
}
for (i = 0; i < omap->nports; i++) {
char clkname[30];
/* clock names are indexed from 1*/
snprintf(clkname, sizeof(clkname),
"usb_host_hs_utmi_p%d_clk", i + 1);
/* If a clock is not found we won't bail out as not all
* platforms have all clocks and we can function without
* them
*/
omap->utmi_clk[i] = devm_clk_get(dev, clkname);
if (IS_ERR(omap->utmi_clk[i])) {
ret = PTR_ERR(omap->utmi_clk[i]);
dev_err(dev, "Failed to get clock : %s : %d\n",
clkname, ret);
goto err_mem;
}
snprintf(clkname, sizeof(clkname),
"usb_host_hs_hsic480m_p%d_clk", i + 1);
omap->hsic480m_clk[i] = devm_clk_get(dev, clkname);
if (IS_ERR(omap->hsic480m_clk[i])) {
ret = PTR_ERR(omap->hsic480m_clk[i]);
dev_err(dev, "Failed to get clock : %s : %d\n",
clkname, ret);
goto err_mem;
}
snprintf(clkname, sizeof(clkname),
"usb_host_hs_hsic60m_p%d_clk", i + 1);
omap->hsic60m_clk[i] = devm_clk_get(dev, clkname);
if (IS_ERR(omap->hsic60m_clk[i])) {
ret = PTR_ERR(omap->hsic60m_clk[i]);
dev_err(dev, "Failed to get clock : %s : %d\n",
clkname, ret);
goto err_mem;
}
}
if (is_ehci_phy_mode(pdata->port_mode[0])) {
ret = clk_set_parent(omap->utmi_p1_gfclk,
omap->xclk60mhsp1_ck);
if (ret != 0) {
dev_err(dev, "xclk60mhsp1_ck set parent failed: %d\n",
ret);
goto err_mem;
}
} else if (is_ehci_tll_mode(pdata->port_mode[0])) {
ret = clk_set_parent(omap->utmi_p1_gfclk,
omap->init_60m_fclk);
if (ret != 0) {
dev_err(dev, "P0 init_60m_fclk set parent failed: %d\n",
ret);
goto err_mem;
}
}
if (is_ehci_phy_mode(pdata->port_mode[1])) {
ret = clk_set_parent(omap->utmi_p2_gfclk,
omap->xclk60mhsp2_ck);
if (ret != 0) {
dev_err(dev, "xclk60mhsp2_ck set parent failed: %d\n",
ret);
goto err_mem;
}
} else if (is_ehci_tll_mode(pdata->port_mode[1])) {
ret = clk_set_parent(omap->utmi_p2_gfclk,
omap->init_60m_fclk);
if (ret != 0) {
dev_err(dev, "P1 init_60m_fclk set parent failed: %d\n",
ret);
goto err_mem;
}
}
initialize:
omap_usbhs_init(dev);
if (dev->of_node) {
ret = of_platform_populate(dev->of_node,
usbhs_child_match_table, NULL, dev);
if (ret) {
dev_err(dev, "Failed to create DT children: %d\n", ret);
goto err_mem;
}
} else {
ret = omap_usbhs_alloc_children(pdev);
if (ret) {
dev_err(dev, "omap_usbhs_alloc_children failed: %d\n",
ret);
goto err_mem;
}
}
return 0;
err_mem:
pm_runtime_disable(dev);
return ret;
}
static int usbhs_omap_remove_child(struct device *dev, void *data)
{
dev_info(dev, "unregistering\n");
platform_device_unregister(to_platform_device(dev));
return 0;
}
/**
* usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
* @pdev: USB Host Controller being removed
*
* Reverses the effect of usbhs_omap_probe().
*/
static int usbhs_omap_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
/* remove children */
device_for_each_child(&pdev->dev, NULL, usbhs_omap_remove_child);
return 0;
}
static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
.runtime_suspend = usbhs_runtime_suspend,
.runtime_resume = usbhs_runtime_resume,
};
static const struct of_device_id usbhs_omap_dt_ids[] = {
{ .compatible = "ti,usbhs-host" },
{ }
};
MODULE_DEVICE_TABLE(of, usbhs_omap_dt_ids);
static struct platform_driver usbhs_omap_driver = {
.driver = {
.name = usbhs_driver_name,
.pm = &usbhsomap_dev_pm_ops,
.of_match_table = usbhs_omap_dt_ids,
},
.probe = usbhs_omap_probe,
.remove = usbhs_omap_remove,
};
MODULE_AUTHOR("Keshava Munegowda <[email protected]>");
MODULE_AUTHOR("Roger Quadros <[email protected]>");
MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
static int omap_usbhs_drvinit(void)
{
return platform_driver_register(&usbhs_omap_driver);
}
/*
* init before ehci and ohci drivers;
* The usbhs core driver should be initialized much before
* the omap ehci and ohci probe functions are called.
* This usbhs core driver should be initialized after
* usb tll driver
*/
fs_initcall_sync(omap_usbhs_drvinit);
static void omap_usbhs_drvexit(void)
{
platform_driver_unregister(&usbhs_omap_driver);
}
module_exit(omap_usbhs_drvexit);
| linux-master | drivers/mfd/omap-usb-host.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* I2C bus interface to Cirrus Logic Madera codecs
*
* Copyright (C) 2015-2018 Cirrus Logic
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/mfd/madera/core.h>
#include "madera.h"
static int madera_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
struct madera *madera;
const struct regmap_config *regmap_16bit_config = NULL;
const struct regmap_config *regmap_32bit_config = NULL;
const void *of_data;
unsigned long type;
const char *name;
int ret;
of_data = of_device_get_match_data(&i2c->dev);
if (of_data)
type = (unsigned long)of_data;
else
type = id->driver_data;
switch (type) {
case CS47L15:
if (IS_ENABLED(CONFIG_MFD_CS47L15)) {
regmap_16bit_config = &cs47l15_16bit_i2c_regmap;
regmap_32bit_config = &cs47l15_32bit_i2c_regmap;
}
break;
case CS47L35:
if (IS_ENABLED(CONFIG_MFD_CS47L35)) {
regmap_16bit_config = &cs47l35_16bit_i2c_regmap;
regmap_32bit_config = &cs47l35_32bit_i2c_regmap;
}
break;
case CS47L85:
case WM1840:
if (IS_ENABLED(CONFIG_MFD_CS47L85)) {
regmap_16bit_config = &cs47l85_16bit_i2c_regmap;
regmap_32bit_config = &cs47l85_32bit_i2c_regmap;
}
break;
case CS47L90:
case CS47L91:
if (IS_ENABLED(CONFIG_MFD_CS47L90)) {
regmap_16bit_config = &cs47l90_16bit_i2c_regmap;
regmap_32bit_config = &cs47l90_32bit_i2c_regmap;
}
break;
case CS42L92:
case CS47L92:
case CS47L93:
if (IS_ENABLED(CONFIG_MFD_CS47L92)) {
regmap_16bit_config = &cs47l92_16bit_i2c_regmap;
regmap_32bit_config = &cs47l92_32bit_i2c_regmap;
}
break;
default:
dev_err(&i2c->dev,
"Unknown Madera I2C device type %ld\n", type);
return -EINVAL;
}
name = madera_name_from_type(type);
if (!regmap_16bit_config) {
/* it's polite to say which codec isn't built into the kernel */
dev_err(&i2c->dev,
"Kernel does not include support for %s\n", name);
return -EINVAL;
}
madera = devm_kzalloc(&i2c->dev, sizeof(*madera), GFP_KERNEL);
if (!madera)
return -ENOMEM;
madera->regmap = devm_regmap_init_i2c(i2c, regmap_16bit_config);
if (IS_ERR(madera->regmap)) {
ret = PTR_ERR(madera->regmap);
dev_err(&i2c->dev,
"Failed to allocate 16-bit register map: %d\n", ret);
return ret;
}
madera->regmap_32bit = devm_regmap_init_i2c(i2c, regmap_32bit_config);
if (IS_ERR(madera->regmap_32bit)) {
ret = PTR_ERR(madera->regmap_32bit);
dev_err(&i2c->dev,
"Failed to allocate 32-bit register map: %d\n", ret);
return ret;
}
madera->type = type;
madera->type_name = name;
madera->dev = &i2c->dev;
madera->irq = i2c->irq;
return madera_dev_init(madera);
}
static void madera_i2c_remove(struct i2c_client *i2c)
{
struct madera *madera = dev_get_drvdata(&i2c->dev);
madera_dev_exit(madera);
}
static const struct i2c_device_id madera_i2c_id[] = {
{ "cs47l15", CS47L15 },
{ "cs47l35", CS47L35 },
{ "cs47l85", CS47L85 },
{ "cs47l90", CS47L90 },
{ "cs47l91", CS47L91 },
{ "cs42l92", CS42L92 },
{ "cs47l92", CS47L92 },
{ "cs47l93", CS47L93 },
{ "wm1840", WM1840 },
{ }
};
MODULE_DEVICE_TABLE(i2c, madera_i2c_id);
static struct i2c_driver madera_i2c_driver = {
.driver = {
.name = "madera",
.pm = &madera_pm_ops,
.of_match_table = of_match_ptr(madera_of_match),
},
.probe = madera_i2c_probe,
.remove = madera_i2c_remove,
.id_table = madera_i2c_id,
};
module_i2c_driver(madera_i2c_driver);
MODULE_DESCRIPTION("Madera I2C bus interface");
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/madera-i2c.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) STMicroelectronics 2018
// Author: Pascal Paillet <[email protected]>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mfd/stpmic1.h>
#include <linux/module.h>
#include <linux/reboot.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pm_wakeirq.h>
#include <linux/regmap.h>
#include <dt-bindings/mfd/st,stpmic1.h>
#define STPMIC1_MAIN_IRQ 0
static const struct regmap_range stpmic1_readable_ranges[] = {
regmap_reg_range(TURN_ON_SR, VERSION_SR),
regmap_reg_range(MAIN_CR, LDO6_STDBY_CR),
regmap_reg_range(BST_SW_CR, BST_SW_CR),
regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4),
regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
regmap_reg_range(INT_MASK_R1, INT_MASK_R4),
regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4),
regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4),
regmap_reg_range(INT_SRC_R1, INT_SRC_R1),
};
static const struct regmap_range stpmic1_writeable_ranges[] = {
regmap_reg_range(MAIN_CR, LDO6_STDBY_CR),
regmap_reg_range(BST_SW_CR, BST_SW_CR),
regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4),
regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4),
};
static const struct regmap_range stpmic1_volatile_ranges[] = {
regmap_reg_range(TURN_ON_SR, VERSION_SR),
regmap_reg_range(WCHDG_CR, WCHDG_CR),
regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4),
regmap_reg_range(INT_SRC_R1, INT_SRC_R4),
};
static const struct regmap_access_table stpmic1_readable_table = {
.yes_ranges = stpmic1_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(stpmic1_readable_ranges),
};
static const struct regmap_access_table stpmic1_writeable_table = {
.yes_ranges = stpmic1_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(stpmic1_writeable_ranges),
};
static const struct regmap_access_table stpmic1_volatile_table = {
.yes_ranges = stpmic1_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(stpmic1_volatile_ranges),
};
static const struct regmap_config stpmic1_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.max_register = PMIC_MAX_REGISTER_ADDRESS,
.rd_table = &stpmic1_readable_table,
.wr_table = &stpmic1_writeable_table,
.volatile_table = &stpmic1_volatile_table,
};
static const struct regmap_irq stpmic1_irqs[] = {
REGMAP_IRQ_REG(IT_PONKEY_F, 0, 0x01),
REGMAP_IRQ_REG(IT_PONKEY_R, 0, 0x02),
REGMAP_IRQ_REG(IT_WAKEUP_F, 0, 0x04),
REGMAP_IRQ_REG(IT_WAKEUP_R, 0, 0x08),
REGMAP_IRQ_REG(IT_VBUS_OTG_F, 0, 0x10),
REGMAP_IRQ_REG(IT_VBUS_OTG_R, 0, 0x20),
REGMAP_IRQ_REG(IT_SWOUT_F, 0, 0x40),
REGMAP_IRQ_REG(IT_SWOUT_R, 0, 0x80),
REGMAP_IRQ_REG(IT_CURLIM_BUCK1, 1, 0x01),
REGMAP_IRQ_REG(IT_CURLIM_BUCK2, 1, 0x02),
REGMAP_IRQ_REG(IT_CURLIM_BUCK3, 1, 0x04),
REGMAP_IRQ_REG(IT_CURLIM_BUCK4, 1, 0x08),
REGMAP_IRQ_REG(IT_OCP_OTG, 1, 0x10),
REGMAP_IRQ_REG(IT_OCP_SWOUT, 1, 0x20),
REGMAP_IRQ_REG(IT_OCP_BOOST, 1, 0x40),
REGMAP_IRQ_REG(IT_OVP_BOOST, 1, 0x80),
REGMAP_IRQ_REG(IT_CURLIM_LDO1, 2, 0x01),
REGMAP_IRQ_REG(IT_CURLIM_LDO2, 2, 0x02),
REGMAP_IRQ_REG(IT_CURLIM_LDO3, 2, 0x04),
REGMAP_IRQ_REG(IT_CURLIM_LDO4, 2, 0x08),
REGMAP_IRQ_REG(IT_CURLIM_LDO5, 2, 0x10),
REGMAP_IRQ_REG(IT_CURLIM_LDO6, 2, 0x20),
REGMAP_IRQ_REG(IT_SHORT_SWOTG, 2, 0x40),
REGMAP_IRQ_REG(IT_SHORT_SWOUT, 2, 0x80),
REGMAP_IRQ_REG(IT_TWARN_F, 3, 0x01),
REGMAP_IRQ_REG(IT_TWARN_R, 3, 0x02),
REGMAP_IRQ_REG(IT_VINLOW_F, 3, 0x04),
REGMAP_IRQ_REG(IT_VINLOW_R, 3, 0x08),
REGMAP_IRQ_REG(IT_SWIN_F, 3, 0x40),
REGMAP_IRQ_REG(IT_SWIN_R, 3, 0x80),
};
static const struct regmap_irq_chip stpmic1_regmap_irq_chip = {
.name = "pmic_irq",
.status_base = INT_PENDING_R1,
.mask_base = INT_SET_MASK_R1,
.unmask_base = INT_CLEAR_MASK_R1,
.mask_unmask_non_inverted = true,
.ack_base = INT_CLEAR_R1,
.num_regs = STPMIC1_PMIC_NUM_IRQ_REGS,
.irqs = stpmic1_irqs,
.num_irqs = ARRAY_SIZE(stpmic1_irqs),
};
static int stpmic1_power_off(struct sys_off_data *data)
{
struct stpmic1 *ddata = data->cb_data;
regmap_update_bits(ddata->regmap, MAIN_CR,
SOFTWARE_SWITCH_OFF, SOFTWARE_SWITCH_OFF);
return NOTIFY_DONE;
}
static int stpmic1_probe(struct i2c_client *i2c)
{
struct stpmic1 *ddata;
struct device *dev = &i2c->dev;
int ret;
struct device_node *np = dev->of_node;
u32 reg;
ddata = devm_kzalloc(dev, sizeof(struct stpmic1), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
i2c_set_clientdata(i2c, ddata);
ddata->dev = dev;
ddata->regmap = devm_regmap_init_i2c(i2c, &stpmic1_regmap_config);
if (IS_ERR(ddata->regmap))
return PTR_ERR(ddata->regmap);
ddata->irq = of_irq_get(np, STPMIC1_MAIN_IRQ);
if (ddata->irq < 0) {
dev_err(dev, "Failed to get main IRQ: %d\n", ddata->irq);
return ddata->irq;
}
ret = regmap_read(ddata->regmap, VERSION_SR, ®);
if (ret) {
dev_err(dev, "Unable to read PMIC version\n");
return ret;
}
dev_info(dev, "PMIC Chip Version: 0x%x\n", reg);
/* Initialize PMIC IRQ Chip & associated IRQ domains */
ret = devm_regmap_add_irq_chip(dev, ddata->regmap, ddata->irq,
IRQF_ONESHOT | IRQF_SHARED,
0, &stpmic1_regmap_irq_chip,
&ddata->irq_data);
if (ret) {
dev_err(dev, "IRQ Chip registration failed: %d\n", ret);
return ret;
}
ret = devm_register_sys_off_handler(ddata->dev,
SYS_OFF_MODE_POWER_OFF,
SYS_OFF_PRIO_DEFAULT,
stpmic1_power_off,
ddata);
if (ret) {
dev_err(ddata->dev, "failed to register sys-off handler: %d\n", ret);
return ret;
}
return devm_of_platform_populate(dev);
}
static int stpmic1_suspend(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct stpmic1 *pmic_dev = i2c_get_clientdata(i2c);
disable_irq(pmic_dev->irq);
return 0;
}
static int stpmic1_resume(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct stpmic1 *pmic_dev = i2c_get_clientdata(i2c);
int ret;
ret = regcache_sync(pmic_dev->regmap);
if (ret)
return ret;
enable_irq(pmic_dev->irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(stpmic1_pm, stpmic1_suspend, stpmic1_resume);
static const struct of_device_id stpmic1_of_match[] = {
{ .compatible = "st,stpmic1", },
{},
};
MODULE_DEVICE_TABLE(of, stpmic1_of_match);
static struct i2c_driver stpmic1_driver = {
.driver = {
.name = "stpmic1",
.of_match_table = stpmic1_of_match,
.pm = pm_sleep_ptr(&stpmic1_pm),
},
.probe = stpmic1_probe,
};
module_i2c_driver(stpmic1_driver);
MODULE_DESCRIPTION("STPMIC1 PMIC Driver");
MODULE_AUTHOR("Pascal Paillet <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/stpmic1.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2021 Richtek Technology Corp.
*
* Author: ChiYuan Huang <[email protected]>
*/
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/regmap.h>
#define RT4831_REG_REVISION 0x01
#define RT4831_REG_ENABLE 0x08
#define RT4831_REG_I2CPROT 0x15
#define RICHTEK_VENDOR_ID 0x03
#define RT4831_VID_MASK GENMASK(1, 0)
#define RT4831_RESET_MASK BIT(7)
#define RT4831_I2CSAFETMR_MASK BIT(0)
static const struct mfd_cell rt4831_subdevs[] = {
MFD_CELL_OF("rt4831-backlight", NULL, NULL, 0, 0, "richtek,rt4831-backlight"),
MFD_CELL_NAME("rt4831-regulator")
};
static bool rt4831_is_accessible_reg(struct device *dev, unsigned int reg)
{
if (reg >= RT4831_REG_REVISION && reg <= RT4831_REG_I2CPROT)
return true;
return false;
}
static const struct regmap_config rt4831_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = RT4831_REG_I2CPROT,
.readable_reg = rt4831_is_accessible_reg,
.writeable_reg = rt4831_is_accessible_reg,
};
static int rt4831_probe(struct i2c_client *client)
{
struct gpio_desc *enable_gpio;
struct regmap *regmap;
unsigned int chip_id;
int ret;
enable_gpio = devm_gpiod_get_optional(&client->dev, "enable", GPIOD_OUT_HIGH);
if (IS_ERR(enable_gpio)) {
dev_err(&client->dev, "Failed to get 'enable' GPIO\n");
return PTR_ERR(enable_gpio);
}
regmap = devm_regmap_init_i2c(client, &rt4831_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "Failed to initialize regmap\n");
return PTR_ERR(regmap);
}
ret = regmap_read(regmap, RT4831_REG_REVISION, &chip_id);
if (ret) {
dev_err(&client->dev, "Failed to get H/W revision\n");
return ret;
}
if ((chip_id & RT4831_VID_MASK) != RICHTEK_VENDOR_ID) {
dev_err(&client->dev, "Chip vendor ID 0x%02x not matched\n", chip_id);
return -ENODEV;
}
/*
* Used to prevent the abnormal shutdown.
* If SCL/SDA both keep low for one second to reset HW.
*/
ret = regmap_update_bits(regmap, RT4831_REG_I2CPROT, RT4831_I2CSAFETMR_MASK,
RT4831_I2CSAFETMR_MASK);
if (ret) {
dev_err(&client->dev, "Failed to enable I2C safety timer\n");
return ret;
}
return devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, rt4831_subdevs,
ARRAY_SIZE(rt4831_subdevs), NULL, 0, NULL);
}
static void rt4831_remove(struct i2c_client *client)
{
struct regmap *regmap = dev_get_regmap(&client->dev, NULL);
int ret;
/* Disable WLED and DSV outputs */
ret = regmap_update_bits(regmap, RT4831_REG_ENABLE, RT4831_RESET_MASK, RT4831_RESET_MASK);
if (ret)
dev_warn(&client->dev, "Failed to disable outputs (%pe)\n", ERR_PTR(ret));
}
static const struct of_device_id __maybe_unused rt4831_of_match[] = {
{ .compatible = "richtek,rt4831", },
{}
};
MODULE_DEVICE_TABLE(of, rt4831_of_match);
static struct i2c_driver rt4831_driver = {
.driver = {
.name = "rt4831",
.of_match_table = rt4831_of_match,
},
.probe = rt4831_probe,
.remove = rt4831_remove,
};
module_i2c_driver(rt4831_driver);
MODULE_AUTHOR("ChiYuan Huang <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/rt4831.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Intel LPSS PCI support.
*
* Copyright (C) 2015, Intel Corporation
*
* Authors: Andy Shevchenko <[email protected]>
* Mika Westerberg <[email protected]>
*/
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/pxa2xx_ssp.h>
#include "intel-lpss.h"
/* Some DSDTs have an unused GEXP ACPI device conflicting with I2C4 resources */
static const struct pci_device_id ignore_resource_conflicts_ids[] = {
/* Microsoft Surface Go (version 1) I2C4 */
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, 0x9d64, 0x152d, 0x1182), },
/* Microsoft Surface Go 2 I2C4 */
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, 0x9d64, 0x152d, 0x1237), },
{ }
};
static int intel_lpss_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct intel_lpss_platform_info *info;
int ret;
ret = pcim_enable_device(pdev);
if (ret)
return ret;
info = devm_kmemdup(&pdev->dev, (void *)id->driver_data, sizeof(*info),
GFP_KERNEL);
if (!info)
return -ENOMEM;
info->mem = &pdev->resource[0];
info->irq = pdev->irq;
if (pci_match_id(ignore_resource_conflicts_ids, pdev))
info->ignore_resource_conflicts = true;
pdev->d3cold_delay = 0;
/* Probably it is enough to set this for iDMA capable devices only */
pci_set_master(pdev);
pci_try_set_mwi(pdev);
ret = intel_lpss_probe(&pdev->dev, info);
if (ret)
return ret;
pm_runtime_put(&pdev->dev);
pm_runtime_allow(&pdev->dev);
return 0;
}
static void intel_lpss_pci_remove(struct pci_dev *pdev)
{
pm_runtime_forbid(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
intel_lpss_remove(&pdev->dev);
}
static INTEL_LPSS_PM_OPS(intel_lpss_pci_pm_ops);
static const struct property_entry spt_spi_properties[] = {
PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_SPT_SSP),
{ }
};
static const struct software_node spt_spi_node = {
.properties = spt_spi_properties,
};
static const struct intel_lpss_platform_info spt_info = {
.clk_rate = 120000000,
.swnode = &spt_spi_node,
};
static const struct property_entry spt_i2c_properties[] = {
PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 230),
{ },
};
static const struct software_node spt_i2c_node = {
.properties = spt_i2c_properties,
};
static const struct intel_lpss_platform_info spt_i2c_info = {
.clk_rate = 120000000,
.swnode = &spt_i2c_node,
};
static const struct property_entry uart_properties[] = {
PROPERTY_ENTRY_U32("reg-io-width", 4),
PROPERTY_ENTRY_U32("reg-shift", 2),
PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
{ },
};
static const struct software_node uart_node = {
.properties = uart_properties,
};
static const struct intel_lpss_platform_info spt_uart_info = {
.clk_rate = 120000000,
.clk_con_id = "baudclk",
.swnode = &uart_node,
};
static const struct property_entry bxt_spi_properties[] = {
PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BXT_SSP),
{ }
};
static const struct software_node bxt_spi_node = {
.properties = bxt_spi_properties,
};
static const struct intel_lpss_platform_info bxt_info = {
.clk_rate = 100000000,
.swnode = &bxt_spi_node,
};
static const struct intel_lpss_platform_info bxt_uart_info = {
.clk_rate = 100000000,
.clk_con_id = "baudclk",
.swnode = &uart_node,
};
static const struct property_entry bxt_i2c_properties[] = {
PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 42),
PROPERTY_ENTRY_U32("i2c-sda-falling-time-ns", 171),
PROPERTY_ENTRY_U32("i2c-scl-falling-time-ns", 208),
{ },
};
static const struct software_node bxt_i2c_node = {
.properties = bxt_i2c_properties,
};
static const struct intel_lpss_platform_info bxt_i2c_info = {
.clk_rate = 133000000,
.swnode = &bxt_i2c_node,
};
static const struct property_entry apl_i2c_properties[] = {
PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 207),
PROPERTY_ENTRY_U32("i2c-sda-falling-time-ns", 171),
PROPERTY_ENTRY_U32("i2c-scl-falling-time-ns", 208),
{ },
};
static const struct software_node apl_i2c_node = {
.properties = apl_i2c_properties,
};
static const struct intel_lpss_platform_info apl_i2c_info = {
.clk_rate = 133000000,
.swnode = &apl_i2c_node,
};
static const struct property_entry glk_i2c_properties[] = {
PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 313),
PROPERTY_ENTRY_U32("i2c-sda-falling-time-ns", 171),
PROPERTY_ENTRY_U32("i2c-scl-falling-time-ns", 290),
{ },
};
static const struct software_node glk_i2c_node = {
.properties = glk_i2c_properties,
};
static const struct intel_lpss_platform_info glk_i2c_info = {
.clk_rate = 133000000,
.swnode = &glk_i2c_node,
};
static const struct property_entry cnl_spi_properties[] = {
PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_CNL_SSP),
{ }
};
static const struct software_node cnl_spi_node = {
.properties = cnl_spi_properties,
};
static const struct intel_lpss_platform_info cnl_info = {
.clk_rate = 120000000,
.swnode = &cnl_spi_node,
};
static const struct intel_lpss_platform_info cnl_i2c_info = {
.clk_rate = 216000000,
.swnode = &spt_i2c_node,
};
static const struct intel_lpss_platform_info ehl_i2c_info = {
.clk_rate = 100000000,
.swnode = &bxt_i2c_node,
};
static const struct property_entry tgl_spi_properties[] = {
PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_CNL_SSP),
{ }
};
static const struct software_node tgl_spi_node = {
.properties = tgl_spi_properties,
};
static const struct intel_lpss_platform_info tgl_info = {
.clk_rate = 100000000,
.swnode = &tgl_spi_node,
};
static const struct pci_device_id intel_lpss_pci_ids[] = {
/* CML-LP */
{ PCI_VDEVICE(INTEL, 0x02a8), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x02a9), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x02aa), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x02ab), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x02c5), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x02c6), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x02c7), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x02e8), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x02e9), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x02ea), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x02eb), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x02fb), (kernel_ulong_t)&cnl_info },
/* CML-H */
{ PCI_VDEVICE(INTEL, 0x06a8), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x06a9), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x06aa), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x06ab), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x06c7), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x06e8), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x06e9), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x06ea), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x06eb), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x06fb), (kernel_ulong_t)&cnl_info },
/* BXT A-Step */
{ PCI_VDEVICE(INTEL, 0x0aac), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x0aae), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x0ab0), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x0ab2), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x0ab4), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x0ab6), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x0ab8), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x0aba), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x0abc), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x0abe), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x0ac0), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x0ac2), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x0ac4), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x0ac6), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x0aee), (kernel_ulong_t)&bxt_uart_info },
/* BXT B-Step */
{ PCI_VDEVICE(INTEL, 0x1aac), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x1aae), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x1ab0), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x1ab2), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x1ab4), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x1ab6), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x1ab8), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x1aba), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x1abc), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x1abe), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x1ac0), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x1ac2), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x1ac4), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x1ac6), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x1aee), (kernel_ulong_t)&bxt_uart_info },
/* EBG */
{ PCI_VDEVICE(INTEL, 0x1bad), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x1bae), (kernel_ulong_t)&bxt_uart_info },
/* GLK */
{ PCI_VDEVICE(INTEL, 0x31ac), (kernel_ulong_t)&glk_i2c_info },
{ PCI_VDEVICE(INTEL, 0x31ae), (kernel_ulong_t)&glk_i2c_info },
{ PCI_VDEVICE(INTEL, 0x31b0), (kernel_ulong_t)&glk_i2c_info },
{ PCI_VDEVICE(INTEL, 0x31b2), (kernel_ulong_t)&glk_i2c_info },
{ PCI_VDEVICE(INTEL, 0x31b4), (kernel_ulong_t)&glk_i2c_info },
{ PCI_VDEVICE(INTEL, 0x31b6), (kernel_ulong_t)&glk_i2c_info },
{ PCI_VDEVICE(INTEL, 0x31b8), (kernel_ulong_t)&glk_i2c_info },
{ PCI_VDEVICE(INTEL, 0x31ba), (kernel_ulong_t)&glk_i2c_info },
{ PCI_VDEVICE(INTEL, 0x31bc), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x31be), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x31c0), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x31c2), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x31c4), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x31c6), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x31ee), (kernel_ulong_t)&bxt_uart_info },
/* ICL-LP */
{ PCI_VDEVICE(INTEL, 0x34a8), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x34a9), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x34aa), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x34ab), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x34c5), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x34c6), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x34c7), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x34e8), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x34e9), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x34ea), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x34eb), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x34fb), (kernel_ulong_t)&cnl_info },
/* ICL-N */
{ PCI_VDEVICE(INTEL, 0x38a8), (kernel_ulong_t)&spt_uart_info },
/* TGL-H */
{ PCI_VDEVICE(INTEL, 0x43a7), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x43a8), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x43a9), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x43aa), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x43ab), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x43ad), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x43ae), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x43d8), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x43da), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x43e8), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x43e9), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x43ea), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x43eb), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x43fb), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x43fd), (kernel_ulong_t)&tgl_info },
/* EHL */
{ PCI_VDEVICE(INTEL, 0x4b28), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x4b29), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x4b2a), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x4b2b), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x4b37), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x4b44), (kernel_ulong_t)&ehl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x4b45), (kernel_ulong_t)&ehl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x4b4b), (kernel_ulong_t)&ehl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x4b4c), (kernel_ulong_t)&ehl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x4b4d), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x4b78), (kernel_ulong_t)&ehl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x4b79), (kernel_ulong_t)&ehl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x4b7a), (kernel_ulong_t)&ehl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x4b7b), (kernel_ulong_t)&ehl_i2c_info },
/* JSL */
{ PCI_VDEVICE(INTEL, 0x4da8), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x4da9), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x4daa), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x4dab), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x4dc5), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x4dc6), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x4dc7), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x4de8), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x4de9), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x4dea), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x4deb), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x4dfb), (kernel_ulong_t)&cnl_info },
/* ADL-P */
{ PCI_VDEVICE(INTEL, 0x51a8), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x51a9), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x51aa), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x51ab), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x51c5), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x51c6), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x51c7), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x51d8), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x51d9), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x51e8), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x51e9), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x51ea), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x51eb), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x51fb), (kernel_ulong_t)&tgl_info },
/* ADL-M */
{ PCI_VDEVICE(INTEL, 0x54a8), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x54a9), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x54aa), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x54ab), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x54c5), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x54c6), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x54c7), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x54e8), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x54e9), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x54ea), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x54eb), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x54fb), (kernel_ulong_t)&tgl_info },
/* APL */
{ PCI_VDEVICE(INTEL, 0x5aac), (kernel_ulong_t)&apl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x5aae), (kernel_ulong_t)&apl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x5ab0), (kernel_ulong_t)&apl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x5ab2), (kernel_ulong_t)&apl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x5ab4), (kernel_ulong_t)&apl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x5ab6), (kernel_ulong_t)&apl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x5ab8), (kernel_ulong_t)&apl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x5aba), (kernel_ulong_t)&apl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x5abc), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x5abe), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x5ac0), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x5ac2), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x5ac4), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x5ac6), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x5aee), (kernel_ulong_t)&bxt_uart_info },
/* RPL-S */
{ PCI_VDEVICE(INTEL, 0x7a28), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7a29), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7a2a), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x7a2b), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x7a4c), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7a4d), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7a4e), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7a4f), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7a5c), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7a79), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x7a7b), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x7a7c), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7a7d), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7a7e), (kernel_ulong_t)&bxt_uart_info },
/* ADL-S */
{ PCI_VDEVICE(INTEL, 0x7aa8), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7aa9), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7aaa), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x7aab), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x7acc), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7acd), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7ace), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7acf), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7adc), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7af9), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x7afb), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x7afc), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7afd), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7afe), (kernel_ulong_t)&bxt_uart_info },
/* MTL-P */
{ PCI_VDEVICE(INTEL, 0x7e25), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7e26), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7e27), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x7e30), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x7e46), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x7e50), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7e51), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7e52), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7e78), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7e79), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7e7a), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7e7b), (kernel_ulong_t)&bxt_i2c_info },
/* MTP-S */
{ PCI_VDEVICE(INTEL, 0x7f28), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7f29), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7f2a), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x7f2b), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x7f4c), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7f4d), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7f4e), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7f4f), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7f5c), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7f5d), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7f5e), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x7f5f), (kernel_ulong_t)&tgl_info },
{ PCI_VDEVICE(INTEL, 0x7f7a), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7f7b), (kernel_ulong_t)&bxt_i2c_info },
/* LKF */
{ PCI_VDEVICE(INTEL, 0x98a8), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x98a9), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x98aa), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x98c5), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x98c6), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x98c7), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x98e8), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x98e9), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x98ea), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x98eb), (kernel_ulong_t)&bxt_i2c_info },
/* SPT-LP */
{ PCI_VDEVICE(INTEL, 0x9d27), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x9d28), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x9d29), (kernel_ulong_t)&spt_info },
{ PCI_VDEVICE(INTEL, 0x9d2a), (kernel_ulong_t)&spt_info },
{ PCI_VDEVICE(INTEL, 0x9d60), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x9d61), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x9d62), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x9d63), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x9d64), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x9d65), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x9d66), (kernel_ulong_t)&spt_uart_info },
/* CNL-LP */
{ PCI_VDEVICE(INTEL, 0x9da8), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x9da9), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x9daa), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x9dab), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0x9dc5), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x9dc6), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x9dc7), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0x9de8), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x9de9), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x9dea), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x9deb), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0x9dfb), (kernel_ulong_t)&cnl_info },
/* TGL-LP */
{ PCI_VDEVICE(INTEL, 0xa0a8), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa0a9), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa0aa), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0xa0ab), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0xa0c5), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa0c6), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa0c7), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa0d8), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa0d9), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa0da), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa0db), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa0dc), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa0dd), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa0de), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0xa0df), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0xa0e8), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa0e9), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa0ea), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa0eb), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa0fb), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0xa0fd), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0xa0fe), (kernel_ulong_t)&cnl_info },
/* SPT-H */
{ PCI_VDEVICE(INTEL, 0xa127), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa128), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa129), (kernel_ulong_t)&spt_info },
{ PCI_VDEVICE(INTEL, 0xa12a), (kernel_ulong_t)&spt_info },
{ PCI_VDEVICE(INTEL, 0xa160), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa161), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa162), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa166), (kernel_ulong_t)&spt_uart_info },
/* KBL-H */
{ PCI_VDEVICE(INTEL, 0xa2a7), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa2a8), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa2a9), (kernel_ulong_t)&spt_info },
{ PCI_VDEVICE(INTEL, 0xa2aa), (kernel_ulong_t)&spt_info },
{ PCI_VDEVICE(INTEL, 0xa2e0), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa2e1), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa2e2), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa2e3), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa2e6), (kernel_ulong_t)&spt_uart_info },
/* CNL-H */
{ PCI_VDEVICE(INTEL, 0xa328), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa329), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa32a), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0xa32b), (kernel_ulong_t)&cnl_info },
{ PCI_VDEVICE(INTEL, 0xa347), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa368), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa369), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa36a), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa36b), (kernel_ulong_t)&cnl_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa37b), (kernel_ulong_t)&cnl_info },
/* CML-V */
{ PCI_VDEVICE(INTEL, 0xa3a7), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa3a8), (kernel_ulong_t)&spt_uart_info },
{ PCI_VDEVICE(INTEL, 0xa3a9), (kernel_ulong_t)&spt_info },
{ PCI_VDEVICE(INTEL, 0xa3aa), (kernel_ulong_t)&spt_info },
{ PCI_VDEVICE(INTEL, 0xa3e0), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa3e1), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa3e2), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa3e3), (kernel_ulong_t)&spt_i2c_info },
{ PCI_VDEVICE(INTEL, 0xa3e6), (kernel_ulong_t)&spt_uart_info },
{ }
};
MODULE_DEVICE_TABLE(pci, intel_lpss_pci_ids);
static struct pci_driver intel_lpss_pci_driver = {
.name = "intel-lpss",
.id_table = intel_lpss_pci_ids,
.probe = intel_lpss_pci_probe,
.remove = intel_lpss_pci_remove,
.driver = {
.pm = &intel_lpss_pci_pm_ops,
},
};
module_pci_driver(intel_lpss_pci_driver);
MODULE_AUTHOR("Andy Shevchenko <[email protected]>");
MODULE_AUTHOR("Mika Westerberg <[email protected]>");
MODULE_DESCRIPTION("Intel LPSS PCI driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/intel-lpss-pci.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* The Netronix embedded controller is a microcontroller found in some
* e-book readers designed by the original design manufacturer Netronix, Inc.
* It contains RTC, battery monitoring, system power management, and PWM
* functionality.
*
* This driver implements register access, version detection, and system
* power-off/reset.
*
* Copyright 2020 Jonathan Neuschäfer <[email protected]>
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#include <linux/mfd/ntxec.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
#include <linux/types.h>
#include <asm/unaligned.h>
#define NTXEC_REG_VERSION 0x00
#define NTXEC_REG_POWEROFF 0x50
#define NTXEC_REG_POWERKEEP 0x70
#define NTXEC_REG_RESET 0x90
#define NTXEC_POWEROFF_VALUE 0x0100
#define NTXEC_POWERKEEP_VALUE 0x0800
#define NTXEC_RESET_VALUE 0xff00
static struct i2c_client *poweroff_restart_client;
static void ntxec_poweroff(void)
{
int res;
u8 buf[3] = { NTXEC_REG_POWEROFF };
struct i2c_msg msgs[] = {
{
.addr = poweroff_restart_client->addr,
.flags = 0,
.len = sizeof(buf),
.buf = buf,
},
};
put_unaligned_be16(NTXEC_POWEROFF_VALUE, buf + 1);
res = i2c_transfer(poweroff_restart_client->adapter, msgs, ARRAY_SIZE(msgs));
if (res < 0)
dev_warn(&poweroff_restart_client->dev,
"Failed to power off (err = %d)\n", res);
/*
* The time from the register write until the host CPU is powered off
* has been observed to be about 2.5 to 3 seconds. Sleep long enough to
* safely avoid returning from the poweroff handler.
*/
msleep(5000);
}
static int ntxec_restart(struct notifier_block *nb,
unsigned long action, void *data)
{
int res;
u8 buf[3] = { NTXEC_REG_RESET };
/*
* NOTE: The lower half of the reset value is not sent, because sending
* it causes an I2C error. (The reset handler in the downstream driver
* does send the full two-byte value, but doesn't check the result).
*/
struct i2c_msg msgs[] = {
{
.addr = poweroff_restart_client->addr,
.flags = 0,
.len = sizeof(buf) - 1,
.buf = buf,
},
};
put_unaligned_be16(NTXEC_RESET_VALUE, buf + 1);
res = i2c_transfer(poweroff_restart_client->adapter, msgs, ARRAY_SIZE(msgs));
if (res < 0)
dev_warn(&poweroff_restart_client->dev,
"Failed to restart (err = %d)\n", res);
return NOTIFY_DONE;
}
static struct notifier_block ntxec_restart_handler = {
.notifier_call = ntxec_restart,
.priority = 128,
};
static int regmap_ignore_write(void *context,
unsigned int reg, unsigned int val)
{
struct regmap *regmap = context;
regmap_write(regmap, reg, val);
return 0;
}
static int regmap_wrap_read(void *context, unsigned int reg,
unsigned int *val)
{
struct regmap *regmap = context;
return regmap_read(regmap, reg, val);
}
/*
* Some firmware versions do not ack written data, add a wrapper. It
* is used to stack another regmap on top.
*/
static const struct regmap_config regmap_config_noack = {
.name = "ntxec_noack",
.reg_bits = 8,
.val_bits = 16,
.cache_type = REGCACHE_NONE,
.reg_write = regmap_ignore_write,
.reg_read = regmap_wrap_read
};
static const struct regmap_config regmap_config = {
.name = "ntxec",
.reg_bits = 8,
.val_bits = 16,
.cache_type = REGCACHE_NONE,
.val_format_endian = REGMAP_ENDIAN_BIG,
};
static const struct mfd_cell ntxec_subdev[] = {
{ .name = "ntxec-rtc" },
{ .name = "ntxec-pwm" },
};
static const struct mfd_cell ntxec_subdev_pwm[] = {
{ .name = "ntxec-pwm" },
};
static int ntxec_probe(struct i2c_client *client)
{
struct ntxec *ec;
unsigned int version;
int res;
const struct mfd_cell *subdevs;
size_t n_subdevs;
ec = devm_kmalloc(&client->dev, sizeof(*ec), GFP_KERNEL);
if (!ec)
return -ENOMEM;
ec->dev = &client->dev;
ec->regmap = devm_regmap_init_i2c(client, ®map_config);
if (IS_ERR(ec->regmap)) {
dev_err(ec->dev, "Failed to set up regmap for device\n");
return PTR_ERR(ec->regmap);
}
/* Determine the firmware version */
res = regmap_read(ec->regmap, NTXEC_REG_VERSION, &version);
if (res < 0) {
dev_err(ec->dev, "Failed to read firmware version number\n");
return res;
}
/* Bail out if we encounter an unknown firmware version */
switch (version) {
case NTXEC_VERSION_KOBO_AURA:
case NTXEC_VERSION_TOLINO_VISION:
subdevs = ntxec_subdev;
n_subdevs = ARRAY_SIZE(ntxec_subdev);
break;
case NTXEC_VERSION_TOLINO_SHINE2:
subdevs = ntxec_subdev_pwm;
n_subdevs = ARRAY_SIZE(ntxec_subdev_pwm);
/* Another regmap stacked on top of the other */
ec->regmap = devm_regmap_init(ec->dev, NULL,
ec->regmap,
®map_config_noack);
if (IS_ERR(ec->regmap))
return PTR_ERR(ec->regmap);
break;
default:
dev_err(ec->dev,
"Netronix embedded controller version %04x is not supported.\n",
version);
return -ENODEV;
}
dev_info(ec->dev,
"Netronix embedded controller version %04x detected.\n", version);
if (of_device_is_system_power_controller(ec->dev->of_node)) {
/*
* Set the 'powerkeep' bit. This is necessary on some boards
* in order to keep the system running.
*/
res = regmap_write(ec->regmap, NTXEC_REG_POWERKEEP,
NTXEC_POWERKEEP_VALUE);
if (res < 0)
return res;
if (poweroff_restart_client)
/*
* Another instance of the driver already took
* poweroff/restart duties.
*/
dev_err(ec->dev, "poweroff_restart_client already assigned\n");
else
poweroff_restart_client = client;
if (pm_power_off)
/* Another driver already registered a poweroff handler. */
dev_err(ec->dev, "pm_power_off already assigned\n");
else
pm_power_off = ntxec_poweroff;
res = register_restart_handler(&ntxec_restart_handler);
if (res)
dev_err(ec->dev,
"Failed to register restart handler: %d\n", res);
}
i2c_set_clientdata(client, ec);
res = devm_mfd_add_devices(ec->dev, PLATFORM_DEVID_NONE,
subdevs, n_subdevs, NULL, 0, NULL);
if (res)
dev_err(ec->dev, "Failed to add subdevices: %d\n", res);
return res;
}
static void ntxec_remove(struct i2c_client *client)
{
if (client == poweroff_restart_client) {
poweroff_restart_client = NULL;
pm_power_off = NULL;
unregister_restart_handler(&ntxec_restart_handler);
}
}
static const struct of_device_id of_ntxec_match_table[] = {
{ .compatible = "netronix,ntxec", },
{}
};
MODULE_DEVICE_TABLE(of, of_ntxec_match_table);
static struct i2c_driver ntxec_driver = {
.driver = {
.name = "ntxec",
.of_match_table = of_ntxec_match_table,
},
.probe = ntxec_probe,
.remove = ntxec_remove,
};
module_i2c_driver(ntxec_driver);
MODULE_AUTHOR("Jonathan Neuschäfer <[email protected]>");
MODULE_DESCRIPTION("Core driver for Netronix EC");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/ntxec.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/mfd/mcp-core.c
*
* Copyright (C) 2001 Russell King
*
* Generic MCP (Multimedia Communications Port) layer. All MCP locking
* is solely held within this file.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/smp.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/mfd/mcp.h>
#define to_mcp(d) container_of(d, struct mcp, attached_device)
#define to_mcp_driver(d) container_of(d, struct mcp_driver, drv)
static int mcp_bus_match(struct device *dev, struct device_driver *drv)
{
return 1;
}
static int mcp_bus_probe(struct device *dev)
{
struct mcp *mcp = to_mcp(dev);
struct mcp_driver *drv = to_mcp_driver(dev->driver);
return drv->probe(mcp);
}
static void mcp_bus_remove(struct device *dev)
{
struct mcp *mcp = to_mcp(dev);
struct mcp_driver *drv = to_mcp_driver(dev->driver);
drv->remove(mcp);
}
static struct bus_type mcp_bus_type = {
.name = "mcp",
.match = mcp_bus_match,
.probe = mcp_bus_probe,
.remove = mcp_bus_remove,
};
/**
* mcp_set_telecom_divisor - set the telecom divisor
* @mcp: MCP interface structure
* @div: SIB clock divisor
*
* Set the telecom divisor on the MCP interface. The resulting
* sample rate is SIBCLOCK/div.
*/
void mcp_set_telecom_divisor(struct mcp *mcp, unsigned int div)
{
unsigned long flags;
spin_lock_irqsave(&mcp->lock, flags);
mcp->ops->set_telecom_divisor(mcp, div);
spin_unlock_irqrestore(&mcp->lock, flags);
}
EXPORT_SYMBOL(mcp_set_telecom_divisor);
/**
* mcp_set_audio_divisor - set the audio divisor
* @mcp: MCP interface structure
* @div: SIB clock divisor
*
* Set the audio divisor on the MCP interface.
*/
void mcp_set_audio_divisor(struct mcp *mcp, unsigned int div)
{
unsigned long flags;
spin_lock_irqsave(&mcp->lock, flags);
mcp->ops->set_audio_divisor(mcp, div);
spin_unlock_irqrestore(&mcp->lock, flags);
}
EXPORT_SYMBOL(mcp_set_audio_divisor);
/**
* mcp_reg_write - write a device register
* @mcp: MCP interface structure
* @reg: 4-bit register index
* @val: 16-bit data value
*
* Write a device register. The MCP interface must be enabled
* to prevent this function hanging.
*/
void mcp_reg_write(struct mcp *mcp, unsigned int reg, unsigned int val)
{
unsigned long flags;
spin_lock_irqsave(&mcp->lock, flags);
mcp->ops->reg_write(mcp, reg, val);
spin_unlock_irqrestore(&mcp->lock, flags);
}
EXPORT_SYMBOL(mcp_reg_write);
/**
* mcp_reg_read - read a device register
* @mcp: MCP interface structure
* @reg: 4-bit register index
*
* Read a device register and return its value. The MCP interface
* must be enabled to prevent this function hanging.
*/
unsigned int mcp_reg_read(struct mcp *mcp, unsigned int reg)
{
unsigned long flags;
unsigned int val;
spin_lock_irqsave(&mcp->lock, flags);
val = mcp->ops->reg_read(mcp, reg);
spin_unlock_irqrestore(&mcp->lock, flags);
return val;
}
EXPORT_SYMBOL(mcp_reg_read);
/**
* mcp_enable - enable the MCP interface
* @mcp: MCP interface to enable
*
* Enable the MCP interface. Each call to mcp_enable will need
* a corresponding call to mcp_disable to disable the interface.
*/
void mcp_enable(struct mcp *mcp)
{
unsigned long flags;
spin_lock_irqsave(&mcp->lock, flags);
if (mcp->use_count++ == 0)
mcp->ops->enable(mcp);
spin_unlock_irqrestore(&mcp->lock, flags);
}
EXPORT_SYMBOL(mcp_enable);
/**
* mcp_disable - disable the MCP interface
* @mcp: MCP interface to disable
*
* Disable the MCP interface. The MCP interface will only be
* disabled once the number of calls to mcp_enable matches the
* number of calls to mcp_disable.
*/
void mcp_disable(struct mcp *mcp)
{
unsigned long flags;
spin_lock_irqsave(&mcp->lock, flags);
if (--mcp->use_count == 0)
mcp->ops->disable(mcp);
spin_unlock_irqrestore(&mcp->lock, flags);
}
EXPORT_SYMBOL(mcp_disable);
static void mcp_release(struct device *dev)
{
struct mcp *mcp = container_of(dev, struct mcp, attached_device);
kfree(mcp);
}
struct mcp *mcp_host_alloc(struct device *parent, size_t size)
{
struct mcp *mcp;
mcp = kzalloc(sizeof(struct mcp) + size, GFP_KERNEL);
if (mcp) {
spin_lock_init(&mcp->lock);
device_initialize(&mcp->attached_device);
mcp->attached_device.parent = parent;
mcp->attached_device.bus = &mcp_bus_type;
mcp->attached_device.dma_mask = parent->dma_mask;
mcp->attached_device.release = mcp_release;
}
return mcp;
}
EXPORT_SYMBOL(mcp_host_alloc);
int mcp_host_add(struct mcp *mcp, void *pdata)
{
mcp->attached_device.platform_data = pdata;
dev_set_name(&mcp->attached_device, "mcp0");
return device_add(&mcp->attached_device);
}
EXPORT_SYMBOL(mcp_host_add);
void mcp_host_del(struct mcp *mcp)
{
device_del(&mcp->attached_device);
}
EXPORT_SYMBOL(mcp_host_del);
void mcp_host_free(struct mcp *mcp)
{
put_device(&mcp->attached_device);
}
EXPORT_SYMBOL(mcp_host_free);
int mcp_driver_register(struct mcp_driver *mcpdrv)
{
mcpdrv->drv.bus = &mcp_bus_type;
return driver_register(&mcpdrv->drv);
}
EXPORT_SYMBOL(mcp_driver_register);
void mcp_driver_unregister(struct mcp_driver *mcpdrv)
{
driver_unregister(&mcpdrv->drv);
}
EXPORT_SYMBOL(mcp_driver_unregister);
static int __init mcp_init(void)
{
return bus_register(&mcp_bus_type);
}
static void __exit mcp_exit(void)
{
bus_unregister(&mcp_bus_type);
}
module_init(mcp_init);
module_exit(mcp_exit);
MODULE_AUTHOR("Russell King <[email protected]>");
MODULE_DESCRIPTION("Core multimedia communications port driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/mcp-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* I2C driver for Maxim MAX8925
*
* Copyright (C) 2009 Marvell International Ltd.
* Haojian Zhuang <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/mfd/max8925.h>
#include <linux/slab.h>
#define RTC_I2C_ADDR 0x68
#define ADC_I2C_ADDR 0x47
static inline int max8925_read_device(struct i2c_client *i2c,
int reg, int bytes, void *dest)
{
int ret;
if (bytes > 1)
ret = i2c_smbus_read_i2c_block_data(i2c, reg, bytes, dest);
else {
ret = i2c_smbus_read_byte_data(i2c, reg);
if (ret < 0)
return ret;
*(unsigned char *)dest = (unsigned char)ret;
}
return ret;
}
static inline int max8925_write_device(struct i2c_client *i2c,
int reg, int bytes, void *src)
{
unsigned char buf[9];
int ret;
buf[0] = (unsigned char)reg;
memcpy(&buf[1], src, bytes);
ret = i2c_master_send(i2c, buf, bytes + 1);
if (ret < 0)
return ret;
return 0;
}
int max8925_reg_read(struct i2c_client *i2c, int reg)
{
struct max8925_chip *chip = i2c_get_clientdata(i2c);
unsigned char data = 0;
int ret;
mutex_lock(&chip->io_lock);
ret = max8925_read_device(i2c, reg, 1, &data);
mutex_unlock(&chip->io_lock);
if (ret < 0)
return ret;
else
return (int)data;
}
EXPORT_SYMBOL(max8925_reg_read);
int max8925_reg_write(struct i2c_client *i2c, int reg,
unsigned char data)
{
struct max8925_chip *chip = i2c_get_clientdata(i2c);
int ret;
mutex_lock(&chip->io_lock);
ret = max8925_write_device(i2c, reg, 1, &data);
mutex_unlock(&chip->io_lock);
return ret;
}
EXPORT_SYMBOL(max8925_reg_write);
int max8925_bulk_read(struct i2c_client *i2c, int reg,
int count, unsigned char *buf)
{
struct max8925_chip *chip = i2c_get_clientdata(i2c);
int ret;
mutex_lock(&chip->io_lock);
ret = max8925_read_device(i2c, reg, count, buf);
mutex_unlock(&chip->io_lock);
return ret;
}
EXPORT_SYMBOL(max8925_bulk_read);
int max8925_bulk_write(struct i2c_client *i2c, int reg,
int count, unsigned char *buf)
{
struct max8925_chip *chip = i2c_get_clientdata(i2c);
int ret;
mutex_lock(&chip->io_lock);
ret = max8925_write_device(i2c, reg, count, buf);
mutex_unlock(&chip->io_lock);
return ret;
}
EXPORT_SYMBOL(max8925_bulk_write);
int max8925_set_bits(struct i2c_client *i2c, int reg,
unsigned char mask, unsigned char data)
{
struct max8925_chip *chip = i2c_get_clientdata(i2c);
unsigned char value;
int ret;
mutex_lock(&chip->io_lock);
ret = max8925_read_device(i2c, reg, 1, &value);
if (ret < 0)
goto out;
value &= ~mask;
value |= data;
ret = max8925_write_device(i2c, reg, 1, &value);
out:
mutex_unlock(&chip->io_lock);
return ret;
}
EXPORT_SYMBOL(max8925_set_bits);
static const struct i2c_device_id max8925_id_table[] = {
{ "max8925", 0 },
{ },
};
static int max8925_dt_init(struct device_node *np, struct device *dev,
struct max8925_platform_data *pdata)
{
int ret;
ret = of_property_read_u32(np, "maxim,tsc-irq", &pdata->tsc_irq);
if (ret) {
dev_err(dev, "Not found maxim,tsc-irq property\n");
return -EINVAL;
}
return 0;
}
static int max8925_probe(struct i2c_client *client)
{
struct max8925_platform_data *pdata = dev_get_platdata(&client->dev);
struct max8925_chip *chip;
struct device_node *node = client->dev.of_node;
if (node && !pdata) {
/* parse DT to get platform data */
pdata = devm_kzalloc(&client->dev,
sizeof(struct max8925_platform_data),
GFP_KERNEL);
if (!pdata)
return -ENOMEM;
if (max8925_dt_init(node, &client->dev, pdata))
return -EINVAL;
} else if (!pdata) {
pr_info("%s: platform data is missing\n", __func__);
return -EINVAL;
}
chip = devm_kzalloc(&client->dev,
sizeof(struct max8925_chip), GFP_KERNEL);
if (chip == NULL)
return -ENOMEM;
chip->i2c = client;
chip->dev = &client->dev;
i2c_set_clientdata(client, chip);
mutex_init(&chip->io_lock);
chip->rtc = i2c_new_dummy_device(chip->i2c->adapter, RTC_I2C_ADDR);
if (IS_ERR(chip->rtc)) {
dev_err(chip->dev, "Failed to allocate I2C device for RTC\n");
return PTR_ERR(chip->rtc);
}
i2c_set_clientdata(chip->rtc, chip);
chip->adc = i2c_new_dummy_device(chip->i2c->adapter, ADC_I2C_ADDR);
if (IS_ERR(chip->adc)) {
dev_err(chip->dev, "Failed to allocate I2C device for ADC\n");
i2c_unregister_device(chip->rtc);
return PTR_ERR(chip->adc);
}
i2c_set_clientdata(chip->adc, chip);
device_init_wakeup(&client->dev, 1);
max8925_device_init(chip, pdata);
return 0;
}
static void max8925_remove(struct i2c_client *client)
{
struct max8925_chip *chip = i2c_get_clientdata(client);
max8925_device_exit(chip);
i2c_unregister_device(chip->adc);
i2c_unregister_device(chip->rtc);
}
static int max8925_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct max8925_chip *chip = i2c_get_clientdata(client);
if (device_may_wakeup(dev) && chip->wakeup_flag)
enable_irq_wake(chip->core_irq);
return 0;
}
static int max8925_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct max8925_chip *chip = i2c_get_clientdata(client);
if (device_may_wakeup(dev) && chip->wakeup_flag)
disable_irq_wake(chip->core_irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(max8925_pm_ops,
max8925_suspend, max8925_resume);
static const struct of_device_id max8925_dt_ids[] = {
{ .compatible = "maxim,max8925", },
{},
};
static struct i2c_driver max8925_driver = {
.driver = {
.name = "max8925",
.pm = pm_sleep_ptr(&max8925_pm_ops),
.of_match_table = max8925_dt_ids,
},
.probe = max8925_probe,
.remove = max8925_remove,
.id_table = max8925_id_table,
};
static int __init max8925_i2c_init(void)
{
int ret;
ret = i2c_add_driver(&max8925_driver);
if (ret != 0)
pr_err("Failed to register MAX8925 I2C driver: %d\n", ret);
return ret;
}
subsys_initcall(max8925_i2c_init);
| linux-master | drivers/mfd/max8925-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Arizona-i2c.c -- Arizona I2C bus interface
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/mfd/arizona/core.h>
#include "arizona.h"
static int arizona_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
const void *match_data;
struct arizona *arizona;
const struct regmap_config *regmap_config = NULL;
unsigned long type = 0;
int ret;
match_data = device_get_match_data(&i2c->dev);
if (match_data)
type = (unsigned long)match_data;
else if (id)
type = id->driver_data;
switch (type) {
case WM5102:
if (IS_ENABLED(CONFIG_MFD_WM5102))
regmap_config = &wm5102_i2c_regmap;
break;
case WM5110:
case WM8280:
if (IS_ENABLED(CONFIG_MFD_WM5110))
regmap_config = &wm5110_i2c_regmap;
break;
case WM8997:
if (IS_ENABLED(CONFIG_MFD_WM8997))
regmap_config = &wm8997_i2c_regmap;
break;
case WM8998:
case WM1814:
if (IS_ENABLED(CONFIG_MFD_WM8998))
regmap_config = &wm8998_i2c_regmap;
break;
default:
dev_err(&i2c->dev, "Unknown device type %ld\n", type);
return -EINVAL;
}
if (!regmap_config) {
dev_err(&i2c->dev,
"No kernel support for device type %ld\n", type);
return -EINVAL;
}
arizona = devm_kzalloc(&i2c->dev, sizeof(*arizona), GFP_KERNEL);
if (arizona == NULL)
return -ENOMEM;
arizona->regmap = devm_regmap_init_i2c(i2c, regmap_config);
if (IS_ERR(arizona->regmap)) {
ret = PTR_ERR(arizona->regmap);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
arizona->type = type;
arizona->dev = &i2c->dev;
arizona->irq = i2c->irq;
return arizona_dev_init(arizona);
}
static void arizona_i2c_remove(struct i2c_client *i2c)
{
struct arizona *arizona = dev_get_drvdata(&i2c->dev);
arizona_dev_exit(arizona);
}
static const struct i2c_device_id arizona_i2c_id[] = {
{ "wm5102", WM5102 },
{ "wm5110", WM5110 },
{ "wm8280", WM8280 },
{ "wm8997", WM8997 },
{ "wm8998", WM8998 },
{ "wm1814", WM1814 },
{ }
};
MODULE_DEVICE_TABLE(i2c, arizona_i2c_id);
#ifdef CONFIG_OF
static const struct of_device_id arizona_i2c_of_match[] = {
{ .compatible = "wlf,wm5102", .data = (void *)WM5102 },
{ .compatible = "wlf,wm5110", .data = (void *)WM5110 },
{ .compatible = "wlf,wm8280", .data = (void *)WM8280 },
{ .compatible = "wlf,wm8997", .data = (void *)WM8997 },
{ .compatible = "wlf,wm8998", .data = (void *)WM8998 },
{ .compatible = "wlf,wm1814", .data = (void *)WM1814 },
{},
};
MODULE_DEVICE_TABLE(of, arizona_i2c_of_match);
#endif
static struct i2c_driver arizona_i2c_driver = {
.driver = {
.name = "arizona",
.pm = pm_ptr(&arizona_pm_ops),
.of_match_table = of_match_ptr(arizona_i2c_of_match),
},
.probe = arizona_i2c_probe,
.remove = arizona_i2c_remove,
.id_table = arizona_i2c_id,
};
module_i2c_driver(arizona_i2c_driver);
MODULE_SOFTDEP("pre: arizona_ldo1");
MODULE_DESCRIPTION("Arizona I2C bus interface");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/arizona-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Core driver access RC5T583 power management chip.
*
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
* Author: Laxman dewangan <[email protected]>
*
* Based on code
* Copyright (C) 2011 RICOH COMPANY,LTD
*/
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#include <linux/mfd/rc5t583.h>
#include <linux/regmap.h>
#define RICOH_ONOFFSEL_REG 0x10
#define RICOH_SWCTL_REG 0x5E
struct deepsleep_control_data {
u8 reg_add;
u8 ds_pos_bit;
};
#define DEEPSLEEP_INIT(_id, _reg, _pos) \
{ \
.reg_add = RC5T583_##_reg, \
.ds_pos_bit = _pos, \
}
static struct deepsleep_control_data deepsleep_data[] = {
DEEPSLEEP_INIT(DC0, SLPSEQ1, 0),
DEEPSLEEP_INIT(DC1, SLPSEQ1, 4),
DEEPSLEEP_INIT(DC2, SLPSEQ2, 0),
DEEPSLEEP_INIT(DC3, SLPSEQ2, 4),
DEEPSLEEP_INIT(LDO0, SLPSEQ3, 0),
DEEPSLEEP_INIT(LDO1, SLPSEQ3, 4),
DEEPSLEEP_INIT(LDO2, SLPSEQ4, 0),
DEEPSLEEP_INIT(LDO3, SLPSEQ4, 4),
DEEPSLEEP_INIT(LDO4, SLPSEQ5, 0),
DEEPSLEEP_INIT(LDO5, SLPSEQ5, 4),
DEEPSLEEP_INIT(LDO6, SLPSEQ6, 0),
DEEPSLEEP_INIT(LDO7, SLPSEQ6, 4),
DEEPSLEEP_INIT(LDO8, SLPSEQ7, 0),
DEEPSLEEP_INIT(LDO9, SLPSEQ7, 4),
DEEPSLEEP_INIT(PSO0, SLPSEQ8, 0),
DEEPSLEEP_INIT(PSO1, SLPSEQ8, 4),
DEEPSLEEP_INIT(PSO2, SLPSEQ9, 0),
DEEPSLEEP_INIT(PSO3, SLPSEQ9, 4),
DEEPSLEEP_INIT(PSO4, SLPSEQ10, 0),
DEEPSLEEP_INIT(PSO5, SLPSEQ10, 4),
DEEPSLEEP_INIT(PSO6, SLPSEQ11, 0),
DEEPSLEEP_INIT(PSO7, SLPSEQ11, 4),
};
#define EXT_PWR_REQ \
(RC5T583_EXT_PWRREQ1_CONTROL | RC5T583_EXT_PWRREQ2_CONTROL)
static const struct mfd_cell rc5t583_subdevs[] = {
{.name = "rc5t583-gpio",},
{.name = "rc5t583-regulator",},
{.name = "rc5t583-rtc", },
{.name = "rc5t583-key", }
};
static int __rc5t583_set_ext_pwrreq1_control(struct device *dev,
int id, int ext_pwr, int slots)
{
int ret;
uint8_t sleepseq_val = 0;
unsigned int en_bit;
unsigned int slot_bit;
if (id == RC5T583_DS_DC0) {
dev_err(dev, "PWRREQ1 is invalid control for rail %d\n", id);
return -EINVAL;
}
en_bit = deepsleep_data[id].ds_pos_bit;
slot_bit = en_bit + 1;
ret = rc5t583_read(dev, deepsleep_data[id].reg_add, &sleepseq_val);
if (ret < 0) {
dev_err(dev, "Error in reading reg 0x%x\n",
deepsleep_data[id].reg_add);
return ret;
}
sleepseq_val &= ~(0xF << en_bit);
sleepseq_val |= BIT(en_bit);
sleepseq_val |= ((slots & 0x7) << slot_bit);
ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(1));
if (ret < 0) {
dev_err(dev, "Error in updating the 0x%02x register\n",
RICOH_ONOFFSEL_REG);
return ret;
}
ret = rc5t583_write(dev, deepsleep_data[id].reg_add, sleepseq_val);
if (ret < 0) {
dev_err(dev, "Error in writing reg 0x%x\n",
deepsleep_data[id].reg_add);
return ret;
}
if (id == RC5T583_DS_LDO4) {
ret = rc5t583_write(dev, RICOH_SWCTL_REG, 0x1);
if (ret < 0)
dev_err(dev, "Error in writing reg 0x%x\n",
RICOH_SWCTL_REG);
}
return ret;
}
static int __rc5t583_set_ext_pwrreq2_control(struct device *dev,
int id, int ext_pwr)
{
int ret;
if (id != RC5T583_DS_DC0) {
dev_err(dev, "PWRREQ2 is invalid control for rail %d\n", id);
return -EINVAL;
}
ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(2));
if (ret < 0)
dev_err(dev, "Error in updating the ONOFFSEL 0x10 register\n");
return ret;
}
int rc5t583_ext_power_req_config(struct device *dev, int ds_id,
int ext_pwr_req, int deepsleep_slot_nr)
{
if ((ext_pwr_req & EXT_PWR_REQ) == EXT_PWR_REQ)
return -EINVAL;
if (ext_pwr_req & RC5T583_EXT_PWRREQ1_CONTROL)
return __rc5t583_set_ext_pwrreq1_control(dev, ds_id,
ext_pwr_req, deepsleep_slot_nr);
if (ext_pwr_req & RC5T583_EXT_PWRREQ2_CONTROL)
return __rc5t583_set_ext_pwrreq2_control(dev,
ds_id, ext_pwr_req);
return 0;
}
EXPORT_SYMBOL(rc5t583_ext_power_req_config);
static int rc5t583_clear_ext_power_req(struct rc5t583 *rc5t583,
struct rc5t583_platform_data *pdata)
{
int ret;
int i;
uint8_t on_off_val = 0;
/* Clear ONOFFSEL register */
if (pdata->enable_shutdown)
on_off_val = 0x1;
ret = rc5t583_write(rc5t583->dev, RICOH_ONOFFSEL_REG, on_off_val);
if (ret < 0)
dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
RICOH_ONOFFSEL_REG, ret);
ret = rc5t583_write(rc5t583->dev, RICOH_SWCTL_REG, 0x0);
if (ret < 0)
dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
RICOH_SWCTL_REG, ret);
/* Clear sleep sequence register */
for (i = RC5T583_SLPSEQ1; i <= RC5T583_SLPSEQ11; ++i) {
ret = rc5t583_write(rc5t583->dev, i, 0x0);
if (ret < 0)
dev_warn(rc5t583->dev,
"Error in writing reg 0x%02x error: %d\n",
i, ret);
}
return 0;
}
static bool volatile_reg(struct device *dev, unsigned int reg)
{
/* Enable caching in interrupt registers */
switch (reg) {
case RC5T583_INT_EN_SYS1:
case RC5T583_INT_EN_SYS2:
case RC5T583_INT_EN_DCDC:
case RC5T583_INT_EN_RTC:
case RC5T583_INT_EN_ADC1:
case RC5T583_INT_EN_ADC2:
case RC5T583_INT_EN_ADC3:
case RC5T583_GPIO_GPEDGE1:
case RC5T583_GPIO_GPEDGE2:
case RC5T583_GPIO_EN_INT:
return false;
case RC5T583_GPIO_MON_IOIN:
/* This is gpio input register */
return true;
default:
/* Enable caching in gpio registers */
if ((reg >= RC5T583_GPIO_IOSEL) &&
(reg <= RC5T583_GPIO_GPOFUNC))
return false;
/* Enable caching in sleep seq registers */
if ((reg >= RC5T583_SLPSEQ1) && (reg <= RC5T583_SLPSEQ11))
return false;
/* Enable caching of regulator registers */
if ((reg >= RC5T583_REG_DC0CTL) && (reg <= RC5T583_REG_SR3CTL))
return false;
if ((reg >= RC5T583_REG_LDOEN1) &&
(reg <= RC5T583_REG_LDO9DAC_DS))
return false;
break;
}
return true;
}
static const struct regmap_config rc5t583_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = volatile_reg,
.max_register = RC5T583_MAX_REG,
.num_reg_defaults_raw = RC5T583_NUM_REGS,
.cache_type = REGCACHE_RBTREE,
};
static int rc5t583_i2c_probe(struct i2c_client *i2c)
{
struct rc5t583 *rc5t583;
struct rc5t583_platform_data *pdata = dev_get_platdata(&i2c->dev);
int ret;
if (!pdata) {
dev_err(&i2c->dev, "Err: Platform data not found\n");
return -EINVAL;
}
rc5t583 = devm_kzalloc(&i2c->dev, sizeof(*rc5t583), GFP_KERNEL);
if (!rc5t583)
return -ENOMEM;
rc5t583->dev = &i2c->dev;
i2c_set_clientdata(i2c, rc5t583);
rc5t583->regmap = devm_regmap_init_i2c(i2c, &rc5t583_regmap_config);
if (IS_ERR(rc5t583->regmap)) {
ret = PTR_ERR(rc5t583->regmap);
dev_err(&i2c->dev, "regmap initialization failed: %d\n", ret);
return ret;
}
ret = rc5t583_clear_ext_power_req(rc5t583, pdata);
if (ret < 0)
return ret;
if (i2c->irq) {
ret = rc5t583_irq_init(rc5t583, i2c->irq, pdata->irq_base);
/* Still continue with warning, if irq init fails */
if (ret)
dev_warn(&i2c->dev, "IRQ init failed: %d\n", ret);
}
ret = devm_mfd_add_devices(rc5t583->dev, -1, rc5t583_subdevs,
ARRAY_SIZE(rc5t583_subdevs), NULL, 0, NULL);
if (ret) {
dev_err(&i2c->dev, "add mfd devices failed: %d\n", ret);
return ret;
}
return 0;
}
static const struct i2c_device_id rc5t583_i2c_id[] = {
{.name = "rc5t583", .driver_data = 0},
{}
};
static struct i2c_driver rc5t583_i2c_driver = {
.driver = {
.name = "rc5t583",
},
.probe = rc5t583_i2c_probe,
.id_table = rc5t583_i2c_id,
};
static int __init rc5t583_i2c_init(void)
{
return i2c_add_driver(&rc5t583_i2c_driver);
}
subsys_initcall(rc5t583_i2c_init);
| linux-master | drivers/mfd/rc5t583.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Regmap tables for CS47L92 codec
*
* Copyright (C) 2016-2019 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*
* Author: Stuart Henderson <[email protected]>
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/mfd/madera/core.h>
#include <linux/mfd/madera/registers.h>
#include "madera.h"
static const struct reg_sequence cs47l92_reva_16_patch[] = {
{ 0x3A2, 0x2C29 },
{ 0x3A3, 0x0E00 },
{ 0x281, 0x0000 },
{ 0x282, 0x0000 },
{ 0x4EA, 0x0100 },
{ 0x22B, 0x0000 },
{ 0x4A0, 0x0080 },
{ 0x4A1, 0x0000 },
{ 0x4A2, 0x0000 },
{ 0x180B, 0x033F },
{ 0x190B, 0x033F },
{ 0x442, 0x0304 },
{ 0x34C, 0x0003 },
{ 0x124, 0x0C49 },
{ 0x120, 0x0345 },
{ 0x120, 0x0305 },
{ 0x4FA, 0x5064 },
{ 0x1300, 0x050E },
{ 0x1302, 0x0101 },
{ 0x1380, 0x02E0 },
{ 0x1381, 0xF942 },
{ 0x1382, 0x04CE },
{ 0x1383, 0xFF06 },
{ 0x1390, 0x0304 },
{ 0x1391, 0xF8FF },
{ 0x1392, 0x04F3 },
{ 0x1393, 0xFF00 },
{ 0x13A0, 0x02E0 },
{ 0x13A1, 0xF942 },
{ 0x13A2, 0x04CE },
{ 0x13A3, 0xFF06 },
{ 0x13B0, 0x0304 },
{ 0x13B1, 0xF8FF },
{ 0x13B2, 0x04F3 },
{ 0x13B3, 0xFF00 },
{ 0x412, 0x0005 },
{ 0x41A, 0x0005 },
{ 0x422, 0x0005 },
};
static const struct reg_sequence cs47l92_reva_32_patch[] = {
{ 0x3030, 0x04A00C01 },
{ 0x3032, 0x0225F501 },
{ 0x3044, 0x04A00C00 },
{ 0x3046, 0x0225FF01 },
{ 0x3080, 0x04A00C01 },
{ 0x3082, 0x0226F501 },
{ 0x3094, 0x04A00C00 },
{ 0x3096, 0x0226FF01 },
{ 0x30D1, 0x04A10C01 },
{ 0x30D2, 0x0227F501 },
{ 0x30E4, 0x04A10C00 },
{ 0x30E6, 0x0227FF01 },
{ 0x3120, 0x04A10C01 },
{ 0x3122, 0x0228F501 },
{ 0x3134, 0x04A10C00 },
{ 0x3136, 0x0228FF01 },
{ 0x3170, 0x04A20C01 },
{ 0x3172, 0x022B0101 },
{ 0x3174, 0x0229F501 },
{ 0x3184, 0x04A20C00 },
{ 0x3186, 0x022B0100 },
{ 0x3188, 0x0229FF01 },
{ 0x31C0, 0x04A20C01 },
{ 0x31C2, 0x022B0001 },
{ 0x31C4, 0x022AF501 },
{ 0x31D4, 0x04A20C00 },
{ 0x31D6, 0x022B0000 },
{ 0x31D8, 0x022AFF01 },
};
int cs47l92_patch(struct madera *madera)
{
int ret;
ret = regmap_register_patch(madera->regmap,
cs47l92_reva_16_patch,
ARRAY_SIZE(cs47l92_reva_16_patch));
if (ret < 0) {
dev_err(madera->dev,
"Error in applying 16-bit patch: %d\n", ret);
return ret;
}
ret = regmap_register_patch(madera->regmap_32bit,
cs47l92_reva_32_patch,
ARRAY_SIZE(cs47l92_reva_32_patch));
if (ret < 0) {
dev_err(madera->dev,
"Error in applying 32-bit patch: %d\n", ret);
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(cs47l92_patch);
static const struct reg_default cs47l92_reg_default[] = {
{ 0x00000020, 0x0000 }, /* R32 (0x20) - Tone Generator 1 */
{ 0x00000021, 0x1000 }, /* R33 (0x21) - Tone Generator 2 */
{ 0x00000022, 0x0000 }, /* R34 (0x22) - Tone Generator 3 */
{ 0x00000023, 0x1000 }, /* R35 (0x23) - Tone Generator 4 */
{ 0x00000024, 0x0000 }, /* R36 (0x24) - Tone Generator 5 */
{ 0x00000030, 0x0000 }, /* R48 (0x30) - PWM Drive 1 */
{ 0x00000031, 0x0100 }, /* R49 (0x31) - PWM Drive 2 */
{ 0x00000032, 0x0100 }, /* R50 (0x32) - PWM Drive 3 */
{ 0x00000061, 0x01ff }, /* R97 (0x61) - Sample Rate Sequence Select 1 */
{ 0x00000062, 0x01ff }, /* R98 (0x62) - Sample Rate Sequence Select 2 */
{ 0x00000063, 0x01ff }, /* R99 (0x63) - Sample Rate Sequence Select 3 */
{ 0x00000064, 0x01ff }, /* R100 (0x64) - Sample Rate Sequence Select 4 */
{ 0x00000090, 0x0000 }, /* R144 (0x90) - Haptics Control 1 */
{ 0x00000091, 0x7fff }, /* R145 (0x91) - Haptics Control 2 */
{ 0x00000092, 0x0000 }, /* R146 (0x92) - Haptics Phase 1 Intensity */
{ 0x00000093, 0x0000 }, /* R147 (0x93) - Haptics Phase 1 Duration */
{ 0x00000094, 0x0000 }, /* R148 (0x94) - Haptics Phase 2 Intensity */
{ 0x00000095, 0x0000 }, /* R149 (0x95) - Haptics Phase 2 Duration */
{ 0x00000096, 0x0000 }, /* R150 (0x96) - Haptics Phase 3 Intensity */
{ 0x00000097, 0x0000 }, /* R151 (0x97) - Haptics Phase 3 Duration */
{ 0x000000a0, 0x0000 }, /* R160 (0xa0) - Comfort Noise Generator */
{ 0x00000100, 0x0002 }, /* R256 (0x100) - Clock 32k 1 */
{ 0x00000101, 0x0404 }, /* R257 (0x101) - System Clock 1 */
{ 0x00000102, 0x0011 }, /* R258 (0x102) - Sample Rate 1 */
{ 0x00000103, 0x0011 }, /* R259 (0x103) - Sample Rate 2 */
{ 0x00000104, 0x0011 }, /* R260 (0x104) - Sample Rate 3 */
{ 0x00000112, 0x0305 }, /* R274 (0x112) - Async Clock 1 */
{ 0x00000113, 0x0011 }, /* R275 (0x113) - Async Sample Rate 1 */
{ 0x00000114, 0x0011 }, /* R276 (0x114) - Async Sample Rate 2 */
{ 0x00000120, 0x0305 }, /* R288 (0x120) - DSP Clock 1 */
{ 0x00000122, 0x0000 }, /* R290 (0x122) - DSP Clock 2 */
{ 0x00000149, 0x0000 }, /* R329 (0x149) - Output System Clock */
{ 0x0000014a, 0x0000 }, /* R330 (0x14a) - Output Async Clock */
{ 0x00000152, 0x0000 }, /* R338 (0x152) - Rate Estimator 1 */
{ 0x00000153, 0x0000 }, /* R339 (0x153) - Rate Estimator 2 */
{ 0x00000154, 0x0000 }, /* R340 (0x154) - Rate Estimator 3 */
{ 0x00000155, 0x0000 }, /* R341 (0x155) - Rate Estimator 4 */
{ 0x00000156, 0x0000 }, /* R342 (0x156) - Rate Estimator 5 */
{ 0x00000171, 0x7004 }, /* R369 (0x171) - FLL1 Control 1 */
{ 0x00000172, 0x0004 }, /* R370 (0x172) - FLL1 Control 2 */
{ 0x00000173, 0x0000 }, /* R371 (0x173) - FLL1 Control 3 */
{ 0x00000174, 0x0000 }, /* R372 (0x174) - FLL1 Control 4 */
{ 0x00000175, 0x0001 }, /* R373 (0x175) - FLL1 Control 5 */
{ 0x00000176, 0x8000 }, /* R374 (0x176) - FLL1 Control 6 */
{ 0x00000177, 0x0680 }, /* R375 (0x177) - FLL1 Control 7 */
{ 0x00000178, 0x21f0 }, /* R376 (0x178) - FLL1 Control 8 */
{ 0x00000179, 0x0000 }, /* R377 (0x179) - FLL1 Control 9 */
{ 0x0000017a, 0x0000 }, /* R378 (0x17a) - FLL1 Control 10 */
{ 0x0000017b, 0x0011 }, /* R379 (0x17b) - FLL1 Control 11 */
{ 0x0000017d, 0x33e8 }, /* R381 (0x17d) - FLL1 Digital Test 1 */
{ 0x00000181, 0x7000 }, /* R385 (0x181) - FLL1 Synchroniser 1 */
{ 0x00000182, 0x0004 }, /* R386 (0x182) - FLL1 Synchroniser 2 */
{ 0x00000183, 0x0000 }, /* R387 (0x183) - FLL1 Synchroniser 3 */
{ 0x00000184, 0x0000 }, /* R388 (0x184) - FLL1 Synchroniser 4 */
{ 0x00000185, 0x0001 }, /* R389 (0x185) - FLL1 Synchroniser 5 */
{ 0x00000186, 0x0000 }, /* R390 (0x186) - FLL1 Synchroniser 6 */
{ 0x0000018e, 0x0c04 }, /* R398 (0x18e) - FLL1 GPIO Clock */
{ 0x00000191, 0x7000 }, /* R401 (0x191) - FLL2 Control 1 */
{ 0x00000192, 0x0004 }, /* R402 (0x192) - FLL2 Control 2 */
{ 0x00000193, 0x0000 }, /* R403 (0x193) - FLL2 Control 3 */
{ 0x00000194, 0x0000 }, /* R404 (0x194) - FLL2 Control 4 */
{ 0x00000195, 0x0001 }, /* R405 (0x195) - FLL2 Control 5 */
{ 0x00000196, 0x8000 }, /* R406 (0x196) - FLL2 Control 6 */
{ 0x00000197, 0x0680 }, /* R407 (0x197) - FLL2 Control 7 */
{ 0x00000198, 0x21f0 }, /* R408 (0x198) - FLL2 Control 8 */
{ 0x00000199, 0x0000 }, /* R409 (0x199) - FLL2 Control 9 */
{ 0x0000019a, 0x0000 }, /* R410 (0x19a) - FLL2 Control 10 */
{ 0x0000019b, 0x0011 }, /* R411 (0x19b) - FLL2 Control 11 */
{ 0x0000019d, 0x33e8 }, /* R413 (0x19d) - FLL2 Digital Test 1 */
{ 0x000001a1, 0x7000 }, /* R417 (0x1a1) - FLL2 Synchroniser 1 */
{ 0x000001a2, 0x0004 }, /* R418 (0x1a2) - FLL2 Synchroniser 2 */
{ 0x000001a3, 0x0000 }, /* R419 (0x1a3) - FLL2 Synchroniser 3 */
{ 0x000001a4, 0x0000 }, /* R420 (0x1a4) - FLL2 Synchroniser 4 */
{ 0x000001a5, 0x0001 }, /* R421 (0x1a5) - FLL2 Synchroniser 5 */
{ 0x000001a6, 0x0000 }, /* R422 (0x1a6) - FLL2 Synchroniser 6 */
{ 0x000001ae, 0x0c04 }, /* R430 (0x1ae) - FLL2 GPIO Clock */
{ 0x00000200, 0x0006 }, /* R512 (0x200) - Mic Charge Pump 1 */
{ 0x00000213, 0x03e4 }, /* R531 (0x213) - LDO2 Control 1 */
{ 0x00000218, 0x00e6 }, /* R536 (0x218) - Mic Bias Ctrl 1 */
{ 0x00000219, 0x00e6 }, /* R537 (0x219) - Mic Bias Ctrl 2 */
{ 0x0000021c, 0x2222 }, /* R540 (0x21c) - Mic Bias Ctrl 5 */
{ 0x0000021e, 0x0022 }, /* R542 (0x21e) - Mic Bias Ctrl 6 */
{ 0x00000293, 0x0080 }, /* R659 (0x293) - Accessory Detect Mode 1 */
{ 0x00000299, 0x0000 }, /* R665 (0x299) - Headphone Detect 0 */
{ 0x0000029b, 0x0000 }, /* R667 (0x29b) - Headphone Detect 1 */
{ 0x000002a2, 0x0010 }, /* R674 (0x2a2) - Mic Detect 1 Control 0 */
{ 0x000002a3, 0x1102 }, /* R675 (0x2a3) - Mic Detect 1 Control 1 */
{ 0x000002a4, 0x009f }, /* R676 (0x2a4) - Mic Detect 1 Control 2 */
{ 0x000002a6, 0x3d3d }, /* R678 (0x2a6) - Mic Detect 1 Level 1 */
{ 0x000002a7, 0x3d3d }, /* R679 (0x2a7) - Mic Detect 1 Level 2 */
{ 0x000002a8, 0x333d }, /* R680 (0x2a8) - Mic Detect 1 Level 3 */
{ 0x000002a9, 0x202d }, /* R681 (0x2a9) - Mic Detect 1 Level 4 */
{ 0x000002b2, 0x0010 }, /* R690 (0x2b2) - Mic Detect 2 Control 0 */
{ 0x000002b3, 0x1102 }, /* R691 (0x2b3) - Mic Detect 2 Control 1 */
{ 0x000002b4, 0x009f }, /* R692 (0x2b4) - Mic Detect 2 Control 2 */
{ 0x000002b6, 0x3d3d }, /* R694 (0x2b6) - Mic Detect 2 Level 1 */
{ 0x000002b7, 0x3d3d }, /* R695 (0x2b7) - Mic Detect 2 Level 2 */
{ 0x000002b8, 0x333d }, /* R696 (0x2b8) - Mic Detect 2 Level 3 */
{ 0x000002b9, 0x202d }, /* R697 (0x2b9) - Mic Detect 2 Level 4 */
{ 0x000002c6, 0x0210 }, /* R710 (0x2c6) - Micd Clamp control */
{ 0x000002c8, 0x0000 }, /* R712 (0x2c8) - GP Switch 1 */
{ 0x000002d3, 0x0000 }, /* R723 (0x2d3) - Jack Detect Analogue */
{ 0x00000300, 0x0000 }, /* R768 (0x300) - Input Enables */
{ 0x00000308, 0x0400 }, /* R776 (0x308) - Input Rate */
{ 0x00000309, 0x0022 }, /* R777 (0x309) - Input Volume Ramp */
{ 0x0000030c, 0x0002 }, /* R780 (0x30c) - HPF Control */
{ 0x00000310, 0x0080 }, /* R784 (0x310) - IN1L Control */
{ 0x00000311, 0x0180 }, /* R785 (0x311) - ADC Digital Volume 1L */
{ 0x00000312, 0x0500 }, /* R786 (0x312) - DMIC1L Control */
{ 0x00000313, 0x0000 }, /* R787 (0x313) - IN1L Rate Control */
{ 0x00000314, 0x0080 }, /* R788 (0x314) - IN1R Control */
{ 0x00000315, 0x0180 }, /* R789 (0x315) - ADC Digital Volume 1R */
{ 0x00000316, 0x0000 }, /* R790 (0x316) - DMIC1R Control */
{ 0x00000317, 0x0000 }, /* R791 (0x317) - IN1R Rate Control */
{ 0x00000318, 0x0080 }, /* R792 (0x318) - IN2L Control */
{ 0x00000319, 0x0180 }, /* R793 (0x319) - ADC Digital Volume 2L */
{ 0x0000031a, 0x0500 }, /* R794 (0x31a) - DMIC2L Control */
{ 0x0000031b, 0x0000 }, /* R795 (0x31b) - IN2L Rate Control */
{ 0x0000031c, 0x0080 }, /* R796 (0x31c) - IN2R Control */
{ 0x0000031d, 0x0180 }, /* R797 (0x31d) - ADC Digital Volume 2R */
{ 0x0000031e, 0x0000 }, /* R798 (0x31e) - DMIC2R Control */
{ 0x0000031f, 0x0000 }, /* R799 (0x31f) - IN2R Rate Control */
{ 0x00000320, 0x0000 }, /* R800 (0x320) - IN3L Control */
{ 0x00000321, 0x0180 }, /* R801 (0x321) - ADC Digital Volume 3L */
{ 0x00000322, 0x0500 }, /* R802 (0x322) - DMIC3L Control */
{ 0x00000323, 0x0000 }, /* R803 (0x323) - IN3L Rate Control */
{ 0x00000324, 0x0000 }, /* R804 (0x324) - IN3R Control */
{ 0x00000325, 0x0180 }, /* R805 (0x325) - ADC Digital Volume 3R */
{ 0x00000326, 0x0000 }, /* R806 (0x326) - DMIC3R Control */
{ 0x00000327, 0x0000 }, /* R807 (0x327) - IN3R Rate Control */
{ 0x00000328, 0x0000 }, /* R808 (0x328) - IN4L Control */
{ 0x00000329, 0x0180 }, /* R809 (0x329) - ADC Digital Volume 4L */
{ 0x0000032a, 0x0500 }, /* R810 (0x32a) - DMIC4L Control */
{ 0x0000032b, 0x0000 }, /* R811 (0x32b) - IN4L Rate Control */
{ 0x0000032c, 0x0000 }, /* R812 (0x32c) - IN4R Control */
{ 0x0000032d, 0x0180 }, /* R813 (0x32d) - ADC Digital Volume 4R */
{ 0x0000032e, 0x0000 }, /* R814 (0x32e) - DMIC4R Control */
{ 0x0000032f, 0x0000 }, /* R815 (0x32f) - IN4R Rate Control */
{ 0x00000400, 0x0000 }, /* R1024 (0x400) - Output Enables 1 */
{ 0x00000408, 0x0040 }, /* R1032 (0x408) - Output Rate 1 */
{ 0x00000409, 0x0022 }, /* R1033 (0x409) - Output Volume Ramp */
{ 0x00000410, 0x0080 }, /* R1040 (0x410) - Output Path Config 1L */
{ 0x00000411, 0x0180 }, /* R1041 (0x411) - DAC Digital Volume 1L */
{ 0x00000412, 0x0005 }, /* R1042 (0x412) - Output Path Config 1 */
{ 0x00000413, 0x0001 }, /* R1043 (0x413) - Noise Gate Select 1L */
{ 0x00000414, 0x0080 }, /* R1044 (0x414) - Output Path Config 1R */
{ 0x00000415, 0x0180 }, /* R1045 (0x415) - DAC Digital Volume 1R */
{ 0x00000417, 0x0002 }, /* R1047 (0x417) - Noise Gate Select 1R */
{ 0x00000418, 0x0080 }, /* R1048 (0x418) - Output Path Config 2L */
{ 0x00000419, 0x0180 }, /* R1049 (0x419) - DAC Digital Volume 2L */
{ 0x0000041a, 0x0005 }, /* R1050 (0x41a) - Output Path Config 2 */
{ 0x0000041b, 0x0004 }, /* R1051 (0x41b) - Noise Gate Select 2L */
{ 0x0000041c, 0x0080 }, /* R1052 (0x41c) - Output Path Config 2R */
{ 0x0000041d, 0x0180 }, /* R1053 (0x41d) - DAC Digital Volume 2R */
{ 0x0000041f, 0x0008 }, /* R1055 (0x41f) - Noise Gate Select 2R */
{ 0x00000420, 0x0080 }, /* R1056 (0x420) - Output Path Config 3L */
{ 0x00000421, 0x0180 }, /* R1057 (0x421) - DAC Digital Volume 3L */
{ 0x00000422, 0x0005 }, /* R1058 (0x422) - Output Path Config 3 */
{ 0x00000423, 0x0010 }, /* R1059 (0x423) - Noise Gate Select 3L */
{ 0x00000424, 0x0080 }, /* R1060 (0x424) - Output Path Config 3R */
{ 0x00000425, 0x0180 }, /* R1061 (0x425) - DAC Digital Volume 3R */
{ 0x00000427, 0x0020 }, /* R1063 (0x427) - Noise Gate Select 3R */
{ 0x00000430, 0x0000 }, /* R1072 (0x430) - Output Path Config 5L */
{ 0x00000431, 0x0180 }, /* R1073 (0x431) - DAC Digital Volume 5L */
{ 0x00000433, 0x0100 }, /* R1075 (0x433) - Noise Gate Select 5L */
{ 0x00000434, 0x0000 }, /* R1076 (0x434) - Output Path Config 5R */
{ 0x00000435, 0x0180 }, /* R1077 (0x435) - DAC Digital Volume 5R */
{ 0x00000437, 0x0200 }, /* R1079 (0x437) - Noise Gate Select 5R */
{ 0x00000450, 0x0000 }, /* R1104 (0x450) - DAC AEC Control 1 */
{ 0x00000451, 0x0000 }, /* R1105 (0x451) - DAC AEC Control 2 */
{ 0x00000458, 0x0000 }, /* R1112 (0x458) - Noise Gate Control */
{ 0x00000490, 0x0069 }, /* R1168 (0x490) - PDM SPK1 Ctrl 1 */
{ 0x00000491, 0x0000 }, /* R1169 (0x491) - PDM SPK1 Ctrl 2 */
{ 0x000004a0, 0x0080 }, /* R1184 (0x4a0) - HP1 Short Circuit Ctrl */
{ 0x000004a1, 0x0000 }, /* R1185 (0x4a1) - HP2 Short Circuit Ctrl */
{ 0x000004a2, 0x0000 }, /* R1186 (0x4a2) - HP3 Short Circuit Ctrl */
{ 0x00000500, 0x000c }, /* R1280 (0x500) - AIF1 BCLK Ctrl */
{ 0x00000501, 0x0000 }, /* R1281 (0x501) - AIF1 Tx Pin Ctrl */
{ 0x00000502, 0x0000 }, /* R1282 (0x502) - AIF1 Rx Pin Ctrl */
{ 0x00000503, 0x0000 }, /* R1283 (0x503) - AIF1 Rate Ctrl */
{ 0x00000504, 0x0000 }, /* R1284 (0x504) - AIF1 Format */
{ 0x00000506, 0x0040 }, /* R1286 (0x506) - AIF1 Rx BCLK Rate */
{ 0x00000507, 0x1818 }, /* R1287 (0x507) - AIF1 Frame Ctrl 1 */
{ 0x00000508, 0x1818 }, /* R1288 (0x508) - AIF1 Frame Ctrl 2 */
{ 0x00000509, 0x0000 }, /* R1289 (0x509) - AIF1 Frame Ctrl 3 */
{ 0x0000050a, 0x0001 }, /* R1290 (0x50a) - AIF1 Frame Ctrl 4 */
{ 0x0000050b, 0x0002 }, /* R1291 (0x50b) - AIF1 Frame Ctrl 5 */
{ 0x0000050c, 0x0003 }, /* R1292 (0x50c) - AIF1 Frame Ctrl 6 */
{ 0x0000050d, 0x0004 }, /* R1293 (0x50d) - AIF1 Frame Ctrl 7 */
{ 0x0000050e, 0x0005 }, /* R1294 (0x50e) - AIF1 Frame Ctrl 8 */
{ 0x0000050f, 0x0006 }, /* R1295 (0x50f) - AIF1 Frame Ctrl 9 */
{ 0x00000510, 0x0007 }, /* R1296 (0x510) - AIF1 Frame Ctrl 10 */
{ 0x00000511, 0x0000 }, /* R1297 (0x511) - AIF1 Frame Ctrl 11 */
{ 0x00000512, 0x0001 }, /* R1298 (0x512) - AIF1 Frame Ctrl 12 */
{ 0x00000513, 0x0002 }, /* R1299 (0x513) - AIF1 Frame Ctrl 13 */
{ 0x00000514, 0x0003 }, /* R1300 (0x514) - AIF1 Frame Ctrl 14 */
{ 0x00000515, 0x0004 }, /* R1301 (0x515) - AIF1 Frame Ctrl 15 */
{ 0x00000516, 0x0005 }, /* R1302 (0x516) - AIF1 Frame Ctrl 16 */
{ 0x00000517, 0x0006 }, /* R1303 (0x517) - AIF1 Frame Ctrl 17 */
{ 0x00000518, 0x0007 }, /* R1304 (0x518) - AIF1 Frame Ctrl 18 */
{ 0x00000519, 0x0000 }, /* R1305 (0x519) - AIF1 Tx Enables */
{ 0x0000051a, 0x0000 }, /* R1306 (0x51a) - AIF1 Rx Enables */
{ 0x00000540, 0x000c }, /* R1344 (0x540) - AIF2 BCLK Ctrl */
{ 0x00000541, 0x0000 }, /* R1345 (0x541) - AIF2 Tx Pin Ctrl */
{ 0x00000542, 0x0000 }, /* R1346 (0x542) - AIF2 Rx Pin Ctrl */
{ 0x00000543, 0x0000 }, /* R1347 (0x543) - AIF2 Rate Ctrl */
{ 0x00000544, 0x0000 }, /* R1348 (0x544) - AIF2 Format */
{ 0x00000546, 0x0040 }, /* R1350 (0x546) - AIF2 Rx BCLK Rate */
{ 0x00000547, 0x1818 }, /* R1351 (0x547) - AIF2 Frame Ctrl 1 */
{ 0x00000548, 0x1818 }, /* R1352 (0x548) - AIF2 Frame Ctrl 2 */
{ 0x00000549, 0x0000 }, /* R1353 (0x549) - AIF2 Frame Ctrl 3 */
{ 0x0000054a, 0x0001 }, /* R1354 (0x54a) - AIF2 Frame Ctrl 4 */
{ 0x0000054b, 0x0002 }, /* R1355 (0x54b) - AIF2 Frame Ctrl 5 */
{ 0x0000054c, 0x0003 }, /* R1356 (0x54c) - AIF2 Frame Ctrl 6 */
{ 0x0000054d, 0x0004 }, /* R1357 (0x54d) - AIF2 Frame Ctrl 7 */
{ 0x0000054e, 0x0005 }, /* R1358 (0x54e) - AIF2 Frame Ctrl 8 */
{ 0x0000054f, 0x0006 }, /* R1359 (0x54f) - AIF2 Frame Ctrl 9 */
{ 0x00000550, 0x0007 }, /* R1360 (0x550) - AIF2 Frame Ctrl 10 */
{ 0x00000551, 0x0000 }, /* R1361 (0x551) - AIF2 Frame Ctrl 11 */
{ 0x00000552, 0x0001 }, /* R1362 (0x552) - AIF2 Frame Ctrl 12 */
{ 0x00000553, 0x0002 }, /* R1363 (0x553) - AIF2 Frame Ctrl 13 */
{ 0x00000554, 0x0003 }, /* R1364 (0x554) - AIF2 Frame Ctrl 14 */
{ 0x00000555, 0x0004 }, /* R1365 (0x555) - AIF2 Frame Ctrl 15 */
{ 0x00000556, 0x0005 }, /* R1366 (0x556) - AIF2 Frame Ctrl 16 */
{ 0x00000557, 0x0006 }, /* R1367 (0x557) - AIF2 Frame Ctrl 17 */
{ 0x00000558, 0x0007 }, /* R1368 (0x558) - AIF2 Frame Ctrl 18 */
{ 0x00000559, 0x0000 }, /* R1369 (0x559) - AIF2 Tx Enables */
{ 0x0000055a, 0x0000 }, /* R1370 (0x55a) - AIF2 Rx Enables */
{ 0x00000580, 0x000c }, /* R1408 (0x580) - AIF3 BCLK Ctrl */
{ 0x00000581, 0x0000 }, /* R1409 (0x581) - AIF3 Tx Pin Ctrl */
{ 0x00000582, 0x0000 }, /* R1410 (0x582) - AIF3 Rx Pin Ctrl */
{ 0x00000583, 0x0000 }, /* R1411 (0x583) - AIF3 Rate Ctrl */
{ 0x00000584, 0x0000 }, /* R1412 (0x584) - AIF3 Format */
{ 0x00000586, 0x0040 }, /* R1414 (0x586) - AIF3 Rx BCLK Rate */
{ 0x00000587, 0x1818 }, /* R1415 (0x587) - AIF3 Frame Ctrl 1 */
{ 0x00000588, 0x1818 }, /* R1416 (0x588) - AIF3 Frame Ctrl 2 */
{ 0x00000589, 0x0000 }, /* R1417 (0x589) - AIF3 Frame Ctrl 3 */
{ 0x0000058a, 0x0001 }, /* R1418 (0x58a) - AIF3 Frame Ctrl 4 */
{ 0x0000058b, 0x0002 }, /* R1419 (0x58b) - AIF3 Frame Ctrl 5 */
{ 0x0000058c, 0x0003 }, /* R1420 (0x58c) - AIF3 Frame Ctrl 6 */
{ 0x0000058d, 0x0004 }, /* R1421 (0x58d) - AIF3 Frame Ctrl 7 */
{ 0x0000058e, 0x0005 }, /* R1422 (0x58e) - AIF3 Frame Ctrl 8 */
{ 0x0000058f, 0x0006 }, /* R1423 (0x58f) - AIF3 Frame Ctrl 9 */
{ 0x00000590, 0x0007 }, /* R1424 (0x590) - AIF3 Frame Ctrl 10 */
{ 0x00000591, 0x0000 }, /* R1425 (0x591) - AIF3 Frame Ctrl 11 */
{ 0x00000592, 0x0001 }, /* R1426 (0x592) - AIF3 Frame Ctrl 12 */
{ 0x00000593, 0x0002 }, /* R1427 (0x593) - AIF3 Frame Ctrl 13 */
{ 0x00000594, 0x0003 }, /* R1428 (0x594) - AIF3 Frame Ctrl 14 */
{ 0x00000595, 0x0004 }, /* R1429 (0x595) - AIF3 Frame Ctrl 15 */
{ 0x00000596, 0x0005 }, /* R1430 (0x596) - AIF3 Frame Ctrl 16 */
{ 0x00000597, 0x0006 }, /* R1431 (0x597) - AIF3 Frame Ctrl 17 */
{ 0x00000598, 0x0007 }, /* R1432 (0x598) - AIF3 Frame Ctrl 18 */
{ 0x00000599, 0x0000 }, /* R1433 (0x599) - AIF3 Tx Enables */
{ 0x0000059a, 0x0000 }, /* R1434 (0x59a) - AIF3 Rx Enables */
{ 0x000005c2, 0x0000 }, /* R1474 (0x5c2) - SPD1 Tx Control */
{ 0x000005e3, 0x0000 }, /* R1507 (0x5e3) - SLIMBus Framer Ref Gear */
{ 0x000005e5, 0x0000 }, /* R1509 (0x5e5) - SLIMBus Rates 1 */
{ 0x000005e6, 0x0000 }, /* R1510 (0x5e6) - SLIMBus Rates 2 */
{ 0x000005e7, 0x0000 }, /* R1511 (0x5e7) - SLIMBus Rates 3 */
{ 0x000005e8, 0x0000 }, /* R1512 (0x5e8) - SLIMBus Rates 4 */
{ 0x000005e9, 0x0000 }, /* R1513 (0x5e9) - SLIMBus Rates 5 */
{ 0x000005ea, 0x0000 }, /* R1514 (0x5ea) - SLIMBus Rates 6 */
{ 0x000005eb, 0x0000 }, /* R1515 (0x5eb) - SLIMBus Rates 7 */
{ 0x000005ec, 0x0000 }, /* R1516 (0x5ec) - SLIMBus Rates 8 */
{ 0x000005f5, 0x0000 }, /* R1525 (0x5f5) - SLIMBus RX Channel Enable */
{ 0x000005f6, 0x0000 }, /* R1526 (0x5f6) - SLIMBus TX Channel Enable */
{ 0x00000640, 0x0000 }, /* R1600 (0x640) - PWM1MIX Input 1 Source */
{ 0x00000641, 0x0080 }, /* R1601 (0x641) - PWM1MIX Input 1 Volume */
{ 0x00000642, 0x0000 }, /* R1602 (0x642) - PWM1MIX Input 2 Source */
{ 0x00000643, 0x0080 }, /* R1603 (0x643) - PWM1MIX Input 2 Volume */
{ 0x00000644, 0x0000 }, /* R1604 (0x644) - PWM1MIX Input 3 Source */
{ 0x00000645, 0x0080 }, /* R1605 (0x645) - PWM1MIX Input 3 Volume */
{ 0x00000646, 0x0000 }, /* R1606 (0x646) - PWM1MIX Input 4 Source */
{ 0x00000647, 0x0080 }, /* R1607 (0x647) - PWM1MIX Input 4 Volume */
{ 0x00000648, 0x0000 }, /* R1608 (0x648) - PWM2MIX Input 1 Source */
{ 0x00000649, 0x0080 }, /* R1609 (0x649) - PWM2MIX Input 1 Volume */
{ 0x0000064a, 0x0000 }, /* R1610 (0x64a) - PWM2MIX Input 2 Source */
{ 0x0000064b, 0x0080 }, /* R1611 (0x64b) - PWM2MIX Input 2 Volume */
{ 0x0000064c, 0x0000 }, /* R1612 (0x64c) - PWM2MIX Input 3 Source */
{ 0x0000064d, 0x0080 }, /* R1613 (0x64d) - PWM2MIX Input 3 Volume */
{ 0x0000064e, 0x0000 }, /* R1614 (0x64e) - PWM2MIX Input 4 Source */
{ 0x0000064f, 0x0080 }, /* R1615 (0x64f) - PWM2MIX Input 4 Volume */
{ 0x00000680, 0x0000 }, /* R1664 (0x680) - OUT1LMIX Input 1 Source */
{ 0x00000681, 0x0080 }, /* R1665 (0x681) - OUT1LMIX Input 1 Volume */
{ 0x00000682, 0x0000 }, /* R1666 (0x682) - OUT1LMIX Input 2 Source */
{ 0x00000683, 0x0080 }, /* R1667 (0x683) - OUT1LMIX Input 2 Volume */
{ 0x00000684, 0x0000 }, /* R1668 (0x684) - OUT1LMIX Input 3 Source */
{ 0x00000685, 0x0080 }, /* R1669 (0x685) - OUT1LMIX Input 3 Volume */
{ 0x00000686, 0x0000 }, /* R1670 (0x686) - OUT1LMIX Input 4 Source */
{ 0x00000687, 0x0080 }, /* R1671 (0x687) - OUT1LMIX Input 4 Volume */
{ 0x00000688, 0x0000 }, /* R1672 (0x688) - OUT1RMIX Input 1 Source */
{ 0x00000689, 0x0080 }, /* R1673 (0x689) - OUT1RMIX Input 1 Volume */
{ 0x0000068a, 0x0000 }, /* R1674 (0x68a) - OUT1RMIX Input 2 Source */
{ 0x0000068b, 0x0080 }, /* R1675 (0x68b) - OUT1RMIX Input 2 Volume */
{ 0x0000068c, 0x0000 }, /* R1676 (0x68c) - OUT1RMIX Input 3 Source */
{ 0x0000068d, 0x0080 }, /* R1677 (0x68d) - OUT1RMIX Input 3 Volume */
{ 0x0000068e, 0x0000 }, /* R1678 (0x68e) - OUT1RMIX Input 4 Source */
{ 0x0000068f, 0x0080 }, /* R1679 (0x68f) - OUT1RMIX Input 4 Volume */
{ 0x00000690, 0x0000 }, /* R1680 (0x690) - OUT2LMIX Input 1 Source */
{ 0x00000691, 0x0080 }, /* R1681 (0x691) - OUT2LMIX Input 1 Volume */
{ 0x00000692, 0x0000 }, /* R1682 (0x692) - OUT2LMIX Input 2 Source */
{ 0x00000693, 0x0080 }, /* R1683 (0x693) - OUT2LMIX Input 2 Volume */
{ 0x00000694, 0x0000 }, /* R1684 (0x694) - OUT2LMIX Input 3 Source */
{ 0x00000695, 0x0080 }, /* R1685 (0x695) - OUT2LMIX Input 3 Volume */
{ 0x00000696, 0x0000 }, /* R1686 (0x696) - OUT2LMIX Input 4 Source */
{ 0x00000697, 0x0080 }, /* R1687 (0x697) - OUT2LMIX Input 4 Volume */
{ 0x00000698, 0x0000 }, /* R1688 (0x698) - OUT2RMIX Input 1 Source */
{ 0x00000699, 0x0080 }, /* R1689 (0x699) - OUT2RMIX Input 1 Volume */
{ 0x0000069a, 0x0000 }, /* R1690 (0x69a) - OUT2RMIX Input 2 Source */
{ 0x0000069b, 0x0080 }, /* R1691 (0x69b) - OUT2RMIX Input 2 Volume */
{ 0x0000069c, 0x0000 }, /* R1692 (0x69c) - OUT2RMIX Input 3 Source */
{ 0x0000069d, 0x0080 }, /* R1693 (0x69d) - OUT2RMIX Input 3 Volume */
{ 0x0000069e, 0x0000 }, /* R1694 (0x69e) - OUT2RMIX Input 4 Source */
{ 0x0000069f, 0x0080 }, /* R1695 (0x69f) - OUT2RMIX Input 4 Volume */
{ 0x000006a0, 0x0000 }, /* R1696 (0x6a0) - OUT3LMIX Input 1 Source */
{ 0x000006a1, 0x0080 }, /* R1697 (0x6a1) - OUT3LMIX Input 1 Volume */
{ 0x000006a2, 0x0000 }, /* R1698 (0x6a2) - OUT3LMIX Input 2 Source */
{ 0x000006a3, 0x0080 }, /* R1699 (0x6a3) - OUT3LMIX Input 2 Volume */
{ 0x000006a4, 0x0000 }, /* R1700 (0x6a4) - OUT3LMIX Input 3 Source */
{ 0x000006a5, 0x0080 }, /* R1701 (0x6a5) - OUT3LMIX Input 3 Volume */
{ 0x000006a6, 0x0000 }, /* R1702 (0x6a6) - OUT3LMIX Input 4 Source */
{ 0x000006a7, 0x0080 }, /* R1703 (0x6a7) - OUT3LMIX Input 4 Volume */
{ 0x000006a8, 0x0000 }, /* R1704 (0x6a8) - OUT3RMIX Input 1 Source */
{ 0x000006a9, 0x0080 }, /* R1705 (0x6a9) - OUT3RMIX Input 1 Volume */
{ 0x000006aa, 0x0000 }, /* R1706 (0x6aa) - OUT3RMIX Input 2 Source */
{ 0x000006ab, 0x0080 }, /* R1707 (0x6ab) - OUT3RMIX Input 2 Volume */
{ 0x000006ac, 0x0000 }, /* R1708 (0x6ac) - OUT3RMIX Input 3 Source */
{ 0x000006ad, 0x0080 }, /* R1709 (0x6ad) - OUT3RMIX Input 3 Volume */
{ 0x000006ae, 0x0000 }, /* R1710 (0x6ae) - OUT3RMIX Input 4 Source */
{ 0x000006af, 0x0080 }, /* R1711 (0x6af) - OUT3RMIX Input 4 Volume */
{ 0x000006c0, 0x0000 }, /* R1728 (0x6c0) - OUT5LMIX Input 1 Source */
{ 0x000006c1, 0x0080 }, /* R1729 (0x6c1) - OUT5LMIX Input 1 Volume */
{ 0x000006c2, 0x0000 }, /* R1730 (0x6c2) - OUT5LMIX Input 2 Source */
{ 0x000006c3, 0x0080 }, /* R1731 (0x6c3) - OUT5LMIX Input 2 Volume */
{ 0x000006c4, 0x0000 }, /* R1732 (0x6c4) - OUT5LMIX Input 3 Source */
{ 0x000006c5, 0x0080 }, /* R1733 (0x6c5) - OUT5LMIX Input 3 Volume */
{ 0x000006c6, 0x0000 }, /* R1734 (0x6c6) - OUT5LMIX Input 4 Source */
{ 0x000006c7, 0x0080 }, /* R1735 (0x6c7) - OUT5LMIX Input 4 Volume */
{ 0x000006c8, 0x0000 }, /* R1736 (0x6c8) - OUT5RMIX Input 1 Source */
{ 0x000006c9, 0x0080 }, /* R1737 (0x6c9) - OUT5RMIX Input 1 Volume */
{ 0x000006ca, 0x0000 }, /* R1738 (0x6ca) - OUT5RMIX Input 2 Source */
{ 0x000006cb, 0x0080 }, /* R1739 (0x6cb) - OUT5RMIX Input 2 Volume */
{ 0x000006cc, 0x0000 }, /* R1740 (0x6cc) - OUT5RMIX Input 3 Source */
{ 0x000006cd, 0x0080 }, /* R1741 (0x6cd) - OUT5RMIX Input 3 Volume */
{ 0x000006ce, 0x0000 }, /* R1742 (0x6ce) - OUT5RMIX Input 4 Source */
{ 0x000006cf, 0x0080 }, /* R1743 (0x6cf) - OUT5RMIX Input 4 Volume */
{ 0x00000700, 0x0000 }, /* R1792 (0x700) - AIF1TX1MIX Input 1 Source */
{ 0x00000701, 0x0080 }, /* R1793 (0x701) - AIF1TX1MIX Input 1 Volume */
{ 0x00000702, 0x0000 }, /* R1794 (0x702) - AIF1TX1MIX Input 2 Source */
{ 0x00000703, 0x0080 }, /* R1795 (0x703) - AIF1TX1MIX Input 2 Volume */
{ 0x00000704, 0x0000 }, /* R1796 (0x704) - AIF1TX1MIX Input 3 Source */
{ 0x00000705, 0x0080 }, /* R1797 (0x705) - AIF1TX1MIX Input 3 Volume */
{ 0x00000706, 0x0000 }, /* R1798 (0x706) - AIF1TX1MIX Input 4 Source */
{ 0x00000707, 0x0080 }, /* R1799 (0x707) - AIF1TX1MIX Input 4 Volume */
{ 0x00000708, 0x0000 }, /* R1800 (0x708) - AIF1TX2MIX Input 1 Source */
{ 0x00000709, 0x0080 }, /* R1801 (0x709) - AIF1TX2MIX Input 1 Volume */
{ 0x0000070a, 0x0000 }, /* R1802 (0x70a) - AIF1TX2MIX Input 2 Source */
{ 0x0000070b, 0x0080 }, /* R1803 (0x70b) - AIF1TX2MIX Input 2 Volume */
{ 0x0000070c, 0x0000 }, /* R1804 (0x70c) - AIF1TX2MIX Input 3 Source */
{ 0x0000070d, 0x0080 }, /* R1805 (0x70d) - AIF1TX2MIX Input 3 Volume */
{ 0x0000070e, 0x0000 }, /* R1806 (0x70e) - AIF1TX2MIX Input 4 Source */
{ 0x0000070f, 0x0080 }, /* R1807 (0x70f) - AIF1TX2MIX Input 4 Volume */
{ 0x00000710, 0x0000 }, /* R1808 (0x710) - AIF1TX3MIX Input 1 Source */
{ 0x00000711, 0x0080 }, /* R1809 (0x711) - AIF1TX3MIX Input 1 Volume */
{ 0x00000712, 0x0000 }, /* R1810 (0x712) - AIF1TX3MIX Input 2 Source */
{ 0x00000713, 0x0080 }, /* R1811 (0x713) - AIF1TX3MIX Input 2 Volume */
{ 0x00000714, 0x0000 }, /* R1812 (0x714) - AIF1TX3MIX Input 3 Source */
{ 0x00000715, 0x0080 }, /* R1813 (0x715) - AIF1TX3MIX Input 3 Volume */
{ 0x00000716, 0x0000 }, /* R1814 (0x716) - AIF1TX3MIX Input 4 Source */
{ 0x00000717, 0x0080 }, /* R1815 (0x717) - AIF1TX3MIX Input 4 Volume */
{ 0x00000718, 0x0000 }, /* R1816 (0x718) - AIF1TX4MIX Input 1 Source */
{ 0x00000719, 0x0080 }, /* R1817 (0x719) - AIF1TX4MIX Input 1 Volume */
{ 0x0000071a, 0x0000 }, /* R1818 (0x71a) - AIF1TX4MIX Input 2 Source */
{ 0x0000071b, 0x0080 }, /* R1819 (0x71b) - AIF1TX4MIX Input 2 Volume */
{ 0x0000071c, 0x0000 }, /* R1820 (0x71c) - AIF1TX4MIX Input 3 Source */
{ 0x0000071d, 0x0080 }, /* R1821 (0x71d) - AIF1TX4MIX Input 3 Volume */
{ 0x0000071e, 0x0000 }, /* R1822 (0x71e) - AIF1TX4MIX Input 4 Source */
{ 0x0000071f, 0x0080 }, /* R1823 (0x71f) - AIF1TX4MIX Input 4 Volume */
{ 0x00000720, 0x0000 }, /* R1824 (0x720) - AIF1TX5MIX Input 1 Source */
{ 0x00000721, 0x0080 }, /* R1825 (0x721) - AIF1TX5MIX Input 1 Volume */
{ 0x00000722, 0x0000 }, /* R1826 (0x722) - AIF1TX5MIX Input 2 Source */
{ 0x00000723, 0x0080 }, /* R1827 (0x723) - AIF1TX5MIX Input 2 Volume */
{ 0x00000724, 0x0000 }, /* R1828 (0x724) - AIF1TX5MIX Input 3 Source */
{ 0x00000725, 0x0080 }, /* R1829 (0x725) - AIF1TX5MIX Input 3 Volume */
{ 0x00000726, 0x0000 }, /* R1830 (0x726) - AIF1TX5MIX Input 4 Source */
{ 0x00000727, 0x0080 }, /* R1831 (0x727) - AIF1TX5MIX Input 4 Volume */
{ 0x00000728, 0x0000 }, /* R1832 (0x728) - AIF1TX6MIX Input 1 Source */
{ 0x00000729, 0x0080 }, /* R1833 (0x729) - AIF1TX6MIX Input 1 Volume */
{ 0x0000072a, 0x0000 }, /* R1834 (0x72a) - AIF1TX6MIX Input 2 Source */
{ 0x0000072b, 0x0080 }, /* R1835 (0x72b) - AIF1TX6MIX Input 2 Volume */
{ 0x0000072c, 0x0000 }, /* R1836 (0x72c) - AIF1TX6MIX Input 3 Source */
{ 0x0000072d, 0x0080 }, /* R1837 (0x72d) - AIF1TX6MIX Input 3 Volume */
{ 0x0000072e, 0x0000 }, /* R1838 (0x72e) - AIF1TX6MIX Input 4 Source */
{ 0x0000072f, 0x0080 }, /* R1839 (0x72f) - AIF1TX6MIX Input 4 Volume */
{ 0x00000730, 0x0000 }, /* R1840 (0x730) - AIF1TX7MIX Input 1 Source */
{ 0x00000731, 0x0080 }, /* R1841 (0x731) - AIF1TX7MIX Input 1 Volume */
{ 0x00000732, 0x0000 }, /* R1842 (0x732) - AIF1TX7MIX Input 2 Source */
{ 0x00000733, 0x0080 }, /* R1843 (0x733) - AIF1TX7MIX Input 2 Volume */
{ 0x00000734, 0x0000 }, /* R1844 (0x734) - AIF1TX7MIX Input 3 Source */
{ 0x00000735, 0x0080 }, /* R1845 (0x735) - AIF1TX7MIX Input 3 Volume */
{ 0x00000736, 0x0000 }, /* R1846 (0x736) - AIF1TX7MIX Input 4 Source */
{ 0x00000737, 0x0080 }, /* R1847 (0x737) - AIF1TX7MIX Input 4 Volume */
{ 0x00000738, 0x0000 }, /* R1848 (0x738) - AIF1TX8MIX Input 1 Source */
{ 0x00000739, 0x0080 }, /* R1849 (0x739) - AIF1TX8MIX Input 1 Volume */
{ 0x0000073a, 0x0000 }, /* R1850 (0x73a) - AIF1TX8MIX Input 2 Source */
{ 0x0000073b, 0x0080 }, /* R1851 (0x73b) - AIF1TX8MIX Input 2 Volume */
{ 0x0000073c, 0x0000 }, /* R1852 (0x73c) - AIF1TX8MIX Input 3 Source */
{ 0x0000073d, 0x0080 }, /* R1853 (0x73d) - AIF1TX8MIX Input 3 Volume */
{ 0x0000073e, 0x0000 }, /* R1854 (0x73e) - AIF1TX8MIX Input 4 Source */
{ 0x0000073f, 0x0080 }, /* R1855 (0x73f) - AIF1TX8MIX Input 4 Volume */
{ 0x00000740, 0x0000 }, /* R1856 (0x740) - AIF2TX1MIX Input 1 Source */
{ 0x00000741, 0x0080 }, /* R1857 (0x741) - AIF2TX1MIX Input 1 Volume */
{ 0x00000742, 0x0000 }, /* R1858 (0x742) - AIF2TX1MIX Input 2 Source */
{ 0x00000743, 0x0080 }, /* R1859 (0x743) - AIF2TX1MIX Input 2 Volume */
{ 0x00000744, 0x0000 }, /* R1860 (0x744) - AIF2TX1MIX Input 3 Source */
{ 0x00000745, 0x0080 }, /* R1861 (0x745) - AIF2TX1MIX Input 3 Volume */
{ 0x00000746, 0x0000 }, /* R1862 (0x746) - AIF2TX1MIX Input 4 Source */
{ 0x00000747, 0x0080 }, /* R1863 (0x747) - AIF2TX1MIX Input 4 Volume */
{ 0x00000748, 0x0000 }, /* R1864 (0x748) - AIF2TX2MIX Input 1 Source */
{ 0x00000749, 0x0080 }, /* R1865 (0x749) - AIF2TX2MIX Input 1 Volume */
{ 0x0000074a, 0x0000 }, /* R1866 (0x74a) - AIF2TX2MIX Input 2 Source */
{ 0x0000074b, 0x0080 }, /* R1867 (0x74b) - AIF2TX2MIX Input 2 Volume */
{ 0x0000074c, 0x0000 }, /* R1868 (0x74c) - AIF2TX2MIX Input 3 Source */
{ 0x0000074d, 0x0080 }, /* R1869 (0x74d) - AIF2TX2MIX Input 3 Volume */
{ 0x0000074e, 0x0000 }, /* R1870 (0x74e) - AIF2TX2MIX Input 4 Source */
{ 0x0000074f, 0x0080 }, /* R1871 (0x74f) - AIF2TX2MIX Input 4 Volume */
{ 0x00000750, 0x0000 }, /* R1872 (0x750) - AIF2TX3MIX Input 1 Source */
{ 0x00000751, 0x0080 }, /* R1873 (0x751) - AIF2TX3MIX Input 1 Volume */
{ 0x00000752, 0x0000 }, /* R1874 (0x752) - AIF2TX3MIX Input 2 Source */
{ 0x00000753, 0x0080 }, /* R1875 (0x753) - AIF2TX3MIX Input 2 Volume */
{ 0x00000754, 0x0000 }, /* R1876 (0x754) - AIF2TX3MIX Input 3 Source */
{ 0x00000755, 0x0080 }, /* R1877 (0x755) - AIF2TX3MIX Input 3 Volume */
{ 0x00000756, 0x0000 }, /* R1878 (0x756) - AIF2TX3MIX Input 4 Source */
{ 0x00000757, 0x0080 }, /* R1879 (0x757) - AIF2TX3MIX Input 4 Volume */
{ 0x00000758, 0x0000 }, /* R1880 (0x758) - AIF2TX4MIX Input 1 Source */
{ 0x00000759, 0x0080 }, /* R1881 (0x759) - AIF2TX4MIX Input 1 Volume */
{ 0x0000075a, 0x0000 }, /* R1882 (0x75a) - AIF2TX4MIX Input 2 Source */
{ 0x0000075b, 0x0080 }, /* R1883 (0x75b) - AIF2TX4MIX Input 2 Volume */
{ 0x0000075c, 0x0000 }, /* R1884 (0x75c) - AIF2TX4MIX Input 3 Source */
{ 0x0000075d, 0x0080 }, /* R1885 (0x75d) - AIF2TX4MIX Input 3 Volume */
{ 0x0000075e, 0x0000 }, /* R1886 (0x75e) - AIF2TX4MIX Input 4 Source */
{ 0x0000075f, 0x0080 }, /* R1887 (0x75f) - AIF2TX4MIX Input 4 Volume */
{ 0x00000760, 0x0000 }, /* R1888 (0x760) - AIF2TX5MIX Input 1 Source */
{ 0x00000761, 0x0080 }, /* R1889 (0x761) - AIF2TX5MIX Input 1 Volume */
{ 0x00000762, 0x0000 }, /* R1890 (0x762) - AIF2TX5MIX Input 2 Source */
{ 0x00000763, 0x0080 }, /* R1891 (0x763) - AIF2TX5MIX Input 2 Volume */
{ 0x00000764, 0x0000 }, /* R1892 (0x764) - AIF2TX5MIX Input 3 Source */
{ 0x00000765, 0x0080 }, /* R1893 (0x765) - AIF2TX5MIX Input 3 Volume */
{ 0x00000766, 0x0000 }, /* R1894 (0x766) - AIF2TX5MIX Input 4 Source */
{ 0x00000767, 0x0080 }, /* R1895 (0x767) - AIF2TX5MIX Input 4 Volume */
{ 0x00000768, 0x0000 }, /* R1896 (0x768) - AIF2TX6MIX Input 1 Source */
{ 0x00000769, 0x0080 }, /* R1897 (0x769) - AIF2TX6MIX Input 1 Volume */
{ 0x0000076a, 0x0000 }, /* R1898 (0x76a) - AIF2TX6MIX Input 2 Source */
{ 0x0000076b, 0x0080 }, /* R1899 (0x76b) - AIF2TX6MIX Input 2 Volume */
{ 0x0000076c, 0x0000 }, /* R1900 (0x76c) - AIF2TX6MIX Input 3 Source */
{ 0x0000076d, 0x0080 }, /* R1901 (0x76d) - AIF2TX6MIX Input 3 Volume */
{ 0x0000076e, 0x0000 }, /* R1902 (0x76e) - AIF2TX6MIX Input 4 Source */
{ 0x0000076f, 0x0080 }, /* R1903 (0x76f) - AIF2TX6MIX Input 4 Volume */
{ 0x00000770, 0x0000 }, /* R1904 (0x770) - AIF2TX7MIX Input 1 Source */
{ 0x00000771, 0x0080 }, /* R1905 (0x771) - AIF2TX7MIX Input 1 Volume */
{ 0x00000772, 0x0000 }, /* R1906 (0x772) - AIF2TX7MIX Input 2 Source */
{ 0x00000773, 0x0080 }, /* R1907 (0x773) - AIF2TX7MIX Input 2 Volume */
{ 0x00000774, 0x0000 }, /* R1908 (0x774) - AIF2TX7MIX Input 3 Source */
{ 0x00000775, 0x0080 }, /* R1909 (0x775) - AIF2TX7MIX Input 3 Volume */
{ 0x00000776, 0x0000 }, /* R1910 (0x776) - AIF2TX7MIX Input 4 Source */
{ 0x00000777, 0x0080 }, /* R1911 (0x777) - AIF2TX7MIX Input 4 Volume */
{ 0x00000778, 0x0000 }, /* R1912 (0x778) - AIF2TX8MIX Input 1 Source */
{ 0x00000779, 0x0080 }, /* R1913 (0x779) - AIF2TX8MIX Input 1 Volume */
{ 0x0000077a, 0x0000 }, /* R1914 (0x77a) - AIF2TX8MIX Input 2 Source */
{ 0x0000077b, 0x0080 }, /* R1915 (0x77b) - AIF2TX8MIX Input 2 Volume */
{ 0x0000077c, 0x0000 }, /* R1916 (0x77c) - AIF2TX8MIX Input 3 Source */
{ 0x0000077d, 0x0080 }, /* R1917 (0x77d) - AIF2TX8MIX Input 3 Volume */
{ 0x0000077e, 0x0000 }, /* R1918 (0x77e) - AIF2TX8MIX Input 4 Source */
{ 0x0000077f, 0x0080 }, /* R1919 (0x77f) - AIF2TX8MIX Input 4 Volume */
{ 0x00000780, 0x0000 }, /* R1920 (0x780) - AIF3TX1MIX Input 1 Source */
{ 0x00000781, 0x0080 }, /* R1921 (0x781) - AIF3TX1MIX Input 1 Volume */
{ 0x00000782, 0x0000 }, /* R1922 (0x782) - AIF3TX1MIX Input 2 Source */
{ 0x00000783, 0x0080 }, /* R1923 (0x783) - AIF3TX1MIX Input 2 Volume */
{ 0x00000784, 0x0000 }, /* R1924 (0x784) - AIF3TX1MIX Input 3 Source */
{ 0x00000785, 0x0080 }, /* R1925 (0x785) - AIF3TX1MIX Input 3 Volume */
{ 0x00000786, 0x0000 }, /* R1926 (0x786) - AIF3TX1MIX Input 4 Source */
{ 0x00000787, 0x0080 }, /* R1927 (0x787) - AIF3TX1MIX Input 4 Volume */
{ 0x00000788, 0x0000 }, /* R1928 (0x788) - AIF3TX2MIX Input 1 Source */
{ 0x00000789, 0x0080 }, /* R1929 (0x789) - AIF3TX2MIX Input 1 Volume */
{ 0x0000078a, 0x0000 }, /* R1930 (0x78a) - AIF3TX2MIX Input 2 Source */
{ 0x0000078b, 0x0080 }, /* R1931 (0x78b) - AIF3TX2MIX Input 2 Volume */
{ 0x0000078c, 0x0000 }, /* R1932 (0x78c) - AIF3TX2MIX Input 3 Source */
{ 0x0000078d, 0x0080 }, /* R1933 (0x78d) - AIF3TX2MIX Input 3 Volume */
{ 0x0000078e, 0x0000 }, /* R1934 (0x78e) - AIF3TX2MIX Input 4 Source */
{ 0x0000078f, 0x0080 }, /* R1935 (0x78f) - AIF3TX2MIX Input 4 Volume */
{ 0x00000790, 0x0000 }, /* R1936 (0x790) - AIF3TX3MIX Input 1 Source */
{ 0x00000791, 0x0080 }, /* R1937 (0x791) - AIF3TX3MIX Input 1 Volume */
{ 0x00000792, 0x0000 }, /* R1938 (0x792) - AIF3TX3MIX Input 2 Source */
{ 0x00000793, 0x0080 }, /* R1939 (0x793) - AIF3TX3MIX Input 2 Volume */
{ 0x00000794, 0x0000 }, /* R1940 (0x794) - AIF3TX3MIX Input 3 Source */
{ 0x00000795, 0x0080 }, /* R1941 (0x795) - AIF3TX3MIX Input 3 Volume */
{ 0x00000796, 0x0000 }, /* R1942 (0x796) - AIF3TX3MIX Input 4 Source */
{ 0x00000797, 0x0080 }, /* R1943 (0x797) - AIF3TX3MIX Input 4 Volume */
{ 0x00000798, 0x0000 }, /* R1944 (0x798) - AIF3TX4MIX Input 1 Source */
{ 0x00000799, 0x0080 }, /* R1945 (0x799) - AIF3TX4MIX Input 1 Volume */
{ 0x0000079a, 0x0000 }, /* R1946 (0x79a) - AIF3TX4MIX Input 2 Source */
{ 0x0000079b, 0x0080 }, /* R1947 (0x79b) - AIF3TX4MIX Input 2 Volume */
{ 0x0000079c, 0x0000 }, /* R1948 (0x79c) - AIF3TX4MIX Input 3 Source */
{ 0x0000079d, 0x0080 }, /* R1949 (0x79d) - AIF3TX4MIX Input 3 Volume */
{ 0x0000079e, 0x0000 }, /* R1950 (0x79e) - AIF3TX4MIX Input 4 Source */
{ 0x0000079f, 0x0080 }, /* R1951 (0x79f) - AIF3TX4MIX Input 4 Volume */
{ 0x000007a0, 0x0000 }, /* R1952 (0x7a0) - AIF3TX5MIX Input 1 Source */
{ 0x000007a1, 0x0080 }, /* R1953 (0x7a1) - AIF3TX5MIX Input 1 Volume */
{ 0x000007a2, 0x0000 }, /* R1954 (0x7a2) - AIF3TX5MIX Input 2 Source */
{ 0x000007a3, 0x0080 }, /* R1955 (0x7a3) - AIF3TX5MIX Input 2 Volume */
{ 0x000007a4, 0x0000 }, /* R1956 (0x7a4) - AIF3TX5MIX Input 3 Source */
{ 0x000007a5, 0x0080 }, /* R1957 (0x7a5) - AIF3TX5MIX Input 3 Volume */
{ 0x000007a6, 0x0000 }, /* R1958 (0x7a6) - AIF3TX5MIX Input 4 Source */
{ 0x000007a7, 0x0080 }, /* R1959 (0x7a7) - AIF3TX5MIX Input 4 Volume */
{ 0x000007a8, 0x0000 }, /* R1960 (0x7a8) - AIF3TX6MIX Input 1 Source */
{ 0x000007a9, 0x0080 }, /* R1961 (0x7a9) - AIF3TX6MIX Input 1 Volume */
{ 0x000007aa, 0x0000 }, /* R1962 (0x7aa) - AIF3TX6MIX Input 2 Source */
{ 0x000007ab, 0x0080 }, /* R1963 (0x7ab) - AIF3TX6MIX Input 2 Volume */
{ 0x000007ac, 0x0000 }, /* R1964 (0x7ac) - AIF3TX6MIX Input 3 Source */
{ 0x000007ad, 0x0080 }, /* R1965 (0x7ad) - AIF3TX6MIX Input 3 Volume */
{ 0x000007ae, 0x0000 }, /* R1966 (0x7ae) - AIF3TX6MIX Input 4 Source */
{ 0x000007af, 0x0080 }, /* R1967 (0x7af) - AIF3TX6MIX Input 4 Volume */
{ 0x000007b0, 0x0000 }, /* R1968 (0x7b0) - AIF3TX7MIX Input 1 Source */
{ 0x000007b1, 0x0080 }, /* R1969 (0x7b1) - AIF3TX7MIX Input 1 Volume */
{ 0x000007b2, 0x0000 }, /* R1970 (0x7b2) - AIF3TX7MIX Input 2 Source */
{ 0x000007b3, 0x0080 }, /* R1971 (0x7b3) - AIF3TX7MIX Input 2 Volume */
{ 0x000007b4, 0x0000 }, /* R1972 (0x7b4) - AIF3TX7MIX Input 3 Source */
{ 0x000007b5, 0x0080 }, /* R1973 (0x7b5) - AIF3TX7MIX Input 3 Volume */
{ 0x000007b6, 0x0000 }, /* R1974 (0x7b6) - AIF3TX7MIX Input 4 Source */
{ 0x000007b7, 0x0080 }, /* R1975 (0x7b7) - AIF3TX7MIX Input 4 Volume */
{ 0x000007b8, 0x0000 }, /* R1976 (0x7b8) - AIF3TX8MIX Input 1 Source */
{ 0x000007b9, 0x0080 }, /* R1977 (0x7b9) - AIF3TX8MIX Input 1 Volume */
{ 0x000007ba, 0x0000 }, /* R1978 (0x7ba) - AIF3TX8MIX Input 2 Source */
{ 0x000007bb, 0x0080 }, /* R1979 (0x7bb) - AIF3TX8MIX Input 2 Volume */
{ 0x000007bc, 0x0000 }, /* R1980 (0x7bc) - AIF3TX8MIX Input 3 Source */
{ 0x000007bd, 0x0080 }, /* R1981 (0x7bd) - AIF3TX8MIX Input 3 Volume */
{ 0x000007be, 0x0000 }, /* R1982 (0x7be) - AIF3TX8MIX Input 4 Source */
{ 0x000007bf, 0x0080 }, /* R1983 (0x7bf) - AIF3TX8MIX Input 4 Volume */
{ 0x000007c0, 0x0000 }, /* R1984 (0x7c0) - SLIMTX1MIX Input 1 Source */
{ 0x000007c1, 0x0080 }, /* R1985 (0x7c1) - SLIMTX1MIX Input 1 Volume */
{ 0x000007c2, 0x0000 }, /* R1986 (0x7c2) - SLIMTX1MIX Input 2 Source */
{ 0x000007c3, 0x0080 }, /* R1987 (0x7c3) - SLIMTX1MIX Input 2 Volume */
{ 0x000007c4, 0x0000 }, /* R1988 (0x7c4) - SLIMTX1MIX Input 3 Source */
{ 0x000007c5, 0x0080 }, /* R1989 (0x7c5) - SLIMTX1MIX Input 3 Volume */
{ 0x000007c6, 0x0000 }, /* R1990 (0x7c6) - SLIMTX1MIX Input 4 Source */
{ 0x000007c7, 0x0080 }, /* R1991 (0x7c7) - SLIMTX1MIX Input 4 Volume */
{ 0x000007c8, 0x0000 }, /* R1992 (0x7c8) - SLIMTX2MIX Input 1 Source */
{ 0x000007c9, 0x0080 }, /* R1993 (0x7c9) - SLIMTX2MIX Input 1 Volume */
{ 0x000007ca, 0x0000 }, /* R1994 (0x7ca) - SLIMTX2MIX Input 2 Source */
{ 0x000007cb, 0x0080 }, /* R1995 (0x7cb) - SLIMTX2MIX Input 2 Volume */
{ 0x000007cc, 0x0000 }, /* R1996 (0x7cc) - SLIMTX2MIX Input 3 Source */
{ 0x000007cd, 0x0080 }, /* R1997 (0x7cd) - SLIMTX2MIX Input 3 Volume */
{ 0x000007ce, 0x0000 }, /* R1998 (0x7ce) - SLIMTX2MIX Input 4 Source */
{ 0x000007cf, 0x0080 }, /* R1999 (0x7cf) - SLIMTX2MIX Input 4 Volume */
{ 0x000007d0, 0x0000 }, /* R2000 (0x7d0) - SLIMTX3MIX Input 1 Source */
{ 0x000007d1, 0x0080 }, /* R2001 (0x7d1) - SLIMTX3MIX Input 1 Volume */
{ 0x000007d2, 0x0000 }, /* R2002 (0x7d2) - SLIMTX3MIX Input 2 Source */
{ 0x000007d3, 0x0080 }, /* R2003 (0x7d3) - SLIMTX3MIX Input 2 Volume */
{ 0x000007d4, 0x0000 }, /* R2004 (0x7d4) - SLIMTX3MIX Input 3 Source */
{ 0x000007d5, 0x0080 }, /* R2005 (0x7d5) - SLIMTX3MIX Input 3 Volume */
{ 0x000007d6, 0x0000 }, /* R2006 (0x7d6) - SLIMTX3MIX Input 4 Source */
{ 0x000007d7, 0x0080 }, /* R2007 (0x7d7) - SLIMTX3MIX Input 4 Volume */
{ 0x000007d8, 0x0000 }, /* R2008 (0x7d8) - SLIMTX4MIX Input 1 Source */
{ 0x000007d9, 0x0080 }, /* R2009 (0x7d9) - SLIMTX4MIX Input 1 Volume */
{ 0x000007da, 0x0000 }, /* R2010 (0x7da) - SLIMTX4MIX Input 2 Source */
{ 0x000007db, 0x0080 }, /* R2011 (0x7db) - SLIMTX4MIX Input 2 Volume */
{ 0x000007dc, 0x0000 }, /* R2012 (0x7dc) - SLIMTX4MIX Input 3 Source */
{ 0x000007dd, 0x0080 }, /* R2013 (0x7dd) - SLIMTX4MIX Input 3 Volume */
{ 0x000007de, 0x0000 }, /* R2014 (0x7de) - SLIMTX4MIX Input 4 Source */
{ 0x000007df, 0x0080 }, /* R2015 (0x7df) - SLIMTX4MIX Input 4 Volume */
{ 0x000007e0, 0x0000 }, /* R2016 (0x7e0) - SLIMTX5MIX Input 1 Source */
{ 0x000007e1, 0x0080 }, /* R2017 (0x7e1) - SLIMTX5MIX Input 1 Volume */
{ 0x000007e2, 0x0000 }, /* R2018 (0x7e2) - SLIMTX5MIX Input 2 Source */
{ 0x000007e3, 0x0080 }, /* R2019 (0x7e3) - SLIMTX5MIX Input 2 Volume */
{ 0x000007e4, 0x0000 }, /* R2020 (0x7e4) - SLIMTX5MIX Input 3 Source */
{ 0x000007e5, 0x0080 }, /* R2021 (0x7e5) - SLIMTX5MIX Input 3 Volume */
{ 0x000007e6, 0x0000 }, /* R2022 (0x7e6) - SLIMTX5MIX Input 4 Source */
{ 0x000007e7, 0x0080 }, /* R2023 (0x7e7) - SLIMTX5MIX Input 4 Volume */
{ 0x000007e8, 0x0000 }, /* R2024 (0x7e8) - SLIMTX6MIX Input 1 Source */
{ 0x000007e9, 0x0080 }, /* R2025 (0x7e9) - SLIMTX6MIX Input 1 Volume */
{ 0x000007ea, 0x0000 }, /* R2026 (0x7ea) - SLIMTX6MIX Input 2 Source */
{ 0x000007eb, 0x0080 }, /* R2027 (0x7eb) - SLIMTX6MIX Input 2 Volume */
{ 0x000007ec, 0x0000 }, /* R2028 (0x7ec) - SLIMTX6MIX Input 3 Source */
{ 0x000007ed, 0x0080 }, /* R2029 (0x7ed) - SLIMTX6MIX Input 3 Volume */
{ 0x000007ee, 0x0000 }, /* R2030 (0x7ee) - SLIMTX6MIX Input 4 Source */
{ 0x000007ef, 0x0080 }, /* R2031 (0x7ef) - SLIMTX6MIX Input 4 Volume */
{ 0x000007f0, 0x0000 }, /* R2032 (0x7f0) - SLIMTX7MIX Input 1 Source */
{ 0x000007f1, 0x0080 }, /* R2033 (0x7f1) - SLIMTX7MIX Input 1 Volume */
{ 0x000007f2, 0x0000 }, /* R2034 (0x7f2) - SLIMTX7MIX Input 2 Source */
{ 0x000007f3, 0x0080 }, /* R2035 (0x7f3) - SLIMTX7MIX Input 2 Volume */
{ 0x000007f4, 0x0000 }, /* R2036 (0x7f4) - SLIMTX7MIX Input 3 Source */
{ 0x000007f5, 0x0080 }, /* R2037 (0x7f5) - SLIMTX7MIX Input 3 Volume */
{ 0x000007f6, 0x0000 }, /* R2038 (0x7f6) - SLIMTX7MIX Input 4 Source */
{ 0x000007f7, 0x0080 }, /* R2039 (0x7f7) - SLIMTX7MIX Input 4 Volume */
{ 0x000007f8, 0x0000 }, /* R2040 (0x7f8) - SLIMTX8MIX Input 1 Source */
{ 0x000007f9, 0x0080 }, /* R2041 (0x7f9) - SLIMTX8MIX Input 1 Volume */
{ 0x000007fa, 0x0000 }, /* R2042 (0x7fa) - SLIMTX8MIX Input 2 Source */
{ 0x000007fb, 0x0080 }, /* R2043 (0x7fb) - SLIMTX8MIX Input 2 Volume */
{ 0x000007fc, 0x0000 }, /* R2044 (0x7fc) - SLIMTX8MIX Input 3 Source */
{ 0x000007fd, 0x0080 }, /* R2045 (0x7fd) - SLIMTX8MIX Input 3 Volume */
{ 0x000007fe, 0x0000 }, /* R2046 (0x7fe) - SLIMTX8MIX Input 4 Source */
{ 0x000007ff, 0x0080 }, /* R2047 (0x7ff) - SLIMTX8MIX Input 4 Volume */
{ 0x00000800, 0x0000 }, /* R2048 (0x800) - SPDIF1TX1MIX Input 1 Source */
{ 0x00000801, 0x0080 }, /* R2049 (0x801) - SPDIF1TX1MIX Input 1 Volume */
{ 0x00000808, 0x0000 }, /* R2056 (0x808) - SPDIF1TX2MIX Input 1 Source */
{ 0x00000809, 0x0080 }, /* R2057 (0x809) - SPDIF1TX2MIX Input 1 Volume */
{ 0x00000880, 0x0000 }, /* R2176 (0x880) - EQ1MIX Input 1 Source */
{ 0x00000881, 0x0080 }, /* R2177 (0x881) - EQ1MIX Input 1 Volume */
{ 0x00000882, 0x0000 }, /* R2178 (0x882) - EQ1MIX Input 2 Source */
{ 0x00000883, 0x0080 }, /* R2179 (0x883) - EQ1MIX Input 2 Volume */
{ 0x00000884, 0x0000 }, /* R2180 (0x884) - EQ1MIX Input 3 Source */
{ 0x00000885, 0x0080 }, /* R2181 (0x885) - EQ1MIX Input 3 Volume */
{ 0x00000886, 0x0000 }, /* R2182 (0x886) - EQ1MIX Input 4 Source */
{ 0x00000887, 0x0080 }, /* R2183 (0x887) - EQ1MIX Input 4 Volume */
{ 0x00000888, 0x0000 }, /* R2184 (0x888) - EQ2MIX Input 1 Source */
{ 0x00000889, 0x0080 }, /* R2185 (0x889) - EQ2MIX Input 1 Volume */
{ 0x0000088a, 0x0000 }, /* R2186 (0x88a) - EQ2MIX Input 2 Source */
{ 0x0000088b, 0x0080 }, /* R2187 (0x88b) - EQ2MIX Input 2 Volume */
{ 0x0000088c, 0x0000 }, /* R2188 (0x88c) - EQ2MIX Input 3 Source */
{ 0x0000088d, 0x0080 }, /* R2189 (0x88d) - EQ2MIX Input 3 Volume */
{ 0x0000088e, 0x0000 }, /* R2190 (0x88e) - EQ2MIX Input 4 Source */
{ 0x0000088f, 0x0080 }, /* R2191 (0x88f) - EQ2MIX Input 4 Volume */
{ 0x00000890, 0x0000 }, /* R2192 (0x890) - EQ3MIX Input 1 Source */
{ 0x00000891, 0x0080 }, /* R2193 (0x891) - EQ3MIX Input 1 Volume */
{ 0x00000892, 0x0000 }, /* R2194 (0x892) - EQ3MIX Input 2 Source */
{ 0x00000893, 0x0080 }, /* R2195 (0x893) - EQ3MIX Input 2 Volume */
{ 0x00000894, 0x0000 }, /* R2196 (0x894) - EQ3MIX Input 3 Source */
{ 0x00000895, 0x0080 }, /* R2197 (0x895) - EQ3MIX Input 3 Volume */
{ 0x00000896, 0x0000 }, /* R2198 (0x896) - EQ3MIX Input 4 Source */
{ 0x00000897, 0x0080 }, /* R2199 (0x897) - EQ3MIX Input 4 Volume */
{ 0x00000898, 0x0000 }, /* R2200 (0x898) - EQ4MIX Input 1 Source */
{ 0x00000899, 0x0080 }, /* R2201 (0x899) - EQ4MIX Input 1 Volume */
{ 0x0000089a, 0x0000 }, /* R2202 (0x89a) - EQ4MIX Input 2 Source */
{ 0x0000089b, 0x0080 }, /* R2203 (0x89b) - EQ4MIX Input 2 Volume */
{ 0x0000089c, 0x0000 }, /* R2204 (0x89c) - EQ4MIX Input 3 Source */
{ 0x0000089d, 0x0080 }, /* R2205 (0x89d) - EQ4MIX Input 3 Volume */
{ 0x0000089e, 0x0000 }, /* R2206 (0x89e) - EQ4MIX Input 4 Source */
{ 0x0000089f, 0x0080 }, /* R2207 (0x89f) - EQ4MIX Input 4 Volume */
{ 0x000008c0, 0x0000 }, /* R2240 (0x8c0) - DRC1LMIX Input 1 Source */
{ 0x000008c1, 0x0080 }, /* R2241 (0x8c1) - DRC1LMIX Input 1 Volume */
{ 0x000008c2, 0x0000 }, /* R2242 (0x8c2) - DRC1LMIX Input 2 Source */
{ 0x000008c3, 0x0080 }, /* R2243 (0x8c3) - DRC1LMIX Input 2 Volume */
{ 0x000008c4, 0x0000 }, /* R2244 (0x8c4) - DRC1LMIX Input 3 Source */
{ 0x000008c5, 0x0080 }, /* R2245 (0x8c5) - DRC1LMIX Input 3 Volume */
{ 0x000008c6, 0x0000 }, /* R2246 (0x8c6) - DRC1LMIX Input 4 Source */
{ 0x000008c7, 0x0080 }, /* R2247 (0x8c7) - DRC1LMIX Input 4 Volume */
{ 0x000008c8, 0x0000 }, /* R2248 (0x8c8) - DRC1RMIX Input 1 Source */
{ 0x000008c9, 0x0080 }, /* R2249 (0x8c9) - DRC1RMIX Input 1 Volume */
{ 0x000008ca, 0x0000 }, /* R2250 (0x8ca) - DRC1RMIX Input 2 Source */
{ 0x000008cb, 0x0080 }, /* R2251 (0x8cb) - DRC1RMIX Input 2 Volume */
{ 0x000008cc, 0x0000 }, /* R2252 (0x8cc) - DRC1RMIX Input 3 Source */
{ 0x000008cd, 0x0080 }, /* R2253 (0x8cd) - DRC1RMIX Input 3 Volume */
{ 0x000008ce, 0x0000 }, /* R2254 (0x8ce) - DRC1RMIX Input 4 Source */
{ 0x000008cf, 0x0080 }, /* R2255 (0x8cf) - DRC1RMIX Input 4 Volume */
{ 0x000008d0, 0x0000 }, /* R2256 (0x8d0) - DRC2LMIX Input 1 Source */
{ 0x000008d1, 0x0080 }, /* R2257 (0x8d1) - DRC2LMIX Input 1 Volume */
{ 0x000008d2, 0x0000 }, /* R2258 (0x8d2) - DRC2LMIX Input 2 Source */
{ 0x000008d3, 0x0080 }, /* R2259 (0x8d3) - DRC2LMIX Input 2 Volume */
{ 0x000008d4, 0x0000 }, /* R2260 (0x8d4) - DRC2LMIX Input 3 Source */
{ 0x000008d5, 0x0080 }, /* R2261 (0x8d5) - DRC2LMIX Input 3 Volume */
{ 0x000008d6, 0x0000 }, /* R2262 (0x8d6) - DRC2LMIX Input 4 Source */
{ 0x000008d7, 0x0080 }, /* R2263 (0x8d7) - DRC2LMIX Input 4 Volume */
{ 0x000008d8, 0x0000 }, /* R2264 (0x8d8) - DRC2RMIX Input 1 Source */
{ 0x000008d9, 0x0080 }, /* R2265 (0x8d9) - DRC2RMIX Input 1 Volume */
{ 0x000008da, 0x0000 }, /* R2266 (0x8da) - DRC2RMIX Input 2 Source */
{ 0x000008db, 0x0080 }, /* R2267 (0x8db) - DRC2RMIX Input 2 Volume */
{ 0x000008dc, 0x0000 }, /* R2268 (0x8dc) - DRC2RMIX Input 3 Source */
{ 0x000008dd, 0x0080 }, /* R2269 (0x8dd) - DRC2RMIX Input 3 Volume */
{ 0x000008de, 0x0000 }, /* R2270 (0x8de) - DRC2RMIX Input 4 Source */
{ 0x000008df, 0x0080 }, /* R2271 (0x8df) - DRC2RMIX Input 4 Volume */
{ 0x00000900, 0x0000 }, /* R2304 (0x900) - HPLP1MIX Input 1 Source */
{ 0x00000901, 0x0080 }, /* R2305 (0x901) - HPLP1MIX Input 1 Volume */
{ 0x00000902, 0x0000 }, /* R2306 (0x902) - HPLP1MIX Input 2 Source */
{ 0x00000903, 0x0080 }, /* R2307 (0x903) - HPLP1MIX Input 2 Volume */
{ 0x00000904, 0x0000 }, /* R2308 (0x904) - HPLP1MIX Input 3 Source */
{ 0x00000905, 0x0080 }, /* R2309 (0x905) - HPLP1MIX Input 3 Volume */
{ 0x00000906, 0x0000 }, /* R2310 (0x906) - HPLP1MIX Input 4 Source */
{ 0x00000907, 0x0080 }, /* R2311 (0x907) - HPLP1MIX Input 4 Volume */
{ 0x00000908, 0x0000 }, /* R2312 (0x908) - HPLP2MIX Input 1 Source */
{ 0x00000909, 0x0080 }, /* R2313 (0x909) - HPLP2MIX Input 1 Volume */
{ 0x0000090a, 0x0000 }, /* R2314 (0x90a) - HPLP2MIX Input 2 Source */
{ 0x0000090b, 0x0080 }, /* R2315 (0x90b) - HPLP2MIX Input 2 Volume */
{ 0x0000090c, 0x0000 }, /* R2316 (0x90c) - HPLP2MIX Input 3 Source */
{ 0x0000090d, 0x0080 }, /* R2317 (0x90d) - HPLP2MIX Input 3 Volume */
{ 0x0000090e, 0x0000 }, /* R2318 (0x90e) - HPLP2MIX Input 4 Source */
{ 0x0000090f, 0x0080 }, /* R2319 (0x90f) - HPLP2MIX Input 4 Volume */
{ 0x00000910, 0x0000 }, /* R2320 (0x910) - HPLP3MIX Input 1 Source */
{ 0x00000911, 0x0080 }, /* R2321 (0x911) - HPLP3MIX Input 1 Volume */
{ 0x00000912, 0x0000 }, /* R2322 (0x912) - HPLP3MIX Input 2 Source */
{ 0x00000913, 0x0080 }, /* R2323 (0x913) - HPLP3MIX Input 2 Volume */
{ 0x00000914, 0x0000 }, /* R2324 (0x914) - HPLP3MIX Input 3 Source */
{ 0x00000915, 0x0080 }, /* R2325 (0x915) - HPLP3MIX Input 3 Volume */
{ 0x00000916, 0x0000 }, /* R2326 (0x916) - HPLP3MIX Input 4 Source */
{ 0x00000917, 0x0080 }, /* R2327 (0x917) - HPLP3MIX Input 4 Volume */
{ 0x00000918, 0x0000 }, /* R2328 (0x918) - HPLP4MIX Input 1 Source */
{ 0x00000919, 0x0080 }, /* R2329 (0x919) - HPLP4MIX Input 1 Volume */
{ 0x0000091a, 0x0000 }, /* R2330 (0x91a) - HPLP4MIX Input 2 Source */
{ 0x0000091b, 0x0080 }, /* R2331 (0x91b) - HPLP4MIX Input 2 Volume */
{ 0x0000091c, 0x0000 }, /* R2332 (0x91c) - HPLP4MIX Input 3 Source */
{ 0x0000091d, 0x0080 }, /* R2333 (0x91d) - HPLP4MIX Input 3 Volume */
{ 0x0000091e, 0x0000 }, /* R2334 (0x91e) - HPLP4MIX Input 4 Source */
{ 0x0000091f, 0x0080 }, /* R2335 (0x91f) - HPLP4MIX Input 4 Volume */
{ 0x00000940, 0x0000 }, /* R2368 (0x940) - DSP1LMIX Input 1 Source */
{ 0x00000941, 0x0080 }, /* R2369 (0x941) - DSP1LMIX Input 1 Volume */
{ 0x00000942, 0x0000 }, /* R2370 (0x942) - DSP1LMIX Input 2 Source */
{ 0x00000943, 0x0080 }, /* R2371 (0x943) - DSP1LMIX Input 2 Volume */
{ 0x00000944, 0x0000 }, /* R2372 (0x944) - DSP1LMIX Input 3 Source */
{ 0x00000945, 0x0080 }, /* R2373 (0x945) - DSP1LMIX Input 3 Volume */
{ 0x00000946, 0x0000 }, /* R2374 (0x946) - DSP1LMIX Input 4 Source */
{ 0x00000947, 0x0080 }, /* R2375 (0x947) - DSP1LMIX Input 4 Volume */
{ 0x00000948, 0x0000 }, /* R2376 (0x948) - DSP1RMIX Input 1 Source */
{ 0x00000949, 0x0080 }, /* R2377 (0x949) - DSP1RMIX Input 1 Volume */
{ 0x0000094a, 0x0000 }, /* R2378 (0x94a) - DSP1RMIX Input 2 Source */
{ 0x0000094b, 0x0080 }, /* R2379 (0x94b) - DSP1RMIX Input 2 Volume */
{ 0x0000094c, 0x0000 }, /* R2380 (0x94c) - DSP1RMIX Input 3 Source */
{ 0x0000094d, 0x0080 }, /* R2381 (0x94d) - DSP1RMIX Input 3 Volume */
{ 0x0000094e, 0x0000 }, /* R2382 (0x94e) - DSP1RMIX Input 4 Source */
{ 0x0000094f, 0x0080 }, /* R2383 (0x94f) - DSP1RMIX Input 4 Volume */
{ 0x00000950, 0x0000 }, /* R2384 (0x950) - DSP1AUX1MIX Input 1 Source */
{ 0x00000958, 0x0000 }, /* R2392 (0x958) - DSP1AUX2MIX Input 1 Source */
{ 0x00000960, 0x0000 }, /* R2400 (0x960) - DSP1AUX3MIX Input 1 Source */
{ 0x00000968, 0x0000 }, /* R2408 (0x968) - DSP1AUX4MIX Input 1 Source */
{ 0x00000970, 0x0000 }, /* R2416 (0x970) - DSP1AUX5MIX Input 1 Source */
{ 0x00000978, 0x0000 }, /* R2424 (0x978) - DSP1AUX6MIX Input 1 Source */
{ 0x00000a80, 0x0000 }, /* R2688 (0xa80) - ASRC1 1LMIX Input 1 Source */
{ 0x00000a88, 0x0000 }, /* R2696 (0xa88) - ASRC1 1RMIX Input 1 Source */
{ 0x00000a90, 0x0000 }, /* R2704 (0xa90) - ASRC1 2LMIX Input 1 Source */
{ 0x00000a98, 0x0000 }, /* R2712 (0xa98) - ASRC1 2RMIX Input 1 Source */
{ 0x00000b00, 0x0000 }, /* R2816 (0xb00) - ISRC1DEC1MIX Input 1 Source */
{ 0x00000b08, 0x0000 }, /* R2824 (0xb08) - ISRC1DEC2MIX Input 1 Source */
{ 0x00000b20, 0x0000 }, /* R2848 (0xb20) - ISRC1INT1MIX Input 1 Source */
{ 0x00000b28, 0x0000 }, /* R2856 (0xb28) - ISRC1INT2MIX Input 1 Source */
{ 0x00000b40, 0x0000 }, /* R2880 (0xb40) - ISRC2DEC1MIX Input 1 Source */
{ 0x00000b48, 0x0000 }, /* R2888 (0xb48) - ISRC2DEC2MIX Input 1 Source */
{ 0x00000b60, 0x0000 }, /* R2912 (0xb60) - ISRC2INT1MIX Input 1 Source */
{ 0x00000b68, 0x0000 }, /* R2920 (0xb68) - ISRC2INT2MIX Input 1 Source */
{ 0x00000dc0, 0x0000 }, /* R3520 (0xdc0) - DFC1MIX Input 1 Source */
{ 0x00000dc8, 0x0000 }, /* R3528 (0xdc8) - DFC2MIX Input 1 Source */
{ 0x00000dd0, 0x0000 }, /* R3536 (0xdd0) - DFC3MIX Input 1 Source */
{ 0x00000dd8, 0x0000 }, /* R3544 (0xdd8) - DFC4MIX Input 1 Source */
{ 0x00000de0, 0x0000 }, /* R3552 (0xde0) - DFC5MIX Input 1 Source */
{ 0x00000de8, 0x0000 }, /* R3560 (0xde8) - DFC6MIX Input 1 Source */
{ 0x00000df0, 0x0000 }, /* R3568 (0xdf0) - DFC7MIX Input 1 Source */
{ 0x00000df8, 0x0000 }, /* R3576 (0xdf8) - DFC8MIX Input 1 Source */
{ 0x00000e00, 0x0000 }, /* R3584 (0xe00) - FX Ctrl 1 */
{ 0x00000e10, 0x6318 }, /* R3600 (0xe10) - EQ1 1 */
{ 0x00000e11, 0x6300 }, /* R3601 (0xe11) - EQ1 2 */
{ 0x00000e12, 0x0fc8 }, /* R3602 (0xe12) - EQ1 3 */
{ 0x00000e13, 0x03fe }, /* R3603 (0xe13) - EQ1 4 */
{ 0x00000e14, 0x00e0 }, /* R3604 (0xe14) - EQ1 5 */
{ 0x00000e15, 0x1ec4 }, /* R3605 (0xe15) - EQ1 6 */
{ 0x00000e16, 0xf136 }, /* R3606 (0xe16) - EQ1 7 */
{ 0x00000e17, 0x0409 }, /* R3607 (0xe17) - EQ1 8 */
{ 0x00000e18, 0x04cc }, /* R3608 (0xe18) - EQ1 9 */
{ 0x00000e19, 0x1c9b }, /* R3609 (0xe19) - EQ1 10 */
{ 0x00000e1a, 0xf337 }, /* R3610 (0xe1a) - EQ1 11 */
{ 0x00000e1b, 0x040b }, /* R3611 (0xe1b) - EQ1 12 */
{ 0x00000e1c, 0x0cbb }, /* R3612 (0xe1c) - EQ1 13 */
{ 0x00000e1d, 0x16f8 }, /* R3613 (0xe1d) - EQ1 14 */
{ 0x00000e1e, 0xf7d9 }, /* R3614 (0xe1e) - EQ1 15 */
{ 0x00000e1f, 0x040a }, /* R3615 (0xe1f) - EQ1 16 */
{ 0x00000e20, 0x1f14 }, /* R3616 (0xe20) - EQ1 17 */
{ 0x00000e21, 0x058c }, /* R3617 (0xe21) - EQ1 18 */
{ 0x00000e22, 0x0563 }, /* R3618 (0xe22) - EQ1 19 */
{ 0x00000e23, 0x4000 }, /* R3619 (0xe23) - EQ1 20 */
{ 0x00000e24, 0x0b75 }, /* R3620 (0xe24) - EQ1 21 */
{ 0x00000e26, 0x6318 }, /* R3622 (0xe26) - EQ2 1 */
{ 0x00000e27, 0x6300 }, /* R3623 (0xe27) - EQ2 2 */
{ 0x00000e28, 0x0fc8 }, /* R3624 (0xe28) - EQ2 3 */
{ 0x00000e29, 0x03fe }, /* R3625 (0xe29) - EQ2 4 */
{ 0x00000e2a, 0x00e0 }, /* R3626 (0xe2a) - EQ2 5 */
{ 0x00000e2b, 0x1ec4 }, /* R3627 (0xe2b) - EQ2 6 */
{ 0x00000e2c, 0xf136 }, /* R3628 (0xe2c) - EQ2 7 */
{ 0x00000e2d, 0x0409 }, /* R3629 (0xe2d) - EQ2 8 */
{ 0x00000e2e, 0x04cc }, /* R3630 (0xe2e) - EQ2 9 */
{ 0x00000e2f, 0x1c9b }, /* R3631 (0xe2f) - EQ2 10 */
{ 0x00000e30, 0xf337 }, /* R3632 (0xe30) - EQ2 11 */
{ 0x00000e31, 0x040b }, /* R3633 (0xe31) - EQ2 12 */
{ 0x00000e32, 0x0cbb }, /* R3634 (0xe32) - EQ2 13 */
{ 0x00000e33, 0x16f8 }, /* R3635 (0xe33) - EQ2 14 */
{ 0x00000e34, 0xf7d9 }, /* R3636 (0xe34) - EQ2 15 */
{ 0x00000e35, 0x040a }, /* R3637 (0xe35) - EQ2 16 */
{ 0x00000e36, 0x1f14 }, /* R3638 (0xe36) - EQ2 17 */
{ 0x00000e37, 0x058c }, /* R3639 (0xe37) - EQ2 18 */
{ 0x00000e38, 0x0563 }, /* R3640 (0xe38) - EQ2 19 */
{ 0x00000e39, 0x4000 }, /* R3641 (0xe39) - EQ2 20 */
{ 0x00000e3a, 0x0b75 }, /* R3642 (0xe3a) - EQ2 21 */
{ 0x00000e3c, 0x6318 }, /* R3644 (0xe3c) - EQ3 1 */
{ 0x00000e3d, 0x6300 }, /* R3645 (0xe3d) - EQ3 2 */
{ 0x00000e3e, 0x0fc8 }, /* R3646 (0xe3e) - EQ3 3 */
{ 0x00000e3f, 0x03fe }, /* R3647 (0xe3f) - EQ3 4 */
{ 0x00000e40, 0x00e0 }, /* R3648 (0xe40) - EQ3 5 */
{ 0x00000e41, 0x1ec4 }, /* R3649 (0xe41) - EQ3 6 */
{ 0x00000e42, 0xf136 }, /* R3650 (0xe42) - EQ3 7 */
{ 0x00000e43, 0x0409 }, /* R3651 (0xe43) - EQ3 8 */
{ 0x00000e44, 0x04cc }, /* R3652 (0xe44) - EQ3 9 */
{ 0x00000e45, 0x1c9b }, /* R3653 (0xe45) - EQ3 10 */
{ 0x00000e46, 0xf337 }, /* R3654 (0xe46) - EQ3 11 */
{ 0x00000e47, 0x040b }, /* R3655 (0xe47) - EQ3 12 */
{ 0x00000e48, 0x0cbb }, /* R3656 (0xe48) - EQ3 13 */
{ 0x00000e49, 0x16f8 }, /* R3657 (0xe49) - EQ3 14 */
{ 0x00000e4a, 0xf7d9 }, /* R3658 (0xe4a) - EQ3 15 */
{ 0x00000e4b, 0x040a }, /* R3659 (0xe4b) - EQ3 16 */
{ 0x00000e4c, 0x1f14 }, /* R3660 (0xe4c) - EQ3 17 */
{ 0x00000e4d, 0x058c }, /* R3661 (0xe4d) - EQ3 18 */
{ 0x00000e4e, 0x0563 }, /* R3662 (0xe4e) - EQ3 19 */
{ 0x00000e4f, 0x4000 }, /* R3663 (0xe4f) - EQ3 20 */
{ 0x00000e50, 0x0b75 }, /* R3664 (0xe50) - EQ3 21 */
{ 0x00000e52, 0x6318 }, /* R3666 (0xe52) - EQ4 1 */
{ 0x00000e53, 0x6300 }, /* R3667 (0xe53) - EQ4 2 */
{ 0x00000e54, 0x0fc8 }, /* R3668 (0xe54) - EQ4 3 */
{ 0x00000e55, 0x03fe }, /* R3669 (0xe55) - EQ4 4 */
{ 0x00000e56, 0x00e0 }, /* R3670 (0xe56) - EQ4 5 */
{ 0x00000e57, 0x1ec4 }, /* R3671 (0xe57) - EQ4 6 */
{ 0x00000e58, 0xf136 }, /* R3672 (0xe58) - EQ4 7 */
{ 0x00000e59, 0x0409 }, /* R3673 (0xe59) - EQ4 8 */
{ 0x00000e5a, 0x04cc }, /* R3674 (0xe5a) - EQ4 9 */
{ 0x00000e5b, 0x1c9b }, /* R3675 (0xe5b) - EQ4 10 */
{ 0x00000e5c, 0xf337 }, /* R3676 (0xe5c) - EQ4 11 */
{ 0x00000e5d, 0x040b }, /* R3677 (0xe5d) - EQ4 12 */
{ 0x00000e5e, 0x0cbb }, /* R3678 (0xe5e) - EQ4 13 */
{ 0x00000e5f, 0x16f8 }, /* R3679 (0xe5f) - EQ4 14 */
{ 0x00000e60, 0xf7d9 }, /* R3680 (0xe60) - EQ4 15 */
{ 0x00000e61, 0x040a }, /* R3681 (0xe61) - EQ4 16 */
{ 0x00000e62, 0x1f14 }, /* R3682 (0xe62) - EQ4 17 */
{ 0x00000e63, 0x058c }, /* R3683 (0xe63) - EQ4 18 */
{ 0x00000e64, 0x0563 }, /* R3684 (0xe64) - EQ4 19 */
{ 0x00000e65, 0x4000 }, /* R3685 (0xe65) - EQ4 20 */
{ 0x00000e66, 0x0b75 }, /* R3686 (0xe66) - EQ4 21 */
{ 0x00000e80, 0x0018 }, /* R3712 (0xe80) - DRC1 Ctrl 1 */
{ 0x00000e81, 0x0933 }, /* R3713 (0xe81) - DRC1 Ctrl 2 */
{ 0x00000e82, 0x0018 }, /* R3714 (0xe82) - DRC1 Ctrl 3 */
{ 0x00000e83, 0x0000 }, /* R3715 (0xe83) - DRC1 Ctrl 4 */
{ 0x00000e84, 0x0000 }, /* R3716 (0xe84) - DRC1 Ctrl 5 */
{ 0x00000e88, 0x0018 }, /* R3720 (0xe88) - DRC2 Ctrl 1 */
{ 0x00000e89, 0x0933 }, /* R3721 (0xe89) - DRC2 Ctrl 2 */
{ 0x00000e8a, 0x0018 }, /* R3722 (0xe8a) - DRC2 Ctrl 3 */
{ 0x00000e8b, 0x0000 }, /* R3723 (0xe8b) - DRC2 Ctrl 4 */
{ 0x00000e8c, 0x0000 }, /* R3724 (0xe8c) - DRC2 Ctrl 5 */
{ 0x00000ec0, 0x0000 }, /* R3776 (0xec0) - HPLPF1 1 */
{ 0x00000ec1, 0x0000 }, /* R3777 (0xec1) - HPLPF1 2 */
{ 0x00000ec4, 0x0000 }, /* R3780 (0xec4) - HPLPF2 1 */
{ 0x00000ec5, 0x0000 }, /* R3781 (0xec5) - HPLPF2 2 */
{ 0x00000ec8, 0x0000 }, /* R3784 (0xec8) - HPLPF3 1 */
{ 0x00000ec9, 0x0000 }, /* R3785 (0xec9) - HPLPF3 2 */
{ 0x00000ecc, 0x0000 }, /* R3788 (0xecc) - HPLPF4 1 */
{ 0x00000ecd, 0x0000 }, /* R3789 (0xecd) - HPLPF4 2 */
{ 0x00000ee0, 0x0000 }, /* R3808 (0xee0) - ASRC1 Enable */
{ 0x00000ee2, 0x0000 }, /* R3810 (0xee2) - ASRC1 Rate 1 */
{ 0x00000ee3, 0x4000 }, /* R3811 (0xee3) - ASRC1 Rate 2 */
{ 0x00000ef0, 0x0000 }, /* R3824 (0xef0) - ISRC1 Ctrl 1 */
{ 0x00000ef1, 0x0001 }, /* R3825 (0xef1) - ISRC1 Ctrl 2 */
{ 0x00000ef2, 0x0000 }, /* R3826 (0xef2) - ISRC1 Ctrl 3 */
{ 0x00000ef3, 0x0000 }, /* R3827 (0xef3) - ISRC2 Ctrl 1 */
{ 0x00000ef4, 0x0001 }, /* R3828 (0xef4) - ISRC2 Ctrl 2 */
{ 0x00000ef5, 0x0000 }, /* R3829 (0xef5) - ISRC2 Ctrl 3 */
{ 0x000010c0, 0x0008 }, /* R4288 (0x10c0) - AUXPDM1 Ctrl 0 */
{ 0x000010c1, 0x4000 }, /* R4289 (0x10c1) - AUXPDM1 Ctrl 1 */
{ 0x00001480, 0x0000 }, /* R5248 (0x1480) - DFC1 Ctrl W0 */
{ 0x00001482, 0x1f00 }, /* R5250 (0x1482) - DFC1 Rx W0 */
{ 0x00001484, 0x1f00 }, /* R5252 (0x1484) - DFC1 Tx W0 */
{ 0x00001486, 0x0000 }, /* R5254 (0x1486) - DFC2 Ctrl W0 */
{ 0x00001488, 0x1f00 }, /* R5256 (0x1488) - DFC2 Rx W0 */
{ 0x0000148a, 0x1f00 }, /* R5258 (0x148a) - DFC2 Tx W0 */
{ 0x0000148c, 0x0000 }, /* R5260 (0x148c) - DFC3 Ctrl W0 */
{ 0x0000148e, 0x1f00 }, /* R5262 (0x148e) - DFC3 Rx W0 */
{ 0x00001490, 0x1f00 }, /* R5264 (0x1490) - DFC3 Tx W0 */
{ 0x00001492, 0x0000 }, /* R5266 (0x1492) - DFC4 Ctrl W0 */
{ 0x00001494, 0x1f00 }, /* R5268 (0x1494) - DFC4 Rx W0 */
{ 0x00001496, 0x1f00 }, /* R5270 (0x1496) - DFC4 Tx W0 */
{ 0x00001498, 0x0000 }, /* R5272 (0x1498) - DFC5 Ctrl W0 */
{ 0x0000149a, 0x1f00 }, /* R5274 (0x149a) - DFC5 Rx W0 */
{ 0x0000149c, 0x1f00 }, /* R5276 (0x149c) - DFC5 Tx W0 */
{ 0x0000149e, 0x0000 }, /* R5278 (0x149e) - DFC6 Ctrl W0 */
{ 0x000014a0, 0x1f00 }, /* R5280 (0x14a0) - DFC6 Rx W0 */
{ 0x000014a2, 0x1f00 }, /* R5282 (0x14a2) - DFC6 Tx W0 */
{ 0x000014a4, 0x0000 }, /* R5284 (0x14a4) - DFC7 Ctrl W0 */
{ 0x000014a6, 0x1f00 }, /* R5286 (0x14a6) - DFC7 Rx W0 */
{ 0x000014a8, 0x1f00 }, /* R5288 (0x14a8) - DFC7 Tx W0 */
{ 0x000014aa, 0x0000 }, /* R5290 (0x14aa) - DFC8 Ctrl W0 */
{ 0x000014ac, 0x1f00 }, /* R5292 (0x14ac) - DFC8 Rx W0 */
{ 0x000014ae, 0x1f00 }, /* R5294 (0x14ae) - DFC8 Tx W0 */
{ 0x00001700, 0x2001 }, /* R5888 (0x1700) - GPIO1 Ctrl 1 */
{ 0x00001701, 0xf000 }, /* R5889 (0x1701) - GPIO1 Ctrl 2 */
{ 0x00001702, 0x2001 }, /* R5890 (0x1702) - GPIO2 Ctrl 1 */
{ 0x00001703, 0xf000 }, /* R5891 (0x1703) - GPIO2 Ctrl 2 */
{ 0x00001704, 0x2001 }, /* R5892 (0x1704) - GPIO3 Ctrl 1 */
{ 0x00001705, 0xf000 }, /* R5893 (0x1705) - GPIO3 Ctrl 2 */
{ 0x00001706, 0x2001 }, /* R5894 (0x1706) - GPIO4 Ctrl 1 */
{ 0x00001707, 0xf000 }, /* R5895 (0x1707) - GPIO4 Ctrl 2 */
{ 0x00001708, 0x2001 }, /* R5896 (0x1708) - GPIO5 Ctrl 1 */
{ 0x00001709, 0xf000 }, /* R5897 (0x1709) - GPIO5 Ctrl 2 */
{ 0x0000170a, 0x2001 }, /* R5898 (0x170a) - GPIO6 Ctrl 1 */
{ 0x0000170b, 0xf000 }, /* R5899 (0x170b) - GPIO6 Ctrl 2 */
{ 0x0000170c, 0x2001 }, /* R5900 (0x170c) - GPIO7 Ctrl 1 */
{ 0x0000170d, 0xf000 }, /* R5901 (0x170d) - GPIO7 Ctrl 2 */
{ 0x0000170e, 0x2001 }, /* R5902 (0x170e) - GPIO8 Ctrl 1 */
{ 0x0000170f, 0xf000 }, /* R5903 (0x170f) - GPIO8 Ctrl 2 */
{ 0x00001710, 0x2001 }, /* R5904 (0x1710) - GPIO9 Ctrl 1 */
{ 0x00001711, 0xf000 }, /* R5905 (0x1711) - GPIO9 Ctrl 2 */
{ 0x00001712, 0x2001 }, /* R5906 (0x1712) - GPIO10 Ctrl 1 */
{ 0x00001713, 0xf000 }, /* R5907 (0x1713) - GPIO10 Ctrl 2 */
{ 0x00001714, 0x2001 }, /* R5908 (0x1714) - GPIO11 Ctrl 1 */
{ 0x00001715, 0xf000 }, /* R5909 (0x1715) - GPIO11 Ctrl 2 */
{ 0x00001716, 0x2001 }, /* R5910 (0x1716) - GPIO12 Ctrl 1 */
{ 0x00001717, 0xf000 }, /* R5911 (0x1717) - GPIO12 Ctrl 2 */
{ 0x00001718, 0x2001 }, /* R5912 (0x1718) - GPIO13 Ctrl 1 */
{ 0x00001719, 0xf000 }, /* R5913 (0x1719) - GPIO13 Ctrl 2 */
{ 0x0000171a, 0x2001 }, /* R5914 (0x171a) - GPIO14 Ctrl 1 */
{ 0x0000171b, 0xf000 }, /* R5915 (0x171b) - GPIO14 Ctrl 2 */
{ 0x0000171c, 0x2001 }, /* R5916 (0x171c) - GPIO15 Ctrl 1 */
{ 0x0000171d, 0xf000 }, /* R5917 (0x171d) - GPIO15 Ctrl 2 */
{ 0x0000171e, 0x2001 }, /* R5918 (0x171e) - GPIO16 Ctrl 1 */
{ 0x0000171f, 0xf000 }, /* R5919 (0x171f) - GPIO16 Ctrl 2 */
{ 0x00001840, 0x1200 }, /* R6208 (0x1840) - IRQ1 Mask 1 */
{ 0x00001841, 0x77e0 }, /* R6209 (0x1841) - IRQ1 Mask 2 */
{ 0x00001842, 0xffff }, /* R6210 (0x1842) - IRQ1 Mask 3 */
{ 0x00001843, 0xffff }, /* R6211 (0x1843) - IRQ1 Mask 4 */
{ 0x00001844, 0xffff }, /* R6212 (0x1844) - IRQ1 Mask 5 */
{ 0x00001845, 0x0301 }, /* R6213 (0x1845) - IRQ1 Mask 6 */
{ 0x00001846, 0x0f3f }, /* R6214 (0x1846) - IRQ1 Mask 7 */
{ 0x00001847, 0xffff }, /* R6215 (0x1847) - IRQ1 Mask 8 */
{ 0x00001848, 0x031f }, /* R6216 (0x1848) - IRQ1 Mask 9 */
{ 0x00001849, 0x031f }, /* R6217 (0x1849) - IRQ1 Mask 10 */
{ 0x0000184a, 0xffff }, /* R6218 (0x184a) - IRQ1 Mask 11 */
{ 0x0000184b, 0x033f }, /* R6219 (0x184b) - IRQ1 Mask 12 */
{ 0x0000184c, 0x003f }, /* R6220 (0x184c) - IRQ1 Mask 13 */
{ 0x0000184d, 0x003f }, /* R6221 (0x184d) - IRQ1 Mask 14 */
{ 0x0000184e, 0x1000 }, /* R6222 (0x184e) - IRQ1 Mask 15 */
{ 0x0000184f, 0xffff }, /* R6223 (0x184f) - IRQ1 Mask 16 */
{ 0x00001850, 0xffff }, /* R6224 (0x1850) - IRQ1 Mask 17 */
{ 0x00001851, 0xffff }, /* R6225 (0x1851) - IRQ1 Mask 18 */
{ 0x00001852, 0xffff }, /* R6226 (0x1852) - IRQ1 Mask 19 */
{ 0x00001853, 0xffff }, /* R6227 (0x1853) - IRQ1 Mask 20 */
{ 0x00001854, 0x0001 }, /* R6228 (0x1854) - IRQ1 Mask 21 */
{ 0x00001855, 0x0001 }, /* R6229 (0x1855) - IRQ1 Mask 22 */
{ 0x00001856, 0x0001 }, /* R6230 (0x1856) - IRQ1 Mask 23 */
{ 0x00001857, 0x0001 }, /* R6231 (0x1857) - IRQ1 Mask 24 */
{ 0x00001858, 0x0001 }, /* R6232 (0x1858) - IRQ1 Mask 25 */
{ 0x00001859, 0xffff }, /* R6233 (0x1859) - IRQ1 Mask 26 */
{ 0x0000185a, 0x0001 }, /* R6234 (0x185a) - IRQ1 Mask 27 */
{ 0x0000185b, 0x0001 }, /* R6235 (0x185b) - IRQ1 Mask 28 */
{ 0x0000185c, 0xffff }, /* R6236 (0x185c) - IRQ1 Mask 29 */
{ 0x0000185d, 0x0001 }, /* R6237 (0x185d) - IRQ1 Mask 30 */
{ 0x0000185e, 0xffff }, /* R6238 (0x185e) - IRQ1 Mask 31 */
{ 0x0000185f, 0xffff }, /* R6239 (0x185f) - IRQ1 Mask 32 */
{ 0x00001860, 0x0001 }, /* R6240 (0x1860) - IRQ1 Mask 33 */
{ 0x00001a06, 0x0000 }, /* R6662 (0x1a06) - Interrupt Debounce 7 */
{ 0x00001a80, 0x4400 }, /* R6784 (0x1a80) - IRQ1 Ctrl */
};
static bool cs47l92_is_adsp_memory(unsigned int reg)
{
switch (reg) {
case 0x080000 ... 0x082ffe:
case 0x0a0000 ... 0x0a1ffe:
case 0x0c0000 ... 0x0c1ffe:
case 0x0e0000 ... 0x0e1ffe:
return true;
default:
return false;
}
}
static bool cs47l92_16bit_readable_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_SOFTWARE_RESET:
case MADERA_HARDWARE_REVISION:
case MADERA_WRITE_SEQUENCER_CTRL_0 ... MADERA_WRITE_SEQUENCER_CTRL_2:
case MADERA_TONE_GENERATOR_1 ... MADERA_TONE_GENERATOR_5:
case MADERA_PWM_DRIVE_1 ... MADERA_PWM_DRIVE_3:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_1:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_2:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_3:
case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_4:
case MADERA_HAPTICS_CONTROL_1 ... MADERA_HAPTICS_CONTROL_2:
case MADERA_HAPTICS_PHASE_1_INTENSITY:
case MADERA_HAPTICS_PHASE_1_DURATION:
case MADERA_HAPTICS_PHASE_2_INTENSITY:
case MADERA_HAPTICS_PHASE_2_DURATION:
case MADERA_HAPTICS_PHASE_3_INTENSITY:
case MADERA_HAPTICS_PHASE_3_DURATION:
case MADERA_HAPTICS_STATUS:
case MADERA_COMFORT_NOISE_GENERATOR:
case MADERA_CLOCK_32K_1:
case MADERA_SYSTEM_CLOCK_1:
case MADERA_SAMPLE_RATE_1 ... MADERA_SAMPLE_RATE_3:
case MADERA_SAMPLE_RATE_1_STATUS:
case MADERA_SAMPLE_RATE_2_STATUS:
case MADERA_SAMPLE_RATE_3_STATUS:
case MADERA_ASYNC_CLOCK_1:
case MADERA_ASYNC_SAMPLE_RATE_1:
case MADERA_ASYNC_SAMPLE_RATE_1_STATUS:
case MADERA_ASYNC_SAMPLE_RATE_2:
case MADERA_ASYNC_SAMPLE_RATE_2_STATUS:
case MADERA_DSP_CLOCK_1:
case MADERA_DSP_CLOCK_2:
case MADERA_OUTPUT_SYSTEM_CLOCK:
case MADERA_OUTPUT_ASYNC_CLOCK:
case MADERA_RATE_ESTIMATOR_1 ... MADERA_RATE_ESTIMATOR_5:
case MADERA_FLL1_CONTROL_1 ... MADERA_FLL1_CONTROL_6:
case CS47L92_FLL1_CONTROL_7 ... CS47L92_FLL1_CONTROL_10:
case MADERA_FLL1_CONTROL_11:
case MADERA_FLL1_DIGITAL_TEST_1:
case MADERA_FLL1_SYNCHRONISER_1 ... MADERA_FLL1_SYNCHRONISER_6:
case CS47L92_FLL1_GPIO_CLOCK:
case MADERA_FLL2_CONTROL_1 ... MADERA_FLL2_CONTROL_6:
case CS47L92_FLL2_CONTROL_7 ... CS47L92_FLL2_CONTROL_10:
case MADERA_FLL2_CONTROL_11:
case MADERA_FLL2_DIGITAL_TEST_1:
case MADERA_FLL2_SYNCHRONISER_1 ... MADERA_FLL2_SYNCHRONISER_6:
case CS47L92_FLL2_GPIO_CLOCK:
case MADERA_MIC_CHARGE_PUMP_1:
case MADERA_LDO2_CONTROL_1:
case MADERA_MIC_BIAS_CTRL_1:
case MADERA_MIC_BIAS_CTRL_2:
case MADERA_MIC_BIAS_CTRL_5:
case MADERA_MIC_BIAS_CTRL_6:
case MADERA_HP_CTRL_1L:
case MADERA_HP_CTRL_1R:
case MADERA_HP_CTRL_2L:
case MADERA_HP_CTRL_2R:
case MADERA_HP_CTRL_3L:
case MADERA_HP_CTRL_3R:
case MADERA_ACCESSORY_DETECT_MODE_1:
case MADERA_HEADPHONE_DETECT_0:
case MADERA_HEADPHONE_DETECT_1:
case MADERA_HEADPHONE_DETECT_2:
case MADERA_HEADPHONE_DETECT_3:
case MADERA_HEADPHONE_DETECT_5:
case MADERA_MICD_CLAMP_CONTROL:
case MADERA_MIC_DETECT_1_CONTROL_0:
case MADERA_MIC_DETECT_1_CONTROL_1:
case MADERA_MIC_DETECT_1_CONTROL_2:
case MADERA_MIC_DETECT_1_CONTROL_3:
case MADERA_MIC_DETECT_1_CONTROL_4:
case MADERA_MIC_DETECT_1_LEVEL_1 ... MADERA_MIC_DETECT_1_LEVEL_4:
case MADERA_MIC_DETECT_2_CONTROL_0:
case MADERA_MIC_DETECT_2_CONTROL_1:
case MADERA_MIC_DETECT_2_CONTROL_2:
case MADERA_MIC_DETECT_2_CONTROL_3:
case MADERA_MIC_DETECT_2_CONTROL_4:
case MADERA_MIC_DETECT_2_LEVEL_1 ... MADERA_MIC_DETECT_2_LEVEL_4:
case MADERA_GP_SWITCH_1:
case MADERA_JACK_DETECT_ANALOGUE:
case MADERA_INPUT_ENABLES:
case MADERA_INPUT_ENABLES_STATUS:
case MADERA_INPUT_RATE:
case MADERA_INPUT_VOLUME_RAMP:
case MADERA_HPF_CONTROL:
case MADERA_IN1L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_1L:
case MADERA_DMIC1L_CONTROL:
case MADERA_IN1L_RATE_CONTROL:
case MADERA_IN1R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_1R:
case MADERA_DMIC1R_CONTROL:
case MADERA_IN1R_RATE_CONTROL:
case MADERA_IN2L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_2L:
case MADERA_DMIC2L_CONTROL:
case MADERA_IN2L_RATE_CONTROL:
case MADERA_IN2R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_2R:
case MADERA_DMIC2R_CONTROL:
case MADERA_IN2R_RATE_CONTROL:
case MADERA_IN3L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_3L:
case MADERA_DMIC3L_CONTROL:
case MADERA_IN3L_RATE_CONTROL:
case MADERA_IN3R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_3R:
case MADERA_DMIC3R_CONTROL:
case MADERA_IN3R_RATE_CONTROL:
case MADERA_IN4L_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_4L:
case MADERA_DMIC4L_CONTROL:
case MADERA_IN4L_RATE_CONTROL:
case MADERA_IN4R_CONTROL:
case MADERA_ADC_DIGITAL_VOLUME_4R:
case MADERA_DMIC4R_CONTROL:
case MADERA_IN4R_RATE_CONTROL:
case MADERA_OUTPUT_ENABLES_1:
case MADERA_OUTPUT_STATUS_1:
case MADERA_RAW_OUTPUT_STATUS_1:
case MADERA_OUTPUT_RATE_1:
case MADERA_OUTPUT_VOLUME_RAMP:
case MADERA_OUTPUT_PATH_CONFIG_1L:
case MADERA_DAC_DIGITAL_VOLUME_1L:
case MADERA_OUTPUT_PATH_CONFIG_1:
case MADERA_NOISE_GATE_SELECT_1L:
case MADERA_OUTPUT_PATH_CONFIG_1R:
case MADERA_DAC_DIGITAL_VOLUME_1R:
case MADERA_NOISE_GATE_SELECT_1R:
case MADERA_OUTPUT_PATH_CONFIG_2L:
case MADERA_DAC_DIGITAL_VOLUME_2L:
case MADERA_OUTPUT_PATH_CONFIG_2:
case MADERA_NOISE_GATE_SELECT_2L:
case MADERA_OUTPUT_PATH_CONFIG_2R:
case MADERA_DAC_DIGITAL_VOLUME_2R:
case MADERA_NOISE_GATE_SELECT_2R:
case MADERA_OUTPUT_PATH_CONFIG_3L:
case MADERA_DAC_DIGITAL_VOLUME_3L:
case MADERA_OUTPUT_PATH_CONFIG_3:
case MADERA_NOISE_GATE_SELECT_3L:
case MADERA_OUTPUT_PATH_CONFIG_3R:
case MADERA_DAC_DIGITAL_VOLUME_3R:
case MADERA_NOISE_GATE_SELECT_3R:
case MADERA_OUTPUT_PATH_CONFIG_5L:
case MADERA_DAC_DIGITAL_VOLUME_5L:
case MADERA_NOISE_GATE_SELECT_5L:
case MADERA_OUTPUT_PATH_CONFIG_5R:
case MADERA_DAC_DIGITAL_VOLUME_5R:
case MADERA_NOISE_GATE_SELECT_5R:
case MADERA_DAC_AEC_CONTROL_1 ... MADERA_DAC_AEC_CONTROL_2:
case MADERA_NOISE_GATE_CONTROL:
case MADERA_PDM_SPK1_CTRL_1 ... MADERA_PDM_SPK1_CTRL_2:
case MADERA_HP1_SHORT_CIRCUIT_CTRL:
case MADERA_HP2_SHORT_CIRCUIT_CTRL:
case MADERA_HP3_SHORT_CIRCUIT_CTRL:
case MADERA_AIF1_BCLK_CTRL:
case MADERA_AIF1_TX_PIN_CTRL:
case MADERA_AIF1_RX_PIN_CTRL:
case MADERA_AIF1_RATE_CTRL:
case MADERA_AIF1_FORMAT:
case MADERA_AIF1_RX_BCLK_RATE:
case MADERA_AIF1_FRAME_CTRL_1 ... MADERA_AIF1_FRAME_CTRL_18:
case MADERA_AIF1_TX_ENABLES:
case MADERA_AIF1_RX_ENABLES:
case MADERA_AIF2_BCLK_CTRL:
case MADERA_AIF2_TX_PIN_CTRL:
case MADERA_AIF2_RX_PIN_CTRL:
case MADERA_AIF2_RATE_CTRL:
case MADERA_AIF2_FORMAT:
case MADERA_AIF2_RX_BCLK_RATE:
case MADERA_AIF2_FRAME_CTRL_1 ... MADERA_AIF2_FRAME_CTRL_18:
case MADERA_AIF2_TX_ENABLES:
case MADERA_AIF2_RX_ENABLES:
case MADERA_AIF3_BCLK_CTRL:
case MADERA_AIF3_TX_PIN_CTRL:
case MADERA_AIF3_RX_PIN_CTRL:
case MADERA_AIF3_RATE_CTRL:
case MADERA_AIF3_FORMAT:
case MADERA_AIF3_RX_BCLK_RATE:
case MADERA_AIF3_FRAME_CTRL_1 ... MADERA_AIF3_FRAME_CTRL_18:
case MADERA_AIF3_TX_ENABLES:
case MADERA_AIF3_RX_ENABLES:
case MADERA_SPD1_TX_CONTROL:
case MADERA_SPD1_TX_CHANNEL_STATUS_1:
case MADERA_SPD1_TX_CHANNEL_STATUS_2:
case MADERA_SPD1_TX_CHANNEL_STATUS_3:
case MADERA_SLIMBUS_FRAMER_REF_GEAR:
case MADERA_SLIMBUS_RATES_1 ... MADERA_SLIMBUS_RATES_8:
case MADERA_SLIMBUS_RX_CHANNEL_ENABLE:
case MADERA_SLIMBUS_TX_CHANNEL_ENABLE:
case MADERA_SLIMBUS_RX_PORT_STATUS:
case MADERA_SLIMBUS_TX_PORT_STATUS:
case MADERA_PWM1MIX_INPUT_1_SOURCE:
case MADERA_PWM1MIX_INPUT_1_VOLUME:
case MADERA_PWM1MIX_INPUT_2_SOURCE:
case MADERA_PWM1MIX_INPUT_2_VOLUME:
case MADERA_PWM1MIX_INPUT_3_SOURCE:
case MADERA_PWM1MIX_INPUT_3_VOLUME:
case MADERA_PWM1MIX_INPUT_4_SOURCE:
case MADERA_PWM1MIX_INPUT_4_VOLUME:
case MADERA_PWM2MIX_INPUT_1_SOURCE:
case MADERA_PWM2MIX_INPUT_1_VOLUME:
case MADERA_PWM2MIX_INPUT_2_SOURCE:
case MADERA_PWM2MIX_INPUT_2_VOLUME:
case MADERA_PWM2MIX_INPUT_3_SOURCE:
case MADERA_PWM2MIX_INPUT_3_VOLUME:
case MADERA_PWM2MIX_INPUT_4_SOURCE:
case MADERA_PWM2MIX_INPUT_4_VOLUME:
case MADERA_OUT1LMIX_INPUT_1_SOURCE:
case MADERA_OUT1LMIX_INPUT_1_VOLUME:
case MADERA_OUT1LMIX_INPUT_2_SOURCE:
case MADERA_OUT1LMIX_INPUT_2_VOLUME:
case MADERA_OUT1LMIX_INPUT_3_SOURCE:
case MADERA_OUT1LMIX_INPUT_3_VOLUME:
case MADERA_OUT1LMIX_INPUT_4_SOURCE:
case MADERA_OUT1LMIX_INPUT_4_VOLUME:
case MADERA_OUT1RMIX_INPUT_1_SOURCE:
case MADERA_OUT1RMIX_INPUT_1_VOLUME:
case MADERA_OUT1RMIX_INPUT_2_SOURCE:
case MADERA_OUT1RMIX_INPUT_2_VOLUME:
case MADERA_OUT1RMIX_INPUT_3_SOURCE:
case MADERA_OUT1RMIX_INPUT_3_VOLUME:
case MADERA_OUT1RMIX_INPUT_4_SOURCE:
case MADERA_OUT1RMIX_INPUT_4_VOLUME:
case MADERA_OUT2LMIX_INPUT_1_SOURCE:
case MADERA_OUT2LMIX_INPUT_1_VOLUME:
case MADERA_OUT2LMIX_INPUT_2_SOURCE:
case MADERA_OUT2LMIX_INPUT_2_VOLUME:
case MADERA_OUT2LMIX_INPUT_3_SOURCE:
case MADERA_OUT2LMIX_INPUT_3_VOLUME:
case MADERA_OUT2LMIX_INPUT_4_SOURCE:
case MADERA_OUT2LMIX_INPUT_4_VOLUME:
case MADERA_OUT2RMIX_INPUT_1_SOURCE:
case MADERA_OUT2RMIX_INPUT_1_VOLUME:
case MADERA_OUT2RMIX_INPUT_2_SOURCE:
case MADERA_OUT2RMIX_INPUT_2_VOLUME:
case MADERA_OUT2RMIX_INPUT_3_SOURCE:
case MADERA_OUT2RMIX_INPUT_3_VOLUME:
case MADERA_OUT2RMIX_INPUT_4_SOURCE:
case MADERA_OUT2RMIX_INPUT_4_VOLUME:
case MADERA_OUT3LMIX_INPUT_1_SOURCE:
case MADERA_OUT3LMIX_INPUT_1_VOLUME:
case MADERA_OUT3LMIX_INPUT_2_SOURCE:
case MADERA_OUT3LMIX_INPUT_2_VOLUME:
case MADERA_OUT3LMIX_INPUT_3_SOURCE:
case MADERA_OUT3LMIX_INPUT_3_VOLUME:
case MADERA_OUT3LMIX_INPUT_4_SOURCE:
case MADERA_OUT3LMIX_INPUT_4_VOLUME:
case MADERA_OUT3RMIX_INPUT_1_SOURCE:
case MADERA_OUT3RMIX_INPUT_1_VOLUME:
case MADERA_OUT3RMIX_INPUT_2_SOURCE:
case MADERA_OUT3RMIX_INPUT_2_VOLUME:
case MADERA_OUT3RMIX_INPUT_3_SOURCE:
case MADERA_OUT3RMIX_INPUT_3_VOLUME:
case MADERA_OUT3RMIX_INPUT_4_SOURCE:
case MADERA_OUT3RMIX_INPUT_4_VOLUME:
case MADERA_OUT5LMIX_INPUT_1_SOURCE:
case MADERA_OUT5LMIX_INPUT_1_VOLUME:
case MADERA_OUT5LMIX_INPUT_2_SOURCE:
case MADERA_OUT5LMIX_INPUT_2_VOLUME:
case MADERA_OUT5LMIX_INPUT_3_SOURCE:
case MADERA_OUT5LMIX_INPUT_3_VOLUME:
case MADERA_OUT5LMIX_INPUT_4_SOURCE:
case MADERA_OUT5LMIX_INPUT_4_VOLUME:
case MADERA_OUT5RMIX_INPUT_1_SOURCE:
case MADERA_OUT5RMIX_INPUT_1_VOLUME:
case MADERA_OUT5RMIX_INPUT_2_SOURCE:
case MADERA_OUT5RMIX_INPUT_2_VOLUME:
case MADERA_OUT5RMIX_INPUT_3_SOURCE:
case MADERA_OUT5RMIX_INPUT_3_VOLUME:
case MADERA_OUT5RMIX_INPUT_4_SOURCE:
case MADERA_OUT5RMIX_INPUT_4_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX2MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX3MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX3MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX4MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX4MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX5MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX5MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX6MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX6MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX7MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX7MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX7MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX7MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX7MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX7MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX7MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX7MIX_INPUT_4_VOLUME:
case MADERA_AIF1TX8MIX_INPUT_1_SOURCE:
case MADERA_AIF1TX8MIX_INPUT_1_VOLUME:
case MADERA_AIF1TX8MIX_INPUT_2_SOURCE:
case MADERA_AIF1TX8MIX_INPUT_2_VOLUME:
case MADERA_AIF1TX8MIX_INPUT_3_SOURCE:
case MADERA_AIF1TX8MIX_INPUT_3_VOLUME:
case MADERA_AIF1TX8MIX_INPUT_4_SOURCE:
case MADERA_AIF1TX8MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX2MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX3MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX3MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX4MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX4MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX5MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX5MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX5MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX5MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX5MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX5MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX5MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX5MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX6MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX6MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX6MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX6MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX6MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX6MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX6MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX6MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX7MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX7MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX7MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX7MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX7MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX7MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX7MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX7MIX_INPUT_4_VOLUME:
case MADERA_AIF2TX8MIX_INPUT_1_SOURCE:
case MADERA_AIF2TX8MIX_INPUT_1_VOLUME:
case MADERA_AIF2TX8MIX_INPUT_2_SOURCE:
case MADERA_AIF2TX8MIX_INPUT_2_VOLUME:
case MADERA_AIF2TX8MIX_INPUT_3_SOURCE:
case MADERA_AIF2TX8MIX_INPUT_3_VOLUME:
case MADERA_AIF2TX8MIX_INPUT_4_SOURCE:
case MADERA_AIF2TX8MIX_INPUT_4_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_1_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_1_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_2_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_2_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_3_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_3_VOLUME:
case MADERA_AIF3TX1MIX_INPUT_4_SOURCE:
case MADERA_AIF3TX1MIX_INPUT_4_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_1_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_1_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_2_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_2_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_3_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_3_VOLUME:
case MADERA_AIF3TX2MIX_INPUT_4_SOURCE:
case MADERA_AIF3TX2MIX_INPUT_4_VOLUME:
case MADERA_AIF3TX3MIX_INPUT_1_SOURCE:
case MADERA_AIF3TX3MIX_INPUT_1_VOLUME:
case MADERA_AIF3TX3MIX_INPUT_2_SOURCE:
case MADERA_AIF3TX3MIX_INPUT_2_VOLUME:
case MADERA_AIF3TX3MIX_INPUT_3_SOURCE:
case MADERA_AIF3TX3MIX_INPUT_3_VOLUME:
case MADERA_AIF3TX3MIX_INPUT_4_SOURCE:
case MADERA_AIF3TX3MIX_INPUT_4_VOLUME:
case MADERA_AIF3TX4MIX_INPUT_1_SOURCE:
case MADERA_AIF3TX4MIX_INPUT_1_VOLUME:
case MADERA_AIF3TX4MIX_INPUT_2_SOURCE:
case MADERA_AIF3TX4MIX_INPUT_2_VOLUME:
case MADERA_AIF3TX4MIX_INPUT_3_SOURCE:
case MADERA_AIF3TX4MIX_INPUT_3_VOLUME:
case MADERA_AIF3TX4MIX_INPUT_4_SOURCE:
case MADERA_AIF3TX4MIX_INPUT_4_VOLUME:
case CS47L92_AIF3TX5MIX_INPUT_1_SOURCE:
case CS47L92_AIF3TX5MIX_INPUT_1_VOLUME:
case CS47L92_AIF3TX5MIX_INPUT_2_SOURCE:
case CS47L92_AIF3TX5MIX_INPUT_2_VOLUME:
case CS47L92_AIF3TX5MIX_INPUT_3_SOURCE:
case CS47L92_AIF3TX5MIX_INPUT_3_VOLUME:
case CS47L92_AIF3TX5MIX_INPUT_4_SOURCE:
case CS47L92_AIF3TX5MIX_INPUT_4_VOLUME:
case CS47L92_AIF3TX6MIX_INPUT_1_SOURCE:
case CS47L92_AIF3TX6MIX_INPUT_1_VOLUME:
case CS47L92_AIF3TX6MIX_INPUT_2_SOURCE:
case CS47L92_AIF3TX6MIX_INPUT_2_VOLUME:
case CS47L92_AIF3TX6MIX_INPUT_3_SOURCE:
case CS47L92_AIF3TX6MIX_INPUT_3_VOLUME:
case CS47L92_AIF3TX6MIX_INPUT_4_SOURCE:
case CS47L92_AIF3TX6MIX_INPUT_4_VOLUME:
case CS47L92_AIF3TX7MIX_INPUT_1_SOURCE:
case CS47L92_AIF3TX7MIX_INPUT_1_VOLUME:
case CS47L92_AIF3TX7MIX_INPUT_2_SOURCE:
case CS47L92_AIF3TX7MIX_INPUT_2_VOLUME:
case CS47L92_AIF3TX7MIX_INPUT_3_SOURCE:
case CS47L92_AIF3TX7MIX_INPUT_3_VOLUME:
case CS47L92_AIF3TX7MIX_INPUT_4_SOURCE:
case CS47L92_AIF3TX7MIX_INPUT_4_VOLUME:
case CS47L92_AIF3TX8MIX_INPUT_1_SOURCE:
case CS47L92_AIF3TX8MIX_INPUT_1_VOLUME:
case CS47L92_AIF3TX8MIX_INPUT_2_SOURCE:
case CS47L92_AIF3TX8MIX_INPUT_2_VOLUME:
case CS47L92_AIF3TX8MIX_INPUT_3_SOURCE:
case CS47L92_AIF3TX8MIX_INPUT_3_VOLUME:
case CS47L92_AIF3TX8MIX_INPUT_4_SOURCE:
case CS47L92_AIF3TX8MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX1MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX1MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX2MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX2MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX3MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX3MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX4MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX4MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX5MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX5MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX6MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX6MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX7MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX7MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX7MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX7MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX7MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX7MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX7MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX7MIX_INPUT_4_VOLUME:
case MADERA_SLIMTX8MIX_INPUT_1_SOURCE:
case MADERA_SLIMTX8MIX_INPUT_1_VOLUME:
case MADERA_SLIMTX8MIX_INPUT_2_SOURCE:
case MADERA_SLIMTX8MIX_INPUT_2_VOLUME:
case MADERA_SLIMTX8MIX_INPUT_3_SOURCE:
case MADERA_SLIMTX8MIX_INPUT_3_VOLUME:
case MADERA_SLIMTX8MIX_INPUT_4_SOURCE:
case MADERA_SLIMTX8MIX_INPUT_4_VOLUME:
case MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE:
case MADERA_SPDIF1TX1MIX_INPUT_1_VOLUME:
case MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE:
case MADERA_SPDIF1TX2MIX_INPUT_1_VOLUME:
case MADERA_EQ1MIX_INPUT_1_SOURCE:
case MADERA_EQ1MIX_INPUT_1_VOLUME:
case MADERA_EQ1MIX_INPUT_2_SOURCE:
case MADERA_EQ1MIX_INPUT_2_VOLUME:
case MADERA_EQ1MIX_INPUT_3_SOURCE:
case MADERA_EQ1MIX_INPUT_3_VOLUME:
case MADERA_EQ1MIX_INPUT_4_SOURCE:
case MADERA_EQ1MIX_INPUT_4_VOLUME:
case MADERA_EQ2MIX_INPUT_1_SOURCE:
case MADERA_EQ2MIX_INPUT_1_VOLUME:
case MADERA_EQ2MIX_INPUT_2_SOURCE:
case MADERA_EQ2MIX_INPUT_2_VOLUME:
case MADERA_EQ2MIX_INPUT_3_SOURCE:
case MADERA_EQ2MIX_INPUT_3_VOLUME:
case MADERA_EQ2MIX_INPUT_4_SOURCE:
case MADERA_EQ2MIX_INPUT_4_VOLUME:
case MADERA_EQ3MIX_INPUT_1_SOURCE:
case MADERA_EQ3MIX_INPUT_1_VOLUME:
case MADERA_EQ3MIX_INPUT_2_SOURCE:
case MADERA_EQ3MIX_INPUT_2_VOLUME:
case MADERA_EQ3MIX_INPUT_3_SOURCE:
case MADERA_EQ3MIX_INPUT_3_VOLUME:
case MADERA_EQ3MIX_INPUT_4_SOURCE:
case MADERA_EQ3MIX_INPUT_4_VOLUME:
case MADERA_EQ4MIX_INPUT_1_SOURCE:
case MADERA_EQ4MIX_INPUT_1_VOLUME:
case MADERA_EQ4MIX_INPUT_2_SOURCE:
case MADERA_EQ4MIX_INPUT_2_VOLUME:
case MADERA_EQ4MIX_INPUT_3_SOURCE:
case MADERA_EQ4MIX_INPUT_3_VOLUME:
case MADERA_EQ4MIX_INPUT_4_SOURCE:
case MADERA_EQ4MIX_INPUT_4_VOLUME:
case MADERA_DRC1LMIX_INPUT_1_SOURCE:
case MADERA_DRC1LMIX_INPUT_1_VOLUME:
case MADERA_DRC1LMIX_INPUT_2_SOURCE:
case MADERA_DRC1LMIX_INPUT_2_VOLUME:
case MADERA_DRC1LMIX_INPUT_3_SOURCE:
case MADERA_DRC1LMIX_INPUT_3_VOLUME:
case MADERA_DRC1LMIX_INPUT_4_SOURCE:
case MADERA_DRC1LMIX_INPUT_4_VOLUME:
case MADERA_DRC1RMIX_INPUT_1_SOURCE:
case MADERA_DRC1RMIX_INPUT_1_VOLUME:
case MADERA_DRC1RMIX_INPUT_2_SOURCE:
case MADERA_DRC1RMIX_INPUT_2_VOLUME:
case MADERA_DRC1RMIX_INPUT_3_SOURCE:
case MADERA_DRC1RMIX_INPUT_3_VOLUME:
case MADERA_DRC1RMIX_INPUT_4_SOURCE:
case MADERA_DRC1RMIX_INPUT_4_VOLUME:
case MADERA_DRC2LMIX_INPUT_1_SOURCE:
case MADERA_DRC2LMIX_INPUT_1_VOLUME:
case MADERA_DRC2LMIX_INPUT_2_SOURCE:
case MADERA_DRC2LMIX_INPUT_2_VOLUME:
case MADERA_DRC2LMIX_INPUT_3_SOURCE:
case MADERA_DRC2LMIX_INPUT_3_VOLUME:
case MADERA_DRC2LMIX_INPUT_4_SOURCE:
case MADERA_DRC2LMIX_INPUT_4_VOLUME:
case MADERA_DRC2RMIX_INPUT_1_SOURCE:
case MADERA_DRC2RMIX_INPUT_1_VOLUME:
case MADERA_DRC2RMIX_INPUT_2_SOURCE:
case MADERA_DRC2RMIX_INPUT_2_VOLUME:
case MADERA_DRC2RMIX_INPUT_3_SOURCE:
case MADERA_DRC2RMIX_INPUT_3_VOLUME:
case MADERA_DRC2RMIX_INPUT_4_SOURCE:
case MADERA_DRC2RMIX_INPUT_4_VOLUME:
case MADERA_HPLP1MIX_INPUT_1_SOURCE:
case MADERA_HPLP1MIX_INPUT_1_VOLUME:
case MADERA_HPLP1MIX_INPUT_2_SOURCE:
case MADERA_HPLP1MIX_INPUT_2_VOLUME:
case MADERA_HPLP1MIX_INPUT_3_SOURCE:
case MADERA_HPLP1MIX_INPUT_3_VOLUME:
case MADERA_HPLP1MIX_INPUT_4_SOURCE:
case MADERA_HPLP1MIX_INPUT_4_VOLUME:
case MADERA_HPLP2MIX_INPUT_1_SOURCE:
case MADERA_HPLP2MIX_INPUT_1_VOLUME:
case MADERA_HPLP2MIX_INPUT_2_SOURCE:
case MADERA_HPLP2MIX_INPUT_2_VOLUME:
case MADERA_HPLP2MIX_INPUT_3_SOURCE:
case MADERA_HPLP2MIX_INPUT_3_VOLUME:
case MADERA_HPLP2MIX_INPUT_4_SOURCE:
case MADERA_HPLP2MIX_INPUT_4_VOLUME:
case MADERA_HPLP3MIX_INPUT_1_SOURCE:
case MADERA_HPLP3MIX_INPUT_1_VOLUME:
case MADERA_HPLP3MIX_INPUT_2_SOURCE:
case MADERA_HPLP3MIX_INPUT_2_VOLUME:
case MADERA_HPLP3MIX_INPUT_3_SOURCE:
case MADERA_HPLP3MIX_INPUT_3_VOLUME:
case MADERA_HPLP3MIX_INPUT_4_SOURCE:
case MADERA_HPLP3MIX_INPUT_4_VOLUME:
case MADERA_HPLP4MIX_INPUT_1_SOURCE:
case MADERA_HPLP4MIX_INPUT_1_VOLUME:
case MADERA_HPLP4MIX_INPUT_2_SOURCE:
case MADERA_HPLP4MIX_INPUT_2_VOLUME:
case MADERA_HPLP4MIX_INPUT_3_SOURCE:
case MADERA_HPLP4MIX_INPUT_3_VOLUME:
case MADERA_HPLP4MIX_INPUT_4_SOURCE:
case MADERA_HPLP4MIX_INPUT_4_VOLUME:
case MADERA_DSP1LMIX_INPUT_1_SOURCE:
case MADERA_DSP1LMIX_INPUT_1_VOLUME:
case MADERA_DSP1LMIX_INPUT_2_SOURCE:
case MADERA_DSP1LMIX_INPUT_2_VOLUME:
case MADERA_DSP1LMIX_INPUT_3_SOURCE:
case MADERA_DSP1LMIX_INPUT_3_VOLUME:
case MADERA_DSP1LMIX_INPUT_4_SOURCE:
case MADERA_DSP1LMIX_INPUT_4_VOLUME:
case MADERA_DSP1RMIX_INPUT_1_SOURCE:
case MADERA_DSP1RMIX_INPUT_1_VOLUME:
case MADERA_DSP1RMIX_INPUT_2_SOURCE:
case MADERA_DSP1RMIX_INPUT_2_VOLUME:
case MADERA_DSP1RMIX_INPUT_3_SOURCE:
case MADERA_DSP1RMIX_INPUT_3_VOLUME:
case MADERA_DSP1RMIX_INPUT_4_SOURCE:
case MADERA_DSP1RMIX_INPUT_4_VOLUME:
case MADERA_DSP1AUX1MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX2MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX3MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX4MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX5MIX_INPUT_1_SOURCE:
case MADERA_DSP1AUX6MIX_INPUT_1_SOURCE:
case MADERA_ASRC1_1LMIX_INPUT_1_SOURCE:
case MADERA_ASRC1_1RMIX_INPUT_1_SOURCE:
case MADERA_ASRC1_2LMIX_INPUT_1_SOURCE:
case MADERA_ASRC1_2RMIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE:
case MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT1MIX_INPUT_1_SOURCE:
case MADERA_ISRC1INT2MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE:
case MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT1MIX_INPUT_1_SOURCE:
case MADERA_ISRC2INT2MIX_INPUT_1_SOURCE:
case MADERA_DFC1MIX_INPUT_1_SOURCE:
case MADERA_DFC2MIX_INPUT_1_SOURCE:
case MADERA_DFC3MIX_INPUT_1_SOURCE:
case MADERA_DFC4MIX_INPUT_1_SOURCE:
case MADERA_DFC5MIX_INPUT_1_SOURCE:
case MADERA_DFC6MIX_INPUT_1_SOURCE:
case MADERA_DFC7MIX_INPUT_1_SOURCE:
case MADERA_DFC8MIX_INPUT_1_SOURCE:
case MADERA_FX_CTRL1 ... MADERA_FX_CTRL2:
case MADERA_EQ1_1 ... MADERA_EQ1_21:
case MADERA_EQ2_1 ... MADERA_EQ2_21:
case MADERA_EQ3_1 ... MADERA_EQ3_21:
case MADERA_EQ4_1 ... MADERA_EQ4_21:
case MADERA_DRC1_CTRL1 ... MADERA_DRC1_CTRL5:
case MADERA_DRC2_CTRL1 ... MADERA_DRC2_CTRL5:
case MADERA_HPLPF1_1 ... MADERA_HPLPF1_2:
case MADERA_HPLPF2_1 ... MADERA_HPLPF2_2:
case MADERA_HPLPF3_1 ... MADERA_HPLPF3_2:
case MADERA_HPLPF4_1 ... MADERA_HPLPF4_2:
case MADERA_ASRC1_ENABLE:
case MADERA_ASRC1_STATUS:
case MADERA_ASRC1_RATE1 ... MADERA_ASRC1_RATE2:
case MADERA_ISRC_1_CTRL_1 ... MADERA_ISRC_1_CTRL_3:
case MADERA_ISRC_2_CTRL_1 ... MADERA_ISRC_2_CTRL_3:
case MADERA_AUXPDM1_CTRL_0 ... MADERA_AUXPDM1_CTRL_1:
case MADERA_DFC1_CTRL:
case MADERA_DFC1_RX:
case MADERA_DFC1_TX:
case MADERA_DFC2_CTRL:
case MADERA_DFC2_RX:
case MADERA_DFC2_TX:
case MADERA_DFC3_CTRL:
case MADERA_DFC3_RX:
case MADERA_DFC3_TX:
case MADERA_DFC4_CTRL:
case MADERA_DFC4_RX:
case MADERA_DFC4_TX:
case MADERA_DFC5_CTRL:
case MADERA_DFC5_RX:
case MADERA_DFC5_TX:
case MADERA_DFC6_CTRL:
case MADERA_DFC6_RX:
case MADERA_DFC6_TX:
case MADERA_DFC7_CTRL:
case MADERA_DFC7_RX:
case MADERA_DFC7_TX:
case MADERA_DFC8_CTRL:
case MADERA_DFC8_RX:
case MADERA_DFC8_TX:
case MADERA_DFC_STATUS:
case MADERA_GPIO1_CTRL_1 ... MADERA_GPIO16_CTRL_2:
case MADERA_IRQ1_STATUS_1 ... MADERA_IRQ1_STATUS_33:
case MADERA_IRQ1_MASK_1 ... MADERA_IRQ1_MASK_33:
case MADERA_IRQ1_RAW_STATUS_1 ... MADERA_IRQ1_RAW_STATUS_33:
case MADERA_INTERRUPT_DEBOUNCE_7:
case MADERA_IRQ1_CTRL:
return true;
default:
return false;
}
}
static bool cs47l92_16bit_volatile_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_SOFTWARE_RESET:
case MADERA_HARDWARE_REVISION:
case MADERA_WRITE_SEQUENCER_CTRL_0 ... MADERA_WRITE_SEQUENCER_CTRL_2:
case MADERA_HAPTICS_STATUS:
case MADERA_SAMPLE_RATE_1_STATUS:
case MADERA_SAMPLE_RATE_2_STATUS:
case MADERA_SAMPLE_RATE_3_STATUS:
case MADERA_ASYNC_SAMPLE_RATE_1_STATUS:
case MADERA_ASYNC_SAMPLE_RATE_2_STATUS:
case MADERA_HP_CTRL_1L:
case MADERA_HP_CTRL_1R:
case MADERA_HP_CTRL_2L:
case MADERA_HP_CTRL_2R:
case MADERA_HP_CTRL_3L:
case MADERA_HP_CTRL_3R:
case MADERA_MIC_DETECT_1_CONTROL_3:
case MADERA_MIC_DETECT_1_CONTROL_4:
case MADERA_MIC_DETECT_2_CONTROL_3:
case MADERA_MIC_DETECT_2_CONTROL_4:
case MADERA_HEADPHONE_DETECT_2:
case MADERA_HEADPHONE_DETECT_3:
case MADERA_HEADPHONE_DETECT_5:
case MADERA_INPUT_ENABLES_STATUS:
case MADERA_OUTPUT_STATUS_1:
case MADERA_RAW_OUTPUT_STATUS_1:
case MADERA_SPD1_TX_CHANNEL_STATUS_1:
case MADERA_SPD1_TX_CHANNEL_STATUS_2:
case MADERA_SPD1_TX_CHANNEL_STATUS_3:
case MADERA_SLIMBUS_RX_PORT_STATUS:
case MADERA_SLIMBUS_TX_PORT_STATUS:
case MADERA_FX_CTRL2:
case MADERA_ASRC1_STATUS:
case MADERA_DFC_STATUS:
case MADERA_IRQ1_STATUS_1 ... MADERA_IRQ1_STATUS_33:
case MADERA_IRQ1_RAW_STATUS_1 ... MADERA_IRQ1_RAW_STATUS_33:
return true;
default:
return false;
}
}
static bool cs47l92_32bit_readable_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_WSEQ_SEQUENCE_1 ... MADERA_WSEQ_SEQUENCE_508:
case MADERA_OTP_HPDET_CAL_1 ... MADERA_OTP_HPDET_CAL_2:
case MADERA_DSP1_CONFIG_1 ... MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
return true;
default:
return cs47l92_is_adsp_memory(reg);
}
}
static bool cs47l92_32bit_volatile_register(struct device *dev,
unsigned int reg)
{
switch (reg) {
case MADERA_WSEQ_SEQUENCE_1 ... MADERA_WSEQ_SEQUENCE_508:
case MADERA_OTP_HPDET_CAL_1 ... MADERA_OTP_HPDET_CAL_2:
case MADERA_DSP1_CONFIG_1 ... MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR:
return true;
default:
return cs47l92_is_adsp_memory(reg);
}
}
const struct regmap_config cs47l92_16bit_spi_regmap = {
.name = "cs47l92_16bit",
.reg_bits = 32,
.pad_bits = 16,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = MADERA_INTERRUPT_RAW_STATUS_1,
.readable_reg = &cs47l92_16bit_readable_register,
.volatile_reg = &cs47l92_16bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = cs47l92_reg_default,
.num_reg_defaults = ARRAY_SIZE(cs47l92_reg_default),
};
EXPORT_SYMBOL_GPL(cs47l92_16bit_spi_regmap);
const struct regmap_config cs47l92_16bit_i2c_regmap = {
.name = "cs47l92_16bit",
.reg_bits = 32,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = MADERA_INTERRUPT_RAW_STATUS_1,
.readable_reg = &cs47l92_16bit_readable_register,
.volatile_reg = &cs47l92_16bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = cs47l92_reg_default,
.num_reg_defaults = ARRAY_SIZE(cs47l92_reg_default),
};
EXPORT_SYMBOL_GPL(cs47l92_16bit_i2c_regmap);
const struct regmap_config cs47l92_32bit_spi_regmap = {
.name = "cs47l92_32bit",
.reg_bits = 32,
.reg_stride = 2,
.pad_bits = 16,
.val_bits = 32,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR,
.readable_reg = &cs47l92_32bit_readable_register,
.volatile_reg = &cs47l92_32bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(cs47l92_32bit_spi_regmap);
const struct regmap_config cs47l92_32bit_i2c_regmap = {
.name = "cs47l92_32bit",
.reg_bits = 32,
.reg_stride = 2,
.val_bits = 32,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR,
.readable_reg = &cs47l92_32bit_readable_register,
.volatile_reg = &cs47l92_32bit_volatile_register,
.cache_type = REGCACHE_MAPLE,
};
EXPORT_SYMBOL_GPL(cs47l92_32bit_i2c_regmap);
| linux-master | drivers/mfd/cs47l92-tables.c |
// SPDX-License-Identifier: GPL-2.0+
//
// max77686.c - mfd core driver for the Maxim 77686/802
//
// Copyright (C) 2012 Samsung Electronics
// Chiwoong Byun <[email protected]>
// Jonghwa Lee <[email protected]>
//
//This driver is based on max8997.c
#include <linux/export.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include <linux/module.h>
#include <linux/mfd/core.h>
#include <linux/mfd/max77686.h>
#include <linux/mfd/max77686-private.h>
#include <linux/err.h>
#include <linux/of.h>
static const struct mfd_cell max77686_devs[] = {
{ .name = "max77686-pmic", },
{ .name = "max77686-rtc", },
{ .name = "max77686-clk", },
};
static const struct mfd_cell max77802_devs[] = {
{ .name = "max77802-pmic", },
{ .name = "max77802-clk", },
{ .name = "max77802-rtc", },
};
static bool max77802_pmic_is_accessible_reg(struct device *dev,
unsigned int reg)
{
return reg < MAX77802_REG_PMIC_END;
}
static bool max77802_rtc_is_accessible_reg(struct device *dev,
unsigned int reg)
{
return (reg >= MAX77802_RTC_INT && reg < MAX77802_RTC_END);
}
static bool max77802_is_accessible_reg(struct device *dev, unsigned int reg)
{
return (max77802_pmic_is_accessible_reg(dev, reg) ||
max77802_rtc_is_accessible_reg(dev, reg));
}
static bool max77802_pmic_is_precious_reg(struct device *dev, unsigned int reg)
{
return (reg == MAX77802_REG_INTSRC || reg == MAX77802_REG_INT1 ||
reg == MAX77802_REG_INT2);
}
static bool max77802_rtc_is_precious_reg(struct device *dev, unsigned int reg)
{
return (reg == MAX77802_RTC_INT ||
reg == MAX77802_RTC_UPDATE0 ||
reg == MAX77802_RTC_UPDATE1);
}
static bool max77802_is_precious_reg(struct device *dev, unsigned int reg)
{
return (max77802_pmic_is_precious_reg(dev, reg) ||
max77802_rtc_is_precious_reg(dev, reg));
}
static bool max77802_pmic_is_volatile_reg(struct device *dev, unsigned int reg)
{
return (max77802_is_precious_reg(dev, reg) ||
reg == MAX77802_REG_STATUS1 || reg == MAX77802_REG_STATUS2 ||
reg == MAX77802_REG_PWRON);
}
static bool max77802_rtc_is_volatile_reg(struct device *dev, unsigned int reg)
{
return (max77802_rtc_is_precious_reg(dev, reg) ||
reg == MAX77802_RTC_SEC ||
reg == MAX77802_RTC_MIN ||
reg == MAX77802_RTC_HOUR ||
reg == MAX77802_RTC_WEEKDAY ||
reg == MAX77802_RTC_MONTH ||
reg == MAX77802_RTC_YEAR ||
reg == MAX77802_RTC_MONTHDAY);
}
static bool max77802_is_volatile_reg(struct device *dev, unsigned int reg)
{
return (max77802_pmic_is_volatile_reg(dev, reg) ||
max77802_rtc_is_volatile_reg(dev, reg));
}
static const struct regmap_config max77686_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
static const struct regmap_config max77802_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.writeable_reg = max77802_is_accessible_reg,
.readable_reg = max77802_is_accessible_reg,
.precious_reg = max77802_is_precious_reg,
.volatile_reg = max77802_is_volatile_reg,
.name = "max77802-pmic",
.cache_type = REGCACHE_RBTREE,
};
static const struct regmap_irq max77686_irqs[] = {
/* INT1 interrupts */
{ .reg_offset = 0, .mask = MAX77686_INT1_PWRONF_MSK, },
{ .reg_offset = 0, .mask = MAX77686_INT1_PWRONR_MSK, },
{ .reg_offset = 0, .mask = MAX77686_INT1_JIGONBF_MSK, },
{ .reg_offset = 0, .mask = MAX77686_INT1_JIGONBR_MSK, },
{ .reg_offset = 0, .mask = MAX77686_INT1_ACOKBF_MSK, },
{ .reg_offset = 0, .mask = MAX77686_INT1_ACOKBR_MSK, },
{ .reg_offset = 0, .mask = MAX77686_INT1_ONKEY1S_MSK, },
{ .reg_offset = 0, .mask = MAX77686_INT1_MRSTB_MSK, },
/* INT2 interrupts */
{ .reg_offset = 1, .mask = MAX77686_INT2_140C_MSK, },
{ .reg_offset = 1, .mask = MAX77686_INT2_120C_MSK, },
};
static const struct regmap_irq_chip max77686_irq_chip = {
.name = "max77686-pmic",
.status_base = MAX77686_REG_INT1,
.mask_base = MAX77686_REG_INT1MSK,
.num_regs = 2,
.irqs = max77686_irqs,
.num_irqs = ARRAY_SIZE(max77686_irqs),
};
static const struct regmap_irq_chip max77802_irq_chip = {
.name = "max77802-pmic",
.status_base = MAX77802_REG_INT1,
.mask_base = MAX77802_REG_INT1MSK,
.num_regs = 2,
.irqs = max77686_irqs, /* same masks as 77686 */
.num_irqs = ARRAY_SIZE(max77686_irqs),
};
static const struct of_device_id max77686_pmic_dt_match[] = {
{
.compatible = "maxim,max77686",
.data = (void *)TYPE_MAX77686,
},
{
.compatible = "maxim,max77802",
.data = (void *)TYPE_MAX77802,
},
{ },
};
MODULE_DEVICE_TABLE(of, max77686_pmic_dt_match);
static int max77686_i2c_probe(struct i2c_client *i2c)
{
struct max77686_dev *max77686 = NULL;
unsigned int data;
int ret = 0;
const struct regmap_config *config;
const struct regmap_irq_chip *irq_chip;
const struct mfd_cell *cells;
int n_devs;
max77686 = devm_kzalloc(&i2c->dev,
sizeof(struct max77686_dev), GFP_KERNEL);
if (!max77686)
return -ENOMEM;
i2c_set_clientdata(i2c, max77686);
max77686->type = (unsigned long)of_device_get_match_data(&i2c->dev);
max77686->dev = &i2c->dev;
max77686->i2c = i2c;
max77686->irq = i2c->irq;
if (max77686->type == TYPE_MAX77686) {
config = &max77686_regmap_config;
irq_chip = &max77686_irq_chip;
cells = max77686_devs;
n_devs = ARRAY_SIZE(max77686_devs);
} else {
config = &max77802_regmap_config;
irq_chip = &max77802_irq_chip;
cells = max77802_devs;
n_devs = ARRAY_SIZE(max77802_devs);
}
max77686->regmap = devm_regmap_init_i2c(i2c, config);
if (IS_ERR(max77686->regmap)) {
ret = PTR_ERR(max77686->regmap);
dev_err(max77686->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
ret = regmap_read(max77686->regmap, MAX77686_REG_DEVICE_ID, &data);
if (ret < 0) {
dev_err(max77686->dev,
"device not found on this channel (this is not an error)\n");
return -ENODEV;
}
ret = devm_regmap_add_irq_chip(&i2c->dev, max77686->regmap,
max77686->irq,
IRQF_ONESHOT | IRQF_SHARED, 0, irq_chip,
&max77686->irq_data);
if (ret < 0) {
dev_err(&i2c->dev, "failed to add PMIC irq chip: %d\n", ret);
return ret;
}
ret = devm_mfd_add_devices(max77686->dev, -1, cells, n_devs, NULL,
0, NULL);
if (ret < 0) {
dev_err(&i2c->dev, "failed to add MFD devices: %d\n", ret);
return ret;
}
return 0;
}
static int max77686_suspend(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct max77686_dev *max77686 = i2c_get_clientdata(i2c);
if (device_may_wakeup(dev))
enable_irq_wake(max77686->irq);
/*
* IRQ must be disabled during suspend because if it happens
* while suspended it will be handled before resuming I2C.
*
* When device is woken up from suspend (e.g. by RTC wake alarm),
* an interrupt occurs before resuming I2C bus controller.
* Interrupt handler tries to read registers but this read
* will fail because I2C is still suspended.
*/
disable_irq(max77686->irq);
return 0;
}
static int max77686_resume(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct max77686_dev *max77686 = i2c_get_clientdata(i2c);
if (device_may_wakeup(dev))
disable_irq_wake(max77686->irq);
enable_irq(max77686->irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(max77686_pm, max77686_suspend, max77686_resume);
static struct i2c_driver max77686_i2c_driver = {
.driver = {
.name = "max77686",
.pm = pm_sleep_ptr(&max77686_pm),
.of_match_table = max77686_pmic_dt_match,
},
.probe = max77686_i2c_probe,
};
module_i2c_driver(max77686_i2c_driver);
MODULE_DESCRIPTION("MAXIM 77686/802 multi-function core driver");
MODULE_AUTHOR("Chiwoong Byun <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/max77686.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* TI Palmas MFD Driver
*
* Copyright 2011-2012 Texas Instruments Inc.
*
* Author: Graeme Gregory <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/regmap.h>
#include <linux/err.h>
#include <linux/mfd/core.h>
#include <linux/mfd/palmas.h>
#include <linux/of.h>
#include <linux/of_platform.h>
static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
{
.reg_bits = 8,
.val_bits = 8,
.max_register = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
PALMAS_PRIMARY_SECONDARY_PAD3),
},
{
.reg_bits = 8,
.val_bits = 8,
.max_register = PALMAS_BASE_TO_REG(PALMAS_GPADC_BASE,
PALMAS_GPADC_SMPS_VSEL_MONITORING),
},
{
.reg_bits = 8,
.val_bits = 8,
.max_register = PALMAS_BASE_TO_REG(PALMAS_TRIM_GPADC_BASE,
PALMAS_GPADC_TRIM16),
},
};
static const struct regmap_irq tps65917_irqs[] = {
/* INT1 IRQs */
[TPS65917_RESERVED1] = {
.mask = TPS65917_RESERVED,
},
[TPS65917_PWRON_IRQ] = {
.mask = TPS65917_INT1_STATUS_PWRON,
},
[TPS65917_LONG_PRESS_KEY_IRQ] = {
.mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
},
[TPS65917_RESERVED2] = {
.mask = TPS65917_RESERVED,
},
[TPS65917_PWRDOWN_IRQ] = {
.mask = TPS65917_INT1_STATUS_PWRDOWN,
},
[TPS65917_HOTDIE_IRQ] = {
.mask = TPS65917_INT1_STATUS_HOTDIE,
},
[TPS65917_VSYS_MON_IRQ] = {
.mask = TPS65917_INT1_STATUS_VSYS_MON,
},
[TPS65917_RESERVED3] = {
.mask = TPS65917_RESERVED,
},
/* INT2 IRQs*/
[TPS65917_RESERVED4] = {
.mask = TPS65917_RESERVED,
.reg_offset = 1,
},
[TPS65917_OTP_ERROR_IRQ] = {
.mask = TPS65917_INT2_STATUS_OTP_ERROR,
.reg_offset = 1,
},
[TPS65917_WDT_IRQ] = {
.mask = TPS65917_INT2_STATUS_WDT,
.reg_offset = 1,
},
[TPS65917_RESERVED5] = {
.mask = TPS65917_RESERVED,
.reg_offset = 1,
},
[TPS65917_RESET_IN_IRQ] = {
.mask = TPS65917_INT2_STATUS_RESET_IN,
.reg_offset = 1,
},
[TPS65917_FSD_IRQ] = {
.mask = TPS65917_INT2_STATUS_FSD,
.reg_offset = 1,
},
[TPS65917_SHORT_IRQ] = {
.mask = TPS65917_INT2_STATUS_SHORT,
.reg_offset = 1,
},
[TPS65917_RESERVED6] = {
.mask = TPS65917_RESERVED,
.reg_offset = 1,
},
/* INT3 IRQs */
[TPS65917_GPADC_AUTO_0_IRQ] = {
.mask = TPS65917_INT3_STATUS_GPADC_AUTO_0,
.reg_offset = 2,
},
[TPS65917_GPADC_AUTO_1_IRQ] = {
.mask = TPS65917_INT3_STATUS_GPADC_AUTO_1,
.reg_offset = 2,
},
[TPS65917_GPADC_EOC_SW_IRQ] = {
.mask = TPS65917_INT3_STATUS_GPADC_EOC_SW,
.reg_offset = 2,
},
[TPS65917_RESREVED6] = {
.mask = TPS65917_RESERVED6,
.reg_offset = 2,
},
[TPS65917_RESERVED7] = {
.mask = TPS65917_RESERVED,
.reg_offset = 2,
},
[TPS65917_RESERVED8] = {
.mask = TPS65917_RESERVED,
.reg_offset = 2,
},
[TPS65917_RESERVED9] = {
.mask = TPS65917_RESERVED,
.reg_offset = 2,
},
[TPS65917_VBUS_IRQ] = {
.mask = TPS65917_INT3_STATUS_VBUS,
.reg_offset = 2,
},
/* INT4 IRQs */
[TPS65917_GPIO_0_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_0,
.reg_offset = 3,
},
[TPS65917_GPIO_1_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_1,
.reg_offset = 3,
},
[TPS65917_GPIO_2_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_2,
.reg_offset = 3,
},
[TPS65917_GPIO_3_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_3,
.reg_offset = 3,
},
[TPS65917_GPIO_4_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_4,
.reg_offset = 3,
},
[TPS65917_GPIO_5_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_5,
.reg_offset = 3,
},
[TPS65917_GPIO_6_IRQ] = {
.mask = TPS65917_INT4_STATUS_GPIO_6,
.reg_offset = 3,
},
[TPS65917_RESERVED10] = {
.mask = TPS65917_RESERVED10,
.reg_offset = 3,
},
};
static const struct regmap_irq palmas_irqs[] = {
/* INT1 IRQs */
[PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = {
.mask = PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV,
},
[PALMAS_PWRON_IRQ] = {
.mask = PALMAS_INT1_STATUS_PWRON,
},
[PALMAS_LONG_PRESS_KEY_IRQ] = {
.mask = PALMAS_INT1_STATUS_LONG_PRESS_KEY,
},
[PALMAS_RPWRON_IRQ] = {
.mask = PALMAS_INT1_STATUS_RPWRON,
},
[PALMAS_PWRDOWN_IRQ] = {
.mask = PALMAS_INT1_STATUS_PWRDOWN,
},
[PALMAS_HOTDIE_IRQ] = {
.mask = PALMAS_INT1_STATUS_HOTDIE,
},
[PALMAS_VSYS_MON_IRQ] = {
.mask = PALMAS_INT1_STATUS_VSYS_MON,
},
[PALMAS_VBAT_MON_IRQ] = {
.mask = PALMAS_INT1_STATUS_VBAT_MON,
},
/* INT2 IRQs*/
[PALMAS_RTC_ALARM_IRQ] = {
.mask = PALMAS_INT2_STATUS_RTC_ALARM,
.reg_offset = 1,
},
[PALMAS_RTC_TIMER_IRQ] = {
.mask = PALMAS_INT2_STATUS_RTC_TIMER,
.reg_offset = 1,
},
[PALMAS_WDT_IRQ] = {
.mask = PALMAS_INT2_STATUS_WDT,
.reg_offset = 1,
},
[PALMAS_BATREMOVAL_IRQ] = {
.mask = PALMAS_INT2_STATUS_BATREMOVAL,
.reg_offset = 1,
},
[PALMAS_RESET_IN_IRQ] = {
.mask = PALMAS_INT2_STATUS_RESET_IN,
.reg_offset = 1,
},
[PALMAS_FBI_BB_IRQ] = {
.mask = PALMAS_INT2_STATUS_FBI_BB,
.reg_offset = 1,
},
[PALMAS_SHORT_IRQ] = {
.mask = PALMAS_INT2_STATUS_SHORT,
.reg_offset = 1,
},
[PALMAS_VAC_ACOK_IRQ] = {
.mask = PALMAS_INT2_STATUS_VAC_ACOK,
.reg_offset = 1,
},
/* INT3 IRQs */
[PALMAS_GPADC_AUTO_0_IRQ] = {
.mask = PALMAS_INT3_STATUS_GPADC_AUTO_0,
.reg_offset = 2,
},
[PALMAS_GPADC_AUTO_1_IRQ] = {
.mask = PALMAS_INT3_STATUS_GPADC_AUTO_1,
.reg_offset = 2,
},
[PALMAS_GPADC_EOC_SW_IRQ] = {
.mask = PALMAS_INT3_STATUS_GPADC_EOC_SW,
.reg_offset = 2,
},
[PALMAS_GPADC_EOC_RT_IRQ] = {
.mask = PALMAS_INT3_STATUS_GPADC_EOC_RT,
.reg_offset = 2,
},
[PALMAS_ID_OTG_IRQ] = {
.mask = PALMAS_INT3_STATUS_ID_OTG,
.reg_offset = 2,
},
[PALMAS_ID_IRQ] = {
.mask = PALMAS_INT3_STATUS_ID,
.reg_offset = 2,
},
[PALMAS_VBUS_OTG_IRQ] = {
.mask = PALMAS_INT3_STATUS_VBUS_OTG,
.reg_offset = 2,
},
[PALMAS_VBUS_IRQ] = {
.mask = PALMAS_INT3_STATUS_VBUS,
.reg_offset = 2,
},
/* INT4 IRQs */
[PALMAS_GPIO_0_IRQ] = {
.mask = PALMAS_INT4_STATUS_GPIO_0,
.reg_offset = 3,
},
[PALMAS_GPIO_1_IRQ] = {
.mask = PALMAS_INT4_STATUS_GPIO_1,
.reg_offset = 3,
},
[PALMAS_GPIO_2_IRQ] = {
.mask = PALMAS_INT4_STATUS_GPIO_2,
.reg_offset = 3,
},
[PALMAS_GPIO_3_IRQ] = {
.mask = PALMAS_INT4_STATUS_GPIO_3,
.reg_offset = 3,
},
[PALMAS_GPIO_4_IRQ] = {
.mask = PALMAS_INT4_STATUS_GPIO_4,
.reg_offset = 3,
},
[PALMAS_GPIO_5_IRQ] = {
.mask = PALMAS_INT4_STATUS_GPIO_5,
.reg_offset = 3,
},
[PALMAS_GPIO_6_IRQ] = {
.mask = PALMAS_INT4_STATUS_GPIO_6,
.reg_offset = 3,
},
[PALMAS_GPIO_7_IRQ] = {
.mask = PALMAS_INT4_STATUS_GPIO_7,
.reg_offset = 3,
},
};
static struct regmap_irq_chip palmas_irq_chip = {
.name = "palmas",
.irqs = palmas_irqs,
.num_irqs = ARRAY_SIZE(palmas_irqs),
.num_regs = 4,
.irq_reg_stride = 5,
.status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
PALMAS_INT1_STATUS),
.mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
PALMAS_INT1_MASK),
};
static struct regmap_irq_chip tps65917_irq_chip = {
.name = "tps65917",
.irqs = tps65917_irqs,
.num_irqs = ARRAY_SIZE(tps65917_irqs),
.num_regs = 4,
.irq_reg_stride = 5,
.status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
PALMAS_INT1_STATUS),
.mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
PALMAS_INT1_MASK),
};
int palmas_ext_control_req_config(struct palmas *palmas,
enum palmas_external_requestor_id id, int ext_ctrl, bool enable)
{
struct palmas_pmic_driver_data *pmic_ddata = palmas->pmic_ddata;
int preq_mask_bit = 0;
int reg_add = 0;
int bit_pos, ret;
if (!(ext_ctrl & PALMAS_EXT_REQ))
return 0;
if (id >= PALMAS_EXTERNAL_REQSTR_ID_MAX)
return 0;
if (ext_ctrl & PALMAS_EXT_CONTROL_NSLEEP) {
reg_add = PALMAS_NSLEEP_RES_ASSIGN;
preq_mask_bit = 0;
} else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE1) {
reg_add = PALMAS_ENABLE1_RES_ASSIGN;
preq_mask_bit = 1;
} else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE2) {
reg_add = PALMAS_ENABLE2_RES_ASSIGN;
preq_mask_bit = 2;
}
bit_pos = pmic_ddata->sleep_req_info[id].bit_pos;
reg_add += pmic_ddata->sleep_req_info[id].reg_offset;
if (enable)
ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
reg_add, BIT(bit_pos), BIT(bit_pos));
else
ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
reg_add, BIT(bit_pos), 0);
if (ret < 0) {
dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
reg_add, ret);
return ret;
}
/* Unmask the PREQ */
ret = palmas_update_bits(palmas, PALMAS_PMU_CONTROL_BASE,
PALMAS_POWER_CTRL, BIT(preq_mask_bit), 0);
if (ret < 0) {
dev_err(palmas->dev, "POWER_CTRL register update failed %d\n",
ret);
return ret;
}
return ret;
}
EXPORT_SYMBOL_GPL(palmas_ext_control_req_config);
static int palmas_set_pdata_irq_flag(struct i2c_client *i2c,
struct palmas_platform_data *pdata)
{
struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
if (!irq_data) {
dev_err(&i2c->dev, "Invalid IRQ: %d\n", i2c->irq);
return -EINVAL;
}
pdata->irq_flags = irqd_get_trigger_type(irq_data);
dev_info(&i2c->dev, "Irq flag is 0x%08x\n", pdata->irq_flags);
return 0;
}
static void palmas_dt_to_pdata(struct i2c_client *i2c,
struct palmas_platform_data *pdata)
{
struct device_node *node = i2c->dev.of_node;
int ret;
u32 prop;
ret = of_property_read_u32(node, "ti,mux-pad1", &prop);
if (!ret) {
pdata->mux_from_pdata = 1;
pdata->pad1 = prop;
}
ret = of_property_read_u32(node, "ti,mux-pad2", &prop);
if (!ret) {
pdata->mux_from_pdata = 1;
pdata->pad2 = prop;
}
/* The default for this register is all masked */
ret = of_property_read_u32(node, "ti,power-ctrl", &prop);
if (!ret)
pdata->power_ctrl = prop;
else
pdata->power_ctrl = PALMAS_POWER_CTRL_NSLEEP_MASK |
PALMAS_POWER_CTRL_ENABLE1_MASK |
PALMAS_POWER_CTRL_ENABLE2_MASK;
if (i2c->irq)
palmas_set_pdata_irq_flag(i2c, pdata);
pdata->pm_off = of_property_read_bool(node,
"ti,system-power-controller");
}
static struct palmas *palmas_dev;
static void palmas_power_off(void)
{
unsigned int addr;
int ret, slave;
u8 powerhold_mask;
struct device_node *np = palmas_dev->dev->of_node;
if (of_property_read_bool(np, "ti,palmas-override-powerhold")) {
addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
PALMAS_PRIMARY_SECONDARY_PAD2);
slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
if (of_device_is_compatible(np, "ti,tps65917"))
powerhold_mask =
TPS65917_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK;
else
powerhold_mask =
PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK;
ret = regmap_update_bits(palmas_dev->regmap[slave], addr,
powerhold_mask, 0);
if (ret)
dev_err(palmas_dev->dev,
"Unable to write PRIMARY_SECONDARY_PAD2 %d\n",
ret);
}
slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_DEV_CTRL);
ret = regmap_update_bits(
palmas_dev->regmap[slave],
addr,
PALMAS_DEV_CTRL_DEV_ON,
0);
if (ret)
pr_err("%s: Unable to write to DEV_CTRL_DEV_ON: %d\n",
__func__, ret);
}
static unsigned int palmas_features = PALMAS_PMIC_FEATURE_SMPS10_BOOST;
static unsigned int tps659038_features;
struct palmas_driver_data {
unsigned int *features;
struct regmap_irq_chip *irq_chip;
};
static struct palmas_driver_data palmas_data = {
.features = &palmas_features,
.irq_chip = &palmas_irq_chip,
};
static struct palmas_driver_data tps659038_data = {
.features = &tps659038_features,
.irq_chip = &palmas_irq_chip,
};
static struct palmas_driver_data tps65917_data = {
.features = &tps659038_features,
.irq_chip = &tps65917_irq_chip,
};
static const struct of_device_id of_palmas_match_tbl[] = {
{
.compatible = "ti,palmas",
.data = &palmas_data,
},
{
.compatible = "ti,tps659038",
.data = &tps659038_data,
},
{
.compatible = "ti,tps65917",
.data = &tps65917_data,
},
{ },
};
MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
static int palmas_i2c_probe(struct i2c_client *i2c)
{
struct palmas *palmas;
struct palmas_platform_data *pdata;
struct palmas_driver_data *driver_data;
struct device_node *node = i2c->dev.of_node;
int ret = 0, i;
unsigned int reg, addr;
int slave;
pdata = dev_get_platdata(&i2c->dev);
if (node && !pdata) {
pdata = devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
palmas_dt_to_pdata(i2c, pdata);
}
if (!pdata)
return -EINVAL;
palmas = devm_kzalloc(&i2c->dev, sizeof(struct palmas), GFP_KERNEL);
if (palmas == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, palmas);
palmas->dev = &i2c->dev;
palmas->irq = i2c->irq;
driver_data = (struct palmas_driver_data *) device_get_match_data(&i2c->dev);
palmas->features = *driver_data->features;
for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
if (i == 0)
palmas->i2c_clients[i] = i2c;
else {
palmas->i2c_clients[i] =
i2c_new_dummy_device(i2c->adapter,
i2c->addr + i);
if (IS_ERR(palmas->i2c_clients[i])) {
dev_err(palmas->dev,
"can't attach client %d\n", i);
ret = PTR_ERR(palmas->i2c_clients[i]);
goto err_i2c;
}
palmas->i2c_clients[i]->dev.of_node = of_node_get(node);
}
palmas->regmap[i] = devm_regmap_init_i2c(palmas->i2c_clients[i],
&palmas_regmap_config[i]);
if (IS_ERR(palmas->regmap[i])) {
ret = PTR_ERR(palmas->regmap[i]);
dev_err(palmas->dev,
"Failed to allocate regmap %d, err: %d\n",
i, ret);
goto err_i2c;
}
}
if (!palmas->irq) {
dev_warn(palmas->dev, "IRQ missing: skipping irq request\n");
goto no_irq;
}
/* Change interrupt line output polarity */
if (pdata->irq_flags & IRQ_TYPE_LEVEL_HIGH)
reg = PALMAS_POLARITY_CTRL_INT_POLARITY;
else
reg = 0;
ret = palmas_update_bits(palmas, PALMAS_PU_PD_OD_BASE,
PALMAS_POLARITY_CTRL, PALMAS_POLARITY_CTRL_INT_POLARITY,
reg);
if (ret < 0) {
dev_err(palmas->dev, "POLARITY_CTRL update failed: %d\n", ret);
goto err_i2c;
}
/* Change IRQ into clear on read mode for efficiency */
slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE);
addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, PALMAS_INT_CTRL);
reg = PALMAS_INT_CTRL_INT_CLEAR;
regmap_write(palmas->regmap[slave], addr, reg);
ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
IRQF_ONESHOT | pdata->irq_flags, 0,
driver_data->irq_chip, &palmas->irq_data);
if (ret < 0)
goto err_i2c;
no_irq:
slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
PALMAS_PRIMARY_SECONDARY_PAD1);
if (pdata->mux_from_pdata) {
reg = pdata->pad1;
ret = regmap_write(palmas->regmap[slave], addr, reg);
if (ret)
goto err_irq;
} else {
ret = regmap_read(palmas->regmap[slave], addr, ®);
if (ret)
goto err_irq;
}
if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0))
palmas->gpio_muxed |= PALMAS_GPIO_0_MUXED;
if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK))
palmas->gpio_muxed |= PALMAS_GPIO_1_MUXED;
else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
(2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
palmas->led_muxed |= PALMAS_LED1_MUXED;
else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
(3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
palmas->pwm_muxed |= PALMAS_PWM1_MUXED;
if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK))
palmas->gpio_muxed |= PALMAS_GPIO_2_MUXED;
else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
(2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
palmas->led_muxed |= PALMAS_LED2_MUXED;
else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
(3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
palmas->pwm_muxed |= PALMAS_PWM2_MUXED;
if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3))
palmas->gpio_muxed |= PALMAS_GPIO_3_MUXED;
addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
PALMAS_PRIMARY_SECONDARY_PAD2);
if (pdata->mux_from_pdata) {
reg = pdata->pad2;
ret = regmap_write(palmas->regmap[slave], addr, reg);
if (ret)
goto err_irq;
} else {
ret = regmap_read(palmas->regmap[slave], addr, ®);
if (ret)
goto err_irq;
}
if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4))
palmas->gpio_muxed |= PALMAS_GPIO_4_MUXED;
if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK))
palmas->gpio_muxed |= PALMAS_GPIO_5_MUXED;
if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6))
palmas->gpio_muxed |= PALMAS_GPIO_6_MUXED;
if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK))
palmas->gpio_muxed |= PALMAS_GPIO_7_MUXED;
dev_info(palmas->dev, "Muxing GPIO %x, PWM %x, LED %x\n",
palmas->gpio_muxed, palmas->pwm_muxed,
palmas->led_muxed);
reg = pdata->power_ctrl;
slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_POWER_CTRL);
ret = regmap_write(palmas->regmap[slave], addr, reg);
if (ret)
goto err_irq;
/*
* If we are probing with DT do this the DT way and return here
* otherwise continue and add devices using mfd helpers.
*/
if (node) {
ret = devm_of_platform_populate(&i2c->dev);
if (ret < 0) {
goto err_irq;
} else if (pdata->pm_off && !pm_power_off) {
palmas_dev = palmas;
pm_power_off = palmas_power_off;
}
}
return ret;
err_irq:
regmap_del_irq_chip(palmas->irq, palmas->irq_data);
err_i2c:
for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
if (palmas->i2c_clients[i])
i2c_unregister_device(palmas->i2c_clients[i]);
}
return ret;
}
static void palmas_i2c_remove(struct i2c_client *i2c)
{
struct palmas *palmas = i2c_get_clientdata(i2c);
int i;
regmap_del_irq_chip(palmas->irq, palmas->irq_data);
for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
if (palmas->i2c_clients[i])
i2c_unregister_device(palmas->i2c_clients[i]);
}
if (palmas == palmas_dev) {
pm_power_off = NULL;
palmas_dev = NULL;
}
}
static const struct i2c_device_id palmas_i2c_id[] = {
{ "palmas", },
{ "twl6035", },
{ "twl6037", },
{ "tps65913", },
{ /* end */ }
};
MODULE_DEVICE_TABLE(i2c, palmas_i2c_id);
static struct i2c_driver palmas_i2c_driver = {
.driver = {
.name = "palmas",
.of_match_table = of_palmas_match_tbl,
},
.probe = palmas_i2c_probe,
.remove = palmas_i2c_remove,
.id_table = palmas_i2c_id,
};
static int __init palmas_i2c_init(void)
{
return i2c_add_driver(&palmas_i2c_driver);
}
/* init early so consumer devices can complete system boot */
subsys_initcall(palmas_i2c_init);
static void __exit palmas_i2c_exit(void)
{
i2c_del_driver(&palmas_i2c_driver);
}
module_exit(palmas_i2c_exit);
MODULE_AUTHOR("Graeme Gregory <[email protected]>");
MODULE_DESCRIPTION("Palmas chip family multi-function driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/palmas.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* twl_core.c - driver for TWL4030/TWL5030/TWL60X0/TPS659x0 PM
* and audio CODEC devices
*
* Copyright (C) 2005-2006 Texas Instruments, Inc.
*
* Modifications to defer interrupt handling to a kernel thread:
* Copyright (C) 2006 MontaVista Software, Inc.
*
* Based on tlv320aic23.c:
* Copyright (c) by Kai Svahn <[email protected]>
*
* Code cleanup and modifications to IRQ handler.
* by syed khasim <[email protected]>
*/
#include <linux/init.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/device.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/regulator/machine.h>
#include <linux/i2c.h>
#include <linux/mfd/twl.h>
/* Register descriptions for audio */
#include <linux/mfd/twl4030-audio.h>
#include "twl-core.h"
/*
* The TWL4030 "Triton 2" is one of a family of a multi-function "Power
* Management and System Companion Device" chips originally designed for
* use in OMAP2 and OMAP 3 based systems. Its control interfaces use I2C,
* often at around 3 Mbit/sec, including for interrupt handling.
*
* This driver core provides genirq support for the interrupts emitted,
* by the various modules, and exports register access primitives.
*
* FIXME this driver currently requires use of the first interrupt line
* (and associated registers).
*/
#define DRIVER_NAME "twl"
/* Triton Core internal information (BEGIN) */
/* Base Address defns for twl4030_map[] */
/* subchip/slave 0 - USB ID */
#define TWL4030_BASEADD_USB 0x0000
/* subchip/slave 1 - AUD ID */
#define TWL4030_BASEADD_AUDIO_VOICE 0x0000
#define TWL4030_BASEADD_GPIO 0x0098
#define TWL4030_BASEADD_INTBR 0x0085
#define TWL4030_BASEADD_PIH 0x0080
#define TWL4030_BASEADD_TEST 0x004C
/* subchip/slave 2 - AUX ID */
#define TWL4030_BASEADD_INTERRUPTS 0x00B9
#define TWL4030_BASEADD_LED 0x00EE
#define TWL4030_BASEADD_MADC 0x0000
#define TWL4030_BASEADD_MAIN_CHARGE 0x0074
#define TWL4030_BASEADD_PRECHARGE 0x00AA
#define TWL4030_BASEADD_PWM 0x00F8
#define TWL4030_BASEADD_KEYPAD 0x00D2
#define TWL5031_BASEADD_ACCESSORY 0x0074 /* Replaces Main Charge */
#define TWL5031_BASEADD_INTERRUPTS 0x00B9 /* Different than TWL4030's
one */
/* subchip/slave 3 - POWER ID */
#define TWL4030_BASEADD_BACKUP 0x0014
#define TWL4030_BASEADD_INT 0x002E
#define TWL4030_BASEADD_PM_MASTER 0x0036
#define TWL4030_BASEADD_PM_RECEIVER 0x005B
#define TWL4030_DCDC_GLOBAL_CFG 0x06
#define SMARTREFLEX_ENABLE BIT(3)
#define TWL4030_BASEADD_RTC 0x001C
#define TWL4030_BASEADD_SECURED_REG 0x0000
/* Triton Core internal information (END) */
/* subchip/slave 0 0x48 - POWER */
#define TWL6030_BASEADD_RTC 0x0000
#define TWL6030_BASEADD_SECURED_REG 0x0017
#define TWL6030_BASEADD_PM_MASTER 0x001F
#define TWL6030_BASEADD_PM_SLAVE_MISC 0x0030 /* PM_RECEIVER */
#define TWL6030_BASEADD_PM_MISC 0x00E2
#define TWL6030_BASEADD_PM_PUPD 0x00F0
/* subchip/slave 1 0x49 - FEATURE */
#define TWL6030_BASEADD_USB 0x0000
#define TWL6030_BASEADD_GPADC_CTRL 0x002E
#define TWL6030_BASEADD_AUX 0x0090
#define TWL6030_BASEADD_PWM 0x00BA
#define TWL6030_BASEADD_GASGAUGE 0x00C0
#define TWL6030_BASEADD_PIH 0x00D0
#define TWL6032_BASEADD_CHARGER 0x00DA
#define TWL6030_BASEADD_CHARGER 0x00E0
#define TWL6030_BASEADD_LED 0x00F4
/* subchip/slave 2 0x4A - DFT */
#define TWL6030_BASEADD_DIEID 0x00C0
/* subchip/slave 3 0x4B - AUDIO */
#define TWL6030_BASEADD_AUDIO 0x0000
#define TWL6030_BASEADD_RSV 0x0000
#define TWL6030_BASEADD_ZERO 0x0000
/* Few power values */
#define R_CFG_BOOT 0x05
/* some fields in R_CFG_BOOT */
#define HFCLK_FREQ_19p2_MHZ (1 << 0)
#define HFCLK_FREQ_26_MHZ (2 << 0)
#define HFCLK_FREQ_38p4_MHZ (3 << 0)
#define HIGH_PERF_SQ (1 << 3)
#define CK32K_LOWPWR_EN (1 << 7)
/*----------------------------------------------------------------------*/
/* Structure for each TWL4030/TWL6030 Slave */
struct twl_client {
struct i2c_client *client;
struct regmap *regmap;
};
/* mapping the module id to slave id and base address */
struct twl_mapping {
unsigned char sid; /* Slave ID */
unsigned char base; /* base address */
};
struct twl_private {
bool ready; /* The core driver is ready to be used */
u32 twl_idcode; /* TWL IDCODE Register value */
unsigned int twl_id;
struct twl_mapping *twl_map;
struct twl_client *twl_modules;
};
static struct twl_private *twl_priv;
static struct twl_mapping twl4030_map[] = {
/*
* NOTE: don't change this table without updating the
* <linux/mfd/twl.h> defines for TWL4030_MODULE_*
* so they continue to match the order in this table.
*/
/* Common IPs */
{ 0, TWL4030_BASEADD_USB },
{ 1, TWL4030_BASEADD_PIH },
{ 2, TWL4030_BASEADD_MAIN_CHARGE },
{ 3, TWL4030_BASEADD_PM_MASTER },
{ 3, TWL4030_BASEADD_PM_RECEIVER },
{ 3, TWL4030_BASEADD_RTC },
{ 2, TWL4030_BASEADD_PWM },
{ 2, TWL4030_BASEADD_LED },
{ 3, TWL4030_BASEADD_SECURED_REG },
/* TWL4030 specific IPs */
{ 1, TWL4030_BASEADD_AUDIO_VOICE },
{ 1, TWL4030_BASEADD_GPIO },
{ 1, TWL4030_BASEADD_INTBR },
{ 1, TWL4030_BASEADD_TEST },
{ 2, TWL4030_BASEADD_KEYPAD },
{ 2, TWL4030_BASEADD_MADC },
{ 2, TWL4030_BASEADD_INTERRUPTS },
{ 2, TWL4030_BASEADD_PRECHARGE },
{ 3, TWL4030_BASEADD_BACKUP },
{ 3, TWL4030_BASEADD_INT },
{ 2, TWL5031_BASEADD_ACCESSORY },
{ 2, TWL5031_BASEADD_INTERRUPTS },
};
static const struct reg_default twl4030_49_defaults[] = {
/* Audio Registers */
{ 0x01, 0x00}, /* CODEC_MODE */
{ 0x02, 0x00}, /* OPTION */
/* 0x03 Unused */
{ 0x04, 0x00}, /* MICBIAS_CTL */
{ 0x05, 0x00}, /* ANAMICL */
{ 0x06, 0x00}, /* ANAMICR */
{ 0x07, 0x00}, /* AVADC_CTL */
{ 0x08, 0x00}, /* ADCMICSEL */
{ 0x09, 0x00}, /* DIGMIXING */
{ 0x0a, 0x0f}, /* ATXL1PGA */
{ 0x0b, 0x0f}, /* ATXR1PGA */
{ 0x0c, 0x0f}, /* AVTXL2PGA */
{ 0x0d, 0x0f}, /* AVTXR2PGA */
{ 0x0e, 0x00}, /* AUDIO_IF */
{ 0x0f, 0x00}, /* VOICE_IF */
{ 0x10, 0x3f}, /* ARXR1PGA */
{ 0x11, 0x3f}, /* ARXL1PGA */
{ 0x12, 0x3f}, /* ARXR2PGA */
{ 0x13, 0x3f}, /* ARXL2PGA */
{ 0x14, 0x25}, /* VRXPGA */
{ 0x15, 0x00}, /* VSTPGA */
{ 0x16, 0x00}, /* VRX2ARXPGA */
{ 0x17, 0x00}, /* AVDAC_CTL */
{ 0x18, 0x00}, /* ARX2VTXPGA */
{ 0x19, 0x32}, /* ARXL1_APGA_CTL*/
{ 0x1a, 0x32}, /* ARXR1_APGA_CTL*/
{ 0x1b, 0x32}, /* ARXL2_APGA_CTL*/
{ 0x1c, 0x32}, /* ARXR2_APGA_CTL*/
{ 0x1d, 0x00}, /* ATX2ARXPGA */
{ 0x1e, 0x00}, /* BT_IF */
{ 0x1f, 0x55}, /* BTPGA */
{ 0x20, 0x00}, /* BTSTPGA */
{ 0x21, 0x00}, /* EAR_CTL */
{ 0x22, 0x00}, /* HS_SEL */
{ 0x23, 0x00}, /* HS_GAIN_SET */
{ 0x24, 0x00}, /* HS_POPN_SET */
{ 0x25, 0x00}, /* PREDL_CTL */
{ 0x26, 0x00}, /* PREDR_CTL */
{ 0x27, 0x00}, /* PRECKL_CTL */
{ 0x28, 0x00}, /* PRECKR_CTL */
{ 0x29, 0x00}, /* HFL_CTL */
{ 0x2a, 0x00}, /* HFR_CTL */
{ 0x2b, 0x05}, /* ALC_CTL */
{ 0x2c, 0x00}, /* ALC_SET1 */
{ 0x2d, 0x00}, /* ALC_SET2 */
{ 0x2e, 0x00}, /* BOOST_CTL */
{ 0x2f, 0x00}, /* SOFTVOL_CTL */
{ 0x30, 0x13}, /* DTMF_FREQSEL */
{ 0x31, 0x00}, /* DTMF_TONEXT1H */
{ 0x32, 0x00}, /* DTMF_TONEXT1L */
{ 0x33, 0x00}, /* DTMF_TONEXT2H */
{ 0x34, 0x00}, /* DTMF_TONEXT2L */
{ 0x35, 0x79}, /* DTMF_TONOFF */
{ 0x36, 0x11}, /* DTMF_WANONOFF */
{ 0x37, 0x00}, /* I2S_RX_SCRAMBLE_H */
{ 0x38, 0x00}, /* I2S_RX_SCRAMBLE_M */
{ 0x39, 0x00}, /* I2S_RX_SCRAMBLE_L */
{ 0x3a, 0x06}, /* APLL_CTL */
{ 0x3b, 0x00}, /* DTMF_CTL */
{ 0x3c, 0x44}, /* DTMF_PGA_CTL2 (0x3C) */
{ 0x3d, 0x69}, /* DTMF_PGA_CTL1 (0x3D) */
{ 0x3e, 0x00}, /* MISC_SET_1 */
{ 0x3f, 0x00}, /* PCMBTMUX */
/* 0x40 - 0x42 Unused */
{ 0x43, 0x00}, /* RX_PATH_SEL */
{ 0x44, 0x32}, /* VDL_APGA_CTL */
{ 0x45, 0x00}, /* VIBRA_CTL */
{ 0x46, 0x00}, /* VIBRA_SET */
{ 0x47, 0x00}, /* VIBRA_PWM_SET */
{ 0x48, 0x00}, /* ANAMIC_GAIN */
{ 0x49, 0x00}, /* MISC_SET_2 */
/* End of Audio Registers */
};
static bool twl4030_49_nop_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x00:
case 0x03:
case 0x40:
case 0x41:
case 0x42:
return false;
default:
return true;
}
}
static const struct regmap_range twl4030_49_volatile_ranges[] = {
regmap_reg_range(TWL4030_BASEADD_TEST, 0xff),
};
static const struct regmap_access_table twl4030_49_volatile_table = {
.yes_ranges = twl4030_49_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(twl4030_49_volatile_ranges),
};
static const struct regmap_config twl4030_regmap_config[4] = {
{
/* Address 0x48 */
.reg_bits = 8,
.val_bits = 8,
.max_register = 0xff,
},
{
/* Address 0x49 */
.reg_bits = 8,
.val_bits = 8,
.max_register = 0xff,
.readable_reg = twl4030_49_nop_reg,
.writeable_reg = twl4030_49_nop_reg,
.volatile_table = &twl4030_49_volatile_table,
.reg_defaults = twl4030_49_defaults,
.num_reg_defaults = ARRAY_SIZE(twl4030_49_defaults),
.cache_type = REGCACHE_RBTREE,
},
{
/* Address 0x4a */
.reg_bits = 8,
.val_bits = 8,
.max_register = 0xff,
},
{
/* Address 0x4b */
.reg_bits = 8,
.val_bits = 8,
.max_register = 0xff,
},
};
static struct twl_mapping twl6030_map[] = {
/*
* NOTE: don't change this table without updating the
* <linux/mfd/twl.h> defines for TWL4030_MODULE_*
* so they continue to match the order in this table.
*/
/* Common IPs */
{ 1, TWL6030_BASEADD_USB },
{ 1, TWL6030_BASEADD_PIH },
{ 1, TWL6030_BASEADD_CHARGER },
{ 0, TWL6030_BASEADD_PM_MASTER },
{ 0, TWL6030_BASEADD_PM_SLAVE_MISC },
{ 0, TWL6030_BASEADD_RTC },
{ 1, TWL6030_BASEADD_PWM },
{ 1, TWL6030_BASEADD_LED },
{ 0, TWL6030_BASEADD_SECURED_REG },
/* TWL6030 specific IPs */
{ 0, TWL6030_BASEADD_ZERO },
{ 1, TWL6030_BASEADD_ZERO },
{ 2, TWL6030_BASEADD_ZERO },
{ 1, TWL6030_BASEADD_GPADC_CTRL },
{ 1, TWL6030_BASEADD_GASGAUGE },
/* TWL6032 specific charger registers */
{ 1, TWL6032_BASEADD_CHARGER },
};
static const struct regmap_config twl6030_regmap_config[3] = {
{
/* Address 0x48 */
.reg_bits = 8,
.val_bits = 8,
.max_register = 0xff,
},
{
/* Address 0x49 */
.reg_bits = 8,
.val_bits = 8,
.max_register = 0xff,
},
{
/* Address 0x4a */
.reg_bits = 8,
.val_bits = 8,
.max_register = 0xff,
},
};
/*----------------------------------------------------------------------*/
static inline int twl_get_num_slaves(void)
{
if (twl_class_is_4030())
return 4; /* TWL4030 class have four slave address */
else
return 3; /* TWL6030 class have three slave address */
}
static inline int twl_get_last_module(void)
{
if (twl_class_is_4030())
return TWL4030_MODULE_LAST;
else
return TWL6030_MODULE_LAST;
}
/* Exported Functions */
unsigned int twl_rev(void)
{
return twl_priv ? twl_priv->twl_id : 0;
}
EXPORT_SYMBOL(twl_rev);
/**
* twl_get_regmap - Get the regmap associated with the given module
* @mod_no: module number
*
* Returns the regmap pointer or NULL in case of failure.
*/
static struct regmap *twl_get_regmap(u8 mod_no)
{
int sid;
struct twl_client *twl;
if (unlikely(!twl_priv || !twl_priv->ready)) {
pr_err("%s: not initialized\n", DRIVER_NAME);
return NULL;
}
if (unlikely(mod_no >= twl_get_last_module())) {
pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no);
return NULL;
}
sid = twl_priv->twl_map[mod_no].sid;
twl = &twl_priv->twl_modules[sid];
return twl->regmap;
}
/**
* twl_i2c_write - Writes a n bit register in TWL4030/TWL5030/TWL60X0
* @mod_no: module number
* @value: an array of num_bytes+1 containing data to write
* @reg: register address (just offset will do)
* @num_bytes: number of bytes to transfer
*
* Returns 0 on success or else a negative error code.
*/
int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
{
struct regmap *regmap = twl_get_regmap(mod_no);
int ret;
if (!regmap)
return -EPERM;
ret = regmap_bulk_write(regmap, twl_priv->twl_map[mod_no].base + reg,
value, num_bytes);
if (ret)
pr_err("%s: Write failed (mod %d, reg 0x%02x count %d)\n",
DRIVER_NAME, mod_no, reg, num_bytes);
return ret;
}
EXPORT_SYMBOL(twl_i2c_write);
/**
* twl_i2c_read - Reads a n bit register in TWL4030/TWL5030/TWL60X0
* @mod_no: module number
* @value: an array of num_bytes containing data to be read
* @reg: register address (just offset will do)
* @num_bytes: number of bytes to transfer
*
* Returns 0 on success or else a negative error code.
*/
int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
{
struct regmap *regmap = twl_get_regmap(mod_no);
int ret;
if (!regmap)
return -EPERM;
ret = regmap_bulk_read(regmap, twl_priv->twl_map[mod_no].base + reg,
value, num_bytes);
if (ret)
pr_err("%s: Read failed (mod %d, reg 0x%02x count %d)\n",
DRIVER_NAME, mod_no, reg, num_bytes);
return ret;
}
EXPORT_SYMBOL(twl_i2c_read);
/**
* twl_set_regcache_bypass - Configure the regcache bypass for the regmap associated
* with the module
* @mod_no: module number
* @enable: Regcache bypass state
*
* Returns 0 else failure.
*/
int twl_set_regcache_bypass(u8 mod_no, bool enable)
{
struct regmap *regmap = twl_get_regmap(mod_no);
if (!regmap)
return -EPERM;
regcache_cache_bypass(regmap, enable);
return 0;
}
EXPORT_SYMBOL(twl_set_regcache_bypass);
/*----------------------------------------------------------------------*/
/**
* twl_read_idcode_register - API to read the IDCODE register.
*
* Unlocks the IDCODE register and read the 32 bit value.
*/
static int twl_read_idcode_register(void)
{
int err;
err = twl_i2c_write_u8(TWL4030_MODULE_INTBR, TWL_EEPROM_R_UNLOCK,
REG_UNLOCK_TEST_REG);
if (err) {
pr_err("TWL4030 Unable to unlock IDCODE registers -%d\n", err);
goto fail;
}
err = twl_i2c_read(TWL4030_MODULE_INTBR, (u8 *)(&twl_priv->twl_idcode),
REG_IDCODE_7_0, 4);
if (err) {
pr_err("TWL4030: unable to read IDCODE -%d\n", err);
goto fail;
}
err = twl_i2c_write_u8(TWL4030_MODULE_INTBR, 0x0, REG_UNLOCK_TEST_REG);
if (err)
pr_err("TWL4030 Unable to relock IDCODE registers -%d\n", err);
fail:
return err;
}
/**
* twl_get_type - API to get TWL Si type.
*
* Api to get the TWL Si type from IDCODE value.
*/
int twl_get_type(void)
{
return TWL_SIL_TYPE(twl_priv->twl_idcode);
}
EXPORT_SYMBOL_GPL(twl_get_type);
/**
* twl_get_version - API to get TWL Si version.
*
* Api to get the TWL Si version from IDCODE value.
*/
int twl_get_version(void)
{
return TWL_SIL_REV(twl_priv->twl_idcode);
}
EXPORT_SYMBOL_GPL(twl_get_version);
/**
* twl_get_hfclk_rate - API to get TWL external HFCLK clock rate.
*
* Api to get the TWL HFCLK rate based on BOOT_CFG register.
*/
int twl_get_hfclk_rate(void)
{
u8 ctrl;
int rate;
twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &ctrl, R_CFG_BOOT);
switch (ctrl & 0x3) {
case HFCLK_FREQ_19p2_MHZ:
rate = 19200000;
break;
case HFCLK_FREQ_26_MHZ:
rate = 26000000;
break;
case HFCLK_FREQ_38p4_MHZ:
rate = 38400000;
break;
default:
pr_err("TWL4030: HFCLK is not configured\n");
rate = -EINVAL;
break;
}
return rate;
}
EXPORT_SYMBOL_GPL(twl_get_hfclk_rate);
/*----------------------------------------------------------------------*/
/*
* These three functions initialize the on-chip clock framework,
* letting it generate the right frequencies for USB, MADC, and
* other purposes.
*/
static inline int protect_pm_master(void)
{
int e = 0;
e = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
TWL4030_PM_MASTER_PROTECT_KEY);
return e;
}
static inline int unprotect_pm_master(void)
{
int e = 0;
e |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
TWL4030_PM_MASTER_PROTECT_KEY);
e |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
TWL4030_PM_MASTER_PROTECT_KEY);
return e;
}
static void clocks_init(struct device *dev)
{
int e = 0;
struct clk *osc;
u32 rate;
u8 ctrl = HFCLK_FREQ_26_MHZ;
osc = clk_get(dev, "fck");
if (IS_ERR(osc)) {
printk(KERN_WARNING "Skipping twl internal clock init and "
"using bootloader value (unknown osc rate)\n");
return;
}
rate = clk_get_rate(osc);
clk_put(osc);
switch (rate) {
case 19200000:
ctrl = HFCLK_FREQ_19p2_MHZ;
break;
case 26000000:
ctrl = HFCLK_FREQ_26_MHZ;
break;
case 38400000:
ctrl = HFCLK_FREQ_38p4_MHZ;
break;
}
ctrl |= HIGH_PERF_SQ;
e |= unprotect_pm_master();
/* effect->MADC+USB ck en */
e |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, ctrl, R_CFG_BOOT);
e |= protect_pm_master();
if (e < 0)
pr_err("%s: clock init err [%d]\n", DRIVER_NAME, e);
}
/*----------------------------------------------------------------------*/
static void twl_remove(struct i2c_client *client)
{
unsigned i, num_slaves;
if (twl_class_is_4030())
twl4030_exit_irq();
else
twl6030_exit_irq();
num_slaves = twl_get_num_slaves();
for (i = 0; i < num_slaves; i++) {
struct twl_client *twl = &twl_priv->twl_modules[i];
if (twl->client && twl->client != client)
i2c_unregister_device(twl->client);
twl->client = NULL;
}
twl_priv->ready = false;
}
static struct of_dev_auxdata twl_auxdata_lookup[] = {
OF_DEV_AUXDATA("ti,twl4030-gpio", 0, "twl4030-gpio", NULL),
{ /* sentinel */ },
};
/* NOTE: This driver only handles a single twl4030/tps659x0 chip */
static int
twl_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
struct device_node *node = client->dev.of_node;
struct platform_device *pdev;
const struct regmap_config *twl_regmap_config;
int irq_base = 0;
int status;
unsigned i, num_slaves;
if (!node) {
dev_err(&client->dev, "no platform data\n");
return -EINVAL;
}
if (twl_priv) {
dev_dbg(&client->dev, "only one instance of %s allowed\n",
DRIVER_NAME);
return -EBUSY;
}
pdev = platform_device_alloc(DRIVER_NAME, -1);
if (!pdev) {
dev_err(&client->dev, "can't alloc pdev\n");
return -ENOMEM;
}
status = platform_device_add(pdev);
if (status) {
platform_device_put(pdev);
return status;
}
if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) == 0) {
dev_dbg(&client->dev, "can't talk I2C?\n");
status = -EIO;
goto free;
}
twl_priv = devm_kzalloc(&client->dev, sizeof(struct twl_private),
GFP_KERNEL);
if (!twl_priv) {
status = -ENOMEM;
goto free;
}
if ((id->driver_data) & TWL6030_CLASS) {
twl_priv->twl_id = TWL6030_CLASS_ID;
twl_priv->twl_map = &twl6030_map[0];
twl_regmap_config = twl6030_regmap_config;
} else {
twl_priv->twl_id = TWL4030_CLASS_ID;
twl_priv->twl_map = &twl4030_map[0];
twl_regmap_config = twl4030_regmap_config;
}
num_slaves = twl_get_num_slaves();
twl_priv->twl_modules = devm_kcalloc(&client->dev,
num_slaves,
sizeof(struct twl_client),
GFP_KERNEL);
if (!twl_priv->twl_modules) {
status = -ENOMEM;
goto free;
}
for (i = 0; i < num_slaves; i++) {
struct twl_client *twl = &twl_priv->twl_modules[i];
if (i == 0) {
twl->client = client;
} else {
twl->client = i2c_new_dummy_device(client->adapter,
client->addr + i);
if (IS_ERR(twl->client)) {
dev_err(&client->dev,
"can't attach client %d\n", i);
status = PTR_ERR(twl->client);
goto fail;
}
}
twl->regmap = devm_regmap_init_i2c(twl->client,
&twl_regmap_config[i]);
if (IS_ERR(twl->regmap)) {
status = PTR_ERR(twl->regmap);
dev_err(&client->dev,
"Failed to allocate regmap %d, err: %d\n", i,
status);
goto fail;
}
}
twl_priv->ready = true;
/* setup clock framework */
clocks_init(&client->dev);
/* read TWL IDCODE Register */
if (twl_class_is_4030()) {
status = twl_read_idcode_register();
WARN(status < 0, "Error: reading twl_idcode register value\n");
}
/* Maybe init the T2 Interrupt subsystem */
if (client->irq) {
if (twl_class_is_4030()) {
twl4030_init_chip_irq(id->name);
irq_base = twl4030_init_irq(&client->dev, client->irq);
} else {
irq_base = twl6030_init_irq(&client->dev, client->irq);
}
if (irq_base < 0) {
status = irq_base;
goto fail;
}
}
/*
* Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
* Program I2C_SCL_CTRL_PU(bit 0)=0, I2C_SDA_CTRL_PU (bit 2)=0,
* SR_I2C_SCL_CTRL_PU(bit 4)=0 and SR_I2C_SDA_CTRL_PU(bit 6)=0.
*
* Also, always enable SmartReflex bit as that's needed for omaps to
* do anything over I2C4 for voltage scaling even if SmartReflex
* is disabled. Without the SmartReflex bit omap sys_clkreq idle
* signal will never trigger for retention idle.
*/
if (twl_class_is_4030()) {
u8 temp;
twl_i2c_read_u8(TWL4030_MODULE_INTBR, &temp, REG_GPPUPDCTR1);
temp &= ~(SR_I2C_SDA_CTRL_PU | SR_I2C_SCL_CTRL_PU | \
I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU);
twl_i2c_write_u8(TWL4030_MODULE_INTBR, temp, REG_GPPUPDCTR1);
twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
TWL4030_DCDC_GLOBAL_CFG);
temp |= SMARTREFLEX_ENABLE;
twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
TWL4030_DCDC_GLOBAL_CFG);
}
status = of_platform_populate(node, NULL, twl_auxdata_lookup,
&client->dev);
fail:
if (status < 0)
twl_remove(client);
free:
if (status < 0)
platform_device_unregister(pdev);
return status;
}
static int __maybe_unused twl_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
if (client->irq)
disable_irq(client->irq);
return 0;
}
static int __maybe_unused twl_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
if (client->irq)
enable_irq(client->irq);
return 0;
}
static SIMPLE_DEV_PM_OPS(twl_dev_pm_ops, twl_suspend, twl_resume);
static const struct i2c_device_id twl_ids[] = {
{ "twl4030", TWL4030_VAUX2 }, /* "Triton 2" */
{ "twl5030", 0 }, /* T2 updated */
{ "twl5031", TWL5031 }, /* TWL5030 updated */
{ "tps65950", 0 }, /* catalog version of twl5030 */
{ "tps65930", TPS_SUBSET }, /* fewer LDOs and DACs; no charger */
{ "tps65920", TPS_SUBSET }, /* fewer LDOs; no codec or charger */
{ "tps65921", TPS_SUBSET }, /* fewer LDOs; no codec, no LED
and vibrator. Charger in USB module*/
{ "twl6030", TWL6030_CLASS }, /* "Phoenix power chip" */
{ "twl6032", TWL6030_CLASS | TWL6032_SUBCLASS }, /* "Phoenix lite" */
{ /* end of list */ },
};
/* One Client Driver , 4 Clients */
static struct i2c_driver twl_driver = {
.driver.name = DRIVER_NAME,
.driver.pm = &twl_dev_pm_ops,
.id_table = twl_ids,
.probe = twl_probe,
.remove = twl_remove,
};
builtin_i2c_driver(twl_driver);
| linux-master | drivers/mfd/twl-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2022 Richtek Technology Corp.
* Author: ChiYuan Huang <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/regmap.h>
#define RT5120_REG_INTENABLE 0x1D
#define RT5120_REG_INTSTAT 0x1E
#define RT5120_REG_FZCMODE 0x44
#define RT5120_INT_HOTDIE 0
#define RT5120_INT_PWRKEY_REL 5
#define RT5120_INT_PWRKEY_PRESS 6
static const struct regmap_range rt5120_rd_yes_ranges[] = {
regmap_reg_range(0x03, 0x13),
regmap_reg_range(0x1c, 0x20),
regmap_reg_range(0x44, 0x44),
};
static const struct regmap_range rt5120_wr_yes_ranges[] = {
regmap_reg_range(0x06, 0x13),
regmap_reg_range(0x1c, 0x20),
regmap_reg_range(0x44, 0x44),
};
static const struct regmap_access_table rt5120_rd_table = {
.yes_ranges = rt5120_rd_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(rt5120_rd_yes_ranges),
};
static const struct regmap_access_table rt5120_wr_table = {
.yes_ranges = rt5120_wr_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(rt5120_wr_yes_ranges),
};
static const struct regmap_config rt5120_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = RT5120_REG_FZCMODE,
.wr_table = &rt5120_wr_table,
.rd_table = &rt5120_rd_table,
};
static const struct regmap_irq rt5120_irqs[] = {
REGMAP_IRQ_REG_LINE(RT5120_INT_HOTDIE, 8),
REGMAP_IRQ_REG_LINE(RT5120_INT_PWRKEY_REL, 8),
REGMAP_IRQ_REG_LINE(RT5120_INT_PWRKEY_PRESS, 8),
};
static const struct regmap_irq_chip rt5120_irq_chip = {
.name = "rt5120-pmic",
.status_base = RT5120_REG_INTSTAT,
.unmask_base = RT5120_REG_INTENABLE,
.ack_base = RT5120_REG_INTSTAT,
.use_ack = true,
.num_regs = 1,
.irqs = rt5120_irqs,
.num_irqs = ARRAY_SIZE(rt5120_irqs),
};
static const struct resource rt5120_regulator_resources[] = {
DEFINE_RES_IRQ(RT5120_INT_HOTDIE),
};
static const struct resource rt5120_pwrkey_resources[] = {
DEFINE_RES_IRQ_NAMED(RT5120_INT_PWRKEY_PRESS, "pwrkey-press"),
DEFINE_RES_IRQ_NAMED(RT5120_INT_PWRKEY_REL, "pwrkey-release"),
};
static const struct mfd_cell rt5120_devs[] = {
MFD_CELL_RES("rt5120-regulator", rt5120_regulator_resources),
MFD_CELL_OF("rt5120-pwrkey", rt5120_pwrkey_resources, NULL, 0, 0, "richtek,rt5120-pwrkey"),
};
static int rt5120_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct regmap *regmap;
struct regmap_irq_chip_data *irq_data;
int ret;
regmap = devm_regmap_init_i2c(i2c, &rt5120_regmap_config);
if (IS_ERR(regmap))
return dev_err_probe(dev, PTR_ERR(regmap),
"Failed to init regmap\n");
ret = devm_regmap_add_irq_chip(dev, regmap, i2c->irq, IRQF_ONESHOT, 0,
&rt5120_irq_chip, &irq_data);
if (ret)
return dev_err_probe(dev, ret, "Failed to add IRQ chip\n");
return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, rt5120_devs,
ARRAY_SIZE(rt5120_devs), NULL, 0,
regmap_irq_get_domain(irq_data));
}
static const struct of_device_id rt5120_device_match_table[] = {
{ .compatible = "richtek,rt5120" },
{}
};
MODULE_DEVICE_TABLE(of, rt5120_device_match_table);
static struct i2c_driver rt5120_driver = {
.driver = {
.name = "rt5120",
.of_match_table = rt5120_device_match_table,
},
.probe = rt5120_probe,
};
module_i2c_driver(rt5120_driver);
MODULE_AUTHOR("ChiYuan Huang <[email protected]>");
MODULE_DESCRIPTION("Richtek RT5120 I2C driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/rt5120.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2022 Richtek Technology Corp.
*
* Author: ChiYuan Huang <[email protected]>
*/
#include <linux/bits.h>
#include <linux/bitfield.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include "mt6370.h"
#define MT6370_REG_DEV_INFO 0x100
#define MT6370_REG_CHG_IRQ1 0x1C0
#define MT6370_REG_CHG_MASK1 0x1E0
#define MT6370_REG_MAXADDR 0x1FF
#define MT6370_VENID_MASK GENMASK(7, 4)
#define MT6370_NUM_IRQREGS 16
#define MT6370_USBC_I2CADDR 0x4E
#define MT6370_MAX_ADDRLEN 2
#define MT6370_VENID_RT5081 0x8
#define MT6370_VENID_RT5081A 0xA
#define MT6370_VENID_MT6370 0xE
#define MT6370_VENID_MT6371 0xF
#define MT6370_VENID_MT6372P 0x9
#define MT6370_VENID_MT6372CP 0xB
static const struct regmap_irq mt6370_irqs[] = {
REGMAP_IRQ_REG_LINE(MT6370_IRQ_DIRCHGON, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_TREG, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_AICR, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_MIVR, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_PWR_RDY, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_FL_CHG_VINOVP, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_VSYSUV, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_VSYSOV, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_VBATOV, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_VINOVPCHG, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_TS_BAT_COLD, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_TS_BAT_COOL, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_TS_BAT_WARM, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_TS_BAT_HOT, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_TS_STATC, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_FAULT, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_STATC, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_TMR, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_BATABS, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_ADPBAD, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_RVP, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_TSHUTDOWN, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_IINMEAS, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_ICCMEAS, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHGDET_DONE, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_WDTMR, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_SSFINISH, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_RECHG, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_TERM, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_IEOC, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_ADC_DONE, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_PUMPX_DONE, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_BST_BATUV, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_BST_MIDOV, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_BST_OLP, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_ATTACH, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_DETACH, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_HVDCP_STPDONE, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_HVDCP_VBUSDET_DONE, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_HVDCP_DET, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHGDET, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_DCDT, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_DIRCHG_VGOK, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_DIRCHG_WDTMR, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_DIRCHG_UC, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_DIRCHG_OC, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_DIRCHG_OV, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_OVPCTRL_SWON, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_OVPCTRL_UVP_D, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_OVPCTRL_UVP, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_OVPCTRL_OVP_D, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_OVPCTRL_OVP, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED_STRBPIN, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED_TORPIN, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED_TX, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED_LVF, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED2_SHORT, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED1_SHORT, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED2_STRB, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED1_STRB, 8),
REGMAP_IRQ_REG_LINE(mT6370_IRQ_FLED2_STRB_TO, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED1_STRB_TO, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED2_TOR, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_FLED1_TOR, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_OTP, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_VDDA_OVP, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_VDDA_UV, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_LDO_OC, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_BLED_OCP, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_BLED_OVP, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_DSV_VNEG_OCP, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_DSV_VPOS_OCP, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_DSV_BST_OCP, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_DSV_VNEG_SCP, 8),
REGMAP_IRQ_REG_LINE(MT6370_IRQ_DSV_VPOS_SCP, 8),
};
static const struct regmap_irq_chip mt6370_irq_chip = {
.name = "mt6370-irqs",
.status_base = MT6370_REG_CHG_IRQ1,
.mask_base = MT6370_REG_CHG_MASK1,
.num_regs = MT6370_NUM_IRQREGS,
.irqs = mt6370_irqs,
.num_irqs = ARRAY_SIZE(mt6370_irqs),
};
static const struct resource mt6370_regulator_irqs[] = {
DEFINE_RES_IRQ_NAMED(MT6370_IRQ_DSV_VPOS_SCP, "db_vpos_scp"),
DEFINE_RES_IRQ_NAMED(MT6370_IRQ_DSV_VNEG_SCP, "db_vneg_scp"),
DEFINE_RES_IRQ_NAMED(MT6370_IRQ_DSV_BST_OCP, "db_vbst_ocp"),
DEFINE_RES_IRQ_NAMED(MT6370_IRQ_DSV_VPOS_OCP, "db_vpos_ocp"),
DEFINE_RES_IRQ_NAMED(MT6370_IRQ_DSV_VNEG_OCP, "db_vneg_ocp"),
DEFINE_RES_IRQ_NAMED(MT6370_IRQ_LDO_OC, "ldo_oc"),
};
static const struct mfd_cell mt6370_devices[] = {
MFD_CELL_OF("mt6370-adc",
NULL, NULL, 0, 0, "mediatek,mt6370-adc"),
MFD_CELL_OF("mt6370-charger",
NULL, NULL, 0, 0, "mediatek,mt6370-charger"),
MFD_CELL_OF("mt6370-flashlight",
NULL, NULL, 0, 0, "mediatek,mt6370-flashlight"),
MFD_CELL_OF("mt6370-indicator",
NULL, NULL, 0, 0, "mediatek,mt6370-indicator"),
MFD_CELL_OF("mt6370-tcpc",
NULL, NULL, 0, 0, "mediatek,mt6370-tcpc"),
MFD_CELL_RES("mt6370-regulator", mt6370_regulator_irqs),
};
static const struct mfd_cell mt6370_exclusive_devices[] = {
MFD_CELL_OF("mt6370-backlight",
NULL, NULL, 0, 0, "mediatek,mt6370-backlight"),
};
static const struct mfd_cell mt6372_exclusive_devices[] = {
MFD_CELL_OF("mt6370-backlight",
NULL, NULL, 0, 0, "mediatek,mt6372-backlight"),
};
static int mt6370_check_vendor_info(struct device *dev, struct regmap *rmap,
int *vid)
{
unsigned int devinfo;
int ret;
ret = regmap_read(rmap, MT6370_REG_DEV_INFO, &devinfo);
if (ret)
return ret;
*vid = FIELD_GET(MT6370_VENID_MASK, devinfo);
switch (*vid) {
case MT6370_VENID_RT5081:
case MT6370_VENID_RT5081A:
case MT6370_VENID_MT6370:
case MT6370_VENID_MT6371:
case MT6370_VENID_MT6372P:
case MT6370_VENID_MT6372CP:
return 0;
default:
dev_err(dev, "Unknown Vendor ID 0x%02x\n", devinfo);
return -ENODEV;
}
}
static int mt6370_regmap_read(void *context, const void *reg_buf,
size_t reg_size, void *val_buf, size_t val_size)
{
struct mt6370_info *info = context;
const u8 *u8_buf = reg_buf;
u8 bank_idx, bank_addr;
int ret;
bank_idx = u8_buf[0];
bank_addr = u8_buf[1];
ret = i2c_smbus_read_i2c_block_data(info->i2c[bank_idx], bank_addr,
val_size, val_buf);
if (ret < 0)
return ret;
if (ret != val_size)
return -EIO;
return 0;
}
static int mt6370_regmap_write(void *context, const void *data, size_t count)
{
struct mt6370_info *info = context;
const u8 *u8_buf = data;
u8 bank_idx, bank_addr;
int len = count - MT6370_MAX_ADDRLEN;
bank_idx = u8_buf[0];
bank_addr = u8_buf[1];
return i2c_smbus_write_i2c_block_data(info->i2c[bank_idx], bank_addr,
len, data + MT6370_MAX_ADDRLEN);
}
static const struct regmap_bus mt6370_regmap_bus = {
.read = mt6370_regmap_read,
.write = mt6370_regmap_write,
};
static const struct regmap_config mt6370_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.max_register = MT6370_REG_MAXADDR,
};
static int mt6370_probe(struct i2c_client *i2c)
{
struct mt6370_info *info;
struct i2c_client *usbc_i2c;
struct regmap *regmap;
struct device *dev = &i2c->dev;
int ret, vid;
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
usbc_i2c = devm_i2c_new_dummy_device(dev, i2c->adapter,
MT6370_USBC_I2CADDR);
if (IS_ERR(usbc_i2c))
return dev_err_probe(dev, PTR_ERR(usbc_i2c),
"Failed to register USBC I2C client\n");
/* Assign I2C client for PMU and TypeC */
info->i2c[MT6370_PMU_I2C] = i2c;
info->i2c[MT6370_USBC_I2C] = usbc_i2c;
regmap = devm_regmap_init(dev, &mt6370_regmap_bus,
info, &mt6370_regmap_config);
if (IS_ERR(regmap))
return dev_err_probe(dev, PTR_ERR(regmap),
"Failed to init regmap\n");
ret = mt6370_check_vendor_info(dev, regmap, &vid);
if (ret)
return dev_err_probe(dev, ret, "Failed to check vendor info\n");
ret = devm_regmap_add_irq_chip(dev, regmap, i2c->irq,
IRQF_ONESHOT, -1, &mt6370_irq_chip,
&info->irq_data);
if (ret)
return dev_err_probe(dev, ret, "Failed to add irq chip\n");
switch (vid) {
case MT6370_VENID_MT6372P:
case MT6370_VENID_MT6372CP:
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO,
mt6372_exclusive_devices,
ARRAY_SIZE(mt6372_exclusive_devices),
NULL, 0,
regmap_irq_get_domain(info->irq_data));
break;
default:
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO,
mt6370_exclusive_devices,
ARRAY_SIZE(mt6370_exclusive_devices),
NULL, 0,
regmap_irq_get_domain(info->irq_data));
break;
}
if (ret)
return dev_err_probe(dev, ret, "Failed to add the exclusive devices\n");
return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO,
mt6370_devices, ARRAY_SIZE(mt6370_devices),
NULL, 0,
regmap_irq_get_domain(info->irq_data));
}
static const struct of_device_id mt6370_match_table[] = {
{ .compatible = "mediatek,mt6370" },
{}
};
MODULE_DEVICE_TABLE(of, mt6370_match_table);
static struct i2c_driver mt6370_driver = {
.driver = {
.name = "mt6370",
.of_match_table = mt6370_match_table,
},
.probe = mt6370_probe,
};
module_i2c_driver(mt6370_driver);
MODULE_AUTHOR("ChiYuan Huang <[email protected]>");
MODULE_DESCRIPTION("MediaTek MT6370 SubPMIC Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/mt6370.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2007-2010 ST-Ericsson
* Register access functions for the ABX500 Mixed Signal IC family.
* Author: Mattias Wallin <[email protected]>
*/
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/mfd/abx500.h>
static LIST_HEAD(abx500_list);
struct abx500_device_entry {
struct list_head list;
struct abx500_ops ops;
struct device *dev;
};
static void lookup_ops(struct device *dev, struct abx500_ops **ops)
{
struct abx500_device_entry *dev_entry;
*ops = NULL;
list_for_each_entry(dev_entry, &abx500_list, list) {
if (dev_entry->dev == dev) {
*ops = &dev_entry->ops;
return;
}
}
}
int abx500_register_ops(struct device *dev, struct abx500_ops *ops)
{
struct abx500_device_entry *dev_entry;
dev_entry = devm_kzalloc(dev, sizeof(*dev_entry), GFP_KERNEL);
if (!dev_entry)
return -ENOMEM;
dev_entry->dev = dev;
memcpy(&dev_entry->ops, ops, sizeof(*ops));
list_add_tail(&dev_entry->list, &abx500_list);
return 0;
}
EXPORT_SYMBOL(abx500_register_ops);
void abx500_remove_ops(struct device *dev)
{
struct abx500_device_entry *dev_entry, *tmp;
list_for_each_entry_safe(dev_entry, tmp, &abx500_list, list)
if (dev_entry->dev == dev)
list_del(&dev_entry->list);
}
EXPORT_SYMBOL(abx500_remove_ops);
int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,
u8 value)
{
struct abx500_ops *ops;
lookup_ops(dev->parent, &ops);
if (ops && ops->set_register)
return ops->set_register(dev, bank, reg, value);
else
return -ENOTSUPP;
}
EXPORT_SYMBOL(abx500_set_register_interruptible);
int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg,
u8 *value)
{
struct abx500_ops *ops;
lookup_ops(dev->parent, &ops);
if (ops && ops->get_register)
return ops->get_register(dev, bank, reg, value);
else
return -ENOTSUPP;
}
EXPORT_SYMBOL(abx500_get_register_interruptible);
int abx500_get_register_page_interruptible(struct device *dev, u8 bank,
u8 first_reg, u8 *regvals, u8 numregs)
{
struct abx500_ops *ops;
lookup_ops(dev->parent, &ops);
if (ops && ops->get_register_page)
return ops->get_register_page(dev, bank,
first_reg, regvals, numregs);
else
return -ENOTSUPP;
}
EXPORT_SYMBOL(abx500_get_register_page_interruptible);
int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank,
u8 reg, u8 bitmask, u8 bitvalues)
{
struct abx500_ops *ops;
lookup_ops(dev->parent, &ops);
if (ops && ops->mask_and_set_register)
return ops->mask_and_set_register(dev, bank,
reg, bitmask, bitvalues);
else
return -ENOTSUPP;
}
EXPORT_SYMBOL(abx500_mask_and_set_register_interruptible);
int abx500_get_chip_id(struct device *dev)
{
struct abx500_ops *ops;
lookup_ops(dev->parent, &ops);
if (ops && ops->get_chip_id)
return ops->get_chip_id(dev);
else
return -ENOTSUPP;
}
EXPORT_SYMBOL(abx500_get_chip_id);
int abx500_event_registers_startup_state_get(struct device *dev, u8 *event)
{
struct abx500_ops *ops;
lookup_ops(dev->parent, &ops);
if (ops && ops->event_registers_startup_state_get)
return ops->event_registers_startup_state_get(dev, event);
else
return -ENOTSUPP;
}
EXPORT_SYMBOL(abx500_event_registers_startup_state_get);
int abx500_startup_irq_enabled(struct device *dev, unsigned int irq)
{
struct abx500_ops *ops;
lookup_ops(dev->parent, &ops);
if (ops && ops->startup_irq_enabled)
return ops->startup_irq_enabled(dev, irq);
else
return -ENOTSUPP;
}
EXPORT_SYMBOL(abx500_startup_irq_enabled);
| linux-master | drivers/mfd/abx500-core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* DA9150 Core MFD Driver
*
* Copyright (c) 2014 Dialog Semiconductor
*
* Author: Adam Thomson <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mfd/da9150/core.h>
#include <linux/mfd/da9150/registers.h>
/* Raw device access, used for QIF */
static int da9150_i2c_read_device(struct i2c_client *client, u8 addr, int count,
u8 *buf)
{
struct i2c_msg xfer;
int ret;
/*
* Read is split into two transfers as device expects STOP/START rather
* than repeated start to carry out this kind of access.
*/
/* Write address */
xfer.addr = client->addr;
xfer.flags = 0;
xfer.len = 1;
xfer.buf = &addr;
ret = i2c_transfer(client->adapter, &xfer, 1);
if (ret != 1) {
if (ret < 0)
return ret;
else
return -EIO;
}
/* Read data */
xfer.addr = client->addr;
xfer.flags = I2C_M_RD;
xfer.len = count;
xfer.buf = buf;
ret = i2c_transfer(client->adapter, &xfer, 1);
if (ret == 1)
return 0;
else if (ret < 0)
return ret;
else
return -EIO;
}
static int da9150_i2c_write_device(struct i2c_client *client, u8 addr,
int count, const u8 *buf)
{
struct i2c_msg xfer;
u8 *reg_data;
int ret;
reg_data = kzalloc(1 + count, GFP_KERNEL);
if (!reg_data)
return -ENOMEM;
reg_data[0] = addr;
memcpy(®_data[1], buf, count);
/* Write address & data */
xfer.addr = client->addr;
xfer.flags = 0;
xfer.len = 1 + count;
xfer.buf = reg_data;
ret = i2c_transfer(client->adapter, &xfer, 1);
kfree(reg_data);
if (ret == 1)
return 0;
else if (ret < 0)
return ret;
else
return -EIO;
}
static bool da9150_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case DA9150_PAGE_CON:
case DA9150_STATUS_A:
case DA9150_STATUS_B:
case DA9150_STATUS_C:
case DA9150_STATUS_D:
case DA9150_STATUS_E:
case DA9150_STATUS_F:
case DA9150_STATUS_G:
case DA9150_STATUS_H:
case DA9150_STATUS_I:
case DA9150_STATUS_J:
case DA9150_STATUS_K:
case DA9150_STATUS_L:
case DA9150_STATUS_N:
case DA9150_FAULT_LOG_A:
case DA9150_FAULT_LOG_B:
case DA9150_EVENT_E:
case DA9150_EVENT_F:
case DA9150_EVENT_G:
case DA9150_EVENT_H:
case DA9150_CONTROL_B:
case DA9150_CONTROL_C:
case DA9150_GPADC_MAN:
case DA9150_GPADC_RES_A:
case DA9150_GPADC_RES_B:
case DA9150_ADETVB_CFG_C:
case DA9150_ADETD_STAT:
case DA9150_ADET_CMPSTAT:
case DA9150_ADET_CTRL_A:
case DA9150_PPR_TCTR_B:
case DA9150_COREBTLD_STAT_A:
case DA9150_CORE_DATA_A:
case DA9150_CORE_DATA_B:
case DA9150_CORE_DATA_C:
case DA9150_CORE_DATA_D:
case DA9150_CORE2WIRE_STAT_A:
case DA9150_FW_CTRL_C:
case DA9150_FG_CTRL_B:
case DA9150_FW_CTRL_B:
case DA9150_GPADC_CMAN:
case DA9150_GPADC_CRES_A:
case DA9150_GPADC_CRES_B:
case DA9150_CC_ICHG_RES_A:
case DA9150_CC_ICHG_RES_B:
case DA9150_CC_IAVG_RES_A:
case DA9150_CC_IAVG_RES_B:
case DA9150_TAUX_CTRL_A:
case DA9150_TAUX_VALUE_H:
case DA9150_TAUX_VALUE_L:
case DA9150_TBAT_RES_A:
case DA9150_TBAT_RES_B:
return true;
default:
return false;
}
}
static const struct regmap_range_cfg da9150_range_cfg[] = {
{
.range_min = DA9150_PAGE_CON,
.range_max = DA9150_TBAT_RES_B,
.selector_reg = DA9150_PAGE_CON,
.selector_mask = DA9150_I2C_PAGE_MASK,
.selector_shift = DA9150_I2C_PAGE_SHIFT,
.window_start = 0,
.window_len = 256,
},
};
static const struct regmap_config da9150_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.ranges = da9150_range_cfg,
.num_ranges = ARRAY_SIZE(da9150_range_cfg),
.max_register = DA9150_TBAT_RES_B,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = da9150_volatile_reg,
};
void da9150_read_qif(struct da9150 *da9150, u8 addr, int count, u8 *buf)
{
int ret;
ret = da9150_i2c_read_device(da9150->core_qif, addr, count, buf);
if (ret < 0)
dev_err(da9150->dev, "Failed to read from QIF 0x%x: %d\n",
addr, ret);
}
EXPORT_SYMBOL_GPL(da9150_read_qif);
void da9150_write_qif(struct da9150 *da9150, u8 addr, int count, const u8 *buf)
{
int ret;
ret = da9150_i2c_write_device(da9150->core_qif, addr, count, buf);
if (ret < 0)
dev_err(da9150->dev, "Failed to write to QIF 0x%x: %d\n",
addr, ret);
}
EXPORT_SYMBOL_GPL(da9150_write_qif);
u8 da9150_reg_read(struct da9150 *da9150, u16 reg)
{
int val, ret;
ret = regmap_read(da9150->regmap, reg, &val);
if (ret)
dev_err(da9150->dev, "Failed to read from reg 0x%x: %d\n",
reg, ret);
return (u8) val;
}
EXPORT_SYMBOL_GPL(da9150_reg_read);
void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val)
{
int ret;
ret = regmap_write(da9150->regmap, reg, val);
if (ret)
dev_err(da9150->dev, "Failed to write to reg 0x%x: %d\n",
reg, ret);
}
EXPORT_SYMBOL_GPL(da9150_reg_write);
void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val)
{
int ret;
ret = regmap_update_bits(da9150->regmap, reg, mask, val);
if (ret)
dev_err(da9150->dev, "Failed to set bits in reg 0x%x: %d\n",
reg, ret);
}
EXPORT_SYMBOL_GPL(da9150_set_bits);
void da9150_bulk_read(struct da9150 *da9150, u16 reg, int count, u8 *buf)
{
int ret;
ret = regmap_bulk_read(da9150->regmap, reg, buf, count);
if (ret)
dev_err(da9150->dev, "Failed to bulk read from reg 0x%x: %d\n",
reg, ret);
}
EXPORT_SYMBOL_GPL(da9150_bulk_read);
void da9150_bulk_write(struct da9150 *da9150, u16 reg, int count, const u8 *buf)
{
int ret;
ret = regmap_raw_write(da9150->regmap, reg, buf, count);
if (ret)
dev_err(da9150->dev, "Failed to bulk write to reg 0x%x %d\n",
reg, ret);
}
EXPORT_SYMBOL_GPL(da9150_bulk_write);
static const struct regmap_irq da9150_irqs[] = {
[DA9150_IRQ_VBUS] = {
.reg_offset = 0,
.mask = DA9150_E_VBUS_MASK,
},
[DA9150_IRQ_CHG] = {
.reg_offset = 0,
.mask = DA9150_E_CHG_MASK,
},
[DA9150_IRQ_TCLASS] = {
.reg_offset = 0,
.mask = DA9150_E_TCLASS_MASK,
},
[DA9150_IRQ_TJUNC] = {
.reg_offset = 0,
.mask = DA9150_E_TJUNC_MASK,
},
[DA9150_IRQ_VFAULT] = {
.reg_offset = 0,
.mask = DA9150_E_VFAULT_MASK,
},
[DA9150_IRQ_CONF] = {
.reg_offset = 1,
.mask = DA9150_E_CONF_MASK,
},
[DA9150_IRQ_DAT] = {
.reg_offset = 1,
.mask = DA9150_E_DAT_MASK,
},
[DA9150_IRQ_DTYPE] = {
.reg_offset = 1,
.mask = DA9150_E_DTYPE_MASK,
},
[DA9150_IRQ_ID] = {
.reg_offset = 1,
.mask = DA9150_E_ID_MASK,
},
[DA9150_IRQ_ADP] = {
.reg_offset = 1,
.mask = DA9150_E_ADP_MASK,
},
[DA9150_IRQ_SESS_END] = {
.reg_offset = 1,
.mask = DA9150_E_SESS_END_MASK,
},
[DA9150_IRQ_SESS_VLD] = {
.reg_offset = 1,
.mask = DA9150_E_SESS_VLD_MASK,
},
[DA9150_IRQ_FG] = {
.reg_offset = 2,
.mask = DA9150_E_FG_MASK,
},
[DA9150_IRQ_GP] = {
.reg_offset = 2,
.mask = DA9150_E_GP_MASK,
},
[DA9150_IRQ_TBAT] = {
.reg_offset = 2,
.mask = DA9150_E_TBAT_MASK,
},
[DA9150_IRQ_GPIOA] = {
.reg_offset = 2,
.mask = DA9150_E_GPIOA_MASK,
},
[DA9150_IRQ_GPIOB] = {
.reg_offset = 2,
.mask = DA9150_E_GPIOB_MASK,
},
[DA9150_IRQ_GPIOC] = {
.reg_offset = 2,
.mask = DA9150_E_GPIOC_MASK,
},
[DA9150_IRQ_GPIOD] = {
.reg_offset = 2,
.mask = DA9150_E_GPIOD_MASK,
},
[DA9150_IRQ_GPADC] = {
.reg_offset = 2,
.mask = DA9150_E_GPADC_MASK,
},
[DA9150_IRQ_WKUP] = {
.reg_offset = 3,
.mask = DA9150_E_WKUP_MASK,
},
};
static const struct regmap_irq_chip da9150_regmap_irq_chip = {
.name = "da9150_irq",
.status_base = DA9150_EVENT_E,
.mask_base = DA9150_IRQ_MASK_E,
.ack_base = DA9150_EVENT_E,
.num_regs = DA9150_NUM_IRQ_REGS,
.irqs = da9150_irqs,
.num_irqs = ARRAY_SIZE(da9150_irqs),
};
static const struct resource da9150_gpadc_resources[] = {
DEFINE_RES_IRQ_NAMED(DA9150_IRQ_GPADC, "GPADC"),
};
static const struct resource da9150_charger_resources[] = {
DEFINE_RES_IRQ_NAMED(DA9150_IRQ_CHG, "CHG_STATUS"),
DEFINE_RES_IRQ_NAMED(DA9150_IRQ_TJUNC, "CHG_TJUNC"),
DEFINE_RES_IRQ_NAMED(DA9150_IRQ_VFAULT, "CHG_VFAULT"),
DEFINE_RES_IRQ_NAMED(DA9150_IRQ_VBUS, "CHG_VBUS"),
};
static const struct resource da9150_fg_resources[] = {
DEFINE_RES_IRQ_NAMED(DA9150_IRQ_FG, "FG"),
};
enum da9150_dev_idx {
DA9150_GPADC_IDX = 0,
DA9150_CHARGER_IDX,
DA9150_FG_IDX,
};
static struct mfd_cell da9150_devs[] = {
[DA9150_GPADC_IDX] = {
.name = "da9150-gpadc",
.of_compatible = "dlg,da9150-gpadc",
.resources = da9150_gpadc_resources,
.num_resources = ARRAY_SIZE(da9150_gpadc_resources),
},
[DA9150_CHARGER_IDX] = {
.name = "da9150-charger",
.of_compatible = "dlg,da9150-charger",
.resources = da9150_charger_resources,
.num_resources = ARRAY_SIZE(da9150_charger_resources),
},
[DA9150_FG_IDX] = {
.name = "da9150-fuel-gauge",
.of_compatible = "dlg,da9150-fuel-gauge",
.resources = da9150_fg_resources,
.num_resources = ARRAY_SIZE(da9150_fg_resources),
},
};
static int da9150_probe(struct i2c_client *client)
{
struct da9150 *da9150;
struct da9150_pdata *pdata = dev_get_platdata(&client->dev);
int qif_addr;
int ret;
da9150 = devm_kzalloc(&client->dev, sizeof(*da9150), GFP_KERNEL);
if (!da9150)
return -ENOMEM;
da9150->dev = &client->dev;
da9150->irq = client->irq;
i2c_set_clientdata(client, da9150);
da9150->regmap = devm_regmap_init_i2c(client, &da9150_regmap_config);
if (IS_ERR(da9150->regmap)) {
ret = PTR_ERR(da9150->regmap);
dev_err(da9150->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
/* Setup secondary I2C interface for QIF access */
qif_addr = da9150_reg_read(da9150, DA9150_CORE2WIRE_CTRL_A);
qif_addr = (qif_addr & DA9150_CORE_BASE_ADDR_MASK) >> 1;
qif_addr |= DA9150_QIF_I2C_ADDR_LSB;
da9150->core_qif = i2c_new_dummy_device(client->adapter, qif_addr);
if (IS_ERR(da9150->core_qif)) {
dev_err(da9150->dev, "Failed to attach QIF client\n");
return PTR_ERR(da9150->core_qif);
}
i2c_set_clientdata(da9150->core_qif, da9150);
if (pdata) {
da9150->irq_base = pdata->irq_base;
da9150_devs[DA9150_FG_IDX].platform_data = pdata->fg_pdata;
da9150_devs[DA9150_FG_IDX].pdata_size =
sizeof(struct da9150_fg_pdata);
} else {
da9150->irq_base = -1;
}
ret = regmap_add_irq_chip(da9150->regmap, da9150->irq,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
da9150->irq_base, &da9150_regmap_irq_chip,
&da9150->regmap_irq_data);
if (ret) {
dev_err(da9150->dev, "Failed to add regmap irq chip: %d\n",
ret);
goto regmap_irq_fail;
}
da9150->irq_base = regmap_irq_chip_get_base(da9150->regmap_irq_data);
enable_irq_wake(da9150->irq);
ret = mfd_add_devices(da9150->dev, -1, da9150_devs,
ARRAY_SIZE(da9150_devs), NULL,
da9150->irq_base, NULL);
if (ret) {
dev_err(da9150->dev, "Failed to add child devices: %d\n", ret);
goto mfd_fail;
}
return 0;
mfd_fail:
regmap_del_irq_chip(da9150->irq, da9150->regmap_irq_data);
regmap_irq_fail:
i2c_unregister_device(da9150->core_qif);
return ret;
}
static void da9150_remove(struct i2c_client *client)
{
struct da9150 *da9150 = i2c_get_clientdata(client);
regmap_del_irq_chip(da9150->irq, da9150->regmap_irq_data);
mfd_remove_devices(da9150->dev);
i2c_unregister_device(da9150->core_qif);
}
static void da9150_shutdown(struct i2c_client *client)
{
struct da9150 *da9150 = i2c_get_clientdata(client);
/* Make sure we have a wakup source for the device */
da9150_set_bits(da9150, DA9150_CONFIG_D,
DA9150_WKUP_PM_EN_MASK,
DA9150_WKUP_PM_EN_MASK);
/* Set device to DISABLED mode */
da9150_set_bits(da9150, DA9150_CONTROL_C,
DA9150_DISABLE_MASK, DA9150_DISABLE_MASK);
}
static const struct i2c_device_id da9150_i2c_id[] = {
{ "da9150", },
{ }
};
MODULE_DEVICE_TABLE(i2c, da9150_i2c_id);
static const struct of_device_id da9150_of_match[] = {
{ .compatible = "dlg,da9150", },
{ }
};
MODULE_DEVICE_TABLE(of, da9150_of_match);
static struct i2c_driver da9150_driver = {
.driver = {
.name = "da9150",
.of_match_table = da9150_of_match,
},
.probe = da9150_probe,
.remove = da9150_remove,
.shutdown = da9150_shutdown,
.id_table = da9150_i2c_id,
};
module_i2c_driver(da9150_driver);
MODULE_DESCRIPTION("MFD Core Driver for DA9150");
MODULE_AUTHOR("Adam Thomson <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/da9150-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* drivers/mfd/si476x-i2c.c -- Core device driver for si476x MFD
* device
*
* Copyright (C) 2012 Innovative Converged Devices(ICD)
* Copyright (C) 2013 Andrey Smirnov
*
* Author: Andrey Smirnov <[email protected]>
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/mfd/si476x-core.h>
#define SI476X_MAX_IO_ERRORS 10
#define SI476X_DRIVER_RDS_FIFO_DEPTH 128
/**
* si476x_core_config_pinmux() - pin function configuration function
*
* @core: Core device structure
*
* Configure the functions of the pins of the radio chip.
*
* The function returns zero in case of succes or negative error code
* otherwise.
*/
static int si476x_core_config_pinmux(struct si476x_core *core)
{
int err;
dev_dbg(&core->client->dev, "Configuring pinmux\n");
err = si476x_core_cmd_dig_audio_pin_cfg(core,
core->pinmux.dclk,
core->pinmux.dfs,
core->pinmux.dout,
core->pinmux.xout);
if (err < 0) {
dev_err(&core->client->dev,
"Failed to configure digital audio pins(err = %d)\n",
err);
return err;
}
err = si476x_core_cmd_zif_pin_cfg(core,
core->pinmux.iqclk,
core->pinmux.iqfs,
core->pinmux.iout,
core->pinmux.qout);
if (err < 0) {
dev_err(&core->client->dev,
"Failed to configure ZIF pins(err = %d)\n",
err);
return err;
}
err = si476x_core_cmd_ic_link_gpo_ctl_pin_cfg(core,
core->pinmux.icin,
core->pinmux.icip,
core->pinmux.icon,
core->pinmux.icop);
if (err < 0) {
dev_err(&core->client->dev,
"Failed to configure IC-Link/GPO pins(err = %d)\n",
err);
return err;
}
err = si476x_core_cmd_ana_audio_pin_cfg(core,
core->pinmux.lrout);
if (err < 0) {
dev_err(&core->client->dev,
"Failed to configure analog audio pins(err = %d)\n",
err);
return err;
}
err = si476x_core_cmd_intb_pin_cfg(core,
core->pinmux.intb,
core->pinmux.a1);
if (err < 0) {
dev_err(&core->client->dev,
"Failed to configure interrupt pins(err = %d)\n",
err);
return err;
}
return 0;
}
static inline void si476x_core_schedule_polling_work(struct si476x_core *core)
{
schedule_delayed_work(&core->status_monitor,
usecs_to_jiffies(SI476X_STATUS_POLL_US));
}
/**
* si476x_core_start() - early chip startup function
* @core: Core device structure
* @soft: When set, this flag forces "soft" startup, where "soft"
* power down is the one done by sending appropriate command instead
* of using reset pin of the tuner
*
* Perform required startup sequence to correctly power
* up the chip and perform initial configuration. It does the
* following sequence of actions:
* 1. Claims and enables the power supplies VD and VIO1 required
* for I2C interface of the chip operation.
* 2. Waits for 100us, pulls the reset line up, enables irq,
* waits for another 100us as it is specified by the
* datasheet.
* 3. Sends 'POWER_UP' command to the device with all provided
* information about power-up parameters.
* 4. Configures, pin multiplexor, disables digital audio and
* configures interrupt sources.
*
* The function returns zero in case of succes or negative error code
* otherwise.
*/
int si476x_core_start(struct si476x_core *core, bool soft)
{
struct i2c_client *client = core->client;
int err;
if (!soft) {
if (gpio_is_valid(core->gpio_reset))
gpio_set_value_cansleep(core->gpio_reset, 1);
if (client->irq)
enable_irq(client->irq);
udelay(100);
if (!client->irq) {
atomic_set(&core->is_alive, 1);
si476x_core_schedule_polling_work(core);
}
} else {
if (client->irq)
enable_irq(client->irq);
else {
atomic_set(&core->is_alive, 1);
si476x_core_schedule_polling_work(core);
}
}
err = si476x_core_cmd_power_up(core,
&core->power_up_parameters);
if (err < 0) {
dev_err(&core->client->dev,
"Power up failure(err = %d)\n",
err);
goto disable_irq;
}
if (client->irq)
atomic_set(&core->is_alive, 1);
err = si476x_core_config_pinmux(core);
if (err < 0) {
dev_err(&core->client->dev,
"Failed to configure pinmux(err = %d)\n",
err);
goto disable_irq;
}
if (client->irq) {
err = regmap_write(core->regmap,
SI476X_PROP_INT_CTL_ENABLE,
SI476X_RDSIEN |
SI476X_STCIEN |
SI476X_CTSIEN);
if (err < 0) {
dev_err(&core->client->dev,
"Failed to configure interrupt sources"
"(err = %d)\n", err);
goto disable_irq;
}
}
return 0;
disable_irq:
if (err == -ENODEV)
atomic_set(&core->is_alive, 0);
if (client->irq)
disable_irq(client->irq);
else
cancel_delayed_work_sync(&core->status_monitor);
if (gpio_is_valid(core->gpio_reset))
gpio_set_value_cansleep(core->gpio_reset, 0);
return err;
}
EXPORT_SYMBOL_GPL(si476x_core_start);
/**
* si476x_core_stop() - chip power-down function
* @core: Core device structure
* @soft: When set, function sends a POWER_DOWN command instead of
* bringing reset line low
*
* Power down the chip by performing following actions:
* 1. Disable IRQ or stop the polling worker
* 2. Send the POWER_DOWN command if the power down is soft or bring
* reset line low if not.
*
* The function returns zero in case of succes or negative error code
* otherwise.
*/
int si476x_core_stop(struct si476x_core *core, bool soft)
{
int err = 0;
atomic_set(&core->is_alive, 0);
if (soft) {
/* TODO: This probably shoud be a configurable option,
* so it is possible to have the chips keep their
* oscillators running
*/
struct si476x_power_down_args args = {
.xosc = false,
};
err = si476x_core_cmd_power_down(core, &args);
}
/* We couldn't disable those before
* 'si476x_core_cmd_power_down' since we expect to get CTS
* interrupt */
if (core->client->irq)
disable_irq(core->client->irq);
else
cancel_delayed_work_sync(&core->status_monitor);
if (!soft) {
if (gpio_is_valid(core->gpio_reset))
gpio_set_value_cansleep(core->gpio_reset, 0);
}
return err;
}
EXPORT_SYMBOL_GPL(si476x_core_stop);
/**
* si476x_core_set_power_state() - set the level at which the power is
* supplied for the chip.
* @core: Core device structure
* @next_state: enum si476x_power_state describing power state to
* switch to.
*
* Switch on all the required power supplies
*
* This function returns 0 in case of suvccess and negative error code
* otherwise.
*/
int si476x_core_set_power_state(struct si476x_core *core,
enum si476x_power_state next_state)
{
/*
It is not clear form the datasheet if it is possible to
work with device if not all power domains are operational.
So for now the power-up policy is "power-up all the things!"
*/
int err = 0;
if (core->power_state == SI476X_POWER_INCONSISTENT) {
dev_err(&core->client->dev,
"The device in inconsistent power state\n");
return -EINVAL;
}
if (next_state != core->power_state) {
switch (next_state) {
case SI476X_POWER_UP_FULL:
err = regulator_bulk_enable(ARRAY_SIZE(core->supplies),
core->supplies);
if (err < 0) {
core->power_state = SI476X_POWER_INCONSISTENT;
break;
}
/*
* Startup timing diagram recommends to have a
* 100 us delay between enabling of the power
* supplies and turning the tuner on.
*/
udelay(100);
err = si476x_core_start(core, false);
if (err < 0)
goto disable_regulators;
core->power_state = next_state;
break;
case SI476X_POWER_DOWN:
core->power_state = next_state;
err = si476x_core_stop(core, false);
if (err < 0)
core->power_state = SI476X_POWER_INCONSISTENT;
disable_regulators:
err = regulator_bulk_disable(ARRAY_SIZE(core->supplies),
core->supplies);
if (err < 0)
core->power_state = SI476X_POWER_INCONSISTENT;
break;
default:
BUG();
}
}
return err;
}
EXPORT_SYMBOL_GPL(si476x_core_set_power_state);
/**
* si476x_core_report_drainer_stop() - mark the completion of the RDS
* buffer drain porcess by the worker.
*
* @core: Core device structure
*/
static inline void si476x_core_report_drainer_stop(struct si476x_core *core)
{
mutex_lock(&core->rds_drainer_status_lock);
core->rds_drainer_is_working = false;
mutex_unlock(&core->rds_drainer_status_lock);
}
/**
* si476x_core_start_rds_drainer_once() - start RDS drainer worker if
* ther is none working, do nothing otherwise
*
* @core: Datastructure corresponding to the chip.
*/
static inline void si476x_core_start_rds_drainer_once(struct si476x_core *core)
{
mutex_lock(&core->rds_drainer_status_lock);
if (!core->rds_drainer_is_working) {
core->rds_drainer_is_working = true;
schedule_work(&core->rds_fifo_drainer);
}
mutex_unlock(&core->rds_drainer_status_lock);
}
/**
* si476x_core_drain_rds_fifo() - RDS buffer drainer.
* @work: struct work_struct being ppassed to the function by the
* kernel.
*
* Drain the contents of the RDS FIFO of
*/
static void si476x_core_drain_rds_fifo(struct work_struct *work)
{
int err;
struct si476x_core *core = container_of(work, struct si476x_core,
rds_fifo_drainer);
struct si476x_rds_status_report report;
si476x_core_lock(core);
err = si476x_core_cmd_fm_rds_status(core, true, false, false, &report);
if (!err) {
int i = report.rdsfifoused;
dev_dbg(&core->client->dev,
"%d elements in RDS FIFO. Draining.\n", i);
for (; i > 0; --i) {
err = si476x_core_cmd_fm_rds_status(core, false, false,
(i == 1), &report);
if (err < 0)
goto unlock;
kfifo_in(&core->rds_fifo, report.rds,
sizeof(report.rds));
dev_dbg(&core->client->dev, "RDS data:\n %*ph\n",
(int)sizeof(report.rds), report.rds);
}
dev_dbg(&core->client->dev, "Drrrrained!\n");
wake_up_interruptible(&core->rds_read_queue);
}
unlock:
si476x_core_unlock(core);
si476x_core_report_drainer_stop(core);
}
/**
* si476x_core_pronounce_dead()
*
* @core: Core device structure
*
* Mark the device as being dead and wake up all potentially waiting
* threads of execution.
*
*/
static void si476x_core_pronounce_dead(struct si476x_core *core)
{
dev_info(&core->client->dev, "Core device is dead.\n");
atomic_set(&core->is_alive, 0);
/* Wake up al possible waiting processes */
wake_up_interruptible(&core->rds_read_queue);
atomic_set(&core->cts, 1);
wake_up(&core->command);
atomic_set(&core->stc, 1);
wake_up(&core->tuning);
}
/**
* si476x_core_i2c_xfer()
*
* @core: Core device structure
* @type: Transfer type
* @buf: Transfer buffer for/with data
* @count: Transfer buffer size
*
* Perfrom and I2C transfer(either read or write) and keep a counter
* of I/O errors. If the error counter rises above the threshold
* pronounce device dead.
*
* The function returns zero on succes or negative error code on
* failure.
*/
int si476x_core_i2c_xfer(struct si476x_core *core,
enum si476x_i2c_type type,
char *buf, int count)
{
static int io_errors_count;
int err;
if (type == SI476X_I2C_SEND)
err = i2c_master_send(core->client, buf, count);
else
err = i2c_master_recv(core->client, buf, count);
if (err < 0) {
if (io_errors_count++ > SI476X_MAX_IO_ERRORS)
si476x_core_pronounce_dead(core);
} else {
io_errors_count = 0;
}
return err;
}
EXPORT_SYMBOL_GPL(si476x_core_i2c_xfer);
/**
* si476x_core_get_status()
* @core: Core device structure
*
* Get the status byte of the core device by berforming one byte I2C
* read.
*
* The function returns a status value or a negative error code on
* error.
*/
static int si476x_core_get_status(struct si476x_core *core)
{
u8 response;
int err = si476x_core_i2c_xfer(core, SI476X_I2C_RECV,
&response, sizeof(response));
return (err < 0) ? err : response;
}
/**
* si476x_core_get_and_signal_status() - IRQ dispatcher
* @core: Core device structure
*
* Dispatch the arrived interrupt request based on the value of the
* status byte reported by the tuner.
*
*/
static void si476x_core_get_and_signal_status(struct si476x_core *core)
{
int status = si476x_core_get_status(core);
if (status < 0) {
dev_err(&core->client->dev, "Failed to get status\n");
return;
}
if (status & SI476X_CTS) {
/* Unfortunately completions could not be used for
* signalling CTS since this flag cannot be cleared
* in status byte, and therefore once it becomes true
* multiple calls to 'complete' would cause the
* commands following the current one to be completed
* before they actually are */
dev_dbg(&core->client->dev, "[interrupt] CTSINT\n");
atomic_set(&core->cts, 1);
wake_up(&core->command);
}
if (status & SI476X_FM_RDS_INT) {
dev_dbg(&core->client->dev, "[interrupt] RDSINT\n");
si476x_core_start_rds_drainer_once(core);
}
if (status & SI476X_STC_INT) {
dev_dbg(&core->client->dev, "[interrupt] STCINT\n");
atomic_set(&core->stc, 1);
wake_up(&core->tuning);
}
}
static void si476x_core_poll_loop(struct work_struct *work)
{
struct si476x_core *core = SI476X_WORK_TO_CORE(work);
si476x_core_get_and_signal_status(core);
if (atomic_read(&core->is_alive))
si476x_core_schedule_polling_work(core);
}
static irqreturn_t si476x_core_interrupt(int irq, void *dev)
{
struct si476x_core *core = dev;
si476x_core_get_and_signal_status(core);
return IRQ_HANDLED;
}
/**
* si476x_core_fwver_to_revision()
* @core: Core device structure
* @func: Selects the boot function of the device:
* *_BOOTLOADER - Boot loader
* *_FM_RECEIVER - FM receiver
* *_AM_RECEIVER - AM receiver
* *_WB_RECEIVER - Weatherband receiver
* @major: Firmware major number
* @minor1: Firmware first minor number
* @minor2: Firmware second minor number
*
* Convert a chip's firmware version number into an offset that later
* will be used to as offset in "vtable" of tuner functions
*
* This function returns a positive offset in case of success and a -1
* in case of failure.
*/
static int si476x_core_fwver_to_revision(struct si476x_core *core,
int func, int major,
int minor1, int minor2)
{
switch (func) {
case SI476X_FUNC_FM_RECEIVER:
switch (major) {
case 5:
return SI476X_REVISION_A10;
case 8:
return SI476X_REVISION_A20;
case 10:
return SI476X_REVISION_A30;
default:
goto unknown_revision;
}
case SI476X_FUNC_AM_RECEIVER:
switch (major) {
case 5:
return SI476X_REVISION_A10;
case 7:
return SI476X_REVISION_A20;
case 9:
return SI476X_REVISION_A30;
default:
goto unknown_revision;
}
case SI476X_FUNC_WB_RECEIVER:
switch (major) {
case 3:
return SI476X_REVISION_A10;
case 5:
return SI476X_REVISION_A20;
case 7:
return SI476X_REVISION_A30;
default:
goto unknown_revision;
}
case SI476X_FUNC_BOOTLOADER:
default: /* FALLTHROUGH */
BUG();
return -1;
}
unknown_revision:
dev_err(&core->client->dev,
"Unsupported version of the firmware: %d.%d.%d, "
"reverting to A10 compatible functions\n",
major, minor1, minor2);
return SI476X_REVISION_A10;
}
/**
* si476x_core_get_revision_info()
* @core: Core device structure
*
* Get the firmware version number of the device. It is done in
* following three steps:
* 1. Power-up the device
* 2. Send the 'FUNC_INFO' command
* 3. Powering the device down.
*
* The function return zero on success and a negative error code on
* failure.
*/
static int si476x_core_get_revision_info(struct si476x_core *core)
{
int rval;
struct si476x_func_info info;
si476x_core_lock(core);
rval = si476x_core_set_power_state(core, SI476X_POWER_UP_FULL);
if (rval < 0)
goto exit;
rval = si476x_core_cmd_func_info(core, &info);
if (rval < 0)
goto power_down;
core->revision = si476x_core_fwver_to_revision(core, info.func,
info.firmware.major,
info.firmware.minor[0],
info.firmware.minor[1]);
power_down:
si476x_core_set_power_state(core, SI476X_POWER_DOWN);
exit:
si476x_core_unlock(core);
return rval;
}
bool si476x_core_has_am(struct si476x_core *core)
{
return core->chip_id == SI476X_CHIP_SI4761 ||
core->chip_id == SI476X_CHIP_SI4764;
}
EXPORT_SYMBOL_GPL(si476x_core_has_am);
bool si476x_core_has_diversity(struct si476x_core *core)
{
return core->chip_id == SI476X_CHIP_SI4764;
}
EXPORT_SYMBOL_GPL(si476x_core_has_diversity);
bool si476x_core_is_a_secondary_tuner(struct si476x_core *core)
{
return si476x_core_has_diversity(core) &&
(core->diversity_mode == SI476X_PHDIV_SECONDARY_ANTENNA ||
core->diversity_mode == SI476X_PHDIV_SECONDARY_COMBINING);
}
EXPORT_SYMBOL_GPL(si476x_core_is_a_secondary_tuner);
bool si476x_core_is_a_primary_tuner(struct si476x_core *core)
{
return si476x_core_has_diversity(core) &&
(core->diversity_mode == SI476X_PHDIV_PRIMARY_ANTENNA ||
core->diversity_mode == SI476X_PHDIV_PRIMARY_COMBINING);
}
EXPORT_SYMBOL_GPL(si476x_core_is_a_primary_tuner);
bool si476x_core_is_in_am_receiver_mode(struct si476x_core *core)
{
return si476x_core_has_am(core) &&
(core->power_up_parameters.func == SI476X_FUNC_AM_RECEIVER);
}
EXPORT_SYMBOL_GPL(si476x_core_is_in_am_receiver_mode);
bool si476x_core_is_powered_up(struct si476x_core *core)
{
return core->power_state == SI476X_POWER_UP_FULL;
}
EXPORT_SYMBOL_GPL(si476x_core_is_powered_up);
static int si476x_core_probe(struct i2c_client *client)
{
const struct i2c_device_id *id = i2c_client_get_device_id(client);
int rval;
struct si476x_core *core;
struct si476x_platform_data *pdata;
struct mfd_cell *cell;
int cell_num;
core = devm_kzalloc(&client->dev, sizeof(*core), GFP_KERNEL);
if (!core)
return -ENOMEM;
core->client = client;
core->regmap = devm_regmap_init_si476x(core);
if (IS_ERR(core->regmap)) {
rval = PTR_ERR(core->regmap);
dev_err(&client->dev,
"Failed to allocate register map: %d\n",
rval);
return rval;
}
i2c_set_clientdata(client, core);
atomic_set(&core->is_alive, 0);
core->power_state = SI476X_POWER_DOWN;
pdata = dev_get_platdata(&client->dev);
if (pdata) {
memcpy(&core->power_up_parameters,
&pdata->power_up_parameters,
sizeof(core->power_up_parameters));
core->gpio_reset = -1;
if (gpio_is_valid(pdata->gpio_reset)) {
rval = gpio_request(pdata->gpio_reset, "si476x reset");
if (rval) {
dev_err(&client->dev,
"Failed to request gpio: %d\n", rval);
return rval;
}
core->gpio_reset = pdata->gpio_reset;
gpio_direction_output(core->gpio_reset, 0);
}
core->diversity_mode = pdata->diversity_mode;
memcpy(&core->pinmux, &pdata->pinmux,
sizeof(struct si476x_pinmux));
} else {
dev_err(&client->dev, "No platform data provided\n");
return -EINVAL;
}
core->supplies[0].supply = "vd";
core->supplies[1].supply = "va";
core->supplies[2].supply = "vio1";
core->supplies[3].supply = "vio2";
rval = devm_regulator_bulk_get(&client->dev,
ARRAY_SIZE(core->supplies),
core->supplies);
if (rval) {
dev_err(&client->dev, "Failed to get all of the regulators\n");
goto free_gpio;
}
mutex_init(&core->cmd_lock);
init_waitqueue_head(&core->command);
init_waitqueue_head(&core->tuning);
rval = kfifo_alloc(&core->rds_fifo,
SI476X_DRIVER_RDS_FIFO_DEPTH *
sizeof(struct v4l2_rds_data),
GFP_KERNEL);
if (rval) {
dev_err(&client->dev, "Could not allocate the FIFO\n");
goto free_gpio;
}
mutex_init(&core->rds_drainer_status_lock);
init_waitqueue_head(&core->rds_read_queue);
INIT_WORK(&core->rds_fifo_drainer, si476x_core_drain_rds_fifo);
if (client->irq) {
rval = devm_request_threaded_irq(&client->dev,
client->irq, NULL,
si476x_core_interrupt,
IRQF_TRIGGER_FALLING |
IRQF_ONESHOT,
client->name, core);
if (rval < 0) {
dev_err(&client->dev, "Could not request IRQ %d\n",
client->irq);
goto free_kfifo;
}
disable_irq(client->irq);
dev_dbg(&client->dev, "IRQ requested.\n");
core->rds_fifo_depth = 20;
} else {
INIT_DELAYED_WORK(&core->status_monitor,
si476x_core_poll_loop);
dev_info(&client->dev,
"No IRQ number specified, will use polling\n");
core->rds_fifo_depth = 5;
}
core->chip_id = id->driver_data;
rval = si476x_core_get_revision_info(core);
if (rval < 0) {
rval = -ENODEV;
goto free_kfifo;
}
cell_num = 0;
cell = &core->cells[SI476X_RADIO_CELL];
cell->name = "si476x-radio";
cell_num++;
#ifdef CONFIG_SND_SOC_SI476X
if ((core->chip_id == SI476X_CHIP_SI4761 ||
core->chip_id == SI476X_CHIP_SI4764) &&
core->pinmux.dclk == SI476X_DCLK_DAUDIO &&
core->pinmux.dfs == SI476X_DFS_DAUDIO &&
core->pinmux.dout == SI476X_DOUT_I2S_OUTPUT &&
core->pinmux.xout == SI476X_XOUT_TRISTATE) {
cell = &core->cells[SI476X_CODEC_CELL];
cell->name = "si476x-codec";
cell_num++;
}
#endif
rval = mfd_add_devices(&client->dev,
(client->adapter->nr << 8) + client->addr,
core->cells, cell_num,
NULL, 0, NULL);
if (!rval)
return 0;
free_kfifo:
kfifo_free(&core->rds_fifo);
free_gpio:
if (gpio_is_valid(core->gpio_reset))
gpio_free(core->gpio_reset);
return rval;
}
static void si476x_core_remove(struct i2c_client *client)
{
struct si476x_core *core = i2c_get_clientdata(client);
si476x_core_pronounce_dead(core);
mfd_remove_devices(&client->dev);
if (client->irq)
disable_irq(client->irq);
else
cancel_delayed_work_sync(&core->status_monitor);
kfifo_free(&core->rds_fifo);
if (gpio_is_valid(core->gpio_reset))
gpio_free(core->gpio_reset);
}
static const struct i2c_device_id si476x_id[] = {
{ "si4761", SI476X_CHIP_SI4761 },
{ "si4764", SI476X_CHIP_SI4764 },
{ "si4768", SI476X_CHIP_SI4768 },
{ },
};
MODULE_DEVICE_TABLE(i2c, si476x_id);
static struct i2c_driver si476x_core_driver = {
.driver = {
.name = "si476x-core",
},
.probe = si476x_core_probe,
.remove = si476x_core_remove,
.id_table = si476x_id,
};
module_i2c_driver(si476x_core_driver);
MODULE_AUTHOR("Andrey Smirnov <[email protected]>");
MODULE_DESCRIPTION("Si4761/64/68 AM/FM MFD core device driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/si476x-i2c.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) STMicroelectronics 2016
* Author: Benjamin Gaignard <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/mfd/stm32-timers.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#define STM32_TIMERS_MAX_REGISTERS 0x3fc
/* DIER register DMA enable bits */
static const u32 stm32_timers_dier_dmaen[STM32_TIMERS_MAX_DMAS] = {
TIM_DIER_CC1DE,
TIM_DIER_CC2DE,
TIM_DIER_CC3DE,
TIM_DIER_CC4DE,
TIM_DIER_UIE,
TIM_DIER_TDE,
TIM_DIER_COMDE
};
static void stm32_timers_dma_done(void *p)
{
struct stm32_timers_dma *dma = p;
struct dma_tx_state state;
enum dma_status status;
status = dmaengine_tx_status(dma->chan, dma->chan->cookie, &state);
if (status == DMA_COMPLETE)
complete(&dma->completion);
}
/**
* stm32_timers_dma_burst_read - Read from timers registers using DMA.
*
* Read from STM32 timers registers using DMA on a single event.
* @dev: reference to stm32_timers MFD device
* @buf: DMA'able destination buffer
* @id: stm32_timers_dmas event identifier (ch[1..4], up, trig or com)
* @reg: registers start offset for DMA to read from (like CCRx for capture)
* @num_reg: number of registers to read upon each DMA request, starting @reg.
* @bursts: number of bursts to read (e.g. like two for pwm period capture)
* @tmo_ms: timeout (milliseconds)
*/
int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
enum stm32_timers_dmas id, u32 reg,
unsigned int num_reg, unsigned int bursts,
unsigned long tmo_ms)
{
struct stm32_timers *ddata = dev_get_drvdata(dev);
unsigned long timeout = msecs_to_jiffies(tmo_ms);
struct regmap *regmap = ddata->regmap;
struct stm32_timers_dma *dma = &ddata->dma;
size_t len = num_reg * bursts * sizeof(u32);
struct dma_async_tx_descriptor *desc;
struct dma_slave_config config;
dma_cookie_t cookie;
dma_addr_t dma_buf;
u32 dbl, dba;
long err;
int ret;
/* Sanity check */
if (id < STM32_TIMERS_DMA_CH1 || id >= STM32_TIMERS_MAX_DMAS)
return -EINVAL;
if (!num_reg || !bursts || reg > STM32_TIMERS_MAX_REGISTERS ||
(reg + num_reg * sizeof(u32)) > STM32_TIMERS_MAX_REGISTERS)
return -EINVAL;
if (!dma->chans[id])
return -ENODEV;
mutex_lock(&dma->lock);
/* Select DMA channel in use */
dma->chan = dma->chans[id];
dma_buf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
if (dma_mapping_error(dev, dma_buf)) {
ret = -ENOMEM;
goto unlock;
}
/* Prepare DMA read from timer registers, using DMA burst mode */
memset(&config, 0, sizeof(config));
config.src_addr = (dma_addr_t)dma->phys_base + TIM_DMAR;
config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
ret = dmaengine_slave_config(dma->chan, &config);
if (ret)
goto unmap;
desc = dmaengine_prep_slave_single(dma->chan, dma_buf, len,
DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
if (!desc) {
ret = -EBUSY;
goto unmap;
}
desc->callback = stm32_timers_dma_done;
desc->callback_param = dma;
cookie = dmaengine_submit(desc);
ret = dma_submit_error(cookie);
if (ret)
goto dma_term;
reinit_completion(&dma->completion);
dma_async_issue_pending(dma->chan);
/* Setup and enable timer DMA burst mode */
dbl = FIELD_PREP(TIM_DCR_DBL, bursts - 1);
dba = FIELD_PREP(TIM_DCR_DBA, reg >> 2);
ret = regmap_write(regmap, TIM_DCR, dbl | dba);
if (ret)
goto dma_term;
/* Clear pending flags before enabling DMA request */
ret = regmap_write(regmap, TIM_SR, 0);
if (ret)
goto dcr_clr;
ret = regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id],
stm32_timers_dier_dmaen[id]);
if (ret)
goto dcr_clr;
err = wait_for_completion_interruptible_timeout(&dma->completion,
timeout);
if (err == 0)
ret = -ETIMEDOUT;
else if (err < 0)
ret = err;
regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id], 0);
regmap_write(regmap, TIM_SR, 0);
dcr_clr:
regmap_write(regmap, TIM_DCR, 0);
dma_term:
dmaengine_terminate_all(dma->chan);
unmap:
dma_unmap_single(dev, dma_buf, len, DMA_FROM_DEVICE);
unlock:
dma->chan = NULL;
mutex_unlock(&dma->lock);
return ret;
}
EXPORT_SYMBOL_GPL(stm32_timers_dma_burst_read);
static const struct regmap_config stm32_timers_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = sizeof(u32),
.max_register = STM32_TIMERS_MAX_REGISTERS,
};
static void stm32_timers_get_arr_size(struct stm32_timers *ddata)
{
u32 arr;
/* Backup ARR to restore it after getting the maximum value */
regmap_read(ddata->regmap, TIM_ARR, &arr);
/*
* Only the available bits will be written so when readback
* we get the maximum value of auto reload register
*/
regmap_write(ddata->regmap, TIM_ARR, ~0L);
regmap_read(ddata->regmap, TIM_ARR, &ddata->max_arr);
regmap_write(ddata->regmap, TIM_ARR, arr);
}
static int stm32_timers_dma_probe(struct device *dev,
struct stm32_timers *ddata)
{
int i;
int ret = 0;
char name[4];
init_completion(&ddata->dma.completion);
mutex_init(&ddata->dma.lock);
/* Optional DMA support: get valid DMA channel(s) or NULL */
for (i = STM32_TIMERS_DMA_CH1; i <= STM32_TIMERS_DMA_CH4; i++) {
snprintf(name, ARRAY_SIZE(name), "ch%1d", i + 1);
ddata->dma.chans[i] = dma_request_chan(dev, name);
}
ddata->dma.chans[STM32_TIMERS_DMA_UP] = dma_request_chan(dev, "up");
ddata->dma.chans[STM32_TIMERS_DMA_TRIG] = dma_request_chan(dev, "trig");
ddata->dma.chans[STM32_TIMERS_DMA_COM] = dma_request_chan(dev, "com");
for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++) {
if (IS_ERR(ddata->dma.chans[i])) {
/* Save the first error code to return */
if (PTR_ERR(ddata->dma.chans[i]) != -ENODEV && !ret)
ret = PTR_ERR(ddata->dma.chans[i]);
ddata->dma.chans[i] = NULL;
}
}
return ret;
}
static void stm32_timers_dma_remove(struct device *dev,
struct stm32_timers *ddata)
{
int i;
for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++)
if (ddata->dma.chans[i])
dma_release_channel(ddata->dma.chans[i]);
}
static int stm32_timers_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct stm32_timers *ddata;
struct resource *res;
void __iomem *mmio;
int ret;
ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(mmio))
return PTR_ERR(mmio);
/* Timer physical addr for DMA */
ddata->dma.phys_base = res->start;
ddata->regmap = devm_regmap_init_mmio_clk(dev, "int", mmio,
&stm32_timers_regmap_cfg);
if (IS_ERR(ddata->regmap))
return PTR_ERR(ddata->regmap);
ddata->clk = devm_clk_get(dev, NULL);
if (IS_ERR(ddata->clk))
return PTR_ERR(ddata->clk);
stm32_timers_get_arr_size(ddata);
ret = stm32_timers_dma_probe(dev, ddata);
if (ret) {
stm32_timers_dma_remove(dev, ddata);
return ret;
}
platform_set_drvdata(pdev, ddata);
ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
if (ret)
stm32_timers_dma_remove(dev, ddata);
return ret;
}
static int stm32_timers_remove(struct platform_device *pdev)
{
struct stm32_timers *ddata = platform_get_drvdata(pdev);
/*
* Don't use devm_ here: enfore of_platform_depopulate() happens before
* DMA are released, to avoid race on DMA.
*/
of_platform_depopulate(&pdev->dev);
stm32_timers_dma_remove(&pdev->dev, ddata);
return 0;
}
static const struct of_device_id stm32_timers_of_match[] = {
{ .compatible = "st,stm32-timers", },
{ /* end node */ },
};
MODULE_DEVICE_TABLE(of, stm32_timers_of_match);
static struct platform_driver stm32_timers_driver = {
.probe = stm32_timers_probe,
.remove = stm32_timers_remove,
.driver = {
.name = "stm32-timers",
.of_match_table = stm32_timers_of_match,
},
};
module_platform_driver(stm32_timers_driver);
MODULE_DESCRIPTION("STMicroelectronics STM32 Timers");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/stm32-timers.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI/National Semiconductor LP3943 MFD Core Driver
*
* Copyright 2013 Texas Instruments
*
* Author: Milo Kim <[email protected]>
*
* Driver structure:
* LP3943 is an integrated device capable of driving 16 output channels.
* It can be used for a GPIO expander and PWM generators.
*
* LED control General usage for a device
* ___________ ____________________________
*
* LP3943 MFD ---- GPIO expander leds-gpio eg) HW enable pin
* |
* --- PWM generator leds-pwm eg) PWM input
*
* Internal two PWM channels are used for LED dimming effect.
* And each output pin can be used as a GPIO as well.
* The LED functionality can work with GPIOs or PWMs.
* LEDs can be controlled with legacy leds-gpio(static brightness) or
* leds-pwm drivers(dynamic brightness control).
* Alternatively, it can be used for generic GPIO and PWM controller.
* For example, a GPIO is HW enable pin of a device.
* A PWM is input pin of a backlight device.
*/
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#include <linux/mfd/lp3943.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/slab.h>
#define LP3943_MAX_REGISTERS 0x09
/* Register configuration for pin MUX */
static const struct lp3943_reg_cfg lp3943_mux_cfg[] = {
/* address, mask, shift */
{ LP3943_REG_MUX0, 0x03, 0 },
{ LP3943_REG_MUX0, 0x0C, 2 },
{ LP3943_REG_MUX0, 0x30, 4 },
{ LP3943_REG_MUX0, 0xC0, 6 },
{ LP3943_REG_MUX1, 0x03, 0 },
{ LP3943_REG_MUX1, 0x0C, 2 },
{ LP3943_REG_MUX1, 0x30, 4 },
{ LP3943_REG_MUX1, 0xC0, 6 },
{ LP3943_REG_MUX2, 0x03, 0 },
{ LP3943_REG_MUX2, 0x0C, 2 },
{ LP3943_REG_MUX2, 0x30, 4 },
{ LP3943_REG_MUX2, 0xC0, 6 },
{ LP3943_REG_MUX3, 0x03, 0 },
{ LP3943_REG_MUX3, 0x0C, 2 },
{ LP3943_REG_MUX3, 0x30, 4 },
{ LP3943_REG_MUX3, 0xC0, 6 },
};
static const struct mfd_cell lp3943_devs[] = {
{
.name = "lp3943-pwm",
.of_compatible = "ti,lp3943-pwm",
},
{
.name = "lp3943-gpio",
.of_compatible = "ti,lp3943-gpio",
},
};
int lp3943_read_byte(struct lp3943 *lp3943, u8 reg, u8 *read)
{
int ret;
unsigned int val;
ret = regmap_read(lp3943->regmap, reg, &val);
if (ret < 0)
return ret;
*read = (u8)val;
return 0;
}
EXPORT_SYMBOL_GPL(lp3943_read_byte);
int lp3943_write_byte(struct lp3943 *lp3943, u8 reg, u8 data)
{
return regmap_write(lp3943->regmap, reg, data);
}
EXPORT_SYMBOL_GPL(lp3943_write_byte);
int lp3943_update_bits(struct lp3943 *lp3943, u8 reg, u8 mask, u8 data)
{
return regmap_update_bits(lp3943->regmap, reg, mask, data);
}
EXPORT_SYMBOL_GPL(lp3943_update_bits);
static const struct regmap_config lp3943_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = LP3943_MAX_REGISTERS,
};
static int lp3943_probe(struct i2c_client *cl)
{
struct lp3943 *lp3943;
struct device *dev = &cl->dev;
lp3943 = devm_kzalloc(dev, sizeof(*lp3943), GFP_KERNEL);
if (!lp3943)
return -ENOMEM;
lp3943->regmap = devm_regmap_init_i2c(cl, &lp3943_regmap_config);
if (IS_ERR(lp3943->regmap))
return PTR_ERR(lp3943->regmap);
lp3943->pdata = dev_get_platdata(dev);
lp3943->dev = dev;
lp3943->mux_cfg = lp3943_mux_cfg;
i2c_set_clientdata(cl, lp3943);
return devm_mfd_add_devices(dev, -1, lp3943_devs,
ARRAY_SIZE(lp3943_devs),
NULL, 0, NULL);
}
static const struct i2c_device_id lp3943_ids[] = {
{ "lp3943", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, lp3943_ids);
#ifdef CONFIG_OF
static const struct of_device_id lp3943_of_match[] = {
{ .compatible = "ti,lp3943", },
{ }
};
MODULE_DEVICE_TABLE(of, lp3943_of_match);
#endif
static struct i2c_driver lp3943_driver = {
.probe = lp3943_probe,
.driver = {
.name = "lp3943",
.of_match_table = of_match_ptr(lp3943_of_match),
},
.id_table = lp3943_ids,
};
module_i2c_driver(lp3943_driver);
MODULE_DESCRIPTION("LP3943 MFD Core Driver");
MODULE_AUTHOR("Milo Kim");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/lp3943.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Acer Iconia Tab A500 Embedded Controller Driver
*
* Copyright 2020 GRATE-driver project
*/
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
#define A500_EC_I2C_ERR_TIMEOUT 500
#define A500_EC_POWER_CMD_TIMEOUT 1000
/*
* Controller's firmware expects specific command opcodes to be used for the
* corresponding registers. Unsupported commands are skipped by the firmware.
*/
#define CMD_SHUTDOWN 0x0
#define CMD_WARM_REBOOT 0x0
#define CMD_COLD_REBOOT 0x1
enum {
REG_CURRENT_NOW = 0x03,
REG_SHUTDOWN = 0x52,
REG_WARM_REBOOT = 0x54,
REG_COLD_REBOOT = 0x55,
};
static struct i2c_client *a500_ec_client_pm_off;
static int a500_ec_read(void *context, const void *reg_buf, size_t reg_size,
void *val_buf, size_t val_sizel)
{
struct i2c_client *client = context;
unsigned int reg, retries = 5;
u16 *ret_val = val_buf;
s32 ret = 0;
reg = *(u8 *)reg_buf;
while (retries-- > 0) {
ret = i2c_smbus_read_word_data(client, reg);
if (ret >= 0)
break;
msleep(A500_EC_I2C_ERR_TIMEOUT);
}
if (ret < 0) {
dev_err(&client->dev, "read 0x%x failed: %d\n", reg, ret);
return ret;
}
*ret_val = ret;
if (reg == REG_CURRENT_NOW)
fsleep(10000);
return 0;
}
static int a500_ec_write(void *context, const void *data, size_t count)
{
struct i2c_client *client = context;
unsigned int reg, val, retries = 5;
s32 ret = 0;
reg = *(u8 *)(data + 0);
val = *(u16 *)(data + 1);
while (retries-- > 0) {
ret = i2c_smbus_write_word_data(client, reg, val);
if (ret >= 0)
break;
msleep(A500_EC_I2C_ERR_TIMEOUT);
}
if (ret < 0) {
dev_err(&client->dev, "write 0x%x failed: %d\n", reg, ret);
return ret;
}
return 0;
}
static const struct regmap_config a500_ec_regmap_config = {
.name = "KB930",
.reg_bits = 8,
.val_bits = 16,
.max_register = 0xff,
};
static const struct regmap_bus a500_ec_regmap_bus = {
.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
.write = a500_ec_write,
.read = a500_ec_read,
.max_raw_read = 2,
};
static void a500_ec_poweroff(void)
{
i2c_smbus_write_word_data(a500_ec_client_pm_off,
REG_SHUTDOWN, CMD_SHUTDOWN);
mdelay(A500_EC_POWER_CMD_TIMEOUT);
}
static int a500_ec_restart_notify(struct notifier_block *this,
unsigned long reboot_mode, void *data)
{
if (reboot_mode == REBOOT_WARM)
i2c_smbus_write_word_data(a500_ec_client_pm_off,
REG_WARM_REBOOT, CMD_WARM_REBOOT);
else
i2c_smbus_write_word_data(a500_ec_client_pm_off,
REG_COLD_REBOOT, CMD_COLD_REBOOT);
mdelay(A500_EC_POWER_CMD_TIMEOUT);
return NOTIFY_DONE;
}
static struct notifier_block a500_ec_restart_handler = {
.notifier_call = a500_ec_restart_notify,
.priority = 200,
};
static const struct mfd_cell a500_ec_cells[] = {
{ .name = "acer-a500-iconia-battery", },
{ .name = "acer-a500-iconia-leds", },
};
static int a500_ec_probe(struct i2c_client *client)
{
struct regmap *regmap;
int err;
regmap = devm_regmap_init(&client->dev, &a500_ec_regmap_bus,
client, &a500_ec_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
err = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO,
a500_ec_cells, ARRAY_SIZE(a500_ec_cells),
NULL, 0, NULL);
if (err) {
dev_err(&client->dev, "failed to add sub-devices: %d\n", err);
return err;
}
if (of_device_is_system_power_controller(client->dev.of_node)) {
a500_ec_client_pm_off = client;
err = register_restart_handler(&a500_ec_restart_handler);
if (err)
return err;
if (!pm_power_off)
pm_power_off = a500_ec_poweroff;
}
return 0;
}
static void a500_ec_remove(struct i2c_client *client)
{
if (of_device_is_system_power_controller(client->dev.of_node)) {
if (pm_power_off == a500_ec_poweroff)
pm_power_off = NULL;
unregister_restart_handler(&a500_ec_restart_handler);
}
}
static const struct of_device_id a500_ec_match[] = {
{ .compatible = "acer,a500-iconia-ec" },
{ }
};
MODULE_DEVICE_TABLE(of, a500_ec_match);
static struct i2c_driver a500_ec_driver = {
.driver = {
.name = "acer-a500-embedded-controller",
.of_match_table = a500_ec_match,
},
.probe = a500_ec_probe,
.remove = a500_ec_remove,
};
module_i2c_driver(a500_ec_driver);
MODULE_DESCRIPTION("Acer Iconia Tab A500 Embedded Controller driver");
MODULE_AUTHOR("Dmitry Osipenko <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/acer-ec-a500.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm831x-spi.c -- SPI access for Wolfson WM831x PMICs
*
* Copyright 2009,2010 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm.h>
#include <linux/spi/spi.h>
#include <linux/regmap.h>
#include <linux/err.h>
#include <linux/mfd/wm831x/core.h>
static int wm831x_spi_probe(struct spi_device *spi)
{
struct wm831x_pdata *pdata = dev_get_platdata(&spi->dev);
const struct spi_device_id *id = spi_get_device_id(spi);
const struct of_device_id *of_id;
struct wm831x *wm831x;
enum wm831x_parent type;
int ret;
if (spi->dev.of_node) {
of_id = of_match_device(wm831x_of_match, &spi->dev);
if (!of_id) {
dev_err(&spi->dev, "Failed to match device\n");
return -ENODEV;
}
type = (uintptr_t)of_id->data;
} else {
type = (enum wm831x_parent)id->driver_data;
}
wm831x = devm_kzalloc(&spi->dev, sizeof(struct wm831x), GFP_KERNEL);
if (wm831x == NULL)
return -ENOMEM;
spi->mode = SPI_MODE_0;
spi_set_drvdata(spi, wm831x);
wm831x->dev = &spi->dev;
wm831x->type = type;
wm831x->regmap = devm_regmap_init_spi(spi, &wm831x_regmap_config);
if (IS_ERR(wm831x->regmap)) {
ret = PTR_ERR(wm831x->regmap);
dev_err(wm831x->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
if (pdata)
memcpy(&wm831x->pdata, pdata, sizeof(*pdata));
return wm831x_device_init(wm831x, spi->irq);
}
static int wm831x_spi_suspend(struct device *dev)
{
struct wm831x *wm831x = dev_get_drvdata(dev);
return wm831x_device_suspend(wm831x);
}
static int wm831x_spi_poweroff(struct device *dev)
{
struct wm831x *wm831x = dev_get_drvdata(dev);
wm831x_device_shutdown(wm831x);
return 0;
}
static const struct dev_pm_ops wm831x_spi_pm = {
.freeze = wm831x_spi_suspend,
.suspend = wm831x_spi_suspend,
.poweroff = wm831x_spi_poweroff,
};
static const struct spi_device_id wm831x_spi_ids[] = {
{ "wm8310", WM8310 },
{ "wm8311", WM8311 },
{ "wm8312", WM8312 },
{ "wm8320", WM8320 },
{ "wm8321", WM8321 },
{ "wm8325", WM8325 },
{ "wm8326", WM8326 },
{ },
};
static struct spi_driver wm831x_spi_driver = {
.driver = {
.name = "wm831x",
.pm = &wm831x_spi_pm,
.of_match_table = of_match_ptr(wm831x_of_match),
.suppress_bind_attrs = true,
},
.id_table = wm831x_spi_ids,
.probe = wm831x_spi_probe,
};
static int __init wm831x_spi_init(void)
{
int ret;
ret = spi_register_driver(&wm831x_spi_driver);
if (ret != 0)
pr_err("Failed to register WM831x SPI driver: %d\n", ret);
return 0;
}
subsys_initcall(wm831x_spi_init);
| linux-master | drivers/mfd/wm831x-spi.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SGI IOC3 multifunction device driver
*
* Copyright (C) 2018, 2019 Thomas Bogendoerfer <[email protected]>
*
* Based on work by:
* Stanislaw Skowronek <[email protected]>
* Joshua Kinard <[email protected]>
* Brent Casavant <[email protected]> - IOC4 master driver
* Pat Gefre <[email protected]> - IOC3 serial port IRQ demuxer
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/platform_data/sgi-w1.h>
#include <linux/rtc/ds1685.h>
#include <asm/pci/bridge.h>
#include <asm/sn/ioc3.h>
#define IOC3_IRQ_SERIAL_A 6
#define IOC3_IRQ_SERIAL_B 15
#define IOC3_IRQ_KBD 22
/* Bitmask for selecting which IRQs are level triggered */
#define IOC3_LVL_MASK (BIT(IOC3_IRQ_SERIAL_A) | BIT(IOC3_IRQ_SERIAL_B))
#define M48T35_REG_SIZE 32768 /* size of m48t35 registers */
/* 1.2 us latency timer (40 cycles at 33 MHz) */
#define IOC3_LATENCY 40
struct ioc3_priv_data {
struct irq_domain *domain;
struct ioc3 __iomem *regs;
struct pci_dev *pdev;
int domain_irq;
};
static void ioc3_irq_ack(struct irq_data *d)
{
struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
unsigned int hwirq = irqd_to_hwirq(d);
writel(BIT(hwirq), &ipd->regs->sio_ir);
}
static void ioc3_irq_mask(struct irq_data *d)
{
struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
unsigned int hwirq = irqd_to_hwirq(d);
writel(BIT(hwirq), &ipd->regs->sio_iec);
}
static void ioc3_irq_unmask(struct irq_data *d)
{
struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
unsigned int hwirq = irqd_to_hwirq(d);
writel(BIT(hwirq), &ipd->regs->sio_ies);
}
static struct irq_chip ioc3_irq_chip = {
.name = "IOC3",
.irq_ack = ioc3_irq_ack,
.irq_mask = ioc3_irq_mask,
.irq_unmask = ioc3_irq_unmask,
};
static int ioc3_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
/* Set level IRQs for every interrupt contained in IOC3_LVL_MASK */
if (BIT(hwirq) & IOC3_LVL_MASK)
irq_set_chip_and_handler(irq, &ioc3_irq_chip, handle_level_irq);
else
irq_set_chip_and_handler(irq, &ioc3_irq_chip, handle_edge_irq);
irq_set_chip_data(irq, d->host_data);
return 0;
}
static void ioc3_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
{
irq_set_chip_and_handler(irq, NULL, NULL);
irq_set_chip_data(irq, NULL);
}
static const struct irq_domain_ops ioc3_irq_domain_ops = {
.map = ioc3_irq_domain_map,
.unmap = ioc3_irq_domain_unmap,
};
static void ioc3_irq_handler(struct irq_desc *desc)
{
struct irq_domain *domain = irq_desc_get_handler_data(desc);
struct ioc3_priv_data *ipd = domain->host_data;
struct ioc3 __iomem *regs = ipd->regs;
u32 pending, mask;
pending = readl(®s->sio_ir);
mask = readl(®s->sio_ies);
pending &= mask; /* Mask off not enabled interrupts */
if (pending)
generic_handle_domain_irq(domain, __ffs(pending));
else
spurious_interrupt();
}
/*
* System boards/BaseIOs use more interrupt pins of the bridge ASIC
* to which the IOC3 is connected. Since the IOC3 MFD driver
* knows wiring of these extra pins, we use the map_irq function
* to get interrupts activated
*/
static int ioc3_map_irq(struct pci_dev *pdev, int slot, int pin)
{
struct pci_host_bridge *hbrg = pci_find_host_bridge(pdev->bus);
return hbrg->map_irq(pdev, slot, pin);
}
static int ioc3_irq_domain_setup(struct ioc3_priv_data *ipd, int irq)
{
struct irq_domain *domain;
struct fwnode_handle *fn;
fn = irq_domain_alloc_named_fwnode("IOC3");
if (!fn)
goto err;
domain = irq_domain_create_linear(fn, 24, &ioc3_irq_domain_ops, ipd);
if (!domain) {
irq_domain_free_fwnode(fn);
goto err;
}
ipd->domain = domain;
irq_set_chained_handler_and_data(irq, ioc3_irq_handler, domain);
ipd->domain_irq = irq;
return 0;
err:
dev_err(&ipd->pdev->dev, "irq domain setup failed\n");
return -ENOMEM;
}
static const struct resource ioc3_uarta_resources[] = {
DEFINE_RES_MEM(offsetof(struct ioc3, sregs.uarta),
sizeof_field(struct ioc3, sregs.uarta)),
DEFINE_RES_IRQ(IOC3_IRQ_SERIAL_A)
};
static const struct resource ioc3_uartb_resources[] = {
DEFINE_RES_MEM(offsetof(struct ioc3, sregs.uartb),
sizeof_field(struct ioc3, sregs.uartb)),
DEFINE_RES_IRQ(IOC3_IRQ_SERIAL_B)
};
static struct mfd_cell ioc3_serial_cells[] = {
{
.name = "ioc3-serial8250",
.resources = ioc3_uarta_resources,
.num_resources = ARRAY_SIZE(ioc3_uarta_resources),
},
{
.name = "ioc3-serial8250",
.resources = ioc3_uartb_resources,
.num_resources = ARRAY_SIZE(ioc3_uartb_resources),
}
};
static int ioc3_serial_setup(struct ioc3_priv_data *ipd)
{
int ret;
/* Set gpio pins for RS232/RS422 mode selection */
writel(GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL,
&ipd->regs->gpcr_s);
/* Select RS232 mode for uart a */
writel(0, &ipd->regs->gppr[6]);
/* Select RS232 mode for uart b */
writel(0, &ipd->regs->gppr[7]);
/* Switch both ports to 16650 mode */
writel(readl(&ipd->regs->port_a.sscr) & ~SSCR_DMA_EN,
&ipd->regs->port_a.sscr);
writel(readl(&ipd->regs->port_b.sscr) & ~SSCR_DMA_EN,
&ipd->regs->port_b.sscr);
udelay(1000); /* Wait until mode switch is done */
ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
ioc3_serial_cells, ARRAY_SIZE(ioc3_serial_cells),
&ipd->pdev->resource[0], 0, ipd->domain);
if (ret) {
dev_err(&ipd->pdev->dev, "Failed to add 16550 subdevs\n");
return ret;
}
return 0;
}
static const struct resource ioc3_kbd_resources[] = {
DEFINE_RES_MEM(offsetof(struct ioc3, serio),
sizeof_field(struct ioc3, serio)),
DEFINE_RES_IRQ(IOC3_IRQ_KBD)
};
static struct mfd_cell ioc3_kbd_cells[] = {
{
.name = "ioc3-kbd",
.resources = ioc3_kbd_resources,
.num_resources = ARRAY_SIZE(ioc3_kbd_resources),
}
};
static int ioc3_kbd_setup(struct ioc3_priv_data *ipd)
{
int ret;
ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
ioc3_kbd_cells, ARRAY_SIZE(ioc3_kbd_cells),
&ipd->pdev->resource[0], 0, ipd->domain);
if (ret) {
dev_err(&ipd->pdev->dev, "Failed to add 16550 subdevs\n");
return ret;
}
return 0;
}
static const struct resource ioc3_eth_resources[] = {
DEFINE_RES_MEM(offsetof(struct ioc3, eth),
sizeof_field(struct ioc3, eth)),
DEFINE_RES_MEM(offsetof(struct ioc3, ssram),
sizeof_field(struct ioc3, ssram)),
DEFINE_RES_IRQ(0)
};
static const struct resource ioc3_w1_resources[] = {
DEFINE_RES_MEM(offsetof(struct ioc3, mcr),
sizeof_field(struct ioc3, mcr)),
};
static struct sgi_w1_platform_data ioc3_w1_platform_data;
static struct mfd_cell ioc3_eth_cells[] = {
{
.name = "ioc3-eth",
.resources = ioc3_eth_resources,
.num_resources = ARRAY_SIZE(ioc3_eth_resources),
},
{
.name = "sgi_w1",
.resources = ioc3_w1_resources,
.num_resources = ARRAY_SIZE(ioc3_w1_resources),
.platform_data = &ioc3_w1_platform_data,
.pdata_size = sizeof(ioc3_w1_platform_data),
}
};
static int ioc3_eth_setup(struct ioc3_priv_data *ipd)
{
int ret;
/* Enable One-Wire bus */
writel(GPCR_MLAN_EN, &ipd->regs->gpcr_s);
/* Generate unique identifier */
snprintf(ioc3_w1_platform_data.dev_id,
sizeof(ioc3_w1_platform_data.dev_id), "ioc3-%012llx",
ipd->pdev->resource->start);
ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
ioc3_eth_cells, ARRAY_SIZE(ioc3_eth_cells),
&ipd->pdev->resource[0], ipd->pdev->irq, NULL);
if (ret) {
dev_err(&ipd->pdev->dev, "Failed to add ETH/W1 subdev\n");
return ret;
}
return 0;
}
static const struct resource ioc3_m48t35_resources[] = {
DEFINE_RES_MEM(IOC3_BYTEBUS_DEV0, M48T35_REG_SIZE)
};
static struct mfd_cell ioc3_m48t35_cells[] = {
{
.name = "rtc-m48t35",
.resources = ioc3_m48t35_resources,
.num_resources = ARRAY_SIZE(ioc3_m48t35_resources),
}
};
static int ioc3_m48t35_setup(struct ioc3_priv_data *ipd)
{
int ret;
ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
ioc3_m48t35_cells, ARRAY_SIZE(ioc3_m48t35_cells),
&ipd->pdev->resource[0], 0, ipd->domain);
if (ret)
dev_err(&ipd->pdev->dev, "Failed to add M48T35 subdev\n");
return ret;
}
static struct ds1685_rtc_platform_data ip30_rtc_platform_data = {
.bcd_mode = false,
.no_irq = false,
.uie_unsupported = true,
.access_type = ds1685_reg_indirect,
};
static const struct resource ioc3_rtc_ds1685_resources[] = {
DEFINE_RES_MEM(IOC3_BYTEBUS_DEV1, 1),
DEFINE_RES_MEM(IOC3_BYTEBUS_DEV2, 1),
DEFINE_RES_IRQ(0)
};
static struct mfd_cell ioc3_ds1685_cells[] = {
{
.name = "rtc-ds1685",
.resources = ioc3_rtc_ds1685_resources,
.num_resources = ARRAY_SIZE(ioc3_rtc_ds1685_resources),
.platform_data = &ip30_rtc_platform_data,
.pdata_size = sizeof(ip30_rtc_platform_data),
.id = PLATFORM_DEVID_NONE,
}
};
static int ioc3_ds1685_setup(struct ioc3_priv_data *ipd)
{
int ret, irq;
irq = ioc3_map_irq(ipd->pdev, 6, 0);
ret = mfd_add_devices(&ipd->pdev->dev, 0, ioc3_ds1685_cells,
ARRAY_SIZE(ioc3_ds1685_cells),
&ipd->pdev->resource[0], irq, NULL);
if (ret)
dev_err(&ipd->pdev->dev, "Failed to add DS1685 subdev\n");
return ret;
};
static const struct resource ioc3_leds_resources[] = {
DEFINE_RES_MEM(offsetof(struct ioc3, gppr[0]),
sizeof_field(struct ioc3, gppr[0])),
DEFINE_RES_MEM(offsetof(struct ioc3, gppr[1]),
sizeof_field(struct ioc3, gppr[1])),
};
static struct mfd_cell ioc3_led_cells[] = {
{
.name = "ip30-leds",
.resources = ioc3_leds_resources,
.num_resources = ARRAY_SIZE(ioc3_leds_resources),
.id = PLATFORM_DEVID_NONE,
}
};
static int ioc3_led_setup(struct ioc3_priv_data *ipd)
{
int ret;
ret = mfd_add_devices(&ipd->pdev->dev, 0, ioc3_led_cells,
ARRAY_SIZE(ioc3_led_cells),
&ipd->pdev->resource[0], 0, ipd->domain);
if (ret)
dev_err(&ipd->pdev->dev, "Failed to add LED subdev\n");
return ret;
}
static int ip27_baseio_setup(struct ioc3_priv_data *ipd)
{
int ret, io_irq;
io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
PCI_INTERRUPT_INTB);
ret = ioc3_irq_domain_setup(ipd, io_irq);
if (ret)
return ret;
ret = ioc3_eth_setup(ipd);
if (ret)
return ret;
ret = ioc3_serial_setup(ipd);
if (ret)
return ret;
return ioc3_m48t35_setup(ipd);
}
static int ip27_baseio6g_setup(struct ioc3_priv_data *ipd)
{
int ret, io_irq;
io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
PCI_INTERRUPT_INTB);
ret = ioc3_irq_domain_setup(ipd, io_irq);
if (ret)
return ret;
ret = ioc3_eth_setup(ipd);
if (ret)
return ret;
ret = ioc3_serial_setup(ipd);
if (ret)
return ret;
ret = ioc3_m48t35_setup(ipd);
if (ret)
return ret;
return ioc3_kbd_setup(ipd);
}
static int ip27_mio_setup(struct ioc3_priv_data *ipd)
{
int ret;
ret = ioc3_irq_domain_setup(ipd, ipd->pdev->irq);
if (ret)
return ret;
ret = ioc3_serial_setup(ipd);
if (ret)
return ret;
return ioc3_kbd_setup(ipd);
}
static int ip30_sysboard_setup(struct ioc3_priv_data *ipd)
{
int ret, io_irq;
io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
PCI_INTERRUPT_INTB);
ret = ioc3_irq_domain_setup(ipd, io_irq);
if (ret)
return ret;
ret = ioc3_eth_setup(ipd);
if (ret)
return ret;
ret = ioc3_serial_setup(ipd);
if (ret)
return ret;
ret = ioc3_kbd_setup(ipd);
if (ret)
return ret;
ret = ioc3_ds1685_setup(ipd);
if (ret)
return ret;
return ioc3_led_setup(ipd);
}
static int ioc3_menet_setup(struct ioc3_priv_data *ipd)
{
int ret, io_irq;
io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
PCI_INTERRUPT_INTB);
ret = ioc3_irq_domain_setup(ipd, io_irq);
if (ret)
return ret;
ret = ioc3_eth_setup(ipd);
if (ret)
return ret;
return ioc3_serial_setup(ipd);
}
static int ioc3_menet4_setup(struct ioc3_priv_data *ipd)
{
return ioc3_eth_setup(ipd);
}
static int ioc3_cad_duo_setup(struct ioc3_priv_data *ipd)
{
int ret, io_irq;
io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
PCI_INTERRUPT_INTB);
ret = ioc3_irq_domain_setup(ipd, io_irq);
if (ret)
return ret;
ret = ioc3_eth_setup(ipd);
if (ret)
return ret;
return ioc3_kbd_setup(ipd);
}
/* Helper macro for filling ioc3_info array */
#define IOC3_SID(_name, _sid, _setup) \
{ \
.name = _name, \
.sid = PCI_VENDOR_ID_SGI | (IOC3_SUBSYS_ ## _sid << 16), \
.setup = _setup, \
}
static struct {
const char *name;
u32 sid;
int (*setup)(struct ioc3_priv_data *ipd);
} ioc3_infos[] = {
IOC3_SID("IP27 BaseIO6G", IP27_BASEIO6G, &ip27_baseio6g_setup),
IOC3_SID("IP27 MIO", IP27_MIO, &ip27_mio_setup),
IOC3_SID("IP27 BaseIO", IP27_BASEIO, &ip27_baseio_setup),
IOC3_SID("IP29 System Board", IP29_SYSBOARD, &ip27_baseio6g_setup),
IOC3_SID("IP30 System Board", IP30_SYSBOARD, &ip30_sysboard_setup),
IOC3_SID("MENET", MENET, &ioc3_menet_setup),
IOC3_SID("MENET4", MENET4, &ioc3_menet4_setup)
};
#undef IOC3_SID
static int ioc3_setup(struct ioc3_priv_data *ipd)
{
u32 sid;
int i;
/* Clear IRQs */
writel(~0, &ipd->regs->sio_iec);
writel(~0, &ipd->regs->sio_ir);
writel(0, &ipd->regs->eth.eier);
writel(~0, &ipd->regs->eth.eisr);
/* Read subsystem vendor id and subsystem id */
pci_read_config_dword(ipd->pdev, PCI_SUBSYSTEM_VENDOR_ID, &sid);
for (i = 0; i < ARRAY_SIZE(ioc3_infos); i++)
if (sid == ioc3_infos[i].sid) {
pr_info("ioc3: %s\n", ioc3_infos[i].name);
return ioc3_infos[i].setup(ipd);
}
/* Treat everything not identified by PCI subid as CAD DUO */
pr_info("ioc3: CAD DUO\n");
return ioc3_cad_duo_setup(ipd);
}
static int ioc3_mfd_probe(struct pci_dev *pdev,
const struct pci_device_id *pci_id)
{
struct ioc3_priv_data *ipd;
struct ioc3 __iomem *regs;
int ret;
ret = pci_enable_device(pdev);
if (ret)
return ret;
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, IOC3_LATENCY);
pci_set_master(pdev);
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
if (ret) {
pr_err("%s: No usable DMA configuration, aborting.\n",
pci_name(pdev));
goto out_disable_device;
}
/* Set up per-IOC3 data */
ipd = devm_kzalloc(&pdev->dev, sizeof(struct ioc3_priv_data),
GFP_KERNEL);
if (!ipd) {
ret = -ENOMEM;
goto out_disable_device;
}
ipd->pdev = pdev;
/*
* Map all IOC3 registers. These are shared between subdevices
* so the main IOC3 module manages them.
*/
regs = pci_ioremap_bar(pdev, 0);
if (!regs) {
dev_warn(&pdev->dev, "ioc3: Unable to remap PCI BAR for %s.\n",
pci_name(pdev));
ret = -ENOMEM;
goto out_disable_device;
}
ipd->regs = regs;
/* Track PCI-device specific data */
pci_set_drvdata(pdev, ipd);
ret = ioc3_setup(ipd);
if (ret) {
/* Remove all already added MFD devices */
mfd_remove_devices(&ipd->pdev->dev);
if (ipd->domain) {
struct fwnode_handle *fn = ipd->domain->fwnode;
irq_domain_remove(ipd->domain);
irq_domain_free_fwnode(fn);
free_irq(ipd->domain_irq, (void *)ipd);
}
pci_iounmap(pdev, regs);
goto out_disable_device;
}
return 0;
out_disable_device:
pci_disable_device(pdev);
return ret;
}
static void ioc3_mfd_remove(struct pci_dev *pdev)
{
struct ioc3_priv_data *ipd;
ipd = pci_get_drvdata(pdev);
/* Clear and disable all IRQs */
writel(~0, &ipd->regs->sio_iec);
writel(~0, &ipd->regs->sio_ir);
/* Release resources */
mfd_remove_devices(&ipd->pdev->dev);
if (ipd->domain) {
struct fwnode_handle *fn = ipd->domain->fwnode;
irq_domain_remove(ipd->domain);
irq_domain_free_fwnode(fn);
free_irq(ipd->domain_irq, (void *)ipd);
}
pci_iounmap(pdev, ipd->regs);
pci_disable_device(pdev);
}
static struct pci_device_id ioc3_mfd_id_table[] = {
{ PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, ioc3_mfd_id_table);
static struct pci_driver ioc3_mfd_driver = {
.name = "IOC3",
.id_table = ioc3_mfd_id_table,
.probe = ioc3_mfd_probe,
.remove = ioc3_mfd_remove,
};
module_pci_driver(ioc3_mfd_driver);
MODULE_AUTHOR("Thomas Bogendoerfer <[email protected]>");
MODULE_DESCRIPTION("SGI IOC3 MFD driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/ioc3.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm831x-irq.c -- Interrupt controller support for Wolfson WM831x PMICs
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/mfd/wm831x/core.h>
#include <linux/mfd/wm831x/pdata.h>
#include <linux/mfd/wm831x/gpio.h>
#include <linux/mfd/wm831x/irq.h>
#include <linux/delay.h>
struct wm831x_irq_data {
int primary;
int reg;
int mask;
};
static struct wm831x_irq_data wm831x_irqs[] = {
[WM831X_IRQ_TEMP_THW] = {
.primary = WM831X_TEMP_INT,
.reg = 1,
.mask = WM831X_TEMP_THW_EINT,
},
[WM831X_IRQ_GPIO_1] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP1_EINT,
},
[WM831X_IRQ_GPIO_2] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP2_EINT,
},
[WM831X_IRQ_GPIO_3] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP3_EINT,
},
[WM831X_IRQ_GPIO_4] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP4_EINT,
},
[WM831X_IRQ_GPIO_5] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP5_EINT,
},
[WM831X_IRQ_GPIO_6] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP6_EINT,
},
[WM831X_IRQ_GPIO_7] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP7_EINT,
},
[WM831X_IRQ_GPIO_8] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP8_EINT,
},
[WM831X_IRQ_GPIO_9] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP9_EINT,
},
[WM831X_IRQ_GPIO_10] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP10_EINT,
},
[WM831X_IRQ_GPIO_11] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP11_EINT,
},
[WM831X_IRQ_GPIO_12] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP12_EINT,
},
[WM831X_IRQ_GPIO_13] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP13_EINT,
},
[WM831X_IRQ_GPIO_14] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP14_EINT,
},
[WM831X_IRQ_GPIO_15] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP15_EINT,
},
[WM831X_IRQ_GPIO_16] = {
.primary = WM831X_GP_INT,
.reg = 5,
.mask = WM831X_GP16_EINT,
},
[WM831X_IRQ_ON] = {
.primary = WM831X_ON_PIN_INT,
.reg = 1,
.mask = WM831X_ON_PIN_EINT,
},
[WM831X_IRQ_PPM_SYSLO] = {
.primary = WM831X_PPM_INT,
.reg = 1,
.mask = WM831X_PPM_SYSLO_EINT,
},
[WM831X_IRQ_PPM_PWR_SRC] = {
.primary = WM831X_PPM_INT,
.reg = 1,
.mask = WM831X_PPM_PWR_SRC_EINT,
},
[WM831X_IRQ_PPM_USB_CURR] = {
.primary = WM831X_PPM_INT,
.reg = 1,
.mask = WM831X_PPM_USB_CURR_EINT,
},
[WM831X_IRQ_WDOG_TO] = {
.primary = WM831X_WDOG_INT,
.reg = 1,
.mask = WM831X_WDOG_TO_EINT,
},
[WM831X_IRQ_RTC_PER] = {
.primary = WM831X_RTC_INT,
.reg = 1,
.mask = WM831X_RTC_PER_EINT,
},
[WM831X_IRQ_RTC_ALM] = {
.primary = WM831X_RTC_INT,
.reg = 1,
.mask = WM831X_RTC_ALM_EINT,
},
[WM831X_IRQ_CHG_BATT_HOT] = {
.primary = WM831X_CHG_INT,
.reg = 2,
.mask = WM831X_CHG_BATT_HOT_EINT,
},
[WM831X_IRQ_CHG_BATT_COLD] = {
.primary = WM831X_CHG_INT,
.reg = 2,
.mask = WM831X_CHG_BATT_COLD_EINT,
},
[WM831X_IRQ_CHG_BATT_FAIL] = {
.primary = WM831X_CHG_INT,
.reg = 2,
.mask = WM831X_CHG_BATT_FAIL_EINT,
},
[WM831X_IRQ_CHG_OV] = {
.primary = WM831X_CHG_INT,
.reg = 2,
.mask = WM831X_CHG_OV_EINT,
},
[WM831X_IRQ_CHG_END] = {
.primary = WM831X_CHG_INT,
.reg = 2,
.mask = WM831X_CHG_END_EINT,
},
[WM831X_IRQ_CHG_TO] = {
.primary = WM831X_CHG_INT,
.reg = 2,
.mask = WM831X_CHG_TO_EINT,
},
[WM831X_IRQ_CHG_MODE] = {
.primary = WM831X_CHG_INT,
.reg = 2,
.mask = WM831X_CHG_MODE_EINT,
},
[WM831X_IRQ_CHG_START] = {
.primary = WM831X_CHG_INT,
.reg = 2,
.mask = WM831X_CHG_START_EINT,
},
[WM831X_IRQ_TCHDATA] = {
.primary = WM831X_TCHDATA_INT,
.reg = 1,
.mask = WM831X_TCHDATA_EINT,
},
[WM831X_IRQ_TCHPD] = {
.primary = WM831X_TCHPD_INT,
.reg = 1,
.mask = WM831X_TCHPD_EINT,
},
[WM831X_IRQ_AUXADC_DATA] = {
.primary = WM831X_AUXADC_INT,
.reg = 1,
.mask = WM831X_AUXADC_DATA_EINT,
},
[WM831X_IRQ_AUXADC_DCOMP1] = {
.primary = WM831X_AUXADC_INT,
.reg = 1,
.mask = WM831X_AUXADC_DCOMP1_EINT,
},
[WM831X_IRQ_AUXADC_DCOMP2] = {
.primary = WM831X_AUXADC_INT,
.reg = 1,
.mask = WM831X_AUXADC_DCOMP2_EINT,
},
[WM831X_IRQ_AUXADC_DCOMP3] = {
.primary = WM831X_AUXADC_INT,
.reg = 1,
.mask = WM831X_AUXADC_DCOMP3_EINT,
},
[WM831X_IRQ_AUXADC_DCOMP4] = {
.primary = WM831X_AUXADC_INT,
.reg = 1,
.mask = WM831X_AUXADC_DCOMP4_EINT,
},
[WM831X_IRQ_CS1] = {
.primary = WM831X_CS_INT,
.reg = 2,
.mask = WM831X_CS1_EINT,
},
[WM831X_IRQ_CS2] = {
.primary = WM831X_CS_INT,
.reg = 2,
.mask = WM831X_CS2_EINT,
},
[WM831X_IRQ_HC_DC1] = {
.primary = WM831X_HC_INT,
.reg = 4,
.mask = WM831X_HC_DC1_EINT,
},
[WM831X_IRQ_HC_DC2] = {
.primary = WM831X_HC_INT,
.reg = 4,
.mask = WM831X_HC_DC2_EINT,
},
[WM831X_IRQ_UV_LDO1] = {
.primary = WM831X_UV_INT,
.reg = 3,
.mask = WM831X_UV_LDO1_EINT,
},
[WM831X_IRQ_UV_LDO2] = {
.primary = WM831X_UV_INT,
.reg = 3,
.mask = WM831X_UV_LDO2_EINT,
},
[WM831X_IRQ_UV_LDO3] = {
.primary = WM831X_UV_INT,
.reg = 3,
.mask = WM831X_UV_LDO3_EINT,
},
[WM831X_IRQ_UV_LDO4] = {
.primary = WM831X_UV_INT,
.reg = 3,
.mask = WM831X_UV_LDO4_EINT,
},
[WM831X_IRQ_UV_LDO5] = {
.primary = WM831X_UV_INT,
.reg = 3,
.mask = WM831X_UV_LDO5_EINT,
},
[WM831X_IRQ_UV_LDO6] = {
.primary = WM831X_UV_INT,
.reg = 3,
.mask = WM831X_UV_LDO6_EINT,
},
[WM831X_IRQ_UV_LDO7] = {
.primary = WM831X_UV_INT,
.reg = 3,
.mask = WM831X_UV_LDO7_EINT,
},
[WM831X_IRQ_UV_LDO8] = {
.primary = WM831X_UV_INT,
.reg = 3,
.mask = WM831X_UV_LDO8_EINT,
},
[WM831X_IRQ_UV_LDO9] = {
.primary = WM831X_UV_INT,
.reg = 3,
.mask = WM831X_UV_LDO9_EINT,
},
[WM831X_IRQ_UV_LDO10] = {
.primary = WM831X_UV_INT,
.reg = 3,
.mask = WM831X_UV_LDO10_EINT,
},
[WM831X_IRQ_UV_DC1] = {
.primary = WM831X_UV_INT,
.reg = 4,
.mask = WM831X_UV_DC1_EINT,
},
[WM831X_IRQ_UV_DC2] = {
.primary = WM831X_UV_INT,
.reg = 4,
.mask = WM831X_UV_DC2_EINT,
},
[WM831X_IRQ_UV_DC3] = {
.primary = WM831X_UV_INT,
.reg = 4,
.mask = WM831X_UV_DC3_EINT,
},
[WM831X_IRQ_UV_DC4] = {
.primary = WM831X_UV_INT,
.reg = 4,
.mask = WM831X_UV_DC4_EINT,
},
};
static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
{
return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
}
static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x,
int irq)
{
return &wm831x_irqs[irq];
}
static void wm831x_irq_lock(struct irq_data *data)
{
struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
mutex_lock(&wm831x->irq_lock);
}
static void wm831x_irq_sync_unlock(struct irq_data *data)
{
struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
int i;
for (i = 0; i < ARRAY_SIZE(wm831x->gpio_update); i++) {
if (wm831x->gpio_update[i]) {
wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + i,
WM831X_GPN_INT_MODE | WM831X_GPN_POL,
wm831x->gpio_update[i]);
wm831x->gpio_update[i] = 0;
}
}
for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
/* If there's been a change in the mask write it back
* to the hardware. */
if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n",
WM831X_INTERRUPT_STATUS_1_MASK + i,
wm831x->irq_masks_cur[i]);
wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
wm831x_reg_write(wm831x,
WM831X_INTERRUPT_STATUS_1_MASK + i,
wm831x->irq_masks_cur[i]);
}
}
mutex_unlock(&wm831x->irq_lock);
}
static void wm831x_irq_enable(struct irq_data *data)
{
struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
data->hwirq);
wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
}
static void wm831x_irq_disable(struct irq_data *data)
{
struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
data->hwirq);
wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
}
static int wm831x_irq_set_type(struct irq_data *data, unsigned int type)
{
struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
int irq;
irq = data->hwirq;
if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11) {
/* Ignore internal-only IRQs */
if (irq >= 0 && irq < WM831X_NUM_IRQS)
return 0;
else
return -EINVAL;
}
/* Rebase the IRQ into the GPIO range so we've got a sensible array
* index.
*/
irq -= WM831X_IRQ_GPIO_1;
/* We set the high bit to flag that we need an update; don't
* do the update here as we can be called with the bus lock
* held.
*/
wm831x->gpio_level_low[irq] = false;
wm831x->gpio_level_high[irq] = false;
switch (type) {
case IRQ_TYPE_EDGE_BOTH:
wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_INT_MODE;
break;
case IRQ_TYPE_EDGE_RISING:
wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
break;
case IRQ_TYPE_EDGE_FALLING:
wm831x->gpio_update[irq] = 0x10000;
break;
case IRQ_TYPE_LEVEL_HIGH:
wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
wm831x->gpio_level_high[irq] = true;
break;
case IRQ_TYPE_LEVEL_LOW:
wm831x->gpio_update[irq] = 0x10000;
wm831x->gpio_level_low[irq] = true;
break;
default:
return -EINVAL;
}
return 0;
}
static struct irq_chip wm831x_irq_chip = {
.name = "wm831x",
.irq_bus_lock = wm831x_irq_lock,
.irq_bus_sync_unlock = wm831x_irq_sync_unlock,
.irq_disable = wm831x_irq_disable,
.irq_enable = wm831x_irq_enable,
.irq_set_type = wm831x_irq_set_type,
};
/* The processing of the primary interrupt occurs in a thread so that
* we can interact with the device over I2C or SPI. */
static irqreturn_t wm831x_irq_thread(int irq, void *data)
{
struct wm831x *wm831x = data;
unsigned int i;
int primary, status_addr, ret;
int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
int read[WM831X_NUM_IRQ_REGS] = { 0 };
int *status;
primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
if (primary < 0) {
dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
primary);
goto out;
}
/* The touch interrupts are visible in the primary register as
* an optimisation; open code this to avoid complicating the
* main handling loop and so we can also skip iterating the
* descriptors.
*/
if (primary & WM831X_TCHPD_INT)
handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
WM831X_IRQ_TCHPD));
if (primary & WM831X_TCHDATA_INT)
handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
WM831X_IRQ_TCHDATA));
primary &= ~(WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT);
for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
int offset = wm831x_irqs[i].reg - 1;
if (!(primary & wm831x_irqs[i].primary))
continue;
status = &status_regs[offset];
/* Hopefully there should only be one register to read
* each time otherwise we ought to do a block read. */
if (!read[offset]) {
status_addr = irq_data_to_status_reg(&wm831x_irqs[i]);
*status = wm831x_reg_read(wm831x, status_addr);
if (*status < 0) {
dev_err(wm831x->dev,
"Failed to read IRQ status: %d\n",
*status);
goto out;
}
read[offset] = 1;
/* Ignore any bits that we don't think are masked */
*status &= ~wm831x->irq_masks_cur[offset];
/* Acknowledge now so we don't miss
* notifications while we handle.
*/
wm831x_reg_write(wm831x, status_addr, *status);
}
if (*status & wm831x_irqs[i].mask)
handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
i));
/* Simulate an edge triggered IRQ by polling the input
* status. This is sucky but improves interoperability.
*/
if (primary == WM831X_GP_INT &&
wm831x->gpio_level_high[i - WM831X_IRQ_GPIO_1]) {
ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
while (ret & 1 << (i - WM831X_IRQ_GPIO_1)) {
handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
i));
ret = wm831x_reg_read(wm831x,
WM831X_GPIO_LEVEL);
}
}
if (primary == WM831X_GP_INT &&
wm831x->gpio_level_low[i - WM831X_IRQ_GPIO_1]) {
ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
while (!(ret & 1 << (i - WM831X_IRQ_GPIO_1))) {
handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
i));
ret = wm831x_reg_read(wm831x,
WM831X_GPIO_LEVEL);
}
}
}
out:
return IRQ_HANDLED;
}
static int wm831x_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
irq_set_chip_data(virq, h->host_data);
irq_set_chip_and_handler(virq, &wm831x_irq_chip, handle_edge_irq);
irq_set_nested_thread(virq, 1);
irq_set_noprobe(virq);
return 0;
}
static const struct irq_domain_ops wm831x_irq_domain_ops = {
.map = wm831x_irq_map,
.xlate = irq_domain_xlate_twocell,
};
int wm831x_irq_init(struct wm831x *wm831x, int irq)
{
struct wm831x_pdata *pdata = &wm831x->pdata;
struct irq_domain *domain;
int i, ret, irq_base;
mutex_init(&wm831x->irq_lock);
/* Mask the individual interrupt sources */
for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
wm831x->irq_masks_cur[i] = 0xffff;
wm831x->irq_masks_cache[i] = 0xffff;
wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
0xffff);
}
/* Try to dynamically allocate IRQs if no base is specified */
if (pdata->irq_base) {
irq_base = irq_alloc_descs(pdata->irq_base, 0,
WM831X_NUM_IRQS, 0);
if (irq_base < 0) {
dev_warn(wm831x->dev, "Failed to allocate IRQs: %d\n",
irq_base);
irq_base = 0;
}
} else {
irq_base = 0;
}
if (irq_base)
domain = irq_domain_add_legacy(wm831x->dev->of_node,
ARRAY_SIZE(wm831x_irqs),
irq_base, 0,
&wm831x_irq_domain_ops,
wm831x);
else
domain = irq_domain_add_linear(wm831x->dev->of_node,
ARRAY_SIZE(wm831x_irqs),
&wm831x_irq_domain_ops,
wm831x);
if (!domain) {
dev_warn(wm831x->dev, "Failed to allocate IRQ domain\n");
return -EINVAL;
}
if (pdata->irq_cmos)
i = 0;
else
i = WM831X_IRQ_OD;
wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
WM831X_IRQ_OD, i);
wm831x->irq = irq;
wm831x->irq_domain = domain;
if (irq) {
/* Try to flag /IRQ as a wake source; there are a number of
* unconditional wake sources in the PMIC so this isn't
* conditional but we don't actually care *too* much if it
* fails.
*/
ret = enable_irq_wake(irq);
if (ret != 0) {
dev_warn(wm831x->dev,
"Can't enable IRQ as wake source: %d\n",
ret);
}
ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
"wm831x", wm831x);
if (ret != 0) {
dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
irq, ret);
return ret;
}
} else {
dev_warn(wm831x->dev,
"No interrupt specified - functionality limited\n");
}
/* Enable top level interrupts, we mask at secondary level */
wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
return 0;
}
void wm831x_irq_exit(struct wm831x *wm831x)
{
if (wm831x->irq)
free_irq(wm831x->irq, wm831x);
}
| linux-master | drivers/mfd/wm831x-irq.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* RDC321x MFD southbridge driver
*
* Copyright (C) 2007-2010 Florian Fainelli <[email protected]>
* Copyright (C) 2010 Bernhard Loos <[email protected]>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/mfd/core.h>
#include <linux/mfd/rdc321x.h>
static struct rdc321x_wdt_pdata rdc321x_wdt_pdata;
static const struct resource rdc321x_wdt_resource[] = {
{
.name = "wdt-reg",
.start = RDC321X_WDT_CTRL,
.end = RDC321X_WDT_CTRL + 0x3,
.flags = IORESOURCE_IO,
}
};
static struct rdc321x_gpio_pdata rdc321x_gpio_pdata = {
.max_gpios = RDC321X_NUM_GPIO,
};
static const struct resource rdc321x_gpio_resources[] = {
{
.name = "gpio-reg1",
.start = RDC321X_GPIO_CTRL_REG1,
.end = RDC321X_GPIO_CTRL_REG1 + 0x7,
.flags = IORESOURCE_IO,
}, {
.name = "gpio-reg2",
.start = RDC321X_GPIO_CTRL_REG2,
.end = RDC321X_GPIO_CTRL_REG2 + 0x7,
.flags = IORESOURCE_IO,
}
};
static const struct mfd_cell rdc321x_sb_cells[] = {
{
.name = "rdc321x-wdt",
.resources = rdc321x_wdt_resource,
.num_resources = ARRAY_SIZE(rdc321x_wdt_resource),
.platform_data = &rdc321x_wdt_pdata,
.pdata_size = sizeof(rdc321x_wdt_pdata),
}, {
.name = "rdc321x-gpio",
.resources = rdc321x_gpio_resources,
.num_resources = ARRAY_SIZE(rdc321x_gpio_resources),
.platform_data = &rdc321x_gpio_pdata,
.pdata_size = sizeof(rdc321x_gpio_pdata),
},
};
static int rdc321x_sb_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
int err;
err = pci_enable_device(pdev);
if (err) {
dev_err(&pdev->dev, "failed to enable device\n");
return err;
}
rdc321x_gpio_pdata.sb_pdev = pdev;
rdc321x_wdt_pdata.sb_pdev = pdev;
return devm_mfd_add_devices(&pdev->dev, -1,
rdc321x_sb_cells,
ARRAY_SIZE(rdc321x_sb_cells),
NULL, 0, NULL);
}
static const struct pci_device_id rdc321x_sb_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_RDC, PCI_DEVICE_ID_RDC_R6030) },
{}
};
MODULE_DEVICE_TABLE(pci, rdc321x_sb_table);
static struct pci_driver rdc321x_sb_driver = {
.name = "RDC321x Southbridge",
.id_table = rdc321x_sb_table,
.probe = rdc321x_sb_probe,
};
module_pci_driver(rdc321x_sb_driver);
MODULE_AUTHOR("Florian Fainelli <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("RDC R-321x MFD southbridge driver");
| linux-master | drivers/mfd/rdc321x-southbridge.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* MFD core driver for the Richtek RT5033.
*
* RT5033 comprises multiple sub-devices switcing charger, fuel gauge,
* flash LED, current source, LDO and BUCK regulators.
*
* Copyright (C) 2014 Samsung Electronics, Co., Ltd.
* Author: Beomho Seo <[email protected]>
*/
#include <linux/err.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mfd/rt5033.h>
#include <linux/mfd/rt5033-private.h>
static const struct regmap_irq rt5033_irqs[] = {
{ .mask = RT5033_PMIC_IRQ_BUCKOCP, },
{ .mask = RT5033_PMIC_IRQ_BUCKLV, },
{ .mask = RT5033_PMIC_IRQ_SAFELDOLV, },
{ .mask = RT5033_PMIC_IRQ_LDOLV, },
{ .mask = RT5033_PMIC_IRQ_OT, },
{ .mask = RT5033_PMIC_IRQ_VDDA_UV, },
};
static const struct regmap_irq_chip rt5033_irq_chip = {
.name = "rt5033",
.status_base = RT5033_REG_PMIC_IRQ_STAT,
.unmask_base = RT5033_REG_PMIC_IRQ_CTRL,
.num_regs = 1,
.irqs = rt5033_irqs,
.num_irqs = ARRAY_SIZE(rt5033_irqs),
};
static const struct mfd_cell rt5033_devs[] = {
{ .name = "rt5033-regulator", },
{
.name = "rt5033-charger",
.of_compatible = "richtek,rt5033-charger",
}, {
.name = "rt5033-led",
.of_compatible = "richtek,rt5033-led",
},
};
static const struct regmap_config rt5033_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = RT5033_REG_END,
};
static int rt5033_i2c_probe(struct i2c_client *i2c)
{
struct rt5033_dev *rt5033;
unsigned int dev_id, chip_rev;
int ret;
rt5033 = devm_kzalloc(&i2c->dev, sizeof(*rt5033), GFP_KERNEL);
if (!rt5033)
return -ENOMEM;
i2c_set_clientdata(i2c, rt5033);
rt5033->dev = &i2c->dev;
rt5033->irq = i2c->irq;
rt5033->wakeup = true;
rt5033->regmap = devm_regmap_init_i2c(i2c, &rt5033_regmap_config);
if (IS_ERR(rt5033->regmap)) {
dev_err(&i2c->dev, "Failed to allocate register map.\n");
return PTR_ERR(rt5033->regmap);
}
ret = regmap_read(rt5033->regmap, RT5033_REG_DEVICE_ID, &dev_id);
if (ret) {
dev_err(&i2c->dev, "Device not found\n");
return -ENODEV;
}
chip_rev = dev_id & RT5033_CHIP_REV_MASK;
dev_info(&i2c->dev, "Device found (rev. %d)\n", chip_rev);
ret = regmap_add_irq_chip(rt5033->regmap, rt5033->irq,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
0, &rt5033_irq_chip, &rt5033->irq_data);
if (ret) {
dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
rt5033->irq, ret);
return ret;
}
ret = devm_mfd_add_devices(rt5033->dev, -1, rt5033_devs,
ARRAY_SIZE(rt5033_devs), NULL, 0,
regmap_irq_get_domain(rt5033->irq_data));
if (ret < 0) {
dev_err(&i2c->dev, "Failed to add RT5033 child devices.\n");
return ret;
}
device_init_wakeup(rt5033->dev, rt5033->wakeup);
return 0;
}
static const struct i2c_device_id rt5033_i2c_id[] = {
{ "rt5033", },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt5033_i2c_id);
static const struct of_device_id rt5033_dt_match[] = {
{ .compatible = "richtek,rt5033", },
{ }
};
MODULE_DEVICE_TABLE(of, rt5033_dt_match);
static struct i2c_driver rt5033_driver = {
.driver = {
.name = "rt5033",
.of_match_table = rt5033_dt_match,
},
.probe = rt5033_i2c_probe,
.id_table = rt5033_i2c_id,
};
module_i2c_driver(rt5033_driver);
MODULE_DESCRIPTION("Richtek RT5033 multi-function core driver");
MODULE_AUTHOR("Beomho Seo <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/rt5033.c |
// SPDX-License-Identifier: GPL-2.0
/*
* STM32 Low-Power Timer parent driver.
* Copyright (C) STMicroelectronics 2017
* Author: Fabrice Gasnier <[email protected]>
* Inspired by Benjamin Gaignard's stm32-timers driver
*/
#include <linux/mfd/stm32-lptimer.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#define STM32_LPTIM_MAX_REGISTER 0x3fc
static const struct regmap_config stm32_lptimer_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = sizeof(u32),
.max_register = STM32_LPTIM_MAX_REGISTER,
.fast_io = true,
};
static int stm32_lptimer_detect_encoder(struct stm32_lptimer *ddata)
{
u32 val;
int ret;
/*
* Quadrature encoder mode bit can only be written and read back when
* Low-Power Timer supports it.
*/
ret = regmap_update_bits(ddata->regmap, STM32_LPTIM_CFGR,
STM32_LPTIM_ENC, STM32_LPTIM_ENC);
if (ret)
return ret;
ret = regmap_read(ddata->regmap, STM32_LPTIM_CFGR, &val);
if (ret)
return ret;
ret = regmap_update_bits(ddata->regmap, STM32_LPTIM_CFGR,
STM32_LPTIM_ENC, 0);
if (ret)
return ret;
ddata->has_encoder = !!(val & STM32_LPTIM_ENC);
return 0;
}
static int stm32_lptimer_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct stm32_lptimer *ddata;
void __iomem *mmio;
int ret;
ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
mmio = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(mmio))
return PTR_ERR(mmio);
ddata->regmap = devm_regmap_init_mmio_clk(dev, "mux", mmio,
&stm32_lptimer_regmap_cfg);
if (IS_ERR(ddata->regmap))
return PTR_ERR(ddata->regmap);
ddata->clk = devm_clk_get(dev, NULL);
if (IS_ERR(ddata->clk))
return PTR_ERR(ddata->clk);
ret = stm32_lptimer_detect_encoder(ddata);
if (ret)
return ret;
platform_set_drvdata(pdev, ddata);
return devm_of_platform_populate(&pdev->dev);
}
static const struct of_device_id stm32_lptimer_of_match[] = {
{ .compatible = "st,stm32-lptimer", },
{},
};
MODULE_DEVICE_TABLE(of, stm32_lptimer_of_match);
static struct platform_driver stm32_lptimer_driver = {
.probe = stm32_lptimer_probe,
.driver = {
.name = "stm32-lptimer",
.of_match_table = stm32_lptimer_of_match,
},
};
module_platform_driver(stm32_lptimer_driver);
MODULE_AUTHOR("Fabrice Gasnier <[email protected]>");
MODULE_DESCRIPTION("STMicroelectronics STM32 Low-Power Timer");
MODULE_ALIAS("platform:stm32-lptimer");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/stm32-lptimer.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* AB8500 system control driver
*
* Copyright (C) ST-Ericsson SA 2010
* Author: Mattias Nilsson <[email protected]> for ST Ericsson.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/reboot.h>
#include <linux/signal.h>
#include <linux/power_supply.h>
#include <linux/mfd/abx500.h>
#include <linux/mfd/abx500/ab8500.h>
#include <linux/mfd/abx500/ab8500-sysctrl.h>
/* RtcCtrl bits */
#define AB8500_ALARM_MIN_LOW 0x08
#define AB8500_ALARM_MIN_MID 0x09
#define RTC_CTRL 0x0B
#define RTC_ALARM_ENABLE 0x4
static struct device *sysctrl_dev;
static void ab8500_power_off(void)
{
sigset_t old;
sigset_t all;
static const char * const pss[] = {"ab8500_ac", "pm2301", "ab8500_usb"};
int i;
bool charger_present = false;
union power_supply_propval val;
struct power_supply *psy;
int ret;
if (sysctrl_dev == NULL) {
pr_err("%s: sysctrl not initialized\n", __func__);
return;
}
/*
* If we have a charger connected and we're powering off,
* reboot into charge-only mode.
*/
for (i = 0; i < ARRAY_SIZE(pss); i++) {
psy = power_supply_get_by_name(pss[i]);
if (!psy)
continue;
ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_ONLINE,
&val);
power_supply_put(psy);
if (!ret && val.intval) {
charger_present = true;
break;
}
}
if (!charger_present)
goto shutdown;
/* Check if battery is known */
psy = power_supply_get_by_name("ab8500_btemp");
if (psy) {
ret = power_supply_get_property(psy,
POWER_SUPPLY_PROP_TECHNOLOGY, &val);
if (!ret && val.intval != POWER_SUPPLY_TECHNOLOGY_UNKNOWN) {
pr_info("Charger '%s' is connected with known battery",
pss[i]);
pr_info(" - Rebooting.\n");
machine_restart("charging");
}
power_supply_put(psy);
}
shutdown:
sigfillset(&all);
if (!sigprocmask(SIG_BLOCK, &all, &old)) {
(void)ab8500_sysctrl_set(AB8500_STW4500CTRL1,
AB8500_STW4500CTRL1_SWOFF |
AB8500_STW4500CTRL1_SWRESET4500N);
(void)sigprocmask(SIG_SETMASK, &old, NULL);
}
}
static inline bool valid_bank(u8 bank)
{
return ((bank == AB8500_SYS_CTRL1_BLOCK) ||
(bank == AB8500_SYS_CTRL2_BLOCK));
}
int ab8500_sysctrl_read(u16 reg, u8 *value)
{
u8 bank;
if (sysctrl_dev == NULL)
return -EPROBE_DEFER;
bank = (reg >> 8);
if (!valid_bank(bank))
return -EINVAL;
return abx500_get_register_interruptible(sysctrl_dev, bank,
(u8)(reg & 0xFF), value);
}
EXPORT_SYMBOL(ab8500_sysctrl_read);
int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value)
{
u8 bank;
if (sysctrl_dev == NULL)
return -EPROBE_DEFER;
bank = (reg >> 8);
if (!valid_bank(bank)) {
pr_err("invalid bank\n");
return -EINVAL;
}
return abx500_mask_and_set_register_interruptible(sysctrl_dev, bank,
(u8)(reg & 0xFF), mask, value);
}
EXPORT_SYMBOL(ab8500_sysctrl_write);
static int ab8500_sysctrl_probe(struct platform_device *pdev)
{
sysctrl_dev = &pdev->dev;
if (!pm_power_off)
pm_power_off = ab8500_power_off;
return 0;
}
static int ab8500_sysctrl_remove(struct platform_device *pdev)
{
sysctrl_dev = NULL;
if (pm_power_off == ab8500_power_off)
pm_power_off = NULL;
return 0;
}
static const struct of_device_id ab8500_sysctrl_match[] = {
{ .compatible = "stericsson,ab8500-sysctrl", },
{}
};
static struct platform_driver ab8500_sysctrl_driver = {
.driver = {
.name = "ab8500-sysctrl",
.of_match_table = ab8500_sysctrl_match,
},
.probe = ab8500_sysctrl_probe,
.remove = ab8500_sysctrl_remove,
};
static int __init ab8500_sysctrl_init(void)
{
return platform_driver_register(&ab8500_sysctrl_driver);
}
arch_initcall(ab8500_sysctrl_init);
| linux-master | drivers/mfd/ab8500-sysctrl.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Azoteq IQS620A/621/622/624/625 Multi-Function Sensors
*
* Copyright (C) 2019 Jeff LaBundy <[email protected]>
*
* These devices rely on application-specific register settings and calibration
* data developed in and exported from a suite of GUIs offered by the vendor. A
* separate tool converts the GUIs' ASCII-based output into a standard firmware
* file parsed by the driver.
*
* Link to datasheets and GUIs: https://www.azoteq.com/
*
* Link to conversion tool: https://github.com/jlabundy/iqs62x-h2bin.git
*/
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/firmware.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/mfd/core.h>
#include <linux/mfd/iqs62x.h>
#include <linux/module.h>
#include <linux/notifier.h>
#include <linux/of.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <asm/unaligned.h>
#define IQS62X_PROD_NUM 0x00
#define IQS62X_SYS_FLAGS 0x10
#define IQS620_HALL_FLAGS 0x16
#define IQS621_HALL_FLAGS 0x19
#define IQS622_HALL_FLAGS IQS621_HALL_FLAGS
#define IQS624_INTERVAL_NUM 0x18
#define IQS625_INTERVAL_NUM 0x12
#define IQS622_PROX_SETTINGS_4 0x48
#define IQS620_PROX_SETTINGS_4 0x50
#define IQS620_PROX_SETTINGS_4_SAR_EN BIT(7)
#define IQS621_ALS_CAL_DIV_LUX 0x82
#define IQS621_ALS_CAL_DIV_IR 0x83
#define IQS620_TEMP_CAL_MULT 0xC2
#define IQS620_TEMP_CAL_DIV 0xC3
#define IQS620_TEMP_CAL_OFFS 0xC4
#define IQS62X_SYS_SETTINGS 0xD0
#define IQS62X_SYS_SETTINGS_ACK_RESET BIT(6)
#define IQS62X_SYS_SETTINGS_EVENT_MODE BIT(5)
#define IQS62X_SYS_SETTINGS_CLK_DIV BIT(4)
#define IQS62X_SYS_SETTINGS_COMM_ATI BIT(3)
#define IQS62X_SYS_SETTINGS_REDO_ATI BIT(1)
#define IQS62X_PWR_SETTINGS 0xD2
#define IQS62X_PWR_SETTINGS_DIS_AUTO BIT(5)
#define IQS62X_PWR_SETTINGS_PWR_MODE_MASK (BIT(4) | BIT(3))
#define IQS62X_PWR_SETTINGS_PWR_MODE_HALT (BIT(4) | BIT(3))
#define IQS62X_PWR_SETTINGS_PWR_MODE_NORM 0
#define IQS62X_OTP_CMD 0xF0
#define IQS62X_OTP_CMD_FG3 0x13
#define IQS62X_OTP_DATA 0xF1
#define IQS62X_MAX_REG 0xFF
#define IQS62X_HALL_CAL_MASK GENMASK(3, 0)
#define IQS62X_FW_REC_TYPE_INFO 0
#define IQS62X_FW_REC_TYPE_PROD 1
#define IQS62X_FW_REC_TYPE_HALL 2
#define IQS62X_FW_REC_TYPE_MASK 3
#define IQS62X_FW_REC_TYPE_DATA 4
#define IQS62X_ATI_STARTUP_MS 350
#define IQS62X_FILT_SETTLE_MS 250
struct iqs62x_fw_rec {
u8 type;
u8 addr;
u8 len;
u8 data;
} __packed;
struct iqs62x_fw_blk {
struct list_head list;
u8 addr;
u8 mask;
u8 len;
u8 data[];
};
struct iqs62x_info {
u8 prod_num;
u8 sw_num;
u8 hw_num;
} __packed;
static int iqs62x_dev_init(struct iqs62x_core *iqs62x)
{
struct iqs62x_fw_blk *fw_blk;
unsigned int val;
int ret;
list_for_each_entry(fw_blk, &iqs62x->fw_blk_head, list) {
/*
* In case ATI is in progress, wait for it to complete before
* lowering the core clock frequency.
*/
if (fw_blk->addr == IQS62X_SYS_SETTINGS &&
*fw_blk->data & IQS62X_SYS_SETTINGS_CLK_DIV)
msleep(IQS62X_ATI_STARTUP_MS);
if (fw_blk->mask)
ret = regmap_update_bits(iqs62x->regmap, fw_blk->addr,
fw_blk->mask, *fw_blk->data);
else
ret = regmap_raw_write(iqs62x->regmap, fw_blk->addr,
fw_blk->data, fw_blk->len);
if (ret)
return ret;
}
switch (iqs62x->dev_desc->prod_num) {
case IQS620_PROD_NUM:
case IQS622_PROD_NUM:
ret = regmap_read(iqs62x->regmap,
iqs62x->dev_desc->prox_settings, &val);
if (ret)
return ret;
if (val & IQS620_PROX_SETTINGS_4_SAR_EN)
iqs62x->ui_sel = IQS62X_UI_SAR1;
fallthrough;
case IQS621_PROD_NUM:
ret = regmap_write(iqs62x->regmap, IQS620_GLBL_EVENT_MASK,
IQS620_GLBL_EVENT_MASK_PMU |
iqs62x->dev_desc->prox_mask |
iqs62x->dev_desc->sar_mask |
iqs62x->dev_desc->hall_mask |
iqs62x->dev_desc->hyst_mask |
iqs62x->dev_desc->temp_mask |
iqs62x->dev_desc->als_mask |
iqs62x->dev_desc->ir_mask);
if (ret)
return ret;
break;
default:
ret = regmap_write(iqs62x->regmap, IQS624_HALL_UI,
IQS624_HALL_UI_WHL_EVENT |
IQS624_HALL_UI_INT_EVENT |
IQS624_HALL_UI_AUTO_CAL);
if (ret)
return ret;
/*
* The IQS625 default interval divider is below the minimum
* permissible value, and the datasheet mandates that it is
* corrected during initialization (unless an updated value
* has already been provided by firmware).
*
* To protect against an unacceptably low user-entered value
* stored in the firmware, the same check is extended to the
* IQS624 as well.
*/
ret = regmap_read(iqs62x->regmap, IQS624_INTERVAL_DIV, &val);
if (ret)
return ret;
if (val >= iqs62x->dev_desc->interval_div)
break;
ret = regmap_write(iqs62x->regmap, IQS624_INTERVAL_DIV,
iqs62x->dev_desc->interval_div);
if (ret)
return ret;
}
/*
* Place the device in streaming mode at first so as not to miss the
* limited number of interrupts that would otherwise occur after ATI
* completes. The device is subsequently placed in event mode by the
* interrupt handler.
*
* In the meantime, mask interrupts during ATI to prevent the device
* from soliciting I2C traffic until the noise-sensitive ATI process
* is complete.
*/
ret = regmap_update_bits(iqs62x->regmap, IQS62X_SYS_SETTINGS,
IQS62X_SYS_SETTINGS_ACK_RESET |
IQS62X_SYS_SETTINGS_EVENT_MODE |
IQS62X_SYS_SETTINGS_COMM_ATI |
IQS62X_SYS_SETTINGS_REDO_ATI,
IQS62X_SYS_SETTINGS_ACK_RESET |
IQS62X_SYS_SETTINGS_REDO_ATI);
if (ret)
return ret;
/*
* The following delay gives the device time to deassert its RDY output
* in case a communication window was open while the REDO_ATI field was
* written. This prevents an interrupt from being serviced prematurely.
*/
usleep_range(5000, 5100);
return 0;
}
static int iqs62x_firmware_parse(struct iqs62x_core *iqs62x,
const struct firmware *fw)
{
struct i2c_client *client = iqs62x->client;
struct iqs62x_fw_rec *fw_rec;
struct iqs62x_fw_blk *fw_blk;
unsigned int val;
size_t pos = 0;
int ret = 0;
u8 mask, len, *data;
u8 hall_cal_index = 0;
while (pos < fw->size) {
if (pos + sizeof(*fw_rec) > fw->size) {
ret = -EINVAL;
break;
}
fw_rec = (struct iqs62x_fw_rec *)(fw->data + pos);
pos += sizeof(*fw_rec);
if (pos + fw_rec->len - 1 > fw->size) {
ret = -EINVAL;
break;
}
pos += fw_rec->len - 1;
switch (fw_rec->type) {
case IQS62X_FW_REC_TYPE_INFO:
continue;
case IQS62X_FW_REC_TYPE_PROD:
if (fw_rec->data == iqs62x->dev_desc->prod_num)
continue;
dev_err(&client->dev,
"Incompatible product number: 0x%02X\n",
fw_rec->data);
ret = -EINVAL;
break;
case IQS62X_FW_REC_TYPE_HALL:
if (!hall_cal_index) {
ret = regmap_write(iqs62x->regmap,
IQS62X_OTP_CMD,
IQS62X_OTP_CMD_FG3);
if (ret)
break;
ret = regmap_read(iqs62x->regmap,
IQS62X_OTP_DATA, &val);
if (ret)
break;
hall_cal_index = val & IQS62X_HALL_CAL_MASK;
if (!hall_cal_index) {
dev_err(&client->dev,
"Uncalibrated device\n");
ret = -ENODATA;
break;
}
}
if (hall_cal_index > fw_rec->len) {
ret = -EINVAL;
break;
}
mask = 0;
data = &fw_rec->data + hall_cal_index - 1;
len = sizeof(*data);
break;
case IQS62X_FW_REC_TYPE_MASK:
if (fw_rec->len < (sizeof(mask) + sizeof(*data))) {
ret = -EINVAL;
break;
}
mask = fw_rec->data;
data = &fw_rec->data + sizeof(mask);
len = sizeof(*data);
break;
case IQS62X_FW_REC_TYPE_DATA:
mask = 0;
data = &fw_rec->data;
len = fw_rec->len;
break;
default:
dev_err(&client->dev,
"Unrecognized record type: 0x%02X\n",
fw_rec->type);
ret = -EINVAL;
}
if (ret)
break;
fw_blk = devm_kzalloc(&client->dev,
struct_size(fw_blk, data, len),
GFP_KERNEL);
if (!fw_blk) {
ret = -ENOMEM;
break;
}
fw_blk->addr = fw_rec->addr;
fw_blk->mask = mask;
fw_blk->len = len;
memcpy(fw_blk->data, data, len);
list_add(&fw_blk->list, &iqs62x->fw_blk_head);
}
release_firmware(fw);
return ret;
}
const struct iqs62x_event_desc iqs62x_events[IQS62X_NUM_EVENTS] = {
[IQS62X_EVENT_PROX_CH0_T] = {
.reg = IQS62X_EVENT_PROX,
.mask = BIT(4),
.val = BIT(4),
},
[IQS62X_EVENT_PROX_CH0_P] = {
.reg = IQS62X_EVENT_PROX,
.mask = BIT(0),
.val = BIT(0),
},
[IQS62X_EVENT_PROX_CH1_T] = {
.reg = IQS62X_EVENT_PROX,
.mask = BIT(5),
.val = BIT(5),
},
[IQS62X_EVENT_PROX_CH1_P] = {
.reg = IQS62X_EVENT_PROX,
.mask = BIT(1),
.val = BIT(1),
},
[IQS62X_EVENT_PROX_CH2_T] = {
.reg = IQS62X_EVENT_PROX,
.mask = BIT(6),
.val = BIT(6),
},
[IQS62X_EVENT_PROX_CH2_P] = {
.reg = IQS62X_EVENT_PROX,
.mask = BIT(2),
.val = BIT(2),
},
[IQS62X_EVENT_HYST_POS_T] = {
.reg = IQS62X_EVENT_HYST,
.mask = BIT(6) | BIT(7),
.val = BIT(6),
},
[IQS62X_EVENT_HYST_POS_P] = {
.reg = IQS62X_EVENT_HYST,
.mask = BIT(5) | BIT(7),
.val = BIT(5),
},
[IQS62X_EVENT_HYST_NEG_T] = {
.reg = IQS62X_EVENT_HYST,
.mask = BIT(6) | BIT(7),
.val = BIT(6) | BIT(7),
},
[IQS62X_EVENT_HYST_NEG_P] = {
.reg = IQS62X_EVENT_HYST,
.mask = BIT(5) | BIT(7),
.val = BIT(5) | BIT(7),
},
[IQS62X_EVENT_SAR1_ACT] = {
.reg = IQS62X_EVENT_HYST,
.mask = BIT(4),
.val = BIT(4),
},
[IQS62X_EVENT_SAR1_QRD] = {
.reg = IQS62X_EVENT_HYST,
.mask = BIT(2),
.val = BIT(2),
},
[IQS62X_EVENT_SAR1_MOVE] = {
.reg = IQS62X_EVENT_HYST,
.mask = BIT(1),
.val = BIT(1),
},
[IQS62X_EVENT_SAR1_HALT] = {
.reg = IQS62X_EVENT_HYST,
.mask = BIT(0),
.val = BIT(0),
},
[IQS62X_EVENT_WHEEL_UP] = {
.reg = IQS62X_EVENT_WHEEL,
.mask = BIT(7) | BIT(6),
.val = BIT(7),
},
[IQS62X_EVENT_WHEEL_DN] = {
.reg = IQS62X_EVENT_WHEEL,
.mask = BIT(7) | BIT(6),
.val = BIT(7) | BIT(6),
},
[IQS62X_EVENT_HALL_N_T] = {
.reg = IQS62X_EVENT_HALL,
.mask = BIT(2) | BIT(0),
.val = BIT(2),
},
[IQS62X_EVENT_HALL_N_P] = {
.reg = IQS62X_EVENT_HALL,
.mask = BIT(1) | BIT(0),
.val = BIT(1),
},
[IQS62X_EVENT_HALL_S_T] = {
.reg = IQS62X_EVENT_HALL,
.mask = BIT(2) | BIT(0),
.val = BIT(2) | BIT(0),
},
[IQS62X_EVENT_HALL_S_P] = {
.reg = IQS62X_EVENT_HALL,
.mask = BIT(1) | BIT(0),
.val = BIT(1) | BIT(0),
},
[IQS62X_EVENT_SYS_RESET] = {
.reg = IQS62X_EVENT_SYS,
.mask = BIT(7),
.val = BIT(7),
},
[IQS62X_EVENT_SYS_ATI] = {
.reg = IQS62X_EVENT_SYS,
.mask = BIT(2),
.val = BIT(2),
},
};
EXPORT_SYMBOL_GPL(iqs62x_events);
static irqreturn_t iqs62x_irq(int irq, void *context)
{
struct iqs62x_core *iqs62x = context;
struct i2c_client *client = iqs62x->client;
struct iqs62x_event_data event_data;
struct iqs62x_event_desc event_desc;
enum iqs62x_event_reg event_reg;
unsigned long event_flags = 0;
int ret, i, j;
u8 event_map[IQS62X_EVENT_SIZE];
/*
* The device asserts the RDY output to signal the beginning of a
* communication window, which is closed by an I2C stop condition.
* As such, all interrupt status is captured in a single read and
* broadcast to any interested sub-device drivers.
*/
ret = regmap_raw_read(iqs62x->regmap, IQS62X_SYS_FLAGS, event_map,
sizeof(event_map));
if (ret) {
dev_err(&client->dev, "Failed to read device status: %d\n",
ret);
return IRQ_NONE;
}
for (i = 0; i < sizeof(event_map); i++) {
event_reg = iqs62x->dev_desc->event_regs[iqs62x->ui_sel][i];
switch (event_reg) {
case IQS62X_EVENT_UI_LO:
event_data.ui_data = get_unaligned_le16(&event_map[i]);
fallthrough;
case IQS62X_EVENT_UI_HI:
case IQS62X_EVENT_NONE:
continue;
case IQS62X_EVENT_ALS:
event_data.als_flags = event_map[i];
continue;
case IQS62X_EVENT_IR:
event_data.ir_flags = event_map[i];
continue;
case IQS62X_EVENT_INTER:
event_data.interval = event_map[i];
continue;
case IQS62X_EVENT_HYST:
event_map[i] <<= iqs62x->dev_desc->hyst_shift;
fallthrough;
case IQS62X_EVENT_WHEEL:
case IQS62X_EVENT_HALL:
case IQS62X_EVENT_PROX:
case IQS62X_EVENT_SYS:
break;
}
for (j = 0; j < IQS62X_NUM_EVENTS; j++) {
event_desc = iqs62x_events[j];
if (event_desc.reg != event_reg)
continue;
if ((event_map[i] & event_desc.mask) == event_desc.val)
event_flags |= BIT(j);
}
}
/*
* The device resets itself in response to the I2C master stalling
* communication past a fixed timeout. In this case, all registers
* are restored and any interested sub-device drivers are notified.
*/
if (event_flags & BIT(IQS62X_EVENT_SYS_RESET)) {
dev_err(&client->dev, "Unexpected device reset\n");
ret = iqs62x_dev_init(iqs62x);
if (ret) {
dev_err(&client->dev,
"Failed to re-initialize device: %d\n", ret);
return IRQ_NONE;
}
iqs62x->event_cache |= BIT(IQS62X_EVENT_SYS_RESET);
reinit_completion(&iqs62x->ati_done);
} else if (event_flags & BIT(IQS62X_EVENT_SYS_ATI)) {
iqs62x->event_cache |= BIT(IQS62X_EVENT_SYS_ATI);
reinit_completion(&iqs62x->ati_done);
} else if (!completion_done(&iqs62x->ati_done)) {
ret = regmap_update_bits(iqs62x->regmap, IQS62X_SYS_SETTINGS,
IQS62X_SYS_SETTINGS_EVENT_MODE, 0xFF);
if (ret) {
dev_err(&client->dev,
"Failed to enable event mode: %d\n", ret);
return IRQ_NONE;
}
msleep(IQS62X_FILT_SETTLE_MS);
complete_all(&iqs62x->ati_done);
}
/*
* Reset and ATI events are not broadcast to the sub-device drivers
* until ATI has completed. Any other events that may have occurred
* during ATI are ignored.
*/
if (completion_done(&iqs62x->ati_done)) {
event_flags |= iqs62x->event_cache;
ret = blocking_notifier_call_chain(&iqs62x->nh, event_flags,
&event_data);
if (ret & NOTIFY_STOP_MASK)
return IRQ_NONE;
iqs62x->event_cache = 0;
}
/*
* Once the communication window is closed, a small delay is added to
* ensure the device's RDY output has been deasserted by the time the
* interrupt handler returns.
*/
usleep_range(150, 200);
return IRQ_HANDLED;
}
static void iqs62x_firmware_load(const struct firmware *fw, void *context)
{
struct iqs62x_core *iqs62x = context;
struct i2c_client *client = iqs62x->client;
int ret;
if (fw) {
ret = iqs62x_firmware_parse(iqs62x, fw);
if (ret) {
dev_err(&client->dev, "Failed to parse firmware: %d\n",
ret);
goto err_out;
}
}
ret = iqs62x_dev_init(iqs62x);
if (ret) {
dev_err(&client->dev, "Failed to initialize device: %d\n", ret);
goto err_out;
}
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, iqs62x_irq, IRQF_ONESHOT,
client->name, iqs62x);
if (ret) {
dev_err(&client->dev, "Failed to request IRQ: %d\n", ret);
goto err_out;
}
if (!wait_for_completion_timeout(&iqs62x->ati_done,
msecs_to_jiffies(2000))) {
dev_err(&client->dev, "Failed to complete ATI\n");
goto err_out;
}
ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_NONE,
iqs62x->dev_desc->sub_devs,
iqs62x->dev_desc->num_sub_devs,
NULL, 0, NULL);
if (ret)
dev_err(&client->dev, "Failed to add sub-devices: %d\n", ret);
err_out:
complete_all(&iqs62x->fw_done);
}
static const struct mfd_cell iqs620at_sub_devs[] = {
{
.name = "iqs62x-keys",
.of_compatible = "azoteq,iqs620a-keys",
},
{
.name = "iqs620a-pwm",
.of_compatible = "azoteq,iqs620a-pwm",
},
{ .name = "iqs620at-temp", },
};
static const struct mfd_cell iqs620a_sub_devs[] = {
{
.name = "iqs62x-keys",
.of_compatible = "azoteq,iqs620a-keys",
},
{
.name = "iqs620a-pwm",
.of_compatible = "azoteq,iqs620a-pwm",
},
};
static const struct mfd_cell iqs621_sub_devs[] = {
{
.name = "iqs62x-keys",
.of_compatible = "azoteq,iqs621-keys",
},
{ .name = "iqs621-als", },
};
static const struct mfd_cell iqs622_sub_devs[] = {
{
.name = "iqs62x-keys",
.of_compatible = "azoteq,iqs622-keys",
},
{ .name = "iqs621-als", },
};
static const struct mfd_cell iqs624_sub_devs[] = {
{
.name = "iqs62x-keys",
.of_compatible = "azoteq,iqs624-keys",
},
{ .name = "iqs624-pos", },
};
static const struct mfd_cell iqs625_sub_devs[] = {
{
.name = "iqs62x-keys",
.of_compatible = "azoteq,iqs625-keys",
},
{ .name = "iqs624-pos", },
};
static const u8 iqs620at_cal_regs[] = {
IQS620_TEMP_CAL_MULT,
IQS620_TEMP_CAL_DIV,
IQS620_TEMP_CAL_OFFS,
};
static const u8 iqs621_cal_regs[] = {
IQS621_ALS_CAL_DIV_LUX,
IQS621_ALS_CAL_DIV_IR,
};
static const enum iqs62x_event_reg iqs620a_event_regs[][IQS62X_EVENT_SIZE] = {
[IQS62X_UI_PROX] = {
IQS62X_EVENT_SYS, /* 0x10 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_PROX, /* 0x12 */
IQS62X_EVENT_HYST, /* 0x13 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_NONE,
IQS62X_EVENT_HALL, /* 0x16 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_NONE,
IQS62X_EVENT_NONE,
},
[IQS62X_UI_SAR1] = {
IQS62X_EVENT_SYS, /* 0x10 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_NONE,
IQS62X_EVENT_HYST, /* 0x13 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_NONE,
IQS62X_EVENT_HALL, /* 0x16 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_NONE,
IQS62X_EVENT_NONE,
},
};
static const enum iqs62x_event_reg iqs621_event_regs[][IQS62X_EVENT_SIZE] = {
[IQS62X_UI_PROX] = {
IQS62X_EVENT_SYS, /* 0x10 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_PROX, /* 0x12 */
IQS62X_EVENT_HYST, /* 0x13 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_NONE,
IQS62X_EVENT_ALS, /* 0x16 */
IQS62X_EVENT_UI_LO, /* 0x17 */
IQS62X_EVENT_UI_HI, /* 0x18 */
IQS62X_EVENT_HALL, /* 0x19 */
},
};
static const enum iqs62x_event_reg iqs622_event_regs[][IQS62X_EVENT_SIZE] = {
[IQS62X_UI_PROX] = {
IQS62X_EVENT_SYS, /* 0x10 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_PROX, /* 0x12 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_ALS, /* 0x14 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_IR, /* 0x16 */
IQS62X_EVENT_UI_LO, /* 0x17 */
IQS62X_EVENT_UI_HI, /* 0x18 */
IQS62X_EVENT_HALL, /* 0x19 */
},
[IQS62X_UI_SAR1] = {
IQS62X_EVENT_SYS, /* 0x10 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_NONE,
IQS62X_EVENT_HYST, /* 0x13 */
IQS62X_EVENT_ALS, /* 0x14 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_IR, /* 0x16 */
IQS62X_EVENT_UI_LO, /* 0x17 */
IQS62X_EVENT_UI_HI, /* 0x18 */
IQS62X_EVENT_HALL, /* 0x19 */
},
};
static const enum iqs62x_event_reg iqs624_event_regs[][IQS62X_EVENT_SIZE] = {
[IQS62X_UI_PROX] = {
IQS62X_EVENT_SYS, /* 0x10 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_PROX, /* 0x12 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_WHEEL, /* 0x14 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_UI_LO, /* 0x16 */
IQS62X_EVENT_UI_HI, /* 0x17 */
IQS62X_EVENT_INTER, /* 0x18 */
IQS62X_EVENT_NONE,
},
};
static const enum iqs62x_event_reg iqs625_event_regs[][IQS62X_EVENT_SIZE] = {
[IQS62X_UI_PROX] = {
IQS62X_EVENT_SYS, /* 0x10 */
IQS62X_EVENT_PROX, /* 0x11 */
IQS62X_EVENT_INTER, /* 0x12 */
IQS62X_EVENT_NONE,
IQS62X_EVENT_NONE,
IQS62X_EVENT_NONE,
IQS62X_EVENT_NONE,
IQS62X_EVENT_NONE,
IQS62X_EVENT_NONE,
IQS62X_EVENT_NONE,
},
};
static const struct iqs62x_dev_desc iqs62x_devs[] = {
{
.dev_name = "iqs620at",
.sub_devs = iqs620at_sub_devs,
.num_sub_devs = ARRAY_SIZE(iqs620at_sub_devs),
.prod_num = IQS620_PROD_NUM,
.sw_num = 0x08,
.cal_regs = iqs620at_cal_regs,
.num_cal_regs = ARRAY_SIZE(iqs620at_cal_regs),
.prox_mask = BIT(0),
.sar_mask = BIT(1) | BIT(7),
.hall_mask = BIT(2),
.hyst_mask = BIT(3),
.temp_mask = BIT(4),
.prox_settings = IQS620_PROX_SETTINGS_4,
.hall_flags = IQS620_HALL_FLAGS,
.fw_name = "iqs620a.bin",
.event_regs = &iqs620a_event_regs[IQS62X_UI_PROX],
},
{
.dev_name = "iqs620a",
.sub_devs = iqs620a_sub_devs,
.num_sub_devs = ARRAY_SIZE(iqs620a_sub_devs),
.prod_num = IQS620_PROD_NUM,
.sw_num = 0x08,
.prox_mask = BIT(0),
.sar_mask = BIT(1) | BIT(7),
.hall_mask = BIT(2),
.hyst_mask = BIT(3),
.temp_mask = BIT(4),
.prox_settings = IQS620_PROX_SETTINGS_4,
.hall_flags = IQS620_HALL_FLAGS,
.fw_name = "iqs620a.bin",
.event_regs = &iqs620a_event_regs[IQS62X_UI_PROX],
},
{
.dev_name = "iqs621",
.sub_devs = iqs621_sub_devs,
.num_sub_devs = ARRAY_SIZE(iqs621_sub_devs),
.prod_num = IQS621_PROD_NUM,
.sw_num = 0x09,
.cal_regs = iqs621_cal_regs,
.num_cal_regs = ARRAY_SIZE(iqs621_cal_regs),
.prox_mask = BIT(0),
.hall_mask = BIT(1),
.als_mask = BIT(2),
.hyst_mask = BIT(3),
.temp_mask = BIT(4),
.als_flags = IQS621_ALS_FLAGS,
.hall_flags = IQS621_HALL_FLAGS,
.hyst_shift = 5,
.fw_name = "iqs621.bin",
.event_regs = &iqs621_event_regs[IQS62X_UI_PROX],
},
{
.dev_name = "iqs622",
.sub_devs = iqs622_sub_devs,
.num_sub_devs = ARRAY_SIZE(iqs622_sub_devs),
.prod_num = IQS622_PROD_NUM,
.sw_num = 0x06,
.prox_mask = BIT(0),
.sar_mask = BIT(1),
.hall_mask = BIT(2),
.als_mask = BIT(3),
.ir_mask = BIT(4),
.prox_settings = IQS622_PROX_SETTINGS_4,
.als_flags = IQS622_ALS_FLAGS,
.hall_flags = IQS622_HALL_FLAGS,
.fw_name = "iqs622.bin",
.event_regs = &iqs622_event_regs[IQS62X_UI_PROX],
},
{
.dev_name = "iqs624",
.sub_devs = iqs624_sub_devs,
.num_sub_devs = ARRAY_SIZE(iqs624_sub_devs),
.prod_num = IQS624_PROD_NUM,
.sw_num = 0x0B,
.interval = IQS624_INTERVAL_NUM,
.interval_div = 3,
.fw_name = "iqs624.bin",
.event_regs = &iqs624_event_regs[IQS62X_UI_PROX],
},
{
.dev_name = "iqs625",
.sub_devs = iqs625_sub_devs,
.num_sub_devs = ARRAY_SIZE(iqs625_sub_devs),
.prod_num = IQS625_PROD_NUM,
.sw_num = 0x0B,
.interval = IQS625_INTERVAL_NUM,
.interval_div = 10,
.fw_name = "iqs625.bin",
.event_regs = &iqs625_event_regs[IQS62X_UI_PROX],
},
};
static const struct regmap_config iqs62x_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = IQS62X_MAX_REG,
};
static int iqs62x_probe(struct i2c_client *client)
{
struct iqs62x_core *iqs62x;
struct iqs62x_info info;
unsigned int val;
int ret, i, j;
const char *fw_name = NULL;
iqs62x = devm_kzalloc(&client->dev, sizeof(*iqs62x), GFP_KERNEL);
if (!iqs62x)
return -ENOMEM;
i2c_set_clientdata(client, iqs62x);
iqs62x->client = client;
BLOCKING_INIT_NOTIFIER_HEAD(&iqs62x->nh);
INIT_LIST_HEAD(&iqs62x->fw_blk_head);
init_completion(&iqs62x->ati_done);
init_completion(&iqs62x->fw_done);
iqs62x->regmap = devm_regmap_init_i2c(client, &iqs62x_regmap_config);
if (IS_ERR(iqs62x->regmap)) {
ret = PTR_ERR(iqs62x->regmap);
dev_err(&client->dev, "Failed to initialize register map: %d\n",
ret);
return ret;
}
ret = regmap_raw_read(iqs62x->regmap, IQS62X_PROD_NUM, &info,
sizeof(info));
if (ret)
return ret;
/*
* The following sequence validates the device's product and software
* numbers. It then determines if the device is factory-calibrated by
* checking for nonzero values in the device's designated calibration
* registers (if applicable). Depending on the device, the absence of
* calibration data indicates a reduced feature set or invalid device.
*
* For devices given in both calibrated and uncalibrated versions, the
* calibrated version (e.g. IQS620AT) appears first in the iqs62x_devs
* array. The uncalibrated version (e.g. IQS620A) appears next and has
* the same product and software numbers, but no calibration registers
* are specified.
*/
for (i = 0; i < ARRAY_SIZE(iqs62x_devs); i++) {
if (info.prod_num != iqs62x_devs[i].prod_num)
continue;
iqs62x->dev_desc = &iqs62x_devs[i];
if (info.sw_num < iqs62x->dev_desc->sw_num)
continue;
iqs62x->sw_num = info.sw_num;
iqs62x->hw_num = info.hw_num;
/*
* Read each of the device's designated calibration registers,
* if any, and exit from the inner loop early if any are equal
* to zero (indicating the device is uncalibrated). This could
* be acceptable depending on the device (e.g. IQS620A instead
* of IQS620AT).
*/
for (j = 0; j < iqs62x->dev_desc->num_cal_regs; j++) {
ret = regmap_read(iqs62x->regmap,
iqs62x->dev_desc->cal_regs[j], &val);
if (ret)
return ret;
if (!val)
break;
}
/*
* If the number of nonzero values read from the device equals
* the number of designated calibration registers (which could
* be zero), exit from the outer loop early to signal that the
* device's product and software numbers match a known device,
* and the device is calibrated (if applicable).
*/
if (j == iqs62x->dev_desc->num_cal_regs)
break;
}
if (!iqs62x->dev_desc) {
dev_err(&client->dev, "Unrecognized product number: 0x%02X\n",
info.prod_num);
return -EINVAL;
}
if (!iqs62x->sw_num) {
dev_err(&client->dev, "Unrecognized software number: 0x%02X\n",
info.sw_num);
return -EINVAL;
}
if (i == ARRAY_SIZE(iqs62x_devs)) {
dev_err(&client->dev, "Uncalibrated device\n");
return -ENODATA;
}
device_property_read_string(&client->dev, "firmware-name", &fw_name);
ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
fw_name ? : iqs62x->dev_desc->fw_name,
&client->dev, GFP_KERNEL, iqs62x,
iqs62x_firmware_load);
if (ret)
dev_err(&client->dev, "Failed to request firmware: %d\n", ret);
return ret;
}
static void iqs62x_remove(struct i2c_client *client)
{
struct iqs62x_core *iqs62x = i2c_get_clientdata(client);
wait_for_completion(&iqs62x->fw_done);
}
static int __maybe_unused iqs62x_suspend(struct device *dev)
{
struct iqs62x_core *iqs62x = dev_get_drvdata(dev);
int ret;
wait_for_completion(&iqs62x->fw_done);
/*
* As per the datasheet, automatic mode switching must be disabled
* before the device is placed in or taken out of halt mode.
*/
ret = regmap_update_bits(iqs62x->regmap, IQS62X_PWR_SETTINGS,
IQS62X_PWR_SETTINGS_DIS_AUTO, 0xFF);
if (ret)
return ret;
return regmap_update_bits(iqs62x->regmap, IQS62X_PWR_SETTINGS,
IQS62X_PWR_SETTINGS_PWR_MODE_MASK,
IQS62X_PWR_SETTINGS_PWR_MODE_HALT);
}
static int __maybe_unused iqs62x_resume(struct device *dev)
{
struct iqs62x_core *iqs62x = dev_get_drvdata(dev);
int ret;
ret = regmap_update_bits(iqs62x->regmap, IQS62X_PWR_SETTINGS,
IQS62X_PWR_SETTINGS_PWR_MODE_MASK,
IQS62X_PWR_SETTINGS_PWR_MODE_NORM);
if (ret)
return ret;
return regmap_update_bits(iqs62x->regmap, IQS62X_PWR_SETTINGS,
IQS62X_PWR_SETTINGS_DIS_AUTO, 0);
}
static SIMPLE_DEV_PM_OPS(iqs62x_pm, iqs62x_suspend, iqs62x_resume);
static const struct of_device_id iqs62x_of_match[] = {
{ .compatible = "azoteq,iqs620a" },
{ .compatible = "azoteq,iqs621" },
{ .compatible = "azoteq,iqs622" },
{ .compatible = "azoteq,iqs624" },
{ .compatible = "azoteq,iqs625" },
{ }
};
MODULE_DEVICE_TABLE(of, iqs62x_of_match);
static struct i2c_driver iqs62x_i2c_driver = {
.driver = {
.name = "iqs62x",
.of_match_table = iqs62x_of_match,
.pm = &iqs62x_pm,
},
.probe = iqs62x_probe,
.remove = iqs62x_remove,
};
module_i2c_driver(iqs62x_i2c_driver);
MODULE_AUTHOR("Jeff LaBundy <[email protected]>");
MODULE_DESCRIPTION("Azoteq IQS620A/621/622/624/625 Multi-Function Sensors");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/iqs62x.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* lm3533-ctrlbank.c -- LM3533 Generic Control Bank interface
*
* Copyright (C) 2011-2012 Texas Instruments
*
* Author: Johan Hovold <[email protected]>
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/mfd/lm3533.h>
#define LM3533_MAX_CURRENT_MIN 5000
#define LM3533_MAX_CURRENT_MAX 29800
#define LM3533_MAX_CURRENT_STEP 800
#define LM3533_PWM_MAX 0x3f
#define LM3533_REG_PWM_BASE 0x14
#define LM3533_REG_MAX_CURRENT_BASE 0x1f
#define LM3533_REG_CTRLBANK_ENABLE 0x27
#define LM3533_REG_BRIGHTNESS_BASE 0x40
static inline u8 lm3533_ctrlbank_get_reg(struct lm3533_ctrlbank *cb, u8 base)
{
return base + cb->id;
}
int lm3533_ctrlbank_enable(struct lm3533_ctrlbank *cb)
{
u8 mask;
int ret;
dev_dbg(cb->dev, "%s - %d\n", __func__, cb->id);
mask = 1 << cb->id;
ret = lm3533_update(cb->lm3533, LM3533_REG_CTRLBANK_ENABLE,
mask, mask);
if (ret)
dev_err(cb->dev, "failed to enable ctrlbank %d\n", cb->id);
return ret;
}
EXPORT_SYMBOL_GPL(lm3533_ctrlbank_enable);
int lm3533_ctrlbank_disable(struct lm3533_ctrlbank *cb)
{
u8 mask;
int ret;
dev_dbg(cb->dev, "%s - %d\n", __func__, cb->id);
mask = 1 << cb->id;
ret = lm3533_update(cb->lm3533, LM3533_REG_CTRLBANK_ENABLE, 0, mask);
if (ret)
dev_err(cb->dev, "failed to disable ctrlbank %d\n", cb->id);
return ret;
}
EXPORT_SYMBOL_GPL(lm3533_ctrlbank_disable);
/*
* Full-scale current.
*
* imax 5000 - 29800 uA (800 uA step)
*/
int lm3533_ctrlbank_set_max_current(struct lm3533_ctrlbank *cb, u16 imax)
{
u8 reg;
u8 val;
int ret;
if (imax < LM3533_MAX_CURRENT_MIN || imax > LM3533_MAX_CURRENT_MAX)
return -EINVAL;
val = (imax - LM3533_MAX_CURRENT_MIN) / LM3533_MAX_CURRENT_STEP;
reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_MAX_CURRENT_BASE);
ret = lm3533_write(cb->lm3533, reg, val);
if (ret)
dev_err(cb->dev, "failed to set max current\n");
return ret;
}
EXPORT_SYMBOL_GPL(lm3533_ctrlbank_set_max_current);
int lm3533_ctrlbank_set_brightness(struct lm3533_ctrlbank *cb, u8 val)
{
u8 reg;
int ret;
reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_BRIGHTNESS_BASE);
ret = lm3533_write(cb->lm3533, reg, val);
if (ret)
dev_err(cb->dev, "failed to set brightness\n");
return ret;
}
EXPORT_SYMBOL_GPL(lm3533_ctrlbank_set_brightness);
int lm3533_ctrlbank_get_brightness(struct lm3533_ctrlbank *cb, u8 *val)
{
u8 reg;
int ret;
reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_BRIGHTNESS_BASE);
ret = lm3533_read(cb->lm3533, reg, val);
if (ret)
dev_err(cb->dev, "failed to get brightness\n");
return ret;
}
EXPORT_SYMBOL_GPL(lm3533_ctrlbank_get_brightness);
/*
* PWM-input control mask:
*
* bit 5 - PWM-input enabled in Zone 4
* bit 4 - PWM-input enabled in Zone 3
* bit 3 - PWM-input enabled in Zone 2
* bit 2 - PWM-input enabled in Zone 1
* bit 1 - PWM-input enabled in Zone 0
* bit 0 - PWM-input enabled
*/
int lm3533_ctrlbank_set_pwm(struct lm3533_ctrlbank *cb, u8 val)
{
u8 reg;
int ret;
if (val > LM3533_PWM_MAX)
return -EINVAL;
reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_PWM_BASE);
ret = lm3533_write(cb->lm3533, reg, val);
if (ret)
dev_err(cb->dev, "failed to set PWM mask\n");
return ret;
}
EXPORT_SYMBOL_GPL(lm3533_ctrlbank_set_pwm);
int lm3533_ctrlbank_get_pwm(struct lm3533_ctrlbank *cb, u8 *val)
{
u8 reg;
int ret;
reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_PWM_BASE);
ret = lm3533_read(cb->lm3533, reg, val);
if (ret)
dev_err(cb->dev, "failed to get PWM mask\n");
return ret;
}
EXPORT_SYMBOL_GPL(lm3533_ctrlbank_get_pwm);
MODULE_AUTHOR("Johan Hovold <[email protected]>");
MODULE_DESCRIPTION("LM3533 Control Bank interface");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/lm3533-ctrlbank.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Free Electrons
* Copyright (C) 2014 Atmel
*
* Author: Boris BREZILLON <[email protected]>
*/
#include <linux/clk.h>
#include <linux/iopoll.h>
#include <linux/mfd/atmel-hlcdc.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#define ATMEL_HLCDC_REG_MAX (0x4000 - 0x4)
struct atmel_hlcdc_regmap {
void __iomem *regs;
struct device *dev;
};
static const struct mfd_cell atmel_hlcdc_cells[] = {
{
.name = "atmel-hlcdc-pwm",
.of_compatible = "atmel,hlcdc-pwm",
},
{
.name = "atmel-hlcdc-dc",
.of_compatible = "atmel,hlcdc-display-controller",
},
};
static int regmap_atmel_hlcdc_reg_write(void *context, unsigned int reg,
unsigned int val)
{
struct atmel_hlcdc_regmap *hregmap = context;
if (reg <= ATMEL_HLCDC_DIS) {
u32 status;
int ret;
ret = readl_poll_timeout_atomic(hregmap->regs + ATMEL_HLCDC_SR,
status,
!(status & ATMEL_HLCDC_SIP),
1, 100);
if (ret) {
dev_err(hregmap->dev,
"Timeout! Clock domain synchronization is in progress!\n");
return ret;
}
}
writel(val, hregmap->regs + reg);
return 0;
}
static int regmap_atmel_hlcdc_reg_read(void *context, unsigned int reg,
unsigned int *val)
{
struct atmel_hlcdc_regmap *hregmap = context;
*val = readl(hregmap->regs + reg);
return 0;
}
static const struct regmap_config atmel_hlcdc_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = ATMEL_HLCDC_REG_MAX,
.reg_write = regmap_atmel_hlcdc_reg_write,
.reg_read = regmap_atmel_hlcdc_reg_read,
.fast_io = true,
};
static int atmel_hlcdc_probe(struct platform_device *pdev)
{
struct atmel_hlcdc_regmap *hregmap;
struct device *dev = &pdev->dev;
struct atmel_hlcdc *hlcdc;
hregmap = devm_kzalloc(dev, sizeof(*hregmap), GFP_KERNEL);
if (!hregmap)
return -ENOMEM;
hlcdc = devm_kzalloc(dev, sizeof(*hlcdc), GFP_KERNEL);
if (!hlcdc)
return -ENOMEM;
hregmap->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(hregmap->regs))
return PTR_ERR(hregmap->regs);
hregmap->dev = &pdev->dev;
hlcdc->irq = platform_get_irq(pdev, 0);
if (hlcdc->irq < 0)
return hlcdc->irq;
hlcdc->periph_clk = devm_clk_get(dev, "periph_clk");
if (IS_ERR(hlcdc->periph_clk)) {
dev_err(dev, "failed to get peripheral clock\n");
return PTR_ERR(hlcdc->periph_clk);
}
hlcdc->sys_clk = devm_clk_get(dev, "sys_clk");
if (IS_ERR(hlcdc->sys_clk)) {
dev_err(dev, "failed to get system clock\n");
return PTR_ERR(hlcdc->sys_clk);
}
hlcdc->slow_clk = devm_clk_get(dev, "slow_clk");
if (IS_ERR(hlcdc->slow_clk)) {
dev_err(dev, "failed to get slow clock\n");
return PTR_ERR(hlcdc->slow_clk);
}
hlcdc->regmap = devm_regmap_init(dev, NULL, hregmap,
&atmel_hlcdc_regmap_config);
if (IS_ERR(hlcdc->regmap))
return PTR_ERR(hlcdc->regmap);
dev_set_drvdata(dev, hlcdc);
return devm_mfd_add_devices(dev, -1, atmel_hlcdc_cells,
ARRAY_SIZE(atmel_hlcdc_cells),
NULL, 0, NULL);
}
static const struct of_device_id atmel_hlcdc_match[] = {
{ .compatible = "atmel,at91sam9n12-hlcdc" },
{ .compatible = "atmel,at91sam9x5-hlcdc" },
{ .compatible = "atmel,sama5d2-hlcdc" },
{ .compatible = "atmel,sama5d3-hlcdc" },
{ .compatible = "atmel,sama5d4-hlcdc" },
{ .compatible = "microchip,sam9x60-hlcdc" },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, atmel_hlcdc_match);
static struct platform_driver atmel_hlcdc_driver = {
.probe = atmel_hlcdc_probe,
.driver = {
.name = "atmel-hlcdc",
.of_match_table = atmel_hlcdc_match,
},
};
module_platform_driver(atmel_hlcdc_driver);
MODULE_ALIAS("platform:atmel-hlcdc");
MODULE_AUTHOR("Boris Brezillon <[email protected]>");
MODULE_DESCRIPTION("Atmel HLCDC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/atmel-hlcdc.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8350-core.c -- Device access for Wolfson WM8350
*
* Copyright 2007, 2008 Wolfson Microelectronics PLC.
*
* Author: Liam Girdwood, Mark Brown
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/slab.h>
#include <linux/bug.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/regmap.h>
#include <linux/workqueue.h>
#include <linux/mfd/wm8350/core.h>
#include <linux/mfd/wm8350/audio.h>
#include <linux/mfd/wm8350/comparator.h>
#include <linux/mfd/wm8350/gpio.h>
#include <linux/mfd/wm8350/pmic.h>
#include <linux/mfd/wm8350/rtc.h>
#include <linux/mfd/wm8350/supply.h>
#include <linux/mfd/wm8350/wdt.h>
#define WM8350_CLOCK_CONTROL_1 0x28
#define WM8350_AIF_TEST 0x74
/* debug */
#define WM8350_BUS_DEBUG 0
#if WM8350_BUS_DEBUG
#define dump(regs, src) do { \
int i_; \
u16 *src_ = src; \
printk(KERN_DEBUG); \
for (i_ = 0; i_ < regs; i_++) \
printk(" 0x%4.4x", *src_++); \
printk("\n"); \
} while (0);
#else
#define dump(bytes, src)
#endif
#define WM8350_LOCK_DEBUG 0
#if WM8350_LOCK_DEBUG
#define ldbg(format, arg...) printk(format, ## arg)
#else
#define ldbg(format, arg...)
#endif
/*
* WM8350 Device IO
*/
static DEFINE_MUTEX(reg_lock_mutex);
/*
* Safe read, modify, write methods
*/
int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
{
return regmap_update_bits(wm8350->regmap, reg, mask, 0);
}
EXPORT_SYMBOL_GPL(wm8350_clear_bits);
int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
{
return regmap_update_bits(wm8350->regmap, reg, mask, mask);
}
EXPORT_SYMBOL_GPL(wm8350_set_bits);
u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
{
unsigned int data;
int err;
err = regmap_read(wm8350->regmap, reg, &data);
if (err)
dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
return data;
}
EXPORT_SYMBOL_GPL(wm8350_reg_read);
int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
{
int ret;
ret = regmap_write(wm8350->regmap, reg, val);
if (ret)
dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
return ret;
}
EXPORT_SYMBOL_GPL(wm8350_reg_write);
int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
u16 *dest)
{
int err = 0;
err = regmap_bulk_read(wm8350->regmap, start_reg, dest, regs);
if (err)
dev_err(wm8350->dev, "block read starting from R%d failed\n",
start_reg);
return err;
}
EXPORT_SYMBOL_GPL(wm8350_block_read);
int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
u16 *src)
{
int ret = 0;
ret = regmap_bulk_write(wm8350->regmap, start_reg, src, regs);
if (ret)
dev_err(wm8350->dev, "block write starting at R%d failed\n",
start_reg);
return ret;
}
EXPORT_SYMBOL_GPL(wm8350_block_write);
/**
* wm8350_reg_lock()
*
* The WM8350 has a hardware lock which can be used to prevent writes to
* some registers (generally those which can cause particularly serious
* problems if misused). This function enables that lock.
*
* @wm8350: pointer to local driver data structure
*/
int wm8350_reg_lock(struct wm8350 *wm8350)
{
int ret;
mutex_lock(®_lock_mutex);
ldbg(__func__);
ret = wm8350_reg_write(wm8350, WM8350_SECURITY, WM8350_LOCK_KEY);
if (ret)
dev_err(wm8350->dev, "lock failed\n");
wm8350->unlocked = false;
mutex_unlock(®_lock_mutex);
return ret;
}
EXPORT_SYMBOL_GPL(wm8350_reg_lock);
/**
* wm8350_reg_unlock()
*
* The WM8350 has a hardware lock which can be used to prevent writes to
* some registers (generally those which can cause particularly serious
* problems if misused). This function disables that lock so updates
* can be performed. For maximum safety this should be done only when
* required.
*
* @wm8350: pointer to local driver data structure
*/
int wm8350_reg_unlock(struct wm8350 *wm8350)
{
int ret;
mutex_lock(®_lock_mutex);
ldbg(__func__);
ret = wm8350_reg_write(wm8350, WM8350_SECURITY, WM8350_UNLOCK_KEY);
if (ret)
dev_err(wm8350->dev, "unlock failed\n");
wm8350->unlocked = true;
mutex_unlock(®_lock_mutex);
return ret;
}
EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
int wm8350_read_auxadc(struct wm8350 *wm8350, int channel, int scale, int vref)
{
u16 reg, result = 0;
if (channel < WM8350_AUXADC_AUX1 || channel > WM8350_AUXADC_TEMP)
return -EINVAL;
if (channel >= WM8350_AUXADC_USB && channel <= WM8350_AUXADC_TEMP
&& (scale != 0 || vref != 0))
return -EINVAL;
mutex_lock(&wm8350->auxadc_mutex);
/* Turn on the ADC */
reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5, reg | WM8350_AUXADC_ENA);
if (scale || vref) {
reg = scale << 13;
reg |= vref << 12;
wm8350_reg_write(wm8350, WM8350_AUX1_READBACK + channel, reg);
}
reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
reg |= 1 << channel | WM8350_AUXADC_POLL;
wm8350_reg_write(wm8350, WM8350_DIGITISER_CONTROL_1, reg);
/* If a late IRQ left the completion signalled then consume
* the completion. */
try_wait_for_completion(&wm8350->auxadc_done);
/* We ignore the result of the completion and just check for a
* conversion result, allowing us to soldier on if the IRQ
* infrastructure is not set up for the chip. */
wait_for_completion_timeout(&wm8350->auxadc_done, msecs_to_jiffies(5));
reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
if (reg & WM8350_AUXADC_POLL)
dev_err(wm8350->dev, "adc chn %d read timeout\n", channel);
else
result = wm8350_reg_read(wm8350,
WM8350_AUX1_READBACK + channel);
/* Turn off the ADC */
reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5,
reg & ~WM8350_AUXADC_ENA);
mutex_unlock(&wm8350->auxadc_mutex);
return result & WM8350_AUXADC_DATA1_MASK;
}
EXPORT_SYMBOL_GPL(wm8350_read_auxadc);
static irqreturn_t wm8350_auxadc_irq(int irq, void *irq_data)
{
struct wm8350 *wm8350 = irq_data;
complete(&wm8350->auxadc_done);
return IRQ_HANDLED;
}
/*
* Register a client device. This is non-fatal since there is no need to
* fail the entire device init due to a single platform device failing.
*/
static void wm8350_client_dev_register(struct wm8350 *wm8350,
const char *name,
struct platform_device **pdev)
{
int ret;
*pdev = platform_device_alloc(name, -1);
if (*pdev == NULL) {
dev_err(wm8350->dev, "Failed to allocate %s\n", name);
return;
}
(*pdev)->dev.parent = wm8350->dev;
platform_set_drvdata(*pdev, wm8350);
ret = platform_device_add(*pdev);
if (ret != 0) {
dev_err(wm8350->dev, "Failed to register %s: %d\n", name, ret);
platform_device_put(*pdev);
*pdev = NULL;
}
}
int wm8350_device_init(struct wm8350 *wm8350, int irq,
struct wm8350_platform_data *pdata)
{
int ret;
unsigned int id1, id2, mask_rev;
unsigned int cust_id, mode, chip_rev;
dev_set_drvdata(wm8350->dev, wm8350);
/* get WM8350 revision and config mode */
ret = regmap_read(wm8350->regmap, WM8350_RESET_ID, &id1);
if (ret != 0) {
dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
goto err;
}
ret = regmap_read(wm8350->regmap, WM8350_ID, &id2);
if (ret != 0) {
dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
goto err;
}
ret = regmap_read(wm8350->regmap, WM8350_REVISION, &mask_rev);
if (ret != 0) {
dev_err(wm8350->dev, "Failed to read revision: %d\n", ret);
goto err;
}
if (id1 != 0x6143) {
dev_err(wm8350->dev,
"Device with ID %x is not a WM8350\n", id1);
ret = -ENODEV;
goto err;
}
mode = (id2 & WM8350_CONF_STS_MASK) >> 10;
cust_id = id2 & WM8350_CUST_ID_MASK;
chip_rev = (id2 & WM8350_CHIP_REV_MASK) >> 12;
dev_info(wm8350->dev,
"CONF_STS %d, CUST_ID %d, MASK_REV %d, CHIP_REV %d\n",
mode, cust_id, mask_rev, chip_rev);
if (cust_id != 0) {
dev_err(wm8350->dev, "Unsupported CUST_ID\n");
ret = -ENODEV;
goto err;
}
switch (mask_rev) {
case 0:
wm8350->pmic.max_dcdc = WM8350_DCDC_6;
wm8350->pmic.max_isink = WM8350_ISINK_B;
switch (chip_rev) {
case WM8350_REV_E:
dev_info(wm8350->dev, "WM8350 Rev E\n");
break;
case WM8350_REV_F:
dev_info(wm8350->dev, "WM8350 Rev F\n");
break;
case WM8350_REV_G:
dev_info(wm8350->dev, "WM8350 Rev G\n");
wm8350->power.rev_g_coeff = 1;
break;
case WM8350_REV_H:
dev_info(wm8350->dev, "WM8350 Rev H\n");
wm8350->power.rev_g_coeff = 1;
break;
default:
/* For safety we refuse to run on unknown hardware */
dev_err(wm8350->dev, "Unknown WM8350 CHIP_REV\n");
ret = -ENODEV;
goto err;
}
break;
case 1:
wm8350->pmic.max_dcdc = WM8350_DCDC_4;
wm8350->pmic.max_isink = WM8350_ISINK_A;
switch (chip_rev) {
case 0:
dev_info(wm8350->dev, "WM8351 Rev A\n");
wm8350->power.rev_g_coeff = 1;
break;
case 1:
dev_info(wm8350->dev, "WM8351 Rev B\n");
wm8350->power.rev_g_coeff = 1;
break;
default:
dev_err(wm8350->dev, "Unknown WM8351 CHIP_REV\n");
ret = -ENODEV;
goto err;
}
break;
case 2:
wm8350->pmic.max_dcdc = WM8350_DCDC_6;
wm8350->pmic.max_isink = WM8350_ISINK_B;
switch (chip_rev) {
case 0:
dev_info(wm8350->dev, "WM8352 Rev A\n");
wm8350->power.rev_g_coeff = 1;
break;
default:
dev_err(wm8350->dev, "Unknown WM8352 CHIP_REV\n");
ret = -ENODEV;
goto err;
}
break;
default:
dev_err(wm8350->dev, "Unknown MASK_REV\n");
ret = -ENODEV;
goto err;
}
mutex_init(&wm8350->auxadc_mutex);
init_completion(&wm8350->auxadc_done);
ret = wm8350_irq_init(wm8350, irq, pdata);
if (ret < 0)
goto err;
if (wm8350->irq_base) {
ret = request_threaded_irq(wm8350->irq_base +
WM8350_IRQ_AUXADC_DATARDY,
NULL, wm8350_auxadc_irq,
IRQF_ONESHOT,
"auxadc", wm8350);
if (ret < 0)
dev_warn(wm8350->dev,
"Failed to request AUXADC IRQ: %d\n", ret);
}
if (pdata && pdata->init) {
ret = pdata->init(wm8350);
if (ret != 0) {
dev_err(wm8350->dev, "Platform init() failed: %d\n",
ret);
goto err_irq;
}
}
wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
wm8350_client_dev_register(wm8350, "wm8350-codec",
&(wm8350->codec.pdev));
wm8350_client_dev_register(wm8350, "wm8350-gpio",
&(wm8350->gpio.pdev));
wm8350_client_dev_register(wm8350, "wm8350-hwmon",
&(wm8350->hwmon.pdev));
wm8350_client_dev_register(wm8350, "wm8350-power",
&(wm8350->power.pdev));
wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
wm8350_client_dev_register(wm8350, "wm8350-wdt", &(wm8350->wdt.pdev));
return 0;
err_irq:
wm8350_irq_exit(wm8350);
err:
return ret;
}
EXPORT_SYMBOL_GPL(wm8350_device_init);
| linux-master | drivers/mfd/wm8350-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Arizona core driver
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/regulator/machine.h>
#include <linux/slab.h>
#include <linux/ktime.h>
#include <linux/platform_device.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/registers.h>
#include "arizona.h"
static const char * const wm5102_core_supplies[] = {
"AVDD",
"DBVDD1",
};
int arizona_clk32k_enable(struct arizona *arizona)
{
int ret = 0;
mutex_lock(&arizona->clk_lock);
arizona->clk32k_ref++;
if (arizona->clk32k_ref == 1) {
switch (arizona->pdata.clk32k_src) {
case ARIZONA_32KZ_MCLK1:
ret = pm_runtime_resume_and_get(arizona->dev);
if (ret != 0)
goto err_ref;
ret = clk_prepare_enable(arizona->mclk[ARIZONA_MCLK1]);
if (ret != 0) {
pm_runtime_put_sync(arizona->dev);
goto err_ref;
}
break;
case ARIZONA_32KZ_MCLK2:
ret = clk_prepare_enable(arizona->mclk[ARIZONA_MCLK2]);
if (ret != 0)
goto err_ref;
break;
}
ret = regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
ARIZONA_CLK_32K_ENA,
ARIZONA_CLK_32K_ENA);
}
err_ref:
if (ret != 0)
arizona->clk32k_ref--;
mutex_unlock(&arizona->clk_lock);
return ret;
}
EXPORT_SYMBOL_GPL(arizona_clk32k_enable);
int arizona_clk32k_disable(struct arizona *arizona)
{
mutex_lock(&arizona->clk_lock);
WARN_ON(arizona->clk32k_ref <= 0);
arizona->clk32k_ref--;
if (arizona->clk32k_ref == 0) {
regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
ARIZONA_CLK_32K_ENA, 0);
switch (arizona->pdata.clk32k_src) {
case ARIZONA_32KZ_MCLK1:
pm_runtime_put_sync(arizona->dev);
clk_disable_unprepare(arizona->mclk[ARIZONA_MCLK1]);
break;
case ARIZONA_32KZ_MCLK2:
clk_disable_unprepare(arizona->mclk[ARIZONA_MCLK2]);
break;
}
}
mutex_unlock(&arizona->clk_lock);
return 0;
}
EXPORT_SYMBOL_GPL(arizona_clk32k_disable);
static irqreturn_t arizona_clkgen_err(int irq, void *data)
{
struct arizona *arizona = data;
dev_err(arizona->dev, "CLKGEN error\n");
return IRQ_HANDLED;
}
static irqreturn_t arizona_underclocked(int irq, void *data)
{
struct arizona *arizona = data;
unsigned int val;
int ret;
ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_8,
&val);
if (ret != 0) {
dev_err(arizona->dev, "Failed to read underclock status: %d\n",
ret);
return IRQ_NONE;
}
if (val & ARIZONA_AIF3_UNDERCLOCKED_STS)
dev_err(arizona->dev, "AIF3 underclocked\n");
if (val & ARIZONA_AIF2_UNDERCLOCKED_STS)
dev_err(arizona->dev, "AIF2 underclocked\n");
if (val & ARIZONA_AIF1_UNDERCLOCKED_STS)
dev_err(arizona->dev, "AIF1 underclocked\n");
if (val & ARIZONA_ISRC3_UNDERCLOCKED_STS)
dev_err(arizona->dev, "ISRC3 underclocked\n");
if (val & ARIZONA_ISRC2_UNDERCLOCKED_STS)
dev_err(arizona->dev, "ISRC2 underclocked\n");
if (val & ARIZONA_ISRC1_UNDERCLOCKED_STS)
dev_err(arizona->dev, "ISRC1 underclocked\n");
if (val & ARIZONA_FX_UNDERCLOCKED_STS)
dev_err(arizona->dev, "FX underclocked\n");
if (val & ARIZONA_ASRC_UNDERCLOCKED_STS)
dev_err(arizona->dev, "ASRC underclocked\n");
if (val & ARIZONA_DAC_UNDERCLOCKED_STS)
dev_err(arizona->dev, "DAC underclocked\n");
if (val & ARIZONA_ADC_UNDERCLOCKED_STS)
dev_err(arizona->dev, "ADC underclocked\n");
if (val & ARIZONA_MIXER_UNDERCLOCKED_STS)
dev_err(arizona->dev, "Mixer dropped sample\n");
return IRQ_HANDLED;
}
static irqreturn_t arizona_overclocked(int irq, void *data)
{
struct arizona *arizona = data;
unsigned int val[3];
int ret;
ret = regmap_bulk_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_6,
&val[0], 3);
if (ret != 0) {
dev_err(arizona->dev, "Failed to read overclock status: %d\n",
ret);
return IRQ_NONE;
}
switch (arizona->type) {
case WM8998:
case WM1814:
/* Some bits are shifted on WM8998,
* rearrange to match the standard bit layout
*/
val[0] = ((val[0] & 0x60e0) >> 1) |
((val[0] & 0x1e00) >> 2) |
(val[0] & 0x000f);
break;
default:
break;
}
if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS)
dev_err(arizona->dev, "PWM overclocked\n");
if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS)
dev_err(arizona->dev, "FX core overclocked\n");
if (val[0] & ARIZONA_DAC_SYS_OVERCLOCKED_STS)
dev_err(arizona->dev, "DAC SYS overclocked\n");
if (val[0] & ARIZONA_DAC_WARP_OVERCLOCKED_STS)
dev_err(arizona->dev, "DAC WARP overclocked\n");
if (val[0] & ARIZONA_ADC_OVERCLOCKED_STS)
dev_err(arizona->dev, "ADC overclocked\n");
if (val[0] & ARIZONA_MIXER_OVERCLOCKED_STS)
dev_err(arizona->dev, "Mixer overclocked\n");
if (val[0] & ARIZONA_AIF3_SYNC_OVERCLOCKED_STS)
dev_err(arizona->dev, "AIF3 overclocked\n");
if (val[0] & ARIZONA_AIF2_SYNC_OVERCLOCKED_STS)
dev_err(arizona->dev, "AIF2 overclocked\n");
if (val[0] & ARIZONA_AIF1_SYNC_OVERCLOCKED_STS)
dev_err(arizona->dev, "AIF1 overclocked\n");
if (val[0] & ARIZONA_PAD_CTRL_OVERCLOCKED_STS)
dev_err(arizona->dev, "Pad control overclocked\n");
if (val[1] & ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS)
dev_err(arizona->dev, "Slimbus subsystem overclocked\n");
if (val[1] & ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS)
dev_err(arizona->dev, "Slimbus async overclocked\n");
if (val[1] & ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS)
dev_err(arizona->dev, "Slimbus sync overclocked\n");
if (val[1] & ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS)
dev_err(arizona->dev, "ASRC async system overclocked\n");
if (val[1] & ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS)
dev_err(arizona->dev, "ASRC async WARP overclocked\n");
if (val[1] & ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS)
dev_err(arizona->dev, "ASRC sync system overclocked\n");
if (val[1] & ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS)
dev_err(arizona->dev, "ASRC sync WARP overclocked\n");
if (val[1] & ARIZONA_ADSP2_1_OVERCLOCKED_STS)
dev_err(arizona->dev, "DSP1 overclocked\n");
if (val[1] & ARIZONA_ISRC3_OVERCLOCKED_STS)
dev_err(arizona->dev, "ISRC3 overclocked\n");
if (val[1] & ARIZONA_ISRC2_OVERCLOCKED_STS)
dev_err(arizona->dev, "ISRC2 overclocked\n");
if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS)
dev_err(arizona->dev, "ISRC1 overclocked\n");
if (val[2] & ARIZONA_SPDIF_OVERCLOCKED_STS)
dev_err(arizona->dev, "SPDIF overclocked\n");
return IRQ_HANDLED;
}
#define ARIZONA_REG_POLL_DELAY_US 7500
static inline bool arizona_poll_reg_delay(ktime_t timeout)
{
if (ktime_compare(ktime_get(), timeout) > 0)
return false;
usleep_range(ARIZONA_REG_POLL_DELAY_US / 2, ARIZONA_REG_POLL_DELAY_US);
return true;
}
static int arizona_poll_reg(struct arizona *arizona,
int timeout_ms, unsigned int reg,
unsigned int mask, unsigned int target)
{
ktime_t timeout = ktime_add_us(ktime_get(), timeout_ms * USEC_PER_MSEC);
unsigned int val = 0;
int ret;
do {
ret = regmap_read(arizona->regmap, reg, &val);
if ((val & mask) == target)
return 0;
} while (arizona_poll_reg_delay(timeout));
if (ret) {
dev_err(arizona->dev, "Failed polling reg 0x%x: %d\n",
reg, ret);
return ret;
}
dev_err(arizona->dev, "Polling reg 0x%x timed out: %x\n", reg, val);
return -ETIMEDOUT;
}
static int arizona_wait_for_boot(struct arizona *arizona)
{
int ret;
/*
* We can't use an interrupt as we need to runtime resume to do so,
* we won't race with the interrupt handler as it'll be blocked on
* runtime resume.
*/
ret = arizona_poll_reg(arizona, 30, ARIZONA_INTERRUPT_RAW_STATUS_5,
ARIZONA_BOOT_DONE_STS, ARIZONA_BOOT_DONE_STS);
if (!ret)
regmap_write(arizona->regmap, ARIZONA_INTERRUPT_STATUS_5,
ARIZONA_BOOT_DONE_STS);
pm_runtime_mark_last_busy(arizona->dev);
return ret;
}
static inline void arizona_enable_reset(struct arizona *arizona)
{
if (arizona->pdata.reset)
gpiod_set_raw_value_cansleep(arizona->pdata.reset, 0);
}
static void arizona_disable_reset(struct arizona *arizona)
{
if (arizona->pdata.reset) {
switch (arizona->type) {
case WM5110:
case WM8280:
/* Meet requirements for minimum reset duration */
usleep_range(5000, 10000);
break;
default:
break;
}
gpiod_set_raw_value_cansleep(arizona->pdata.reset, 1);
usleep_range(1000, 5000);
}
}
struct arizona_sysclk_state {
unsigned int fll;
unsigned int sysclk;
};
static int arizona_enable_freerun_sysclk(struct arizona *arizona,
struct arizona_sysclk_state *state)
{
int ret, err;
/* Cache existing FLL and SYSCLK settings */
ret = regmap_read(arizona->regmap, ARIZONA_FLL1_CONTROL_1, &state->fll);
if (ret) {
dev_err(arizona->dev, "Failed to cache FLL settings: %d\n",
ret);
return ret;
}
ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1,
&state->sysclk);
if (ret) {
dev_err(arizona->dev, "Failed to cache SYSCLK settings: %d\n",
ret);
return ret;
}
/* Start up SYSCLK using the FLL in free running mode */
ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1,
ARIZONA_FLL1_ENA | ARIZONA_FLL1_FREERUN);
if (ret) {
dev_err(arizona->dev,
"Failed to start FLL in freerunning mode: %d\n",
ret);
return ret;
}
ret = arizona_poll_reg(arizona, 180, ARIZONA_INTERRUPT_RAW_STATUS_5,
ARIZONA_FLL1_CLOCK_OK_STS,
ARIZONA_FLL1_CLOCK_OK_STS);
if (ret)
goto err_fll;
ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, 0x0144);
if (ret) {
dev_err(arizona->dev, "Failed to start SYSCLK: %d\n", ret);
goto err_fll;
}
return 0;
err_fll:
err = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, state->fll);
if (err)
dev_err(arizona->dev,
"Failed to re-apply old FLL settings: %d\n", err);
return ret;
}
static int arizona_disable_freerun_sysclk(struct arizona *arizona,
struct arizona_sysclk_state *state)
{
int ret;
ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1,
state->sysclk);
if (ret) {
dev_err(arizona->dev,
"Failed to re-apply old SYSCLK settings: %d\n", ret);
return ret;
}
ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, state->fll);
if (ret) {
dev_err(arizona->dev,
"Failed to re-apply old FLL settings: %d\n", ret);
return ret;
}
return 0;
}
static int wm5102_apply_hardware_patch(struct arizona *arizona)
{
struct arizona_sysclk_state state;
int err, ret;
ret = arizona_enable_freerun_sysclk(arizona, &state);
if (ret)
return ret;
/* Start the write sequencer and wait for it to finish */
ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
ARIZONA_WSEQ_ENA | ARIZONA_WSEQ_START | 160);
if (ret) {
dev_err(arizona->dev, "Failed to start write sequencer: %d\n",
ret);
goto err;
}
ret = arizona_poll_reg(arizona, 30, ARIZONA_WRITE_SEQUENCER_CTRL_1,
ARIZONA_WSEQ_BUSY, 0);
if (ret)
regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
ARIZONA_WSEQ_ABORT);
err:
err = arizona_disable_freerun_sysclk(arizona, &state);
return ret ?: err;
}
/*
* Register patch to some of the CODECs internal write sequences
* to ensure a clean exit from the low power sleep state.
*/
static const struct reg_sequence wm5110_sleep_patch[] = {
{ 0x337A, 0xC100 },
{ 0x337B, 0x0041 },
{ 0x3300, 0xA210 },
{ 0x3301, 0x050C },
};
static int wm5110_apply_sleep_patch(struct arizona *arizona)
{
struct arizona_sysclk_state state;
int err, ret;
ret = arizona_enable_freerun_sysclk(arizona, &state);
if (ret)
return ret;
ret = regmap_multi_reg_write_bypassed(arizona->regmap,
wm5110_sleep_patch,
ARRAY_SIZE(wm5110_sleep_patch));
err = arizona_disable_freerun_sysclk(arizona, &state);
return ret ?: err;
}
static int wm5102_clear_write_sequencer(struct arizona *arizona)
{
int ret;
ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_3,
0x0);
if (ret) {
dev_err(arizona->dev,
"Failed to clear write sequencer state: %d\n", ret);
return ret;
}
arizona_enable_reset(arizona);
regulator_disable(arizona->dcvdd);
msleep(20);
ret = regulator_enable(arizona->dcvdd);
if (ret) {
dev_err(arizona->dev, "Failed to re-enable DCVDD: %d\n", ret);
return ret;
}
arizona_disable_reset(arizona);
return 0;
}
static int arizona_isolate_dcvdd(struct arizona *arizona)
{
int ret;
ret = regmap_update_bits(arizona->regmap,
ARIZONA_ISOLATION_CONTROL,
ARIZONA_ISOLATE_DCVDD1,
ARIZONA_ISOLATE_DCVDD1);
if (ret != 0)
dev_err(arizona->dev, "Failed to isolate DCVDD: %d\n", ret);
return ret;
}
static int arizona_connect_dcvdd(struct arizona *arizona)
{
int ret;
ret = regmap_update_bits(arizona->regmap,
ARIZONA_ISOLATION_CONTROL,
ARIZONA_ISOLATE_DCVDD1, 0);
if (ret != 0)
dev_err(arizona->dev, "Failed to connect DCVDD: %d\n", ret);
return ret;
}
static int arizona_is_jack_det_active(struct arizona *arizona)
{
unsigned int val;
int ret;
ret = regmap_read(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, &val);
if (ret) {
dev_err(arizona->dev,
"Failed to check jack det status: %d\n", ret);
return ret;
} else if (val & ARIZONA_JD1_ENA) {
return 1;
} else {
return 0;
}
}
static int arizona_runtime_resume(struct device *dev)
{
struct arizona *arizona = dev_get_drvdata(dev);
int ret;
dev_dbg(arizona->dev, "Leaving AoD mode\n");
if (arizona->has_fully_powered_off) {
dev_dbg(arizona->dev, "Re-enabling core supplies\n");
ret = regulator_bulk_enable(arizona->num_core_supplies,
arizona->core_supplies);
if (ret) {
dev_err(dev, "Failed to enable core supplies: %d\n",
ret);
return ret;
}
}
ret = regulator_enable(arizona->dcvdd);
if (ret != 0) {
dev_err(arizona->dev, "Failed to enable DCVDD: %d\n", ret);
if (arizona->has_fully_powered_off)
regulator_bulk_disable(arizona->num_core_supplies,
arizona->core_supplies);
return ret;
}
if (arizona->has_fully_powered_off) {
arizona_disable_reset(arizona);
enable_irq(arizona->irq);
arizona->has_fully_powered_off = false;
}
regcache_cache_only(arizona->regmap, false);
switch (arizona->type) {
case WM5102:
if (arizona->external_dcvdd) {
ret = arizona_connect_dcvdd(arizona);
if (ret != 0)
goto err;
}
ret = wm5102_patch(arizona);
if (ret != 0) {
dev_err(arizona->dev, "Failed to apply patch: %d\n",
ret);
goto err;
}
ret = wm5102_apply_hardware_patch(arizona);
if (ret) {
dev_err(arizona->dev,
"Failed to apply hardware patch: %d\n",
ret);
goto err;
}
break;
case WM5110:
case WM8280:
ret = arizona_wait_for_boot(arizona);
if (ret)
goto err;
if (arizona->external_dcvdd) {
ret = arizona_connect_dcvdd(arizona);
if (ret != 0)
goto err;
} else {
/*
* As this is only called for the internal regulator
* (where we know voltage ranges available) it is ok
* to request an exact range.
*/
ret = regulator_set_voltage(arizona->dcvdd,
1200000, 1200000);
if (ret < 0) {
dev_err(arizona->dev,
"Failed to set resume voltage: %d\n",
ret);
goto err;
}
}
ret = wm5110_apply_sleep_patch(arizona);
if (ret) {
dev_err(arizona->dev,
"Failed to re-apply sleep patch: %d\n",
ret);
goto err;
}
break;
case WM1831:
case CS47L24:
ret = arizona_wait_for_boot(arizona);
if (ret != 0)
goto err;
break;
default:
ret = arizona_wait_for_boot(arizona);
if (ret != 0)
goto err;
if (arizona->external_dcvdd) {
ret = arizona_connect_dcvdd(arizona);
if (ret != 0)
goto err;
}
break;
}
ret = regcache_sync(arizona->regmap);
if (ret != 0) {
dev_err(arizona->dev, "Failed to restore register cache\n");
goto err;
}
return 0;
err:
regcache_cache_only(arizona->regmap, true);
regulator_disable(arizona->dcvdd);
return ret;
}
static int arizona_runtime_suspend(struct device *dev)
{
struct arizona *arizona = dev_get_drvdata(dev);
int jd_active = 0;
int ret;
dev_dbg(arizona->dev, "Entering AoD mode\n");
switch (arizona->type) {
case WM5110:
case WM8280:
jd_active = arizona_is_jack_det_active(arizona);
if (jd_active < 0)
return jd_active;
if (arizona->external_dcvdd) {
ret = arizona_isolate_dcvdd(arizona);
if (ret != 0)
return ret;
} else {
/*
* As this is only called for the internal regulator
* (where we know voltage ranges available) it is ok
* to request an exact range.
*/
ret = regulator_set_voltage(arizona->dcvdd,
1175000, 1175000);
if (ret < 0) {
dev_err(arizona->dev,
"Failed to set suspend voltage: %d\n",
ret);
return ret;
}
}
break;
case WM5102:
jd_active = arizona_is_jack_det_active(arizona);
if (jd_active < 0)
return jd_active;
if (arizona->external_dcvdd) {
ret = arizona_isolate_dcvdd(arizona);
if (ret != 0)
return ret;
}
if (!jd_active) {
ret = regmap_write(arizona->regmap,
ARIZONA_WRITE_SEQUENCER_CTRL_3, 0x0);
if (ret) {
dev_err(arizona->dev,
"Failed to clear write sequencer: %d\n",
ret);
return ret;
}
}
break;
case WM1831:
case CS47L24:
break;
default:
jd_active = arizona_is_jack_det_active(arizona);
if (jd_active < 0)
return jd_active;
if (arizona->external_dcvdd) {
ret = arizona_isolate_dcvdd(arizona);
if (ret != 0)
return ret;
}
break;
}
regcache_cache_only(arizona->regmap, true);
regcache_mark_dirty(arizona->regmap);
regulator_disable(arizona->dcvdd);
/* Allow us to completely power down if no jack detection */
if (!jd_active) {
dev_dbg(arizona->dev, "Fully powering off\n");
arizona->has_fully_powered_off = true;
disable_irq_nosync(arizona->irq);
arizona_enable_reset(arizona);
regulator_bulk_disable(arizona->num_core_supplies,
arizona->core_supplies);
}
return 0;
}
static int arizona_suspend(struct device *dev)
{
struct arizona *arizona = dev_get_drvdata(dev);
dev_dbg(arizona->dev, "Suspend, disabling IRQ\n");
disable_irq(arizona->irq);
return 0;
}
static int arizona_suspend_noirq(struct device *dev)
{
struct arizona *arizona = dev_get_drvdata(dev);
dev_dbg(arizona->dev, "Late suspend, reenabling IRQ\n");
enable_irq(arizona->irq);
return 0;
}
static int arizona_resume_noirq(struct device *dev)
{
struct arizona *arizona = dev_get_drvdata(dev);
dev_dbg(arizona->dev, "Early resume, disabling IRQ\n");
disable_irq(arizona->irq);
return 0;
}
static int arizona_resume(struct device *dev)
{
struct arizona *arizona = dev_get_drvdata(dev);
dev_dbg(arizona->dev, "Resume, reenabling IRQ\n");
enable_irq(arizona->irq);
return 0;
}
EXPORT_GPL_DEV_PM_OPS(arizona_pm_ops) = {
RUNTIME_PM_OPS(arizona_runtime_suspend,
arizona_runtime_resume,
NULL)
SYSTEM_SLEEP_PM_OPS(arizona_suspend, arizona_resume)
NOIRQ_SYSTEM_SLEEP_PM_OPS(arizona_suspend_noirq,
arizona_resume_noirq)
};
#ifdef CONFIG_OF
static int arizona_of_get_core_pdata(struct arizona *arizona)
{
struct arizona_pdata *pdata = &arizona->pdata;
int ret, i;
/* Handle old non-standard DT binding */
pdata->reset = devm_gpiod_get(arizona->dev, "wlf,reset", GPIOD_OUT_LOW);
if (IS_ERR(pdata->reset)) {
ret = PTR_ERR(pdata->reset);
/*
* Reset missing will be caught when other binding is read
* but all other errors imply this binding is in use but has
* encountered a problem so should be handled.
*/
if (ret == -EPROBE_DEFER)
return ret;
else if (ret != -ENOENT && ret != -ENOSYS)
dev_err(arizona->dev, "Reset GPIO malformed: %d\n",
ret);
pdata->reset = NULL;
}
ret = of_property_read_u32_array(arizona->dev->of_node,
"wlf,gpio-defaults",
pdata->gpio_defaults,
ARRAY_SIZE(pdata->gpio_defaults));
if (ret >= 0) {
/*
* All values are literal except out of range values
* which are chip default, translate into platform
* data which uses 0 as chip default and out of range
* as zero.
*/
for (i = 0; i < ARRAY_SIZE(pdata->gpio_defaults); i++) {
if (pdata->gpio_defaults[i] > 0xffff)
pdata->gpio_defaults[i] = 0;
else if (pdata->gpio_defaults[i] == 0)
pdata->gpio_defaults[i] = 0x10000;
}
} else {
dev_err(arizona->dev, "Failed to parse GPIO defaults: %d\n",
ret);
}
return 0;
}
#else
static inline int arizona_of_get_core_pdata(struct arizona *arizona)
{
return 0;
}
#endif
static const struct mfd_cell early_devs[] = {
{ .name = "arizona-ldo1" },
};
static const char * const wm5102_supplies[] = {
"MICVDD",
"DBVDD2",
"DBVDD3",
"CPVDD",
"SPKVDDL",
"SPKVDDR",
};
static const struct mfd_cell wm5102_devs[] = {
{ .name = "arizona-micsupp" },
{ .name = "arizona-gpio" },
{ .name = "arizona-haptics" },
{ .name = "arizona-pwm" },
{
.name = "wm5102-codec",
.parent_supplies = wm5102_supplies,
.num_parent_supplies = ARRAY_SIZE(wm5102_supplies),
},
};
static const struct mfd_cell wm5110_devs[] = {
{ .name = "arizona-micsupp" },
{ .name = "arizona-gpio" },
{ .name = "arizona-haptics" },
{ .name = "arizona-pwm" },
{
.name = "wm5110-codec",
.parent_supplies = wm5102_supplies,
.num_parent_supplies = ARRAY_SIZE(wm5102_supplies),
},
};
static const char * const cs47l24_supplies[] = {
"MICVDD",
"CPVDD",
"SPKVDD",
};
static const struct mfd_cell cs47l24_devs[] = {
{ .name = "arizona-gpio" },
{ .name = "arizona-haptics" },
{ .name = "arizona-pwm" },
{
.name = "cs47l24-codec",
.parent_supplies = cs47l24_supplies,
.num_parent_supplies = ARRAY_SIZE(cs47l24_supplies),
},
};
static const char * const wm8997_supplies[] = {
"MICVDD",
"DBVDD2",
"CPVDD",
"SPKVDD",
};
static const struct mfd_cell wm8997_devs[] = {
{ .name = "arizona-micsupp" },
{ .name = "arizona-gpio" },
{ .name = "arizona-haptics" },
{ .name = "arizona-pwm" },
{
.name = "wm8997-codec",
.parent_supplies = wm8997_supplies,
.num_parent_supplies = ARRAY_SIZE(wm8997_supplies),
},
};
static const struct mfd_cell wm8998_devs[] = {
{ .name = "arizona-micsupp" },
{ .name = "arizona-gpio" },
{ .name = "arizona-haptics" },
{ .name = "arizona-pwm" },
{
.name = "wm8998-codec",
.parent_supplies = wm5102_supplies,
.num_parent_supplies = ARRAY_SIZE(wm5102_supplies),
},
};
int arizona_dev_init(struct arizona *arizona)
{
static const char * const mclk_name[] = { "mclk1", "mclk2" };
struct device *dev = arizona->dev;
const char *type_name = NULL;
unsigned int reg, val;
int (*apply_patch)(struct arizona *) = NULL;
const struct mfd_cell *subdevs = NULL;
int n_subdevs = 0, ret, i;
dev_set_drvdata(arizona->dev, arizona);
mutex_init(&arizona->clk_lock);
if (dev_get_platdata(arizona->dev)) {
memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
sizeof(arizona->pdata));
} else {
ret = arizona_of_get_core_pdata(arizona);
if (ret < 0)
return ret;
}
BUILD_BUG_ON(ARRAY_SIZE(arizona->mclk) != ARRAY_SIZE(mclk_name));
for (i = 0; i < ARRAY_SIZE(arizona->mclk); i++) {
arizona->mclk[i] = devm_clk_get(arizona->dev, mclk_name[i]);
if (IS_ERR(arizona->mclk[i])) {
dev_info(arizona->dev, "Failed to get %s: %ld\n",
mclk_name[i], PTR_ERR(arizona->mclk[i]));
arizona->mclk[i] = NULL;
}
}
regcache_cache_only(arizona->regmap, true);
switch (arizona->type) {
case WM5102:
case WM5110:
case WM8280:
case WM8997:
case WM8998:
case WM1814:
case WM1831:
case CS47L24:
for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
arizona->core_supplies[i].supply
= wm5102_core_supplies[i];
arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
break;
default:
dev_err(arizona->dev, "Unknown device type %d\n",
arizona->type);
return -ENODEV;
}
/* Mark DCVDD as external, LDO1 driver will clear if internal */
arizona->external_dcvdd = true;
switch (arizona->type) {
case WM1831:
case CS47L24:
break; /* No LDO1 regulator */
default:
ret = mfd_add_devices(arizona->dev, -1, early_devs,
ARRAY_SIZE(early_devs), NULL, 0, NULL);
if (ret != 0) {
dev_err(dev, "Failed to add early children: %d\n", ret);
return ret;
}
break;
}
ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies,
arizona->core_supplies);
if (ret != 0) {
dev_err(dev, "Failed to request core supplies: %d\n",
ret);
goto err_early;
}
/**
* Don't use devres here because the only device we have to get
* against is the MFD device and DCVDD will likely be supplied by
* one of its children. Meaning that the regulator will be
* destroyed by the time devres calls regulator put.
*/
arizona->dcvdd = regulator_get(arizona->dev, "DCVDD");
if (IS_ERR(arizona->dcvdd)) {
ret = PTR_ERR(arizona->dcvdd);
dev_err(dev, "Failed to request DCVDD: %d\n", ret);
goto err_early;
}
if (!arizona->pdata.reset) {
/* Start out with /RESET low to put the chip into reset */
arizona->pdata.reset = devm_gpiod_get(arizona->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(arizona->pdata.reset)) {
ret = PTR_ERR(arizona->pdata.reset);
if (ret == -EPROBE_DEFER)
goto err_dcvdd;
dev_err(arizona->dev,
"Reset GPIO missing/malformed: %d\n", ret);
arizona->pdata.reset = NULL;
}
}
ret = regulator_bulk_enable(arizona->num_core_supplies,
arizona->core_supplies);
if (ret != 0) {
dev_err(dev, "Failed to enable core supplies: %d\n",
ret);
goto err_dcvdd;
}
ret = regulator_enable(arizona->dcvdd);
if (ret != 0) {
dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
goto err_enable;
}
arizona_disable_reset(arizona);
regcache_cache_only(arizona->regmap, false);
/* Verify that this is a chip we know about */
ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, ®);
if (ret != 0) {
dev_err(dev, "Failed to read ID register: %d\n", ret);
goto err_reset;
}
switch (reg) {
case 0x5102:
case 0x5110:
case 0x6349:
case 0x6363:
case 0x8997:
break;
default:
dev_err(arizona->dev, "Unknown device ID: %x\n", reg);
ret = -ENODEV;
goto err_reset;
}
/* If we have a /RESET GPIO we'll already be reset */
if (!arizona->pdata.reset) {
ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
if (ret != 0) {
dev_err(dev, "Failed to reset device: %d\n", ret);
goto err_reset;
}
usleep_range(1000, 5000);
}
/* Ensure device startup is complete */
switch (arizona->type) {
case WM5102:
ret = regmap_read(arizona->regmap,
ARIZONA_WRITE_SEQUENCER_CTRL_3, &val);
if (ret) {
dev_err(dev,
"Failed to check write sequencer state: %d\n",
ret);
} else if (val & 0x01) {
ret = wm5102_clear_write_sequencer(arizona);
if (ret)
return ret;
}
break;
default:
break;
}
ret = arizona_wait_for_boot(arizona);
if (ret) {
dev_err(arizona->dev, "Device failed initial boot: %d\n", ret);
goto err_reset;
}
/* Read the device ID information & do device specific stuff */
ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, ®);
if (ret != 0) {
dev_err(dev, "Failed to read ID register: %d\n", ret);
goto err_reset;
}
ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
&arizona->rev);
if (ret != 0) {
dev_err(dev, "Failed to read revision register: %d\n", ret);
goto err_reset;
}
arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
switch (reg) {
case 0x5102:
if (IS_ENABLED(CONFIG_MFD_WM5102)) {
type_name = "WM5102";
if (arizona->type != WM5102) {
dev_warn(arizona->dev,
"WM5102 registered as %d\n",
arizona->type);
arizona->type = WM5102;
}
apply_patch = wm5102_patch;
arizona->rev &= 0x7;
subdevs = wm5102_devs;
n_subdevs = ARRAY_SIZE(wm5102_devs);
}
break;
case 0x5110:
if (IS_ENABLED(CONFIG_MFD_WM5110)) {
switch (arizona->type) {
case WM5110:
type_name = "WM5110";
break;
case WM8280:
type_name = "WM8280";
break;
default:
type_name = "WM5110";
dev_warn(arizona->dev,
"WM5110 registered as %d\n",
arizona->type);
arizona->type = WM5110;
break;
}
apply_patch = wm5110_patch;
subdevs = wm5110_devs;
n_subdevs = ARRAY_SIZE(wm5110_devs);
}
break;
case 0x6363:
if (IS_ENABLED(CONFIG_MFD_CS47L24)) {
switch (arizona->type) {
case CS47L24:
type_name = "CS47L24";
break;
case WM1831:
type_name = "WM1831";
break;
default:
dev_warn(arizona->dev,
"CS47L24 registered as %d\n",
arizona->type);
arizona->type = CS47L24;
break;
}
apply_patch = cs47l24_patch;
subdevs = cs47l24_devs;
n_subdevs = ARRAY_SIZE(cs47l24_devs);
}
break;
case 0x8997:
if (IS_ENABLED(CONFIG_MFD_WM8997)) {
type_name = "WM8997";
if (arizona->type != WM8997) {
dev_warn(arizona->dev,
"WM8997 registered as %d\n",
arizona->type);
arizona->type = WM8997;
}
apply_patch = wm8997_patch;
subdevs = wm8997_devs;
n_subdevs = ARRAY_SIZE(wm8997_devs);
}
break;
case 0x6349:
if (IS_ENABLED(CONFIG_MFD_WM8998)) {
switch (arizona->type) {
case WM8998:
type_name = "WM8998";
break;
case WM1814:
type_name = "WM1814";
break;
default:
type_name = "WM8998";
dev_warn(arizona->dev,
"WM8998 registered as %d\n",
arizona->type);
arizona->type = WM8998;
}
apply_patch = wm8998_patch;
subdevs = wm8998_devs;
n_subdevs = ARRAY_SIZE(wm8998_devs);
}
break;
default:
dev_err(arizona->dev, "Unknown device ID %x\n", reg);
ret = -ENODEV;
goto err_reset;
}
if (!subdevs) {
dev_err(arizona->dev,
"No kernel support for device ID %x\n", reg);
ret = -ENODEV;
goto err_reset;
}
dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
if (apply_patch) {
ret = apply_patch(arizona);
if (ret != 0) {
dev_err(arizona->dev, "Failed to apply patch: %d\n",
ret);
goto err_reset;
}
switch (arizona->type) {
case WM5102:
ret = wm5102_apply_hardware_patch(arizona);
if (ret) {
dev_err(arizona->dev,
"Failed to apply hardware patch: %d\n",
ret);
goto err_reset;
}
break;
case WM5110:
case WM8280:
ret = wm5110_apply_sleep_patch(arizona);
if (ret) {
dev_err(arizona->dev,
"Failed to apply sleep patch: %d\n",
ret);
goto err_reset;
}
break;
default:
break;
}
}
for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
if (!arizona->pdata.gpio_defaults[i])
continue;
regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
arizona->pdata.gpio_defaults[i]);
}
/* Chip default */
if (!arizona->pdata.clk32k_src)
arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
switch (arizona->pdata.clk32k_src) {
case ARIZONA_32KZ_MCLK1:
case ARIZONA_32KZ_MCLK2:
regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
ARIZONA_CLK_32K_SRC_MASK,
arizona->pdata.clk32k_src - 1);
arizona_clk32k_enable(arizona);
break;
case ARIZONA_32KZ_NONE:
regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
ARIZONA_CLK_32K_SRC_MASK, 2);
break;
default:
dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
arizona->pdata.clk32k_src);
ret = -EINVAL;
goto err_reset;
}
for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) {
if (!arizona->pdata.micbias[i].mV &&
!arizona->pdata.micbias[i].bypass)
continue;
/* Apply default for bypass mode */
if (!arizona->pdata.micbias[i].mV)
arizona->pdata.micbias[i].mV = 2800;
val = (arizona->pdata.micbias[i].mV - 1500) / 100;
val <<= ARIZONA_MICB1_LVL_SHIFT;
if (arizona->pdata.micbias[i].ext_cap)
val |= ARIZONA_MICB1_EXT_CAP;
if (arizona->pdata.micbias[i].discharge)
val |= ARIZONA_MICB1_DISCH;
if (arizona->pdata.micbias[i].soft_start)
val |= ARIZONA_MICB1_RATE;
if (arizona->pdata.micbias[i].bypass)
val |= ARIZONA_MICB1_BYPASS;
regmap_update_bits(arizona->regmap,
ARIZONA_MIC_BIAS_CTRL_1 + i,
ARIZONA_MICB1_LVL_MASK |
ARIZONA_MICB1_EXT_CAP |
ARIZONA_MICB1_DISCH |
ARIZONA_MICB1_BYPASS |
ARIZONA_MICB1_RATE, val);
}
pm_runtime_set_active(arizona->dev);
pm_runtime_enable(arizona->dev);
/* Set up for interrupts */
ret = arizona_irq_init(arizona);
if (ret != 0)
goto err_pm;
pm_runtime_set_autosuspend_delay(arizona->dev, 100);
pm_runtime_use_autosuspend(arizona->dev);
arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
arizona_clkgen_err, arizona);
arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
arizona_overclocked, arizona);
arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
arizona_underclocked, arizona);
ret = mfd_add_devices(arizona->dev, PLATFORM_DEVID_NONE,
subdevs, n_subdevs, NULL, 0, NULL);
if (ret) {
dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
goto err_irq;
}
return 0;
err_irq:
arizona_irq_exit(arizona);
err_pm:
pm_runtime_disable(arizona->dev);
switch (arizona->pdata.clk32k_src) {
case ARIZONA_32KZ_MCLK1:
case ARIZONA_32KZ_MCLK2:
arizona_clk32k_disable(arizona);
break;
default:
break;
}
err_reset:
arizona_enable_reset(arizona);
regulator_disable(arizona->dcvdd);
err_enable:
regulator_bulk_disable(arizona->num_core_supplies,
arizona->core_supplies);
err_dcvdd:
regulator_put(arizona->dcvdd);
err_early:
mfd_remove_devices(dev);
return ret;
}
EXPORT_SYMBOL_GPL(arizona_dev_init);
int arizona_dev_exit(struct arizona *arizona)
{
disable_irq(arizona->irq);
pm_runtime_disable(arizona->dev);
regulator_disable(arizona->dcvdd);
regulator_put(arizona->dcvdd);
switch (arizona->pdata.clk32k_src) {
case ARIZONA_32KZ_MCLK1:
case ARIZONA_32KZ_MCLK2:
arizona_clk32k_disable(arizona);
break;
default:
break;
}
mfd_remove_devices(arizona->dev);
arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona);
arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona);
arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona);
arizona_irq_exit(arizona);
arizona_enable_reset(arizona);
regulator_bulk_disable(arizona->num_core_supplies,
arizona->core_supplies);
return 0;
}
EXPORT_SYMBOL_GPL(arizona_dev_exit);
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/arizona-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Core driver for STw4810/STw4811
*
* Copyright (C) 2013 ST-Ericsson SA
* Written on behalf of Linaro for ST-Ericsson
*
* Author: Linus Walleij <[email protected]>
*/
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/mfd/core.h>
#include <linux/mfd/stw481x.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
/*
* This driver can only access the non-USB portions of STw4811, the register
* range 0x00-0x10 dealing with USB is bound to the two special I2C pins used
* for USB control.
*/
/* Registers inside the power control address space */
#define STW_PC_VCORE_SEL 0x05U
#define STW_PC_VAUX_SEL 0x06U
#define STW_PC_VPLL_SEL 0x07U
/**
* stw481x_get_pctl_reg() - get a power control register
* @stw481x: handle to the stw481x chip
* @reg: power control register to fetch
*
* The power control registers is a set of one-time-programmable registers
* in its own register space, accessed by writing addess bits to these
* two registers: bits 7,6,5 of PCTL_REG_LO corresponds to the 3 LSBs of
* the address and bits 8,9 of PCTL_REG_HI corresponds to the 2 MSBs of
* the address, forming an address space of 5 bits, i.e. 32 registers
* 0x00 ... 0x1f can be obtained.
*/
static int stw481x_get_pctl_reg(struct stw481x *stw481x, u8 reg)
{
u8 msb = (reg >> 3) & 0x03;
u8 lsb = (reg << 5) & 0xe0;
unsigned int val;
u8 vrfy;
int ret;
ret = regmap_write(stw481x->map, STW_PCTL_REG_HI, msb);
if (ret)
return ret;
ret = regmap_write(stw481x->map, STW_PCTL_REG_LO, lsb);
if (ret)
return ret;
ret = regmap_read(stw481x->map, STW_PCTL_REG_HI, &val);
if (ret)
return ret;
vrfy = (val & 0x03) << 3;
ret = regmap_read(stw481x->map, STW_PCTL_REG_LO, &val);
if (ret)
return ret;
vrfy |= ((val >> 5) & 0x07);
if (vrfy != reg)
return -EIO;
return (val >> 1) & 0x0f;
}
static int stw481x_startup(struct stw481x *stw481x)
{
/* Voltages multiplied by 100 */
static const u8 vcore_val[] = {
100, 105, 110, 115, 120, 122, 124, 126, 128,
130, 132, 134, 136, 138, 140, 145
};
static const u8 vpll_val[] = { 105, 120, 130, 180 };
static const u8 vaux_val[] = { 15, 18, 25, 28 };
u8 vcore;
u8 vcore_slp;
u8 vpll;
u8 vaux;
bool vaux_en;
bool it_warn;
int ret;
unsigned int val;
ret = regmap_read(stw481x->map, STW_CONF1, &val);
if (ret)
return ret;
vaux_en = !!(val & STW_CONF1_PDN_VAUX);
it_warn = !!(val & STW_CONF1_IT_WARN);
dev_info(&stw481x->client->dev, "voltages %s\n",
(val & STW_CONF1_V_MONITORING) ? "OK" : "LOW");
dev_info(&stw481x->client->dev, "MMC level shifter %s\n",
(val & STW_CONF1_MMC_LS_STATUS) ? "high impedance" : "ON");
dev_info(&stw481x->client->dev, "VMMC: %s\n",
(val & STW_CONF1_PDN_VMMC) ? "ON" : "disabled");
dev_info(&stw481x->client->dev, "STw481x power control registers:\n");
ret = stw481x_get_pctl_reg(stw481x, STW_PC_VCORE_SEL);
if (ret < 0)
return ret;
vcore = ret & 0x0f;
ret = stw481x_get_pctl_reg(stw481x, STW_PC_VAUX_SEL);
if (ret < 0)
return ret;
vaux = (ret >> 2) & 3;
vpll = (ret >> 4) & 1; /* Save bit 4 */
ret = stw481x_get_pctl_reg(stw481x, STW_PC_VPLL_SEL);
if (ret < 0)
return ret;
vpll |= (ret >> 1) & 2;
dev_info(&stw481x->client->dev, "VCORE: %u.%uV %s\n",
vcore_val[vcore] / 100, vcore_val[vcore] % 100,
(ret & 4) ? "ON" : "OFF");
dev_info(&stw481x->client->dev, "VPLL: %u.%uV %s\n",
vpll_val[vpll] / 100, vpll_val[vpll] % 100,
(ret & 0x10) ? "ON" : "OFF");
dev_info(&stw481x->client->dev, "VAUX: %u.%uV %s\n",
vaux_val[vaux] / 10, vaux_val[vaux] % 10,
vaux_en ? "ON" : "OFF");
ret = regmap_read(stw481x->map, STW_CONF2, &val);
if (ret)
return ret;
dev_info(&stw481x->client->dev, "TWARN: %s threshold, %s\n",
it_warn ? "below" : "above",
(val & STW_CONF2_MASK_TWARN) ?
"enabled" : "mask through VDDOK");
dev_info(&stw481x->client->dev, "VMMC: %s\n",
(val & STW_CONF2_VMMC_EXT) ? "internal" : "external");
dev_info(&stw481x->client->dev, "IT WAKE UP: %s\n",
(val & STW_CONF2_MASK_IT_WAKE_UP) ? "enabled" : "masked");
dev_info(&stw481x->client->dev, "GPO1: %s\n",
(val & STW_CONF2_GPO1) ? "low" : "high impedance");
dev_info(&stw481x->client->dev, "GPO2: %s\n",
(val & STW_CONF2_GPO2) ? "low" : "high impedance");
ret = regmap_read(stw481x->map, STW_VCORE_SLEEP, &val);
if (ret)
return ret;
vcore_slp = val & 0x0f;
dev_info(&stw481x->client->dev, "VCORE SLEEP: %u.%uV\n",
vcore_val[vcore_slp] / 100, vcore_val[vcore_slp] % 100);
return 0;
}
/*
* MFD cells - we have one cell which is selected operation
* mode, and we always have a GPIO cell.
*/
static struct mfd_cell stw481x_cells[] = {
{
.of_compatible = "st,stw481x-vmmc",
.name = "stw481x-vmmc-regulator",
.id = -1,
},
};
static const struct regmap_config stw481x_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
static int stw481x_probe(struct i2c_client *client)
{
struct stw481x *stw481x;
int ret;
int i;
stw481x = devm_kzalloc(&client->dev, sizeof(*stw481x), GFP_KERNEL);
if (!stw481x)
return -ENOMEM;
i2c_set_clientdata(client, stw481x);
stw481x->client = client;
stw481x->map = devm_regmap_init_i2c(client, &stw481x_regmap_config);
if (IS_ERR(stw481x->map)) {
ret = PTR_ERR(stw481x->map);
dev_err(&client->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
ret = stw481x_startup(stw481x);
if (ret) {
dev_err(&client->dev, "chip initialization failed\n");
return ret;
}
/* Set up and register the platform devices. */
for (i = 0; i < ARRAY_SIZE(stw481x_cells); i++) {
/* One state holder for all drivers, this is simple */
stw481x_cells[i].platform_data = stw481x;
stw481x_cells[i].pdata_size = sizeof(*stw481x);
}
ret = devm_mfd_add_devices(&client->dev, 0, stw481x_cells,
ARRAY_SIZE(stw481x_cells), NULL, 0, NULL);
if (ret)
return ret;
dev_info(&client->dev, "initialized STw481x device\n");
return ret;
}
/*
* This ID table is completely unused, as this is a pure
* device-tree probed driver, but it has to be here due to
* the structure of the I2C core.
*/
static const struct i2c_device_id stw481x_id[] = {
{ "stw481x", 0 },
{ },
};
MODULE_DEVICE_TABLE(i2c, stw481x_id);
static const struct of_device_id stw481x_match[] = {
{ .compatible = "st,stw4810", },
{ .compatible = "st,stw4811", },
{ },
};
MODULE_DEVICE_TABLE(of, stw481x_match);
static struct i2c_driver stw481x_driver = {
.driver = {
.name = "stw481x",
.of_match_table = stw481x_match,
},
.probe = stw481x_probe,
.id_table = stw481x_id,
};
module_i2c_driver(stw481x_driver);
MODULE_AUTHOR("Linus Walleij");
MODULE_DESCRIPTION("STw481x PMIC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/stw481x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* drivers/mfd/si476x-cmd.c -- Subroutines implementing command
* protocol of si476x series of chips
*
* Copyright (C) 2012 Innovative Converged Devices(ICD)
* Copyright (C) 2013 Andrey Smirnov
*
* Author: Andrey Smirnov <[email protected]>
*/
#include <linux/module.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/atomic.h>
#include <linux/i2c.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/videodev2.h>
#include <linux/mfd/si476x-core.h>
#include <asm/unaligned.h>
#define msb(x) ((u8)((u16) x >> 8))
#define lsb(x) ((u8)((u16) x & 0x00FF))
#define CMD_POWER_UP 0x01
#define CMD_POWER_UP_A10_NRESP 1
#define CMD_POWER_UP_A10_NARGS 5
#define CMD_POWER_UP_A20_NRESP 1
#define CMD_POWER_UP_A20_NARGS 5
#define POWER_UP_DELAY_MS 110
#define CMD_POWER_DOWN 0x11
#define CMD_POWER_DOWN_A10_NRESP 1
#define CMD_POWER_DOWN_A20_NRESP 1
#define CMD_POWER_DOWN_A20_NARGS 1
#define CMD_FUNC_INFO 0x12
#define CMD_FUNC_INFO_NRESP 7
#define CMD_SET_PROPERTY 0x13
#define CMD_SET_PROPERTY_NARGS 5
#define CMD_SET_PROPERTY_NRESP 1
#define CMD_GET_PROPERTY 0x14
#define CMD_GET_PROPERTY_NARGS 3
#define CMD_GET_PROPERTY_NRESP 4
#define CMD_AGC_STATUS 0x17
#define CMD_AGC_STATUS_NRESP_A10 2
#define CMD_AGC_STATUS_NRESP_A20 6
#define PIN_CFG_BYTE(x) (0x7F & (x))
#define CMD_DIG_AUDIO_PIN_CFG 0x18
#define CMD_DIG_AUDIO_PIN_CFG_NARGS 4
#define CMD_DIG_AUDIO_PIN_CFG_NRESP 5
#define CMD_ZIF_PIN_CFG 0x19
#define CMD_ZIF_PIN_CFG_NARGS 4
#define CMD_ZIF_PIN_CFG_NRESP 5
#define CMD_IC_LINK_GPO_CTL_PIN_CFG 0x1A
#define CMD_IC_LINK_GPO_CTL_PIN_CFG_NARGS 4
#define CMD_IC_LINK_GPO_CTL_PIN_CFG_NRESP 5
#define CMD_ANA_AUDIO_PIN_CFG 0x1B
#define CMD_ANA_AUDIO_PIN_CFG_NARGS 1
#define CMD_ANA_AUDIO_PIN_CFG_NRESP 2
#define CMD_INTB_PIN_CFG 0x1C
#define CMD_INTB_PIN_CFG_NARGS 2
#define CMD_INTB_PIN_CFG_A10_NRESP 6
#define CMD_INTB_PIN_CFG_A20_NRESP 3
#define CMD_FM_TUNE_FREQ 0x30
#define CMD_FM_TUNE_FREQ_A10_NARGS 5
#define CMD_FM_TUNE_FREQ_A20_NARGS 3
#define CMD_FM_TUNE_FREQ_NRESP 1
#define CMD_FM_RSQ_STATUS 0x32
#define CMD_FM_RSQ_STATUS_A10_NARGS 1
#define CMD_FM_RSQ_STATUS_A10_NRESP 17
#define CMD_FM_RSQ_STATUS_A30_NARGS 1
#define CMD_FM_RSQ_STATUS_A30_NRESP 23
#define CMD_FM_SEEK_START 0x31
#define CMD_FM_SEEK_START_NARGS 1
#define CMD_FM_SEEK_START_NRESP 1
#define CMD_FM_RDS_STATUS 0x36
#define CMD_FM_RDS_STATUS_NARGS 1
#define CMD_FM_RDS_STATUS_NRESP 16
#define CMD_FM_RDS_BLOCKCOUNT 0x37
#define CMD_FM_RDS_BLOCKCOUNT_NARGS 1
#define CMD_FM_RDS_BLOCKCOUNT_NRESP 8
#define CMD_FM_PHASE_DIVERSITY 0x38
#define CMD_FM_PHASE_DIVERSITY_NARGS 1
#define CMD_FM_PHASE_DIVERSITY_NRESP 1
#define CMD_FM_PHASE_DIV_STATUS 0x39
#define CMD_FM_PHASE_DIV_STATUS_NRESP 2
#define CMD_AM_TUNE_FREQ 0x40
#define CMD_AM_TUNE_FREQ_NARGS 3
#define CMD_AM_TUNE_FREQ_NRESP 1
#define CMD_AM_RSQ_STATUS 0x42
#define CMD_AM_RSQ_STATUS_NARGS 1
#define CMD_AM_RSQ_STATUS_NRESP 13
#define CMD_AM_SEEK_START 0x41
#define CMD_AM_SEEK_START_NARGS 1
#define CMD_AM_SEEK_START_NRESP 1
#define CMD_AM_ACF_STATUS 0x45
#define CMD_AM_ACF_STATUS_NRESP 6
#define CMD_AM_ACF_STATUS_NARGS 1
#define CMD_FM_ACF_STATUS 0x35
#define CMD_FM_ACF_STATUS_NRESP 8
#define CMD_FM_ACF_STATUS_NARGS 1
#define CMD_MAX_ARGS_COUNT (10)
enum si476x_acf_status_report_bits {
SI476X_ACF_BLEND_INT = (1 << 4),
SI476X_ACF_HIBLEND_INT = (1 << 3),
SI476X_ACF_HICUT_INT = (1 << 2),
SI476X_ACF_CHBW_INT = (1 << 1),
SI476X_ACF_SOFTMUTE_INT = (1 << 0),
SI476X_ACF_SMUTE = (1 << 0),
SI476X_ACF_SMATTN = 0x1f,
SI476X_ACF_PILOT = (1 << 7),
SI476X_ACF_STBLEND = ~SI476X_ACF_PILOT,
};
enum si476x_agc_status_report_bits {
SI476X_AGC_MXHI = (1 << 5),
SI476X_AGC_MXLO = (1 << 4),
SI476X_AGC_LNAHI = (1 << 3),
SI476X_AGC_LNALO = (1 << 2),
};
enum si476x_errors {
SI476X_ERR_BAD_COMMAND = 0x10,
SI476X_ERR_BAD_ARG1 = 0x11,
SI476X_ERR_BAD_ARG2 = 0x12,
SI476X_ERR_BAD_ARG3 = 0x13,
SI476X_ERR_BAD_ARG4 = 0x14,
SI476X_ERR_BUSY = 0x18,
SI476X_ERR_BAD_INTERNAL_MEMORY = 0x20,
SI476X_ERR_BAD_PATCH = 0x30,
SI476X_ERR_BAD_BOOT_MODE = 0x31,
SI476X_ERR_BAD_PROPERTY = 0x40,
};
static int si476x_core_parse_and_nag_about_error(struct si476x_core *core)
{
int err;
char *cause;
u8 buffer[2];
if (core->revision != SI476X_REVISION_A10) {
err = si476x_core_i2c_xfer(core, SI476X_I2C_RECV,
buffer, sizeof(buffer));
if (err == sizeof(buffer)) {
switch (buffer[1]) {
case SI476X_ERR_BAD_COMMAND:
cause = "Bad command";
err = -EINVAL;
break;
case SI476X_ERR_BAD_ARG1:
cause = "Bad argument #1";
err = -EINVAL;
break;
case SI476X_ERR_BAD_ARG2:
cause = "Bad argument #2";
err = -EINVAL;
break;
case SI476X_ERR_BAD_ARG3:
cause = "Bad argument #3";
err = -EINVAL;
break;
case SI476X_ERR_BAD_ARG4:
cause = "Bad argument #4";
err = -EINVAL;
break;
case SI476X_ERR_BUSY:
cause = "Chip is busy";
err = -EBUSY;
break;
case SI476X_ERR_BAD_INTERNAL_MEMORY:
cause = "Bad internal memory";
err = -EIO;
break;
case SI476X_ERR_BAD_PATCH:
cause = "Bad patch";
err = -EINVAL;
break;
case SI476X_ERR_BAD_BOOT_MODE:
cause = "Bad boot mode";
err = -EINVAL;
break;
case SI476X_ERR_BAD_PROPERTY:
cause = "Bad property";
err = -EINVAL;
break;
default:
cause = "Unknown";
err = -EIO;
}
dev_err(&core->client->dev,
"[Chip error status]: %s\n", cause);
} else {
dev_err(&core->client->dev,
"Failed to fetch error code\n");
err = (err >= 0) ? -EIO : err;
}
} else {
err = -EIO;
}
return err;
}
/**
* si476x_core_send_command() - sends a command to si476x and waits its
* response
* @core: si476x_device structure for the device we are
* communicating with
* @command: command id
* @args: command arguments we are sending
* @argn: actual size of @args
* @resp: buffer to place the expected response from the device
* @respn: actual size of @resp
* @usecs: amount of time to wait before reading the response (in
* usecs)
*
* Function returns 0 on success and negative error code on
* failure
*/
static int si476x_core_send_command(struct si476x_core *core,
const u8 command,
const u8 args[],
const int argn,
u8 resp[],
const int respn,
const int usecs)
{
struct i2c_client *client = core->client;
int err;
u8 data[CMD_MAX_ARGS_COUNT + 1];
if (argn > CMD_MAX_ARGS_COUNT) {
err = -ENOMEM;
goto exit;
}
if (!client->adapter) {
err = -ENODEV;
goto exit;
}
/* First send the command and its arguments */
data[0] = command;
memcpy(&data[1], args, argn);
dev_dbg(&client->dev, "Command:\n %*ph\n", argn + 1, data);
err = si476x_core_i2c_xfer(core, SI476X_I2C_SEND,
(char *) data, argn + 1);
if (err != argn + 1) {
dev_err(&core->client->dev,
"Error while sending command 0x%02x\n",
command);
err = (err >= 0) ? -EIO : err;
goto exit;
}
/* Set CTS to zero only after the command is send to avoid
* possible racing conditions when working in polling mode */
atomic_set(&core->cts, 0);
/* if (unlikely(command == CMD_POWER_DOWN) */
if (!wait_event_timeout(core->command,
atomic_read(&core->cts),
usecs_to_jiffies(usecs) + 1))
dev_warn(&core->client->dev,
"(%s) [CMD 0x%02x] Answer timeout.\n",
__func__, command);
/*
When working in polling mode, for some reason the tuner will
report CTS bit as being set in the first status byte read,
but all the consequtive ones will return zeros until the
tuner is actually completed the POWER_UP command. To
workaround that we wait for second CTS to be reported
*/
if (unlikely(!core->client->irq && command == CMD_POWER_UP)) {
if (!wait_event_timeout(core->command,
atomic_read(&core->cts),
usecs_to_jiffies(usecs) + 1))
dev_warn(&core->client->dev,
"(%s) Power up took too much time.\n",
__func__);
}
/* Then get the response */
err = si476x_core_i2c_xfer(core, SI476X_I2C_RECV, resp, respn);
if (err != respn) {
dev_err(&core->client->dev,
"Error while reading response for command 0x%02x\n",
command);
err = (err >= 0) ? -EIO : err;
goto exit;
}
dev_dbg(&client->dev, "Response:\n %*ph\n", respn, resp);
err = 0;
if (resp[0] & SI476X_ERR) {
dev_err(&core->client->dev,
"[CMD 0x%02x] Chip set error flag\n", command);
err = si476x_core_parse_and_nag_about_error(core);
goto exit;
}
if (!(resp[0] & SI476X_CTS))
err = -EBUSY;
exit:
return err;
}
static int si476x_cmd_clear_stc(struct si476x_core *core)
{
int err;
struct si476x_rsq_status_args args = {
.primary = false,
.rsqack = false,
.attune = false,
.cancel = false,
.stcack = true,
};
switch (core->power_up_parameters.func) {
case SI476X_FUNC_FM_RECEIVER:
err = si476x_core_cmd_fm_rsq_status(core, &args, NULL);
break;
case SI476X_FUNC_AM_RECEIVER:
err = si476x_core_cmd_am_rsq_status(core, &args, NULL);
break;
default:
err = -EINVAL;
}
return err;
}
static int si476x_cmd_tune_seek_freq(struct si476x_core *core,
uint8_t cmd,
const uint8_t args[], size_t argn,
uint8_t *resp, size_t respn)
{
int err;
atomic_set(&core->stc, 0);
err = si476x_core_send_command(core, cmd, args, argn, resp, respn,
SI476X_TIMEOUT_TUNE);
if (!err) {
wait_event_killable(core->tuning,
atomic_read(&core->stc));
si476x_cmd_clear_stc(core);
}
return err;
}
/**
* si476x_core_cmd_func_info() - send 'FUNC_INFO' command to the device
* @core: device to send the command to
* @info: struct si476x_func_info to fill all the information
* returned by the command
*
* The command requests the firmware and patch version for currently
* loaded firmware (dependent on the function of the device FM/AM/WB)
*
* Function returns 0 on success and negative error code on
* failure
*/
int si476x_core_cmd_func_info(struct si476x_core *core,
struct si476x_func_info *info)
{
int err;
u8 resp[CMD_FUNC_INFO_NRESP];
err = si476x_core_send_command(core, CMD_FUNC_INFO,
NULL, 0,
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
info->firmware.major = resp[1];
info->firmware.minor[0] = resp[2];
info->firmware.minor[1] = resp[3];
info->patch_id = ((u16) resp[4] << 8) | resp[5];
info->func = resp[6];
return err;
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_func_info);
/**
* si476x_core_cmd_set_property() - send 'SET_PROPERTY' command to the device
* @core: device to send the command to
* @property: property address
* @value: property value
*
* Function returns 0 on success and negative error code on
* failure
*/
int si476x_core_cmd_set_property(struct si476x_core *core,
u16 property, u16 value)
{
u8 resp[CMD_SET_PROPERTY_NRESP];
const u8 args[CMD_SET_PROPERTY_NARGS] = {
0x00,
msb(property),
lsb(property),
msb(value),
lsb(value),
};
return si476x_core_send_command(core, CMD_SET_PROPERTY,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_set_property);
/**
* si476x_core_cmd_get_property() - send 'GET_PROPERTY' command to the device
* @core: device to send the command to
* @property: property address
*
* Function return the value of property as u16 on success or a
* negative error on failure
*/
int si476x_core_cmd_get_property(struct si476x_core *core, u16 property)
{
int err;
u8 resp[CMD_GET_PROPERTY_NRESP];
const u8 args[CMD_GET_PROPERTY_NARGS] = {
0x00,
msb(property),
lsb(property),
};
err = si476x_core_send_command(core, CMD_GET_PROPERTY,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
if (err < 0)
return err;
else
return get_unaligned_be16(resp + 2);
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_get_property);
/**
* si476x_core_cmd_dig_audio_pin_cfg() - send 'DIG_AUDIO_PIN_CFG' command to
* the device
* @core: device to send the command to
* @dclk: DCLK pin function configuration:
* #SI476X_DCLK_NOOP - do not modify the behaviour
* #SI476X_DCLK_TRISTATE - put the pin in tristate condition,
* enable 1MOhm pulldown
* #SI476X_DCLK_DAUDIO - set the pin to be a part of digital
* audio interface
* @dfs: DFS pin function configuration:
* #SI476X_DFS_NOOP - do not modify the behaviour
* #SI476X_DFS_TRISTATE - put the pin in tristate condition,
* enable 1MOhm pulldown
* SI476X_DFS_DAUDIO - set the pin to be a part of digital
* audio interface
* @dout: - DOUT pin function configuration:
* SI476X_DOUT_NOOP - do not modify the behaviour
* SI476X_DOUT_TRISTATE - put the pin in tristate condition,
* enable 1MOhm pulldown
* SI476X_DOUT_I2S_OUTPUT - set this pin to be digital out on I2S
* port 1
* SI476X_DOUT_I2S_INPUT - set this pin to be digital in on I2S
* port 1
* @xout: - XOUT pin function configuration:
* SI476X_XOUT_NOOP - do not modify the behaviour
* SI476X_XOUT_TRISTATE - put the pin in tristate condition,
* enable 1MOhm pulldown
* SI476X_XOUT_I2S_INPUT - set this pin to be digital in on I2S
* port 1
* SI476X_XOUT_MODE_SELECT - set this pin to be the input that
* selects the mode of the I2S audio
* combiner (analog or HD)
* [SI4761/63/65/67 Only]
*
* Function returns 0 on success and negative error code on failure
*/
int si476x_core_cmd_dig_audio_pin_cfg(struct si476x_core *core,
enum si476x_dclk_config dclk,
enum si476x_dfs_config dfs,
enum si476x_dout_config dout,
enum si476x_xout_config xout)
{
u8 resp[CMD_DIG_AUDIO_PIN_CFG_NRESP];
const u8 args[CMD_DIG_AUDIO_PIN_CFG_NARGS] = {
PIN_CFG_BYTE(dclk),
PIN_CFG_BYTE(dfs),
PIN_CFG_BYTE(dout),
PIN_CFG_BYTE(xout),
};
return si476x_core_send_command(core, CMD_DIG_AUDIO_PIN_CFG,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_dig_audio_pin_cfg);
/**
* si476x_core_cmd_zif_pin_cfg - send 'ZIF_PIN_CFG_COMMAND'
* @core: - device to send the command to
* @iqclk: - IQCL pin function configuration:
* SI476X_IQCLK_NOOP - do not modify the behaviour
* SI476X_IQCLK_TRISTATE - put the pin in tristate condition,
* enable 1MOhm pulldown
* SI476X_IQCLK_IQ - set pin to be a part of I/Q interface
* in master mode
* @iqfs: - IQFS pin function configuration:
* SI476X_IQFS_NOOP - do not modify the behaviour
* SI476X_IQFS_TRISTATE - put the pin in tristate condition,
* enable 1MOhm pulldown
* SI476X_IQFS_IQ - set pin to be a part of I/Q interface
* in master mode
* @iout: - IOUT pin function configuration:
* SI476X_IOUT_NOOP - do not modify the behaviour
* SI476X_IOUT_TRISTATE - put the pin in tristate condition,
* enable 1MOhm pulldown
* SI476X_IOUT_OUTPUT - set pin to be I out
* @qout: - QOUT pin function configuration:
* SI476X_QOUT_NOOP - do not modify the behaviour
* SI476X_QOUT_TRISTATE - put the pin in tristate condition,
* enable 1MOhm pulldown
* SI476X_QOUT_OUTPUT - set pin to be Q out
*
* Function returns 0 on success and negative error code on failure
*/
int si476x_core_cmd_zif_pin_cfg(struct si476x_core *core,
enum si476x_iqclk_config iqclk,
enum si476x_iqfs_config iqfs,
enum si476x_iout_config iout,
enum si476x_qout_config qout)
{
u8 resp[CMD_ZIF_PIN_CFG_NRESP];
const u8 args[CMD_ZIF_PIN_CFG_NARGS] = {
PIN_CFG_BYTE(iqclk),
PIN_CFG_BYTE(iqfs),
PIN_CFG_BYTE(iout),
PIN_CFG_BYTE(qout),
};
return si476x_core_send_command(core, CMD_ZIF_PIN_CFG,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_zif_pin_cfg);
/**
* si476x_core_cmd_ic_link_gpo_ctl_pin_cfg - send
* 'IC_LINK_GPIO_CTL_PIN_CFG' command to the device
* @core: - device to send the command to
* @icin: - ICIN pin function configuration:
* SI476X_ICIN_NOOP - do not modify the behaviour
* SI476X_ICIN_TRISTATE - put the pin in tristate condition,
* enable 1MOhm pulldown
* SI476X_ICIN_GPO1_HIGH - set pin to be an output, drive it high
* SI476X_ICIN_GPO1_LOW - set pin to be an output, drive it low
* SI476X_ICIN_IC_LINK - set the pin to be a part of Inter-Chip link
* @icip: - ICIP pin function configuration:
* SI476X_ICIP_NOOP - do not modify the behaviour
* SI476X_ICIP_TRISTATE - put the pin in tristate condition,
* enable 1MOhm pulldown
* SI476X_ICIP_GPO1_HIGH - set pin to be an output, drive it high
* SI476X_ICIP_GPO1_LOW - set pin to be an output, drive it low
* SI476X_ICIP_IC_LINK - set the pin to be a part of Inter-Chip link
* @icon: - ICON pin function configuration:
* SI476X_ICON_NOOP - do not modify the behaviour
* SI476X_ICON_TRISTATE - put the pin in tristate condition,
* enable 1MOhm pulldown
* SI476X_ICON_I2S - set the pin to be a part of audio
* interface in slave mode (DCLK)
* SI476X_ICON_IC_LINK - set the pin to be a part of Inter-Chip link
* @icop: - ICOP pin function configuration:
* SI476X_ICOP_NOOP - do not modify the behaviour
* SI476X_ICOP_TRISTATE - put the pin in tristate condition,
* enable 1MOhm pulldown
* SI476X_ICOP_I2S - set the pin to be a part of audio
* interface in slave mode (DOUT)
* [Si4761/63/65/67 Only]
* SI476X_ICOP_IC_LINK - set the pin to be a part of Inter-Chip link
*
* Function returns 0 on success and negative error code on failure
*/
int si476x_core_cmd_ic_link_gpo_ctl_pin_cfg(struct si476x_core *core,
enum si476x_icin_config icin,
enum si476x_icip_config icip,
enum si476x_icon_config icon,
enum si476x_icop_config icop)
{
u8 resp[CMD_IC_LINK_GPO_CTL_PIN_CFG_NRESP];
const u8 args[CMD_IC_LINK_GPO_CTL_PIN_CFG_NARGS] = {
PIN_CFG_BYTE(icin),
PIN_CFG_BYTE(icip),
PIN_CFG_BYTE(icon),
PIN_CFG_BYTE(icop),
};
return si476x_core_send_command(core, CMD_IC_LINK_GPO_CTL_PIN_CFG,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_ic_link_gpo_ctl_pin_cfg);
/**
* si476x_core_cmd_ana_audio_pin_cfg - send 'ANA_AUDIO_PIN_CFG' to the
* device
* @core: - device to send the command to
* @lrout: - LROUT pin function configuration:
* SI476X_LROUT_NOOP - do not modify the behaviour
* SI476X_LROUT_TRISTATE - put the pin in tristate condition,
* enable 1MOhm pulldown
* SI476X_LROUT_AUDIO - set pin to be audio output
* SI476X_LROUT_MPX - set pin to be MPX output
*
* Function returns 0 on success and negative error code on failure
*/
int si476x_core_cmd_ana_audio_pin_cfg(struct si476x_core *core,
enum si476x_lrout_config lrout)
{
u8 resp[CMD_ANA_AUDIO_PIN_CFG_NRESP];
const u8 args[CMD_ANA_AUDIO_PIN_CFG_NARGS] = {
PIN_CFG_BYTE(lrout),
};
return si476x_core_send_command(core, CMD_ANA_AUDIO_PIN_CFG,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_ana_audio_pin_cfg);
/**
* si476x_core_cmd_intb_pin_cfg_a10 - send 'INTB_PIN_CFG' command to the device
* @core: - device to send the command to
* @intb: - INTB pin function configuration:
* SI476X_INTB_NOOP - do not modify the behaviour
* SI476X_INTB_TRISTATE - put the pin in tristate condition,
* enable 1MOhm pulldown
* SI476X_INTB_DAUDIO - set pin to be a part of digital
* audio interface in slave mode
* SI476X_INTB_IRQ - set pin to be an interrupt request line
* @a1: - A1 pin function configuration:
* SI476X_A1_NOOP - do not modify the behaviour
* SI476X_A1_TRISTATE - put the pin in tristate condition,
* enable 1MOhm pulldown
* SI476X_A1_IRQ - set pin to be an interrupt request line
*
* Function returns 0 on success and negative error code on failure
*/
static int si476x_core_cmd_intb_pin_cfg_a10(struct si476x_core *core,
enum si476x_intb_config intb,
enum si476x_a1_config a1)
{
u8 resp[CMD_INTB_PIN_CFG_A10_NRESP];
const u8 args[CMD_INTB_PIN_CFG_NARGS] = {
PIN_CFG_BYTE(intb),
PIN_CFG_BYTE(a1),
};
return si476x_core_send_command(core, CMD_INTB_PIN_CFG,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
}
static int si476x_core_cmd_intb_pin_cfg_a20(struct si476x_core *core,
enum si476x_intb_config intb,
enum si476x_a1_config a1)
{
u8 resp[CMD_INTB_PIN_CFG_A20_NRESP];
const u8 args[CMD_INTB_PIN_CFG_NARGS] = {
PIN_CFG_BYTE(intb),
PIN_CFG_BYTE(a1),
};
return si476x_core_send_command(core, CMD_INTB_PIN_CFG,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
}
/**
* si476x_core_cmd_am_rsq_status - send 'AM_RSQ_STATUS' command to the
* device
* @core: - device to send the command to
* @rsqargs: - pointer to a structure containing a group of sub-args
* relevant to sending the RSQ status command
* @report: - all signal quality information returned by the command
* (if NULL then the output of the command is ignored)
*
* Function returns 0 on success and negative error code on failure
*/
int si476x_core_cmd_am_rsq_status(struct si476x_core *core,
struct si476x_rsq_status_args *rsqargs,
struct si476x_rsq_status_report *report)
{
int err;
u8 resp[CMD_AM_RSQ_STATUS_NRESP];
const u8 args[CMD_AM_RSQ_STATUS_NARGS] = {
rsqargs->rsqack << 3 | rsqargs->attune << 2 |
rsqargs->cancel << 1 | rsqargs->stcack,
};
err = si476x_core_send_command(core, CMD_AM_RSQ_STATUS,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
/*
* Besides getting received signal quality information this
* command can be used to just acknowledge different interrupt
* flags in those cases it is useless to copy and parse
* received data so user can pass NULL, and thus avoid
* unnecessary copying.
*/
if (!report)
return err;
report->snrhint = 0x08 & resp[1];
report->snrlint = 0x04 & resp[1];
report->rssihint = 0x02 & resp[1];
report->rssilint = 0x01 & resp[1];
report->bltf = 0x80 & resp[2];
report->snr_ready = 0x20 & resp[2];
report->rssiready = 0x08 & resp[2];
report->afcrl = 0x02 & resp[2];
report->valid = 0x01 & resp[2];
report->readfreq = get_unaligned_be16(resp + 3);
report->freqoff = resp[5];
report->rssi = resp[6];
report->snr = resp[7];
report->lassi = resp[9];
report->hassi = resp[10];
report->mult = resp[11];
report->dev = resp[12];
return err;
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_am_rsq_status);
int si476x_core_cmd_fm_acf_status(struct si476x_core *core,
struct si476x_acf_status_report *report)
{
int err;
u8 resp[CMD_FM_ACF_STATUS_NRESP];
const u8 args[CMD_FM_ACF_STATUS_NARGS] = {
0x0,
};
if (!report)
return -EINVAL;
err = si476x_core_send_command(core, CMD_FM_ACF_STATUS,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
if (err < 0)
return err;
report->blend_int = resp[1] & SI476X_ACF_BLEND_INT;
report->hblend_int = resp[1] & SI476X_ACF_HIBLEND_INT;
report->hicut_int = resp[1] & SI476X_ACF_HICUT_INT;
report->chbw_int = resp[1] & SI476X_ACF_CHBW_INT;
report->softmute_int = resp[1] & SI476X_ACF_SOFTMUTE_INT;
report->smute = resp[2] & SI476X_ACF_SMUTE;
report->smattn = resp[3] & SI476X_ACF_SMATTN;
report->chbw = resp[4];
report->hicut = resp[5];
report->hiblend = resp[6];
report->pilot = resp[7] & SI476X_ACF_PILOT;
report->stblend = resp[7] & SI476X_ACF_STBLEND;
return err;
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_acf_status);
int si476x_core_cmd_am_acf_status(struct si476x_core *core,
struct si476x_acf_status_report *report)
{
int err;
u8 resp[CMD_AM_ACF_STATUS_NRESP];
const u8 args[CMD_AM_ACF_STATUS_NARGS] = {
0x0,
};
if (!report)
return -EINVAL;
err = si476x_core_send_command(core, CMD_AM_ACF_STATUS,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
if (err < 0)
return err;
report->blend_int = resp[1] & SI476X_ACF_BLEND_INT;
report->hblend_int = resp[1] & SI476X_ACF_HIBLEND_INT;
report->hicut_int = resp[1] & SI476X_ACF_HICUT_INT;
report->chbw_int = resp[1] & SI476X_ACF_CHBW_INT;
report->softmute_int = resp[1] & SI476X_ACF_SOFTMUTE_INT;
report->smute = resp[2] & SI476X_ACF_SMUTE;
report->smattn = resp[3] & SI476X_ACF_SMATTN;
report->chbw = resp[4];
report->hicut = resp[5];
return err;
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_am_acf_status);
/**
* si476x_core_cmd_fm_seek_start - send 'FM_SEEK_START' command to the
* device
* @core: - device to send the command to
* @seekup: - if set the direction of the search is 'up'
* @wrap: - if set seek wraps when hitting band limit
*
* This function begins search for a valid station. The station is
* considered valid when 'FM_VALID_SNR_THRESHOLD' and
* 'FM_VALID_RSSI_THRESHOLD' and 'FM_VALID_MAX_TUNE_ERROR' criteria
* are met.
} *
* Function returns 0 on success and negative error code on failure
*/
int si476x_core_cmd_fm_seek_start(struct si476x_core *core,
bool seekup, bool wrap)
{
u8 resp[CMD_FM_SEEK_START_NRESP];
const u8 args[CMD_FM_SEEK_START_NARGS] = {
seekup << 3 | wrap << 2,
};
return si476x_cmd_tune_seek_freq(core, CMD_FM_SEEK_START,
args, sizeof(args),
resp, sizeof(resp));
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_seek_start);
/**
* si476x_core_cmd_fm_rds_status - send 'FM_RDS_STATUS' command to the
* device
* @core: - device to send the command to
* @status_only: - if set the data is not removed from RDSFIFO,
* RDSFIFOUSED is not decremented and data in all the
* rest RDS data contains the last valid info received
* @mtfifo: if set the command clears RDS receive FIFO
* @intack: if set the command clards the RDSINT bit.
* @report: - all signal quality information returned by the command
* (if NULL then the output of the command is ignored)
*
* Function returns 0 on success and negative error code on failure
*/
int si476x_core_cmd_fm_rds_status(struct si476x_core *core,
bool status_only,
bool mtfifo,
bool intack,
struct si476x_rds_status_report *report)
{
int err;
u8 resp[CMD_FM_RDS_STATUS_NRESP];
const u8 args[CMD_FM_RDS_STATUS_NARGS] = {
status_only << 2 | mtfifo << 1 | intack,
};
err = si476x_core_send_command(core, CMD_FM_RDS_STATUS,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
/*
* Besides getting RDS status information this command can be
* used to just acknowledge different interrupt flags in those
* cases it is useless to copy and parse received data so user
* can pass NULL, and thus avoid unnecessary copying.
*/
if (err < 0 || report == NULL)
return err;
report->rdstpptyint = 0x10 & resp[1];
report->rdspiint = 0x08 & resp[1];
report->rdssyncint = 0x02 & resp[1];
report->rdsfifoint = 0x01 & resp[1];
report->tpptyvalid = 0x10 & resp[2];
report->pivalid = 0x08 & resp[2];
report->rdssync = 0x02 & resp[2];
report->rdsfifolost = 0x01 & resp[2];
report->tp = 0x20 & resp[3];
report->pty = 0x1f & resp[3];
report->pi = get_unaligned_be16(resp + 4);
report->rdsfifoused = resp[6];
report->ble[V4L2_RDS_BLOCK_A] = 0xc0 & resp[7];
report->ble[V4L2_RDS_BLOCK_B] = 0x30 & resp[7];
report->ble[V4L2_RDS_BLOCK_C] = 0x0c & resp[7];
report->ble[V4L2_RDS_BLOCK_D] = 0x03 & resp[7];
report->rds[V4L2_RDS_BLOCK_A].block = V4L2_RDS_BLOCK_A;
report->rds[V4L2_RDS_BLOCK_A].msb = resp[8];
report->rds[V4L2_RDS_BLOCK_A].lsb = resp[9];
report->rds[V4L2_RDS_BLOCK_B].block = V4L2_RDS_BLOCK_B;
report->rds[V4L2_RDS_BLOCK_B].msb = resp[10];
report->rds[V4L2_RDS_BLOCK_B].lsb = resp[11];
report->rds[V4L2_RDS_BLOCK_C].block = V4L2_RDS_BLOCK_C;
report->rds[V4L2_RDS_BLOCK_C].msb = resp[12];
report->rds[V4L2_RDS_BLOCK_C].lsb = resp[13];
report->rds[V4L2_RDS_BLOCK_D].block = V4L2_RDS_BLOCK_D;
report->rds[V4L2_RDS_BLOCK_D].msb = resp[14];
report->rds[V4L2_RDS_BLOCK_D].lsb = resp[15];
return err;
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_rds_status);
int si476x_core_cmd_fm_rds_blockcount(struct si476x_core *core,
bool clear,
struct si476x_rds_blockcount_report *report)
{
int err;
u8 resp[CMD_FM_RDS_BLOCKCOUNT_NRESP];
const u8 args[CMD_FM_RDS_BLOCKCOUNT_NARGS] = {
clear,
};
if (!report)
return -EINVAL;
err = si476x_core_send_command(core, CMD_FM_RDS_BLOCKCOUNT,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
if (!err) {
report->expected = get_unaligned_be16(resp + 2);
report->received = get_unaligned_be16(resp + 4);
report->uncorrectable = get_unaligned_be16(resp + 6);
}
return err;
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_rds_blockcount);
int si476x_core_cmd_fm_phase_diversity(struct si476x_core *core,
enum si476x_phase_diversity_mode mode)
{
u8 resp[CMD_FM_PHASE_DIVERSITY_NRESP];
const u8 args[CMD_FM_PHASE_DIVERSITY_NARGS] = {
mode & 0x07,
};
return si476x_core_send_command(core, CMD_FM_PHASE_DIVERSITY,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_phase_diversity);
/**
* si476x_core_cmd_fm_phase_div_status() - get the phase diversity
* status
*
* @core: si476x device
*
* NOTE caller must hold core lock
*
* Function returns the value of the status bit in case of success and
* negative error code in case of failure.
*/
int si476x_core_cmd_fm_phase_div_status(struct si476x_core *core)
{
int err;
u8 resp[CMD_FM_PHASE_DIV_STATUS_NRESP];
err = si476x_core_send_command(core, CMD_FM_PHASE_DIV_STATUS,
NULL, 0,
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
return (err < 0) ? err : resp[1];
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_phase_div_status);
/**
* si476x_core_cmd_am_seek_start - send 'FM_SEEK_START' command to the
* device
* @core: - device to send the command to
* @seekup: - if set the direction of the search is 'up'
* @wrap: - if set seek wraps when hitting band limit
*
* This function begins search for a valid station. The station is
* considered valid when 'FM_VALID_SNR_THRESHOLD' and
* 'FM_VALID_RSSI_THRESHOLD' and 'FM_VALID_MAX_TUNE_ERROR' criteria
* are met.
*
* Function returns 0 on success and negative error code on failure
*/
int si476x_core_cmd_am_seek_start(struct si476x_core *core,
bool seekup, bool wrap)
{
u8 resp[CMD_AM_SEEK_START_NRESP];
const u8 args[CMD_AM_SEEK_START_NARGS] = {
seekup << 3 | wrap << 2,
};
return si476x_cmd_tune_seek_freq(core, CMD_AM_SEEK_START,
args, sizeof(args),
resp, sizeof(resp));
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_am_seek_start);
static int si476x_core_cmd_power_up_a10(struct si476x_core *core,
struct si476x_power_up_args *puargs)
{
u8 resp[CMD_POWER_UP_A10_NRESP];
const bool intsel = (core->pinmux.a1 == SI476X_A1_IRQ);
const bool ctsen = (core->client->irq != 0);
const u8 args[CMD_POWER_UP_A10_NARGS] = {
0xF7, /* Reserved, always 0xF7 */
0x3F & puargs->xcload, /* First two bits are reserved to be
* zeros */
ctsen << 7 | intsel << 6 | 0x07, /* Last five bits
* are reserved to
* be written as 0x7 */
puargs->func << 4 | puargs->freq,
0x11, /* Reserved, always 0x11 */
};
return si476x_core_send_command(core, CMD_POWER_UP,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_TIMEOUT_POWER_UP);
}
static int si476x_core_cmd_power_up_a20(struct si476x_core *core,
struct si476x_power_up_args *puargs)
{
u8 resp[CMD_POWER_UP_A20_NRESP];
const bool intsel = (core->pinmux.a1 == SI476X_A1_IRQ);
const bool ctsen = (core->client->irq != 0);
const u8 args[CMD_POWER_UP_A20_NARGS] = {
puargs->ibias6x << 7 | puargs->xstart,
0x3F & puargs->xcload, /* First two bits are reserved to be
* zeros */
ctsen << 7 | intsel << 6 | puargs->fastboot << 5 |
puargs->xbiashc << 3 | puargs->xbias,
puargs->func << 4 | puargs->freq,
0x10 | puargs->xmode,
};
return si476x_core_send_command(core, CMD_POWER_UP,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_TIMEOUT_POWER_UP);
}
static int si476x_core_cmd_power_down_a10(struct si476x_core *core,
struct si476x_power_down_args *pdargs)
{
u8 resp[CMD_POWER_DOWN_A10_NRESP];
return si476x_core_send_command(core, CMD_POWER_DOWN,
NULL, 0,
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
}
static int si476x_core_cmd_power_down_a20(struct si476x_core *core,
struct si476x_power_down_args *pdargs)
{
u8 resp[CMD_POWER_DOWN_A20_NRESP];
const u8 args[CMD_POWER_DOWN_A20_NARGS] = {
pdargs->xosc,
};
return si476x_core_send_command(core, CMD_POWER_DOWN,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
}
static int si476x_core_cmd_am_tune_freq_a10(struct si476x_core *core,
struct si476x_tune_freq_args *tuneargs)
{
const int am_freq = tuneargs->freq;
u8 resp[CMD_AM_TUNE_FREQ_NRESP];
const u8 args[CMD_AM_TUNE_FREQ_NARGS] = {
(tuneargs->hd << 6),
msb(am_freq),
lsb(am_freq),
};
return si476x_cmd_tune_seek_freq(core, CMD_AM_TUNE_FREQ, args,
sizeof(args),
resp, sizeof(resp));
}
static int si476x_core_cmd_am_tune_freq_a20(struct si476x_core *core,
struct si476x_tune_freq_args *tuneargs)
{
const int am_freq = tuneargs->freq;
u8 resp[CMD_AM_TUNE_FREQ_NRESP];
const u8 args[CMD_AM_TUNE_FREQ_NARGS] = {
(tuneargs->zifsr << 6) | (tuneargs->injside & 0x03),
msb(am_freq),
lsb(am_freq),
};
return si476x_cmd_tune_seek_freq(core, CMD_AM_TUNE_FREQ,
args, sizeof(args),
resp, sizeof(resp));
}
static int si476x_core_cmd_fm_rsq_status_a10(struct si476x_core *core,
struct si476x_rsq_status_args *rsqargs,
struct si476x_rsq_status_report *report)
{
int err;
u8 resp[CMD_FM_RSQ_STATUS_A10_NRESP];
const u8 args[CMD_FM_RSQ_STATUS_A10_NARGS] = {
rsqargs->rsqack << 3 | rsqargs->attune << 2 |
rsqargs->cancel << 1 | rsqargs->stcack,
};
err = si476x_core_send_command(core, CMD_FM_RSQ_STATUS,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
/*
* Besides getting received signal quality information this
* command can be used to just acknowledge different interrupt
* flags in those cases it is useless to copy and parse
* received data so user can pass NULL, and thus avoid
* unnecessary copying.
*/
if (err < 0 || report == NULL)
return err;
report->multhint = 0x80 & resp[1];
report->multlint = 0x40 & resp[1];
report->snrhint = 0x08 & resp[1];
report->snrlint = 0x04 & resp[1];
report->rssihint = 0x02 & resp[1];
report->rssilint = 0x01 & resp[1];
report->bltf = 0x80 & resp[2];
report->snr_ready = 0x20 & resp[2];
report->rssiready = 0x08 & resp[2];
report->afcrl = 0x02 & resp[2];
report->valid = 0x01 & resp[2];
report->readfreq = get_unaligned_be16(resp + 3);
report->freqoff = resp[5];
report->rssi = resp[6];
report->snr = resp[7];
report->lassi = resp[9];
report->hassi = resp[10];
report->mult = resp[11];
report->dev = resp[12];
report->readantcap = get_unaligned_be16(resp + 13);
report->assi = resp[15];
report->usn = resp[16];
return err;
}
static int si476x_core_cmd_fm_rsq_status_a20(struct si476x_core *core,
struct si476x_rsq_status_args *rsqargs,
struct si476x_rsq_status_report *report)
{
int err;
u8 resp[CMD_FM_RSQ_STATUS_A10_NRESP];
const u8 args[CMD_FM_RSQ_STATUS_A30_NARGS] = {
rsqargs->primary << 4 | rsqargs->rsqack << 3 |
rsqargs->attune << 2 | rsqargs->cancel << 1 |
rsqargs->stcack,
};
err = si476x_core_send_command(core, CMD_FM_RSQ_STATUS,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
/*
* Besides getting received signal quality information this
* command can be used to just acknowledge different interrupt
* flags in those cases it is useless to copy and parse
* received data so user can pass NULL, and thus avoid
* unnecessary copying.
*/
if (err < 0 || report == NULL)
return err;
report->multhint = 0x80 & resp[1];
report->multlint = 0x40 & resp[1];
report->snrhint = 0x08 & resp[1];
report->snrlint = 0x04 & resp[1];
report->rssihint = 0x02 & resp[1];
report->rssilint = 0x01 & resp[1];
report->bltf = 0x80 & resp[2];
report->snr_ready = 0x20 & resp[2];
report->rssiready = 0x08 & resp[2];
report->afcrl = 0x02 & resp[2];
report->valid = 0x01 & resp[2];
report->readfreq = get_unaligned_be16(resp + 3);
report->freqoff = resp[5];
report->rssi = resp[6];
report->snr = resp[7];
report->lassi = resp[9];
report->hassi = resp[10];
report->mult = resp[11];
report->dev = resp[12];
report->readantcap = get_unaligned_be16(resp + 13);
report->assi = resp[15];
report->usn = resp[16];
return err;
}
static int si476x_core_cmd_fm_rsq_status_a30(struct si476x_core *core,
struct si476x_rsq_status_args *rsqargs,
struct si476x_rsq_status_report *report)
{
int err;
u8 resp[CMD_FM_RSQ_STATUS_A30_NRESP];
const u8 args[CMD_FM_RSQ_STATUS_A30_NARGS] = {
rsqargs->primary << 4 | rsqargs->rsqack << 3 |
rsqargs->attune << 2 | rsqargs->cancel << 1 |
rsqargs->stcack,
};
err = si476x_core_send_command(core, CMD_FM_RSQ_STATUS,
args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
/*
* Besides getting received signal quality information this
* command can be used to just acknowledge different interrupt
* flags in those cases it is useless to copy and parse
* received data so user can pass NULL, and thus avoid
* unnecessary copying.
*/
if (err < 0 || report == NULL)
return err;
report->multhint = 0x80 & resp[1];
report->multlint = 0x40 & resp[1];
report->snrhint = 0x08 & resp[1];
report->snrlint = 0x04 & resp[1];
report->rssihint = 0x02 & resp[1];
report->rssilint = 0x01 & resp[1];
report->bltf = 0x80 & resp[2];
report->snr_ready = 0x20 & resp[2];
report->rssiready = 0x08 & resp[2];
report->injside = 0x04 & resp[2];
report->afcrl = 0x02 & resp[2];
report->valid = 0x01 & resp[2];
report->readfreq = get_unaligned_be16(resp + 3);
report->freqoff = resp[5];
report->rssi = resp[6];
report->snr = resp[7];
report->issi = resp[8];
report->lassi = resp[9];
report->hassi = resp[10];
report->mult = resp[11];
report->dev = resp[12];
report->readantcap = get_unaligned_be16(resp + 13);
report->assi = resp[15];
report->usn = resp[16];
report->pilotdev = resp[17];
report->rdsdev = resp[18];
report->assidev = resp[19];
report->strongdev = resp[20];
report->rdspi = get_unaligned_be16(resp + 21);
return err;
}
static int si476x_core_cmd_fm_tune_freq_a10(struct si476x_core *core,
struct si476x_tune_freq_args *tuneargs)
{
u8 resp[CMD_FM_TUNE_FREQ_NRESP];
const u8 args[CMD_FM_TUNE_FREQ_A10_NARGS] = {
(tuneargs->hd << 6) | (tuneargs->tunemode << 4)
| (tuneargs->smoothmetrics << 2),
msb(tuneargs->freq),
lsb(tuneargs->freq),
msb(tuneargs->antcap),
lsb(tuneargs->antcap)
};
return si476x_cmd_tune_seek_freq(core, CMD_FM_TUNE_FREQ,
args, sizeof(args),
resp, sizeof(resp));
}
static int si476x_core_cmd_fm_tune_freq_a20(struct si476x_core *core,
struct si476x_tune_freq_args *tuneargs)
{
u8 resp[CMD_FM_TUNE_FREQ_NRESP];
const u8 args[CMD_FM_TUNE_FREQ_A20_NARGS] = {
(tuneargs->hd << 6) | (tuneargs->tunemode << 4)
| (tuneargs->smoothmetrics << 2) | (tuneargs->injside),
msb(tuneargs->freq),
lsb(tuneargs->freq),
};
return si476x_cmd_tune_seek_freq(core, CMD_FM_TUNE_FREQ,
args, sizeof(args),
resp, sizeof(resp));
}
static int si476x_core_cmd_agc_status_a20(struct si476x_core *core,
struct si476x_agc_status_report *report)
{
int err;
u8 resp[CMD_AGC_STATUS_NRESP_A20];
if (!report)
return -EINVAL;
err = si476x_core_send_command(core, CMD_AGC_STATUS,
NULL, 0,
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
if (err < 0)
return err;
report->mxhi = resp[1] & SI476X_AGC_MXHI;
report->mxlo = resp[1] & SI476X_AGC_MXLO;
report->lnahi = resp[1] & SI476X_AGC_LNAHI;
report->lnalo = resp[1] & SI476X_AGC_LNALO;
report->fmagc1 = resp[2];
report->fmagc2 = resp[3];
report->pgagain = resp[4];
report->fmwblang = resp[5];
return err;
}
static int si476x_core_cmd_agc_status_a10(struct si476x_core *core,
struct si476x_agc_status_report *report)
{
int err;
u8 resp[CMD_AGC_STATUS_NRESP_A10];
if (!report)
return -EINVAL;
err = si476x_core_send_command(core, CMD_AGC_STATUS,
NULL, 0,
resp, ARRAY_SIZE(resp),
SI476X_DEFAULT_TIMEOUT);
if (err < 0)
return err;
report->mxhi = resp[1] & SI476X_AGC_MXHI;
report->mxlo = resp[1] & SI476X_AGC_MXLO;
report->lnahi = resp[1] & SI476X_AGC_LNAHI;
report->lnalo = resp[1] & SI476X_AGC_LNALO;
return err;
}
typedef int (*tune_freq_func_t) (struct si476x_core *core,
struct si476x_tune_freq_args *tuneargs);
static struct {
int (*power_up)(struct si476x_core *,
struct si476x_power_up_args *);
int (*power_down)(struct si476x_core *,
struct si476x_power_down_args *);
tune_freq_func_t fm_tune_freq;
tune_freq_func_t am_tune_freq;
int (*fm_rsq_status)(struct si476x_core *,
struct si476x_rsq_status_args *,
struct si476x_rsq_status_report *);
int (*agc_status)(struct si476x_core *,
struct si476x_agc_status_report *);
int (*intb_pin_cfg)(struct si476x_core *core,
enum si476x_intb_config intb,
enum si476x_a1_config a1);
} si476x_cmds_vtable[] = {
[SI476X_REVISION_A10] = {
.power_up = si476x_core_cmd_power_up_a10,
.power_down = si476x_core_cmd_power_down_a10,
.fm_tune_freq = si476x_core_cmd_fm_tune_freq_a10,
.am_tune_freq = si476x_core_cmd_am_tune_freq_a10,
.fm_rsq_status = si476x_core_cmd_fm_rsq_status_a10,
.agc_status = si476x_core_cmd_agc_status_a10,
.intb_pin_cfg = si476x_core_cmd_intb_pin_cfg_a10,
},
[SI476X_REVISION_A20] = {
.power_up = si476x_core_cmd_power_up_a20,
.power_down = si476x_core_cmd_power_down_a20,
.fm_tune_freq = si476x_core_cmd_fm_tune_freq_a20,
.am_tune_freq = si476x_core_cmd_am_tune_freq_a20,
.fm_rsq_status = si476x_core_cmd_fm_rsq_status_a20,
.agc_status = si476x_core_cmd_agc_status_a20,
.intb_pin_cfg = si476x_core_cmd_intb_pin_cfg_a20,
},
[SI476X_REVISION_A30] = {
.power_up = si476x_core_cmd_power_up_a20,
.power_down = si476x_core_cmd_power_down_a20,
.fm_tune_freq = si476x_core_cmd_fm_tune_freq_a20,
.am_tune_freq = si476x_core_cmd_am_tune_freq_a20,
.fm_rsq_status = si476x_core_cmd_fm_rsq_status_a30,
.agc_status = si476x_core_cmd_agc_status_a20,
.intb_pin_cfg = si476x_core_cmd_intb_pin_cfg_a20,
},
};
int si476x_core_cmd_power_up(struct si476x_core *core,
struct si476x_power_up_args *args)
{
BUG_ON(core->revision > SI476X_REVISION_A30 ||
core->revision == -1);
return si476x_cmds_vtable[core->revision].power_up(core, args);
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_power_up);
int si476x_core_cmd_power_down(struct si476x_core *core,
struct si476x_power_down_args *args)
{
BUG_ON(core->revision > SI476X_REVISION_A30 ||
core->revision == -1);
return si476x_cmds_vtable[core->revision].power_down(core, args);
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_power_down);
int si476x_core_cmd_fm_tune_freq(struct si476x_core *core,
struct si476x_tune_freq_args *args)
{
BUG_ON(core->revision > SI476X_REVISION_A30 ||
core->revision == -1);
return si476x_cmds_vtable[core->revision].fm_tune_freq(core, args);
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_tune_freq);
int si476x_core_cmd_am_tune_freq(struct si476x_core *core,
struct si476x_tune_freq_args *args)
{
BUG_ON(core->revision > SI476X_REVISION_A30 ||
core->revision == -1);
return si476x_cmds_vtable[core->revision].am_tune_freq(core, args);
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_am_tune_freq);
int si476x_core_cmd_fm_rsq_status(struct si476x_core *core,
struct si476x_rsq_status_args *args,
struct si476x_rsq_status_report *report)
{
BUG_ON(core->revision > SI476X_REVISION_A30 ||
core->revision == -1);
return si476x_cmds_vtable[core->revision].fm_rsq_status(core, args,
report);
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_fm_rsq_status);
int si476x_core_cmd_agc_status(struct si476x_core *core,
struct si476x_agc_status_report *report)
{
BUG_ON(core->revision > SI476X_REVISION_A30 ||
core->revision == -1);
return si476x_cmds_vtable[core->revision].agc_status(core, report);
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_agc_status);
int si476x_core_cmd_intb_pin_cfg(struct si476x_core *core,
enum si476x_intb_config intb,
enum si476x_a1_config a1)
{
BUG_ON(core->revision > SI476X_REVISION_A30 ||
core->revision == -1);
return si476x_cmds_vtable[core->revision].intb_pin_cfg(core, intb, a1);
}
EXPORT_SYMBOL_GPL(si476x_core_cmd_intb_pin_cfg);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Andrey Smirnov <[email protected]>");
MODULE_DESCRIPTION("API for command exchange for si476x");
| linux-master | drivers/mfd/si476x-cmd.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Atmel SMC (Static Memory Controller) helper functions.
*
* Copyright (C) 2017 Atmel
* Copyright (C) 2017 Free Electrons
*
* Author: Boris Brezillon <[email protected]>
*/
#include <linux/mfd/syscon/atmel-smc.h>
#include <linux/string.h>
/**
* atmel_smc_cs_conf_init - initialize a SMC CS conf
* @conf: the SMC CS conf to initialize
*
* Set all fields to 0 so that one can start defining a new config.
*/
void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf)
{
memset(conf, 0, sizeof(*conf));
}
EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_init);
/**
* atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
* format expected by the SMC engine
* @ncycles: number of MCK clk cycles
* @msbpos: position of the MSB part of the timing field
* @msbwidth: width of the MSB part of the timing field
* @msbfactor: factor applied to the MSB
* @encodedval: param used to store the encoding result
*
* This function encodes the @ncycles value as described in the datasheet
* (section "SMC Setup/Pulse/Cycle/Timings Register"). This is a generic
* helper which called with different parameter depending on the encoding
* scheme.
*
* If the @ncycles value is too big to be encoded, -ERANGE is returned and
* the encodedval is contains the maximum val. Otherwise, 0 is returned.
*/
static int atmel_smc_cs_encode_ncycles(unsigned int ncycles,
unsigned int msbpos,
unsigned int msbwidth,
unsigned int msbfactor,
unsigned int *encodedval)
{
unsigned int lsbmask = GENMASK(msbpos - 1, 0);
unsigned int msbmask = GENMASK(msbwidth - 1, 0);
unsigned int msb, lsb;
int ret = 0;
msb = ncycles / msbfactor;
lsb = ncycles % msbfactor;
if (lsb > lsbmask) {
lsb = 0;
msb++;
}
/*
* Let's just put the maximum we can if the requested setting does
* not fit in the register field.
* We still return -ERANGE in case the caller cares.
*/
if (msb > msbmask) {
msb = msbmask;
lsb = lsbmask;
ret = -ERANGE;
}
*encodedval = (msb << msbpos) | lsb;
return ret;
}
/**
* atmel_smc_cs_conf_set_timing - set the SMC CS conf Txx parameter to a
* specific value
* @conf: SMC CS conf descriptor
* @shift: the position of the Txx field in the TIMINGS register
* @ncycles: value (expressed in MCK clk cycles) to assign to this Txx
* parameter
*
* This function encodes the @ncycles value as described in the datasheet
* (section "SMC Timings Register"), and then stores the result in the
* @conf->timings field at @shift position.
*
* Returns -EINVAL if shift is invalid, -ERANGE if ncycles does not fit in
* the field, and 0 otherwise.
*/
int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf,
unsigned int shift, unsigned int ncycles)
{
unsigned int val;
int ret;
if (shift != ATMEL_HSMC_TIMINGS_TCLR_SHIFT &&
shift != ATMEL_HSMC_TIMINGS_TADL_SHIFT &&
shift != ATMEL_HSMC_TIMINGS_TAR_SHIFT &&
shift != ATMEL_HSMC_TIMINGS_TRR_SHIFT &&
shift != ATMEL_HSMC_TIMINGS_TWB_SHIFT)
return -EINVAL;
/*
* The formula described in atmel datasheets (section "HSMC Timings
* Register"):
*
* ncycles = (Txx[3] * 64) + Txx[2:0]
*/
ret = atmel_smc_cs_encode_ncycles(ncycles, 3, 1, 64, &val);
conf->timings &= ~GENMASK(shift + 3, shift);
conf->timings |= val << shift;
return ret;
}
EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_timing);
/**
* atmel_smc_cs_conf_set_setup - set the SMC CS conf xx_SETUP parameter to a
* specific value
* @conf: SMC CS conf descriptor
* @shift: the position of the xx_SETUP field in the SETUP register
* @ncycles: value (expressed in MCK clk cycles) to assign to this xx_SETUP
* parameter
*
* This function encodes the @ncycles value as described in the datasheet
* (section "SMC Setup Register"), and then stores the result in the
* @conf->setup field at @shift position.
*
* Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
* the field, and 0 otherwise.
*/
int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf,
unsigned int shift, unsigned int ncycles)
{
unsigned int val;
int ret;
if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
return -EINVAL;
/*
* The formula described in atmel datasheets (section "SMC Setup
* Register"):
*
* ncycles = (128 * xx_SETUP[5]) + xx_SETUP[4:0]
*/
ret = atmel_smc_cs_encode_ncycles(ncycles, 5, 1, 128, &val);
conf->setup &= ~GENMASK(shift + 7, shift);
conf->setup |= val << shift;
return ret;
}
EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_setup);
/**
* atmel_smc_cs_conf_set_pulse - set the SMC CS conf xx_PULSE parameter to a
* specific value
* @conf: SMC CS conf descriptor
* @shift: the position of the xx_PULSE field in the PULSE register
* @ncycles: value (expressed in MCK clk cycles) to assign to this xx_PULSE
* parameter
*
* This function encodes the @ncycles value as described in the datasheet
* (section "SMC Pulse Register"), and then stores the result in the
* @conf->setup field at @shift position.
*
* Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
* the field, and 0 otherwise.
*/
int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf,
unsigned int shift, unsigned int ncycles)
{
unsigned int val;
int ret;
if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
return -EINVAL;
/*
* The formula described in atmel datasheets (section "SMC Pulse
* Register"):
*
* ncycles = (256 * xx_PULSE[6]) + xx_PULSE[5:0]
*/
ret = atmel_smc_cs_encode_ncycles(ncycles, 6, 1, 256, &val);
conf->pulse &= ~GENMASK(shift + 7, shift);
conf->pulse |= val << shift;
return ret;
}
EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_pulse);
/**
* atmel_smc_cs_conf_set_cycle - set the SMC CS conf xx_CYCLE parameter to a
* specific value
* @conf: SMC CS conf descriptor
* @shift: the position of the xx_CYCLE field in the CYCLE register
* @ncycles: value (expressed in MCK clk cycles) to assign to this xx_CYCLE
* parameter
*
* This function encodes the @ncycles value as described in the datasheet
* (section "SMC Cycle Register"), and then stores the result in the
* @conf->setup field at @shift position.
*
* Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
* the field, and 0 otherwise.
*/
int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf,
unsigned int shift, unsigned int ncycles)
{
unsigned int val;
int ret;
if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NRD_SHIFT)
return -EINVAL;
/*
* The formula described in atmel datasheets (section "SMC Cycle
* Register"):
*
* ncycles = (xx_CYCLE[8:7] * 256) + xx_CYCLE[6:0]
*/
ret = atmel_smc_cs_encode_ncycles(ncycles, 7, 2, 256, &val);
conf->cycle &= ~GENMASK(shift + 15, shift);
conf->cycle |= val << shift;
return ret;
}
EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_cycle);
/**
* atmel_smc_cs_conf_apply - apply an SMC CS conf
* @regmap: the SMC regmap
* @cs: the CS id
* @conf: the SMC CS conf to apply
*
* Applies an SMC CS configuration.
* Only valid on at91sam9 SoCs.
*/
void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs,
const struct atmel_smc_cs_conf *conf)
{
regmap_write(regmap, ATMEL_SMC_SETUP(cs), conf->setup);
regmap_write(regmap, ATMEL_SMC_PULSE(cs), conf->pulse);
regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle);
regmap_write(regmap, ATMEL_SMC_MODE(cs), conf->mode);
}
EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_apply);
/**
* atmel_hsmc_cs_conf_apply - apply an SMC CS conf
* @regmap: the HSMC regmap
* @cs: the CS id
* @layout: the layout of registers
* @conf: the SMC CS conf to apply
*
* Applies an SMC CS configuration.
* Only valid on post-sama5 SoCs.
*/
void atmel_hsmc_cs_conf_apply(struct regmap *regmap,
const struct atmel_hsmc_reg_layout *layout,
int cs, const struct atmel_smc_cs_conf *conf)
{
regmap_write(regmap, ATMEL_HSMC_SETUP(layout, cs), conf->setup);
regmap_write(regmap, ATMEL_HSMC_PULSE(layout, cs), conf->pulse);
regmap_write(regmap, ATMEL_HSMC_CYCLE(layout, cs), conf->cycle);
regmap_write(regmap, ATMEL_HSMC_TIMINGS(layout, cs), conf->timings);
regmap_write(regmap, ATMEL_HSMC_MODE(layout, cs), conf->mode);
}
EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_apply);
/**
* atmel_smc_cs_conf_get - retrieve the current SMC CS conf
* @regmap: the SMC regmap
* @cs: the CS id
* @conf: the SMC CS conf object to store the current conf
*
* Retrieve the SMC CS configuration.
* Only valid on at91sam9 SoCs.
*/
void atmel_smc_cs_conf_get(struct regmap *regmap, int cs,
struct atmel_smc_cs_conf *conf)
{
regmap_read(regmap, ATMEL_SMC_SETUP(cs), &conf->setup);
regmap_read(regmap, ATMEL_SMC_PULSE(cs), &conf->pulse);
regmap_read(regmap, ATMEL_SMC_CYCLE(cs), &conf->cycle);
regmap_read(regmap, ATMEL_SMC_MODE(cs), &conf->mode);
}
EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_get);
/**
* atmel_hsmc_cs_conf_get - retrieve the current SMC CS conf
* @regmap: the HSMC regmap
* @cs: the CS id
* @layout: the layout of registers
* @conf: the SMC CS conf object to store the current conf
*
* Retrieve the SMC CS configuration.
* Only valid on post-sama5 SoCs.
*/
void atmel_hsmc_cs_conf_get(struct regmap *regmap,
const struct atmel_hsmc_reg_layout *layout,
int cs, struct atmel_smc_cs_conf *conf)
{
regmap_read(regmap, ATMEL_HSMC_SETUP(layout, cs), &conf->setup);
regmap_read(regmap, ATMEL_HSMC_PULSE(layout, cs), &conf->pulse);
regmap_read(regmap, ATMEL_HSMC_CYCLE(layout, cs), &conf->cycle);
regmap_read(regmap, ATMEL_HSMC_TIMINGS(layout, cs), &conf->timings);
regmap_read(regmap, ATMEL_HSMC_MODE(layout, cs), &conf->mode);
}
EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_get);
static const struct atmel_hsmc_reg_layout sama5d3_reg_layout = {
.timing_regs_offset = 0x600,
};
static const struct atmel_hsmc_reg_layout sama5d2_reg_layout = {
.timing_regs_offset = 0x700,
};
static const struct of_device_id atmel_smc_ids[] __maybe_unused = {
{ .compatible = "atmel,at91sam9260-smc", .data = NULL },
{ .compatible = "atmel,sama5d3-smc", .data = &sama5d3_reg_layout },
{ .compatible = "atmel,sama5d2-smc", .data = &sama5d2_reg_layout },
{ /* sentinel */ },
};
/**
* atmel_hsmc_get_reg_layout - retrieve the layout of HSMC registers
* @np: the HSMC regmap
*
* Retrieve the layout of HSMC registers.
*
* Returns NULL in case of SMC, a struct atmel_hsmc_reg_layout pointer
* in HSMC case, otherwise ERR_PTR(-EINVAL).
*/
const struct atmel_hsmc_reg_layout *
atmel_hsmc_get_reg_layout(struct device_node *np)
{
const struct of_device_id *match;
match = of_match_node(atmel_smc_ids, np);
return match ? match->data : ERR_PTR(-EINVAL);
}
EXPORT_SYMBOL_GPL(atmel_hsmc_get_reg_layout);
| linux-master | drivers/mfd/atmel-smc.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Core support for ATC260x PMICs
*
* Copyright (C) 2019 Manivannan Sadhasivam <[email protected]>
* Copyright (C) 2020 Cristian Ciocaltea <[email protected]>
*/
#include <linux/interrupt.h>
#include <linux/mfd/atc260x/core.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#define ATC260X_CHIP_REV_MAX 31
struct atc260x_init_regs {
unsigned int cmu_devrst;
unsigned int cmu_devrst_ints;
unsigned int ints_msk;
unsigned int pad_en;
unsigned int pad_en_extirq;
};
static void regmap_lock_mutex(void *__mutex)
{
struct mutex *mutex = __mutex;
/*
* Using regmap within an atomic context (e.g. accessing a PMIC when
* powering system down) is normally allowed only if the regmap type
* is MMIO and the regcache type is either REGCACHE_NONE or
* REGCACHE_FLAT. For slow buses like I2C and SPI, the regmap is
* internally protected by a mutex which is acquired non-atomically.
*
* Let's improve this by using a customized locking scheme inspired
* from I2C atomic transfer. See i2c_in_atomic_xfer_mode() for a
* starting point.
*/
if (system_state > SYSTEM_RUNNING && irqs_disabled())
mutex_trylock(mutex);
else
mutex_lock(mutex);
}
static void regmap_unlock_mutex(void *__mutex)
{
struct mutex *mutex = __mutex;
mutex_unlock(mutex);
}
static const struct regmap_config atc2603c_regmap_config = {
.reg_bits = 8,
.val_bits = 16,
.max_register = ATC2603C_SADDR,
.cache_type = REGCACHE_NONE,
};
static const struct regmap_config atc2609a_regmap_config = {
.reg_bits = 8,
.val_bits = 16,
.max_register = ATC2609A_SADDR,
.cache_type = REGCACHE_NONE,
};
static const struct regmap_irq atc2603c_regmap_irqs[] = {
REGMAP_IRQ_REG(ATC2603C_IRQ_AUDIO, 0, ATC2603C_INTS_MSK_AUDIO),
REGMAP_IRQ_REG(ATC2603C_IRQ_OV, 0, ATC2603C_INTS_MSK_OV),
REGMAP_IRQ_REG(ATC2603C_IRQ_OC, 0, ATC2603C_INTS_MSK_OC),
REGMAP_IRQ_REG(ATC2603C_IRQ_OT, 0, ATC2603C_INTS_MSK_OT),
REGMAP_IRQ_REG(ATC2603C_IRQ_UV, 0, ATC2603C_INTS_MSK_UV),
REGMAP_IRQ_REG(ATC2603C_IRQ_ALARM, 0, ATC2603C_INTS_MSK_ALARM),
REGMAP_IRQ_REG(ATC2603C_IRQ_ONOFF, 0, ATC2603C_INTS_MSK_ONOFF),
REGMAP_IRQ_REG(ATC2603C_IRQ_SGPIO, 0, ATC2603C_INTS_MSK_SGPIO),
REGMAP_IRQ_REG(ATC2603C_IRQ_IR, 0, ATC2603C_INTS_MSK_IR),
REGMAP_IRQ_REG(ATC2603C_IRQ_REMCON, 0, ATC2603C_INTS_MSK_REMCON),
REGMAP_IRQ_REG(ATC2603C_IRQ_POWER_IN, 0, ATC2603C_INTS_MSK_POWERIN),
};
static const struct regmap_irq atc2609a_regmap_irqs[] = {
REGMAP_IRQ_REG(ATC2609A_IRQ_AUDIO, 0, ATC2609A_INTS_MSK_AUDIO),
REGMAP_IRQ_REG(ATC2609A_IRQ_OV, 0, ATC2609A_INTS_MSK_OV),
REGMAP_IRQ_REG(ATC2609A_IRQ_OC, 0, ATC2609A_INTS_MSK_OC),
REGMAP_IRQ_REG(ATC2609A_IRQ_OT, 0, ATC2609A_INTS_MSK_OT),
REGMAP_IRQ_REG(ATC2609A_IRQ_UV, 0, ATC2609A_INTS_MSK_UV),
REGMAP_IRQ_REG(ATC2609A_IRQ_ALARM, 0, ATC2609A_INTS_MSK_ALARM),
REGMAP_IRQ_REG(ATC2609A_IRQ_ONOFF, 0, ATC2609A_INTS_MSK_ONOFF),
REGMAP_IRQ_REG(ATC2609A_IRQ_WKUP, 0, ATC2609A_INTS_MSK_WKUP),
REGMAP_IRQ_REG(ATC2609A_IRQ_IR, 0, ATC2609A_INTS_MSK_IR),
REGMAP_IRQ_REG(ATC2609A_IRQ_REMCON, 0, ATC2609A_INTS_MSK_REMCON),
REGMAP_IRQ_REG(ATC2609A_IRQ_POWER_IN, 0, ATC2609A_INTS_MSK_POWERIN),
};
static const struct regmap_irq_chip atc2603c_regmap_irq_chip = {
.name = "atc2603c",
.irqs = atc2603c_regmap_irqs,
.num_irqs = ARRAY_SIZE(atc2603c_regmap_irqs),
.num_regs = 1,
.status_base = ATC2603C_INTS_PD,
.unmask_base = ATC2603C_INTS_MSK,
};
static const struct regmap_irq_chip atc2609a_regmap_irq_chip = {
.name = "atc2609a",
.irqs = atc2609a_regmap_irqs,
.num_irqs = ARRAY_SIZE(atc2609a_regmap_irqs),
.num_regs = 1,
.status_base = ATC2609A_INTS_PD,
.unmask_base = ATC2609A_INTS_MSK,
};
static const struct resource atc2603c_onkey_resources[] = {
DEFINE_RES_IRQ(ATC2603C_IRQ_ONOFF),
};
static const struct resource atc2609a_onkey_resources[] = {
DEFINE_RES_IRQ(ATC2609A_IRQ_ONOFF),
};
static const struct mfd_cell atc2603c_mfd_cells[] = {
{ .name = "atc260x-regulator" },
{ .name = "atc260x-pwrc" },
{
.name = "atc260x-onkey",
.num_resources = ARRAY_SIZE(atc2603c_onkey_resources),
.resources = atc2603c_onkey_resources,
},
};
static const struct mfd_cell atc2609a_mfd_cells[] = {
{ .name = "atc260x-regulator" },
{ .name = "atc260x-pwrc" },
{
.name = "atc260x-onkey",
.num_resources = ARRAY_SIZE(atc2609a_onkey_resources),
.resources = atc2609a_onkey_resources,
},
};
static const struct atc260x_init_regs atc2603c_init_regs = {
.cmu_devrst = ATC2603C_CMU_DEVRST,
.cmu_devrst_ints = ATC2603C_CMU_DEVRST_INTS,
.ints_msk = ATC2603C_INTS_MSK,
.pad_en = ATC2603C_PAD_EN,
.pad_en_extirq = ATC2603C_PAD_EN_EXTIRQ,
};
static const struct atc260x_init_regs atc2609a_init_regs = {
.cmu_devrst = ATC2609A_CMU_DEVRST,
.cmu_devrst_ints = ATC2609A_CMU_DEVRST_INTS,
.ints_msk = ATC2609A_INTS_MSK,
.pad_en = ATC2609A_PAD_EN,
.pad_en_extirq = ATC2609A_PAD_EN_EXTIRQ,
};
static void atc260x_cmu_reset(struct atc260x *atc260x)
{
const struct atc260x_init_regs *regs = atc260x->init_regs;
/* Assert reset */
regmap_update_bits(atc260x->regmap, regs->cmu_devrst,
regs->cmu_devrst_ints, ~regs->cmu_devrst_ints);
/* De-assert reset */
regmap_update_bits(atc260x->regmap, regs->cmu_devrst,
regs->cmu_devrst_ints, regs->cmu_devrst_ints);
}
static void atc260x_dev_init(struct atc260x *atc260x)
{
const struct atc260x_init_regs *regs = atc260x->init_regs;
/* Initialize interrupt block */
atc260x_cmu_reset(atc260x);
/* Disable all interrupt sources */
regmap_write(atc260x->regmap, regs->ints_msk, 0);
/* Enable EXTIRQ pad */
regmap_update_bits(atc260x->regmap, regs->pad_en,
regs->pad_en_extirq, regs->pad_en_extirq);
}
/**
* atc260x_match_device(): Setup ATC260x variant related fields
*
* @atc260x: ATC260x device to setup (.dev field must be set)
* @regmap_cfg: regmap config associated with this ATC260x device
*
* This lets the ATC260x core configure the MFD cells and register maps
* for later use.
*/
int atc260x_match_device(struct atc260x *atc260x, struct regmap_config *regmap_cfg)
{
struct device *dev = atc260x->dev;
const void *of_data;
of_data = of_device_get_match_data(dev);
if (!of_data)
return -ENODEV;
atc260x->ic_type = (unsigned long)of_data;
switch (atc260x->ic_type) {
case ATC2603C:
*regmap_cfg = atc2603c_regmap_config;
atc260x->regmap_irq_chip = &atc2603c_regmap_irq_chip;
atc260x->cells = atc2603c_mfd_cells;
atc260x->nr_cells = ARRAY_SIZE(atc2603c_mfd_cells);
atc260x->type_name = "atc2603c";
atc260x->rev_reg = ATC2603C_CHIP_VER;
atc260x->init_regs = &atc2603c_init_regs;
break;
case ATC2609A:
*regmap_cfg = atc2609a_regmap_config;
atc260x->regmap_irq_chip = &atc2609a_regmap_irq_chip;
atc260x->cells = atc2609a_mfd_cells;
atc260x->nr_cells = ARRAY_SIZE(atc2609a_mfd_cells);
atc260x->type_name = "atc2609a";
atc260x->rev_reg = ATC2609A_CHIP_VER;
atc260x->init_regs = &atc2609a_init_regs;
break;
default:
dev_err(dev, "Unsupported ATC260x device type: %u\n",
atc260x->ic_type);
return -EINVAL;
}
atc260x->regmap_mutex = devm_kzalloc(dev, sizeof(*atc260x->regmap_mutex),
GFP_KERNEL);
if (!atc260x->regmap_mutex)
return -ENOMEM;
mutex_init(atc260x->regmap_mutex);
regmap_cfg->lock = regmap_lock_mutex,
regmap_cfg->unlock = regmap_unlock_mutex,
regmap_cfg->lock_arg = atc260x->regmap_mutex;
return 0;
}
EXPORT_SYMBOL_GPL(atc260x_match_device);
/**
* atc260x_device_probe(): Probe a configured ATC260x device
*
* @atc260x: ATC260x device to probe (must be configured)
*
* This function lets the ATC260x core register the ATC260x MFD devices
* and IRQCHIP. The ATC260x device passed in must be fully configured
* with atc260x_match_device, its IRQ set, and regmap created.
*/
int atc260x_device_probe(struct atc260x *atc260x)
{
struct device *dev = atc260x->dev;
unsigned int chip_rev;
int ret;
if (!atc260x->irq) {
dev_err(dev, "No interrupt support\n");
return -EINVAL;
}
/* Initialize the hardware */
atc260x_dev_init(atc260x);
ret = regmap_read(atc260x->regmap, atc260x->rev_reg, &chip_rev);
if (ret) {
dev_err(dev, "Failed to get chip revision\n");
return ret;
}
if (chip_rev > ATC260X_CHIP_REV_MAX) {
dev_err(dev, "Unknown chip revision: %u\n", chip_rev);
return -EINVAL;
}
atc260x->ic_ver = __ffs(chip_rev + 1U);
dev_info(dev, "Detected chip type %s rev.%c\n",
atc260x->type_name, 'A' + atc260x->ic_ver);
ret = devm_regmap_add_irq_chip(dev, atc260x->regmap, atc260x->irq, IRQF_ONESHOT,
-1, atc260x->regmap_irq_chip, &atc260x->irq_data);
if (ret) {
dev_err(dev, "Failed to add IRQ chip: %d\n", ret);
return ret;
}
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
atc260x->cells, atc260x->nr_cells, NULL, 0,
regmap_irq_get_domain(atc260x->irq_data));
if (ret) {
dev_err(dev, "Failed to add child devices: %d\n", ret);
regmap_del_irq_chip(atc260x->irq, atc260x->irq_data);
}
return ret;
}
EXPORT_SYMBOL_GPL(atc260x_device_probe);
MODULE_DESCRIPTION("ATC260x PMICs Core support");
MODULE_AUTHOR("Manivannan Sadhasivam <[email protected]>");
MODULE_AUTHOR("Cristian Ciocaltea <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/atc260x-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* SPI access driver for TI TPS65912x PMICs
*
* Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/
* Andrew F. Davis <[email protected]>
*
* Based on the TPS65218 driver and the previous TPS65912 driver by
* Margarita Olaya Cabrera <[email protected]>
*/
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/mfd/tps65912.h>
static const struct of_device_id tps65912_spi_of_match_table[] = {
{ .compatible = "ti,tps65912", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, tps65912_spi_of_match_table);
static int tps65912_spi_probe(struct spi_device *spi)
{
struct tps65912 *tps;
tps = devm_kzalloc(&spi->dev, sizeof(*tps), GFP_KERNEL);
if (!tps)
return -ENOMEM;
spi_set_drvdata(spi, tps);
tps->dev = &spi->dev;
tps->irq = spi->irq;
tps->regmap = devm_regmap_init_spi(spi, &tps65912_regmap_config);
if (IS_ERR(tps->regmap)) {
dev_err(tps->dev, "Failed to initialize register map\n");
return PTR_ERR(tps->regmap);
}
return tps65912_device_init(tps);
}
static void tps65912_spi_remove(struct spi_device *spi)
{
struct tps65912 *tps = spi_get_drvdata(spi);
tps65912_device_exit(tps);
}
static const struct spi_device_id tps65912_spi_id_table[] = {
{ "tps65912", 0 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(spi, tps65912_spi_id_table);
static struct spi_driver tps65912_spi_driver = {
.driver = {
.name = "tps65912",
.of_match_table = tps65912_spi_of_match_table,
},
.probe = tps65912_spi_probe,
.remove = tps65912_spi_remove,
.id_table = tps65912_spi_id_table,
};
module_spi_driver(tps65912_spi_driver);
MODULE_AUTHOR("Andrew F. Davis <[email protected]>");
MODULE_DESCRIPTION("TPS65912x SPI Interface Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/tps65912-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* MFD driver for TWL6040 audio device
*
* Authors: Misael Lopez Cruz <[email protected]>
* Jorge Eduardo Candelaria <[email protected]>
* Peter Ujfalusi <[email protected]>
*
* Copyright: (C) 2011 Texas Instruments, Inc.
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/gpio/consumer.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/mfd/twl6040.h>
#include <linux/regulator/consumer.h>
#define VIBRACTRL_MEMBER(reg) ((reg == TWL6040_REG_VIBCTLL) ? 0 : 1)
#define TWL6040_NUM_SUPPLIES (2)
static const struct reg_default twl6040_defaults[] = {
{ 0x01, 0x4B }, /* REG_ASICID (ro) */
{ 0x02, 0x00 }, /* REG_ASICREV (ro) */
{ 0x03, 0x00 }, /* REG_INTID */
{ 0x04, 0x00 }, /* REG_INTMR */
{ 0x05, 0x00 }, /* REG_NCPCTRL */
{ 0x06, 0x00 }, /* REG_LDOCTL */
{ 0x07, 0x60 }, /* REG_HPPLLCTL */
{ 0x08, 0x00 }, /* REG_LPPLLCTL */
{ 0x09, 0x4A }, /* REG_LPPLLDIV */
{ 0x0A, 0x00 }, /* REG_AMICBCTL */
{ 0x0B, 0x00 }, /* REG_DMICBCTL */
{ 0x0C, 0x00 }, /* REG_MICLCTL */
{ 0x0D, 0x00 }, /* REG_MICRCTL */
{ 0x0E, 0x00 }, /* REG_MICGAIN */
{ 0x0F, 0x1B }, /* REG_LINEGAIN */
{ 0x10, 0x00 }, /* REG_HSLCTL */
{ 0x11, 0x00 }, /* REG_HSRCTL */
{ 0x12, 0x00 }, /* REG_HSGAIN */
{ 0x13, 0x00 }, /* REG_EARCTL */
{ 0x14, 0x00 }, /* REG_HFLCTL */
{ 0x15, 0x00 }, /* REG_HFLGAIN */
{ 0x16, 0x00 }, /* REG_HFRCTL */
{ 0x17, 0x00 }, /* REG_HFRGAIN */
{ 0x18, 0x00 }, /* REG_VIBCTLL */
{ 0x19, 0x00 }, /* REG_VIBDATL */
{ 0x1A, 0x00 }, /* REG_VIBCTLR */
{ 0x1B, 0x00 }, /* REG_VIBDATR */
{ 0x1C, 0x00 }, /* REG_HKCTL1 */
{ 0x1D, 0x00 }, /* REG_HKCTL2 */
{ 0x1E, 0x00 }, /* REG_GPOCTL */
{ 0x1F, 0x00 }, /* REG_ALB */
{ 0x20, 0x00 }, /* REG_DLB */
/* 0x28, REG_TRIM1 */
/* 0x29, REG_TRIM2 */
/* 0x2A, REG_TRIM3 */
/* 0x2B, REG_HSOTRIM */
/* 0x2C, REG_HFOTRIM */
{ 0x2D, 0x08 }, /* REG_ACCCTL */
{ 0x2E, 0x00 }, /* REG_STATUS (ro) */
};
static struct reg_sequence twl6040_patch[] = {
/*
* Select I2C bus access to dual access registers
* Interrupt register is cleared on read
* Select fast mode for i2c (400KHz)
*/
{ TWL6040_REG_ACCCTL,
TWL6040_I2CSEL | TWL6040_INTCLRMODE | TWL6040_I2CMODE(1) },
};
static bool twl6040_has_vibra(struct device_node *parent)
{
struct device_node *node;
node = of_get_child_by_name(parent, "vibra");
if (node) {
of_node_put(node);
return true;
}
return false;
}
int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg)
{
int ret;
unsigned int val;
ret = regmap_read(twl6040->regmap, reg, &val);
if (ret < 0)
return ret;
return val;
}
EXPORT_SYMBOL(twl6040_reg_read);
int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, u8 val)
{
int ret;
ret = regmap_write(twl6040->regmap, reg, val);
return ret;
}
EXPORT_SYMBOL(twl6040_reg_write);
int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
{
return regmap_update_bits(twl6040->regmap, reg, mask, mask);
}
EXPORT_SYMBOL(twl6040_set_bits);
int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
{
return regmap_update_bits(twl6040->regmap, reg, mask, 0);
}
EXPORT_SYMBOL(twl6040_clear_bits);
/* twl6040 codec manual power-up sequence */
static int twl6040_power_up_manual(struct twl6040 *twl6040)
{
u8 ldoctl, ncpctl, lppllctl;
int ret;
/* enable high-side LDO, reference system and internal oscillator */
ldoctl = TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA;
ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
if (ret)
return ret;
usleep_range(10000, 10500);
/* enable negative charge pump */
ncpctl = TWL6040_NCPENA;
ret = twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
if (ret)
goto ncp_err;
usleep_range(1000, 1500);
/* enable low-side LDO */
ldoctl |= TWL6040_LSLDOENA;
ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
if (ret)
goto lsldo_err;
usleep_range(1000, 1500);
/* enable low-power PLL */
lppllctl = TWL6040_LPLLENA;
ret = twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
if (ret)
goto lppll_err;
usleep_range(5000, 5500);
/* disable internal oscillator */
ldoctl &= ~TWL6040_OSCENA;
ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
if (ret)
goto osc_err;
return 0;
osc_err:
lppllctl &= ~TWL6040_LPLLENA;
twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
lppll_err:
ldoctl &= ~TWL6040_LSLDOENA;
twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
lsldo_err:
ncpctl &= ~TWL6040_NCPENA;
twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
ncp_err:
ldoctl &= ~(TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA);
twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
dev_err(twl6040->dev, "manual power-up failed\n");
return ret;
}
/* twl6040 manual power-down sequence */
static void twl6040_power_down_manual(struct twl6040 *twl6040)
{
u8 ncpctl, ldoctl, lppllctl;
ncpctl = twl6040_reg_read(twl6040, TWL6040_REG_NCPCTL);
ldoctl = twl6040_reg_read(twl6040, TWL6040_REG_LDOCTL);
lppllctl = twl6040_reg_read(twl6040, TWL6040_REG_LPPLLCTL);
/* enable internal oscillator */
ldoctl |= TWL6040_OSCENA;
twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
usleep_range(1000, 1500);
/* disable low-power PLL */
lppllctl &= ~TWL6040_LPLLENA;
twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
/* disable low-side LDO */
ldoctl &= ~TWL6040_LSLDOENA;
twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
/* disable negative charge pump */
ncpctl &= ~TWL6040_NCPENA;
twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
/* disable high-side LDO, reference system and internal oscillator */
ldoctl &= ~(TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA);
twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
}
static irqreturn_t twl6040_readyint_handler(int irq, void *data)
{
struct twl6040 *twl6040 = data;
complete(&twl6040->ready);
return IRQ_HANDLED;
}
static irqreturn_t twl6040_thint_handler(int irq, void *data)
{
struct twl6040 *twl6040 = data;
u8 status;
status = twl6040_reg_read(twl6040, TWL6040_REG_STATUS);
if (status & TWL6040_TSHUTDET) {
dev_warn(twl6040->dev, "Thermal shutdown, powering-off");
twl6040_power(twl6040, 0);
} else {
dev_warn(twl6040->dev, "Leaving thermal shutdown, powering-on");
twl6040_power(twl6040, 1);
}
return IRQ_HANDLED;
}
static int twl6040_power_up_automatic(struct twl6040 *twl6040)
{
int time_left;
gpiod_set_value_cansleep(twl6040->audpwron, 1);
time_left = wait_for_completion_timeout(&twl6040->ready,
msecs_to_jiffies(144));
if (!time_left) {
u8 intid;
dev_warn(twl6040->dev, "timeout waiting for READYINT\n");
intid = twl6040_reg_read(twl6040, TWL6040_REG_INTID);
if (!(intid & TWL6040_READYINT)) {
dev_err(twl6040->dev, "automatic power-up failed\n");
gpiod_set_value_cansleep(twl6040->audpwron, 0);
return -ETIMEDOUT;
}
}
return 0;
}
int twl6040_power(struct twl6040 *twl6040, int on)
{
int ret = 0;
mutex_lock(&twl6040->mutex);
if (on) {
/* already powered-up */
if (twl6040->power_count++)
goto out;
ret = clk_prepare_enable(twl6040->clk32k);
if (ret) {
twl6040->power_count = 0;
goto out;
}
/* Allow writes to the chip */
regcache_cache_only(twl6040->regmap, false);
if (twl6040->audpwron) {
/* use automatic power-up sequence */
ret = twl6040_power_up_automatic(twl6040);
if (ret) {
clk_disable_unprepare(twl6040->clk32k);
twl6040->power_count = 0;
goto out;
}
} else {
/* use manual power-up sequence */
ret = twl6040_power_up_manual(twl6040);
if (ret) {
clk_disable_unprepare(twl6040->clk32k);
twl6040->power_count = 0;
goto out;
}
}
/*
* Register access can produce errors after power-up unless we
* wait at least 8ms based on measurements on duovero.
*/
usleep_range(10000, 12000);
/* Sync with the HW */
ret = regcache_sync(twl6040->regmap);
if (ret) {
dev_err(twl6040->dev, "Failed to sync with the HW: %i\n",
ret);
goto out;
}
/* Default PLL configuration after power up */
twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL;
twl6040->sysclk_rate = 19200000;
} else {
/* already powered-down */
if (!twl6040->power_count) {
dev_err(twl6040->dev,
"device is already powered-off\n");
ret = -EPERM;
goto out;
}
if (--twl6040->power_count)
goto out;
if (twl6040->audpwron) {
/* use AUDPWRON line */
gpiod_set_value_cansleep(twl6040->audpwron, 0);
/* power-down sequence latency */
usleep_range(500, 700);
} else {
/* use manual power-down sequence */
twl6040_power_down_manual(twl6040);
}
/* Set regmap to cache only and mark it as dirty */
regcache_cache_only(twl6040->regmap, true);
regcache_mark_dirty(twl6040->regmap);
twl6040->sysclk_rate = 0;
if (twl6040->pll == TWL6040_SYSCLK_SEL_HPPLL) {
clk_disable_unprepare(twl6040->mclk);
twl6040->mclk_rate = 0;
}
clk_disable_unprepare(twl6040->clk32k);
}
out:
mutex_unlock(&twl6040->mutex);
return ret;
}
EXPORT_SYMBOL(twl6040_power);
int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
unsigned int freq_in, unsigned int freq_out)
{
u8 hppllctl, lppllctl;
int ret = 0;
mutex_lock(&twl6040->mutex);
hppllctl = twl6040_reg_read(twl6040, TWL6040_REG_HPPLLCTL);
lppllctl = twl6040_reg_read(twl6040, TWL6040_REG_LPPLLCTL);
/* Force full reconfiguration when switching between PLL */
if (pll_id != twl6040->pll) {
twl6040->sysclk_rate = 0;
twl6040->mclk_rate = 0;
}
switch (pll_id) {
case TWL6040_SYSCLK_SEL_LPPLL:
/* low-power PLL divider */
/* Change the sysclk configuration only if it has been canged */
if (twl6040->sysclk_rate != freq_out) {
switch (freq_out) {
case 17640000:
lppllctl |= TWL6040_LPLLFIN;
break;
case 19200000:
lppllctl &= ~TWL6040_LPLLFIN;
break;
default:
dev_err(twl6040->dev,
"freq_out %d not supported\n",
freq_out);
ret = -EINVAL;
goto pll_out;
}
twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
lppllctl);
}
/* The PLL in use has not been change, we can exit */
if (twl6040->pll == pll_id)
break;
switch (freq_in) {
case 32768:
lppllctl |= TWL6040_LPLLENA;
twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
lppllctl);
mdelay(5);
lppllctl &= ~TWL6040_HPLLSEL;
twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
lppllctl);
hppllctl &= ~TWL6040_HPLLENA;
twl6040_reg_write(twl6040, TWL6040_REG_HPPLLCTL,
hppllctl);
break;
default:
dev_err(twl6040->dev,
"freq_in %d not supported\n", freq_in);
ret = -EINVAL;
goto pll_out;
}
clk_disable_unprepare(twl6040->mclk);
break;
case TWL6040_SYSCLK_SEL_HPPLL:
/* high-performance PLL can provide only 19.2 MHz */
if (freq_out != 19200000) {
dev_err(twl6040->dev,
"freq_out %d not supported\n", freq_out);
ret = -EINVAL;
goto pll_out;
}
if (twl6040->mclk_rate != freq_in) {
hppllctl &= ~TWL6040_MCLK_MSK;
switch (freq_in) {
case 12000000:
/* PLL enabled, active mode */
hppllctl |= TWL6040_MCLK_12000KHZ |
TWL6040_HPLLENA;
break;
case 19200000:
/* PLL enabled, bypass mode */
hppllctl |= TWL6040_MCLK_19200KHZ |
TWL6040_HPLLBP | TWL6040_HPLLENA;
break;
case 26000000:
/* PLL enabled, active mode */
hppllctl |= TWL6040_MCLK_26000KHZ |
TWL6040_HPLLENA;
break;
case 38400000:
/* PLL enabled, bypass mode */
hppllctl |= TWL6040_MCLK_38400KHZ |
TWL6040_HPLLBP | TWL6040_HPLLENA;
break;
default:
dev_err(twl6040->dev,
"freq_in %d not supported\n", freq_in);
ret = -EINVAL;
goto pll_out;
}
/* When switching to HPPLL, enable the mclk first */
if (pll_id != twl6040->pll)
clk_prepare_enable(twl6040->mclk);
/*
* enable clock slicer to ensure input waveform is
* square
*/
hppllctl |= TWL6040_HPLLSQRENA;
twl6040_reg_write(twl6040, TWL6040_REG_HPPLLCTL,
hppllctl);
usleep_range(500, 700);
lppllctl |= TWL6040_HPLLSEL;
twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
lppllctl);
lppllctl &= ~TWL6040_LPLLENA;
twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
lppllctl);
twl6040->mclk_rate = freq_in;
}
break;
default:
dev_err(twl6040->dev, "unknown pll id %d\n", pll_id);
ret = -EINVAL;
goto pll_out;
}
twl6040->sysclk_rate = freq_out;
twl6040->pll = pll_id;
pll_out:
mutex_unlock(&twl6040->mutex);
return ret;
}
EXPORT_SYMBOL(twl6040_set_pll);
int twl6040_get_pll(struct twl6040 *twl6040)
{
if (twl6040->power_count)
return twl6040->pll;
else
return -ENODEV;
}
EXPORT_SYMBOL(twl6040_get_pll);
unsigned int twl6040_get_sysclk(struct twl6040 *twl6040)
{
return twl6040->sysclk_rate;
}
EXPORT_SYMBOL(twl6040_get_sysclk);
/* Get the combined status of the vibra control register */
int twl6040_get_vibralr_status(struct twl6040 *twl6040)
{
unsigned int reg;
int ret;
u8 status;
ret = regmap_read(twl6040->regmap, TWL6040_REG_VIBCTLL, ®);
if (ret != 0)
return ret;
status = reg;
ret = regmap_read(twl6040->regmap, TWL6040_REG_VIBCTLR, ®);
if (ret != 0)
return ret;
status |= reg;
status &= (TWL6040_VIBENA | TWL6040_VIBSEL);
return status;
}
EXPORT_SYMBOL(twl6040_get_vibralr_status);
static struct resource twl6040_vibra_rsrc[] = {
{
.flags = IORESOURCE_IRQ,
},
};
static struct resource twl6040_codec_rsrc[] = {
{
.flags = IORESOURCE_IRQ,
},
};
static bool twl6040_readable_reg(struct device *dev, unsigned int reg)
{
/* Register 0 is not readable */
if (!reg)
return false;
return true;
}
static bool twl6040_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TWL6040_REG_ASICID:
case TWL6040_REG_ASICREV:
case TWL6040_REG_INTID:
case TWL6040_REG_LPPLLCTL:
case TWL6040_REG_HPPLLCTL:
case TWL6040_REG_STATUS:
return true;
default:
return false;
}
}
static bool twl6040_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TWL6040_REG_ASICID:
case TWL6040_REG_ASICREV:
case TWL6040_REG_STATUS:
return false;
default:
return true;
}
}
static const struct regmap_config twl6040_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.reg_defaults = twl6040_defaults,
.num_reg_defaults = ARRAY_SIZE(twl6040_defaults),
.max_register = TWL6040_REG_STATUS, /* 0x2e */
.readable_reg = twl6040_readable_reg,
.volatile_reg = twl6040_volatile_reg,
.writeable_reg = twl6040_writeable_reg,
.cache_type = REGCACHE_MAPLE,
.use_single_read = true,
.use_single_write = true,
};
static const struct regmap_irq twl6040_irqs[] = {
{ .reg_offset = 0, .mask = TWL6040_THINT, },
{ .reg_offset = 0, .mask = TWL6040_PLUGINT | TWL6040_UNPLUGINT, },
{ .reg_offset = 0, .mask = TWL6040_HOOKINT, },
{ .reg_offset = 0, .mask = TWL6040_HFINT, },
{ .reg_offset = 0, .mask = TWL6040_VIBINT, },
{ .reg_offset = 0, .mask = TWL6040_READYINT, },
};
static struct regmap_irq_chip twl6040_irq_chip = {
.name = "twl6040",
.irqs = twl6040_irqs,
.num_irqs = ARRAY_SIZE(twl6040_irqs),
.num_regs = 1,
.status_base = TWL6040_REG_INTID,
.mask_base = TWL6040_REG_INTMR,
};
static int twl6040_probe(struct i2c_client *client)
{
struct device_node *node = client->dev.of_node;
struct twl6040 *twl6040;
struct mfd_cell *cell = NULL;
int irq, ret, children = 0;
if (!node) {
dev_err(&client->dev, "of node is missing\n");
return -EINVAL;
}
/* In order to operate correctly we need valid interrupt config */
if (!client->irq) {
dev_err(&client->dev, "Invalid IRQ configuration\n");
return -EINVAL;
}
twl6040 = devm_kzalloc(&client->dev, sizeof(struct twl6040),
GFP_KERNEL);
if (!twl6040)
return -ENOMEM;
twl6040->regmap = devm_regmap_init_i2c(client, &twl6040_regmap_config);
if (IS_ERR(twl6040->regmap))
return PTR_ERR(twl6040->regmap);
i2c_set_clientdata(client, twl6040);
twl6040->clk32k = devm_clk_get(&client->dev, "clk32k");
if (IS_ERR(twl6040->clk32k)) {
if (PTR_ERR(twl6040->clk32k) == -EPROBE_DEFER)
return -EPROBE_DEFER;
dev_dbg(&client->dev, "clk32k is not handled\n");
twl6040->clk32k = NULL;
}
twl6040->mclk = devm_clk_get(&client->dev, "mclk");
if (IS_ERR(twl6040->mclk)) {
if (PTR_ERR(twl6040->mclk) == -EPROBE_DEFER)
return -EPROBE_DEFER;
dev_dbg(&client->dev, "mclk is not handled\n");
twl6040->mclk = NULL;
}
twl6040->supplies[0].supply = "vio";
twl6040->supplies[1].supply = "v2v1";
ret = devm_regulator_bulk_get(&client->dev, TWL6040_NUM_SUPPLIES,
twl6040->supplies);
if (ret != 0) {
dev_err(&client->dev, "Failed to get supplies: %d\n", ret);
return ret;
}
ret = regulator_bulk_enable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
if (ret != 0) {
dev_err(&client->dev, "Failed to enable supplies: %d\n", ret);
return ret;
}
twl6040->dev = &client->dev;
twl6040->irq = client->irq;
mutex_init(&twl6040->mutex);
init_completion(&twl6040->ready);
regmap_register_patch(twl6040->regmap, twl6040_patch,
ARRAY_SIZE(twl6040_patch));
twl6040->rev = twl6040_reg_read(twl6040, TWL6040_REG_ASICREV);
if (twl6040->rev < 0) {
dev_err(&client->dev, "Failed to read revision register: %d\n",
twl6040->rev);
ret = twl6040->rev;
goto gpio_err;
}
/* ERRATA: Automatic power-up is not possible in ES1.0 */
if (twl6040_get_revid(twl6040) > TWL6040_REV_ES1_0) {
twl6040->audpwron = devm_gpiod_get_optional(&client->dev,
"ti,audpwron",
GPIOD_OUT_LOW);
ret = PTR_ERR_OR_ZERO(twl6040->audpwron);
if (ret)
goto gpio_err;
gpiod_set_consumer_name(twl6040->audpwron, "audpwron");
/* Clear any pending interrupt */
twl6040_reg_read(twl6040, TWL6040_REG_INTID);
}
ret = regmap_add_irq_chip(twl6040->regmap, twl6040->irq, IRQF_ONESHOT,
0, &twl6040_irq_chip, &twl6040->irq_data);
if (ret < 0)
goto gpio_err;
twl6040->irq_ready = regmap_irq_get_virq(twl6040->irq_data,
TWL6040_IRQ_READY);
twl6040->irq_th = regmap_irq_get_virq(twl6040->irq_data,
TWL6040_IRQ_TH);
ret = devm_request_threaded_irq(twl6040->dev, twl6040->irq_ready, NULL,
twl6040_readyint_handler, IRQF_ONESHOT,
"twl6040_irq_ready", twl6040);
if (ret) {
dev_err(twl6040->dev, "READY IRQ request failed: %d\n", ret);
goto readyirq_err;
}
ret = devm_request_threaded_irq(twl6040->dev, twl6040->irq_th, NULL,
twl6040_thint_handler, IRQF_ONESHOT,
"twl6040_irq_th", twl6040);
if (ret) {
dev_err(twl6040->dev, "Thermal IRQ request failed: %d\n", ret);
goto readyirq_err;
}
/*
* The main functionality of twl6040 to provide audio on OMAP4+ systems.
* We can add the ASoC codec child whenever this driver has been loaded.
*/
irq = regmap_irq_get_virq(twl6040->irq_data, TWL6040_IRQ_PLUG);
cell = &twl6040->cells[children];
cell->name = "twl6040-codec";
twl6040_codec_rsrc[0].start = irq;
twl6040_codec_rsrc[0].end = irq;
cell->resources = twl6040_codec_rsrc;
cell->num_resources = ARRAY_SIZE(twl6040_codec_rsrc);
children++;
/* Vibra input driver support */
if (twl6040_has_vibra(node)) {
irq = regmap_irq_get_virq(twl6040->irq_data, TWL6040_IRQ_VIB);
cell = &twl6040->cells[children];
cell->name = "twl6040-vibra";
twl6040_vibra_rsrc[0].start = irq;
twl6040_vibra_rsrc[0].end = irq;
cell->resources = twl6040_vibra_rsrc;
cell->num_resources = ARRAY_SIZE(twl6040_vibra_rsrc);
children++;
}
/* GPO support */
cell = &twl6040->cells[children];
cell->name = "twl6040-gpo";
children++;
/* PDM clock support */
cell = &twl6040->cells[children];
cell->name = "twl6040-pdmclk";
children++;
/* The chip is powered down so mark regmap to cache only and dirty */
regcache_cache_only(twl6040->regmap, true);
regcache_mark_dirty(twl6040->regmap);
ret = mfd_add_devices(&client->dev, -1, twl6040->cells, children,
NULL, 0, NULL);
if (ret)
goto readyirq_err;
return 0;
readyirq_err:
regmap_del_irq_chip(twl6040->irq, twl6040->irq_data);
gpio_err:
regulator_bulk_disable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
return ret;
}
static void twl6040_remove(struct i2c_client *client)
{
struct twl6040 *twl6040 = i2c_get_clientdata(client);
if (twl6040->power_count)
twl6040_power(twl6040, 0);
regmap_del_irq_chip(twl6040->irq, twl6040->irq_data);
mfd_remove_devices(&client->dev);
regulator_bulk_disable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
}
static const struct i2c_device_id twl6040_i2c_id[] = {
{ "twl6040", 0, },
{ "twl6041", 0, },
{ },
};
MODULE_DEVICE_TABLE(i2c, twl6040_i2c_id);
static struct i2c_driver twl6040_driver = {
.driver = {
.name = "twl6040",
},
.probe = twl6040_probe,
.remove = twl6040_remove,
.id_table = twl6040_i2c_id,
};
module_i2c_driver(twl6040_driver);
MODULE_DESCRIPTION("TWL6040 MFD");
MODULE_AUTHOR("Misael Lopez Cruz <[email protected]>");
MODULE_AUTHOR("Jorge Eduardo Candelaria <[email protected]>");
| linux-master | drivers/mfd/twl6040.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Core, IRQ and I2C device driver for DA9061 and DA9062 PMICs
* Copyright (C) 2015-2017 Dialog Semiconductor
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/i2c.h>
#include <linux/mfd/da9062/core.h>
#include <linux/mfd/da9062/registers.h>
#include <linux/regulator/of_regulator.h>
#define DA9062_REG_EVENT_A_OFFSET 0
#define DA9062_REG_EVENT_B_OFFSET 1
#define DA9062_REG_EVENT_C_OFFSET 2
#define DA9062_IRQ_LOW 0
#define DA9062_IRQ_HIGH 1
static struct regmap_irq da9061_irqs[] = {
/* EVENT A */
[DA9061_IRQ_ONKEY] = {
.reg_offset = DA9062_REG_EVENT_A_OFFSET,
.mask = DA9062AA_M_NONKEY_MASK,
},
[DA9061_IRQ_WDG_WARN] = {
.reg_offset = DA9062_REG_EVENT_A_OFFSET,
.mask = DA9062AA_M_WDG_WARN_MASK,
},
[DA9061_IRQ_SEQ_RDY] = {
.reg_offset = DA9062_REG_EVENT_A_OFFSET,
.mask = DA9062AA_M_SEQ_RDY_MASK,
},
/* EVENT B */
[DA9061_IRQ_TEMP] = {
.reg_offset = DA9062_REG_EVENT_B_OFFSET,
.mask = DA9062AA_M_TEMP_MASK,
},
[DA9061_IRQ_LDO_LIM] = {
.reg_offset = DA9062_REG_EVENT_B_OFFSET,
.mask = DA9062AA_M_LDO_LIM_MASK,
},
[DA9061_IRQ_DVC_RDY] = {
.reg_offset = DA9062_REG_EVENT_B_OFFSET,
.mask = DA9062AA_M_DVC_RDY_MASK,
},
[DA9061_IRQ_VDD_WARN] = {
.reg_offset = DA9062_REG_EVENT_B_OFFSET,
.mask = DA9062AA_M_VDD_WARN_MASK,
},
/* EVENT C */
[DA9061_IRQ_GPI0] = {
.reg_offset = DA9062_REG_EVENT_C_OFFSET,
.mask = DA9062AA_M_GPI0_MASK,
},
[DA9061_IRQ_GPI1] = {
.reg_offset = DA9062_REG_EVENT_C_OFFSET,
.mask = DA9062AA_M_GPI1_MASK,
},
[DA9061_IRQ_GPI2] = {
.reg_offset = DA9062_REG_EVENT_C_OFFSET,
.mask = DA9062AA_M_GPI2_MASK,
},
[DA9061_IRQ_GPI3] = {
.reg_offset = DA9062_REG_EVENT_C_OFFSET,
.mask = DA9062AA_M_GPI3_MASK,
},
[DA9061_IRQ_GPI4] = {
.reg_offset = DA9062_REG_EVENT_C_OFFSET,
.mask = DA9062AA_M_GPI4_MASK,
},
};
static struct regmap_irq_chip da9061_irq_chip = {
.name = "da9061-irq",
.irqs = da9061_irqs,
.num_irqs = DA9061_NUM_IRQ,
.num_regs = 3,
.status_base = DA9062AA_EVENT_A,
.mask_base = DA9062AA_IRQ_MASK_A,
.ack_base = DA9062AA_EVENT_A,
};
static struct regmap_irq da9062_irqs[] = {
/* EVENT A */
[DA9062_IRQ_ONKEY] = {
.reg_offset = DA9062_REG_EVENT_A_OFFSET,
.mask = DA9062AA_M_NONKEY_MASK,
},
[DA9062_IRQ_ALARM] = {
.reg_offset = DA9062_REG_EVENT_A_OFFSET,
.mask = DA9062AA_M_ALARM_MASK,
},
[DA9062_IRQ_TICK] = {
.reg_offset = DA9062_REG_EVENT_A_OFFSET,
.mask = DA9062AA_M_TICK_MASK,
},
[DA9062_IRQ_WDG_WARN] = {
.reg_offset = DA9062_REG_EVENT_A_OFFSET,
.mask = DA9062AA_M_WDG_WARN_MASK,
},
[DA9062_IRQ_SEQ_RDY] = {
.reg_offset = DA9062_REG_EVENT_A_OFFSET,
.mask = DA9062AA_M_SEQ_RDY_MASK,
},
/* EVENT B */
[DA9062_IRQ_TEMP] = {
.reg_offset = DA9062_REG_EVENT_B_OFFSET,
.mask = DA9062AA_M_TEMP_MASK,
},
[DA9062_IRQ_LDO_LIM] = {
.reg_offset = DA9062_REG_EVENT_B_OFFSET,
.mask = DA9062AA_M_LDO_LIM_MASK,
},
[DA9062_IRQ_DVC_RDY] = {
.reg_offset = DA9062_REG_EVENT_B_OFFSET,
.mask = DA9062AA_M_DVC_RDY_MASK,
},
[DA9062_IRQ_VDD_WARN] = {
.reg_offset = DA9062_REG_EVENT_B_OFFSET,
.mask = DA9062AA_M_VDD_WARN_MASK,
},
/* EVENT C */
[DA9062_IRQ_GPI0] = {
.reg_offset = DA9062_REG_EVENT_C_OFFSET,
.mask = DA9062AA_M_GPI0_MASK,
},
[DA9062_IRQ_GPI1] = {
.reg_offset = DA9062_REG_EVENT_C_OFFSET,
.mask = DA9062AA_M_GPI1_MASK,
},
[DA9062_IRQ_GPI2] = {
.reg_offset = DA9062_REG_EVENT_C_OFFSET,
.mask = DA9062AA_M_GPI2_MASK,
},
[DA9062_IRQ_GPI3] = {
.reg_offset = DA9062_REG_EVENT_C_OFFSET,
.mask = DA9062AA_M_GPI3_MASK,
},
[DA9062_IRQ_GPI4] = {
.reg_offset = DA9062_REG_EVENT_C_OFFSET,
.mask = DA9062AA_M_GPI4_MASK,
},
};
static struct regmap_irq_chip da9062_irq_chip = {
.name = "da9062-irq",
.irqs = da9062_irqs,
.num_irqs = DA9062_NUM_IRQ,
.num_regs = 3,
.status_base = DA9062AA_EVENT_A,
.mask_base = DA9062AA_IRQ_MASK_A,
.ack_base = DA9062AA_EVENT_A,
};
static const struct resource da9061_core_resources[] = {
DEFINE_RES_IRQ_NAMED(DA9061_IRQ_VDD_WARN, "VDD_WARN"),
};
static const struct resource da9061_regulators_resources[] = {
DEFINE_RES_IRQ_NAMED(DA9061_IRQ_LDO_LIM, "LDO_LIM"),
};
static const struct resource da9061_thermal_resources[] = {
DEFINE_RES_IRQ_NAMED(DA9061_IRQ_TEMP, "THERMAL"),
};
static const struct resource da9061_wdt_resources[] = {
DEFINE_RES_IRQ_NAMED(DA9061_IRQ_WDG_WARN, "WD_WARN"),
};
static const struct resource da9061_onkey_resources[] = {
DEFINE_RES_IRQ_NAMED(DA9061_IRQ_ONKEY, "ONKEY"),
};
static const struct mfd_cell da9061_devs_irq[] = {
MFD_CELL_OF("da9061-core", da9061_core_resources, NULL, 0, 0,
NULL),
MFD_CELL_OF("da9062-regulators", da9061_regulators_resources, NULL, 0, 0,
NULL),
MFD_CELL_OF("da9061-watchdog", da9061_wdt_resources, NULL, 0, 0,
"dlg,da9061-watchdog"),
MFD_CELL_OF("da9061-thermal", da9061_thermal_resources, NULL, 0, 0,
"dlg,da9061-thermal"),
MFD_CELL_OF("da9061-onkey", da9061_onkey_resources, NULL, 0, 0,
"dlg,da9061-onkey"),
};
static const struct mfd_cell da9061_devs_noirq[] = {
MFD_CELL_OF("da9061-core", NULL, NULL, 0, 0, NULL),
MFD_CELL_OF("da9062-regulators", NULL, NULL, 0, 0, NULL),
MFD_CELL_OF("da9061-watchdog", NULL, NULL, 0, 0, "dlg,da9061-watchdog"),
MFD_CELL_OF("da9061-thermal", NULL, NULL, 0, 0, "dlg,da9061-thermal"),
MFD_CELL_OF("da9061-onkey", NULL, NULL, 0, 0, "dlg,da9061-onkey"),
};
static const struct resource da9062_core_resources[] = {
DEFINE_RES_NAMED(DA9062_IRQ_VDD_WARN, 1, "VDD_WARN", IORESOURCE_IRQ),
};
static const struct resource da9062_regulators_resources[] = {
DEFINE_RES_NAMED(DA9062_IRQ_LDO_LIM, 1, "LDO_LIM", IORESOURCE_IRQ),
};
static const struct resource da9062_thermal_resources[] = {
DEFINE_RES_NAMED(DA9062_IRQ_TEMP, 1, "THERMAL", IORESOURCE_IRQ),
};
static const struct resource da9062_wdt_resources[] = {
DEFINE_RES_NAMED(DA9062_IRQ_WDG_WARN, 1, "WD_WARN", IORESOURCE_IRQ),
};
static const struct resource da9062_rtc_resources[] = {
DEFINE_RES_NAMED(DA9062_IRQ_ALARM, 1, "ALARM", IORESOURCE_IRQ),
DEFINE_RES_NAMED(DA9062_IRQ_TICK, 1, "TICK", IORESOURCE_IRQ),
};
static const struct resource da9062_onkey_resources[] = {
DEFINE_RES_NAMED(DA9062_IRQ_ONKEY, 1, "ONKEY", IORESOURCE_IRQ),
};
static const struct resource da9062_gpio_resources[] = {
DEFINE_RES_NAMED(DA9062_IRQ_GPI0, 1, "GPI0", IORESOURCE_IRQ),
DEFINE_RES_NAMED(DA9062_IRQ_GPI1, 1, "GPI1", IORESOURCE_IRQ),
DEFINE_RES_NAMED(DA9062_IRQ_GPI2, 1, "GPI2", IORESOURCE_IRQ),
DEFINE_RES_NAMED(DA9062_IRQ_GPI3, 1, "GPI3", IORESOURCE_IRQ),
DEFINE_RES_NAMED(DA9062_IRQ_GPI4, 1, "GPI4", IORESOURCE_IRQ),
};
static const struct mfd_cell da9062_devs_irq[] = {
MFD_CELL_OF("da9062-core", da9062_core_resources, NULL, 0, 0,
NULL),
MFD_CELL_OF("da9062-regulators", da9062_regulators_resources, NULL, 0, 0,
NULL),
MFD_CELL_OF("da9062-watchdog", da9062_wdt_resources, NULL, 0, 0,
"dlg,da9062-watchdog"),
MFD_CELL_OF("da9062-thermal", da9062_thermal_resources, NULL, 0, 0,
"dlg,da9062-thermal"),
MFD_CELL_OF("da9062-rtc", da9062_rtc_resources, NULL, 0, 0,
"dlg,da9062-rtc"),
MFD_CELL_OF("da9062-onkey", da9062_onkey_resources, NULL, 0, 0,
"dlg,da9062-onkey"),
MFD_CELL_OF("da9062-gpio", da9062_gpio_resources, NULL, 0, 0,
"dlg,da9062-gpio"),
};
static const struct mfd_cell da9062_devs_noirq[] = {
MFD_CELL_OF("da9062-core", NULL, NULL, 0, 0, NULL),
MFD_CELL_OF("da9062-regulators", NULL, NULL, 0, 0, NULL),
MFD_CELL_OF("da9062-watchdog", NULL, NULL, 0, 0, "dlg,da9062-watchdog"),
MFD_CELL_OF("da9062-thermal", NULL, NULL, 0, 0, "dlg,da9062-thermal"),
MFD_CELL_OF("da9062-rtc", NULL, NULL, 0, 0, "dlg,da9062-rtc"),
MFD_CELL_OF("da9062-onkey", NULL, NULL, 0, 0, "dlg,da9062-onkey"),
MFD_CELL_OF("da9062-gpio", NULL, NULL, 0, 0, "dlg,da9062-gpio"),
};
static int da9062_clear_fault_log(struct da9062 *chip)
{
int ret;
int fault_log;
ret = regmap_read(chip->regmap, DA9062AA_FAULT_LOG, &fault_log);
if (ret < 0)
return ret;
if (fault_log) {
if (fault_log & DA9062AA_TWD_ERROR_MASK)
dev_dbg(chip->dev, "Fault log entry detected: TWD_ERROR\n");
if (fault_log & DA9062AA_POR_MASK)
dev_dbg(chip->dev, "Fault log entry detected: POR\n");
if (fault_log & DA9062AA_VDD_FAULT_MASK)
dev_dbg(chip->dev, "Fault log entry detected: VDD_FAULT\n");
if (fault_log & DA9062AA_VDD_START_MASK)
dev_dbg(chip->dev, "Fault log entry detected: VDD_START\n");
if (fault_log & DA9062AA_TEMP_CRIT_MASK)
dev_dbg(chip->dev, "Fault log entry detected: TEMP_CRIT\n");
if (fault_log & DA9062AA_KEY_RESET_MASK)
dev_dbg(chip->dev, "Fault log entry detected: KEY_RESET\n");
if (fault_log & DA9062AA_NSHUTDOWN_MASK)
dev_dbg(chip->dev, "Fault log entry detected: NSHUTDOWN\n");
if (fault_log & DA9062AA_WAIT_SHUT_MASK)
dev_dbg(chip->dev, "Fault log entry detected: WAIT_SHUT\n");
ret = regmap_write(chip->regmap, DA9062AA_FAULT_LOG,
fault_log);
}
return ret;
}
static int da9062_get_device_type(struct da9062 *chip)
{
int device_id, variant_id, variant_mrc, variant_vrc;
char *type;
int ret;
ret = regmap_read(chip->regmap, DA9062AA_DEVICE_ID, &device_id);
if (ret < 0) {
dev_err(chip->dev, "Cannot read chip ID.\n");
return -EIO;
}
if (device_id != DA9062_PMIC_DEVICE_ID) {
dev_err(chip->dev, "Invalid device ID: 0x%02x\n", device_id);
return -ENODEV;
}
ret = regmap_read(chip->regmap, DA9062AA_VARIANT_ID, &variant_id);
if (ret < 0) {
dev_err(chip->dev, "Cannot read chip variant id.\n");
return -EIO;
}
variant_vrc = (variant_id & DA9062AA_VRC_MASK) >> DA9062AA_VRC_SHIFT;
switch (variant_vrc) {
case DA9062_PMIC_VARIANT_VRC_DA9061:
type = "DA9061";
break;
case DA9062_PMIC_VARIANT_VRC_DA9062:
type = "DA9062";
break;
default:
type = "Unknown";
break;
}
dev_info(chip->dev,
"Device detected (device-ID: 0x%02X, var-ID: 0x%02X, %s)\n",
device_id, variant_id, type);
variant_mrc = (variant_id & DA9062AA_MRC_MASK) >> DA9062AA_MRC_SHIFT;
if (variant_mrc < DA9062_PMIC_VARIANT_MRC_AA) {
dev_err(chip->dev,
"Cannot support variant MRC: 0x%02X\n", variant_mrc);
return -ENODEV;
}
return ret;
}
static u32 da9062_configure_irq_type(struct da9062 *chip, int irq, u32 *trigger)
{
u32 irq_type = 0;
struct irq_data *irq_data = irq_get_irq_data(irq);
if (!irq_data) {
dev_err(chip->dev, "Invalid IRQ: %d\n", irq);
return -EINVAL;
}
*trigger = irqd_get_trigger_type(irq_data);
switch (*trigger) {
case IRQ_TYPE_LEVEL_HIGH:
irq_type = DA9062_IRQ_HIGH;
break;
case IRQ_TYPE_LEVEL_LOW:
irq_type = DA9062_IRQ_LOW;
break;
default:
dev_warn(chip->dev, "Unsupported IRQ type: %d\n", *trigger);
return -EINVAL;
}
return regmap_update_bits(chip->regmap, DA9062AA_CONFIG_A,
DA9062AA_IRQ_TYPE_MASK,
irq_type << DA9062AA_IRQ_TYPE_SHIFT);
}
static const struct regmap_range da9061_aa_readable_ranges[] = {
regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_GPIO_OUT3_4),
regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT),
regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_WAIT),
regmap_reg_range(DA9062AA_RESET, DA9062AA_BUCK_ILIM_C),
regmap_reg_range(DA9062AA_BUCK1_CFG, DA9062AA_BUCK3_CFG),
regmap_reg_range(DA9062AA_VBUCK1_A, DA9062AA_VBUCK4_A),
regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
regmap_reg_range(DA9062AA_CONFIG_A, DA9062AA_CONFIG_A),
regmap_reg_range(DA9062AA_VBUCK1_B, DA9062AA_VBUCK4_B),
regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
regmap_reg_range(DA9062AA_INTERFACE, DA9062AA_CONFIG_E),
regmap_reg_range(DA9062AA_CONFIG_G, DA9062AA_CONFIG_K),
regmap_reg_range(DA9062AA_CONFIG_M, DA9062AA_CONFIG_M),
regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19),
regmap_reg_range(DA9062AA_DEVICE_ID, DA9062AA_CONFIG_ID),
};
static const struct regmap_range da9061_aa_writeable_ranges[] = {
regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_PAGE_CON),
regmap_reg_range(DA9062AA_FAULT_LOG, DA9062AA_EVENT_C),
regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_GPIO_OUT3_4),
regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT),
regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_WAIT),
regmap_reg_range(DA9062AA_RESET, DA9062AA_BUCK_ILIM_C),
regmap_reg_range(DA9062AA_BUCK1_CFG, DA9062AA_BUCK3_CFG),
regmap_reg_range(DA9062AA_VBUCK1_A, DA9062AA_VBUCK4_A),
regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
regmap_reg_range(DA9062AA_CONFIG_A, DA9062AA_CONFIG_A),
regmap_reg_range(DA9062AA_VBUCK1_B, DA9062AA_VBUCK4_B),
regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
regmap_reg_range(DA9062AA_CONFIG_J, DA9062AA_CONFIG_J),
regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19),
};
static const struct regmap_range da9061_aa_volatile_ranges[] = {
regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_CONTROL_B),
regmap_reg_range(DA9062AA_CONTROL_E, DA9062AA_CONTROL_F),
regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT),
regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
regmap_reg_range(DA9062AA_SEQ, DA9062AA_SEQ),
};
static const struct regmap_access_table da9061_aa_readable_table = {
.yes_ranges = da9061_aa_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(da9061_aa_readable_ranges),
};
static const struct regmap_access_table da9061_aa_writeable_table = {
.yes_ranges = da9061_aa_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(da9061_aa_writeable_ranges),
};
static const struct regmap_access_table da9061_aa_volatile_table = {
.yes_ranges = da9061_aa_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(da9061_aa_volatile_ranges),
};
static const struct regmap_range_cfg da9061_range_cfg[] = {
{
.range_min = DA9062AA_PAGE_CON,
.range_max = DA9062AA_CONFIG_ID,
.selector_reg = DA9062AA_PAGE_CON,
.selector_mask = 1 << DA9062_I2C_PAGE_SEL_SHIFT,
.selector_shift = DA9062_I2C_PAGE_SEL_SHIFT,
.window_start = 0,
.window_len = 256,
}
};
static struct regmap_config da9061_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.ranges = da9061_range_cfg,
.num_ranges = ARRAY_SIZE(da9061_range_cfg),
.max_register = DA9062AA_CONFIG_ID,
.cache_type = REGCACHE_RBTREE,
.rd_table = &da9061_aa_readable_table,
.wr_table = &da9061_aa_writeable_table,
.volatile_table = &da9061_aa_volatile_table,
};
static const struct regmap_range da9062_aa_readable_ranges[] = {
regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_BUCK4_CONT),
regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_SECOND_D),
regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_BUCK3_CFG),
regmap_reg_range(DA9062AA_VBUCK2_A, DA9062AA_VBUCK4_A),
regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
regmap_reg_range(DA9062AA_VBUCK2_B, DA9062AA_VBUCK4_B),
regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
regmap_reg_range(DA9062AA_BBAT_CONT, DA9062AA_BBAT_CONT),
regmap_reg_range(DA9062AA_INTERFACE, DA9062AA_CONFIG_E),
regmap_reg_range(DA9062AA_CONFIG_G, DA9062AA_CONFIG_K),
regmap_reg_range(DA9062AA_CONFIG_M, DA9062AA_CONFIG_M),
regmap_reg_range(DA9062AA_TRIM_CLDR, DA9062AA_GP_ID_19),
regmap_reg_range(DA9062AA_DEVICE_ID, DA9062AA_CONFIG_ID),
};
static const struct regmap_range da9062_aa_writeable_ranges[] = {
regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_PAGE_CON),
regmap_reg_range(DA9062AA_FAULT_LOG, DA9062AA_EVENT_C),
regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_BUCK4_CONT),
regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_ALARM_Y),
regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_BUCK3_CFG),
regmap_reg_range(DA9062AA_VBUCK2_A, DA9062AA_VBUCK4_A),
regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
regmap_reg_range(DA9062AA_VBUCK2_B, DA9062AA_VBUCK4_B),
regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
regmap_reg_range(DA9062AA_BBAT_CONT, DA9062AA_BBAT_CONT),
regmap_reg_range(DA9062AA_CONFIG_J, DA9062AA_CONFIG_J),
regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19),
};
static const struct regmap_range da9062_aa_volatile_ranges[] = {
regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_CONTROL_B),
regmap_reg_range(DA9062AA_CONTROL_E, DA9062AA_CONTROL_F),
regmap_reg_range(DA9062AA_BUCK2_CONT, DA9062AA_BUCK4_CONT),
regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_SECOND_D),
regmap_reg_range(DA9062AA_SEQ, DA9062AA_SEQ),
regmap_reg_range(DA9062AA_EN_32K, DA9062AA_EN_32K),
};
static const struct regmap_access_table da9062_aa_readable_table = {
.yes_ranges = da9062_aa_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(da9062_aa_readable_ranges),
};
static const struct regmap_access_table da9062_aa_writeable_table = {
.yes_ranges = da9062_aa_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(da9062_aa_writeable_ranges),
};
static const struct regmap_access_table da9062_aa_volatile_table = {
.yes_ranges = da9062_aa_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(da9062_aa_volatile_ranges),
};
static const struct regmap_range_cfg da9062_range_cfg[] = {
{
.range_min = DA9062AA_PAGE_CON,
.range_max = DA9062AA_CONFIG_ID,
.selector_reg = DA9062AA_PAGE_CON,
.selector_mask = 1 << DA9062_I2C_PAGE_SEL_SHIFT,
.selector_shift = DA9062_I2C_PAGE_SEL_SHIFT,
.window_start = 0,
.window_len = 256,
}
};
static struct regmap_config da9062_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.ranges = da9062_range_cfg,
.num_ranges = ARRAY_SIZE(da9062_range_cfg),
.max_register = DA9062AA_CONFIG_ID,
.cache_type = REGCACHE_RBTREE,
.rd_table = &da9062_aa_readable_table,
.wr_table = &da9062_aa_writeable_table,
.volatile_table = &da9062_aa_volatile_table,
};
static const struct of_device_id da9062_dt_ids[] = {
{ .compatible = "dlg,da9061", .data = (void *)COMPAT_TYPE_DA9061, },
{ .compatible = "dlg,da9062", .data = (void *)COMPAT_TYPE_DA9062, },
{ }
};
MODULE_DEVICE_TABLE(of, da9062_dt_ids);
static int da9062_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
struct da9062 *chip;
unsigned int irq_base = 0;
const struct mfd_cell *cell;
const struct regmap_irq_chip *irq_chip;
const struct regmap_config *config;
int cell_num;
u32 trigger_type = 0;
int ret;
chip = devm_kzalloc(&i2c->dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
if (i2c->dev.of_node)
chip->chip_type = (uintptr_t)of_device_get_match_data(&i2c->dev);
else
chip->chip_type = id->driver_data;
i2c_set_clientdata(i2c, chip);
chip->dev = &i2c->dev;
/* Start with a base configuration without IRQ */
switch (chip->chip_type) {
case COMPAT_TYPE_DA9061:
cell = da9061_devs_noirq;
cell_num = ARRAY_SIZE(da9061_devs_noirq);
config = &da9061_regmap_config;
break;
case COMPAT_TYPE_DA9062:
cell = da9062_devs_noirq;
cell_num = ARRAY_SIZE(da9062_devs_noirq);
config = &da9062_regmap_config;
break;
default:
dev_err(chip->dev, "Unrecognised chip type\n");
return -ENODEV;
}
chip->regmap = devm_regmap_init_i2c(i2c, config);
if (IS_ERR(chip->regmap)) {
ret = PTR_ERR(chip->regmap);
dev_err(chip->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
/* If SMBus is not available and only I2C is possible, enter I2C mode */
if (i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C)) {
dev_info(chip->dev, "Entering I2C mode!\n");
ret = regmap_clear_bits(chip->regmap, DA9062AA_CONFIG_J,
DA9062AA_TWOWIRE_TO_MASK);
if (ret < 0) {
dev_err(chip->dev, "Failed to set Two-Wire Bus Mode.\n");
return ret;
}
}
ret = da9062_clear_fault_log(chip);
if (ret < 0)
dev_warn(chip->dev, "Cannot clear fault log\n");
ret = da9062_get_device_type(chip);
if (ret)
return ret;
/* If IRQ is available, reconfigure it accordingly */
if (i2c->irq) {
if (chip->chip_type == COMPAT_TYPE_DA9061) {
cell = da9061_devs_irq;
cell_num = ARRAY_SIZE(da9061_devs_irq);
irq_chip = &da9061_irq_chip;
} else {
cell = da9062_devs_irq;
cell_num = ARRAY_SIZE(da9062_devs_irq);
irq_chip = &da9062_irq_chip;
}
ret = da9062_configure_irq_type(chip, i2c->irq, &trigger_type);
if (ret < 0) {
dev_err(chip->dev, "Failed to configure IRQ type\n");
return ret;
}
ret = regmap_add_irq_chip(chip->regmap, i2c->irq,
trigger_type | IRQF_SHARED | IRQF_ONESHOT,
-1, irq_chip, &chip->regmap_irq);
if (ret) {
dev_err(chip->dev, "Failed to request IRQ %d: %d\n",
i2c->irq, ret);
return ret;
}
irq_base = regmap_irq_chip_get_base(chip->regmap_irq);
}
ret = mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE, cell,
cell_num, NULL, irq_base,
NULL);
if (ret) {
dev_err(chip->dev, "Cannot register child devices\n");
if (i2c->irq)
regmap_del_irq_chip(i2c->irq, chip->regmap_irq);
return ret;
}
return ret;
}
static void da9062_i2c_remove(struct i2c_client *i2c)
{
struct da9062 *chip = i2c_get_clientdata(i2c);
mfd_remove_devices(chip->dev);
regmap_del_irq_chip(i2c->irq, chip->regmap_irq);
}
static const struct i2c_device_id da9062_i2c_id[] = {
{ "da9061", COMPAT_TYPE_DA9061 },
{ "da9062", COMPAT_TYPE_DA9062 },
{ },
};
MODULE_DEVICE_TABLE(i2c, da9062_i2c_id);
static struct i2c_driver da9062_i2c_driver = {
.driver = {
.name = "da9062",
.of_match_table = da9062_dt_ids,
},
.probe = da9062_i2c_probe,
.remove = da9062_i2c_remove,
.id_table = da9062_i2c_id,
};
module_i2c_driver(da9062_i2c_driver);
MODULE_DESCRIPTION("Core device driver for Dialog DA9061 and DA9062");
MODULE_AUTHOR("Steve Twiss <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/da9062-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ST Microelectronics MFD: stmpe's i2c client specific driver
*
* Copyright (C) ST-Ericsson SA 2010
* Copyright (C) ST Microelectronics SA 2011
*
* Author: Rabin Vincent <[email protected]> for ST-Ericsson
* Author: Viresh Kumar <[email protected]> for ST Microelectronics
*/
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/of_device.h>
#include "stmpe.h"
static int i2c_reg_read(struct stmpe *stmpe, u8 reg)
{
struct i2c_client *i2c = stmpe->client;
return i2c_smbus_read_byte_data(i2c, reg);
}
static int i2c_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
{
struct i2c_client *i2c = stmpe->client;
return i2c_smbus_write_byte_data(i2c, reg, val);
}
static int i2c_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values)
{
struct i2c_client *i2c = stmpe->client;
return i2c_smbus_read_i2c_block_data(i2c, reg, length, values);
}
static int i2c_block_write(struct stmpe *stmpe, u8 reg, u8 length,
const u8 *values)
{
struct i2c_client *i2c = stmpe->client;
return i2c_smbus_write_i2c_block_data(i2c, reg, length, values);
}
static struct stmpe_client_info i2c_ci = {
.read_byte = i2c_reg_read,
.write_byte = i2c_reg_write,
.read_block = i2c_block_read,
.write_block = i2c_block_write,
};
static const struct of_device_id stmpe_of_match[] = {
{ .compatible = "st,stmpe610", .data = (void *)STMPE610, },
{ .compatible = "st,stmpe801", .data = (void *)STMPE801, },
{ .compatible = "st,stmpe811", .data = (void *)STMPE811, },
{ .compatible = "st,stmpe1600", .data = (void *)STMPE1600, },
{ .compatible = "st,stmpe1601", .data = (void *)STMPE1601, },
{ .compatible = "st,stmpe1801", .data = (void *)STMPE1801, },
{ .compatible = "st,stmpe2401", .data = (void *)STMPE2401, },
{ .compatible = "st,stmpe2403", .data = (void *)STMPE2403, },
{},
};
MODULE_DEVICE_TABLE(of, stmpe_of_match);
static int
stmpe_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
enum stmpe_partnum partnum;
const struct of_device_id *of_id;
i2c_ci.data = (void *)id;
i2c_ci.irq = i2c->irq;
i2c_ci.client = i2c;
i2c_ci.dev = &i2c->dev;
of_id = of_match_device(stmpe_of_match, &i2c->dev);
if (!of_id) {
/*
* This happens when the I2C ID matches the node name
* but no real compatible string has been given.
*/
dev_info(&i2c->dev, "matching on node name, compatible is preferred\n");
partnum = id->driver_data;
} else
partnum = (uintptr_t)of_id->data;
return stmpe_probe(&i2c_ci, partnum);
}
static void stmpe_i2c_remove(struct i2c_client *i2c)
{
struct stmpe *stmpe = dev_get_drvdata(&i2c->dev);
stmpe_remove(stmpe);
}
static const struct i2c_device_id stmpe_i2c_id[] = {
{ "stmpe610", STMPE610 },
{ "stmpe801", STMPE801 },
{ "stmpe811", STMPE811 },
{ "stmpe1600", STMPE1600 },
{ "stmpe1601", STMPE1601 },
{ "stmpe1801", STMPE1801 },
{ "stmpe2401", STMPE2401 },
{ "stmpe2403", STMPE2403 },
{ }
};
MODULE_DEVICE_TABLE(i2c, stmpe_i2c_id);
static struct i2c_driver stmpe_i2c_driver = {
.driver = {
.name = "stmpe-i2c",
.pm = pm_sleep_ptr(&stmpe_dev_pm_ops),
.of_match_table = stmpe_of_match,
},
.probe = stmpe_i2c_probe,
.remove = stmpe_i2c_remove,
.id_table = stmpe_i2c_id,
};
static int __init stmpe_init(void)
{
return i2c_add_driver(&stmpe_i2c_driver);
}
subsys_initcall(stmpe_init);
static void __exit stmpe_exit(void)
{
i2c_del_driver(&stmpe_i2c_driver);
}
module_exit(stmpe_exit);
MODULE_DESCRIPTION("STMPE MFD I2C Interface Driver");
MODULE_AUTHOR("Rabin Vincent <[email protected]>");
| linux-master | drivers/mfd/stmpe-i2c.c |
// SPDX-License-Identifier: GPL-2.0+
//
// max14577.c - mfd core driver for the Maxim 14577/77836
//
// Copyright (C) 2014 Samsung Electronics
// Chanwoo Choi <[email protected]>
// Krzysztof Kozlowski <[email protected]>
//
// This driver is based on max8997.c
#include <linux/err.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/of_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/max14577.h>
#include <linux/mfd/max14577-private.h>
/*
* Table of valid charger currents for different Maxim chipsets.
* It is placed here because it is used by both charger and regulator driver.
*/
const struct maxim_charger_current maxim_charger_currents[] = {
[MAXIM_DEVICE_TYPE_UNKNOWN] = { 0, 0, 0, 0 },
[MAXIM_DEVICE_TYPE_MAX14577] = {
.min = MAX14577_CHARGER_CURRENT_LIMIT_MIN,
.high_start = MAX14577_CHARGER_CURRENT_LIMIT_HIGH_START,
.high_step = MAX14577_CHARGER_CURRENT_LIMIT_HIGH_STEP,
.max = MAX14577_CHARGER_CURRENT_LIMIT_MAX,
},
[MAXIM_DEVICE_TYPE_MAX77836] = {
.min = MAX77836_CHARGER_CURRENT_LIMIT_MIN,
.high_start = MAX77836_CHARGER_CURRENT_LIMIT_HIGH_START,
.high_step = MAX77836_CHARGER_CURRENT_LIMIT_HIGH_STEP,
.max = MAX77836_CHARGER_CURRENT_LIMIT_MAX,
},
};
EXPORT_SYMBOL_GPL(maxim_charger_currents);
/*
* maxim_charger_calc_reg_current - Calculate register value for current
* @limits: constraints for charger, matching the MBCICHWRC register
* @min_ua: minimal requested current, micro Amps
* @max_ua: maximum requested current, micro Amps
* @dst: destination to store calculated register value
*
* Calculates the value of MBCICHWRC (Fast Battery Charge Current) register
* for given current and stores it under pointed 'dst'. The stored value
* combines low bit (MBCICHWRCL) and high bits (MBCICHWRCH). It is also
* properly shifted.
*
* The calculated register value matches the current which:
* - is always between <limits.min, limits.max>;
* - is always less or equal to max_ua;
* - is the highest possible value;
* - may be lower than min_ua.
*
* On success returns 0. On error returns -EINVAL (requested min/max current
* is outside of given charger limits) and 'dst' is not set.
*/
int maxim_charger_calc_reg_current(const struct maxim_charger_current *limits,
unsigned int min_ua, unsigned int max_ua, u8 *dst)
{
unsigned int current_bits;
if (min_ua > max_ua)
return -EINVAL;
if (min_ua > limits->max || max_ua < limits->min)
return -EINVAL;
if (max_ua < limits->high_start) {
/*
* Less than high_start, so set the minimal current
* (turn Low Bit off, 0 as high bits).
*/
*dst = 0x0;
return 0;
}
/* max_ua is in range: <high_start, infinite>, cut it to limits.max */
max_ua = min(limits->max, max_ua);
max_ua -= limits->high_start;
/*
* There is no risk of overflow 'max_ua' here because:
* - max_ua >= limits.high_start
* - BUILD_BUG checks that 'limits' are: max >= high_start + high_step
*/
current_bits = max_ua / limits->high_step;
/* Turn Low Bit on (use range <limits.high_start, limits.max>) ... */
*dst = 0x1 << CHGCTRL4_MBCICHWRCL_SHIFT;
/* and set proper High Bits */
*dst |= current_bits << CHGCTRL4_MBCICHWRCH_SHIFT;
return 0;
}
EXPORT_SYMBOL_GPL(maxim_charger_calc_reg_current);
static const struct mfd_cell max14577_devs[] = {
{
.name = "max14577-muic",
.of_compatible = "maxim,max14577-muic",
},
{
.name = "max14577-regulator",
.of_compatible = "maxim,max14577-regulator",
},
{
.name = "max14577-charger",
.of_compatible = "maxim,max14577-charger",
},
};
static const struct mfd_cell max77836_devs[] = {
{
.name = "max77836-muic",
.of_compatible = "maxim,max77836-muic",
},
{
.name = "max77836-regulator",
.of_compatible = "maxim,max77836-regulator",
},
{
.name = "max77836-charger",
.of_compatible = "maxim,max77836-charger",
},
{
.name = "max77836-battery",
.of_compatible = "maxim,max77836-battery",
},
};
static const struct of_device_id max14577_dt_match[] = {
{
.compatible = "maxim,max14577",
.data = (void *)MAXIM_DEVICE_TYPE_MAX14577,
},
{
.compatible = "maxim,max77836",
.data = (void *)MAXIM_DEVICE_TYPE_MAX77836,
},
{},
};
static bool max14577_muic_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX14577_REG_INT1 ... MAX14577_REG_STATUS3:
return true;
default:
break;
}
return false;
}
static bool max77836_muic_volatile_reg(struct device *dev, unsigned int reg)
{
/* Any max14577 volatile registers are also max77836 volatile. */
if (max14577_muic_volatile_reg(dev, reg))
return true;
switch (reg) {
case MAX77836_FG_REG_VCELL_MSB ... MAX77836_FG_REG_SOC_LSB:
case MAX77836_FG_REG_CRATE_MSB ... MAX77836_FG_REG_CRATE_LSB:
case MAX77836_FG_REG_STATUS_H ... MAX77836_FG_REG_STATUS_L:
case MAX77836_PMIC_REG_INTSRC:
case MAX77836_PMIC_REG_TOPSYS_INT:
case MAX77836_PMIC_REG_TOPSYS_STAT:
return true;
default:
break;
}
return false;
}
static const struct regmap_config max14577_muic_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = max14577_muic_volatile_reg,
.max_register = MAX14577_REG_END,
};
static const struct regmap_config max77836_pmic_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = max77836_muic_volatile_reg,
.max_register = MAX77836_PMIC_REG_END,
};
static const struct regmap_irq max14577_irqs[] = {
/* INT1 interrupts */
{ .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
{ .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
{ .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
/* INT2 interrupts */
{ .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
{ .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
{ .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
{ .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
{ .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
/* INT3 interrupts */
{ .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
{ .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },
{ .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, },
{ .reg_offset = 2, .mask = MAX14577_INT3_MBCCHGERR_MASK, },
};
static const struct regmap_irq_chip max14577_irq_chip = {
.name = "max14577",
.status_base = MAX14577_REG_INT1,
.unmask_base = MAX14577_REG_INTMASK1,
.num_regs = 3,
.irqs = max14577_irqs,
.num_irqs = ARRAY_SIZE(max14577_irqs),
};
static const struct regmap_irq max77836_muic_irqs[] = {
/* INT1 interrupts */
{ .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
{ .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
{ .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
{ .reg_offset = 0, .mask = MAX77836_INT1_ADC1K_MASK, },
/* INT2 interrupts */
{ .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
{ .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
{ .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
{ .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
{ .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
{ .reg_offset = 1, .mask = MAX77836_INT2_VIDRM_MASK, },
/* INT3 interrupts */
{ .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
{ .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },
{ .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, },
{ .reg_offset = 2, .mask = MAX14577_INT3_MBCCHGERR_MASK, },
};
static const struct regmap_irq_chip max77836_muic_irq_chip = {
.name = "max77836-muic",
.status_base = MAX14577_REG_INT1,
.unmask_base = MAX14577_REG_INTMASK1,
.num_regs = 3,
.irqs = max77836_muic_irqs,
.num_irqs = ARRAY_SIZE(max77836_muic_irqs),
};
static const struct regmap_irq max77836_pmic_irqs[] = {
{ .reg_offset = 0, .mask = MAX77836_TOPSYS_INT_T120C_MASK, },
{ .reg_offset = 0, .mask = MAX77836_TOPSYS_INT_T140C_MASK, },
};
static const struct regmap_irq_chip max77836_pmic_irq_chip = {
.name = "max77836-pmic",
.status_base = MAX77836_PMIC_REG_TOPSYS_INT,
.mask_base = MAX77836_PMIC_REG_TOPSYS_INT_MASK,
.num_regs = 1,
.irqs = max77836_pmic_irqs,
.num_irqs = ARRAY_SIZE(max77836_pmic_irqs),
};
static void max14577_print_dev_type(struct max14577 *max14577)
{
u8 reg_data, vendor_id, device_id;
int ret;
ret = max14577_read_reg(max14577->regmap, MAX14577_REG_DEVICEID,
®_data);
if (ret) {
dev_err(max14577->dev,
"Failed to read DEVICEID register: %d\n", ret);
return;
}
vendor_id = ((reg_data & DEVID_VENDORID_MASK) >>
DEVID_VENDORID_SHIFT);
device_id = ((reg_data & DEVID_DEVICEID_MASK) >>
DEVID_DEVICEID_SHIFT);
dev_info(max14577->dev, "Device type: %u (ID: 0x%x, vendor: 0x%x)\n",
max14577->dev_type, device_id, vendor_id);
}
/*
* Max77836 specific initialization code for driver probe.
* Adds new I2C dummy device, regmap and regmap IRQ chip.
* Unmasks Interrupt Source register.
*
* On success returns 0.
* On failure returns errno and reverts any changes done so far (e.g. remove
* I2C dummy device), except masking the INT SRC register.
*/
static int max77836_init(struct max14577 *max14577)
{
int ret;
u8 intsrc_mask;
max14577->i2c_pmic = i2c_new_dummy_device(max14577->i2c->adapter,
I2C_ADDR_PMIC);
if (IS_ERR(max14577->i2c_pmic)) {
dev_err(max14577->dev, "Failed to register PMIC I2C device\n");
return PTR_ERR(max14577->i2c_pmic);
}
i2c_set_clientdata(max14577->i2c_pmic, max14577);
max14577->regmap_pmic = devm_regmap_init_i2c(max14577->i2c_pmic,
&max77836_pmic_regmap_config);
if (IS_ERR(max14577->regmap_pmic)) {
ret = PTR_ERR(max14577->regmap_pmic);
dev_err(max14577->dev, "Failed to allocate PMIC register map: %d\n",
ret);
goto err;
}
/* Un-mask MAX77836 Interrupt Source register */
ret = max14577_read_reg(max14577->regmap_pmic,
MAX77836_PMIC_REG_INTSRC_MASK, &intsrc_mask);
if (ret < 0) {
dev_err(max14577->dev, "Failed to read PMIC register\n");
goto err;
}
intsrc_mask &= ~(MAX77836_INTSRC_MASK_TOP_INT_MASK);
intsrc_mask &= ~(MAX77836_INTSRC_MASK_MUIC_CHG_INT_MASK);
ret = max14577_write_reg(max14577->regmap_pmic,
MAX77836_PMIC_REG_INTSRC_MASK, intsrc_mask);
if (ret < 0) {
dev_err(max14577->dev, "Failed to write PMIC register\n");
goto err;
}
ret = regmap_add_irq_chip(max14577->regmap_pmic, max14577->irq,
IRQF_ONESHOT | IRQF_SHARED,
0, &max77836_pmic_irq_chip,
&max14577->irq_data_pmic);
if (ret != 0) {
dev_err(max14577->dev, "Failed to request PMIC IRQ %d: %d\n",
max14577->irq, ret);
goto err;
}
return 0;
err:
i2c_unregister_device(max14577->i2c_pmic);
return ret;
}
/*
* Max77836 specific de-initialization code for driver remove.
*/
static void max77836_remove(struct max14577 *max14577)
{
regmap_del_irq_chip(max14577->irq, max14577->irq_data_pmic);
i2c_unregister_device(max14577->i2c_pmic);
}
static int max14577_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
struct max14577 *max14577;
struct max14577_platform_data *pdata = dev_get_platdata(&i2c->dev);
struct device_node *np = i2c->dev.of_node;
int ret = 0;
const struct regmap_irq_chip *irq_chip;
const struct mfd_cell *mfd_devs;
unsigned int mfd_devs_size;
int irq_flags;
if (np) {
pdata = devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
i2c->dev.platform_data = pdata;
}
if (!pdata) {
dev_err(&i2c->dev, "No platform data found.\n");
return -EINVAL;
}
max14577 = devm_kzalloc(&i2c->dev, sizeof(*max14577), GFP_KERNEL);
if (!max14577)
return -ENOMEM;
i2c_set_clientdata(i2c, max14577);
max14577->dev = &i2c->dev;
max14577->i2c = i2c;
max14577->irq = i2c->irq;
max14577->regmap = devm_regmap_init_i2c(i2c,
&max14577_muic_regmap_config);
if (IS_ERR(max14577->regmap)) {
ret = PTR_ERR(max14577->regmap);
dev_err(max14577->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
if (np) {
const struct of_device_id *of_id;
of_id = of_match_device(max14577_dt_match, &i2c->dev);
if (of_id)
max14577->dev_type = (uintptr_t)of_id->data;
} else {
max14577->dev_type = id->driver_data;
}
max14577_print_dev_type(max14577);
switch (max14577->dev_type) {
case MAXIM_DEVICE_TYPE_MAX77836:
irq_chip = &max77836_muic_irq_chip;
mfd_devs = max77836_devs;
mfd_devs_size = ARRAY_SIZE(max77836_devs);
irq_flags = IRQF_ONESHOT | IRQF_SHARED;
break;
case MAXIM_DEVICE_TYPE_MAX14577:
default:
irq_chip = &max14577_irq_chip;
mfd_devs = max14577_devs;
mfd_devs_size = ARRAY_SIZE(max14577_devs);
irq_flags = IRQF_ONESHOT;
break;
}
ret = regmap_add_irq_chip(max14577->regmap, max14577->irq,
irq_flags, 0, irq_chip,
&max14577->irq_data);
if (ret != 0) {
dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
max14577->irq, ret);
return ret;
}
/* Max77836 specific initialization code (additional regmap) */
if (max14577->dev_type == MAXIM_DEVICE_TYPE_MAX77836) {
ret = max77836_init(max14577);
if (ret < 0)
goto err_max77836;
}
ret = mfd_add_devices(max14577->dev, -1, mfd_devs,
mfd_devs_size, NULL, 0, NULL);
if (ret < 0)
goto err_mfd;
device_init_wakeup(max14577->dev, 1);
return 0;
err_mfd:
if (max14577->dev_type == MAXIM_DEVICE_TYPE_MAX77836)
max77836_remove(max14577);
err_max77836:
regmap_del_irq_chip(max14577->irq, max14577->irq_data);
return ret;
}
static void max14577_i2c_remove(struct i2c_client *i2c)
{
struct max14577 *max14577 = i2c_get_clientdata(i2c);
mfd_remove_devices(max14577->dev);
regmap_del_irq_chip(max14577->irq, max14577->irq_data);
if (max14577->dev_type == MAXIM_DEVICE_TYPE_MAX77836)
max77836_remove(max14577);
}
static const struct i2c_device_id max14577_i2c_id[] = {
{ "max14577", MAXIM_DEVICE_TYPE_MAX14577, },
{ "max77836", MAXIM_DEVICE_TYPE_MAX77836, },
{ }
};
MODULE_DEVICE_TABLE(i2c, max14577_i2c_id);
static int max14577_suspend(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct max14577 *max14577 = i2c_get_clientdata(i2c);
if (device_may_wakeup(dev))
enable_irq_wake(max14577->irq);
/*
* MUIC IRQ must be disabled during suspend because if it happens
* while suspended it will be handled before resuming I2C.
*
* When device is woken up from suspend (e.g. by ADC change),
* an interrupt occurs before resuming I2C bus controller.
* Interrupt handler tries to read registers but this read
* will fail because I2C is still suspended.
*/
disable_irq(max14577->irq);
return 0;
}
static int max14577_resume(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct max14577 *max14577 = i2c_get_clientdata(i2c);
if (device_may_wakeup(dev))
disable_irq_wake(max14577->irq);
enable_irq(max14577->irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(max14577_pm, max14577_suspend, max14577_resume);
static struct i2c_driver max14577_i2c_driver = {
.driver = {
.name = "max14577",
.pm = pm_sleep_ptr(&max14577_pm),
.of_match_table = max14577_dt_match,
},
.probe = max14577_i2c_probe,
.remove = max14577_i2c_remove,
.id_table = max14577_i2c_id,
};
static int __init max14577_i2c_init(void)
{
BUILD_BUG_ON(ARRAY_SIZE(max14577_i2c_id) != MAXIM_DEVICE_TYPE_NUM);
BUILD_BUG_ON(ARRAY_SIZE(max14577_dt_match) != MAXIM_DEVICE_TYPE_NUM);
/* Valid charger current values must be provided for each chipset */
BUILD_BUG_ON(ARRAY_SIZE(maxim_charger_currents) != MAXIM_DEVICE_TYPE_NUM);
/* Check for valid values for charger */
BUILD_BUG_ON(MAX14577_CHARGER_CURRENT_LIMIT_HIGH_START +
MAX14577_CHARGER_CURRENT_LIMIT_HIGH_STEP * 0xf !=
MAX14577_CHARGER_CURRENT_LIMIT_MAX);
BUILD_BUG_ON(MAX14577_CHARGER_CURRENT_LIMIT_HIGH_STEP == 0);
BUILD_BUG_ON(MAX77836_CHARGER_CURRENT_LIMIT_HIGH_START +
MAX77836_CHARGER_CURRENT_LIMIT_HIGH_STEP * 0xf !=
MAX77836_CHARGER_CURRENT_LIMIT_MAX);
BUILD_BUG_ON(MAX77836_CHARGER_CURRENT_LIMIT_HIGH_STEP == 0);
return i2c_add_driver(&max14577_i2c_driver);
}
module_init(max14577_i2c_init);
static void __exit max14577_i2c_exit(void)
{
i2c_del_driver(&max14577_i2c_driver);
}
module_exit(max14577_i2c_exit);
MODULE_AUTHOR("Chanwoo Choi <[email protected]>, Krzysztof Kozlowski <[email protected]>");
MODULE_DESCRIPTION("Maxim 14577/77836 multi-function core driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/max14577.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Base driver for Maxim MAX8925
*
* Copyright (C) 2009-2010 Marvell International Ltd.
* Haojian Zhuang <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/platform_device.h>
#include <linux/regulator/machine.h>
#include <linux/mfd/core.h>
#include <linux/mfd/max8925.h>
#include <linux/of.h>
static const struct resource bk_resources[] = {
{ 0x84, 0x84, "mode control", IORESOURCE_REG, },
{ 0x85, 0x85, "control", IORESOURCE_REG, },
};
static struct mfd_cell bk_devs[] = {
{
.name = "max8925-backlight",
.num_resources = ARRAY_SIZE(bk_resources),
.resources = &bk_resources[0],
.id = -1,
},
};
static const struct resource touch_resources[] = {
{
.name = "max8925-tsc",
.start = MAX8925_TSC_IRQ,
.end = MAX8925_ADC_RES_END,
.flags = IORESOURCE_REG,
},
};
static const struct mfd_cell touch_devs[] = {
{
.name = "max8925-touch",
.num_resources = 1,
.resources = &touch_resources[0],
.id = -1,
},
};
static const struct resource power_supply_resources[] = {
{
.name = "max8925-power",
.start = MAX8925_CHG_IRQ1,
.end = MAX8925_CHG_IRQ1_MASK,
.flags = IORESOURCE_REG,
},
};
static const struct mfd_cell power_devs[] = {
{
.name = "max8925-power",
.num_resources = 1,
.resources = &power_supply_resources[0],
.id = -1,
},
};
static const struct resource rtc_resources[] = {
{
.name = "max8925-rtc",
.start = MAX8925_IRQ_RTC_ALARM0,
.end = MAX8925_IRQ_RTC_ALARM0,
.flags = IORESOURCE_IRQ,
},
};
static const struct mfd_cell rtc_devs[] = {
{
.name = "max8925-rtc",
.num_resources = 1,
.resources = &rtc_resources[0],
.id = -1,
},
};
static const struct resource onkey_resources[] = {
{
.name = "max8925-onkey",
.start = MAX8925_IRQ_GPM_SW_R,
.end = MAX8925_IRQ_GPM_SW_R,
.flags = IORESOURCE_IRQ,
}, {
.name = "max8925-onkey",
.start = MAX8925_IRQ_GPM_SW_F,
.end = MAX8925_IRQ_GPM_SW_F,
.flags = IORESOURCE_IRQ,
},
};
static const struct mfd_cell onkey_devs[] = {
{
.name = "max8925-onkey",
.num_resources = 2,
.resources = &onkey_resources[0],
.id = -1,
},
};
static const struct resource sd1_resources[] = {
{0x06, 0x06, "sdv", IORESOURCE_REG, },
};
static const struct resource sd2_resources[] = {
{0x09, 0x09, "sdv", IORESOURCE_REG, },
};
static const struct resource sd3_resources[] = {
{0x0c, 0x0c, "sdv", IORESOURCE_REG, },
};
static const struct resource ldo1_resources[] = {
{0x1a, 0x1a, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo2_resources[] = {
{0x1e, 0x1e, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo3_resources[] = {
{0x22, 0x22, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo4_resources[] = {
{0x26, 0x26, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo5_resources[] = {
{0x2a, 0x2a, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo6_resources[] = {
{0x2e, 0x2e, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo7_resources[] = {
{0x32, 0x32, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo8_resources[] = {
{0x36, 0x36, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo9_resources[] = {
{0x3a, 0x3a, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo10_resources[] = {
{0x3e, 0x3e, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo11_resources[] = {
{0x42, 0x42, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo12_resources[] = {
{0x46, 0x46, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo13_resources[] = {
{0x4a, 0x4a, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo14_resources[] = {
{0x4e, 0x4e, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo15_resources[] = {
{0x52, 0x52, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo16_resources[] = {
{0x12, 0x12, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo17_resources[] = {
{0x16, 0x16, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo18_resources[] = {
{0x74, 0x74, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo19_resources[] = {
{0x5e, 0x5e, "ldov", IORESOURCE_REG, },
};
static const struct resource ldo20_resources[] = {
{0x9e, 0x9e, "ldov", IORESOURCE_REG, },
};
static struct mfd_cell reg_devs[] = {
{
.name = "max8925-regulator",
.id = 0,
.num_resources = ARRAY_SIZE(sd1_resources),
.resources = sd1_resources,
}, {
.name = "max8925-regulator",
.id = 1,
.num_resources = ARRAY_SIZE(sd2_resources),
.resources = sd2_resources,
}, {
.name = "max8925-regulator",
.id = 2,
.num_resources = ARRAY_SIZE(sd3_resources),
.resources = sd3_resources,
}, {
.name = "max8925-regulator",
.id = 3,
.num_resources = ARRAY_SIZE(ldo1_resources),
.resources = ldo1_resources,
}, {
.name = "max8925-regulator",
.id = 4,
.num_resources = ARRAY_SIZE(ldo2_resources),
.resources = ldo2_resources,
}, {
.name = "max8925-regulator",
.id = 5,
.num_resources = ARRAY_SIZE(ldo3_resources),
.resources = ldo3_resources,
}, {
.name = "max8925-regulator",
.id = 6,
.num_resources = ARRAY_SIZE(ldo4_resources),
.resources = ldo4_resources,
}, {
.name = "max8925-regulator",
.id = 7,
.num_resources = ARRAY_SIZE(ldo5_resources),
.resources = ldo5_resources,
}, {
.name = "max8925-regulator",
.id = 8,
.num_resources = ARRAY_SIZE(ldo6_resources),
.resources = ldo6_resources,
}, {
.name = "max8925-regulator",
.id = 9,
.num_resources = ARRAY_SIZE(ldo7_resources),
.resources = ldo7_resources,
}, {
.name = "max8925-regulator",
.id = 10,
.num_resources = ARRAY_SIZE(ldo8_resources),
.resources = ldo8_resources,
}, {
.name = "max8925-regulator",
.id = 11,
.num_resources = ARRAY_SIZE(ldo9_resources),
.resources = ldo9_resources,
}, {
.name = "max8925-regulator",
.id = 12,
.num_resources = ARRAY_SIZE(ldo10_resources),
.resources = ldo10_resources,
}, {
.name = "max8925-regulator",
.id = 13,
.num_resources = ARRAY_SIZE(ldo11_resources),
.resources = ldo11_resources,
}, {
.name = "max8925-regulator",
.id = 14,
.num_resources = ARRAY_SIZE(ldo12_resources),
.resources = ldo12_resources,
}, {
.name = "max8925-regulator",
.id = 15,
.num_resources = ARRAY_SIZE(ldo13_resources),
.resources = ldo13_resources,
}, {
.name = "max8925-regulator",
.id = 16,
.num_resources = ARRAY_SIZE(ldo14_resources),
.resources = ldo14_resources,
}, {
.name = "max8925-regulator",
.id = 17,
.num_resources = ARRAY_SIZE(ldo15_resources),
.resources = ldo15_resources,
}, {
.name = "max8925-regulator",
.id = 18,
.num_resources = ARRAY_SIZE(ldo16_resources),
.resources = ldo16_resources,
}, {
.name = "max8925-regulator",
.id = 19,
.num_resources = ARRAY_SIZE(ldo17_resources),
.resources = ldo17_resources,
}, {
.name = "max8925-regulator",
.id = 20,
.num_resources = ARRAY_SIZE(ldo18_resources),
.resources = ldo18_resources,
}, {
.name = "max8925-regulator",
.id = 21,
.num_resources = ARRAY_SIZE(ldo19_resources),
.resources = ldo19_resources,
}, {
.name = "max8925-regulator",
.id = 22,
.num_resources = ARRAY_SIZE(ldo20_resources),
.resources = ldo20_resources,
},
};
enum {
FLAGS_ADC = 1, /* register in ADC component */
FLAGS_RTC, /* register in RTC component */
};
struct max8925_irq_data {
int reg;
int mask_reg;
int enable; /* enable or not */
int offs; /* bit offset in mask register */
int flags;
int tsc_irq;
};
static struct max8925_irq_data max8925_irqs[] = {
[MAX8925_IRQ_VCHG_DC_OVP] = {
.reg = MAX8925_CHG_IRQ1,
.mask_reg = MAX8925_CHG_IRQ1_MASK,
.offs = 1 << 0,
},
[MAX8925_IRQ_VCHG_DC_F] = {
.reg = MAX8925_CHG_IRQ1,
.mask_reg = MAX8925_CHG_IRQ1_MASK,
.offs = 1 << 1,
},
[MAX8925_IRQ_VCHG_DC_R] = {
.reg = MAX8925_CHG_IRQ1,
.mask_reg = MAX8925_CHG_IRQ1_MASK,
.offs = 1 << 2,
},
[MAX8925_IRQ_VCHG_THM_OK_R] = {
.reg = MAX8925_CHG_IRQ2,
.mask_reg = MAX8925_CHG_IRQ2_MASK,
.offs = 1 << 0,
},
[MAX8925_IRQ_VCHG_THM_OK_F] = {
.reg = MAX8925_CHG_IRQ2,
.mask_reg = MAX8925_CHG_IRQ2_MASK,
.offs = 1 << 1,
},
[MAX8925_IRQ_VCHG_SYSLOW_F] = {
.reg = MAX8925_CHG_IRQ2,
.mask_reg = MAX8925_CHG_IRQ2_MASK,
.offs = 1 << 2,
},
[MAX8925_IRQ_VCHG_SYSLOW_R] = {
.reg = MAX8925_CHG_IRQ2,
.mask_reg = MAX8925_CHG_IRQ2_MASK,
.offs = 1 << 3,
},
[MAX8925_IRQ_VCHG_RST] = {
.reg = MAX8925_CHG_IRQ2,
.mask_reg = MAX8925_CHG_IRQ2_MASK,
.offs = 1 << 4,
},
[MAX8925_IRQ_VCHG_DONE] = {
.reg = MAX8925_CHG_IRQ2,
.mask_reg = MAX8925_CHG_IRQ2_MASK,
.offs = 1 << 5,
},
[MAX8925_IRQ_VCHG_TOPOFF] = {
.reg = MAX8925_CHG_IRQ2,
.mask_reg = MAX8925_CHG_IRQ2_MASK,
.offs = 1 << 6,
},
[MAX8925_IRQ_VCHG_TMR_FAULT] = {
.reg = MAX8925_CHG_IRQ2,
.mask_reg = MAX8925_CHG_IRQ2_MASK,
.offs = 1 << 7,
},
[MAX8925_IRQ_GPM_RSTIN] = {
.reg = MAX8925_ON_OFF_IRQ1,
.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
.offs = 1 << 0,
},
[MAX8925_IRQ_GPM_MPL] = {
.reg = MAX8925_ON_OFF_IRQ1,
.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
.offs = 1 << 1,
},
[MAX8925_IRQ_GPM_SW_3SEC] = {
.reg = MAX8925_ON_OFF_IRQ1,
.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
.offs = 1 << 2,
},
[MAX8925_IRQ_GPM_EXTON_F] = {
.reg = MAX8925_ON_OFF_IRQ1,
.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
.offs = 1 << 3,
},
[MAX8925_IRQ_GPM_EXTON_R] = {
.reg = MAX8925_ON_OFF_IRQ1,
.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
.offs = 1 << 4,
},
[MAX8925_IRQ_GPM_SW_1SEC] = {
.reg = MAX8925_ON_OFF_IRQ1,
.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
.offs = 1 << 5,
},
[MAX8925_IRQ_GPM_SW_F] = {
.reg = MAX8925_ON_OFF_IRQ1,
.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
.offs = 1 << 6,
},
[MAX8925_IRQ_GPM_SW_R] = {
.reg = MAX8925_ON_OFF_IRQ1,
.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
.offs = 1 << 7,
},
[MAX8925_IRQ_GPM_SYSCKEN_F] = {
.reg = MAX8925_ON_OFF_IRQ2,
.mask_reg = MAX8925_ON_OFF_IRQ2_MASK,
.offs = 1 << 0,
},
[MAX8925_IRQ_GPM_SYSCKEN_R] = {
.reg = MAX8925_ON_OFF_IRQ2,
.mask_reg = MAX8925_ON_OFF_IRQ2_MASK,
.offs = 1 << 1,
},
[MAX8925_IRQ_RTC_ALARM1] = {
.reg = MAX8925_RTC_IRQ,
.mask_reg = MAX8925_RTC_IRQ_MASK,
.offs = 1 << 2,
.flags = FLAGS_RTC,
},
[MAX8925_IRQ_RTC_ALARM0] = {
.reg = MAX8925_RTC_IRQ,
.mask_reg = MAX8925_RTC_IRQ_MASK,
.offs = 1 << 3,
.flags = FLAGS_RTC,
},
[MAX8925_IRQ_TSC_STICK] = {
.reg = MAX8925_TSC_IRQ,
.mask_reg = MAX8925_TSC_IRQ_MASK,
.offs = 1 << 0,
.flags = FLAGS_ADC,
.tsc_irq = 1,
},
[MAX8925_IRQ_TSC_NSTICK] = {
.reg = MAX8925_TSC_IRQ,
.mask_reg = MAX8925_TSC_IRQ_MASK,
.offs = 1 << 1,
.flags = FLAGS_ADC,
.tsc_irq = 1,
},
};
static irqreturn_t max8925_irq(int irq, void *data)
{
struct max8925_chip *chip = data;
struct max8925_irq_data *irq_data;
struct i2c_client *i2c;
int read_reg = -1, value = 0;
int i;
for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
irq_data = &max8925_irqs[i];
/* TSC IRQ should be serviced in max8925_tsc_irq() */
if (irq_data->tsc_irq)
continue;
if (irq_data->flags == FLAGS_RTC)
i2c = chip->rtc;
else if (irq_data->flags == FLAGS_ADC)
i2c = chip->adc;
else
i2c = chip->i2c;
if (read_reg != irq_data->reg) {
read_reg = irq_data->reg;
value = max8925_reg_read(i2c, irq_data->reg);
}
if (value & irq_data->enable)
handle_nested_irq(chip->irq_base + i);
}
return IRQ_HANDLED;
}
static irqreturn_t max8925_tsc_irq(int irq, void *data)
{
struct max8925_chip *chip = data;
struct max8925_irq_data *irq_data;
struct i2c_client *i2c;
int read_reg = -1, value = 0;
int i;
for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
irq_data = &max8925_irqs[i];
/* non TSC IRQ should be serviced in max8925_irq() */
if (!irq_data->tsc_irq)
continue;
if (irq_data->flags == FLAGS_RTC)
i2c = chip->rtc;
else if (irq_data->flags == FLAGS_ADC)
i2c = chip->adc;
else
i2c = chip->i2c;
if (read_reg != irq_data->reg) {
read_reg = irq_data->reg;
value = max8925_reg_read(i2c, irq_data->reg);
}
if (value & irq_data->enable)
handle_nested_irq(chip->irq_base + i);
}
return IRQ_HANDLED;
}
static void max8925_irq_lock(struct irq_data *data)
{
struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
mutex_lock(&chip->irq_lock);
}
static void max8925_irq_sync_unlock(struct irq_data *data)
{
struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
struct max8925_irq_data *irq_data;
static unsigned char cache_chg[2] = {0xff, 0xff};
static unsigned char cache_on[2] = {0xff, 0xff};
static unsigned char cache_rtc = 0xff, cache_tsc = 0xff;
unsigned char irq_chg[2], irq_on[2];
unsigned char irq_rtc, irq_tsc;
int i;
/* Load cached value. In initial, all IRQs are masked */
irq_chg[0] = cache_chg[0];
irq_chg[1] = cache_chg[1];
irq_on[0] = cache_on[0];
irq_on[1] = cache_on[1];
irq_rtc = cache_rtc;
irq_tsc = cache_tsc;
for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
irq_data = &max8925_irqs[i];
/* 1 -- disable, 0 -- enable */
switch (irq_data->mask_reg) {
case MAX8925_CHG_IRQ1_MASK:
irq_chg[0] &= ~irq_data->enable;
break;
case MAX8925_CHG_IRQ2_MASK:
irq_chg[1] &= ~irq_data->enable;
break;
case MAX8925_ON_OFF_IRQ1_MASK:
irq_on[0] &= ~irq_data->enable;
break;
case MAX8925_ON_OFF_IRQ2_MASK:
irq_on[1] &= ~irq_data->enable;
break;
case MAX8925_RTC_IRQ_MASK:
irq_rtc &= ~irq_data->enable;
break;
case MAX8925_TSC_IRQ_MASK:
irq_tsc &= ~irq_data->enable;
break;
default:
dev_err(chip->dev, "wrong IRQ\n");
break;
}
}
/* update mask into registers */
if (cache_chg[0] != irq_chg[0]) {
cache_chg[0] = irq_chg[0];
max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK,
irq_chg[0]);
}
if (cache_chg[1] != irq_chg[1]) {
cache_chg[1] = irq_chg[1];
max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK,
irq_chg[1]);
}
if (cache_on[0] != irq_on[0]) {
cache_on[0] = irq_on[0];
max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK,
irq_on[0]);
}
if (cache_on[1] != irq_on[1]) {
cache_on[1] = irq_on[1];
max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK,
irq_on[1]);
}
if (cache_rtc != irq_rtc) {
cache_rtc = irq_rtc;
max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, irq_rtc);
}
if (cache_tsc != irq_tsc) {
cache_tsc = irq_tsc;
max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, irq_tsc);
}
mutex_unlock(&chip->irq_lock);
}
static void max8925_irq_enable(struct irq_data *data)
{
struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
max8925_irqs[data->irq - chip->irq_base].enable
= max8925_irqs[data->irq - chip->irq_base].offs;
}
static void max8925_irq_disable(struct irq_data *data)
{
struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
max8925_irqs[data->irq - chip->irq_base].enable = 0;
}
static struct irq_chip max8925_irq_chip = {
.name = "max8925",
.irq_bus_lock = max8925_irq_lock,
.irq_bus_sync_unlock = max8925_irq_sync_unlock,
.irq_enable = max8925_irq_enable,
.irq_disable = max8925_irq_disable,
};
static int max8925_irq_domain_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hw)
{
irq_set_chip_data(virq, d->host_data);
irq_set_chip_and_handler(virq, &max8925_irq_chip, handle_edge_irq);
irq_set_nested_thread(virq, 1);
irq_set_noprobe(virq);
return 0;
}
static const struct irq_domain_ops max8925_irq_domain_ops = {
.map = max8925_irq_domain_map,
.xlate = irq_domain_xlate_onetwocell,
};
static int max8925_irq_init(struct max8925_chip *chip, int irq,
struct max8925_platform_data *pdata)
{
unsigned long flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
int ret;
struct device_node *node = chip->dev->of_node;
/* clear all interrupts */
max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ1);
max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ2);
max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ1);
max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ2);
max8925_reg_read(chip->rtc, MAX8925_RTC_IRQ);
max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
/* mask all interrupts except for TSC */
max8925_reg_write(chip->rtc, MAX8925_ALARM0_CNTL, 0);
max8925_reg_write(chip->rtc, MAX8925_ALARM1_CNTL, 0);
max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK, 0xff);
max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK, 0xff);
max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK, 0xff);
max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK, 0xff);
max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, 0xff);
mutex_init(&chip->irq_lock);
chip->irq_base = irq_alloc_descs(-1, 0, MAX8925_NR_IRQS, 0);
if (chip->irq_base < 0) {
dev_err(chip->dev, "Failed to allocate interrupts, ret:%d\n",
chip->irq_base);
return -EBUSY;
}
irq_domain_add_legacy(node, MAX8925_NR_IRQS, chip->irq_base, 0,
&max8925_irq_domain_ops, chip);
/* request irq handler for pmic main irq*/
chip->core_irq = irq;
if (!chip->core_irq)
return -EBUSY;
ret = request_threaded_irq(irq, NULL, max8925_irq, flags | IRQF_ONESHOT,
"max8925", chip);
if (ret) {
dev_err(chip->dev, "Failed to request core IRQ: %d\n", ret);
chip->core_irq = 0;
return -EBUSY;
}
/* request irq handler for pmic tsc irq*/
/* mask TSC interrupt */
max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, 0x0f);
if (!pdata->tsc_irq) {
dev_warn(chip->dev, "No interrupt support on TSC IRQ\n");
return 0;
}
chip->tsc_irq = pdata->tsc_irq;
ret = request_threaded_irq(chip->tsc_irq, NULL, max8925_tsc_irq,
flags | IRQF_ONESHOT, "max8925-tsc", chip);
if (ret) {
dev_err(chip->dev, "Failed to request TSC IRQ: %d\n", ret);
chip->tsc_irq = 0;
}
return 0;
}
static void init_regulator(struct max8925_chip *chip,
struct max8925_platform_data *pdata)
{
int ret;
if (!pdata)
return;
if (pdata->sd1) {
reg_devs[0].platform_data = pdata->sd1;
reg_devs[0].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->sd2) {
reg_devs[1].platform_data = pdata->sd2;
reg_devs[1].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->sd3) {
reg_devs[2].platform_data = pdata->sd3;
reg_devs[2].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo1) {
reg_devs[3].platform_data = pdata->ldo1;
reg_devs[3].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo2) {
reg_devs[4].platform_data = pdata->ldo2;
reg_devs[4].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo3) {
reg_devs[5].platform_data = pdata->ldo3;
reg_devs[5].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo4) {
reg_devs[6].platform_data = pdata->ldo4;
reg_devs[6].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo5) {
reg_devs[7].platform_data = pdata->ldo5;
reg_devs[7].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo6) {
reg_devs[8].platform_data = pdata->ldo6;
reg_devs[8].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo7) {
reg_devs[9].platform_data = pdata->ldo7;
reg_devs[9].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo8) {
reg_devs[10].platform_data = pdata->ldo8;
reg_devs[10].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo9) {
reg_devs[11].platform_data = pdata->ldo9;
reg_devs[11].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo10) {
reg_devs[12].platform_data = pdata->ldo10;
reg_devs[12].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo11) {
reg_devs[13].platform_data = pdata->ldo11;
reg_devs[13].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo12) {
reg_devs[14].platform_data = pdata->ldo12;
reg_devs[14].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo13) {
reg_devs[15].platform_data = pdata->ldo13;
reg_devs[15].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo14) {
reg_devs[16].platform_data = pdata->ldo14;
reg_devs[16].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo15) {
reg_devs[17].platform_data = pdata->ldo15;
reg_devs[17].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo16) {
reg_devs[18].platform_data = pdata->ldo16;
reg_devs[18].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo17) {
reg_devs[19].platform_data = pdata->ldo17;
reg_devs[19].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo18) {
reg_devs[20].platform_data = pdata->ldo18;
reg_devs[20].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo19) {
reg_devs[21].platform_data = pdata->ldo19;
reg_devs[21].pdata_size = sizeof(struct regulator_init_data);
}
if (pdata->ldo20) {
reg_devs[22].platform_data = pdata->ldo20;
reg_devs[22].pdata_size = sizeof(struct regulator_init_data);
}
ret = mfd_add_devices(chip->dev, 0, reg_devs, ARRAY_SIZE(reg_devs),
NULL, 0, NULL);
if (ret < 0) {
dev_err(chip->dev, "Failed to add regulator subdev\n");
return;
}
}
int max8925_device_init(struct max8925_chip *chip,
struct max8925_platform_data *pdata)
{
int ret;
max8925_irq_init(chip, chip->i2c->irq, pdata);
if (pdata && (pdata->power || pdata->touch)) {
/* enable ADC to control internal reference */
max8925_set_bits(chip->i2c, MAX8925_RESET_CNFG, 1, 1);
/* enable internal reference for ADC */
max8925_set_bits(chip->adc, MAX8925_TSC_CNFG1, 3, 2);
/* check for internal reference IRQ */
do {
ret = max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
} while (ret & MAX8925_NREF_OK);
/* enaable ADC scheduler, interval is 1 second */
max8925_set_bits(chip->adc, MAX8925_ADC_SCHED, 3, 2);
}
/* enable Momentary Power Loss */
max8925_set_bits(chip->rtc, MAX8925_MPL_CNTL, 1 << 4, 1 << 4);
ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
ARRAY_SIZE(rtc_devs),
NULL, chip->irq_base, NULL);
if (ret < 0) {
dev_err(chip->dev, "Failed to add rtc subdev\n");
goto out;
}
ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
ARRAY_SIZE(onkey_devs),
NULL, chip->irq_base, NULL);
if (ret < 0) {
dev_err(chip->dev, "Failed to add onkey subdev\n");
goto out_dev;
}
init_regulator(chip, pdata);
if (pdata && pdata->backlight) {
bk_devs[0].platform_data = &pdata->backlight;
bk_devs[0].pdata_size = sizeof(struct max8925_backlight_pdata);
}
ret = mfd_add_devices(chip->dev, 0, bk_devs, ARRAY_SIZE(bk_devs),
NULL, 0, NULL);
if (ret < 0) {
dev_err(chip->dev, "Failed to add backlight subdev\n");
goto out_dev;
}
ret = mfd_add_devices(chip->dev, 0, &power_devs[0],
ARRAY_SIZE(power_devs),
NULL, 0, NULL);
if (ret < 0) {
dev_err(chip->dev,
"Failed to add power supply subdev, err = %d\n", ret);
goto out_dev;
}
if (pdata && pdata->touch) {
ret = mfd_add_devices(chip->dev, 0, &touch_devs[0],
ARRAY_SIZE(touch_devs),
NULL, chip->tsc_irq, NULL);
if (ret < 0) {
dev_err(chip->dev, "Failed to add touch subdev\n");
goto out_dev;
}
}
return 0;
out_dev:
mfd_remove_devices(chip->dev);
out:
return ret;
}
void max8925_device_exit(struct max8925_chip *chip)
{
if (chip->core_irq)
free_irq(chip->core_irq, chip);
if (chip->tsc_irq)
free_irq(chip->tsc_irq, chip);
mfd_remove_devices(chip->dev);
}
| linux-master | drivers/mfd/max8925-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Interrupt driver for RICOH583 power management chip.
*
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
* Author: Laxman dewangan <[email protected]>
*
* based on code
* Copyright (C) 2011 RICOH COMPANY,LTD
*/
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mfd/rc5t583.h>
enum int_type {
SYS_INT = 0x1,
DCDC_INT = 0x2,
RTC_INT = 0x4,
ADC_INT = 0x8,
GPIO_INT = 0x10,
};
static int gpedge_add[] = {
RC5T583_GPIO_GPEDGE2,
RC5T583_GPIO_GPEDGE2
};
static int irq_en_add[] = {
RC5T583_INT_EN_SYS1,
RC5T583_INT_EN_SYS2,
RC5T583_INT_EN_DCDC,
RC5T583_INT_EN_RTC,
RC5T583_INT_EN_ADC1,
RC5T583_INT_EN_ADC2,
RC5T583_INT_EN_ADC3,
RC5T583_GPIO_EN_INT
};
static int irq_mon_add[] = {
RC5T583_INT_MON_SYS1,
RC5T583_INT_MON_SYS2,
RC5T583_INT_MON_DCDC,
RC5T583_INT_MON_RTC,
RC5T583_INT_IR_ADCL,
RC5T583_INT_IR_ADCH,
RC5T583_INT_IR_ADCEND,
RC5T583_INT_IR_GPIOF,
RC5T583_INT_IR_GPIOR
};
static int irq_clr_add[] = {
RC5T583_INT_IR_SYS1,
RC5T583_INT_IR_SYS2,
RC5T583_INT_IR_DCDC,
RC5T583_INT_IR_RTC,
RC5T583_INT_IR_ADCL,
RC5T583_INT_IR_ADCH,
RC5T583_INT_IR_ADCEND,
RC5T583_INT_IR_GPIOF,
RC5T583_INT_IR_GPIOR
};
static int main_int_type[] = {
SYS_INT,
SYS_INT,
DCDC_INT,
RTC_INT,
ADC_INT,
ADC_INT,
ADC_INT,
GPIO_INT,
GPIO_INT,
};
struct rc5t583_irq_data {
u8 int_type;
u8 master_bit;
u8 int_en_bit;
u8 mask_reg_index;
int grp_index;
};
#define RC5T583_IRQ(_int_type, _master_bit, _grp_index, \
_int_bit, _mask_ind) \
{ \
.int_type = _int_type, \
.master_bit = _master_bit, \
.grp_index = _grp_index, \
.int_en_bit = _int_bit, \
.mask_reg_index = _mask_ind, \
}
static const struct rc5t583_irq_data rc5t583_irqs[RC5T583_MAX_IRQS] = {
[RC5T583_IRQ_ONKEY] = RC5T583_IRQ(SYS_INT, 0, 0, 0, 0),
[RC5T583_IRQ_ACOK] = RC5T583_IRQ(SYS_INT, 0, 1, 1, 0),
[RC5T583_IRQ_LIDOPEN] = RC5T583_IRQ(SYS_INT, 0, 2, 2, 0),
[RC5T583_IRQ_PREOT] = RC5T583_IRQ(SYS_INT, 0, 3, 3, 0),
[RC5T583_IRQ_CLKSTP] = RC5T583_IRQ(SYS_INT, 0, 4, 4, 0),
[RC5T583_IRQ_ONKEY_OFF] = RC5T583_IRQ(SYS_INT, 0, 5, 5, 0),
[RC5T583_IRQ_WD] = RC5T583_IRQ(SYS_INT, 0, 7, 7, 0),
[RC5T583_IRQ_EN_PWRREQ1] = RC5T583_IRQ(SYS_INT, 0, 8, 0, 1),
[RC5T583_IRQ_EN_PWRREQ2] = RC5T583_IRQ(SYS_INT, 0, 9, 1, 1),
[RC5T583_IRQ_PRE_VINDET] = RC5T583_IRQ(SYS_INT, 0, 10, 2, 1),
[RC5T583_IRQ_DC0LIM] = RC5T583_IRQ(DCDC_INT, 1, 0, 0, 2),
[RC5T583_IRQ_DC1LIM] = RC5T583_IRQ(DCDC_INT, 1, 1, 1, 2),
[RC5T583_IRQ_DC2LIM] = RC5T583_IRQ(DCDC_INT, 1, 2, 2, 2),
[RC5T583_IRQ_DC3LIM] = RC5T583_IRQ(DCDC_INT, 1, 3, 3, 2),
[RC5T583_IRQ_CTC] = RC5T583_IRQ(RTC_INT, 2, 0, 0, 3),
[RC5T583_IRQ_YALE] = RC5T583_IRQ(RTC_INT, 2, 5, 5, 3),
[RC5T583_IRQ_DALE] = RC5T583_IRQ(RTC_INT, 2, 6, 6, 3),
[RC5T583_IRQ_WALE] = RC5T583_IRQ(RTC_INT, 2, 7, 7, 3),
[RC5T583_IRQ_AIN1L] = RC5T583_IRQ(ADC_INT, 3, 0, 0, 4),
[RC5T583_IRQ_AIN2L] = RC5T583_IRQ(ADC_INT, 3, 1, 1, 4),
[RC5T583_IRQ_AIN3L] = RC5T583_IRQ(ADC_INT, 3, 2, 2, 4),
[RC5T583_IRQ_VBATL] = RC5T583_IRQ(ADC_INT, 3, 3, 3, 4),
[RC5T583_IRQ_VIN3L] = RC5T583_IRQ(ADC_INT, 3, 4, 4, 4),
[RC5T583_IRQ_VIN8L] = RC5T583_IRQ(ADC_INT, 3, 5, 5, 4),
[RC5T583_IRQ_AIN1H] = RC5T583_IRQ(ADC_INT, 3, 6, 0, 5),
[RC5T583_IRQ_AIN2H] = RC5T583_IRQ(ADC_INT, 3, 7, 1, 5),
[RC5T583_IRQ_AIN3H] = RC5T583_IRQ(ADC_INT, 3, 8, 2, 5),
[RC5T583_IRQ_VBATH] = RC5T583_IRQ(ADC_INT, 3, 9, 3, 5),
[RC5T583_IRQ_VIN3H] = RC5T583_IRQ(ADC_INT, 3, 10, 4, 5),
[RC5T583_IRQ_VIN8H] = RC5T583_IRQ(ADC_INT, 3, 11, 5, 5),
[RC5T583_IRQ_ADCEND] = RC5T583_IRQ(ADC_INT, 3, 12, 0, 6),
[RC5T583_IRQ_GPIO0] = RC5T583_IRQ(GPIO_INT, 4, 0, 0, 7),
[RC5T583_IRQ_GPIO1] = RC5T583_IRQ(GPIO_INT, 4, 1, 1, 7),
[RC5T583_IRQ_GPIO2] = RC5T583_IRQ(GPIO_INT, 4, 2, 2, 7),
[RC5T583_IRQ_GPIO3] = RC5T583_IRQ(GPIO_INT, 4, 3, 3, 7),
[RC5T583_IRQ_GPIO4] = RC5T583_IRQ(GPIO_INT, 4, 4, 4, 7),
[RC5T583_IRQ_GPIO5] = RC5T583_IRQ(GPIO_INT, 4, 5, 5, 7),
[RC5T583_IRQ_GPIO6] = RC5T583_IRQ(GPIO_INT, 4, 6, 6, 7),
[RC5T583_IRQ_GPIO7] = RC5T583_IRQ(GPIO_INT, 4, 7, 7, 7),
};
static void rc5t583_irq_lock(struct irq_data *irq_data)
{
struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
mutex_lock(&rc5t583->irq_lock);
}
static void rc5t583_irq_unmask(struct irq_data *irq_data)
{
struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
unsigned int __irq = irq_data->irq - rc5t583->irq_base;
const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];
rc5t583->group_irq_en[data->grp_index] |= 1 << data->grp_index;
rc5t583->intc_inten_reg |= 1 << data->master_bit;
rc5t583->irq_en_reg[data->mask_reg_index] |= 1 << data->int_en_bit;
}
static void rc5t583_irq_mask(struct irq_data *irq_data)
{
struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
unsigned int __irq = irq_data->irq - rc5t583->irq_base;
const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];
rc5t583->group_irq_en[data->grp_index] &= ~(1 << data->grp_index);
if (!rc5t583->group_irq_en[data->grp_index])
rc5t583->intc_inten_reg &= ~(1 << data->master_bit);
rc5t583->irq_en_reg[data->mask_reg_index] &= ~(1 << data->int_en_bit);
}
static int rc5t583_irq_set_type(struct irq_data *irq_data, unsigned int type)
{
struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
unsigned int __irq = irq_data->irq - rc5t583->irq_base;
const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];
int val = 0;
int gpedge_index;
int gpedge_bit_pos;
/* Supporting only trigger level inetrrupt */
if ((data->int_type & GPIO_INT) && (type & IRQ_TYPE_EDGE_BOTH)) {
gpedge_index = data->int_en_bit / 4;
gpedge_bit_pos = data->int_en_bit % 4;
if (type & IRQ_TYPE_EDGE_FALLING)
val |= 0x2;
if (type & IRQ_TYPE_EDGE_RISING)
val |= 0x1;
rc5t583->gpedge_reg[gpedge_index] &= ~(3 << gpedge_bit_pos);
rc5t583->gpedge_reg[gpedge_index] |= (val << gpedge_bit_pos);
rc5t583_irq_unmask(irq_data);
return 0;
}
return -EINVAL;
}
static void rc5t583_irq_sync_unlock(struct irq_data *irq_data)
{
struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
int i;
int ret;
for (i = 0; i < ARRAY_SIZE(rc5t583->gpedge_reg); i++) {
ret = rc5t583_write(rc5t583->dev, gpedge_add[i],
rc5t583->gpedge_reg[i]);
if (ret < 0)
dev_warn(rc5t583->dev,
"Error in writing reg 0x%02x error: %d\n",
gpedge_add[i], ret);
}
for (i = 0; i < ARRAY_SIZE(rc5t583->irq_en_reg); i++) {
ret = rc5t583_write(rc5t583->dev, irq_en_add[i],
rc5t583->irq_en_reg[i]);
if (ret < 0)
dev_warn(rc5t583->dev,
"Error in writing reg 0x%02x error: %d\n",
irq_en_add[i], ret);
}
ret = rc5t583_write(rc5t583->dev, RC5T583_INTC_INTEN,
rc5t583->intc_inten_reg);
if (ret < 0)
dev_warn(rc5t583->dev,
"Error in writing reg 0x%02x error: %d\n",
RC5T583_INTC_INTEN, ret);
mutex_unlock(&rc5t583->irq_lock);
}
static int rc5t583_irq_set_wake(struct irq_data *irq_data, unsigned int on)
{
struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
return irq_set_irq_wake(rc5t583->chip_irq, on);
}
static irqreturn_t rc5t583_irq(int irq, void *data)
{
struct rc5t583 *rc5t583 = data;
uint8_t int_sts[RC5T583_MAX_INTERRUPT_MASK_REGS];
uint8_t master_int = 0;
int i;
int ret;
unsigned int rtc_int_sts = 0;
/* Clear the status */
for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; i++)
int_sts[i] = 0;
ret = rc5t583_read(rc5t583->dev, RC5T583_INTC_INTMON, &master_int);
if (ret < 0) {
dev_err(rc5t583->dev,
"Error in reading reg 0x%02x error: %d\n",
RC5T583_INTC_INTMON, ret);
return IRQ_HANDLED;
}
for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; ++i) {
if (!(master_int & main_int_type[i]))
continue;
ret = rc5t583_read(rc5t583->dev, irq_mon_add[i], &int_sts[i]);
if (ret < 0) {
dev_warn(rc5t583->dev,
"Error in reading reg 0x%02x error: %d\n",
irq_mon_add[i], ret);
int_sts[i] = 0;
continue;
}
if (main_int_type[i] & RTC_INT) {
rtc_int_sts = 0;
if (int_sts[i] & 0x1)
rtc_int_sts |= BIT(6);
if (int_sts[i] & 0x2)
rtc_int_sts |= BIT(7);
if (int_sts[i] & 0x4)
rtc_int_sts |= BIT(0);
if (int_sts[i] & 0x8)
rtc_int_sts |= BIT(5);
}
ret = rc5t583_write(rc5t583->dev, irq_clr_add[i],
~int_sts[i]);
if (ret < 0)
dev_warn(rc5t583->dev,
"Error in reading reg 0x%02x error: %d\n",
irq_clr_add[i], ret);
if (main_int_type[i] & RTC_INT)
int_sts[i] = rtc_int_sts;
}
/* Merge gpio interrupts for rising and falling case*/
int_sts[7] |= int_sts[8];
/* Call interrupt handler if enabled */
for (i = 0; i < RC5T583_MAX_IRQS; ++i) {
const struct rc5t583_irq_data *data = &rc5t583_irqs[i];
if ((int_sts[data->mask_reg_index] & (1 << data->int_en_bit)) &&
(rc5t583->group_irq_en[data->master_bit] &
(1 << data->grp_index)))
handle_nested_irq(rc5t583->irq_base + i);
}
return IRQ_HANDLED;
}
static struct irq_chip rc5t583_irq_chip = {
.name = "rc5t583-irq",
.irq_mask = rc5t583_irq_mask,
.irq_unmask = rc5t583_irq_unmask,
.irq_bus_lock = rc5t583_irq_lock,
.irq_bus_sync_unlock = rc5t583_irq_sync_unlock,
.irq_set_type = rc5t583_irq_set_type,
.irq_set_wake = pm_sleep_ptr(rc5t583_irq_set_wake),
};
int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base)
{
int i, ret;
if (!irq_base) {
dev_warn(rc5t583->dev, "No interrupt support on IRQ base\n");
return -EINVAL;
}
mutex_init(&rc5t583->irq_lock);
/* Initailize all int register to 0 */
for (i = 0; i < RC5T583_MAX_INTERRUPT_EN_REGS; i++) {
ret = rc5t583_write(rc5t583->dev, irq_en_add[i],
rc5t583->irq_en_reg[i]);
if (ret < 0)
dev_warn(rc5t583->dev,
"Error in writing reg 0x%02x error: %d\n",
irq_en_add[i], ret);
}
for (i = 0; i < RC5T583_MAX_GPEDGE_REG; i++) {
ret = rc5t583_write(rc5t583->dev, gpedge_add[i],
rc5t583->gpedge_reg[i]);
if (ret < 0)
dev_warn(rc5t583->dev,
"Error in writing reg 0x%02x error: %d\n",
gpedge_add[i], ret);
}
ret = rc5t583_write(rc5t583->dev, RC5T583_INTC_INTEN, 0x0);
if (ret < 0)
dev_warn(rc5t583->dev,
"Error in writing reg 0x%02x error: %d\n",
RC5T583_INTC_INTEN, ret);
/* Clear all interrupts in case they woke up active. */
for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; i++) {
ret = rc5t583_write(rc5t583->dev, irq_clr_add[i], 0);
if (ret < 0)
dev_warn(rc5t583->dev,
"Error in writing reg 0x%02x error: %d\n",
irq_clr_add[i], ret);
}
rc5t583->irq_base = irq_base;
rc5t583->chip_irq = irq;
for (i = 0; i < RC5T583_MAX_IRQS; i++) {
int __irq = i + rc5t583->irq_base;
irq_set_chip_data(__irq, rc5t583);
irq_set_chip_and_handler(__irq, &rc5t583_irq_chip,
handle_simple_irq);
irq_set_nested_thread(__irq, 1);
irq_clear_status_flags(__irq, IRQ_NOREQUEST);
}
ret = devm_request_threaded_irq(rc5t583->dev, irq, NULL, rc5t583_irq,
IRQF_ONESHOT, "rc5t583", rc5t583);
if (ret < 0)
dev_err(rc5t583->dev,
"Error in registering interrupt error: %d\n", ret);
return ret;
}
| linux-master | drivers/mfd/rc5t583-irq.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ROHM BD9571MWV-M and BD9574MVF-M core driver
*
* Copyright (C) 2017 Marek Vasut <[email protected]>
* Copyright (C) 2020 Renesas Electronics Corporation
*
* Based on the TPS65086 driver
*/
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mfd/rohm-generic.h>
#include <linux/module.h>
#include <linux/mfd/bd9571mwv.h>
static const struct mfd_cell bd9571mwv_cells[] = {
{ .name = "bd9571mwv-regulator", },
{ .name = "bd9571mwv-gpio", },
};
static const struct regmap_range bd9571mwv_readable_yes_ranges[] = {
regmap_reg_range(BD9571MWV_VENDOR_CODE, BD9571MWV_PRODUCT_REVISION),
regmap_reg_range(BD9571MWV_BKUP_MODE_CNT, BD9571MWV_BKUP_MODE_CNT),
regmap_reg_range(BD9571MWV_AVS_SET_MONI, BD9571MWV_AVS_DVFS_VID(3)),
regmap_reg_range(BD9571MWV_VD18_VID, BD9571MWV_VD33_VID),
regmap_reg_range(BD9571MWV_DVFS_VINIT, BD9571MWV_DVFS_VINIT),
regmap_reg_range(BD9571MWV_DVFS_SETVMAX, BD9571MWV_DVFS_MONIVDAC),
regmap_reg_range(BD9571MWV_GPIO_IN, BD9571MWV_GPIO_IN),
regmap_reg_range(BD9571MWV_GPIO_INT, BD9571MWV_GPIO_INTMASK),
regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTMASK),
};
static const struct regmap_access_table bd9571mwv_readable_table = {
.yes_ranges = bd9571mwv_readable_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(bd9571mwv_readable_yes_ranges),
};
static const struct regmap_range bd9571mwv_writable_yes_ranges[] = {
regmap_reg_range(BD9571MWV_BKUP_MODE_CNT, BD9571MWV_BKUP_MODE_CNT),
regmap_reg_range(BD9571MWV_AVS_VD09_VID(0), BD9571MWV_AVS_VD09_VID(3)),
regmap_reg_range(BD9571MWV_DVFS_SETVID, BD9571MWV_DVFS_SETVID),
regmap_reg_range(BD9571MWV_GPIO_DIR, BD9571MWV_GPIO_OUT),
regmap_reg_range(BD9571MWV_GPIO_INT_SET, BD9571MWV_GPIO_INTMASK),
regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTMASK),
};
static const struct regmap_access_table bd9571mwv_writable_table = {
.yes_ranges = bd9571mwv_writable_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(bd9571mwv_writable_yes_ranges),
};
static const struct regmap_range bd9571mwv_volatile_yes_ranges[] = {
regmap_reg_range(BD9571MWV_DVFS_MONIVDAC, BD9571MWV_DVFS_MONIVDAC),
regmap_reg_range(BD9571MWV_GPIO_IN, BD9571MWV_GPIO_IN),
regmap_reg_range(BD9571MWV_GPIO_INT, BD9571MWV_GPIO_INT),
regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTREQ),
};
static const struct regmap_access_table bd9571mwv_volatile_table = {
.yes_ranges = bd9571mwv_volatile_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(bd9571mwv_volatile_yes_ranges),
};
static const struct regmap_config bd9571mwv_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.rd_table = &bd9571mwv_readable_table,
.wr_table = &bd9571mwv_writable_table,
.volatile_table = &bd9571mwv_volatile_table,
.max_register = 0xff,
};
static const struct regmap_irq bd9571mwv_irqs[] = {
REGMAP_IRQ_REG(BD9571MWV_IRQ_MD1, 0,
BD9571MWV_INT_INTREQ_MD1_INT),
REGMAP_IRQ_REG(BD9571MWV_IRQ_MD2_E1, 0,
BD9571MWV_INT_INTREQ_MD2_E1_INT),
REGMAP_IRQ_REG(BD9571MWV_IRQ_MD2_E2, 0,
BD9571MWV_INT_INTREQ_MD2_E2_INT),
REGMAP_IRQ_REG(BD9571MWV_IRQ_PROT_ERR, 0,
BD9571MWV_INT_INTREQ_PROT_ERR_INT),
REGMAP_IRQ_REG(BD9571MWV_IRQ_GP, 0,
BD9571MWV_INT_INTREQ_GP_INT),
REGMAP_IRQ_REG(BD9571MWV_IRQ_128H_OF, 0,
BD9571MWV_INT_INTREQ_128H_OF_INT),
REGMAP_IRQ_REG(BD9571MWV_IRQ_WDT_OF, 0,
BD9571MWV_INT_INTREQ_WDT_OF_INT),
REGMAP_IRQ_REG(BD9571MWV_IRQ_BKUP_TRG, 0,
BD9571MWV_INT_INTREQ_BKUP_TRG_INT),
};
static struct regmap_irq_chip bd9571mwv_irq_chip = {
.name = "bd9571mwv",
.status_base = BD9571MWV_INT_INTREQ,
.mask_base = BD9571MWV_INT_INTMASK,
.ack_base = BD9571MWV_INT_INTREQ,
.init_ack_masked = true,
.num_regs = 1,
.irqs = bd9571mwv_irqs,
.num_irqs = ARRAY_SIZE(bd9571mwv_irqs),
};
static const struct mfd_cell bd9574mwf_cells[] = {
{ .name = "bd9574mwf-regulator", },
{ .name = "bd9574mwf-gpio", },
};
static const struct regmap_range bd9574mwf_readable_yes_ranges[] = {
regmap_reg_range(BD9571MWV_VENDOR_CODE, BD9571MWV_PRODUCT_REVISION),
regmap_reg_range(BD9571MWV_BKUP_MODE_CNT, BD9571MWV_BKUP_MODE_CNT),
regmap_reg_range(BD9571MWV_DVFS_VINIT, BD9571MWV_DVFS_SETVMAX),
regmap_reg_range(BD9571MWV_DVFS_SETVID, BD9571MWV_DVFS_MONIVDAC),
regmap_reg_range(BD9571MWV_GPIO_IN, BD9571MWV_GPIO_IN),
regmap_reg_range(BD9571MWV_GPIO_INT, BD9571MWV_GPIO_INTMASK),
regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTMASK),
};
static const struct regmap_access_table bd9574mwf_readable_table = {
.yes_ranges = bd9574mwf_readable_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(bd9574mwf_readable_yes_ranges),
};
static const struct regmap_range bd9574mwf_writable_yes_ranges[] = {
regmap_reg_range(BD9571MWV_BKUP_MODE_CNT, BD9571MWV_BKUP_MODE_CNT),
regmap_reg_range(BD9571MWV_DVFS_SETVID, BD9571MWV_DVFS_SETVID),
regmap_reg_range(BD9571MWV_GPIO_DIR, BD9571MWV_GPIO_OUT),
regmap_reg_range(BD9571MWV_GPIO_INT_SET, BD9571MWV_GPIO_INTMASK),
regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTMASK),
};
static const struct regmap_access_table bd9574mwf_writable_table = {
.yes_ranges = bd9574mwf_writable_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(bd9574mwf_writable_yes_ranges),
};
static const struct regmap_range bd9574mwf_volatile_yes_ranges[] = {
regmap_reg_range(BD9571MWV_DVFS_MONIVDAC, BD9571MWV_DVFS_MONIVDAC),
regmap_reg_range(BD9571MWV_GPIO_IN, BD9571MWV_GPIO_IN),
regmap_reg_range(BD9571MWV_GPIO_INT, BD9571MWV_GPIO_INT),
regmap_reg_range(BD9571MWV_INT_INTREQ, BD9571MWV_INT_INTREQ),
};
static const struct regmap_access_table bd9574mwf_volatile_table = {
.yes_ranges = bd9574mwf_volatile_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(bd9574mwf_volatile_yes_ranges),
};
static const struct regmap_config bd9574mwf_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.rd_table = &bd9574mwf_readable_table,
.wr_table = &bd9574mwf_writable_table,
.volatile_table = &bd9574mwf_volatile_table,
.max_register = 0xff,
};
static struct regmap_irq_chip bd9574mwf_irq_chip = {
.name = "bd9574mwf",
.status_base = BD9571MWV_INT_INTREQ,
.mask_base = BD9571MWV_INT_INTMASK,
.ack_base = BD9571MWV_INT_INTREQ,
.init_ack_masked = true,
.num_regs = 1,
.irqs = bd9571mwv_irqs,
.num_irqs = ARRAY_SIZE(bd9571mwv_irqs),
};
static int bd957x_identify(struct device *dev, struct regmap *regmap)
{
unsigned int value;
int ret;
ret = regmap_read(regmap, BD9571MWV_VENDOR_CODE, &value);
if (ret) {
dev_err(dev, "Failed to read vendor code register (ret=%i)\n",
ret);
return ret;
}
if (value != BD9571MWV_VENDOR_CODE_VAL) {
dev_err(dev, "Invalid vendor code ID %02x (expected %02x)\n",
value, BD9571MWV_VENDOR_CODE_VAL);
return -EINVAL;
}
ret = regmap_read(regmap, BD9571MWV_PRODUCT_CODE, &value);
if (ret) {
dev_err(dev, "Failed to read product code register (ret=%i)\n",
ret);
return ret;
}
ret = regmap_read(regmap, BD9571MWV_PRODUCT_REVISION, &value);
if (ret) {
dev_err(dev, "Failed to read revision register (ret=%i)\n",
ret);
return ret;
}
return 0;
}
static int bd9571mwv_probe(struct i2c_client *client)
{
const struct regmap_config *regmap_config;
const struct regmap_irq_chip *irq_chip;
const struct mfd_cell *cells;
struct device *dev = &client->dev;
struct regmap *regmap;
struct regmap_irq_chip_data *irq_data;
int ret, num_cells, irq = client->irq;
/* Read the PMIC product code */
ret = i2c_smbus_read_byte_data(client, BD9571MWV_PRODUCT_CODE);
if (ret < 0) {
dev_err(dev, "Failed to read product code\n");
return ret;
}
switch (ret) {
case BD9571MWV_PRODUCT_CODE_BD9571MWV:
regmap_config = &bd9571mwv_regmap_config;
irq_chip = &bd9571mwv_irq_chip;
cells = bd9571mwv_cells;
num_cells = ARRAY_SIZE(bd9571mwv_cells);
break;
case BD9571MWV_PRODUCT_CODE_BD9574MWF:
regmap_config = &bd9574mwf_regmap_config;
irq_chip = &bd9574mwf_irq_chip;
cells = bd9574mwf_cells;
num_cells = ARRAY_SIZE(bd9574mwf_cells);
break;
default:
dev_err(dev, "Unsupported device 0x%x\n", ret);
return -ENODEV;
}
regmap = devm_regmap_init_i2c(client, regmap_config);
if (IS_ERR(regmap)) {
dev_err(dev, "Failed to initialize register map\n");
return PTR_ERR(regmap);
}
ret = bd957x_identify(dev, regmap);
if (ret)
return ret;
ret = devm_regmap_add_irq_chip(dev, regmap, irq, IRQF_ONESHOT, 0,
irq_chip, &irq_data);
if (ret) {
dev_err(dev, "Failed to register IRQ chip\n");
return ret;
}
return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cells, num_cells,
NULL, 0, regmap_irq_get_domain(irq_data));
}
static const struct of_device_id bd9571mwv_of_match_table[] = {
{ .compatible = "rohm,bd9571mwv", },
{ .compatible = "rohm,bd9574mwf", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, bd9571mwv_of_match_table);
static const struct i2c_device_id bd9571mwv_id_table[] = {
{ "bd9571mwv", 0 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(i2c, bd9571mwv_id_table);
static struct i2c_driver bd9571mwv_driver = {
.driver = {
.name = "bd9571mwv",
.of_match_table = bd9571mwv_of_match_table,
},
.probe = bd9571mwv_probe,
.id_table = bd9571mwv_id_table,
};
module_i2c_driver(bd9571mwv_driver);
MODULE_AUTHOR("Marek Vasut <[email protected]>");
MODULE_DESCRIPTION("BD9571MWV PMIC Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/bd9571mwv.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Data tables for CS47L24 codec
*
* Copyright 2015 Cirrus Logic, Inc.
*
* Author: Richard Fitzgerald <[email protected]>
*/
#include <linux/module.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/registers.h>
#include <linux/device.h>
#include "arizona.h"
#define CS47L24_NUM_ISR 5
static const struct reg_sequence cs47l24_reva_patch[] = {
{ 0x80, 0x3 },
{ 0x27C, 0x0010 },
{ 0x221, 0x0070 },
{ 0x80, 0x0 },
};
int cs47l24_patch(struct arizona *arizona)
{
return regmap_register_patch(arizona->regmap,
cs47l24_reva_patch,
ARRAY_SIZE(cs47l24_reva_patch));
}
EXPORT_SYMBOL_GPL(cs47l24_patch);
static const struct regmap_irq cs47l24_irqs[ARIZONA_NUM_IRQ] = {
[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
[ARIZONA_IRQ_DSP3_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP2_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP_IRQ8] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
},
[ARIZONA_IRQ_DSP_IRQ7] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
},
[ARIZONA_IRQ_DSP_IRQ6] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1
},
[ARIZONA_IRQ_DSP_IRQ5] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1
},
[ARIZONA_IRQ_DSP_IRQ4] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1
},
[ARIZONA_IRQ_DSP_IRQ3] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1
},
[ARIZONA_IRQ_DSP_IRQ2] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
},
[ARIZONA_IRQ_DSP_IRQ1] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT_WARN] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
},
[ARIZONA_IRQ_WSEQ_DONE] = {
.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
},
[ARIZONA_IRQ_DRC2_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1
},
[ARIZONA_IRQ_DRC1_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
},
[ARIZONA_IRQ_ASRC2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1
},
[ARIZONA_IRQ_ASRC1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1
},
[ARIZONA_IRQ_UNDERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1
},
[ARIZONA_IRQ_OVERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1
},
[ARIZONA_IRQ_FLL2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
},
[ARIZONA_IRQ_FLL1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1
},
[ARIZONA_IRQ_CTRLIF_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_CTRLIF_ERR_EINT1
},
[ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = {
.reg_offset = 3, .mask = ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1
},
[ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_SYSCLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_V2_SYSCLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_ISRC1_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_ISRC1_CFG_ERR_EINT1
},
[ARIZONA_IRQ_ISRC2_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_ISRC2_CFG_ERR_EINT1
},
[ARIZONA_IRQ_ISRC3_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_V2_ISRC3_CFG_ERR_EINT1
},
[ARIZONA_IRQ_HP1R_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1
},
[ARIZONA_IRQ_HP1L_DONE] = {
.reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1
},
[ARIZONA_IRQ_BOOT_DONE] = {
.reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1
},
[ARIZONA_IRQ_ASRC_CFG_ERR] = {
.reg_offset = 4, .mask = ARIZONA_V2_ASRC_CFG_ERR_EINT1
},
[ARIZONA_IRQ_FLL2_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1
},
[ARIZONA_IRQ_FLL1_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1
},
[ARIZONA_IRQ_DSP_SHARED_WR_COLL] = {
.reg_offset = 5, .mask = ARIZONA_DSP_SHARED_WR_COLL_EINT1
},
[ARIZONA_IRQ_SPK_SHUTDOWN] = {
.reg_offset = 5, .mask = ARIZONA_SPK_SHUTDOWN_EINT1
},
[ARIZONA_IRQ_SPK1R_SHORT] = {
.reg_offset = 5, .mask = ARIZONA_SPK1R_SHORT_EINT1
},
[ARIZONA_IRQ_SPK1L_SHORT] = {
.reg_offset = 5, .mask = ARIZONA_SPK1L_SHORT_EINT1
},
[ARIZONA_IRQ_HP1R_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP1R_SC_POS_EINT1
},
[ARIZONA_IRQ_HP1L_SC_POS] = {
.reg_offset = 5, .mask = ARIZONA_HP1L_SC_POS_EINT1
},
};
const struct regmap_irq_chip cs47l24_irq = {
.name = "cs47l24 IRQ",
.status_base = ARIZONA_INTERRUPT_STATUS_1,
.mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK,
.ack_base = ARIZONA_INTERRUPT_STATUS_1,
.num_regs = 6,
.irqs = cs47l24_irqs,
.num_irqs = ARRAY_SIZE(cs47l24_irqs),
};
EXPORT_SYMBOL_GPL(cs47l24_irq);
static const struct reg_default cs47l24_reg_default[] = {
{ 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */
{ 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */
{ 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */
{ 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */
{ 0x00000023, 0x1000 }, /* R35 - Tone Generator 4 */
{ 0x00000024, 0x0000 }, /* R36 - Tone Generator 5 */
{ 0x00000030, 0x0000 }, /* R48 - PWM Drive 1 */
{ 0x00000031, 0x0100 }, /* R49 - PWM Drive 2 */
{ 0x00000032, 0x0100 }, /* R50 - PWM Drive 3 */
{ 0x00000041, 0x0000 }, /* R65 - Sequence control */
{ 0x00000061, 0x01FF }, /* R97 - Sample Rate Sequence Select 1 */
{ 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */
{ 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */
{ 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */
{ 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */
{ 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */
{ 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */
{ 0x00000092, 0x0000 }, /* R146 - Haptics phase 1 intensity */
{ 0x00000093, 0x0000 }, /* R147 - Haptics phase 1 duration */
{ 0x00000094, 0x0000 }, /* R148 - Haptics phase 2 intensity */
{ 0x00000095, 0x0000 }, /* R149 - Haptics phase 2 duration */
{ 0x00000096, 0x0000 }, /* R150 - Haptics phase 3 intensity */
{ 0x00000097, 0x0000 }, /* R151 - Haptics phase 3 duration */
{ 0x00000100, 0x0002 }, /* R256 - Clock 32k 1 */
{ 0x00000101, 0x0504 }, /* R257 - System Clock 1 */
{ 0x00000102, 0x0011 }, /* R258 - Sample rate 1 */
{ 0x00000103, 0x0011 }, /* R259 - Sample rate 2 */
{ 0x00000104, 0x0011 }, /* R260 - Sample rate 3 */
{ 0x00000112, 0x0305 }, /* R274 - Async clock 1 */
{ 0x00000113, 0x0011 }, /* R275 - Async sample rate 1 */
{ 0x00000114, 0x0011 }, /* R276 - Async sample rate 2 */
{ 0x00000149, 0x0000 }, /* R329 - Output system clock */
{ 0x0000014A, 0x0000 }, /* R330 - Output async clock */
{ 0x00000152, 0x0000 }, /* R338 - Rate Estimator 1 */
{ 0x00000153, 0x0000 }, /* R339 - Rate Estimator 2 */
{ 0x00000154, 0x0000 }, /* R340 - Rate Estimator 3 */
{ 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */
{ 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */
{ 0x00000171, 0x0002 }, /* R369 - FLL1 Control 1 */
{ 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */
{ 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */
{ 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */
{ 0x00000175, 0x0006 }, /* R373 - FLL1 Control 5 */
{ 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */
{ 0x00000179, 0x0000 }, /* R376 - FLL1 Control 7 */
{ 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */
{ 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */
{ 0x00000183, 0x0000 }, /* R387 - FLL1 Synchroniser 3 */
{ 0x00000184, 0x0000 }, /* R388 - FLL1 Synchroniser 4 */
{ 0x00000185, 0x0000 }, /* R389 - FLL1 Synchroniser 5 */
{ 0x00000186, 0x0000 }, /* R390 - FLL1 Synchroniser 6 */
{ 0x00000187, 0x0001 }, /* R390 - FLL1 Synchroniser 7 */
{ 0x00000189, 0x0000 }, /* R393 - FLL1 Spread Spectrum */
{ 0x0000018A, 0x000C }, /* R394 - FLL1 GPIO Clock */
{ 0x00000191, 0x0002 }, /* R401 - FLL2 Control 1 */
{ 0x00000192, 0x0008 }, /* R402 - FLL2 Control 2 */
{ 0x00000193, 0x0018 }, /* R403 - FLL2 Control 3 */
{ 0x00000194, 0x007D }, /* R404 - FLL2 Control 4 */
{ 0x00000195, 0x000C }, /* R405 - FLL2 Control 5 */
{ 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */
{ 0x00000199, 0x0000 }, /* R408 - FLL2 Control 7 */
{ 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */
{ 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */
{ 0x000001A3, 0x0000 }, /* R419 - FLL2 Synchroniser 3 */
{ 0x000001A4, 0x0000 }, /* R420 - FLL2 Synchroniser 4 */
{ 0x000001A5, 0x0000 }, /* R421 - FLL2 Synchroniser 5 */
{ 0x000001A6, 0x0000 }, /* R422 - FLL2 Synchroniser 6 */
{ 0x000001A7, 0x0001 }, /* R422 - FLL2 Synchroniser 7 */
{ 0x000001A9, 0x0000 }, /* R425 - FLL2 Spread Spectrum */
{ 0x000001AA, 0x000C }, /* R426 - FLL2 GPIO Clock */
{ 0x00000218, 0x00E6 }, /* R536 - Mic Bias Ctrl 1 */
{ 0x00000219, 0x00E6 }, /* R537 - Mic Bias Ctrl 2 */
{ 0x00000300, 0x0000 }, /* R768 - Input Enables */
{ 0x00000308, 0x0000 }, /* R776 - Input Rate */
{ 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */
{ 0x0000030C, 0x0002 }, /* R780 - HPF Control */
{ 0x00000310, 0x2000 }, /* R784 - IN1L Control */
{ 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */
{ 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */
{ 0x00000314, 0x0000 }, /* R788 - IN1R Control */
{ 0x00000315, 0x0180 }, /* R789 - ADC Digital Volume 1R */
{ 0x00000316, 0x0000 }, /* R790 - DMIC1R Control */
{ 0x00000318, 0x2000 }, /* R792 - IN2L Control */
{ 0x00000319, 0x0180 }, /* R793 - ADC Digital Volume 2L */
{ 0x0000031A, 0x0000 }, /* R794 - DMIC2L Control */
{ 0x0000031C, 0x0000 }, /* R796 - IN2R Control */
{ 0x0000031D, 0x0180 }, /* R797 - ADC Digital Volume 2R */
{ 0x0000031E, 0x0000 }, /* R798 - DMIC2R Control */
{ 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */
{ 0x00000408, 0x0000 }, /* R1032 - Output Rate 1 */
{ 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */
{ 0x00000410, 0x0080 }, /* R1040 - Output Path Config 1L */
{ 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */
{ 0x00000412, 0x0081 }, /* R1042 - DAC Volume Limit 1L */
{ 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */
{ 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */
{ 0x00000416, 0x0081 }, /* R1046 - DAC Volume Limit 1R */
{ 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */
{ 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */
{ 0x0000042A, 0x0081 }, /* R1066 - Out Volume 4L */
{ 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */
{ 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */
{ 0x00000458, 0x0000 }, /* R1112 - Noise Gate Control */
{ 0x000004A0, 0x3480 }, /* R1184 - HP1 Short Circuit Ctrl */
{ 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */
{ 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */
{ 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */
{ 0x00000503, 0x0000 }, /* R1283 - AIF1 Rate Ctrl */
{ 0x00000504, 0x0000 }, /* R1284 - AIF1 Format */
{ 0x00000505, 0x0040 }, /* R1285 - AIF1 Tx BCLK Rate */
{ 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */
{ 0x00000507, 0x1818 }, /* R1287 - AIF1 Frame Ctrl 1 */
{ 0x00000508, 0x1818 }, /* R1288 - AIF1 Frame Ctrl 2 */
{ 0x00000509, 0x0000 }, /* R1289 - AIF1 Frame Ctrl 3 */
{ 0x0000050A, 0x0001 }, /* R1290 - AIF1 Frame Ctrl 4 */
{ 0x0000050B, 0x0002 }, /* R1291 - AIF1 Frame Ctrl 5 */
{ 0x0000050C, 0x0003 }, /* R1292 - AIF1 Frame Ctrl 6 */
{ 0x0000050D, 0x0004 }, /* R1293 - AIF1 Frame Ctrl 7 */
{ 0x0000050E, 0x0005 }, /* R1294 - AIF1 Frame Ctrl 8 */
{ 0x0000050F, 0x0006 }, /* R1295 - AIF1 Frame Ctrl 9 */
{ 0x00000510, 0x0007 }, /* R1296 - AIF1 Frame Ctrl 10 */
{ 0x00000511, 0x0000 }, /* R1297 - AIF1 Frame Ctrl 11 */
{ 0x00000512, 0x0001 }, /* R1298 - AIF1 Frame Ctrl 12 */
{ 0x00000513, 0x0002 }, /* R1299 - AIF1 Frame Ctrl 13 */
{ 0x00000514, 0x0003 }, /* R1300 - AIF1 Frame Ctrl 14 */
{ 0x00000515, 0x0004 }, /* R1301 - AIF1 Frame Ctrl 15 */
{ 0x00000516, 0x0005 }, /* R1302 - AIF1 Frame Ctrl 16 */
{ 0x00000517, 0x0006 }, /* R1303 - AIF1 Frame Ctrl 17 */
{ 0x00000518, 0x0007 }, /* R1304 - AIF1 Frame Ctrl 18 */
{ 0x00000519, 0x0000 }, /* R1305 - AIF1 Tx Enables */
{ 0x0000051A, 0x0000 }, /* R1306 - AIF1 Rx Enables */
{ 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */
{ 0x00000541, 0x0008 }, /* R1345 - AIF2 Tx Pin Ctrl */
{ 0x00000542, 0x0000 }, /* R1346 - AIF2 Rx Pin Ctrl */
{ 0x00000543, 0x0000 }, /* R1347 - AIF2 Rate Ctrl */
{ 0x00000544, 0x0000 }, /* R1348 - AIF2 Format */
{ 0x00000545, 0x0040 }, /* R1349 - AIF2 Tx BCLK Rate */
{ 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */
{ 0x00000547, 0x1818 }, /* R1351 - AIF2 Frame Ctrl 1 */
{ 0x00000548, 0x1818 }, /* R1352 - AIF2 Frame Ctrl 2 */
{ 0x00000549, 0x0000 }, /* R1353 - AIF2 Frame Ctrl 3 */
{ 0x0000054A, 0x0001 }, /* R1354 - AIF2 Frame Ctrl 4 */
{ 0x0000054B, 0x0002 }, /* R1355 - AIF2 Frame Ctrl 5 */
{ 0x0000054C, 0x0003 }, /* R1356 - AIF2 Frame Ctrl 6 */
{ 0x0000054D, 0x0004 }, /* R1357 - AIF2 Frame Ctrl 7 */
{ 0x0000054E, 0x0005 }, /* R1358 - AIF2 Frame Ctrl 8 */
{ 0x00000551, 0x0000 }, /* R1361 - AIF2 Frame Ctrl 11 */
{ 0x00000552, 0x0001 }, /* R1362 - AIF2 Frame Ctrl 12 */
{ 0x00000553, 0x0002 }, /* R1363 - AIF2 Frame Ctrl 13 */
{ 0x00000554, 0x0003 }, /* R1364 - AIF2 Frame Ctrl 14 */
{ 0x00000555, 0x0004 }, /* R1365 - AIF2 Frame Ctrl 15 */
{ 0x00000556, 0x0005 }, /* R1366 - AIF2 Frame Ctrl 16 */
{ 0x00000559, 0x0000 }, /* R1369 - AIF2 Tx Enables */
{ 0x0000055A, 0x0000 }, /* R1370 - AIF2 Rx Enables */
{ 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */
{ 0x00000581, 0x0008 }, /* R1409 - AIF3 Tx Pin Ctrl */
{ 0x00000582, 0x0000 }, /* R1410 - AIF3 Rx Pin Ctrl */
{ 0x00000583, 0x0000 }, /* R1411 - AIF3 Rate Ctrl */
{ 0x00000584, 0x0000 }, /* R1412 - AIF3 Format */
{ 0x00000585, 0x0040 }, /* R1413 - AIF3 Tx BCLK Rate */
{ 0x00000586, 0x0040 }, /* R1414 - AIF3 Rx BCLK Rate */
{ 0x00000587, 0x1818 }, /* R1415 - AIF3 Frame Ctrl 1 */
{ 0x00000588, 0x1818 }, /* R1416 - AIF3 Frame Ctrl 2 */
{ 0x00000589, 0x0000 }, /* R1417 - AIF3 Frame Ctrl 3 */
{ 0x0000058A, 0x0001 }, /* R1418 - AIF3 Frame Ctrl 4 */
{ 0x00000591, 0x0000 }, /* R1425 - AIF3 Frame Ctrl 11 */
{ 0x00000592, 0x0001 }, /* R1426 - AIF3 Frame Ctrl 12 */
{ 0x00000599, 0x0000 }, /* R1433 - AIF3 Tx Enables */
{ 0x0000059A, 0x0000 }, /* R1434 - AIF3 Rx Enables */
{ 0x00000640, 0x0000 }, /* R1600 - PWM1MIX Input 1 Source */
{ 0x00000641, 0x0080 }, /* R1601 - PWM1MIX Input 1 Volume */
{ 0x00000642, 0x0000 }, /* R1602 - PWM1MIX Input 2 Source */
{ 0x00000643, 0x0080 }, /* R1603 - PWM1MIX Input 2 Volume */
{ 0x00000644, 0x0000 }, /* R1604 - PWM1MIX Input 3 Source */
{ 0x00000645, 0x0080 }, /* R1605 - PWM1MIX Input 3 Volume */
{ 0x00000646, 0x0000 }, /* R1606 - PWM1MIX Input 4 Source */
{ 0x00000647, 0x0080 }, /* R1607 - PWM1MIX Input 4 Volume */
{ 0x00000648, 0x0000 }, /* R1608 - PWM2MIX Input 1 Source */
{ 0x00000649, 0x0080 }, /* R1609 - PWM2MIX Input 1 Volume */
{ 0x0000064A, 0x0000 }, /* R1610 - PWM2MIX Input 2 Source */
{ 0x0000064B, 0x0080 }, /* R1611 - PWM2MIX Input 2 Volume */
{ 0x0000064C, 0x0000 }, /* R1612 - PWM2MIX Input 3 Source */
{ 0x0000064D, 0x0080 }, /* R1613 - PWM2MIX Input 3 Volume */
{ 0x0000064E, 0x0000 }, /* R1614 - PWM2MIX Input 4 Source */
{ 0x0000064F, 0x0080 }, /* R1615 - PWM2MIX Input 4 Volume */
{ 0x00000680, 0x0000 }, /* R1664 - OUT1LMIX Input 1 Source */
{ 0x00000681, 0x0080 }, /* R1665 - OUT1LMIX Input 1 Volume */
{ 0x00000682, 0x0000 }, /* R1666 - OUT1LMIX Input 2 Source */
{ 0x00000683, 0x0080 }, /* R1667 - OUT1LMIX Input 2 Volume */
{ 0x00000684, 0x0000 }, /* R1668 - OUT1LMIX Input 3 Source */
{ 0x00000685, 0x0080 }, /* R1669 - OUT1LMIX Input 3 Volume */
{ 0x00000686, 0x0000 }, /* R1670 - OUT1LMIX Input 4 Source */
{ 0x00000687, 0x0080 }, /* R1671 - OUT1LMIX Input 4 Volume */
{ 0x00000688, 0x0000 }, /* R1672 - OUT1RMIX Input 1 Source */
{ 0x00000689, 0x0080 }, /* R1673 - OUT1RMIX Input 1 Volume */
{ 0x0000068A, 0x0000 }, /* R1674 - OUT1RMIX Input 2 Source */
{ 0x0000068B, 0x0080 }, /* R1675 - OUT1RMIX Input 2 Volume */
{ 0x0000068C, 0x0000 }, /* R1676 - OUT1RMIX Input 3 Source */
{ 0x0000068D, 0x0080 }, /* R1677 - OUT1RMIX Input 3 Volume */
{ 0x0000068E, 0x0000 }, /* R1678 - OUT1RMIX Input 4 Source */
{ 0x0000068F, 0x0080 }, /* R1679 - OUT1RMIX Input 4 Volume */
{ 0x000006B0, 0x0000 }, /* R1712 - OUT4LMIX Input 1 Source */
{ 0x000006B1, 0x0080 }, /* R1713 - OUT4LMIX Input 1 Volume */
{ 0x000006B2, 0x0000 }, /* R1714 - OUT4LMIX Input 2 Source */
{ 0x000006B3, 0x0080 }, /* R1715 - OUT4LMIX Input 2 Volume */
{ 0x000006B4, 0x0000 }, /* R1716 - OUT4LMIX Input 3 Source */
{ 0x000006B5, 0x0080 }, /* R1717 - OUT4LMIX Input 3 Volume */
{ 0x000006B6, 0x0000 }, /* R1718 - OUT4LMIX Input 4 Source */
{ 0x000006B7, 0x0080 }, /* R1719 - OUT4LMIX Input 4 Volume */
{ 0x00000700, 0x0000 }, /* R1792 - AIF1TX1MIX Input 1 Source */
{ 0x00000701, 0x0080 }, /* R1793 - AIF1TX1MIX Input 1 Volume */
{ 0x00000702, 0x0000 }, /* R1794 - AIF1TX1MIX Input 2 Source */
{ 0x00000703, 0x0080 }, /* R1795 - AIF1TX1MIX Input 2 Volume */
{ 0x00000704, 0x0000 }, /* R1796 - AIF1TX1MIX Input 3 Source */
{ 0x00000705, 0x0080 }, /* R1797 - AIF1TX1MIX Input 3 Volume */
{ 0x00000706, 0x0000 }, /* R1798 - AIF1TX1MIX Input 4 Source */
{ 0x00000707, 0x0080 }, /* R1799 - AIF1TX1MIX Input 4 Volume */
{ 0x00000708, 0x0000 }, /* R1800 - AIF1TX2MIX Input 1 Source */
{ 0x00000709, 0x0080 }, /* R1801 - AIF1TX2MIX Input 1 Volume */
{ 0x0000070A, 0x0000 }, /* R1802 - AIF1TX2MIX Input 2 Source */
{ 0x0000070B, 0x0080 }, /* R1803 - AIF1TX2MIX Input 2 Volume */
{ 0x0000070C, 0x0000 }, /* R1804 - AIF1TX2MIX Input 3 Source */
{ 0x0000070D, 0x0080 }, /* R1805 - AIF1TX2MIX Input 3 Volume */
{ 0x0000070E, 0x0000 }, /* R1806 - AIF1TX2MIX Input 4 Source */
{ 0x0000070F, 0x0080 }, /* R1807 - AIF1TX2MIX Input 4 Volume */
{ 0x00000710, 0x0000 }, /* R1808 - AIF1TX3MIX Input 1 Source */
{ 0x00000711, 0x0080 }, /* R1809 - AIF1TX3MIX Input 1 Volume */
{ 0x00000712, 0x0000 }, /* R1810 - AIF1TX3MIX Input 2 Source */
{ 0x00000713, 0x0080 }, /* R1811 - AIF1TX3MIX Input 2 Volume */
{ 0x00000714, 0x0000 }, /* R1812 - AIF1TX3MIX Input 3 Source */
{ 0x00000715, 0x0080 }, /* R1813 - AIF1TX3MIX Input 3 Volume */
{ 0x00000716, 0x0000 }, /* R1814 - AIF1TX3MIX Input 4 Source */
{ 0x00000717, 0x0080 }, /* R1815 - AIF1TX3MIX Input 4 Volume */
{ 0x00000718, 0x0000 }, /* R1816 - AIF1TX4MIX Input 1 Source */
{ 0x00000719, 0x0080 }, /* R1817 - AIF1TX4MIX Input 1 Volume */
{ 0x0000071A, 0x0000 }, /* R1818 - AIF1TX4MIX Input 2 Source */
{ 0x0000071B, 0x0080 }, /* R1819 - AIF1TX4MIX Input 2 Volume */
{ 0x0000071C, 0x0000 }, /* R1820 - AIF1TX4MIX Input 3 Source */
{ 0x0000071D, 0x0080 }, /* R1821 - AIF1TX4MIX Input 3 Volume */
{ 0x0000071E, 0x0000 }, /* R1822 - AIF1TX4MIX Input 4 Source */
{ 0x0000071F, 0x0080 }, /* R1823 - AIF1TX4MIX Input 4 Volume */
{ 0x00000720, 0x0000 }, /* R1824 - AIF1TX5MIX Input 1 Source */
{ 0x00000721, 0x0080 }, /* R1825 - AIF1TX5MIX Input 1 Volume */
{ 0x00000722, 0x0000 }, /* R1826 - AIF1TX5MIX Input 2 Source */
{ 0x00000723, 0x0080 }, /* R1827 - AIF1TX5MIX Input 2 Volume */
{ 0x00000724, 0x0000 }, /* R1828 - AIF1TX5MIX Input 3 Source */
{ 0x00000725, 0x0080 }, /* R1829 - AIF1TX5MIX Input 3 Volume */
{ 0x00000726, 0x0000 }, /* R1830 - AIF1TX5MIX Input 4 Source */
{ 0x00000727, 0x0080 }, /* R1831 - AIF1TX5MIX Input 4 Volume */
{ 0x00000728, 0x0000 }, /* R1832 - AIF1TX6MIX Input 1 Source */
{ 0x00000729, 0x0080 }, /* R1833 - AIF1TX6MIX Input 1 Volume */
{ 0x0000072A, 0x0000 }, /* R1834 - AIF1TX6MIX Input 2 Source */
{ 0x0000072B, 0x0080 }, /* R1835 - AIF1TX6MIX Input 2 Volume */
{ 0x0000072C, 0x0000 }, /* R1836 - AIF1TX6MIX Input 3 Source */
{ 0x0000072D, 0x0080 }, /* R1837 - AIF1TX6MIX Input 3 Volume */
{ 0x0000072E, 0x0000 }, /* R1838 - AIF1TX6MIX Input 4 Source */
{ 0x0000072F, 0x0080 }, /* R1839 - AIF1TX6MIX Input 4 Volume */
{ 0x00000730, 0x0000 }, /* R1840 - AIF1TX7MIX Input 1 Source */
{ 0x00000731, 0x0080 }, /* R1841 - AIF1TX7MIX Input 1 Volume */
{ 0x00000732, 0x0000 }, /* R1842 - AIF1TX7MIX Input 2 Source */
{ 0x00000733, 0x0080 }, /* R1843 - AIF1TX7MIX Input 2 Volume */
{ 0x00000734, 0x0000 }, /* R1844 - AIF1TX7MIX Input 3 Source */
{ 0x00000735, 0x0080 }, /* R1845 - AIF1TX7MIX Input 3 Volume */
{ 0x00000736, 0x0000 }, /* R1846 - AIF1TX7MIX Input 4 Source */
{ 0x00000737, 0x0080 }, /* R1847 - AIF1TX7MIX Input 4 Volume */
{ 0x00000738, 0x0000 }, /* R1848 - AIF1TX8MIX Input 1 Source */
{ 0x00000739, 0x0080 }, /* R1849 - AIF1TX8MIX Input 1 Volume */
{ 0x0000073A, 0x0000 }, /* R1850 - AIF1TX8MIX Input 2 Source */
{ 0x0000073B, 0x0080 }, /* R1851 - AIF1TX8MIX Input 2 Volume */
{ 0x0000073C, 0x0000 }, /* R1852 - AIF1TX8MIX Input 3 Source */
{ 0x0000073D, 0x0080 }, /* R1853 - AIF1TX8MIX Input 3 Volume */
{ 0x0000073E, 0x0000 }, /* R1854 - AIF1TX8MIX Input 4 Source */
{ 0x0000073F, 0x0080 }, /* R1855 - AIF1TX8MIX Input 4 Volume */
{ 0x00000740, 0x0000 }, /* R1856 - AIF2TX1MIX Input 1 Source */
{ 0x00000741, 0x0080 }, /* R1857 - AIF2TX1MIX Input 1 Volume */
{ 0x00000742, 0x0000 }, /* R1858 - AIF2TX1MIX Input 2 Source */
{ 0x00000743, 0x0080 }, /* R1859 - AIF2TX1MIX Input 2 Volume */
{ 0x00000744, 0x0000 }, /* R1860 - AIF2TX1MIX Input 3 Source */
{ 0x00000745, 0x0080 }, /* R1861 - AIF2TX1MIX Input 3 Volume */
{ 0x00000746, 0x0000 }, /* R1862 - AIF2TX1MIX Input 4 Source */
{ 0x00000747, 0x0080 }, /* R1863 - AIF2TX1MIX Input 4 Volume */
{ 0x00000748, 0x0000 }, /* R1864 - AIF2TX2MIX Input 1 Source */
{ 0x00000749, 0x0080 }, /* R1865 - AIF2TX2MIX Input 1 Volume */
{ 0x0000074A, 0x0000 }, /* R1866 - AIF2TX2MIX Input 2 Source */
{ 0x0000074B, 0x0080 }, /* R1867 - AIF2TX2MIX Input 2 Volume */
{ 0x0000074C, 0x0000 }, /* R1868 - AIF2TX2MIX Input 3 Source */
{ 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */
{ 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */
{ 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */
{ 0x00000750, 0x0000 }, /* R1872 - AIF2TX3MIX Input 1 Source */
{ 0x00000751, 0x0080 }, /* R1873 - AIF2TX3MIX Input 1 Volume */
{ 0x00000752, 0x0000 }, /* R1874 - AIF2TX3MIX Input 2 Source */
{ 0x00000753, 0x0080 }, /* R1875 - AIF2TX3MIX Input 2 Volume */
{ 0x00000754, 0x0000 }, /* R1876 - AIF2TX3MIX Input 3 Source */
{ 0x00000755, 0x0080 }, /* R1877 - AIF2TX3MIX Input 3 Volume */
{ 0x00000756, 0x0000 }, /* R1878 - AIF2TX3MIX Input 4 Source */
{ 0x00000757, 0x0080 }, /* R1879 - AIF2TX3MIX Input 4 Volume */
{ 0x00000758, 0x0000 }, /* R1880 - AIF2TX4MIX Input 1 Source */
{ 0x00000759, 0x0080 }, /* R1881 - AIF2TX4MIX Input 1 Volume */
{ 0x0000075A, 0x0000 }, /* R1882 - AIF2TX4MIX Input 2 Source */
{ 0x0000075B, 0x0080 }, /* R1883 - AIF2TX4MIX Input 2 Volume */
{ 0x0000075C, 0x0000 }, /* R1884 - AIF2TX4MIX Input 3 Source */
{ 0x0000075D, 0x0080 }, /* R1885 - AIF2TX4MIX Input 3 Volume */
{ 0x0000075E, 0x0000 }, /* R1886 - AIF2TX4MIX Input 4 Source */
{ 0x0000075F, 0x0080 }, /* R1887 - AIF2TX4MIX Input 4 Volume */
{ 0x00000760, 0x0000 }, /* R1888 - AIF2TX5MIX Input 1 Source */
{ 0x00000761, 0x0080 }, /* R1889 - AIF2TX5MIX Input 1 Volume */
{ 0x00000762, 0x0000 }, /* R1890 - AIF2TX5MIX Input 2 Source */
{ 0x00000763, 0x0080 }, /* R1891 - AIF2TX5MIX Input 2 Volume */
{ 0x00000764, 0x0000 }, /* R1892 - AIF2TX5MIX Input 3 Source */
{ 0x00000765, 0x0080 }, /* R1893 - AIF2TX5MIX Input 3 Volume */
{ 0x00000766, 0x0000 }, /* R1894 - AIF2TX5MIX Input 4 Source */
{ 0x00000767, 0x0080 }, /* R1895 - AIF2TX5MIX Input 4 Volume */
{ 0x00000768, 0x0000 }, /* R1896 - AIF2TX6MIX Input 1 Source */
{ 0x00000769, 0x0080 }, /* R1897 - AIF2TX6MIX Input 1 Volume */
{ 0x0000076A, 0x0000 }, /* R1898 - AIF2TX6MIX Input 2 Source */
{ 0x0000076B, 0x0080 }, /* R1899 - AIF2TX6MIX Input 2 Volume */
{ 0x0000076C, 0x0000 }, /* R1900 - AIF2TX6MIX Input 3 Source */
{ 0x0000076D, 0x0080 }, /* R1901 - AIF2TX6MIX Input 3 Volume */
{ 0x0000076E, 0x0000 }, /* R1902 - AIF2TX6MIX Input 4 Source */
{ 0x0000076F, 0x0080 }, /* R1903 - AIF2TX6MIX Input 4 Volume */
{ 0x00000780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */
{ 0x00000781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */
{ 0x00000782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */
{ 0x00000783, 0x0080 }, /* R1923 - AIF3TX1MIX Input 2 Volume */
{ 0x00000784, 0x0000 }, /* R1924 - AIF3TX1MIX Input 3 Source */
{ 0x00000785, 0x0080 }, /* R1925 - AIF3TX1MIX Input 3 Volume */
{ 0x00000786, 0x0000 }, /* R1926 - AIF3TX1MIX Input 4 Source */
{ 0x00000787, 0x0080 }, /* R1927 - AIF3TX1MIX Input 4 Volume */
{ 0x00000788, 0x0000 }, /* R1928 - AIF3TX2MIX Input 1 Source */
{ 0x00000789, 0x0080 }, /* R1929 - AIF3TX2MIX Input 1 Volume */
{ 0x0000078A, 0x0000 }, /* R1930 - AIF3TX2MIX Input 2 Source */
{ 0x0000078B, 0x0080 }, /* R1931 - AIF3TX2MIX Input 2 Volume */
{ 0x0000078C, 0x0000 }, /* R1932 - AIF3TX2MIX Input 3 Source */
{ 0x0000078D, 0x0080 }, /* R1933 - AIF3TX2MIX Input 3 Volume */
{ 0x0000078E, 0x0000 }, /* R1934 - AIF3TX2MIX Input 4 Source */
{ 0x0000078F, 0x0080 }, /* R1935 - AIF3TX2MIX Input 4 Volume */
{ 0x00000880, 0x0000 }, /* R2176 - EQ1MIX Input 1 Source */
{ 0x00000881, 0x0080 }, /* R2177 - EQ1MIX Input 1 Volume */
{ 0x00000882, 0x0000 }, /* R2178 - EQ1MIX Input 2 Source */
{ 0x00000883, 0x0080 }, /* R2179 - EQ1MIX Input 2 Volume */
{ 0x00000884, 0x0000 }, /* R2180 - EQ1MIX Input 3 Source */
{ 0x00000885, 0x0080 }, /* R2181 - EQ1MIX Input 3 Volume */
{ 0x00000886, 0x0000 }, /* R2182 - EQ1MIX Input 4 Source */
{ 0x00000887, 0x0080 }, /* R2183 - EQ1MIX Input 4 Volume */
{ 0x00000888, 0x0000 }, /* R2184 - EQ2MIX Input 1 Source */
{ 0x00000889, 0x0080 }, /* R2185 - EQ2MIX Input 1 Volume */
{ 0x0000088A, 0x0000 }, /* R2186 - EQ2MIX Input 2 Source */
{ 0x0000088B, 0x0080 }, /* R2187 - EQ2MIX Input 2 Volume */
{ 0x0000088C, 0x0000 }, /* R2188 - EQ2MIX Input 3 Source */
{ 0x0000088D, 0x0080 }, /* R2189 - EQ2MIX Input 3 Volume */
{ 0x0000088E, 0x0000 }, /* R2190 - EQ2MIX Input 4 Source */
{ 0x0000088F, 0x0080 }, /* R2191 - EQ2MIX Input 4 Volume */
{ 0x000008C0, 0x0000 }, /* R2240 - DRC1LMIX Input 1 Source */
{ 0x000008C1, 0x0080 }, /* R2241 - DRC1LMIX Input 1 Volume */
{ 0x000008C2, 0x0000 }, /* R2242 - DRC1LMIX Input 2 Source */
{ 0x000008C3, 0x0080 }, /* R2243 - DRC1LMIX Input 2 Volume */
{ 0x000008C4, 0x0000 }, /* R2244 - DRC1LMIX Input 3 Source */
{ 0x000008C5, 0x0080 }, /* R2245 - DRC1LMIX Input 3 Volume */
{ 0x000008C6, 0x0000 }, /* R2246 - DRC1LMIX Input 4 Source */
{ 0x000008C7, 0x0080 }, /* R2247 - DRC1LMIX Input 4 Volume */
{ 0x000008C8, 0x0000 }, /* R2248 - DRC1RMIX Input 1 Source */
{ 0x000008C9, 0x0080 }, /* R2249 - DRC1RMIX Input 1 Volume */
{ 0x000008CA, 0x0000 }, /* R2250 - DRC1RMIX Input 2 Source */
{ 0x000008CB, 0x0080 }, /* R2251 - DRC1RMIX Input 2 Volume */
{ 0x000008CC, 0x0000 }, /* R2252 - DRC1RMIX Input 3 Source */
{ 0x000008CD, 0x0080 }, /* R2253 - DRC1RMIX Input 3 Volume */
{ 0x000008CE, 0x0000 }, /* R2254 - DRC1RMIX Input 4 Source */
{ 0x000008CF, 0x0080 }, /* R2255 - DRC1RMIX Input 4 Volume */
{ 0x000008D0, 0x0000 }, /* R2256 - DRC2LMIX Input 1 Source */
{ 0x000008D1, 0x0080 }, /* R2257 - DRC2LMIX Input 1 Volume */
{ 0x000008D2, 0x0000 }, /* R2258 - DRC2LMIX Input 2 Source */
{ 0x000008D3, 0x0080 }, /* R2259 - DRC2LMIX Input 2 Volume */
{ 0x000008D4, 0x0000 }, /* R2260 - DRC2LMIX Input 3 Source */
{ 0x000008D5, 0x0080 }, /* R2261 - DRC2LMIX Input 3 Volume */
{ 0x000008D6, 0x0000 }, /* R2262 - DRC2LMIX Input 4 Source */
{ 0x000008D7, 0x0080 }, /* R2263 - DRC2LMIX Input 4 Volume */
{ 0x000008D8, 0x0000 }, /* R2264 - DRC2RMIX Input 1 Source */
{ 0x000008D9, 0x0080 }, /* R2265 - DRC2RMIX Input 1 Volume */
{ 0x000008DA, 0x0000 }, /* R2266 - DRC2RMIX Input 2 Source */
{ 0x000008DB, 0x0080 }, /* R2267 - DRC2RMIX Input 2 Volume */
{ 0x000008DC, 0x0000 }, /* R2268 - DRC2RMIX Input 3 Source */
{ 0x000008DD, 0x0080 }, /* R2269 - DRC2RMIX Input 3 Volume */
{ 0x000008DE, 0x0000 }, /* R2270 - DRC2RMIX Input 4 Source */
{ 0x000008DF, 0x0080 }, /* R2271 - DRC2RMIX Input 4 Volume */
{ 0x00000900, 0x0000 }, /* R2304 - HPLP1MIX Input 1 Source */
{ 0x00000901, 0x0080 }, /* R2305 - HPLP1MIX Input 1 Volume */
{ 0x00000902, 0x0000 }, /* R2306 - HPLP1MIX Input 2 Source */
{ 0x00000903, 0x0080 }, /* R2307 - HPLP1MIX Input 2 Volume */
{ 0x00000904, 0x0000 }, /* R2308 - HPLP1MIX Input 3 Source */
{ 0x00000905, 0x0080 }, /* R2309 - HPLP1MIX Input 3 Volume */
{ 0x00000906, 0x0000 }, /* R2310 - HPLP1MIX Input 4 Source */
{ 0x00000907, 0x0080 }, /* R2311 - HPLP1MIX Input 4 Volume */
{ 0x00000908, 0x0000 }, /* R2312 - HPLP2MIX Input 1 Source */
{ 0x00000909, 0x0080 }, /* R2313 - HPLP2MIX Input 1 Volume */
{ 0x0000090A, 0x0000 }, /* R2314 - HPLP2MIX Input 2 Source */
{ 0x0000090B, 0x0080 }, /* R2315 - HPLP2MIX Input 2 Volume */
{ 0x0000090C, 0x0000 }, /* R2316 - HPLP2MIX Input 3 Source */
{ 0x0000090D, 0x0080 }, /* R2317 - HPLP2MIX Input 3 Volume */
{ 0x0000090E, 0x0000 }, /* R2318 - HPLP2MIX Input 4 Source */
{ 0x0000090F, 0x0080 }, /* R2319 - HPLP2MIX Input 4 Volume */
{ 0x00000910, 0x0000 }, /* R2320 - HPLP3MIX Input 1 Source */
{ 0x00000911, 0x0080 }, /* R2321 - HPLP3MIX Input 1 Volume */
{ 0x00000912, 0x0000 }, /* R2322 - HPLP3MIX Input 2 Source */
{ 0x00000913, 0x0080 }, /* R2323 - HPLP3MIX Input 2 Volume */
{ 0x00000914, 0x0000 }, /* R2324 - HPLP3MIX Input 3 Source */
{ 0x00000915, 0x0080 }, /* R2325 - HPLP3MIX Input 3 Volume */
{ 0x00000916, 0x0000 }, /* R2326 - HPLP3MIX Input 4 Source */
{ 0x00000917, 0x0080 }, /* R2327 - HPLP3MIX Input 4 Volume */
{ 0x00000918, 0x0000 }, /* R2328 - HPLP4MIX Input 1 Source */
{ 0x00000919, 0x0080 }, /* R2329 - HPLP4MIX Input 1 Volume */
{ 0x0000091A, 0x0000 }, /* R2330 - HPLP4MIX Input 2 Source */
{ 0x0000091B, 0x0080 }, /* R2331 - HPLP4MIX Input 2 Volume */
{ 0x0000091C, 0x0000 }, /* R2332 - HPLP4MIX Input 3 Source */
{ 0x0000091D, 0x0080 }, /* R2333 - HPLP4MIX Input 3 Volume */
{ 0x0000091E, 0x0000 }, /* R2334 - HPLP4MIX Input 4 Source */
{ 0x0000091F, 0x0080 }, /* R2335 - HPLP4MIX Input 4 Volume */
{ 0x00000980, 0x0000 }, /* R2432 - DSP2LMIX Input 1 Source */
{ 0x00000981, 0x0080 }, /* R2433 - DSP2LMIX Input 1 Volume */
{ 0x00000982, 0x0000 }, /* R2434 - DSP2LMIX Input 2 Source */
{ 0x00000983, 0x0080 }, /* R2435 - DSP2LMIX Input 2 Volume */
{ 0x00000984, 0x0000 }, /* R2436 - DSP2LMIX Input 3 Source */
{ 0x00000985, 0x0080 }, /* R2437 - DSP2LMIX Input 3 Volume */
{ 0x00000986, 0x0000 }, /* R2438 - DSP2LMIX Input 4 Source */
{ 0x00000987, 0x0080 }, /* R2439 - DSP2LMIX Input 4 Volume */
{ 0x00000988, 0x0000 }, /* R2440 - DSP2RMIX Input 1 Source */
{ 0x00000989, 0x0080 }, /* R2441 - DSP2RMIX Input 1 Volume */
{ 0x0000098A, 0x0000 }, /* R2442 - DSP2RMIX Input 2 Source */
{ 0x0000098B, 0x0080 }, /* R2443 - DSP2RMIX Input 2 Volume */
{ 0x0000098C, 0x0000 }, /* R2444 - DSP2RMIX Input 3 Source */
{ 0x0000098D, 0x0080 }, /* R2445 - DSP2RMIX Input 3 Volume */
{ 0x0000098E, 0x0000 }, /* R2446 - DSP2RMIX Input 4 Source */
{ 0x0000098F, 0x0080 }, /* R2447 - DSP2RMIX Input 4 Volume */
{ 0x00000990, 0x0000 }, /* R2448 - DSP2AUX1MIX Input 1 Source */
{ 0x00000998, 0x0000 }, /* R2456 - DSP2AUX2MIX Input 1 Source */
{ 0x000009A0, 0x0000 }, /* R2464 - DSP2AUX3MIX Input 1 Source */
{ 0x000009A8, 0x0000 }, /* R2472 - DSP2AUX4MIX Input 1 Source */
{ 0x000009B0, 0x0000 }, /* R2480 - DSP2AUX5MIX Input 1 Source */
{ 0x000009B8, 0x0000 }, /* R2488 - DSP2AUX6MIX Input 1 Source */
{ 0x000009C0, 0x0000 }, /* R2496 - DSP3LMIX Input 1 Source */
{ 0x000009C1, 0x0080 }, /* R2497 - DSP3LMIX Input 1 Volume */
{ 0x000009C2, 0x0000 }, /* R2498 - DSP3LMIX Input 2 Source */
{ 0x000009C3, 0x0080 }, /* R2499 - DSP3LMIX Input 2 Volume */
{ 0x000009C4, 0x0000 }, /* R2500 - DSP3LMIX Input 3 Source */
{ 0x000009C5, 0x0080 }, /* R2501 - DSP3LMIX Input 3 Volume */
{ 0x000009C6, 0x0000 }, /* R2502 - DSP3LMIX Input 4 Source */
{ 0x000009C7, 0x0080 }, /* R2503 - DSP3LMIX Input 4 Volume */
{ 0x000009C8, 0x0000 }, /* R2504 - DSP3RMIX Input 1 Source */
{ 0x000009C9, 0x0080 }, /* R2505 - DSP3RMIX Input 1 Volume */
{ 0x000009CA, 0x0000 }, /* R2506 - DSP3RMIX Input 2 Source */
{ 0x000009CB, 0x0080 }, /* R2507 - DSP3RMIX Input 2 Volume */
{ 0x000009CC, 0x0000 }, /* R2508 - DSP3RMIX Input 3 Source */
{ 0x000009CD, 0x0080 }, /* R2509 - DSP3RMIX Input 3 Volume */
{ 0x000009CE, 0x0000 }, /* R2510 - DSP3RMIX Input 4 Source */
{ 0x000009CF, 0x0080 }, /* R2511 - DSP3RMIX Input 4 Volume */
{ 0x000009D0, 0x0000 }, /* R2512 - DSP3AUX1MIX Input 1 Source */
{ 0x000009D8, 0x0000 }, /* R2520 - DSP3AUX2MIX Input 1 Source */
{ 0x000009E0, 0x0000 }, /* R2528 - DSP3AUX3MIX Input 1 Source */
{ 0x000009E8, 0x0000 }, /* R2536 - DSP3AUX4MIX Input 1 Source */
{ 0x000009F0, 0x0000 }, /* R2544 - DSP3AUX5MIX Input 1 Source */
{ 0x000009F8, 0x0000 }, /* R2552 - DSP3AUX6MIX Input 1 Source */
{ 0x00000A80, 0x0000 }, /* R2688 - ASRC1LMIX Input 1 Source */
{ 0x00000A88, 0x0000 }, /* R2696 - ASRC1RMIX Input 1 Source */
{ 0x00000A90, 0x0000 }, /* R2704 - ASRC2LMIX Input 1 Source */
{ 0x00000A98, 0x0000 }, /* R2712 - ASRC2RMIX Input 1 Source */
{ 0x00000B00, 0x0000 }, /* R2816 - ISRC1DEC1MIX Input 1 Source */
{ 0x00000B08, 0x0000 }, /* R2824 - ISRC1DEC2MIX Input 1 Source */
{ 0x00000B10, 0x0000 }, /* R2832 - ISRC1DEC3MIX Input 1 Source */
{ 0x00000B18, 0x0000 }, /* R2840 - ISRC1DEC4MIX Input 1 Source */
{ 0x00000B20, 0x0000 }, /* R2848 - ISRC1INT1MIX Input 1 Source */
{ 0x00000B28, 0x0000 }, /* R2856 - ISRC1INT2MIX Input 1 Source */
{ 0x00000B30, 0x0000 }, /* R2864 - ISRC1INT3MIX Input 1 Source */
{ 0x00000B38, 0x0000 }, /* R2872 - ISRC1INT4MIX Input 1 Source */
{ 0x00000B40, 0x0000 }, /* R2880 - ISRC2DEC1MIX Input 1 Source */
{ 0x00000B48, 0x0000 }, /* R2888 - ISRC2DEC2MIX Input 1 Source */
{ 0x00000B50, 0x0000 }, /* R2896 - ISRC2DEC3MIX Input 1 Source */
{ 0x00000B58, 0x0000 }, /* R2904 - ISRC2DEC4MIX Input 1 Source */
{ 0x00000B60, 0x0000 }, /* R2912 - ISRC2INT1MIX Input 1 Source */
{ 0x00000B68, 0x0000 }, /* R2920 - ISRC2INT2MIX Input 1 Source */
{ 0x00000B70, 0x0000 }, /* R2928 - ISRC2INT3MIX Input 1 Source */
{ 0x00000B78, 0x0000 }, /* R2936 - ISRC2INT4MIX Input 1 Source */
{ 0x00000B80, 0x0000 }, /* R2944 - ISRC3DEC1MIX Input 1 Source */
{ 0x00000B88, 0x0000 }, /* R2952 - ISRC3DEC2MIX Input 1 Source */
{ 0x00000B90, 0x0000 }, /* R2960 - ISRC3DEC3MIX Input 1 Source */
{ 0x00000B98, 0x0000 }, /* R2968 - ISRC3DEC4MIX Input 1 Source */
{ 0x00000BA0, 0x0000 }, /* R2976 - ISRC3INT1MIX Input 1 Source */
{ 0x00000BA8, 0x0000 }, /* R2984 - ISRC3INT2MIX Input 1 Source */
{ 0x00000BB0, 0x0000 }, /* R2992 - ISRC3INT3MIX Input 1 Source */
{ 0x00000BB8, 0x0000 }, /* R3000 - ISRC3INT4MIX Input 1 Source */
{ 0x00000C00, 0xA101 }, /* R3072 - GPIO1 CTRL */
{ 0x00000C01, 0xA101 }, /* R3073 - GPIO2 CTRL */
{ 0x00000C0F, 0x0400 }, /* R3087 - IRQ CTRL 1 */
{ 0x00000C10, 0x1000 }, /* R3088 - GPIO Debounce Config */
{ 0x00000C20, 0x0002 }, /* R3104 - Misc Pad Ctrl 1 */
{ 0x00000C21, 0x0000 }, /* R3105 - Misc Pad Ctrl 2 */
{ 0x00000C22, 0x0000 }, /* R3106 - Misc Pad Ctrl 3 */
{ 0x00000C23, 0x0000 }, /* R3107 - Misc Pad Ctrl 4 */
{ 0x00000C24, 0x0000 }, /* R3108 - Misc Pad Ctrl 5 */
{ 0x00000C25, 0x0000 }, /* R3109 - Misc Pad Ctrl 6 */
{ 0x00000C30, 0x0404 }, /* R3120 - Misc Pad Ctrl 7 */
{ 0x00000C32, 0x0404 }, /* R3122 - Misc Pad Ctrl 9 */
{ 0x00000C33, 0x0404 }, /* R3123 - Misc Pad Ctrl 10 */
{ 0x00000C34, 0x0404 }, /* R3124 - Misc Pad Ctrl 11 */
{ 0x00000C35, 0x0404 }, /* R3125 - Misc Pad Ctrl 12 */
{ 0x00000C36, 0x0400 }, /* R3126 - Misc Pad Ctrl 13 */
{ 0x00000C37, 0x0404 }, /* R3127 - Misc Pad Ctrl 14 */
{ 0x00000C39, 0x0400 }, /* R3129 - Misc Pad Ctrl 16 */
{ 0x00000D08, 0x0007 }, /* R3336 - Interrupt Status 1 Mask */
{ 0x00000D09, 0x06FF }, /* R3337 - Interrupt Status 2 Mask */
{ 0x00000D0A, 0xCFEF }, /* R3338 - Interrupt Status 3 Mask */
{ 0x00000D0B, 0xFFC3 }, /* R3339 - Interrupt Status 4 Mask */
{ 0x00000D0C, 0x000B }, /* R3340 - Interrupt Status 5 Mask */
{ 0x00000D0D, 0xD005 }, /* R3341 - Interrupt Status 6 Mask */
{ 0x00000D0F, 0x0000 }, /* R3343 - Interrupt Control */
{ 0x00000D18, 0x0007 }, /* R3352 - IRQ2 Status 1 Mask */
{ 0x00000D19, 0x06FF }, /* R3353 - IRQ2 Status 2 Mask */
{ 0x00000D1A, 0xCFEF }, /* R3354 - IRQ2 Status 3 Mask */
{ 0x00000D1B, 0xFFC3 }, /* R3355 - IRQ2 Status 4 Mask */
{ 0x00000D1C, 0x000B }, /* R3356 - IRQ2 Status 5 Mask */
{ 0x00000D1D, 0xD005 }, /* R3357 - IRQ2 Status 6 Mask */
{ 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */
{ 0x00000E00, 0x0000 }, /* R3584 - FX_Ctrl1 */
{ 0x00000E10, 0x6318 }, /* R3600 - EQ1_1 */
{ 0x00000E11, 0x6300 }, /* R3601 - EQ1_2 */
{ 0x00000E12, 0x0FC8 }, /* R3602 - EQ1_3 */
{ 0x00000E13, 0x03FE }, /* R3603 - EQ1_4 */
{ 0x00000E14, 0x00E0 }, /* R3604 - EQ1_5 */
{ 0x00000E15, 0x1EC4 }, /* R3605 - EQ1_6 */
{ 0x00000E16, 0xF136 }, /* R3606 - EQ1_7 */
{ 0x00000E17, 0x0409 }, /* R3607 - EQ1_8 */
{ 0x00000E18, 0x04CC }, /* R3608 - EQ1_9 */
{ 0x00000E19, 0x1C9B }, /* R3609 - EQ1_10 */
{ 0x00000E1A, 0xF337 }, /* R3610 - EQ1_11 */
{ 0x00000E1B, 0x040B }, /* R3611 - EQ1_12 */
{ 0x00000E1C, 0x0CBB }, /* R3612 - EQ1_13 */
{ 0x00000E1D, 0x16F8 }, /* R3613 - EQ1_14 */
{ 0x00000E1E, 0xF7D9 }, /* R3614 - EQ1_15 */
{ 0x00000E1F, 0x040A }, /* R3615 - EQ1_16 */
{ 0x00000E20, 0x1F14 }, /* R3616 - EQ1_17 */
{ 0x00000E21, 0x058C }, /* R3617 - EQ1_18 */
{ 0x00000E22, 0x0563 }, /* R3618 - EQ1_19 */
{ 0x00000E23, 0x4000 }, /* R3619 - EQ1_20 */
{ 0x00000E24, 0x0B75 }, /* R3620 - EQ1_21 */
{ 0x00000E26, 0x6318 }, /* R3622 - EQ2_1 */
{ 0x00000E27, 0x6300 }, /* R3623 - EQ2_2 */
{ 0x00000E28, 0x0FC8 }, /* R3624 - EQ2_3 */
{ 0x00000E29, 0x03FE }, /* R3625 - EQ2_4 */
{ 0x00000E2A, 0x00E0 }, /* R3626 - EQ2_5 */
{ 0x00000E2B, 0x1EC4 }, /* R3627 - EQ2_6 */
{ 0x00000E2C, 0xF136 }, /* R3628 - EQ2_7 */
{ 0x00000E2D, 0x0409 }, /* R3629 - EQ2_8 */
{ 0x00000E2E, 0x04CC }, /* R3630 - EQ2_9 */
{ 0x00000E2F, 0x1C9B }, /* R3631 - EQ2_10 */
{ 0x00000E30, 0xF337 }, /* R3632 - EQ2_11 */
{ 0x00000E31, 0x040B }, /* R3633 - EQ2_12 */
{ 0x00000E32, 0x0CBB }, /* R3634 - EQ2_13 */
{ 0x00000E33, 0x16F8 }, /* R3635 - EQ2_14 */
{ 0x00000E34, 0xF7D9 }, /* R3636 - EQ2_15 */
{ 0x00000E35, 0x040A }, /* R3637 - EQ2_16 */
{ 0x00000E36, 0x1F14 }, /* R3638 - EQ2_17 */
{ 0x00000E37, 0x058C }, /* R3639 - EQ2_18 */
{ 0x00000E38, 0x0563 }, /* R3640 - EQ2_19 */
{ 0x00000E39, 0x4000 }, /* R3641 - EQ2_20 */
{ 0x00000E3A, 0x0B75 }, /* R3642 - EQ2_21 */
{ 0x00000E80, 0x0018 }, /* R3712 - DRC1 ctrl1 */
{ 0x00000E81, 0x0933 }, /* R3713 - DRC1 ctrl2 */
{ 0x00000E82, 0x0018 }, /* R3714 - DRC1 ctrl3 */
{ 0x00000E83, 0x0000 }, /* R3715 - DRC1 ctrl4 */
{ 0x00000E84, 0x0000 }, /* R3716 - DRC1 ctrl5 */
{ 0x00000E89, 0x0018 }, /* R3721 - DRC2 ctrl1 */
{ 0x00000E8A, 0x0933 }, /* R3722 - DRC2 ctrl2 */
{ 0x00000E8B, 0x0018 }, /* R3723 - DRC2 ctrl3 */
{ 0x00000E8C, 0x0000 }, /* R3724 - DRC2 ctrl4 */
{ 0x00000E8D, 0x0000 }, /* R3725 - DRC2 ctrl5 */
{ 0x00000EC0, 0x0000 }, /* R3776 - HPLPF1_1 */
{ 0x00000EC1, 0x0000 }, /* R3777 - HPLPF1_2 */
{ 0x00000EC4, 0x0000 }, /* R3780 - HPLPF2_1 */
{ 0x00000EC5, 0x0000 }, /* R3781 - HPLPF2_2 */
{ 0x00000EC8, 0x0000 }, /* R3784 - HPLPF3_1 */
{ 0x00000EC9, 0x0000 }, /* R3785 - HPLPF3_2 */
{ 0x00000ECC, 0x0000 }, /* R3788 - HPLPF4_1 */
{ 0x00000ECD, 0x0000 }, /* R3789 - HPLPF4_2 */
{ 0x00000EE0, 0x0000 }, /* R3808 - ASRC_ENABLE */
{ 0x00000EE2, 0x0000 }, /* R3810 - ASRC_RATE1 */
{ 0x00000EE3, 0x4000 }, /* R3811 - ASRC_RATE2 */
{ 0x00000EF0, 0x0000 }, /* R3824 - ISRC 1 CTRL 1 */
{ 0x00000EF1, 0x0000 }, /* R3825 - ISRC 1 CTRL 2 */
{ 0x00000EF2, 0x0000 }, /* R3826 - ISRC 1 CTRL 3 */
{ 0x00000EF3, 0x0000 }, /* R3827 - ISRC 2 CTRL 1 */
{ 0x00000EF4, 0x0000 }, /* R3828 - ISRC 2 CTRL 2 */
{ 0x00000EF5, 0x0000 }, /* R3829 - ISRC 2 CTRL 3 */
{ 0x00000EF6, 0x0000 }, /* R3830 - ISRC 3 CTRL 1 */
{ 0x00000EF7, 0x0000 }, /* R3831 - ISRC 3 CTRL 2 */
{ 0x00000EF8, 0x0000 }, /* R3832 - ISRC 3 CTRL 3 */
{ 0x00001200, 0x0010 }, /* R4608 - DSP2 Control 1 */
{ 0x00001300, 0x0010 }, /* R4864 - DSP3 Control 1 */
};
static bool cs47l24_is_adsp_memory(unsigned int reg)
{
switch (reg) {
case 0x200000 ... 0x205fff: /* DSP2 PM */
case 0x280000 ... 0x281fff: /* DSP2 ZM */
case 0x290000 ... 0x2a7fff: /* DSP2 XM */
case 0x2a8000 ... 0x2b3fff: /* DSP2 YM */
case 0x300000 ... 0x308fff: /* DSP3 PM */
case 0x380000 ... 0x381fff: /* DSP3 ZM */
case 0x390000 ... 0x3a7fff: /* DSP3 XM */
case 0x3a8000 ... 0x3b3fff: /* DSP3 YM */
return true;
default:
return false;
}
}
static bool cs47l24_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case ARIZONA_SOFTWARE_RESET:
case ARIZONA_DEVICE_REVISION:
case ARIZONA_CTRL_IF_SPI_CFG_1:
case ARIZONA_WRITE_SEQUENCER_CTRL_0:
case ARIZONA_WRITE_SEQUENCER_CTRL_1:
case ARIZONA_WRITE_SEQUENCER_CTRL_2:
case ARIZONA_TONE_GENERATOR_1:
case ARIZONA_TONE_GENERATOR_2:
case ARIZONA_TONE_GENERATOR_3:
case ARIZONA_TONE_GENERATOR_4:
case ARIZONA_TONE_GENERATOR_5:
case ARIZONA_PWM_DRIVE_1:
case ARIZONA_PWM_DRIVE_2:
case ARIZONA_PWM_DRIVE_3:
case ARIZONA_SEQUENCE_CONTROL:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4:
case ARIZONA_COMFORT_NOISE_GENERATOR:
case ARIZONA_HAPTICS_CONTROL_1:
case ARIZONA_HAPTICS_CONTROL_2:
case ARIZONA_HAPTICS_PHASE_1_INTENSITY:
case ARIZONA_HAPTICS_PHASE_1_DURATION:
case ARIZONA_HAPTICS_PHASE_2_INTENSITY:
case ARIZONA_HAPTICS_PHASE_2_DURATION:
case ARIZONA_HAPTICS_PHASE_3_INTENSITY:
case ARIZONA_HAPTICS_PHASE_3_DURATION:
case ARIZONA_HAPTICS_STATUS:
case ARIZONA_CLOCK_32K_1:
case ARIZONA_SYSTEM_CLOCK_1:
case ARIZONA_SAMPLE_RATE_1:
case ARIZONA_SAMPLE_RATE_2:
case ARIZONA_SAMPLE_RATE_3:
case ARIZONA_SAMPLE_RATE_1_STATUS:
case ARIZONA_SAMPLE_RATE_2_STATUS:
case ARIZONA_SAMPLE_RATE_3_STATUS:
case ARIZONA_ASYNC_CLOCK_1:
case ARIZONA_ASYNC_SAMPLE_RATE_1:
case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
case ARIZONA_ASYNC_SAMPLE_RATE_2:
case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS:
case ARIZONA_OUTPUT_SYSTEM_CLOCK:
case ARIZONA_OUTPUT_ASYNC_CLOCK:
case ARIZONA_RATE_ESTIMATOR_1:
case ARIZONA_RATE_ESTIMATOR_2:
case ARIZONA_RATE_ESTIMATOR_3:
case ARIZONA_RATE_ESTIMATOR_4:
case ARIZONA_RATE_ESTIMATOR_5:
case ARIZONA_FLL1_CONTROL_1:
case ARIZONA_FLL1_CONTROL_2:
case ARIZONA_FLL1_CONTROL_3:
case ARIZONA_FLL1_CONTROL_4:
case ARIZONA_FLL1_CONTROL_5:
case ARIZONA_FLL1_CONTROL_6:
case ARIZONA_FLL1_CONTROL_7:
case ARIZONA_FLL1_SYNCHRONISER_1:
case ARIZONA_FLL1_SYNCHRONISER_2:
case ARIZONA_FLL1_SYNCHRONISER_3:
case ARIZONA_FLL1_SYNCHRONISER_4:
case ARIZONA_FLL1_SYNCHRONISER_5:
case ARIZONA_FLL1_SYNCHRONISER_6:
case ARIZONA_FLL1_SYNCHRONISER_7:
case ARIZONA_FLL1_SPREAD_SPECTRUM:
case ARIZONA_FLL1_GPIO_CLOCK:
case ARIZONA_FLL2_CONTROL_1:
case ARIZONA_FLL2_CONTROL_2:
case ARIZONA_FLL2_CONTROL_3:
case ARIZONA_FLL2_CONTROL_4:
case ARIZONA_FLL2_CONTROL_5:
case ARIZONA_FLL2_CONTROL_6:
case ARIZONA_FLL2_CONTROL_7:
case ARIZONA_FLL2_SYNCHRONISER_1:
case ARIZONA_FLL2_SYNCHRONISER_2:
case ARIZONA_FLL2_SYNCHRONISER_3:
case ARIZONA_FLL2_SYNCHRONISER_4:
case ARIZONA_FLL2_SYNCHRONISER_5:
case ARIZONA_FLL2_SYNCHRONISER_6:
case ARIZONA_FLL2_SYNCHRONISER_7:
case ARIZONA_FLL2_SPREAD_SPECTRUM:
case ARIZONA_FLL2_GPIO_CLOCK:
case ARIZONA_MIC_BIAS_CTRL_1:
case ARIZONA_MIC_BIAS_CTRL_2:
case ARIZONA_HP_CTRL_1L:
case ARIZONA_HP_CTRL_1R:
case ARIZONA_INPUT_ENABLES:
case ARIZONA_INPUT_ENABLES_STATUS:
case ARIZONA_INPUT_RATE:
case ARIZONA_INPUT_VOLUME_RAMP:
case ARIZONA_HPF_CONTROL:
case ARIZONA_IN1L_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_1L:
case ARIZONA_DMIC1L_CONTROL:
case ARIZONA_IN1R_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_1R:
case ARIZONA_DMIC1R_CONTROL:
case ARIZONA_IN2L_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_2L:
case ARIZONA_DMIC2L_CONTROL:
case ARIZONA_IN2R_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_2R:
case ARIZONA_DMIC2R_CONTROL:
case ARIZONA_OUTPUT_ENABLES_1:
case ARIZONA_OUTPUT_STATUS_1:
case ARIZONA_RAW_OUTPUT_STATUS_1:
case ARIZONA_OUTPUT_RATE_1:
case ARIZONA_OUTPUT_VOLUME_RAMP:
case ARIZONA_OUTPUT_PATH_CONFIG_1L:
case ARIZONA_DAC_DIGITAL_VOLUME_1L:
case ARIZONA_DAC_VOLUME_LIMIT_1L:
case ARIZONA_NOISE_GATE_SELECT_1L:
case ARIZONA_DAC_DIGITAL_VOLUME_1R:
case ARIZONA_DAC_VOLUME_LIMIT_1R:
case ARIZONA_NOISE_GATE_SELECT_1R:
case ARIZONA_DAC_DIGITAL_VOLUME_4L:
case ARIZONA_OUT_VOLUME_4L:
case ARIZONA_NOISE_GATE_SELECT_4L:
case ARIZONA_DAC_AEC_CONTROL_1:
case ARIZONA_NOISE_GATE_CONTROL:
case ARIZONA_HP1_SHORT_CIRCUIT_CTRL:
case ARIZONA_AIF1_BCLK_CTRL:
case ARIZONA_AIF1_TX_PIN_CTRL:
case ARIZONA_AIF1_RX_PIN_CTRL:
case ARIZONA_AIF1_RATE_CTRL:
case ARIZONA_AIF1_FORMAT:
case ARIZONA_AIF1_TX_BCLK_RATE:
case ARIZONA_AIF1_RX_BCLK_RATE:
case ARIZONA_AIF1_FRAME_CTRL_1:
case ARIZONA_AIF1_FRAME_CTRL_2:
case ARIZONA_AIF1_FRAME_CTRL_3:
case ARIZONA_AIF1_FRAME_CTRL_4:
case ARIZONA_AIF1_FRAME_CTRL_5:
case ARIZONA_AIF1_FRAME_CTRL_6:
case ARIZONA_AIF1_FRAME_CTRL_7:
case ARIZONA_AIF1_FRAME_CTRL_8:
case ARIZONA_AIF1_FRAME_CTRL_9:
case ARIZONA_AIF1_FRAME_CTRL_10:
case ARIZONA_AIF1_FRAME_CTRL_11:
case ARIZONA_AIF1_FRAME_CTRL_12:
case ARIZONA_AIF1_FRAME_CTRL_13:
case ARIZONA_AIF1_FRAME_CTRL_14:
case ARIZONA_AIF1_FRAME_CTRL_15:
case ARIZONA_AIF1_FRAME_CTRL_16:
case ARIZONA_AIF1_FRAME_CTRL_17:
case ARIZONA_AIF1_FRAME_CTRL_18:
case ARIZONA_AIF1_TX_ENABLES:
case ARIZONA_AIF1_RX_ENABLES:
case ARIZONA_AIF2_BCLK_CTRL:
case ARIZONA_AIF2_TX_PIN_CTRL:
case ARIZONA_AIF2_RX_PIN_CTRL:
case ARIZONA_AIF2_RATE_CTRL:
case ARIZONA_AIF2_FORMAT:
case ARIZONA_AIF2_TX_BCLK_RATE:
case ARIZONA_AIF2_RX_BCLK_RATE:
case ARIZONA_AIF2_FRAME_CTRL_1:
case ARIZONA_AIF2_FRAME_CTRL_2:
case ARIZONA_AIF2_FRAME_CTRL_3:
case ARIZONA_AIF2_FRAME_CTRL_4:
case ARIZONA_AIF2_FRAME_CTRL_5:
case ARIZONA_AIF2_FRAME_CTRL_6:
case ARIZONA_AIF2_FRAME_CTRL_7:
case ARIZONA_AIF2_FRAME_CTRL_8:
case ARIZONA_AIF2_FRAME_CTRL_11:
case ARIZONA_AIF2_FRAME_CTRL_12:
case ARIZONA_AIF2_FRAME_CTRL_13:
case ARIZONA_AIF2_FRAME_CTRL_14:
case ARIZONA_AIF2_FRAME_CTRL_15:
case ARIZONA_AIF2_FRAME_CTRL_16:
case ARIZONA_AIF2_TX_ENABLES:
case ARIZONA_AIF2_RX_ENABLES:
case ARIZONA_AIF3_BCLK_CTRL:
case ARIZONA_AIF3_TX_PIN_CTRL:
case ARIZONA_AIF3_RX_PIN_CTRL:
case ARIZONA_AIF3_RATE_CTRL:
case ARIZONA_AIF3_FORMAT:
case ARIZONA_AIF3_TX_BCLK_RATE:
case ARIZONA_AIF3_RX_BCLK_RATE:
case ARIZONA_AIF3_FRAME_CTRL_1:
case ARIZONA_AIF3_FRAME_CTRL_2:
case ARIZONA_AIF3_FRAME_CTRL_3:
case ARIZONA_AIF3_FRAME_CTRL_4:
case ARIZONA_AIF3_FRAME_CTRL_11:
case ARIZONA_AIF3_FRAME_CTRL_12:
case ARIZONA_AIF3_TX_ENABLES:
case ARIZONA_AIF3_RX_ENABLES:
case ARIZONA_PWM1MIX_INPUT_1_SOURCE:
case ARIZONA_PWM1MIX_INPUT_1_VOLUME:
case ARIZONA_PWM1MIX_INPUT_2_SOURCE:
case ARIZONA_PWM1MIX_INPUT_2_VOLUME:
case ARIZONA_PWM1MIX_INPUT_3_SOURCE:
case ARIZONA_PWM1MIX_INPUT_3_VOLUME:
case ARIZONA_PWM1MIX_INPUT_4_SOURCE:
case ARIZONA_PWM1MIX_INPUT_4_VOLUME:
case ARIZONA_PWM2MIX_INPUT_1_SOURCE:
case ARIZONA_PWM2MIX_INPUT_1_VOLUME:
case ARIZONA_PWM2MIX_INPUT_2_SOURCE:
case ARIZONA_PWM2MIX_INPUT_2_VOLUME:
case ARIZONA_PWM2MIX_INPUT_3_SOURCE:
case ARIZONA_PWM2MIX_INPUT_3_VOLUME:
case ARIZONA_PWM2MIX_INPUT_4_SOURCE:
case ARIZONA_PWM2MIX_INPUT_4_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_4_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME:
case ARIZONA_EQ1MIX_INPUT_1_SOURCE:
case ARIZONA_EQ1MIX_INPUT_1_VOLUME:
case ARIZONA_EQ1MIX_INPUT_2_SOURCE:
case ARIZONA_EQ1MIX_INPUT_2_VOLUME:
case ARIZONA_EQ1MIX_INPUT_3_SOURCE:
case ARIZONA_EQ1MIX_INPUT_3_VOLUME:
case ARIZONA_EQ1MIX_INPUT_4_SOURCE:
case ARIZONA_EQ1MIX_INPUT_4_VOLUME:
case ARIZONA_EQ2MIX_INPUT_1_SOURCE:
case ARIZONA_EQ2MIX_INPUT_1_VOLUME:
case ARIZONA_EQ2MIX_INPUT_2_SOURCE:
case ARIZONA_EQ2MIX_INPUT_2_VOLUME:
case ARIZONA_EQ2MIX_INPUT_3_SOURCE:
case ARIZONA_EQ2MIX_INPUT_3_VOLUME:
case ARIZONA_EQ2MIX_INPUT_4_SOURCE:
case ARIZONA_EQ2MIX_INPUT_4_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_1_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_1_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_2_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_2_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_3_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_3_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_4_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_4_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_1_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_1_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_2_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_2_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_3_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_3_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_4_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_4_VOLUME:
case ARIZONA_DRC2LMIX_INPUT_1_SOURCE:
case ARIZONA_DRC2LMIX_INPUT_1_VOLUME:
case ARIZONA_DRC2LMIX_INPUT_2_SOURCE:
case ARIZONA_DRC2LMIX_INPUT_2_VOLUME:
case ARIZONA_DRC2LMIX_INPUT_3_SOURCE:
case ARIZONA_DRC2LMIX_INPUT_3_VOLUME:
case ARIZONA_DRC2LMIX_INPUT_4_SOURCE:
case ARIZONA_DRC2LMIX_INPUT_4_VOLUME:
case ARIZONA_DRC2RMIX_INPUT_1_SOURCE:
case ARIZONA_DRC2RMIX_INPUT_1_VOLUME:
case ARIZONA_DRC2RMIX_INPUT_2_SOURCE:
case ARIZONA_DRC2RMIX_INPUT_2_VOLUME:
case ARIZONA_DRC2RMIX_INPUT_3_SOURCE:
case ARIZONA_DRC2RMIX_INPUT_3_VOLUME:
case ARIZONA_DRC2RMIX_INPUT_4_SOURCE:
case ARIZONA_DRC2RMIX_INPUT_4_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_4_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_4_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_4_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_4_VOLUME:
case ARIZONA_DSP2LMIX_INPUT_1_SOURCE:
case ARIZONA_DSP2LMIX_INPUT_1_VOLUME:
case ARIZONA_DSP2LMIX_INPUT_2_SOURCE:
case ARIZONA_DSP2LMIX_INPUT_2_VOLUME:
case ARIZONA_DSP2LMIX_INPUT_3_SOURCE:
case ARIZONA_DSP2LMIX_INPUT_3_VOLUME:
case ARIZONA_DSP2LMIX_INPUT_4_SOURCE:
case ARIZONA_DSP2LMIX_INPUT_4_VOLUME:
case ARIZONA_DSP2RMIX_INPUT_1_SOURCE:
case ARIZONA_DSP2RMIX_INPUT_1_VOLUME:
case ARIZONA_DSP2RMIX_INPUT_2_SOURCE:
case ARIZONA_DSP2RMIX_INPUT_2_VOLUME:
case ARIZONA_DSP2RMIX_INPUT_3_SOURCE:
case ARIZONA_DSP2RMIX_INPUT_3_VOLUME:
case ARIZONA_DSP2RMIX_INPUT_4_SOURCE:
case ARIZONA_DSP2RMIX_INPUT_4_VOLUME:
case ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE:
case ARIZONA_DSP2AUX2MIX_INPUT_1_SOURCE:
case ARIZONA_DSP2AUX3MIX_INPUT_1_SOURCE:
case ARIZONA_DSP2AUX4MIX_INPUT_1_SOURCE:
case ARIZONA_DSP2AUX5MIX_INPUT_1_SOURCE:
case ARIZONA_DSP2AUX6MIX_INPUT_1_SOURCE:
case ARIZONA_DSP3LMIX_INPUT_1_SOURCE:
case ARIZONA_DSP3LMIX_INPUT_1_VOLUME:
case ARIZONA_DSP3LMIX_INPUT_2_SOURCE:
case ARIZONA_DSP3LMIX_INPUT_2_VOLUME:
case ARIZONA_DSP3LMIX_INPUT_3_SOURCE:
case ARIZONA_DSP3LMIX_INPUT_3_VOLUME:
case ARIZONA_DSP3LMIX_INPUT_4_SOURCE:
case ARIZONA_DSP3LMIX_INPUT_4_VOLUME:
case ARIZONA_DSP3RMIX_INPUT_1_SOURCE:
case ARIZONA_DSP3RMIX_INPUT_1_VOLUME:
case ARIZONA_DSP3RMIX_INPUT_2_SOURCE:
case ARIZONA_DSP3RMIX_INPUT_2_VOLUME:
case ARIZONA_DSP3RMIX_INPUT_3_SOURCE:
case ARIZONA_DSP3RMIX_INPUT_3_VOLUME:
case ARIZONA_DSP3RMIX_INPUT_4_SOURCE:
case ARIZONA_DSP3RMIX_INPUT_4_VOLUME:
case ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE:
case ARIZONA_DSP3AUX2MIX_INPUT_1_SOURCE:
case ARIZONA_DSP3AUX3MIX_INPUT_1_SOURCE:
case ARIZONA_DSP3AUX4MIX_INPUT_1_SOURCE:
case ARIZONA_DSP3AUX5MIX_INPUT_1_SOURCE:
case ARIZONA_DSP3AUX6MIX_INPUT_1_SOURCE:
case ARIZONA_ASRC1LMIX_INPUT_1_SOURCE:
case ARIZONA_ASRC1RMIX_INPUT_1_SOURCE:
case ARIZONA_ASRC2LMIX_INPUT_1_SOURCE:
case ARIZONA_ASRC2RMIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3DEC3MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3DEC4MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3INT3MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC3INT4MIX_INPUT_1_SOURCE:
case ARIZONA_GPIO1_CTRL:
case ARIZONA_GPIO2_CTRL:
case ARIZONA_IRQ_CTRL_1:
case ARIZONA_GPIO_DEBOUNCE_CONFIG:
case ARIZONA_MISC_PAD_CTRL_1:
case ARIZONA_MISC_PAD_CTRL_2:
case ARIZONA_MISC_PAD_CTRL_3:
case ARIZONA_MISC_PAD_CTRL_4:
case ARIZONA_MISC_PAD_CTRL_5:
case ARIZONA_MISC_PAD_CTRL_6:
case ARIZONA_MISC_PAD_CTRL_7:
case ARIZONA_MISC_PAD_CTRL_9:
case ARIZONA_MISC_PAD_CTRL_10:
case ARIZONA_MISC_PAD_CTRL_11:
case ARIZONA_MISC_PAD_CTRL_12:
case ARIZONA_MISC_PAD_CTRL_13:
case ARIZONA_MISC_PAD_CTRL_14:
case ARIZONA_MISC_PAD_CTRL_16:
case ARIZONA_INTERRUPT_STATUS_1:
case ARIZONA_INTERRUPT_STATUS_2:
case ARIZONA_INTERRUPT_STATUS_3:
case ARIZONA_INTERRUPT_STATUS_4:
case ARIZONA_INTERRUPT_STATUS_5:
case ARIZONA_INTERRUPT_STATUS_6:
case ARIZONA_INTERRUPT_STATUS_1_MASK:
case ARIZONA_INTERRUPT_STATUS_2_MASK:
case ARIZONA_INTERRUPT_STATUS_3_MASK:
case ARIZONA_INTERRUPT_STATUS_4_MASK:
case ARIZONA_INTERRUPT_STATUS_5_MASK:
case ARIZONA_INTERRUPT_STATUS_6_MASK:
case ARIZONA_INTERRUPT_CONTROL:
case ARIZONA_IRQ2_STATUS_1:
case ARIZONA_IRQ2_STATUS_2:
case ARIZONA_IRQ2_STATUS_3:
case ARIZONA_IRQ2_STATUS_4:
case ARIZONA_IRQ2_STATUS_5:
case ARIZONA_IRQ2_STATUS_6:
case ARIZONA_IRQ2_STATUS_1_MASK:
case ARIZONA_IRQ2_STATUS_2_MASK:
case ARIZONA_IRQ2_STATUS_3_MASK:
case ARIZONA_IRQ2_STATUS_4_MASK:
case ARIZONA_IRQ2_STATUS_5_MASK:
case ARIZONA_IRQ2_STATUS_6_MASK:
case ARIZONA_IRQ2_CONTROL:
case ARIZONA_INTERRUPT_RAW_STATUS_2:
case ARIZONA_INTERRUPT_RAW_STATUS_3:
case ARIZONA_INTERRUPT_RAW_STATUS_4:
case ARIZONA_INTERRUPT_RAW_STATUS_5:
case ARIZONA_INTERRUPT_RAW_STATUS_6:
case ARIZONA_INTERRUPT_RAW_STATUS_7:
case ARIZONA_INTERRUPT_RAW_STATUS_8:
case ARIZONA_INTERRUPT_RAW_STATUS_9:
case ARIZONA_IRQ_PIN_STATUS:
case ARIZONA_FX_CTRL1:
case ARIZONA_FX_CTRL2:
case ARIZONA_EQ1_1:
case ARIZONA_EQ1_2:
case ARIZONA_EQ1_3:
case ARIZONA_EQ1_4:
case ARIZONA_EQ1_5:
case ARIZONA_EQ1_6:
case ARIZONA_EQ1_7:
case ARIZONA_EQ1_8:
case ARIZONA_EQ1_9:
case ARIZONA_EQ1_10:
case ARIZONA_EQ1_11:
case ARIZONA_EQ1_12:
case ARIZONA_EQ1_13:
case ARIZONA_EQ1_14:
case ARIZONA_EQ1_15:
case ARIZONA_EQ1_16:
case ARIZONA_EQ1_17:
case ARIZONA_EQ1_18:
case ARIZONA_EQ1_19:
case ARIZONA_EQ1_20:
case ARIZONA_EQ1_21:
case ARIZONA_EQ2_1:
case ARIZONA_EQ2_2:
case ARIZONA_EQ2_3:
case ARIZONA_EQ2_4:
case ARIZONA_EQ2_5:
case ARIZONA_EQ2_6:
case ARIZONA_EQ2_7:
case ARIZONA_EQ2_8:
case ARIZONA_EQ2_9:
case ARIZONA_EQ2_10:
case ARIZONA_EQ2_11:
case ARIZONA_EQ2_12:
case ARIZONA_EQ2_13:
case ARIZONA_EQ2_14:
case ARIZONA_EQ2_15:
case ARIZONA_EQ2_16:
case ARIZONA_EQ2_17:
case ARIZONA_EQ2_18:
case ARIZONA_EQ2_19:
case ARIZONA_EQ2_20:
case ARIZONA_EQ2_21:
case ARIZONA_DRC1_CTRL1:
case ARIZONA_DRC1_CTRL2:
case ARIZONA_DRC1_CTRL3:
case ARIZONA_DRC1_CTRL4:
case ARIZONA_DRC1_CTRL5:
case ARIZONA_DRC2_CTRL1:
case ARIZONA_DRC2_CTRL2:
case ARIZONA_DRC2_CTRL3:
case ARIZONA_DRC2_CTRL4:
case ARIZONA_DRC2_CTRL5:
case ARIZONA_HPLPF1_1:
case ARIZONA_HPLPF1_2:
case ARIZONA_HPLPF2_1:
case ARIZONA_HPLPF2_2:
case ARIZONA_HPLPF3_1:
case ARIZONA_HPLPF3_2:
case ARIZONA_HPLPF4_1:
case ARIZONA_HPLPF4_2:
case ARIZONA_ASRC_ENABLE:
case ARIZONA_ASRC_STATUS:
case ARIZONA_ASRC_RATE1:
case ARIZONA_ASRC_RATE2:
case ARIZONA_ISRC_1_CTRL_1:
case ARIZONA_ISRC_1_CTRL_2:
case ARIZONA_ISRC_1_CTRL_3:
case ARIZONA_ISRC_2_CTRL_1:
case ARIZONA_ISRC_2_CTRL_2:
case ARIZONA_ISRC_2_CTRL_3:
case ARIZONA_ISRC_3_CTRL_1:
case ARIZONA_ISRC_3_CTRL_2:
case ARIZONA_ISRC_3_CTRL_3:
case ARIZONA_DSP2_CONTROL_1:
case ARIZONA_DSP2_CLOCKING_1:
case ARIZONA_DSP2_STATUS_1:
case ARIZONA_DSP2_STATUS_2:
case ARIZONA_DSP2_STATUS_3:
case ARIZONA_DSP2_STATUS_4:
case ARIZONA_DSP2_WDMA_BUFFER_1:
case ARIZONA_DSP2_WDMA_BUFFER_2:
case ARIZONA_DSP2_WDMA_BUFFER_3:
case ARIZONA_DSP2_WDMA_BUFFER_4:
case ARIZONA_DSP2_WDMA_BUFFER_5:
case ARIZONA_DSP2_WDMA_BUFFER_6:
case ARIZONA_DSP2_WDMA_BUFFER_7:
case ARIZONA_DSP2_WDMA_BUFFER_8:
case ARIZONA_DSP2_RDMA_BUFFER_1:
case ARIZONA_DSP2_RDMA_BUFFER_2:
case ARIZONA_DSP2_RDMA_BUFFER_3:
case ARIZONA_DSP2_RDMA_BUFFER_4:
case ARIZONA_DSP2_RDMA_BUFFER_5:
case ARIZONA_DSP2_RDMA_BUFFER_6:
case ARIZONA_DSP2_WDMA_CONFIG_1:
case ARIZONA_DSP2_WDMA_CONFIG_2:
case ARIZONA_DSP2_WDMA_OFFSET_1:
case ARIZONA_DSP2_RDMA_CONFIG_1:
case ARIZONA_DSP2_RDMA_OFFSET_1:
case ARIZONA_DSP2_EXTERNAL_START_SELECT_1:
case ARIZONA_DSP2_SCRATCH_0:
case ARIZONA_DSP2_SCRATCH_1:
case ARIZONA_DSP2_SCRATCH_2:
case ARIZONA_DSP2_SCRATCH_3:
case ARIZONA_DSP3_CONTROL_1:
case ARIZONA_DSP3_CLOCKING_1:
case ARIZONA_DSP3_STATUS_1:
case ARIZONA_DSP3_STATUS_2:
case ARIZONA_DSP3_STATUS_3:
case ARIZONA_DSP3_STATUS_4:
case ARIZONA_DSP3_WDMA_BUFFER_1:
case ARIZONA_DSP3_WDMA_BUFFER_2:
case ARIZONA_DSP3_WDMA_BUFFER_3:
case ARIZONA_DSP3_WDMA_BUFFER_4:
case ARIZONA_DSP3_WDMA_BUFFER_5:
case ARIZONA_DSP3_WDMA_BUFFER_6:
case ARIZONA_DSP3_WDMA_BUFFER_7:
case ARIZONA_DSP3_WDMA_BUFFER_8:
case ARIZONA_DSP3_RDMA_BUFFER_1:
case ARIZONA_DSP3_RDMA_BUFFER_2:
case ARIZONA_DSP3_RDMA_BUFFER_3:
case ARIZONA_DSP3_RDMA_BUFFER_4:
case ARIZONA_DSP3_RDMA_BUFFER_5:
case ARIZONA_DSP3_RDMA_BUFFER_6:
case ARIZONA_DSP3_WDMA_CONFIG_1:
case ARIZONA_DSP3_WDMA_CONFIG_2:
case ARIZONA_DSP3_WDMA_OFFSET_1:
case ARIZONA_DSP3_RDMA_CONFIG_1:
case ARIZONA_DSP3_RDMA_OFFSET_1:
case ARIZONA_DSP3_EXTERNAL_START_SELECT_1:
case ARIZONA_DSP3_SCRATCH_0:
case ARIZONA_DSP3_SCRATCH_1:
case ARIZONA_DSP3_SCRATCH_2:
case ARIZONA_DSP3_SCRATCH_3:
return true;
default:
return cs47l24_is_adsp_memory(reg);
}
}
static bool cs47l24_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case ARIZONA_SOFTWARE_RESET:
case ARIZONA_DEVICE_REVISION:
case ARIZONA_WRITE_SEQUENCER_CTRL_0:
case ARIZONA_WRITE_SEQUENCER_CTRL_1:
case ARIZONA_WRITE_SEQUENCER_CTRL_2:
case ARIZONA_HAPTICS_STATUS:
case ARIZONA_SAMPLE_RATE_1_STATUS:
case ARIZONA_SAMPLE_RATE_2_STATUS:
case ARIZONA_SAMPLE_RATE_3_STATUS:
case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS:
case ARIZONA_HP_CTRL_1L:
case ARIZONA_HP_CTRL_1R:
case ARIZONA_INPUT_ENABLES_STATUS:
case ARIZONA_OUTPUT_STATUS_1:
case ARIZONA_RAW_OUTPUT_STATUS_1:
case ARIZONA_INTERRUPT_STATUS_1:
case ARIZONA_INTERRUPT_STATUS_2:
case ARIZONA_INTERRUPT_STATUS_3:
case ARIZONA_INTERRUPT_STATUS_4:
case ARIZONA_INTERRUPT_STATUS_5:
case ARIZONA_INTERRUPT_STATUS_6:
case ARIZONA_IRQ2_STATUS_1:
case ARIZONA_IRQ2_STATUS_2:
case ARIZONA_IRQ2_STATUS_3:
case ARIZONA_IRQ2_STATUS_4:
case ARIZONA_IRQ2_STATUS_5:
case ARIZONA_IRQ2_STATUS_6:
case ARIZONA_INTERRUPT_RAW_STATUS_2:
case ARIZONA_INTERRUPT_RAW_STATUS_3:
case ARIZONA_INTERRUPT_RAW_STATUS_4:
case ARIZONA_INTERRUPT_RAW_STATUS_5:
case ARIZONA_INTERRUPT_RAW_STATUS_6:
case ARIZONA_INTERRUPT_RAW_STATUS_7:
case ARIZONA_INTERRUPT_RAW_STATUS_8:
case ARIZONA_INTERRUPT_RAW_STATUS_9:
case ARIZONA_IRQ_PIN_STATUS:
case ARIZONA_FX_CTRL2:
case ARIZONA_ASRC_STATUS:
case ARIZONA_DSP2_STATUS_1:
case ARIZONA_DSP2_STATUS_2:
case ARIZONA_DSP2_STATUS_3:
case ARIZONA_DSP2_STATUS_4:
case ARIZONA_DSP2_WDMA_BUFFER_1:
case ARIZONA_DSP2_WDMA_BUFFER_2:
case ARIZONA_DSP2_WDMA_BUFFER_3:
case ARIZONA_DSP2_WDMA_BUFFER_4:
case ARIZONA_DSP2_WDMA_BUFFER_5:
case ARIZONA_DSP2_WDMA_BUFFER_6:
case ARIZONA_DSP2_WDMA_BUFFER_7:
case ARIZONA_DSP2_WDMA_BUFFER_8:
case ARIZONA_DSP2_RDMA_BUFFER_1:
case ARIZONA_DSP2_RDMA_BUFFER_2:
case ARIZONA_DSP2_RDMA_BUFFER_3:
case ARIZONA_DSP2_RDMA_BUFFER_4:
case ARIZONA_DSP2_RDMA_BUFFER_5:
case ARIZONA_DSP2_RDMA_BUFFER_6:
case ARIZONA_DSP2_WDMA_CONFIG_1:
case ARIZONA_DSP2_WDMA_CONFIG_2:
case ARIZONA_DSP2_WDMA_OFFSET_1:
case ARIZONA_DSP2_RDMA_CONFIG_1:
case ARIZONA_DSP2_RDMA_OFFSET_1:
case ARIZONA_DSP2_EXTERNAL_START_SELECT_1:
case ARIZONA_DSP2_SCRATCH_0:
case ARIZONA_DSP2_SCRATCH_1:
case ARIZONA_DSP2_SCRATCH_2:
case ARIZONA_DSP2_SCRATCH_3:
case ARIZONA_DSP2_CLOCKING_1:
case ARIZONA_DSP3_STATUS_1:
case ARIZONA_DSP3_STATUS_2:
case ARIZONA_DSP3_STATUS_3:
case ARIZONA_DSP3_STATUS_4:
case ARIZONA_DSP3_WDMA_BUFFER_1:
case ARIZONA_DSP3_WDMA_BUFFER_2:
case ARIZONA_DSP3_WDMA_BUFFER_3:
case ARIZONA_DSP3_WDMA_BUFFER_4:
case ARIZONA_DSP3_WDMA_BUFFER_5:
case ARIZONA_DSP3_WDMA_BUFFER_6:
case ARIZONA_DSP3_WDMA_BUFFER_7:
case ARIZONA_DSP3_WDMA_BUFFER_8:
case ARIZONA_DSP3_RDMA_BUFFER_1:
case ARIZONA_DSP3_RDMA_BUFFER_2:
case ARIZONA_DSP3_RDMA_BUFFER_3:
case ARIZONA_DSP3_RDMA_BUFFER_4:
case ARIZONA_DSP3_RDMA_BUFFER_5:
case ARIZONA_DSP3_RDMA_BUFFER_6:
case ARIZONA_DSP3_WDMA_CONFIG_1:
case ARIZONA_DSP3_WDMA_CONFIG_2:
case ARIZONA_DSP3_WDMA_OFFSET_1:
case ARIZONA_DSP3_RDMA_CONFIG_1:
case ARIZONA_DSP3_RDMA_OFFSET_1:
case ARIZONA_DSP3_EXTERNAL_START_SELECT_1:
case ARIZONA_DSP3_SCRATCH_0:
case ARIZONA_DSP3_SCRATCH_1:
case ARIZONA_DSP3_SCRATCH_2:
case ARIZONA_DSP3_SCRATCH_3:
case ARIZONA_DSP3_CLOCKING_1:
return true;
default:
return cs47l24_is_adsp_memory(reg);
}
}
#define CS47L24_MAX_REGISTER 0x3b3fff
const struct regmap_config cs47l24_spi_regmap = {
.reg_bits = 32,
.pad_bits = 16,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = CS47L24_MAX_REGISTER,
.readable_reg = cs47l24_readable_register,
.volatile_reg = cs47l24_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = cs47l24_reg_default,
.num_reg_defaults = ARRAY_SIZE(cs47l24_reg_default),
};
EXPORT_SYMBOL_GPL(cs47l24_spi_regmap);
| linux-master | drivers/mfd/cs47l24-tables.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm8350-regmap.c -- Wolfson Microelectronics WM8350 register map
*
* This file splits out the tables describing the defaults and access
* status of the WM8350 registers since they are rather large.
*
* Copyright 2007, 2008 Wolfson Microelectronics PLC.
*/
#include <linux/mfd/wm8350/core.h>
/*
* Access masks.
*/
static const struct wm8350_reg_access {
u16 readable; /* Mask of readable bits */
u16 writable; /* Mask of writable bits */
u16 vol; /* Mask of volatile bits */
} wm8350_reg_io_map[] = {
/* read write volatile */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R0 - Reset/ID */
{ 0x7CFF, 0x0C00, 0x0000 }, /* R1 - ID */
{ 0x007F, 0x0000, 0x0000 }, /* R2 - ROM Mask ID */
{ 0xBE3B, 0xBE3B, 0x8000 }, /* R3 - System Control 1 */
{ 0xFEF7, 0xFEF7, 0xF800 }, /* R4 - System Control 2 */
{ 0x80FF, 0x80FF, 0x8000 }, /* R5 - System Hibernate */
{ 0xFB0E, 0xFB0E, 0x0000 }, /* R6 - Interface Control */
{ 0x0000, 0x0000, 0x0000 }, /* R7 */
{ 0xE537, 0xE537, 0xFFFF }, /* R8 - Power mgmt (1) */
{ 0x0FF3, 0x0FF3, 0xFFFF }, /* R9 - Power mgmt (2) */
{ 0x008F, 0x008F, 0xFFFF }, /* R10 - Power mgmt (3) */
{ 0x6D3C, 0x6D3C, 0xFFFF }, /* R11 - Power mgmt (4) */
{ 0x1F8F, 0x1F8F, 0xFFFF }, /* R12 - Power mgmt (5) */
{ 0x8F3F, 0x8F3F, 0xFFFF }, /* R13 - Power mgmt (6) */
{ 0x0003, 0x0003, 0xFFFF }, /* R14 - Power mgmt (7) */
{ 0x0000, 0x0000, 0x0000 }, /* R15 */
{ 0x7F7F, 0x7F7F, 0xFFFF }, /* R16 - RTC Seconds/Minutes */
{ 0x073F, 0x073F, 0xFFFF }, /* R17 - RTC Hours/Day */
{ 0x1F3F, 0x1F3F, 0xFFFF }, /* R18 - RTC Date/Month */
{ 0x3FFF, 0x00FF, 0xFFFF }, /* R19 - RTC Year */
{ 0x7F7F, 0x7F7F, 0x0000 }, /* R20 - Alarm Seconds/Minutes */
{ 0x0F3F, 0x0F3F, 0x0000 }, /* R21 - Alarm Hours/Day */
{ 0x1F3F, 0x1F3F, 0x0000 }, /* R22 - Alarm Date/Month */
{ 0xEF7F, 0xEA7F, 0xFFFF }, /* R23 - RTC Time Control */
{ 0x3BFF, 0x0000, 0xFFFF }, /* R24 - System Interrupts */
{ 0xFEE7, 0x0000, 0xFFFF }, /* R25 - Interrupt Status 1 */
{ 0x35FF, 0x0000, 0xFFFF }, /* R26 - Interrupt Status 2 */
{ 0x0F3F, 0x0000, 0xFFFF }, /* R27 - Power Up Interrupt Status */
{ 0x0F3F, 0x0000, 0xFFFF }, /* R28 - Under Voltage Interrupt status */
{ 0x8000, 0x0000, 0xFFFF }, /* R29 - Over Current Interrupt status */
{ 0x1FFF, 0x0000, 0xFFFF }, /* R30 - GPIO Interrupt Status */
{ 0xEF7F, 0x0000, 0xFFFF }, /* R31 - Comparator Interrupt Status */
{ 0x3FFF, 0x3FFF, 0x0000 }, /* R32 - System Interrupts Mask */
{ 0xFEE7, 0xFEE7, 0x0000 }, /* R33 - Interrupt Status 1 Mask */
{ 0xF5FF, 0xF5FF, 0x0000 }, /* R34 - Interrupt Status 2 Mask */
{ 0x0F3F, 0x0F3F, 0x0000 }, /* R35 - Power Up Interrupt Status Mask */
{ 0x0F3F, 0x0F3F, 0x0000 }, /* R36 - Under Voltage Int status Mask */
{ 0x8000, 0x8000, 0x0000 }, /* R37 - Over Current Int status Mask */
{ 0x1FFF, 0x1FFF, 0x0000 }, /* R38 - GPIO Interrupt Status Mask */
{ 0xEF7F, 0xEF7F, 0x0000 }, /* R39 - Comparator IntStatus Mask */
{ 0xC9F7, 0xC9F7, 0xFFFF }, /* R40 - Clock Control 1 */
{ 0x8001, 0x8001, 0x0000 }, /* R41 - Clock Control 2 */
{ 0xFFF7, 0xFFF7, 0xFFFF }, /* R42 - FLL Control 1 */
{ 0xFBFF, 0xFBFF, 0x0000 }, /* R43 - FLL Control 2 */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R44 - FLL Control 3 */
{ 0x0033, 0x0033, 0x0000 }, /* R45 - FLL Control 4 */
{ 0x0000, 0x0000, 0x0000 }, /* R46 */
{ 0x0000, 0x0000, 0x0000 }, /* R47 */
{ 0x3033, 0x3033, 0x0000 }, /* R48 - DAC Control */
{ 0x0000, 0x0000, 0x0000 }, /* R49 */
{ 0x81FF, 0x81FF, 0xFFFF }, /* R50 - DAC Digital Volume L */
{ 0x81FF, 0x81FF, 0xFFFF }, /* R51 - DAC Digital Volume R */
{ 0x0000, 0x0000, 0x0000 }, /* R52 */
{ 0x0FFF, 0x0FFF, 0xFFFF }, /* R53 - DAC LR Rate */
{ 0x0017, 0x0017, 0x0000 }, /* R54 - DAC Clock Control */
{ 0x0000, 0x0000, 0x0000 }, /* R55 */
{ 0x0000, 0x0000, 0x0000 }, /* R56 */
{ 0x0000, 0x0000, 0x0000 }, /* R57 */
{ 0x4000, 0x4000, 0x0000 }, /* R58 - DAC Mute */
{ 0x7000, 0x7000, 0x0000 }, /* R59 - DAC Mute Volume */
{ 0x3C00, 0x3C00, 0x0000 }, /* R60 - DAC Side */
{ 0x0000, 0x0000, 0x0000 }, /* R61 */
{ 0x0000, 0x0000, 0x0000 }, /* R62 */
{ 0x0000, 0x0000, 0x0000 }, /* R63 */
{ 0x8303, 0x8303, 0xFFFF }, /* R64 - ADC Control */
{ 0x0000, 0x0000, 0x0000 }, /* R65 */
{ 0x81FF, 0x81FF, 0xFFFF }, /* R66 - ADC Digital Volume L */
{ 0x81FF, 0x81FF, 0xFFFF }, /* R67 - ADC Digital Volume R */
{ 0x0FFF, 0x0FFF, 0x0000 }, /* R68 - ADC Divider */
{ 0x0000, 0x0000, 0x0000 }, /* R69 */
{ 0x0FFF, 0x0FFF, 0xFFFF }, /* R70 - ADC LR Rate */
{ 0x0000, 0x0000, 0x0000 }, /* R71 */
{ 0x0707, 0x0707, 0xFFFF }, /* R72 - Input Control */
{ 0xC0C0, 0xC0C0, 0xFFFF }, /* R73 - IN3 Input Control */
{ 0xC09F, 0xC09F, 0xFFFF }, /* R74 - Mic Bias Control */
{ 0x0000, 0x0000, 0x0000 }, /* R75 */
{ 0x0F15, 0x0F15, 0xFFFF }, /* R76 - Output Control */
{ 0xC000, 0xC000, 0xFFFF }, /* R77 - Jack Detect */
{ 0x03FF, 0x03FF, 0x0000 }, /* R78 - Anti Pop Control */
{ 0x0000, 0x0000, 0x0000 }, /* R79 */
{ 0xE1FC, 0xE1FC, 0x8000 }, /* R80 - Left Input Volume */
{ 0xE1FC, 0xE1FC, 0x8000 }, /* R81 - Right Input Volume */
{ 0x0000, 0x0000, 0x0000 }, /* R82 */
{ 0x0000, 0x0000, 0x0000 }, /* R83 */
{ 0x0000, 0x0000, 0x0000 }, /* R84 */
{ 0x0000, 0x0000, 0x0000 }, /* R85 */
{ 0x0000, 0x0000, 0x0000 }, /* R86 */
{ 0x0000, 0x0000, 0x0000 }, /* R87 */
{ 0x9807, 0x9807, 0xFFFF }, /* R88 - Left Mixer Control */
{ 0x980B, 0x980B, 0xFFFF }, /* R89 - Right Mixer Control */
{ 0x0000, 0x0000, 0x0000 }, /* R90 */
{ 0x0000, 0x0000, 0x0000 }, /* R91 */
{ 0x8909, 0x8909, 0xFFFF }, /* R92 - OUT3 Mixer Control */
{ 0x9E07, 0x9E07, 0xFFFF }, /* R93 - OUT4 Mixer Control */
{ 0x0000, 0x0000, 0x0000 }, /* R94 */
{ 0x0000, 0x0000, 0x0000 }, /* R95 */
{ 0x0EEE, 0x0EEE, 0x0000 }, /* R96 - Output Left Mixer Volume */
{ 0xE0EE, 0xE0EE, 0x0000 }, /* R97 - Output Right Mixer Volume */
{ 0x0E0F, 0x0E0F, 0x0000 }, /* R98 - Input Mixer Volume L */
{ 0xE0E1, 0xE0E1, 0x0000 }, /* R99 - Input Mixer Volume R */
{ 0x800E, 0x800E, 0x0000 }, /* R100 - Input Mixer Volume */
{ 0x0000, 0x0000, 0x0000 }, /* R101 */
{ 0x0000, 0x0000, 0x0000 }, /* R102 */
{ 0x0000, 0x0000, 0x0000 }, /* R103 */
{ 0xE1FC, 0xE1FC, 0xFFFF }, /* R104 - LOUT1 Volume */
{ 0xE1FC, 0xE1FC, 0xFFFF }, /* R105 - ROUT1 Volume */
{ 0xE1FC, 0xE1FC, 0xFFFF }, /* R106 - LOUT2 Volume */
{ 0xE7FC, 0xE7FC, 0xFFFF }, /* R107 - ROUT2 Volume */
{ 0x0000, 0x0000, 0x0000 }, /* R108 */
{ 0x0000, 0x0000, 0x0000 }, /* R109 */
{ 0x0000, 0x0000, 0x0000 }, /* R110 */
{ 0x80E0, 0x80E0, 0xFFFF }, /* R111 - BEEP Volume */
{ 0xBF00, 0xBF00, 0x0000 }, /* R112 - AI Formating */
{ 0x00F1, 0x00F1, 0x0000 }, /* R113 - ADC DAC COMP */
{ 0x00F8, 0x00F8, 0x0000 }, /* R114 - AI ADC Control */
{ 0x40FB, 0x40FB, 0x0000 }, /* R115 - AI DAC Control */
{ 0x7C30, 0x7C30, 0x0000 }, /* R116 - AIF Test */
{ 0x0000, 0x0000, 0x0000 }, /* R117 */
{ 0x0000, 0x0000, 0x0000 }, /* R118 */
{ 0x0000, 0x0000, 0x0000 }, /* R119 */
{ 0x0000, 0x0000, 0x0000 }, /* R120 */
{ 0x0000, 0x0000, 0x0000 }, /* R121 */
{ 0x0000, 0x0000, 0x0000 }, /* R122 */
{ 0x0000, 0x0000, 0x0000 }, /* R123 */
{ 0x0000, 0x0000, 0x0000 }, /* R124 */
{ 0x0000, 0x0000, 0x0000 }, /* R125 */
{ 0x0000, 0x0000, 0x0000 }, /* R126 */
{ 0x0000, 0x0000, 0x0000 }, /* R127 */
{ 0x1FFF, 0x1FFF, 0x0000 }, /* R128 - GPIO Debounce */
{ 0x1FFF, 0x1FFF, 0x0000 }, /* R129 - GPIO Pin pull up Control */
{ 0x1FFF, 0x1FFF, 0x0000 }, /* R130 - GPIO Pull down Control */
{ 0x1FFF, 0x1FFF, 0x0000 }, /* R131 - GPIO Interrupt Mode */
{ 0x0000, 0x0000, 0x0000 }, /* R132 */
{ 0x00C0, 0x00C0, 0x0000 }, /* R133 - GPIO Control */
{ 0x1FFF, 0x1FFF, 0x0000 }, /* R134 - GPIO Configuration (i/o) */
{ 0x1FFF, 0x1FFF, 0x0000 }, /* R135 - GPIO Pin Polarity / Type */
{ 0x0000, 0x0000, 0x0000 }, /* R136 */
{ 0x0000, 0x0000, 0x0000 }, /* R137 */
{ 0x0000, 0x0000, 0x0000 }, /* R138 */
{ 0x0000, 0x0000, 0x0000 }, /* R139 */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R140 - GPIO Function Select 1 */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R141 - GPIO Function Select 2 */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R142 - GPIO Function Select 3 */
{ 0x000F, 0x000F, 0x0000 }, /* R143 - GPIO Function Select 4 */
{ 0xF0FF, 0xF0FF, 0xA000 }, /* R144 - Digitiser Control (1) */
{ 0x3707, 0x3707, 0x0000 }, /* R145 - Digitiser Control (2) */
{ 0x0000, 0x0000, 0x0000 }, /* R146 */
{ 0x0000, 0x0000, 0x0000 }, /* R147 */
{ 0x0000, 0x0000, 0x0000 }, /* R148 */
{ 0x0000, 0x0000, 0x0000 }, /* R149 */
{ 0x0000, 0x0000, 0x0000 }, /* R150 */
{ 0x0000, 0x0000, 0x0000 }, /* R151 */
{ 0x7FFF, 0x7000, 0xFFFF }, /* R152 - AUX1 Readback */
{ 0x7FFF, 0x7000, 0xFFFF }, /* R153 - AUX2 Readback */
{ 0x7FFF, 0x7000, 0xFFFF }, /* R154 - AUX3 Readback */
{ 0x7FFF, 0x7000, 0xFFFF }, /* R155 - AUX4 Readback */
{ 0x0FFF, 0x0000, 0xFFFF }, /* R156 - USB Voltage Readback */
{ 0x0FFF, 0x0000, 0xFFFF }, /* R157 - LINE Voltage Readback */
{ 0x0FFF, 0x0000, 0xFFFF }, /* R158 - BATT Voltage Readback */
{ 0x0FFF, 0x0000, 0xFFFF }, /* R159 - Chip Temp Readback */
{ 0x0000, 0x0000, 0x0000 }, /* R160 */
{ 0x0000, 0x0000, 0x0000 }, /* R161 */
{ 0x0000, 0x0000, 0x0000 }, /* R162 */
{ 0x000F, 0x000F, 0x0000 }, /* R163 - Generic Comparator Control */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R164 - Generic comparator 1 */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R165 - Generic comparator 2 */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R166 - Generic comparator 3 */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R167 - Generic comparator 4 */
{ 0xBFFF, 0xBFFF, 0x8000 }, /* R168 - Battery Charger Control 1 */
{ 0xFFFF, 0x4FFF, 0xB000 }, /* R169 - Battery Charger Control 2 */
{ 0x007F, 0x007F, 0x0000 }, /* R170 - Battery Charger Control 3 */
{ 0x0000, 0x0000, 0x0000 }, /* R171 */
{ 0x903F, 0x903F, 0xFFFF }, /* R172 - Current Sink Driver A */
{ 0xE333, 0xE333, 0xFFFF }, /* R173 - CSA Flash control */
{ 0x903F, 0x903F, 0xFFFF }, /* R174 - Current Sink Driver B */
{ 0xE333, 0xE333, 0xFFFF }, /* R175 - CSB Flash control */
{ 0x8F3F, 0x8F3F, 0xFFFF }, /* R176 - DCDC/LDO requested */
{ 0x332D, 0x332D, 0x0000 }, /* R177 - DCDC Active options */
{ 0x002D, 0x002D, 0x0000 }, /* R178 - DCDC Sleep options */
{ 0x5177, 0x5177, 0x8000 }, /* R179 - Power-check comparator */
{ 0x047F, 0x047F, 0x0000 }, /* R180 - DCDC1 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R181 - DCDC1 Timeouts */
{ 0x737F, 0x737F, 0x0000 }, /* R182 - DCDC1 Low Power */
{ 0x535B, 0x535B, 0x0000 }, /* R183 - DCDC2 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R184 - DCDC2 Timeouts */
{ 0x0000, 0x0000, 0x0000 }, /* R185 */
{ 0x047F, 0x047F, 0x0000 }, /* R186 - DCDC3 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R187 - DCDC3 Timeouts */
{ 0x737F, 0x737F, 0x0000 }, /* R188 - DCDC3 Low Power */
{ 0x047F, 0x047F, 0x0000 }, /* R189 - DCDC4 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R190 - DCDC4 Timeouts */
{ 0x737F, 0x737F, 0x0000 }, /* R191 - DCDC4 Low Power */
{ 0x535B, 0x535B, 0x0000 }, /* R192 - DCDC5 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R193 - DCDC5 Timeouts */
{ 0x0000, 0x0000, 0x0000 }, /* R194 */
{ 0x047F, 0x047F, 0x0000 }, /* R195 - DCDC6 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R196 - DCDC6 Timeouts */
{ 0x737F, 0x737F, 0x0000 }, /* R197 - DCDC6 Low Power */
{ 0x0000, 0x0000, 0x0000 }, /* R198 */
{ 0xFFD3, 0xFFD3, 0x0000 }, /* R199 - Limit Switch Control */
{ 0x441F, 0x441F, 0x0000 }, /* R200 - LDO1 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R201 - LDO1 Timeouts */
{ 0x331F, 0x331F, 0x0000 }, /* R202 - LDO1 Low Power */
{ 0x441F, 0x441F, 0x0000 }, /* R203 - LDO2 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R204 - LDO2 Timeouts */
{ 0x331F, 0x331F, 0x0000 }, /* R205 - LDO2 Low Power */
{ 0x441F, 0x441F, 0x0000 }, /* R206 - LDO3 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R207 - LDO3 Timeouts */
{ 0x331F, 0x331F, 0x0000 }, /* R208 - LDO3 Low Power */
{ 0x441F, 0x441F, 0x0000 }, /* R209 - LDO4 Control */
{ 0xFFC0, 0xFFC0, 0x0000 }, /* R210 - LDO4 Timeouts */
{ 0x331F, 0x331F, 0x0000 }, /* R211 - LDO4 Low Power */
{ 0x0000, 0x0000, 0x0000 }, /* R212 */
{ 0x0000, 0x0000, 0x0000 }, /* R213 */
{ 0x0000, 0x0000, 0x0000 }, /* R214 */
{ 0x8F3F, 0x8F3F, 0x0000 }, /* R215 - VCC_FAULT Masks */
{ 0xFF3F, 0xE03F, 0x0000 }, /* R216 - Main Bandgap Control */
{ 0xEF2F, 0xE02F, 0x0000 }, /* R217 - OSC Control */
{ 0xF3FF, 0xB3FF, 0xc000 }, /* R218 - RTC Tick Control */
{ 0xFFFF, 0xFFFF, 0x0000 }, /* R219 - Security */
{ 0x09FF, 0x01FF, 0x0000 }, /* R220 - RAM BIST 1 */
{ 0x0000, 0x0000, 0x0000 }, /* R221 */
{ 0xFFFF, 0xFFFF, 0xFFFF }, /* R222 */
{ 0xFFFF, 0xFFFF, 0xFFFF }, /* R223 */
{ 0x0000, 0x0000, 0x0000 }, /* R224 */
{ 0x8F3F, 0x0000, 0xFFFF }, /* R225 - DCDC/LDO status */
{ 0x0000, 0x0000, 0xFFFF }, /* R226 - Charger status */
{ 0x34FE, 0x0000, 0xFFFF }, /* R227 */
{ 0x0000, 0x0000, 0x0000 }, /* R228 */
{ 0x0000, 0x0000, 0x0000 }, /* R229 */
{ 0xFFFF, 0x1FFF, 0xFFFF }, /* R230 - GPIO Pin Status */
{ 0xFFFF, 0x1FFF, 0xFFFF }, /* R231 */
{ 0xFFFF, 0x1FFF, 0xFFFF }, /* R232 */
{ 0xFFFF, 0x1FFF, 0xFFFF }, /* R233 */
{ 0x0000, 0x0000, 0x0000 }, /* R234 */
{ 0x0000, 0x0000, 0x0000 }, /* R235 */
{ 0x0000, 0x0000, 0x0000 }, /* R236 */
{ 0x0000, 0x0000, 0x0000 }, /* R237 */
{ 0x0000, 0x0000, 0x0000 }, /* R238 */
{ 0x0000, 0x0000, 0x0000 }, /* R239 */
{ 0x0000, 0x0000, 0x0000 }, /* R240 */
{ 0x0000, 0x0000, 0x0000 }, /* R241 */
{ 0x0000, 0x0000, 0x0000 }, /* R242 */
{ 0x0000, 0x0000, 0x0000 }, /* R243 */
{ 0x0000, 0x0000, 0x0000 }, /* R244 */
{ 0x0000, 0x0000, 0x0000 }, /* R245 */
{ 0x0000, 0x0000, 0x0000 }, /* R246 */
{ 0x0000, 0x0000, 0x0000 }, /* R247 */
{ 0xFFFF, 0x0010, 0xFFFF }, /* R248 */
{ 0x0000, 0x0000, 0x0000 }, /* R249 */
{ 0xFFFF, 0x0010, 0xFFFF }, /* R250 */
{ 0xFFFF, 0x0010, 0xFFFF }, /* R251 */
{ 0x0000, 0x0000, 0x0000 }, /* R252 */
{ 0xFFFF, 0x0010, 0xFFFF }, /* R253 */
{ 0x0000, 0x0000, 0x0000 }, /* R254 */
{ 0x0000, 0x0000, 0x0000 }, /* R255 */
};
static bool wm8350_readable(struct device *dev, unsigned int reg)
{
return wm8350_reg_io_map[reg].readable;
}
static bool wm8350_writeable(struct device *dev, unsigned int reg)
{
struct wm8350 *wm8350 = dev_get_drvdata(dev);
if (!wm8350->unlocked) {
if ((reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
(reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
return false;
}
return wm8350_reg_io_map[reg].writable;
}
static bool wm8350_volatile(struct device *dev, unsigned int reg)
{
return wm8350_reg_io_map[reg].vol;
}
static bool wm8350_precious(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8350_SYSTEM_INTERRUPTS:
case WM8350_INT_STATUS_1:
case WM8350_INT_STATUS_2:
case WM8350_POWER_UP_INT_STATUS:
case WM8350_UNDER_VOLTAGE_INT_STATUS:
case WM8350_OVER_CURRENT_INT_STATUS:
case WM8350_GPIO_INT_STATUS:
case WM8350_COMPARATOR_INT_STATUS:
return true;
default:
return false;
}
}
const struct regmap_config wm8350_regmap = {
.reg_bits = 8,
.val_bits = 16,
.cache_type = REGCACHE_RBTREE,
.max_register = WM8350_MAX_REGISTER,
.readable_reg = wm8350_readable,
.writeable_reg = wm8350_writeable,
.volatile_reg = wm8350_volatile,
.precious_reg = wm8350_precious,
};
| linux-master | drivers/mfd/wm8350-regmap.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* DB8500 PRCM Unit driver
*
* Copyright (C) STMicroelectronics 2009
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Kumar Sanghvi <[email protected]>
* Author: Sundar Iyer <[email protected]>
* Author: Mattias Nilsson <[email protected]>
*
* U8500 PRCM Unit interface driver
*/
#include <linux/init.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/mutex.h>
#include <linux/completion.h>
#include <linux/irq.h>
#include <linux/jiffies.h>
#include <linux/bitops.h>
#include <linux/fs.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/uaccess.h>
#include <linux/mfd/core.h>
#include <linux/mfd/dbx500-prcmu.h>
#include <linux/mfd/abx500/ab8500.h>
#include <linux/regulator/db8500-prcmu.h>
#include <linux/regulator/machine.h>
#include "db8500-prcmu-regs.h"
/* Index of different voltages to be used when accessing AVSData */
#define PRCM_AVS_BASE 0x2FC
#define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
#define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
#define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
#define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
#define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
#define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
#define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
#define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
#define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
#define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
#define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
#define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
#define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
#define PRCM_AVS_VOLTAGE 0
#define PRCM_AVS_VOLTAGE_MASK 0x3f
#define PRCM_AVS_ISSLOWSTARTUP 6
#define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
#define PRCM_AVS_ISMODEENABLE 7
#define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
#define PRCM_BOOT_STATUS 0xFFF
#define PRCM_ROMCODE_A2P 0xFFE
#define PRCM_ROMCODE_P2A 0xFFD
#define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
#define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
#define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
#define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
#define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
#define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
#define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
#define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
#define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
#define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
/* Req Mailboxes */
#define PRCM_REQ_MB0 0xFDC /* 12 bytes */
#define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
#define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
#define PRCM_REQ_MB3 0xE4C /* 372 bytes */
#define PRCM_REQ_MB4 0xE48 /* 4 bytes */
#define PRCM_REQ_MB5 0xE44 /* 4 bytes */
/* Ack Mailboxes */
#define PRCM_ACK_MB0 0xE08 /* 52 bytes */
#define PRCM_ACK_MB1 0xE04 /* 4 bytes */
#define PRCM_ACK_MB2 0xE00 /* 4 bytes */
#define PRCM_ACK_MB3 0xDFC /* 4 bytes */
#define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
#define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
/* Mailbox 0 headers */
#define MB0H_POWER_STATE_TRANS 0
#define MB0H_CONFIG_WAKEUPS_EXE 1
#define MB0H_READ_WAKEUP_ACK 3
#define MB0H_CONFIG_WAKEUPS_SLEEP 4
#define MB0H_WAKEUP_EXE 2
#define MB0H_WAKEUP_SLEEP 5
/* Mailbox 0 REQs */
#define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
#define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
#define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
#define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
#define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
#define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
/* Mailbox 0 ACKs */
#define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
#define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
#define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
#define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
#define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
#define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
#define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
/* Mailbox 1 headers */
#define MB1H_ARM_APE_OPP 0x0
#define MB1H_RESET_MODEM 0x2
#define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
#define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
#define MB1H_RELEASE_USB_WAKEUP 0x5
#define MB1H_PLL_ON_OFF 0x6
/* Mailbox 1 Requests */
#define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
#define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
#define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
#define PLL_SOC0_OFF 0x1
#define PLL_SOC0_ON 0x2
#define PLL_SOC1_OFF 0x4
#define PLL_SOC1_ON 0x8
/* Mailbox 1 ACKs */
#define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
#define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
#define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
#define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
/* Mailbox 2 headers */
#define MB2H_DPS 0x0
#define MB2H_AUTO_PWR 0x1
/* Mailbox 2 REQs */
#define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
#define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
#define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
#define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
#define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
#define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
#define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
#define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
#define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
#define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
/* Mailbox 2 ACKs */
#define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
#define HWACC_PWR_ST_OK 0xFE
/* Mailbox 3 headers */
#define MB3H_ANC 0x0
#define MB3H_SIDETONE 0x1
#define MB3H_SYSCLK 0xE
/* Mailbox 3 Requests */
#define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
#define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
#define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
#define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
#define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
#define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
#define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
/* Mailbox 4 headers */
#define MB4H_DDR_INIT 0x0
#define MB4H_MEM_ST 0x1
#define MB4H_HOTDOG 0x12
#define MB4H_HOTMON 0x13
#define MB4H_HOT_PERIOD 0x14
#define MB4H_A9WDOG_CONF 0x16
#define MB4H_A9WDOG_EN 0x17
#define MB4H_A9WDOG_DIS 0x18
#define MB4H_A9WDOG_LOAD 0x19
#define MB4H_A9WDOG_KICK 0x20
/* Mailbox 4 Requests */
#define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
#define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
#define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
#define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
#define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
#define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
#define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
#define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
#define HOTMON_CONFIG_LOW BIT(0)
#define HOTMON_CONFIG_HIGH BIT(1)
#define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
#define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
#define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
#define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
#define A9WDOG_AUTO_OFF_EN BIT(7)
#define A9WDOG_AUTO_OFF_DIS 0
#define A9WDOG_ID_MASK 0xf
/* Mailbox 5 Requests */
#define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
#define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
#define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
#define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
#define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
#define PRCMU_I2C_STOP_EN BIT(3)
/* Mailbox 5 ACKs */
#define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
#define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
#define I2C_WR_OK 0x1
#define I2C_RD_OK 0x2
#define NUM_MB 8
#define MBOX_BIT BIT
#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
/*
* Wakeups/IRQs
*/
#define WAKEUP_BIT_RTC BIT(0)
#define WAKEUP_BIT_RTT0 BIT(1)
#define WAKEUP_BIT_RTT1 BIT(2)
#define WAKEUP_BIT_HSI0 BIT(3)
#define WAKEUP_BIT_HSI1 BIT(4)
#define WAKEUP_BIT_CA_WAKE BIT(5)
#define WAKEUP_BIT_USB BIT(6)
#define WAKEUP_BIT_ABB BIT(7)
#define WAKEUP_BIT_ABB_FIFO BIT(8)
#define WAKEUP_BIT_SYSCLK_OK BIT(9)
#define WAKEUP_BIT_CA_SLEEP BIT(10)
#define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
#define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
#define WAKEUP_BIT_ANC_OK BIT(13)
#define WAKEUP_BIT_SW_ERROR BIT(14)
#define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
#define WAKEUP_BIT_ARM BIT(17)
#define WAKEUP_BIT_HOTMON_LOW BIT(18)
#define WAKEUP_BIT_HOTMON_HIGH BIT(19)
#define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
#define WAKEUP_BIT_GPIO0 BIT(23)
#define WAKEUP_BIT_GPIO1 BIT(24)
#define WAKEUP_BIT_GPIO2 BIT(25)
#define WAKEUP_BIT_GPIO3 BIT(26)
#define WAKEUP_BIT_GPIO4 BIT(27)
#define WAKEUP_BIT_GPIO5 BIT(28)
#define WAKEUP_BIT_GPIO6 BIT(29)
#define WAKEUP_BIT_GPIO7 BIT(30)
#define WAKEUP_BIT_GPIO8 BIT(31)
static struct {
bool valid;
struct prcmu_fw_version version;
} fw_info;
static struct irq_domain *db8500_irq_domain;
/*
* This vector maps irq numbers to the bits in the bit field used in
* communication with the PRCMU firmware.
*
* The reason for having this is to keep the irq numbers contiguous even though
* the bits in the bit field are not. (The bits also have a tendency to move
* around, to further complicate matters.)
*/
#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
#define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
#define IRQ_PRCMU_RTC 0
#define IRQ_PRCMU_RTT0 1
#define IRQ_PRCMU_RTT1 2
#define IRQ_PRCMU_HSI0 3
#define IRQ_PRCMU_HSI1 4
#define IRQ_PRCMU_CA_WAKE 5
#define IRQ_PRCMU_USB 6
#define IRQ_PRCMU_ABB 7
#define IRQ_PRCMU_ABB_FIFO 8
#define IRQ_PRCMU_ARM 9
#define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
#define IRQ_PRCMU_GPIO0 11
#define IRQ_PRCMU_GPIO1 12
#define IRQ_PRCMU_GPIO2 13
#define IRQ_PRCMU_GPIO3 14
#define IRQ_PRCMU_GPIO4 15
#define IRQ_PRCMU_GPIO5 16
#define IRQ_PRCMU_GPIO6 17
#define IRQ_PRCMU_GPIO7 18
#define IRQ_PRCMU_GPIO8 19
#define IRQ_PRCMU_CA_SLEEP 20
#define IRQ_PRCMU_HOTMON_LOW 21
#define IRQ_PRCMU_HOTMON_HIGH 22
#define NUM_PRCMU_WAKEUPS 23
static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
IRQ_ENTRY(RTC),
IRQ_ENTRY(RTT0),
IRQ_ENTRY(RTT1),
IRQ_ENTRY(HSI0),
IRQ_ENTRY(HSI1),
IRQ_ENTRY(CA_WAKE),
IRQ_ENTRY(USB),
IRQ_ENTRY(ABB),
IRQ_ENTRY(ABB_FIFO),
IRQ_ENTRY(CA_SLEEP),
IRQ_ENTRY(ARM),
IRQ_ENTRY(HOTMON_LOW),
IRQ_ENTRY(HOTMON_HIGH),
IRQ_ENTRY(MODEM_SW_RESET_REQ),
IRQ_ENTRY(GPIO0),
IRQ_ENTRY(GPIO1),
IRQ_ENTRY(GPIO2),
IRQ_ENTRY(GPIO3),
IRQ_ENTRY(GPIO4),
IRQ_ENTRY(GPIO5),
IRQ_ENTRY(GPIO6),
IRQ_ENTRY(GPIO7),
IRQ_ENTRY(GPIO8)
};
#define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
#define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
WAKEUP_ENTRY(RTC),
WAKEUP_ENTRY(RTT0),
WAKEUP_ENTRY(RTT1),
WAKEUP_ENTRY(HSI0),
WAKEUP_ENTRY(HSI1),
WAKEUP_ENTRY(USB),
WAKEUP_ENTRY(ABB),
WAKEUP_ENTRY(ABB_FIFO),
WAKEUP_ENTRY(ARM)
};
/*
* mb0_transfer - state needed for mailbox 0 communication.
* @lock: The transaction lock.
* @dbb_events_lock: A lock used to handle concurrent access to (parts of)
* the request data.
* @mask_work: Work structure used for (un)masking wakeup interrupts.
* @req: Request data that need to persist between requests.
*/
static struct {
spinlock_t lock;
spinlock_t dbb_irqs_lock;
struct work_struct mask_work;
struct mutex ac_wake_lock;
struct completion ac_wake_work;
struct {
u32 dbb_irqs;
u32 dbb_wakeups;
u32 abb_events;
} req;
} mb0_transfer;
/*
* mb1_transfer - state needed for mailbox 1 communication.
* @lock: The transaction lock.
* @work: The transaction completion structure.
* @ape_opp: The current APE OPP.
* @ack: Reply ("acknowledge") data.
*/
static struct {
struct mutex lock;
struct completion work;
u8 ape_opp;
struct {
u8 header;
u8 arm_opp;
u8 ape_opp;
u8 ape_voltage_status;
} ack;
} mb1_transfer;
/*
* mb2_transfer - state needed for mailbox 2 communication.
* @lock: The transaction lock.
* @work: The transaction completion structure.
* @auto_pm_lock: The autonomous power management configuration lock.
* @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
* @req: Request data that need to persist between requests.
* @ack: Reply ("acknowledge") data.
*/
static struct {
struct mutex lock;
struct completion work;
spinlock_t auto_pm_lock;
bool auto_pm_enabled;
struct {
u8 status;
} ack;
} mb2_transfer;
/*
* mb3_transfer - state needed for mailbox 3 communication.
* @lock: The request lock.
* @sysclk_lock: A lock used to handle concurrent sysclk requests.
* @sysclk_work: Work structure used for sysclk requests.
*/
static struct {
spinlock_t lock;
struct mutex sysclk_lock;
struct completion sysclk_work;
} mb3_transfer;
/*
* mb4_transfer - state needed for mailbox 4 communication.
* @lock: The transaction lock.
* @work: The transaction completion structure.
*/
static struct {
struct mutex lock;
struct completion work;
} mb4_transfer;
/*
* mb5_transfer - state needed for mailbox 5 communication.
* @lock: The transaction lock.
* @work: The transaction completion structure.
* @ack: Reply ("acknowledge") data.
*/
static struct {
struct mutex lock;
struct completion work;
struct {
u8 status;
u8 value;
} ack;
} mb5_transfer;
static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
/* Spinlocks */
static DEFINE_SPINLOCK(prcmu_lock);
static DEFINE_SPINLOCK(clkout_lock);
/* Global var to runtime determine TCDM base for v2 or v1 */
static __iomem void *tcdm_base;
static __iomem void *prcmu_base;
struct clk_mgt {
u32 offset;
u32 pllsw;
int branch;
bool clk38div;
};
enum {
PLL_RAW,
PLL_FIX,
PLL_DIV
};
static DEFINE_SPINLOCK(clk_mgt_lock);
#define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
{ (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
};
struct dsiclk {
u32 divsel_mask;
u32 divsel_shift;
u32 divsel;
};
static struct dsiclk dsiclk[2] = {
{
.divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
.divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
.divsel = PRCM_DSI_PLLOUT_SEL_PHI,
},
{
.divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
.divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
.divsel = PRCM_DSI_PLLOUT_SEL_PHI,
}
};
struct dsiescclk {
u32 en;
u32 div_mask;
u32 div_shift;
};
static struct dsiescclk dsiescclk[3] = {
{
.en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
.div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
.div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
},
{
.en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
.div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
.div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
},
{
.en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
.div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
.div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
}
};
u32 db8500_prcmu_read(unsigned int reg)
{
return readl(prcmu_base + reg);
}
void db8500_prcmu_write(unsigned int reg, u32 value)
{
unsigned long flags;
spin_lock_irqsave(&prcmu_lock, flags);
writel(value, (prcmu_base + reg));
spin_unlock_irqrestore(&prcmu_lock, flags);
}
void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
{
u32 val;
unsigned long flags;
spin_lock_irqsave(&prcmu_lock, flags);
val = readl(prcmu_base + reg);
val = ((val & ~mask) | (value & mask));
writel(val, (prcmu_base + reg));
spin_unlock_irqrestore(&prcmu_lock, flags);
}
struct prcmu_fw_version *prcmu_get_fw_version(void)
{
return fw_info.valid ? &fw_info.version : NULL;
}
static bool prcmu_is_ulppll_disabled(void)
{
struct prcmu_fw_version *ver;
ver = prcmu_get_fw_version();
return ver && ver->project == PRCMU_FW_PROJECT_U8420_SYSCLK;
}
bool prcmu_has_arm_maxopp(void)
{
return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
}
/**
* prcmu_set_rc_a2p - This function is used to run few power state sequences
* @val: Value to be set, i.e. transition requested
* Returns: 0 on success, -EINVAL on invalid argument
*
* This function is used to run the following power state sequences -
* any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
*/
int prcmu_set_rc_a2p(enum romcode_write val)
{
if (val < RDY_2_DS || val > RDY_2_XP70_RST)
return -EINVAL;
writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
return 0;
}
/**
* prcmu_get_rc_p2a - This function is used to get power state sequences
* Returns: the power transition that has last happened
*
* This function can return the following transitions-
* any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
*/
enum romcode_read prcmu_get_rc_p2a(void)
{
return readb(tcdm_base + PRCM_ROMCODE_P2A);
}
/**
* prcmu_get_xp70_current_state - Return the current XP70 power mode
* Returns: Returns the current AP(ARM) power mode: init,
* apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
*/
enum ap_pwrst prcmu_get_xp70_current_state(void)
{
return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
}
/**
* prcmu_config_clkout - Configure one of the programmable clock outputs.
* @clkout: The CLKOUT number (0 or 1).
* @source: The clock to be used (one of the PRCMU_CLKSRC_*).
* @div: The divider to be applied.
*
* Configures one of the programmable clock outputs (CLKOUTs).
* @div should be in the range [1,63] to request a configuration, or 0 to
* inform that the configuration is no longer requested.
*/
int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
{
static int requests[2];
int r = 0;
unsigned long flags;
u32 val;
u32 bits;
u32 mask;
u32 div_mask;
BUG_ON(clkout > 1);
BUG_ON(div > 63);
BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
if (!div && !requests[clkout])
return -EINVAL;
if (clkout == 0) {
div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
(div << PRCM_CLKOCR_CLKODIV0_SHIFT));
} else {
div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
PRCM_CLKOCR_CLK1TYPE);
bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
(div << PRCM_CLKOCR_CLKODIV1_SHIFT));
}
bits &= mask;
spin_lock_irqsave(&clkout_lock, flags);
val = readl(PRCM_CLKOCR);
if (val & div_mask) {
if (div) {
if ((val & mask) != bits) {
r = -EBUSY;
goto unlock_and_return;
}
} else {
if ((val & mask & ~div_mask) != bits) {
r = -EINVAL;
goto unlock_and_return;
}
}
}
writel((bits | (val & ~mask)), PRCM_CLKOCR);
requests[clkout] += (div ? 1 : -1);
unlock_and_return:
spin_unlock_irqrestore(&clkout_lock, flags);
return r;
}
int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
{
unsigned long flags;
BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
spin_lock_irqsave(&mb0_transfer.lock, flags);
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
cpu_relax();
writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
writeb((keep_ulp_clk ? 1 : 0),
(tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
spin_unlock_irqrestore(&mb0_transfer.lock, flags);
return 0;
}
u8 db8500_prcmu_get_power_state_result(void)
{
return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
}
/* This function should only be called while mb0_transfer.lock is held. */
static void config_wakeups(void)
{
const u8 header[2] = {
MB0H_CONFIG_WAKEUPS_EXE,
MB0H_CONFIG_WAKEUPS_SLEEP
};
static u32 last_dbb_events;
static u32 last_abb_events;
u32 dbb_events;
u32 abb_events;
unsigned int i;
dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
abb_events = mb0_transfer.req.abb_events;
if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
return;
for (i = 0; i < 2; i++) {
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
cpu_relax();
writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
}
last_dbb_events = dbb_events;
last_abb_events = abb_events;
}
void db8500_prcmu_enable_wakeups(u32 wakeups)
{
unsigned long flags;
u32 bits;
int i;
BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
if (wakeups & BIT(i))
bits |= prcmu_wakeup_bit[i];
}
spin_lock_irqsave(&mb0_transfer.lock, flags);
mb0_transfer.req.dbb_wakeups = bits;
config_wakeups();
spin_unlock_irqrestore(&mb0_transfer.lock, flags);
}
void db8500_prcmu_config_abb_event_readout(u32 abb_events)
{
unsigned long flags;
spin_lock_irqsave(&mb0_transfer.lock, flags);
mb0_transfer.req.abb_events = abb_events;
config_wakeups();
spin_unlock_irqrestore(&mb0_transfer.lock, flags);
}
void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
{
if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
*buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
else
*buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
}
/**
* db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
* @opp: The new ARM operating point to which transition is to be made
* Returns: 0 on success, non-zero on failure
*
* This function sets the operating point of the ARM.
*/
int db8500_prcmu_set_arm_opp(u8 opp)
{
int r;
if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
return -EINVAL;
r = 0;
mutex_lock(&mb1_transfer.lock);
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
cpu_relax();
writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
wait_for_completion(&mb1_transfer.work);
if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
(mb1_transfer.ack.arm_opp != opp))
r = -EIO;
mutex_unlock(&mb1_transfer.lock);
return r;
}
/**
* db8500_prcmu_get_arm_opp - get the current ARM OPP
*
* Returns: the current ARM OPP
*/
int db8500_prcmu_get_arm_opp(void)
{
return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
}
/**
* db8500_prcmu_get_ddr_opp - get the current DDR OPP
*
* Returns: the current DDR OPP
*/
int db8500_prcmu_get_ddr_opp(void)
{
return readb(PRCM_DDR_SUBSYS_APE_MINBW);
}
/* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
static void request_even_slower_clocks(bool enable)
{
u32 clock_reg[] = {
PRCM_ACLK_MGT,
PRCM_DMACLK_MGT
};
unsigned long flags;
unsigned int i;
spin_lock_irqsave(&clk_mgt_lock, flags);
/* Grab the HW semaphore. */
while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
cpu_relax();
for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
u32 val;
u32 div;
val = readl(prcmu_base + clock_reg[i]);
div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
if (enable) {
if ((div <= 1) || (div > 15)) {
pr_err("prcmu: Bad clock divider %d in %s\n",
div, __func__);
goto unlock_and_return;
}
div <<= 1;
} else {
if (div <= 2)
goto unlock_and_return;
div >>= 1;
}
val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
(div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
writel(val, prcmu_base + clock_reg[i]);
}
unlock_and_return:
/* Release the HW semaphore. */
writel(0, PRCM_SEM);
spin_unlock_irqrestore(&clk_mgt_lock, flags);
}
/**
* db8500_prcmu_set_ape_opp - set the appropriate APE OPP
* @opp: The new APE operating point to which transition is to be made
* Returns: 0 on success, non-zero on failure
*
* This function sets the operating point of the APE.
*/
int db8500_prcmu_set_ape_opp(u8 opp)
{
int r = 0;
if (opp == mb1_transfer.ape_opp)
return 0;
mutex_lock(&mb1_transfer.lock);
if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
request_even_slower_clocks(false);
if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
goto skip_message;
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
cpu_relax();
writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
(tcdm_base + PRCM_REQ_MB1_APE_OPP));
writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
wait_for_completion(&mb1_transfer.work);
if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
(mb1_transfer.ack.ape_opp != opp))
r = -EIO;
skip_message:
if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
(r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
request_even_slower_clocks(true);
if (!r)
mb1_transfer.ape_opp = opp;
mutex_unlock(&mb1_transfer.lock);
return r;
}
/**
* db8500_prcmu_get_ape_opp - get the current APE OPP
*
* Returns: the current APE OPP
*/
int db8500_prcmu_get_ape_opp(void)
{
return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
}
/**
* db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
* @enable: true to request the higher voltage, false to drop a request.
*
* Calls to this function to enable and disable requests must be balanced.
*/
int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
{
int r = 0;
u8 header;
static unsigned int requests;
mutex_lock(&mb1_transfer.lock);
if (enable) {
if (0 != requests++)
goto unlock_and_return;
header = MB1H_REQUEST_APE_OPP_100_VOLT;
} else {
if (requests == 0) {
r = -EIO;
goto unlock_and_return;
} else if (1 != requests--) {
goto unlock_and_return;
}
header = MB1H_RELEASE_APE_OPP_100_VOLT;
}
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
cpu_relax();
writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
wait_for_completion(&mb1_transfer.work);
if ((mb1_transfer.ack.header != header) ||
((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
r = -EIO;
unlock_and_return:
mutex_unlock(&mb1_transfer.lock);
return r;
}
/**
* prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
*
* This function releases the power state requirements of a USB wakeup.
*/
int prcmu_release_usb_wakeup_state(void)
{
int r = 0;
mutex_lock(&mb1_transfer.lock);
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
cpu_relax();
writeb(MB1H_RELEASE_USB_WAKEUP,
(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
wait_for_completion(&mb1_transfer.work);
if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
r = -EIO;
mutex_unlock(&mb1_transfer.lock);
return r;
}
static int request_pll(u8 clock, bool enable)
{
int r = 0;
if (clock == PRCMU_PLLSOC0)
clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
else if (clock == PRCMU_PLLSOC1)
clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
else
return -EINVAL;
mutex_lock(&mb1_transfer.lock);
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
cpu_relax();
writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
wait_for_completion(&mb1_transfer.work);
if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
r = -EIO;
mutex_unlock(&mb1_transfer.lock);
return r;
}
/**
* db8500_prcmu_set_epod - set the state of a EPOD (power domain)
* @epod_id: The EPOD to set
* @epod_state: The new EPOD state
*
* This function sets the state of a EPOD (power domain). It may not be called
* from interrupt context.
*/
int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
{
int r = 0;
bool ram_retention = false;
int i;
/* check argument */
BUG_ON(epod_id >= NUM_EPOD_ID);
/* set flag if retention is possible */
switch (epod_id) {
case EPOD_ID_SVAMMDSP:
case EPOD_ID_SIAMMDSP:
case EPOD_ID_ESRAM12:
case EPOD_ID_ESRAM34:
ram_retention = true;
break;
}
/* check argument */
BUG_ON(epod_state > EPOD_STATE_ON);
BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
/* get lock */
mutex_lock(&mb2_transfer.lock);
/* wait for mailbox */
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
cpu_relax();
/* fill in mailbox */
for (i = 0; i < NUM_EPOD_ID; i++)
writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
/*
* The current firmware version does not handle errors correctly,
* and we cannot recover if there is an error.
* This is expected to change when the firmware is updated.
*/
if (!wait_for_completion_timeout(&mb2_transfer.work,
msecs_to_jiffies(20000))) {
pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
__func__);
r = -EIO;
goto unlock_and_return;
}
if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
r = -EIO;
unlock_and_return:
mutex_unlock(&mb2_transfer.lock);
return r;
}
/**
* prcmu_configure_auto_pm - Configure autonomous power management.
* @sleep: Configuration for ApSleep.
* @idle: Configuration for ApIdle.
*/
void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
struct prcmu_auto_pm_config *idle)
{
u32 sleep_cfg;
u32 idle_cfg;
unsigned long flags;
BUG_ON((sleep == NULL) || (idle == NULL));
sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
idle_cfg = (idle->sva_auto_pm_enable & 0xF);
idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
/*
* The autonomous power management configuration is done through
* fields in mailbox 2, but these fields are only used as shared
* variables - i.e. there is no need to send a message.
*/
writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
mb2_transfer.auto_pm_enabled =
((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
(sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
(idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
(idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
}
EXPORT_SYMBOL(prcmu_configure_auto_pm);
bool prcmu_is_auto_pm_enabled(void)
{
return mb2_transfer.auto_pm_enabled;
}
static int request_sysclk(bool enable)
{
int r;
unsigned long flags;
r = 0;
mutex_lock(&mb3_transfer.sysclk_lock);
spin_lock_irqsave(&mb3_transfer.lock, flags);
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
cpu_relax();
writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
spin_unlock_irqrestore(&mb3_transfer.lock, flags);
/*
* The firmware only sends an ACK if we want to enable the
* SysClk, and it succeeds.
*/
if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
msecs_to_jiffies(20000))) {
pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
__func__);
r = -EIO;
}
mutex_unlock(&mb3_transfer.sysclk_lock);
return r;
}
static int request_timclk(bool enable)
{
u32 val;
/*
* On the U8420_CLKSEL firmware, the ULP (Ultra Low Power)
* PLL is disabled so we cannot use doze mode, this will
* stop the clock on this firmware.
*/
if (prcmu_is_ulppll_disabled())
val = 0;
else
val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
if (!enable)
val |= PRCM_TCR_STOP_TIMERS |
PRCM_TCR_DOZE_MODE |
PRCM_TCR_TENSEL_MASK;
writel(val, PRCM_TCR);
return 0;
}
static int request_clock(u8 clock, bool enable)
{
u32 val;
unsigned long flags;
spin_lock_irqsave(&clk_mgt_lock, flags);
/* Grab the HW semaphore. */
while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
cpu_relax();
val = readl(prcmu_base + clk_mgt[clock].offset);
if (enable) {
val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
} else {
clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
}
writel(val, prcmu_base + clk_mgt[clock].offset);
/* Release the HW semaphore. */
writel(0, PRCM_SEM);
spin_unlock_irqrestore(&clk_mgt_lock, flags);
return 0;
}
static int request_sga_clock(u8 clock, bool enable)
{
u32 val;
int ret;
if (enable) {
val = readl(PRCM_CGATING_BYPASS);
writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
}
ret = request_clock(clock, enable);
if (!ret && !enable) {
val = readl(PRCM_CGATING_BYPASS);
writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
}
return ret;
}
static inline bool plldsi_locked(void)
{
return (readl(PRCM_PLLDSI_LOCKP) &
(PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
(PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
}
static int request_plldsi(bool enable)
{
int r = 0;
u32 val;
writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
val = readl(PRCM_PLLDSI_ENABLE);
if (enable)
val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
else
val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
writel(val, PRCM_PLLDSI_ENABLE);
if (enable) {
unsigned int i;
bool locked = plldsi_locked();
for (i = 10; !locked && (i > 0); --i) {
udelay(100);
locked = plldsi_locked();
}
if (locked) {
writel(PRCM_APE_RESETN_DSIPLL_RESETN,
PRCM_APE_RESETN_SET);
} else {
writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
PRCM_MMIP_LS_CLAMP_SET);
val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
writel(val, PRCM_PLLDSI_ENABLE);
r = -EAGAIN;
}
} else {
writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
}
return r;
}
static int request_dsiclk(u8 n, bool enable)
{
u32 val;
val = readl(PRCM_DSI_PLLOUT_SEL);
val &= ~dsiclk[n].divsel_mask;
val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
dsiclk[n].divsel_shift);
writel(val, PRCM_DSI_PLLOUT_SEL);
return 0;
}
static int request_dsiescclk(u8 n, bool enable)
{
u32 val;
val = readl(PRCM_DSITVCLK_DIV);
enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
writel(val, PRCM_DSITVCLK_DIV);
return 0;
}
/**
* db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
* @clock: The clock for which the request is made.
* @enable: Whether the clock should be enabled (true) or disabled (false).
*
* This function should only be used by the clock implementation.
* Do not use it from any other place!
*/
int db8500_prcmu_request_clock(u8 clock, bool enable)
{
if (clock == PRCMU_SGACLK)
return request_sga_clock(clock, enable);
else if (clock < PRCMU_NUM_REG_CLOCKS)
return request_clock(clock, enable);
else if (clock == PRCMU_TIMCLK)
return request_timclk(enable);
else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
else if (clock == PRCMU_PLLDSI)
return request_plldsi(enable);
else if (clock == PRCMU_SYSCLK)
return request_sysclk(enable);
else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
return request_pll(clock, enable);
else
return -EINVAL;
}
static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
int branch)
{
u64 rate;
u32 val;
u32 d;
u32 div = 1;
val = readl(reg);
rate = src_rate;
rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
if (d > 1)
div *= d;
d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
if (d > 1)
div *= d;
if (val & PRCM_PLL_FREQ_SELDIV2)
div *= 2;
if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
(val & PRCM_PLL_FREQ_DIV2EN) &&
((reg == PRCM_PLLSOC0_FREQ) ||
(reg == PRCM_PLLARM_FREQ) ||
(reg == PRCM_PLLDDR_FREQ))))
div *= 2;
(void)do_div(rate, div);
return (unsigned long)rate;
}
#define ROOT_CLOCK_RATE 38400000
static unsigned long clock_rate(u8 clock)
{
u32 val;
u32 pllsw;
unsigned long rate = ROOT_CLOCK_RATE;
val = readl(prcmu_base + clk_mgt[clock].offset);
if (val & PRCM_CLK_MGT_CLK38) {
if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
rate /= 2;
return rate;
}
val |= clk_mgt[clock].pllsw;
pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
else
return 0;
if ((clock == PRCMU_SGACLK) &&
(val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
u64 r = (rate * 10);
(void)do_div(r, 25);
return (unsigned long)r;
}
val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
if (val)
return rate / val;
else
return 0;
}
static unsigned long armss_rate(void)
{
u32 r;
unsigned long rate;
r = readl(PRCM_ARM_CHGCLKREQ);
if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
/* External ARMCLKFIX clock */
rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
/* Check PRCM_ARM_CHGCLKREQ divider */
if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
rate /= 2;
/* Check PRCM_ARMCLKFIX_MGT divider */
r = readl(PRCM_ARMCLKFIX_MGT);
r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
rate /= r;
} else {/* ARM PLL */
rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
}
return rate;
}
static unsigned long dsiclk_rate(u8 n)
{
u32 divsel;
u32 div = 1;
divsel = readl(PRCM_DSI_PLLOUT_SEL);
divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
divsel = dsiclk[n].divsel;
else
dsiclk[n].divsel = divsel;
switch (divsel) {
case PRCM_DSI_PLLOUT_SEL_PHI_4:
div *= 2;
fallthrough;
case PRCM_DSI_PLLOUT_SEL_PHI_2:
div *= 2;
fallthrough;
case PRCM_DSI_PLLOUT_SEL_PHI:
return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
PLL_RAW) / div;
default:
return 0;
}
}
static unsigned long dsiescclk_rate(u8 n)
{
u32 div;
div = readl(PRCM_DSITVCLK_DIV);
div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
}
unsigned long prcmu_clock_rate(u8 clock)
{
if (clock < PRCMU_NUM_REG_CLOCKS)
return clock_rate(clock);
else if (clock == PRCMU_TIMCLK)
return prcmu_is_ulppll_disabled() ?
32768 : ROOT_CLOCK_RATE / 16;
else if (clock == PRCMU_SYSCLK)
return ROOT_CLOCK_RATE;
else if (clock == PRCMU_PLLSOC0)
return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
else if (clock == PRCMU_PLLSOC1)
return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
else if (clock == PRCMU_ARMSS)
return armss_rate();
else if (clock == PRCMU_PLLDDR)
return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
else if (clock == PRCMU_PLLDSI)
return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
PLL_RAW);
else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
return dsiclk_rate(clock - PRCMU_DSI0CLK);
else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
else
return 0;
}
static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
{
if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
return ROOT_CLOCK_RATE;
clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
else
return 0;
}
static u32 clock_divider(unsigned long src_rate, unsigned long rate)
{
u32 div;
div = (src_rate / rate);
if (div == 0)
return 1;
if (rate < (src_rate / div))
div++;
return div;
}
static long round_clock_rate(u8 clock, unsigned long rate)
{
u32 val;
u32 div;
unsigned long src_rate;
long rounded_rate;
val = readl(prcmu_base + clk_mgt[clock].offset);
src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
clk_mgt[clock].branch);
div = clock_divider(src_rate, rate);
if (val & PRCM_CLK_MGT_CLK38) {
if (clk_mgt[clock].clk38div) {
if (div > 2)
div = 2;
} else {
div = 1;
}
} else if ((clock == PRCMU_SGACLK) && (div == 3)) {
u64 r = (src_rate * 10);
(void)do_div(r, 25);
if (r <= rate)
return (unsigned long)r;
}
rounded_rate = (src_rate / min(div, (u32)31));
return rounded_rate;
}
static const unsigned long db8500_armss_freqs[] = {
199680000,
399360000,
798720000,
998400000
};
/* The DB8520 has slightly higher ARMSS max frequency */
static const unsigned long db8520_armss_freqs[] = {
199680000,
399360000,
798720000,
1152000000
};
static long round_armss_rate(unsigned long rate)
{
unsigned long freq = 0;
const unsigned long *freqs;
int nfreqs;
int i;
if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
freqs = db8520_armss_freqs;
nfreqs = ARRAY_SIZE(db8520_armss_freqs);
} else {
freqs = db8500_armss_freqs;
nfreqs = ARRAY_SIZE(db8500_armss_freqs);
}
/* Find the corresponding arm opp from the cpufreq table. */
for (i = 0; i < nfreqs; i++) {
freq = freqs[i];
if (rate <= freq)
break;
}
/* Return the last valid value, even if a match was not found. */
return freq;
}
#define MIN_PLL_VCO_RATE 600000000ULL
#define MAX_PLL_VCO_RATE 1680640000ULL
static long round_plldsi_rate(unsigned long rate)
{
long rounded_rate = 0;
unsigned long src_rate;
unsigned long rem;
u32 r;
src_rate = clock_rate(PRCMU_HDMICLK);
rem = rate;
for (r = 7; (rem > 0) && (r > 0); r--) {
u64 d;
d = (r * rate);
(void)do_div(d, src_rate);
if (d < 6)
d = 6;
else if (d > 255)
d = 255;
d *= src_rate;
if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
((r * MAX_PLL_VCO_RATE) < (2 * d)))
continue;
(void)do_div(d, r);
if (rate < d) {
if (rounded_rate == 0)
rounded_rate = (long)d;
break;
}
if ((rate - d) < rem) {
rem = (rate - d);
rounded_rate = (long)d;
}
}
return rounded_rate;
}
static long round_dsiclk_rate(unsigned long rate)
{
u32 div;
unsigned long src_rate;
long rounded_rate;
src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
PLL_RAW);
div = clock_divider(src_rate, rate);
rounded_rate = (src_rate / ((div > 2) ? 4 : div));
return rounded_rate;
}
static long round_dsiescclk_rate(unsigned long rate)
{
u32 div;
unsigned long src_rate;
long rounded_rate;
src_rate = clock_rate(PRCMU_TVCLK);
div = clock_divider(src_rate, rate);
rounded_rate = (src_rate / min(div, (u32)255));
return rounded_rate;
}
long prcmu_round_clock_rate(u8 clock, unsigned long rate)
{
if (clock < PRCMU_NUM_REG_CLOCKS)
return round_clock_rate(clock, rate);
else if (clock == PRCMU_ARMSS)
return round_armss_rate(rate);
else if (clock == PRCMU_PLLDSI)
return round_plldsi_rate(rate);
else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
return round_dsiclk_rate(rate);
else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
return round_dsiescclk_rate(rate);
else
return (long)prcmu_clock_rate(clock);
}
static void set_clock_rate(u8 clock, unsigned long rate)
{
u32 val;
u32 div;
unsigned long src_rate;
unsigned long flags;
spin_lock_irqsave(&clk_mgt_lock, flags);
/* Grab the HW semaphore. */
while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
cpu_relax();
val = readl(prcmu_base + clk_mgt[clock].offset);
src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
clk_mgt[clock].branch);
div = clock_divider(src_rate, rate);
if (val & PRCM_CLK_MGT_CLK38) {
if (clk_mgt[clock].clk38div) {
if (div > 1)
val |= PRCM_CLK_MGT_CLK38DIV;
else
val &= ~PRCM_CLK_MGT_CLK38DIV;
}
} else if (clock == PRCMU_SGACLK) {
val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
if (div == 3) {
u64 r = (src_rate * 10);
(void)do_div(r, 25);
if (r <= rate) {
val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
div = 0;
}
}
val |= min(div, (u32)31);
} else {
val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
val |= min(div, (u32)31);
}
writel(val, prcmu_base + clk_mgt[clock].offset);
/* Release the HW semaphore. */
writel(0, PRCM_SEM);
spin_unlock_irqrestore(&clk_mgt_lock, flags);
}
static int set_armss_rate(unsigned long rate)
{
unsigned long freq;
u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP };
const unsigned long *freqs;
int nfreqs;
int i;
if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
freqs = db8520_armss_freqs;
nfreqs = ARRAY_SIZE(db8520_armss_freqs);
} else {
freqs = db8500_armss_freqs;
nfreqs = ARRAY_SIZE(db8500_armss_freqs);
}
/* Find the corresponding arm opp from the cpufreq table. */
for (i = 0; i < nfreqs; i++) {
freq = freqs[i];
if (rate == freq)
break;
}
if (rate != freq)
return -EINVAL;
/* Set the new arm opp. */
pr_debug("SET ARM OPP 0x%02x\n", opps[i]);
return db8500_prcmu_set_arm_opp(opps[i]);
}
static int set_plldsi_rate(unsigned long rate)
{
unsigned long src_rate;
unsigned long rem;
u32 pll_freq = 0;
u32 r;
src_rate = clock_rate(PRCMU_HDMICLK);
rem = rate;
for (r = 7; (rem > 0) && (r > 0); r--) {
u64 d;
u64 hwrate;
d = (r * rate);
(void)do_div(d, src_rate);
if (d < 6)
d = 6;
else if (d > 255)
d = 255;
hwrate = (d * src_rate);
if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
continue;
(void)do_div(hwrate, r);
if (rate < hwrate) {
if (pll_freq == 0)
pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
(r << PRCM_PLL_FREQ_R_SHIFT));
break;
}
if ((rate - hwrate) < rem) {
rem = (rate - hwrate);
pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
(r << PRCM_PLL_FREQ_R_SHIFT));
}
}
if (pll_freq == 0)
return -EINVAL;
pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
writel(pll_freq, PRCM_PLLDSI_FREQ);
return 0;
}
static void set_dsiclk_rate(u8 n, unsigned long rate)
{
u32 val;
u32 div;
div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
(div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
/* else */ PRCM_DSI_PLLOUT_SEL_PHI_4;
val = readl(PRCM_DSI_PLLOUT_SEL);
val &= ~dsiclk[n].divsel_mask;
val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
writel(val, PRCM_DSI_PLLOUT_SEL);
}
static void set_dsiescclk_rate(u8 n, unsigned long rate)
{
u32 val;
u32 div;
div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
val = readl(PRCM_DSITVCLK_DIV);
val &= ~dsiescclk[n].div_mask;
val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
writel(val, PRCM_DSITVCLK_DIV);
}
int prcmu_set_clock_rate(u8 clock, unsigned long rate)
{
if (clock < PRCMU_NUM_REG_CLOCKS)
set_clock_rate(clock, rate);
else if (clock == PRCMU_ARMSS)
return set_armss_rate(rate);
else if (clock == PRCMU_PLLDSI)
return set_plldsi_rate(rate);
else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
return 0;
}
int db8500_prcmu_config_esram0_deep_sleep(u8 state)
{
if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
(state < ESRAM0_DEEP_SLEEP_STATE_OFF))
return -EINVAL;
mutex_lock(&mb4_transfer.lock);
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
cpu_relax();
writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
(tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
writeb(DDR_PWR_STATE_ON,
(tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
wait_for_completion(&mb4_transfer.work);
mutex_unlock(&mb4_transfer.lock);
return 0;
}
int db8500_prcmu_config_hotdog(u8 threshold)
{
mutex_lock(&mb4_transfer.lock);
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
cpu_relax();
writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
wait_for_completion(&mb4_transfer.work);
mutex_unlock(&mb4_transfer.lock);
return 0;
}
int db8500_prcmu_config_hotmon(u8 low, u8 high)
{
mutex_lock(&mb4_transfer.lock);
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
cpu_relax();
writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
(tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
wait_for_completion(&mb4_transfer.work);
mutex_unlock(&mb4_transfer.lock);
return 0;
}
EXPORT_SYMBOL_GPL(db8500_prcmu_config_hotmon);
static int config_hot_period(u16 val)
{
mutex_lock(&mb4_transfer.lock);
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
cpu_relax();
writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
wait_for_completion(&mb4_transfer.work);
mutex_unlock(&mb4_transfer.lock);
return 0;
}
int db8500_prcmu_start_temp_sense(u16 cycles32k)
{
if (cycles32k == 0xFFFF)
return -EINVAL;
return config_hot_period(cycles32k);
}
EXPORT_SYMBOL_GPL(db8500_prcmu_start_temp_sense);
int db8500_prcmu_stop_temp_sense(void)
{
return config_hot_period(0xFFFF);
}
EXPORT_SYMBOL_GPL(db8500_prcmu_stop_temp_sense);
static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
{
mutex_lock(&mb4_transfer.lock);
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
cpu_relax();
writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
wait_for_completion(&mb4_transfer.work);
mutex_unlock(&mb4_transfer.lock);
return 0;
}
int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
{
BUG_ON(num == 0 || num > 0xf);
return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
A9WDOG_AUTO_OFF_DIS);
}
EXPORT_SYMBOL(db8500_prcmu_config_a9wdog);
int db8500_prcmu_enable_a9wdog(u8 id)
{
return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
}
EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog);
int db8500_prcmu_disable_a9wdog(u8 id)
{
return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
}
EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog);
int db8500_prcmu_kick_a9wdog(u8 id)
{
return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
}
EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog);
/*
* timeout is 28 bit, in ms.
*/
int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
{
return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
(id & A9WDOG_ID_MASK) |
/*
* Put the lowest 28 bits of timeout at
* offset 4. Four first bits are used for id.
*/
(u8)((timeout << 4) & 0xf0),
(u8)((timeout >> 4) & 0xff),
(u8)((timeout >> 12) & 0xff),
(u8)((timeout >> 20) & 0xff));
}
EXPORT_SYMBOL(db8500_prcmu_load_a9wdog);
/**
* prcmu_abb_read() - Read register value(s) from the ABB.
* @slave: The I2C slave address.
* @reg: The (start) register address.
* @value: The read out value(s).
* @size: The number of registers to read.
*
* Reads register value(s) from the ABB.
* @size has to be 1 for the current firmware version.
*/
int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
{
int r;
if (size != 1)
return -EINVAL;
mutex_lock(&mb5_transfer.lock);
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
cpu_relax();
writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
if (!wait_for_completion_timeout(&mb5_transfer.work,
msecs_to_jiffies(20000))) {
pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
__func__);
r = -EIO;
} else {
r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
}
if (!r)
*value = mb5_transfer.ack.value;
mutex_unlock(&mb5_transfer.lock);
return r;
}
/**
* prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
* @slave: The I2C slave address.
* @reg: The (start) register address.
* @value: The value(s) to write.
* @mask: The mask(s) to use.
* @size: The number of registers to write.
*
* Writes masked register value(s) to the ABB.
* For each @value, only the bits set to 1 in the corresponding @mask
* will be written. The other bits are not changed.
* @size has to be 1 for the current firmware version.
*/
int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
{
int r;
if (size != 1)
return -EINVAL;
mutex_lock(&mb5_transfer.lock);
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
cpu_relax();
writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
if (!wait_for_completion_timeout(&mb5_transfer.work,
msecs_to_jiffies(20000))) {
pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
__func__);
r = -EIO;
} else {
r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
}
mutex_unlock(&mb5_transfer.lock);
return r;
}
/**
* prcmu_abb_write() - Write register value(s) to the ABB.
* @slave: The I2C slave address.
* @reg: The (start) register address.
* @value: The value(s) to write.
* @size: The number of registers to write.
*
* Writes register value(s) to the ABB.
* @size has to be 1 for the current firmware version.
*/
int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
{
u8 mask = ~0;
return prcmu_abb_write_masked(slave, reg, value, &mask, size);
}
/**
* prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
*/
int prcmu_ac_wake_req(void)
{
u32 val;
int ret = 0;
mutex_lock(&mb0_transfer.ac_wake_lock);
val = readl(PRCM_HOSTACCESS_REQ);
if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
goto unlock_and_return;
atomic_set(&ac_wake_req_state, 1);
/*
* Force Modem Wake-up before hostaccess_req ping-pong.
* It prevents Modem to enter in Sleep while acking the hostaccess
* request. The 31us delay has been calculated by HWI.
*/
val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
writel(val, PRCM_HOSTACCESS_REQ);
udelay(31);
val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
writel(val, PRCM_HOSTACCESS_REQ);
if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
msecs_to_jiffies(5000))) {
pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
__func__);
ret = -EFAULT;
}
unlock_and_return:
mutex_unlock(&mb0_transfer.ac_wake_lock);
return ret;
}
/**
* prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
*/
void prcmu_ac_sleep_req(void)
{
u32 val;
mutex_lock(&mb0_transfer.ac_wake_lock);
val = readl(PRCM_HOSTACCESS_REQ);
if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
goto unlock_and_return;
writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
PRCM_HOSTACCESS_REQ);
if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
msecs_to_jiffies(5000))) {
pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
__func__);
}
atomic_set(&ac_wake_req_state, 0);
unlock_and_return:
mutex_unlock(&mb0_transfer.ac_wake_lock);
}
bool db8500_prcmu_is_ac_wake_requested(void)
{
return (atomic_read(&ac_wake_req_state) != 0);
}
/**
* db8500_prcmu_system_reset - System reset
*
* Saves the reset reason code and then sets the APE_SOFTRST register which
* fires interrupt to fw
*
* @reset_code: The reason for system reset
*/
void db8500_prcmu_system_reset(u16 reset_code)
{
writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
writel(1, PRCM_APE_SOFTRST);
}
/**
* db8500_prcmu_get_reset_code - Retrieve SW reset reason code
*
* Retrieves the reset reason code stored by prcmu_system_reset() before
* last restart.
*/
u16 db8500_prcmu_get_reset_code(void)
{
return readw(tcdm_base + PRCM_SW_RST_REASON);
}
/**
* db8500_prcmu_modem_reset - ask the PRCMU to reset modem
*/
void db8500_prcmu_modem_reset(void)
{
mutex_lock(&mb1_transfer.lock);
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
cpu_relax();
writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
wait_for_completion(&mb1_transfer.work);
/*
* No need to check return from PRCMU as modem should go in reset state
* This state is already managed by upper layer
*/
mutex_unlock(&mb1_transfer.lock);
}
static void ack_dbb_wakeup(void)
{
unsigned long flags;
spin_lock_irqsave(&mb0_transfer.lock, flags);
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
cpu_relax();
writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
spin_unlock_irqrestore(&mb0_transfer.lock, flags);
}
static inline void print_unknown_header_warning(u8 n, u8 header)
{
pr_warn("prcmu: Unknown message header (%d) in mailbox %d\n",
header, n);
}
static bool read_mailbox_0(void)
{
bool r;
u32 ev;
unsigned int n;
u8 header;
header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
switch (header) {
case MB0H_WAKEUP_EXE:
case MB0H_WAKEUP_SLEEP:
if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
else
ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
complete(&mb0_transfer.ac_wake_work);
if (ev & WAKEUP_BIT_SYSCLK_OK)
complete(&mb3_transfer.sysclk_work);
ev &= mb0_transfer.req.dbb_irqs;
for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
if (ev & prcmu_irq_bit[n])
generic_handle_domain_irq(db8500_irq_domain, n);
}
r = true;
break;
default:
print_unknown_header_warning(0, header);
r = false;
break;
}
writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
return r;
}
static bool read_mailbox_1(void)
{
mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
mb1_transfer.ack.arm_opp = readb(tcdm_base +
PRCM_ACK_MB1_CURRENT_ARM_OPP);
mb1_transfer.ack.ape_opp = readb(tcdm_base +
PRCM_ACK_MB1_CURRENT_APE_OPP);
mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
complete(&mb1_transfer.work);
return false;
}
static bool read_mailbox_2(void)
{
mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
complete(&mb2_transfer.work);
return false;
}
static bool read_mailbox_3(void)
{
writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
return false;
}
static bool read_mailbox_4(void)
{
u8 header;
bool do_complete = true;
header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
switch (header) {
case MB4H_MEM_ST:
case MB4H_HOTDOG:
case MB4H_HOTMON:
case MB4H_HOT_PERIOD:
case MB4H_A9WDOG_CONF:
case MB4H_A9WDOG_EN:
case MB4H_A9WDOG_DIS:
case MB4H_A9WDOG_LOAD:
case MB4H_A9WDOG_KICK:
break;
default:
print_unknown_header_warning(4, header);
do_complete = false;
break;
}
writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
if (do_complete)
complete(&mb4_transfer.work);
return false;
}
static bool read_mailbox_5(void)
{
mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
complete(&mb5_transfer.work);
return false;
}
static bool read_mailbox_6(void)
{
writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
return false;
}
static bool read_mailbox_7(void)
{
writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
return false;
}
static bool (* const read_mailbox[NUM_MB])(void) = {
read_mailbox_0,
read_mailbox_1,
read_mailbox_2,
read_mailbox_3,
read_mailbox_4,
read_mailbox_5,
read_mailbox_6,
read_mailbox_7
};
static irqreturn_t prcmu_irq_handler(int irq, void *data)
{
u32 bits;
u8 n;
irqreturn_t r;
bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
if (unlikely(!bits))
return IRQ_NONE;
r = IRQ_HANDLED;
for (n = 0; bits; n++) {
if (bits & MBOX_BIT(n)) {
bits -= MBOX_BIT(n);
if (read_mailbox[n]())
r = IRQ_WAKE_THREAD;
}
}
return r;
}
static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
{
ack_dbb_wakeup();
return IRQ_HANDLED;
}
static void prcmu_mask_work(struct work_struct *work)
{
unsigned long flags;
spin_lock_irqsave(&mb0_transfer.lock, flags);
config_wakeups();
spin_unlock_irqrestore(&mb0_transfer.lock, flags);
}
static void prcmu_irq_mask(struct irq_data *d)
{
unsigned long flags;
spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
if (d->irq != IRQ_PRCMU_CA_SLEEP)
schedule_work(&mb0_transfer.mask_work);
}
static void prcmu_irq_unmask(struct irq_data *d)
{
unsigned long flags;
spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
if (d->irq != IRQ_PRCMU_CA_SLEEP)
schedule_work(&mb0_transfer.mask_work);
}
static void noop(struct irq_data *d)
{
}
static struct irq_chip prcmu_irq_chip = {
.name = "prcmu",
.irq_disable = prcmu_irq_mask,
.irq_ack = noop,
.irq_mask = prcmu_irq_mask,
.irq_unmask = prcmu_irq_unmask,
};
static char *fw_project_name(u32 project)
{
switch (project) {
case PRCMU_FW_PROJECT_U8500:
return "U8500";
case PRCMU_FW_PROJECT_U8400:
return "U8400";
case PRCMU_FW_PROJECT_U9500:
return "U9500";
case PRCMU_FW_PROJECT_U8500_MBB:
return "U8500 MBB";
case PRCMU_FW_PROJECT_U8500_C1:
return "U8500 C1";
case PRCMU_FW_PROJECT_U8500_C2:
return "U8500 C2";
case PRCMU_FW_PROJECT_U8500_C3:
return "U8500 C3";
case PRCMU_FW_PROJECT_U8500_C4:
return "U8500 C4";
case PRCMU_FW_PROJECT_U9500_MBL:
return "U9500 MBL";
case PRCMU_FW_PROJECT_U8500_SSG1:
return "U8500 Samsung 1";
case PRCMU_FW_PROJECT_U8500_MBL2:
return "U8500 MBL2";
case PRCMU_FW_PROJECT_U8520:
return "U8520 MBL";
case PRCMU_FW_PROJECT_U8420:
return "U8420";
case PRCMU_FW_PROJECT_U8500_SSG2:
return "U8500 Samsung 2";
case PRCMU_FW_PROJECT_U8420_SYSCLK:
return "U8420-sysclk";
case PRCMU_FW_PROJECT_U9540:
return "U9540";
case PRCMU_FW_PROJECT_A9420:
return "A9420";
case PRCMU_FW_PROJECT_L8540:
return "L8540";
case PRCMU_FW_PROJECT_L8580:
return "L8580";
default:
return "Unknown";
}
}
static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hwirq)
{
irq_set_chip_and_handler(virq, &prcmu_irq_chip,
handle_simple_irq);
return 0;
}
static const struct irq_domain_ops db8500_irq_ops = {
.map = db8500_irq_map,
.xlate = irq_domain_xlate_twocell,
};
static int db8500_irq_init(struct device_node *np)
{
int i;
db8500_irq_domain = irq_domain_add_simple(
np, NUM_PRCMU_WAKEUPS, 0,
&db8500_irq_ops, NULL);
if (!db8500_irq_domain) {
pr_err("Failed to create irqdomain\n");
return -ENOSYS;
}
/* All wakeups will be used, so create mappings for all */
for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
irq_create_mapping(db8500_irq_domain, i);
return 0;
}
static void dbx500_fw_version_init(struct device_node *np)
{
void __iomem *tcpm_base;
u32 version;
tcpm_base = of_iomap(np, 1);
if (!tcpm_base) {
pr_err("no prcmu tcpm mem region provided\n");
return;
}
version = readl(tcpm_base + DB8500_PRCMU_FW_VERSION_OFFSET);
fw_info.version.project = (version & 0xFF);
fw_info.version.api_version = (version >> 8) & 0xFF;
fw_info.version.func_version = (version >> 16) & 0xFF;
fw_info.version.errata = (version >> 24) & 0xFF;
strncpy(fw_info.version.project_name,
fw_project_name(fw_info.version.project),
PRCMU_FW_PROJECT_NAME_LEN);
fw_info.valid = true;
pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
fw_info.version.project_name,
fw_info.version.project,
fw_info.version.api_version,
fw_info.version.func_version,
fw_info.version.errata);
iounmap(tcpm_base);
}
void __init db8500_prcmu_early_init(void)
{
/*
* This is a temporary remap to bring up the clocks. It is
* subsequently replaces with a real remap. After the merge of
* the mailbox subsystem all of this early code goes away, and the
* clock driver can probe independently. An early initcall will
* still be needed, but it can be diverted into drivers/clk/ux500.
*/
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu");
prcmu_base = of_iomap(np, 0);
if (!prcmu_base) {
of_node_put(np);
pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
return;
}
dbx500_fw_version_init(np);
of_node_put(np);
spin_lock_init(&mb0_transfer.lock);
spin_lock_init(&mb0_transfer.dbb_irqs_lock);
mutex_init(&mb0_transfer.ac_wake_lock);
init_completion(&mb0_transfer.ac_wake_work);
mutex_init(&mb1_transfer.lock);
init_completion(&mb1_transfer.work);
mb1_transfer.ape_opp = APE_NO_CHANGE;
mutex_init(&mb2_transfer.lock);
init_completion(&mb2_transfer.work);
spin_lock_init(&mb2_transfer.auto_pm_lock);
spin_lock_init(&mb3_transfer.lock);
mutex_init(&mb3_transfer.sysclk_lock);
init_completion(&mb3_transfer.sysclk_work);
mutex_init(&mb4_transfer.lock);
init_completion(&mb4_transfer.work);
mutex_init(&mb5_transfer.lock);
init_completion(&mb5_transfer.work);
INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
}
static void init_prcm_registers(void)
{
u32 val;
val = readl(PRCM_A9PL_FORCE_CLKEN);
val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
writel(val, (PRCM_A9PL_FORCE_CLKEN));
}
/*
* Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
*/
static struct regulator_consumer_supply db8500_vape_consumers[] = {
REGULATOR_SUPPLY("v-ape", NULL),
REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
/* "v-mmc" changed to "vcore" in the mainline kernel */
REGULATOR_SUPPLY("vcore", "sdi0"),
REGULATOR_SUPPLY("vcore", "sdi1"),
REGULATOR_SUPPLY("vcore", "sdi2"),
REGULATOR_SUPPLY("vcore", "sdi3"),
REGULATOR_SUPPLY("vcore", "sdi4"),
REGULATOR_SUPPLY("v-dma", "dma40.0"),
REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
/* "v-uart" changed to "vcore" in the mainline kernel */
REGULATOR_SUPPLY("vcore", "uart0"),
REGULATOR_SUPPLY("vcore", "uart1"),
REGULATOR_SUPPLY("vcore", "uart2"),
REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
};
static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
/* AV8100 regulator */
REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
};
static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
REGULATOR_SUPPLY("vsupply", "mcde"),
};
/* SVA MMDSP regulator switch */
static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
};
/* SVA pipe regulator switch */
static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
REGULATOR_SUPPLY("sva-pipe", "cm_control"),
};
/* SIA MMDSP regulator switch */
static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
};
/* SIA pipe regulator switch */
static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
REGULATOR_SUPPLY("sia-pipe", "cm_control"),
};
static struct regulator_consumer_supply db8500_sga_consumers[] = {
REGULATOR_SUPPLY("v-mali", NULL),
};
/* ESRAM1 and 2 regulator switch */
static struct regulator_consumer_supply db8500_esram12_consumers[] = {
REGULATOR_SUPPLY("esram12", "cm_control"),
};
/* ESRAM3 and 4 regulator switch */
static struct regulator_consumer_supply db8500_esram34_consumers[] = {
REGULATOR_SUPPLY("v-esram34", "mcde"),
REGULATOR_SUPPLY("esram34", "cm_control"),
REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
};
static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
[DB8500_REGULATOR_VAPE] = {
.constraints = {
.name = "db8500-vape",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.always_on = true,
},
.consumer_supplies = db8500_vape_consumers,
.num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
},
[DB8500_REGULATOR_VARM] = {
.constraints = {
.name = "db8500-varm",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
},
[DB8500_REGULATOR_VMODEM] = {
.constraints = {
.name = "db8500-vmodem",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
},
[DB8500_REGULATOR_VPLL] = {
.constraints = {
.name = "db8500-vpll",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
},
[DB8500_REGULATOR_VSMPS1] = {
.constraints = {
.name = "db8500-vsmps1",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
},
[DB8500_REGULATOR_VSMPS2] = {
.constraints = {
.name = "db8500-vsmps2",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.consumer_supplies = db8500_vsmps2_consumers,
.num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
},
[DB8500_REGULATOR_VSMPS3] = {
.constraints = {
.name = "db8500-vsmps3",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
},
[DB8500_REGULATOR_VRF1] = {
.constraints = {
.name = "db8500-vrf1",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
},
[DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
/* dependency to u8500-vape is handled outside regulator framework */
.constraints = {
.name = "db8500-sva-mmdsp",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.consumer_supplies = db8500_svammdsp_consumers,
.num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
},
[DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
.constraints = {
/* "ret" means "retention" */
.name = "db8500-sva-mmdsp-ret",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
},
[DB8500_REGULATOR_SWITCH_SVAPIPE] = {
/* dependency to u8500-vape is handled outside regulator framework */
.constraints = {
.name = "db8500-sva-pipe",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.consumer_supplies = db8500_svapipe_consumers,
.num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
},
[DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
/* dependency to u8500-vape is handled outside regulator framework */
.constraints = {
.name = "db8500-sia-mmdsp",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.consumer_supplies = db8500_siammdsp_consumers,
.num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
},
[DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
.constraints = {
.name = "db8500-sia-mmdsp-ret",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
},
[DB8500_REGULATOR_SWITCH_SIAPIPE] = {
/* dependency to u8500-vape is handled outside regulator framework */
.constraints = {
.name = "db8500-sia-pipe",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.consumer_supplies = db8500_siapipe_consumers,
.num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
},
[DB8500_REGULATOR_SWITCH_SGA] = {
.supply_regulator = "db8500-vape",
.constraints = {
.name = "db8500-sga",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.consumer_supplies = db8500_sga_consumers,
.num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
},
[DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
.supply_regulator = "db8500-vape",
.constraints = {
.name = "db8500-b2r2-mcde",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.consumer_supplies = db8500_b2r2_mcde_consumers,
.num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
},
[DB8500_REGULATOR_SWITCH_ESRAM12] = {
/*
* esram12 is set in retention and supplied by Vsafe when Vape is off,
* no need to hold Vape
*/
.constraints = {
.name = "db8500-esram12",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.consumer_supplies = db8500_esram12_consumers,
.num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
},
[DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
.constraints = {
.name = "db8500-esram12-ret",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
},
[DB8500_REGULATOR_SWITCH_ESRAM34] = {
/*
* esram34 is set in retention and supplied by Vsafe when Vape is off,
* no need to hold Vape
*/
.constraints = {
.name = "db8500-esram34",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.consumer_supplies = db8500_esram34_consumers,
.num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
},
[DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
.constraints = {
.name = "db8500-esram34-ret",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
},
};
static const struct mfd_cell common_prcmu_devs[] = {
MFD_CELL_NAME("db8500_wdt"),
MFD_CELL_NAME("db8500-cpuidle"),
};
static const struct mfd_cell db8500_prcmu_devs[] = {
MFD_CELL_OF("db8500-prcmu-regulators", NULL,
&db8500_regulators, sizeof(db8500_regulators), 0,
"stericsson,db8500-prcmu-regulator"),
MFD_CELL_OF("db8500-thermal",
NULL, NULL, 0, 0, "stericsson,db8500-thermal"),
};
static int db8500_prcmu_register_ab8500(struct device *parent)
{
struct device_node *np;
struct resource ab850x_resource;
const struct mfd_cell ab8500_cell = {
.name = "ab8500-core",
.of_compatible = "stericsson,ab8500",
.id = AB8500_VERSION_AB8500,
.resources = &ab850x_resource,
.num_resources = 1,
};
const struct mfd_cell ab8505_cell = {
.name = "ab8505-core",
.of_compatible = "stericsson,ab8505",
.id = AB8500_VERSION_AB8505,
.resources = &ab850x_resource,
.num_resources = 1,
};
const struct mfd_cell *ab850x_cell;
if (!parent->of_node)
return -ENODEV;
/* Look up the device node, sneak the IRQ out of it */
for_each_child_of_node(parent->of_node, np) {
if (of_device_is_compatible(np, ab8500_cell.of_compatible)) {
ab850x_cell = &ab8500_cell;
break;
}
if (of_device_is_compatible(np, ab8505_cell.of_compatible)) {
ab850x_cell = &ab8505_cell;
break;
}
}
if (!np) {
dev_info(parent, "could not find AB850X node in the device tree\n");
return -ENODEV;
}
of_irq_to_resource_table(np, &ab850x_resource, 1);
return mfd_add_devices(parent, 0, ab850x_cell, 1, NULL, 0, NULL);
}
static int db8500_prcmu_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
int irq = 0, err = 0;
struct resource *res;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
if (!res) {
dev_err(&pdev->dev, "no prcmu memory region provided\n");
return -EINVAL;
}
prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
if (!prcmu_base) {
dev_err(&pdev->dev,
"failed to ioremap prcmu register memory\n");
return -ENOMEM;
}
init_prcm_registers();
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
if (!res) {
dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
return -EINVAL;
}
tcdm_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!tcdm_base) {
dev_err(&pdev->dev,
"failed to ioremap prcmu-tcdm register memory\n");
return -ENOMEM;
}
/* Clean up the mailbox interrupts after pre-kernel code. */
writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
irq = platform_get_irq(pdev, 0);
if (irq <= 0)
return irq;
err = request_threaded_irq(irq, prcmu_irq_handler,
prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
if (err < 0) {
pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
return err;
}
db8500_irq_init(np);
prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
if (err) {
pr_err("prcmu: Failed to add subdevices\n");
return err;
}
/* TODO: Remove restriction when clk definitions are available. */
if (!of_machine_is_compatible("st-ericsson,u8540")) {
err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
ARRAY_SIZE(db8500_prcmu_devs), NULL, 0,
db8500_irq_domain);
if (err) {
mfd_remove_devices(&pdev->dev);
pr_err("prcmu: Failed to add subdevices\n");
return err;
}
}
err = db8500_prcmu_register_ab8500(&pdev->dev);
if (err) {
mfd_remove_devices(&pdev->dev);
pr_err("prcmu: Failed to add ab8500 subdevice\n");
return err;
}
pr_info("DB8500 PRCMU initialized\n");
return err;
}
static const struct of_device_id db8500_prcmu_match[] = {
{ .compatible = "stericsson,db8500-prcmu"},
{ },
};
static struct platform_driver db8500_prcmu_driver = {
.driver = {
.name = "db8500-prcmu",
.of_match_table = db8500_prcmu_match,
},
.probe = db8500_prcmu_probe,
};
static int __init db8500_prcmu_init(void)
{
return platform_driver_register(&db8500_prcmu_driver);
}
core_initcall(db8500_prcmu_init);
| linux-master | drivers/mfd/db8500-prcmu.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Intel LPSS ACPI support.
*
* Copyright (C) 2015, Intel Corporation
*
* Authors: Andy Shevchenko <[email protected]>
* Mika Westerberg <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/pxa2xx_ssp.h>
#include "intel-lpss.h"
static const struct property_entry spt_spi_properties[] = {
PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_SPT_SSP),
{ }
};
static const struct software_node spt_spi_node = {
.properties = spt_spi_properties,
};
static const struct intel_lpss_platform_info spt_info = {
.clk_rate = 120000000,
.swnode = &spt_spi_node,
};
static const struct property_entry spt_i2c_properties[] = {
PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 230),
{ },
};
static const struct software_node spt_i2c_node = {
.properties = spt_i2c_properties,
};
static const struct intel_lpss_platform_info spt_i2c_info = {
.clk_rate = 120000000,
.swnode = &spt_i2c_node,
};
static const struct property_entry uart_properties[] = {
PROPERTY_ENTRY_U32("reg-io-width", 4),
PROPERTY_ENTRY_U32("reg-shift", 2),
PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
{ },
};
static const struct software_node uart_node = {
.properties = uart_properties,
};
static const struct intel_lpss_platform_info spt_uart_info = {
.clk_rate = 120000000,
.clk_con_id = "baudclk",
.swnode = &uart_node,
};
static const struct property_entry bxt_spi_properties[] = {
PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_BXT_SSP),
{ }
};
static const struct software_node bxt_spi_node = {
.properties = bxt_spi_properties,
};
static const struct intel_lpss_platform_info bxt_info = {
.clk_rate = 100000000,
.swnode = &bxt_spi_node,
};
static const struct property_entry bxt_i2c_properties[] = {
PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 42),
PROPERTY_ENTRY_U32("i2c-sda-falling-time-ns", 171),
PROPERTY_ENTRY_U32("i2c-scl-falling-time-ns", 208),
{ },
};
static const struct software_node bxt_i2c_node = {
.properties = bxt_i2c_properties,
};
static const struct intel_lpss_platform_info bxt_i2c_info = {
.clk_rate = 133000000,
.swnode = &bxt_i2c_node,
};
static const struct property_entry apl_i2c_properties[] = {
PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 207),
PROPERTY_ENTRY_U32("i2c-sda-falling-time-ns", 171),
PROPERTY_ENTRY_U32("i2c-scl-falling-time-ns", 208),
{ },
};
static const struct software_node apl_i2c_node = {
.properties = apl_i2c_properties,
};
static const struct intel_lpss_platform_info apl_i2c_info = {
.clk_rate = 133000000,
.swnode = &apl_i2c_node,
};
static const struct property_entry cnl_spi_properties[] = {
PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_CNL_SSP),
{ }
};
static const struct software_node cnl_spi_node = {
.properties = cnl_spi_properties,
};
static const struct intel_lpss_platform_info cnl_info = {
.clk_rate = 120000000,
.swnode = &cnl_spi_node,
};
static const struct intel_lpss_platform_info cnl_i2c_info = {
.clk_rate = 216000000,
.swnode = &spt_i2c_node,
};
static const struct acpi_device_id intel_lpss_acpi_ids[] = {
/* SPT */
{ "INT3440", (kernel_ulong_t)&spt_info },
{ "INT3441", (kernel_ulong_t)&spt_info },
{ "INT3442", (kernel_ulong_t)&spt_i2c_info },
{ "INT3443", (kernel_ulong_t)&spt_i2c_info },
{ "INT3444", (kernel_ulong_t)&spt_i2c_info },
{ "INT3445", (kernel_ulong_t)&spt_i2c_info },
{ "INT3446", (kernel_ulong_t)&spt_i2c_info },
{ "INT3447", (kernel_ulong_t)&spt_i2c_info },
{ "INT3448", (kernel_ulong_t)&spt_uart_info },
{ "INT3449", (kernel_ulong_t)&spt_uart_info },
{ "INT344A", (kernel_ulong_t)&spt_uart_info },
/* CNL */
{ "INT34B0", (kernel_ulong_t)&cnl_info },
{ "INT34B1", (kernel_ulong_t)&cnl_info },
{ "INT34B2", (kernel_ulong_t)&cnl_i2c_info },
{ "INT34B3", (kernel_ulong_t)&cnl_i2c_info },
{ "INT34B4", (kernel_ulong_t)&cnl_i2c_info },
{ "INT34B5", (kernel_ulong_t)&cnl_i2c_info },
{ "INT34B6", (kernel_ulong_t)&cnl_i2c_info },
{ "INT34B7", (kernel_ulong_t)&cnl_i2c_info },
{ "INT34B8", (kernel_ulong_t)&spt_uart_info },
{ "INT34B9", (kernel_ulong_t)&spt_uart_info },
{ "INT34BA", (kernel_ulong_t)&spt_uart_info },
{ "INT34BC", (kernel_ulong_t)&cnl_info },
/* BXT */
{ "80860AAC", (kernel_ulong_t)&bxt_i2c_info },
{ "80860ABC", (kernel_ulong_t)&bxt_info },
{ "80860AC2", (kernel_ulong_t)&bxt_info },
/* APL */
{ "80865AAC", (kernel_ulong_t)&apl_i2c_info },
{ "80865ABC", (kernel_ulong_t)&bxt_info },
{ "80865AC2", (kernel_ulong_t)&bxt_info },
{ }
};
MODULE_DEVICE_TABLE(acpi, intel_lpss_acpi_ids);
static int intel_lpss_acpi_probe(struct platform_device *pdev)
{
struct intel_lpss_platform_info *info;
const struct acpi_device_id *id;
int ret;
id = acpi_match_device(intel_lpss_acpi_ids, &pdev->dev);
if (!id)
return -ENODEV;
info = devm_kmemdup(&pdev->dev, (void *)id->driver_data, sizeof(*info),
GFP_KERNEL);
if (!info)
return -ENOMEM;
info->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!info->mem)
return -ENODEV;
info->irq = platform_get_irq(pdev, 0);
ret = intel_lpss_probe(&pdev->dev, info);
if (ret)
return ret;
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
return 0;
}
static int intel_lpss_acpi_remove(struct platform_device *pdev)
{
intel_lpss_remove(&pdev->dev);
pm_runtime_disable(&pdev->dev);
return 0;
}
static INTEL_LPSS_PM_OPS(intel_lpss_acpi_pm_ops);
static struct platform_driver intel_lpss_acpi_driver = {
.probe = intel_lpss_acpi_probe,
.remove = intel_lpss_acpi_remove,
.driver = {
.name = "intel-lpss",
.acpi_match_table = intel_lpss_acpi_ids,
.pm = &intel_lpss_acpi_pm_ops,
},
};
module_platform_driver(intel_lpss_acpi_driver);
MODULE_AUTHOR("Andy Shevchenko <[email protected]>");
MODULE_AUTHOR("Mika Westerberg <[email protected]>");
MODULE_DESCRIPTION("Intel LPSS ACPI driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/intel-lpss-acpi.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Intel MAX 10 Board Management Controller chip - common code
*
* Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
*/
#include <linux/bitfield.h>
#include <linux/device.h>
#include <linux/dev_printk.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel-m10-bmc.h>
#include <linux/module.h>
void m10bmc_fw_state_set(struct intel_m10bmc *m10bmc, enum m10bmc_fw_state new_state)
{
/* bmcfw_state is only needed if handshake_sys_reg_nranges > 0 */
if (!m10bmc->info->handshake_sys_reg_nranges)
return;
down_write(&m10bmc->bmcfw_lock);
m10bmc->bmcfw_state = new_state;
up_write(&m10bmc->bmcfw_lock);
}
EXPORT_SYMBOL_NS_GPL(m10bmc_fw_state_set, INTEL_M10_BMC_CORE);
/*
* For some Intel FPGA devices, the BMC firmware is not available to service
* handshake registers during a secure update.
*/
static bool m10bmc_reg_always_available(struct intel_m10bmc *m10bmc, unsigned int offset)
{
if (!m10bmc->info->handshake_sys_reg_nranges)
return true;
return !regmap_reg_in_ranges(offset, m10bmc->info->handshake_sys_reg_ranges,
m10bmc->info->handshake_sys_reg_nranges);
}
/*
* m10bmc_handshake_reg_unavailable - Checks if reg access collides with secure update state
* @m10bmc: M10 BMC structure
*
* For some Intel FPGA devices, the BMC firmware is not available to service
* handshake registers during a secure update erase and write phases.
*
* Context: @m10bmc->bmcfw_lock must be held.
*/
static bool m10bmc_handshake_reg_unavailable(struct intel_m10bmc *m10bmc)
{
return m10bmc->bmcfw_state == M10BMC_FW_STATE_SEC_UPDATE_PREPARE ||
m10bmc->bmcfw_state == M10BMC_FW_STATE_SEC_UPDATE_WRITE;
}
/*
* This function helps to simplify the accessing of the system registers.
*
* The base of the system registers is configured through the struct
* csr_map.
*/
int m10bmc_sys_read(struct intel_m10bmc *m10bmc, unsigned int offset, unsigned int *val)
{
const struct m10bmc_csr_map *csr_map = m10bmc->info->csr_map;
int ret;
if (m10bmc_reg_always_available(m10bmc, offset))
return m10bmc_raw_read(m10bmc, csr_map->base + offset, val);
down_read(&m10bmc->bmcfw_lock);
if (m10bmc_handshake_reg_unavailable(m10bmc))
ret = -EBUSY; /* Reg not available during secure update */
else
ret = m10bmc_raw_read(m10bmc, csr_map->base + offset, val);
up_read(&m10bmc->bmcfw_lock);
return ret;
}
EXPORT_SYMBOL_NS_GPL(m10bmc_sys_read, INTEL_M10_BMC_CORE);
int m10bmc_sys_update_bits(struct intel_m10bmc *m10bmc, unsigned int offset,
unsigned int msk, unsigned int val)
{
const struct m10bmc_csr_map *csr_map = m10bmc->info->csr_map;
int ret;
if (m10bmc_reg_always_available(m10bmc, offset))
return regmap_update_bits(m10bmc->regmap, csr_map->base + offset, msk, val);
down_read(&m10bmc->bmcfw_lock);
if (m10bmc_handshake_reg_unavailable(m10bmc))
ret = -EBUSY; /* Reg not available during secure update */
else
ret = regmap_update_bits(m10bmc->regmap, csr_map->base + offset, msk, val);
up_read(&m10bmc->bmcfw_lock);
return ret;
}
EXPORT_SYMBOL_NS_GPL(m10bmc_sys_update_bits, INTEL_M10_BMC_CORE);
static ssize_t bmc_version_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct intel_m10bmc *ddata = dev_get_drvdata(dev);
unsigned int val;
int ret;
ret = m10bmc_sys_read(ddata, ddata->info->csr_map->build_version, &val);
if (ret)
return ret;
return sprintf(buf, "0x%x\n", val);
}
static DEVICE_ATTR_RO(bmc_version);
static ssize_t bmcfw_version_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct intel_m10bmc *ddata = dev_get_drvdata(dev);
unsigned int val;
int ret;
ret = m10bmc_sys_read(ddata, ddata->info->csr_map->fw_version, &val);
if (ret)
return ret;
return sprintf(buf, "0x%x\n", val);
}
static DEVICE_ATTR_RO(bmcfw_version);
static ssize_t mac_address_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct intel_m10bmc *ddata = dev_get_drvdata(dev);
unsigned int macaddr_low, macaddr_high;
int ret;
ret = m10bmc_sys_read(ddata, ddata->info->csr_map->mac_low, &macaddr_low);
if (ret)
return ret;
ret = m10bmc_sys_read(ddata, ddata->info->csr_map->mac_high, &macaddr_high);
if (ret)
return ret;
return sysfs_emit(buf, "%02x:%02x:%02x:%02x:%02x:%02x\n",
(u8)FIELD_GET(M10BMC_N3000_MAC_BYTE1, macaddr_low),
(u8)FIELD_GET(M10BMC_N3000_MAC_BYTE2, macaddr_low),
(u8)FIELD_GET(M10BMC_N3000_MAC_BYTE3, macaddr_low),
(u8)FIELD_GET(M10BMC_N3000_MAC_BYTE4, macaddr_low),
(u8)FIELD_GET(M10BMC_N3000_MAC_BYTE5, macaddr_high),
(u8)FIELD_GET(M10BMC_N3000_MAC_BYTE6, macaddr_high));
}
static DEVICE_ATTR_RO(mac_address);
static ssize_t mac_count_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct intel_m10bmc *ddata = dev_get_drvdata(dev);
unsigned int macaddr_high;
int ret;
ret = m10bmc_sys_read(ddata, ddata->info->csr_map->mac_high, &macaddr_high);
if (ret)
return ret;
return sysfs_emit(buf, "%u\n", (u8)FIELD_GET(M10BMC_N3000_MAC_COUNT, macaddr_high));
}
static DEVICE_ATTR_RO(mac_count);
static struct attribute *m10bmc_attrs[] = {
&dev_attr_bmc_version.attr,
&dev_attr_bmcfw_version.attr,
&dev_attr_mac_address.attr,
&dev_attr_mac_count.attr,
NULL,
};
static const struct attribute_group m10bmc_group = {
.attrs = m10bmc_attrs,
};
const struct attribute_group *m10bmc_dev_groups[] = {
&m10bmc_group,
NULL,
};
EXPORT_SYMBOL_NS_GPL(m10bmc_dev_groups, INTEL_M10_BMC_CORE);
int m10bmc_dev_init(struct intel_m10bmc *m10bmc, const struct intel_m10bmc_platform_info *info)
{
int ret;
m10bmc->info = info;
dev_set_drvdata(m10bmc->dev, m10bmc);
init_rwsem(&m10bmc->bmcfw_lock);
ret = devm_mfd_add_devices(m10bmc->dev, PLATFORM_DEVID_AUTO,
info->cells, info->n_cells,
NULL, 0, NULL);
if (ret)
dev_err(m10bmc->dev, "Failed to register sub-devices: %d\n", ret);
return ret;
}
EXPORT_SYMBOL_NS_GPL(m10bmc_dev_init, INTEL_M10_BMC_CORE);
MODULE_DESCRIPTION("Intel MAX 10 BMC core driver");
MODULE_AUTHOR("Intel Corporation");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/intel-m10-bmc-core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm831x-otp.c -- OTP for Wolfson WM831x PMICs
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/bcd.h>
#include <linux/delay.h>
#include <linux/mfd/core.h>
#include <linux/random.h>
#include <linux/mfd/wm831x/core.h>
#include <linux/mfd/wm831x/otp.h>
/* In bytes */
#define WM831X_UNIQUE_ID_LEN 16
/* Read the unique ID from the chip into id */
static int wm831x_unique_id_read(struct wm831x *wm831x, char *id)
{
int i, val;
for (i = 0; i < WM831X_UNIQUE_ID_LEN / 2; i++) {
val = wm831x_reg_read(wm831x, WM831X_UNIQUE_ID_1 + i);
if (val < 0)
return val;
id[i * 2] = (val >> 8) & 0xff;
id[(i * 2) + 1] = val & 0xff;
}
return 0;
}
static ssize_t unique_id_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct wm831x *wm831x = dev_get_drvdata(dev);
int rval;
char id[WM831X_UNIQUE_ID_LEN];
rval = wm831x_unique_id_read(wm831x, id);
if (rval < 0)
return 0;
return sprintf(buf, "%*phN\n", WM831X_UNIQUE_ID_LEN, id);
}
static DEVICE_ATTR_RO(unique_id);
int wm831x_otp_init(struct wm831x *wm831x)
{
char uuid[WM831X_UNIQUE_ID_LEN];
int ret;
ret = device_create_file(wm831x->dev, &dev_attr_unique_id);
if (ret != 0)
dev_err(wm831x->dev, "Unique ID attribute not created: %d\n",
ret);
ret = wm831x_unique_id_read(wm831x, uuid);
if (ret == 0)
add_device_randomness(uuid, sizeof(uuid));
else
dev_err(wm831x->dev, "Failed to read UUID: %d\n", ret);
return ret;
}
void wm831x_otp_exit(struct wm831x *wm831x)
{
device_remove_file(wm831x->dev, &dev_attr_unique_id);
}
| linux-master | drivers/mfd/wm831x-otp.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Device access for Dollar Cove TI PMIC
*
* Copyright (c) 2014, Intel Corporation.
* Author: Ramakrishna Pallala <[email protected]>
*
* Cleanup and forward-ported
* Copyright (c) 2017 Takashi Iwai <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/module.h>
#include <linux/regmap.h>
#define CHTDC_TI_IRQLVL1 0x01
#define CHTDC_TI_MASK_IRQLVL1 0x02
/* Level 1 IRQs */
enum {
CHTDC_TI_PWRBTN = 0, /* power button */
CHTDC_TI_DIETMPWARN, /* thermal */
CHTDC_TI_ADCCMPL, /* ADC */
/* No IRQ 3 */
CHTDC_TI_VBATLOW = 4, /* battery */
CHTDC_TI_VBUSDET, /* power source */
/* No IRQ 6 */
CHTDC_TI_CCEOCAL = 7, /* battery */
};
static const struct resource power_button_resources[] = {
DEFINE_RES_IRQ(CHTDC_TI_PWRBTN),
};
static const struct resource thermal_resources[] = {
DEFINE_RES_IRQ(CHTDC_TI_DIETMPWARN),
};
static const struct resource adc_resources[] = {
DEFINE_RES_IRQ(CHTDC_TI_ADCCMPL),
};
static const struct resource pwrsrc_resources[] = {
DEFINE_RES_IRQ(CHTDC_TI_VBUSDET),
};
static const struct resource battery_resources[] = {
DEFINE_RES_IRQ(CHTDC_TI_VBATLOW),
DEFINE_RES_IRQ(CHTDC_TI_CCEOCAL),
};
static struct mfd_cell chtdc_ti_dev[] = {
{
.name = "chtdc_ti_pwrbtn",
.num_resources = ARRAY_SIZE(power_button_resources),
.resources = power_button_resources,
}, {
.name = "chtdc_ti_adc",
.num_resources = ARRAY_SIZE(adc_resources),
.resources = adc_resources,
}, {
.name = "chtdc_ti_thermal",
.num_resources = ARRAY_SIZE(thermal_resources),
.resources = thermal_resources,
}, {
.name = "chtdc_ti_pwrsrc",
.num_resources = ARRAY_SIZE(pwrsrc_resources),
.resources = pwrsrc_resources,
}, {
.name = "chtdc_ti_battery",
.num_resources = ARRAY_SIZE(battery_resources),
.resources = battery_resources,
},
{ .name = "chtdc_ti_region", },
};
static const struct regmap_config chtdc_ti_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 128,
.cache_type = REGCACHE_NONE,
};
static const struct regmap_irq chtdc_ti_irqs[] = {
REGMAP_IRQ_REG(CHTDC_TI_PWRBTN, 0, BIT(CHTDC_TI_PWRBTN)),
REGMAP_IRQ_REG(CHTDC_TI_DIETMPWARN, 0, BIT(CHTDC_TI_DIETMPWARN)),
REGMAP_IRQ_REG(CHTDC_TI_ADCCMPL, 0, BIT(CHTDC_TI_ADCCMPL)),
REGMAP_IRQ_REG(CHTDC_TI_VBATLOW, 0, BIT(CHTDC_TI_VBATLOW)),
REGMAP_IRQ_REG(CHTDC_TI_VBUSDET, 0, BIT(CHTDC_TI_VBUSDET)),
REGMAP_IRQ_REG(CHTDC_TI_CCEOCAL, 0, BIT(CHTDC_TI_CCEOCAL)),
};
static const struct regmap_irq_chip chtdc_ti_irq_chip = {
.name = KBUILD_MODNAME,
.irqs = chtdc_ti_irqs,
.num_irqs = ARRAY_SIZE(chtdc_ti_irqs),
.num_regs = 1,
.status_base = CHTDC_TI_IRQLVL1,
.mask_base = CHTDC_TI_MASK_IRQLVL1,
.ack_base = CHTDC_TI_IRQLVL1,
};
static int chtdc_ti_probe(struct i2c_client *i2c)
{
struct device *dev = &i2c->dev;
struct intel_soc_pmic *pmic;
int ret;
pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
if (!pmic)
return -ENOMEM;
i2c_set_clientdata(i2c, pmic);
pmic->regmap = devm_regmap_init_i2c(i2c, &chtdc_ti_regmap_config);
if (IS_ERR(pmic->regmap))
return PTR_ERR(pmic->regmap);
pmic->irq = i2c->irq;
ret = devm_regmap_add_irq_chip(dev, pmic->regmap, pmic->irq,
IRQF_ONESHOT, 0,
&chtdc_ti_irq_chip,
&pmic->irq_chip_data);
if (ret)
return ret;
return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, chtdc_ti_dev,
ARRAY_SIZE(chtdc_ti_dev), NULL, 0,
regmap_irq_get_domain(pmic->irq_chip_data));
}
static void chtdc_ti_shutdown(struct i2c_client *i2c)
{
struct intel_soc_pmic *pmic = i2c_get_clientdata(i2c);
disable_irq(pmic->irq);
}
static int chtdc_ti_suspend(struct device *dev)
{
struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
disable_irq(pmic->irq);
return 0;
}
static int chtdc_ti_resume(struct device *dev)
{
struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
enable_irq(pmic->irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(chtdc_ti_pm_ops, chtdc_ti_suspend, chtdc_ti_resume);
static const struct acpi_device_id chtdc_ti_acpi_ids[] = {
{ "INT33F5" },
{ },
};
MODULE_DEVICE_TABLE(acpi, chtdc_ti_acpi_ids);
static struct i2c_driver chtdc_ti_i2c_driver = {
.driver = {
.name = "intel_soc_pmic_chtdc_ti",
.pm = pm_sleep_ptr(&chtdc_ti_pm_ops),
.acpi_match_table = chtdc_ti_acpi_ids,
},
.probe = chtdc_ti_probe,
.shutdown = chtdc_ti_shutdown,
};
module_i2c_driver(chtdc_ti_i2c_driver);
MODULE_DESCRIPTION("I2C driver for Intel SoC Dollar Cove TI PMIC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/intel_soc_pmic_chtdc_ti.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI LMU (Lighting Management Unit) Core Driver
*
* Copyright 2017 Texas Instruments
*
* Author: Milo Kim <[email protected]>
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/ti-lmu.h>
#include <linux/mfd/ti-lmu-register.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/slab.h>
struct ti_lmu_data {
const struct mfd_cell *cells;
int num_cells;
unsigned int max_register;
};
static int ti_lmu_enable_hw(struct ti_lmu *lmu, enum ti_lmu_id id)
{
if (lmu->en_gpio)
gpiod_set_value(lmu->en_gpio, 1);
/* Delay about 1ms after HW enable pin control */
usleep_range(1000, 1500);
/* LM3631 has additional power up sequence - enable LCD_EN bit. */
if (id == LM3631) {
return regmap_update_bits(lmu->regmap, LM3631_REG_DEVCTRL,
LM3631_LCD_EN_MASK,
LM3631_LCD_EN_MASK);
}
return 0;
}
static void ti_lmu_disable_hw(void *data)
{
struct ti_lmu *lmu = data;
if (lmu->en_gpio)
gpiod_set_value(lmu->en_gpio, 0);
}
#define LM363X_REGULATOR(_id) \
{ \
.name = "lm363x-regulator", \
.id = _id, \
.of_compatible = "ti,lm363x-regulator", \
} \
static const struct mfd_cell lm3631_devices[] = {
LM363X_REGULATOR(LM3631_BOOST),
LM363X_REGULATOR(LM3631_LDO_CONT),
LM363X_REGULATOR(LM3631_LDO_OREF),
LM363X_REGULATOR(LM3631_LDO_POS),
LM363X_REGULATOR(LM3631_LDO_NEG),
{
.name = "ti-lmu-backlight",
.id = LM3631,
.of_compatible = "ti,lm3631-backlight",
},
};
static const struct mfd_cell lm3632_devices[] = {
LM363X_REGULATOR(LM3632_BOOST),
LM363X_REGULATOR(LM3632_LDO_POS),
LM363X_REGULATOR(LM3632_LDO_NEG),
{
.name = "ti-lmu-backlight",
.id = LM3632,
.of_compatible = "ti,lm3632-backlight",
},
};
static const struct mfd_cell lm3633_devices[] = {
{
.name = "ti-lmu-backlight",
.id = LM3633,
.of_compatible = "ti,lm3633-backlight",
},
{
.name = "lm3633-leds",
.of_compatible = "ti,lm3633-leds",
},
/* Monitoring driver for open/short circuit detection */
{
.name = "ti-lmu-fault-monitor",
.id = LM3633,
.of_compatible = "ti,lm3633-fault-monitor",
},
};
static const struct mfd_cell lm3695_devices[] = {
{
.name = "ti-lmu-backlight",
.id = LM3695,
.of_compatible = "ti,lm3695-backlight",
},
};
static const struct mfd_cell lm36274_devices[] = {
LM363X_REGULATOR(LM36274_BOOST),
LM363X_REGULATOR(LM36274_LDO_POS),
LM363X_REGULATOR(LM36274_LDO_NEG),
{
.name = "lm36274-leds",
.id = LM36274,
.of_compatible = "ti,lm36274-backlight",
},
};
#define TI_LMU_DATA(chip, max_reg) \
static const struct ti_lmu_data chip##_data = \
{ \
.cells = chip##_devices, \
.num_cells = ARRAY_SIZE(chip##_devices),\
.max_register = max_reg, \
} \
TI_LMU_DATA(lm3631, LM3631_MAX_REG);
TI_LMU_DATA(lm3632, LM3632_MAX_REG);
TI_LMU_DATA(lm3633, LM3633_MAX_REG);
TI_LMU_DATA(lm3695, LM3695_MAX_REG);
TI_LMU_DATA(lm36274, LM36274_MAX_REG);
static int ti_lmu_probe(struct i2c_client *cl)
{
const struct i2c_device_id *id = i2c_client_get_device_id(cl);
struct device *dev = &cl->dev;
const struct ti_lmu_data *data;
struct regmap_config regmap_cfg;
struct ti_lmu *lmu;
int ret;
/*
* Get device specific data from of_match table.
* This data is defined by using TI_LMU_DATA() macro.
*/
data = of_device_get_match_data(dev);
if (!data)
return -ENODEV;
lmu = devm_kzalloc(dev, sizeof(*lmu), GFP_KERNEL);
if (!lmu)
return -ENOMEM;
lmu->dev = &cl->dev;
/* Setup regmap */
memset(®map_cfg, 0, sizeof(struct regmap_config));
regmap_cfg.reg_bits = 8;
regmap_cfg.val_bits = 8;
regmap_cfg.name = id->name;
regmap_cfg.max_register = data->max_register;
lmu->regmap = devm_regmap_init_i2c(cl, ®map_cfg);
if (IS_ERR(lmu->regmap))
return PTR_ERR(lmu->regmap);
/* HW enable pin control and additional power up sequence if required */
lmu->en_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIGH);
if (IS_ERR(lmu->en_gpio)) {
ret = PTR_ERR(lmu->en_gpio);
dev_err(dev, "Can not request enable GPIO: %d\n", ret);
return ret;
}
ret = ti_lmu_enable_hw(lmu, id->driver_data);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, ti_lmu_disable_hw, lmu);
if (ret)
return ret;
/*
* Fault circuit(open/short) can be detected by ti-lmu-fault-monitor.
* After fault detection is done, some devices should re-initialize
* configuration. The notifier enables such kind of handling.
*/
BLOCKING_INIT_NOTIFIER_HEAD(&lmu->notifier);
i2c_set_clientdata(cl, lmu);
return devm_mfd_add_devices(lmu->dev, 0, data->cells,
data->num_cells, NULL, 0, NULL);
}
static const struct of_device_id ti_lmu_of_match[] = {
{ .compatible = "ti,lm3631", .data = &lm3631_data },
{ .compatible = "ti,lm3632", .data = &lm3632_data },
{ .compatible = "ti,lm3633", .data = &lm3633_data },
{ .compatible = "ti,lm3695", .data = &lm3695_data },
{ .compatible = "ti,lm36274", .data = &lm36274_data },
{ }
};
MODULE_DEVICE_TABLE(of, ti_lmu_of_match);
static const struct i2c_device_id ti_lmu_ids[] = {
{ "lm3631", LM3631 },
{ "lm3632", LM3632 },
{ "lm3633", LM3633 },
{ "lm3695", LM3695 },
{ "lm36274", LM36274 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ti_lmu_ids);
static struct i2c_driver ti_lmu_driver = {
.probe = ti_lmu_probe,
.driver = {
.name = "ti-lmu",
.of_match_table = ti_lmu_of_match,
},
.id_table = ti_lmu_ids,
};
module_i2c_driver(ti_lmu_driver);
MODULE_DESCRIPTION("TI LMU MFD Core Driver");
MODULE_AUTHOR("Milo Kim");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/ti-lmu.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* RSB driver for the X-Powers' Power Management ICs
*
* AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
* converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
* as well as configurable GPIOs.
*
* This driver supports the RSB variants.
*
* Copyright (C) 2015 Chen-Yu Tsai
*
* Author: Chen-Yu Tsai <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/err.h>
#include <linux/mfd/axp20x.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/sunxi-rsb.h>
static int axp20x_rsb_probe(struct sunxi_rsb_device *rdev)
{
struct axp20x_dev *axp20x;
int ret;
axp20x = devm_kzalloc(&rdev->dev, sizeof(*axp20x), GFP_KERNEL);
if (!axp20x)
return -ENOMEM;
axp20x->dev = &rdev->dev;
axp20x->irq = rdev->irq;
dev_set_drvdata(&rdev->dev, axp20x);
ret = axp20x_match_device(axp20x);
if (ret)
return ret;
axp20x->regmap = devm_regmap_init_sunxi_rsb(rdev, axp20x->regmap_cfg);
if (IS_ERR(axp20x->regmap)) {
ret = PTR_ERR(axp20x->regmap);
dev_err(&rdev->dev, "regmap init failed: %d\n", ret);
return ret;
}
return axp20x_device_probe(axp20x);
}
static void axp20x_rsb_remove(struct sunxi_rsb_device *rdev)
{
struct axp20x_dev *axp20x = sunxi_rsb_device_get_drvdata(rdev);
axp20x_device_remove(axp20x);
}
static const struct of_device_id axp20x_rsb_of_match[] = {
{ .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
{ .compatible = "x-powers,axp803", .data = (void *)AXP803_ID },
{ .compatible = "x-powers,axp806", .data = (void *)AXP806_ID },
{ .compatible = "x-powers,axp809", .data = (void *)AXP809_ID },
{ .compatible = "x-powers,axp813", .data = (void *)AXP813_ID },
{ },
};
MODULE_DEVICE_TABLE(of, axp20x_rsb_of_match);
static struct sunxi_rsb_driver axp20x_rsb_driver = {
.driver = {
.name = "axp20x-rsb",
.of_match_table = of_match_ptr(axp20x_rsb_of_match),
},
.probe = axp20x_rsb_probe,
.remove = axp20x_rsb_remove,
};
module_sunxi_rsb_driver(axp20x_rsb_driver);
MODULE_DESCRIPTION("PMIC MFD sunXi RSB driver for AXP20X");
MODULE_AUTHOR("Chen-Yu Tsai <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/axp20x-rsb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* drivers/mfd/si476x-prop.c -- Subroutines to access
* properties of si476x chips
*
* Copyright (C) 2012 Innovative Converged Devices(ICD)
* Copyright (C) 2013 Andrey Smirnov
*
* Author: Andrey Smirnov <[email protected]>
*/
#include <linux/module.h>
#include <linux/mfd/si476x-core.h>
struct si476x_property_range {
u16 low, high;
};
static bool si476x_core_element_is_in_array(u16 element,
const u16 array[],
size_t size)
{
int i;
for (i = 0; i < size; i++)
if (element == array[i])
return true;
return false;
}
static bool si476x_core_element_is_in_range(u16 element,
const struct si476x_property_range range[],
size_t size)
{
int i;
for (i = 0; i < size; i++)
if (element <= range[i].high && element >= range[i].low)
return true;
return false;
}
static bool si476x_core_is_valid_property_a10(struct si476x_core *core,
u16 property)
{
static const u16 valid_properties[] = {
0x0000,
0x0500, 0x0501,
0x0600,
0x0709, 0x070C, 0x070D, 0x70E, 0x710,
0x0718,
0x1207, 0x1208,
0x2007,
0x2300,
};
static const struct si476x_property_range valid_ranges[] = {
{ 0x0200, 0x0203 },
{ 0x0300, 0x0303 },
{ 0x0400, 0x0404 },
{ 0x0700, 0x0707 },
{ 0x1100, 0x1102 },
{ 0x1200, 0x1204 },
{ 0x1300, 0x1306 },
{ 0x2000, 0x2005 },
{ 0x2100, 0x2104 },
{ 0x2106, 0x2106 },
{ 0x2200, 0x220E },
{ 0x3100, 0x3104 },
{ 0x3207, 0x320F },
{ 0x3300, 0x3304 },
{ 0x3500, 0x3517 },
{ 0x3600, 0x3617 },
{ 0x3700, 0x3717 },
{ 0x4000, 0x4003 },
};
return si476x_core_element_is_in_range(property, valid_ranges,
ARRAY_SIZE(valid_ranges)) ||
si476x_core_element_is_in_array(property, valid_properties,
ARRAY_SIZE(valid_properties));
}
static bool si476x_core_is_valid_property_a20(struct si476x_core *core,
u16 property)
{
static const u16 valid_properties[] = {
0x071B,
0x1006,
0x2210,
0x3401,
};
static const struct si476x_property_range valid_ranges[] = {
{ 0x2215, 0x2219 },
};
return si476x_core_is_valid_property_a10(core, property) ||
si476x_core_element_is_in_range(property, valid_ranges,
ARRAY_SIZE(valid_ranges)) ||
si476x_core_element_is_in_array(property, valid_properties,
ARRAY_SIZE(valid_properties));
}
static bool si476x_core_is_valid_property_a30(struct si476x_core *core,
u16 property)
{
static const u16 valid_properties[] = {
0x071C, 0x071D,
0x1007, 0x1008,
0x220F, 0x2214,
0x2301,
0x3105, 0x3106,
0x3402,
};
static const struct si476x_property_range valid_ranges[] = {
{ 0x0405, 0x0411 },
{ 0x2008, 0x200B },
{ 0x2220, 0x2223 },
{ 0x3100, 0x3106 },
};
return si476x_core_is_valid_property_a20(core, property) ||
si476x_core_element_is_in_range(property, valid_ranges,
ARRAY_SIZE(valid_ranges)) ||
si476x_core_element_is_in_array(property, valid_properties,
ARRAY_SIZE(valid_properties));
}
typedef bool (*valid_property_pred_t) (struct si476x_core *, u16);
static bool si476x_core_is_valid_property(struct si476x_core *core,
u16 property)
{
static const valid_property_pred_t is_valid_property[] = {
[SI476X_REVISION_A10] = si476x_core_is_valid_property_a10,
[SI476X_REVISION_A20] = si476x_core_is_valid_property_a20,
[SI476X_REVISION_A30] = si476x_core_is_valid_property_a30,
};
BUG_ON(core->revision > SI476X_REVISION_A30 ||
core->revision == -1);
return is_valid_property[core->revision](core, property);
}
static bool si476x_core_is_readonly_property(struct si476x_core *core,
u16 property)
{
BUG_ON(core->revision > SI476X_REVISION_A30 ||
core->revision == -1);
switch (core->revision) {
case SI476X_REVISION_A10:
return (property == 0x3200);
case SI476X_REVISION_A20:
return (property == 0x1006 ||
property == 0x2210 ||
property == 0x3200);
case SI476X_REVISION_A30:
return false;
}
return false;
}
static bool si476x_core_regmap_readable_register(struct device *dev,
unsigned int reg)
{
struct i2c_client *client = to_i2c_client(dev);
struct si476x_core *core = i2c_get_clientdata(client);
return si476x_core_is_valid_property(core, (u16) reg);
}
static bool si476x_core_regmap_writable_register(struct device *dev,
unsigned int reg)
{
struct i2c_client *client = to_i2c_client(dev);
struct si476x_core *core = i2c_get_clientdata(client);
return si476x_core_is_valid_property(core, (u16) reg) &&
!si476x_core_is_readonly_property(core, (u16) reg);
}
static int si476x_core_regmap_write(void *context, unsigned int reg,
unsigned int val)
{
return si476x_core_cmd_set_property(context, reg, val);
}
static int si476x_core_regmap_read(void *context, unsigned int reg,
unsigned *val)
{
struct si476x_core *core = context;
int err;
err = si476x_core_cmd_get_property(core, reg);
if (err < 0)
return err;
*val = err;
return 0;
}
static const struct regmap_config si476x_regmap_config = {
.reg_bits = 16,
.val_bits = 16,
.max_register = 0x4003,
.writeable_reg = si476x_core_regmap_writable_register,
.readable_reg = si476x_core_regmap_readable_register,
.reg_read = si476x_core_regmap_read,
.reg_write = si476x_core_regmap_write,
.cache_type = REGCACHE_RBTREE,
};
struct regmap *devm_regmap_init_si476x(struct si476x_core *core)
{
return devm_regmap_init(&core->client->dev, NULL,
core, &si476x_regmap_config);
}
EXPORT_SYMBOL_GPL(devm_regmap_init_si476x);
| linux-master | drivers/mfd/si476x-prop.c |
// SPDX-License-Identifier: GPL-2.0+
/* I2C support for Dialog DA9063
*
* Copyright 2012 Dialog Semiconductor Ltd.
* Copyright 2013 Philipp Zabel, Pengutronix
*
* Author: Krystian Garbaciak, Dialog Semiconductor
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/mfd/core.h>
#include <linux/mfd/da9063/core.h>
#include <linux/mfd/da9063/registers.h>
#include <linux/of.h>
#include <linux/regulator/of_regulator.h>
/*
* Raw I2C access required for just accessing chip and variant info before we
* know which device is present. The info read from the device using this
* approach is then used to select the correct regmap tables.
*/
#define DA9063_REG_PAGE_SIZE 0x100
#define DA9063_REG_PAGED_ADDR_MASK 0xFF
enum da9063_page_sel_buf_fmt {
DA9063_PAGE_SEL_BUF_PAGE_REG = 0,
DA9063_PAGE_SEL_BUF_PAGE_VAL,
DA9063_PAGE_SEL_BUF_SIZE,
};
enum da9063_paged_read_msgs {
DA9063_PAGED_READ_MSG_PAGE_SEL = 0,
DA9063_PAGED_READ_MSG_REG_SEL,
DA9063_PAGED_READ_MSG_DATA,
DA9063_PAGED_READ_MSG_CNT,
};
static int da9063_i2c_blockreg_read(struct i2c_client *client, u16 addr,
u8 *buf, int count)
{
struct i2c_msg xfer[DA9063_PAGED_READ_MSG_CNT];
u8 page_sel_buf[DA9063_PAGE_SEL_BUF_SIZE];
u8 page_num, paged_addr;
int ret;
/* Determine page info based on register address */
page_num = (addr / DA9063_REG_PAGE_SIZE);
if (page_num > 1) {
dev_err(&client->dev, "Invalid register address provided\n");
return -EINVAL;
}
paged_addr = (addr % DA9063_REG_PAGE_SIZE) & DA9063_REG_PAGED_ADDR_MASK;
page_sel_buf[DA9063_PAGE_SEL_BUF_PAGE_REG] = DA9063_REG_PAGE_CON;
page_sel_buf[DA9063_PAGE_SEL_BUF_PAGE_VAL] =
(page_num << DA9063_I2C_PAGE_SEL_SHIFT) & DA9063_REG_PAGE_MASK;
/* Write reg address, page selection */
xfer[DA9063_PAGED_READ_MSG_PAGE_SEL].addr = client->addr;
xfer[DA9063_PAGED_READ_MSG_PAGE_SEL].flags = 0;
xfer[DA9063_PAGED_READ_MSG_PAGE_SEL].len = DA9063_PAGE_SEL_BUF_SIZE;
xfer[DA9063_PAGED_READ_MSG_PAGE_SEL].buf = page_sel_buf;
/* Select register address */
xfer[DA9063_PAGED_READ_MSG_REG_SEL].addr = client->addr;
xfer[DA9063_PAGED_READ_MSG_REG_SEL].flags = 0;
xfer[DA9063_PAGED_READ_MSG_REG_SEL].len = sizeof(paged_addr);
xfer[DA9063_PAGED_READ_MSG_REG_SEL].buf = &paged_addr;
/* Read data */
xfer[DA9063_PAGED_READ_MSG_DATA].addr = client->addr;
xfer[DA9063_PAGED_READ_MSG_DATA].flags = I2C_M_RD;
xfer[DA9063_PAGED_READ_MSG_DATA].len = count;
xfer[DA9063_PAGED_READ_MSG_DATA].buf = buf;
ret = i2c_transfer(client->adapter, xfer, DA9063_PAGED_READ_MSG_CNT);
if (ret < 0) {
dev_err(&client->dev, "Paged block read failed: %d\n", ret);
return ret;
}
if (ret != DA9063_PAGED_READ_MSG_CNT) {
dev_err(&client->dev, "Paged block read failed to complete\n");
return -EIO;
}
return 0;
}
enum {
DA9063_DEV_ID_REG = 0,
DA9063_VAR_ID_REG,
DA9063_CHIP_ID_REGS,
};
static int da9063_get_device_type(struct i2c_client *i2c, struct da9063 *da9063)
{
u8 buf[DA9063_CHIP_ID_REGS];
int ret;
ret = da9063_i2c_blockreg_read(i2c, DA9063_REG_DEVICE_ID, buf,
DA9063_CHIP_ID_REGS);
if (ret)
return ret;
if (buf[DA9063_DEV_ID_REG] != PMIC_CHIP_ID_DA9063) {
dev_err(da9063->dev,
"Invalid chip device ID: 0x%02x\n",
buf[DA9063_DEV_ID_REG]);
return -ENODEV;
}
dev_info(da9063->dev,
"Device detected (chip-ID: 0x%02X, var-ID: 0x%02X)\n",
buf[DA9063_DEV_ID_REG], buf[DA9063_VAR_ID_REG]);
da9063->variant_code =
(buf[DA9063_VAR_ID_REG] & DA9063_VARIANT_ID_MRC_MASK)
>> DA9063_VARIANT_ID_MRC_SHIFT;
return 0;
}
/*
* Variant specific regmap configs
*/
static const struct regmap_range da9063_ad_readable_ranges[] = {
regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_AD_REG_SECOND_D),
regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
regmap_reg_range(DA9063_REG_T_OFFSET, DA9063_AD_REG_GP_ID_19),
regmap_reg_range(DA9063_REG_DEVICE_ID, DA9063_REG_VARIANT_ID),
};
static const struct regmap_range da9063_ad_writeable_ranges[] = {
regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_PAGE_CON),
regmap_reg_range(DA9063_REG_FAULT_LOG, DA9063_REG_VSYS_MON),
regmap_reg_range(DA9063_REG_COUNT_S, DA9063_AD_REG_ALARM_Y),
regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
regmap_reg_range(DA9063_REG_CONFIG_I, DA9063_AD_REG_MON_REG_4),
regmap_reg_range(DA9063_AD_REG_GP_ID_0, DA9063_AD_REG_GP_ID_19),
};
static const struct regmap_range da9063_ad_volatile_ranges[] = {
regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_EVENT_D),
regmap_reg_range(DA9063_REG_CONTROL_A, DA9063_REG_CONTROL_B),
regmap_reg_range(DA9063_REG_CONTROL_E, DA9063_REG_CONTROL_F),
regmap_reg_range(DA9063_REG_BCORE2_CONT, DA9063_REG_LDO11_CONT),
regmap_reg_range(DA9063_REG_DVC_1, DA9063_REG_ADC_MAN),
regmap_reg_range(DA9063_REG_ADC_RES_L, DA9063_AD_REG_SECOND_D),
regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_SEQ),
regmap_reg_range(DA9063_REG_EN_32K, DA9063_REG_EN_32K),
regmap_reg_range(DA9063_AD_REG_MON_REG_5, DA9063_AD_REG_MON_REG_6),
};
static const struct regmap_access_table da9063_ad_readable_table = {
.yes_ranges = da9063_ad_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(da9063_ad_readable_ranges),
};
static const struct regmap_access_table da9063_ad_writeable_table = {
.yes_ranges = da9063_ad_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(da9063_ad_writeable_ranges),
};
static const struct regmap_access_table da9063_ad_volatile_table = {
.yes_ranges = da9063_ad_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(da9063_ad_volatile_ranges),
};
static const struct regmap_range da9063_bb_readable_ranges[] = {
regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_BB_REG_SECOND_D),
regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
regmap_reg_range(DA9063_REG_T_OFFSET, DA9063_BB_REG_GP_ID_19),
regmap_reg_range(DA9063_REG_DEVICE_ID, DA9063_REG_VARIANT_ID),
};
static const struct regmap_range da9063_bb_writeable_ranges[] = {
regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_PAGE_CON),
regmap_reg_range(DA9063_REG_FAULT_LOG, DA9063_REG_VSYS_MON),
regmap_reg_range(DA9063_REG_COUNT_S, DA9063_BB_REG_ALARM_Y),
regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
regmap_reg_range(DA9063_REG_CONFIG_I, DA9063_BB_REG_MON_REG_4),
regmap_reg_range(DA9063_BB_REG_GP_ID_0, DA9063_BB_REG_GP_ID_19),
};
static const struct regmap_range da9063_bb_da_volatile_ranges[] = {
regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_EVENT_D),
regmap_reg_range(DA9063_REG_CONTROL_A, DA9063_REG_CONTROL_B),
regmap_reg_range(DA9063_REG_CONTROL_E, DA9063_REG_CONTROL_F),
regmap_reg_range(DA9063_REG_BCORE2_CONT, DA9063_REG_LDO11_CONT),
regmap_reg_range(DA9063_REG_DVC_1, DA9063_REG_ADC_MAN),
regmap_reg_range(DA9063_REG_ADC_RES_L, DA9063_BB_REG_SECOND_D),
regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_SEQ),
regmap_reg_range(DA9063_REG_EN_32K, DA9063_REG_EN_32K),
regmap_reg_range(DA9063_BB_REG_MON_REG_5, DA9063_BB_REG_MON_REG_6),
};
static const struct regmap_access_table da9063_bb_readable_table = {
.yes_ranges = da9063_bb_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(da9063_bb_readable_ranges),
};
static const struct regmap_access_table da9063_bb_writeable_table = {
.yes_ranges = da9063_bb_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(da9063_bb_writeable_ranges),
};
static const struct regmap_access_table da9063_bb_da_volatile_table = {
.yes_ranges = da9063_bb_da_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(da9063_bb_da_volatile_ranges),
};
static const struct regmap_range da9063l_bb_readable_ranges[] = {
regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_MON_A10_RES),
regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
regmap_reg_range(DA9063_REG_T_OFFSET, DA9063_BB_REG_GP_ID_19),
regmap_reg_range(DA9063_REG_DEVICE_ID, DA9063_REG_VARIANT_ID),
};
static const struct regmap_range da9063l_bb_writeable_ranges[] = {
regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_PAGE_CON),
regmap_reg_range(DA9063_REG_FAULT_LOG, DA9063_REG_VSYS_MON),
regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
regmap_reg_range(DA9063_REG_CONFIG_I, DA9063_BB_REG_MON_REG_4),
regmap_reg_range(DA9063_BB_REG_GP_ID_0, DA9063_BB_REG_GP_ID_19),
};
static const struct regmap_range da9063l_bb_da_volatile_ranges[] = {
regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_EVENT_D),
regmap_reg_range(DA9063_REG_CONTROL_A, DA9063_REG_CONTROL_B),
regmap_reg_range(DA9063_REG_CONTROL_E, DA9063_REG_CONTROL_F),
regmap_reg_range(DA9063_REG_BCORE2_CONT, DA9063_REG_LDO11_CONT),
regmap_reg_range(DA9063_REG_DVC_1, DA9063_REG_ADC_MAN),
regmap_reg_range(DA9063_REG_ADC_RES_L, DA9063_REG_MON_A10_RES),
regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_SEQ),
regmap_reg_range(DA9063_REG_EN_32K, DA9063_REG_EN_32K),
regmap_reg_range(DA9063_BB_REG_MON_REG_5, DA9063_BB_REG_MON_REG_6),
};
static const struct regmap_access_table da9063l_bb_readable_table = {
.yes_ranges = da9063l_bb_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(da9063l_bb_readable_ranges),
};
static const struct regmap_access_table da9063l_bb_writeable_table = {
.yes_ranges = da9063l_bb_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(da9063l_bb_writeable_ranges),
};
static const struct regmap_access_table da9063l_bb_da_volatile_table = {
.yes_ranges = da9063l_bb_da_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(da9063l_bb_da_volatile_ranges),
};
static const struct regmap_range da9063_da_readable_ranges[] = {
regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_BB_REG_SECOND_D),
regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
regmap_reg_range(DA9063_REG_T_OFFSET, DA9063_BB_REG_GP_ID_11),
regmap_reg_range(DA9063_REG_DEVICE_ID, DA9063_REG_VARIANT_ID),
};
static const struct regmap_range da9063_da_writeable_ranges[] = {
regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_PAGE_CON),
regmap_reg_range(DA9063_REG_FAULT_LOG, DA9063_REG_VSYS_MON),
regmap_reg_range(DA9063_REG_COUNT_S, DA9063_BB_REG_ALARM_Y),
regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
regmap_reg_range(DA9063_REG_CONFIG_I, DA9063_BB_REG_MON_REG_4),
regmap_reg_range(DA9063_BB_REG_GP_ID_0, DA9063_BB_REG_GP_ID_11),
};
static const struct regmap_access_table da9063_da_readable_table = {
.yes_ranges = da9063_da_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(da9063_da_readable_ranges),
};
static const struct regmap_access_table da9063_da_writeable_table = {
.yes_ranges = da9063_da_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(da9063_da_writeable_ranges),
};
static const struct regmap_range da9063l_da_readable_ranges[] = {
regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_MON_A10_RES),
regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
regmap_reg_range(DA9063_REG_T_OFFSET, DA9063_BB_REG_GP_ID_11),
regmap_reg_range(DA9063_REG_DEVICE_ID, DA9063_REG_VARIANT_ID),
};
static const struct regmap_range da9063l_da_writeable_ranges[] = {
regmap_reg_range(DA9063_REG_PAGE_CON, DA9063_REG_PAGE_CON),
regmap_reg_range(DA9063_REG_FAULT_LOG, DA9063_REG_VSYS_MON),
regmap_reg_range(DA9063_REG_SEQ, DA9063_REG_ID_32_31),
regmap_reg_range(DA9063_REG_SEQ_A, DA9063_REG_AUTO3_LOW),
regmap_reg_range(DA9063_REG_CONFIG_I, DA9063_BB_REG_MON_REG_4),
regmap_reg_range(DA9063_BB_REG_GP_ID_0, DA9063_BB_REG_GP_ID_11),
};
static const struct regmap_access_table da9063l_da_readable_table = {
.yes_ranges = da9063l_da_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(da9063l_da_readable_ranges),
};
static const struct regmap_access_table da9063l_da_writeable_table = {
.yes_ranges = da9063l_da_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(da9063l_da_writeable_ranges),
};
static const struct regmap_range_cfg da9063_range_cfg[] = {
{
.range_min = DA9063_REG_PAGE_CON,
.range_max = DA9063_REG_CONFIG_ID,
.selector_reg = DA9063_REG_PAGE_CON,
.selector_mask = 1 << DA9063_I2C_PAGE_SEL_SHIFT,
.selector_shift = DA9063_I2C_PAGE_SEL_SHIFT,
.window_start = 0,
.window_len = 256,
}
};
static struct regmap_config da9063_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.ranges = da9063_range_cfg,
.num_ranges = ARRAY_SIZE(da9063_range_cfg),
.max_register = DA9063_REG_CONFIG_ID,
.cache_type = REGCACHE_RBTREE,
};
static const struct of_device_id da9063_dt_ids[] = {
{ .compatible = "dlg,da9063", },
{ .compatible = "dlg,da9063l", },
{ }
};
MODULE_DEVICE_TABLE(of, da9063_dt_ids);
static int da9063_i2c_probe(struct i2c_client *i2c)
{
const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
struct da9063 *da9063;
int ret;
da9063 = devm_kzalloc(&i2c->dev, sizeof(struct da9063), GFP_KERNEL);
if (da9063 == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, da9063);
da9063->dev = &i2c->dev;
da9063->chip_irq = i2c->irq;
da9063->type = id->driver_data;
ret = da9063_get_device_type(i2c, da9063);
if (ret)
return ret;
switch (da9063->type) {
case PMIC_TYPE_DA9063:
switch (da9063->variant_code) {
case PMIC_DA9063_AD:
da9063_regmap_config.rd_table =
&da9063_ad_readable_table;
da9063_regmap_config.wr_table =
&da9063_ad_writeable_table;
da9063_regmap_config.volatile_table =
&da9063_ad_volatile_table;
break;
case PMIC_DA9063_BB:
case PMIC_DA9063_CA:
da9063_regmap_config.rd_table =
&da9063_bb_readable_table;
da9063_regmap_config.wr_table =
&da9063_bb_writeable_table;
da9063_regmap_config.volatile_table =
&da9063_bb_da_volatile_table;
break;
case PMIC_DA9063_DA:
case PMIC_DA9063_EA:
da9063_regmap_config.rd_table =
&da9063_da_readable_table;
da9063_regmap_config.wr_table =
&da9063_da_writeable_table;
da9063_regmap_config.volatile_table =
&da9063_bb_da_volatile_table;
break;
default:
dev_err(da9063->dev,
"Chip variant not supported for DA9063\n");
return -ENODEV;
}
break;
case PMIC_TYPE_DA9063L:
switch (da9063->variant_code) {
case PMIC_DA9063_BB:
case PMIC_DA9063_CA:
da9063_regmap_config.rd_table =
&da9063l_bb_readable_table;
da9063_regmap_config.wr_table =
&da9063l_bb_writeable_table;
da9063_regmap_config.volatile_table =
&da9063l_bb_da_volatile_table;
break;
case PMIC_DA9063_DA:
case PMIC_DA9063_EA:
da9063_regmap_config.rd_table =
&da9063l_da_readable_table;
da9063_regmap_config.wr_table =
&da9063l_da_writeable_table;
da9063_regmap_config.volatile_table =
&da9063l_bb_da_volatile_table;
break;
default:
dev_err(da9063->dev,
"Chip variant not supported for DA9063L\n");
return -ENODEV;
}
break;
default:
dev_err(da9063->dev, "Chip type not supported\n");
return -ENODEV;
}
da9063->regmap = devm_regmap_init_i2c(i2c, &da9063_regmap_config);
if (IS_ERR(da9063->regmap)) {
ret = PTR_ERR(da9063->regmap);
dev_err(da9063->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
/* If SMBus is not available and only I2C is possible, enter I2C mode */
if (i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C)) {
ret = regmap_clear_bits(da9063->regmap, DA9063_REG_CONFIG_J,
DA9063_TWOWIRE_TO);
if (ret < 0) {
dev_err(da9063->dev, "Failed to set Two-Wire Bus Mode.\n");
return ret;
}
}
return da9063_device_init(da9063, i2c->irq);
}
static const struct i2c_device_id da9063_i2c_id[] = {
{ "da9063", PMIC_TYPE_DA9063 },
{ "da9063l", PMIC_TYPE_DA9063L },
{},
};
MODULE_DEVICE_TABLE(i2c, da9063_i2c_id);
static struct i2c_driver da9063_i2c_driver = {
.driver = {
.name = "da9063",
.of_match_table = da9063_dt_ids,
},
.probe = da9063_i2c_probe,
.id_table = da9063_i2c_id,
};
module_i2c_driver(da9063_i2c_driver);
| linux-master | drivers/mfd/da9063-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Intel Quark MFD PCI driver for I2C & GPIO
*
* Copyright(c) 2014 Intel Corporation.
*
* Intel Quark PCI device for I2C and GPIO controller sharing the same
* PCI function. This PCI driver will split the 2 devices into their
* respective drivers.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/mfd/core.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/dmi.h>
#include <linux/i2c.h>
#include <linux/property.h>
/* PCI BAR for register base address */
#define MFD_I2C_BAR 0
#define MFD_GPIO_BAR 1
/* ACPI _ADR value to match the child node */
#define MFD_ACPI_MATCH_GPIO 0ULL
#define MFD_ACPI_MATCH_I2C 1ULL
#define INTEL_QUARK_IORES_MEM 0
#define INTEL_QUARK_IORES_IRQ 1
#define INTEL_QUARK_I2C_CONTROLLER_CLK "i2c_designware.0"
/* The Quark I2C controller source clock */
#define INTEL_QUARK_I2C_CLK_HZ 33000000
struct intel_quark_mfd {
struct clk *i2c_clk;
struct clk_lookup *i2c_clk_lookup;
};
static const struct property_entry intel_quark_i2c_controller_standard_properties[] = {
PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ),
{ }
};
static const struct software_node intel_quark_i2c_controller_standard_node = {
.name = "intel-quark-i2c-controller",
.properties = intel_quark_i2c_controller_standard_properties,
};
static const struct property_entry intel_quark_i2c_controller_fast_properties[] = {
PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_FAST_MODE_FREQ),
{ }
};
static const struct software_node intel_quark_i2c_controller_fast_node = {
.name = "intel-quark-i2c-controller",
.properties = intel_quark_i2c_controller_fast_properties,
};
static const struct dmi_system_id dmi_platform_info[] = {
{
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
},
.driver_data = (void *)&intel_quark_i2c_controller_standard_node,
},
{
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
},
.driver_data = (void *)&intel_quark_i2c_controller_fast_node,
},
{
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
},
.driver_data = (void *)&intel_quark_i2c_controller_fast_node,
},
{}
};
/* This is used as a place holder and will be modified at run-time */
static struct resource intel_quark_i2c_res[] = {
[INTEL_QUARK_IORES_MEM] = {
.flags = IORESOURCE_MEM,
},
[INTEL_QUARK_IORES_IRQ] = {
.flags = IORESOURCE_IRQ,
},
};
static struct mfd_cell_acpi_match intel_quark_acpi_match_i2c = {
.adr = MFD_ACPI_MATCH_I2C,
};
/* This is used as a place holder and will be modified at run-time */
static struct resource intel_quark_gpio_res[] = {
[INTEL_QUARK_IORES_MEM] = {
.flags = IORESOURCE_MEM,
},
[INTEL_QUARK_IORES_IRQ] = {
.flags = IORESOURCE_IRQ,
},
};
static struct mfd_cell_acpi_match intel_quark_acpi_match_gpio = {
.adr = MFD_ACPI_MATCH_GPIO,
};
static const struct software_node intel_quark_gpio_controller_node = {
.name = "intel-quark-gpio-controller",
};
static const struct property_entry intel_quark_gpio_portA_properties[] = {
PROPERTY_ENTRY_U32("reg", 0),
PROPERTY_ENTRY_U32("snps,nr-gpios", 8),
PROPERTY_ENTRY_U32("gpio-base", 8),
{ }
};
static const struct software_node intel_quark_gpio_portA_node = {
.name = "portA",
.parent = &intel_quark_gpio_controller_node,
.properties = intel_quark_gpio_portA_properties,
};
static const struct software_node *intel_quark_gpio_node_group[] = {
&intel_quark_gpio_controller_node,
&intel_quark_gpio_portA_node,
NULL
};
static struct mfd_cell intel_quark_mfd_cells[] = {
[MFD_I2C_BAR] = {
.id = MFD_I2C_BAR,
.name = "i2c_designware",
.acpi_match = &intel_quark_acpi_match_i2c,
.num_resources = ARRAY_SIZE(intel_quark_i2c_res),
.resources = intel_quark_i2c_res,
.ignore_resource_conflicts = true,
},
[MFD_GPIO_BAR] = {
.id = MFD_GPIO_BAR,
.name = "gpio-dwapb",
.acpi_match = &intel_quark_acpi_match_gpio,
.num_resources = ARRAY_SIZE(intel_quark_gpio_res),
.resources = intel_quark_gpio_res,
.ignore_resource_conflicts = true,
},
};
static const struct pci_device_id intel_quark_mfd_ids[] = {
{ PCI_VDEVICE(INTEL, 0x0934), },
{},
};
MODULE_DEVICE_TABLE(pci, intel_quark_mfd_ids);
static int intel_quark_register_i2c_clk(struct device *dev)
{
struct intel_quark_mfd *quark_mfd = dev_get_drvdata(dev);
struct clk *i2c_clk;
i2c_clk = clk_register_fixed_rate(dev,
INTEL_QUARK_I2C_CONTROLLER_CLK, NULL,
0, INTEL_QUARK_I2C_CLK_HZ);
if (IS_ERR(i2c_clk))
return PTR_ERR(i2c_clk);
quark_mfd->i2c_clk = i2c_clk;
quark_mfd->i2c_clk_lookup = clkdev_create(i2c_clk, NULL,
INTEL_QUARK_I2C_CONTROLLER_CLK);
if (!quark_mfd->i2c_clk_lookup) {
clk_unregister(quark_mfd->i2c_clk);
dev_err(dev, "Fixed clk register failed\n");
return -ENOMEM;
}
return 0;
}
static void intel_quark_unregister_i2c_clk(struct device *dev)
{
struct intel_quark_mfd *quark_mfd = dev_get_drvdata(dev);
if (!quark_mfd->i2c_clk_lookup)
return;
clkdev_drop(quark_mfd->i2c_clk_lookup);
clk_unregister(quark_mfd->i2c_clk);
}
static int intel_quark_i2c_setup(struct pci_dev *pdev)
{
struct mfd_cell *cell = &intel_quark_mfd_cells[MFD_I2C_BAR];
struct resource *res = intel_quark_i2c_res;
const struct dmi_system_id *dmi_id;
res[INTEL_QUARK_IORES_MEM].start = pci_resource_start(pdev, MFD_I2C_BAR);
res[INTEL_QUARK_IORES_MEM].end = pci_resource_end(pdev, MFD_I2C_BAR);
res[INTEL_QUARK_IORES_IRQ].start = pci_irq_vector(pdev, 0);
res[INTEL_QUARK_IORES_IRQ].end = pci_irq_vector(pdev, 0);
/* Normal mode by default */
cell->swnode = &intel_quark_i2c_controller_standard_node;
dmi_id = dmi_first_match(dmi_platform_info);
if (dmi_id)
cell->swnode = (struct software_node *)dmi_id->driver_data;
return 0;
}
static int intel_quark_gpio_setup(struct pci_dev *pdev)
{
struct mfd_cell *cell = &intel_quark_mfd_cells[MFD_GPIO_BAR];
struct resource *res = intel_quark_gpio_res;
int ret;
res[INTEL_QUARK_IORES_MEM].start = pci_resource_start(pdev, MFD_GPIO_BAR);
res[INTEL_QUARK_IORES_MEM].end = pci_resource_end(pdev, MFD_GPIO_BAR);
res[INTEL_QUARK_IORES_IRQ].start = pci_irq_vector(pdev, 0);
res[INTEL_QUARK_IORES_IRQ].end = pci_irq_vector(pdev, 0);
ret = software_node_register_node_group(intel_quark_gpio_node_group);
if (ret)
return ret;
cell->swnode = &intel_quark_gpio_controller_node;
return 0;
}
static int intel_quark_mfd_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct intel_quark_mfd *quark_mfd;
int ret;
ret = pcim_enable_device(pdev);
if (ret)
return ret;
quark_mfd = devm_kzalloc(&pdev->dev, sizeof(*quark_mfd), GFP_KERNEL);
if (!quark_mfd)
return -ENOMEM;
dev_set_drvdata(&pdev->dev, quark_mfd);
ret = intel_quark_register_i2c_clk(&pdev->dev);
if (ret)
return ret;
pci_set_master(pdev);
/* This driver only requires 1 IRQ vector */
ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
if (ret < 0)
goto err_unregister_i2c_clk;
ret = intel_quark_i2c_setup(pdev);
if (ret)
goto err_free_irq_vectors;
ret = intel_quark_gpio_setup(pdev);
if (ret)
goto err_free_irq_vectors;
ret = mfd_add_devices(&pdev->dev, 0, intel_quark_mfd_cells,
ARRAY_SIZE(intel_quark_mfd_cells), NULL, 0,
NULL);
if (ret)
goto err_unregister_gpio_node_group;
return 0;
err_unregister_gpio_node_group:
software_node_unregister_node_group(intel_quark_gpio_node_group);
err_free_irq_vectors:
pci_free_irq_vectors(pdev);
err_unregister_i2c_clk:
intel_quark_unregister_i2c_clk(&pdev->dev);
return ret;
}
static void intel_quark_mfd_remove(struct pci_dev *pdev)
{
mfd_remove_devices(&pdev->dev);
software_node_unregister_node_group(intel_quark_gpio_node_group);
pci_free_irq_vectors(pdev);
intel_quark_unregister_i2c_clk(&pdev->dev);
}
static struct pci_driver intel_quark_mfd_driver = {
.name = "intel_quark_mfd_i2c_gpio",
.id_table = intel_quark_mfd_ids,
.probe = intel_quark_mfd_probe,
.remove = intel_quark_mfd_remove,
};
module_pci_driver(intel_quark_mfd_driver);
MODULE_AUTHOR("Raymond Tan <[email protected]>");
MODULE_DESCRIPTION("Intel Quark MFD PCI driver for I2C & GPIO");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/intel_quark_i2c_gpio.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2009-2010 Pengutronix
* Uwe Kleine-Koenig <[email protected]>
*
* loosely based on an earlier driver that has
* Copyright 2009 Pengutronix, Sascha Hauer <[email protected]>
*/
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mfd/mc13xxx.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/err.h>
#include <linux/spi/spi.h>
#include "mc13xxx.h"
static const struct spi_device_id mc13xxx_device_id[] = {
{
.name = "mc13783",
.driver_data = (kernel_ulong_t)&mc13xxx_variant_mc13783,
}, {
.name = "mc13892",
.driver_data = (kernel_ulong_t)&mc13xxx_variant_mc13892,
}, {
.name = "mc34708",
.driver_data = (kernel_ulong_t)&mc13xxx_variant_mc34708,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(spi, mc13xxx_device_id);
static const struct of_device_id mc13xxx_dt_ids[] = {
{ .compatible = "fsl,mc13783", .data = &mc13xxx_variant_mc13783, },
{ .compatible = "fsl,mc13892", .data = &mc13xxx_variant_mc13892, },
{ .compatible = "fsl,mc34708", .data = &mc13xxx_variant_mc34708, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
static const struct regmap_config mc13xxx_regmap_spi_config = {
.reg_bits = 7,
.pad_bits = 1,
.val_bits = 24,
.write_flag_mask = 0x80,
.max_register = MC13XXX_NUMREGS,
.cache_type = REGCACHE_NONE,
.use_single_read = true,
.use_single_write = true,
};
static int mc13xxx_spi_read(void *context, const void *reg, size_t reg_size,
void *val, size_t val_size)
{
unsigned char w[4] = { *((unsigned char *) reg), 0, 0, 0};
unsigned char r[4];
unsigned char *p = val;
struct device *dev = context;
struct spi_device *spi = to_spi_device(dev);
struct spi_transfer t = {
.tx_buf = w,
.rx_buf = r,
.len = 4,
};
struct spi_message m;
int ret;
if (val_size != 3 || reg_size != 1)
return -ENOTSUPP;
spi_message_init(&m);
spi_message_add_tail(&t, &m);
ret = spi_sync(spi, &m);
memcpy(p, &r[1], 3);
return ret;
}
static int mc13xxx_spi_write(void *context, const void *data, size_t count)
{
struct device *dev = context;
struct spi_device *spi = to_spi_device(dev);
const char *reg = data;
if (count != 4)
return -ENOTSUPP;
/* include errata fix for spi audio problems */
if (*reg == MC13783_AUDIO_CODEC || *reg == MC13783_AUDIO_DAC)
spi_write(spi, data, count);
return spi_write(spi, data, count);
}
/*
* We cannot use regmap-spi generic bus implementation here.
* The MC13783 chip will get corrupted if CS signal is deasserted
* and on i.Mx31 SoC (the target SoC for MC13783 PMIC) the SPI controller
* has the following errata (DSPhl22960):
* "The CSPI negates SS when the FIFO becomes empty with
* SSCTL= 0. Software cannot guarantee that the FIFO will not
* drain because of higher priority interrupts and the
* non-realtime characteristics of the operating system. As a
* result, the SS will negate before all of the data has been
* transferred to/from the peripheral."
* We workaround this by accessing the SPI controller with a
* single transfer.
*/
static struct regmap_bus regmap_mc13xxx_bus = {
.write = mc13xxx_spi_write,
.read = mc13xxx_spi_read,
};
static int mc13xxx_spi_probe(struct spi_device *spi)
{
struct mc13xxx *mc13xxx;
int ret;
mc13xxx = devm_kzalloc(&spi->dev, sizeof(*mc13xxx), GFP_KERNEL);
if (!mc13xxx)
return -ENOMEM;
dev_set_drvdata(&spi->dev, mc13xxx);
spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
mc13xxx->irq = spi->irq;
spi->max_speed_hz = spi->max_speed_hz ? : 26000000;
ret = spi_setup(spi);
if (ret)
return ret;
mc13xxx->regmap = devm_regmap_init(&spi->dev, ®map_mc13xxx_bus,
&spi->dev,
&mc13xxx_regmap_spi_config);
if (IS_ERR(mc13xxx->regmap)) {
ret = PTR_ERR(mc13xxx->regmap);
dev_err(&spi->dev, "Failed to initialize regmap: %d\n", ret);
return ret;
}
if (spi->dev.of_node) {
const struct of_device_id *of_id =
of_match_device(mc13xxx_dt_ids, &spi->dev);
mc13xxx->variant = of_id->data;
} else {
const struct spi_device_id *id_entry = spi_get_device_id(spi);
mc13xxx->variant = (void *)id_entry->driver_data;
}
return mc13xxx_common_init(&spi->dev);
}
static void mc13xxx_spi_remove(struct spi_device *spi)
{
mc13xxx_common_exit(&spi->dev);
}
static struct spi_driver mc13xxx_spi_driver = {
.id_table = mc13xxx_device_id,
.driver = {
.name = "mc13xxx",
.of_match_table = mc13xxx_dt_ids,
},
.probe = mc13xxx_spi_probe,
.remove = mc13xxx_spi_remove,
};
static int __init mc13xxx_init(void)
{
return spi_register_driver(&mc13xxx_spi_driver);
}
subsys_initcall(mc13xxx_init);
static void __exit mc13xxx_exit(void)
{
spi_unregister_driver(&mc13xxx_spi_driver);
}
module_exit(mc13xxx_exit);
MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
MODULE_AUTHOR("Uwe Kleine-Koenig <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/mc13xxx-spi.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Device access for Crystal Cove PMIC
*
* Copyright (C) 2012-2014, 2022 Intel Corporation. All rights reserved.
*
* Author: Yang, Bin <[email protected]>
* Author: Zhu, Lejun <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/platform_data/x86/soc.h>
#include <linux/pwm.h>
#include <linux/regmap.h>
#define CRYSTAL_COVE_MAX_REGISTER 0xC6
#define CRYSTAL_COVE_REG_IRQLVL1 0x02
#define CRYSTAL_COVE_REG_MIRQLVL1 0x0E
#define CRYSTAL_COVE_IRQ_PWRSRC 0
#define CRYSTAL_COVE_IRQ_THRM 1
#define CRYSTAL_COVE_IRQ_BCU 2
#define CRYSTAL_COVE_IRQ_ADC 3
#define CRYSTAL_COVE_IRQ_CHGR 4
#define CRYSTAL_COVE_IRQ_GPIO 5
#define CRYSTAL_COVE_IRQ_VHDMIOCP 6
static const struct resource pwrsrc_resources[] = {
DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_PWRSRC, "PWRSRC"),
};
static const struct resource thermal_resources[] = {
DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_THRM, "THERMAL"),
};
static const struct resource bcu_resources[] = {
DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_BCU, "BCU"),
};
static const struct resource adc_resources[] = {
DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_ADC, "ADC"),
};
static const struct resource charger_resources[] = {
DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_CHGR, "CHGR"),
};
static const struct resource gpio_resources[] = {
DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_GPIO, "GPIO"),
};
static struct mfd_cell crystal_cove_byt_dev[] = {
{
.name = "crystal_cove_pwrsrc",
.num_resources = ARRAY_SIZE(pwrsrc_resources),
.resources = pwrsrc_resources,
},
{
.name = "crystal_cove_thermal",
.num_resources = ARRAY_SIZE(thermal_resources),
.resources = thermal_resources,
},
{
.name = "crystal_cove_bcu",
.num_resources = ARRAY_SIZE(bcu_resources),
.resources = bcu_resources,
},
{
.name = "crystal_cove_adc",
.num_resources = ARRAY_SIZE(adc_resources),
.resources = adc_resources,
},
{
.name = "crystal_cove_charger",
.num_resources = ARRAY_SIZE(charger_resources),
.resources = charger_resources,
},
{
.name = "crystal_cove_gpio",
.num_resources = ARRAY_SIZE(gpio_resources),
.resources = gpio_resources,
},
{
.name = "byt_crystal_cove_pmic",
},
{
.name = "crystal_cove_pwm",
},
};
static struct mfd_cell crystal_cove_cht_dev[] = {
{
.name = "crystal_cove_gpio",
.num_resources = ARRAY_SIZE(gpio_resources),
.resources = gpio_resources,
},
{
.name = "cht_crystal_cove_pmic",
},
{
.name = "crystal_cove_pwm",
},
};
static const struct regmap_config crystal_cove_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = CRYSTAL_COVE_MAX_REGISTER,
.cache_type = REGCACHE_NONE,
};
static const struct regmap_irq crystal_cove_irqs[] = {
REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_PWRSRC, 0, BIT(CRYSTAL_COVE_IRQ_PWRSRC)),
REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_THRM, 0, BIT(CRYSTAL_COVE_IRQ_THRM)),
REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_BCU, 0, BIT(CRYSTAL_COVE_IRQ_BCU)),
REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_ADC, 0, BIT(CRYSTAL_COVE_IRQ_ADC)),
REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_CHGR, 0, BIT(CRYSTAL_COVE_IRQ_CHGR)),
REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_GPIO, 0, BIT(CRYSTAL_COVE_IRQ_GPIO)),
REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_VHDMIOCP, 0, BIT(CRYSTAL_COVE_IRQ_VHDMIOCP)),
};
static const struct regmap_irq_chip crystal_cove_irq_chip = {
.name = "Crystal Cove",
.irqs = crystal_cove_irqs,
.num_irqs = ARRAY_SIZE(crystal_cove_irqs),
.num_regs = 1,
.status_base = CRYSTAL_COVE_REG_IRQLVL1,
.mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
};
/* PWM consumed by the Intel GFX */
static struct pwm_lookup crc_pwm_lookup[] = {
PWM_LOOKUP("crystal_cove_pwm", 0, "0000:00:02.0", "pwm_pmic_backlight", 0, PWM_POLARITY_NORMAL),
};
struct crystal_cove_config {
unsigned long irq_flags;
struct mfd_cell *cell_dev;
int n_cell_devs;
const struct regmap_config *regmap_config;
const struct regmap_irq_chip *irq_chip;
};
static const struct crystal_cove_config crystal_cove_config_byt_crc = {
.irq_flags = IRQF_TRIGGER_RISING,
.cell_dev = crystal_cove_byt_dev,
.n_cell_devs = ARRAY_SIZE(crystal_cove_byt_dev),
.regmap_config = &crystal_cove_regmap_config,
.irq_chip = &crystal_cove_irq_chip,
};
static const struct crystal_cove_config crystal_cove_config_cht_crc = {
.irq_flags = IRQF_TRIGGER_RISING,
.cell_dev = crystal_cove_cht_dev,
.n_cell_devs = ARRAY_SIZE(crystal_cove_cht_dev),
.regmap_config = &crystal_cove_regmap_config,
.irq_chip = &crystal_cove_irq_chip,
};
static int crystal_cove_i2c_probe(struct i2c_client *i2c)
{
const struct crystal_cove_config *config;
struct device *dev = &i2c->dev;
struct intel_soc_pmic *pmic;
int ret;
if (soc_intel_is_byt())
config = &crystal_cove_config_byt_crc;
else
config = &crystal_cove_config_cht_crc;
pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
if (!pmic)
return -ENOMEM;
i2c_set_clientdata(i2c, pmic);
pmic->regmap = devm_regmap_init_i2c(i2c, config->regmap_config);
if (IS_ERR(pmic->regmap))
return PTR_ERR(pmic->regmap);
pmic->irq = i2c->irq;
ret = devm_regmap_add_irq_chip(dev, pmic->regmap, pmic->irq,
config->irq_flags | IRQF_ONESHOT,
0, config->irq_chip, &pmic->irq_chip_data);
if (ret)
return ret;
ret = enable_irq_wake(pmic->irq);
if (ret)
dev_warn(dev, "Can't enable IRQ as wake source: %d\n", ret);
/* Add lookup table for crc-pwm */
pwm_add_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup));
/* To distuingish this domain from the GPIO/charger's irqchip domains */
irq_domain_update_bus_token(regmap_irq_get_domain(pmic->irq_chip_data),
DOMAIN_BUS_NEXUS);
ret = mfd_add_devices(dev, PLATFORM_DEVID_NONE, config->cell_dev,
config->n_cell_devs, NULL, 0,
regmap_irq_get_domain(pmic->irq_chip_data));
if (ret)
pwm_remove_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup));
return ret;
}
static void crystal_cove_i2c_remove(struct i2c_client *i2c)
{
/* remove crc-pwm lookup table */
pwm_remove_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup));
mfd_remove_devices(&i2c->dev);
}
static void crystal_cove_shutdown(struct i2c_client *i2c)
{
struct intel_soc_pmic *pmic = i2c_get_clientdata(i2c);
disable_irq(pmic->irq);
return;
}
static int crystal_cove_suspend(struct device *dev)
{
struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
disable_irq(pmic->irq);
return 0;
}
static int crystal_cove_resume(struct device *dev)
{
struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
enable_irq(pmic->irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(crystal_cove_pm_ops, crystal_cove_suspend, crystal_cove_resume);
static const struct acpi_device_id crystal_cove_acpi_match[] = {
{ "INT33FD" },
{ },
};
MODULE_DEVICE_TABLE(acpi, crystal_cove_acpi_match);
static struct i2c_driver crystal_cove_i2c_driver = {
.driver = {
.name = "crystal_cove_i2c",
.pm = pm_sleep_ptr(&crystal_cove_pm_ops),
.acpi_match_table = crystal_cove_acpi_match,
},
.probe = crystal_cove_i2c_probe,
.remove = crystal_cove_i2c_remove,
.shutdown = crystal_cove_shutdown,
};
module_i2c_driver(crystal_cove_i2c_driver);
MODULE_DESCRIPTION("I2C driver for Intel SoC PMIC");
MODULE_AUTHOR("Yang, Bin <[email protected]>");
MODULE_AUTHOR("Zhu, Lejun <[email protected]>");
| linux-master | drivers/mfd/intel_soc_pmic_crc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* max8907.c - mfd driver for MAX8907
*
* Copyright (C) 2010 Gyungoh Yoo <[email protected]>
* Copyright (C) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/mfd/max8907.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/slab.h>
static const struct mfd_cell max8907_cells[] = {
{ .name = "max8907-regulator", },
{ .name = "max8907-rtc", },
};
static bool max8907_gen_is_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX8907_REG_ON_OFF_IRQ1:
case MAX8907_REG_ON_OFF_STAT:
case MAX8907_REG_ON_OFF_IRQ2:
case MAX8907_REG_CHG_IRQ1:
case MAX8907_REG_CHG_IRQ2:
case MAX8907_REG_CHG_STAT:
return true;
default:
return false;
}
}
static bool max8907_gen_is_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX8907_REG_ON_OFF_IRQ1:
case MAX8907_REG_ON_OFF_IRQ2:
case MAX8907_REG_CHG_IRQ1:
case MAX8907_REG_CHG_IRQ2:
return true;
default:
return false;
}
}
static bool max8907_gen_is_writeable_reg(struct device *dev, unsigned int reg)
{
return !max8907_gen_is_volatile_reg(dev, reg);
}
static const struct regmap_config max8907_regmap_gen_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = max8907_gen_is_volatile_reg,
.precious_reg = max8907_gen_is_precious_reg,
.writeable_reg = max8907_gen_is_writeable_reg,
.max_register = MAX8907_REG_LDO20VOUT,
.cache_type = REGCACHE_RBTREE,
};
static bool max8907_rtc_is_volatile_reg(struct device *dev, unsigned int reg)
{
if (reg <= MAX8907_REG_RTC_YEAR2)
return true;
switch (reg) {
case MAX8907_REG_RTC_STATUS:
case MAX8907_REG_RTC_IRQ:
return true;
default:
return false;
}
}
static bool max8907_rtc_is_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX8907_REG_RTC_IRQ:
return true;
default:
return false;
}
}
static bool max8907_rtc_is_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX8907_REG_RTC_STATUS:
case MAX8907_REG_RTC_IRQ:
return false;
default:
return true;
}
}
static const struct regmap_config max8907_regmap_rtc_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_reg = max8907_rtc_is_volatile_reg,
.precious_reg = max8907_rtc_is_precious_reg,
.writeable_reg = max8907_rtc_is_writeable_reg,
.max_register = MAX8907_REG_MPL_CNTL,
.cache_type = REGCACHE_RBTREE,
};
static const struct regmap_irq max8907_chg_irqs[] = {
{ .reg_offset = 0, .mask = 1 << 0, },
{ .reg_offset = 0, .mask = 1 << 1, },
{ .reg_offset = 0, .mask = 1 << 2, },
{ .reg_offset = 1, .mask = 1 << 0, },
{ .reg_offset = 1, .mask = 1 << 1, },
{ .reg_offset = 1, .mask = 1 << 2, },
{ .reg_offset = 1, .mask = 1 << 3, },
{ .reg_offset = 1, .mask = 1 << 4, },
{ .reg_offset = 1, .mask = 1 << 5, },
{ .reg_offset = 1, .mask = 1 << 6, },
{ .reg_offset = 1, .mask = 1 << 7, },
};
static const struct regmap_irq_chip max8907_chg_irq_chip = {
.name = "max8907 chg",
.status_base = MAX8907_REG_CHG_IRQ1,
.mask_base = MAX8907_REG_CHG_IRQ1_MASK,
.wake_base = MAX8907_REG_CHG_IRQ1_MASK,
.irq_reg_stride = MAX8907_REG_CHG_IRQ2 - MAX8907_REG_CHG_IRQ1,
.num_regs = 2,
.irqs = max8907_chg_irqs,
.num_irqs = ARRAY_SIZE(max8907_chg_irqs),
};
static const struct regmap_irq max8907_on_off_irqs[] = {
{ .reg_offset = 0, .mask = 1 << 0, },
{ .reg_offset = 0, .mask = 1 << 1, },
{ .reg_offset = 0, .mask = 1 << 2, },
{ .reg_offset = 0, .mask = 1 << 3, },
{ .reg_offset = 0, .mask = 1 << 4, },
{ .reg_offset = 0, .mask = 1 << 5, },
{ .reg_offset = 0, .mask = 1 << 6, },
{ .reg_offset = 0, .mask = 1 << 7, },
{ .reg_offset = 1, .mask = 1 << 0, },
{ .reg_offset = 1, .mask = 1 << 1, },
};
static const struct regmap_irq_chip max8907_on_off_irq_chip = {
.name = "max8907 on_off",
.status_base = MAX8907_REG_ON_OFF_IRQ1,
.mask_base = MAX8907_REG_ON_OFF_IRQ1_MASK,
.irq_reg_stride = MAX8907_REG_ON_OFF_IRQ2 - MAX8907_REG_ON_OFF_IRQ1,
.num_regs = 2,
.irqs = max8907_on_off_irqs,
.num_irqs = ARRAY_SIZE(max8907_on_off_irqs),
};
static const struct regmap_irq max8907_rtc_irqs[] = {
{ .reg_offset = 0, .mask = 1 << 2, },
{ .reg_offset = 0, .mask = 1 << 3, },
};
static const struct regmap_irq_chip max8907_rtc_irq_chip = {
.name = "max8907 rtc",
.status_base = MAX8907_REG_RTC_IRQ,
.mask_base = MAX8907_REG_RTC_IRQ_MASK,
.num_regs = 1,
.irqs = max8907_rtc_irqs,
.num_irqs = ARRAY_SIZE(max8907_rtc_irqs),
};
static struct max8907 *max8907_pm_off;
static void max8907_power_off(void)
{
regmap_update_bits(max8907_pm_off->regmap_gen, MAX8907_REG_RESET_CNFG,
MAX8907_MASK_POWER_OFF, MAX8907_MASK_POWER_OFF);
}
static int max8907_i2c_probe(struct i2c_client *i2c)
{
struct max8907 *max8907;
int ret;
struct max8907_platform_data *pdata = dev_get_platdata(&i2c->dev);
bool pm_off = false;
if (pdata)
pm_off = pdata->pm_off;
else if (i2c->dev.of_node)
pm_off = of_property_read_bool(i2c->dev.of_node,
"maxim,system-power-controller");
max8907 = devm_kzalloc(&i2c->dev, sizeof(struct max8907), GFP_KERNEL);
if (!max8907) {
ret = -ENOMEM;
goto err_alloc_drvdata;
}
max8907->dev = &i2c->dev;
max8907->i2c_gen = i2c;
i2c_set_clientdata(i2c, max8907);
max8907->regmap_gen = devm_regmap_init_i2c(i2c,
&max8907_regmap_gen_config);
if (IS_ERR(max8907->regmap_gen)) {
ret = PTR_ERR(max8907->regmap_gen);
dev_err(&i2c->dev, "gen regmap init failed: %d\n", ret);
goto err_regmap_gen;
}
max8907->i2c_rtc = i2c_new_dummy_device(i2c->adapter, MAX8907_RTC_I2C_ADDR);
if (IS_ERR(max8907->i2c_rtc)) {
ret = PTR_ERR(max8907->i2c_rtc);
goto err_dummy_rtc;
}
i2c_set_clientdata(max8907->i2c_rtc, max8907);
max8907->regmap_rtc = devm_regmap_init_i2c(max8907->i2c_rtc,
&max8907_regmap_rtc_config);
if (IS_ERR(max8907->regmap_rtc)) {
ret = PTR_ERR(max8907->regmap_rtc);
dev_err(&i2c->dev, "rtc regmap init failed: %d\n", ret);
goto err_regmap_rtc;
}
ret = regmap_add_irq_chip(max8907->regmap_gen, max8907->i2c_gen->irq,
IRQF_ONESHOT | IRQF_SHARED,
-1, &max8907_chg_irq_chip,
&max8907->irqc_chg);
if (ret != 0) {
dev_err(&i2c->dev, "failed to add chg irq chip: %d\n", ret);
goto err_irqc_chg;
}
ret = regmap_add_irq_chip(max8907->regmap_gen, max8907->i2c_gen->irq,
IRQF_ONESHOT | IRQF_SHARED, -1,
&max8907_on_off_irq_chip,
&max8907->irqc_on_off);
if (ret != 0) {
dev_err(&i2c->dev, "failed to add on off irq chip: %d\n", ret);
goto err_irqc_on_off;
}
ret = regmap_add_irq_chip(max8907->regmap_rtc, max8907->i2c_gen->irq,
IRQF_ONESHOT | IRQF_SHARED, -1,
&max8907_rtc_irq_chip,
&max8907->irqc_rtc);
if (ret != 0) {
dev_err(&i2c->dev, "failed to add rtc irq chip: %d\n", ret);
goto err_irqc_rtc;
}
ret = mfd_add_devices(max8907->dev, -1, max8907_cells,
ARRAY_SIZE(max8907_cells), NULL, 0, NULL);
if (ret != 0) {
dev_err(&i2c->dev, "failed to add MFD devices %d\n", ret);
goto err_add_devices;
}
if (pm_off && !pm_power_off) {
max8907_pm_off = max8907;
pm_power_off = max8907_power_off;
}
return 0;
err_add_devices:
regmap_del_irq_chip(max8907->i2c_gen->irq, max8907->irqc_rtc);
err_irqc_rtc:
regmap_del_irq_chip(max8907->i2c_gen->irq, max8907->irqc_on_off);
err_irqc_on_off:
regmap_del_irq_chip(max8907->i2c_gen->irq, max8907->irqc_chg);
err_irqc_chg:
err_regmap_rtc:
i2c_unregister_device(max8907->i2c_rtc);
err_dummy_rtc:
err_regmap_gen:
err_alloc_drvdata:
return ret;
}
static void max8907_i2c_remove(struct i2c_client *i2c)
{
struct max8907 *max8907 = i2c_get_clientdata(i2c);
mfd_remove_devices(max8907->dev);
regmap_del_irq_chip(max8907->i2c_gen->irq, max8907->irqc_rtc);
regmap_del_irq_chip(max8907->i2c_gen->irq, max8907->irqc_on_off);
regmap_del_irq_chip(max8907->i2c_gen->irq, max8907->irqc_chg);
i2c_unregister_device(max8907->i2c_rtc);
}
#ifdef CONFIG_OF
static const struct of_device_id max8907_of_match[] = {
{ .compatible = "maxim,max8907" },
{ },
};
MODULE_DEVICE_TABLE(of, max8907_of_match);
#endif
static const struct i2c_device_id max8907_i2c_id[] = {
{"max8907", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, max8907_i2c_id);
static struct i2c_driver max8907_i2c_driver = {
.driver = {
.name = "max8907",
.of_match_table = of_match_ptr(max8907_of_match),
},
.probe = max8907_i2c_probe,
.remove = max8907_i2c_remove,
.id_table = max8907_i2c_id,
};
static int __init max8907_i2c_init(void)
{
int ret = -ENODEV;
ret = i2c_add_driver(&max8907_i2c_driver);
if (ret != 0)
pr_err("Failed to register I2C driver: %d\n", ret);
return ret;
}
subsys_initcall(max8907_i2c_init);
static void __exit max8907_i2c_exit(void)
{
i2c_del_driver(&max8907_i2c_driver);
}
module_exit(max8907_i2c_exit);
MODULE_DESCRIPTION("MAX8907 multi-function core driver");
MODULE_AUTHOR("Gyungoh Yoo <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/max8907.c |
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Core driver for the Ocelot chip family.
*
* The VSC7511, 7512, 7513, and 7514 can be controlled internally via an
* on-chip MIPS processor, or externally via SPI, I2C, PCIe. This core driver is
* intended to be the bus-agnostic glue between, for example, the SPI bus and
* the child devices.
*
* Copyright 2021-2022 Innovative Advantage Inc.
*
* Author: Colin Foster <[email protected]>
*/
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/export.h>
#include <linux/iopoll.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/mfd/core.h>
#include <linux/mfd/ocelot.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/types.h>
#include <soc/mscc/ocelot.h>
#include "ocelot.h"
#define REG_GCB_SOFT_RST 0x0008
#define BIT_SOFT_CHIP_RST BIT(0)
#define VSC7512_MIIM0_RES_START 0x7107009c
#define VSC7512_MIIM1_RES_START 0x710700c0
#define VSC7512_MIIM_RES_SIZE 0x00000024
#define VSC7512_PHY_RES_START 0x710700f0
#define VSC7512_PHY_RES_SIZE 0x00000004
#define VSC7512_GPIO_RES_START 0x71070034
#define VSC7512_GPIO_RES_SIZE 0x0000006c
#define VSC7512_SIO_CTRL_RES_START 0x710700f8
#define VSC7512_SIO_CTRL_RES_SIZE 0x00000100
#define VSC7512_HSIO_RES_START 0x710d0000
#define VSC7512_HSIO_RES_SIZE 0x00000128
#define VSC7512_ANA_RES_START 0x71880000
#define VSC7512_ANA_RES_SIZE 0x00010000
#define VSC7512_QS_RES_START 0x71080000
#define VSC7512_QS_RES_SIZE 0x00000100
#define VSC7512_QSYS_RES_START 0x71800000
#define VSC7512_QSYS_RES_SIZE 0x00200000
#define VSC7512_REW_RES_START 0x71030000
#define VSC7512_REW_RES_SIZE 0x00010000
#define VSC7512_SYS_RES_START 0x71010000
#define VSC7512_SYS_RES_SIZE 0x00010000
#define VSC7512_S0_RES_START 0x71040000
#define VSC7512_S1_RES_START 0x71050000
#define VSC7512_S2_RES_START 0x71060000
#define VCAP_RES_SIZE 0x00000400
#define VSC7512_PORT_0_RES_START 0x711e0000
#define VSC7512_PORT_1_RES_START 0x711f0000
#define VSC7512_PORT_2_RES_START 0x71200000
#define VSC7512_PORT_3_RES_START 0x71210000
#define VSC7512_PORT_4_RES_START 0x71220000
#define VSC7512_PORT_5_RES_START 0x71230000
#define VSC7512_PORT_6_RES_START 0x71240000
#define VSC7512_PORT_7_RES_START 0x71250000
#define VSC7512_PORT_8_RES_START 0x71260000
#define VSC7512_PORT_9_RES_START 0x71270000
#define VSC7512_PORT_10_RES_START 0x71280000
#define VSC7512_PORT_RES_SIZE 0x00010000
#define VSC7512_GCB_RST_SLEEP_US 100
#define VSC7512_GCB_RST_TIMEOUT_US 100000
static int ocelot_gcb_chip_rst_status(struct ocelot_ddata *ddata)
{
int val, err;
err = regmap_read(ddata->gcb_regmap, REG_GCB_SOFT_RST, &val);
if (err)
return err;
return val;
}
int ocelot_chip_reset(struct device *dev)
{
struct ocelot_ddata *ddata = dev_get_drvdata(dev);
int ret, val;
/*
* Reset the entire chip here to put it into a completely known state.
* Other drivers may want to reset their own subsystems. The register
* self-clears, so one write is all that is needed and wait for it to
* clear.
*/
ret = regmap_write(ddata->gcb_regmap, REG_GCB_SOFT_RST, BIT_SOFT_CHIP_RST);
if (ret)
return ret;
return readx_poll_timeout(ocelot_gcb_chip_rst_status, ddata, val, !val,
VSC7512_GCB_RST_SLEEP_US, VSC7512_GCB_RST_TIMEOUT_US);
}
EXPORT_SYMBOL_NS(ocelot_chip_reset, MFD_OCELOT);
static const struct resource vsc7512_miim0_resources[] = {
DEFINE_RES_REG_NAMED(VSC7512_MIIM0_RES_START, VSC7512_MIIM_RES_SIZE, "gcb_miim0"),
DEFINE_RES_REG_NAMED(VSC7512_PHY_RES_START, VSC7512_PHY_RES_SIZE, "gcb_phy"),
};
static const struct resource vsc7512_miim1_resources[] = {
DEFINE_RES_REG_NAMED(VSC7512_MIIM1_RES_START, VSC7512_MIIM_RES_SIZE, "gcb_miim1"),
};
static const struct resource vsc7512_pinctrl_resources[] = {
DEFINE_RES_REG_NAMED(VSC7512_GPIO_RES_START, VSC7512_GPIO_RES_SIZE, "gcb_gpio"),
};
static const struct resource vsc7512_sgpio_resources[] = {
DEFINE_RES_REG_NAMED(VSC7512_SIO_CTRL_RES_START, VSC7512_SIO_CTRL_RES_SIZE, "gcb_sio"),
};
static const struct resource vsc7512_serdes_resources[] = {
DEFINE_RES_REG_NAMED(VSC7512_HSIO_RES_START, VSC7512_HSIO_RES_SIZE, "hsio"),
};
static const struct resource vsc7512_switch_resources[] = {
DEFINE_RES_REG_NAMED(VSC7512_ANA_RES_START, VSC7512_ANA_RES_SIZE, "ana"),
DEFINE_RES_REG_NAMED(VSC7512_HSIO_RES_START, VSC7512_HSIO_RES_SIZE, "hsio"),
DEFINE_RES_REG_NAMED(VSC7512_QS_RES_START, VSC7512_QS_RES_SIZE, "qs"),
DEFINE_RES_REG_NAMED(VSC7512_QSYS_RES_START, VSC7512_QSYS_RES_SIZE, "qsys"),
DEFINE_RES_REG_NAMED(VSC7512_REW_RES_START, VSC7512_REW_RES_SIZE, "rew"),
DEFINE_RES_REG_NAMED(VSC7512_SYS_RES_START, VSC7512_SYS_RES_SIZE, "sys"),
DEFINE_RES_REG_NAMED(VSC7512_S0_RES_START, VCAP_RES_SIZE, "s0"),
DEFINE_RES_REG_NAMED(VSC7512_S1_RES_START, VCAP_RES_SIZE, "s1"),
DEFINE_RES_REG_NAMED(VSC7512_S2_RES_START, VCAP_RES_SIZE, "s2"),
DEFINE_RES_REG_NAMED(VSC7512_PORT_0_RES_START, VSC7512_PORT_RES_SIZE, "port0"),
DEFINE_RES_REG_NAMED(VSC7512_PORT_1_RES_START, VSC7512_PORT_RES_SIZE, "port1"),
DEFINE_RES_REG_NAMED(VSC7512_PORT_2_RES_START, VSC7512_PORT_RES_SIZE, "port2"),
DEFINE_RES_REG_NAMED(VSC7512_PORT_3_RES_START, VSC7512_PORT_RES_SIZE, "port3"),
DEFINE_RES_REG_NAMED(VSC7512_PORT_4_RES_START, VSC7512_PORT_RES_SIZE, "port4"),
DEFINE_RES_REG_NAMED(VSC7512_PORT_5_RES_START, VSC7512_PORT_RES_SIZE, "port5"),
DEFINE_RES_REG_NAMED(VSC7512_PORT_6_RES_START, VSC7512_PORT_RES_SIZE, "port6"),
DEFINE_RES_REG_NAMED(VSC7512_PORT_7_RES_START, VSC7512_PORT_RES_SIZE, "port7"),
DEFINE_RES_REG_NAMED(VSC7512_PORT_8_RES_START, VSC7512_PORT_RES_SIZE, "port8"),
DEFINE_RES_REG_NAMED(VSC7512_PORT_9_RES_START, VSC7512_PORT_RES_SIZE, "port9"),
DEFINE_RES_REG_NAMED(VSC7512_PORT_10_RES_START, VSC7512_PORT_RES_SIZE, "port10")
};
static const struct mfd_cell vsc7512_devs[] = {
{
.name = "ocelot-pinctrl",
.of_compatible = "mscc,ocelot-pinctrl",
.num_resources = ARRAY_SIZE(vsc7512_pinctrl_resources),
.resources = vsc7512_pinctrl_resources,
}, {
.name = "ocelot-sgpio",
.of_compatible = "mscc,ocelot-sgpio",
.num_resources = ARRAY_SIZE(vsc7512_sgpio_resources),
.resources = vsc7512_sgpio_resources,
}, {
.name = "ocelot-miim0",
.of_compatible = "mscc,ocelot-miim",
.of_reg = VSC7512_MIIM0_RES_START,
.use_of_reg = true,
.num_resources = ARRAY_SIZE(vsc7512_miim0_resources),
.resources = vsc7512_miim0_resources,
}, {
.name = "ocelot-miim1",
.of_compatible = "mscc,ocelot-miim",
.of_reg = VSC7512_MIIM1_RES_START,
.use_of_reg = true,
.num_resources = ARRAY_SIZE(vsc7512_miim1_resources),
.resources = vsc7512_miim1_resources,
}, {
.name = "ocelot-serdes",
.of_compatible = "mscc,vsc7514-serdes",
.num_resources = ARRAY_SIZE(vsc7512_serdes_resources),
.resources = vsc7512_serdes_resources,
}, {
.name = "ocelot-ext-switch",
.of_compatible = "mscc,vsc7512-switch",
.num_resources = ARRAY_SIZE(vsc7512_switch_resources),
.resources = vsc7512_switch_resources,
},
};
static void ocelot_core_try_add_regmap(struct device *dev,
const struct resource *res)
{
if (dev_get_regmap(dev, res->name))
return;
ocelot_spi_init_regmap(dev, res);
}
static void ocelot_core_try_add_regmaps(struct device *dev,
const struct mfd_cell *cell)
{
int i;
for (i = 0; i < cell->num_resources; i++)
ocelot_core_try_add_regmap(dev, &cell->resources[i]);
}
int ocelot_core_init(struct device *dev)
{
int i, ndevs;
ndevs = ARRAY_SIZE(vsc7512_devs);
for (i = 0; i < ndevs; i++)
ocelot_core_try_add_regmaps(dev, &vsc7512_devs[i]);
return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, vsc7512_devs, ndevs, NULL, 0, NULL);
}
EXPORT_SYMBOL_NS(ocelot_core_init, MFD_OCELOT);
MODULE_DESCRIPTION("Externally Controlled Ocelot Chip Driver");
MODULE_AUTHOR("Colin Foster <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(MFD_OCELOT_SPI);
| linux-master | drivers/mfd/ocelot-core.c |
// SPDX-License-Identifier: GPL-2.0
/*
* CS42L43 SoundWire driver
*
* Copyright (C) 2022-2023 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*/
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/mfd/cs42l43-regs.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/soundwire/sdw_type.h>
#include "cs42l43.h"
enum cs42l43_sdw_ports {
CS42L43_DMIC_DEC_ASP_PORT = 1,
CS42L43_SPK_TX_PORT,
CS42L43_SPDIF_HP_PORT,
CS42L43_SPK_RX_PORT,
CS42L43_ASP_PORT,
};
static const struct regmap_config cs42l43_sdw_regmap = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.reg_format_endian = REGMAP_ENDIAN_LITTLE,
.val_format_endian = REGMAP_ENDIAN_LITTLE,
.max_register = CS42L43_MCU_RAM_MAX,
.readable_reg = cs42l43_readable_register,
.volatile_reg = cs42l43_volatile_register,
.precious_reg = cs42l43_precious_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = cs42l43_reg_default,
.num_reg_defaults = ARRAY_SIZE(cs42l43_reg_default),
};
static int cs42l43_read_prop(struct sdw_slave *sdw)
{
struct sdw_slave_prop *prop = &sdw->prop;
struct device *dev = &sdw->dev;
struct sdw_dpn_prop *dpn;
unsigned long addr;
int nval;
int i;
u32 bit;
prop->use_domain_irq = true;
prop->paging_support = true;
prop->wake_capable = true;
prop->source_ports = BIT(CS42L43_DMIC_DEC_ASP_PORT) | BIT(CS42L43_SPK_TX_PORT);
prop->sink_ports = BIT(CS42L43_SPDIF_HP_PORT) |
BIT(CS42L43_SPK_RX_PORT) | BIT(CS42L43_ASP_PORT);
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY |
SDW_SCP_INT1_IMPL_DEF;
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(dev, nval, sizeof(*prop->src_dpn_prop),
GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->src_dpn_prop;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].max_ch = 2;
dpn[i].type = SDW_DPN_FULL;
dpn[i].max_word = 24;
i++;
}
/*
* All ports are 2 channels max, except the first one,
* CS42L43_DMIC_DEC_ASP_PORT.
*/
dpn[CS42L43_DMIC_DEC_ASP_PORT].max_ch = 4;
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(dev, nval, sizeof(*prop->sink_dpn_prop),
GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].max_ch = 2;
dpn[i].type = SDW_DPN_FULL;
dpn[i].max_word = 24;
i++;
}
return 0;
}
static int cs42l43_sdw_update_status(struct sdw_slave *sdw, enum sdw_slave_status status)
{
struct cs42l43 *cs42l43 = dev_get_drvdata(&sdw->dev);
switch (status) {
case SDW_SLAVE_ATTACHED:
dev_dbg(cs42l43->dev, "Device attach\n");
sdw_write_no_pm(sdw, CS42L43_GEN_INT_MASK_1,
CS42L43_INT_STAT_GEN1_MASK);
cs42l43->attached = true;
complete(&cs42l43->device_attach);
break;
case SDW_SLAVE_UNATTACHED:
dev_dbg(cs42l43->dev, "Device detach\n");
cs42l43->attached = false;
reinit_completion(&cs42l43->device_attach);
complete(&cs42l43->device_detach);
break;
default:
break;
}
return 0;
}
static int cs42l43_sdw_interrupt(struct sdw_slave *sdw,
struct sdw_slave_intr_status *status)
{
/*
* The IRQ itself was handled through the regmap_irq handler, this is
* just clearing up the additional Cirrus SoundWire registers that are
* not covered by the SoundWire framework or the IRQ handler itself.
* There is only a single bit in GEN_INT_STAT_1 and it doesn't clear if
* IRQs are still pending so doing a read/write here after handling the
* IRQ is fine.
*/
sdw_read_no_pm(sdw, CS42L43_GEN_INT_STAT_1);
sdw_write_no_pm(sdw, CS42L43_GEN_INT_STAT_1, CS42L43_INT_STAT_GEN1_MASK);
return 0;
}
static int cs42l43_sdw_bus_config(struct sdw_slave *sdw,
struct sdw_bus_params *params)
{
struct cs42l43 *cs42l43 = dev_get_drvdata(&sdw->dev);
int ret = 0;
mutex_lock(&cs42l43->pll_lock);
if (cs42l43->sdw_freq != params->curr_dr_freq / 2) {
if (cs42l43->sdw_pll_active) {
dev_err(cs42l43->dev,
"PLL active can't change SoundWire bus clock\n");
ret = -EBUSY;
} else {
cs42l43->sdw_freq = params->curr_dr_freq / 2;
}
}
mutex_unlock(&cs42l43->pll_lock);
return ret;
}
static const struct sdw_slave_ops cs42l43_sdw_ops = {
.read_prop = cs42l43_read_prop,
.update_status = cs42l43_sdw_update_status,
.interrupt_callback = cs42l43_sdw_interrupt,
.bus_config = cs42l43_sdw_bus_config,
};
static int cs42l43_sdw_probe(struct sdw_slave *sdw, const struct sdw_device_id *id)
{
struct cs42l43 *cs42l43;
struct device *dev = &sdw->dev;
int ret;
cs42l43 = devm_kzalloc(dev, sizeof(*cs42l43), GFP_KERNEL);
if (!cs42l43)
return -ENOMEM;
cs42l43->dev = dev;
cs42l43->sdw = sdw;
cs42l43->regmap = devm_regmap_init_sdw(sdw, &cs42l43_sdw_regmap);
if (IS_ERR(cs42l43->regmap)) {
ret = PTR_ERR(cs42l43->regmap);
dev_err(cs42l43->dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
return cs42l43_dev_probe(cs42l43);
}
static int cs42l43_sdw_remove(struct sdw_slave *sdw)
{
struct cs42l43 *cs42l43 = dev_get_drvdata(&sdw->dev);
cs42l43_dev_remove(cs42l43);
return 0;
}
static const struct sdw_device_id cs42l43_sdw_id[] = {
SDW_SLAVE_ENTRY(0x01FA, 0x4243, 0),
{}
};
MODULE_DEVICE_TABLE(sdw, cs42l43_sdw_id);
static struct sdw_driver cs42l43_sdw_driver = {
.driver = {
.name = "cs42l43",
.pm = pm_ptr(&cs42l43_pm_ops),
},
.probe = cs42l43_sdw_probe,
.remove = cs42l43_sdw_remove,
.id_table = cs42l43_sdw_id,
.ops = &cs42l43_sdw_ops,
};
module_sdw_driver(cs42l43_sdw_driver);
MODULE_IMPORT_NS(MFD_CS42L43);
MODULE_DESCRIPTION("CS42L43 SoundWire Driver");
MODULE_AUTHOR("Lucas Tanure <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/cs42l43-sdw.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (c) 2012 Samsung Electronics Co., Ltd
// http://www.samsung.com
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/of.h>
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include <linux/mutex.h>
#include <linux/mfd/core.h>
#include <linux/mfd/samsung/core.h>
#include <linux/mfd/samsung/irq.h>
#include <linux/mfd/samsung/s2mpa01.h>
#include <linux/mfd/samsung/s2mps11.h>
#include <linux/mfd/samsung/s2mps13.h>
#include <linux/mfd/samsung/s2mps14.h>
#include <linux/mfd/samsung/s2mps15.h>
#include <linux/mfd/samsung/s2mpu02.h>
#include <linux/mfd/samsung/s5m8767.h>
#include <linux/regmap.h>
static const struct mfd_cell s5m8767_devs[] = {
{ .name = "s5m8767-pmic", },
{ .name = "s5m-rtc", },
{
.name = "s5m8767-clk",
.of_compatible = "samsung,s5m8767-clk",
},
};
static const struct mfd_cell s2mps11_devs[] = {
{ .name = "s2mps11-regulator", },
{ .name = "s2mps14-rtc", },
{
.name = "s2mps11-clk",
.of_compatible = "samsung,s2mps11-clk",
},
};
static const struct mfd_cell s2mps13_devs[] = {
{ .name = "s2mps13-regulator", },
{ .name = "s2mps13-rtc", },
{
.name = "s2mps13-clk",
.of_compatible = "samsung,s2mps13-clk",
},
};
static const struct mfd_cell s2mps14_devs[] = {
{ .name = "s2mps14-regulator", },
{ .name = "s2mps14-rtc", },
{
.name = "s2mps14-clk",
.of_compatible = "samsung,s2mps14-clk",
},
};
static const struct mfd_cell s2mps15_devs[] = {
{ .name = "s2mps15-regulator", },
{ .name = "s2mps15-rtc", },
{
.name = "s2mps13-clk",
.of_compatible = "samsung,s2mps13-clk",
},
};
static const struct mfd_cell s2mpa01_devs[] = {
{ .name = "s2mpa01-pmic", },
{ .name = "s2mps14-rtc", },
};
static const struct mfd_cell s2mpu02_devs[] = {
{ .name = "s2mpu02-regulator", },
};
static const struct of_device_id sec_dt_match[] = {
{
.compatible = "samsung,s5m8767-pmic",
.data = (void *)S5M8767X,
}, {
.compatible = "samsung,s2mps11-pmic",
.data = (void *)S2MPS11X,
}, {
.compatible = "samsung,s2mps13-pmic",
.data = (void *)S2MPS13X,
}, {
.compatible = "samsung,s2mps14-pmic",
.data = (void *)S2MPS14X,
}, {
.compatible = "samsung,s2mps15-pmic",
.data = (void *)S2MPS15X,
}, {
.compatible = "samsung,s2mpa01-pmic",
.data = (void *)S2MPA01,
}, {
.compatible = "samsung,s2mpu02-pmic",
.data = (void *)S2MPU02,
}, {
/* Sentinel */
},
};
MODULE_DEVICE_TABLE(of, sec_dt_match);
static bool s2mpa01_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case S2MPA01_REG_INT1M:
case S2MPA01_REG_INT2M:
case S2MPA01_REG_INT3M:
return false;
default:
return true;
}
}
static bool s2mps11_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case S2MPS11_REG_INT1M:
case S2MPS11_REG_INT2M:
case S2MPS11_REG_INT3M:
return false;
default:
return true;
}
}
static bool s2mpu02_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case S2MPU02_REG_INT1M:
case S2MPU02_REG_INT2M:
case S2MPU02_REG_INT3M:
return false;
default:
return true;
}
}
static const struct regmap_config sec_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
static const struct regmap_config s2mpa01_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = S2MPA01_REG_LDO_OVCB4,
.volatile_reg = s2mpa01_volatile,
.cache_type = REGCACHE_FLAT,
};
static const struct regmap_config s2mps11_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = S2MPS11_REG_L38CTRL,
.volatile_reg = s2mps11_volatile,
.cache_type = REGCACHE_FLAT,
};
static const struct regmap_config s2mps13_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = S2MPS13_REG_LDODSCH5,
.volatile_reg = s2mps11_volatile,
.cache_type = REGCACHE_FLAT,
};
static const struct regmap_config s2mps14_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = S2MPS14_REG_LDODSCH3,
.volatile_reg = s2mps11_volatile,
.cache_type = REGCACHE_FLAT,
};
static const struct regmap_config s2mps15_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = S2MPS15_REG_LDODSCH4,
.volatile_reg = s2mps11_volatile,
.cache_type = REGCACHE_FLAT,
};
static const struct regmap_config s2mpu02_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = S2MPU02_REG_DVSDATA,
.volatile_reg = s2mpu02_volatile,
.cache_type = REGCACHE_FLAT,
};
static const struct regmap_config s5m8767_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = S5M8767_REG_LDO28CTRL,
.volatile_reg = s2mps11_volatile,
.cache_type = REGCACHE_FLAT,
};
static void sec_pmic_dump_rev(struct sec_pmic_dev *sec_pmic)
{
unsigned int val;
/* For each device type, the REG_ID is always the first register */
if (!regmap_read(sec_pmic->regmap_pmic, S2MPS11_REG_ID, &val))
dev_dbg(sec_pmic->dev, "Revision: 0x%x\n", val);
}
static void sec_pmic_configure(struct sec_pmic_dev *sec_pmic)
{
int err;
if (sec_pmic->device_type != S2MPS13X)
return;
if (sec_pmic->pdata->disable_wrstbi) {
/*
* If WRSTBI pin is pulled down this feature must be disabled
* because each Suspend to RAM will trigger buck voltage reset
* to default values.
*/
err = regmap_update_bits(sec_pmic->regmap_pmic,
S2MPS13_REG_WRSTBI,
S2MPS13_REG_WRSTBI_MASK, 0x0);
if (err)
dev_warn(sec_pmic->dev,
"Cannot initialize WRSTBI config: %d\n",
err);
}
}
/*
* Only the common platform data elements for s5m8767 are parsed here from the
* device tree. Other sub-modules of s5m8767 such as pmic, rtc , charger and
* others have to parse their own platform data elements from device tree.
*
* The s5m8767 platform data structure is instantiated here and the drivers for
* the sub-modules need not instantiate another instance while parsing their
* platform data.
*/
static struct sec_platform_data *
sec_pmic_i2c_parse_dt_pdata(struct device *dev)
{
struct sec_platform_data *pd;
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
if (!pd)
return ERR_PTR(-ENOMEM);
pd->manual_poweroff = of_property_read_bool(dev->of_node,
"samsung,s2mps11-acokb-ground");
pd->disable_wrstbi = of_property_read_bool(dev->of_node,
"samsung,s2mps11-wrstbi-ground");
return pd;
}
static int sec_pmic_probe(struct i2c_client *i2c)
{
const struct regmap_config *regmap;
struct sec_platform_data *pdata;
const struct mfd_cell *sec_devs;
struct sec_pmic_dev *sec_pmic;
int ret, num_sec_devs;
sec_pmic = devm_kzalloc(&i2c->dev, sizeof(struct sec_pmic_dev),
GFP_KERNEL);
if (sec_pmic == NULL)
return -ENOMEM;
i2c_set_clientdata(i2c, sec_pmic);
sec_pmic->dev = &i2c->dev;
sec_pmic->i2c = i2c;
sec_pmic->irq = i2c->irq;
pdata = sec_pmic_i2c_parse_dt_pdata(sec_pmic->dev);
if (IS_ERR(pdata)) {
ret = PTR_ERR(pdata);
return ret;
}
sec_pmic->device_type = (unsigned long)of_device_get_match_data(sec_pmic->dev);
sec_pmic->pdata = pdata;
switch (sec_pmic->device_type) {
case S2MPA01:
regmap = &s2mpa01_regmap_config;
break;
case S2MPS11X:
regmap = &s2mps11_regmap_config;
break;
case S2MPS13X:
regmap = &s2mps13_regmap_config;
break;
case S2MPS14X:
regmap = &s2mps14_regmap_config;
break;
case S2MPS15X:
regmap = &s2mps15_regmap_config;
break;
case S5M8767X:
regmap = &s5m8767_regmap_config;
break;
case S2MPU02:
regmap = &s2mpu02_regmap_config;
break;
default:
regmap = &sec_regmap_config;
break;
}
sec_pmic->regmap_pmic = devm_regmap_init_i2c(i2c, regmap);
if (IS_ERR(sec_pmic->regmap_pmic)) {
ret = PTR_ERR(sec_pmic->regmap_pmic);
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
sec_irq_init(sec_pmic);
pm_runtime_set_active(sec_pmic->dev);
switch (sec_pmic->device_type) {
case S5M8767X:
sec_devs = s5m8767_devs;
num_sec_devs = ARRAY_SIZE(s5m8767_devs);
break;
case S2MPA01:
sec_devs = s2mpa01_devs;
num_sec_devs = ARRAY_SIZE(s2mpa01_devs);
break;
case S2MPS11X:
sec_devs = s2mps11_devs;
num_sec_devs = ARRAY_SIZE(s2mps11_devs);
break;
case S2MPS13X:
sec_devs = s2mps13_devs;
num_sec_devs = ARRAY_SIZE(s2mps13_devs);
break;
case S2MPS14X:
sec_devs = s2mps14_devs;
num_sec_devs = ARRAY_SIZE(s2mps14_devs);
break;
case S2MPS15X:
sec_devs = s2mps15_devs;
num_sec_devs = ARRAY_SIZE(s2mps15_devs);
break;
case S2MPU02:
sec_devs = s2mpu02_devs;
num_sec_devs = ARRAY_SIZE(s2mpu02_devs);
break;
default:
dev_err(&i2c->dev, "Unsupported device type (%lu)\n",
sec_pmic->device_type);
return -ENODEV;
}
ret = devm_mfd_add_devices(sec_pmic->dev, -1, sec_devs, num_sec_devs,
NULL, 0, NULL);
if (ret)
return ret;
sec_pmic_configure(sec_pmic);
sec_pmic_dump_rev(sec_pmic);
return ret;
}
static void sec_pmic_shutdown(struct i2c_client *i2c)
{
struct sec_pmic_dev *sec_pmic = i2c_get_clientdata(i2c);
unsigned int reg, mask;
if (!sec_pmic->pdata->manual_poweroff)
return;
switch (sec_pmic->device_type) {
case S2MPS11X:
reg = S2MPS11_REG_CTRL1;
mask = S2MPS11_CTRL1_PWRHOLD_MASK;
break;
default:
/*
* Currently only one board with S2MPS11 needs this, so just
* ignore the rest.
*/
dev_warn(sec_pmic->dev,
"Unsupported device %lu for manual power off\n",
sec_pmic->device_type);
return;
}
regmap_update_bits(sec_pmic->regmap_pmic, reg, mask, 0);
}
static int sec_pmic_suspend(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct sec_pmic_dev *sec_pmic = i2c_get_clientdata(i2c);
if (device_may_wakeup(dev))
enable_irq_wake(sec_pmic->irq);
/*
* PMIC IRQ must be disabled during suspend for RTC alarm
* to work properly.
* When device is woken up from suspend, an
* interrupt occurs before resuming I2C bus controller.
* The interrupt is handled by regmap_irq_thread which tries
* to read RTC registers. This read fails (I2C is still
* suspended) and RTC Alarm interrupt is disabled.
*/
disable_irq(sec_pmic->irq);
return 0;
}
static int sec_pmic_resume(struct device *dev)
{
struct i2c_client *i2c = to_i2c_client(dev);
struct sec_pmic_dev *sec_pmic = i2c_get_clientdata(i2c);
if (device_may_wakeup(dev))
disable_irq_wake(sec_pmic->irq);
enable_irq(sec_pmic->irq);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(sec_pmic_pm_ops,
sec_pmic_suspend, sec_pmic_resume);
static struct i2c_driver sec_pmic_driver = {
.driver = {
.name = "sec_pmic",
.pm = pm_sleep_ptr(&sec_pmic_pm_ops),
.of_match_table = sec_dt_match,
},
.probe = sec_pmic_probe,
.shutdown = sec_pmic_shutdown,
};
module_i2c_driver(sec_pmic_driver);
MODULE_AUTHOR("Sangbeom Kim <[email protected]>");
MODULE_DESCRIPTION("Core support for the S5M MFD");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/sec-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2009-2010 Pengutronix
* Uwe Kleine-Koenig <[email protected]>
*
* loosely based on an earlier driver that has
* Copyright 2009 Pengutronix, Sascha Hauer <[email protected]>
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include "mc13xxx.h"
#define MC13XXX_IRQSTAT0 0
#define MC13XXX_IRQMASK0 1
#define MC13XXX_IRQSTAT1 3
#define MC13XXX_IRQMASK1 4
#define MC13XXX_REVISION 7
#define MC13XXX_REVISION_REVMETAL (0x07 << 0)
#define MC13XXX_REVISION_REVFULL (0x03 << 3)
#define MC13XXX_REVISION_ICID (0x07 << 6)
#define MC13XXX_REVISION_FIN (0x03 << 9)
#define MC13XXX_REVISION_FAB (0x03 << 11)
#define MC13XXX_REVISION_ICIDCODE (0x3f << 13)
#define MC34708_REVISION_REVMETAL (0x07 << 0)
#define MC34708_REVISION_REVFULL (0x07 << 3)
#define MC34708_REVISION_FIN (0x07 << 6)
#define MC34708_REVISION_FAB (0x07 << 9)
#define MC13XXX_PWRCTRL 15
#define MC13XXX_PWRCTRL_WDIRESET (1 << 12)
#define MC13XXX_ADC1 44
#define MC13XXX_ADC1_ADEN (1 << 0)
#define MC13XXX_ADC1_RAND (1 << 1)
#define MC13XXX_ADC1_ADSEL (1 << 3)
#define MC13XXX_ADC1_ASC (1 << 20)
#define MC13XXX_ADC1_ADTRIGIGN (1 << 21)
#define MC13XXX_ADC2 45
void mc13xxx_lock(struct mc13xxx *mc13xxx)
{
if (!mutex_trylock(&mc13xxx->lock)) {
dev_dbg(mc13xxx->dev, "wait for %s from %ps\n",
__func__, __builtin_return_address(0));
mutex_lock(&mc13xxx->lock);
}
dev_dbg(mc13xxx->dev, "%s from %ps\n",
__func__, __builtin_return_address(0));
}
EXPORT_SYMBOL(mc13xxx_lock);
void mc13xxx_unlock(struct mc13xxx *mc13xxx)
{
dev_dbg(mc13xxx->dev, "%s from %ps\n",
__func__, __builtin_return_address(0));
mutex_unlock(&mc13xxx->lock);
}
EXPORT_SYMBOL(mc13xxx_unlock);
int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
{
int ret;
ret = regmap_read(mc13xxx->regmap, offset, val);
dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
return ret;
}
EXPORT_SYMBOL(mc13xxx_reg_read);
int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
{
dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);
if (val >= BIT(24))
return -EINVAL;
return regmap_write(mc13xxx->regmap, offset, val);
}
EXPORT_SYMBOL(mc13xxx_reg_write);
int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
u32 mask, u32 val)
{
BUG_ON(val & ~mask);
dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x (mask: 0x%06x)\n",
offset, val, mask);
return regmap_update_bits(mc13xxx->regmap, offset, mask, val);
}
EXPORT_SYMBOL(mc13xxx_reg_rmw);
int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
{
int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
disable_irq_nosync(virq);
return 0;
}
EXPORT_SYMBOL(mc13xxx_irq_mask);
int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
{
int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
enable_irq(virq);
return 0;
}
EXPORT_SYMBOL(mc13xxx_irq_unmask);
int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
int *enabled, int *pending)
{
int ret;
unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
if (irq < 0 || irq >= ARRAY_SIZE(mc13xxx->irqs))
return -EINVAL;
if (enabled) {
u32 mask;
ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
if (ret)
return ret;
*enabled = mask & irqbit;
}
if (pending) {
u32 stat;
ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
if (ret)
return ret;
*pending = stat & irqbit;
}
return 0;
}
EXPORT_SYMBOL(mc13xxx_irq_status);
int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
irq_handler_t handler, const char *name, void *dev)
{
int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
return devm_request_threaded_irq(mc13xxx->dev, virq, NULL, handler,
IRQF_ONESHOT, name, dev);
}
EXPORT_SYMBOL(mc13xxx_irq_request);
int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
{
int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
devm_free_irq(mc13xxx->dev, virq, dev);
return 0;
}
EXPORT_SYMBOL(mc13xxx_irq_free);
#define maskval(reg, mask) (((reg) & (mask)) >> __ffs(mask))
static void mc13xxx_print_revision(struct mc13xxx *mc13xxx, u32 revision)
{
dev_info(mc13xxx->dev, "%s: rev: %d.%d, "
"fin: %d, fab: %d, icid: %d/%d\n",
mc13xxx->variant->name,
maskval(revision, MC13XXX_REVISION_REVFULL),
maskval(revision, MC13XXX_REVISION_REVMETAL),
maskval(revision, MC13XXX_REVISION_FIN),
maskval(revision, MC13XXX_REVISION_FAB),
maskval(revision, MC13XXX_REVISION_ICID),
maskval(revision, MC13XXX_REVISION_ICIDCODE));
}
static void mc34708_print_revision(struct mc13xxx *mc13xxx, u32 revision)
{
dev_info(mc13xxx->dev, "%s: rev %d.%d, fin: %d, fab: %d\n",
mc13xxx->variant->name,
maskval(revision, MC34708_REVISION_REVFULL),
maskval(revision, MC34708_REVISION_REVMETAL),
maskval(revision, MC34708_REVISION_FIN),
maskval(revision, MC34708_REVISION_FAB));
}
/* These are only exported for mc13xxx-i2c and mc13xxx-spi */
struct mc13xxx_variant mc13xxx_variant_mc13783 = {
.name = "mc13783",
.print_revision = mc13xxx_print_revision,
};
EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13783);
struct mc13xxx_variant mc13xxx_variant_mc13892 = {
.name = "mc13892",
.print_revision = mc13xxx_print_revision,
};
EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13892);
struct mc13xxx_variant mc13xxx_variant_mc34708 = {
.name = "mc34708",
.print_revision = mc34708_print_revision,
};
EXPORT_SYMBOL_GPL(mc13xxx_variant_mc34708);
static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
{
return mc13xxx->variant->name;
}
int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
{
return mc13xxx->flags;
}
EXPORT_SYMBOL(mc13xxx_get_flags);
#define MC13XXX_ADC1_CHAN0_SHIFT 5
#define MC13XXX_ADC1_CHAN1_SHIFT 8
#define MC13783_ADC1_ATO_SHIFT 11
#define MC13783_ADC1_ATOX (1 << 19)
struct mc13xxx_adcdone_data {
struct mc13xxx *mc13xxx;
struct completion done;
};
static irqreturn_t mc13xxx_handler_adcdone(int irq, void *data)
{
struct mc13xxx_adcdone_data *adcdone_data = data;
complete_all(&adcdone_data->done);
return IRQ_HANDLED;
}
#define MC13XXX_ADC_WORKING (1 << 0)
int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
unsigned int channel, u8 ato, bool atox,
unsigned int *sample)
{
u32 adc0, adc1, old_adc0;
int i, ret;
struct mc13xxx_adcdone_data adcdone_data = {
.mc13xxx = mc13xxx,
};
init_completion(&adcdone_data.done);
dev_dbg(mc13xxx->dev, "%s\n", __func__);
mc13xxx_lock(mc13xxx);
if (mc13xxx->adcflags & MC13XXX_ADC_WORKING) {
ret = -EBUSY;
goto out;
}
mc13xxx->adcflags |= MC13XXX_ADC_WORKING;
ret = mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);
if (ret)
goto out;
adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2 |
MC13XXX_ADC0_CHRGRAWDIV;
adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;
/*
* Channels mapped through ADIN7:
* 7 - General purpose ADIN7
* 16 - UID
* 17 - Die temperature
*/
if (channel > 7 && channel < 16) {
adc1 |= MC13XXX_ADC1_ADSEL;
} else if (channel == 16) {
adc0 |= MC13XXX_ADC0_ADIN7SEL_UID;
channel = 7;
} else if (channel == 17) {
adc0 |= MC13XXX_ADC0_ADIN7SEL_DIE;
channel = 7;
}
switch (mode) {
case MC13XXX_ADC_MODE_TS:
adc0 |= MC13XXX_ADC0_ADREFEN | MC13XXX_ADC0_TSMOD0 |
MC13XXX_ADC0_TSMOD1;
adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
break;
case MC13XXX_ADC_MODE_SINGLE_CHAN:
adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
adc1 |= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
adc1 |= MC13XXX_ADC1_RAND;
break;
case MC13XXX_ADC_MODE_MULT_CHAN:
adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
break;
default:
mc13xxx_unlock(mc13xxx);
return -EINVAL;
}
adc1 |= ato << MC13783_ADC1_ATO_SHIFT;
if (atox)
adc1 |= MC13783_ADC1_ATOX;
dev_dbg(mc13xxx->dev, "%s: request irq\n", __func__);
ret = mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
mc13xxx_handler_adcdone, __func__, &adcdone_data);
if (ret)
goto out;
mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, adc0);
mc13xxx_reg_write(mc13xxx, MC13XXX_ADC1, adc1);
mc13xxx_unlock(mc13xxx);
ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
if (!ret)
ret = -ETIMEDOUT;
mc13xxx_lock(mc13xxx);
mc13xxx_irq_free(mc13xxx, MC13XXX_IRQ_ADCDONE, &adcdone_data);
if (ret > 0)
for (i = 0; i < 4; ++i) {
ret = mc13xxx_reg_read(mc13xxx,
MC13XXX_ADC2, &sample[i]);
if (ret)
break;
}
if (mode == MC13XXX_ADC_MODE_TS)
/* restore TSMOD */
mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, old_adc0);
mc13xxx->adcflags &= ~MC13XXX_ADC_WORKING;
out:
mc13xxx_unlock(mc13xxx);
return ret;
}
EXPORT_SYMBOL_GPL(mc13xxx_adc_do_conversion);
static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
const char *format, void *pdata, size_t pdata_size)
{
char buf[30];
const char *name = mc13xxx_get_chipname(mc13xxx);
struct mfd_cell cell = {
.platform_data = pdata,
.pdata_size = pdata_size,
};
/* there is no asnprintf in the kernel :-( */
if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
return -E2BIG;
cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
if (!cell.name)
return -ENOMEM;
return mfd_add_devices(mc13xxx->dev, -1, &cell, 1, NULL, 0,
regmap_irq_get_domain(mc13xxx->irq_data));
}
static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
{
return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
}
#ifdef CONFIG_OF
static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
{
struct device_node *np = mc13xxx->dev->of_node;
if (!np)
return -ENODEV;
if (of_property_read_bool(np, "fsl,mc13xxx-uses-adc"))
mc13xxx->flags |= MC13XXX_USE_ADC;
if (of_property_read_bool(np, "fsl,mc13xxx-uses-codec"))
mc13xxx->flags |= MC13XXX_USE_CODEC;
if (of_property_read_bool(np, "fsl,mc13xxx-uses-rtc"))
mc13xxx->flags |= MC13XXX_USE_RTC;
if (of_property_read_bool(np, "fsl,mc13xxx-uses-touch"))
mc13xxx->flags |= MC13XXX_USE_TOUCHSCREEN;
return 0;
}
#else
static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
{
return -ENODEV;
}
#endif
int mc13xxx_common_init(struct device *dev)
{
struct mc13xxx_platform_data *pdata = dev_get_platdata(dev);
struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
u32 revision;
int i, ret;
mc13xxx->dev = dev;
ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
if (ret)
return ret;
mc13xxx->variant->print_revision(mc13xxx, revision);
ret = mc13xxx_reg_rmw(mc13xxx, MC13XXX_PWRCTRL,
MC13XXX_PWRCTRL_WDIRESET, MC13XXX_PWRCTRL_WDIRESET);
if (ret)
return ret;
for (i = 0; i < ARRAY_SIZE(mc13xxx->irqs); i++) {
mc13xxx->irqs[i].reg_offset = i / MC13XXX_IRQ_PER_REG;
mc13xxx->irqs[i].mask = BIT(i % MC13XXX_IRQ_PER_REG);
}
mc13xxx->irq_chip.name = dev_name(dev);
mc13xxx->irq_chip.status_base = MC13XXX_IRQSTAT0;
mc13xxx->irq_chip.mask_base = MC13XXX_IRQMASK0;
mc13xxx->irq_chip.ack_base = MC13XXX_IRQSTAT0;
mc13xxx->irq_chip.irq_reg_stride = MC13XXX_IRQSTAT1 - MC13XXX_IRQSTAT0;
mc13xxx->irq_chip.init_ack_masked = true;
mc13xxx->irq_chip.use_ack = true;
mc13xxx->irq_chip.num_regs = MC13XXX_IRQ_REG_CNT;
mc13xxx->irq_chip.irqs = mc13xxx->irqs;
mc13xxx->irq_chip.num_irqs = ARRAY_SIZE(mc13xxx->irqs);
ret = regmap_add_irq_chip(mc13xxx->regmap, mc13xxx->irq, IRQF_ONESHOT,
0, &mc13xxx->irq_chip, &mc13xxx->irq_data);
if (ret)
return ret;
mutex_init(&mc13xxx->lock);
if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
mc13xxx->flags = pdata->flags;
if (pdata) {
mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
&pdata->regulators, sizeof(pdata->regulators));
mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
pdata->leds, sizeof(*pdata->leds));
mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
pdata->buttons, sizeof(*pdata->buttons));
if (mc13xxx->flags & MC13XXX_USE_CODEC)
mc13xxx_add_subdevice_pdata(mc13xxx, "%s-codec",
pdata->codec, sizeof(*pdata->codec));
if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
mc13xxx_add_subdevice_pdata(mc13xxx, "%s-ts",
&pdata->touch, sizeof(pdata->touch));
} else {
mc13xxx_add_subdevice(mc13xxx, "%s-regulator");
mc13xxx_add_subdevice(mc13xxx, "%s-led");
mc13xxx_add_subdevice(mc13xxx, "%s-pwrbutton");
if (mc13xxx->flags & MC13XXX_USE_CODEC)
mc13xxx_add_subdevice(mc13xxx, "%s-codec");
if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
mc13xxx_add_subdevice(mc13xxx, "%s-ts");
}
if (mc13xxx->flags & MC13XXX_USE_ADC)
mc13xxx_add_subdevice(mc13xxx, "%s-adc");
if (mc13xxx->flags & MC13XXX_USE_RTC)
mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
return 0;
}
EXPORT_SYMBOL_GPL(mc13xxx_common_init);
void mc13xxx_common_exit(struct device *dev)
{
struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
mfd_remove_devices(dev);
regmap_del_irq_chip(mc13xxx->irq, mc13xxx->irq_data);
mutex_destroy(&mc13xxx->lock);
}
EXPORT_SYMBOL_GPL(mc13xxx_common_exit);
MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
MODULE_AUTHOR("Uwe Kleine-Koenig <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/mc13xxx-core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
//
// Copyright (C) 2018 ROHM Semiconductors
//
// ROHM BD71837MWV and BD71847MWV PMIC driver
//
// Datasheet for BD71837MWV available from
// https://www.rohm.com/datasheet/BD71837MWV/bd71837mwv-e
#include <linux/gpio_keys.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/mfd/rohm-bd718x7.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/types.h>
static struct gpio_keys_button button = {
.code = KEY_POWER,
.gpio = -1,
.type = EV_KEY,
};
static struct gpio_keys_platform_data bd718xx_powerkey_data = {
.buttons = &button,
.nbuttons = 1,
.name = "bd718xx-pwrkey",
};
static struct mfd_cell bd71837_mfd_cells[] = {
{
.name = "gpio-keys",
.platform_data = &bd718xx_powerkey_data,
.pdata_size = sizeof(bd718xx_powerkey_data),
},
{ .name = "bd71837-clk", },
{ .name = "bd71837-pmic", },
};
static struct mfd_cell bd71847_mfd_cells[] = {
{
.name = "gpio-keys",
.platform_data = &bd718xx_powerkey_data,
.pdata_size = sizeof(bd718xx_powerkey_data),
},
{ .name = "bd71847-clk", },
{ .name = "bd71847-pmic", },
};
static const struct regmap_irq bd718xx_irqs[] = {
REGMAP_IRQ_REG(BD718XX_INT_SWRST, 0, BD718XX_INT_SWRST_MASK),
REGMAP_IRQ_REG(BD718XX_INT_PWRBTN_S, 0, BD718XX_INT_PWRBTN_S_MASK),
REGMAP_IRQ_REG(BD718XX_INT_PWRBTN_L, 0, BD718XX_INT_PWRBTN_L_MASK),
REGMAP_IRQ_REG(BD718XX_INT_PWRBTN, 0, BD718XX_INT_PWRBTN_MASK),
REGMAP_IRQ_REG(BD718XX_INT_WDOG, 0, BD718XX_INT_WDOG_MASK),
REGMAP_IRQ_REG(BD718XX_INT_ON_REQ, 0, BD718XX_INT_ON_REQ_MASK),
REGMAP_IRQ_REG(BD718XX_INT_STBY_REQ, 0, BD718XX_INT_STBY_REQ_MASK),
};
static struct regmap_irq_chip bd718xx_irq_chip = {
.name = "bd718xx-irq",
.irqs = bd718xx_irqs,
.num_irqs = ARRAY_SIZE(bd718xx_irqs),
.num_regs = 1,
.irq_reg_stride = 1,
.status_base = BD718XX_REG_IRQ,
.mask_base = BD718XX_REG_MIRQ,
.ack_base = BD718XX_REG_IRQ,
.init_ack_masked = true,
};
static const struct regmap_range pmic_status_range = {
.range_min = BD718XX_REG_IRQ,
.range_max = BD718XX_REG_POW_STATE,
};
static const struct regmap_access_table volatile_regs = {
.yes_ranges = &pmic_status_range,
.n_yes_ranges = 1,
};
static const struct regmap_config bd718xx_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_table = &volatile_regs,
.max_register = BD718XX_MAX_REGISTER - 1,
.cache_type = REGCACHE_RBTREE,
};
static int bd718xx_init_press_duration(struct regmap *regmap,
struct device *dev)
{
u32 short_press_ms, long_press_ms;
u32 short_press_value, long_press_value;
int ret;
ret = of_property_read_u32(dev->of_node, "rohm,short-press-ms",
&short_press_ms);
if (!ret) {
short_press_value = min(15u, (short_press_ms + 250) / 500);
ret = regmap_update_bits(regmap, BD718XX_REG_PWRONCONFIG0,
BD718XX_PWRBTN_PRESS_DURATION_MASK,
short_press_value);
if (ret) {
dev_err(dev, "Failed to init pwron short press\n");
return ret;
}
}
ret = of_property_read_u32(dev->of_node, "rohm,long-press-ms",
&long_press_ms);
if (!ret) {
long_press_value = min(15u, (long_press_ms + 500) / 1000);
ret = regmap_update_bits(regmap, BD718XX_REG_PWRONCONFIG1,
BD718XX_PWRBTN_PRESS_DURATION_MASK,
long_press_value);
if (ret) {
dev_err(dev, "Failed to init pwron long press\n");
return ret;
}
}
return 0;
}
static int bd718xx_i2c_probe(struct i2c_client *i2c)
{
struct regmap *regmap;
struct regmap_irq_chip_data *irq_data;
int ret;
unsigned int chip_type;
struct mfd_cell *mfd;
int cells;
if (!i2c->irq) {
dev_err(&i2c->dev, "No IRQ configured\n");
return -EINVAL;
}
chip_type = (unsigned int)(uintptr_t)
of_device_get_match_data(&i2c->dev);
switch (chip_type) {
case ROHM_CHIP_TYPE_BD71837:
mfd = bd71837_mfd_cells;
cells = ARRAY_SIZE(bd71837_mfd_cells);
break;
case ROHM_CHIP_TYPE_BD71847:
mfd = bd71847_mfd_cells;
cells = ARRAY_SIZE(bd71847_mfd_cells);
break;
default:
dev_err(&i2c->dev, "Unknown device type");
return -EINVAL;
}
regmap = devm_regmap_init_i2c(i2c, &bd718xx_regmap_config);
if (IS_ERR(regmap))
return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
"regmap initialization failed\n");
ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq,
IRQF_ONESHOT, 0, &bd718xx_irq_chip,
&irq_data);
if (ret)
return dev_err_probe(&i2c->dev, ret, "Failed to add irq_chip\n");
ret = bd718xx_init_press_duration(regmap, &i2c->dev);
if (ret)
return ret;
ret = regmap_irq_get_virq(irq_data, BD718XX_INT_PWRBTN_S);
if (ret < 0)
return dev_err_probe(&i2c->dev, ret, "Failed to get the IRQ\n");
button.irq = ret;
ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
mfd, cells, NULL, 0,
regmap_irq_get_domain(irq_data));
if (ret)
dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n");
return ret;
}
static const struct of_device_id bd718xx_of_match[] = {
{
.compatible = "rohm,bd71837",
.data = (void *)ROHM_CHIP_TYPE_BD71837,
},
{
.compatible = "rohm,bd71847",
.data = (void *)ROHM_CHIP_TYPE_BD71847,
},
{
.compatible = "rohm,bd71850",
.data = (void *)ROHM_CHIP_TYPE_BD71847,
},
{ }
};
MODULE_DEVICE_TABLE(of, bd718xx_of_match);
static struct i2c_driver bd718xx_i2c_driver = {
.driver = {
.name = "rohm-bd718x7",
.of_match_table = bd718xx_of_match,
},
.probe = bd718xx_i2c_probe,
};
static int __init bd718xx_i2c_init(void)
{
return i2c_add_driver(&bd718xx_i2c_driver);
}
/* Initialise early so consumer devices can complete system boot */
subsys_initcall(bd718xx_i2c_init);
static void __exit bd718xx_i2c_exit(void)
{
i2c_del_driver(&bd718xx_i2c_driver);
}
module_exit(bd718xx_i2c_exit);
MODULE_AUTHOR("Matti Vaittinen <[email protected]>");
MODULE_DESCRIPTION("ROHM BD71837/BD71847 Power Management IC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/rohm-bd718x7.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm8998-tables.c -- data tables for wm8998-class codecs
*
* Copyright 2014 Wolfson Microelectronics plc
*
* Author: Richard Fitzgerald <[email protected]>
*/
#include <linux/module.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/registers.h>
#include <linux/device.h>
#include "arizona.h"
#define WM8998_NUM_AOD_ISR 2
#define WM8998_NUM_ISR 5
static const struct reg_sequence wm8998_rev_a_patch[] = {
{ 0x0212, 0x0000 },
{ 0x0211, 0x0014 },
{ 0x04E4, 0x0E0D },
{ 0x04E5, 0x0E0D },
{ 0x04E6, 0x0E0D },
{ 0x04EB, 0x060E },
{ 0x0441, 0xC759 },
{ 0x0442, 0x2A08 },
{ 0x0443, 0x5CFA },
{ 0x026E, 0x0064 },
{ 0x026F, 0x00EA },
{ 0x0270, 0x1F16 },
{ 0x0410, 0x2080 },
{ 0x0418, 0x2080 },
{ 0x0420, 0x2080 },
{ 0x04B8, 0x1120 },
{ 0x047E, 0x080E },
{ 0x0448, 0x03EF },
};
/* We use a function so we can use ARRAY_SIZE() */
int wm8998_patch(struct arizona *arizona)
{
return regmap_register_patch(arizona->regmap,
wm8998_rev_a_patch,
ARRAY_SIZE(wm8998_rev_a_patch));
}
static const struct regmap_irq wm8998_aod_irqs[ARIZONA_NUM_IRQ] = {
[ARIZONA_IRQ_MICD_CLAMP_FALL] = {
.mask = ARIZONA_MICD_CLAMP_FALL_EINT1
},
[ARIZONA_IRQ_MICD_CLAMP_RISE] = {
.mask = ARIZONA_MICD_CLAMP_RISE_EINT1
},
[ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 },
[ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 },
[ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 },
[ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 },
};
struct regmap_irq_chip wm8998_aod = {
.name = "wm8998 AOD",
.status_base = ARIZONA_AOD_IRQ1,
.mask_base = ARIZONA_AOD_IRQ_MASK_IRQ1,
.ack_base = ARIZONA_AOD_IRQ1,
.wake_base = ARIZONA_WAKE_CONTROL,
.wake_invert = 1,
.num_regs = 1,
.irqs = wm8998_aod_irqs,
.num_irqs = ARRAY_SIZE(wm8998_aod_irqs),
};
static const struct regmap_irq wm8998_irqs[ARIZONA_NUM_IRQ] = {
[ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
[ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
[ARIZONA_IRQ_SPK_OVERHEAT_WARN] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
},
[ARIZONA_IRQ_HPDET] = {
.reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
},
[ARIZONA_IRQ_MICDET] = {
.reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
},
[ARIZONA_IRQ_WSEQ_DONE] = {
.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
},
[ARIZONA_IRQ_DRC1_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
},
[ARIZONA_IRQ_ASRC2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1
},
[ARIZONA_IRQ_ASRC1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1
},
[ARIZONA_IRQ_UNDERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1
},
[ARIZONA_IRQ_OVERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1
},
[ARIZONA_IRQ_FLL2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
},
[ARIZONA_IRQ_FLL1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1
},
[ARIZONA_IRQ_ASRC_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1
},
[ARIZONA_IRQ_AIF3_ERR] = {
.reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1
},
[ARIZONA_IRQ_AIF2_ERR] = {
.reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1
},
[ARIZONA_IRQ_AIF1_ERR] = {
.reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1
},
[ARIZONA_IRQ_CTRLIF_ERR] = {
.reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1
},
[ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = {
.reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1
},
[ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_SYSCLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_ISRC1_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1
},
[ARIZONA_IRQ_ISRC2_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1
},
[ARIZONA_IRQ_BOOT_DONE] = {
.reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1
},
[ARIZONA_IRQ_FLL2_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1
},
[ARIZONA_IRQ_FLL1_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1
},
};
struct regmap_irq_chip wm8998_irq = {
.name = "wm8998 IRQ",
.status_base = ARIZONA_INTERRUPT_STATUS_1,
.mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK,
.ack_base = ARIZONA_INTERRUPT_STATUS_1,
.num_regs = 5,
.irqs = wm8998_irqs,
.num_irqs = ARRAY_SIZE(wm8998_irqs),
};
static const struct reg_default wm8998_reg_default[] = {
{ 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */
{ 0x0000000B, 0x001A }, /* R11 - Ctrl IF I2C1 CFG 2 */
{ 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */
{ 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */
{ 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */
{ 0x00000023, 0x1000 }, /* R35 - Tone Generator 4 */
{ 0x00000024, 0x0000 }, /* R36 - Tone Generator 5 */
{ 0x00000030, 0x0000 }, /* R48 - PWM Drive 1 */
{ 0x00000031, 0x0100 }, /* R49 - PWM Drive 2 */
{ 0x00000032, 0x0100 }, /* R50 - PWM Drive 3 */
{ 0x00000040, 0x0000 }, /* R64 - Wake control */
{ 0x00000041, 0x0000 }, /* R65 - Sequence control */
{ 0x00000061, 0x01FF }, /* R97 - Sample Rate Sequence Select 1 */
{ 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */
{ 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */
{ 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */
{ 0x00000066, 0x01FF }, /* R102 - Always On Triggers Sequence Select 1 */
{ 0x00000067, 0x01FF }, /* R103 - Always On Triggers Sequence Select 2 */
{ 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 3 */
{ 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 4 */
{ 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 5 */
{ 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 6 */
{ 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */
{ 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */
{ 0x00000092, 0x0000 }, /* R146 - Haptics phase 1 intensity */
{ 0x00000093, 0x0000 }, /* R147 - Haptics phase 1 duration */
{ 0x00000094, 0x0000 }, /* R148 - Haptics phase 2 intensity */
{ 0x00000095, 0x0000 }, /* R149 - Haptics phase 2 duration */
{ 0x00000096, 0x0000 }, /* R150 - Haptics phase 3 intensity */
{ 0x00000097, 0x0000 }, /* R151 - Haptics phase 3 duration */
{ 0x00000100, 0x0002 }, /* R256 - Clock 32k 1 */
{ 0x00000101, 0x0304 }, /* R257 - System Clock 1 */
{ 0x00000102, 0x0011 }, /* R258 - Sample rate 1 */
{ 0x00000103, 0x0011 }, /* R259 - Sample rate 2 */
{ 0x00000104, 0x0011 }, /* R260 - Sample rate 3 */
{ 0x00000112, 0x0305 }, /* R274 - Async clock 1 */
{ 0x00000113, 0x0011 }, /* R275 - Async sample rate 1 */
{ 0x00000114, 0x0011 }, /* R276 - Async sample rate 2 */
{ 0x00000149, 0x0000 }, /* R329 - Output system clock */
{ 0x0000014A, 0x0000 }, /* R330 - Output async clock */
{ 0x00000152, 0x0000 }, /* R338 - Rate Estimator 1 */
{ 0x00000153, 0x0000 }, /* R339 - Rate Estimator 2 */
{ 0x00000154, 0x0000 }, /* R340 - Rate Estimator 3 */
{ 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */
{ 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */
{ 0x00000161, 0x0000 }, /* R353 - Dynamic Frequency Scaling 1 */
{ 0x00000171, 0x0002 }, /* R369 - FLL1 Control 1 */
{ 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */
{ 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */
{ 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */
{ 0x00000175, 0x0004 }, /* R373 - FLL1 Control 5 */
{ 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */
{ 0x00000179, 0x0000 }, /* R377 - FLL1 Control 7 */
{ 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */
{ 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */
{ 0x00000183, 0x0000 }, /* R387 - FLL1 Synchroniser 3 */
{ 0x00000184, 0x0000 }, /* R388 - FLL1 Synchroniser 4 */
{ 0x00000185, 0x0000 }, /* R389 - FLL1 Synchroniser 5 */
{ 0x00000186, 0x0000 }, /* R390 - FLL1 Synchroniser 6 */
{ 0x00000187, 0x0001 }, /* R391 - FLL1 Synchroniser 7 */
{ 0x00000189, 0x0000 }, /* R393 - FLL1 Spread Spectrum */
{ 0x0000018A, 0x0004 }, /* R394 - FLL1 GPIO Clock */
{ 0x00000191, 0x0000 }, /* R401 - FLL2 Control 1 */
{ 0x00000192, 0x0008 }, /* R402 - FLL2 Control 2 */
{ 0x00000193, 0x0018 }, /* R403 - FLL2 Control 3 */
{ 0x00000194, 0x007D }, /* R404 - FLL2 Control 4 */
{ 0x00000195, 0x0004 }, /* R405 - FLL2 Control 5 */
{ 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */
{ 0x00000199, 0x0000 }, /* R409 - FLL2 Control 7 */
{ 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */
{ 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */
{ 0x000001A3, 0x0000 }, /* R419 - FLL2 Synchroniser 3 */
{ 0x000001A4, 0x0000 }, /* R420 - FLL2 Synchroniser 4 */
{ 0x000001A5, 0x0000 }, /* R421 - FLL2 Synchroniser 5 */
{ 0x000001A6, 0x0000 }, /* R422 - FLL2 Synchroniser 6 */
{ 0x000001A7, 0x0001 }, /* R423 - FLL2 Synchroniser 7 */
{ 0x000001A9, 0x0000 }, /* R425 - FLL2 Spread Spectrum */
{ 0x000001AA, 0x0004 }, /* R426 - FLL2 GPIO Clock */
{ 0x00000200, 0x0006 }, /* R512 - Mic Charge Pump 1 */
{ 0x00000210, 0x00D4 }, /* R528 - LDO1 Control 1 */
{ 0x00000212, 0x0000 }, /* R530 - LDO1 Control 2 */
{ 0x00000213, 0x0344 }, /* R531 - LDO2 Control 1 */
{ 0x00000218, 0x01A6 }, /* R536 - Mic Bias Ctrl 1 */
{ 0x00000219, 0x01A6 }, /* R537 - Mic Bias Ctrl 2 */
{ 0x0000021A, 0x01A6 }, /* R538 - Mic Bias Ctrl 3 */
{ 0x00000293, 0x0080 }, /* R659 - Accessory Detect Mode 1 */
{ 0x0000029B, 0x0000 }, /* R667 - Headphone Detect 1 */
{ 0x000002A2, 0x0000 }, /* R674 - Micd Clamp control */
{ 0x000002A3, 0x1102 }, /* R675 - Mic Detect 1 */
{ 0x000002A4, 0x009F }, /* R676 - Mic Detect 2 */
{ 0x000002A6, 0x3737 }, /* R678 - Mic Detect Level 1 */
{ 0x000002A7, 0x2C37 }, /* R679 - Mic Detect Level 2 */
{ 0x000002A8, 0x1422 }, /* R680 - Mic Detect Level 3 */
{ 0x000002A9, 0x030A }, /* R681 - Mic Detect Level 4 */
{ 0x000002CB, 0x0000 }, /* R715 - Isolation control */
{ 0x000002D3, 0x0000 }, /* R723 - Jack detect analogue */
{ 0x00000300, 0x0000 }, /* R768 - Input Enables */
{ 0x00000308, 0x0000 }, /* R776 - Input Rate */
{ 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */
{ 0x0000030C, 0x0002 }, /* R780 - HPF Control */
{ 0x00000310, 0x2080 }, /* R784 - IN1L Control */
{ 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */
{ 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */
{ 0x00000314, 0x0080 }, /* R788 - IN1R Control */
{ 0x00000315, 0x0180 }, /* R789 - ADC Digital Volume 1R */
{ 0x00000316, 0x0000 }, /* R790 - DMIC1R Control */
{ 0x00000318, 0x2080 }, /* R792 - IN2L Control */
{ 0x00000319, 0x0180 }, /* R793 - ADC Digital Volume 2L */
{ 0x0000031A, 0x0000 }, /* R794 - DMIC2L Control */
{ 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */
{ 0x00000408, 0x0000 }, /* R1032 - Output Rate 1 */
{ 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */
{ 0x00000410, 0x2080 }, /* R1040 - Output Path Config 1L */
{ 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */
{ 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */
{ 0x00000414, 0x0080 }, /* R1044 - Output Path Config 1R */
{ 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */
{ 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */
{ 0x00000418, 0x2080 }, /* R1048 - Output Path Config 2L */
{ 0x00000419, 0x0180 }, /* R1049 - DAC Digital Volume 2L */
{ 0x0000041B, 0x0004 }, /* R1051 - Noise Gate Select 2L */
{ 0x0000041C, 0x0080 }, /* R1052 - Output Path Config 2R */
{ 0x0000041D, 0x0180 }, /* R1053 - DAC Digital Volume 2R */
{ 0x0000041F, 0x0008 }, /* R1055 - Noise Gate Select 2R */
{ 0x00000420, 0x2080 }, /* R1056 - Output Path Config 3L */
{ 0x00000421, 0x0180 }, /* R1057 - DAC Digital Volume 3L */
{ 0x00000423, 0x0010 }, /* R1059 - Noise Gate Select 3L */
{ 0x00000428, 0x0000 }, /* R1064 - Output Path Config 4L */
{ 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */
{ 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */
{ 0x0000042C, 0x0000 }, /* R1068 - Output Path Config 4R */
{ 0x0000042D, 0x0180 }, /* R1069 - DAC Digital Volume 4R */
{ 0x0000042F, 0x0080 }, /* R1071 - Noise Gate Select 4R */
{ 0x00000430, 0x0000 }, /* R1072 - Output Path Config 5L */
{ 0x00000431, 0x0180 }, /* R1073 - DAC Digital Volume 5L */
{ 0x00000433, 0x0100 }, /* R1075 - Noise Gate Select 5L */
{ 0x00000434, 0x0000 }, /* R1076 - Output Path Config 5R */
{ 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */
{ 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */
{ 0x00000440, 0x002F }, /* R1088 - DRE Enable */
{ 0x00000441, 0xC759 }, /* R1089 - DRE Control 1 */
{ 0x00000442, 0x2A08 }, /* R1089 - DRE Control 2 */
{ 0x00000443, 0x5CFA }, /* R1089 - DRE Control 3 */
{ 0x00000448, 0x03EF }, /* R1096 - EDRE Enable */
{ 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */
{ 0x00000451, 0x0000 }, /* R1105 - DAC AEC Control 2 */
{ 0x00000458, 0x0000 }, /* R1112 - Noise Gate Control */
{ 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */
{ 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */
{ 0x0000049A, 0x0000 }, /* R1178 - HP_TEST_CTRL_13 */
{ 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */
{ 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */
{ 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */
{ 0x00000503, 0x0000 }, /* R1283 - AIF1 Rate Ctrl */
{ 0x00000504, 0x0000 }, /* R1284 - AIF1 Format */
{ 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */
{ 0x00000507, 0x1818 }, /* R1287 - AIF1 Frame Ctrl 1 */
{ 0x00000508, 0x1818 }, /* R1288 - AIF1 Frame Ctrl 2 */
{ 0x00000509, 0x0000 }, /* R1289 - AIF1 Frame Ctrl 3 */
{ 0x0000050A, 0x0001 }, /* R1290 - AIF1 Frame Ctrl 4 */
{ 0x0000050B, 0x0002 }, /* R1291 - AIF1 Frame Ctrl 5 */
{ 0x0000050C, 0x0003 }, /* R1292 - AIF1 Frame Ctrl 6 */
{ 0x0000050D, 0x0004 }, /* R1293 - AIF1 Frame Ctrl 7 */
{ 0x0000050E, 0x0005 }, /* R1294 - AIF1 Frame Ctrl 8 */
{ 0x00000511, 0x0000 }, /* R1297 - AIF1 Frame Ctrl 11 */
{ 0x00000512, 0x0001 }, /* R1298 - AIF1 Frame Ctrl 12 */
{ 0x00000513, 0x0002 }, /* R1299 - AIF1 Frame Ctrl 13 */
{ 0x00000514, 0x0003 }, /* R1300 - AIF1 Frame Ctrl 14 */
{ 0x00000515, 0x0004 }, /* R1301 - AIF1 Frame Ctrl 15 */
{ 0x00000516, 0x0005 }, /* R1302 - AIF1 Frame Ctrl 16 */
{ 0x00000519, 0x0000 }, /* R1305 - AIF1 Tx Enables */
{ 0x0000051A, 0x0000 }, /* R1306 - AIF1 Rx Enables */
{ 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */
{ 0x00000541, 0x0008 }, /* R1345 - AIF2 Tx Pin Ctrl */
{ 0x00000542, 0x0000 }, /* R1346 - AIF2 Rx Pin Ctrl */
{ 0x00000543, 0x0000 }, /* R1347 - AIF2 Rate Ctrl */
{ 0x00000544, 0x0000 }, /* R1348 - AIF2 Format */
{ 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */
{ 0x00000547, 0x1818 }, /* R1351 - AIF2 Frame Ctrl 1 */
{ 0x00000548, 0x1818 }, /* R1352 - AIF2 Frame Ctrl 2 */
{ 0x00000549, 0x0000 }, /* R1353 - AIF2 Frame Ctrl 3 */
{ 0x0000054A, 0x0001 }, /* R1354 - AIF2 Frame Ctrl 4 */
{ 0x0000054B, 0x0002 }, /* R1355 - AIF2 Frame Ctrl 5 */
{ 0x0000054C, 0x0003 }, /* R1356 - AIF2 Frame Ctrl 6 */
{ 0x0000054D, 0x0004 }, /* R1357 - AIF2 Frame Ctrl 7 */
{ 0x0000054E, 0x0005 }, /* R1358 - AIF2 Frame Ctrl 8 */
{ 0x00000551, 0x0000 }, /* R1361 - AIF2 Frame Ctrl 11 */
{ 0x00000552, 0x0001 }, /* R1362 - AIF2 Frame Ctrl 12 */
{ 0x00000553, 0x0002 }, /* R1363 - AIF2 Frame Ctrl 13 */
{ 0x00000554, 0x0003 }, /* R1364 - AIF2 Frame Ctrl 14 */
{ 0x00000555, 0x0004 }, /* R1365 - AIF2 Frame Ctrl 15 */
{ 0x00000556, 0x0005 }, /* R1366 - AIF2 Frame Ctrl 16 */
{ 0x00000559, 0x0000 }, /* R1369 - AIF2 Tx Enables */
{ 0x0000055A, 0x0000 }, /* R1370 - AIF2 Rx Enables */
{ 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */
{ 0x00000581, 0x0008 }, /* R1409 - AIF3 Tx Pin Ctrl */
{ 0x00000582, 0x0000 }, /* R1410 - AIF3 Rx Pin Ctrl */
{ 0x00000583, 0x0000 }, /* R1411 - AIF3 Rate Ctrl */
{ 0x00000584, 0x0000 }, /* R1412 - AIF3 Format */
{ 0x00000586, 0x0040 }, /* R1414 - AIF3 Rx BCLK Rate */
{ 0x00000587, 0x1818 }, /* R1415 - AIF3 Frame Ctrl 1 */
{ 0x00000588, 0x1818 }, /* R1416 - AIF3 Frame Ctrl 2 */
{ 0x00000589, 0x0000 }, /* R1417 - AIF3 Frame Ctrl 3 */
{ 0x0000058A, 0x0001 }, /* R1418 - AIF3 Frame Ctrl 4 */
{ 0x00000591, 0x0000 }, /* R1425 - AIF3 Frame Ctrl 11 */
{ 0x00000592, 0x0001 }, /* R1426 - AIF3 Frame Ctrl 12 */
{ 0x00000599, 0x0000 }, /* R1433 - AIF3 Tx Enables */
{ 0x0000059A, 0x0000 }, /* R1434 - AIF3 Rx Enables */
{ 0x000005C2, 0x0000 }, /* R1474 - SPD1 TX Control */
{ 0x000005C3, 0x0000 }, /* R1475 - SPD1 TX Channel Status 1 */
{ 0x000005C4, 0x0B01 }, /* R1476 - SPD1 TX Channel Status 2 */
{ 0x000005C5, 0x0000 }, /* R1477 - SPD1 TX Channel Status 3 */
{ 0x000005E3, 0x0004 }, /* R1507 - SLIMbus Framer Ref Gear */
{ 0x000005E5, 0x0000 }, /* R1509 - SLIMbus Rates 1 */
{ 0x000005E6, 0x0000 }, /* R1510 - SLIMbus Rates 2 */
{ 0x000005E9, 0x0000 }, /* R1513 - SLIMbus Rates 5 */
{ 0x000005EA, 0x0000 }, /* R1514 - SLIMbus Rates 6 */
{ 0x000005EB, 0x0000 }, /* R1515 - SLIMbus Rates 7 */
{ 0x000005F5, 0x0000 }, /* R1525 - SLIMbus RX Channel Enable */
{ 0x000005F6, 0x0000 }, /* R1526 - SLIMbus TX Channel Enable */
{ 0x00000640, 0x0000 }, /* R1600 - PWM1MIX Input 1 Source */
{ 0x00000641, 0x0080 }, /* R1601 - PWM1MIX Input 1 Volume */
{ 0x00000642, 0x0000 }, /* R1602 - PWM1MIX Input 2 Source */
{ 0x00000643, 0x0080 }, /* R1603 - PWM1MIX Input 2 Volume */
{ 0x00000644, 0x0000 }, /* R1604 - PWM1MIX Input 3 Source */
{ 0x00000645, 0x0080 }, /* R1605 - PWM1MIX Input 3 Volume */
{ 0x00000646, 0x0000 }, /* R1606 - PWM1MIX Input 4 Source */
{ 0x00000647, 0x0080 }, /* R1607 - PWM1MIX Input 4 Volume */
{ 0x00000648, 0x0000 }, /* R1608 - PWM2MIX Input 1 Source */
{ 0x00000649, 0x0080 }, /* R1609 - PWM2MIX Input 1 Volume */
{ 0x0000064A, 0x0000 }, /* R1610 - PWM2MIX Input 2 Source */
{ 0x0000064B, 0x0080 }, /* R1611 - PWM2MIX Input 2 Volume */
{ 0x0000064C, 0x0000 }, /* R1612 - PWM2MIX Input 3 Source */
{ 0x0000064D, 0x0080 }, /* R1613 - PWM2MIX Input 3 Volume */
{ 0x0000064E, 0x0000 }, /* R1614 - PWM2MIX Input 4 Source */
{ 0x0000064F, 0x0080 }, /* R1615 - PWM2MIX Input 4 Volume */
{ 0x00000680, 0x0000 }, /* R1664 - OUT1LMIX Input 1 Source */
{ 0x00000681, 0x0080 }, /* R1665 - OUT1LMIX Input 1 Volume */
{ 0x00000682, 0x0000 }, /* R1666 - OUT1LMIX Input 2 Source */
{ 0x00000683, 0x0080 }, /* R1667 - OUT1LMIX Input 2 Volume */
{ 0x00000684, 0x0000 }, /* R1668 - OUT1LMIX Input 3 Source */
{ 0x00000685, 0x0080 }, /* R1669 - OUT1LMIX Input 3 Volume */
{ 0x00000686, 0x0000 }, /* R1670 - OUT1LMIX Input 4 Source */
{ 0x00000687, 0x0080 }, /* R1671 - OUT1LMIX Input 4 Volume */
{ 0x00000688, 0x0000 }, /* R1672 - OUT1RMIX Input 1 Source */
{ 0x00000689, 0x0080 }, /* R1673 - OUT1RMIX Input 1 Volume */
{ 0x0000068A, 0x0000 }, /* R1674 - OUT1RMIX Input 2 Source */
{ 0x0000068B, 0x0080 }, /* R1675 - OUT1RMIX Input 2 Volume */
{ 0x0000068C, 0x0000 }, /* R1676 - OUT1RMIX Input 3 Source */
{ 0x0000068D, 0x0080 }, /* R1677 - OUT1RMIX Input 3 Volume */
{ 0x0000068E, 0x0000 }, /* R1678 - OUT1RMIX Input 4 Source */
{ 0x0000068F, 0x0080 }, /* R1679 - OUT1RMIX Input 4 Volume */
{ 0x00000690, 0x0000 }, /* R1680 - OUT2LMIX Input 1 Source */
{ 0x00000691, 0x0080 }, /* R1681 - OUT2LMIX Input 1 Volume */
{ 0x00000692, 0x0000 }, /* R1682 - OUT2LMIX Input 2 Source */
{ 0x00000693, 0x0080 }, /* R1683 - OUT2LMIX Input 2 Volume */
{ 0x00000694, 0x0000 }, /* R1684 - OUT2LMIX Input 3 Source */
{ 0x00000695, 0x0080 }, /* R1685 - OUT2LMIX Input 3 Volume */
{ 0x00000696, 0x0000 }, /* R1686 - OUT2LMIX Input 4 Source */
{ 0x00000697, 0x0080 }, /* R1687 - OUT2LMIX Input 4 Volume */
{ 0x00000698, 0x0000 }, /* R1688 - OUT2RMIX Input 1 Source */
{ 0x00000699, 0x0080 }, /* R1689 - OUT2RMIX Input 1 Volume */
{ 0x0000069A, 0x0000 }, /* R1690 - OUT2RMIX Input 2 Source */
{ 0x0000069B, 0x0080 }, /* R1691 - OUT2RMIX Input 2 Volume */
{ 0x0000069C, 0x0000 }, /* R1692 - OUT2RMIX Input 3 Source */
{ 0x0000069D, 0x0080 }, /* R1693 - OUT2RMIX Input 3 Volume */
{ 0x0000069E, 0x0000 }, /* R1694 - OUT2RMIX Input 4 Source */
{ 0x0000069F, 0x0080 }, /* R1695 - OUT2RMIX Input 4 Volume */
{ 0x000006A0, 0x0000 }, /* R1696 - OUT3LMIX Input 1 Source */
{ 0x000006A1, 0x0080 }, /* R1697 - OUT3LMIX Input 1 Volume */
{ 0x000006A2, 0x0000 }, /* R1698 - OUT3LMIX Input 2 Source */
{ 0x000006A3, 0x0080 }, /* R1699 - OUT3LMIX Input 2 Volume */
{ 0x000006A4, 0x0000 }, /* R1700 - OUT3LMIX Input 3 Source */
{ 0x000006A5, 0x0080 }, /* R1701 - OUT3LMIX Input 3 Volume */
{ 0x000006A6, 0x0000 }, /* R1702 - OUT3LMIX Input 4 Source */
{ 0x000006A7, 0x0080 }, /* R1703 - OUT3LMIX Input 4 Volume */
{ 0x000006B0, 0x0000 }, /* R1712 - OUT4LMIX Input 1 Source */
{ 0x000006B1, 0x0080 }, /* R1713 - OUT4LMIX Input 1 Volume */
{ 0x000006B2, 0x0000 }, /* R1714 - OUT4LMIX Input 2 Source */
{ 0x000006B3, 0x0080 }, /* R1715 - OUT4LMIX Input 2 Volume */
{ 0x000006B4, 0x0000 }, /* R1716 - OUT4LMIX Input 3 Source */
{ 0x000006B5, 0x0080 }, /* R1717 - OUT4LMIX Input 3 Volume */
{ 0x000006B6, 0x0000 }, /* R1718 - OUT4LMIX Input 4 Source */
{ 0x000006B7, 0x0080 }, /* R1719 - OUT4LMIX Input 4 Volume */
{ 0x000006B8, 0x0000 }, /* R1720 - OUT4RMIX Input 1 Source */
{ 0x000006B9, 0x0080 }, /* R1721 - OUT4RMIX Input 1 Volume */
{ 0x000006BA, 0x0000 }, /* R1722 - OUT4RMIX Input 2 Source */
{ 0x000006BB, 0x0080 }, /* R1723 - OUT4RMIX Input 2 Volume */
{ 0x000006BC, 0x0000 }, /* R1724 - OUT4RMIX Input 3 Source */
{ 0x000006BD, 0x0080 }, /* R1725 - OUT4RMIX Input 3 Volume */
{ 0x000006BE, 0x0000 }, /* R1726 - OUT4RMIX Input 4 Source */
{ 0x000006BF, 0x0080 }, /* R1727 - OUT4RMIX Input 4 Volume */
{ 0x000006C0, 0x0000 }, /* R1728 - OUT5LMIX Input 1 Source */
{ 0x000006C1, 0x0080 }, /* R1729 - OUT5LMIX Input 1 Volume */
{ 0x000006C2, 0x0000 }, /* R1730 - OUT5LMIX Input 2 Source */
{ 0x000006C3, 0x0080 }, /* R1731 - OUT5LMIX Input 2 Volume */
{ 0x000006C4, 0x0000 }, /* R1732 - OUT5LMIX Input 3 Source */
{ 0x000006C5, 0x0080 }, /* R1733 - OUT5LMIX Input 3 Volume */
{ 0x000006C6, 0x0000 }, /* R1734 - OUT5LMIX Input 4 Source */
{ 0x000006C7, 0x0080 }, /* R1735 - OUT5LMIX Input 4 Volume */
{ 0x000006C8, 0x0000 }, /* R1736 - OUT5RMIX Input 1 Source */
{ 0x000006C9, 0x0080 }, /* R1737 - OUT5RMIX Input 1 Volume */
{ 0x000006CA, 0x0000 }, /* R1738 - OUT5RMIX Input 2 Source */
{ 0x000006CB, 0x0080 }, /* R1739 - OUT5RMIX Input 2 Volume */
{ 0x000006CC, 0x0000 }, /* R1740 - OUT5RMIX Input 3 Source */
{ 0x000006CD, 0x0080 }, /* R1741 - OUT5RMIX Input 3 Volume */
{ 0x000006CE, 0x0000 }, /* R1742 - OUT5RMIX Input 4 Source */
{ 0x000006CF, 0x0080 }, /* R1743 - OUT5RMIX Input 4 Volume */
{ 0x00000700, 0x0000 }, /* R1792 - AIF1TX1MIX Input 1 Source */
{ 0x00000701, 0x0080 }, /* R1793 - AIF1TX1MIX Input 1 Volume */
{ 0x00000702, 0x0000 }, /* R1794 - AIF1TX1MIX Input 2 Source */
{ 0x00000703, 0x0080 }, /* R1795 - AIF1TX1MIX Input 2 Volume */
{ 0x00000704, 0x0000 }, /* R1796 - AIF1TX1MIX Input 3 Source */
{ 0x00000705, 0x0080 }, /* R1797 - AIF1TX1MIX Input 3 Volume */
{ 0x00000706, 0x0000 }, /* R1798 - AIF1TX1MIX Input 4 Source */
{ 0x00000707, 0x0080 }, /* R1799 - AIF1TX1MIX Input 4 Volume */
{ 0x00000708, 0x0000 }, /* R1800 - AIF1TX2MIX Input 1 Source */
{ 0x00000709, 0x0080 }, /* R1801 - AIF1TX2MIX Input 1 Volume */
{ 0x0000070A, 0x0000 }, /* R1802 - AIF1TX2MIX Input 2 Source */
{ 0x0000070B, 0x0080 }, /* R1803 - AIF1TX2MIX Input 2 Volume */
{ 0x0000070C, 0x0000 }, /* R1804 - AIF1TX2MIX Input 3 Source */
{ 0x0000070D, 0x0080 }, /* R1805 - AIF1TX2MIX Input 3 Volume */
{ 0x0000070E, 0x0000 }, /* R1806 - AIF1TX2MIX Input 4 Source */
{ 0x0000070F, 0x0080 }, /* R1807 - AIF1TX2MIX Input 4 Volume */
{ 0x00000710, 0x0000 }, /* R1808 - AIF1TX3MIX Input 1 Source */
{ 0x00000711, 0x0080 }, /* R1809 - AIF1TX3MIX Input 1 Volume */
{ 0x00000712, 0x0000 }, /* R1810 - AIF1TX3MIX Input 2 Source */
{ 0x00000713, 0x0080 }, /* R1811 - AIF1TX3MIX Input 2 Volume */
{ 0x00000714, 0x0000 }, /* R1812 - AIF1TX3MIX Input 3 Source */
{ 0x00000715, 0x0080 }, /* R1813 - AIF1TX3MIX Input 3 Volume */
{ 0x00000716, 0x0000 }, /* R1814 - AIF1TX3MIX Input 4 Source */
{ 0x00000717, 0x0080 }, /* R1815 - AIF1TX3MIX Input 4 Volume */
{ 0x00000718, 0x0000 }, /* R1816 - AIF1TX4MIX Input 1 Source */
{ 0x00000719, 0x0080 }, /* R1817 - AIF1TX4MIX Input 1 Volume */
{ 0x0000071A, 0x0000 }, /* R1818 - AIF1TX4MIX Input 2 Source */
{ 0x0000071B, 0x0080 }, /* R1819 - AIF1TX4MIX Input 2 Volume */
{ 0x0000071C, 0x0000 }, /* R1820 - AIF1TX4MIX Input 3 Source */
{ 0x0000071D, 0x0080 }, /* R1821 - AIF1TX4MIX Input 3 Volume */
{ 0x0000071E, 0x0000 }, /* R1822 - AIF1TX4MIX Input 4 Source */
{ 0x0000071F, 0x0080 }, /* R1823 - AIF1TX4MIX Input 4 Volume */
{ 0x00000720, 0x0000 }, /* R1824 - AIF1TX5MIX Input 1 Source */
{ 0x00000721, 0x0080 }, /* R1825 - AIF1TX5MIX Input 1 Volume */
{ 0x00000722, 0x0000 }, /* R1826 - AIF1TX5MIX Input 2 Source */
{ 0x00000723, 0x0080 }, /* R1827 - AIF1TX5MIX Input 2 Volume */
{ 0x00000724, 0x0000 }, /* R1828 - AIF1TX5MIX Input 3 Source */
{ 0x00000725, 0x0080 }, /* R1829 - AIF1TX5MIX Input 3 Volume */
{ 0x00000726, 0x0000 }, /* R1830 - AIF1TX5MIX Input 4 Source */
{ 0x00000727, 0x0080 }, /* R1831 - AIF1TX5MIX Input 4 Volume */
{ 0x00000728, 0x0000 }, /* R1832 - AIF1TX6MIX Input 1 Source */
{ 0x00000729, 0x0080 }, /* R1833 - AIF1TX6MIX Input 1 Volume */
{ 0x0000072A, 0x0000 }, /* R1834 - AIF1TX6MIX Input 2 Source */
{ 0x0000072B, 0x0080 }, /* R1835 - AIF1TX6MIX Input 2 Volume */
{ 0x0000072C, 0x0000 }, /* R1836 - AIF1TX6MIX Input 3 Source */
{ 0x0000072D, 0x0080 }, /* R1837 - AIF1TX6MIX Input 3 Volume */
{ 0x0000072E, 0x0000 }, /* R1838 - AIF1TX6MIX Input 4 Source */
{ 0x0000072F, 0x0080 }, /* R1839 - AIF1TX6MIX Input 4 Volume */
{ 0x00000740, 0x0000 }, /* R1856 - AIF2TX1MIX Input 1 Source */
{ 0x00000741, 0x0080 }, /* R1857 - AIF2TX1MIX Input 1 Volume */
{ 0x00000742, 0x0000 }, /* R1858 - AIF2TX1MIX Input 2 Source */
{ 0x00000743, 0x0080 }, /* R1859 - AIF2TX1MIX Input 2 Volume */
{ 0x00000744, 0x0000 }, /* R1860 - AIF2TX1MIX Input 3 Source */
{ 0x00000745, 0x0080 }, /* R1861 - AIF2TX1MIX Input 3 Volume */
{ 0x00000746, 0x0000 }, /* R1862 - AIF2TX1MIX Input 4 Source */
{ 0x00000747, 0x0080 }, /* R1863 - AIF2TX1MIX Input 4 Volume */
{ 0x00000748, 0x0000 }, /* R1864 - AIF2TX2MIX Input 1 Source */
{ 0x00000749, 0x0080 }, /* R1865 - AIF2TX2MIX Input 1 Volume */
{ 0x0000074A, 0x0000 }, /* R1866 - AIF2TX2MIX Input 2 Source */
{ 0x0000074B, 0x0080 }, /* R1867 - AIF2TX2MIX Input 2 Volume */
{ 0x0000074C, 0x0000 }, /* R1868 - AIF2TX2MIX Input 3 Source */
{ 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */
{ 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */
{ 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */
{ 0x00000750, 0x0000 }, /* R1872 - AIF2TX3MIX Input 1 Source */
{ 0x00000751, 0x0080 }, /* R1873 - AIF2TX3MIX Input 1 Volume */
{ 0x00000752, 0x0000 }, /* R1874 - AIF2TX3MIX Input 2 Source */
{ 0x00000753, 0x0080 }, /* R1875 - AIF2TX3MIX Input 2 Volume */
{ 0x00000754, 0x0000 }, /* R1876 - AIF2TX3MIX Input 3 Source */
{ 0x00000755, 0x0080 }, /* R1877 - AIF2TX3MIX Input 3 Volume */
{ 0x00000756, 0x0000 }, /* R1878 - AIF2TX3MIX Input 4 Source */
{ 0x00000757, 0x0080 }, /* R1879 - AIF2TX3MIX Input 4 Volume */
{ 0x00000758, 0x0000 }, /* R1880 - AIF2TX4MIX Input 1 Source */
{ 0x00000759, 0x0080 }, /* R1881 - AIF2TX4MIX Input 1 Volume */
{ 0x0000075A, 0x0000 }, /* R1882 - AIF2TX4MIX Input 2 Source */
{ 0x0000075B, 0x0080 }, /* R1883 - AIF2TX4MIX Input 2 Volume */
{ 0x0000075C, 0x0000 }, /* R1884 - AIF2TX4MIX Input 3 Source */
{ 0x0000075D, 0x0080 }, /* R1885 - AIF2TX4MIX Input 3 Volume */
{ 0x0000075E, 0x0000 }, /* R1886 - AIF2TX4MIX Input 4 Source */
{ 0x0000075F, 0x0080 }, /* R1887 - AIF2TX4MIX Input 4 Volume */
{ 0x00000760, 0x0000 }, /* R1888 - AIF2TX5MIX Input 1 Source */
{ 0x00000761, 0x0080 }, /* R1889 - AIF2TX5MIX Input 1 Volume */
{ 0x00000762, 0x0000 }, /* R1890 - AIF2TX5MIX Input 2 Source */
{ 0x00000763, 0x0080 }, /* R1891 - AIF2TX5MIX Input 2 Volume */
{ 0x00000764, 0x0000 }, /* R1892 - AIF2TX5MIX Input 3 Source */
{ 0x00000765, 0x0080 }, /* R1893 - AIF2TX5MIX Input 3 Volume */
{ 0x00000766, 0x0000 }, /* R1894 - AIF2TX5MIX Input 4 Source */
{ 0x00000767, 0x0080 }, /* R1895 - AIF2TX5MIX Input 4 Volume */
{ 0x00000768, 0x0000 }, /* R1896 - AIF2TX6MIX Input 1 Source */
{ 0x00000769, 0x0080 }, /* R1897 - AIF2TX6MIX Input 1 Volume */
{ 0x0000076A, 0x0000 }, /* R1898 - AIF2TX6MIX Input 2 Source */
{ 0x0000076B, 0x0080 }, /* R1899 - AIF2TX6MIX Input 2 Volume */
{ 0x0000076C, 0x0000 }, /* R1900 - AIF2TX6MIX Input 3 Source */
{ 0x0000076D, 0x0080 }, /* R1901 - AIF2TX6MIX Input 3 Volume */
{ 0x0000076E, 0x0000 }, /* R1902 - AIF2TX6MIX Input 4 Source */
{ 0x0000076F, 0x0080 }, /* R1903 - AIF2TX6MIX Input 4 Volume */
{ 0x00000780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */
{ 0x00000781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */
{ 0x00000782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */
{ 0x00000783, 0x0080 }, /* R1923 - AIF3TX1MIX Input 2 Volume */
{ 0x00000784, 0x0000 }, /* R1924 - AIF3TX1MIX Input 3 Source */
{ 0x00000785, 0x0080 }, /* R1925 - AIF3TX1MIX Input 3 Volume */
{ 0x00000786, 0x0000 }, /* R1926 - AIF3TX1MIX Input 4 Source */
{ 0x00000787, 0x0080 }, /* R1927 - AIF3TX1MIX Input 4 Volume */
{ 0x00000788, 0x0000 }, /* R1928 - AIF3TX2MIX Input 1 Source */
{ 0x00000789, 0x0080 }, /* R1929 - AIF3TX2MIX Input 1 Volume */
{ 0x0000078A, 0x0000 }, /* R1930 - AIF3TX2MIX Input 2 Source */
{ 0x0000078B, 0x0080 }, /* R1931 - AIF3TX2MIX Input 2 Volume */
{ 0x0000078C, 0x0000 }, /* R1932 - AIF3TX2MIX Input 3 Source */
{ 0x0000078D, 0x0080 }, /* R1933 - AIF3TX2MIX Input 3 Volume */
{ 0x0000078E, 0x0000 }, /* R1934 - AIF3TX2MIX Input 4 Source */
{ 0x0000078F, 0x0080 }, /* R1935 - AIF3TX2MIX Input 4 Volume */
{ 0x000007C0, 0x0000 }, /* R1984 - SLIMTX1MIX Input 1 Source */
{ 0x000007C1, 0x0080 }, /* R1985 - SLIMTX1MIX Input 1 Volume */
{ 0x000007C8, 0x0000 }, /* R1992 - SLIMTX2MIX Input 1 Source */
{ 0x000007C9, 0x0080 }, /* R1993 - SLIMTX2MIX Input 1 Volume */
{ 0x000007D0, 0x0000 }, /* R2000 - SLIMTX3MIX Input 1 Source */
{ 0x000007D1, 0x0080 }, /* R2001 - SLIMTX3MIX Input 1 Volume */
{ 0x000007D8, 0x0000 }, /* R2008 - SLIMTX4MIX Input 1 Source */
{ 0x000007D9, 0x0080 }, /* R2009 - SLIMTX4MIX Input 1 Volume */
{ 0x000007E0, 0x0000 }, /* R2016 - SLIMTX5MIX Input 1 Source */
{ 0x000007E1, 0x0080 }, /* R2017 - SLIMTX5MIX Input 1 Volume */
{ 0x000007E8, 0x0000 }, /* R2024 - SLIMTX6MIX Input 1 Source */
{ 0x000007E9, 0x0080 }, /* R2025 - SLIMTX6MIX Input 1 Volume */
{ 0x00000800, 0x0000 }, /* R2048 - SPDIF1TX1MIX Input 1 Source */
{ 0x00000801, 0x0080 }, /* R2049 - SPDIF1TX1MIX Input 1 Volume */
{ 0x00000808, 0x0000 }, /* R2056 - SPDIF1TX2MIX Input 1 Source */
{ 0x00000809, 0x0080 }, /* R2057 - SPDIF1TX2MIX Input 1 Volume */
{ 0x00000880, 0x0000 }, /* R2176 - EQ1MIX Input 1 Source */
{ 0x00000881, 0x0080 }, /* R2177 - EQ1MIX Input 1 Volume */
{ 0x00000888, 0x0000 }, /* R2184 - EQ2MIX Input 1 Source */
{ 0x00000889, 0x0080 }, /* R2185 - EQ2MIX Input 1 Volume */
{ 0x00000890, 0x0000 }, /* R2192 - EQ3MIX Input 1 Source */
{ 0x00000891, 0x0080 }, /* R2193 - EQ3MIX Input 1 Volume */
{ 0x00000898, 0x0000 }, /* R2200 - EQ4MIX Input 1 Source */
{ 0x00000899, 0x0080 }, /* R2201 - EQ4MIX Input 1 Volume */
{ 0x000008C0, 0x0000 }, /* R2240 - DRC1LMIX Input 1 Source */
{ 0x000008C1, 0x0080 }, /* R2241 - DRC1LMIX Input 1 Volume */
{ 0x000008C8, 0x0000 }, /* R2248 - DRC1RMIX Input 1 Source */
{ 0x000008C9, 0x0080 }, /* R2249 - DRC1RMIX Input 1 Volume */
{ 0x00000900, 0x0000 }, /* R2304 - HPLP1MIX Input 1 Source */
{ 0x00000901, 0x0080 }, /* R2305 - HPLP1MIX Input 1 Volume */
{ 0x00000902, 0x0000 }, /* R2306 - HPLP1MIX Input 2 Source */
{ 0x00000903, 0x0080 }, /* R2307 - HPLP1MIX Input 2 Volume */
{ 0x00000904, 0x0000 }, /* R2308 - HPLP1MIX Input 3 Source */
{ 0x00000905, 0x0080 }, /* R2309 - HPLP1MIX Input 3 Volume */
{ 0x00000906, 0x0000 }, /* R2310 - HPLP1MIX Input 4 Source */
{ 0x00000907, 0x0080 }, /* R2311 - HPLP1MIX Input 4 Volume */
{ 0x00000908, 0x0000 }, /* R2312 - HPLP2MIX Input 1 Source */
{ 0x00000909, 0x0080 }, /* R2313 - HPLP2MIX Input 1 Volume */
{ 0x0000090A, 0x0000 }, /* R2314 - HPLP2MIX Input 2 Source */
{ 0x0000090B, 0x0080 }, /* R2315 - HPLP2MIX Input 2 Volume */
{ 0x0000090C, 0x0000 }, /* R2316 - HPLP2MIX Input 3 Source */
{ 0x0000090D, 0x0080 }, /* R2317 - HPLP2MIX Input 3 Volume */
{ 0x0000090E, 0x0000 }, /* R2318 - HPLP2MIX Input 4 Source */
{ 0x0000090F, 0x0080 }, /* R2319 - HPLP2MIX Input 4 Volume */
{ 0x00000910, 0x0000 }, /* R2320 - HPLP3MIX Input 1 Source */
{ 0x00000911, 0x0080 }, /* R2321 - HPLP3MIX Input 1 Volume */
{ 0x00000912, 0x0000 }, /* R2322 - HPLP3MIX Input 2 Source */
{ 0x00000913, 0x0080 }, /* R2323 - HPLP3MIX Input 2 Volume */
{ 0x00000914, 0x0000 }, /* R2324 - HPLP3MIX Input 3 Source */
{ 0x00000915, 0x0080 }, /* R2325 - HPLP3MIX Input 3 Volume */
{ 0x00000916, 0x0000 }, /* R2326 - HPLP3MIX Input 4 Source */
{ 0x00000917, 0x0080 }, /* R2327 - HPLP3MIX Input 4 Volume */
{ 0x00000918, 0x0000 }, /* R2328 - HPLP4MIX Input 1 Source */
{ 0x00000919, 0x0080 }, /* R2329 - HPLP4MIX Input 1 Volume */
{ 0x0000091A, 0x0000 }, /* R2330 - HPLP4MIX Input 2 Source */
{ 0x0000091B, 0x0080 }, /* R2331 - HPLP4MIX Input 2 Volume */
{ 0x0000091C, 0x0000 }, /* R2332 - HPLP4MIX Input 3 Source */
{ 0x0000091D, 0x0080 }, /* R2333 - HPLP4MIX Input 3 Volume */
{ 0x0000091E, 0x0000 }, /* R2334 - HPLP4MIX Input 4 Source */
{ 0x0000091F, 0x0080 }, /* R2335 - HPLP4MIX Input 4 Volume */
{ 0x00000A80, 0x0000 }, /* R2688 - ASRC1LMIX Input 1 Source */
{ 0x00000A88, 0x0000 }, /* R2696 - ASRC1RMIX Input 1 Source */
{ 0x00000A90, 0x0000 }, /* R2704 - ASRC2LMIX Input 1 Source */
{ 0x00000A98, 0x0000 }, /* R2712 - ASRC2RMIX Input 1 Source */
{ 0x00000B00, 0x0000 }, /* R2816 - ISRC1DEC1MIX Input 1 Source */
{ 0x00000B08, 0x0000 }, /* R2824 - ISRC1DEC2MIX Input 1 Source */
{ 0x00000B10, 0x0000 }, /* R2832 - ISRC1DEC3MIX Input 1 Source */
{ 0x00000B18, 0x0000 }, /* R2840 - ISRC1DEC4MIX Input 1 Source */
{ 0x00000B20, 0x0000 }, /* R2848 - ISRC1INT1MIX Input 1 Source */
{ 0x00000B28, 0x0000 }, /* R2856 - ISRC1INT2MIX Input 1 Source */
{ 0x00000B30, 0x0000 }, /* R2864 - ISRC1INT3MIX Input 1 Source */
{ 0x00000B38, 0x0000 }, /* R2872 - ISRC1INT4MIX Input 1 Source */
{ 0x00000B40, 0x0000 }, /* R2880 - ISRC2DEC1MIX Input 1 Source */
{ 0x00000B48, 0x0000 }, /* R2888 - ISRC2DEC2MIX Input 1 Source */
{ 0x00000B60, 0x0000 }, /* R2912 - ISRC2INT1MIX Input 1 Source */
{ 0x00000B68, 0x0000 }, /* R2920 - ISRC2INT2MIX Input 1 Source */
{ 0x00000C00, 0xA101 }, /* R3072 - GPIO1 CTRL */
{ 0x00000C01, 0xA101 }, /* R3073 - GPIO2 CTRL */
{ 0x00000C02, 0xA101 }, /* R3074 - GPIO3 CTRL */
{ 0x00000C03, 0xA101 }, /* R3075 - GPIO4 CTRL */
{ 0x00000C04, 0xA101 }, /* R3076 - GPIO5 CTRL */
{ 0x00000C0F, 0x0400 }, /* R3087 - IRQ CTRL 1 */
{ 0x00000C10, 0x1000 }, /* R3088 - GPIO Debounce Config */
{ 0x00000C18, 0x0000 }, /* R3096 - GP Switch 1 */
{ 0x00000C20, 0x8002 }, /* R3104 - Misc Pad Ctrl 1 */
{ 0x00000C21, 0x0001 }, /* R3105 - Misc Pad Ctrl 2 */
{ 0x00000C22, 0x0000 }, /* R3106 - Misc Pad Ctrl 3 */
{ 0x00000C23, 0x0000 }, /* R3107 - Misc Pad Ctrl 4 */
{ 0x00000C24, 0x0000 }, /* R3108 - Misc Pad Ctrl 5 */
{ 0x00000C25, 0x0000 }, /* R3109 - Misc Pad Ctrl 6 */
{ 0x00000D08, 0xFFFF }, /* R3336 - Interrupt Status 1 Mask */
{ 0x00000D09, 0xFFFF }, /* R3337 - Interrupt Status 2 Mask */
{ 0x00000D0A, 0xFFFF }, /* R3338 - Interrupt Status 3 Mask */
{ 0x00000D0B, 0xFFFF }, /* R3339 - Interrupt Status 4 Mask */
{ 0x00000D0C, 0xFEFF }, /* R3340 - Interrupt Status 5 Mask */
{ 0x00000D0F, 0x0000 }, /* R3343 - Interrupt Control */
{ 0x00000D18, 0xFFFF }, /* R3352 - IRQ2 Status 1 Mask */
{ 0x00000D19, 0xFFFF }, /* R3353 - IRQ2 Status 2 Mask */
{ 0x00000D1A, 0xFFFF }, /* R3354 - IRQ2 Status 3 Mask */
{ 0x00000D1B, 0xFFFF }, /* R3355 - IRQ2 Status 4 Mask */
{ 0x00000D1C, 0xFEFF }, /* R3356 - IRQ2 Status 5 Mask */
{ 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */
{ 0x00000D53, 0xFFFF }, /* R3411 - AOD IRQ Mask IRQ1 */
{ 0x00000D54, 0xFFFF }, /* R3412 - AOD IRQ Mask IRQ2 */
{ 0x00000D56, 0x0000 }, /* R3414 - Jack detect debounce */
{ 0x00000E00, 0x0000 }, /* R3584 - FX_Ctrl1 */
{ 0x00000E10, 0x6318 }, /* R3600 - EQ1_1 */
{ 0x00000E11, 0x6300 }, /* R3601 - EQ1_2 */
{ 0x00000E12, 0x0FC8 }, /* R3602 - EQ1_3 */
{ 0x00000E13, 0x03FE }, /* R3603 - EQ1_4 */
{ 0x00000E14, 0x00E0 }, /* R3604 - EQ1_5 */
{ 0x00000E15, 0x1EC4 }, /* R3605 - EQ1_6 */
{ 0x00000E16, 0xF136 }, /* R3606 - EQ1_7 */
{ 0x00000E17, 0x0409 }, /* R3607 - EQ1_8 */
{ 0x00000E18, 0x04CC }, /* R3608 - EQ1_9 */
{ 0x00000E19, 0x1C9B }, /* R3609 - EQ1_10 */
{ 0x00000E1A, 0xF337 }, /* R3610 - EQ1_11 */
{ 0x00000E1B, 0x040B }, /* R3611 - EQ1_12 */
{ 0x00000E1C, 0x0CBB }, /* R3612 - EQ1_13 */
{ 0x00000E1D, 0x16F8 }, /* R3613 - EQ1_14 */
{ 0x00000E1E, 0xF7D9 }, /* R3614 - EQ1_15 */
{ 0x00000E1F, 0x040A }, /* R3615 - EQ1_16 */
{ 0x00000E20, 0x1F14 }, /* R3616 - EQ1_17 */
{ 0x00000E21, 0x058C }, /* R3617 - EQ1_18 */
{ 0x00000E22, 0x0563 }, /* R3618 - EQ1_19 */
{ 0x00000E23, 0x4000 }, /* R3619 - EQ1_20 */
{ 0x00000E24, 0x0B75 }, /* R3620 - EQ1_21 */
{ 0x00000E26, 0x6318 }, /* R3622 - EQ2_1 */
{ 0x00000E27, 0x6300 }, /* R3623 - EQ2_2 */
{ 0x00000E28, 0x0FC8 }, /* R3624 - EQ2_3 */
{ 0x00000E29, 0x03FE }, /* R3625 - EQ2_4 */
{ 0x00000E2A, 0x00E0 }, /* R3626 - EQ2_5 */
{ 0x00000E2B, 0x1EC4 }, /* R3627 - EQ2_6 */
{ 0x00000E2C, 0xF136 }, /* R3628 - EQ2_7 */
{ 0x00000E2D, 0x0409 }, /* R3629 - EQ2_8 */
{ 0x00000E2E, 0x04CC }, /* R3630 - EQ2_9 */
{ 0x00000E2F, 0x1C9B }, /* R3631 - EQ2_10 */
{ 0x00000E30, 0xF337 }, /* R3632 - EQ2_11 */
{ 0x00000E31, 0x040B }, /* R3633 - EQ2_12 */
{ 0x00000E32, 0x0CBB }, /* R3634 - EQ2_13 */
{ 0x00000E33, 0x16F8 }, /* R3635 - EQ2_14 */
{ 0x00000E34, 0xF7D9 }, /* R3636 - EQ2_15 */
{ 0x00000E35, 0x040A }, /* R3637 - EQ2_16 */
{ 0x00000E36, 0x1F14 }, /* R3638 - EQ2_17 */
{ 0x00000E37, 0x058C }, /* R3639 - EQ2_18 */
{ 0x00000E38, 0x0563 }, /* R3640 - EQ2_19 */
{ 0x00000E39, 0x4000 }, /* R3641 - EQ2_20 */
{ 0x00000E3A, 0x0B75 }, /* R3642 - EQ2_21 */
{ 0x00000E3C, 0x6318 }, /* R3644 - EQ3_1 */
{ 0x00000E3D, 0x6300 }, /* R3645 - EQ3_2 */
{ 0x00000E3E, 0x0FC8 }, /* R3646 - EQ3_3 */
{ 0x00000E3F, 0x03FE }, /* R3647 - EQ3_4 */
{ 0x00000E40, 0x00E0 }, /* R3648 - EQ3_5 */
{ 0x00000E41, 0x1EC4 }, /* R3649 - EQ3_6 */
{ 0x00000E42, 0xF136 }, /* R3650 - EQ3_7 */
{ 0x00000E43, 0x0409 }, /* R3651 - EQ3_8 */
{ 0x00000E44, 0x04CC }, /* R3652 - EQ3_9 */
{ 0x00000E45, 0x1C9B }, /* R3653 - EQ3_10 */
{ 0x00000E46, 0xF337 }, /* R3654 - EQ3_11 */
{ 0x00000E47, 0x040B }, /* R3655 - EQ3_12 */
{ 0x00000E48, 0x0CBB }, /* R3656 - EQ3_13 */
{ 0x00000E49, 0x16F8 }, /* R3657 - EQ3_14 */
{ 0x00000E4A, 0xF7D9 }, /* R3658 - EQ3_15 */
{ 0x00000E4B, 0x040A }, /* R3659 - EQ3_16 */
{ 0x00000E4C, 0x1F14 }, /* R3660 - EQ3_17 */
{ 0x00000E4D, 0x058C }, /* R3661 - EQ3_18 */
{ 0x00000E4E, 0x0563 }, /* R3662 - EQ3_19 */
{ 0x00000E4F, 0x4000 }, /* R3663 - EQ3_20 */
{ 0x00000E50, 0x0B75 }, /* R3664 - EQ3_21 */
{ 0x00000E52, 0x6318 }, /* R3666 - EQ4_1 */
{ 0x00000E53, 0x6300 }, /* R3667 - EQ4_2 */
{ 0x00000E54, 0x0FC8 }, /* R3668 - EQ4_3 */
{ 0x00000E55, 0x03FE }, /* R3669 - EQ4_4 */
{ 0x00000E56, 0x00E0 }, /* R3670 - EQ4_5 */
{ 0x00000E57, 0x1EC4 }, /* R3671 - EQ4_6 */
{ 0x00000E58, 0xF136 }, /* R3672 - EQ4_7 */
{ 0x00000E59, 0x0409 }, /* R3673 - EQ4_8 */
{ 0x00000E5A, 0x04CC }, /* R3674 - EQ4_9 */
{ 0x00000E5B, 0x1C9B }, /* R3675 - EQ4_10 */
{ 0x00000E5C, 0xF337 }, /* R3676 - EQ4_11 */
{ 0x00000E5D, 0x040B }, /* R3677 - EQ4_12 */
{ 0x00000E5E, 0x0CBB }, /* R3678 - EQ4_13 */
{ 0x00000E5F, 0x16F8 }, /* R3679 - EQ4_14 */
{ 0x00000E60, 0xF7D9 }, /* R3680 - EQ4_15 */
{ 0x00000E61, 0x040A }, /* R3681 - EQ4_16 */
{ 0x00000E62, 0x1F14 }, /* R3682 - EQ4_17 */
{ 0x00000E63, 0x058C }, /* R3683 - EQ4_18 */
{ 0x00000E64, 0x0563 }, /* R3684 - EQ4_19 */
{ 0x00000E65, 0x4000 }, /* R3685 - EQ4_20 */
{ 0x00000E66, 0x0B75 }, /* R3686 - EQ4_21 */
{ 0x00000E80, 0x0018 }, /* R3712 - DRC1 ctrl1 */
{ 0x00000E81, 0x0933 }, /* R3713 - DRC1 ctrl2 */
{ 0x00000E82, 0x0018 }, /* R3714 - DRC1 ctrl3 */
{ 0x00000E83, 0x0000 }, /* R3715 - DRC1 ctrl4 */
{ 0x00000E84, 0x0000 }, /* R3716 - DRC1 ctrl5 */
{ 0x00000EC0, 0x0000 }, /* R3776 - HPLPF1_1 */
{ 0x00000EC1, 0x0000 }, /* R3777 - HPLPF1_2 */
{ 0x00000EC4, 0x0000 }, /* R3780 - HPLPF2_1 */
{ 0x00000EC5, 0x0000 }, /* R3781 - HPLPF2_2 */
{ 0x00000EC8, 0x0000 }, /* R3784 - HPLPF3_1 */
{ 0x00000EC9, 0x0000 }, /* R3785 - HPLPF3_2 */
{ 0x00000ECC, 0x0000 }, /* R3788 - HPLPF4_1 */
{ 0x00000ECD, 0x0000 }, /* R3789 - HPLPF4_2 */
{ 0x00000EE0, 0x0000 }, /* R3808 - ASRC_ENABLE */
{ 0x00000EE2, 0x0000 }, /* R3810 - ASRC_RATE1 */
{ 0x00000EE3, 0x4000 }, /* R3811 - ASRC_RATE2 */
{ 0x00000EF0, 0x0000 }, /* R3824 - ISRC 1 CTRL 1 */
{ 0x00000EF1, 0x0001 }, /* R3825 - ISRC 1 CTRL 2 */
{ 0x00000EF2, 0x0000 }, /* R3826 - ISRC 1 CTRL 3 */
{ 0x00000EF3, 0x0000 }, /* R3827 - ISRC 2 CTRL 1 */
{ 0x00000EF4, 0x0001 }, /* R3828 - ISRC 2 CTRL 2 */
{ 0x00000EF5, 0x0000 }, /* R3829 - ISRC 2 CTRL 3 */
};
static bool wm8998_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case ARIZONA_SOFTWARE_RESET:
case ARIZONA_DEVICE_REVISION:
case ARIZONA_CTRL_IF_I2C1_CFG_1:
case ARIZONA_CTRL_IF_I2C1_CFG_2:
case ARIZONA_WRITE_SEQUENCER_CTRL_0:
case ARIZONA_WRITE_SEQUENCER_CTRL_1:
case ARIZONA_WRITE_SEQUENCER_CTRL_2:
case ARIZONA_TONE_GENERATOR_1:
case ARIZONA_TONE_GENERATOR_2:
case ARIZONA_TONE_GENERATOR_3:
case ARIZONA_TONE_GENERATOR_4:
case ARIZONA_TONE_GENERATOR_5:
case ARIZONA_PWM_DRIVE_1:
case ARIZONA_PWM_DRIVE_2:
case ARIZONA_PWM_DRIVE_3:
case ARIZONA_WAKE_CONTROL:
case ARIZONA_SEQUENCE_CONTROL:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6:
case ARIZONA_HAPTICS_CONTROL_1:
case ARIZONA_HAPTICS_CONTROL_2:
case ARIZONA_HAPTICS_PHASE_1_INTENSITY:
case ARIZONA_HAPTICS_PHASE_1_DURATION:
case ARIZONA_HAPTICS_PHASE_2_INTENSITY:
case ARIZONA_HAPTICS_PHASE_2_DURATION:
case ARIZONA_HAPTICS_PHASE_3_INTENSITY:
case ARIZONA_HAPTICS_PHASE_3_DURATION:
case ARIZONA_HAPTICS_STATUS:
case ARIZONA_CLOCK_32K_1:
case ARIZONA_SYSTEM_CLOCK_1:
case ARIZONA_SAMPLE_RATE_1:
case ARIZONA_SAMPLE_RATE_2:
case ARIZONA_SAMPLE_RATE_3:
case ARIZONA_SAMPLE_RATE_1_STATUS:
case ARIZONA_SAMPLE_RATE_2_STATUS:
case ARIZONA_SAMPLE_RATE_3_STATUS:
case ARIZONA_ASYNC_CLOCK_1:
case ARIZONA_ASYNC_SAMPLE_RATE_1:
case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
case ARIZONA_ASYNC_SAMPLE_RATE_2:
case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS:
case ARIZONA_OUTPUT_SYSTEM_CLOCK:
case ARIZONA_OUTPUT_ASYNC_CLOCK:
case ARIZONA_RATE_ESTIMATOR_1:
case ARIZONA_RATE_ESTIMATOR_2:
case ARIZONA_RATE_ESTIMATOR_3:
case ARIZONA_RATE_ESTIMATOR_4:
case ARIZONA_RATE_ESTIMATOR_5:
case ARIZONA_DYNAMIC_FREQUENCY_SCALING_1:
case ARIZONA_FLL1_CONTROL_1:
case ARIZONA_FLL1_CONTROL_2:
case ARIZONA_FLL1_CONTROL_3:
case ARIZONA_FLL1_CONTROL_4:
case ARIZONA_FLL1_CONTROL_5:
case ARIZONA_FLL1_CONTROL_6:
case ARIZONA_FLL1_CONTROL_7:
case ARIZONA_FLL1_SYNCHRONISER_1:
case ARIZONA_FLL1_SYNCHRONISER_2:
case ARIZONA_FLL1_SYNCHRONISER_3:
case ARIZONA_FLL1_SYNCHRONISER_4:
case ARIZONA_FLL1_SYNCHRONISER_5:
case ARIZONA_FLL1_SYNCHRONISER_6:
case ARIZONA_FLL1_SYNCHRONISER_7:
case ARIZONA_FLL1_SPREAD_SPECTRUM:
case ARIZONA_FLL1_GPIO_CLOCK:
case ARIZONA_FLL2_CONTROL_1:
case ARIZONA_FLL2_CONTROL_2:
case ARIZONA_FLL2_CONTROL_3:
case ARIZONA_FLL2_CONTROL_4:
case ARIZONA_FLL2_CONTROL_5:
case ARIZONA_FLL2_CONTROL_6:
case ARIZONA_FLL2_CONTROL_7:
case ARIZONA_FLL2_SYNCHRONISER_1:
case ARIZONA_FLL2_SYNCHRONISER_2:
case ARIZONA_FLL2_SYNCHRONISER_3:
case ARIZONA_FLL2_SYNCHRONISER_4:
case ARIZONA_FLL2_SYNCHRONISER_5:
case ARIZONA_FLL2_SYNCHRONISER_6:
case ARIZONA_FLL2_SYNCHRONISER_7:
case ARIZONA_FLL2_SPREAD_SPECTRUM:
case ARIZONA_FLL2_GPIO_CLOCK:
case ARIZONA_MIC_CHARGE_PUMP_1:
case ARIZONA_LDO1_CONTROL_1:
case ARIZONA_LDO1_CONTROL_2:
case ARIZONA_LDO2_CONTROL_1:
case ARIZONA_MIC_BIAS_CTRL_1:
case ARIZONA_MIC_BIAS_CTRL_2:
case ARIZONA_MIC_BIAS_CTRL_3:
case ARIZONA_ACCESSORY_DETECT_MODE_1:
case ARIZONA_HEADPHONE_DETECT_1:
case ARIZONA_HEADPHONE_DETECT_2:
case ARIZONA_MICD_CLAMP_CONTROL:
case ARIZONA_MIC_DETECT_1:
case ARIZONA_MIC_DETECT_2:
case ARIZONA_MIC_DETECT_3:
case ARIZONA_MIC_DETECT_4:
case ARIZONA_MIC_DETECT_LEVEL_1:
case ARIZONA_MIC_DETECT_LEVEL_2:
case ARIZONA_MIC_DETECT_LEVEL_3:
case ARIZONA_MIC_DETECT_LEVEL_4:
case ARIZONA_ISOLATION_CONTROL:
case ARIZONA_JACK_DETECT_ANALOGUE:
case ARIZONA_INPUT_ENABLES:
case ARIZONA_INPUT_ENABLES_STATUS:
case ARIZONA_INPUT_RATE:
case ARIZONA_INPUT_VOLUME_RAMP:
case ARIZONA_HPF_CONTROL:
case ARIZONA_IN1L_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_1L:
case ARIZONA_DMIC1L_CONTROL:
case ARIZONA_IN1R_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_1R:
case ARIZONA_DMIC1R_CONTROL:
case ARIZONA_IN2L_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_2L:
case ARIZONA_DMIC2L_CONTROL:
case ARIZONA_OUTPUT_ENABLES_1:
case ARIZONA_OUTPUT_STATUS_1:
case ARIZONA_RAW_OUTPUT_STATUS_1:
case ARIZONA_OUTPUT_RATE_1:
case ARIZONA_OUTPUT_VOLUME_RAMP:
case ARIZONA_OUTPUT_PATH_CONFIG_1L:
case ARIZONA_DAC_DIGITAL_VOLUME_1L:
case ARIZONA_NOISE_GATE_SELECT_1L:
case ARIZONA_OUTPUT_PATH_CONFIG_1R:
case ARIZONA_DAC_DIGITAL_VOLUME_1R:
case ARIZONA_NOISE_GATE_SELECT_1R:
case ARIZONA_OUTPUT_PATH_CONFIG_2L:
case ARIZONA_DAC_DIGITAL_VOLUME_2L:
case ARIZONA_NOISE_GATE_SELECT_2L:
case ARIZONA_OUTPUT_PATH_CONFIG_2R:
case ARIZONA_DAC_DIGITAL_VOLUME_2R:
case ARIZONA_NOISE_GATE_SELECT_2R:
case ARIZONA_OUTPUT_PATH_CONFIG_3L:
case ARIZONA_DAC_DIGITAL_VOLUME_3L:
case ARIZONA_NOISE_GATE_SELECT_3L:
case ARIZONA_OUTPUT_PATH_CONFIG_4L:
case ARIZONA_DAC_DIGITAL_VOLUME_4L:
case ARIZONA_NOISE_GATE_SELECT_4L:
case ARIZONA_OUTPUT_PATH_CONFIG_4R:
case ARIZONA_DAC_DIGITAL_VOLUME_4R:
case ARIZONA_NOISE_GATE_SELECT_4R:
case ARIZONA_OUTPUT_PATH_CONFIG_5L:
case ARIZONA_DAC_DIGITAL_VOLUME_5L:
case ARIZONA_NOISE_GATE_SELECT_5L:
case ARIZONA_OUTPUT_PATH_CONFIG_5R:
case ARIZONA_DAC_DIGITAL_VOLUME_5R:
case ARIZONA_NOISE_GATE_SELECT_5R:
case ARIZONA_DRE_ENABLE:
case ARIZONA_DRE_CONTROL_1:
case ARIZONA_DRE_CONTROL_2:
case ARIZONA_DRE_CONTROL_3:
case ARIZONA_EDRE_ENABLE:
case ARIZONA_DAC_AEC_CONTROL_1:
case ARIZONA_DAC_AEC_CONTROL_2:
case ARIZONA_NOISE_GATE_CONTROL:
case ARIZONA_PDM_SPK1_CTRL_1:
case ARIZONA_PDM_SPK1_CTRL_2:
case ARIZONA_HP_TEST_CTRL_13:
case ARIZONA_AIF1_BCLK_CTRL:
case ARIZONA_AIF1_TX_PIN_CTRL:
case ARIZONA_AIF1_RX_PIN_CTRL:
case ARIZONA_AIF1_RATE_CTRL:
case ARIZONA_AIF1_FORMAT:
case ARIZONA_AIF1_RX_BCLK_RATE:
case ARIZONA_AIF1_FRAME_CTRL_1:
case ARIZONA_AIF1_FRAME_CTRL_2:
case ARIZONA_AIF1_FRAME_CTRL_3:
case ARIZONA_AIF1_FRAME_CTRL_4:
case ARIZONA_AIF1_FRAME_CTRL_5:
case ARIZONA_AIF1_FRAME_CTRL_6:
case ARIZONA_AIF1_FRAME_CTRL_7:
case ARIZONA_AIF1_FRAME_CTRL_8:
case ARIZONA_AIF1_FRAME_CTRL_11:
case ARIZONA_AIF1_FRAME_CTRL_12:
case ARIZONA_AIF1_FRAME_CTRL_13:
case ARIZONA_AIF1_FRAME_CTRL_14:
case ARIZONA_AIF1_FRAME_CTRL_15:
case ARIZONA_AIF1_FRAME_CTRL_16:
case ARIZONA_AIF1_TX_ENABLES:
case ARIZONA_AIF1_RX_ENABLES:
case ARIZONA_AIF2_BCLK_CTRL:
case ARIZONA_AIF2_TX_PIN_CTRL:
case ARIZONA_AIF2_RX_PIN_CTRL:
case ARIZONA_AIF2_RATE_CTRL:
case ARIZONA_AIF2_FORMAT:
case ARIZONA_AIF2_RX_BCLK_RATE:
case ARIZONA_AIF2_FRAME_CTRL_1:
case ARIZONA_AIF2_FRAME_CTRL_2:
case ARIZONA_AIF2_FRAME_CTRL_3:
case ARIZONA_AIF2_FRAME_CTRL_4:
case ARIZONA_AIF2_FRAME_CTRL_5:
case ARIZONA_AIF2_FRAME_CTRL_6:
case ARIZONA_AIF2_FRAME_CTRL_7:
case ARIZONA_AIF2_FRAME_CTRL_8:
case ARIZONA_AIF2_FRAME_CTRL_11:
case ARIZONA_AIF2_FRAME_CTRL_12:
case ARIZONA_AIF2_FRAME_CTRL_13:
case ARIZONA_AIF2_FRAME_CTRL_14:
case ARIZONA_AIF2_FRAME_CTRL_15:
case ARIZONA_AIF2_FRAME_CTRL_16:
case ARIZONA_AIF2_TX_ENABLES:
case ARIZONA_AIF2_RX_ENABLES:
case ARIZONA_AIF3_BCLK_CTRL:
case ARIZONA_AIF3_TX_PIN_CTRL:
case ARIZONA_AIF3_RX_PIN_CTRL:
case ARIZONA_AIF3_RATE_CTRL:
case ARIZONA_AIF3_FORMAT:
case ARIZONA_AIF3_RX_BCLK_RATE:
case ARIZONA_AIF3_FRAME_CTRL_1:
case ARIZONA_AIF3_FRAME_CTRL_2:
case ARIZONA_AIF3_FRAME_CTRL_3:
case ARIZONA_AIF3_FRAME_CTRL_4:
case ARIZONA_AIF3_FRAME_CTRL_11:
case ARIZONA_AIF3_FRAME_CTRL_12:
case ARIZONA_AIF3_TX_ENABLES:
case ARIZONA_AIF3_RX_ENABLES:
case ARIZONA_SPD1_TX_CONTROL:
case ARIZONA_SPD1_TX_CHANNEL_STATUS_1:
case ARIZONA_SPD1_TX_CHANNEL_STATUS_2:
case ARIZONA_SPD1_TX_CHANNEL_STATUS_3:
case ARIZONA_SLIMBUS_FRAMER_REF_GEAR:
case ARIZONA_SLIMBUS_RATES_1:
case ARIZONA_SLIMBUS_RATES_2:
case ARIZONA_SLIMBUS_RATES_5:
case ARIZONA_SLIMBUS_RATES_6:
case ARIZONA_SLIMBUS_RATES_7:
case ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE:
case ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE:
case ARIZONA_SLIMBUS_RX_PORT_STATUS:
case ARIZONA_SLIMBUS_TX_PORT_STATUS:
case ARIZONA_PWM1MIX_INPUT_1_SOURCE:
case ARIZONA_PWM1MIX_INPUT_1_VOLUME:
case ARIZONA_PWM1MIX_INPUT_2_SOURCE:
case ARIZONA_PWM1MIX_INPUT_2_VOLUME:
case ARIZONA_PWM1MIX_INPUT_3_SOURCE:
case ARIZONA_PWM1MIX_INPUT_3_VOLUME:
case ARIZONA_PWM1MIX_INPUT_4_SOURCE:
case ARIZONA_PWM1MIX_INPUT_4_VOLUME:
case ARIZONA_PWM2MIX_INPUT_1_SOURCE:
case ARIZONA_PWM2MIX_INPUT_1_VOLUME:
case ARIZONA_PWM2MIX_INPUT_2_SOURCE:
case ARIZONA_PWM2MIX_INPUT_2_VOLUME:
case ARIZONA_PWM2MIX_INPUT_3_SOURCE:
case ARIZONA_PWM2MIX_INPUT_3_VOLUME:
case ARIZONA_PWM2MIX_INPUT_4_SOURCE:
case ARIZONA_PWM2MIX_INPUT_4_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_4_VOLUME:
case ARIZONA_OUT2LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT2LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT2LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT2LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT2LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT2LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT2LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT2LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT2RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT2RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT2RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT2RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT2RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT2RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT2RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT2RMIX_INPUT_4_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT4RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT4RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT4RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT4RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT4RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT4RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT4RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT4RMIX_INPUT_4_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME:
case ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE:
case ARIZONA_SPDIFTX1MIX_INPUT_1_VOLUME:
case ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE:
case ARIZONA_SPDIFTX2MIX_INPUT_1_VOLUME:
case ARIZONA_EQ1MIX_INPUT_1_SOURCE:
case ARIZONA_EQ1MIX_INPUT_1_VOLUME:
case ARIZONA_EQ2MIX_INPUT_1_SOURCE:
case ARIZONA_EQ2MIX_INPUT_1_VOLUME:
case ARIZONA_EQ3MIX_INPUT_1_SOURCE:
case ARIZONA_EQ3MIX_INPUT_1_VOLUME:
case ARIZONA_EQ4MIX_INPUT_1_SOURCE:
case ARIZONA_EQ4MIX_INPUT_1_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_1_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_1_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_1_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_1_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_4_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_4_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_4_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_4_VOLUME:
case ARIZONA_ASRC1LMIX_INPUT_1_SOURCE:
case ARIZONA_ASRC1RMIX_INPUT_1_SOURCE:
case ARIZONA_ASRC2LMIX_INPUT_1_SOURCE:
case ARIZONA_ASRC2RMIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE:
case ARIZONA_GPIO1_CTRL:
case ARIZONA_GPIO2_CTRL:
case ARIZONA_GPIO3_CTRL:
case ARIZONA_GPIO4_CTRL:
case ARIZONA_GPIO5_CTRL:
case ARIZONA_IRQ_CTRL_1:
case ARIZONA_GPIO_DEBOUNCE_CONFIG:
case ARIZONA_GP_SWITCH_1:
case ARIZONA_MISC_PAD_CTRL_1:
case ARIZONA_MISC_PAD_CTRL_2:
case ARIZONA_MISC_PAD_CTRL_3:
case ARIZONA_MISC_PAD_CTRL_4:
case ARIZONA_MISC_PAD_CTRL_5:
case ARIZONA_MISC_PAD_CTRL_6:
case ARIZONA_INTERRUPT_STATUS_1:
case ARIZONA_INTERRUPT_STATUS_2:
case ARIZONA_INTERRUPT_STATUS_3:
case ARIZONA_INTERRUPT_STATUS_4:
case ARIZONA_INTERRUPT_STATUS_5:
case ARIZONA_INTERRUPT_STATUS_1_MASK:
case ARIZONA_INTERRUPT_STATUS_2_MASK:
case ARIZONA_INTERRUPT_STATUS_3_MASK:
case ARIZONA_INTERRUPT_STATUS_4_MASK:
case ARIZONA_INTERRUPT_STATUS_5_MASK:
case ARIZONA_INTERRUPT_CONTROL:
case ARIZONA_IRQ2_STATUS_1:
case ARIZONA_IRQ2_STATUS_2:
case ARIZONA_IRQ2_STATUS_3:
case ARIZONA_IRQ2_STATUS_4:
case ARIZONA_IRQ2_STATUS_5:
case ARIZONA_IRQ2_STATUS_1_MASK:
case ARIZONA_IRQ2_STATUS_2_MASK:
case ARIZONA_IRQ2_STATUS_3_MASK:
case ARIZONA_IRQ2_STATUS_4_MASK:
case ARIZONA_IRQ2_STATUS_5_MASK:
case ARIZONA_IRQ2_CONTROL:
case ARIZONA_INTERRUPT_RAW_STATUS_2:
case ARIZONA_INTERRUPT_RAW_STATUS_3:
case ARIZONA_INTERRUPT_RAW_STATUS_4:
case ARIZONA_INTERRUPT_RAW_STATUS_5:
case ARIZONA_INTERRUPT_RAW_STATUS_6:
case ARIZONA_INTERRUPT_RAW_STATUS_7:
case ARIZONA_INTERRUPT_RAW_STATUS_8:
case ARIZONA_IRQ_PIN_STATUS:
case ARIZONA_AOD_WKUP_AND_TRIG:
case ARIZONA_AOD_IRQ1:
case ARIZONA_AOD_IRQ2:
case ARIZONA_AOD_IRQ_MASK_IRQ1:
case ARIZONA_AOD_IRQ_MASK_IRQ2:
case ARIZONA_AOD_IRQ_RAW_STATUS:
case ARIZONA_JACK_DETECT_DEBOUNCE:
case ARIZONA_FX_CTRL1:
case ARIZONA_FX_CTRL2:
case ARIZONA_EQ1_1:
case ARIZONA_EQ1_2:
case ARIZONA_EQ1_3:
case ARIZONA_EQ1_4:
case ARIZONA_EQ1_5:
case ARIZONA_EQ1_6:
case ARIZONA_EQ1_7:
case ARIZONA_EQ1_8:
case ARIZONA_EQ1_9:
case ARIZONA_EQ1_10:
case ARIZONA_EQ1_11:
case ARIZONA_EQ1_12:
case ARIZONA_EQ1_13:
case ARIZONA_EQ1_14:
case ARIZONA_EQ1_15:
case ARIZONA_EQ1_16:
case ARIZONA_EQ1_17:
case ARIZONA_EQ1_18:
case ARIZONA_EQ1_19:
case ARIZONA_EQ1_20:
case ARIZONA_EQ1_21:
case ARIZONA_EQ2_1:
case ARIZONA_EQ2_2:
case ARIZONA_EQ2_3:
case ARIZONA_EQ2_4:
case ARIZONA_EQ2_5:
case ARIZONA_EQ2_6:
case ARIZONA_EQ2_7:
case ARIZONA_EQ2_8:
case ARIZONA_EQ2_9:
case ARIZONA_EQ2_10:
case ARIZONA_EQ2_11:
case ARIZONA_EQ2_12:
case ARIZONA_EQ2_13:
case ARIZONA_EQ2_14:
case ARIZONA_EQ2_15:
case ARIZONA_EQ2_16:
case ARIZONA_EQ2_17:
case ARIZONA_EQ2_18:
case ARIZONA_EQ2_19:
case ARIZONA_EQ2_20:
case ARIZONA_EQ2_21:
case ARIZONA_EQ3_1:
case ARIZONA_EQ3_2:
case ARIZONA_EQ3_3:
case ARIZONA_EQ3_4:
case ARIZONA_EQ3_5:
case ARIZONA_EQ3_6:
case ARIZONA_EQ3_7:
case ARIZONA_EQ3_8:
case ARIZONA_EQ3_9:
case ARIZONA_EQ3_10:
case ARIZONA_EQ3_11:
case ARIZONA_EQ3_12:
case ARIZONA_EQ3_13:
case ARIZONA_EQ3_14:
case ARIZONA_EQ3_15:
case ARIZONA_EQ3_16:
case ARIZONA_EQ3_17:
case ARIZONA_EQ3_18:
case ARIZONA_EQ3_19:
case ARIZONA_EQ3_20:
case ARIZONA_EQ3_21:
case ARIZONA_EQ4_1:
case ARIZONA_EQ4_2:
case ARIZONA_EQ4_3:
case ARIZONA_EQ4_4:
case ARIZONA_EQ4_5:
case ARIZONA_EQ4_6:
case ARIZONA_EQ4_7:
case ARIZONA_EQ4_8:
case ARIZONA_EQ4_9:
case ARIZONA_EQ4_10:
case ARIZONA_EQ4_11:
case ARIZONA_EQ4_12:
case ARIZONA_EQ4_13:
case ARIZONA_EQ4_14:
case ARIZONA_EQ4_15:
case ARIZONA_EQ4_16:
case ARIZONA_EQ4_17:
case ARIZONA_EQ4_18:
case ARIZONA_EQ4_19:
case ARIZONA_EQ4_20:
case ARIZONA_EQ4_21:
case ARIZONA_DRC1_CTRL1:
case ARIZONA_DRC1_CTRL2:
case ARIZONA_DRC1_CTRL3:
case ARIZONA_DRC1_CTRL4:
case ARIZONA_DRC1_CTRL5:
case ARIZONA_HPLPF1_1:
case ARIZONA_HPLPF1_2:
case ARIZONA_HPLPF2_1:
case ARIZONA_HPLPF2_2:
case ARIZONA_HPLPF3_1:
case ARIZONA_HPLPF3_2:
case ARIZONA_HPLPF4_1:
case ARIZONA_HPLPF4_2:
case ARIZONA_ASRC_ENABLE:
case ARIZONA_ASRC_STATUS:
case ARIZONA_ASRC_RATE1:
case ARIZONA_ASRC_RATE2:
case ARIZONA_ISRC_1_CTRL_1:
case ARIZONA_ISRC_1_CTRL_2:
case ARIZONA_ISRC_1_CTRL_3:
case ARIZONA_ISRC_2_CTRL_1:
case ARIZONA_ISRC_2_CTRL_2:
case ARIZONA_ISRC_2_CTRL_3:
return true;
default:
return false;
}
}
static bool wm8998_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case ARIZONA_SOFTWARE_RESET:
case ARIZONA_DEVICE_REVISION:
case ARIZONA_WRITE_SEQUENCER_CTRL_0:
case ARIZONA_WRITE_SEQUENCER_CTRL_1:
case ARIZONA_WRITE_SEQUENCER_CTRL_2:
case ARIZONA_HAPTICS_STATUS:
case ARIZONA_SAMPLE_RATE_1_STATUS:
case ARIZONA_SAMPLE_RATE_2_STATUS:
case ARIZONA_SAMPLE_RATE_3_STATUS:
case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS:
case ARIZONA_MIC_DETECT_3:
case ARIZONA_MIC_DETECT_4:
case ARIZONA_HEADPHONE_DETECT_2:
case ARIZONA_INPUT_ENABLES_STATUS:
case ARIZONA_OUTPUT_STATUS_1:
case ARIZONA_RAW_OUTPUT_STATUS_1:
case ARIZONA_SLIMBUS_RX_PORT_STATUS:
case ARIZONA_SLIMBUS_TX_PORT_STATUS:
case ARIZONA_INTERRUPT_STATUS_1:
case ARIZONA_INTERRUPT_STATUS_2:
case ARIZONA_INTERRUPT_STATUS_3:
case ARIZONA_INTERRUPT_STATUS_4:
case ARIZONA_INTERRUPT_STATUS_5:
case ARIZONA_IRQ2_STATUS_1:
case ARIZONA_IRQ2_STATUS_2:
case ARIZONA_IRQ2_STATUS_3:
case ARIZONA_IRQ2_STATUS_4:
case ARIZONA_IRQ2_STATUS_5:
case ARIZONA_INTERRUPT_RAW_STATUS_2:
case ARIZONA_INTERRUPT_RAW_STATUS_3:
case ARIZONA_INTERRUPT_RAW_STATUS_4:
case ARIZONA_INTERRUPT_RAW_STATUS_5:
case ARIZONA_INTERRUPT_RAW_STATUS_6:
case ARIZONA_INTERRUPT_RAW_STATUS_7:
case ARIZONA_INTERRUPT_RAW_STATUS_8:
case ARIZONA_IRQ_PIN_STATUS:
case ARIZONA_AOD_WKUP_AND_TRIG:
case ARIZONA_AOD_IRQ1:
case ARIZONA_AOD_IRQ2:
case ARIZONA_AOD_IRQ_RAW_STATUS:
case ARIZONA_FX_CTRL2:
case ARIZONA_ASRC_STATUS:
return true;
default:
return false;
}
}
#define WM8998_MAX_REGISTER 0x31ff
const struct regmap_config wm8998_i2c_regmap = {
.reg_bits = 32,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = WM8998_MAX_REGISTER,
.readable_reg = wm8998_readable_register,
.volatile_reg = wm8998_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm8998_reg_default,
.num_reg_defaults = ARRAY_SIZE(wm8998_reg_default),
};
EXPORT_SYMBOL_GPL(wm8998_i2c_regmap);
| linux-master | drivers/mfd/wm8998-tables.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Device driver for MFD hi655x PMIC
*
* Copyright (c) 2016 HiSilicon Ltd.
*
* Authors:
* Chen Feng <[email protected]>
* Fei Wang <[email protected]>
*/
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/mfd/core.h>
#include <linux/mfd/hi655x-pmic.h>
#include <linux/module.h>
#include <linux/gpio/consumer.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
static const struct regmap_irq hi655x_irqs[] = {
{ .reg_offset = 0, .mask = OTMP_D1R_INT_MASK },
{ .reg_offset = 0, .mask = VSYS_2P5_R_INT_MASK },
{ .reg_offset = 0, .mask = VSYS_UV_D3R_INT_MASK },
{ .reg_offset = 0, .mask = VSYS_6P0_D200UR_INT_MASK },
{ .reg_offset = 0, .mask = PWRON_D4SR_INT_MASK },
{ .reg_offset = 0, .mask = PWRON_D20F_INT_MASK },
{ .reg_offset = 0, .mask = PWRON_D20R_INT_MASK },
{ .reg_offset = 0, .mask = RESERVE_INT_MASK },
};
static const struct regmap_irq_chip hi655x_irq_chip = {
.name = "hi655x-pmic",
.irqs = hi655x_irqs,
.num_regs = 1,
.num_irqs = ARRAY_SIZE(hi655x_irqs),
.status_base = HI655X_IRQ_STAT_BASE,
.ack_base = HI655X_IRQ_STAT_BASE,
.mask_base = HI655X_IRQ_MASK_BASE,
};
static struct regmap_config hi655x_regmap_config = {
.reg_bits = 32,
.reg_stride = HI655X_STRIDE,
.val_bits = 8,
.max_register = HI655X_BUS_ADDR(0x400) - HI655X_STRIDE,
};
static const struct resource pwrkey_resources[] = {
{
.name = "down",
.start = PWRON_D20R_INT,
.end = PWRON_D20R_INT,
.flags = IORESOURCE_IRQ,
}, {
.name = "up",
.start = PWRON_D20F_INT,
.end = PWRON_D20F_INT,
.flags = IORESOURCE_IRQ,
}, {
.name = "hold 4s",
.start = PWRON_D4SR_INT,
.end = PWRON_D4SR_INT,
.flags = IORESOURCE_IRQ,
},
};
static const struct mfd_cell hi655x_pmic_devs[] = {
{
.name = "hi65xx-powerkey",
.num_resources = ARRAY_SIZE(pwrkey_resources),
.resources = &pwrkey_resources[0],
},
{ .name = "hi655x-regulator", },
{ .name = "hi655x-clk", },
};
static void hi655x_local_irq_clear(struct regmap *map)
{
int i;
regmap_write(map, HI655X_ANA_IRQM_BASE, HI655X_IRQ_CLR);
for (i = 0; i < HI655X_IRQ_ARRAY; i++) {
regmap_write(map, HI655X_IRQ_STAT_BASE + i * HI655X_STRIDE,
HI655X_IRQ_CLR);
}
}
static int hi655x_pmic_probe(struct platform_device *pdev)
{
int ret;
struct hi655x_pmic *pmic;
struct device *dev = &pdev->dev;
void __iomem *base;
pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
if (!pmic)
return -ENOMEM;
pmic->dev = dev;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
pmic->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,
&hi655x_regmap_config);
if (IS_ERR(pmic->regmap))
return PTR_ERR(pmic->regmap);
regmap_read(pmic->regmap, HI655X_BUS_ADDR(HI655X_VER_REG), &pmic->ver);
if ((pmic->ver < PMU_VER_START) || (pmic->ver > PMU_VER_END)) {
dev_warn(dev, "PMU version %d unsupported\n", pmic->ver);
return -EINVAL;
}
hi655x_local_irq_clear(pmic->regmap);
pmic->gpio = devm_gpiod_get_optional(dev, "pmic", GPIOD_IN);
if (IS_ERR(pmic->gpio))
return dev_err_probe(dev, PTR_ERR(pmic->gpio),
"Failed to request hi655x pmic-gpio");
ret = regmap_add_irq_chip(pmic->regmap, gpiod_to_irq(pmic->gpio),
IRQF_TRIGGER_LOW | IRQF_NO_SUSPEND, 0,
&hi655x_irq_chip, &pmic->irq_data);
if (ret) {
dev_err(dev, "Failed to obtain 'hi655x_pmic_irq' %d\n", ret);
return ret;
}
platform_set_drvdata(pdev, pmic);
ret = mfd_add_devices(dev, PLATFORM_DEVID_AUTO, hi655x_pmic_devs,
ARRAY_SIZE(hi655x_pmic_devs), NULL, 0,
regmap_irq_get_domain(pmic->irq_data));
if (ret) {
dev_err(dev, "Failed to register device %d\n", ret);
regmap_del_irq_chip(gpiod_to_irq(pmic->gpio), pmic->irq_data);
return ret;
}
return 0;
}
static int hi655x_pmic_remove(struct platform_device *pdev)
{
struct hi655x_pmic *pmic = platform_get_drvdata(pdev);
regmap_del_irq_chip(gpiod_to_irq(pmic->gpio), pmic->irq_data);
mfd_remove_devices(&pdev->dev);
return 0;
}
static const struct of_device_id hi655x_pmic_match[] = {
{ .compatible = "hisilicon,hi655x-pmic", },
{},
};
MODULE_DEVICE_TABLE(of, hi655x_pmic_match);
static struct platform_driver hi655x_pmic_driver = {
.driver = {
.name = "hi655x-pmic",
.of_match_table = hi655x_pmic_match,
},
.probe = hi655x_pmic_probe,
.remove = hi655x_pmic_remove,
};
module_platform_driver(hi655x_pmic_driver);
MODULE_AUTHOR("Chen Feng <[email protected]>");
MODULE_DESCRIPTION("Hisilicon hi655x PMIC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/hi655x-pmic.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Core driver for TI TPS65090 PMIC family
*
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
* Author: Venu Byravarasu <[email protected]>
*/
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tps65090.h>
#include <linux/of.h>
#include <linux/err.h>
#define NUM_INT_REG 2
#define TPS65090_INT1_MASK_VAC_STATUS_CHANGE 1
#define TPS65090_INT1_MASK_VSYS_STATUS_CHANGE 2
#define TPS65090_INT1_MASK_BAT_STATUS_CHANGE 3
#define TPS65090_INT1_MASK_CHARGING_STATUS_CHANGE 4
#define TPS65090_INT1_MASK_CHARGING_COMPLETE 5
#define TPS65090_INT1_MASK_OVERLOAD_DCDC1 6
#define TPS65090_INT1_MASK_OVERLOAD_DCDC2 7
#define TPS65090_INT2_MASK_OVERLOAD_DCDC3 0
#define TPS65090_INT2_MASK_OVERLOAD_FET1 1
#define TPS65090_INT2_MASK_OVERLOAD_FET2 2
#define TPS65090_INT2_MASK_OVERLOAD_FET3 3
#define TPS65090_INT2_MASK_OVERLOAD_FET4 4
#define TPS65090_INT2_MASK_OVERLOAD_FET5 5
#define TPS65090_INT2_MASK_OVERLOAD_FET6 6
#define TPS65090_INT2_MASK_OVERLOAD_FET7 7
static const struct resource charger_resources[] = {
{
.start = TPS65090_IRQ_VAC_STATUS_CHANGE,
.end = TPS65090_IRQ_VAC_STATUS_CHANGE,
.flags = IORESOURCE_IRQ,
}
};
enum tps65090_cells {
PMIC = 0,
CHARGER = 1,
};
static struct mfd_cell tps65090s[] = {
[PMIC] = {
.name = "tps65090-pmic",
},
[CHARGER] = {
.name = "tps65090-charger",
.num_resources = ARRAY_SIZE(charger_resources),
.resources = &charger_resources[0],
.of_compatible = "ti,tps65090-charger",
},
};
static const struct regmap_irq tps65090_irqs[] = {
/* INT1 IRQs*/
[TPS65090_IRQ_VAC_STATUS_CHANGE] = {
.mask = TPS65090_INT1_MASK_VAC_STATUS_CHANGE,
},
[TPS65090_IRQ_VSYS_STATUS_CHANGE] = {
.mask = TPS65090_INT1_MASK_VSYS_STATUS_CHANGE,
},
[TPS65090_IRQ_BAT_STATUS_CHANGE] = {
.mask = TPS65090_INT1_MASK_BAT_STATUS_CHANGE,
},
[TPS65090_IRQ_CHARGING_STATUS_CHANGE] = {
.mask = TPS65090_INT1_MASK_CHARGING_STATUS_CHANGE,
},
[TPS65090_IRQ_CHARGING_COMPLETE] = {
.mask = TPS65090_INT1_MASK_CHARGING_COMPLETE,
},
[TPS65090_IRQ_OVERLOAD_DCDC1] = {
.mask = TPS65090_INT1_MASK_OVERLOAD_DCDC1,
},
[TPS65090_IRQ_OVERLOAD_DCDC2] = {
.mask = TPS65090_INT1_MASK_OVERLOAD_DCDC2,
},
/* INT2 IRQs*/
[TPS65090_IRQ_OVERLOAD_DCDC3] = {
.reg_offset = 1,
.mask = TPS65090_INT2_MASK_OVERLOAD_DCDC3,
},
[TPS65090_IRQ_OVERLOAD_FET1] = {
.reg_offset = 1,
.mask = TPS65090_INT2_MASK_OVERLOAD_FET1,
},
[TPS65090_IRQ_OVERLOAD_FET2] = {
.reg_offset = 1,
.mask = TPS65090_INT2_MASK_OVERLOAD_FET2,
},
[TPS65090_IRQ_OVERLOAD_FET3] = {
.reg_offset = 1,
.mask = TPS65090_INT2_MASK_OVERLOAD_FET3,
},
[TPS65090_IRQ_OVERLOAD_FET4] = {
.reg_offset = 1,
.mask = TPS65090_INT2_MASK_OVERLOAD_FET4,
},
[TPS65090_IRQ_OVERLOAD_FET5] = {
.reg_offset = 1,
.mask = TPS65090_INT2_MASK_OVERLOAD_FET5,
},
[TPS65090_IRQ_OVERLOAD_FET6] = {
.reg_offset = 1,
.mask = TPS65090_INT2_MASK_OVERLOAD_FET6,
},
[TPS65090_IRQ_OVERLOAD_FET7] = {
.reg_offset = 1,
.mask = TPS65090_INT2_MASK_OVERLOAD_FET7,
},
};
static struct regmap_irq_chip tps65090_irq_chip = {
.name = "tps65090",
.irqs = tps65090_irqs,
.num_irqs = ARRAY_SIZE(tps65090_irqs),
.num_regs = NUM_INT_REG,
.status_base = TPS65090_REG_INTR_STS,
.unmask_base = TPS65090_REG_INTR_MASK,
};
static bool is_volatile_reg(struct device *dev, unsigned int reg)
{
/* Nearly all registers have status bits mixed in, except a few */
switch (reg) {
case TPS65090_REG_INTR_MASK:
case TPS65090_REG_INTR_MASK2:
case TPS65090_REG_CG_CTRL0:
case TPS65090_REG_CG_CTRL1:
case TPS65090_REG_CG_CTRL2:
case TPS65090_REG_CG_CTRL3:
case TPS65090_REG_CG_CTRL4:
case TPS65090_REG_CG_CTRL5:
return false;
}
return true;
}
static const struct regmap_config tps65090_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = TPS65090_MAX_REG,
.num_reg_defaults_raw = TPS65090_NUM_REGS,
.cache_type = REGCACHE_RBTREE,
.volatile_reg = is_volatile_reg,
};
#ifdef CONFIG_OF
static const struct of_device_id tps65090_of_match[] = {
{ .compatible = "ti,tps65090",},
{},
};
#endif
static int tps65090_i2c_probe(struct i2c_client *client)
{
struct tps65090_platform_data *pdata = dev_get_platdata(&client->dev);
int irq_base = 0;
struct tps65090 *tps65090;
int ret;
if (!pdata && !client->dev.of_node) {
dev_err(&client->dev,
"tps65090 requires platform data or of_node\n");
return -EINVAL;
}
if (pdata)
irq_base = pdata->irq_base;
tps65090 = devm_kzalloc(&client->dev, sizeof(*tps65090), GFP_KERNEL);
if (!tps65090)
return -ENOMEM;
tps65090->dev = &client->dev;
i2c_set_clientdata(client, tps65090);
tps65090->rmap = devm_regmap_init_i2c(client, &tps65090_regmap_config);
if (IS_ERR(tps65090->rmap)) {
ret = PTR_ERR(tps65090->rmap);
dev_err(&client->dev, "regmap_init failed with err: %d\n", ret);
return ret;
}
if (client->irq) {
ret = regmap_add_irq_chip(tps65090->rmap, client->irq,
IRQF_ONESHOT | IRQF_TRIGGER_LOW, irq_base,
&tps65090_irq_chip, &tps65090->irq_data);
if (ret) {
dev_err(&client->dev,
"IRQ init failed with err: %d\n", ret);
return ret;
}
} else {
/* Don't tell children they have an IRQ that'll never fire */
tps65090s[CHARGER].num_resources = 0;
}
ret = mfd_add_devices(tps65090->dev, -1, tps65090s,
ARRAY_SIZE(tps65090s), NULL,
0, regmap_irq_get_domain(tps65090->irq_data));
if (ret) {
dev_err(&client->dev, "add mfd devices failed with err: %d\n",
ret);
goto err_irq_exit;
}
return 0;
err_irq_exit:
if (client->irq)
regmap_del_irq_chip(client->irq, tps65090->irq_data);
return ret;
}
static const struct i2c_device_id tps65090_id_table[] = {
{ "tps65090", 0 },
{ },
};
static struct i2c_driver tps65090_driver = {
.driver = {
.name = "tps65090",
.suppress_bind_attrs = true,
.of_match_table = of_match_ptr(tps65090_of_match),
},
.probe = tps65090_i2c_probe,
.id_table = tps65090_id_table,
};
static int __init tps65090_init(void)
{
return i2c_add_driver(&tps65090_driver);
}
subsys_initcall(tps65090_init);
| linux-master | drivers/mfd/tps65090.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for TPS65218 Integrated power management chipsets
*
* Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/regmap.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/mutex.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tps65218.h>
#define TPS65218_PASSWORD_REGS_UNLOCK 0x7D
static const struct mfd_cell tps65218_cells[] = {
{
.name = "tps65218-pwrbutton",
.of_compatible = "ti,tps65218-pwrbutton",
},
{
.name = "tps65218-gpio",
.of_compatible = "ti,tps65218-gpio",
},
{ .name = "tps65218-regulator", },
};
/**
* tps65218_reg_write: Write a single tps65218 register.
*
* @tps: Device to write to.
* @reg: Register to write to.
* @val: Value to write.
* @level: Password protected level
*/
int tps65218_reg_write(struct tps65218 *tps, unsigned int reg,
unsigned int val, unsigned int level)
{
int ret;
unsigned int xor_reg_val;
switch (level) {
case TPS65218_PROTECT_NONE:
return regmap_write(tps->regmap, reg, val);
case TPS65218_PROTECT_L1:
xor_reg_val = reg ^ TPS65218_PASSWORD_REGS_UNLOCK;
ret = regmap_write(tps->regmap, TPS65218_REG_PASSWORD,
xor_reg_val);
if (ret < 0)
return ret;
return regmap_write(tps->regmap, reg, val);
default:
return -EINVAL;
}
}
EXPORT_SYMBOL_GPL(tps65218_reg_write);
/**
* tps65218_update_bits: Modify bits w.r.t mask, val and level.
*
* @tps: Device to write to.
* @reg: Register to read-write to.
* @mask: Mask.
* @val: Value to write.
* @level: Password protected level
*/
static int tps65218_update_bits(struct tps65218 *tps, unsigned int reg,
unsigned int mask, unsigned int val, unsigned int level)
{
int ret;
unsigned int data;
ret = regmap_read(tps->regmap, reg, &data);
if (ret) {
dev_err(tps->dev, "Read from reg 0x%x failed\n", reg);
return ret;
}
data &= ~mask;
data |= val & mask;
mutex_lock(&tps->tps_lock);
ret = tps65218_reg_write(tps, reg, data, level);
if (ret)
dev_err(tps->dev, "Write for reg 0x%x failed\n", reg);
mutex_unlock(&tps->tps_lock);
return ret;
}
int tps65218_set_bits(struct tps65218 *tps, unsigned int reg,
unsigned int mask, unsigned int val, unsigned int level)
{
return tps65218_update_bits(tps, reg, mask, val, level);
}
EXPORT_SYMBOL_GPL(tps65218_set_bits);
int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg,
unsigned int mask, unsigned int level)
{
return tps65218_update_bits(tps, reg, mask, 0, level);
}
EXPORT_SYMBOL_GPL(tps65218_clear_bits);
static const struct regmap_range tps65218_yes_ranges[] = {
regmap_reg_range(TPS65218_REG_INT1, TPS65218_REG_INT2),
regmap_reg_range(TPS65218_REG_STATUS, TPS65218_REG_STATUS),
};
static const struct regmap_access_table tps65218_volatile_table = {
.yes_ranges = tps65218_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(tps65218_yes_ranges),
};
static const struct regmap_config tps65218_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.volatile_table = &tps65218_volatile_table,
};
static const struct regmap_irq tps65218_irqs[] = {
/* INT1 IRQs */
[TPS65218_PRGC_IRQ] = {
.mask = TPS65218_INT1_PRGC,
},
[TPS65218_CC_AQC_IRQ] = {
.mask = TPS65218_INT1_CC_AQC,
},
[TPS65218_HOT_IRQ] = {
.mask = TPS65218_INT1_HOT,
},
[TPS65218_PB_IRQ] = {
.mask = TPS65218_INT1_PB,
},
[TPS65218_AC_IRQ] = {
.mask = TPS65218_INT1_AC,
},
[TPS65218_VPRG_IRQ] = {
.mask = TPS65218_INT1_VPRG,
},
[TPS65218_INVALID1_IRQ] = {
},
[TPS65218_INVALID2_IRQ] = {
},
/* INT2 IRQs*/
[TPS65218_LS1_I_IRQ] = {
.mask = TPS65218_INT2_LS1_I,
.reg_offset = 1,
},
[TPS65218_LS2_I_IRQ] = {
.mask = TPS65218_INT2_LS2_I,
.reg_offset = 1,
},
[TPS65218_LS3_I_IRQ] = {
.mask = TPS65218_INT2_LS3_I,
.reg_offset = 1,
},
[TPS65218_LS1_F_IRQ] = {
.mask = TPS65218_INT2_LS1_F,
.reg_offset = 1,
},
[TPS65218_LS2_F_IRQ] = {
.mask = TPS65218_INT2_LS2_F,
.reg_offset = 1,
},
[TPS65218_LS3_F_IRQ] = {
.mask = TPS65218_INT2_LS3_F,
.reg_offset = 1,
},
[TPS65218_INVALID3_IRQ] = {
},
[TPS65218_INVALID4_IRQ] = {
},
};
static struct regmap_irq_chip tps65218_irq_chip = {
.name = "tps65218",
.irqs = tps65218_irqs,
.num_irqs = ARRAY_SIZE(tps65218_irqs),
.num_regs = 2,
.mask_base = TPS65218_REG_INT_MASK1,
.status_base = TPS65218_REG_INT1,
};
static const struct of_device_id of_tps65218_match_table[] = {
{ .compatible = "ti,tps65218", },
{}
};
MODULE_DEVICE_TABLE(of, of_tps65218_match_table);
static int tps65218_voltage_set_strict(struct tps65218 *tps)
{
u32 strict;
if (of_property_read_u32(tps->dev->of_node,
"ti,strict-supply-voltage-supervision",
&strict))
return 0;
if (strict != 0 && strict != 1) {
dev_err(tps->dev,
"Invalid ti,strict-supply-voltage-supervision value\n");
return -EINVAL;
}
tps65218_update_bits(tps, TPS65218_REG_CONFIG1,
TPS65218_CONFIG1_STRICT,
strict ? TPS65218_CONFIG1_STRICT : 0,
TPS65218_PROTECT_L1);
return 0;
}
static int tps65218_voltage_set_uv_hyst(struct tps65218 *tps)
{
u32 hyst;
if (of_property_read_u32(tps->dev->of_node,
"ti,under-voltage-hyst-microvolt", &hyst))
return 0;
if (hyst != 400000 && hyst != 200000) {
dev_err(tps->dev,
"Invalid ti,under-voltage-hyst-microvolt value\n");
return -EINVAL;
}
tps65218_update_bits(tps, TPS65218_REG_CONFIG2,
TPS65218_CONFIG2_UVLOHYS,
hyst == 400000 ? TPS65218_CONFIG2_UVLOHYS : 0,
TPS65218_PROTECT_L1);
return 0;
}
static int tps65218_voltage_set_uvlo(struct tps65218 *tps)
{
u32 uvlo;
int uvloval;
if (of_property_read_u32(tps->dev->of_node,
"ti,under-voltage-limit-microvolt", &uvlo))
return 0;
switch (uvlo) {
case 2750000:
uvloval = TPS65218_CONFIG1_UVLO_2750000;
break;
case 2950000:
uvloval = TPS65218_CONFIG1_UVLO_2950000;
break;
case 3250000:
uvloval = TPS65218_CONFIG1_UVLO_3250000;
break;
case 3350000:
uvloval = TPS65218_CONFIG1_UVLO_3350000;
break;
default:
dev_err(tps->dev,
"Invalid ti,under-voltage-limit-microvolt value\n");
return -EINVAL;
}
tps65218_update_bits(tps, TPS65218_REG_CONFIG1,
TPS65218_CONFIG1_UVLO_MASK, uvloval,
TPS65218_PROTECT_L1);
return 0;
}
static int tps65218_probe(struct i2c_client *client)
{
struct tps65218 *tps;
int ret;
unsigned int chipid;
tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
if (!tps)
return -ENOMEM;
i2c_set_clientdata(client, tps);
tps->dev = &client->dev;
tps->irq = client->irq;
tps->regmap = devm_regmap_init_i2c(client, &tps65218_regmap_config);
if (IS_ERR(tps->regmap)) {
ret = PTR_ERR(tps->regmap);
dev_err(tps->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
mutex_init(&tps->tps_lock);
ret = devm_regmap_add_irq_chip(&client->dev, tps->regmap, tps->irq,
IRQF_ONESHOT, 0, &tps65218_irq_chip,
&tps->irq_data);
if (ret < 0)
return ret;
ret = regmap_read(tps->regmap, TPS65218_REG_CHIPID, &chipid);
if (ret) {
dev_err(tps->dev, "Failed to read chipid: %d\n", ret);
return ret;
}
tps->rev = chipid & TPS65218_CHIPID_REV_MASK;
ret = tps65218_voltage_set_strict(tps);
if (ret)
return ret;
ret = tps65218_voltage_set_uvlo(tps);
if (ret)
return ret;
ret = tps65218_voltage_set_uv_hyst(tps);
if (ret)
return ret;
ret = mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO, tps65218_cells,
ARRAY_SIZE(tps65218_cells), NULL, 0,
regmap_irq_get_domain(tps->irq_data));
return ret;
}
static const struct i2c_device_id tps65218_id_table[] = {
{ "tps65218", TPS65218 },
{ },
};
MODULE_DEVICE_TABLE(i2c, tps65218_id_table);
static struct i2c_driver tps65218_driver = {
.driver = {
.name = "tps65218",
.of_match_table = of_tps65218_match_table,
},
.probe = tps65218_probe,
.id_table = tps65218_id_table,
};
module_i2c_driver(tps65218_driver);
MODULE_AUTHOR("J Keerthy <[email protected]>");
MODULE_DESCRIPTION("TPS65218 chip family multi-function driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/tps65218.c |
// SPDX-License-Identifier: GPL-2.0
/*
* The Gateworks System Controller (GSC) is a multi-function
* device designed for use in Gateworks Single Board Computers.
* The control interface is I2C, with an interrupt. The device supports
* system functions such as push-button monitoring, multiple ADC's for
* voltage and temperature monitoring, fan controller and watchdog monitor.
*
* Copyright (C) 2020 Gateworks Corporation
*/
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/mfd/gsc.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <asm/unaligned.h>
/*
* The GSC suffers from an errata where occasionally during
* ADC cycles the chip can NAK I2C transactions. To ensure we have reliable
* register access we place retries around register access.
*/
#define I2C_RETRIES 3
int gsc_write(void *context, unsigned int reg, unsigned int val)
{
struct i2c_client *client = context;
int retry, ret;
for (retry = 0; retry < I2C_RETRIES; retry++) {
ret = i2c_smbus_write_byte_data(client, reg, val);
/*
* -EAGAIN returned when the i2c host controller is busy
* -EIO returned when i2c device is busy
*/
if (ret != -EAGAIN && ret != -EIO)
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(gsc_write);
int gsc_read(void *context, unsigned int reg, unsigned int *val)
{
struct i2c_client *client = context;
int retry, ret;
for (retry = 0; retry < I2C_RETRIES; retry++) {
ret = i2c_smbus_read_byte_data(client, reg);
/*
* -EAGAIN returned when the i2c host controller is busy
* -EIO returned when i2c device is busy
*/
if (ret != -EAGAIN && ret != -EIO)
break;
}
*val = ret & 0xff;
return 0;
}
EXPORT_SYMBOL_GPL(gsc_read);
/*
* gsc_powerdown - API to use GSC to power down board for a specific time
*
* secs - number of seconds to remain powered off
*/
static int gsc_powerdown(struct gsc_dev *gsc, unsigned long secs)
{
int ret;
unsigned char regs[4];
dev_info(&gsc->i2c->dev, "GSC powerdown for %ld seconds\n",
secs);
put_unaligned_le32(secs, regs);
ret = regmap_bulk_write(gsc->regmap, GSC_TIME_ADD, regs, 4);
if (ret)
return ret;
ret = regmap_update_bits(gsc->regmap, GSC_CTRL_1,
BIT(GSC_CTRL_1_SLEEP_ADD),
BIT(GSC_CTRL_1_SLEEP_ADD));
if (ret)
return ret;
ret = regmap_update_bits(gsc->regmap, GSC_CTRL_1,
BIT(GSC_CTRL_1_SLEEP_ACTIVATE) |
BIT(GSC_CTRL_1_SLEEP_ENABLE),
BIT(GSC_CTRL_1_SLEEP_ACTIVATE) |
BIT(GSC_CTRL_1_SLEEP_ENABLE));
return ret;
}
static ssize_t gsc_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct gsc_dev *gsc = dev_get_drvdata(dev);
const char *name = attr->attr.name;
int rz = 0;
if (strcasecmp(name, "fw_version") == 0)
rz = sprintf(buf, "%d\n", gsc->fwver);
else if (strcasecmp(name, "fw_crc") == 0)
rz = sprintf(buf, "0x%04x\n", gsc->fwcrc);
else
dev_err(dev, "invalid command: '%s'\n", name);
return rz;
}
static ssize_t gsc_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct gsc_dev *gsc = dev_get_drvdata(dev);
const char *name = attr->attr.name;
long value;
if (strcasecmp(name, "powerdown") == 0) {
if (kstrtol(buf, 0, &value) == 0)
gsc_powerdown(gsc, value);
} else {
dev_err(dev, "invalid command: '%s\n", name);
}
return count;
}
static struct device_attribute attr_fwver =
__ATTR(fw_version, 0440, gsc_show, NULL);
static struct device_attribute attr_fwcrc =
__ATTR(fw_crc, 0440, gsc_show, NULL);
static struct device_attribute attr_pwrdown =
__ATTR(powerdown, 0220, NULL, gsc_store);
static struct attribute *gsc_attrs[] = {
&attr_fwver.attr,
&attr_fwcrc.attr,
&attr_pwrdown.attr,
NULL,
};
static struct attribute_group attr_group = {
.attrs = gsc_attrs,
};
static const struct of_device_id gsc_of_match[] = {
{ .compatible = "gw,gsc", },
{ }
};
MODULE_DEVICE_TABLE(of, gsc_of_match);
static struct regmap_bus gsc_regmap_bus = {
.reg_read = gsc_read,
.reg_write = gsc_write,
};
static const struct regmap_config gsc_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.cache_type = REGCACHE_NONE,
.max_register = GSC_WP,
};
static const struct regmap_irq gsc_irqs[] = {
REGMAP_IRQ_REG(GSC_IRQ_PB, 0, BIT(GSC_IRQ_PB)),
REGMAP_IRQ_REG(GSC_IRQ_KEY_ERASED, 0, BIT(GSC_IRQ_KEY_ERASED)),
REGMAP_IRQ_REG(GSC_IRQ_EEPROM_WP, 0, BIT(GSC_IRQ_EEPROM_WP)),
REGMAP_IRQ_REG(GSC_IRQ_RESV, 0, BIT(GSC_IRQ_RESV)),
REGMAP_IRQ_REG(GSC_IRQ_GPIO, 0, BIT(GSC_IRQ_GPIO)),
REGMAP_IRQ_REG(GSC_IRQ_TAMPER, 0, BIT(GSC_IRQ_TAMPER)),
REGMAP_IRQ_REG(GSC_IRQ_WDT_TIMEOUT, 0, BIT(GSC_IRQ_WDT_TIMEOUT)),
REGMAP_IRQ_REG(GSC_IRQ_SWITCH_HOLD, 0, BIT(GSC_IRQ_SWITCH_HOLD)),
};
static const struct regmap_irq_chip gsc_irq_chip = {
.name = "gateworks-gsc",
.irqs = gsc_irqs,
.num_irqs = ARRAY_SIZE(gsc_irqs),
.num_regs = 1,
.status_base = GSC_IRQ_STATUS,
.unmask_base = GSC_IRQ_ENABLE,
.ack_base = GSC_IRQ_STATUS,
.ack_invert = true,
};
static int gsc_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct gsc_dev *gsc;
struct regmap_irq_chip_data *irq_data;
int ret;
unsigned int reg;
gsc = devm_kzalloc(dev, sizeof(*gsc), GFP_KERNEL);
if (!gsc)
return -ENOMEM;
gsc->dev = &client->dev;
gsc->i2c = client;
i2c_set_clientdata(client, gsc);
gsc->regmap = devm_regmap_init(dev, &gsc_regmap_bus, client,
&gsc_regmap_config);
if (IS_ERR(gsc->regmap))
return PTR_ERR(gsc->regmap);
if (regmap_read(gsc->regmap, GSC_FW_VER, ®))
return -EIO;
gsc->fwver = reg;
regmap_read(gsc->regmap, GSC_FW_CRC, ®);
gsc->fwcrc = reg;
regmap_read(gsc->regmap, GSC_FW_CRC + 1, ®);
gsc->fwcrc |= reg << 8;
gsc->i2c_hwmon = devm_i2c_new_dummy_device(dev, client->adapter,
GSC_HWMON);
if (IS_ERR(gsc->i2c_hwmon)) {
dev_err(dev, "Failed to allocate I2C device for HWMON\n");
return PTR_ERR(gsc->i2c_hwmon);
}
ret = devm_regmap_add_irq_chip(dev, gsc->regmap, client->irq,
IRQF_ONESHOT | IRQF_SHARED |
IRQF_TRIGGER_LOW, 0,
&gsc_irq_chip, &irq_data);
if (ret)
return ret;
dev_info(dev, "Gateworks System Controller v%d: fw 0x%04x\n",
gsc->fwver, gsc->fwcrc);
ret = sysfs_create_group(&dev->kobj, &attr_group);
if (ret)
dev_err(dev, "failed to create sysfs attrs\n");
ret = devm_of_platform_populate(dev);
if (ret) {
sysfs_remove_group(&dev->kobj, &attr_group);
return ret;
}
return 0;
}
static void gsc_remove(struct i2c_client *client)
{
sysfs_remove_group(&client->dev.kobj, &attr_group);
}
static struct i2c_driver gsc_driver = {
.driver = {
.name = "gateworks-gsc",
.of_match_table = gsc_of_match,
},
.probe = gsc_probe,
.remove = gsc_remove,
};
module_i2c_driver(gsc_driver);
MODULE_AUTHOR("Tim Harvey <[email protected]>");
MODULE_DESCRIPTION("I2C Core interface for GSC");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/gateworks-gsc.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* cros_ec_dev - expose the Chrome OS Embedded Controller to user-space
*
* Copyright (C) 2014 Google, Inc.
*/
#include <linux/dmi.h>
#include <linux/kconfig.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/platform_data/cros_ec_chardev.h>
#include <linux/platform_data/cros_ec_commands.h>
#include <linux/platform_data/cros_ec_proto.h>
#include <linux/slab.h>
#define DRV_NAME "cros-ec-dev"
static struct class cros_class = {
.name = "chromeos",
};
/**
* struct cros_feature_to_name - CrOS feature id to name/short description.
* @id: The feature identifier.
* @name: Device name associated with the feature id.
* @desc: Short name that will be displayed.
*/
struct cros_feature_to_name {
unsigned int id;
const char *name;
const char *desc;
};
/**
* struct cros_feature_to_cells - CrOS feature id to mfd cells association.
* @id: The feature identifier.
* @mfd_cells: Pointer to the array of mfd cells that needs to be added.
* @num_cells: Number of mfd cells into the array.
*/
struct cros_feature_to_cells {
unsigned int id;
const struct mfd_cell *mfd_cells;
unsigned int num_cells;
};
static const struct cros_feature_to_name cros_mcu_devices[] = {
{
.id = EC_FEATURE_FINGERPRINT,
.name = CROS_EC_DEV_FP_NAME,
.desc = "Fingerprint",
},
{
.id = EC_FEATURE_ISH,
.name = CROS_EC_DEV_ISH_NAME,
.desc = "Integrated Sensor Hub",
},
{
.id = EC_FEATURE_SCP,
.name = CROS_EC_DEV_SCP_NAME,
.desc = "System Control Processor",
},
{
.id = EC_FEATURE_TOUCHPAD,
.name = CROS_EC_DEV_TP_NAME,
.desc = "Touchpad",
},
};
static const struct mfd_cell cros_ec_cec_cells[] = {
{ .name = "cros-ec-cec", },
};
static const struct mfd_cell cros_ec_rtc_cells[] = {
{ .name = "cros-ec-rtc", },
};
static const struct mfd_cell cros_ec_sensorhub_cells[] = {
{ .name = "cros-ec-sensorhub", },
};
static const struct mfd_cell cros_usbpd_charger_cells[] = {
{ .name = "cros-usbpd-charger", },
{ .name = "cros-usbpd-logger", },
};
static const struct mfd_cell cros_usbpd_notify_cells[] = {
{ .name = "cros-usbpd-notify", },
};
static const struct cros_feature_to_cells cros_subdevices[] = {
{
.id = EC_FEATURE_CEC,
.mfd_cells = cros_ec_cec_cells,
.num_cells = ARRAY_SIZE(cros_ec_cec_cells),
},
{
.id = EC_FEATURE_RTC,
.mfd_cells = cros_ec_rtc_cells,
.num_cells = ARRAY_SIZE(cros_ec_rtc_cells),
},
{
.id = EC_FEATURE_USB_PD,
.mfd_cells = cros_usbpd_charger_cells,
.num_cells = ARRAY_SIZE(cros_usbpd_charger_cells),
},
};
static const struct mfd_cell cros_ec_platform_cells[] = {
{ .name = "cros-ec-chardev", },
{ .name = "cros-ec-debugfs", },
{ .name = "cros-ec-sysfs", },
};
static const struct mfd_cell cros_ec_pchg_cells[] = {
{ .name = "cros-ec-pchg", },
};
static const struct mfd_cell cros_ec_lightbar_cells[] = {
{ .name = "cros-ec-lightbar", }
};
static const struct mfd_cell cros_ec_vbc_cells[] = {
{ .name = "cros-ec-vbc", }
};
static void cros_ec_class_release(struct device *dev)
{
kfree(to_cros_ec_dev(dev));
}
static int ec_device_probe(struct platform_device *pdev)
{
int retval = -ENOMEM;
struct device_node *node;
struct device *dev = &pdev->dev;
struct cros_ec_platform *ec_platform = dev_get_platdata(dev);
struct cros_ec_dev *ec = kzalloc(sizeof(*ec), GFP_KERNEL);
struct ec_response_pchg_count pchg_count;
int i;
if (!ec)
return retval;
dev_set_drvdata(dev, ec);
ec->ec_dev = dev_get_drvdata(dev->parent);
ec->dev = dev;
ec->cmd_offset = ec_platform->cmd_offset;
ec->features.flags[0] = -1U; /* Not cached yet */
ec->features.flags[1] = -1U; /* Not cached yet */
device_initialize(&ec->class_dev);
for (i = 0; i < ARRAY_SIZE(cros_mcu_devices); i++) {
/*
* Check whether this is actually a dedicated MCU rather
* than an standard EC.
*/
if (cros_ec_check_features(ec, cros_mcu_devices[i].id)) {
dev_info(dev, "CrOS %s MCU detected\n",
cros_mcu_devices[i].desc);
/*
* Help userspace differentiating ECs from other MCU,
* regardless of the probing order.
*/
ec_platform->ec_name = cros_mcu_devices[i].name;
break;
}
}
/*
* Add the class device
*/
ec->class_dev.class = &cros_class;
ec->class_dev.parent = dev;
ec->class_dev.release = cros_ec_class_release;
retval = dev_set_name(&ec->class_dev, "%s", ec_platform->ec_name);
if (retval) {
dev_err(dev, "dev_set_name failed => %d\n", retval);
goto failed;
}
retval = device_add(&ec->class_dev);
if (retval)
goto failed;
/* check whether this EC is a sensor hub. */
if (cros_ec_get_sensor_count(ec) > 0) {
retval = mfd_add_hotplug_devices(ec->dev,
cros_ec_sensorhub_cells,
ARRAY_SIZE(cros_ec_sensorhub_cells));
if (retval)
dev_err(ec->dev, "failed to add %s subdevice: %d\n",
cros_ec_sensorhub_cells->name, retval);
}
/*
* The following subdevices can be detected by sending the
* EC_FEATURE_GET_CMD Embedded Controller device.
*/
for (i = 0; i < ARRAY_SIZE(cros_subdevices); i++) {
if (cros_ec_check_features(ec, cros_subdevices[i].id)) {
retval = mfd_add_hotplug_devices(ec->dev,
cros_subdevices[i].mfd_cells,
cros_subdevices[i].num_cells);
if (retval)
dev_err(ec->dev,
"failed to add %s subdevice: %d\n",
cros_subdevices[i].mfd_cells->name,
retval);
}
}
/*
* Lightbar is a special case. Newer devices support autodetection,
* but older ones do not.
*/
if (cros_ec_check_features(ec, EC_FEATURE_LIGHTBAR) ||
dmi_match(DMI_PRODUCT_NAME, "Link")) {
retval = mfd_add_hotplug_devices(ec->dev,
cros_ec_lightbar_cells,
ARRAY_SIZE(cros_ec_lightbar_cells));
if (retval)
dev_warn(ec->dev, "failed to add lightbar: %d\n",
retval);
}
/*
* The PD notifier driver cell is separate since it only needs to be
* explicitly added on platforms that don't have the PD notifier ACPI
* device entry defined.
*/
if (IS_ENABLED(CONFIG_OF) && ec->ec_dev->dev->of_node) {
if (cros_ec_check_features(ec, EC_FEATURE_USB_PD)) {
retval = mfd_add_hotplug_devices(ec->dev,
cros_usbpd_notify_cells,
ARRAY_SIZE(cros_usbpd_notify_cells));
if (retval)
dev_err(ec->dev,
"failed to add PD notify devices: %d\n",
retval);
}
}
/*
* The PCHG device cannot be detected by sending EC_FEATURE_GET_CMD, but
* it can be detected by querying the number of peripheral chargers.
*/
retval = cros_ec_cmd(ec->ec_dev, 0, EC_CMD_PCHG_COUNT, NULL, 0,
&pchg_count, sizeof(pchg_count));
if (retval >= 0 && pchg_count.port_count) {
retval = mfd_add_hotplug_devices(ec->dev,
cros_ec_pchg_cells,
ARRAY_SIZE(cros_ec_pchg_cells));
if (retval)
dev_warn(ec->dev, "failed to add pchg: %d\n",
retval);
}
/*
* The following subdevices cannot be detected by sending the
* EC_FEATURE_GET_CMD to the Embedded Controller device.
*/
retval = mfd_add_hotplug_devices(ec->dev, cros_ec_platform_cells,
ARRAY_SIZE(cros_ec_platform_cells));
if (retval)
dev_warn(ec->dev,
"failed to add cros-ec platform devices: %d\n",
retval);
/* Check whether this EC instance has a VBC NVRAM */
node = ec->ec_dev->dev->of_node;
if (of_property_read_bool(node, "google,has-vbc-nvram")) {
retval = mfd_add_hotplug_devices(ec->dev, cros_ec_vbc_cells,
ARRAY_SIZE(cros_ec_vbc_cells));
if (retval)
dev_warn(ec->dev, "failed to add VBC devices: %d\n",
retval);
}
return 0;
failed:
put_device(&ec->class_dev);
return retval;
}
static int ec_device_remove(struct platform_device *pdev)
{
struct cros_ec_dev *ec = dev_get_drvdata(&pdev->dev);
mfd_remove_devices(ec->dev);
device_unregister(&ec->class_dev);
return 0;
}
static const struct platform_device_id cros_ec_id[] = {
{ DRV_NAME, 0 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, cros_ec_id);
static struct platform_driver cros_ec_dev_driver = {
.driver = {
.name = DRV_NAME,
},
.id_table = cros_ec_id,
.probe = ec_device_probe,
.remove = ec_device_remove,
};
static int __init cros_ec_dev_init(void)
{
int ret;
ret = class_register(&cros_class);
if (ret) {
pr_err(CROS_EC_DEV_NAME ": failed to register device class\n");
return ret;
}
/* Register the driver */
ret = platform_driver_register(&cros_ec_dev_driver);
if (ret < 0) {
pr_warn(CROS_EC_DEV_NAME ": can't register driver: %d\n", ret);
goto failed_devreg;
}
return 0;
failed_devreg:
class_unregister(&cros_class);
return ret;
}
static void __exit cros_ec_dev_exit(void)
{
platform_driver_unregister(&cros_ec_dev_driver);
class_unregister(&cros_class);
}
module_init(cros_ec_dev_init);
module_exit(cros_ec_dev_exit);
MODULE_AUTHOR("Bill Richardson <[email protected]>");
MODULE_DESCRIPTION("Userspace interface to the Chrome OS Embedded Controller");
MODULE_VERSION("1.0");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/cros_ec_dev.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for Atmel Flexcom
*
* Copyright (C) 2015 Atmel Corporation
*
* Author: Cyrille Pitchen <[email protected]>
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <dt-bindings/mfd/atmel-flexcom.h>
/* I/O register offsets */
#define FLEX_MR 0x0 /* Mode Register */
#define FLEX_VERSION 0xfc /* Version Register */
/* Mode Register bit fields */
#define FLEX_MR_OPMODE_OFFSET (0) /* Operating Mode */
#define FLEX_MR_OPMODE_MASK (0x3 << FLEX_MR_OPMODE_OFFSET)
#define FLEX_MR_OPMODE(opmode) (((opmode) << FLEX_MR_OPMODE_OFFSET) & \
FLEX_MR_OPMODE_MASK)
struct atmel_flexcom {
void __iomem *base;
u32 opmode;
struct clk *clk;
};
static int atmel_flexcom_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct atmel_flexcom *ddata;
int err;
ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
platform_set_drvdata(pdev, ddata);
err = of_property_read_u32(np, "atmel,flexcom-mode", &ddata->opmode);
if (err)
return err;
if (ddata->opmode < ATMEL_FLEXCOM_MODE_USART ||
ddata->opmode > ATMEL_FLEXCOM_MODE_TWI)
return -EINVAL;
ddata->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(ddata->base))
return PTR_ERR(ddata->base);
ddata->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(ddata->clk))
return PTR_ERR(ddata->clk);
err = clk_prepare_enable(ddata->clk);
if (err)
return err;
/*
* Set the Operating Mode in the Mode Register: only the selected device
* is clocked. Hence, registers of the other serial devices remain
* inaccessible and are read as zero. Also the external I/O lines of the
* Flexcom are muxed to reach the selected device.
*/
writel(FLEX_MR_OPMODE(ddata->opmode), ddata->base + FLEX_MR);
clk_disable_unprepare(ddata->clk);
return devm_of_platform_populate(&pdev->dev);
}
static const struct of_device_id atmel_flexcom_of_match[] = {
{ .compatible = "atmel,sama5d2-flexcom" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, atmel_flexcom_of_match);
static int __maybe_unused atmel_flexcom_resume_noirq(struct device *dev)
{
struct atmel_flexcom *ddata = dev_get_drvdata(dev);
int err;
u32 val;
err = clk_prepare_enable(ddata->clk);
if (err)
return err;
val = FLEX_MR_OPMODE(ddata->opmode),
writel(val, ddata->base + FLEX_MR);
clk_disable_unprepare(ddata->clk);
return 0;
}
static const struct dev_pm_ops __maybe_unused atmel_flexcom_pm_ops = {
.resume_noirq = atmel_flexcom_resume_noirq,
};
static struct platform_driver atmel_flexcom_driver = {
.probe = atmel_flexcom_probe,
.driver = {
.name = "atmel_flexcom",
.pm = pm_ptr(&atmel_flexcom_pm_ops),
.of_match_table = atmel_flexcom_of_match,
},
};
module_platform_driver(atmel_flexcom_driver);
MODULE_AUTHOR("Cyrille Pitchen <[email protected]>");
MODULE_DESCRIPTION("Atmel Flexcom MFD driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/atmel-flexcom.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Device driver for Hi6421 PMIC
*
* Copyright (c) <2011-2014> HiSilicon Technologies Co., Ltd.
* http://www.hisilicon.com
* Copyright (c) <2013-2017> Linaro Ltd.
* https://www.linaro.org
*
* Author: Guodong Xu <[email protected]>
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/mfd/core.h>
#include <linux/mfd/hi6421-pmic.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
static const struct mfd_cell hi6421_devs[] = {
{ .name = "hi6421-regulator", },
};
static const struct mfd_cell hi6421v530_devs[] = {
{ .name = "hi6421v530-regulator", },
};
static const struct regmap_config hi6421_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 8,
.max_register = HI6421_REG_TO_BUS_ADDR(HI6421_REG_MAX),
};
static const struct of_device_id of_hi6421_pmic_match[] = {
{
.compatible = "hisilicon,hi6421-pmic",
.data = (void *)HI6421
},
{
.compatible = "hisilicon,hi6421v530-pmic",
.data = (void *)HI6421_V530
},
{ },
};
MODULE_DEVICE_TABLE(of, of_hi6421_pmic_match);
static int hi6421_pmic_probe(struct platform_device *pdev)
{
struct hi6421_pmic *pmic;
const struct of_device_id *id;
const struct mfd_cell *subdevs;
enum hi6421_type type;
void __iomem *base;
int n_subdevs, ret;
id = of_match_device(of_hi6421_pmic_match, &pdev->dev);
if (!id)
return -EINVAL;
type = (uintptr_t)id->data;
pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
if (!pmic)
return -ENOMEM;
base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(base))
return PTR_ERR(base);
pmic->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
&hi6421_regmap_config);
if (IS_ERR(pmic->regmap)) {
dev_err(&pdev->dev, "Failed to initialise Regmap: %ld\n",
PTR_ERR(pmic->regmap));
return PTR_ERR(pmic->regmap);
}
platform_set_drvdata(pdev, pmic);
switch (type) {
case HI6421:
/* set over-current protection debounce 8ms */
regmap_update_bits(pmic->regmap, HI6421_OCP_DEB_CTRL_REG,
(HI6421_OCP_DEB_SEL_MASK
| HI6421_OCP_EN_DEBOUNCE_MASK
| HI6421_OCP_AUTO_STOP_MASK),
(HI6421_OCP_DEB_SEL_8MS
| HI6421_OCP_EN_DEBOUNCE_ENABLE));
subdevs = hi6421_devs;
n_subdevs = ARRAY_SIZE(hi6421_devs);
break;
case HI6421_V530:
subdevs = hi6421v530_devs;
n_subdevs = ARRAY_SIZE(hi6421v530_devs);
break;
default:
dev_err(&pdev->dev, "Unknown device type %d\n",
(unsigned int)type);
return -EINVAL;
}
ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE,
subdevs, n_subdevs, NULL, 0, NULL);
if (ret) {
dev_err(&pdev->dev, "Failed to add child devices: %d\n", ret);
return ret;
}
return 0;
}
static struct platform_driver hi6421_pmic_driver = {
.driver = {
.name = "hi6421_pmic",
.of_match_table = of_hi6421_pmic_match,
},
.probe = hi6421_pmic_probe,
};
module_platform_driver(hi6421_pmic_driver);
MODULE_AUTHOR("Guodong Xu <[email protected]>");
MODULE_DESCRIPTION("Hi6421 PMIC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/hi6421-pmic-core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Kontron PLD MFD core driver
*
* Copyright (c) 2010-2013 Kontron Europe GmbH
* Author: Michael Brunner <[email protected]>
*/
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/kempld.h>
#include <linux/module.h>
#include <linux/dmi.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/acpi.h>
#define MAX_ID_LEN 4
static char force_device_id[MAX_ID_LEN + 1] = "";
module_param_string(force_device_id, force_device_id,
sizeof(force_device_id), 0);
MODULE_PARM_DESC(force_device_id, "Override detected product");
/*
* Get hardware mutex to block firmware from accessing the pld.
* It is possible for the firmware may hold the mutex for an extended length of
* time. This function will block until access has been granted.
*/
static void kempld_get_hardware_mutex(struct kempld_device_data *pld)
{
/* The mutex bit will read 1 until access has been granted */
while (ioread8(pld->io_index) & KEMPLD_MUTEX_KEY)
usleep_range(1000, 3000);
}
static void kempld_release_hardware_mutex(struct kempld_device_data *pld)
{
/* The harware mutex is released when 1 is written to the mutex bit. */
iowrite8(KEMPLD_MUTEX_KEY, pld->io_index);
}
static int kempld_get_info_generic(struct kempld_device_data *pld)
{
u16 version;
u8 spec;
kempld_get_mutex(pld);
version = kempld_read16(pld, KEMPLD_VERSION);
spec = kempld_read8(pld, KEMPLD_SPEC);
pld->info.buildnr = kempld_read16(pld, KEMPLD_BUILDNR);
pld->info.minor = KEMPLD_VERSION_GET_MINOR(version);
pld->info.major = KEMPLD_VERSION_GET_MAJOR(version);
pld->info.number = KEMPLD_VERSION_GET_NUMBER(version);
pld->info.type = KEMPLD_VERSION_GET_TYPE(version);
if (spec == 0xff) {
pld->info.spec_minor = 0;
pld->info.spec_major = 1;
} else {
pld->info.spec_minor = KEMPLD_SPEC_GET_MINOR(spec);
pld->info.spec_major = KEMPLD_SPEC_GET_MAJOR(spec);
}
if (pld->info.spec_major > 0)
pld->feature_mask = kempld_read16(pld, KEMPLD_FEATURE);
else
pld->feature_mask = 0;
kempld_release_mutex(pld);
return 0;
}
enum kempld_cells {
KEMPLD_I2C = 0,
KEMPLD_WDT,
KEMPLD_GPIO,
KEMPLD_UART,
};
static const char *kempld_dev_names[] = {
[KEMPLD_I2C] = "kempld-i2c",
[KEMPLD_WDT] = "kempld-wdt",
[KEMPLD_GPIO] = "kempld-gpio",
[KEMPLD_UART] = "kempld-uart",
};
#define KEMPLD_MAX_DEVS ARRAY_SIZE(kempld_dev_names)
static int kempld_register_cells_generic(struct kempld_device_data *pld)
{
struct mfd_cell devs[KEMPLD_MAX_DEVS] = {};
int i = 0;
if (pld->feature_mask & KEMPLD_FEATURE_BIT_I2C)
devs[i++].name = kempld_dev_names[KEMPLD_I2C];
if (pld->feature_mask & KEMPLD_FEATURE_BIT_WATCHDOG)
devs[i++].name = kempld_dev_names[KEMPLD_WDT];
if (pld->feature_mask & KEMPLD_FEATURE_BIT_GPIO)
devs[i++].name = kempld_dev_names[KEMPLD_GPIO];
if (pld->feature_mask & KEMPLD_FEATURE_MASK_UART)
devs[i++].name = kempld_dev_names[KEMPLD_UART];
return mfd_add_devices(pld->dev, -1, devs, i, NULL, 0, NULL);
}
static struct resource kempld_ioresource = {
.start = KEMPLD_IOINDEX,
.end = KEMPLD_IODATA,
.flags = IORESOURCE_IO,
};
static const struct kempld_platform_data kempld_platform_data_generic = {
.pld_clock = KEMPLD_CLK,
.ioresource = &kempld_ioresource,
.get_hardware_mutex = kempld_get_hardware_mutex,
.release_hardware_mutex = kempld_release_hardware_mutex,
.get_info = kempld_get_info_generic,
.register_cells = kempld_register_cells_generic,
};
static struct platform_device *kempld_pdev;
static int kempld_create_platform_device(const struct dmi_system_id *id)
{
const struct kempld_platform_data *pdata = id->driver_data;
int ret;
kempld_pdev = platform_device_alloc("kempld", -1);
if (!kempld_pdev)
return -ENOMEM;
ret = platform_device_add_data(kempld_pdev, pdata, sizeof(*pdata));
if (ret)
goto err;
ret = platform_device_add_resources(kempld_pdev, pdata->ioresource, 1);
if (ret)
goto err;
ret = platform_device_add(kempld_pdev);
if (ret)
goto err;
return 0;
err:
platform_device_put(kempld_pdev);
return ret;
}
/**
* kempld_read8 - read 8 bit register
* @pld: kempld_device_data structure describing the PLD
* @index: register index on the chip
*
* kempld_get_mutex must be called prior to calling this function.
*/
u8 kempld_read8(struct kempld_device_data *pld, u8 index)
{
iowrite8(index, pld->io_index);
return ioread8(pld->io_data);
}
EXPORT_SYMBOL_GPL(kempld_read8);
/**
* kempld_write8 - write 8 bit register
* @pld: kempld_device_data structure describing the PLD
* @index: register index on the chip
* @data: new register value
*
* kempld_get_mutex must be called prior to calling this function.
*/
void kempld_write8(struct kempld_device_data *pld, u8 index, u8 data)
{
iowrite8(index, pld->io_index);
iowrite8(data, pld->io_data);
}
EXPORT_SYMBOL_GPL(kempld_write8);
/**
* kempld_read16 - read 16 bit register
* @pld: kempld_device_data structure describing the PLD
* @index: register index on the chip
*
* kempld_get_mutex must be called prior to calling this function.
*/
u16 kempld_read16(struct kempld_device_data *pld, u8 index)
{
return kempld_read8(pld, index) | kempld_read8(pld, index + 1) << 8;
}
EXPORT_SYMBOL_GPL(kempld_read16);
/**
* kempld_write16 - write 16 bit register
* @pld: kempld_device_data structure describing the PLD
* @index: register index on the chip
* @data: new register value
*
* kempld_get_mutex must be called prior to calling this function.
*/
void kempld_write16(struct kempld_device_data *pld, u8 index, u16 data)
{
kempld_write8(pld, index, (u8)data);
kempld_write8(pld, index + 1, (u8)(data >> 8));
}
EXPORT_SYMBOL_GPL(kempld_write16);
/**
* kempld_read32 - read 32 bit register
* @pld: kempld_device_data structure describing the PLD
* @index: register index on the chip
*
* kempld_get_mutex must be called prior to calling this function.
*/
u32 kempld_read32(struct kempld_device_data *pld, u8 index)
{
return kempld_read16(pld, index) | kempld_read16(pld, index + 2) << 16;
}
EXPORT_SYMBOL_GPL(kempld_read32);
/**
* kempld_write32 - write 32 bit register
* @pld: kempld_device_data structure describing the PLD
* @index: register index on the chip
* @data: new register value
*
* kempld_get_mutex must be called prior to calling this function.
*/
void kempld_write32(struct kempld_device_data *pld, u8 index, u32 data)
{
kempld_write16(pld, index, (u16)data);
kempld_write16(pld, index + 2, (u16)(data >> 16));
}
EXPORT_SYMBOL_GPL(kempld_write32);
/**
* kempld_get_mutex - acquire PLD mutex
* @pld: kempld_device_data structure describing the PLD
*/
void kempld_get_mutex(struct kempld_device_data *pld)
{
const struct kempld_platform_data *pdata = dev_get_platdata(pld->dev);
mutex_lock(&pld->lock);
pdata->get_hardware_mutex(pld);
}
EXPORT_SYMBOL_GPL(kempld_get_mutex);
/**
* kempld_release_mutex - release PLD mutex
* @pld: kempld_device_data structure describing the PLD
*/
void kempld_release_mutex(struct kempld_device_data *pld)
{
const struct kempld_platform_data *pdata = dev_get_platdata(pld->dev);
pdata->release_hardware_mutex(pld);
mutex_unlock(&pld->lock);
}
EXPORT_SYMBOL_GPL(kempld_release_mutex);
/**
* kempld_get_info - update device specific information
* @pld: kempld_device_data structure describing the PLD
*
* This function calls the configured board specific kempld_get_info_XXXX
* function which is responsible for gathering information about the specific
* hardware. The information is then stored within the pld structure.
*/
static int kempld_get_info(struct kempld_device_data *pld)
{
int ret;
const struct kempld_platform_data *pdata = dev_get_platdata(pld->dev);
char major, minor;
ret = pdata->get_info(pld);
if (ret)
return ret;
/* The Kontron PLD firmware version string has the following format:
* Pwxy.zzzz
* P: Fixed
* w: PLD number - 1 hex digit
* x: Major version - 1 alphanumerical digit (0-9A-V)
* y: Minor version - 1 alphanumerical digit (0-9A-V)
* zzzz: Build number - 4 zero padded hex digits */
if (pld->info.major < 10)
major = pld->info.major + '0';
else
major = (pld->info.major - 10) + 'A';
if (pld->info.minor < 10)
minor = pld->info.minor + '0';
else
minor = (pld->info.minor - 10) + 'A';
ret = scnprintf(pld->info.version, sizeof(pld->info.version),
"P%X%c%c.%04X", pld->info.number, major, minor,
pld->info.buildnr);
if (ret < 0)
return ret;
return 0;
}
/*
* kempld_register_cells - register cell drivers
*
* This function registers cell drivers for the detected hardware by calling
* the configured kempld_register_cells_XXXX function which is responsible
* to detect and register the needed cell drivers.
*/
static int kempld_register_cells(struct kempld_device_data *pld)
{
const struct kempld_platform_data *pdata = dev_get_platdata(pld->dev);
return pdata->register_cells(pld);
}
static const char *kempld_get_type_string(struct kempld_device_data *pld)
{
const char *version_type;
switch (pld->info.type) {
case 0:
version_type = "release";
break;
case 1:
version_type = "debug";
break;
case 2:
version_type = "custom";
break;
default:
version_type = "unspecified";
break;
}
return version_type;
}
static ssize_t pld_version_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct kempld_device_data *pld = dev_get_drvdata(dev);
return sysfs_emit(buf, "%s\n", pld->info.version);
}
static ssize_t pld_specification_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct kempld_device_data *pld = dev_get_drvdata(dev);
return sysfs_emit(buf, "%d.%d\n", pld->info.spec_major, pld->info.spec_minor);
}
static ssize_t pld_type_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct kempld_device_data *pld = dev_get_drvdata(dev);
return sysfs_emit(buf, "%s\n", kempld_get_type_string(pld));
}
static DEVICE_ATTR_RO(pld_version);
static DEVICE_ATTR_RO(pld_specification);
static DEVICE_ATTR_RO(pld_type);
static struct attribute *pld_attributes[] = {
&dev_attr_pld_version.attr,
&dev_attr_pld_specification.attr,
&dev_attr_pld_type.attr,
NULL
};
static const struct attribute_group pld_attr_group = {
.attrs = pld_attributes,
};
static int kempld_detect_device(struct kempld_device_data *pld)
{
u8 index_reg;
int ret;
mutex_lock(&pld->lock);
/* Check for empty IO space */
index_reg = ioread8(pld->io_index);
if (index_reg == 0xff && ioread8(pld->io_data) == 0xff) {
mutex_unlock(&pld->lock);
return -ENODEV;
}
/* Release hardware mutex if acquired */
if (!(index_reg & KEMPLD_MUTEX_KEY)) {
iowrite8(KEMPLD_MUTEX_KEY, pld->io_index);
/* PXT and COMe-cPC2 boards may require a second release */
iowrite8(KEMPLD_MUTEX_KEY, pld->io_index);
}
mutex_unlock(&pld->lock);
ret = kempld_get_info(pld);
if (ret)
return ret;
dev_info(pld->dev, "Found Kontron PLD - %s (%s), spec %d.%d\n",
pld->info.version, kempld_get_type_string(pld),
pld->info.spec_major, pld->info.spec_minor);
ret = sysfs_create_group(&pld->dev->kobj, &pld_attr_group);
if (ret)
return ret;
ret = kempld_register_cells(pld);
if (ret)
sysfs_remove_group(&pld->dev->kobj, &pld_attr_group);
return ret;
}
#ifdef CONFIG_ACPI
static int kempld_get_acpi_data(struct platform_device *pdev)
{
struct list_head resource_list;
struct resource *resources;
struct resource_entry *rentry;
struct device *dev = &pdev->dev;
struct acpi_device *acpi_dev = ACPI_COMPANION(dev);
const struct kempld_platform_data *pdata;
int ret;
int count;
pdata = acpi_device_get_match_data(dev);
ret = platform_device_add_data(pdev, pdata,
sizeof(struct kempld_platform_data));
if (ret)
return ret;
INIT_LIST_HEAD(&resource_list);
ret = acpi_dev_get_resources(acpi_dev, &resource_list, NULL, NULL);
if (ret < 0)
goto out;
count = ret;
if (count == 0) {
ret = platform_device_add_resources(pdev, pdata->ioresource, 1);
goto out;
}
resources = devm_kcalloc(&acpi_dev->dev, count, sizeof(*resources),
GFP_KERNEL);
if (!resources) {
ret = -ENOMEM;
goto out;
}
count = 0;
list_for_each_entry(rentry, &resource_list, node) {
memcpy(&resources[count], rentry->res,
sizeof(*resources));
count++;
}
ret = platform_device_add_resources(pdev, resources, count);
out:
acpi_dev_free_resource_list(&resource_list);
return ret;
}
#else
static int kempld_get_acpi_data(struct platform_device *pdev)
{
return -ENODEV;
}
#endif /* CONFIG_ACPI */
static int kempld_probe(struct platform_device *pdev)
{
const struct kempld_platform_data *pdata;
struct device *dev = &pdev->dev;
struct kempld_device_data *pld;
struct resource *ioport;
int ret;
if (kempld_pdev == NULL) {
/*
* No kempld_pdev device has been registered in kempld_init,
* so we seem to be probing an ACPI platform device.
*/
ret = kempld_get_acpi_data(pdev);
if (ret)
return ret;
} else if (kempld_pdev != pdev) {
/*
* The platform device we are probing is not the one we
* registered in kempld_init using the DMI table, so this one
* comes from ACPI.
* As we can only probe one - abort here and use the DMI
* based one instead.
*/
dev_notice(dev, "platform device exists - not using ACPI\n");
return -ENODEV;
}
pdata = dev_get_platdata(dev);
pld = devm_kzalloc(dev, sizeof(*pld), GFP_KERNEL);
if (!pld)
return -ENOMEM;
ioport = platform_get_resource(pdev, IORESOURCE_IO, 0);
if (!ioport)
return -EINVAL;
pld->io_base = devm_ioport_map(dev, ioport->start,
resource_size(ioport));
if (!pld->io_base)
return -ENOMEM;
pld->io_index = pld->io_base;
pld->io_data = pld->io_base + 1;
pld->pld_clock = pdata->pld_clock;
pld->dev = dev;
mutex_init(&pld->lock);
platform_set_drvdata(pdev, pld);
return kempld_detect_device(pld);
}
static int kempld_remove(struct platform_device *pdev)
{
struct kempld_device_data *pld = platform_get_drvdata(pdev);
const struct kempld_platform_data *pdata = dev_get_platdata(pld->dev);
sysfs_remove_group(&pld->dev->kobj, &pld_attr_group);
mfd_remove_devices(&pdev->dev);
pdata->release_hardware_mutex(pld);
return 0;
}
#ifdef CONFIG_ACPI
static const struct acpi_device_id kempld_acpi_table[] = {
{ "KEM0000", (kernel_ulong_t)&kempld_platform_data_generic },
{ "KEM0001", (kernel_ulong_t)&kempld_platform_data_generic },
{}
};
MODULE_DEVICE_TABLE(acpi, kempld_acpi_table);
#endif
static struct platform_driver kempld_driver = {
.driver = {
.name = "kempld",
.acpi_match_table = ACPI_PTR(kempld_acpi_table),
},
.probe = kempld_probe,
.remove = kempld_remove,
};
static const struct dmi_system_id kempld_dmi_table[] __initconst = {
{
.ident = "BBD6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-bBD"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "BBL6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-bBL6"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "BDV7",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-bDV7"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "BHL6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-bHL6"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "BKL6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-bKL6"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "BSL6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-bSL6"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CAL6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-cAL"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CBL6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-cBL6"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CBW6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-cBW6"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CCR2",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-bIP2"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CCR6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-bIP6"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CDV7",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-cDV7"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CHL6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-cHL6"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CHR2",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "ETXexpress-SC T2"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CHR2",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "ETXe-SC T2"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CHR2",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-bSC2"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CHR6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "ETXexpress-SC T6"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CHR6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "ETXe-SC T6"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CHR6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-bSC6"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CKL6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-cKL6"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CNTG",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "ETXexpress-PC"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CNTG",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-bPC2"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CNTX",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "PXT"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CSL6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-cSL6"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "CVV6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-cBT"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "FRI2",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "FRI2",
.matches = {
DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "A203",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "KBox A-203"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "M4A1",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-m4AL"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "MAL1",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-mAL10"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "MAPL",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "mITX-APL"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "MBR1",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "ETX-OH"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "MVV1",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-mBT"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "NTC1",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "NTC1",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "nETXe-TT"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "NTC1",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "NUP1",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-mCT"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "PAPL",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "pITX-APL"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "SXAL",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "SMARC-sXAL"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "SXAL4",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "SMARC-sXA4"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "UNP1",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "microETXexpress-DC"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "UNP1",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-cDC2"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "UNTG",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "microETXexpress-PC"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "UNTG",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-cPC2"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "UUP6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-cCT6"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "UTH6",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "COMe-cTH6"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
}, {
.ident = "Q7AL",
.matches = {
DMI_MATCH(DMI_BOARD_VENDOR, "Kontron"),
DMI_MATCH(DMI_BOARD_NAME, "Qseven-Q7AL"),
},
.driver_data = (void *)&kempld_platform_data_generic,
.callback = kempld_create_platform_device,
},
{}
};
MODULE_DEVICE_TABLE(dmi, kempld_dmi_table);
static int __init kempld_init(void)
{
const struct dmi_system_id *id;
if (force_device_id[0]) {
for (id = kempld_dmi_table;
id->matches[0].slot != DMI_NONE; id++)
if (strstr(id->ident, force_device_id))
if (id->callback && !id->callback(id))
break;
if (id->matches[0].slot == DMI_NONE)
return -ENODEV;
} else {
dmi_check_system(kempld_dmi_table);
}
return platform_driver_register(&kempld_driver);
}
static void __exit kempld_exit(void)
{
if (kempld_pdev)
platform_device_unregister(kempld_pdev);
platform_driver_unregister(&kempld_driver);
}
module_init(kempld_init);
module_exit(kempld_exit);
MODULE_DESCRIPTION("KEM PLD Core Driver");
MODULE_AUTHOR("Michael Brunner <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:kempld-core");
| linux-master | drivers/mfd/kempld-core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* wm831x-auxadc.c -- AUXADC for Wolfson WM831x PMICs
*
* Copyright 2009-2011 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/mfd/core.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/mfd/wm831x/core.h>
#include <linux/mfd/wm831x/pdata.h>
#include <linux/mfd/wm831x/irq.h>
#include <linux/mfd/wm831x/auxadc.h>
#include <linux/mfd/wm831x/otp.h>
#include <linux/mfd/wm831x/regulator.h>
struct wm831x_auxadc_req {
struct list_head list;
enum wm831x_auxadc input;
int val;
struct completion done;
};
static int wm831x_auxadc_read_irq(struct wm831x *wm831x,
enum wm831x_auxadc input)
{
struct wm831x_auxadc_req *req;
int ret;
bool ena = false;
req = kzalloc(sizeof(*req), GFP_KERNEL);
if (!req)
return -ENOMEM;
init_completion(&req->done);
req->input = input;
req->val = -ETIMEDOUT;
mutex_lock(&wm831x->auxadc_lock);
/* Enqueue the request */
list_add(&req->list, &wm831x->auxadc_pending);
ena = !wm831x->auxadc_active;
if (ena) {
ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
WM831X_AUX_ENA, WM831X_AUX_ENA);
if (ret != 0) {
dev_err(wm831x->dev, "Failed to enable AUXADC: %d\n",
ret);
goto out;
}
}
/* Enable the conversion if not already running */
if (!(wm831x->auxadc_active & (1 << input))) {
ret = wm831x_set_bits(wm831x, WM831X_AUXADC_SOURCE,
1 << input, 1 << input);
if (ret != 0) {
dev_err(wm831x->dev,
"Failed to set AUXADC source: %d\n", ret);
goto out;
}
wm831x->auxadc_active |= 1 << input;
}
/* We convert at the fastest rate possible */
if (ena) {
ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
WM831X_AUX_CVT_ENA |
WM831X_AUX_RATE_MASK,
WM831X_AUX_CVT_ENA |
WM831X_AUX_RATE_MASK);
if (ret != 0) {
dev_err(wm831x->dev, "Failed to start AUXADC: %d\n",
ret);
goto out;
}
}
mutex_unlock(&wm831x->auxadc_lock);
/* Wait for an interrupt */
wait_for_completion_timeout(&req->done, msecs_to_jiffies(500));
mutex_lock(&wm831x->auxadc_lock);
ret = req->val;
out:
list_del(&req->list);
mutex_unlock(&wm831x->auxadc_lock);
kfree(req);
return ret;
}
static irqreturn_t wm831x_auxadc_irq(int irq, void *irq_data)
{
struct wm831x *wm831x = irq_data;
struct wm831x_auxadc_req *req;
int ret, input, val;
ret = wm831x_reg_read(wm831x, WM831X_AUXADC_DATA);
if (ret < 0) {
dev_err(wm831x->dev,
"Failed to read AUXADC data: %d\n", ret);
return IRQ_NONE;
}
input = ((ret & WM831X_AUX_DATA_SRC_MASK)
>> WM831X_AUX_DATA_SRC_SHIFT) - 1;
if (input == 14)
input = WM831X_AUX_CAL;
val = ret & WM831X_AUX_DATA_MASK;
mutex_lock(&wm831x->auxadc_lock);
/* Disable this conversion, we're about to complete all users */
wm831x_set_bits(wm831x, WM831X_AUXADC_SOURCE,
1 << input, 0);
wm831x->auxadc_active &= ~(1 << input);
/* Turn off the entire convertor if idle */
if (!wm831x->auxadc_active)
wm831x_reg_write(wm831x, WM831X_AUXADC_CONTROL, 0);
/* Wake up any threads waiting for this request */
list_for_each_entry(req, &wm831x->auxadc_pending, list) {
if (req->input == input) {
req->val = val;
complete(&req->done);
}
}
mutex_unlock(&wm831x->auxadc_lock);
return IRQ_HANDLED;
}
static int wm831x_auxadc_read_polled(struct wm831x *wm831x,
enum wm831x_auxadc input)
{
int ret, src, timeout;
mutex_lock(&wm831x->auxadc_lock);
ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
WM831X_AUX_ENA, WM831X_AUX_ENA);
if (ret < 0) {
dev_err(wm831x->dev, "Failed to enable AUXADC: %d\n", ret);
goto out;
}
/* We force a single source at present */
src = input;
ret = wm831x_reg_write(wm831x, WM831X_AUXADC_SOURCE,
1 << src);
if (ret < 0) {
dev_err(wm831x->dev, "Failed to set AUXADC source: %d\n", ret);
goto out;
}
ret = wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL,
WM831X_AUX_CVT_ENA, WM831X_AUX_CVT_ENA);
if (ret < 0) {
dev_err(wm831x->dev, "Failed to start AUXADC: %d\n", ret);
goto disable;
}
/* If we're not using interrupts then poll the
* interrupt status register */
timeout = 5;
while (timeout) {
msleep(1);
ret = wm831x_reg_read(wm831x,
WM831X_INTERRUPT_STATUS_1);
if (ret < 0) {
dev_err(wm831x->dev,
"ISR 1 read failed: %d\n", ret);
goto disable;
}
/* Did it complete? */
if (ret & WM831X_AUXADC_DATA_EINT) {
wm831x_reg_write(wm831x,
WM831X_INTERRUPT_STATUS_1,
WM831X_AUXADC_DATA_EINT);
break;
} else {
dev_err(wm831x->dev,
"AUXADC conversion timeout\n");
ret = -EBUSY;
goto disable;
}
}
ret = wm831x_reg_read(wm831x, WM831X_AUXADC_DATA);
if (ret < 0) {
dev_err(wm831x->dev,
"Failed to read AUXADC data: %d\n", ret);
goto disable;
}
src = ((ret & WM831X_AUX_DATA_SRC_MASK)
>> WM831X_AUX_DATA_SRC_SHIFT) - 1;
if (src == 14)
src = WM831X_AUX_CAL;
if (src != input) {
dev_err(wm831x->dev, "Data from source %d not %d\n",
src, input);
ret = -EINVAL;
} else {
ret &= WM831X_AUX_DATA_MASK;
}
disable:
wm831x_set_bits(wm831x, WM831X_AUXADC_CONTROL, WM831X_AUX_ENA, 0);
out:
mutex_unlock(&wm831x->auxadc_lock);
return ret;
}
/**
* wm831x_auxadc_read: Read a value from the WM831x AUXADC
*
* @wm831x: Device to read from.
* @input: AUXADC input to read.
*/
int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input)
{
return wm831x->auxadc_read(wm831x, input);
}
EXPORT_SYMBOL_GPL(wm831x_auxadc_read);
/**
* wm831x_auxadc_read_uv: Read a voltage from the WM831x AUXADC
*
* @wm831x: Device to read from.
* @input: AUXADC input to read.
*/
int wm831x_auxadc_read_uv(struct wm831x *wm831x, enum wm831x_auxadc input)
{
int ret;
ret = wm831x_auxadc_read(wm831x, input);
if (ret < 0)
return ret;
ret *= 1465;
return ret;
}
EXPORT_SYMBOL_GPL(wm831x_auxadc_read_uv);
void wm831x_auxadc_init(struct wm831x *wm831x)
{
int ret;
mutex_init(&wm831x->auxadc_lock);
INIT_LIST_HEAD(&wm831x->auxadc_pending);
if (wm831x->irq) {
wm831x->auxadc_read = wm831x_auxadc_read_irq;
ret = request_threaded_irq(wm831x_irq(wm831x,
WM831X_IRQ_AUXADC_DATA),
NULL, wm831x_auxadc_irq,
IRQF_ONESHOT,
"auxadc", wm831x);
if (ret < 0) {
dev_err(wm831x->dev, "AUXADC IRQ request failed: %d\n",
ret);
wm831x->auxadc_read = NULL;
}
}
if (!wm831x->auxadc_read)
wm831x->auxadc_read = wm831x_auxadc_read_polled;
}
| linux-master | drivers/mfd/wm831x-auxadc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* MFD driver for twl4030 audio submodule, which contains an audio codec, and
* the vibra control.
*
* Author: Peter Ujfalusi <[email protected]>
*
* Copyright: (C) 2009 Nokia Corporation
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/mfd/twl.h>
#include <linux/mfd/core.h>
#include <linux/mfd/twl4030-audio.h>
#define TWL4030_AUDIO_CELLS 2
static struct platform_device *twl4030_audio_dev;
struct twl4030_audio_resource {
int request_count;
u8 reg;
u8 mask;
};
struct twl4030_audio {
unsigned int audio_mclk;
struct mutex mutex;
struct twl4030_audio_resource resource[TWL4030_AUDIO_RES_MAX];
struct mfd_cell cells[TWL4030_AUDIO_CELLS];
};
/*
* Modify the resource, the function returns the content of the register
* after the modification.
*/
static int twl4030_audio_set_resource(enum twl4030_audio_res id, int enable)
{
struct twl4030_audio *audio = platform_get_drvdata(twl4030_audio_dev);
u8 val;
twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val,
audio->resource[id].reg);
if (enable)
val |= audio->resource[id].mask;
else
val &= ~audio->resource[id].mask;
twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
val, audio->resource[id].reg);
return val;
}
static inline int twl4030_audio_get_resource(enum twl4030_audio_res id)
{
struct twl4030_audio *audio = platform_get_drvdata(twl4030_audio_dev);
u8 val;
twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val,
audio->resource[id].reg);
return val;
}
/*
* Enable the resource.
* The function returns with error or the content of the register
*/
int twl4030_audio_enable_resource(enum twl4030_audio_res id)
{
struct twl4030_audio *audio = platform_get_drvdata(twl4030_audio_dev);
int val;
if (id >= TWL4030_AUDIO_RES_MAX) {
dev_err(&twl4030_audio_dev->dev,
"Invalid resource ID (%u)\n", id);
return -EINVAL;
}
mutex_lock(&audio->mutex);
if (!audio->resource[id].request_count)
/* Resource was disabled, enable it */
val = twl4030_audio_set_resource(id, 1);
else
val = twl4030_audio_get_resource(id);
audio->resource[id].request_count++;
mutex_unlock(&audio->mutex);
return val;
}
EXPORT_SYMBOL_GPL(twl4030_audio_enable_resource);
/*
* Disable the resource.
* The function returns with error or the content of the register
*/
int twl4030_audio_disable_resource(enum twl4030_audio_res id)
{
struct twl4030_audio *audio = platform_get_drvdata(twl4030_audio_dev);
int val;
if (id >= TWL4030_AUDIO_RES_MAX) {
dev_err(&twl4030_audio_dev->dev,
"Invalid resource ID (%u)\n", id);
return -EINVAL;
}
mutex_lock(&audio->mutex);
if (!audio->resource[id].request_count) {
dev_err(&twl4030_audio_dev->dev,
"Resource has been disabled already (%u)\n", id);
mutex_unlock(&audio->mutex);
return -EPERM;
}
audio->resource[id].request_count--;
if (!audio->resource[id].request_count)
/* Resource can be disabled now */
val = twl4030_audio_set_resource(id, 0);
else
val = twl4030_audio_get_resource(id);
mutex_unlock(&audio->mutex);
return val;
}
EXPORT_SYMBOL_GPL(twl4030_audio_disable_resource);
unsigned int twl4030_audio_get_mclk(void)
{
struct twl4030_audio *audio = platform_get_drvdata(twl4030_audio_dev);
return audio->audio_mclk;
}
EXPORT_SYMBOL_GPL(twl4030_audio_get_mclk);
static bool twl4030_audio_has_codec(struct twl4030_audio_data *pdata,
struct device_node *parent)
{
struct device_node *node;
if (pdata && pdata->codec)
return true;
node = of_get_child_by_name(parent, "codec");
if (node) {
of_node_put(node);
return true;
}
return false;
}
static bool twl4030_audio_has_vibra(struct twl4030_audio_data *pdata,
struct device_node *node)
{
int vibra;
if (pdata && pdata->vibra)
return true;
if (!of_property_read_u32(node, "ti,enable-vibra", &vibra) && vibra)
return true;
return false;
}
static int twl4030_audio_probe(struct platform_device *pdev)
{
struct twl4030_audio *audio;
struct twl4030_audio_data *pdata = dev_get_platdata(&pdev->dev);
struct device_node *node = pdev->dev.of_node;
struct mfd_cell *cell = NULL;
int ret, childs = 0;
u8 val;
if (!pdata && !node) {
dev_err(&pdev->dev, "Platform data is missing\n");
return -EINVAL;
}
audio = devm_kzalloc(&pdev->dev, sizeof(struct twl4030_audio),
GFP_KERNEL);
if (!audio)
return -ENOMEM;
mutex_init(&audio->mutex);
audio->audio_mclk = twl_get_hfclk_rate();
/* Configure APLL_INFREQ and disable APLL if enabled */
switch (audio->audio_mclk) {
case 19200000:
val = TWL4030_APLL_INFREQ_19200KHZ;
break;
case 26000000:
val = TWL4030_APLL_INFREQ_26000KHZ;
break;
case 38400000:
val = TWL4030_APLL_INFREQ_38400KHZ;
break;
default:
dev_err(&pdev->dev, "Invalid audio_mclk\n");
return -EINVAL;
}
twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, val, TWL4030_REG_APLL_CTL);
/* Codec power */
audio->resource[TWL4030_AUDIO_RES_POWER].reg = TWL4030_REG_CODEC_MODE;
audio->resource[TWL4030_AUDIO_RES_POWER].mask = TWL4030_CODECPDZ;
/* PLL */
audio->resource[TWL4030_AUDIO_RES_APLL].reg = TWL4030_REG_APLL_CTL;
audio->resource[TWL4030_AUDIO_RES_APLL].mask = TWL4030_APLL_EN;
if (twl4030_audio_has_codec(pdata, node)) {
cell = &audio->cells[childs];
cell->name = "twl4030-codec";
if (pdata) {
cell->platform_data = pdata->codec;
cell->pdata_size = sizeof(*pdata->codec);
}
childs++;
}
if (twl4030_audio_has_vibra(pdata, node)) {
cell = &audio->cells[childs];
cell->name = "twl4030-vibra";
if (pdata) {
cell->platform_data = pdata->vibra;
cell->pdata_size = sizeof(*pdata->vibra);
}
childs++;
}
platform_set_drvdata(pdev, audio);
twl4030_audio_dev = pdev;
if (childs)
ret = mfd_add_devices(&pdev->dev, pdev->id, audio->cells,
childs, NULL, 0, NULL);
else {
dev_err(&pdev->dev, "No platform data found for childs\n");
ret = -ENODEV;
}
if (ret)
twl4030_audio_dev = NULL;
return ret;
}
static int twl4030_audio_remove(struct platform_device *pdev)
{
mfd_remove_devices(&pdev->dev);
twl4030_audio_dev = NULL;
return 0;
}
static const struct of_device_id twl4030_audio_of_match[] = {
{.compatible = "ti,twl4030-audio", },
{ },
};
MODULE_DEVICE_TABLE(of, twl4030_audio_of_match);
static struct platform_driver twl4030_audio_driver = {
.driver = {
.name = "twl4030-audio",
.of_match_table = twl4030_audio_of_match,
},
.probe = twl4030_audio_probe,
.remove = twl4030_audio_remove,
};
module_platform_driver(twl4030_audio_driver);
MODULE_AUTHOR("Peter Ujfalusi <[email protected]>");
MODULE_DESCRIPTION("TWL4030 audio block MFD driver");
MODULE_ALIAS("platform:twl4030-audio");
| linux-master | drivers/mfd/twl4030-audio.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* wm5102-tables.c -- WM5102 data tables
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/registers.h>
#include "arizona.h"
#define WM5102_NUM_AOD_ISR 2
#define WM5102_NUM_ISR 5
static const struct reg_sequence wm5102_reva_patch[] = {
{ 0x80, 0x0003 },
{ 0x221, 0x0090 },
{ 0x211, 0x0014 },
{ 0x212, 0x0000 },
{ 0x214, 0x000C },
{ 0x171, 0x0002 },
{ 0x171, 0x0000 },
{ 0x461, 0x8000 },
{ 0x463, 0x50F0 },
{ 0x465, 0x4820 },
{ 0x467, 0x4040 },
{ 0x469, 0x3940 },
{ 0x46B, 0x3310 },
{ 0x46D, 0x2D80 },
{ 0x46F, 0x2890 },
{ 0x471, 0x1990 },
{ 0x473, 0x1450 },
{ 0x475, 0x1020 },
{ 0x477, 0x0CD0 },
{ 0x479, 0x0A30 },
{ 0x47B, 0x0810 },
{ 0x47D, 0x0510 },
{ 0x4D1, 0x017F },
{ 0x500, 0x000D },
{ 0x507, 0x1820 },
{ 0x508, 0x1820 },
{ 0x540, 0x000D },
{ 0x547, 0x1820 },
{ 0x548, 0x1820 },
{ 0x580, 0x000D },
{ 0x587, 0x1820 },
{ 0x588, 0x1820 },
{ 0x80, 0x0000 },
};
static const struct reg_sequence wm5102_revb_patch[] = {
{ 0x19, 0x0001 },
{ 0x80, 0x0003 },
{ 0x081, 0xE022 },
{ 0x410, 0x6080 },
{ 0x418, 0xa080 },
{ 0x420, 0xa080 },
{ 0x428, 0xe000 },
{ 0x442, 0x3F0A },
{ 0x443, 0xDC1F },
{ 0x4B0, 0x0066 },
{ 0x458, 0x000b },
{ 0x212, 0x0000 },
{ 0x171, 0x0000 },
{ 0x35E, 0x000C },
{ 0x2D4, 0x0000 },
{ 0x4DC, 0x0900 },
{ 0x80, 0x0000 },
};
/* We use a function so we can use ARRAY_SIZE() */
int wm5102_patch(struct arizona *arizona)
{
const struct reg_sequence *wm5102_patch;
int patch_size;
switch (arizona->rev) {
case 0:
wm5102_patch = wm5102_reva_patch;
patch_size = ARRAY_SIZE(wm5102_reva_patch);
break;
default:
wm5102_patch = wm5102_revb_patch;
patch_size = ARRAY_SIZE(wm5102_revb_patch);
}
return regmap_multi_reg_write_bypassed(arizona->regmap,
wm5102_patch,
patch_size);
}
static const struct regmap_irq wm5102_aod_irqs[ARIZONA_NUM_IRQ] = {
[ARIZONA_IRQ_MICD_CLAMP_FALL] = {
.mask = ARIZONA_MICD_CLAMP_FALL_EINT1
},
[ARIZONA_IRQ_MICD_CLAMP_RISE] = {
.mask = ARIZONA_MICD_CLAMP_RISE_EINT1
},
[ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 },
[ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 },
[ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 },
[ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 },
};
const struct regmap_irq_chip wm5102_aod = {
.name = "wm5102 AOD",
.status_base = ARIZONA_AOD_IRQ1,
.mask_base = ARIZONA_AOD_IRQ_MASK_IRQ1,
.ack_base = ARIZONA_AOD_IRQ1,
.wake_base = ARIZONA_WAKE_CONTROL,
.wake_invert = 1,
.num_regs = 1,
.irqs = wm5102_aod_irqs,
.num_irqs = ARRAY_SIZE(wm5102_aod_irqs),
};
static const struct regmap_irq wm5102_irqs[ARIZONA_NUM_IRQ] = {
[ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
[ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
[ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
[ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
[ARIZONA_IRQ_DSP1_RAM_RDY] = {
.reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
},
[ARIZONA_IRQ_DSP_IRQ2] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
},
[ARIZONA_IRQ_DSP_IRQ1] = {
.reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT_WARN] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
},
[ARIZONA_IRQ_SPK_OVERHEAT] = {
.reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
},
[ARIZONA_IRQ_HPDET] = {
.reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
},
[ARIZONA_IRQ_MICDET] = {
.reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
},
[ARIZONA_IRQ_WSEQ_DONE] = {
.reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
},
[ARIZONA_IRQ_DRC2_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1
},
[ARIZONA_IRQ_DRC1_SIG_DET] = {
.reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
},
[ARIZONA_IRQ_ASRC2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1
},
[ARIZONA_IRQ_ASRC1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1
},
[ARIZONA_IRQ_UNDERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1
},
[ARIZONA_IRQ_OVERCLOCKED] = {
.reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1
},
[ARIZONA_IRQ_FLL2_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
},
[ARIZONA_IRQ_FLL1_LOCK] = {
.reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1
},
[ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = {
.reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1
},
[ARIZONA_IRQ_ASRC_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1
},
[ARIZONA_IRQ_AIF3_ERR] = {
.reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1
},
[ARIZONA_IRQ_AIF2_ERR] = {
.reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1
},
[ARIZONA_IRQ_AIF1_ERR] = {
.reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1
},
[ARIZONA_IRQ_CTRLIF_ERR] = {
.reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1
},
[ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = {
.reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1
},
[ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_SYSCLK_ENA_LOW] = {
.reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1
},
[ARIZONA_IRQ_ISRC1_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1
},
[ARIZONA_IRQ_ISRC2_CFG_ERR] = {
.reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1
},
[ARIZONA_IRQ_BOOT_DONE] = {
.reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1
},
[ARIZONA_IRQ_DCS_DAC_DONE] = {
.reg_offset = 4, .mask = ARIZONA_DCS_DAC_DONE_EINT1
},
[ARIZONA_IRQ_DCS_HP_DONE] = {
.reg_offset = 4, .mask = ARIZONA_DCS_HP_DONE_EINT1
},
[ARIZONA_IRQ_FLL2_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1
},
[ARIZONA_IRQ_FLL1_CLOCK_OK] = {
.reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1
},
};
const struct regmap_irq_chip wm5102_irq = {
.name = "wm5102 IRQ",
.status_base = ARIZONA_INTERRUPT_STATUS_1,
.mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK,
.ack_base = ARIZONA_INTERRUPT_STATUS_1,
.num_regs = 5,
.irqs = wm5102_irqs,
.num_irqs = ARRAY_SIZE(wm5102_irqs),
};
static const struct reg_default wm5102_reg_default[] = {
{ 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */
{ 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */
{ 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */
{ 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */
{ 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */
{ 0x00000023, 0x1000 }, /* R35 - Tone Generator 4 */
{ 0x00000024, 0x0000 }, /* R36 - Tone Generator 5 */
{ 0x00000030, 0x0000 }, /* R48 - PWM Drive 1 */
{ 0x00000031, 0x0100 }, /* R49 - PWM Drive 2 */
{ 0x00000032, 0x0100 }, /* R50 - PWM Drive 3 */
{ 0x00000040, 0x0000 }, /* R64 - Wake control */
{ 0x00000041, 0x0000 }, /* R65 - Sequence control */
{ 0x00000061, 0x01FF }, /* R97 - Sample Rate Sequence Select 1 */
{ 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */
{ 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */
{ 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */
{ 0x00000066, 0x01FF }, /* R102 - Always On Triggers Sequence Select 1 */
{ 0x00000067, 0x01FF }, /* R103 - Always On Triggers Sequence Select 2 */
{ 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 3 */
{ 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 4 */
{ 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 5 */
{ 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 6 */
{ 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */
{ 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */
{ 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */
{ 0x00000092, 0x0000 }, /* R146 - Haptics phase 1 intensity */
{ 0x00000093, 0x0000 }, /* R147 - Haptics phase 1 duration */
{ 0x00000094, 0x0000 }, /* R148 - Haptics phase 2 intensity */
{ 0x00000095, 0x0000 }, /* R149 - Haptics phase 2 duration */
{ 0x00000096, 0x0000 }, /* R150 - Haptics phase 3 intensity */
{ 0x00000097, 0x0000 }, /* R151 - Haptics phase 3 duration */
{ 0x00000100, 0x0002 }, /* R256 - Clock 32k 1 */
{ 0x00000101, 0x0304 }, /* R257 - System Clock 1 */
{ 0x00000102, 0x0011 }, /* R258 - Sample rate 1 */
{ 0x00000103, 0x0011 }, /* R259 - Sample rate 2 */
{ 0x00000104, 0x0011 }, /* R260 - Sample rate 3 */
{ 0x00000112, 0x0305 }, /* R274 - Async clock 1 */
{ 0x00000113, 0x0011 }, /* R275 - Async sample rate 1 */
{ 0x00000114, 0x0011 }, /* R276 - Async sample rate 2 */
{ 0x00000149, 0x0000 }, /* R329 - Output system clock */
{ 0x0000014A, 0x0000 }, /* R330 - Output async clock */
{ 0x00000152, 0x0000 }, /* R338 - Rate Estimator 1 */
{ 0x00000153, 0x0000 }, /* R339 - Rate Estimator 2 */
{ 0x00000154, 0x0000 }, /* R340 - Rate Estimator 3 */
{ 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */
{ 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */
{ 0x00000161, 0x0000 }, /* R353 - Dynamic Frequency Scaling 1 */
{ 0x00000171, 0x0000 }, /* R369 - FLL1 Control 1 */
{ 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */
{ 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */
{ 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */
{ 0x00000175, 0x0004 }, /* R373 - FLL1 Control 5 */
{ 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */
{ 0x00000179, 0x0000 }, /* R377 - FLL1 Control 7 */
{ 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */
{ 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */
{ 0x00000183, 0x0000 }, /* R387 - FLL1 Synchroniser 3 */
{ 0x00000184, 0x0000 }, /* R388 - FLL1 Synchroniser 4 */
{ 0x00000185, 0x0000 }, /* R389 - FLL1 Synchroniser 5 */
{ 0x00000186, 0x0000 }, /* R390 - FLL1 Synchroniser 6 */
{ 0x00000187, 0x0001 }, /* R391 - FLL1 Synchroniser 7 */
{ 0x00000189, 0x0000 }, /* R393 - FLL1 Spread Spectrum */
{ 0x0000018A, 0x0004 }, /* R394 - FLL1 GPIO Clock */
{ 0x00000191, 0x0000 }, /* R401 - FLL2 Control 1 */
{ 0x00000192, 0x0008 }, /* R402 - FLL2 Control 2 */
{ 0x00000193, 0x0018 }, /* R403 - FLL2 Control 3 */
{ 0x00000194, 0x007D }, /* R404 - FLL2 Control 4 */
{ 0x00000195, 0x0004 }, /* R405 - FLL2 Control 5 */
{ 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */
{ 0x00000199, 0x0000 }, /* R409 - FLL2 Control 7 */
{ 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */
{ 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */
{ 0x000001A3, 0x0000 }, /* R419 - FLL2 Synchroniser 3 */
{ 0x000001A4, 0x0000 }, /* R420 - FLL2 Synchroniser 4 */
{ 0x000001A5, 0x0000 }, /* R421 - FLL2 Synchroniser 5 */
{ 0x000001A6, 0x0000 }, /* R422 - FLL2 Synchroniser 6 */
{ 0x000001A7, 0x0001 }, /* R423 - FLL2 Synchroniser 7 */
{ 0x000001A9, 0x0000 }, /* R425 - FLL2 Spread Spectrum */
{ 0x000001AA, 0x0004 }, /* R426 - FLL2 GPIO Clock */
{ 0x00000200, 0x0006 }, /* R512 - Mic Charge Pump 1 */
{ 0x00000210, 0x00D4 }, /* R528 - LDO1 Control 1 */
{ 0x00000212, 0x0000 }, /* R530 - LDO1 Control 2 */
{ 0x00000213, 0x0344 }, /* R531 - LDO2 Control 1 */
{ 0x00000218, 0x01A6 }, /* R536 - Mic Bias Ctrl 1 */
{ 0x00000219, 0x01A6 }, /* R537 - Mic Bias Ctrl 2 */
{ 0x0000021A, 0x01A6 }, /* R538 - Mic Bias Ctrl 3 */
{ 0x00000293, 0x0000 }, /* R659 - Accessory Detect Mode 1 */
{ 0x0000029B, 0x0020 }, /* R667 - Headphone Detect 1 */
{ 0x000002A2, 0x0000 }, /* R674 - Micd clamp control */
{ 0x000002A3, 0x1102 }, /* R675 - Mic Detect 1 */
{ 0x000002A4, 0x009F }, /* R676 - Mic Detect 2 */
{ 0x000002A6, 0x3737 }, /* R678 - Mic Detect Level 1 */
{ 0x000002A7, 0x2C37 }, /* R679 - Mic Detect Level 2 */
{ 0x000002A8, 0x1422 }, /* R680 - Mic Detect Level 3 */
{ 0x000002A9, 0x030A }, /* R681 - Mic Detect Level 4 */
{ 0x000002C3, 0x0000 }, /* R707 - Mic noise mix control 1 */
{ 0x000002CB, 0x0000 }, /* R715 - Isolation control */
{ 0x000002D3, 0x0000 }, /* R723 - Jack detect analogue */
{ 0x00000300, 0x0000 }, /* R768 - Input Enables */
{ 0x00000308, 0x0000 }, /* R776 - Input Rate */
{ 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */
{ 0x00000310, 0x2080 }, /* R784 - IN1L Control */
{ 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */
{ 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */
{ 0x00000314, 0x0080 }, /* R788 - IN1R Control */
{ 0x00000315, 0x0180 }, /* R789 - ADC Digital Volume 1R */
{ 0x00000316, 0x0000 }, /* R790 - DMIC1R Control */
{ 0x00000318, 0x2080 }, /* R792 - IN2L Control */
{ 0x00000319, 0x0180 }, /* R793 - ADC Digital Volume 2L */
{ 0x0000031A, 0x0000 }, /* R794 - DMIC2L Control */
{ 0x0000031C, 0x0080 }, /* R796 - IN2R Control */
{ 0x0000031D, 0x0180 }, /* R797 - ADC Digital Volume 2R */
{ 0x0000031E, 0x0000 }, /* R798 - DMIC2R Control */
{ 0x00000320, 0x2080 }, /* R800 - IN3L Control */
{ 0x00000321, 0x0180 }, /* R801 - ADC Digital Volume 3L */
{ 0x00000322, 0x0000 }, /* R802 - DMIC3L Control */
{ 0x00000324, 0x0080 }, /* R804 - IN3R Control */
{ 0x00000325, 0x0180 }, /* R805 - ADC Digital Volume 3R */
{ 0x00000326, 0x0000 }, /* R806 - DMIC3R Control */
{ 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */
{ 0x00000408, 0x0000 }, /* R1032 - Output Rate 1 */
{ 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */
{ 0x00000410, 0x6080 }, /* R1040 - Output Path Config 1L */
{ 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */
{ 0x00000412, 0x0081 }, /* R1042 - DAC Volume Limit 1L */
{ 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */
{ 0x00000414, 0x0080 }, /* R1044 - Output Path Config 1R */
{ 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */
{ 0x00000416, 0x0081 }, /* R1046 - DAC Volume Limit 1R */
{ 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */
{ 0x00000418, 0xA080 }, /* R1048 - Output Path Config 2L */
{ 0x00000419, 0x0180 }, /* R1049 - DAC Digital Volume 2L */
{ 0x0000041A, 0x0081 }, /* R1050 - DAC Volume Limit 2L */
{ 0x0000041B, 0x0004 }, /* R1051 - Noise Gate Select 2L */
{ 0x0000041C, 0x0080 }, /* R1052 - Output Path Config 2R */
{ 0x0000041D, 0x0180 }, /* R1053 - DAC Digital Volume 2R */
{ 0x0000041E, 0x0081 }, /* R1054 - DAC Volume Limit 2R */
{ 0x0000041F, 0x0008 }, /* R1055 - Noise Gate Select 2R */
{ 0x00000420, 0xA080 }, /* R1056 - Output Path Config 3L */
{ 0x00000421, 0x0180 }, /* R1057 - DAC Digital Volume 3L */
{ 0x00000422, 0x0081 }, /* R1058 - DAC Volume Limit 3L */
{ 0x00000423, 0x0010 }, /* R1059 - Noise Gate Select 3L */
{ 0x00000428, 0xE000 }, /* R1064 - Output Path Config 4L */
{ 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */
{ 0x0000042A, 0x0081 }, /* R1066 - Out Volume 4L */
{ 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */
{ 0x0000042D, 0x0180 }, /* R1069 - DAC Digital Volume 4R */
{ 0x0000042E, 0x0081 }, /* R1070 - Out Volume 4R */
{ 0x0000042F, 0x0080 }, /* R1071 - Noise Gate Select 4R */
{ 0x00000430, 0x0000 }, /* R1072 - Output Path Config 5L */
{ 0x00000431, 0x0180 }, /* R1073 - DAC Digital Volume 5L */
{ 0x00000432, 0x0081 }, /* R1074 - DAC Volume Limit 5L */
{ 0x00000433, 0x0100 }, /* R1075 - Noise Gate Select 5L */
{ 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */
{ 0x00000436, 0x0081 }, /* R1078 - DAC Volume Limit 5R */
{ 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */
{ 0x00000440, 0x0FFF }, /* R1088 - DRE Enable */
{ 0x00000442, 0x3F0A }, /* R1090 - DRE Control 2 */
{ 0x00000443, 0xDC1F }, /* R1090 - DRE Control 3 */
{ 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */
{ 0x00000458, 0x000B }, /* R1112 - Noise Gate Control */
{ 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */
{ 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */
{ 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */
{ 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */
{ 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */
{ 0x00000503, 0x0000 }, /* R1283 - AIF1 Rate Ctrl */
{ 0x00000504, 0x0000 }, /* R1284 - AIF1 Format */
{ 0x00000505, 0x0040 }, /* R1285 - AIF1 Tx BCLK Rate */
{ 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */
{ 0x00000507, 0x1818 }, /* R1287 - AIF1 Frame Ctrl 1 */
{ 0x00000508, 0x1818 }, /* R1288 - AIF1 Frame Ctrl 2 */
{ 0x00000509, 0x0000 }, /* R1289 - AIF1 Frame Ctrl 3 */
{ 0x0000050A, 0x0001 }, /* R1290 - AIF1 Frame Ctrl 4 */
{ 0x0000050B, 0x0002 }, /* R1291 - AIF1 Frame Ctrl 5 */
{ 0x0000050C, 0x0003 }, /* R1292 - AIF1 Frame Ctrl 6 */
{ 0x0000050D, 0x0004 }, /* R1293 - AIF1 Frame Ctrl 7 */
{ 0x0000050E, 0x0005 }, /* R1294 - AIF1 Frame Ctrl 8 */
{ 0x0000050F, 0x0006 }, /* R1295 - AIF1 Frame Ctrl 9 */
{ 0x00000510, 0x0007 }, /* R1296 - AIF1 Frame Ctrl 10 */
{ 0x00000511, 0x0000 }, /* R1297 - AIF1 Frame Ctrl 11 */
{ 0x00000512, 0x0001 }, /* R1298 - AIF1 Frame Ctrl 12 */
{ 0x00000513, 0x0002 }, /* R1299 - AIF1 Frame Ctrl 13 */
{ 0x00000514, 0x0003 }, /* R1300 - AIF1 Frame Ctrl 14 */
{ 0x00000515, 0x0004 }, /* R1301 - AIF1 Frame Ctrl 15 */
{ 0x00000516, 0x0005 }, /* R1302 - AIF1 Frame Ctrl 16 */
{ 0x00000517, 0x0006 }, /* R1303 - AIF1 Frame Ctrl 17 */
{ 0x00000518, 0x0007 }, /* R1304 - AIF1 Frame Ctrl 18 */
{ 0x00000519, 0x0000 }, /* R1305 - AIF1 Tx Enables */
{ 0x0000051A, 0x0000 }, /* R1306 - AIF1 Rx Enables */
{ 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */
{ 0x00000541, 0x0008 }, /* R1345 - AIF2 Tx Pin Ctrl */
{ 0x00000542, 0x0000 }, /* R1346 - AIF2 Rx Pin Ctrl */
{ 0x00000543, 0x0000 }, /* R1347 - AIF2 Rate Ctrl */
{ 0x00000544, 0x0000 }, /* R1348 - AIF2 Format */
{ 0x00000545, 0x0040 }, /* R1349 - AIF2 Tx BCLK Rate */
{ 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */
{ 0x00000547, 0x1818 }, /* R1351 - AIF2 Frame Ctrl 1 */
{ 0x00000548, 0x1818 }, /* R1352 - AIF2 Frame Ctrl 2 */
{ 0x00000549, 0x0000 }, /* R1353 - AIF2 Frame Ctrl 3 */
{ 0x0000054A, 0x0001 }, /* R1354 - AIF2 Frame Ctrl 4 */
{ 0x00000551, 0x0000 }, /* R1361 - AIF2 Frame Ctrl 11 */
{ 0x00000552, 0x0001 }, /* R1362 - AIF2 Frame Ctrl 12 */
{ 0x00000559, 0x0000 }, /* R1369 - AIF2 Tx Enables */
{ 0x0000055A, 0x0000 }, /* R1370 - AIF2 Rx Enables */
{ 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */
{ 0x00000581, 0x0008 }, /* R1409 - AIF3 Tx Pin Ctrl */
{ 0x00000582, 0x0000 }, /* R1410 - AIF3 Rx Pin Ctrl */
{ 0x00000583, 0x0000 }, /* R1411 - AIF3 Rate Ctrl */
{ 0x00000584, 0x0000 }, /* R1412 - AIF3 Format */
{ 0x00000585, 0x0040 }, /* R1413 - AIF3 Tx BCLK Rate */
{ 0x00000586, 0x0040 }, /* R1414 - AIF3 Rx BCLK Rate */
{ 0x00000587, 0x1818 }, /* R1415 - AIF3 Frame Ctrl 1 */
{ 0x00000588, 0x1818 }, /* R1416 - AIF3 Frame Ctrl 2 */
{ 0x00000589, 0x0000 }, /* R1417 - AIF3 Frame Ctrl 3 */
{ 0x0000058A, 0x0001 }, /* R1418 - AIF3 Frame Ctrl 4 */
{ 0x00000591, 0x0000 }, /* R1425 - AIF3 Frame Ctrl 11 */
{ 0x00000592, 0x0001 }, /* R1426 - AIF3 Frame Ctrl 12 */
{ 0x00000599, 0x0000 }, /* R1433 - AIF3 Tx Enables */
{ 0x0000059A, 0x0000 }, /* R1434 - AIF3 Rx Enables */
{ 0x000005E3, 0x0004 }, /* R1507 - SLIMbus Framer Ref Gear */
{ 0x000005E5, 0x0000 }, /* R1509 - SLIMbus Rates 1 */
{ 0x000005E6, 0x0000 }, /* R1510 - SLIMbus Rates 2 */
{ 0x000005E7, 0x0000 }, /* R1511 - SLIMbus Rates 3 */
{ 0x000005E8, 0x0000 }, /* R1512 - SLIMbus Rates 4 */
{ 0x000005E9, 0x0000 }, /* R1513 - SLIMbus Rates 5 */
{ 0x000005EA, 0x0000 }, /* R1514 - SLIMbus Rates 6 */
{ 0x000005EB, 0x0000 }, /* R1515 - SLIMbus Rates 7 */
{ 0x000005EC, 0x0000 }, /* R1516 - SLIMbus Rates 8 */
{ 0x000005F5, 0x0000 }, /* R1525 - SLIMbus RX Channel Enable */
{ 0x000005F6, 0x0000 }, /* R1526 - SLIMbus TX Channel Enable */
{ 0x00000640, 0x0000 }, /* R1600 - PWM1MIX Input 1 Source */
{ 0x00000641, 0x0080 }, /* R1601 - PWM1MIX Input 1 Volume */
{ 0x00000642, 0x0000 }, /* R1602 - PWM1MIX Input 2 Source */
{ 0x00000643, 0x0080 }, /* R1603 - PWM1MIX Input 2 Volume */
{ 0x00000644, 0x0000 }, /* R1604 - PWM1MIX Input 3 Source */
{ 0x00000645, 0x0080 }, /* R1605 - PWM1MIX Input 3 Volume */
{ 0x00000646, 0x0000 }, /* R1606 - PWM1MIX Input 4 Source */
{ 0x00000647, 0x0080 }, /* R1607 - PWM1MIX Input 4 Volume */
{ 0x00000648, 0x0000 }, /* R1608 - PWM2MIX Input 1 Source */
{ 0x00000649, 0x0080 }, /* R1609 - PWM2MIX Input 1 Volume */
{ 0x0000064A, 0x0000 }, /* R1610 - PWM2MIX Input 2 Source */
{ 0x0000064B, 0x0080 }, /* R1611 - PWM2MIX Input 2 Volume */
{ 0x0000064C, 0x0000 }, /* R1612 - PWM2MIX Input 3 Source */
{ 0x0000064D, 0x0080 }, /* R1613 - PWM2MIX Input 3 Volume */
{ 0x0000064E, 0x0000 }, /* R1614 - PWM2MIX Input 4 Source */
{ 0x0000064F, 0x0080 }, /* R1615 - PWM2MIX Input 4 Volume */
{ 0x00000660, 0x0000 }, /* R1632 - MICMIX Input 1 Source */
{ 0x00000661, 0x0080 }, /* R1633 - MICMIX Input 1 Volume */
{ 0x00000662, 0x0000 }, /* R1634 - MICMIX Input 2 Source */
{ 0x00000663, 0x0080 }, /* R1635 - MICMIX Input 2 Volume */
{ 0x00000664, 0x0000 }, /* R1636 - MICMIX Input 3 Source */
{ 0x00000665, 0x0080 }, /* R1637 - MICMIX Input 3 Volume */
{ 0x00000666, 0x0000 }, /* R1638 - MICMIX Input 4 Source */
{ 0x00000667, 0x0080 }, /* R1639 - MICMIX Input 4 Volume */
{ 0x00000668, 0x0000 }, /* R1640 - NOISEMIX Input 1 Source */
{ 0x00000669, 0x0080 }, /* R1641 - NOISEMIX Input 1 Volume */
{ 0x0000066A, 0x0000 }, /* R1642 - NOISEMIX Input 2 Source */
{ 0x0000066B, 0x0080 }, /* R1643 - NOISEMIX Input 2 Volume */
{ 0x0000066C, 0x0000 }, /* R1644 - NOISEMIX Input 3 Source */
{ 0x0000066D, 0x0080 }, /* R1645 - NOISEMIX Input 3 Volume */
{ 0x0000066E, 0x0000 }, /* R1646 - NOISEMIX Input 4 Source */
{ 0x0000066F, 0x0080 }, /* R1647 - NOISEMIX Input 4 Volume */
{ 0x00000680, 0x0000 }, /* R1664 - OUT1LMIX Input 1 Source */
{ 0x00000681, 0x0080 }, /* R1665 - OUT1LMIX Input 1 Volume */
{ 0x00000682, 0x0000 }, /* R1666 - OUT1LMIX Input 2 Source */
{ 0x00000683, 0x0080 }, /* R1667 - OUT1LMIX Input 2 Volume */
{ 0x00000684, 0x0000 }, /* R1668 - OUT1LMIX Input 3 Source */
{ 0x00000685, 0x0080 }, /* R1669 - OUT1LMIX Input 3 Volume */
{ 0x00000686, 0x0000 }, /* R1670 - OUT1LMIX Input 4 Source */
{ 0x00000687, 0x0080 }, /* R1671 - OUT1LMIX Input 4 Volume */
{ 0x00000688, 0x0000 }, /* R1672 - OUT1RMIX Input 1 Source */
{ 0x00000689, 0x0080 }, /* R1673 - OUT1RMIX Input 1 Volume */
{ 0x0000068A, 0x0000 }, /* R1674 - OUT1RMIX Input 2 Source */
{ 0x0000068B, 0x0080 }, /* R1675 - OUT1RMIX Input 2 Volume */
{ 0x0000068C, 0x0000 }, /* R1676 - OUT1RMIX Input 3 Source */
{ 0x0000068D, 0x0080 }, /* R1677 - OUT1RMIX Input 3 Volume */
{ 0x0000068E, 0x0000 }, /* R1678 - OUT1RMIX Input 4 Source */
{ 0x0000068F, 0x0080 }, /* R1679 - OUT1RMIX Input 4 Volume */
{ 0x00000690, 0x0000 }, /* R1680 - OUT2LMIX Input 1 Source */
{ 0x00000691, 0x0080 }, /* R1681 - OUT2LMIX Input 1 Volume */
{ 0x00000692, 0x0000 }, /* R1682 - OUT2LMIX Input 2 Source */
{ 0x00000693, 0x0080 }, /* R1683 - OUT2LMIX Input 2 Volume */
{ 0x00000694, 0x0000 }, /* R1684 - OUT2LMIX Input 3 Source */
{ 0x00000695, 0x0080 }, /* R1685 - OUT2LMIX Input 3 Volume */
{ 0x00000696, 0x0000 }, /* R1686 - OUT2LMIX Input 4 Source */
{ 0x00000697, 0x0080 }, /* R1687 - OUT2LMIX Input 4 Volume */
{ 0x00000698, 0x0000 }, /* R1688 - OUT2RMIX Input 1 Source */
{ 0x00000699, 0x0080 }, /* R1689 - OUT2RMIX Input 1 Volume */
{ 0x0000069A, 0x0000 }, /* R1690 - OUT2RMIX Input 2 Source */
{ 0x0000069B, 0x0080 }, /* R1691 - OUT2RMIX Input 2 Volume */
{ 0x0000069C, 0x0000 }, /* R1692 - OUT2RMIX Input 3 Source */
{ 0x0000069D, 0x0080 }, /* R1693 - OUT2RMIX Input 3 Volume */
{ 0x0000069E, 0x0000 }, /* R1694 - OUT2RMIX Input 4 Source */
{ 0x0000069F, 0x0080 }, /* R1695 - OUT2RMIX Input 4 Volume */
{ 0x000006A0, 0x0000 }, /* R1696 - OUT3LMIX Input 1 Source */
{ 0x000006A1, 0x0080 }, /* R1697 - OUT3LMIX Input 1 Volume */
{ 0x000006A2, 0x0000 }, /* R1698 - OUT3LMIX Input 2 Source */
{ 0x000006A3, 0x0080 }, /* R1699 - OUT3LMIX Input 2 Volume */
{ 0x000006A4, 0x0000 }, /* R1700 - OUT3LMIX Input 3 Source */
{ 0x000006A5, 0x0080 }, /* R1701 - OUT3LMIX Input 3 Volume */
{ 0x000006A6, 0x0000 }, /* R1702 - OUT3LMIX Input 4 Source */
{ 0x000006A7, 0x0080 }, /* R1703 - OUT3LMIX Input 4 Volume */
{ 0x000006B0, 0x0000 }, /* R1712 - OUT4LMIX Input 1 Source */
{ 0x000006B1, 0x0080 }, /* R1713 - OUT4LMIX Input 1 Volume */
{ 0x000006B2, 0x0000 }, /* R1714 - OUT4LMIX Input 2 Source */
{ 0x000006B3, 0x0080 }, /* R1715 - OUT4LMIX Input 2 Volume */
{ 0x000006B4, 0x0000 }, /* R1716 - OUT4LMIX Input 3 Source */
{ 0x000006B5, 0x0080 }, /* R1717 - OUT4LMIX Input 3 Volume */
{ 0x000006B6, 0x0000 }, /* R1718 - OUT4LMIX Input 4 Source */
{ 0x000006B7, 0x0080 }, /* R1719 - OUT4LMIX Input 4 Volume */
{ 0x000006B8, 0x0000 }, /* R1720 - OUT4RMIX Input 1 Source */
{ 0x000006B9, 0x0080 }, /* R1721 - OUT4RMIX Input 1 Volume */
{ 0x000006BA, 0x0000 }, /* R1722 - OUT4RMIX Input 2 Source */
{ 0x000006BB, 0x0080 }, /* R1723 - OUT4RMIX Input 2 Volume */
{ 0x000006BC, 0x0000 }, /* R1724 - OUT4RMIX Input 3 Source */
{ 0x000006BD, 0x0080 }, /* R1725 - OUT4RMIX Input 3 Volume */
{ 0x000006BE, 0x0000 }, /* R1726 - OUT4RMIX Input 4 Source */
{ 0x000006BF, 0x0080 }, /* R1727 - OUT4RMIX Input 4 Volume */
{ 0x000006C0, 0x0000 }, /* R1728 - OUT5LMIX Input 1 Source */
{ 0x000006C1, 0x0080 }, /* R1729 - OUT5LMIX Input 1 Volume */
{ 0x000006C2, 0x0000 }, /* R1730 - OUT5LMIX Input 2 Source */
{ 0x000006C3, 0x0080 }, /* R1731 - OUT5LMIX Input 2 Volume */
{ 0x000006C4, 0x0000 }, /* R1732 - OUT5LMIX Input 3 Source */
{ 0x000006C5, 0x0080 }, /* R1733 - OUT5LMIX Input 3 Volume */
{ 0x000006C6, 0x0000 }, /* R1734 - OUT5LMIX Input 4 Source */
{ 0x000006C7, 0x0080 }, /* R1735 - OUT5LMIX Input 4 Volume */
{ 0x000006C8, 0x0000 }, /* R1736 - OUT5RMIX Input 1 Source */
{ 0x000006C9, 0x0080 }, /* R1737 - OUT5RMIX Input 1 Volume */
{ 0x000006CA, 0x0000 }, /* R1738 - OUT5RMIX Input 2 Source */
{ 0x000006CB, 0x0080 }, /* R1739 - OUT5RMIX Input 2 Volume */
{ 0x000006CC, 0x0000 }, /* R1740 - OUT5RMIX Input 3 Source */
{ 0x000006CD, 0x0080 }, /* R1741 - OUT5RMIX Input 3 Volume */
{ 0x000006CE, 0x0000 }, /* R1742 - OUT5RMIX Input 4 Source */
{ 0x000006CF, 0x0080 }, /* R1743 - OUT5RMIX Input 4 Volume */
{ 0x00000700, 0x0000 }, /* R1792 - AIF1TX1MIX Input 1 Source */
{ 0x00000701, 0x0080 }, /* R1793 - AIF1TX1MIX Input 1 Volume */
{ 0x00000702, 0x0000 }, /* R1794 - AIF1TX1MIX Input 2 Source */
{ 0x00000703, 0x0080 }, /* R1795 - AIF1TX1MIX Input 2 Volume */
{ 0x00000704, 0x0000 }, /* R1796 - AIF1TX1MIX Input 3 Source */
{ 0x00000705, 0x0080 }, /* R1797 - AIF1TX1MIX Input 3 Volume */
{ 0x00000706, 0x0000 }, /* R1798 - AIF1TX1MIX Input 4 Source */
{ 0x00000707, 0x0080 }, /* R1799 - AIF1TX1MIX Input 4 Volume */
{ 0x00000708, 0x0000 }, /* R1800 - AIF1TX2MIX Input 1 Source */
{ 0x00000709, 0x0080 }, /* R1801 - AIF1TX2MIX Input 1 Volume */
{ 0x0000070A, 0x0000 }, /* R1802 - AIF1TX2MIX Input 2 Source */
{ 0x0000070B, 0x0080 }, /* R1803 - AIF1TX2MIX Input 2 Volume */
{ 0x0000070C, 0x0000 }, /* R1804 - AIF1TX2MIX Input 3 Source */
{ 0x0000070D, 0x0080 }, /* R1805 - AIF1TX2MIX Input 3 Volume */
{ 0x0000070E, 0x0000 }, /* R1806 - AIF1TX2MIX Input 4 Source */
{ 0x0000070F, 0x0080 }, /* R1807 - AIF1TX2MIX Input 4 Volume */
{ 0x00000710, 0x0000 }, /* R1808 - AIF1TX3MIX Input 1 Source */
{ 0x00000711, 0x0080 }, /* R1809 - AIF1TX3MIX Input 1 Volume */
{ 0x00000712, 0x0000 }, /* R1810 - AIF1TX3MIX Input 2 Source */
{ 0x00000713, 0x0080 }, /* R1811 - AIF1TX3MIX Input 2 Volume */
{ 0x00000714, 0x0000 }, /* R1812 - AIF1TX3MIX Input 3 Source */
{ 0x00000715, 0x0080 }, /* R1813 - AIF1TX3MIX Input 3 Volume */
{ 0x00000716, 0x0000 }, /* R1814 - AIF1TX3MIX Input 4 Source */
{ 0x00000717, 0x0080 }, /* R1815 - AIF1TX3MIX Input 4 Volume */
{ 0x00000718, 0x0000 }, /* R1816 - AIF1TX4MIX Input 1 Source */
{ 0x00000719, 0x0080 }, /* R1817 - AIF1TX4MIX Input 1 Volume */
{ 0x0000071A, 0x0000 }, /* R1818 - AIF1TX4MIX Input 2 Source */
{ 0x0000071B, 0x0080 }, /* R1819 - AIF1TX4MIX Input 2 Volume */
{ 0x0000071C, 0x0000 }, /* R1820 - AIF1TX4MIX Input 3 Source */
{ 0x0000071D, 0x0080 }, /* R1821 - AIF1TX4MIX Input 3 Volume */
{ 0x0000071E, 0x0000 }, /* R1822 - AIF1TX4MIX Input 4 Source */
{ 0x0000071F, 0x0080 }, /* R1823 - AIF1TX4MIX Input 4 Volume */
{ 0x00000720, 0x0000 }, /* R1824 - AIF1TX5MIX Input 1 Source */
{ 0x00000721, 0x0080 }, /* R1825 - AIF1TX5MIX Input 1 Volume */
{ 0x00000722, 0x0000 }, /* R1826 - AIF1TX5MIX Input 2 Source */
{ 0x00000723, 0x0080 }, /* R1827 - AIF1TX5MIX Input 2 Volume */
{ 0x00000724, 0x0000 }, /* R1828 - AIF1TX5MIX Input 3 Source */
{ 0x00000725, 0x0080 }, /* R1829 - AIF1TX5MIX Input 3 Volume */
{ 0x00000726, 0x0000 }, /* R1830 - AIF1TX5MIX Input 4 Source */
{ 0x00000727, 0x0080 }, /* R1831 - AIF1TX5MIX Input 4 Volume */
{ 0x00000728, 0x0000 }, /* R1832 - AIF1TX6MIX Input 1 Source */
{ 0x00000729, 0x0080 }, /* R1833 - AIF1TX6MIX Input 1 Volume */
{ 0x0000072A, 0x0000 }, /* R1834 - AIF1TX6MIX Input 2 Source */
{ 0x0000072B, 0x0080 }, /* R1835 - AIF1TX6MIX Input 2 Volume */
{ 0x0000072C, 0x0000 }, /* R1836 - AIF1TX6MIX Input 3 Source */
{ 0x0000072D, 0x0080 }, /* R1837 - AIF1TX6MIX Input 3 Volume */
{ 0x0000072E, 0x0000 }, /* R1838 - AIF1TX6MIX Input 4 Source */
{ 0x0000072F, 0x0080 }, /* R1839 - AIF1TX6MIX Input 4 Volume */
{ 0x00000730, 0x0000 }, /* R1840 - AIF1TX7MIX Input 1 Source */
{ 0x00000731, 0x0080 }, /* R1841 - AIF1TX7MIX Input 1 Volume */
{ 0x00000732, 0x0000 }, /* R1842 - AIF1TX7MIX Input 2 Source */
{ 0x00000733, 0x0080 }, /* R1843 - AIF1TX7MIX Input 2 Volume */
{ 0x00000734, 0x0000 }, /* R1844 - AIF1TX7MIX Input 3 Source */
{ 0x00000735, 0x0080 }, /* R1845 - AIF1TX7MIX Input 3 Volume */
{ 0x00000736, 0x0000 }, /* R1846 - AIF1TX7MIX Input 4 Source */
{ 0x00000737, 0x0080 }, /* R1847 - AIF1TX7MIX Input 4 Volume */
{ 0x00000738, 0x0000 }, /* R1848 - AIF1TX8MIX Input 1 Source */
{ 0x00000739, 0x0080 }, /* R1849 - AIF1TX8MIX Input 1 Volume */
{ 0x0000073A, 0x0000 }, /* R1850 - AIF1TX8MIX Input 2 Source */
{ 0x0000073B, 0x0080 }, /* R1851 - AIF1TX8MIX Input 2 Volume */
{ 0x0000073C, 0x0000 }, /* R1852 - AIF1TX8MIX Input 3 Source */
{ 0x0000073D, 0x0080 }, /* R1853 - AIF1TX8MIX Input 3 Volume */
{ 0x0000073E, 0x0000 }, /* R1854 - AIF1TX8MIX Input 4 Source */
{ 0x0000073F, 0x0080 }, /* R1855 - AIF1TX8MIX Input 4 Volume */
{ 0x00000740, 0x0000 }, /* R1856 - AIF2TX1MIX Input 1 Source */
{ 0x00000741, 0x0080 }, /* R1857 - AIF2TX1MIX Input 1 Volume */
{ 0x00000742, 0x0000 }, /* R1858 - AIF2TX1MIX Input 2 Source */
{ 0x00000743, 0x0080 }, /* R1859 - AIF2TX1MIX Input 2 Volume */
{ 0x00000744, 0x0000 }, /* R1860 - AIF2TX1MIX Input 3 Source */
{ 0x00000745, 0x0080 }, /* R1861 - AIF2TX1MIX Input 3 Volume */
{ 0x00000746, 0x0000 }, /* R1862 - AIF2TX1MIX Input 4 Source */
{ 0x00000747, 0x0080 }, /* R1863 - AIF2TX1MIX Input 4 Volume */
{ 0x00000748, 0x0000 }, /* R1864 - AIF2TX2MIX Input 1 Source */
{ 0x00000749, 0x0080 }, /* R1865 - AIF2TX2MIX Input 1 Volume */
{ 0x0000074A, 0x0000 }, /* R1866 - AIF2TX2MIX Input 2 Source */
{ 0x0000074B, 0x0080 }, /* R1867 - AIF2TX2MIX Input 2 Volume */
{ 0x0000074C, 0x0000 }, /* R1868 - AIF2TX2MIX Input 3 Source */
{ 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */
{ 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */
{ 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */
{ 0x00000780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */
{ 0x00000781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */
{ 0x00000782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */
{ 0x00000783, 0x0080 }, /* R1923 - AIF3TX1MIX Input 2 Volume */
{ 0x00000784, 0x0000 }, /* R1924 - AIF3TX1MIX Input 3 Source */
{ 0x00000785, 0x0080 }, /* R1925 - AIF3TX1MIX Input 3 Volume */
{ 0x00000786, 0x0000 }, /* R1926 - AIF3TX1MIX Input 4 Source */
{ 0x00000787, 0x0080 }, /* R1927 - AIF3TX1MIX Input 4 Volume */
{ 0x00000788, 0x0000 }, /* R1928 - AIF3TX2MIX Input 1 Source */
{ 0x00000789, 0x0080 }, /* R1929 - AIF3TX2MIX Input 1 Volume */
{ 0x0000078A, 0x0000 }, /* R1930 - AIF3TX2MIX Input 2 Source */
{ 0x0000078B, 0x0080 }, /* R1931 - AIF3TX2MIX Input 2 Volume */
{ 0x0000078C, 0x0000 }, /* R1932 - AIF3TX2MIX Input 3 Source */
{ 0x0000078D, 0x0080 }, /* R1933 - AIF3TX2MIX Input 3 Volume */
{ 0x0000078E, 0x0000 }, /* R1934 - AIF3TX2MIX Input 4 Source */
{ 0x0000078F, 0x0080 }, /* R1935 - AIF3TX2MIX Input 4 Volume */
{ 0x000007C0, 0x0000 }, /* R1984 - SLIMTX1MIX Input 1 Source */
{ 0x000007C1, 0x0080 }, /* R1985 - SLIMTX1MIX Input 1 Volume */
{ 0x000007C2, 0x0000 }, /* R1986 - SLIMTX1MIX Input 2 Source */
{ 0x000007C3, 0x0080 }, /* R1987 - SLIMTX1MIX Input 2 Volume */
{ 0x000007C4, 0x0000 }, /* R1988 - SLIMTX1MIX Input 3 Source */
{ 0x000007C5, 0x0080 }, /* R1989 - SLIMTX1MIX Input 3 Volume */
{ 0x000007C6, 0x0000 }, /* R1990 - SLIMTX1MIX Input 4 Source */
{ 0x000007C7, 0x0080 }, /* R1991 - SLIMTX1MIX Input 4 Volume */
{ 0x000007C8, 0x0000 }, /* R1992 - SLIMTX2MIX Input 1 Source */
{ 0x000007C9, 0x0080 }, /* R1993 - SLIMTX2MIX Input 1 Volume */
{ 0x000007CA, 0x0000 }, /* R1994 - SLIMTX2MIX Input 2 Source */
{ 0x000007CB, 0x0080 }, /* R1995 - SLIMTX2MIX Input 2 Volume */
{ 0x000007CC, 0x0000 }, /* R1996 - SLIMTX2MIX Input 3 Source */
{ 0x000007CD, 0x0080 }, /* R1997 - SLIMTX2MIX Input 3 Volume */
{ 0x000007CE, 0x0000 }, /* R1998 - SLIMTX2MIX Input 4 Source */
{ 0x000007CF, 0x0080 }, /* R1999 - SLIMTX2MIX Input 4 Volume */
{ 0x000007D0, 0x0000 }, /* R2000 - SLIMTX3MIX Input 1 Source */
{ 0x000007D1, 0x0080 }, /* R2001 - SLIMTX3MIX Input 1 Volume */
{ 0x000007D2, 0x0000 }, /* R2002 - SLIMTX3MIX Input 2 Source */
{ 0x000007D3, 0x0080 }, /* R2003 - SLIMTX3MIX Input 2 Volume */
{ 0x000007D4, 0x0000 }, /* R2004 - SLIMTX3MIX Input 3 Source */
{ 0x000007D5, 0x0080 }, /* R2005 - SLIMTX3MIX Input 3 Volume */
{ 0x000007D6, 0x0000 }, /* R2006 - SLIMTX3MIX Input 4 Source */
{ 0x000007D7, 0x0080 }, /* R2007 - SLIMTX3MIX Input 4 Volume */
{ 0x000007D8, 0x0000 }, /* R2008 - SLIMTX4MIX Input 1 Source */
{ 0x000007D9, 0x0080 }, /* R2009 - SLIMTX4MIX Input 1 Volume */
{ 0x000007DA, 0x0000 }, /* R2010 - SLIMTX4MIX Input 2 Source */
{ 0x000007DB, 0x0080 }, /* R2011 - SLIMTX4MIX Input 2 Volume */
{ 0x000007DC, 0x0000 }, /* R2012 - SLIMTX4MIX Input 3 Source */
{ 0x000007DD, 0x0080 }, /* R2013 - SLIMTX4MIX Input 3 Volume */
{ 0x000007DE, 0x0000 }, /* R2014 - SLIMTX4MIX Input 4 Source */
{ 0x000007DF, 0x0080 }, /* R2015 - SLIMTX4MIX Input 4 Volume */
{ 0x000007E0, 0x0000 }, /* R2016 - SLIMTX5MIX Input 1 Source */
{ 0x000007E1, 0x0080 }, /* R2017 - SLIMTX5MIX Input 1 Volume */
{ 0x000007E2, 0x0000 }, /* R2018 - SLIMTX5MIX Input 2 Source */
{ 0x000007E3, 0x0080 }, /* R2019 - SLIMTX5MIX Input 2 Volume */
{ 0x000007E4, 0x0000 }, /* R2020 - SLIMTX5MIX Input 3 Source */
{ 0x000007E5, 0x0080 }, /* R2021 - SLIMTX5MIX Input 3 Volume */
{ 0x000007E6, 0x0000 }, /* R2022 - SLIMTX5MIX Input 4 Source */
{ 0x000007E7, 0x0080 }, /* R2023 - SLIMTX5MIX Input 4 Volume */
{ 0x000007E8, 0x0000 }, /* R2024 - SLIMTX6MIX Input 1 Source */
{ 0x000007E9, 0x0080 }, /* R2025 - SLIMTX6MIX Input 1 Volume */
{ 0x000007EA, 0x0000 }, /* R2026 - SLIMTX6MIX Input 2 Source */
{ 0x000007EB, 0x0080 }, /* R2027 - SLIMTX6MIX Input 2 Volume */
{ 0x000007EC, 0x0000 }, /* R2028 - SLIMTX6MIX Input 3 Source */
{ 0x000007ED, 0x0080 }, /* R2029 - SLIMTX6MIX Input 3 Volume */
{ 0x000007EE, 0x0000 }, /* R2030 - SLIMTX6MIX Input 4 Source */
{ 0x000007EF, 0x0080 }, /* R2031 - SLIMTX6MIX Input 4 Volume */
{ 0x000007F0, 0x0000 }, /* R2032 - SLIMTX7MIX Input 1 Source */
{ 0x000007F1, 0x0080 }, /* R2033 - SLIMTX7MIX Input 1 Volume */
{ 0x000007F2, 0x0000 }, /* R2034 - SLIMTX7MIX Input 2 Source */
{ 0x000007F3, 0x0080 }, /* R2035 - SLIMTX7MIX Input 2 Volume */
{ 0x000007F4, 0x0000 }, /* R2036 - SLIMTX7MIX Input 3 Source */
{ 0x000007F5, 0x0080 }, /* R2037 - SLIMTX7MIX Input 3 Volume */
{ 0x000007F6, 0x0000 }, /* R2038 - SLIMTX7MIX Input 4 Source */
{ 0x000007F7, 0x0080 }, /* R2039 - SLIMTX7MIX Input 4 Volume */
{ 0x000007F8, 0x0000 }, /* R2040 - SLIMTX8MIX Input 1 Source */
{ 0x000007F9, 0x0080 }, /* R2041 - SLIMTX8MIX Input 1 Volume */
{ 0x000007FA, 0x0000 }, /* R2042 - SLIMTX8MIX Input 2 Source */
{ 0x000007FB, 0x0080 }, /* R2043 - SLIMTX8MIX Input 2 Volume */
{ 0x000007FC, 0x0000 }, /* R2044 - SLIMTX8MIX Input 3 Source */
{ 0x000007FD, 0x0080 }, /* R2045 - SLIMTX8MIX Input 3 Volume */
{ 0x000007FE, 0x0000 }, /* R2046 - SLIMTX8MIX Input 4 Source */
{ 0x000007FF, 0x0080 }, /* R2047 - SLIMTX8MIX Input 4 Volume */
{ 0x00000880, 0x0000 }, /* R2176 - EQ1MIX Input 1 Source */
{ 0x00000881, 0x0080 }, /* R2177 - EQ1MIX Input 1 Volume */
{ 0x00000882, 0x0000 }, /* R2178 - EQ1MIX Input 2 Source */
{ 0x00000883, 0x0080 }, /* R2179 - EQ1MIX Input 2 Volume */
{ 0x00000884, 0x0000 }, /* R2180 - EQ1MIX Input 3 Source */
{ 0x00000885, 0x0080 }, /* R2181 - EQ1MIX Input 3 Volume */
{ 0x00000886, 0x0000 }, /* R2182 - EQ1MIX Input 4 Source */
{ 0x00000887, 0x0080 }, /* R2183 - EQ1MIX Input 4 Volume */
{ 0x00000888, 0x0000 }, /* R2184 - EQ2MIX Input 1 Source */
{ 0x00000889, 0x0080 }, /* R2185 - EQ2MIX Input 1 Volume */
{ 0x0000088A, 0x0000 }, /* R2186 - EQ2MIX Input 2 Source */
{ 0x0000088B, 0x0080 }, /* R2187 - EQ2MIX Input 2 Volume */
{ 0x0000088C, 0x0000 }, /* R2188 - EQ2MIX Input 3 Source */
{ 0x0000088D, 0x0080 }, /* R2189 - EQ2MIX Input 3 Volume */
{ 0x0000088E, 0x0000 }, /* R2190 - EQ2MIX Input 4 Source */
{ 0x0000088F, 0x0080 }, /* R2191 - EQ2MIX Input 4 Volume */
{ 0x00000890, 0x0000 }, /* R2192 - EQ3MIX Input 1 Source */
{ 0x00000891, 0x0080 }, /* R2193 - EQ3MIX Input 1 Volume */
{ 0x00000892, 0x0000 }, /* R2194 - EQ3MIX Input 2 Source */
{ 0x00000893, 0x0080 }, /* R2195 - EQ3MIX Input 2 Volume */
{ 0x00000894, 0x0000 }, /* R2196 - EQ3MIX Input 3 Source */
{ 0x00000895, 0x0080 }, /* R2197 - EQ3MIX Input 3 Volume */
{ 0x00000896, 0x0000 }, /* R2198 - EQ3MIX Input 4 Source */
{ 0x00000897, 0x0080 }, /* R2199 - EQ3MIX Input 4 Volume */
{ 0x00000898, 0x0000 }, /* R2200 - EQ4MIX Input 1 Source */
{ 0x00000899, 0x0080 }, /* R2201 - EQ4MIX Input 1 Volume */
{ 0x0000089A, 0x0000 }, /* R2202 - EQ4MIX Input 2 Source */
{ 0x0000089B, 0x0080 }, /* R2203 - EQ4MIX Input 2 Volume */
{ 0x0000089C, 0x0000 }, /* R2204 - EQ4MIX Input 3 Source */
{ 0x0000089D, 0x0080 }, /* R2205 - EQ4MIX Input 3 Volume */
{ 0x0000089E, 0x0000 }, /* R2206 - EQ4MIX Input 4 Source */
{ 0x0000089F, 0x0080 }, /* R2207 - EQ4MIX Input 4 Volume */
{ 0x000008C0, 0x0000 }, /* R2240 - DRC1LMIX Input 1 Source */
{ 0x000008C1, 0x0080 }, /* R2241 - DRC1LMIX Input 1 Volume */
{ 0x000008C2, 0x0000 }, /* R2242 - DRC1LMIX Input 2 Source */
{ 0x000008C3, 0x0080 }, /* R2243 - DRC1LMIX Input 2 Volume */
{ 0x000008C4, 0x0000 }, /* R2244 - DRC1LMIX Input 3 Source */
{ 0x000008C5, 0x0080 }, /* R2245 - DRC1LMIX Input 3 Volume */
{ 0x000008C6, 0x0000 }, /* R2246 - DRC1LMIX Input 4 Source */
{ 0x000008C7, 0x0080 }, /* R2247 - DRC1LMIX Input 4 Volume */
{ 0x000008C8, 0x0000 }, /* R2248 - DRC1RMIX Input 1 Source */
{ 0x000008C9, 0x0080 }, /* R2249 - DRC1RMIX Input 1 Volume */
{ 0x000008CA, 0x0000 }, /* R2250 - DRC1RMIX Input 2 Source */
{ 0x000008CB, 0x0080 }, /* R2251 - DRC1RMIX Input 2 Volume */
{ 0x000008CC, 0x0000 }, /* R2252 - DRC1RMIX Input 3 Source */
{ 0x000008CD, 0x0080 }, /* R2253 - DRC1RMIX Input 3 Volume */
{ 0x000008CE, 0x0000 }, /* R2254 - DRC1RMIX Input 4 Source */
{ 0x000008CF, 0x0080 }, /* R2255 - DRC1RMIX Input 4 Volume */
{ 0x00000900, 0x0000 }, /* R2304 - HPLP1MIX Input 1 Source */
{ 0x00000901, 0x0080 }, /* R2305 - HPLP1MIX Input 1 Volume */
{ 0x00000902, 0x0000 }, /* R2306 - HPLP1MIX Input 2 Source */
{ 0x00000903, 0x0080 }, /* R2307 - HPLP1MIX Input 2 Volume */
{ 0x00000904, 0x0000 }, /* R2308 - HPLP1MIX Input 3 Source */
{ 0x00000905, 0x0080 }, /* R2309 - HPLP1MIX Input 3 Volume */
{ 0x00000906, 0x0000 }, /* R2310 - HPLP1MIX Input 4 Source */
{ 0x00000907, 0x0080 }, /* R2311 - HPLP1MIX Input 4 Volume */
{ 0x00000908, 0x0000 }, /* R2312 - HPLP2MIX Input 1 Source */
{ 0x00000909, 0x0080 }, /* R2313 - HPLP2MIX Input 1 Volume */
{ 0x0000090A, 0x0000 }, /* R2314 - HPLP2MIX Input 2 Source */
{ 0x0000090B, 0x0080 }, /* R2315 - HPLP2MIX Input 2 Volume */
{ 0x0000090C, 0x0000 }, /* R2316 - HPLP2MIX Input 3 Source */
{ 0x0000090D, 0x0080 }, /* R2317 - HPLP2MIX Input 3 Volume */
{ 0x0000090E, 0x0000 }, /* R2318 - HPLP2MIX Input 4 Source */
{ 0x0000090F, 0x0080 }, /* R2319 - HPLP2MIX Input 4 Volume */
{ 0x00000910, 0x0000 }, /* R2320 - HPLP3MIX Input 1 Source */
{ 0x00000911, 0x0080 }, /* R2321 - HPLP3MIX Input 1 Volume */
{ 0x00000912, 0x0000 }, /* R2322 - HPLP3MIX Input 2 Source */
{ 0x00000913, 0x0080 }, /* R2323 - HPLP3MIX Input 2 Volume */
{ 0x00000914, 0x0000 }, /* R2324 - HPLP3MIX Input 3 Source */
{ 0x00000915, 0x0080 }, /* R2325 - HPLP3MIX Input 3 Volume */
{ 0x00000916, 0x0000 }, /* R2326 - HPLP3MIX Input 4 Source */
{ 0x00000917, 0x0080 }, /* R2327 - HPLP3MIX Input 4 Volume */
{ 0x00000918, 0x0000 }, /* R2328 - HPLP4MIX Input 1 Source */
{ 0x00000919, 0x0080 }, /* R2329 - HPLP4MIX Input 1 Volume */
{ 0x0000091A, 0x0000 }, /* R2330 - HPLP4MIX Input 2 Source */
{ 0x0000091B, 0x0080 }, /* R2331 - HPLP4MIX Input 2 Volume */
{ 0x0000091C, 0x0000 }, /* R2332 - HPLP4MIX Input 3 Source */
{ 0x0000091D, 0x0080 }, /* R2333 - HPLP4MIX Input 3 Volume */
{ 0x0000091E, 0x0000 }, /* R2334 - HPLP4MIX Input 4 Source */
{ 0x0000091F, 0x0080 }, /* R2335 - HPLP4MIX Input 4 Volume */
{ 0x00000940, 0x0000 }, /* R2368 - DSP1LMIX Input 1 Source */
{ 0x00000941, 0x0080 }, /* R2369 - DSP1LMIX Input 1 Volume */
{ 0x00000942, 0x0000 }, /* R2370 - DSP1LMIX Input 2 Source */
{ 0x00000943, 0x0080 }, /* R2371 - DSP1LMIX Input 2 Volume */
{ 0x00000944, 0x0000 }, /* R2372 - DSP1LMIX Input 3 Source */
{ 0x00000945, 0x0080 }, /* R2373 - DSP1LMIX Input 3 Volume */
{ 0x00000946, 0x0000 }, /* R2374 - DSP1LMIX Input 4 Source */
{ 0x00000947, 0x0080 }, /* R2375 - DSP1LMIX Input 4 Volume */
{ 0x00000948, 0x0000 }, /* R2376 - DSP1RMIX Input 1 Source */
{ 0x00000949, 0x0080 }, /* R2377 - DSP1RMIX Input 1 Volume */
{ 0x0000094A, 0x0000 }, /* R2378 - DSP1RMIX Input 2 Source */
{ 0x0000094B, 0x0080 }, /* R2379 - DSP1RMIX Input 2 Volume */
{ 0x0000094C, 0x0000 }, /* R2380 - DSP1RMIX Input 3 Source */
{ 0x0000094D, 0x0080 }, /* R2381 - DSP1RMIX Input 3 Volume */
{ 0x0000094E, 0x0000 }, /* R2382 - DSP1RMIX Input 4 Source */
{ 0x0000094F, 0x0080 }, /* R2383 - DSP1RMIX Input 4 Volume */
{ 0x00000950, 0x0000 }, /* R2384 - DSP1AUX1MIX Input 1 Source */
{ 0x00000958, 0x0000 }, /* R2392 - DSP1AUX2MIX Input 1 Source */
{ 0x00000960, 0x0000 }, /* R2400 - DSP1AUX3MIX Input 1 Source */
{ 0x00000968, 0x0000 }, /* R2408 - DSP1AUX4MIX Input 1 Source */
{ 0x00000970, 0x0000 }, /* R2416 - DSP1AUX5MIX Input 1 Source */
{ 0x00000978, 0x0000 }, /* R2424 - DSP1AUX6MIX Input 1 Source */
{ 0x00000A80, 0x0000 }, /* R2688 - ASRC1LMIX Input 1 Source */
{ 0x00000A88, 0x0000 }, /* R2696 - ASRC1RMIX Input 1 Source */
{ 0x00000A90, 0x0000 }, /* R2704 - ASRC2LMIX Input 1 Source */
{ 0x00000A98, 0x0000 }, /* R2712 - ASRC2RMIX Input 1 Source */
{ 0x00000B00, 0x0000 }, /* R2816 - ISRC1DEC1MIX Input 1 Source */
{ 0x00000B08, 0x0000 }, /* R2824 - ISRC1DEC2MIX Input 1 Source */
{ 0x00000B20, 0x0000 }, /* R2848 - ISRC1INT1MIX Input 1 Source */
{ 0x00000B28, 0x0000 }, /* R2856 - ISRC1INT2MIX Input 1 Source */
{ 0x00000B40, 0x0000 }, /* R2880 - ISRC2DEC1MIX Input 1 Source */
{ 0x00000B48, 0x0000 }, /* R2888 - ISRC2DEC2MIX Input 1 Source */
{ 0x00000B60, 0x0000 }, /* R2912 - ISRC2INT1MIX Input 1 Source */
{ 0x00000B68, 0x0000 }, /* R2920 - ISRC2INT2MIX Input 1 Source */
{ 0x00000C00, 0xA101 }, /* R3072 - GPIO1 CTRL */
{ 0x00000C01, 0xA101 }, /* R3073 - GPIO2 CTRL */
{ 0x00000C02, 0xA101 }, /* R3074 - GPIO3 CTRL */
{ 0x00000C03, 0xA101 }, /* R3075 - GPIO4 CTRL */
{ 0x00000C04, 0xA101 }, /* R3076 - GPIO5 CTRL */
{ 0x00000C0F, 0x0400 }, /* R3087 - IRQ CTRL 1 */
{ 0x00000C10, 0x1000 }, /* R3088 - GPIO Debounce Config */
{ 0x00000C20, 0x8002 }, /* R3104 - Misc Pad Ctrl 1 */
{ 0x00000C21, 0x0001 }, /* R3105 - Misc Pad Ctrl 2 */
{ 0x00000C22, 0x0000 }, /* R3106 - Misc Pad Ctrl 3 */
{ 0x00000C23, 0x0000 }, /* R3107 - Misc Pad Ctrl 4 */
{ 0x00000C24, 0x0000 }, /* R3108 - Misc Pad Ctrl 5 */
{ 0x00000C25, 0x0000 }, /* R3109 - Misc Pad Ctrl 6 */
{ 0x00000D08, 0xFFFF }, /* R3336 - Interrupt Status 1 Mask */
{ 0x00000D09, 0xFFFF }, /* R3337 - Interrupt Status 2 Mask */
{ 0x00000D0A, 0xFFFF }, /* R3338 - Interrupt Status 3 Mask */
{ 0x00000D0B, 0xFFFF }, /* R3339 - Interrupt Status 4 Mask */
{ 0x00000D0C, 0xFEFF }, /* R3340 - Interrupt Status 5 Mask */
{ 0x00000D0F, 0x0000 }, /* R3343 - Interrupt Control */
{ 0x00000D18, 0xFFFF }, /* R3352 - IRQ2 Status 1 Mask */
{ 0x00000D19, 0xFFFF }, /* R3353 - IRQ2 Status 2 Mask */
{ 0x00000D1A, 0xFFFF }, /* R3354 - IRQ2 Status 3 Mask */
{ 0x00000D1B, 0xFFFF }, /* R3355 - IRQ2 Status 4 Mask */
{ 0x00000D1C, 0xFFFF }, /* R3356 - IRQ2 Status 5 Mask */
{ 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */
{ 0x00000D41, 0x0000 }, /* R3393 - ADSP2 IRQ0 */
{ 0x00000D53, 0xFFFF }, /* R3411 - AOD IRQ Mask IRQ1 */
{ 0x00000D54, 0xFFFF }, /* R3412 - AOD IRQ Mask IRQ2 */
{ 0x00000D56, 0x0000 }, /* R3414 - Jack detect debounce */
{ 0x00000E00, 0x0000 }, /* R3584 - FX_Ctrl1 */
{ 0x00000E10, 0x6318 }, /* R3600 - EQ1_1 */
{ 0x00000E11, 0x6300 }, /* R3601 - EQ1_2 */
{ 0x00000E12, 0x0FC8 }, /* R3602 - EQ1_3 */
{ 0x00000E13, 0x03FE }, /* R3603 - EQ1_4 */
{ 0x00000E14, 0x00E0 }, /* R3604 - EQ1_5 */
{ 0x00000E15, 0x1EC4 }, /* R3605 - EQ1_6 */
{ 0x00000E16, 0xF136 }, /* R3606 - EQ1_7 */
{ 0x00000E17, 0x0409 }, /* R3607 - EQ1_8 */
{ 0x00000E18, 0x04CC }, /* R3608 - EQ1_9 */
{ 0x00000E19, 0x1C9B }, /* R3609 - EQ1_10 */
{ 0x00000E1A, 0xF337 }, /* R3610 - EQ1_11 */
{ 0x00000E1B, 0x040B }, /* R3611 - EQ1_12 */
{ 0x00000E1C, 0x0CBB }, /* R3612 - EQ1_13 */
{ 0x00000E1D, 0x16F8 }, /* R3613 - EQ1_14 */
{ 0x00000E1E, 0xF7D9 }, /* R3614 - EQ1_15 */
{ 0x00000E1F, 0x040A }, /* R3615 - EQ1_16 */
{ 0x00000E20, 0x1F14 }, /* R3616 - EQ1_17 */
{ 0x00000E21, 0x058C }, /* R3617 - EQ1_18 */
{ 0x00000E22, 0x0563 }, /* R3618 - EQ1_19 */
{ 0x00000E23, 0x4000 }, /* R3619 - EQ1_20 */
{ 0x00000E24, 0x0B75 }, /* R3620 - EQ1_21 */
{ 0x00000E26, 0x6318 }, /* R3622 - EQ2_1 */
{ 0x00000E27, 0x6300 }, /* R3623 - EQ2_2 */
{ 0x00000E28, 0x0FC8 }, /* R3624 - EQ2_3 */
{ 0x00000E29, 0x03FE }, /* R3625 - EQ2_4 */
{ 0x00000E2A, 0x00E0 }, /* R3626 - EQ2_5 */
{ 0x00000E2B, 0x1EC4 }, /* R3627 - EQ2_6 */
{ 0x00000E2C, 0xF136 }, /* R3628 - EQ2_7 */
{ 0x00000E2D, 0x0409 }, /* R3629 - EQ2_8 */
{ 0x00000E2E, 0x04CC }, /* R3630 - EQ2_9 */
{ 0x00000E2F, 0x1C9B }, /* R3631 - EQ2_10 */
{ 0x00000E30, 0xF337 }, /* R3632 - EQ2_11 */
{ 0x00000E31, 0x040B }, /* R3633 - EQ2_12 */
{ 0x00000E32, 0x0CBB }, /* R3634 - EQ2_13 */
{ 0x00000E33, 0x16F8 }, /* R3635 - EQ2_14 */
{ 0x00000E34, 0xF7D9 }, /* R3636 - EQ2_15 */
{ 0x00000E35, 0x040A }, /* R3637 - EQ2_16 */
{ 0x00000E36, 0x1F14 }, /* R3638 - EQ2_17 */
{ 0x00000E37, 0x058C }, /* R3639 - EQ2_18 */
{ 0x00000E38, 0x0563 }, /* R3640 - EQ2_19 */
{ 0x00000E39, 0x4000 }, /* R3641 - EQ2_20 */
{ 0x00000E3A, 0x0B75 }, /* R3642 - EQ2_21 */
{ 0x00000E3C, 0x6318 }, /* R3644 - EQ3_1 */
{ 0x00000E3D, 0x6300 }, /* R3645 - EQ3_2 */
{ 0x00000E3E, 0x0FC8 }, /* R3646 - EQ3_3 */
{ 0x00000E3F, 0x03FE }, /* R3647 - EQ3_4 */
{ 0x00000E40, 0x00E0 }, /* R3648 - EQ3_5 */
{ 0x00000E41, 0x1EC4 }, /* R3649 - EQ3_6 */
{ 0x00000E42, 0xF136 }, /* R3650 - EQ3_7 */
{ 0x00000E43, 0x0409 }, /* R3651 - EQ3_8 */
{ 0x00000E44, 0x04CC }, /* R3652 - EQ3_9 */
{ 0x00000E45, 0x1C9B }, /* R3653 - EQ3_10 */
{ 0x00000E46, 0xF337 }, /* R3654 - EQ3_11 */
{ 0x00000E47, 0x040B }, /* R3655 - EQ3_12 */
{ 0x00000E48, 0x0CBB }, /* R3656 - EQ3_13 */
{ 0x00000E49, 0x16F8 }, /* R3657 - EQ3_14 */
{ 0x00000E4A, 0xF7D9 }, /* R3658 - EQ3_15 */
{ 0x00000E4B, 0x040A }, /* R3659 - EQ3_16 */
{ 0x00000E4C, 0x1F14 }, /* R3660 - EQ3_17 */
{ 0x00000E4D, 0x058C }, /* R3661 - EQ3_18 */
{ 0x00000E4E, 0x0563 }, /* R3662 - EQ3_19 */
{ 0x00000E4F, 0x4000 }, /* R3663 - EQ3_20 */
{ 0x00000E50, 0x0B75 }, /* R3664 - EQ3_21 */
{ 0x00000E52, 0x6318 }, /* R3666 - EQ4_1 */
{ 0x00000E53, 0x6300 }, /* R3667 - EQ4_2 */
{ 0x00000E54, 0x0FC8 }, /* R3668 - EQ4_3 */
{ 0x00000E55, 0x03FE }, /* R3669 - EQ4_4 */
{ 0x00000E56, 0x00E0 }, /* R3670 - EQ4_5 */
{ 0x00000E57, 0x1EC4 }, /* R3671 - EQ4_6 */
{ 0x00000E58, 0xF136 }, /* R3672 - EQ4_7 */
{ 0x00000E59, 0x0409 }, /* R3673 - EQ4_8 */
{ 0x00000E5A, 0x04CC }, /* R3674 - EQ4_9 */
{ 0x00000E5B, 0x1C9B }, /* R3675 - EQ4_10 */
{ 0x00000E5C, 0xF337 }, /* R3676 - EQ4_11 */
{ 0x00000E5D, 0x040B }, /* R3677 - EQ4_12 */
{ 0x00000E5E, 0x0CBB }, /* R3678 - EQ4_13 */
{ 0x00000E5F, 0x16F8 }, /* R3679 - EQ4_14 */
{ 0x00000E60, 0xF7D9 }, /* R3680 - EQ4_15 */
{ 0x00000E61, 0x040A }, /* R3681 - EQ4_16 */
{ 0x00000E62, 0x1F14 }, /* R3682 - EQ4_17 */
{ 0x00000E63, 0x058C }, /* R3683 - EQ4_18 */
{ 0x00000E64, 0x0563 }, /* R3684 - EQ4_19 */
{ 0x00000E65, 0x4000 }, /* R3685 - EQ4_20 */
{ 0x00000E66, 0x0B75 }, /* R3686 - EQ4_21 */
{ 0x00000E80, 0x0018 }, /* R3712 - DRC1 ctrl1 */
{ 0x00000E81, 0x0933 }, /* R3713 - DRC1 ctrl2 */
{ 0x00000E82, 0x0018 }, /* R3714 - DRC1 ctrl3 */
{ 0x00000E83, 0x0000 }, /* R3715 - DRC1 ctrl4 */
{ 0x00000E84, 0x0000 }, /* R3716 - DRC1 ctrl5 */
{ 0x00000EC0, 0x0000 }, /* R3776 - HPLPF1_1 */
{ 0x00000EC1, 0x0000 }, /* R3777 - HPLPF1_2 */
{ 0x00000EC4, 0x0000 }, /* R3780 - HPLPF2_1 */
{ 0x00000EC5, 0x0000 }, /* R3781 - HPLPF2_2 */
{ 0x00000EC8, 0x0000 }, /* R3784 - HPLPF3_1 */
{ 0x00000EC9, 0x0000 }, /* R3785 - HPLPF3_2 */
{ 0x00000ECC, 0x0000 }, /* R3788 - HPLPF4_1 */
{ 0x00000ECD, 0x0000 }, /* R3789 - HPLPF4_2 */
{ 0x00000EE0, 0x0000 }, /* R3808 - ASRC_ENABLE */
{ 0x00000EE2, 0x0000 }, /* R3810 - ASRC_RATE1 */
{ 0x00000EE3, 0x4000 }, /* R3811 - ASRC_RATE2 */
{ 0x00000EF0, 0x0000 }, /* R3824 - ISRC 1 CTRL 1 */
{ 0x00000EF1, 0x0000 }, /* R3825 - ISRC 1 CTRL 2 */
{ 0x00000EF2, 0x0000 }, /* R3826 - ISRC 1 CTRL 3 */
{ 0x00000EF3, 0x0000 }, /* R3827 - ISRC 2 CTRL 1 */
{ 0x00000EF4, 0x0000 }, /* R3828 - ISRC 2 CTRL 2 */
{ 0x00000EF5, 0x0000 }, /* R3829 - ISRC 2 CTRL 3 */
{ 0x00001100, 0x0010 }, /* R4352 - DSP1 Control 1 */
};
static bool wm5102_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case ARIZONA_SOFTWARE_RESET:
case ARIZONA_DEVICE_REVISION:
case ARIZONA_CTRL_IF_SPI_CFG_1:
case ARIZONA_CTRL_IF_I2C1_CFG_1:
case ARIZONA_WRITE_SEQUENCER_CTRL_0:
case ARIZONA_WRITE_SEQUENCER_CTRL_1:
case ARIZONA_WRITE_SEQUENCER_CTRL_2:
case ARIZONA_WRITE_SEQUENCER_CTRL_3:
case ARIZONA_TONE_GENERATOR_1:
case ARIZONA_TONE_GENERATOR_2:
case ARIZONA_TONE_GENERATOR_3:
case ARIZONA_TONE_GENERATOR_4:
case ARIZONA_TONE_GENERATOR_5:
case ARIZONA_PWM_DRIVE_1:
case ARIZONA_PWM_DRIVE_2:
case ARIZONA_PWM_DRIVE_3:
case ARIZONA_WAKE_CONTROL:
case ARIZONA_SEQUENCE_CONTROL:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3:
case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5:
case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6:
case ARIZONA_COMFORT_NOISE_GENERATOR:
case ARIZONA_HAPTICS_CONTROL_1:
case ARIZONA_HAPTICS_CONTROL_2:
case ARIZONA_HAPTICS_PHASE_1_INTENSITY:
case ARIZONA_HAPTICS_PHASE_1_DURATION:
case ARIZONA_HAPTICS_PHASE_2_INTENSITY:
case ARIZONA_HAPTICS_PHASE_2_DURATION:
case ARIZONA_HAPTICS_PHASE_3_INTENSITY:
case ARIZONA_HAPTICS_PHASE_3_DURATION:
case ARIZONA_HAPTICS_STATUS:
case ARIZONA_CLOCK_32K_1:
case ARIZONA_SYSTEM_CLOCK_1:
case ARIZONA_SAMPLE_RATE_1:
case ARIZONA_SAMPLE_RATE_2:
case ARIZONA_SAMPLE_RATE_3:
case ARIZONA_SAMPLE_RATE_1_STATUS:
case ARIZONA_SAMPLE_RATE_2_STATUS:
case ARIZONA_SAMPLE_RATE_3_STATUS:
case ARIZONA_ASYNC_CLOCK_1:
case ARIZONA_ASYNC_SAMPLE_RATE_1:
case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
case ARIZONA_ASYNC_SAMPLE_RATE_2:
case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS:
case ARIZONA_OUTPUT_SYSTEM_CLOCK:
case ARIZONA_OUTPUT_ASYNC_CLOCK:
case ARIZONA_RATE_ESTIMATOR_1:
case ARIZONA_RATE_ESTIMATOR_2:
case ARIZONA_RATE_ESTIMATOR_3:
case ARIZONA_RATE_ESTIMATOR_4:
case ARIZONA_RATE_ESTIMATOR_5:
case ARIZONA_DYNAMIC_FREQUENCY_SCALING_1:
case ARIZONA_FLL1_CONTROL_1:
case ARIZONA_FLL1_CONTROL_2:
case ARIZONA_FLL1_CONTROL_3:
case ARIZONA_FLL1_CONTROL_4:
case ARIZONA_FLL1_CONTROL_5:
case ARIZONA_FLL1_CONTROL_6:
case ARIZONA_FLL1_CONTROL_7:
case ARIZONA_FLL1_SYNCHRONISER_1:
case ARIZONA_FLL1_SYNCHRONISER_2:
case ARIZONA_FLL1_SYNCHRONISER_3:
case ARIZONA_FLL1_SYNCHRONISER_4:
case ARIZONA_FLL1_SYNCHRONISER_5:
case ARIZONA_FLL1_SYNCHRONISER_6:
case ARIZONA_FLL1_SYNCHRONISER_7:
case ARIZONA_FLL1_SPREAD_SPECTRUM:
case ARIZONA_FLL1_GPIO_CLOCK:
case ARIZONA_FLL2_CONTROL_1:
case ARIZONA_FLL2_CONTROL_2:
case ARIZONA_FLL2_CONTROL_3:
case ARIZONA_FLL2_CONTROL_4:
case ARIZONA_FLL2_CONTROL_5:
case ARIZONA_FLL2_CONTROL_6:
case ARIZONA_FLL2_CONTROL_7:
case ARIZONA_FLL2_SYNCHRONISER_1:
case ARIZONA_FLL2_SYNCHRONISER_2:
case ARIZONA_FLL2_SYNCHRONISER_3:
case ARIZONA_FLL2_SYNCHRONISER_4:
case ARIZONA_FLL2_SYNCHRONISER_5:
case ARIZONA_FLL2_SYNCHRONISER_6:
case ARIZONA_FLL2_SYNCHRONISER_7:
case ARIZONA_FLL2_SPREAD_SPECTRUM:
case ARIZONA_FLL2_GPIO_CLOCK:
case ARIZONA_MIC_CHARGE_PUMP_1:
case ARIZONA_LDO1_CONTROL_1:
case ARIZONA_LDO1_CONTROL_2:
case ARIZONA_LDO2_CONTROL_1:
case ARIZONA_MIC_BIAS_CTRL_1:
case ARIZONA_MIC_BIAS_CTRL_2:
case ARIZONA_MIC_BIAS_CTRL_3:
case ARIZONA_HP_CTRL_1L:
case ARIZONA_HP_CTRL_1R:
case ARIZONA_ACCESSORY_DETECT_MODE_1:
case ARIZONA_HEADPHONE_DETECT_1:
case ARIZONA_HEADPHONE_DETECT_2:
case ARIZONA_HP_DACVAL:
case ARIZONA_MICD_CLAMP_CONTROL:
case ARIZONA_MIC_DETECT_1:
case ARIZONA_MIC_DETECT_2:
case ARIZONA_MIC_DETECT_3:
case ARIZONA_MIC_DETECT_LEVEL_1:
case ARIZONA_MIC_DETECT_LEVEL_2:
case ARIZONA_MIC_DETECT_LEVEL_3:
case ARIZONA_MIC_DETECT_LEVEL_4:
case ARIZONA_MIC_NOISE_MIX_CONTROL_1:
case ARIZONA_ISOLATION_CONTROL:
case ARIZONA_JACK_DETECT_ANALOGUE:
case ARIZONA_INPUT_ENABLES:
case ARIZONA_INPUT_RATE:
case ARIZONA_INPUT_VOLUME_RAMP:
case ARIZONA_IN1L_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_1L:
case ARIZONA_DMIC1L_CONTROL:
case ARIZONA_IN1R_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_1R:
case ARIZONA_DMIC1R_CONTROL:
case ARIZONA_IN2L_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_2L:
case ARIZONA_DMIC2L_CONTROL:
case ARIZONA_IN2R_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_2R:
case ARIZONA_DMIC2R_CONTROL:
case ARIZONA_IN3L_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_3L:
case ARIZONA_DMIC3L_CONTROL:
case ARIZONA_IN3R_CONTROL:
case ARIZONA_ADC_DIGITAL_VOLUME_3R:
case ARIZONA_DMIC3R_CONTROL:
case ARIZONA_OUTPUT_ENABLES_1:
case ARIZONA_OUTPUT_STATUS_1:
case ARIZONA_OUTPUT_RATE_1:
case ARIZONA_OUTPUT_VOLUME_RAMP:
case ARIZONA_OUTPUT_PATH_CONFIG_1L:
case ARIZONA_DAC_DIGITAL_VOLUME_1L:
case ARIZONA_DAC_VOLUME_LIMIT_1L:
case ARIZONA_NOISE_GATE_SELECT_1L:
case ARIZONA_OUTPUT_PATH_CONFIG_1R:
case ARIZONA_DAC_DIGITAL_VOLUME_1R:
case ARIZONA_DAC_VOLUME_LIMIT_1R:
case ARIZONA_NOISE_GATE_SELECT_1R:
case ARIZONA_OUTPUT_PATH_CONFIG_2L:
case ARIZONA_DAC_DIGITAL_VOLUME_2L:
case ARIZONA_DAC_VOLUME_LIMIT_2L:
case ARIZONA_NOISE_GATE_SELECT_2L:
case ARIZONA_OUTPUT_PATH_CONFIG_2R:
case ARIZONA_DAC_DIGITAL_VOLUME_2R:
case ARIZONA_DAC_VOLUME_LIMIT_2R:
case ARIZONA_NOISE_GATE_SELECT_2R:
case ARIZONA_OUTPUT_PATH_CONFIG_3L:
case ARIZONA_DAC_DIGITAL_VOLUME_3L:
case ARIZONA_DAC_VOLUME_LIMIT_3L:
case ARIZONA_NOISE_GATE_SELECT_3L:
case ARIZONA_OUTPUT_PATH_CONFIG_4L:
case ARIZONA_DAC_DIGITAL_VOLUME_4L:
case ARIZONA_OUT_VOLUME_4L:
case ARIZONA_NOISE_GATE_SELECT_4L:
case ARIZONA_DAC_DIGITAL_VOLUME_4R:
case ARIZONA_OUT_VOLUME_4R:
case ARIZONA_NOISE_GATE_SELECT_4R:
case ARIZONA_OUTPUT_PATH_CONFIG_5L:
case ARIZONA_DAC_DIGITAL_VOLUME_5L:
case ARIZONA_DAC_VOLUME_LIMIT_5L:
case ARIZONA_NOISE_GATE_SELECT_5L:
case ARIZONA_DAC_DIGITAL_VOLUME_5R:
case ARIZONA_DAC_VOLUME_LIMIT_5R:
case ARIZONA_NOISE_GATE_SELECT_5R:
case ARIZONA_DRE_ENABLE:
case ARIZONA_DRE_CONTROL_2:
case ARIZONA_DRE_CONTROL_3:
case ARIZONA_DAC_AEC_CONTROL_1:
case ARIZONA_NOISE_GATE_CONTROL:
case ARIZONA_PDM_SPK1_CTRL_1:
case ARIZONA_PDM_SPK1_CTRL_2:
case ARIZONA_DAC_COMP_1:
case ARIZONA_DAC_COMP_2:
case ARIZONA_DAC_COMP_3:
case ARIZONA_DAC_COMP_4:
case ARIZONA_AIF1_BCLK_CTRL:
case ARIZONA_AIF1_TX_PIN_CTRL:
case ARIZONA_AIF1_RX_PIN_CTRL:
case ARIZONA_AIF1_RATE_CTRL:
case ARIZONA_AIF1_FORMAT:
case ARIZONA_AIF1_TX_BCLK_RATE:
case ARIZONA_AIF1_RX_BCLK_RATE:
case ARIZONA_AIF1_FRAME_CTRL_1:
case ARIZONA_AIF1_FRAME_CTRL_2:
case ARIZONA_AIF1_FRAME_CTRL_3:
case ARIZONA_AIF1_FRAME_CTRL_4:
case ARIZONA_AIF1_FRAME_CTRL_5:
case ARIZONA_AIF1_FRAME_CTRL_6:
case ARIZONA_AIF1_FRAME_CTRL_7:
case ARIZONA_AIF1_FRAME_CTRL_8:
case ARIZONA_AIF1_FRAME_CTRL_9:
case ARIZONA_AIF1_FRAME_CTRL_10:
case ARIZONA_AIF1_FRAME_CTRL_11:
case ARIZONA_AIF1_FRAME_CTRL_12:
case ARIZONA_AIF1_FRAME_CTRL_13:
case ARIZONA_AIF1_FRAME_CTRL_14:
case ARIZONA_AIF1_FRAME_CTRL_15:
case ARIZONA_AIF1_FRAME_CTRL_16:
case ARIZONA_AIF1_FRAME_CTRL_17:
case ARIZONA_AIF1_FRAME_CTRL_18:
case ARIZONA_AIF1_TX_ENABLES:
case ARIZONA_AIF1_RX_ENABLES:
case ARIZONA_AIF2_BCLK_CTRL:
case ARIZONA_AIF2_TX_PIN_CTRL:
case ARIZONA_AIF2_RX_PIN_CTRL:
case ARIZONA_AIF2_RATE_CTRL:
case ARIZONA_AIF2_FORMAT:
case ARIZONA_AIF2_TX_BCLK_RATE:
case ARIZONA_AIF2_RX_BCLK_RATE:
case ARIZONA_AIF2_FRAME_CTRL_1:
case ARIZONA_AIF2_FRAME_CTRL_2:
case ARIZONA_AIF2_FRAME_CTRL_3:
case ARIZONA_AIF2_FRAME_CTRL_4:
case ARIZONA_AIF2_FRAME_CTRL_11:
case ARIZONA_AIF2_FRAME_CTRL_12:
case ARIZONA_AIF2_TX_ENABLES:
case ARIZONA_AIF2_RX_ENABLES:
case ARIZONA_AIF3_BCLK_CTRL:
case ARIZONA_AIF3_TX_PIN_CTRL:
case ARIZONA_AIF3_RX_PIN_CTRL:
case ARIZONA_AIF3_RATE_CTRL:
case ARIZONA_AIF3_FORMAT:
case ARIZONA_AIF3_TX_BCLK_RATE:
case ARIZONA_AIF3_RX_BCLK_RATE:
case ARIZONA_AIF3_FRAME_CTRL_1:
case ARIZONA_AIF3_FRAME_CTRL_2:
case ARIZONA_AIF3_FRAME_CTRL_3:
case ARIZONA_AIF3_FRAME_CTRL_4:
case ARIZONA_AIF3_FRAME_CTRL_11:
case ARIZONA_AIF3_FRAME_CTRL_12:
case ARIZONA_AIF3_TX_ENABLES:
case ARIZONA_AIF3_RX_ENABLES:
case ARIZONA_SLIMBUS_FRAMER_REF_GEAR:
case ARIZONA_SLIMBUS_RATES_1:
case ARIZONA_SLIMBUS_RATES_2:
case ARIZONA_SLIMBUS_RATES_3:
case ARIZONA_SLIMBUS_RATES_4:
case ARIZONA_SLIMBUS_RATES_5:
case ARIZONA_SLIMBUS_RATES_6:
case ARIZONA_SLIMBUS_RATES_7:
case ARIZONA_SLIMBUS_RATES_8:
case ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE:
case ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE:
case ARIZONA_SLIMBUS_RX_PORT_STATUS:
case ARIZONA_SLIMBUS_TX_PORT_STATUS:
case ARIZONA_PWM1MIX_INPUT_1_SOURCE:
case ARIZONA_PWM1MIX_INPUT_1_VOLUME:
case ARIZONA_PWM1MIX_INPUT_2_SOURCE:
case ARIZONA_PWM1MIX_INPUT_2_VOLUME:
case ARIZONA_PWM1MIX_INPUT_3_SOURCE:
case ARIZONA_PWM1MIX_INPUT_3_VOLUME:
case ARIZONA_PWM1MIX_INPUT_4_SOURCE:
case ARIZONA_PWM1MIX_INPUT_4_VOLUME:
case ARIZONA_PWM2MIX_INPUT_1_SOURCE:
case ARIZONA_PWM2MIX_INPUT_1_VOLUME:
case ARIZONA_PWM2MIX_INPUT_2_SOURCE:
case ARIZONA_PWM2MIX_INPUT_2_VOLUME:
case ARIZONA_PWM2MIX_INPUT_3_SOURCE:
case ARIZONA_PWM2MIX_INPUT_3_VOLUME:
case ARIZONA_PWM2MIX_INPUT_4_SOURCE:
case ARIZONA_PWM2MIX_INPUT_4_VOLUME:
case ARIZONA_MICMIX_INPUT_1_SOURCE:
case ARIZONA_MICMIX_INPUT_1_VOLUME:
case ARIZONA_MICMIX_INPUT_2_SOURCE:
case ARIZONA_MICMIX_INPUT_2_VOLUME:
case ARIZONA_MICMIX_INPUT_3_SOURCE:
case ARIZONA_MICMIX_INPUT_3_VOLUME:
case ARIZONA_MICMIX_INPUT_4_SOURCE:
case ARIZONA_MICMIX_INPUT_4_VOLUME:
case ARIZONA_NOISEMIX_INPUT_1_SOURCE:
case ARIZONA_NOISEMIX_INPUT_1_VOLUME:
case ARIZONA_NOISEMIX_INPUT_2_SOURCE:
case ARIZONA_NOISEMIX_INPUT_2_VOLUME:
case ARIZONA_NOISEMIX_INPUT_3_SOURCE:
case ARIZONA_NOISEMIX_INPUT_3_VOLUME:
case ARIZONA_NOISEMIX_INPUT_4_SOURCE:
case ARIZONA_NOISEMIX_INPUT_4_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT1LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT1LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT1RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT1RMIX_INPUT_4_VOLUME:
case ARIZONA_OUT2LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT2LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT2LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT2LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT2LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT2LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT2LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT2LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT2RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT2RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT2RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT2RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT2RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT2RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT2RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT2RMIX_INPUT_4_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT3LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT3LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT4LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT4LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT4RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT4RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT4RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT4RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT4RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT4RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT4RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT4RMIX_INPUT_4_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_1_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_1_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_2_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_2_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_3_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_3_VOLUME:
case ARIZONA_OUT5LMIX_INPUT_4_SOURCE:
case ARIZONA_OUT5LMIX_INPUT_4_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_1_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_1_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_2_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_2_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_3_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_3_VOLUME:
case ARIZONA_OUT5RMIX_INPUT_4_SOURCE:
case ARIZONA_OUT5RMIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME:
case ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE:
case ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME:
case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE:
case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME:
case ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE:
case ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME:
case ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE:
case ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME:
case ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE:
case ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME:
case ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE:
case ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME:
case ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE:
case ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME:
case ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE:
case ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME:
case ARIZONA_EQ1MIX_INPUT_1_SOURCE:
case ARIZONA_EQ1MIX_INPUT_1_VOLUME:
case ARIZONA_EQ1MIX_INPUT_2_SOURCE:
case ARIZONA_EQ1MIX_INPUT_2_VOLUME:
case ARIZONA_EQ1MIX_INPUT_3_SOURCE:
case ARIZONA_EQ1MIX_INPUT_3_VOLUME:
case ARIZONA_EQ1MIX_INPUT_4_SOURCE:
case ARIZONA_EQ1MIX_INPUT_4_VOLUME:
case ARIZONA_EQ2MIX_INPUT_1_SOURCE:
case ARIZONA_EQ2MIX_INPUT_1_VOLUME:
case ARIZONA_EQ2MIX_INPUT_2_SOURCE:
case ARIZONA_EQ2MIX_INPUT_2_VOLUME:
case ARIZONA_EQ2MIX_INPUT_3_SOURCE:
case ARIZONA_EQ2MIX_INPUT_3_VOLUME:
case ARIZONA_EQ2MIX_INPUT_4_SOURCE:
case ARIZONA_EQ2MIX_INPUT_4_VOLUME:
case ARIZONA_EQ3MIX_INPUT_1_SOURCE:
case ARIZONA_EQ3MIX_INPUT_1_VOLUME:
case ARIZONA_EQ3MIX_INPUT_2_SOURCE:
case ARIZONA_EQ3MIX_INPUT_2_VOLUME:
case ARIZONA_EQ3MIX_INPUT_3_SOURCE:
case ARIZONA_EQ3MIX_INPUT_3_VOLUME:
case ARIZONA_EQ3MIX_INPUT_4_SOURCE:
case ARIZONA_EQ3MIX_INPUT_4_VOLUME:
case ARIZONA_EQ4MIX_INPUT_1_SOURCE:
case ARIZONA_EQ4MIX_INPUT_1_VOLUME:
case ARIZONA_EQ4MIX_INPUT_2_SOURCE:
case ARIZONA_EQ4MIX_INPUT_2_VOLUME:
case ARIZONA_EQ4MIX_INPUT_3_SOURCE:
case ARIZONA_EQ4MIX_INPUT_3_VOLUME:
case ARIZONA_EQ4MIX_INPUT_4_SOURCE:
case ARIZONA_EQ4MIX_INPUT_4_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_1_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_1_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_2_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_2_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_3_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_3_VOLUME:
case ARIZONA_DRC1LMIX_INPUT_4_SOURCE:
case ARIZONA_DRC1LMIX_INPUT_4_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_1_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_1_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_2_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_2_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_3_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_3_VOLUME:
case ARIZONA_DRC1RMIX_INPUT_4_SOURCE:
case ARIZONA_DRC1RMIX_INPUT_4_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP1MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP1MIX_INPUT_4_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP2MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP2MIX_INPUT_4_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP3MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP3MIX_INPUT_4_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_1_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_1_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_2_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_2_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_3_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_3_VOLUME:
case ARIZONA_HPLP4MIX_INPUT_4_SOURCE:
case ARIZONA_HPLP4MIX_INPUT_4_VOLUME:
case ARIZONA_DSP1LMIX_INPUT_1_SOURCE:
case ARIZONA_DSP1LMIX_INPUT_1_VOLUME:
case ARIZONA_DSP1LMIX_INPUT_2_SOURCE:
case ARIZONA_DSP1LMIX_INPUT_2_VOLUME:
case ARIZONA_DSP1LMIX_INPUT_3_SOURCE:
case ARIZONA_DSP1LMIX_INPUT_3_VOLUME:
case ARIZONA_DSP1LMIX_INPUT_4_SOURCE:
case ARIZONA_DSP1LMIX_INPUT_4_VOLUME:
case ARIZONA_DSP1RMIX_INPUT_1_SOURCE:
case ARIZONA_DSP1RMIX_INPUT_1_VOLUME:
case ARIZONA_DSP1RMIX_INPUT_2_SOURCE:
case ARIZONA_DSP1RMIX_INPUT_2_VOLUME:
case ARIZONA_DSP1RMIX_INPUT_3_SOURCE:
case ARIZONA_DSP1RMIX_INPUT_3_VOLUME:
case ARIZONA_DSP1RMIX_INPUT_4_SOURCE:
case ARIZONA_DSP1RMIX_INPUT_4_VOLUME:
case ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE:
case ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE:
case ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE:
case ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE:
case ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE:
case ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE:
case ARIZONA_ASRC1LMIX_INPUT_1_SOURCE:
case ARIZONA_ASRC1RMIX_INPUT_1_SOURCE:
case ARIZONA_ASRC2LMIX_INPUT_1_SOURCE:
case ARIZONA_ASRC2RMIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE:
case ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE:
case ARIZONA_GPIO1_CTRL:
case ARIZONA_GPIO2_CTRL:
case ARIZONA_GPIO3_CTRL:
case ARIZONA_GPIO4_CTRL:
case ARIZONA_GPIO5_CTRL:
case ARIZONA_IRQ_CTRL_1:
case ARIZONA_GPIO_DEBOUNCE_CONFIG:
case ARIZONA_MISC_PAD_CTRL_1:
case ARIZONA_MISC_PAD_CTRL_2:
case ARIZONA_MISC_PAD_CTRL_3:
case ARIZONA_MISC_PAD_CTRL_4:
case ARIZONA_MISC_PAD_CTRL_5:
case ARIZONA_MISC_PAD_CTRL_6:
case ARIZONA_INTERRUPT_STATUS_1:
case ARIZONA_INTERRUPT_STATUS_2:
case ARIZONA_INTERRUPT_STATUS_3:
case ARIZONA_INTERRUPT_STATUS_4:
case ARIZONA_INTERRUPT_STATUS_5:
case ARIZONA_INTERRUPT_STATUS_1_MASK:
case ARIZONA_INTERRUPT_STATUS_2_MASK:
case ARIZONA_INTERRUPT_STATUS_3_MASK:
case ARIZONA_INTERRUPT_STATUS_4_MASK:
case ARIZONA_INTERRUPT_STATUS_5_MASK:
case ARIZONA_INTERRUPT_CONTROL:
case ARIZONA_IRQ2_STATUS_1:
case ARIZONA_IRQ2_STATUS_2:
case ARIZONA_IRQ2_STATUS_3:
case ARIZONA_IRQ2_STATUS_4:
case ARIZONA_IRQ2_STATUS_5:
case ARIZONA_IRQ2_STATUS_1_MASK:
case ARIZONA_IRQ2_STATUS_2_MASK:
case ARIZONA_IRQ2_STATUS_3_MASK:
case ARIZONA_IRQ2_STATUS_4_MASK:
case ARIZONA_IRQ2_STATUS_5_MASK:
case ARIZONA_IRQ2_CONTROL:
case ARIZONA_INTERRUPT_RAW_STATUS_2:
case ARIZONA_INTERRUPT_RAW_STATUS_3:
case ARIZONA_INTERRUPT_RAW_STATUS_4:
case ARIZONA_INTERRUPT_RAW_STATUS_5:
case ARIZONA_INTERRUPT_RAW_STATUS_6:
case ARIZONA_INTERRUPT_RAW_STATUS_7:
case ARIZONA_INTERRUPT_RAW_STATUS_8:
case ARIZONA_IRQ_PIN_STATUS:
case ARIZONA_ADSP2_IRQ0:
case ARIZONA_AOD_WKUP_AND_TRIG:
case ARIZONA_AOD_IRQ1:
case ARIZONA_AOD_IRQ2:
case ARIZONA_AOD_IRQ_MASK_IRQ1:
case ARIZONA_AOD_IRQ_MASK_IRQ2:
case ARIZONA_AOD_IRQ_RAW_STATUS:
case ARIZONA_JACK_DETECT_DEBOUNCE:
case ARIZONA_FX_CTRL1:
case ARIZONA_FX_CTRL2:
case ARIZONA_EQ1_1:
case ARIZONA_EQ1_2:
case ARIZONA_EQ1_3:
case ARIZONA_EQ1_4:
case ARIZONA_EQ1_5:
case ARIZONA_EQ1_6:
case ARIZONA_EQ1_7:
case ARIZONA_EQ1_8:
case ARIZONA_EQ1_9:
case ARIZONA_EQ1_10:
case ARIZONA_EQ1_11:
case ARIZONA_EQ1_12:
case ARIZONA_EQ1_13:
case ARIZONA_EQ1_14:
case ARIZONA_EQ1_15:
case ARIZONA_EQ1_16:
case ARIZONA_EQ1_17:
case ARIZONA_EQ1_18:
case ARIZONA_EQ1_19:
case ARIZONA_EQ1_20:
case ARIZONA_EQ1_21:
case ARIZONA_EQ2_1:
case ARIZONA_EQ2_2:
case ARIZONA_EQ2_3:
case ARIZONA_EQ2_4:
case ARIZONA_EQ2_5:
case ARIZONA_EQ2_6:
case ARIZONA_EQ2_7:
case ARIZONA_EQ2_8:
case ARIZONA_EQ2_9:
case ARIZONA_EQ2_10:
case ARIZONA_EQ2_11:
case ARIZONA_EQ2_12:
case ARIZONA_EQ2_13:
case ARIZONA_EQ2_14:
case ARIZONA_EQ2_15:
case ARIZONA_EQ2_16:
case ARIZONA_EQ2_17:
case ARIZONA_EQ2_18:
case ARIZONA_EQ2_19:
case ARIZONA_EQ2_20:
case ARIZONA_EQ2_21:
case ARIZONA_EQ3_1:
case ARIZONA_EQ3_2:
case ARIZONA_EQ3_3:
case ARIZONA_EQ3_4:
case ARIZONA_EQ3_5:
case ARIZONA_EQ3_6:
case ARIZONA_EQ3_7:
case ARIZONA_EQ3_8:
case ARIZONA_EQ3_9:
case ARIZONA_EQ3_10:
case ARIZONA_EQ3_11:
case ARIZONA_EQ3_12:
case ARIZONA_EQ3_13:
case ARIZONA_EQ3_14:
case ARIZONA_EQ3_15:
case ARIZONA_EQ3_16:
case ARIZONA_EQ3_17:
case ARIZONA_EQ3_18:
case ARIZONA_EQ3_19:
case ARIZONA_EQ3_20:
case ARIZONA_EQ3_21:
case ARIZONA_EQ4_1:
case ARIZONA_EQ4_2:
case ARIZONA_EQ4_3:
case ARIZONA_EQ4_4:
case ARIZONA_EQ4_5:
case ARIZONA_EQ4_6:
case ARIZONA_EQ4_7:
case ARIZONA_EQ4_8:
case ARIZONA_EQ4_9:
case ARIZONA_EQ4_10:
case ARIZONA_EQ4_11:
case ARIZONA_EQ4_12:
case ARIZONA_EQ4_13:
case ARIZONA_EQ4_14:
case ARIZONA_EQ4_15:
case ARIZONA_EQ4_16:
case ARIZONA_EQ4_17:
case ARIZONA_EQ4_18:
case ARIZONA_EQ4_19:
case ARIZONA_EQ4_20:
case ARIZONA_EQ4_21:
case ARIZONA_DRC1_CTRL1:
case ARIZONA_DRC1_CTRL2:
case ARIZONA_DRC1_CTRL3:
case ARIZONA_DRC1_CTRL4:
case ARIZONA_DRC1_CTRL5:
case ARIZONA_HPLPF1_1:
case ARIZONA_HPLPF1_2:
case ARIZONA_HPLPF2_1:
case ARIZONA_HPLPF2_2:
case ARIZONA_HPLPF3_1:
case ARIZONA_HPLPF3_2:
case ARIZONA_HPLPF4_1:
case ARIZONA_HPLPF4_2:
case ARIZONA_ASRC_ENABLE:
case ARIZONA_ASRC_RATE1:
case ARIZONA_ASRC_RATE2:
case ARIZONA_ISRC_1_CTRL_1:
case ARIZONA_ISRC_1_CTRL_2:
case ARIZONA_ISRC_1_CTRL_3:
case ARIZONA_ISRC_2_CTRL_1:
case ARIZONA_ISRC_2_CTRL_2:
case ARIZONA_ISRC_2_CTRL_3:
case ARIZONA_DSP1_CONTROL_1:
case ARIZONA_DSP1_CLOCKING_1:
case ARIZONA_DSP1_STATUS_1:
case ARIZONA_DSP1_STATUS_2:
case ARIZONA_DSP1_STATUS_3:
case ARIZONA_DSP1_WDMA_BUFFER_1:
case ARIZONA_DSP1_WDMA_BUFFER_2:
case ARIZONA_DSP1_WDMA_BUFFER_3:
case ARIZONA_DSP1_WDMA_BUFFER_4:
case ARIZONA_DSP1_WDMA_BUFFER_5:
case ARIZONA_DSP1_WDMA_BUFFER_6:
case ARIZONA_DSP1_WDMA_BUFFER_7:
case ARIZONA_DSP1_WDMA_BUFFER_8:
case ARIZONA_DSP1_RDMA_BUFFER_1:
case ARIZONA_DSP1_RDMA_BUFFER_2:
case ARIZONA_DSP1_RDMA_BUFFER_3:
case ARIZONA_DSP1_RDMA_BUFFER_4:
case ARIZONA_DSP1_RDMA_BUFFER_5:
case ARIZONA_DSP1_RDMA_BUFFER_6:
case ARIZONA_DSP1_WDMA_CONFIG_1:
case ARIZONA_DSP1_WDMA_CONFIG_2:
case ARIZONA_DSP1_RDMA_CONFIG_1:
case ARIZONA_DSP1_SCRATCH_0:
case ARIZONA_DSP1_SCRATCH_1:
case ARIZONA_DSP1_SCRATCH_2:
case ARIZONA_DSP1_SCRATCH_3:
return true;
default:
if ((reg >= 0x100000 && reg < 0x106000) ||
(reg >= 0x180000 && reg < 0x180800) ||
(reg >= 0x190000 && reg < 0x194800) ||
(reg >= 0x1a8000 && reg < 0x1a9800))
return true;
else
return false;
}
}
static bool wm5102_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case ARIZONA_SOFTWARE_RESET:
case ARIZONA_DEVICE_REVISION:
case ARIZONA_WRITE_SEQUENCER_CTRL_0:
case ARIZONA_WRITE_SEQUENCER_CTRL_1:
case ARIZONA_WRITE_SEQUENCER_CTRL_2:
case ARIZONA_WRITE_SEQUENCER_CTRL_3:
case ARIZONA_OUTPUT_STATUS_1:
case ARIZONA_SLIMBUS_RX_PORT_STATUS:
case ARIZONA_SLIMBUS_TX_PORT_STATUS:
case ARIZONA_SAMPLE_RATE_1_STATUS:
case ARIZONA_SAMPLE_RATE_2_STATUS:
case ARIZONA_SAMPLE_RATE_3_STATUS:
case ARIZONA_HAPTICS_STATUS:
case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS:
case ARIZONA_DAC_COMP_1:
case ARIZONA_DAC_COMP_2:
case ARIZONA_DAC_COMP_3:
case ARIZONA_DAC_COMP_4:
case ARIZONA_FX_CTRL2:
case ARIZONA_INTERRUPT_STATUS_1:
case ARIZONA_INTERRUPT_STATUS_2:
case ARIZONA_INTERRUPT_STATUS_3:
case ARIZONA_INTERRUPT_STATUS_4:
case ARIZONA_INTERRUPT_STATUS_5:
case ARIZONA_IRQ2_STATUS_1:
case ARIZONA_IRQ2_STATUS_2:
case ARIZONA_IRQ2_STATUS_3:
case ARIZONA_IRQ2_STATUS_4:
case ARIZONA_IRQ2_STATUS_5:
case ARIZONA_INTERRUPT_RAW_STATUS_2:
case ARIZONA_INTERRUPT_RAW_STATUS_3:
case ARIZONA_INTERRUPT_RAW_STATUS_4:
case ARIZONA_INTERRUPT_RAW_STATUS_5:
case ARIZONA_INTERRUPT_RAW_STATUS_6:
case ARIZONA_INTERRUPT_RAW_STATUS_7:
case ARIZONA_INTERRUPT_RAW_STATUS_8:
case ARIZONA_IRQ_PIN_STATUS:
case ARIZONA_AOD_WKUP_AND_TRIG:
case ARIZONA_AOD_IRQ1:
case ARIZONA_AOD_IRQ2:
case ARIZONA_AOD_IRQ_RAW_STATUS:
case ARIZONA_DSP1_CLOCKING_1:
case ARIZONA_DSP1_STATUS_1:
case ARIZONA_DSP1_STATUS_2:
case ARIZONA_DSP1_STATUS_3:
case ARIZONA_DSP1_WDMA_BUFFER_1:
case ARIZONA_DSP1_WDMA_BUFFER_2:
case ARIZONA_DSP1_WDMA_BUFFER_3:
case ARIZONA_DSP1_WDMA_BUFFER_4:
case ARIZONA_DSP1_WDMA_BUFFER_5:
case ARIZONA_DSP1_WDMA_BUFFER_6:
case ARIZONA_DSP1_WDMA_BUFFER_7:
case ARIZONA_DSP1_WDMA_BUFFER_8:
case ARIZONA_DSP1_RDMA_BUFFER_1:
case ARIZONA_DSP1_RDMA_BUFFER_2:
case ARIZONA_DSP1_RDMA_BUFFER_3:
case ARIZONA_DSP1_RDMA_BUFFER_4:
case ARIZONA_DSP1_RDMA_BUFFER_5:
case ARIZONA_DSP1_RDMA_BUFFER_6:
case ARIZONA_DSP1_WDMA_CONFIG_1:
case ARIZONA_DSP1_WDMA_CONFIG_2:
case ARIZONA_DSP1_RDMA_CONFIG_1:
case ARIZONA_DSP1_SCRATCH_0:
case ARIZONA_DSP1_SCRATCH_1:
case ARIZONA_DSP1_SCRATCH_2:
case ARIZONA_DSP1_SCRATCH_3:
case ARIZONA_HP_CTRL_1L:
case ARIZONA_HP_CTRL_1R:
case ARIZONA_HEADPHONE_DETECT_2:
case ARIZONA_HP_DACVAL:
case ARIZONA_MIC_DETECT_3:
return true;
default:
if ((reg >= 0x100000 && reg < 0x106000) ||
(reg >= 0x180000 && reg < 0x180800) ||
(reg >= 0x190000 && reg < 0x194800) ||
(reg >= 0x1a8000 && reg < 0x1a9800))
return true;
else
return false;
}
}
#define WM5102_MAX_REGISTER 0x1a9800
const struct regmap_config wm5102_spi_regmap = {
.reg_bits = 32,
.pad_bits = 16,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = WM5102_MAX_REGISTER,
.readable_reg = wm5102_readable_register,
.volatile_reg = wm5102_volatile_register,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = wm5102_reg_default,
.num_reg_defaults = ARRAY_SIZE(wm5102_reg_default),
};
EXPORT_SYMBOL_GPL(wm5102_spi_regmap);
const struct regmap_config wm5102_i2c_regmap = {
.reg_bits = 32,
.val_bits = 16,
.reg_format_endian = REGMAP_ENDIAN_BIG,
.val_format_endian = REGMAP_ENDIAN_BIG,
.max_register = WM5102_MAX_REGISTER,
.readable_reg = wm5102_readable_register,
.volatile_reg = wm5102_volatile_register,
.cache_type = REGCACHE_MAPLE,
.reg_defaults = wm5102_reg_default,
.num_reg_defaults = ARRAY_SIZE(wm5102_reg_default),
};
EXPORT_SYMBOL_GPL(wm5102_i2c_regmap);
| linux-master | drivers/mfd/wm5102-tables.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#include <linux/bitops.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/consumer.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <dt-bindings/mfd/qcom-pm8008.h>
#define I2C_INTR_STATUS_BASE 0x0550
#define INT_RT_STS_OFFSET 0x10
#define INT_SET_TYPE_OFFSET 0x11
#define INT_POL_HIGH_OFFSET 0x12
#define INT_POL_LOW_OFFSET 0x13
#define INT_LATCHED_CLR_OFFSET 0x14
#define INT_EN_SET_OFFSET 0x15
#define INT_EN_CLR_OFFSET 0x16
#define INT_LATCHED_STS_OFFSET 0x18
enum {
PM8008_MISC,
PM8008_TEMP_ALARM,
PM8008_GPIO1,
PM8008_GPIO2,
PM8008_NUM_PERIPHS,
};
#define PM8008_PERIPH_0_BASE 0x900
#define PM8008_PERIPH_1_BASE 0x2400
#define PM8008_PERIPH_2_BASE 0xC000
#define PM8008_PERIPH_3_BASE 0xC100
#define PM8008_TEMP_ALARM_ADDR PM8008_PERIPH_1_BASE
#define PM8008_GPIO1_ADDR PM8008_PERIPH_2_BASE
#define PM8008_GPIO2_ADDR PM8008_PERIPH_3_BASE
enum {
SET_TYPE_INDEX,
POLARITY_HI_INDEX,
POLARITY_LO_INDEX,
};
static unsigned int pm8008_config_regs[] = {
INT_SET_TYPE_OFFSET,
INT_POL_HIGH_OFFSET,
INT_POL_LOW_OFFSET,
};
static struct regmap_irq pm8008_irqs[] = {
REGMAP_IRQ_REG(PM8008_IRQ_MISC_UVLO, PM8008_MISC, BIT(0)),
REGMAP_IRQ_REG(PM8008_IRQ_MISC_OVLO, PM8008_MISC, BIT(1)),
REGMAP_IRQ_REG(PM8008_IRQ_MISC_OTST2, PM8008_MISC, BIT(2)),
REGMAP_IRQ_REG(PM8008_IRQ_MISC_OTST3, PM8008_MISC, BIT(3)),
REGMAP_IRQ_REG(PM8008_IRQ_MISC_LDO_OCP, PM8008_MISC, BIT(4)),
REGMAP_IRQ_REG(PM8008_IRQ_TEMP_ALARM, PM8008_TEMP_ALARM, BIT(0)),
REGMAP_IRQ_REG(PM8008_IRQ_GPIO1, PM8008_GPIO1, BIT(0)),
REGMAP_IRQ_REG(PM8008_IRQ_GPIO2, PM8008_GPIO2, BIT(0)),
};
static const unsigned int pm8008_periph_base[] = {
PM8008_PERIPH_0_BASE,
PM8008_PERIPH_1_BASE,
PM8008_PERIPH_2_BASE,
PM8008_PERIPH_3_BASE,
};
static unsigned int pm8008_get_irq_reg(struct regmap_irq_chip_data *data,
unsigned int base, int index)
{
/* Simple linear addressing for the main status register */
if (base == I2C_INTR_STATUS_BASE)
return base + index;
return pm8008_periph_base[index] + base;
}
static int pm8008_set_type_config(unsigned int **buf, unsigned int type,
const struct regmap_irq *irq_data, int idx,
void *irq_drv_data)
{
switch (type) {
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_LEVEL_LOW:
buf[POLARITY_HI_INDEX][idx] &= ~irq_data->mask;
buf[POLARITY_LO_INDEX][idx] |= irq_data->mask;
break;
case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_LEVEL_HIGH:
buf[POLARITY_HI_INDEX][idx] |= irq_data->mask;
buf[POLARITY_LO_INDEX][idx] &= ~irq_data->mask;
break;
case IRQ_TYPE_EDGE_BOTH:
buf[POLARITY_HI_INDEX][idx] |= irq_data->mask;
buf[POLARITY_LO_INDEX][idx] |= irq_data->mask;
break;
default:
return -EINVAL;
}
if (type & IRQ_TYPE_EDGE_BOTH)
buf[SET_TYPE_INDEX][idx] |= irq_data->mask;
else
buf[SET_TYPE_INDEX][idx] &= ~irq_data->mask;
return 0;
}
static struct regmap_irq_chip pm8008_irq_chip = {
.name = "pm8008_irq",
.main_status = I2C_INTR_STATUS_BASE,
.num_main_regs = 1,
.irqs = pm8008_irqs,
.num_irqs = ARRAY_SIZE(pm8008_irqs),
.num_regs = PM8008_NUM_PERIPHS,
.status_base = INT_LATCHED_STS_OFFSET,
.mask_base = INT_EN_CLR_OFFSET,
.unmask_base = INT_EN_SET_OFFSET,
.mask_unmask_non_inverted = true,
.ack_base = INT_LATCHED_CLR_OFFSET,
.config_base = pm8008_config_regs,
.num_config_bases = ARRAY_SIZE(pm8008_config_regs),
.num_config_regs = PM8008_NUM_PERIPHS,
.set_type_config = pm8008_set_type_config,
.get_irq_reg = pm8008_get_irq_reg,
};
static struct regmap_config qcom_mfd_regmap_cfg = {
.reg_bits = 16,
.val_bits = 8,
.max_register = 0xFFFF,
};
static int pm8008_probe_irq_peripherals(struct device *dev,
struct regmap *regmap,
int client_irq)
{
int rc, i;
struct regmap_irq_type *type;
struct regmap_irq_chip_data *irq_data;
for (i = 0; i < ARRAY_SIZE(pm8008_irqs); i++) {
type = &pm8008_irqs[i].type;
type->type_reg_offset = pm8008_irqs[i].reg_offset;
if (type->type_reg_offset == PM8008_MISC)
type->types_supported = IRQ_TYPE_EDGE_RISING;
else
type->types_supported = (IRQ_TYPE_EDGE_BOTH |
IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW);
}
rc = devm_regmap_add_irq_chip(dev, regmap, client_irq,
IRQF_SHARED, 0, &pm8008_irq_chip, &irq_data);
if (rc) {
dev_err(dev, "Failed to add IRQ chip: %d\n", rc);
return rc;
}
return 0;
}
static int pm8008_probe(struct i2c_client *client)
{
int rc;
struct device *dev;
struct regmap *regmap;
dev = &client->dev;
regmap = devm_regmap_init_i2c(client, &qcom_mfd_regmap_cfg);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
i2c_set_clientdata(client, regmap);
if (of_property_read_bool(dev->of_node, "interrupt-controller")) {
rc = pm8008_probe_irq_peripherals(dev, regmap, client->irq);
if (rc)
dev_err(dev, "Failed to probe irq periphs: %d\n", rc);
}
return devm_of_platform_populate(dev);
}
static const struct of_device_id pm8008_match[] = {
{ .compatible = "qcom,pm8008", },
{ },
};
MODULE_DEVICE_TABLE(of, pm8008_match);
static struct i2c_driver pm8008_mfd_driver = {
.driver = {
.name = "pm8008",
.of_match_table = pm8008_match,
},
.probe = pm8008_probe,
};
module_i2c_driver(pm8008_mfd_driver);
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/qcom-pm8008.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
*
* Author: Keerthy <[email protected]>
*/
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/mfd/lp873x.h>
static const struct regmap_config lp873x_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = LP873X_REG_MAX,
};
static const struct mfd_cell lp873x_cells[] = {
{ .name = "lp873x-regulator", },
{ .name = "lp873x-gpio", },
};
static int lp873x_probe(struct i2c_client *client)
{
struct lp873x *lp873;
int ret;
unsigned int otpid;
lp873 = devm_kzalloc(&client->dev, sizeof(*lp873), GFP_KERNEL);
if (!lp873)
return -ENOMEM;
lp873->dev = &client->dev;
lp873->regmap = devm_regmap_init_i2c(client, &lp873x_regmap_config);
if (IS_ERR(lp873->regmap)) {
ret = PTR_ERR(lp873->regmap);
dev_err(lp873->dev,
"Failed to initialize register map: %d\n", ret);
return ret;
}
ret = regmap_read(lp873->regmap, LP873X_REG_OTP_REV, &otpid);
if (ret) {
dev_err(lp873->dev, "Failed to read OTP ID\n");
return ret;
}
lp873->rev = otpid & LP873X_OTP_REV_OTP_ID;
i2c_set_clientdata(client, lp873);
ret = mfd_add_devices(lp873->dev, PLATFORM_DEVID_AUTO, lp873x_cells,
ARRAY_SIZE(lp873x_cells), NULL, 0, NULL);
return ret;
}
static const struct of_device_id of_lp873x_match_table[] = {
{ .compatible = "ti,lp8733", },
{ .compatible = "ti,lp8732", },
{}
};
MODULE_DEVICE_TABLE(of, of_lp873x_match_table);
static const struct i2c_device_id lp873x_id_table[] = {
{ "lp873x", 0 },
{ },
};
MODULE_DEVICE_TABLE(i2c, lp873x_id_table);
static struct i2c_driver lp873x_driver = {
.driver = {
.name = "lp873x",
.of_match_table = of_lp873x_match_table,
},
.probe = lp873x_probe,
.id_table = lp873x_id_table,
};
module_i2c_driver(lp873x_driver);
MODULE_AUTHOR("J Keerthy <[email protected]>");
MODULE_DESCRIPTION("LP873X chip family Multi-Function Device driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/lp873x.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Core driver for ams AS3722 PMICs
*
* Copyright (C) 2013 AMS AG
* Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
*
* Author: Florian Lobmaier <[email protected]>
* Author: Laxman Dewangan <[email protected]>
*/
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mfd/core.h>
#include <linux/mfd/as3722.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#define AS3722_DEVICE_ID 0x0C
static const struct resource as3722_rtc_resource[] = {
DEFINE_RES_IRQ_NAMED(AS3722_IRQ_RTC_ALARM, "as3722-rtc-alarm"),
};
static const struct resource as3722_adc_resource[] = {
DEFINE_RES_IRQ_NAMED(AS3722_IRQ_ADC, "as3722-adc"),
};
static const struct mfd_cell as3722_devs[] = {
{
.name = "as3722-pinctrl",
},
{
.name = "as3722-regulator",
},
{
.name = "as3722-rtc",
.num_resources = ARRAY_SIZE(as3722_rtc_resource),
.resources = as3722_rtc_resource,
},
{
.name = "as3722-adc",
.num_resources = ARRAY_SIZE(as3722_adc_resource),
.resources = as3722_adc_resource,
},
{
.name = "as3722-power-off",
},
{
.name = "as3722-wdt",
},
};
static const struct regmap_irq as3722_irqs[] = {
/* INT1 IRQs */
[AS3722_IRQ_LID] = {
.mask = AS3722_INTERRUPT_MASK1_LID,
},
[AS3722_IRQ_ACOK] = {
.mask = AS3722_INTERRUPT_MASK1_ACOK,
},
[AS3722_IRQ_ENABLE1] = {
.mask = AS3722_INTERRUPT_MASK1_ENABLE1,
},
[AS3722_IRQ_OCCUR_ALARM_SD0] = {
.mask = AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0,
},
[AS3722_IRQ_ONKEY_LONG_PRESS] = {
.mask = AS3722_INTERRUPT_MASK1_ONKEY_LONG,
},
[AS3722_IRQ_ONKEY] = {
.mask = AS3722_INTERRUPT_MASK1_ONKEY,
},
[AS3722_IRQ_OVTMP] = {
.mask = AS3722_INTERRUPT_MASK1_OVTMP,
},
[AS3722_IRQ_LOWBAT] = {
.mask = AS3722_INTERRUPT_MASK1_LOWBAT,
},
/* INT2 IRQs */
[AS3722_IRQ_SD0_LV] = {
.mask = AS3722_INTERRUPT_MASK2_SD0_LV,
.reg_offset = 1,
},
[AS3722_IRQ_SD1_LV] = {
.mask = AS3722_INTERRUPT_MASK2_SD1_LV,
.reg_offset = 1,
},
[AS3722_IRQ_SD2_LV] = {
.mask = AS3722_INTERRUPT_MASK2_SD2345_LV,
.reg_offset = 1,
},
[AS3722_IRQ_PWM1_OV_PROT] = {
.mask = AS3722_INTERRUPT_MASK2_PWM1_OV_PROT,
.reg_offset = 1,
},
[AS3722_IRQ_PWM2_OV_PROT] = {
.mask = AS3722_INTERRUPT_MASK2_PWM2_OV_PROT,
.reg_offset = 1,
},
[AS3722_IRQ_ENABLE2] = {
.mask = AS3722_INTERRUPT_MASK2_ENABLE2,
.reg_offset = 1,
},
[AS3722_IRQ_SD6_LV] = {
.mask = AS3722_INTERRUPT_MASK2_SD6_LV,
.reg_offset = 1,
},
[AS3722_IRQ_RTC_REP] = {
.mask = AS3722_INTERRUPT_MASK2_RTC_REP,
.reg_offset = 1,
},
/* INT3 IRQs */
[AS3722_IRQ_RTC_ALARM] = {
.mask = AS3722_INTERRUPT_MASK3_RTC_ALARM,
.reg_offset = 2,
},
[AS3722_IRQ_GPIO1] = {
.mask = AS3722_INTERRUPT_MASK3_GPIO1,
.reg_offset = 2,
},
[AS3722_IRQ_GPIO2] = {
.mask = AS3722_INTERRUPT_MASK3_GPIO2,
.reg_offset = 2,
},
[AS3722_IRQ_GPIO3] = {
.mask = AS3722_INTERRUPT_MASK3_GPIO3,
.reg_offset = 2,
},
[AS3722_IRQ_GPIO4] = {
.mask = AS3722_INTERRUPT_MASK3_GPIO4,
.reg_offset = 2,
},
[AS3722_IRQ_GPIO5] = {
.mask = AS3722_INTERRUPT_MASK3_GPIO5,
.reg_offset = 2,
},
[AS3722_IRQ_WATCHDOG] = {
.mask = AS3722_INTERRUPT_MASK3_WATCHDOG,
.reg_offset = 2,
},
[AS3722_IRQ_ENABLE3] = {
.mask = AS3722_INTERRUPT_MASK3_ENABLE3,
.reg_offset = 2,
},
/* INT4 IRQs */
[AS3722_IRQ_TEMP_SD0_SHUTDOWN] = {
.mask = AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN,
.reg_offset = 3,
},
[AS3722_IRQ_TEMP_SD1_SHUTDOWN] = {
.mask = AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN,
.reg_offset = 3,
},
[AS3722_IRQ_TEMP_SD2_SHUTDOWN] = {
.mask = AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN,
.reg_offset = 3,
},
[AS3722_IRQ_TEMP_SD0_ALARM] = {
.mask = AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM,
.reg_offset = 3,
},
[AS3722_IRQ_TEMP_SD1_ALARM] = {
.mask = AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM,
.reg_offset = 3,
},
[AS3722_IRQ_TEMP_SD6_ALARM] = {
.mask = AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM,
.reg_offset = 3,
},
[AS3722_IRQ_OCCUR_ALARM_SD6] = {
.mask = AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6,
.reg_offset = 3,
},
[AS3722_IRQ_ADC] = {
.mask = AS3722_INTERRUPT_MASK4_ADC,
.reg_offset = 3,
},
};
static const struct regmap_irq_chip as3722_irq_chip = {
.name = "as3722",
.irqs = as3722_irqs,
.num_irqs = ARRAY_SIZE(as3722_irqs),
.num_regs = 4,
.status_base = AS3722_INTERRUPT_STATUS1_REG,
.mask_base = AS3722_INTERRUPT_MASK1_REG,
};
static int as3722_check_device_id(struct as3722 *as3722)
{
u32 val;
int ret;
/* Check that this is actually a AS3722 */
ret = as3722_read(as3722, AS3722_ASIC_ID1_REG, &val);
if (ret < 0) {
dev_err(as3722->dev, "ASIC_ID1 read failed: %d\n", ret);
return ret;
}
if (val != AS3722_DEVICE_ID) {
dev_err(as3722->dev, "Device is not AS3722, ID is 0x%x\n", val);
return -ENODEV;
}
ret = as3722_read(as3722, AS3722_ASIC_ID2_REG, &val);
if (ret < 0) {
dev_err(as3722->dev, "ASIC_ID2 read failed: %d\n", ret);
return ret;
}
dev_info(as3722->dev, "AS3722 with revision 0x%x found\n", val);
return 0;
}
static int as3722_configure_pullups(struct as3722 *as3722)
{
int ret;
u32 val = 0;
if (as3722->en_intern_int_pullup)
val |= AS3722_INT_PULL_UP;
if (as3722->en_intern_i2c_pullup)
val |= AS3722_I2C_PULL_UP;
ret = as3722_update_bits(as3722, AS3722_IOVOLTAGE_REG,
AS3722_INT_PULL_UP | AS3722_I2C_PULL_UP, val);
if (ret < 0)
dev_err(as3722->dev, "IOVOLTAGE_REG update failed: %d\n", ret);
return ret;
}
static const struct regmap_range as3722_readable_ranges[] = {
regmap_reg_range(AS3722_SD0_VOLTAGE_REG, AS3722_SD6_VOLTAGE_REG),
regmap_reg_range(AS3722_GPIO0_CONTROL_REG, AS3722_LDO7_VOLTAGE_REG),
regmap_reg_range(AS3722_LDO9_VOLTAGE_REG, AS3722_REG_SEQU_MOD3_REG),
regmap_reg_range(AS3722_SD_PHSW_CTRL_REG, AS3722_PWM_CONTROL_H_REG),
regmap_reg_range(AS3722_WATCHDOG_TIMER_REG, AS3722_WATCHDOG_TIMER_REG),
regmap_reg_range(AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG,
AS3722_BATTERY_VOLTAGE_MONITOR2_REG),
regmap_reg_range(AS3722_SD_CONTROL_REG, AS3722_PWM_VCONTROL4_REG),
regmap_reg_range(AS3722_BB_CHARGER_REG, AS3722_SRAM_REG),
regmap_reg_range(AS3722_RTC_ACCESS_REG, AS3722_RTC_ACCESS_REG),
regmap_reg_range(AS3722_RTC_STATUS_REG, AS3722_TEMP_STATUS_REG),
regmap_reg_range(AS3722_ADC0_CONTROL_REG, AS3722_ADC_CONFIGURATION_REG),
regmap_reg_range(AS3722_ASIC_ID1_REG, AS3722_ASIC_ID2_REG),
regmap_reg_range(AS3722_LOCK_REG, AS3722_LOCK_REG),
regmap_reg_range(AS3722_FUSE7_REG, AS3722_FUSE7_REG),
};
static const struct regmap_access_table as3722_readable_table = {
.yes_ranges = as3722_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(as3722_readable_ranges),
};
static const struct regmap_range as3722_writable_ranges[] = {
regmap_reg_range(AS3722_SD0_VOLTAGE_REG, AS3722_SD6_VOLTAGE_REG),
regmap_reg_range(AS3722_GPIO0_CONTROL_REG, AS3722_LDO7_VOLTAGE_REG),
regmap_reg_range(AS3722_LDO9_VOLTAGE_REG, AS3722_GPIO_SIGNAL_OUT_REG),
regmap_reg_range(AS3722_REG_SEQU_MOD1_REG, AS3722_REG_SEQU_MOD3_REG),
regmap_reg_range(AS3722_SD_PHSW_CTRL_REG, AS3722_PWM_CONTROL_H_REG),
regmap_reg_range(AS3722_WATCHDOG_TIMER_REG, AS3722_WATCHDOG_TIMER_REG),
regmap_reg_range(AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG,
AS3722_BATTERY_VOLTAGE_MONITOR2_REG),
regmap_reg_range(AS3722_SD_CONTROL_REG, AS3722_PWM_VCONTROL4_REG),
regmap_reg_range(AS3722_BB_CHARGER_REG, AS3722_SRAM_REG),
regmap_reg_range(AS3722_INTERRUPT_MASK1_REG, AS3722_TEMP_STATUS_REG),
regmap_reg_range(AS3722_ADC0_CONTROL_REG, AS3722_ADC1_CONTROL_REG),
regmap_reg_range(AS3722_ADC1_THRESHOLD_HI_MSB_REG,
AS3722_ADC_CONFIGURATION_REG),
regmap_reg_range(AS3722_LOCK_REG, AS3722_LOCK_REG),
};
static const struct regmap_access_table as3722_writable_table = {
.yes_ranges = as3722_writable_ranges,
.n_yes_ranges = ARRAY_SIZE(as3722_writable_ranges),
};
static const struct regmap_range as3722_cacheable_ranges[] = {
regmap_reg_range(AS3722_SD0_VOLTAGE_REG, AS3722_LDO11_VOLTAGE_REG),
regmap_reg_range(AS3722_SD_CONTROL_REG, AS3722_LDOCONTROL1_REG),
};
static const struct regmap_access_table as3722_volatile_table = {
.no_ranges = as3722_cacheable_ranges,
.n_no_ranges = ARRAY_SIZE(as3722_cacheable_ranges),
};
static const struct regmap_config as3722_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = AS3722_MAX_REGISTER,
.cache_type = REGCACHE_RBTREE,
.rd_table = &as3722_readable_table,
.wr_table = &as3722_writable_table,
.volatile_table = &as3722_volatile_table,
};
static int as3722_i2c_of_probe(struct i2c_client *i2c,
struct as3722 *as3722)
{
struct device_node *np = i2c->dev.of_node;
struct irq_data *irq_data;
if (!np) {
dev_err(&i2c->dev, "Device Tree not found\n");
return -EINVAL;
}
irq_data = irq_get_irq_data(i2c->irq);
if (!irq_data) {
dev_err(&i2c->dev, "Invalid IRQ: %d\n", i2c->irq);
return -EINVAL;
}
as3722->en_intern_int_pullup = of_property_read_bool(np,
"ams,enable-internal-int-pullup");
as3722->en_intern_i2c_pullup = of_property_read_bool(np,
"ams,enable-internal-i2c-pullup");
as3722->en_ac_ok_pwr_on = of_property_read_bool(np,
"ams,enable-ac-ok-power-on");
as3722->irq_flags = irqd_get_trigger_type(irq_data);
dev_dbg(&i2c->dev, "IRQ flags are 0x%08lx\n", as3722->irq_flags);
return 0;
}
static int as3722_i2c_probe(struct i2c_client *i2c)
{
struct as3722 *as3722;
unsigned long irq_flags;
int ret;
u8 val = 0;
as3722 = devm_kzalloc(&i2c->dev, sizeof(struct as3722), GFP_KERNEL);
if (!as3722)
return -ENOMEM;
as3722->dev = &i2c->dev;
as3722->chip_irq = i2c->irq;
i2c_set_clientdata(i2c, as3722);
ret = as3722_i2c_of_probe(i2c, as3722);
if (ret < 0)
return ret;
as3722->regmap = devm_regmap_init_i2c(i2c, &as3722_regmap_config);
if (IS_ERR(as3722->regmap)) {
ret = PTR_ERR(as3722->regmap);
dev_err(&i2c->dev, "regmap init failed: %d\n", ret);
return ret;
}
ret = as3722_check_device_id(as3722);
if (ret < 0)
return ret;
irq_flags = as3722->irq_flags | IRQF_ONESHOT;
ret = devm_regmap_add_irq_chip(as3722->dev, as3722->regmap,
as3722->chip_irq,
irq_flags, -1, &as3722_irq_chip,
&as3722->irq_data);
if (ret < 0) {
dev_err(as3722->dev, "Failed to add regmap irq: %d\n", ret);
return ret;
}
ret = as3722_configure_pullups(as3722);
if (ret < 0)
return ret;
if (as3722->en_ac_ok_pwr_on)
val = AS3722_CTRL_SEQU1_AC_OK_PWR_ON;
ret = as3722_update_bits(as3722, AS3722_CTRL_SEQU1_REG,
AS3722_CTRL_SEQU1_AC_OK_PWR_ON, val);
if (ret < 0) {
dev_err(as3722->dev, "CTRLsequ1 update failed: %d\n", ret);
return ret;
}
ret = devm_mfd_add_devices(&i2c->dev, -1, as3722_devs,
ARRAY_SIZE(as3722_devs), NULL, 0,
regmap_irq_get_domain(as3722->irq_data));
if (ret) {
dev_err(as3722->dev, "Failed to add MFD devices: %d\n", ret);
return ret;
}
device_init_wakeup(as3722->dev, true);
dev_dbg(as3722->dev, "AS3722 core driver initialized successfully\n");
return 0;
}
static int __maybe_unused as3722_i2c_suspend(struct device *dev)
{
struct as3722 *as3722 = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
enable_irq_wake(as3722->chip_irq);
disable_irq(as3722->chip_irq);
return 0;
}
static int __maybe_unused as3722_i2c_resume(struct device *dev)
{
struct as3722 *as3722 = dev_get_drvdata(dev);
enable_irq(as3722->chip_irq);
if (device_may_wakeup(dev))
disable_irq_wake(as3722->chip_irq);
return 0;
}
static const struct of_device_id as3722_of_match[] = {
{ .compatible = "ams,as3722", },
{},
};
MODULE_DEVICE_TABLE(of, as3722_of_match);
static const struct i2c_device_id as3722_i2c_id[] = {
{ "as3722", 0 },
{},
};
MODULE_DEVICE_TABLE(i2c, as3722_i2c_id);
static const struct dev_pm_ops as3722_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(as3722_i2c_suspend, as3722_i2c_resume)
};
static struct i2c_driver as3722_i2c_driver = {
.driver = {
.name = "as3722",
.of_match_table = as3722_of_match,
.pm = &as3722_pm_ops,
},
.probe = as3722_i2c_probe,
.id_table = as3722_i2c_id,
};
module_i2c_driver(as3722_i2c_driver);
MODULE_DESCRIPTION("I2C support for AS3722 PMICs");
MODULE_AUTHOR("Florian Lobmaier <[email protected]>");
MODULE_AUTHOR("Laxman Dewangan <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/as3722.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* twl6030-irq.c - TWL6030 irq support
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
*
* Modifications to defer interrupt handling to a kernel thread:
* Copyright (C) 2006 MontaVista Software, Inc.
*
* Based on tlv320aic23.c:
* Copyright (c) by Kai Svahn <[email protected]>
*
* Code cleanup and modifications to IRQ handler.
* by syed khasim <[email protected]>
*
* TWL6030 specific code and IRQ handling changes by
* Jagadeesh Bhaskar Pakaravoor <[email protected]>
* Balaji T K <[email protected]>
*/
#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kthread.h>
#include <linux/mfd/twl.h>
#include <linux/platform_device.h>
#include <linux/suspend.h>
#include <linux/of.h>
#include <linux/irqdomain.h>
#include <linux/of_device.h>
#include "twl-core.h"
/*
* TWL6030 (unlike its predecessors, which had two level interrupt handling)
* three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
* It exposes status bits saying who has raised an interrupt. There are
* three mask registers that corresponds to these status registers, that
* enables/disables these interrupts.
*
* We set up IRQs starting at a platform-specified base. An interrupt map table,
* specifies mapping between interrupt number and the associated module.
*/
#define TWL6030_NR_IRQS 20
static int twl6030_interrupt_mapping[24] = {
PWR_INTR_OFFSET, /* Bit 0 PWRON */
PWR_INTR_OFFSET, /* Bit 1 RPWRON */
PWR_INTR_OFFSET, /* Bit 2 BAT_VLOW */
RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
SMPSLDO_INTR_OFFSET, /* Bit 7 VMMC_SHORT */
SMPSLDO_INTR_OFFSET, /* Bit 8 VUSIM_SHORT */
BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
RSV_INTR_OFFSET, /* Bit 12 Reserved */
MADC_INTR_OFFSET, /* Bit 13 GPADC_RT_EOC */
MADC_INTR_OFFSET, /* Bit 14 GPADC_SW_EOC */
GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
USBOTG_INTR_OFFSET, /* Bit 18 ID */
USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
RSV_INTR_OFFSET, /* Bit 23 Reserved */
};
static int twl6032_interrupt_mapping[24] = {
PWR_INTR_OFFSET, /* Bit 0 PWRON */
PWR_INTR_OFFSET, /* Bit 1 RPWRON */
PWR_INTR_OFFSET, /* Bit 2 SYS_VLOW */
RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
PWR_INTR_OFFSET, /* Bit 7 SPDURATION */
PWR_INTR_OFFSET, /* Bit 8 WATCHDOG */
BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
MADC_INTR_OFFSET, /* Bit 12 GPADC_RT_EOC */
MADC_INTR_OFFSET, /* Bit 13 GPADC_SW_EOC */
GASGAUGE_INTR_OFFSET, /* Bit 14 CC_EOC */
GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
USBOTG_INTR_OFFSET, /* Bit 18 ID */
USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
RSV_INTR_OFFSET, /* Bit 23 Reserved */
};
/*----------------------------------------------------------------------*/
struct twl6030_irq {
unsigned int irq_base;
int twl_irq;
bool irq_wake_enabled;
atomic_t wakeirqs;
struct notifier_block pm_nb;
struct irq_chip irq_chip;
struct irq_domain *irq_domain;
const int *irq_mapping_tbl;
};
static struct twl6030_irq *twl6030_irq;
static int twl6030_irq_pm_notifier(struct notifier_block *notifier,
unsigned long pm_event, void *unused)
{
int chained_wakeups;
struct twl6030_irq *pdata = container_of(notifier, struct twl6030_irq,
pm_nb);
switch (pm_event) {
case PM_SUSPEND_PREPARE:
chained_wakeups = atomic_read(&pdata->wakeirqs);
if (chained_wakeups && !pdata->irq_wake_enabled) {
if (enable_irq_wake(pdata->twl_irq))
pr_err("twl6030 IRQ wake enable failed\n");
else
pdata->irq_wake_enabled = true;
} else if (!chained_wakeups && pdata->irq_wake_enabled) {
disable_irq_wake(pdata->twl_irq);
pdata->irq_wake_enabled = false;
}
disable_irq(pdata->twl_irq);
break;
case PM_POST_SUSPEND:
enable_irq(pdata->twl_irq);
break;
default:
break;
}
return NOTIFY_DONE;
}
/*
* Threaded irq handler for the twl6030 interrupt.
* We query the interrupt controller in the twl6030 to determine
* which module is generating the interrupt request and call
* handle_nested_irq for that module.
*/
static irqreturn_t twl6030_irq_thread(int irq, void *data)
{
int i, ret;
union {
u8 bytes[4];
__le32 int_sts;
} sts;
u32 int_sts; /* sts.int_sts converted to CPU endianness */
struct twl6030_irq *pdata = data;
/* read INT_STS_A, B and C in one shot using a burst read */
ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes, REG_INT_STS_A, 3);
if (ret) {
pr_warn("twl6030_irq: I2C error %d reading PIH ISR\n", ret);
return IRQ_HANDLED;
}
sts.bytes[3] = 0; /* Only 24 bits are valid*/
/*
* Since VBUS status bit is not reliable for VBUS disconnect
* use CHARGER VBUS detection status bit instead.
*/
if (sts.bytes[2] & 0x10)
sts.bytes[2] |= 0x08;
int_sts = le32_to_cpu(sts.int_sts);
for (i = 0; int_sts; int_sts >>= 1, i++)
if (int_sts & 0x1) {
int module_irq =
irq_find_mapping(pdata->irq_domain,
pdata->irq_mapping_tbl[i]);
if (module_irq)
handle_nested_irq(module_irq);
else
pr_err("twl6030_irq: Unmapped PIH ISR %u detected\n",
i);
pr_debug("twl6030_irq: PIH ISR %u, virq%u\n",
i, module_irq);
}
/*
* NOTE:
* Simulation confirms that documentation is wrong w.r.t the
* interrupt status clear operation. A single *byte* write to
* any one of STS_A to STS_C register results in all three
* STS registers being reset. Since it does not matter which
* value is written, all three registers are cleared on a
* single byte write, so we just use 0x0 to clear.
*/
ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
if (ret)
pr_warn("twl6030_irq: I2C error in clearing PIH ISR\n");
return IRQ_HANDLED;
}
/*----------------------------------------------------------------------*/
static int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
{
struct twl6030_irq *pdata = irq_data_get_irq_chip_data(d);
if (on)
atomic_inc(&pdata->wakeirqs);
else
atomic_dec(&pdata->wakeirqs);
return 0;
}
int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
{
int ret;
u8 unmask_value;
ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
REG_INT_STS_A + offset);
unmask_value &= (~(bit_mask));
ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
return ret;
}
EXPORT_SYMBOL(twl6030_interrupt_unmask);
int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
{
int ret;
u8 mask_value;
ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
REG_INT_STS_A + offset);
mask_value |= (bit_mask);
ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
return ret;
}
EXPORT_SYMBOL(twl6030_interrupt_mask);
int twl6030_mmc_card_detect_config(void)
{
int ret;
u8 reg_val = 0;
/* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
REG_INT_MSK_LINE_B);
twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
REG_INT_MSK_STS_B);
/*
* Initially Configuring MMC_CTRL for receiving interrupts &
* Card status on TWL6030 for MMC1
*/
ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val, TWL6030_MMCCTRL);
if (ret < 0) {
pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
return ret;
}
reg_val &= ~VMMC_AUTO_OFF;
reg_val |= SW_FC;
ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
if (ret < 0) {
pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
return ret;
}
/* Configuring PullUp-PullDown register */
ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val,
TWL6030_CFG_INPUT_PUPD3);
if (ret < 0) {
pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
ret);
return ret;
}
reg_val &= ~(MMC_PU | MMC_PD);
ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
TWL6030_CFG_INPUT_PUPD3);
if (ret < 0) {
pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
ret);
return ret;
}
return irq_find_mapping(twl6030_irq->irq_domain,
MMCDETECT_INTR_OFFSET);
}
EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
int twl6030_mmc_card_detect(struct device *dev, int slot)
{
int ret = -EIO;
u8 read_reg = 0;
struct platform_device *pdev = to_platform_device(dev);
if (pdev->id) {
/* TWL6030 provide's Card detect support for
* only MMC1 controller.
*/
pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
return ret;
}
/*
* BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
* 0 - Card not present ,1 - Card present
*/
ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
TWL6030_MMCCTRL);
if (ret >= 0)
ret = read_reg & STS_MMC;
return ret;
}
EXPORT_SYMBOL(twl6030_mmc_card_detect);
static int twl6030_irq_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hwirq)
{
struct twl6030_irq *pdata = d->host_data;
irq_set_chip_data(virq, pdata);
irq_set_chip_and_handler(virq, &pdata->irq_chip, handle_simple_irq);
irq_set_nested_thread(virq, true);
irq_set_parent(virq, pdata->twl_irq);
irq_set_noprobe(virq);
return 0;
}
static void twl6030_irq_unmap(struct irq_domain *d, unsigned int virq)
{
irq_set_chip_and_handler(virq, NULL, NULL);
irq_set_chip_data(virq, NULL);
}
static const struct irq_domain_ops twl6030_irq_domain_ops = {
.map = twl6030_irq_map,
.unmap = twl6030_irq_unmap,
.xlate = irq_domain_xlate_onetwocell,
};
static const struct of_device_id twl6030_of_match[] __maybe_unused = {
{.compatible = "ti,twl6030", &twl6030_interrupt_mapping},
{.compatible = "ti,twl6032", &twl6032_interrupt_mapping},
{ },
};
int twl6030_init_irq(struct device *dev, int irq_num)
{
struct device_node *node = dev->of_node;
int nr_irqs;
int status;
u8 mask[3];
const struct of_device_id *of_id;
of_id = of_match_device(twl6030_of_match, dev);
if (!of_id || !of_id->data) {
dev_err(dev, "Unknown TWL device model\n");
return -EINVAL;
}
nr_irqs = TWL6030_NR_IRQS;
twl6030_irq = devm_kzalloc(dev, sizeof(*twl6030_irq), GFP_KERNEL);
if (!twl6030_irq)
return -ENOMEM;
mask[0] = 0xFF;
mask[1] = 0xFF;
mask[2] = 0xFF;
/* mask all int lines */
status = twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
/* mask all int sts */
status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
/* clear INT_STS_A,B,C */
status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);
if (status < 0) {
dev_err(dev, "I2C err writing TWL_MODULE_PIH: %d\n", status);
return status;
}
/*
* install an irq handler for each of the modules;
* clone dummy irq_chip since PIH can't *do* anything
*/
twl6030_irq->irq_chip = dummy_irq_chip;
twl6030_irq->irq_chip.name = "twl6030";
twl6030_irq->irq_chip.irq_set_type = NULL;
twl6030_irq->irq_chip.irq_set_wake = twl6030_irq_set_wake;
twl6030_irq->pm_nb.notifier_call = twl6030_irq_pm_notifier;
atomic_set(&twl6030_irq->wakeirqs, 0);
twl6030_irq->irq_mapping_tbl = of_id->data;
twl6030_irq->irq_domain =
irq_domain_add_linear(node, nr_irqs,
&twl6030_irq_domain_ops, twl6030_irq);
if (!twl6030_irq->irq_domain) {
dev_err(dev, "Can't add irq_domain\n");
return -ENOMEM;
}
dev_info(dev, "PIH (irq %d) nested IRQs\n", irq_num);
/* install an irq handler to demultiplex the TWL6030 interrupt */
status = request_threaded_irq(irq_num, NULL, twl6030_irq_thread,
IRQF_ONESHOT, "TWL6030-PIH", twl6030_irq);
if (status < 0) {
dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
goto fail_irq;
}
twl6030_irq->twl_irq = irq_num;
register_pm_notifier(&twl6030_irq->pm_nb);
return 0;
fail_irq:
irq_domain_remove(twl6030_irq->irq_domain);
return status;
}
void twl6030_exit_irq(void)
{
if (twl6030_irq && twl6030_irq->twl_irq) {
unregister_pm_notifier(&twl6030_irq->pm_nb);
free_irq(twl6030_irq->twl_irq, NULL);
/*
* TODO: IRQ domain and allocated nested IRQ descriptors
* should be freed somehow here. Now It can't be done, because
* child devices will not be deleted during removing of
* TWL Core driver and they will still contain allocated
* virt IRQs in their Resources tables.
* The same prevents us from using devm_request_threaded_irq()
* in this module.
*/
}
}
| linux-master | drivers/mfd/twl6030-irq.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* SPI bus interface to Cirrus Logic Madera codecs
*
* Copyright (C) 2015-2018 Cirrus Logic
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/mfd/madera/core.h>
#include "madera.h"
static int madera_spi_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
struct madera *madera;
const struct regmap_config *regmap_16bit_config = NULL;
const struct regmap_config *regmap_32bit_config = NULL;
const void *of_data;
unsigned long type;
const char *name;
int ret;
of_data = of_device_get_match_data(&spi->dev);
if (of_data)
type = (unsigned long)of_data;
else
type = id->driver_data;
switch (type) {
case CS47L15:
if (IS_ENABLED(CONFIG_MFD_CS47L15)) {
regmap_16bit_config = &cs47l15_16bit_spi_regmap;
regmap_32bit_config = &cs47l15_32bit_spi_regmap;
}
break;
case CS47L35:
if (IS_ENABLED(CONFIG_MFD_CS47L35)) {
regmap_16bit_config = &cs47l35_16bit_spi_regmap;
regmap_32bit_config = &cs47l35_32bit_spi_regmap;
}
break;
case CS47L85:
case WM1840:
if (IS_ENABLED(CONFIG_MFD_CS47L85)) {
regmap_16bit_config = &cs47l85_16bit_spi_regmap;
regmap_32bit_config = &cs47l85_32bit_spi_regmap;
}
break;
case CS47L90:
case CS47L91:
if (IS_ENABLED(CONFIG_MFD_CS47L90)) {
regmap_16bit_config = &cs47l90_16bit_spi_regmap;
regmap_32bit_config = &cs47l90_32bit_spi_regmap;
}
break;
case CS42L92:
case CS47L92:
case CS47L93:
if (IS_ENABLED(CONFIG_MFD_CS47L92)) {
regmap_16bit_config = &cs47l92_16bit_spi_regmap;
regmap_32bit_config = &cs47l92_32bit_spi_regmap;
}
break;
default:
dev_err(&spi->dev,
"Unknown Madera SPI device type %ld\n", type);
return -EINVAL;
}
name = madera_name_from_type(type);
if (!regmap_16bit_config) {
/* it's polite to say which codec isn't built into the kernel */
dev_err(&spi->dev,
"Kernel does not include support for %s\n", name);
return -EINVAL;
}
madera = devm_kzalloc(&spi->dev, sizeof(*madera), GFP_KERNEL);
if (!madera)
return -ENOMEM;
madera->regmap = devm_regmap_init_spi(spi, regmap_16bit_config);
if (IS_ERR(madera->regmap)) {
ret = PTR_ERR(madera->regmap);
dev_err(&spi->dev,
"Failed to allocate 16-bit register map: %d\n", ret);
return ret;
}
madera->regmap_32bit = devm_regmap_init_spi(spi, regmap_32bit_config);
if (IS_ERR(madera->regmap_32bit)) {
ret = PTR_ERR(madera->regmap_32bit);
dev_err(&spi->dev,
"Failed to allocate 32-bit register map: %d\n", ret);
return ret;
}
madera->type = type;
madera->type_name = name;
madera->dev = &spi->dev;
madera->irq = spi->irq;
return madera_dev_init(madera);
}
static void madera_spi_remove(struct spi_device *spi)
{
struct madera *madera = spi_get_drvdata(spi);
madera_dev_exit(madera);
}
static const struct spi_device_id madera_spi_ids[] = {
{ "cs47l15", CS47L15 },
{ "cs47l35", CS47L35 },
{ "cs47l85", CS47L85 },
{ "cs47l90", CS47L90 },
{ "cs47l91", CS47L91 },
{ "cs42l92", CS42L92 },
{ "cs47l92", CS47L92 },
{ "cs47l93", CS47L93 },
{ "wm1840", WM1840 },
{ }
};
MODULE_DEVICE_TABLE(spi, madera_spi_ids);
static struct spi_driver madera_spi_driver = {
.driver = {
.name = "madera",
.pm = &madera_pm_ops,
.of_match_table = of_match_ptr(madera_of_match),
},
.probe = madera_spi_probe,
.remove = madera_spi_remove,
.id_table = madera_spi_ids,
};
module_spi_driver(madera_spi_driver);
MODULE_DESCRIPTION("Madera SPI bus interface");
MODULE_AUTHOR("Richard Fitzgerald <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/mfd/madera-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
* Copyright (c) 2010, Google Inc.
*
* Original authors: Code Aurora Forum
*
* Author: Dima Zavin <[email protected]>
* - Largely rewritten from original to not be an i2c driver.
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/ssbi.h>
/* SSBI 2.0 controller registers */
#define SSBI2_CMD 0x0008
#define SSBI2_RD 0x0010
#define SSBI2_STATUS 0x0014
#define SSBI2_MODE2 0x001C
/* SSBI_CMD fields */
#define SSBI_CMD_RDWRN (1 << 24)
/* SSBI_STATUS fields */
#define SSBI_STATUS_RD_READY (1 << 2)
#define SSBI_STATUS_READY (1 << 1)
#define SSBI_STATUS_MCHN_BUSY (1 << 0)
/* SSBI_MODE2 fields */
#define SSBI_MODE2_REG_ADDR_15_8_SHFT 0x04
#define SSBI_MODE2_REG_ADDR_15_8_MASK (0x7f << SSBI_MODE2_REG_ADDR_15_8_SHFT)
#define SET_SSBI_MODE2_REG_ADDR_15_8(MD, AD) \
(((MD) & 0x0F) | ((((AD) >> 8) << SSBI_MODE2_REG_ADDR_15_8_SHFT) & \
SSBI_MODE2_REG_ADDR_15_8_MASK))
/* SSBI PMIC Arbiter command registers */
#define SSBI_PA_CMD 0x0000
#define SSBI_PA_RD_STATUS 0x0004
/* SSBI_PA_CMD fields */
#define SSBI_PA_CMD_RDWRN (1 << 24)
#define SSBI_PA_CMD_ADDR_MASK 0x7fff /* REG_ADDR_7_0, REG_ADDR_8_14*/
/* SSBI_PA_RD_STATUS fields */
#define SSBI_PA_RD_STATUS_TRANS_DONE (1 << 27)
#define SSBI_PA_RD_STATUS_TRANS_DENIED (1 << 26)
#define SSBI_TIMEOUT_US 100
enum ssbi_controller_type {
MSM_SBI_CTRL_SSBI = 0,
MSM_SBI_CTRL_SSBI2,
MSM_SBI_CTRL_PMIC_ARBITER,
};
struct ssbi {
struct device *slave;
void __iomem *base;
spinlock_t lock;
enum ssbi_controller_type controller_type;
int (*read)(struct ssbi *, u16 addr, u8 *buf, int len);
int (*write)(struct ssbi *, u16 addr, const u8 *buf, int len);
};
static inline u32 ssbi_readl(struct ssbi *ssbi, u32 reg)
{
return readl(ssbi->base + reg);
}
static inline void ssbi_writel(struct ssbi *ssbi, u32 val, u32 reg)
{
writel(val, ssbi->base + reg);
}
/*
* Via private exchange with one of the original authors, the hardware
* should generally finish a transaction in about 5us. The worst
* case, is when using the arbiter and both other CPUs have just
* started trying to use the SSBI bus will result in a time of about
* 20us. It should never take longer than this.
*
* As such, this wait merely spins, with a udelay.
*/
static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask)
{
u32 timeout = SSBI_TIMEOUT_US;
u32 val;
while (timeout--) {
val = ssbi_readl(ssbi, SSBI2_STATUS);
if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0))
return 0;
udelay(1);
}
return -ETIMEDOUT;
}
static int
ssbi_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len)
{
u32 cmd = SSBI_CMD_RDWRN | ((addr & 0xff) << 16);
int ret = 0;
if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
ssbi_writel(ssbi, mode2, SSBI2_MODE2);
}
while (len) {
ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
if (ret)
goto err;
ssbi_writel(ssbi, cmd, SSBI2_CMD);
ret = ssbi_wait_mask(ssbi, SSBI_STATUS_RD_READY, 0);
if (ret)
goto err;
*buf++ = ssbi_readl(ssbi, SSBI2_RD) & 0xff;
len--;
}
err:
return ret;
}
static int
ssbi_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len)
{
int ret = 0;
if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
ssbi_writel(ssbi, mode2, SSBI2_MODE2);
}
while (len) {
ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
if (ret)
goto err;
ssbi_writel(ssbi, ((addr & 0xff) << 16) | *buf, SSBI2_CMD);
ret = ssbi_wait_mask(ssbi, 0, SSBI_STATUS_MCHN_BUSY);
if (ret)
goto err;
buf++;
len--;
}
err:
return ret;
}
/*
* See ssbi_wait_mask for an explanation of the time and the
* busywait.
*/
static inline int
ssbi_pa_transfer(struct ssbi *ssbi, u32 cmd, u8 *data)
{
u32 timeout = SSBI_TIMEOUT_US;
u32 rd_status = 0;
ssbi_writel(ssbi, cmd, SSBI_PA_CMD);
while (timeout--) {
rd_status = ssbi_readl(ssbi, SSBI_PA_RD_STATUS);
if (rd_status & SSBI_PA_RD_STATUS_TRANS_DENIED)
return -EPERM;
if (rd_status & SSBI_PA_RD_STATUS_TRANS_DONE) {
if (data)
*data = rd_status & 0xff;
return 0;
}
udelay(1);
}
return -ETIMEDOUT;
}
static int
ssbi_pa_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len)
{
u32 cmd;
int ret = 0;
cmd = SSBI_PA_CMD_RDWRN | (addr & SSBI_PA_CMD_ADDR_MASK) << 8;
while (len) {
ret = ssbi_pa_transfer(ssbi, cmd, buf);
if (ret)
goto err;
buf++;
len--;
}
err:
return ret;
}
static int
ssbi_pa_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len)
{
u32 cmd;
int ret = 0;
while (len) {
cmd = (addr & SSBI_PA_CMD_ADDR_MASK) << 8 | *buf;
ret = ssbi_pa_transfer(ssbi, cmd, NULL);
if (ret)
goto err;
buf++;
len--;
}
err:
return ret;
}
int ssbi_read(struct device *dev, u16 addr, u8 *buf, int len)
{
struct ssbi *ssbi = dev_get_drvdata(dev);
unsigned long flags;
int ret;
spin_lock_irqsave(&ssbi->lock, flags);
ret = ssbi->read(ssbi, addr, buf, len);
spin_unlock_irqrestore(&ssbi->lock, flags);
return ret;
}
EXPORT_SYMBOL_GPL(ssbi_read);
int ssbi_write(struct device *dev, u16 addr, const u8 *buf, int len)
{
struct ssbi *ssbi = dev_get_drvdata(dev);
unsigned long flags;
int ret;
spin_lock_irqsave(&ssbi->lock, flags);
ret = ssbi->write(ssbi, addr, buf, len);
spin_unlock_irqrestore(&ssbi->lock, flags);
return ret;
}
EXPORT_SYMBOL_GPL(ssbi_write);
static int ssbi_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct ssbi *ssbi;
const char *type;
ssbi = devm_kzalloc(&pdev->dev, sizeof(*ssbi), GFP_KERNEL);
if (!ssbi)
return -ENOMEM;
ssbi->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(ssbi->base))
return PTR_ERR(ssbi->base);
platform_set_drvdata(pdev, ssbi);
type = of_get_property(np, "qcom,controller-type", NULL);
if (type == NULL) {
dev_err(&pdev->dev, "Missing qcom,controller-type property\n");
return -EINVAL;
}
dev_info(&pdev->dev, "SSBI controller type: '%s'\n", type);
if (strcmp(type, "ssbi") == 0)
ssbi->controller_type = MSM_SBI_CTRL_SSBI;
else if (strcmp(type, "ssbi2") == 0)
ssbi->controller_type = MSM_SBI_CTRL_SSBI2;
else if (strcmp(type, "pmic-arbiter") == 0)
ssbi->controller_type = MSM_SBI_CTRL_PMIC_ARBITER;
else {
dev_err(&pdev->dev, "Unknown qcom,controller-type\n");
return -EINVAL;
}
if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) {
ssbi->read = ssbi_pa_read_bytes;
ssbi->write = ssbi_pa_write_bytes;
} else {
ssbi->read = ssbi_read_bytes;
ssbi->write = ssbi_write_bytes;
}
spin_lock_init(&ssbi->lock);
return devm_of_platform_populate(&pdev->dev);
}
static const struct of_device_id ssbi_match_table[] = {
{ .compatible = "qcom,ssbi" },
{}
};
MODULE_DEVICE_TABLE(of, ssbi_match_table);
static struct platform_driver ssbi_driver = {
.probe = ssbi_probe,
.driver = {
.name = "ssbi",
.of_match_table = ssbi_match_table,
},
};
module_platform_driver(ssbi_driver);
MODULE_LICENSE("GPL v2");
MODULE_VERSION("1.0");
MODULE_ALIAS("platform:ssbi");
MODULE_AUTHOR("Dima Zavin <[email protected]>");
| linux-master | drivers/mfd/ssbi.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Intel MAX 10 Board Management Controller chip
*
* Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
*/
#include <linux/bitfield.h>
#include <linux/dev_printk.h>
#include <linux/init.h>
#include <linux/mfd/core.h>
#include <linux/mfd/intel-m10-bmc.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
static const struct regmap_range m10bmc_regmap_range[] = {
regmap_reg_range(M10BMC_N3000_LEGACY_BUILD_VER, M10BMC_N3000_LEGACY_BUILD_VER),
regmap_reg_range(M10BMC_N3000_SYS_BASE, M10BMC_N3000_SYS_END),
regmap_reg_range(M10BMC_N3000_FLASH_BASE, M10BMC_N3000_FLASH_END),
};
static const struct regmap_access_table m10bmc_access_table = {
.yes_ranges = m10bmc_regmap_range,
.n_yes_ranges = ARRAY_SIZE(m10bmc_regmap_range),
};
static struct regmap_config intel_m10bmc_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.wr_table = &m10bmc_access_table,
.rd_table = &m10bmc_access_table,
.max_register = M10BMC_N3000_MEM_END,
};
static int check_m10bmc_version(struct intel_m10bmc *ddata)
{
unsigned int v;
int ret;
/*
* This check is to filter out the very old legacy BMC versions. In the
* old BMC chips, the BMC version info is stored in the old version
* register (M10BMC_N3000_LEGACY_BUILD_VER), so its read out value would have
* not been M10BMC_N3000_VER_LEGACY_INVALID (0xffffffff). But in new BMC
* chips that the driver supports, the value of this register should be
* M10BMC_N3000_VER_LEGACY_INVALID.
*/
ret = m10bmc_raw_read(ddata, M10BMC_N3000_LEGACY_BUILD_VER, &v);
if (ret)
return -ENODEV;
if (v != M10BMC_N3000_VER_LEGACY_INVALID) {
dev_err(ddata->dev, "bad version M10BMC detected\n");
return -ENODEV;
}
return 0;
}
static int intel_m10_bmc_spi_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
const struct intel_m10bmc_platform_info *info;
struct device *dev = &spi->dev;
struct intel_m10bmc *ddata;
int ret;
ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
info = (struct intel_m10bmc_platform_info *)id->driver_data;
ddata->dev = dev;
ddata->regmap = devm_regmap_init_spi_avmm(spi, &intel_m10bmc_regmap_config);
if (IS_ERR(ddata->regmap)) {
ret = PTR_ERR(ddata->regmap);
dev_err(dev, "Failed to allocate regmap: %d\n", ret);
return ret;
}
spi_set_drvdata(spi, ddata);
ret = check_m10bmc_version(ddata);
if (ret) {
dev_err(dev, "Failed to identify m10bmc hardware\n");
return ret;
}
return m10bmc_dev_init(ddata, info);
}
static const struct m10bmc_csr_map m10bmc_n3000_csr_map = {
.base = M10BMC_N3000_SYS_BASE,
.build_version = M10BMC_N3000_BUILD_VER,
.fw_version = NIOS2_N3000_FW_VERSION,
.mac_low = M10BMC_N3000_MAC_LOW,
.mac_high = M10BMC_N3000_MAC_HIGH,
.doorbell = M10BMC_N3000_DOORBELL,
.auth_result = M10BMC_N3000_AUTH_RESULT,
.bmc_prog_addr = M10BMC_N3000_BMC_PROG_ADDR,
.bmc_reh_addr = M10BMC_N3000_BMC_REH_ADDR,
.bmc_magic = M10BMC_N3000_BMC_PROG_MAGIC,
.sr_prog_addr = M10BMC_N3000_SR_PROG_ADDR,
.sr_reh_addr = M10BMC_N3000_SR_REH_ADDR,
.sr_magic = M10BMC_N3000_SR_PROG_MAGIC,
.pr_prog_addr = M10BMC_N3000_PR_PROG_ADDR,
.pr_reh_addr = M10BMC_N3000_PR_REH_ADDR,
.pr_magic = M10BMC_N3000_PR_PROG_MAGIC,
.rsu_update_counter = M10BMC_N3000_STAGING_FLASH_COUNT,
};
static struct mfd_cell m10bmc_d5005_subdevs[] = {
{ .name = "d5005bmc-hwmon" },
{ .name = "d5005bmc-sec-update" },
};
static const struct regmap_range m10bmc_d5005_fw_handshake_regs[] = {
regmap_reg_range(M10BMC_N3000_TELEM_START, M10BMC_D5005_TELEM_END),
};
static struct mfd_cell m10bmc_pacn3000_subdevs[] = {
{ .name = "n3000bmc-hwmon" },
{ .name = "n3000bmc-retimer" },
{ .name = "n3000bmc-sec-update" },
};
static const struct regmap_range m10bmc_n3000_fw_handshake_regs[] = {
regmap_reg_range(M10BMC_N3000_TELEM_START, M10BMC_N3000_TELEM_END),
};
static struct mfd_cell m10bmc_n5010_subdevs[] = {
{ .name = "n5010bmc-hwmon" },
};
static const struct intel_m10bmc_platform_info m10bmc_spi_n3000 = {
.cells = m10bmc_pacn3000_subdevs,
.n_cells = ARRAY_SIZE(m10bmc_pacn3000_subdevs),
.handshake_sys_reg_ranges = m10bmc_n3000_fw_handshake_regs,
.handshake_sys_reg_nranges = ARRAY_SIZE(m10bmc_n3000_fw_handshake_regs),
.csr_map = &m10bmc_n3000_csr_map,
};
static const struct intel_m10bmc_platform_info m10bmc_spi_d5005 = {
.cells = m10bmc_d5005_subdevs,
.n_cells = ARRAY_SIZE(m10bmc_d5005_subdevs),
.handshake_sys_reg_ranges = m10bmc_d5005_fw_handshake_regs,
.handshake_sys_reg_nranges = ARRAY_SIZE(m10bmc_d5005_fw_handshake_regs),
.csr_map = &m10bmc_n3000_csr_map,
};
static const struct intel_m10bmc_platform_info m10bmc_spi_n5010 = {
.cells = m10bmc_n5010_subdevs,
.n_cells = ARRAY_SIZE(m10bmc_n5010_subdevs),
.handshake_sys_reg_ranges = m10bmc_n3000_fw_handshake_regs,
.handshake_sys_reg_nranges = ARRAY_SIZE(m10bmc_n3000_fw_handshake_regs),
.csr_map = &m10bmc_n3000_csr_map,
};
static const struct spi_device_id m10bmc_spi_id[] = {
{ "m10-n3000", (kernel_ulong_t)&m10bmc_spi_n3000 },
{ "m10-d5005", (kernel_ulong_t)&m10bmc_spi_d5005 },
{ "m10-n5010", (kernel_ulong_t)&m10bmc_spi_n5010 },
{ }
};
MODULE_DEVICE_TABLE(spi, m10bmc_spi_id);
static struct spi_driver intel_m10bmc_spi_driver = {
.driver = {
.name = "intel-m10-bmc",
.dev_groups = m10bmc_dev_groups,
},
.probe = intel_m10_bmc_spi_probe,
.id_table = m10bmc_spi_id,
};
module_spi_driver(intel_m10bmc_spi_driver);
MODULE_DESCRIPTION("Intel MAX 10 BMC SPI bus interface");
MODULE_AUTHOR("Intel Corporation");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("spi:intel-m10-bmc");
MODULE_IMPORT_NS(INTEL_M10_BMC_CORE);
| linux-master | drivers/mfd/intel-m10-bmc-spi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Arizona interrupt support
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/mfd/arizona/core.h>
#include <linux/mfd/arizona/registers.h>
#include "arizona.h"
#define ARIZONA_AOD_IRQ_INDEX 0
#define ARIZONA_MAIN_IRQ_INDEX 1
static int arizona_map_irq(struct arizona *arizona, int irq)
{
int ret;
if (arizona->aod_irq_chip) {
ret = regmap_irq_get_virq(arizona->aod_irq_chip, irq);
if (ret >= 0)
return ret;
}
return regmap_irq_get_virq(arizona->irq_chip, irq);
}
int arizona_request_irq(struct arizona *arizona, int irq, char *name,
irq_handler_t handler, void *data)
{
irq = arizona_map_irq(arizona, irq);
if (irq < 0)
return irq;
return request_threaded_irq(irq, NULL, handler, IRQF_ONESHOT,
name, data);
}
EXPORT_SYMBOL_GPL(arizona_request_irq);
void arizona_free_irq(struct arizona *arizona, int irq, void *data)
{
irq = arizona_map_irq(arizona, irq);
if (irq < 0)
return;
free_irq(irq, data);
}
EXPORT_SYMBOL_GPL(arizona_free_irq);
int arizona_set_irq_wake(struct arizona *arizona, int irq, int on)
{
irq = arizona_map_irq(arizona, irq);
if (irq < 0)
return irq;
return irq_set_irq_wake(irq, on);
}
EXPORT_SYMBOL_GPL(arizona_set_irq_wake);
static irqreturn_t arizona_boot_done(int irq, void *data)
{
struct arizona *arizona = data;
dev_dbg(arizona->dev, "Boot done\n");
return IRQ_HANDLED;
}
static irqreturn_t arizona_ctrlif_err(int irq, void *data)
{
struct arizona *arizona = data;
/*
* For pretty much all potential sources a register cache sync
* won't help, we've just got a software bug somewhere.
*/
dev_err(arizona->dev, "Control interface error\n");
return IRQ_HANDLED;
}
static irqreturn_t arizona_irq_thread(int irq, void *data)
{
struct arizona *arizona = data;
bool poll;
unsigned int val;
int ret;
ret = pm_runtime_resume_and_get(arizona->dev);
if (ret < 0) {
dev_err(arizona->dev, "Failed to resume device: %d\n", ret);
return IRQ_NONE;
}
do {
poll = false;
if (arizona->aod_irq_chip) {
/*
* Check the AOD status register to determine whether
* the nested IRQ handler should be called.
*/
ret = regmap_read(arizona->regmap,
ARIZONA_AOD_IRQ1, &val);
if (ret)
dev_warn(arizona->dev,
"Failed to read AOD IRQ1 %d\n", ret);
else if (val)
handle_nested_irq(
irq_find_mapping(arizona->virq, 0));
}
/*
* Check if one of the main interrupts is asserted and only
* check that domain if it is.
*/
ret = regmap_read(arizona->regmap, ARIZONA_IRQ_PIN_STATUS,
&val);
if (ret == 0 && val & ARIZONA_IRQ1_STS) {
handle_nested_irq(irq_find_mapping(arizona->virq, 1));
} else if (ret != 0) {
dev_err(arizona->dev,
"Failed to read main IRQ status: %d\n", ret);
}
/*
* Poll the IRQ pin status to see if we're really done
* if the interrupt controller can't do it for us.
*/
if (!arizona->pdata.irq_gpio) {
break;
} else if (arizona->pdata.irq_flags & IRQF_TRIGGER_RISING &&
gpio_get_value_cansleep(arizona->pdata.irq_gpio)) {
poll = true;
} else if (arizona->pdata.irq_flags & IRQF_TRIGGER_FALLING &&
!gpio_get_value_cansleep(arizona->pdata.irq_gpio)) {
poll = true;
}
} while (poll);
pm_runtime_mark_last_busy(arizona->dev);
pm_runtime_put_autosuspend(arizona->dev);
return IRQ_HANDLED;
}
static void arizona_irq_enable(struct irq_data *data)
{
}
static void arizona_irq_disable(struct irq_data *data)
{
}
static int arizona_irq_set_wake(struct irq_data *data, unsigned int on)
{
struct arizona *arizona = irq_data_get_irq_chip_data(data);
return irq_set_irq_wake(arizona->irq, on);
}
static struct irq_chip arizona_irq_chip = {
.name = "arizona",
.irq_disable = arizona_irq_disable,
.irq_enable = arizona_irq_enable,
.irq_set_wake = arizona_irq_set_wake,
};
static struct lock_class_key arizona_irq_lock_class;
static struct lock_class_key arizona_irq_request_class;
static int arizona_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct arizona *data = h->host_data;
irq_set_chip_data(virq, data);
irq_set_lockdep_class(virq, &arizona_irq_lock_class,
&arizona_irq_request_class);
irq_set_chip_and_handler(virq, &arizona_irq_chip, handle_simple_irq);
irq_set_nested_thread(virq, 1);
irq_set_noprobe(virq);
return 0;
}
static const struct irq_domain_ops arizona_domain_ops = {
.map = arizona_irq_map,
.xlate = irq_domain_xlate_twocell,
};
int arizona_irq_init(struct arizona *arizona)
{
int flags = IRQF_ONESHOT;
int ret;
const struct regmap_irq_chip *aod, *irq;
struct irq_data *irq_data;
unsigned int virq;
arizona->ctrlif_error = true;
switch (arizona->type) {
#ifdef CONFIG_MFD_WM5102
case WM5102:
aod = &wm5102_aod;
irq = &wm5102_irq;
arizona->ctrlif_error = false;
break;
#endif
#ifdef CONFIG_MFD_WM5110
case WM5110:
case WM8280:
aod = &wm5110_aod;
switch (arizona->rev) {
case 0 ... 2:
irq = &wm5110_irq;
break;
default:
irq = &wm5110_revd_irq;
break;
}
arizona->ctrlif_error = false;
break;
#endif
#ifdef CONFIG_MFD_CS47L24
case WM1831:
case CS47L24:
aod = NULL;
irq = &cs47l24_irq;
arizona->ctrlif_error = false;
break;
#endif
#ifdef CONFIG_MFD_WM8997
case WM8997:
aod = &wm8997_aod;
irq = &wm8997_irq;
arizona->ctrlif_error = false;
break;
#endif
#ifdef CONFIG_MFD_WM8998
case WM8998:
case WM1814:
aod = &wm8998_aod;
irq = &wm8998_irq;
arizona->ctrlif_error = false;
break;
#endif
default:
BUG_ON("Unknown Arizona class device" == NULL);
return -EINVAL;
}
/* Disable all wake sources by default */
regmap_write(arizona->regmap, ARIZONA_WAKE_CONTROL, 0);
/* Read the flags from the interrupt controller if not specified */
if (!arizona->pdata.irq_flags) {
irq_data = irq_get_irq_data(arizona->irq);
if (!irq_data) {
dev_err(arizona->dev, "Invalid IRQ: %d\n",
arizona->irq);
return -EINVAL;
}
arizona->pdata.irq_flags = irqd_get_trigger_type(irq_data);
switch (arizona->pdata.irq_flags) {
case IRQF_TRIGGER_LOW:
case IRQF_TRIGGER_HIGH:
case IRQF_TRIGGER_RISING:
case IRQF_TRIGGER_FALLING:
break;
case IRQ_TYPE_NONE:
default:
/* Device default */
arizona->pdata.irq_flags = IRQF_TRIGGER_LOW;
break;
}
}
if (arizona->pdata.irq_flags & (IRQF_TRIGGER_HIGH |
IRQF_TRIGGER_RISING)) {
ret = regmap_update_bits(arizona->regmap, ARIZONA_IRQ_CTRL_1,
ARIZONA_IRQ_POL, 0);
if (ret != 0) {
dev_err(arizona->dev, "Couldn't set IRQ polarity: %d\n",
ret);
goto err;
}
}
flags |= arizona->pdata.irq_flags;
/* Allocate a virtual IRQ domain to distribute to the regmap domains */
arizona->virq = irq_domain_add_linear(NULL, 2, &arizona_domain_ops,
arizona);
if (!arizona->virq) {
dev_err(arizona->dev, "Failed to add core IRQ domain\n");
ret = -EINVAL;
goto err;
}
if (aod) {
virq = irq_create_mapping(arizona->virq, ARIZONA_AOD_IRQ_INDEX);
if (!virq) {
dev_err(arizona->dev, "Failed to map AOD IRQs\n");
ret = -EINVAL;
goto err_domain;
}
ret = regmap_add_irq_chip(arizona->regmap, virq, IRQF_ONESHOT,
0, aod, &arizona->aod_irq_chip);
if (ret != 0) {
dev_err(arizona->dev,
"Failed to add AOD IRQs: %d\n", ret);
goto err_map_aod;
}
}
virq = irq_create_mapping(arizona->virq, ARIZONA_MAIN_IRQ_INDEX);
if (!virq) {
dev_err(arizona->dev, "Failed to map main IRQs\n");
ret = -EINVAL;
goto err_aod;
}
ret = regmap_add_irq_chip(arizona->regmap, virq, IRQF_ONESHOT,
0, irq, &arizona->irq_chip);
if (ret != 0) {
dev_err(arizona->dev, "Failed to add main IRQs: %d\n", ret);
goto err_map_main_irq;
}
/* Used to emulate edge trigger and to work around broken pinmux */
if (arizona->pdata.irq_gpio) {
if (gpio_to_irq(arizona->pdata.irq_gpio) != arizona->irq) {
dev_warn(arizona->dev, "IRQ %d is not GPIO %d (%d)\n",
arizona->irq, arizona->pdata.irq_gpio,
gpio_to_irq(arizona->pdata.irq_gpio));
arizona->irq = gpio_to_irq(arizona->pdata.irq_gpio);
}
ret = devm_gpio_request_one(arizona->dev,
arizona->pdata.irq_gpio,
GPIOF_IN, "arizona IRQ");
if (ret != 0) {
dev_err(arizona->dev,
"Failed to request IRQ GPIO %d:: %d\n",
arizona->pdata.irq_gpio, ret);
arizona->pdata.irq_gpio = 0;
}
}
ret = request_threaded_irq(arizona->irq, NULL, arizona_irq_thread,
flags, "arizona", arizona);
if (ret != 0) {
dev_err(arizona->dev, "Failed to request primary IRQ %d: %d\n",
arizona->irq, ret);
goto err_main_irq;
}
/* Make sure the boot done IRQ is unmasked for resumes */
ret = arizona_request_irq(arizona, ARIZONA_IRQ_BOOT_DONE, "Boot done",
arizona_boot_done, arizona);
if (ret != 0) {
dev_err(arizona->dev, "Failed to request boot done %d: %d\n",
arizona->irq, ret);
goto err_boot_done;
}
/* Handle control interface errors in the core */
if (arizona->ctrlif_error) {
ret = arizona_request_irq(arizona, ARIZONA_IRQ_CTRLIF_ERR,
"Control interface error",
arizona_ctrlif_err, arizona);
if (ret != 0) {
dev_err(arizona->dev,
"Failed to request CTRLIF_ERR %d: %d\n",
arizona->irq, ret);
goto err_ctrlif;
}
}
return 0;
err_ctrlif:
arizona_free_irq(arizona, ARIZONA_IRQ_BOOT_DONE, arizona);
err_boot_done:
free_irq(arizona->irq, arizona);
err_main_irq:
regmap_del_irq_chip(irq_find_mapping(arizona->virq,
ARIZONA_MAIN_IRQ_INDEX),
arizona->irq_chip);
err_map_main_irq:
irq_dispose_mapping(irq_find_mapping(arizona->virq,
ARIZONA_MAIN_IRQ_INDEX));
err_aod:
regmap_del_irq_chip(irq_find_mapping(arizona->virq,
ARIZONA_AOD_IRQ_INDEX),
arizona->aod_irq_chip);
err_map_aod:
irq_dispose_mapping(irq_find_mapping(arizona->virq,
ARIZONA_AOD_IRQ_INDEX));
err_domain:
irq_domain_remove(arizona->virq);
err:
return ret;
}
int arizona_irq_exit(struct arizona *arizona)
{
unsigned int virq;
if (arizona->ctrlif_error)
arizona_free_irq(arizona, ARIZONA_IRQ_CTRLIF_ERR, arizona);
arizona_free_irq(arizona, ARIZONA_IRQ_BOOT_DONE, arizona);
virq = irq_find_mapping(arizona->virq, ARIZONA_MAIN_IRQ_INDEX);
regmap_del_irq_chip(virq, arizona->irq_chip);
irq_dispose_mapping(virq);
virq = irq_find_mapping(arizona->virq, ARIZONA_AOD_IRQ_INDEX);
regmap_del_irq_chip(virq, arizona->aod_irq_chip);
irq_dispose_mapping(virq);
irq_domain_remove(arizona->virq);
free_irq(arizona->irq, arizona);
return 0;
}
| linux-master | drivers/mfd/arizona-irq.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Nano River Technologies viperboard driver
*
* This is the core driver for the viperboard. There are cell drivers
* available for I2C, ADC and both GPIOs. SPI is not yet supported.
* The drivers do not support all features the board exposes. See user
* manual of the viperboard.
*
* (C) 2012 by Lemonage GmbH
* Author: Lars Poeschel <[email protected]>
* All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/mutex.h>
#include <linux/mfd/core.h>
#include <linux/mfd/viperboard.h>
#include <linux/usb.h>
static const struct usb_device_id vprbrd_table[] = {
{ USB_DEVICE(0x2058, 0x1005) }, /* Nano River Technologies */
{ } /* Terminating entry */
};
MODULE_DEVICE_TABLE(usb, vprbrd_table);
static const struct mfd_cell vprbrd_devs[] = {
{
.name = "viperboard-gpio",
},
{
.name = "viperboard-i2c",
},
{
.name = "viperboard-adc",
},
};
static int vprbrd_probe(struct usb_interface *interface,
const struct usb_device_id *id)
{
struct vprbrd *vb;
u16 version = 0;
int pipe, ret;
/* allocate memory for our device state and initialize it */
vb = kzalloc(sizeof(*vb), GFP_KERNEL);
if (!vb)
return -ENOMEM;
mutex_init(&vb->lock);
vb->usb_dev = usb_get_dev(interface_to_usbdev(interface));
/* save our data pointer in this interface device */
usb_set_intfdata(interface, vb);
dev_set_drvdata(&vb->pdev.dev, vb);
/* get version information, major first, minor then */
pipe = usb_rcvctrlpipe(vb->usb_dev, 0);
ret = usb_control_msg(vb->usb_dev, pipe, VPRBRD_USB_REQUEST_MAJOR,
VPRBRD_USB_TYPE_IN, 0x0000, 0x0000, vb->buf, 1,
VPRBRD_USB_TIMEOUT_MS);
if (ret == 1)
version = vb->buf[0];
ret = usb_control_msg(vb->usb_dev, pipe, VPRBRD_USB_REQUEST_MINOR,
VPRBRD_USB_TYPE_IN, 0x0000, 0x0000, vb->buf, 1,
VPRBRD_USB_TIMEOUT_MS);
if (ret == 1) {
version <<= 8;
version = version | vb->buf[0];
}
dev_info(&interface->dev,
"version %x.%02x found at bus %03d address %03d\n",
version >> 8, version & 0xff,
vb->usb_dev->bus->busnum, vb->usb_dev->devnum);
ret = mfd_add_hotplug_devices(&interface->dev, vprbrd_devs,
ARRAY_SIZE(vprbrd_devs));
if (ret != 0) {
dev_err(&interface->dev, "Failed to add mfd devices to core.");
goto error;
}
return 0;
error:
if (vb) {
usb_put_dev(vb->usb_dev);
kfree(vb);
}
return ret;
}
static void vprbrd_disconnect(struct usb_interface *interface)
{
struct vprbrd *vb = usb_get_intfdata(interface);
mfd_remove_devices(&interface->dev);
usb_set_intfdata(interface, NULL);
usb_put_dev(vb->usb_dev);
kfree(vb);
dev_dbg(&interface->dev, "disconnected\n");
}
static struct usb_driver vprbrd_driver = {
.name = "viperboard",
.probe = vprbrd_probe,
.disconnect = vprbrd_disconnect,
.id_table = vprbrd_table,
};
module_usb_driver(vprbrd_driver);
MODULE_DESCRIPTION("Nano River Technologies viperboard mfd core driver");
MODULE_AUTHOR("Lars Poeschel <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/viperboard.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arizona-spi.c -- Arizona SPI bus interface
*
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <[email protected]>
*/
#include <linux/acpi.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/machine.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/of.h>
#include <uapi/linux/input-event-codes.h>
#include <linux/mfd/arizona/core.h>
#include "arizona.h"
#ifdef CONFIG_ACPI
static const struct acpi_gpio_params reset_gpios = { 1, 0, false };
static const struct acpi_gpio_params ldoena_gpios = { 2, 0, false };
static const struct acpi_gpio_mapping arizona_acpi_gpios[] = {
{ "reset-gpios", &reset_gpios, 1, },
{ "wlf,ldoena-gpios", &ldoena_gpios, 1 },
{ }
};
/*
* The ACPI resources for the device only describe external GPIO-s. They do
* not provide mappings for the GPIO-s coming from the Arizona codec itself.
*/
static const struct gpiod_lookup arizona_soc_gpios[] = {
{ "arizona", 2, "wlf,spkvdd-ena", 0, GPIO_ACTIVE_HIGH },
{ "arizona", 4, "wlf,micd-pol", 0, GPIO_ACTIVE_LOW },
};
static void arizona_spi_acpi_remove_lookup(void *lookup)
{
gpiod_remove_lookup_table(lookup);
}
/* For ACPI tables from boards which ship with Windows as factory OS */
static int arizona_spi_acpi_windows_probe(struct arizona *arizona)
{
struct gpiod_lookup_table *lookup;
acpi_status status;
int ret;
/* Add mappings for the 2 ACPI declared GPIOs used for reset and ldo-ena */
devm_acpi_dev_add_driver_gpios(arizona->dev, arizona_acpi_gpios);
/* Add lookups for the SoCs own GPIOs used for micdet-polarity and spkVDD-enable */
lookup = devm_kzalloc(arizona->dev,
struct_size(lookup, table, ARRAY_SIZE(arizona_soc_gpios) + 1),
GFP_KERNEL);
if (!lookup)
return -ENOMEM;
lookup->dev_id = dev_name(arizona->dev);
memcpy(lookup->table, arizona_soc_gpios, sizeof(arizona_soc_gpios));
gpiod_add_lookup_table(lookup);
ret = devm_add_action_or_reset(arizona->dev, arizona_spi_acpi_remove_lookup, lookup);
if (ret)
return ret;
/* Enable 32KHz clock from SoC to codec for jack-detect */
status = acpi_evaluate_object(ACPI_HANDLE(arizona->dev), "CLKE", NULL, NULL);
if (ACPI_FAILURE(status))
dev_warn(arizona->dev, "Failed to enable 32KHz clk ACPI error %d\n", status);
return 0;
}
/* For ACPI tables from boards which ship with Android as factory OS */
static int arizona_spi_acpi_android_probe(struct arizona *arizona)
{
int ret;
/*
* Get the reset GPIO, treating -ENOENT as -EPROBE_DEFER to wait for
* the x86-android-tablets module to register the board specific GPIO
* lookup table.
*/
arizona->pdata.reset = devm_gpiod_get(arizona->dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(arizona->pdata.reset)) {
ret = PTR_ERR(arizona->pdata.reset);
if (ret == -ENOENT) {
dev_info_once(arizona->dev,
"Deferring probe till GPIO lookup is registered\n");
ret = -EPROBE_DEFER;
}
return dev_err_probe(arizona->dev, ret, "getting reset GPIO\n");
}
return 0;
}
/*
* The AOSP 3.5 mm Headset: Accessory Specification gives the following values:
* Function A Play/Pause: 0 ohm
* Function D Voice assistant: 135 ohm
* Function B Volume Up 240 ohm
* Function C Volume Down 470 ohm
* Minimum Mic DC resistance 1000 ohm
* Minimum Ear speaker impedance 16 ohm
* Note the first max value below must be less then the min. speaker impedance,
* to allow CTIA/OMTP detection to work. The other max values are the closest
* value from extcon-arizona.c:arizona_micd_levels halfway 2 button resistances.
*/
static const struct arizona_micd_range arizona_micd_aosp_ranges[] = {
{ .max = 11, .key = KEY_PLAYPAUSE },
{ .max = 186, .key = KEY_VOICECOMMAND },
{ .max = 348, .key = KEY_VOLUMEUP },
{ .max = 752, .key = KEY_VOLUMEDOWN },
};
static int arizona_spi_acpi_probe(struct arizona *arizona)
{
struct acpi_device *adev = ACPI_COMPANION(arizona->dev);
int ret;
if (acpi_dev_hid_uid_match(adev, "10WM5102", NULL))
ret = arizona_spi_acpi_android_probe(arizona);
else
ret = arizona_spi_acpi_windows_probe(arizona);
if (ret)
return ret;
/*
* Some DSDTs wrongly declare the IRQ trigger-type as IRQF_TRIGGER_FALLING
* The IRQ line will stay low when a new IRQ event happens between reading
* the IRQ status flags and acknowledging them. When the IRQ line stays
* low like this the IRQ will never trigger again when its type is set
* to IRQF_TRIGGER_FALLING. Correct the IRQ trigger-type to fix this.
*
* Note theoretically it is possible that some boards are not capable
* of handling active low level interrupts. In that case setting the
* flag to IRQF_TRIGGER_FALLING would not be a bug (and we would need
* to work around this) but so far all known usages of IRQF_TRIGGER_FALLING
* are a bug in the board's DSDT.
*/
arizona->pdata.irq_flags = IRQF_TRIGGER_LOW;
/* Wait 200 ms after jack insertion */
arizona->pdata.micd_detect_debounce = 200;
/* Use standard AOSP values for headset-button mappings */
arizona->pdata.micd_ranges = arizona_micd_aosp_ranges;
arizona->pdata.num_micd_ranges = ARRAY_SIZE(arizona_micd_aosp_ranges);
return 0;
}
static const struct acpi_device_id arizona_acpi_match[] = {
{
.id = "WM510204",
.driver_data = WM5102,
},
{
.id = "WM510205",
.driver_data = WM5102,
},
{
.id = "10WM5102",
.driver_data = WM5102,
},
{ }
};
MODULE_DEVICE_TABLE(acpi, arizona_acpi_match);
#else
static int arizona_spi_acpi_probe(struct arizona *arizona)
{
return -ENODEV;
}
#endif
static int arizona_spi_probe(struct spi_device *spi)
{
const struct spi_device_id *id = spi_get_device_id(spi);
const void *match_data;
struct arizona *arizona;
const struct regmap_config *regmap_config = NULL;
unsigned long type = 0;
int ret;
match_data = device_get_match_data(&spi->dev);
if (match_data)
type = (unsigned long)match_data;
else if (id)
type = id->driver_data;
switch (type) {
case WM5102:
if (IS_ENABLED(CONFIG_MFD_WM5102))
regmap_config = &wm5102_spi_regmap;
break;
case WM5110:
case WM8280:
if (IS_ENABLED(CONFIG_MFD_WM5110))
regmap_config = &wm5110_spi_regmap;
break;
case WM1831:
case CS47L24:
if (IS_ENABLED(CONFIG_MFD_CS47L24))
regmap_config = &cs47l24_spi_regmap;
break;
default:
dev_err(&spi->dev, "Unknown device type %ld\n", type);
return -EINVAL;
}
if (!regmap_config) {
dev_err(&spi->dev,
"No kernel support for device type %ld\n", type);
return -EINVAL;
}
arizona = devm_kzalloc(&spi->dev, sizeof(*arizona), GFP_KERNEL);
if (arizona == NULL)
return -ENOMEM;
arizona->regmap = devm_regmap_init_spi(spi, regmap_config);
if (IS_ERR(arizona->regmap)) {
ret = PTR_ERR(arizona->regmap);
dev_err(&spi->dev, "Failed to allocate register map: %d\n",
ret);
return ret;
}
arizona->type = type;
arizona->dev = &spi->dev;
arizona->irq = spi->irq;
if (has_acpi_companion(&spi->dev)) {
ret = arizona_spi_acpi_probe(arizona);
if (ret)
return ret;
}
return arizona_dev_init(arizona);
}
static void arizona_spi_remove(struct spi_device *spi)
{
struct arizona *arizona = spi_get_drvdata(spi);
arizona_dev_exit(arizona);
}
static const struct spi_device_id arizona_spi_ids[] = {
{ "wm5102", WM5102 },
{ "wm5110", WM5110 },
{ "wm8280", WM8280 },
{ "wm1831", WM1831 },
{ "cs47l24", CS47L24 },
{ },
};
MODULE_DEVICE_TABLE(spi, arizona_spi_ids);
#ifdef CONFIG_OF
static const struct of_device_id arizona_spi_of_match[] = {
{ .compatible = "wlf,wm5102", .data = (void *)WM5102 },
{ .compatible = "wlf,wm5110", .data = (void *)WM5110 },
{ .compatible = "wlf,wm8280", .data = (void *)WM8280 },
{ .compatible = "wlf,wm1831", .data = (void *)WM1831 },
{ .compatible = "cirrus,cs47l24", .data = (void *)CS47L24 },
{},
};
MODULE_DEVICE_TABLE(of, arizona_spi_of_match);
#endif
static struct spi_driver arizona_spi_driver = {
.driver = {
.name = "arizona",
.pm = pm_ptr(&arizona_pm_ops),
.of_match_table = of_match_ptr(arizona_spi_of_match),
.acpi_match_table = ACPI_PTR(arizona_acpi_match),
},
.probe = arizona_spi_probe,
.remove = arizona_spi_remove,
.id_table = arizona_spi_ids,
};
module_spi_driver(arizona_spi_driver);
MODULE_SOFTDEP("pre: arizona_ldo1");
MODULE_DESCRIPTION("Arizona SPI bus interface");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/mfd/arizona-spi.c |
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