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// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 ST Microelectronics * Viresh Kumar <[email protected]> * * SPEAr clk - Common routines */ #include <linux/clk-provider.h> #include <linux/types.h> #include "clk.h" long clk_round_rate_index(struct clk_hw *hw, unsigned long drate, unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt, int *index) { unsigned long prev_rate, rate = 0; for (*index = 0; *index < rtbl_cnt; (*index)++) { prev_rate = rate; rate = calc_rate(hw, parent_rate, *index); if (drate < rate) { /* previous clock was best */ if (*index) { rate = prev_rate; (*index)--; } break; } } if ((*index) == rtbl_cnt) (*index)--; return rate; }
linux-master
drivers/clk/spear/clk.c
// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-spear13xx/spear1310_clock.c * * SPEAr1310 machine clock framework source file * * Copyright (C) 2012 ST Microelectronics * Viresh Kumar <[email protected]> */ #include <linux/clkdev.h> #include <linux/clk/spear.h> #include <linux/err.h> #include <linux/io.h> #include <linux/spinlock_types.h> #include "clk.h" /* PLL related registers and bit values */ #define SPEAR1310_PLL_CFG (misc_base + 0x210) /* PLL_CFG bit values */ #define SPEAR1310_CLCD_SYNT_CLK_MASK 1 #define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31 #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2 #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT 29 #define SPEAR1310_RAS_SYNT_CLK_MASK 2 #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT 27 #define SPEAR1310_PLL_CLK_MASK 2 #define SPEAR1310_PLL3_CLK_SHIFT 24 #define SPEAR1310_PLL2_CLK_SHIFT 22 #define SPEAR1310_PLL1_CLK_SHIFT 20 #define SPEAR1310_PLL1_CTR (misc_base + 0x214) #define SPEAR1310_PLL1_FRQ (misc_base + 0x218) #define SPEAR1310_PLL2_CTR (misc_base + 0x220) #define SPEAR1310_PLL2_FRQ (misc_base + 0x224) #define SPEAR1310_PLL3_CTR (misc_base + 0x22C) #define SPEAR1310_PLL3_FRQ (misc_base + 0x230) #define SPEAR1310_PLL4_CTR (misc_base + 0x238) #define SPEAR1310_PLL4_FRQ (misc_base + 0x23C) #define SPEAR1310_PERIP_CLK_CFG (misc_base + 0x244) /* PERIP_CLK_CFG bit values */ #define SPEAR1310_GPT_OSC24_VAL 0 #define SPEAR1310_GPT_APB_VAL 1 #define SPEAR1310_GPT_CLK_MASK 1 #define SPEAR1310_GPT3_CLK_SHIFT 11 #define SPEAR1310_GPT2_CLK_SHIFT 10 #define SPEAR1310_GPT1_CLK_SHIFT 9 #define SPEAR1310_GPT0_CLK_SHIFT 8 #define SPEAR1310_UART_CLK_PLL5_VAL 0 #define SPEAR1310_UART_CLK_OSC24_VAL 1 #define SPEAR1310_UART_CLK_SYNT_VAL 2 #define SPEAR1310_UART_CLK_MASK 2 #define SPEAR1310_UART_CLK_SHIFT 4 #define SPEAR1310_AUX_CLK_PLL5_VAL 0 #define SPEAR1310_AUX_CLK_SYNT_VAL 1 #define SPEAR1310_CLCD_CLK_MASK 2 #define SPEAR1310_CLCD_CLK_SHIFT 2 #define SPEAR1310_C3_CLK_MASK 1 #define SPEAR1310_C3_CLK_SHIFT 1 #define SPEAR1310_GMAC_CLK_CFG (misc_base + 0x248) #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3 #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4 #define SPEAR1310_GMAC_PHY_CLK_MASK 1 #define SPEAR1310_GMAC_PHY_CLK_SHIFT 3 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1 #define SPEAR1310_I2S_CLK_CFG (misc_base + 0x24C) /* I2S_CLK_CFG register mask */ #define SPEAR1310_I2S_SCLK_X_MASK 0x1F #define SPEAR1310_I2S_SCLK_X_SHIFT 27 #define SPEAR1310_I2S_SCLK_Y_MASK 0x1F #define SPEAR1310_I2S_SCLK_Y_SHIFT 22 #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT 21 #define SPEAR1310_I2S_SCLK_SYNTH_ENB 20 #define SPEAR1310_I2S_PRS1_CLK_X_MASK 0xFF #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT 12 #define SPEAR1310_I2S_PRS1_CLK_Y_MASK 0xFF #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT 4 #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT 3 #define SPEAR1310_I2S_REF_SEL_MASK 1 #define SPEAR1310_I2S_REF_SHIFT 2 #define SPEAR1310_I2S_SRC_CLK_MASK 2 #define SPEAR1310_I2S_SRC_CLK_SHIFT 0 #define SPEAR1310_C3_CLK_SYNT (misc_base + 0x250) #define SPEAR1310_UART_CLK_SYNT (misc_base + 0x254) #define SPEAR1310_GMAC_CLK_SYNT (misc_base + 0x258) #define SPEAR1310_SDHCI_CLK_SYNT (misc_base + 0x25C) #define SPEAR1310_CFXD_CLK_SYNT (misc_base + 0x260) #define SPEAR1310_ADC_CLK_SYNT (misc_base + 0x264) #define SPEAR1310_AMBA_CLK_SYNT (misc_base + 0x268) #define SPEAR1310_CLCD_CLK_SYNT (misc_base + 0x270) #define SPEAR1310_RAS_CLK_SYNT0 (misc_base + 0x280) #define SPEAR1310_RAS_CLK_SYNT1 (misc_base + 0x288) #define SPEAR1310_RAS_CLK_SYNT2 (misc_base + 0x290) #define SPEAR1310_RAS_CLK_SYNT3 (misc_base + 0x298) /* Check Fractional synthesizer reg masks */ #define SPEAR1310_PERIP1_CLK_ENB (misc_base + 0x300) /* PERIP1_CLK_ENB register masks */ #define SPEAR1310_RTC_CLK_ENB 31 #define SPEAR1310_ADC_CLK_ENB 30 #define SPEAR1310_C3_CLK_ENB 29 #define SPEAR1310_JPEG_CLK_ENB 28 #define SPEAR1310_CLCD_CLK_ENB 27 #define SPEAR1310_DMA_CLK_ENB 25 #define SPEAR1310_GPIO1_CLK_ENB 24 #define SPEAR1310_GPIO0_CLK_ENB 23 #define SPEAR1310_GPT1_CLK_ENB 22 #define SPEAR1310_GPT0_CLK_ENB 21 #define SPEAR1310_I2S0_CLK_ENB 20 #define SPEAR1310_I2S1_CLK_ENB 19 #define SPEAR1310_I2C0_CLK_ENB 18 #define SPEAR1310_SSP_CLK_ENB 17 #define SPEAR1310_UART_CLK_ENB 15 #define SPEAR1310_PCIE_SATA_2_CLK_ENB 14 #define SPEAR1310_PCIE_SATA_1_CLK_ENB 13 #define SPEAR1310_PCIE_SATA_0_CLK_ENB 12 #define SPEAR1310_UOC_CLK_ENB 11 #define SPEAR1310_UHC1_CLK_ENB 10 #define SPEAR1310_UHC0_CLK_ENB 9 #define SPEAR1310_GMAC_CLK_ENB 8 #define SPEAR1310_CFXD_CLK_ENB 7 #define SPEAR1310_SDHCI_CLK_ENB 6 #define SPEAR1310_SMI_CLK_ENB 5 #define SPEAR1310_FSMC_CLK_ENB 4 #define SPEAR1310_SYSRAM0_CLK_ENB 3 #define SPEAR1310_SYSRAM1_CLK_ENB 2 #define SPEAR1310_SYSROM_CLK_ENB 1 #define SPEAR1310_BUS_CLK_ENB 0 #define SPEAR1310_PERIP2_CLK_ENB (misc_base + 0x304) /* PERIP2_CLK_ENB register masks */ #define SPEAR1310_THSENS_CLK_ENB 8 #define SPEAR1310_I2S_REF_PAD_CLK_ENB 7 #define SPEAR1310_ACP_CLK_ENB 6 #define SPEAR1310_GPT3_CLK_ENB 5 #define SPEAR1310_GPT2_CLK_ENB 4 #define SPEAR1310_KBD_CLK_ENB 3 #define SPEAR1310_CPU_DBG_CLK_ENB 2 #define SPEAR1310_DDR_CORE_CLK_ENB 1 #define SPEAR1310_DDR_CTRL_CLK_ENB 0 #define SPEAR1310_RAS_CLK_ENB (misc_base + 0x310) /* RAS_CLK_ENB register masks */ #define SPEAR1310_SYNT3_CLK_ENB 17 #define SPEAR1310_SYNT2_CLK_ENB 16 #define SPEAR1310_SYNT1_CLK_ENB 15 #define SPEAR1310_SYNT0_CLK_ENB 14 #define SPEAR1310_PCLK3_CLK_ENB 13 #define SPEAR1310_PCLK2_CLK_ENB 12 #define SPEAR1310_PCLK1_CLK_ENB 11 #define SPEAR1310_PCLK0_CLK_ENB 10 #define SPEAR1310_PLL3_CLK_ENB 9 #define SPEAR1310_PLL2_CLK_ENB 8 #define SPEAR1310_C125M_PAD_CLK_ENB 7 #define SPEAR1310_C30M_CLK_ENB 6 #define SPEAR1310_C48M_CLK_ENB 5 #define SPEAR1310_OSC_25M_CLK_ENB 4 #define SPEAR1310_OSC_32K_CLK_ENB 3 #define SPEAR1310_OSC_24M_CLK_ENB 2 #define SPEAR1310_PCLK_CLK_ENB 1 #define SPEAR1310_ACLK_CLK_ENB 0 /* RAS Area Control Register */ #define SPEAR1310_RAS_CTRL_REG0 (ras_base + 0x000) #define SPEAR1310_SSP1_CLK_MASK 3 #define SPEAR1310_SSP1_CLK_SHIFT 26 #define SPEAR1310_TDM_CLK_MASK 1 #define SPEAR1310_TDM2_CLK_SHIFT 24 #define SPEAR1310_TDM1_CLK_SHIFT 23 #define SPEAR1310_I2C_CLK_MASK 1 #define SPEAR1310_I2C7_CLK_SHIFT 22 #define SPEAR1310_I2C6_CLK_SHIFT 21 #define SPEAR1310_I2C5_CLK_SHIFT 20 #define SPEAR1310_I2C4_CLK_SHIFT 19 #define SPEAR1310_I2C3_CLK_SHIFT 18 #define SPEAR1310_I2C2_CLK_SHIFT 17 #define SPEAR1310_I2C1_CLK_SHIFT 16 #define SPEAR1310_GPT64_CLK_MASK 1 #define SPEAR1310_GPT64_CLK_SHIFT 15 #define SPEAR1310_RAS_UART_CLK_MASK 1 #define SPEAR1310_UART5_CLK_SHIFT 14 #define SPEAR1310_UART4_CLK_SHIFT 13 #define SPEAR1310_UART3_CLK_SHIFT 12 #define SPEAR1310_UART2_CLK_SHIFT 11 #define SPEAR1310_UART1_CLK_SHIFT 10 #define SPEAR1310_PCI_CLK_MASK 1 #define SPEAR1310_PCI_CLK_SHIFT 0 #define SPEAR1310_RAS_CTRL_REG1 (ras_base + 0x004) #define SPEAR1310_PHY_CLK_MASK 0x3 #define SPEAR1310_RMII_PHY_CLK_SHIFT 0 #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2 #define SPEAR1310_RAS_SW_CLK_CTRL (ras_base + 0x0148) #define SPEAR1310_CAN1_CLK_ENB 25 #define SPEAR1310_CAN0_CLK_ENB 24 #define SPEAR1310_GPT64_CLK_ENB 23 #define SPEAR1310_SSP1_CLK_ENB 22 #define SPEAR1310_I2C7_CLK_ENB 21 #define SPEAR1310_I2C6_CLK_ENB 20 #define SPEAR1310_I2C5_CLK_ENB 19 #define SPEAR1310_I2C4_CLK_ENB 18 #define SPEAR1310_I2C3_CLK_ENB 17 #define SPEAR1310_I2C2_CLK_ENB 16 #define SPEAR1310_I2C1_CLK_ENB 15 #define SPEAR1310_UART5_CLK_ENB 14 #define SPEAR1310_UART4_CLK_ENB 13 #define SPEAR1310_UART3_CLK_ENB 12 #define SPEAR1310_UART2_CLK_ENB 11 #define SPEAR1310_UART1_CLK_ENB 10 #define SPEAR1310_RS485_1_CLK_ENB 9 #define SPEAR1310_RS485_0_CLK_ENB 8 #define SPEAR1310_TDM2_CLK_ENB 7 #define SPEAR1310_TDM1_CLK_ENB 6 #define SPEAR1310_PCI_CLK_ENB 5 #define SPEAR1310_GMII_CLK_ENB 4 #define SPEAR1310_MII2_CLK_ENB 3 #define SPEAR1310_MII1_CLK_ENB 2 #define SPEAR1310_MII0_CLK_ENB 1 #define SPEAR1310_ESRAM_CLK_ENB 0 static DEFINE_SPINLOCK(_lock); /* pll rate configuration table, in ascending order of rates */ static struct pll_rate_tbl pll_rtbl[] = { /* PCLK 24MHz */ {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */ {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */ {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */ {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */ {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */ {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */ {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ }; /* vco-pll4 rate configuration table, in ascending order of rates */ static struct pll_rate_tbl pll4_rtbl[] = { {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */ {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */ {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */ {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ }; /* aux rate configuration table, in ascending order of rates */ static struct aux_rate_tbl aux_rtbl[] = { /* For VCO1div2 = 500 MHz */ {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */ {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */ {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */ {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */ {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */ {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */ }; /* gmac rate configuration table, in ascending order of rates */ static struct aux_rate_tbl gmac_rtbl[] = { /* For gmac phy input clk */ {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */ {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */ {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */ {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */ }; /* clcd rate configuration table, in ascending order of rates */ static struct frac_rate_tbl clcd_rtbl[] = { {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/ {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/ {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */ {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */ {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/ {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/ {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */ {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/ {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/ {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/ }; /* i2s prescaler1 masks */ static const struct aux_clk_masks i2s_prs1_masks = { .eq_sel_mask = AUX_EQ_SEL_MASK, .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT, .eq1_mask = AUX_EQ1_SEL, .eq2_mask = AUX_EQ2_SEL, .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK, .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT, .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK, .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT, }; /* i2s sclk (bit clock) syynthesizers masks */ static struct aux_clk_masks i2s_sclk_masks = { .eq_sel_mask = AUX_EQ_SEL_MASK, .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT, .eq1_mask = AUX_EQ1_SEL, .eq2_mask = AUX_EQ2_SEL, .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK, .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT, .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK, .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT, .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB, }; /* i2s prs1 aux rate configuration table, in ascending order of rates */ static struct aux_rate_tbl i2s_prs1_rtbl[] = { /* For parent clk = 49.152 MHz */ {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */ {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */ {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */ {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */ /* * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz */ {.xscale = 1, .yscale = 3, .eq = 0}, /* For parent clk = 49.152 MHz */ {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/ {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */ }; /* i2s sclk aux rate configuration table, in ascending order of rates */ static struct aux_rate_tbl i2s_sclk_rtbl[] = { /* For i2s_ref_clk = 12.288MHz */ {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */ {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */ }; /* adc rate configuration table, in ascending order of rates */ /* possible adc range is 2.5 MHz to 20 MHz. */ static struct aux_rate_tbl adc_rtbl[] = { /* For ahb = 166.67 MHz */ {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */ {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */ {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */ {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */ }; /* General synth rate configuration table, in ascending order of rates */ static struct frac_rate_tbl gen_rtbl[] = { /* For vco1div4 = 250 MHz */ {.div = 0x14000}, /* 25 MHz */ {.div = 0x0A000}, /* 50 MHz */ {.div = 0x05000}, /* 100 MHz */ {.div = 0x02000}, /* 250 MHz */ }; /* clock parents */ static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", }; static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", }; static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", }; static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", }; static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk", "osc_25m_clk", }; static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", }; static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", }; static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", }; static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk", "i2s_src_pad_clk", }; static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", }; static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk", "pll3_clk", }; static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk", "pll2_clk", }; static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none", "ras_pll2_clk", "ras_syn0_clk", }; static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk", "ras_pll2_clk", "ras_syn0_clk", }; static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", }; static const char *i2c_parents[] = { "ras_apb_clk", "gen_syn1_clk", }; static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk", "ras_plclk0_clk", }; static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", }; static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", }; void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) { struct clk *clk, *clk1; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); clk_register_clkdev(clk, "osc_32k_clk", NULL); clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000); clk_register_clkdev(clk, "osc_24m_clk", NULL); clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000); clk_register_clkdev(clk, "osc_25m_clk", NULL); clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000); clk_register_clkdev(clk, "gmii_pad_clk", NULL); clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0, 12288000); clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); /* clock derived from 32 KHz osc clk */ clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0580000.rtc"); /* clock derived from 24 or 25 MHz osc clk */ /* vco-pll */ clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "vco1_mclk", NULL); clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco1_clk", NULL); clk_register_clkdev(clk1, "pll1_clk", NULL); clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "vco2_mclk", NULL); clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco2_clk", NULL); clk_register_clkdev(clk1, "pll2_clk", NULL); clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "vco3_mclk", NULL); clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco3_clk", NULL); clk_register_clkdev(clk1, "pll3_clk", NULL); clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk", 0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl, ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco4_clk", NULL); clk_register_clkdev(clk1, "pll4_clk", NULL); clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0, 48000000); clk_register_clkdev(clk, "pll5_clk", NULL); clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0, 25000000); clk_register_clkdev(clk, "pll6_clk", NULL); /* vco div n clocks */ clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, 2); clk_register_clkdev(clk, "vco1div2_clk", NULL); clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, 4); clk_register_clkdev(clk, "vco1div4_clk", NULL); clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, 2); clk_register_clkdev(clk, "vco2div2_clk", NULL); clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, 2); clk_register_clkdev(clk, "vco3div2_clk", NULL); /* peripherals */ clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, 128); clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "spear_thermal"); /* clock derived from pll4 clk */ clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, 1); clk_register_clkdev(clk, "ddr_clk", NULL); /* clock derived from pll1 clk */ clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", CLK_SET_RATE_PARENT, 1, 2); clk_register_clkdev(clk, "cpu_clk", NULL); clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, 2); clk_register_clkdev(clk, NULL, "ec800620.wdt"); clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, 2); clk_register_clkdev(clk, NULL, "smp_twd"); clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1, 6); clk_register_clkdev(clk, "ahb_clk", NULL); clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1, 12); clk_register_clkdev(clk, "apb_clk", NULL); /* gpt clocks */ clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt0_mclk", NULL); clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt0"); clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt1_mclk", NULL); clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt1"); clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt2_mclk", NULL); clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt2"); clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt3_mclk", NULL); clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt3"); /* others */ clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk", 0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "uart_syn_clk", NULL); clk_register_clkdev(clk1, "uart_syn_gclk", NULL); clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT, SPEAR1310_UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart0_mclk", NULL); clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UART_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0000000.serial"); clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "sdhci_syn_clk", NULL); clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SDHCI_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b3000000.sdhci"); clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", 0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "cfxd_syn_clk", NULL); clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CFXD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b2800000.cf"); clk_register_clkdev(clk, NULL, "arasan_xd"); clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "c3_syn_clk", NULL); clk_register_clkdev(clk1, "c3_syn_gclk", NULL); clk = clk_register_mux(NULL, "c3_mclk", c3_parents, ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT, SPEAR1310_C3_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "c3_mclk", NULL); clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "c3"); /* gmac */ clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, ARRAY_SIZE(gmac_phy_input_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_GMAC_CLK_CFG, SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT, SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "phy_input_mclk", NULL); clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk", 0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "phy_syn_clk", NULL); clk_register_clkdev(clk1, "phy_syn_gclk", NULL); clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT, SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "stmmacphy.0", NULL); /* clcd */ clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, ARRAY_SIZE(clcd_synth_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT, SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "clcd_syn_mclk", NULL); clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0, SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl, ARRAY_SIZE(clcd_rtbl), &_lock); clk_register_clkdev(clk, "clcd_syn_clk", NULL); clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT, SPEAR1310_CLCD_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e1000000.clcd"); /* i2s */ clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2s_src_mclk", NULL); clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0, SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl, ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL); clk_register_clkdev(clk, "i2s_prs1_clk", NULL); clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT, SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock); clk_register_clkdev(clk, "i2s_ref_mclk", NULL); clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG, &i2s_sclk_masks, i2s_sclk_rtbl, ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "i2s_sclk_clk", NULL); clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL); /* clock derived from ahb clk */ clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0280000.i2c"); clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "ea800000.dma"); clk_register_clkdev(clk, NULL, "eb000000.dma"); clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b2000000.jpeg"); clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e2000000.eth"); clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b0000000.flash"); clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "ea000000.flash"); clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e4000000.ohci"); clk_register_clkdev(clk, NULL, "e4800000.ehci"); clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e5000000.ohci"); clk_register_clkdev(clk, NULL, "e5800000.ehci"); clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e3800000.otg"); clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b1000000.pcie"); clk_register_clkdev(clk, NULL, "b1000000.ahci"); clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b1800000.pcie"); clk_register_clkdev(clk, NULL, "b1800000.ahci"); clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "b4000000.pcie"); clk_register_clkdev(clk, NULL, "b4000000.ahci"); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "sysram0_clk", NULL); clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "sysram1_clk", NULL); clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk", 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl, ARRAY_SIZE(adc_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "adc_syn_clk", NULL); clk_register_clkdev(clk1, "adc_syn_gclk", NULL); clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0080000.adc"); /* clock derived from apb clk */ clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0100000.spi"); clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0600000.gpio"); clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0680000.gpio"); clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0180000.i2s"); clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0, SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0200000.i2s"); clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0300000.kbd"); /* RAS clks */ clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT0_1_CLK_SHIFT, SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gen_syn0_1_clk", NULL); clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT2_3_CLK_SHIFT, SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gen_syn2_3_clk", NULL); clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0, SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl), &_lock); clk_register_clkdev(clk, "gen_syn0_clk", NULL); clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0, SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl), &_lock); clk_register_clkdev(clk, "gen_syn1_clk", NULL); clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0, SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl), &_lock); clk_register_clkdev(clk, "gen_syn2_clk", NULL); clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0, SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl), &_lock); clk_register_clkdev(clk, "gen_syn3_clk", NULL); clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_osc_24m_clk", NULL); clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_osc_25m_clk", NULL); clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_osc_32k_clk", NULL); clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_pll2_clk", NULL); clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_pll3_clk", NULL); clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_tx125_clk", NULL); clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0, 30000000); clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_30m_clk", NULL); clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0, 48000000); clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_48m_clk", NULL); clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_ahb_clk", NULL); clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_apb_clk", NULL); clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, 0, 50000000); clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, 0, 50000000); clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "c_can_platform.0"); clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "c_can_platform.1"); clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5c400000.eth"); clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5c500000.eth"); clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5c600000.eth"); clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5c700000.eth"); clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk", smii_rgmii_phy_parents, ARRAY_SIZE(smii_rgmii_phy_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1, SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT, SPEAR1310_PHY_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "stmmacphy.1", NULL); clk_register_clkdev(clk, "stmmacphy.2", NULL); clk_register_clkdev(clk, "stmmacphy.4", NULL); clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents, ARRAY_SIZE(rmii_phy_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT, SPEAR1310_PHY_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "stmmacphy.3", NULL); clk = clk_register_mux(NULL, "uart1_mclk", uart_parents, ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart1_mclk", NULL); clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5c800000.serial"); clk = clk_register_mux(NULL, "uart2_mclk", uart_parents, ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart2_mclk", NULL); clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5c900000.serial"); clk = clk_register_mux(NULL, "uart3_mclk", uart_parents, ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart3_mclk", NULL); clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5ca00000.serial"); clk = clk_register_mux(NULL, "uart4_mclk", uart_parents, ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart4_mclk", NULL); clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5cb00000.serial"); clk = clk_register_mux(NULL, "uart5_mclk", uart_parents, ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart5_mclk", NULL); clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5cc00000.serial"); clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents, ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2c1_mclk", NULL); clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5cd00000.i2c"); clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents, ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2c2_mclk", NULL); clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5ce00000.i2c"); clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents, ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2c3_mclk", NULL); clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5cf00000.i2c"); clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents, ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2c4_mclk", NULL); clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5d000000.i2c"); clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents, ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2c5_mclk", NULL); clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5d100000.i2c"); clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents, ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2c6_mclk", NULL); clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5d200000.i2c"); clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents, ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2c7_mclk", NULL); clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5d300000.i2c"); clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents, ARRAY_SIZE(ssp1_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "ssp1_mclk", NULL); clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "5d400000.spi"); clk = clk_register_mux(NULL, "pci_mclk", pci_parents, ARRAY_SIZE(pci_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "pci_mclk", NULL); clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "pci"); clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents, ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "tdm1_mclk", NULL); clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "tdm_hdlc.0"); clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents, ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "tdm2_mclk", NULL); clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "tdm_hdlc.1"); }
linux-master
drivers/clk/spear/spear1310_clock.c
// SPDX-License-Identifier: GPL-2.0-only /* * SPEAr3xx machines clock framework source file * * Copyright (C) 2012 ST Microelectronics * Viresh Kumar <[email protected]> */ #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/clk/spear.h> #include <linux/err.h> #include <linux/io.h> #include <linux/of.h> #include <linux/spinlock_types.h> #include "clk.h" static DEFINE_SPINLOCK(_lock); #define PLL1_CTR (misc_base + 0x008) #define PLL1_FRQ (misc_base + 0x00C) #define PLL2_CTR (misc_base + 0x014) #define PLL2_FRQ (misc_base + 0x018) #define PLL_CLK_CFG (misc_base + 0x020) /* PLL_CLK_CFG register masks */ #define MCTR_CLK_SHIFT 28 #define MCTR_CLK_MASK 3 #define CORE_CLK_CFG (misc_base + 0x024) /* CORE CLK CFG register masks */ #define GEN_SYNTH2_3_CLK_SHIFT 18 #define GEN_SYNTH2_3_CLK_MASK 1 #define HCLK_RATIO_SHIFT 10 #define HCLK_RATIO_MASK 2 #define PCLK_RATIO_SHIFT 8 #define PCLK_RATIO_MASK 2 #define PERIP_CLK_CFG (misc_base + 0x028) /* PERIP_CLK_CFG register masks */ #define UART_CLK_SHIFT 4 #define UART_CLK_MASK 1 #define FIRDA_CLK_SHIFT 5 #define FIRDA_CLK_MASK 2 #define GPT0_CLK_SHIFT 8 #define GPT1_CLK_SHIFT 11 #define GPT2_CLK_SHIFT 12 #define GPT_CLK_MASK 1 #define PERIP1_CLK_ENB (misc_base + 0x02C) /* PERIP1_CLK_ENB register masks */ #define UART_CLK_ENB 3 #define SSP_CLK_ENB 5 #define I2C_CLK_ENB 7 #define JPEG_CLK_ENB 8 #define FIRDA_CLK_ENB 10 #define GPT1_CLK_ENB 11 #define GPT2_CLK_ENB 12 #define ADC_CLK_ENB 15 #define RTC_CLK_ENB 17 #define GPIO_CLK_ENB 18 #define DMA_CLK_ENB 19 #define SMI_CLK_ENB 21 #define GMAC_CLK_ENB 23 #define USBD_CLK_ENB 24 #define USBH_CLK_ENB 25 #define C3_CLK_ENB 31 #define RAS_CLK_ENB (misc_base + 0x034) #define RAS_AHB_CLK_ENB 0 #define RAS_PLL1_CLK_ENB 1 #define RAS_APB_CLK_ENB 2 #define RAS_32K_CLK_ENB 3 #define RAS_24M_CLK_ENB 4 #define RAS_48M_CLK_ENB 5 #define RAS_PLL2_CLK_ENB 7 #define RAS_SYNT0_CLK_ENB 8 #define RAS_SYNT1_CLK_ENB 9 #define RAS_SYNT2_CLK_ENB 10 #define RAS_SYNT3_CLK_ENB 11 #define PRSC0_CLK_CFG (misc_base + 0x044) #define PRSC1_CLK_CFG (misc_base + 0x048) #define PRSC2_CLK_CFG (misc_base + 0x04C) #define AMEM_CLK_CFG (misc_base + 0x050) #define AMEM_CLK_ENB 0 #define CLCD_CLK_SYNT (misc_base + 0x05C) #define FIRDA_CLK_SYNT (misc_base + 0x060) #define UART_CLK_SYNT (misc_base + 0x064) #define GMAC_CLK_SYNT (misc_base + 0x068) #define GEN0_CLK_SYNT (misc_base + 0x06C) #define GEN1_CLK_SYNT (misc_base + 0x070) #define GEN2_CLK_SYNT (misc_base + 0x074) #define GEN3_CLK_SYNT (misc_base + 0x078) /* pll rate configuration table, in ascending order of rates */ static struct pll_rate_tbl pll_rtbl[] = { {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */ {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */ {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */ }; /* aux rate configuration table, in ascending order of rates */ static struct aux_rate_tbl aux_rtbl[] = { /* For PLL1 = 332 MHz */ {.xscale = 1, .yscale = 81, .eq = 0}, /* 2.049 MHz */ {.xscale = 1, .yscale = 59, .eq = 0}, /* 2.822 MHz */ {.xscale = 2, .yscale = 81, .eq = 0}, /* 4.098 MHz */ {.xscale = 3, .yscale = 89, .eq = 0}, /* 5.644 MHz */ {.xscale = 4, .yscale = 81, .eq = 0}, /* 8.197 MHz */ {.xscale = 4, .yscale = 59, .eq = 0}, /* 11.254 MHz */ {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */ {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */ {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */ {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ }; /* gpt rate configuration table, in ascending order of rates */ static struct gpt_rate_tbl gpt_rtbl[] = { /* For pll1 = 332 MHz */ {.mscale = 4, .nscale = 0}, /* 41.5 MHz */ {.mscale = 2, .nscale = 0}, /* 55.3 MHz */ {.mscale = 1, .nscale = 0}, /* 83 MHz */ }; /* clock parents */ static const char *uart0_parents[] = { "pll3_clk", "uart_syn_gclk", }; static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", }; static const char *gpt0_parents[] = { "pll3_clk", "gpt0_syn_clk", }; static const char *gpt1_parents[] = { "pll3_clk", "gpt1_syn_clk", }; static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", }; static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", }; static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", "pll2_clk", }; #ifdef CONFIG_MACH_SPEAR300 static void __init spear300_clk_init(void) { struct clk *clk; clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "60000000.clcd"); clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "94000000.flash"); clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "70000000.sdhci"); clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "a9000000.gpio"); clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "a0000000.kbd"); } #else static inline void spear300_clk_init(void) { } #endif /* array of all spear 310 clock lookups */ #ifdef CONFIG_MACH_SPEAR310 static void __init spear310_clk_init(void) { struct clk *clk; clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, 1); clk_register_clkdev(clk, "emi", NULL); clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "44000000.flash"); clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "tdm"); clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "b2000000.serial"); clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "b2080000.serial"); clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "b2100000.serial"); clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "b2180000.serial"); clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "b2200000.serial"); } #else static inline void spear310_clk_init(void) { } #endif /* array of all spear 320 clock lookups */ #ifdef CONFIG_MACH_SPEAR320 #define SPEAR320_CONTROL_REG (soc_config_base + 0x0010) #define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018) #define SPEAR320_UARTX_PCLK_MASK 0x1 #define SPEAR320_UART2_PCLK_SHIFT 8 #define SPEAR320_UART3_PCLK_SHIFT 9 #define SPEAR320_UART4_PCLK_SHIFT 10 #define SPEAR320_UART5_PCLK_SHIFT 11 #define SPEAR320_UART6_PCLK_SHIFT 12 #define SPEAR320_RS485_PCLK_SHIFT 13 #define SMII_PCLK_SHIFT 18 #define SMII_PCLK_MASK 2 #define SMII_PCLK_VAL_PAD 0x0 #define SMII_PCLK_VAL_PLL2 0x1 #define SMII_PCLK_VAL_SYNTH0 0x2 #define SDHCI_PCLK_SHIFT 15 #define SDHCI_PCLK_MASK 1 #define SDHCI_PCLK_VAL_48M 0x0 #define SDHCI_PCLK_VAL_SYNTH3 0x1 #define I2S_REF_PCLK_SHIFT 8 #define I2S_REF_PCLK_MASK 1 #define I2S_REF_PCLK_SYNTH_VAL 0x1 #define I2S_REF_PCLK_PLL2_VAL 0x0 #define UART1_PCLK_SHIFT 6 #define UART1_PCLK_MASK 1 #define SPEAR320_UARTX_PCLK_VAL_SYNTH1 0x0 #define SPEAR320_UARTX_PCLK_VAL_APB 0x1 static const char *i2s_ref_parents[] = { "ras_pll2_clk", "ras_syn2_gclk", }; static const char *sdhci_parents[] = { "ras_pll3_clk", "ras_syn3_gclk", }; static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk", "ras_syn0_gclk", }; static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", }; static void __init spear320_clk_init(void __iomem *soc_config_base, struct clk *ras_apb_clk) { struct clk *clk; clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL, 0, 125000000); clk_register_clkdev(clk, "smii_125m_pad", NULL); clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "90000000.clcd"); clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, 1); clk_register_clkdev(clk, "emi", NULL); clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "4c000000.flash"); clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "a7000000.i2c"); clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "a8000000.pwm"); clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "a5000000.spi"); clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "a6000000.spi"); clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "c_can_platform.0"); clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "c_can_platform.1"); clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "a9400000.i2s"); clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents, ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT, I2S_REF_PCLK_MASK, 0, &_lock); clk_register_clkdev(clk, "i2s_ref_clk", NULL); clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", CLK_SET_RATE_PARENT, 1, 4); clk_register_clkdev(clk, "i2s_sclk", NULL); clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1, 1); clk_register_clkdev(clk, "hclk", "aa000000.eth"); clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1, 1); clk_register_clkdev(clk, "hclk", "ab000000.eth"); clk = clk_register_mux(NULL, "rs485_clk", uartx_parents, ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "a9300000.serial"); clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents, ARRAY_SIZE(sdhci_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "70000000.sdhci"); clk = clk_register_mux(NULL, "smii_pclk", smii0_parents, ARRAY_SIZE(smii0_parents), CLK_SET_RATE_NO_REPARENT, SPEAR320_CONTROL_REG, SMII_PCLK_SHIFT, SMII_PCLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "smii_pclk"); clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1); clk_register_clkdev(clk, NULL, "smii"); clk = clk_register_mux(NULL, "uart1_clk", uartx_parents, ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "a3000000.serial"); /* Enforce ras_apb_clk */ clk_set_parent(clk, ras_apb_clk); clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "a4000000.serial"); /* Enforce ras_apb_clk */ clk_set_parent(clk, ras_apb_clk); clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "a9100000.serial"); clk = clk_register_mux(NULL, "uart4_clk", uartx_parents, ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "a9200000.serial"); clk = clk_register_mux(NULL, "uart5_clk", uartx_parents, ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "60000000.serial"); clk = clk_register_mux(NULL, "uart6_clk", uartx_parents, ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "60100000.serial"); } #else static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { } #endif void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base) { struct clk *clk, *clk1, *ras_apb_clk; clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); clk_register_clkdev(clk, "osc_32k_clk", NULL); clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000); clk_register_clkdev(clk, "osc_24m_clk", NULL); /* clock derived from 32 KHz osc clk */ clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "fc900000.rtc"); /* clock derived from 24 MHz osc clk */ clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, 48000000); clk_register_clkdev(clk, "pll3_clk", NULL); clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1, 1); clk_register_clkdev(clk, NULL, "fc880000.wdt"); clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco1_clk", NULL); clk_register_clkdev(clk1, "pll1_clk", NULL); clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); clk_register_clkdev(clk, "vco2_clk", NULL); clk_register_clkdev(clk1, "pll2_clk", NULL); /* clock derived from pll1 clk */ clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", CLK_SET_RATE_PARENT, 1, 1); clk_register_clkdev(clk, "cpu_clk", NULL); clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, HCLK_RATIO_MASK, 0, &_lock); clk_register_clkdev(clk, "ahb_clk", NULL); clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "uart_syn_clk", NULL); clk_register_clkdev(clk1, "uart_syn_gclk", NULL); clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "uart0_mclk", NULL); clk = clk_register_gate(NULL, "uart0", "uart0_mclk", CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, UART_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0000000.serial"); clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "firda_syn_clk", NULL); clk_register_clkdev(clk1, "firda_syn_gclk", NULL); clk = clk_register_mux(NULL, "firda_mclk", firda_parents, ARRAY_SIZE(firda_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "firda_mclk", NULL); clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "firda"); /* gpt clocks */ clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, ARRAY_SIZE(gpt0_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt0"); clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents, ARRAY_SIZE(gpt1_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt1_mclk", NULL); clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt1"); clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gpt2_mclk", NULL); clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "gpt2"); /* general synths clocks */ clk = clk_register_aux("gen0_syn_clk", "gen0_syn_gclk", "pll1_clk", 0, GEN0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "gen0_syn_clk", NULL); clk_register_clkdev(clk1, "gen0_syn_gclk", NULL); clk = clk_register_aux("gen1_syn_clk", "gen1_syn_gclk", "pll1_clk", 0, GEN1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "gen1_syn_clk", NULL); clk_register_clkdev(clk1, "gen1_syn_gclk", NULL); clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents, ARRAY_SIZE(gen2_3_parents), CLK_SET_RATE_NO_REPARENT, CORE_CLK_CFG, GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "gen2_3_par_clk", NULL); clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk", "gen2_3_par_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "gen2_syn_clk", NULL); clk_register_clkdev(clk1, "gen2_syn_gclk", NULL); clk = clk_register_aux("gen3_syn_clk", "gen3_syn_gclk", "gen2_3_par_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); clk_register_clkdev(clk, "gen3_syn_clk", NULL); clk_register_clkdev(clk1, "gen3_syn_gclk", NULL); /* clock derived from pll3 clk */ clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB, USBH_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e1800000.ehci"); clk_register_clkdev(clk, NULL, "e1900000.ohci"); clk_register_clkdev(clk, NULL, "e2100000.ohci"); clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1, 1); clk_register_clkdev(clk, "usbh.0_clk", NULL); clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1, 1); clk_register_clkdev(clk, "usbh.1_clk", NULL); clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e1100000.usbd"); /* clock derived from ahb clk */ clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, 1); clk_register_clkdev(clk, "ahbmult2_clk", NULL); clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT, PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock); clk_register_clkdev(clk, "ddr_clk", NULL); clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT, PCLK_RATIO_MASK, 0, &_lock); clk_register_clkdev(clk, "apb_clk", NULL); clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG, AMEM_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "amem_clk", NULL); clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB, C3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "c3_clk"); clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, DMA_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "fc400000.dma"); clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB, GMAC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "e0800000.eth"); clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB, I2C_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0180000.i2c"); clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB, JPEG_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "jpeg"); clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB, SMI_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "fc000000.flash"); /* clock derived from apb clk */ clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, ADC_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0080000.adc"); clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB, GPIO_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "fc980000.gpio"); clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, SSP_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, NULL, "d0100000.spi"); /* RAS clk enable */ clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB, RAS_AHB_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_ahb_clk", NULL); clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB, RAS_APB_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_apb_clk", NULL); ras_apb_clk = clk; clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0, RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_32k_clk", NULL); clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0, RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_24m_clk", NULL); clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0, RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_pll1_clk", NULL); clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_pll2_clk", NULL); clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_pll3_clk", NULL); clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk", CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_syn0_gclk", NULL); clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk", CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_syn1_gclk", NULL); clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk", CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_syn2_gclk", NULL); clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk", CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0, &_lock); clk_register_clkdev(clk, "ras_syn3_gclk", NULL); if (of_machine_is_compatible("st,spear300")) spear300_clk_init(); else if (of_machine_is_compatible("st,spear310")) spear310_clk_init(); else if (of_machine_is_compatible("st,spear320")) spear320_clk_init(soc_config_base, ras_apb_clk); }
linux-master
drivers/clk/spear/spear3xx_clock.c
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 ST Microelectronics * Viresh Kumar <[email protected]> * * Fractional Synthesizer clock implementation */ #define pr_fmt(fmt) "clk-frac-synth: " fmt #include <linux/clk-provider.h> #include <linux/slab.h> #include <linux/io.h> #include <linux/err.h> #include "clk.h" #define DIV_FACTOR_MASK 0x1FFFF /* * DOC: Fractional Synthesizer clock * * Fout from synthesizer can be given from below equation: * * Fout= Fin/2*div (division factor) * div is 17 bits:- * 0-13 (fractional part) * 14-16 (integer part) * div is (16-14 bits).(13-0 bits) (in binary) * * Fout = Fin/(2 * div) * Fout = ((Fin / 10000)/(2 * div)) * 10000 * Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000 * Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000 * * div << 14 simply 17 bit value written at register. * Max error due to scaling down by 10000 is 10 KHz */ #define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw) static unsigned long frac_calc_rate(struct clk_hw *hw, unsigned long prate, int index) { struct clk_frac *frac = to_clk_frac(hw); struct frac_rate_tbl *rtbl = frac->rtbl; prate /= 10000; prate <<= 14; prate /= (2 * rtbl[index].div); prate *= 10000; return prate; } static long clk_frac_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) { struct clk_frac *frac = to_clk_frac(hw); int unused; return clk_round_rate_index(hw, drate, *prate, frac_calc_rate, frac->rtbl_cnt, &unused); } static unsigned long clk_frac_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_frac *frac = to_clk_frac(hw); unsigned long flags = 0; unsigned int div = 1, val; if (frac->lock) spin_lock_irqsave(frac->lock, flags); val = readl_relaxed(frac->reg); if (frac->lock) spin_unlock_irqrestore(frac->lock, flags); div = val & DIV_FACTOR_MASK; if (!div) return 0; parent_rate = parent_rate / 10000; parent_rate = (parent_rate << 14) / (2 * div); return parent_rate * 10000; } /* Configures new clock rate of frac */ static int clk_frac_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { struct clk_frac *frac = to_clk_frac(hw); struct frac_rate_tbl *rtbl = frac->rtbl; unsigned long flags = 0, val; int i; clk_round_rate_index(hw, drate, prate, frac_calc_rate, frac->rtbl_cnt, &i); if (frac->lock) spin_lock_irqsave(frac->lock, flags); val = readl_relaxed(frac->reg) & ~DIV_FACTOR_MASK; val |= rtbl[i].div & DIV_FACTOR_MASK; writel_relaxed(val, frac->reg); if (frac->lock) spin_unlock_irqrestore(frac->lock, flags); return 0; } static const struct clk_ops clk_frac_ops = { .recalc_rate = clk_frac_recalc_rate, .round_rate = clk_frac_round_rate, .set_rate = clk_frac_set_rate, }; struct clk *clk_register_frac(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock) { struct clk_init_data init; struct clk_frac *frac; struct clk *clk; if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { pr_err("Invalid arguments passed\n"); return ERR_PTR(-EINVAL); } frac = kzalloc(sizeof(*frac), GFP_KERNEL); if (!frac) return ERR_PTR(-ENOMEM); /* struct clk_frac assignments */ frac->reg = reg; frac->rtbl = rtbl; frac->rtbl_cnt = rtbl_cnt; frac->lock = lock; frac->hw.init = &init; init.name = name; init.ops = &clk_frac_ops; init.flags = flags; init.parent_names = &parent_name; init.num_parents = 1; clk = clk_register(NULL, &frac->hw); if (!IS_ERR_OR_NULL(clk)) return clk; pr_err("clk register failed\n"); kfree(frac); return NULL; }
linux-master
drivers/clk/spear/clk-frac-synth.c
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 ST Microelectronics * Viresh Kumar <[email protected]> * * Auxiliary Synthesizer clock implementation */ #define pr_fmt(fmt) "clk-aux-synth: " fmt #include <linux/clk-provider.h> #include <linux/slab.h> #include <linux/io.h> #include <linux/err.h> #include "clk.h" /* * DOC: Auxiliary Synthesizer clock * * Aux synth gives rate for different values of eq, x and y * * Fout from synthesizer can be given from two equations: * Fout1 = (Fin * X/Y)/2 EQ1 * Fout2 = Fin * X/Y EQ2 */ #define to_clk_aux(_hw) container_of(_hw, struct clk_aux, hw) static const struct aux_clk_masks default_aux_masks = { .eq_sel_mask = AUX_EQ_SEL_MASK, .eq_sel_shift = AUX_EQ_SEL_SHIFT, .eq1_mask = AUX_EQ1_SEL, .eq2_mask = AUX_EQ2_SEL, .xscale_sel_mask = AUX_XSCALE_MASK, .xscale_sel_shift = AUX_XSCALE_SHIFT, .yscale_sel_mask = AUX_YSCALE_MASK, .yscale_sel_shift = AUX_YSCALE_SHIFT, .enable_bit = AUX_SYNT_ENB, }; static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate, int index) { struct clk_aux *aux = to_clk_aux(hw); struct aux_rate_tbl *rtbl = aux->rtbl; u8 eq = rtbl[index].eq ? 1 : 2; return (((prate / 10000) * rtbl[index].xscale) / (rtbl[index].yscale * eq)) * 10000; } static long clk_aux_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) { struct clk_aux *aux = to_clk_aux(hw); int unused; return clk_round_rate_index(hw, drate, *prate, aux_calc_rate, aux->rtbl_cnt, &unused); } static unsigned long clk_aux_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_aux *aux = to_clk_aux(hw); unsigned int num = 1, den = 1, val, eqn; unsigned long flags = 0; if (aux->lock) spin_lock_irqsave(aux->lock, flags); val = readl_relaxed(aux->reg); if (aux->lock) spin_unlock_irqrestore(aux->lock, flags); eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask; if (eqn == aux->masks->eq1_mask) den = 2; /* calculate numerator */ num = (val >> aux->masks->xscale_sel_shift) & aux->masks->xscale_sel_mask; /* calculate denominator */ den *= (val >> aux->masks->yscale_sel_shift) & aux->masks->yscale_sel_mask; if (!den) return 0; return (((parent_rate / 10000) * num) / den) * 10000; } /* Configures new clock rate of aux */ static int clk_aux_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { struct clk_aux *aux = to_clk_aux(hw); struct aux_rate_tbl *rtbl = aux->rtbl; unsigned long val, flags = 0; int i; clk_round_rate_index(hw, drate, prate, aux_calc_rate, aux->rtbl_cnt, &i); if (aux->lock) spin_lock_irqsave(aux->lock, flags); val = readl_relaxed(aux->reg) & ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift); val |= (rtbl[i].eq & aux->masks->eq_sel_mask) << aux->masks->eq_sel_shift; val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift); val |= (rtbl[i].xscale & aux->masks->xscale_sel_mask) << aux->masks->xscale_sel_shift; val &= ~(aux->masks->yscale_sel_mask << aux->masks->yscale_sel_shift); val |= (rtbl[i].yscale & aux->masks->yscale_sel_mask) << aux->masks->yscale_sel_shift; writel_relaxed(val, aux->reg); if (aux->lock) spin_unlock_irqrestore(aux->lock, flags); return 0; } static const struct clk_ops clk_aux_ops = { .recalc_rate = clk_aux_recalc_rate, .round_rate = clk_aux_round_rate, .set_rate = clk_aux_set_rate, }; struct clk *clk_register_aux(const char *aux_name, const char *gate_name, const char *parent_name, unsigned long flags, void __iomem *reg, const struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk) { struct clk_aux *aux; struct clk_init_data init; struct clk *clk; if (!aux_name || !parent_name || !reg || !rtbl || !rtbl_cnt) { pr_err("Invalid arguments passed"); return ERR_PTR(-EINVAL); } aux = kzalloc(sizeof(*aux), GFP_KERNEL); if (!aux) return ERR_PTR(-ENOMEM); /* struct clk_aux assignments */ if (!masks) aux->masks = &default_aux_masks; else aux->masks = masks; aux->reg = reg; aux->rtbl = rtbl; aux->rtbl_cnt = rtbl_cnt; aux->lock = lock; aux->hw.init = &init; init.name = aux_name; init.ops = &clk_aux_ops; init.flags = flags; init.parent_names = &parent_name; init.num_parents = 1; clk = clk_register(NULL, &aux->hw); if (IS_ERR_OR_NULL(clk)) goto free_aux; if (gate_name) { struct clk *tgate_clk; tgate_clk = clk_register_gate(NULL, gate_name, aux_name, CLK_SET_RATE_PARENT, reg, aux->masks->enable_bit, 0, lock); if (IS_ERR_OR_NULL(tgate_clk)) goto free_aux; if (gate_clk) *gate_clk = tgate_clk; } return clk; free_aux: kfree(aux); pr_err("clk register failed\n"); return NULL; }
linux-master
drivers/clk/spear/clk-aux-synth.c
// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 ST Microelectronics * Viresh Kumar <[email protected]> * * General Purpose Timer Synthesizer clock implementation */ #define pr_fmt(fmt) "clk-gpt-synth: " fmt #include <linux/clk-provider.h> #include <linux/slab.h> #include <linux/io.h> #include <linux/err.h> #include "clk.h" #define GPT_MSCALE_MASK 0xFFF #define GPT_NSCALE_SHIFT 12 #define GPT_NSCALE_MASK 0xF /* * DOC: General Purpose Timer Synthesizer clock * * Calculates gpt synth clk rate for different values of mscale and nscale * * Fout= Fin/((2 ^ (N+1)) * (M+1)) */ #define to_clk_gpt(_hw) container_of(_hw, struct clk_gpt, hw) static unsigned long gpt_calc_rate(struct clk_hw *hw, unsigned long prate, int index) { struct clk_gpt *gpt = to_clk_gpt(hw); struct gpt_rate_tbl *rtbl = gpt->rtbl; prate /= ((1 << (rtbl[index].nscale + 1)) * (rtbl[index].mscale + 1)); return prate; } static long clk_gpt_round_rate(struct clk_hw *hw, unsigned long drate, unsigned long *prate) { struct clk_gpt *gpt = to_clk_gpt(hw); int unused; return clk_round_rate_index(hw, drate, *prate, gpt_calc_rate, gpt->rtbl_cnt, &unused); } static unsigned long clk_gpt_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_gpt *gpt = to_clk_gpt(hw); unsigned long flags = 0; unsigned int div = 1, val; if (gpt->lock) spin_lock_irqsave(gpt->lock, flags); val = readl_relaxed(gpt->reg); if (gpt->lock) spin_unlock_irqrestore(gpt->lock, flags); div += val & GPT_MSCALE_MASK; div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1); if (!div) return 0; return parent_rate / div; } /* Configures new clock rate of gpt */ static int clk_gpt_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { struct clk_gpt *gpt = to_clk_gpt(hw); struct gpt_rate_tbl *rtbl = gpt->rtbl; unsigned long flags = 0, val; int i; clk_round_rate_index(hw, drate, prate, gpt_calc_rate, gpt->rtbl_cnt, &i); if (gpt->lock) spin_lock_irqsave(gpt->lock, flags); val = readl(gpt->reg) & ~GPT_MSCALE_MASK; val &= ~(GPT_NSCALE_MASK << GPT_NSCALE_SHIFT); val |= rtbl[i].mscale & GPT_MSCALE_MASK; val |= (rtbl[i].nscale & GPT_NSCALE_MASK) << GPT_NSCALE_SHIFT; writel_relaxed(val, gpt->reg); if (gpt->lock) spin_unlock_irqrestore(gpt->lock, flags); return 0; } static const struct clk_ops clk_gpt_ops = { .recalc_rate = clk_gpt_recalc_rate, .round_rate = clk_gpt_round_rate, .set_rate = clk_gpt_set_rate, }; struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock) { struct clk_init_data init; struct clk_gpt *gpt; struct clk *clk; if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { pr_err("Invalid arguments passed\n"); return ERR_PTR(-EINVAL); } gpt = kzalloc(sizeof(*gpt), GFP_KERNEL); if (!gpt) return ERR_PTR(-ENOMEM); /* struct clk_gpt assignments */ gpt->reg = reg; gpt->rtbl = rtbl; gpt->rtbl_cnt = rtbl_cnt; gpt->lock = lock; gpt->hw.init = &init; init.name = name; init.ops = &clk_gpt_ops; init.flags = flags; init.parent_names = &parent_name; init.num_parents = 1; clk = clk_register(NULL, &gpt->hw); if (!IS_ERR_OR_NULL(clk)) return clk; pr_err("clk register failed\n"); kfree(gpt); return NULL; }
linux-master
drivers/clk/spear/clk-gpt-synth.c
// SPDX-License-Identifier: GPL-2.0 /* * PLL clock descriptions for TI DA830/OMAP-L137/AM17XX * * Copyright (C) 2018 David Lechner <[email protected]> */ #include <linux/clkdev.h> #include <linux/clk/davinci.h> #include <linux/bitops.h> #include <linux/init.h> #include <linux/types.h> #include "pll.h" static const struct davinci_pll_clk_info da830_pll_info = { .name = "pll0", .pllm_mask = GENMASK(4, 0), .pllm_min = 4, .pllm_max = 32, .pllout_min_rate = 300000000, .pllout_max_rate = 600000000, .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV, }; /* * NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio", * meaning that we could change the divider as long as we keep the correct * ratio between all of the clocks, but we don't support that because there is * currently not a need for it. */ SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV); SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0); SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV); SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0); SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV); SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0); int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) { struct clk *clk; davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, cfgchip); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base); clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0"); clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc1"); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base); clk_register_clkdev(clk, "pll0_sysclk3", "da830-psc0"); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base); clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc0"); clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc1"); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk5, base); clk_register_clkdev(clk, "pll0_sysclk5", "da830-psc1"); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base); clk_register_clkdev(clk, "pll0_sysclk6", "da830-psc0"); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk7, base); clk = davinci_pll_auxclk_register(dev, "pll0_auxclk", base); clk_register_clkdev(clk, NULL, "i2c_davinci.1"); clk_register_clkdev(clk, "timer0", NULL); clk_register_clkdev(clk, NULL, "davinci-wdt"); return 0; }
linux-master
drivers/clk/davinci/pll-da830.c
// SPDX-License-Identifier: GPL-2.0 /* * PSC clock descriptions for TI DA850/OMAP-L138/AM18XX * * Copyright (C) 2018 David Lechner <[email protected]> */ #include <linux/clk-provider.h> #include <linux/reset-controller.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/types.h> #include "psc.h" LPSC_CLKDEV1(emifa_clkdev, NULL, "ti-aemif"); LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0"); LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "da830-mmc.0"); LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0"); /* REVISIT: used dev_id instead of con_id */ LPSC_CLKDEV1(arm_clkdev, "arm", NULL); LPSC_CLKDEV1(dsp_clkdev, NULL, "davinci-rproc.0"); static const struct davinci_lpsc_clk_info da850_psc0_info[] = { LPSC(0, 0, tpcc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(1, 0, tptc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(2, 0, tptc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(3, 0, emifa, async1, emifa_clkdev, 0), LPSC(4, 0, spi0, pll0_sysclk2, spi0_clkdev, 0), LPSC(5, 0, mmcsd0, pll0_sysclk2, mmcsd0_clkdev, 0), LPSC(6, 0, aintc, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED), LPSC(7, 0, arm_rom, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(9, 0, uart0, pll0_sysclk2, uart0_clkdev, 0), LPSC(13, 0, pruss, pll0_sysclk2, NULL, 0), LPSC(14, 0, arm, pll0_sysclk6, arm_clkdev, LPSC_ALWAYS_ENABLED | LPSC_SET_RATE_PARENT), LPSC(15, 1, dsp, pll0_sysclk1, dsp_clkdev, LPSC_FORCE | LPSC_LOCAL_RESET), { } }; LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks", NULL, "musb-da8xx", NULL, "cppi41-dmaengine"); LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx"); /* REVISIT: gpio-davinci.c should be modified to drop con_id */ LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL); LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1", "fck", "davinci_mdio.0"); LPSC_CLKDEV1(mcasp0_clkdev, NULL, "davinci-mcasp.0"); LPSC_CLKDEV1(sata_clkdev, "fck", "ahci_da850"); LPSC_CLKDEV1(vpif_clkdev, NULL, "vpif"); LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1"); LPSC_CLKDEV1(i2c1_clkdev, NULL, "i2c_davinci.2"); LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1"); LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2"); LPSC_CLKDEV1(mcbsp0_clkdev, NULL, "davinci-mcbsp.0"); LPSC_CLKDEV1(mcbsp1_clkdev, NULL, "davinci-mcbsp.1"); LPSC_CLKDEV1(lcdc_clkdev, "fck", "da8xx_lcdc.0"); LPSC_CLKDEV3(ehrpwm_clkdev, "fck", "ehrpwm.0", "fck", "ehrpwm.1", NULL, "da830-tbclksync"); LPSC_CLKDEV1(mmcsd1_clkdev, NULL, "da830-mmc.1"); LPSC_CLKDEV3(ecap_clkdev, "fck", "ecap.0", "fck", "ecap.1", "fck", "ecap.2"); static struct reset_control_lookup da850_psc0_reset_lookup_table[] = { RESET_LOOKUP("da850-psc0", 15, "davinci-rproc.0", NULL), }; static int da850_psc0_init(struct device *dev, void __iomem *base) { reset_controller_add_lookup(da850_psc0_reset_lookup_table, ARRAY_SIZE(da850_psc0_reset_lookup_table)); return davinci_psc_register_clocks(dev, da850_psc0_info, 16, base); } static int of_da850_psc0_init(struct device *dev, void __iomem *base) { return of_davinci_psc_clk_init(dev, da850_psc0_info, 16, base); } static struct clk_bulk_data da850_psc0_parent_clks[] = { { .id = "pll0_sysclk1" }, { .id = "pll0_sysclk2" }, { .id = "pll0_sysclk4" }, { .id = "pll0_sysclk6" }, { .id = "async1" }, }; const struct davinci_psc_init_data da850_psc0_init_data = { .parent_clks = da850_psc0_parent_clks, .num_parent_clks = ARRAY_SIZE(da850_psc0_parent_clks), .psc_init = &da850_psc0_init, }; const struct davinci_psc_init_data of_da850_psc0_init_data = { .parent_clks = da850_psc0_parent_clks, .num_parent_clks = ARRAY_SIZE(da850_psc0_parent_clks), .psc_init = &of_da850_psc0_init, }; static const struct davinci_lpsc_clk_info da850_psc1_info[] = { LPSC(0, 0, tpcc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(1, 0, usb0, pll0_sysclk2, usb0_clkdev, 0), LPSC(2, 0, usb1, pll0_sysclk4, usb1_clkdev, 0), LPSC(3, 0, gpio, pll0_sysclk4, gpio_clkdev, 0), LPSC(5, 0, emac, pll0_sysclk4, emac_clkdev, 0), LPSC(6, 0, ddr, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(7, 0, mcasp0, async3, mcasp0_clkdev, 0), LPSC(8, 0, sata, pll0_sysclk2, sata_clkdev, LPSC_FORCE), LPSC(9, 0, vpif, pll0_sysclk2, vpif_clkdev, 0), LPSC(10, 0, spi1, async3, spi1_clkdev, 0), LPSC(11, 0, i2c1, pll0_sysclk4, i2c1_clkdev, 0), LPSC(12, 0, uart1, async3, uart1_clkdev, 0), LPSC(13, 0, uart2, async3, uart2_clkdev, 0), LPSC(14, 0, mcbsp0, async3, mcbsp0_clkdev, 0), LPSC(15, 0, mcbsp1, async3, mcbsp1_clkdev, 0), LPSC(16, 0, lcdc, pll0_sysclk2, lcdc_clkdev, 0), LPSC(17, 0, ehrpwm, async3, ehrpwm_clkdev, 0), LPSC(18, 0, mmcsd1, pll0_sysclk2, mmcsd1_clkdev, 0), LPSC(20, 0, ecap, async3, ecap_clkdev, 0), LPSC(21, 0, tptc2, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), { } }; static int da850_psc1_init(struct device *dev, void __iomem *base) { return davinci_psc_register_clocks(dev, da850_psc1_info, 32, base); } static int of_da850_psc1_init(struct device *dev, void __iomem *base) { return of_davinci_psc_clk_init(dev, da850_psc1_info, 32, base); } static struct clk_bulk_data da850_psc1_parent_clks[] = { { .id = "pll0_sysclk2" }, { .id = "pll0_sysclk4" }, { .id = "async3" }, }; const struct davinci_psc_init_data da850_psc1_init_data = { .parent_clks = da850_psc1_parent_clks, .num_parent_clks = ARRAY_SIZE(da850_psc1_parent_clks), .psc_init = &da850_psc1_init, }; const struct davinci_psc_init_data of_da850_psc1_init_data = { .parent_clks = da850_psc1_parent_clks, .num_parent_clks = ARRAY_SIZE(da850_psc1_parent_clks), .psc_init = &of_da850_psc1_init, };
linux-master
drivers/clk/davinci/psc-da850.c
// SPDX-License-Identifier: GPL-2.0 /* * PSC clock descriptions for TI DA830/OMAP-L137/AM17XX * * Copyright (C) 2018 David Lechner <[email protected]> */ #include <linux/clk-provider.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/types.h> #include "psc.h" LPSC_CLKDEV1(aemif_clkdev, NULL, "ti-aemif"); LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0"); LPSC_CLKDEV1(mmcsd_clkdev, NULL, "da830-mmc.0"); LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0"); static const struct davinci_lpsc_clk_info da830_psc0_info[] = { LPSC(0, 0, tpcc, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(1, 0, tptc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(2, 0, tptc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(3, 0, aemif, pll0_sysclk3, aemif_clkdev, LPSC_ALWAYS_ENABLED), LPSC(4, 0, spi0, pll0_sysclk2, spi0_clkdev, 0), LPSC(5, 0, mmcsd, pll0_sysclk2, mmcsd_clkdev, 0), LPSC(6, 0, aintc, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED), LPSC(7, 0, arm_rom, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(8, 0, secu_mgr, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED), LPSC(9, 0, uart0, pll0_sysclk2, uart0_clkdev, 0), LPSC(10, 0, scr0_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(11, 0, scr1_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(12, 0, scr2_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(13, 0, pruss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), LPSC(14, 0, arm, pll0_sysclk6, NULL, LPSC_ALWAYS_ENABLED), { } }; static int da830_psc0_init(struct device *dev, void __iomem *base) { return davinci_psc_register_clocks(dev, da830_psc0_info, 16, base); } static struct clk_bulk_data da830_psc0_parent_clks[] = { { .id = "pll0_sysclk2" }, { .id = "pll0_sysclk3" }, { .id = "pll0_sysclk4" }, { .id = "pll0_sysclk6" }, }; const struct davinci_psc_init_data da830_psc0_init_data = { .parent_clks = da830_psc0_parent_clks, .num_parent_clks = ARRAY_SIZE(da830_psc0_parent_clks), .psc_init = &da830_psc0_init, }; LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks", NULL, "musb-da8xx", NULL, "cppi41-dmaengine"); LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx"); /* REVISIT: gpio-davinci.c should be modified to drop con_id */ LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL); LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1", "fck", "davinci_mdio.0"); LPSC_CLKDEV1(mcasp0_clkdev, NULL, "davinci-mcasp.0"); LPSC_CLKDEV1(mcasp1_clkdev, NULL, "davinci-mcasp.1"); LPSC_CLKDEV1(mcasp2_clkdev, NULL, "davinci-mcasp.2"); LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1"); LPSC_CLKDEV1(i2c1_clkdev, NULL, "i2c_davinci.2"); LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1"); LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2"); LPSC_CLKDEV1(lcdc_clkdev, "fck", "da8xx_lcdc.0"); LPSC_CLKDEV2(pwm_clkdev, "fck", "ehrpwm.0", "fck", "ehrpwm.1"); LPSC_CLKDEV3(ecap_clkdev, "fck", "ecap.0", "fck", "ecap.1", "fck", "ecap.2"); LPSC_CLKDEV2(eqep_clkdev, NULL, "eqep.0", NULL, "eqep.1"); static const struct davinci_lpsc_clk_info da830_psc1_info[] = { LPSC(1, 0, usb0, pll0_sysclk2, usb0_clkdev, 0), LPSC(2, 0, usb1, pll0_sysclk4, usb1_clkdev, 0), LPSC(3, 0, gpio, pll0_sysclk4, gpio_clkdev, 0), LPSC(5, 0, emac, pll0_sysclk4, emac_clkdev, 0), LPSC(6, 0, emif3, pll0_sysclk5, NULL, LPSC_ALWAYS_ENABLED), LPSC(7, 0, mcasp0, pll0_sysclk2, mcasp0_clkdev, 0), LPSC(8, 0, mcasp1, pll0_sysclk2, mcasp1_clkdev, 0), LPSC(9, 0, mcasp2, pll0_sysclk2, mcasp2_clkdev, 0), LPSC(10, 0, spi1, pll0_sysclk2, spi1_clkdev, 0), LPSC(11, 0, i2c1, pll0_sysclk4, i2c1_clkdev, 0), LPSC(12, 0, uart1, pll0_sysclk2, uart1_clkdev, 0), LPSC(13, 0, uart2, pll0_sysclk2, uart2_clkdev, 0), LPSC(16, 0, lcdc, pll0_sysclk2, lcdc_clkdev, 0), LPSC(17, 0, pwm, pll0_sysclk2, pwm_clkdev, 0), LPSC(20, 0, ecap, pll0_sysclk2, ecap_clkdev, 0), LPSC(21, 0, eqep, pll0_sysclk2, eqep_clkdev, 0), { } }; static int da830_psc1_init(struct device *dev, void __iomem *base) { return davinci_psc_register_clocks(dev, da830_psc1_info, 32, base); } static struct clk_bulk_data da830_psc1_parent_clks[] = { { .id = "pll0_sysclk2" }, { .id = "pll0_sysclk4" }, { .id = "pll0_sysclk5" }, }; const struct davinci_psc_init_data da830_psc1_init_data = { .parent_clks = da830_psc1_parent_clks, .num_parent_clks = ARRAY_SIZE(da830_psc1_parent_clks), .psc_init = &da830_psc1_init, };
linux-master
drivers/clk/davinci/psc-da830.c
// SPDX-License-Identifier: GPL-2.0 /* * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP * * Copyright (C) 2018 David Lechner <[email protected]> */ #include <linux/clk-provider.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/init.h> #include <linux/mfd/da8xx-cfgchip.h> #include <linux/mfd/syscon.h> #include <linux/of_device.h> #include <linux/of.h> #include <linux/platform_data/clk-da8xx-cfgchip.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/slab.h> /* --- Gate clocks --- */ #define DA8XX_GATE_CLOCK_IS_DIV4P5 BIT(1) struct da8xx_cfgchip_gate_clk_info { const char *name; u32 cfgchip; u32 bit; u32 flags; }; struct da8xx_cfgchip_gate_clk { struct clk_hw hw; struct regmap *regmap; u32 reg; u32 mask; }; #define to_da8xx_cfgchip_gate_clk(_hw) \ container_of((_hw), struct da8xx_cfgchip_gate_clk, hw) static int da8xx_cfgchip_gate_clk_enable(struct clk_hw *hw) { struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw); return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask); } static void da8xx_cfgchip_gate_clk_disable(struct clk_hw *hw) { struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw); regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0); } static int da8xx_cfgchip_gate_clk_is_enabled(struct clk_hw *hw) { struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw); unsigned int val; regmap_read(clk->regmap, clk->reg, &val); return !!(val & clk->mask); } static unsigned long da8xx_cfgchip_div4p5_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { /* this clock divides by 4.5 */ return parent_rate * 2 / 9; } static const struct clk_ops da8xx_cfgchip_gate_clk_ops = { .enable = da8xx_cfgchip_gate_clk_enable, .disable = da8xx_cfgchip_gate_clk_disable, .is_enabled = da8xx_cfgchip_gate_clk_is_enabled, }; static const struct clk_ops da8xx_cfgchip_div4p5_clk_ops = { .enable = da8xx_cfgchip_gate_clk_enable, .disable = da8xx_cfgchip_gate_clk_disable, .is_enabled = da8xx_cfgchip_gate_clk_is_enabled, .recalc_rate = da8xx_cfgchip_div4p5_recalc_rate, }; static struct da8xx_cfgchip_gate_clk * __init da8xx_cfgchip_gate_clk_register(struct device *dev, const struct da8xx_cfgchip_gate_clk_info *info, struct regmap *regmap) { struct clk *parent; const char *parent_name; struct da8xx_cfgchip_gate_clk *gate; struct clk_init_data init; int ret; parent = devm_clk_get(dev, NULL); if (IS_ERR(parent)) return ERR_CAST(parent); parent_name = __clk_get_name(parent); gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); if (!gate) return ERR_PTR(-ENOMEM); init.name = info->name; if (info->flags & DA8XX_GATE_CLOCK_IS_DIV4P5) init.ops = &da8xx_cfgchip_div4p5_clk_ops; else init.ops = &da8xx_cfgchip_gate_clk_ops; init.parent_names = &parent_name; init.num_parents = 1; init.flags = 0; gate->hw.init = &init; gate->regmap = regmap; gate->reg = info->cfgchip; gate->mask = info->bit; ret = devm_clk_hw_register(dev, &gate->hw); if (ret < 0) return ERR_PTR(ret); return gate; } static const struct da8xx_cfgchip_gate_clk_info da8xx_tbclksync_info __initconst = { .name = "ehrpwm_tbclk", .cfgchip = CFGCHIP(1), .bit = CFGCHIP1_TBCLKSYNC, }; static int __init da8xx_cfgchip_register_tbclk(struct device *dev, struct regmap *regmap) { struct da8xx_cfgchip_gate_clk *gate; gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_tbclksync_info, regmap); if (IS_ERR(gate)) return PTR_ERR(gate); clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.0"); clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.1"); return 0; } static const struct da8xx_cfgchip_gate_clk_info da8xx_div4p5ena_info __initconst = { .name = "div4.5", .cfgchip = CFGCHIP(3), .bit = CFGCHIP3_DIV45PENA, .flags = DA8XX_GATE_CLOCK_IS_DIV4P5, }; static int __init da8xx_cfgchip_register_div4p5(struct device *dev, struct regmap *regmap) { struct da8xx_cfgchip_gate_clk *gate; gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_div4p5ena_info, regmap); return PTR_ERR_OR_ZERO(gate); } static int __init of_da8xx_cfgchip_gate_clk_init(struct device *dev, const struct da8xx_cfgchip_gate_clk_info *info, struct regmap *regmap) { struct da8xx_cfgchip_gate_clk *gate; gate = da8xx_cfgchip_gate_clk_register(dev, info, regmap); if (IS_ERR(gate)) return PTR_ERR(gate); return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, gate); } static int __init of_da8xx_tbclksync_init(struct device *dev, struct regmap *regmap) { return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_tbclksync_info, regmap); } static int __init of_da8xx_div4p5ena_init(struct device *dev, struct regmap *regmap) { return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_div4p5ena_info, regmap); } /* --- MUX clocks --- */ struct da8xx_cfgchip_mux_clk_info { const char *name; const char *parent0; const char *parent1; u32 cfgchip; u32 bit; }; struct da8xx_cfgchip_mux_clk { struct clk_hw hw; struct regmap *regmap; u32 reg; u32 mask; }; #define to_da8xx_cfgchip_mux_clk(_hw) \ container_of((_hw), struct da8xx_cfgchip_mux_clk, hw) static int da8xx_cfgchip_mux_clk_set_parent(struct clk_hw *hw, u8 index) { struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw); unsigned int val = index ? clk->mask : 0; return regmap_write_bits(clk->regmap, clk->reg, clk->mask, val); } static u8 da8xx_cfgchip_mux_clk_get_parent(struct clk_hw *hw) { struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw); unsigned int val; regmap_read(clk->regmap, clk->reg, &val); return (val & clk->mask) ? 1 : 0; } static const struct clk_ops da8xx_cfgchip_mux_clk_ops = { .determine_rate = clk_hw_determine_rate_no_reparent, .set_parent = da8xx_cfgchip_mux_clk_set_parent, .get_parent = da8xx_cfgchip_mux_clk_get_parent, }; static struct da8xx_cfgchip_mux_clk * __init da8xx_cfgchip_mux_clk_register(struct device *dev, const struct da8xx_cfgchip_mux_clk_info *info, struct regmap *regmap) { const char * const parent_names[] = { info->parent0, info->parent1 }; struct da8xx_cfgchip_mux_clk *mux; struct clk_init_data init; int ret; mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); if (!mux) return ERR_PTR(-ENOMEM); init.name = info->name; init.ops = &da8xx_cfgchip_mux_clk_ops; init.parent_names = parent_names; init.num_parents = 2; init.flags = 0; mux->hw.init = &init; mux->regmap = regmap; mux->reg = info->cfgchip; mux->mask = info->bit; ret = devm_clk_hw_register(dev, &mux->hw); if (ret < 0) return ERR_PTR(ret); return mux; } static const struct da8xx_cfgchip_mux_clk_info da850_async1_info __initconst = { .name = "async1", .parent0 = "pll0_sysclk3", .parent1 = "div4.5", .cfgchip = CFGCHIP(3), .bit = CFGCHIP3_EMA_CLKSRC, }; static int __init da8xx_cfgchip_register_async1(struct device *dev, struct regmap *regmap) { struct da8xx_cfgchip_mux_clk *mux; mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async1_info, regmap); if (IS_ERR(mux)) return PTR_ERR(mux); clk_hw_register_clkdev(&mux->hw, "async1", "da850-psc0"); return 0; } static const struct da8xx_cfgchip_mux_clk_info da850_async3_info __initconst = { .name = "async3", .parent0 = "pll0_sysclk2", .parent1 = "pll1_sysclk2", .cfgchip = CFGCHIP(3), .bit = CFGCHIP3_ASYNC3_CLKSRC, }; static int __init da850_cfgchip_register_async3(struct device *dev, struct regmap *regmap) { struct da8xx_cfgchip_mux_clk *mux; struct clk_hw *parent; mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async3_info, regmap); if (IS_ERR(mux)) return PTR_ERR(mux); clk_hw_register_clkdev(&mux->hw, "async3", "da850-psc1"); /* pll1_sysclk2 is not affected by CPU scaling, so use it for async3 */ parent = clk_hw_get_parent_by_index(&mux->hw, 1); if (parent) clk_set_parent(mux->hw.clk, parent->clk); else dev_warn(dev, "Failed to find async3 parent clock\n"); return 0; } static int __init of_da8xx_cfgchip_init_mux_clock(struct device *dev, const struct da8xx_cfgchip_mux_clk_info *info, struct regmap *regmap) { struct da8xx_cfgchip_mux_clk *mux; mux = da8xx_cfgchip_mux_clk_register(dev, info, regmap); if (IS_ERR(mux)) return PTR_ERR(mux); return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &mux->hw); } static int __init of_da850_async1_init(struct device *dev, struct regmap *regmap) { return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async1_info, regmap); } static int __init of_da850_async3_init(struct device *dev, struct regmap *regmap) { return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async3_info, regmap); } /* --- USB 2.0 PHY clock --- */ struct da8xx_usb0_clk48 { struct clk_hw hw; struct clk *fck; struct regmap *regmap; }; #define to_da8xx_usb0_clk48(_hw) \ container_of((_hw), struct da8xx_usb0_clk48, hw) static int da8xx_usb0_clk48_prepare(struct clk_hw *hw) { struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw); /* The USB 2.0 PSC clock is only needed temporarily during the USB 2.0 * PHY clock enable, but since clk_prepare() can't be called in an * atomic context (i.e. in clk_enable()), we have to prepare it here. */ return clk_prepare(usb0->fck); } static void da8xx_usb0_clk48_unprepare(struct clk_hw *hw) { struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw); clk_unprepare(usb0->fck); } static int da8xx_usb0_clk48_enable(struct clk_hw *hw) { struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw); unsigned int mask, val; int ret; /* Locking the USB 2.O PLL requires that the USB 2.O PSC is enabled * temporaily. It can be turned back off once the PLL is locked. */ clk_enable(usb0->fck); /* Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1 * PHY may use the USB 2.0 PLL clock without USB 2.0 OTG being used. */ mask = CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_PHY_PLLON; val = CFGCHIP2_PHY_PLLON; regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val); ret = regmap_read_poll_timeout(usb0->regmap, CFGCHIP(2), val, val & CFGCHIP2_PHYCLKGD, 0, 500000); clk_disable(usb0->fck); return ret; } static void da8xx_usb0_clk48_disable(struct clk_hw *hw) { struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw); unsigned int val; val = CFGCHIP2_PHYPWRDN; regmap_write_bits(usb0->regmap, CFGCHIP(2), val, val); } static int da8xx_usb0_clk48_is_enabled(struct clk_hw *hw) { struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw); unsigned int val; regmap_read(usb0->regmap, CFGCHIP(2), &val); return !!(val & CFGCHIP2_PHYCLKGD); } static unsigned long da8xx_usb0_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw); unsigned int mask, val; /* The parent clock rate must be one of the following */ mask = CFGCHIP2_REFFREQ_MASK; switch (parent_rate) { case 12000000: val = CFGCHIP2_REFFREQ_12MHZ; break; case 13000000: val = CFGCHIP2_REFFREQ_13MHZ; break; case 19200000: val = CFGCHIP2_REFFREQ_19_2MHZ; break; case 20000000: val = CFGCHIP2_REFFREQ_20MHZ; break; case 24000000: val = CFGCHIP2_REFFREQ_24MHZ; break; case 26000000: val = CFGCHIP2_REFFREQ_26MHZ; break; case 38400000: val = CFGCHIP2_REFFREQ_38_4MHZ; break; case 40000000: val = CFGCHIP2_REFFREQ_40MHZ; break; case 48000000: val = CFGCHIP2_REFFREQ_48MHZ; break; default: return 0; } regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val); /* USB 2.0 PLL always supplies 48MHz */ return 48000000; } static int da8xx_usb0_clk48_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { req->rate = 48000000; return 0; } static int da8xx_usb0_clk48_set_parent(struct clk_hw *hw, u8 index) { struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw); return regmap_write_bits(usb0->regmap, CFGCHIP(2), CFGCHIP2_USB2PHYCLKMUX, index ? CFGCHIP2_USB2PHYCLKMUX : 0); } static u8 da8xx_usb0_clk48_get_parent(struct clk_hw *hw) { struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw); unsigned int val; regmap_read(usb0->regmap, CFGCHIP(2), &val); return (val & CFGCHIP2_USB2PHYCLKMUX) ? 1 : 0; } static const struct clk_ops da8xx_usb0_clk48_ops = { .prepare = da8xx_usb0_clk48_prepare, .unprepare = da8xx_usb0_clk48_unprepare, .enable = da8xx_usb0_clk48_enable, .disable = da8xx_usb0_clk48_disable, .is_enabled = da8xx_usb0_clk48_is_enabled, .recalc_rate = da8xx_usb0_clk48_recalc_rate, .determine_rate = da8xx_usb0_clk48_determine_rate, .set_parent = da8xx_usb0_clk48_set_parent, .get_parent = da8xx_usb0_clk48_get_parent, }; static struct da8xx_usb0_clk48 * da8xx_cfgchip_register_usb0_clk48(struct device *dev, struct regmap *regmap) { const char * const parent_names[] = { "usb_refclkin", "pll0_auxclk" }; struct clk *fck_clk; struct da8xx_usb0_clk48 *usb0; struct clk_init_data init; int ret; fck_clk = devm_clk_get(dev, "fck"); if (IS_ERR(fck_clk)) { dev_err_probe(dev, PTR_ERR(fck_clk), "Missing fck clock\n"); return ERR_CAST(fck_clk); } usb0 = devm_kzalloc(dev, sizeof(*usb0), GFP_KERNEL); if (!usb0) return ERR_PTR(-ENOMEM); init.name = "usb0_clk48"; init.ops = &da8xx_usb0_clk48_ops; init.parent_names = parent_names; init.num_parents = 2; usb0->hw.init = &init; usb0->fck = fck_clk; usb0->regmap = regmap; ret = devm_clk_hw_register(dev, &usb0->hw); if (ret < 0) return ERR_PTR(ret); return usb0; } /* --- USB 1.1 PHY clock --- */ struct da8xx_usb1_clk48 { struct clk_hw hw; struct regmap *regmap; }; #define to_da8xx_usb1_clk48(_hw) \ container_of((_hw), struct da8xx_usb1_clk48, hw) static int da8xx_usb1_clk48_set_parent(struct clk_hw *hw, u8 index) { struct da8xx_usb1_clk48 *usb1 = to_da8xx_usb1_clk48(hw); return regmap_write_bits(usb1->regmap, CFGCHIP(2), CFGCHIP2_USB1PHYCLKMUX, index ? CFGCHIP2_USB1PHYCLKMUX : 0); } static u8 da8xx_usb1_clk48_get_parent(struct clk_hw *hw) { struct da8xx_usb1_clk48 *usb1 = to_da8xx_usb1_clk48(hw); unsigned int val; regmap_read(usb1->regmap, CFGCHIP(2), &val); return (val & CFGCHIP2_USB1PHYCLKMUX) ? 1 : 0; } static const struct clk_ops da8xx_usb1_clk48_ops = { .determine_rate = clk_hw_determine_rate_no_reparent, .set_parent = da8xx_usb1_clk48_set_parent, .get_parent = da8xx_usb1_clk48_get_parent, }; /** * da8xx_cfgchip_register_usb1_clk48 - Register a new USB 1.1 PHY clock * @dev: The device * @regmap: The CFGCHIP regmap */ static struct da8xx_usb1_clk48 * da8xx_cfgchip_register_usb1_clk48(struct device *dev, struct regmap *regmap) { const char * const parent_names[] = { "usb0_clk48", "usb_refclkin" }; struct da8xx_usb1_clk48 *usb1; struct clk_init_data init; int ret; usb1 = devm_kzalloc(dev, sizeof(*usb1), GFP_KERNEL); if (!usb1) return ERR_PTR(-ENOMEM); init.name = "usb1_clk48"; init.ops = &da8xx_usb1_clk48_ops; init.parent_names = parent_names; init.num_parents = 2; usb1->hw.init = &init; usb1->regmap = regmap; ret = devm_clk_hw_register(dev, &usb1->hw); if (ret < 0) return ERR_PTR(ret); return usb1; } static int da8xx_cfgchip_register_usb_phy_clk(struct device *dev, struct regmap *regmap) { struct da8xx_usb0_clk48 *usb0; struct da8xx_usb1_clk48 *usb1; struct clk_hw *parent; usb0 = da8xx_cfgchip_register_usb0_clk48(dev, regmap); if (IS_ERR(usb0)) return PTR_ERR(usb0); /* * All existing boards use pll0_auxclk as the parent and new boards * should use device tree, so hard-coding the value (1) here. */ parent = clk_hw_get_parent_by_index(&usb0->hw, 1); if (parent) clk_set_parent(usb0->hw.clk, parent->clk); else dev_warn(dev, "Failed to find usb0 parent clock\n"); usb1 = da8xx_cfgchip_register_usb1_clk48(dev, regmap); if (IS_ERR(usb1)) return PTR_ERR(usb1); /* * All existing boards use usb0_clk48 as the parent and new boards * should use device tree, so hard-coding the value (0) here. */ parent = clk_hw_get_parent_by_index(&usb1->hw, 0); if (parent) clk_set_parent(usb1->hw.clk, parent->clk); else dev_warn(dev, "Failed to find usb1 parent clock\n"); clk_hw_register_clkdev(&usb0->hw, "usb0_clk48", "da8xx-usb-phy"); clk_hw_register_clkdev(&usb1->hw, "usb1_clk48", "da8xx-usb-phy"); return 0; } static int of_da8xx_usb_phy_clk_init(struct device *dev, struct regmap *regmap) { struct clk_hw_onecell_data *clk_data; struct da8xx_usb0_clk48 *usb0; struct da8xx_usb1_clk48 *usb1; clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, 2), GFP_KERNEL); if (!clk_data) return -ENOMEM; clk_data->num = 2; usb0 = da8xx_cfgchip_register_usb0_clk48(dev, regmap); if (IS_ERR(usb0)) { if (PTR_ERR(usb0) == -EPROBE_DEFER) return -EPROBE_DEFER; dev_warn(dev, "Failed to register usb0_clk48 (%ld)\n", PTR_ERR(usb0)); clk_data->hws[0] = ERR_PTR(-ENOENT); } else { clk_data->hws[0] = &usb0->hw; } usb1 = da8xx_cfgchip_register_usb1_clk48(dev, regmap); if (IS_ERR(usb1)) { if (PTR_ERR(usb1) == -EPROBE_DEFER) return -EPROBE_DEFER; dev_warn(dev, "Failed to register usb1_clk48 (%ld)\n", PTR_ERR(usb1)); clk_data->hws[1] = ERR_PTR(-ENOENT); } else { clk_data->hws[1] = &usb1->hw; } return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); } /* --- platform device --- */ static const struct of_device_id da8xx_cfgchip_of_match[] = { { .compatible = "ti,da830-tbclksync", .data = of_da8xx_tbclksync_init, }, { .compatible = "ti,da830-div4p5ena", .data = of_da8xx_div4p5ena_init, }, { .compatible = "ti,da850-async1-clksrc", .data = of_da850_async1_init, }, { .compatible = "ti,da850-async3-clksrc", .data = of_da850_async3_init, }, { .compatible = "ti,da830-usb-phy-clocks", .data = of_da8xx_usb_phy_clk_init, }, { } }; static const struct platform_device_id da8xx_cfgchip_id_table[] = { { .name = "da830-tbclksync", .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_tbclk, }, { .name = "da830-div4p5ena", .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_div4p5, }, { .name = "da850-async1-clksrc", .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_async1, }, { .name = "da850-async3-clksrc", .driver_data = (kernel_ulong_t)da850_cfgchip_register_async3, }, { .name = "da830-usb-phy-clks", .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_usb_phy_clk, }, { } }; typedef int (*da8xx_cfgchip_init)(struct device *dev, struct regmap *regmap); static int da8xx_cfgchip_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct da8xx_cfgchip_clk_platform_data *pdata = dev->platform_data; const struct of_device_id *of_id; da8xx_cfgchip_init clk_init = NULL; struct regmap *regmap = NULL; of_id = of_match_device(da8xx_cfgchip_of_match, dev); if (of_id) { struct device_node *parent; clk_init = of_id->data; parent = of_get_parent(dev->of_node); regmap = syscon_node_to_regmap(parent); of_node_put(parent); } else if (pdev->id_entry && pdata) { clk_init = (void *)pdev->id_entry->driver_data; regmap = pdata->cfgchip; } if (!clk_init) { dev_err(dev, "unable to find driver data\n"); return -EINVAL; } if (IS_ERR_OR_NULL(regmap)) { dev_err(dev, "no regmap for CFGCHIP syscon\n"); return regmap ? PTR_ERR(regmap) : -ENOENT; } return clk_init(dev, regmap); } static struct platform_driver da8xx_cfgchip_driver = { .probe = da8xx_cfgchip_probe, .driver = { .name = "da8xx-cfgchip-clk", .of_match_table = da8xx_cfgchip_of_match, }, .id_table = da8xx_cfgchip_id_table, }; static int __init da8xx_cfgchip_driver_init(void) { return platform_driver_register(&da8xx_cfgchip_driver); } /* has to be postcore_initcall because PSC devices depend on the async3 clock */ postcore_initcall(da8xx_cfgchip_driver_init);
linux-master
drivers/clk/davinci/da8xx-cfgchip.c
// SPDX-License-Identifier: GPL-2.0 /* * Clock driver for TI Davinci PSC controllers * * Copyright (C) 2017 David Lechner <[email protected]> * * Based on: drivers/clk/keystone/gate.c * Copyright (C) 2013 Texas Instruments. * Murali Karicheri <[email protected]> * Santosh Shilimkar <[email protected]> * * And: arch/arm/mach-davinci/psc.c * Copyright (C) 2006 Texas Instruments. */ #include <linux/clk-provider.h> #include <linux/clk.h> #include <linux/clk/davinci.h> #include <linux/clkdev.h> #include <linux/err.h> #include <linux/of_address.h> #include <linux/of_device.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_clock.h> #include <linux/pm_domain.h> #include <linux/regmap.h> #include <linux/reset-controller.h> #include <linux/slab.h> #include <linux/types.h> #include "psc.h" /* PSC register offsets */ #define EPCPR 0x070 #define PTCMD 0x120 #define PTSTAT 0x128 #define PDSTAT(n) (0x200 + 4 * (n)) #define PDCTL(n) (0x300 + 4 * (n)) #define MDSTAT(n) (0x800 + 4 * (n)) #define MDCTL(n) (0xa00 + 4 * (n)) /* PSC module states */ enum davinci_lpsc_state { LPSC_STATE_SWRSTDISABLE = 0, LPSC_STATE_SYNCRST = 1, LPSC_STATE_DISABLE = 2, LPSC_STATE_ENABLE = 3, }; #define MDSTAT_STATE_MASK GENMASK(5, 0) #define MDSTAT_MCKOUT BIT(12) #define PDSTAT_STATE_MASK GENMASK(4, 0) #define MDCTL_FORCE BIT(31) #define MDCTL_LRESET BIT(8) #define PDCTL_EPCGOOD BIT(8) #define PDCTL_NEXT BIT(0) struct davinci_psc_data { struct clk_onecell_data clk_data; struct genpd_onecell_data pm_data; struct reset_controller_dev rcdev; }; /** * struct davinci_lpsc_clk - LPSC clock structure * @dev: the device that provides this LPSC or NULL * @hw: clk_hw for the LPSC * @pm_domain: power domain for the LPSC * @genpd_clk: clock reference owned by @pm_domain * @regmap: PSC MMIO region * @md: Module domain (LPSC module id) * @pd: Power domain * @flags: LPSC_* quirk flags */ struct davinci_lpsc_clk { struct device *dev; struct clk_hw hw; struct generic_pm_domain pm_domain; struct clk *genpd_clk; struct regmap *regmap; u32 md; u32 pd; u32 flags; }; #define to_davinci_psc_data(x) container_of(x, struct davinci_psc_data, x) #define to_davinci_lpsc_clk(x) container_of(x, struct davinci_lpsc_clk, x) /** * best_dev_name - get the "best" device name. * @dev: the device * * Returns the device tree compatible name if the device has a DT node, * otherwise return the device name. This is mainly needed because clkdev * lookups are limited to 20 chars for dev_id and when using device tree, * dev_name(dev) is much longer than that. */ static inline const char *best_dev_name(struct device *dev) { const char *compatible; if (!of_property_read_string(dev->of_node, "compatible", &compatible)) return compatible; return dev_name(dev); } static void davinci_lpsc_config(struct davinci_lpsc_clk *lpsc, enum davinci_lpsc_state next_state) { u32 epcpr, pdstat, mdstat, ptstat; regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDSTAT_STATE_MASK, next_state); if (lpsc->flags & LPSC_FORCE) regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_FORCE, MDCTL_FORCE); regmap_read(lpsc->regmap, PDSTAT(lpsc->pd), &pdstat); if ((pdstat & PDSTAT_STATE_MASK) == 0) { regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_NEXT, PDCTL_NEXT); regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd)); regmap_read_poll_timeout(lpsc->regmap, EPCPR, epcpr, epcpr & BIT(lpsc->pd), 0, 0); regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_EPCGOOD, PDCTL_EPCGOOD); } else { regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd)); } regmap_read_poll_timeout(lpsc->regmap, PTSTAT, ptstat, !(ptstat & BIT(lpsc->pd)), 0, 0); regmap_read_poll_timeout(lpsc->regmap, MDSTAT(lpsc->md), mdstat, (mdstat & MDSTAT_STATE_MASK) == next_state, 0, 0); } static int davinci_lpsc_clk_enable(struct clk_hw *hw) { struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw); davinci_lpsc_config(lpsc, LPSC_STATE_ENABLE); return 0; } static void davinci_lpsc_clk_disable(struct clk_hw *hw) { struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw); davinci_lpsc_config(lpsc, LPSC_STATE_DISABLE); } static int davinci_lpsc_clk_is_enabled(struct clk_hw *hw) { struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw); u32 mdstat; regmap_read(lpsc->regmap, MDSTAT(lpsc->md), &mdstat); return (mdstat & MDSTAT_MCKOUT) ? 1 : 0; } static const struct clk_ops davinci_lpsc_clk_ops = { .enable = davinci_lpsc_clk_enable, .disable = davinci_lpsc_clk_disable, .is_enabled = davinci_lpsc_clk_is_enabled, }; static int davinci_psc_genpd_attach_dev(struct generic_pm_domain *pm_domain, struct device *dev) { struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain); struct clk *clk; int ret; /* * pm_clk_remove_clk() will call clk_put(), so we have to use clk_get() * to get the clock instead of using lpsc->hw.clk directly. */ clk = clk_get_sys(best_dev_name(lpsc->dev), clk_hw_get_name(&lpsc->hw)); if (IS_ERR(clk)) return (PTR_ERR(clk)); ret = pm_clk_create(dev); if (ret < 0) goto fail_clk_put; ret = pm_clk_add_clk(dev, clk); if (ret < 0) goto fail_pm_clk_destroy; lpsc->genpd_clk = clk; return 0; fail_pm_clk_destroy: pm_clk_destroy(dev); fail_clk_put: clk_put(clk); return ret; } static void davinci_psc_genpd_detach_dev(struct generic_pm_domain *pm_domain, struct device *dev) { struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain); pm_clk_remove_clk(dev, lpsc->genpd_clk); pm_clk_destroy(dev); lpsc->genpd_clk = NULL; } /** * davinci_lpsc_clk_register - register LPSC clock * @dev: the clocks's device or NULL * @name: name of this clock * @parent_name: name of clock's parent * @regmap: PSC MMIO region * @md: local PSC number * @pd: power domain * @flags: LPSC_* flags */ static struct davinci_lpsc_clk * davinci_lpsc_clk_register(struct device *dev, const char *name, const char *parent_name, struct regmap *regmap, u32 md, u32 pd, u32 flags) { struct clk_init_data init; struct davinci_lpsc_clk *lpsc; int ret; bool is_on; lpsc = kzalloc(sizeof(*lpsc), GFP_KERNEL); if (!lpsc) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &davinci_lpsc_clk_ops; init.parent_names = (parent_name ? &parent_name : NULL); init.num_parents = (parent_name ? 1 : 0); init.flags = 0; if (flags & LPSC_ALWAYS_ENABLED) init.flags |= CLK_IS_CRITICAL; if (flags & LPSC_SET_RATE_PARENT) init.flags |= CLK_SET_RATE_PARENT; lpsc->dev = dev; lpsc->regmap = regmap; lpsc->hw.init = &init; lpsc->md = md; lpsc->pd = pd; lpsc->flags = flags; ret = clk_hw_register(dev, &lpsc->hw); if (ret < 0) { kfree(lpsc); return ERR_PTR(ret); } /* for now, genpd is only registered when using device-tree */ if (!dev || !dev->of_node) return lpsc; /* genpd attach needs a way to look up this clock */ ret = clk_hw_register_clkdev(&lpsc->hw, name, best_dev_name(dev)); lpsc->pm_domain.name = devm_kasprintf(dev, GFP_KERNEL, "%s: %s", best_dev_name(dev), name); lpsc->pm_domain.attach_dev = davinci_psc_genpd_attach_dev; lpsc->pm_domain.detach_dev = davinci_psc_genpd_detach_dev; lpsc->pm_domain.flags = GENPD_FLAG_PM_CLK; is_on = davinci_lpsc_clk_is_enabled(&lpsc->hw); pm_genpd_init(&lpsc->pm_domain, NULL, is_on); return lpsc; } static int davinci_lpsc_clk_reset(struct clk *clk, bool reset) { struct clk_hw *hw = __clk_get_hw(clk); struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw); u32 mdctl; if (IS_ERR_OR_NULL(lpsc)) return -EINVAL; mdctl = reset ? 0 : MDCTL_LRESET; regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_LRESET, mdctl); return 0; } static int davinci_psc_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) { struct davinci_psc_data *psc = to_davinci_psc_data(rcdev); struct clk *clk = psc->clk_data.clks[id]; return davinci_lpsc_clk_reset(clk, true); } static int davinci_psc_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { struct davinci_psc_data *psc = to_davinci_psc_data(rcdev); struct clk *clk = psc->clk_data.clks[id]; return davinci_lpsc_clk_reset(clk, false); } static const struct reset_control_ops davinci_psc_reset_ops = { .assert = davinci_psc_reset_assert, .deassert = davinci_psc_reset_deassert, }; static int davinci_psc_reset_of_xlate(struct reset_controller_dev *rcdev, const struct of_phandle_args *reset_spec) { struct of_phandle_args clkspec = *reset_spec; /* discard const qualifier */ struct clk *clk; struct clk_hw *hw; struct davinci_lpsc_clk *lpsc; /* the clock node is the same as the reset node */ clk = of_clk_get_from_provider(&clkspec); if (IS_ERR(clk)) return PTR_ERR(clk); hw = __clk_get_hw(clk); lpsc = to_davinci_lpsc_clk(hw); clk_put(clk); /* not all modules support local reset */ if (!(lpsc->flags & LPSC_LOCAL_RESET)) return -EINVAL; return lpsc->md; } static const struct regmap_config davinci_psc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, }; static struct davinci_psc_data * __davinci_psc_register_clocks(struct device *dev, const struct davinci_lpsc_clk_info *info, int num_clks, void __iomem *base) { struct davinci_psc_data *psc; struct clk **clks; struct generic_pm_domain **pm_domains; struct regmap *regmap; int i, ret; psc = kzalloc(sizeof(*psc), GFP_KERNEL); if (!psc) return ERR_PTR(-ENOMEM); clks = kmalloc_array(num_clks, sizeof(*clks), GFP_KERNEL); if (!clks) { ret = -ENOMEM; goto err_free_psc; } psc->clk_data.clks = clks; psc->clk_data.clk_num = num_clks; /* * init array with error so that of_clk_src_onecell_get() doesn't * return NULL for gaps in the sparse array */ for (i = 0; i < num_clks; i++) clks[i] = ERR_PTR(-ENOENT); pm_domains = kcalloc(num_clks, sizeof(*pm_domains), GFP_KERNEL); if (!pm_domains) { ret = -ENOMEM; goto err_free_clks; } psc->pm_data.domains = pm_domains; psc->pm_data.num_domains = num_clks; regmap = regmap_init_mmio(dev, base, &davinci_psc_regmap_config); if (IS_ERR(regmap)) { ret = PTR_ERR(regmap); goto err_free_pm_domains; } for (; info->name; info++) { struct davinci_lpsc_clk *lpsc; lpsc = davinci_lpsc_clk_register(dev, info->name, info->parent, regmap, info->md, info->pd, info->flags); if (IS_ERR(lpsc)) { dev_warn(dev, "Failed to register %s (%ld)\n", info->name, PTR_ERR(lpsc)); continue; } clks[info->md] = lpsc->hw.clk; pm_domains[info->md] = &lpsc->pm_domain; } /* * for now, a reset controller is only registered when there is a device * to associate it with. */ if (!dev) return psc; psc->rcdev.ops = &davinci_psc_reset_ops; psc->rcdev.owner = THIS_MODULE; psc->rcdev.dev = dev; psc->rcdev.of_node = dev->of_node; psc->rcdev.of_reset_n_cells = 1; psc->rcdev.of_xlate = davinci_psc_reset_of_xlate; psc->rcdev.nr_resets = num_clks; ret = devm_reset_controller_register(dev, &psc->rcdev); if (ret < 0) dev_warn(dev, "Failed to register reset controller (%d)\n", ret); return psc; err_free_pm_domains: kfree(pm_domains); err_free_clks: kfree(clks); err_free_psc: kfree(psc); return ERR_PTR(ret); } int davinci_psc_register_clocks(struct device *dev, const struct davinci_lpsc_clk_info *info, u8 num_clks, void __iomem *base) { struct davinci_psc_data *psc; psc = __davinci_psc_register_clocks(dev, info, num_clks, base); if (IS_ERR(psc)) return PTR_ERR(psc); for (; info->name; info++) { const struct davinci_lpsc_clkdev_info *cdevs = info->cdevs; struct clk *clk = psc->clk_data.clks[info->md]; if (!cdevs || IS_ERR_OR_NULL(clk)) continue; for (; cdevs->con_id || cdevs->dev_id; cdevs++) clk_register_clkdev(clk, cdevs->con_id, cdevs->dev_id); } return 0; } int of_davinci_psc_clk_init(struct device *dev, const struct davinci_lpsc_clk_info *info, u8 num_clks, void __iomem *base) { struct device_node *node = dev->of_node; struct davinci_psc_data *psc; psc = __davinci_psc_register_clocks(dev, info, num_clks, base); if (IS_ERR(psc)) return PTR_ERR(psc); of_genpd_add_provider_onecell(node, &psc->pm_data); of_clk_add_provider(node, of_clk_src_onecell_get, &psc->clk_data); return 0; } static const struct of_device_id davinci_psc_of_match[] = { #ifdef CONFIG_ARCH_DAVINCI_DA850 { .compatible = "ti,da850-psc0", .data = &of_da850_psc0_init_data }, { .compatible = "ti,da850-psc1", .data = &of_da850_psc1_init_data }, #endif { } }; static const struct platform_device_id davinci_psc_id_table[] = { #ifdef CONFIG_ARCH_DAVINCI_DA830 { .name = "da830-psc0", .driver_data = (kernel_ulong_t)&da830_psc0_init_data }, { .name = "da830-psc1", .driver_data = (kernel_ulong_t)&da830_psc1_init_data }, #endif #ifdef CONFIG_ARCH_DAVINCI_DA850 { .name = "da850-psc0", .driver_data = (kernel_ulong_t)&da850_psc0_init_data }, { .name = "da850-psc1", .driver_data = (kernel_ulong_t)&da850_psc1_init_data }, #endif { } }; static int davinci_psc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; const struct of_device_id *of_id; const struct davinci_psc_init_data *init_data = NULL; void __iomem *base; int ret; of_id = of_match_device(davinci_psc_of_match, dev); if (of_id) init_data = of_id->data; else if (pdev->id_entry) init_data = (void *)pdev->id_entry->driver_data; if (!init_data) { dev_err(dev, "unable to find driver init data\n"); return -EINVAL; } base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); ret = devm_clk_bulk_get(dev, init_data->num_parent_clks, init_data->parent_clks); if (ret < 0) return ret; return init_data->psc_init(dev, base); } static struct platform_driver davinci_psc_driver = { .probe = davinci_psc_probe, .driver = { .name = "davinci-psc-clk", .of_match_table = davinci_psc_of_match, }, .id_table = davinci_psc_id_table, }; static int __init davinci_psc_driver_init(void) { return platform_driver_register(&davinci_psc_driver); } /* has to be postcore_initcall because davinci_gpio depend on PSC clocks */ postcore_initcall(davinci_psc_driver_init);
linux-master
drivers/clk/davinci/psc.c
// SPDX-License-Identifier: GPL-2.0 /* * PLL clock descriptions for TI DA850/OMAP-L138/AM18XX * * Copyright (C) 2018 David Lechner <[email protected]> */ #include <linux/bitops.h> #include <linux/clk-provider.h> #include <linux/clk/davinci.h> #include <linux/clkdev.h> #include <linux/device.h> #include <linux/init.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/mfd/da8xx-cfgchip.h> #include <linux/mfd/syscon.h> #include <linux/of_address.h> #include <linux/of.h> #include <linux/types.h> #include "pll.h" #define OCSEL_OCSRC_OSCIN 0x14 #define OCSEL_OCSRC_PLL0_SYSCLK(n) (0x16 + (n)) #define OCSEL_OCSRC_PLL1_OBSCLK 0x1e #define OCSEL_OCSRC_PLL1_SYSCLK(n) (0x16 + (n)) static const struct davinci_pll_clk_info da850_pll0_info = { .name = "pll0", .unlock_reg = CFGCHIP(0), .unlock_mask = CFGCHIP0_PLL_MASTER_LOCK, .pllm_mask = GENMASK(4, 0), .pllm_min = 4, .pllm_max = 32, .pllout_min_rate = 300000000, .pllout_max_rate = 600000000, .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV | PLL_HAS_EXTCLKSRC, }; /* * NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio", * meaning that we could change the divider as long as we keep the correct * ratio between all of the clocks, but we don't support that because there is * currently not a need for it. */ SYSCLK(1, pll0_sysclk1, pll0_pllen, 5, SYSCLK_FIXED_DIV); SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV); SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0); SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV); SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0); SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_ARM_RATE | SYSCLK_FIXED_DIV); SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0); static const char * const da850_pll0_obsclk_parent_names[] = { "oscin", "pll0_sysclk1", "pll0_sysclk2", "pll0_sysclk3", "pll0_sysclk4", "pll0_sysclk5", "pll0_sysclk6", "pll0_sysclk7", "pll1_obsclk", }; static u32 da850_pll0_obsclk_table[] = { OCSEL_OCSRC_OSCIN, OCSEL_OCSRC_PLL0_SYSCLK(1), OCSEL_OCSRC_PLL0_SYSCLK(2), OCSEL_OCSRC_PLL0_SYSCLK(3), OCSEL_OCSRC_PLL0_SYSCLK(4), OCSEL_OCSRC_PLL0_SYSCLK(5), OCSEL_OCSRC_PLL0_SYSCLK(6), OCSEL_OCSRC_PLL0_SYSCLK(7), OCSEL_OCSRC_PLL1_OBSCLK, }; static const struct davinci_pll_obsclk_info da850_pll0_obsclk_info = { .name = "pll0_obsclk", .parent_names = da850_pll0_obsclk_parent_names, .num_parents = ARRAY_SIZE(da850_pll0_obsclk_parent_names), .table = da850_pll0_obsclk_table, .ocsrc_mask = GENMASK(4, 0), }; int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) { struct clk *clk; davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base); clk_register_clkdev(clk, "pll0_sysclk1", "da850-psc0"); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base); clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc0"); clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc1"); clk_register_clkdev(clk, "pll0_sysclk2", "da850-async3-clksrc"); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base); clk_register_clkdev(clk, "pll0_sysclk3", "da850-async1-clksrc"); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base); clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc0"); clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc1"); davinci_pll_sysclk_register(dev, &pll0_sysclk5, base); clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base); clk_register_clkdev(clk, "pll0_sysclk6", "da850-psc0"); davinci_pll_sysclk_register(dev, &pll0_sysclk7, base); davinci_pll_auxclk_register(dev, "pll0_auxclk", base); clk = clk_register_fixed_factor(dev, "async2", "pll0_auxclk", CLK_IS_CRITICAL, 1, 1); clk_register_clkdev(clk, NULL, "i2c_davinci.1"); clk_register_clkdev(clk, "timer0", NULL); clk_register_clkdev(clk, NULL, "davinci-wdt"); davinci_pll_obsclk_register(dev, &da850_pll0_obsclk_info, base); return 0; } static const struct davinci_pll_sysclk_info *da850_pll0_sysclk_info[] = { &pll0_sysclk1, &pll0_sysclk2, &pll0_sysclk3, &pll0_sysclk4, &pll0_sysclk5, &pll0_sysclk6, &pll0_sysclk7, NULL }; void of_da850_pll0_init(struct device_node *node) { void __iomem *base; struct regmap *cfgchip; base = of_iomap(node, 0); if (!base) { pr_err("%s: ioremap failed\n", __func__); return; } cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); of_davinci_pll_init(NULL, node, &da850_pll0_info, &da850_pll0_obsclk_info, da850_pll0_sysclk_info, 7, base, cfgchip); } static const struct davinci_pll_clk_info da850_pll1_info = { .name = "pll1", .unlock_reg = CFGCHIP(3), .unlock_mask = CFGCHIP3_PLL1_MASTER_LOCK, .pllm_mask = GENMASK(4, 0), .pllm_min = 4, .pllm_max = 32, .pllout_min_rate = 300000000, .pllout_max_rate = 600000000, .flags = PLL_HAS_POSTDIV, }; SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED); SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, 0); SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, 0); static const char * const da850_pll1_obsclk_parent_names[] = { "oscin", "pll1_sysclk1", "pll1_sysclk2", "pll1_sysclk3", }; static u32 da850_pll1_obsclk_table[] = { OCSEL_OCSRC_OSCIN, OCSEL_OCSRC_PLL1_SYSCLK(1), OCSEL_OCSRC_PLL1_SYSCLK(2), OCSEL_OCSRC_PLL1_SYSCLK(3), }; static const struct davinci_pll_obsclk_info da850_pll1_obsclk_info = { .name = "pll1_obsclk", .parent_names = da850_pll1_obsclk_parent_names, .num_parents = ARRAY_SIZE(da850_pll1_obsclk_parent_names), .table = da850_pll1_obsclk_table, .ocsrc_mask = GENMASK(4, 0), }; int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) { struct clk *clk; davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base, cfgchip); davinci_pll_sysclk_register(dev, &pll1_sysclk1, base); clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base); clk_register_clkdev(clk, "pll1_sysclk2", "da850-async3-clksrc"); davinci_pll_sysclk_register(dev, &pll1_sysclk3, base); davinci_pll_obsclk_register(dev, &da850_pll1_obsclk_info, base); return 0; } static const struct davinci_pll_sysclk_info *da850_pll1_sysclk_info[] = { &pll1_sysclk1, &pll1_sysclk2, &pll1_sysclk3, NULL }; int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) { return of_davinci_pll_init(dev, dev->of_node, &da850_pll1_info, &da850_pll1_obsclk_info, da850_pll1_sysclk_info, 3, base, cfgchip); }
linux-master
drivers/clk/davinci/pll-da850.c
// SPDX-License-Identifier: GPL-2.0 /* * PLL clock driver for TI Davinci SoCs * * Copyright (C) 2018 David Lechner <[email protected]> * * Based on arch/arm/mach-davinci/clock.c * Copyright (C) 2006-2007 Texas Instruments. * Copyright (C) 2008-2009 Deep Root Systems, LLC */ #include <linux/clk-provider.h> #include <linux/clk.h> #include <linux/clk/davinci.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/notifier.h> #include <linux/of_address.h> #include <linux/of_device.h> #include <linux/of.h> #include <linux/platform_data/clk-davinci-pll.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/slab.h> #include <linux/types.h> #include "pll.h" #define MAX_NAME_SIZE 20 #define OSCIN_CLK_NAME "oscin" #define REVID 0x000 #define PLLCTL 0x100 #define OCSEL 0x104 #define PLLSECCTL 0x108 #define PLLM 0x110 #define PREDIV 0x114 #define PLLDIV1 0x118 #define PLLDIV2 0x11c #define PLLDIV3 0x120 #define OSCDIV 0x124 #define POSTDIV 0x128 #define BPDIV 0x12c #define PLLCMD 0x138 #define PLLSTAT 0x13c #define ALNCTL 0x140 #define DCHANGE 0x144 #define CKEN 0x148 #define CKSTAT 0x14c #define SYSTAT 0x150 #define PLLDIV4 0x160 #define PLLDIV5 0x164 #define PLLDIV6 0x168 #define PLLDIV7 0x16c #define PLLDIV8 0x170 #define PLLDIV9 0x174 #define PLLCTL_PLLEN BIT(0) #define PLLCTL_PLLPWRDN BIT(1) #define PLLCTL_PLLRST BIT(3) #define PLLCTL_PLLDIS BIT(4) #define PLLCTL_PLLENSRC BIT(5) #define PLLCTL_CLKMODE BIT(8) /* shared by most *DIV registers */ #define DIV_RATIO_SHIFT 0 #define DIV_RATIO_WIDTH 5 #define DIV_ENABLE_SHIFT 15 #define PLLCMD_GOSET BIT(0) #define PLLSTAT_GOSTAT BIT(0) #define CKEN_OBSCLK_SHIFT 1 #define CKEN_AUXEN_SHIFT 0 /* * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input * is ~25MHz. Units are micro seconds. */ #define PLL_BYPASS_TIME 1 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */ #define PLL_RESET_TIME 1 /* * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4 * Units are micro seconds. */ #define PLL_LOCK_TIME 20 /** * struct davinci_pll_clk - Main PLL clock (aka PLLOUT) * @hw: clk_hw for the pll * @base: Base memory address * @pllm_min: The minimum allowable PLLM[PLLM] value * @pllm_max: The maximum allowable PLLM[PLLM] value * @pllm_mask: Bitmask for PLLM[PLLM] value */ struct davinci_pll_clk { struct clk_hw hw; void __iomem *base; u32 pllm_min; u32 pllm_max; u32 pllm_mask; }; #define to_davinci_pll_clk(_hw) \ container_of((_hw), struct davinci_pll_clk, hw) static unsigned long davinci_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); unsigned long rate = parent_rate; u32 mult; mult = readl(pll->base + PLLM) & pll->pllm_mask; rate *= mult + 1; return rate; } static int davinci_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); struct clk_hw *parent = req->best_parent_hw; unsigned long parent_rate = req->best_parent_rate; unsigned long rate = req->rate; unsigned long best_rate, r; u32 mult; /* there is a limited range of valid outputs (see datasheet) */ if (rate < req->min_rate) return -EINVAL; rate = min(rate, req->max_rate); mult = rate / parent_rate; best_rate = parent_rate * mult; /* easy case when there is no PREDIV */ if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { if (best_rate < req->min_rate) return -EINVAL; if (mult < pll->pllm_min || mult > pll->pllm_max) return -EINVAL; req->rate = best_rate; return 0; } /* see if the PREDIV clock can help us */ best_rate = 0; for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) { parent_rate = clk_hw_round_rate(parent, rate / mult); r = parent_rate * mult; if (r < req->min_rate) continue; if (r > rate || r > req->max_rate) break; if (r > best_rate) { best_rate = r; req->rate = best_rate; req->best_parent_rate = parent_rate; if (best_rate == rate) break; } } return 0; } static int davinci_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); u32 mult; mult = rate / parent_rate; writel(mult - 1, pll->base + PLLM); return 0; } #ifdef CONFIG_DEBUG_FS static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry); #else #define davinci_pll_debug_init NULL #endif static const struct clk_ops davinci_pll_ops = { .recalc_rate = davinci_pll_recalc_rate, .determine_rate = davinci_pll_determine_rate, .set_rate = davinci_pll_set_rate, .debug_init = davinci_pll_debug_init, }; /* PLLM works differently on DM365 */ static unsigned long dm365_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); unsigned long rate = parent_rate; u32 mult; mult = readl(pll->base + PLLM) & pll->pllm_mask; rate *= mult * 2; return rate; } static const struct clk_ops dm365_pll_ops = { .recalc_rate = dm365_pll_recalc_rate, .debug_init = davinci_pll_debug_init, }; /** * davinci_pll_div_register - common *DIV clock implementation * @dev: The PLL platform device or NULL * @name: the clock name * @parent_name: the parent clock name * @reg: the *DIV register * @fixed: if true, the divider is a fixed value * @flags: bitmap of CLK_* flags from clock-provider.h */ static struct clk *davinci_pll_div_register(struct device *dev, const char *name, const char *parent_name, void __iomem *reg, bool fixed, u32 flags) { const char * const *parent_names = parent_name ? &parent_name : NULL; int num_parents = parent_name ? 1 : 0; const struct clk_ops *divider_ops = &clk_divider_ops; struct clk_gate *gate; struct clk_divider *divider; struct clk *clk; int ret; gate = kzalloc(sizeof(*gate), GFP_KERNEL); if (!gate) return ERR_PTR(-ENOMEM); gate->reg = reg; gate->bit_idx = DIV_ENABLE_SHIFT; divider = kzalloc(sizeof(*divider), GFP_KERNEL); if (!divider) { ret = -ENOMEM; goto err_free_gate; } divider->reg = reg; divider->shift = DIV_RATIO_SHIFT; divider->width = DIV_RATIO_WIDTH; if (fixed) { divider->flags |= CLK_DIVIDER_READ_ONLY; divider_ops = &clk_divider_ro_ops; } clk = clk_register_composite(dev, name, parent_names, num_parents, NULL, NULL, &divider->hw, divider_ops, &gate->hw, &clk_gate_ops, flags); if (IS_ERR(clk)) { ret = PTR_ERR(clk); goto err_free_divider; } return clk; err_free_divider: kfree(divider); err_free_gate: kfree(gate); return ERR_PTR(ret); } struct davinci_pllen_clk { struct clk_hw hw; void __iomem *base; }; #define to_davinci_pllen_clk(_hw) \ container_of((_hw), struct davinci_pllen_clk, hw) static const struct clk_ops davinci_pllen_ops = { /* this clocks just uses the clock notification feature */ }; /* * The PLL has to be switched into bypass mode while we are chaning the rate, * so we do that on the PLLEN clock since it is the end of the line. This will * switch to bypass before any of the parent clocks (PREDIV, PLL, POSTDIV) are * changed and will switch back to the PLL after the changes have been made. */ static int davinci_pllen_rate_change(struct notifier_block *nb, unsigned long flags, void *data) { struct clk_notifier_data *cnd = data; struct clk_hw *hw = __clk_get_hw(cnd->clk); struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw); u32 ctrl; ctrl = readl(pll->base + PLLCTL); if (flags == PRE_RATE_CHANGE) { /* Switch the PLL to bypass mode */ ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); writel(ctrl, pll->base + PLLCTL); udelay(PLL_BYPASS_TIME); /* Reset and enable PLL */ ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS); writel(ctrl, pll->base + PLLCTL); } else { udelay(PLL_RESET_TIME); /* Bring PLL out of reset */ ctrl |= PLLCTL_PLLRST; writel(ctrl, pll->base + PLLCTL); udelay(PLL_LOCK_TIME); /* Remove PLL from bypass mode */ ctrl |= PLLCTL_PLLEN; writel(ctrl, pll->base + PLLCTL); } return NOTIFY_OK; } static struct notifier_block davinci_pllen_notifier = { .notifier_call = davinci_pllen_rate_change, }; /** * davinci_pll_clk_register - Register a PLL clock * @dev: The PLL platform device or NULL * @info: The device-specific clock info * @parent_name: The parent clock name * @base: The PLL's memory region * @cfgchip: CFGCHIP syscon regmap for info->unlock_reg or NULL * * This creates a series of clocks that represent the PLL. * * OSCIN > [PREDIV >] PLL > [POSTDIV >] PLLEN * * - OSCIN is the parent clock (on secondary PLL, may come from primary PLL) * - PREDIV and POSTDIV are optional (depends on the PLL controller) * - PLL is the PLL output (aka PLLOUT) * - PLLEN is the bypass multiplexer * * Returns: The PLLOUT clock or a negative error code. */ struct clk *davinci_pll_clk_register(struct device *dev, const struct davinci_pll_clk_info *info, const char *parent_name, void __iomem *base, struct regmap *cfgchip) { char prediv_name[MAX_NAME_SIZE]; char pllout_name[MAX_NAME_SIZE]; char postdiv_name[MAX_NAME_SIZE]; char pllen_name[MAX_NAME_SIZE]; struct clk_init_data init; struct davinci_pll_clk *pllout; struct davinci_pllen_clk *pllen; struct clk *oscin_clk = NULL; struct clk *prediv_clk = NULL; struct clk *pllout_clk; struct clk *postdiv_clk = NULL; struct clk *pllen_clk; int ret; if (info->flags & PLL_HAS_CLKMODE) { /* * If a PLL has PLLCTL[CLKMODE], then it is the primary PLL. * We register a clock named "oscin" that serves as the internal * "input clock" domain shared by both PLLs (if there are 2) * and will be the parent clock to the AUXCLK, SYSCLKBP and * OBSCLK domains. NB: The various TRMs use "OSCIN" to mean * a number of different things. In this driver we use it to * mean the signal after the PLLCTL[CLKMODE] switch. */ oscin_clk = clk_register_fixed_factor(dev, OSCIN_CLK_NAME, parent_name, 0, 1, 1); if (IS_ERR(oscin_clk)) return oscin_clk; parent_name = OSCIN_CLK_NAME; } if (info->flags & PLL_HAS_PREDIV) { bool fixed = info->flags & PLL_PREDIV_FIXED_DIV; u32 flags = 0; snprintf(prediv_name, MAX_NAME_SIZE, "%s_prediv", info->name); if (info->flags & PLL_PREDIV_ALWAYS_ENABLED) flags |= CLK_IS_CRITICAL; /* Some? DM355 chips don't correctly report the PREDIV value */ if (info->flags & PLL_PREDIV_FIXED8) prediv_clk = clk_register_fixed_factor(dev, prediv_name, parent_name, flags, 1, 8); else prediv_clk = davinci_pll_div_register(dev, prediv_name, parent_name, base + PREDIV, fixed, flags); if (IS_ERR(prediv_clk)) { ret = PTR_ERR(prediv_clk); goto err_unregister_oscin; } parent_name = prediv_name; } /* Unlock writing to PLL registers */ if (info->unlock_reg) { if (IS_ERR_OR_NULL(cfgchip)) dev_warn(dev, "Failed to get CFGCHIP (%ld)\n", PTR_ERR(cfgchip)); else regmap_write_bits(cfgchip, info->unlock_reg, info->unlock_mask, 0); } pllout = kzalloc(sizeof(*pllout), GFP_KERNEL); if (!pllout) { ret = -ENOMEM; goto err_unregister_prediv; } snprintf(pllout_name, MAX_NAME_SIZE, "%s_pllout", info->name); init.name = pllout_name; if (info->flags & PLL_PLLM_2X) init.ops = &dm365_pll_ops; else init.ops = &davinci_pll_ops; init.parent_names = &parent_name; init.num_parents = 1; init.flags = 0; if (info->flags & PLL_HAS_PREDIV) init.flags |= CLK_SET_RATE_PARENT; pllout->hw.init = &init; pllout->base = base; pllout->pllm_mask = info->pllm_mask; pllout->pllm_min = info->pllm_min; pllout->pllm_max = info->pllm_max; pllout_clk = clk_register(dev, &pllout->hw); if (IS_ERR(pllout_clk)) { ret = PTR_ERR(pllout_clk); goto err_free_pllout; } clk_hw_set_rate_range(&pllout->hw, info->pllout_min_rate, info->pllout_max_rate); parent_name = pllout_name; if (info->flags & PLL_HAS_POSTDIV) { bool fixed = info->flags & PLL_POSTDIV_FIXED_DIV; u32 flags = CLK_SET_RATE_PARENT; snprintf(postdiv_name, MAX_NAME_SIZE, "%s_postdiv", info->name); if (info->flags & PLL_POSTDIV_ALWAYS_ENABLED) flags |= CLK_IS_CRITICAL; postdiv_clk = davinci_pll_div_register(dev, postdiv_name, parent_name, base + POSTDIV, fixed, flags); if (IS_ERR(postdiv_clk)) { ret = PTR_ERR(postdiv_clk); goto err_unregister_pllout; } parent_name = postdiv_name; } pllen = kzalloc(sizeof(*pllen), GFP_KERNEL); if (!pllen) { ret = -ENOMEM; goto err_unregister_postdiv; } snprintf(pllen_name, MAX_NAME_SIZE, "%s_pllen", info->name); init.name = pllen_name; init.ops = &davinci_pllen_ops; init.parent_names = &parent_name; init.num_parents = 1; init.flags = CLK_SET_RATE_PARENT; pllen->hw.init = &init; pllen->base = base; pllen_clk = clk_register(dev, &pllen->hw); if (IS_ERR(pllen_clk)) { ret = PTR_ERR(pllen_clk); goto err_free_pllen; } clk_notifier_register(pllen_clk, &davinci_pllen_notifier); return pllout_clk; err_free_pllen: kfree(pllen); err_unregister_postdiv: clk_unregister(postdiv_clk); err_unregister_pllout: clk_unregister(pllout_clk); err_free_pllout: kfree(pllout); err_unregister_prediv: clk_unregister(prediv_clk); err_unregister_oscin: clk_unregister(oscin_clk); return ERR_PTR(ret); } /** * davinci_pll_auxclk_register - Register bypass clock (AUXCLK) * @dev: The PLL platform device or NULL * @name: The clock name * @base: The PLL memory region */ struct clk *davinci_pll_auxclk_register(struct device *dev, const char *name, void __iomem *base) { return clk_register_gate(dev, name, OSCIN_CLK_NAME, 0, base + CKEN, CKEN_AUXEN_SHIFT, 0, NULL); } /** * davinci_pll_sysclkbp_clk_register - Register bypass divider clock (SYSCLKBP) * @dev: The PLL platform device or NULL * @name: The clock name * @base: The PLL memory region */ struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev, const char *name, void __iomem *base) { return clk_register_divider(dev, name, OSCIN_CLK_NAME, 0, base + BPDIV, DIV_RATIO_SHIFT, DIV_RATIO_WIDTH, CLK_DIVIDER_READ_ONLY, NULL); } /** * davinci_pll_obsclk_register - Register oscillator divider clock (OBSCLK) * @dev: The PLL platform device or NULL * @info: The clock info * @base: The PLL memory region */ struct clk * davinci_pll_obsclk_register(struct device *dev, const struct davinci_pll_obsclk_info *info, void __iomem *base) { struct clk_mux *mux; struct clk_gate *gate; struct clk_divider *divider; struct clk *clk; u32 oscdiv; int ret; mux = kzalloc(sizeof(*mux), GFP_KERNEL); if (!mux) return ERR_PTR(-ENOMEM); mux->reg = base + OCSEL; mux->table = info->table; mux->mask = info->ocsrc_mask; gate = kzalloc(sizeof(*gate), GFP_KERNEL); if (!gate) { ret = -ENOMEM; goto err_free_mux; } gate->reg = base + CKEN; gate->bit_idx = CKEN_OBSCLK_SHIFT; divider = kzalloc(sizeof(*divider), GFP_KERNEL); if (!divider) { ret = -ENOMEM; goto err_free_gate; } divider->reg = base + OSCDIV; divider->shift = DIV_RATIO_SHIFT; divider->width = DIV_RATIO_WIDTH; /* make sure divider is enabled just in case bootloader disabled it */ oscdiv = readl(base + OSCDIV); oscdiv |= BIT(DIV_ENABLE_SHIFT); writel(oscdiv, base + OSCDIV); clk = clk_register_composite(dev, info->name, info->parent_names, info->num_parents, &mux->hw, &clk_mux_ops, &divider->hw, &clk_divider_ops, &gate->hw, &clk_gate_ops, 0); if (IS_ERR(clk)) { ret = PTR_ERR(clk); goto err_free_divider; } return clk; err_free_divider: kfree(divider); err_free_gate: kfree(gate); err_free_mux: kfree(mux); return ERR_PTR(ret); } /* The PLL SYSCLKn clocks have a mechanism for synchronizing rate changes. */ static int davinci_pll_sysclk_rate_change(struct notifier_block *nb, unsigned long flags, void *data) { struct clk_notifier_data *cnd = data; struct clk_hw *hw = __clk_get_hw(clk_get_parent(cnd->clk)); struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw); u32 pllcmd, pllstat; switch (flags) { case POST_RATE_CHANGE: /* apply the changes */ pllcmd = readl(pll->base + PLLCMD); pllcmd |= PLLCMD_GOSET; writel(pllcmd, pll->base + PLLCMD); fallthrough; case PRE_RATE_CHANGE: /* Wait until for outstanding changes to take effect */ do { pllstat = readl(pll->base + PLLSTAT); } while (pllstat & PLLSTAT_GOSTAT); break; } return NOTIFY_OK; } static struct notifier_block davinci_pll_sysclk_notifier = { .notifier_call = davinci_pll_sysclk_rate_change, }; /** * davinci_pll_sysclk_register - Register divider clocks (SYSCLKn) * @dev: The PLL platform device or NULL * @info: The clock info * @base: The PLL memory region */ struct clk * davinci_pll_sysclk_register(struct device *dev, const struct davinci_pll_sysclk_info *info, void __iomem *base) { const struct clk_ops *divider_ops = &clk_divider_ops; struct clk_gate *gate; struct clk_divider *divider; struct clk *clk; u32 reg; u32 flags = 0; int ret; /* PLLDIVn registers are not entirely consecutive */ if (info->id < 4) reg = PLLDIV1 + 4 * (info->id - 1); else reg = PLLDIV4 + 4 * (info->id - 4); gate = kzalloc(sizeof(*gate), GFP_KERNEL); if (!gate) return ERR_PTR(-ENOMEM); gate->reg = base + reg; gate->bit_idx = DIV_ENABLE_SHIFT; divider = kzalloc(sizeof(*divider), GFP_KERNEL); if (!divider) { ret = -ENOMEM; goto err_free_gate; } divider->reg = base + reg; divider->shift = DIV_RATIO_SHIFT; divider->width = info->ratio_width; divider->flags = 0; if (info->flags & SYSCLK_FIXED_DIV) { divider->flags |= CLK_DIVIDER_READ_ONLY; divider_ops = &clk_divider_ro_ops; } /* Only the ARM clock can change the parent PLL rate */ if (info->flags & SYSCLK_ARM_RATE) flags |= CLK_SET_RATE_PARENT; if (info->flags & SYSCLK_ALWAYS_ENABLED) flags |= CLK_IS_CRITICAL; clk = clk_register_composite(dev, info->name, &info->parent_name, 1, NULL, NULL, &divider->hw, divider_ops, &gate->hw, &clk_gate_ops, flags); if (IS_ERR(clk)) { ret = PTR_ERR(clk); goto err_free_divider; } clk_notifier_register(clk, &davinci_pll_sysclk_notifier); return clk; err_free_divider: kfree(divider); err_free_gate: kfree(gate); return ERR_PTR(ret); } int of_davinci_pll_init(struct device *dev, struct device_node *node, const struct davinci_pll_clk_info *info, const struct davinci_pll_obsclk_info *obsclk_info, const struct davinci_pll_sysclk_info **div_info, u8 max_sysclk_id, void __iomem *base, struct regmap *cfgchip) { struct device_node *child; const char *parent_name; struct clk *clk; if (info->flags & PLL_HAS_CLKMODE) parent_name = of_clk_get_parent_name(node, 0); else parent_name = OSCIN_CLK_NAME; clk = davinci_pll_clk_register(dev, info, parent_name, base, cfgchip); if (IS_ERR(clk)) { dev_err(dev, "failed to register %s\n", info->name); return PTR_ERR(clk); } child = of_get_child_by_name(node, "pllout"); if (of_device_is_available(child)) of_clk_add_provider(child, of_clk_src_simple_get, clk); of_node_put(child); child = of_get_child_by_name(node, "sysclk"); if (of_device_is_available(child)) { struct clk_onecell_data *clk_data; struct clk **clks; int n_clks = max_sysclk_id + 1; int i; clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); if (!clk_data) { of_node_put(child); return -ENOMEM; } clks = kmalloc_array(n_clks, sizeof(*clks), GFP_KERNEL); if (!clks) { kfree(clk_data); of_node_put(child); return -ENOMEM; } clk_data->clks = clks; clk_data->clk_num = n_clks; for (i = 0; i < n_clks; i++) clks[i] = ERR_PTR(-ENOENT); for (; *div_info; div_info++) { clk = davinci_pll_sysclk_register(dev, *div_info, base); if (IS_ERR(clk)) dev_warn(dev, "failed to register %s (%ld)\n", (*div_info)->name, PTR_ERR(clk)); else clks[(*div_info)->id] = clk; } of_clk_add_provider(child, of_clk_src_onecell_get, clk_data); } of_node_put(child); child = of_get_child_by_name(node, "auxclk"); if (of_device_is_available(child)) { char child_name[MAX_NAME_SIZE]; snprintf(child_name, MAX_NAME_SIZE, "%s_auxclk", info->name); clk = davinci_pll_auxclk_register(dev, child_name, base); if (IS_ERR(clk)) dev_warn(dev, "failed to register %s (%ld)\n", child_name, PTR_ERR(clk)); else of_clk_add_provider(child, of_clk_src_simple_get, clk); } of_node_put(child); child = of_get_child_by_name(node, "obsclk"); if (of_device_is_available(child)) { if (obsclk_info) clk = davinci_pll_obsclk_register(dev, obsclk_info, base); else clk = ERR_PTR(-EINVAL); if (IS_ERR(clk)) dev_warn(dev, "failed to register obsclk (%ld)\n", PTR_ERR(clk)); else of_clk_add_provider(child, of_clk_src_simple_get, clk); } of_node_put(child); return 0; } static struct davinci_pll_platform_data *davinci_pll_get_pdata(struct device *dev) { struct davinci_pll_platform_data *pdata = dev_get_platdata(dev); /* * Platform data is optional, so allocate a new struct if one was not * provided. For device tree, this will always be the case. */ if (!pdata) pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) return NULL; /* for device tree, we need to fill in the struct */ if (dev->of_node) pdata->cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); return pdata; } /* needed in early boot for clocksource/clockevent */ #ifdef CONFIG_ARCH_DAVINCI_DA850 CLK_OF_DECLARE(da850_pll0, "ti,da850-pll0", of_da850_pll0_init); #endif static const struct of_device_id davinci_pll_of_match[] = { #ifdef CONFIG_ARCH_DAVINCI_DA850 { .compatible = "ti,da850-pll1", .data = of_da850_pll1_init }, #endif { } }; static const struct platform_device_id davinci_pll_id_table[] = { #ifdef CONFIG_ARCH_DAVINCI_DA830 { .name = "da830-pll", .driver_data = (kernel_ulong_t)da830_pll_init }, #endif #ifdef CONFIG_ARCH_DAVINCI_DA850 { .name = "da850-pll0", .driver_data = (kernel_ulong_t)da850_pll0_init }, { .name = "da850-pll1", .driver_data = (kernel_ulong_t)da850_pll1_init }, #endif { } }; typedef int (*davinci_pll_init)(struct device *dev, void __iomem *base, struct regmap *cfgchip); static int davinci_pll_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct davinci_pll_platform_data *pdata; const struct of_device_id *of_id; davinci_pll_init pll_init = NULL; void __iomem *base; of_id = of_match_device(davinci_pll_of_match, dev); if (of_id) pll_init = of_id->data; else if (pdev->id_entry) pll_init = (void *)pdev->id_entry->driver_data; if (!pll_init) { dev_err(dev, "unable to find driver data\n"); return -EINVAL; } pdata = davinci_pll_get_pdata(dev); if (!pdata) { dev_err(dev, "missing platform data\n"); return -EINVAL; } base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); return pll_init(dev, base, pdata->cfgchip); } static struct platform_driver davinci_pll_driver = { .probe = davinci_pll_probe, .driver = { .name = "davinci-pll-clk", .of_match_table = davinci_pll_of_match, }, .id_table = davinci_pll_id_table, }; static int __init davinci_pll_driver_init(void) { return platform_driver_register(&davinci_pll_driver); } /* has to be postcore_initcall because PSC devices depend on PLL parent clocks */ postcore_initcall(davinci_pll_driver_init); #ifdef CONFIG_DEBUG_FS #include <linux/debugfs.h> #define DEBUG_REG(n) \ { \ .name = #n, \ .offset = n, \ } static const struct debugfs_reg32 davinci_pll_regs[] = { DEBUG_REG(REVID), DEBUG_REG(PLLCTL), DEBUG_REG(OCSEL), DEBUG_REG(PLLSECCTL), DEBUG_REG(PLLM), DEBUG_REG(PREDIV), DEBUG_REG(PLLDIV1), DEBUG_REG(PLLDIV2), DEBUG_REG(PLLDIV3), DEBUG_REG(OSCDIV), DEBUG_REG(POSTDIV), DEBUG_REG(BPDIV), DEBUG_REG(PLLCMD), DEBUG_REG(PLLSTAT), DEBUG_REG(ALNCTL), DEBUG_REG(DCHANGE), DEBUG_REG(CKEN), DEBUG_REG(CKSTAT), DEBUG_REG(SYSTAT), DEBUG_REG(PLLDIV4), DEBUG_REG(PLLDIV5), DEBUG_REG(PLLDIV6), DEBUG_REG(PLLDIV7), DEBUG_REG(PLLDIV8), DEBUG_REG(PLLDIV9), }; static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry) { struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); struct debugfs_regset32 *regset; regset = kzalloc(sizeof(*regset), GFP_KERNEL); if (!regset) return; regset->regs = davinci_pll_regs; regset->nregs = ARRAY_SIZE(davinci_pll_regs); regset->base = pll->base; debugfs_create_regset32("registers", 0400, dentry, regset); } #endif
linux-master
drivers/clk/davinci/pll.c
// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2014 Marvell Technology Group Ltd. * * Alexandre Belloni <[email protected]> * Sebastian Hesselbarth <[email protected]> */ #include <linux/bitops.h> #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/slab.h> #include <linux/spinlock.h> #include "berlin2-div.h" /* * Clock dividers in Berlin2 SoCs comprise a complex cell to select * input pll and divider. The virtual structure as it is used in Marvell * BSP code can be seen as: * * +---+ * pll0 --------------->| 0 | +---+ * +---+ |(B)|--+--------------->| 0 | +---+ * pll1.0 -->| 0 | +-->| 1 | | +--------+ |(E)|----->| 0 | +---+ * pll1.1 -->| 1 | | +---+ +-->|(C) 1:M |-->| 1 | |(F)|-->|(G)|-> * ... -->|(A)|--+ | +--------+ +---+ +-->| 1 | +---+ * ... -->| | +-->|(D) 1:3 |----------+ +---+ * pll1.N -->| N | +--------- * +---+ * * (A) input pll clock mux controlled by <PllSelect[1:n]> * (B) input pll bypass mux controlled by <PllSwitch> * (C) programmable clock divider controlled by <Select[1:n]> * (D) constant div-by-3 clock divider * (E) programmable clock divider bypass controlled by <Switch> * (F) constant div-by-3 clock mux controlled by <D3Switch> * (G) clock gate controlled by <Enable> * * For whatever reason, above control signals come in two flavors: * - single register dividers with all bits in one register * - shared register dividers with bits spread over multiple registers * (including signals for the same cell spread over consecutive registers) * * Also, clock gate and pll mux is not available on every div cell, so * we have to deal with those, too. We reuse common clock composite driver * for it. */ #define PLL_SELECT_MASK 0x7 #define DIV_SELECT_MASK 0x7 struct berlin2_div { struct clk_hw hw; void __iomem *base; struct berlin2_div_map map; spinlock_t *lock; }; #define to_berlin2_div(hw) container_of(hw, struct berlin2_div, hw) static u8 clk_div[] = { 1, 2, 4, 6, 8, 12, 1, 1 }; static int berlin2_div_is_enabled(struct clk_hw *hw) { struct berlin2_div *div = to_berlin2_div(hw); struct berlin2_div_map *map = &div->map; u32 reg; if (div->lock) spin_lock(div->lock); reg = readl_relaxed(div->base + map->gate_offs); reg >>= map->gate_shift; if (div->lock) spin_unlock(div->lock); return (reg & 0x1); } static int berlin2_div_enable(struct clk_hw *hw) { struct berlin2_div *div = to_berlin2_div(hw); struct berlin2_div_map *map = &div->map; u32 reg; if (div->lock) spin_lock(div->lock); reg = readl_relaxed(div->base + map->gate_offs); reg |= BIT(map->gate_shift); writel_relaxed(reg, div->base + map->gate_offs); if (div->lock) spin_unlock(div->lock); return 0; } static void berlin2_div_disable(struct clk_hw *hw) { struct berlin2_div *div = to_berlin2_div(hw); struct berlin2_div_map *map = &div->map; u32 reg; if (div->lock) spin_lock(div->lock); reg = readl_relaxed(div->base + map->gate_offs); reg &= ~BIT(map->gate_shift); writel_relaxed(reg, div->base + map->gate_offs); if (div->lock) spin_unlock(div->lock); } static int berlin2_div_set_parent(struct clk_hw *hw, u8 index) { struct berlin2_div *div = to_berlin2_div(hw); struct berlin2_div_map *map = &div->map; u32 reg; if (div->lock) spin_lock(div->lock); /* index == 0 is PLL_SWITCH */ reg = readl_relaxed(div->base + map->pll_switch_offs); if (index == 0) reg &= ~BIT(map->pll_switch_shift); else reg |= BIT(map->pll_switch_shift); writel_relaxed(reg, div->base + map->pll_switch_offs); /* index > 0 is PLL_SELECT */ if (index > 0) { reg = readl_relaxed(div->base + map->pll_select_offs); reg &= ~(PLL_SELECT_MASK << map->pll_select_shift); reg |= (index - 1) << map->pll_select_shift; writel_relaxed(reg, div->base + map->pll_select_offs); } if (div->lock) spin_unlock(div->lock); return 0; } static u8 berlin2_div_get_parent(struct clk_hw *hw) { struct berlin2_div *div = to_berlin2_div(hw); struct berlin2_div_map *map = &div->map; u32 reg; u8 index = 0; if (div->lock) spin_lock(div->lock); /* PLL_SWITCH == 0 is index 0 */ reg = readl_relaxed(div->base + map->pll_switch_offs); reg &= BIT(map->pll_switch_shift); if (reg) { reg = readl_relaxed(div->base + map->pll_select_offs); reg >>= map->pll_select_shift; reg &= PLL_SELECT_MASK; index = 1 + reg; } if (div->lock) spin_unlock(div->lock); return index; } static unsigned long berlin2_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct berlin2_div *div = to_berlin2_div(hw); struct berlin2_div_map *map = &div->map; u32 divsw, div3sw, divider = 1; if (div->lock) spin_lock(div->lock); divsw = readl_relaxed(div->base + map->div_switch_offs) & (1 << map->div_switch_shift); div3sw = readl_relaxed(div->base + map->div3_switch_offs) & (1 << map->div3_switch_shift); /* constant divide-by-3 (dominant) */ if (div3sw != 0) { divider = 3; /* divider can be bypassed with DIV_SWITCH == 0 */ } else if (divsw == 0) { divider = 1; /* clock divider determined by DIV_SELECT */ } else { u32 reg; reg = readl_relaxed(div->base + map->div_select_offs); reg >>= map->div_select_shift; reg &= DIV_SELECT_MASK; divider = clk_div[reg]; } if (div->lock) spin_unlock(div->lock); return parent_rate / divider; } static const struct clk_ops berlin2_div_rate_ops = { .determine_rate = clk_hw_determine_rate_no_reparent, .recalc_rate = berlin2_div_recalc_rate, }; static const struct clk_ops berlin2_div_gate_ops = { .is_enabled = berlin2_div_is_enabled, .enable = berlin2_div_enable, .disable = berlin2_div_disable, }; static const struct clk_ops berlin2_div_mux_ops = { .set_parent = berlin2_div_set_parent, .get_parent = berlin2_div_get_parent, }; struct clk_hw * __init berlin2_div_register(const struct berlin2_div_map *map, void __iomem *base, const char *name, u8 div_flags, const char **parent_names, int num_parents, unsigned long flags, spinlock_t *lock) { const struct clk_ops *mux_ops = &berlin2_div_mux_ops; const struct clk_ops *rate_ops = &berlin2_div_rate_ops; const struct clk_ops *gate_ops = &berlin2_div_gate_ops; struct berlin2_div *div; div = kzalloc(sizeof(*div), GFP_KERNEL); if (!div) return ERR_PTR(-ENOMEM); /* copy div_map to allow __initconst */ memcpy(&div->map, map, sizeof(*map)); div->base = base; div->lock = lock; if ((div_flags & BERLIN2_DIV_HAS_GATE) == 0) gate_ops = NULL; if ((div_flags & BERLIN2_DIV_HAS_MUX) == 0) mux_ops = NULL; return clk_hw_register_composite(NULL, name, parent_names, num_parents, &div->hw, mux_ops, &div->hw, rate_ops, &div->hw, gate_ops, flags); }
linux-master
drivers/clk/berlin/berlin2-div.c
// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2014 Marvell Technology Group Ltd. * * Sebastian Hesselbarth <[email protected]> * Alexandre Belloni <[email protected]> */ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/slab.h> #include "berlin2-avpll.h" /* * Berlin2 SoCs comprise up to two PLLs called AVPLL built upon a * VCO with 8 channels each, channel 8 is the odd-one-out and does * not provide mul/div. * * Unfortunately, its registers are not named but just numbered. To * get in at least some kind of structure, we split each AVPLL into * the VCOs and each channel into separate clock drivers. * * Also, here and there the VCO registers are a bit different with * respect to bit shifts. Make sure to add a comment for those. */ #define NUM_CHANNELS 8 #define AVPLL_CTRL(x) ((x) * 0x4) #define VCO_CTRL0 AVPLL_CTRL(0) /* BG2/BG2CDs VCO_B has an additional shift of 4 for its VCO_CTRL0 reg */ #define VCO_RESET BIT(0) #define VCO_POWERUP BIT(1) #define VCO_INTERPOL_SHIFT 2 #define VCO_INTERPOL_MASK (0xf << VCO_INTERPOL_SHIFT) #define VCO_REG1V45_SEL_SHIFT 6 #define VCO_REG1V45_SEL(x) ((x) << VCO_REG1V45_SEL_SHIFT) #define VCO_REG1V45_SEL_1V40 VCO_REG1V45_SEL(0) #define VCO_REG1V45_SEL_1V45 VCO_REG1V45_SEL(1) #define VCO_REG1V45_SEL_1V50 VCO_REG1V45_SEL(2) #define VCO_REG1V45_SEL_1V55 VCO_REG1V45_SEL(3) #define VCO_REG1V45_SEL_MASK VCO_REG1V45_SEL(3) #define VCO_REG0V9_SEL_SHIFT 8 #define VCO_REG0V9_SEL_MASK (0xf << VCO_REG0V9_SEL_SHIFT) #define VCO_VTHCAL_SHIFT 12 #define VCO_VTHCAL(x) ((x) << VCO_VTHCAL_SHIFT) #define VCO_VTHCAL_0V90 VCO_VTHCAL(0) #define VCO_VTHCAL_0V95 VCO_VTHCAL(1) #define VCO_VTHCAL_1V00 VCO_VTHCAL(2) #define VCO_VTHCAL_1V05 VCO_VTHCAL(3) #define VCO_VTHCAL_MASK VCO_VTHCAL(3) #define VCO_KVCOEXT_SHIFT 14 #define VCO_KVCOEXT_MASK (0x3 << VCO_KVCOEXT_SHIFT) #define VCO_KVCOEXT_ENABLE BIT(17) #define VCO_V2IEXT_SHIFT 18 #define VCO_V2IEXT_MASK (0xf << VCO_V2IEXT_SHIFT) #define VCO_V2IEXT_ENABLE BIT(22) #define VCO_SPEED_SHIFT 23 #define VCO_SPEED(x) ((x) << VCO_SPEED_SHIFT) #define VCO_SPEED_1G08_1G21 VCO_SPEED(0) #define VCO_SPEED_1G21_1G40 VCO_SPEED(1) #define VCO_SPEED_1G40_1G61 VCO_SPEED(2) #define VCO_SPEED_1G61_1G86 VCO_SPEED(3) #define VCO_SPEED_1G86_2G00 VCO_SPEED(4) #define VCO_SPEED_2G00_2G22 VCO_SPEED(5) #define VCO_SPEED_2G22 VCO_SPEED(6) #define VCO_SPEED_MASK VCO_SPEED(0x7) #define VCO_CLKDET_ENABLE BIT(26) #define VCO_CTRL1 AVPLL_CTRL(1) #define VCO_REFDIV_SHIFT 0 #define VCO_REFDIV(x) ((x) << VCO_REFDIV_SHIFT) #define VCO_REFDIV_1 VCO_REFDIV(0) #define VCO_REFDIV_2 VCO_REFDIV(1) #define VCO_REFDIV_4 VCO_REFDIV(2) #define VCO_REFDIV_3 VCO_REFDIV(3) #define VCO_REFDIV_MASK VCO_REFDIV(0x3f) #define VCO_FBDIV_SHIFT 6 #define VCO_FBDIV(x) ((x) << VCO_FBDIV_SHIFT) #define VCO_FBDIV_MASK VCO_FBDIV(0xff) #define VCO_ICP_SHIFT 14 /* PLL Charge Pump Current = 10uA * (x + 1) */ #define VCO_ICP(x) ((x) << VCO_ICP_SHIFT) #define VCO_ICP_MASK VCO_ICP(0xf) #define VCO_LOAD_CAP BIT(18) #define VCO_CALIBRATION_START BIT(19) #define VCO_FREQOFFSETn(x) AVPLL_CTRL(3 + (x)) #define VCO_FREQOFFSET_MASK 0x7ffff #define VCO_CTRL10 AVPLL_CTRL(10) #define VCO_POWERUP_CH1 BIT(20) #define VCO_CTRL11 AVPLL_CTRL(11) #define VCO_CTRL12 AVPLL_CTRL(12) #define VCO_CTRL13 AVPLL_CTRL(13) #define VCO_CTRL14 AVPLL_CTRL(14) #define VCO_CTRL15 AVPLL_CTRL(15) #define VCO_SYNC1n(x) AVPLL_CTRL(15 + (x)) #define VCO_SYNC1_MASK 0x1ffff #define VCO_SYNC2n(x) AVPLL_CTRL(23 + (x)) #define VCO_SYNC2_MASK 0x1ffff #define VCO_CTRL30 AVPLL_CTRL(30) #define VCO_DPLL_CH1_ENABLE BIT(17) struct berlin2_avpll_vco { struct clk_hw hw; void __iomem *base; u8 flags; }; #define to_avpll_vco(hw) container_of(hw, struct berlin2_avpll_vco, hw) static int berlin2_avpll_vco_is_enabled(struct clk_hw *hw) { struct berlin2_avpll_vco *vco = to_avpll_vco(hw); u32 reg; reg = readl_relaxed(vco->base + VCO_CTRL0); if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) reg >>= 4; return !!(reg & VCO_POWERUP); } static int berlin2_avpll_vco_enable(struct clk_hw *hw) { struct berlin2_avpll_vco *vco = to_avpll_vco(hw); u32 reg; reg = readl_relaxed(vco->base + VCO_CTRL0); if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) reg |= VCO_POWERUP << 4; else reg |= VCO_POWERUP; writel_relaxed(reg, vco->base + VCO_CTRL0); return 0; } static void berlin2_avpll_vco_disable(struct clk_hw *hw) { struct berlin2_avpll_vco *vco = to_avpll_vco(hw); u32 reg; reg = readl_relaxed(vco->base + VCO_CTRL0); if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) reg &= ~(VCO_POWERUP << 4); else reg &= ~VCO_POWERUP; writel_relaxed(reg, vco->base + VCO_CTRL0); } static u8 vco_refdiv[] = { 1, 2, 4, 3 }; static unsigned long berlin2_avpll_vco_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct berlin2_avpll_vco *vco = to_avpll_vco(hw); u32 reg, refdiv, fbdiv; u64 freq = parent_rate; /* AVPLL VCO frequency: Fvco = (Fref / refdiv) * fbdiv */ reg = readl_relaxed(vco->base + VCO_CTRL1); refdiv = (reg & VCO_REFDIV_MASK) >> VCO_REFDIV_SHIFT; refdiv = vco_refdiv[refdiv]; fbdiv = (reg & VCO_FBDIV_MASK) >> VCO_FBDIV_SHIFT; freq *= fbdiv; do_div(freq, refdiv); return (unsigned long)freq; } static const struct clk_ops berlin2_avpll_vco_ops = { .is_enabled = berlin2_avpll_vco_is_enabled, .enable = berlin2_avpll_vco_enable, .disable = berlin2_avpll_vco_disable, .recalc_rate = berlin2_avpll_vco_recalc_rate, }; int __init berlin2_avpll_vco_register(void __iomem *base, const char *name, const char *parent_name, u8 vco_flags, unsigned long flags) { struct berlin2_avpll_vco *vco; struct clk_init_data init; vco = kzalloc(sizeof(*vco), GFP_KERNEL); if (!vco) return -ENOMEM; vco->base = base; vco->flags = vco_flags; vco->hw.init = &init; init.name = name; init.ops = &berlin2_avpll_vco_ops; init.parent_names = &parent_name; init.num_parents = 1; init.flags = flags; return clk_hw_register(NULL, &vco->hw); } struct berlin2_avpll_channel { struct clk_hw hw; void __iomem *base; u8 flags; u8 index; }; #define to_avpll_channel(hw) container_of(hw, struct berlin2_avpll_channel, hw) static int berlin2_avpll_channel_is_enabled(struct clk_hw *hw) { struct berlin2_avpll_channel *ch = to_avpll_channel(hw); u32 reg; if (ch->index == 7) return 1; reg = readl_relaxed(ch->base + VCO_CTRL10); reg &= VCO_POWERUP_CH1 << ch->index; return !!reg; } static int berlin2_avpll_channel_enable(struct clk_hw *hw) { struct berlin2_avpll_channel *ch = to_avpll_channel(hw); u32 reg; reg = readl_relaxed(ch->base + VCO_CTRL10); reg |= VCO_POWERUP_CH1 << ch->index; writel_relaxed(reg, ch->base + VCO_CTRL10); return 0; } static void berlin2_avpll_channel_disable(struct clk_hw *hw) { struct berlin2_avpll_channel *ch = to_avpll_channel(hw); u32 reg; reg = readl_relaxed(ch->base + VCO_CTRL10); reg &= ~(VCO_POWERUP_CH1 << ch->index); writel_relaxed(reg, ch->base + VCO_CTRL10); } static const u8 div_hdmi[] = { 1, 2, 4, 6 }; static const u8 div_av1[] = { 1, 2, 5, 5 }; static unsigned long berlin2_avpll_channel_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct berlin2_avpll_channel *ch = to_avpll_channel(hw); u32 reg, div_av2, div_av3, divider = 1; u64 freq = parent_rate; reg = readl_relaxed(ch->base + VCO_CTRL30); if ((reg & (VCO_DPLL_CH1_ENABLE << ch->index)) == 0) goto skip_div; /* * Fch = (Fref * sync2) / * (sync1 * div_hdmi * div_av1 * div_av2 * div_av3) */ reg = readl_relaxed(ch->base + VCO_SYNC1n(ch->index)); /* BG2/BG2CDs SYNC1 reg on AVPLL_B channel 1 is shifted by 4 */ if (ch->flags & BERLIN2_AVPLL_BIT_QUIRK && ch->index == 0) reg >>= 4; divider = reg & VCO_SYNC1_MASK; reg = readl_relaxed(ch->base + VCO_SYNC2n(ch->index)); freq *= reg & VCO_SYNC2_MASK; /* Channel 8 has no dividers */ if (ch->index == 7) goto skip_div; /* * HDMI divider start at VCO_CTRL11, bit 7; MSB is enable, lower 2 bit * determine divider. */ reg = readl_relaxed(ch->base + VCO_CTRL11) >> 7; reg = (reg >> (ch->index * 3)); if (reg & BIT(2)) divider *= div_hdmi[reg & 0x3]; /* * AV1 divider start at VCO_CTRL11, bit 28; MSB is enable, lower 2 bit * determine divider. */ if (ch->index == 0) { reg = readl_relaxed(ch->base + VCO_CTRL11); reg >>= 28; } else { reg = readl_relaxed(ch->base + VCO_CTRL12); reg >>= (ch->index-1) * 3; } if (reg & BIT(2)) divider *= div_av1[reg & 0x3]; /* * AV2 divider start at VCO_CTRL12, bit 18; each 7 bits wide, * zero is not a valid value. */ if (ch->index < 2) { reg = readl_relaxed(ch->base + VCO_CTRL12); reg >>= 18 + (ch->index * 7); } else if (ch->index < 7) { reg = readl_relaxed(ch->base + VCO_CTRL13); reg >>= (ch->index - 2) * 7; } else { reg = readl_relaxed(ch->base + VCO_CTRL14); } div_av2 = reg & 0x7f; if (div_av2) divider *= div_av2; /* * AV3 divider start at VCO_CTRL14, bit 7; each 4 bits wide. * AV2/AV3 form a fractional divider, where only specfic values for AV3 * are allowed. AV3 != 0 divides by AV2/2, AV3=0 is bypass. */ if (ch->index < 6) { reg = readl_relaxed(ch->base + VCO_CTRL14); reg >>= 7 + (ch->index * 4); } else { reg = readl_relaxed(ch->base + VCO_CTRL15); } div_av3 = reg & 0xf; if (div_av2 && div_av3) freq *= 2; skip_div: do_div(freq, divider); return (unsigned long)freq; } static const struct clk_ops berlin2_avpll_channel_ops = { .is_enabled = berlin2_avpll_channel_is_enabled, .enable = berlin2_avpll_channel_enable, .disable = berlin2_avpll_channel_disable, .recalc_rate = berlin2_avpll_channel_recalc_rate, }; /* * Another nice quirk: * On some production SoCs, AVPLL channels are scrambled with respect * to the channel numbering in the registers but still referenced by * their original channel numbers. We deal with it by having a flag * and a translation table for the index. */ static const u8 quirk_index[] __initconst = { 0, 6, 5, 4, 3, 2, 1, 7 }; int __init berlin2_avpll_channel_register(void __iomem *base, const char *name, u8 index, const char *parent_name, u8 ch_flags, unsigned long flags) { struct berlin2_avpll_channel *ch; struct clk_init_data init; ch = kzalloc(sizeof(*ch), GFP_KERNEL); if (!ch) return -ENOMEM; ch->base = base; if (ch_flags & BERLIN2_AVPLL_SCRAMBLE_QUIRK) ch->index = quirk_index[index]; else ch->index = index; ch->flags = ch_flags; ch->hw.init = &init; init.name = name; init.ops = &berlin2_avpll_channel_ops; init.parent_names = &parent_name; init.num_parents = 1; init.flags = flags; return clk_hw_register(NULL, &ch->hw); }
linux-master
drivers/clk/berlin/berlin2-avpll.c
// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2014 Marvell Technology Group Ltd. * * Sebastian Hesselbarth <[email protected]> * Alexandre Belloni <[email protected]> */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/slab.h> #include <dt-bindings/clock/berlin2.h> #include "berlin2-avpll.h" #include "berlin2-div.h" #include "berlin2-pll.h" #include "common.h" #define REG_PINMUX0 0x0000 #define REG_PINMUX1 0x0004 #define REG_SYSPLLCTL0 0x0014 #define REG_SYSPLLCTL4 0x0024 #define REG_MEMPLLCTL0 0x0028 #define REG_MEMPLLCTL4 0x0038 #define REG_CPUPLLCTL0 0x003c #define REG_CPUPLLCTL4 0x004c #define REG_AVPLLCTL0 0x0050 #define REG_AVPLLCTL31 0x00cc #define REG_AVPLLCTL62 0x0148 #define REG_PLLSTATUS 0x014c #define REG_CLKENABLE 0x0150 #define REG_CLKSELECT0 0x0154 #define REG_CLKSELECT1 0x0158 #define REG_CLKSELECT2 0x015c #define REG_CLKSELECT3 0x0160 #define REG_CLKSWITCH0 0x0164 #define REG_CLKSWITCH1 0x0168 #define REG_RESET_TRIGGER 0x0178 #define REG_RESET_STATUS0 0x017c #define REG_RESET_STATUS1 0x0180 #define REG_SW_GENERIC0 0x0184 #define REG_SW_GENERIC3 0x0190 #define REG_PRODUCTID 0x01cc #define REG_PRODUCTID_EXT 0x01d0 #define REG_GFX3DCORE_CLKCTL 0x022c #define REG_GFX3DSYS_CLKCTL 0x0230 #define REG_ARC_CLKCTL 0x0234 #define REG_VIP_CLKCTL 0x0238 #define REG_SDIO0XIN_CLKCTL 0x023c #define REG_SDIO1XIN_CLKCTL 0x0240 #define REG_GFX3DEXTRA_CLKCTL 0x0244 #define REG_GFX3D_RESET 0x0248 #define REG_GC360_CLKCTL 0x024c #define REG_SDIO_DLLMST_CLKCTL 0x0250 /* * BG2/BG2CD SoCs have the following audio/video I/O units: * * audiohd: HDMI TX audio * audio0: 7.1ch TX * audio1: 2ch TX * audio2: 2ch RX * audio3: SPDIF TX * video0: HDMI video * video1: Secondary video * video2: SD auxiliary video * * There are no external audio clocks (ACLKI0, ACLKI1) and * only one external video clock (VCLKI0). * * Currently missing bits and pieces: * - audio_fast_pll is unknown * - audiohd_pll is unknown * - video0_pll is unknown * - audio[023], audiohd parent pll is assumed to be audio_fast_pll * */ #define MAX_CLKS 41 static struct clk_hw_onecell_data *clk_data; static DEFINE_SPINLOCK(lock); static void __iomem *gbase; enum { REFCLK, VIDEO_EXT0, SYSPLL, MEMPLL, CPUPLL, AVPLL_A1, AVPLL_A2, AVPLL_A3, AVPLL_A4, AVPLL_A5, AVPLL_A6, AVPLL_A7, AVPLL_A8, AVPLL_B1, AVPLL_B2, AVPLL_B3, AVPLL_B4, AVPLL_B5, AVPLL_B6, AVPLL_B7, AVPLL_B8, AUDIO1_PLL, AUDIO_FAST_PLL, VIDEO0_PLL, VIDEO0_IN, VIDEO1_PLL, VIDEO1_IN, VIDEO2_PLL, VIDEO2_IN, }; static const char *clk_names[] = { [REFCLK] = "refclk", [VIDEO_EXT0] = "video_ext0", [SYSPLL] = "syspll", [MEMPLL] = "mempll", [CPUPLL] = "cpupll", [AVPLL_A1] = "avpll_a1", [AVPLL_A2] = "avpll_a2", [AVPLL_A3] = "avpll_a3", [AVPLL_A4] = "avpll_a4", [AVPLL_A5] = "avpll_a5", [AVPLL_A6] = "avpll_a6", [AVPLL_A7] = "avpll_a7", [AVPLL_A8] = "avpll_a8", [AVPLL_B1] = "avpll_b1", [AVPLL_B2] = "avpll_b2", [AVPLL_B3] = "avpll_b3", [AVPLL_B4] = "avpll_b4", [AVPLL_B5] = "avpll_b5", [AVPLL_B6] = "avpll_b6", [AVPLL_B7] = "avpll_b7", [AVPLL_B8] = "avpll_b8", [AUDIO1_PLL] = "audio1_pll", [AUDIO_FAST_PLL] = "audio_fast_pll", [VIDEO0_PLL] = "video0_pll", [VIDEO0_IN] = "video0_in", [VIDEO1_PLL] = "video1_pll", [VIDEO1_IN] = "video1_in", [VIDEO2_PLL] = "video2_pll", [VIDEO2_IN] = "video2_in", }; static const struct berlin2_pll_map bg2_pll_map __initconst = { .vcodiv = {10, 15, 20, 25, 30, 40, 50, 60, 80}, .mult = 10, .fbdiv_shift = 6, .rfdiv_shift = 1, .divsel_shift = 7, }; static const u8 default_parent_ids[] = { SYSPLL, AVPLL_B4, AVPLL_A5, AVPLL_B6, AVPLL_B7, SYSPLL }; static const struct berlin2_div_data bg2_divs[] __initconst = { { .name = "sys", .parent_ids = (const u8 []){ SYSPLL, AVPLL_B4, AVPLL_B5, AVPLL_B6, AVPLL_B7, SYSPLL }, .num_parents = 6, .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 0), BERLIN2_PLL_SELECT(REG_CLKSELECT0, 0), BERLIN2_DIV_SELECT(REG_CLKSELECT0, 3), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 3), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 4), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 5), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = CLK_IGNORE_UNUSED, }, { .name = "cpu", .parent_ids = (const u8 []){ CPUPLL, MEMPLL, MEMPLL, MEMPLL, MEMPLL }, .num_parents = 5, .map = { BERLIN2_PLL_SELECT(REG_CLKSELECT0, 6), BERLIN2_DIV_SELECT(REG_CLKSELECT0, 9), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 6), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 7), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 8), }, .div_flags = BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "drmfigo", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 16), BERLIN2_PLL_SELECT(REG_CLKSELECT0, 17), BERLIN2_DIV_SELECT(REG_CLKSELECT0, 20), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 12), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 13), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 14), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "cfg", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 1), BERLIN2_PLL_SELECT(REG_CLKSELECT0, 23), BERLIN2_DIV_SELECT(REG_CLKSELECT0, 26), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 15), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 16), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 17), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "gfx", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 4), BERLIN2_PLL_SELECT(REG_CLKSELECT0, 29), BERLIN2_DIV_SELECT(REG_CLKSELECT1, 0), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 18), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 19), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 20), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "zsp", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 5), BERLIN2_PLL_SELECT(REG_CLKSELECT1, 3), BERLIN2_DIV_SELECT(REG_CLKSELECT1, 6), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 21), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 22), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 23), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "perif", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 6), BERLIN2_PLL_SELECT(REG_CLKSELECT1, 9), BERLIN2_DIV_SELECT(REG_CLKSELECT1, 12), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 24), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 25), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 26), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = CLK_IGNORE_UNUSED, }, { .name = "pcube", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 2), BERLIN2_PLL_SELECT(REG_CLKSELECT1, 15), BERLIN2_DIV_SELECT(REG_CLKSELECT1, 18), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 27), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 28), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 29), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "vscope", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 3), BERLIN2_PLL_SELECT(REG_CLKSELECT1, 21), BERLIN2_DIV_SELECT(REG_CLKSELECT1, 24), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 30), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 31), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 0), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "nfc_ecc", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 18), BERLIN2_PLL_SELECT(REG_CLKSELECT1, 27), BERLIN2_DIV_SELECT(REG_CLKSELECT2, 0), BERLIN2_PLL_SWITCH(REG_CLKSWITCH1, 1), BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 2), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 3), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "vpp", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 21), BERLIN2_PLL_SELECT(REG_CLKSELECT2, 3), BERLIN2_DIV_SELECT(REG_CLKSELECT2, 6), BERLIN2_PLL_SWITCH(REG_CLKSWITCH1, 4), BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 5), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 6), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "app", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 20), BERLIN2_PLL_SELECT(REG_CLKSELECT2, 9), BERLIN2_DIV_SELECT(REG_CLKSELECT2, 12), BERLIN2_PLL_SWITCH(REG_CLKSWITCH1, 7), BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 8), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 9), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "audio0", .parent_ids = (const u8 []){ AUDIO_FAST_PLL }, .num_parents = 1, .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 22), BERLIN2_DIV_SELECT(REG_CLKSELECT2, 17), BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 10), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 11), }, .div_flags = BERLIN2_DIV_HAS_GATE, .flags = 0, }, { .name = "audio2", .parent_ids = (const u8 []){ AUDIO_FAST_PLL }, .num_parents = 1, .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 24), BERLIN2_DIV_SELECT(REG_CLKSELECT2, 20), BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 14), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 15), }, .div_flags = BERLIN2_DIV_HAS_GATE, .flags = 0, }, { .name = "audio3", .parent_ids = (const u8 []){ AUDIO_FAST_PLL }, .num_parents = 1, .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 25), BERLIN2_DIV_SELECT(REG_CLKSELECT2, 23), BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 16), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 17), }, .div_flags = BERLIN2_DIV_HAS_GATE, .flags = 0, }, { .name = "audio1", .parent_ids = (const u8 []){ AUDIO1_PLL }, .num_parents = 1, .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 23), BERLIN2_DIV_SELECT(REG_CLKSELECT3, 0), BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 12), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 13), }, .div_flags = BERLIN2_DIV_HAS_GATE, .flags = 0, }, { .name = "gfx3d_core", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_SINGLE_DIV(REG_GFX3DCORE_CLKCTL), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "gfx3d_sys", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_SINGLE_DIV(REG_GFX3DSYS_CLKCTL), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "arc", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_SINGLE_DIV(REG_ARC_CLKCTL), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "vip", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_SINGLE_DIV(REG_VIP_CLKCTL), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "sdio0xin", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_SINGLE_DIV(REG_SDIO0XIN_CLKCTL), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "sdio1xin", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_SINGLE_DIV(REG_SDIO1XIN_CLKCTL), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "gfx3d_extra", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_SINGLE_DIV(REG_GFX3DEXTRA_CLKCTL), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "gc360", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_SINGLE_DIV(REG_GC360_CLKCTL), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "sdio_dllmst", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_SINGLE_DIV(REG_SDIO_DLLMST_CLKCTL), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, }; static const struct berlin2_gate_data bg2_gates[] __initconst = { { "geth0", "perif", 7 }, { "geth1", "perif", 8 }, { "sata", "perif", 9 }, { "ahbapb", "perif", 10, CLK_IGNORE_UNUSED }, { "usb0", "perif", 11 }, { "usb1", "perif", 12 }, { "pbridge", "perif", 13, CLK_IGNORE_UNUSED }, { "sdio0", "perif", 14 }, { "sdio1", "perif", 15 }, { "nfc", "perif", 17 }, { "smemc", "perif", 19 }, { "audiohd", "audiohd_pll", 26 }, { "video0", "video0_in", 27 }, { "video1", "video1_in", 28 }, { "video2", "video2_in", 29 }, }; static void __init berlin2_clock_setup(struct device_node *np) { struct device_node *parent_np = of_get_parent(np); const char *parent_names[9]; struct clk *clk; struct clk_hw *hw; struct clk_hw **hws; u8 avpll_flags = 0; int n, ret; clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL); if (!clk_data) { of_node_put(parent_np); return; } clk_data->num = MAX_CLKS; hws = clk_data->hws; gbase = of_iomap(parent_np, 0); of_node_put(parent_np); if (!gbase) return; /* overwrite default clock names with DT provided ones */ clk = of_clk_get_by_name(np, clk_names[REFCLK]); if (!IS_ERR(clk)) { clk_names[REFCLK] = __clk_get_name(clk); clk_put(clk); } clk = of_clk_get_by_name(np, clk_names[VIDEO_EXT0]); if (!IS_ERR(clk)) { clk_names[VIDEO_EXT0] = __clk_get_name(clk); clk_put(clk); } /* simple register PLLs */ ret = berlin2_pll_register(&bg2_pll_map, gbase + REG_SYSPLLCTL0, clk_names[SYSPLL], clk_names[REFCLK], 0); if (ret) goto bg2_fail; ret = berlin2_pll_register(&bg2_pll_map, gbase + REG_MEMPLLCTL0, clk_names[MEMPLL], clk_names[REFCLK], 0); if (ret) goto bg2_fail; ret = berlin2_pll_register(&bg2_pll_map, gbase + REG_CPUPLLCTL0, clk_names[CPUPLL], clk_names[REFCLK], 0); if (ret) goto bg2_fail; if (of_device_is_compatible(np, "marvell,berlin2-global-register")) avpll_flags |= BERLIN2_AVPLL_SCRAMBLE_QUIRK; /* audio/video VCOs */ ret = berlin2_avpll_vco_register(gbase + REG_AVPLLCTL0, "avpll_vcoA", clk_names[REFCLK], avpll_flags, 0); if (ret) goto bg2_fail; for (n = 0; n < 8; n++) { ret = berlin2_avpll_channel_register(gbase + REG_AVPLLCTL0, clk_names[AVPLL_A1 + n], n, "avpll_vcoA", avpll_flags, 0); if (ret) goto bg2_fail; } ret = berlin2_avpll_vco_register(gbase + REG_AVPLLCTL31, "avpll_vcoB", clk_names[REFCLK], BERLIN2_AVPLL_BIT_QUIRK | avpll_flags, 0); if (ret) goto bg2_fail; for (n = 0; n < 8; n++) { ret = berlin2_avpll_channel_register(gbase + REG_AVPLLCTL31, clk_names[AVPLL_B1 + n], n, "avpll_vcoB", BERLIN2_AVPLL_BIT_QUIRK | avpll_flags, 0); if (ret) goto bg2_fail; } /* reference clock bypass switches */ parent_names[0] = clk_names[SYSPLL]; parent_names[1] = clk_names[REFCLK]; hw = clk_hw_register_mux(NULL, "syspll_byp", parent_names, 2, 0, gbase + REG_CLKSWITCH0, 0, 1, 0, &lock); if (IS_ERR(hw)) goto bg2_fail; clk_names[SYSPLL] = clk_hw_get_name(hw); parent_names[0] = clk_names[MEMPLL]; parent_names[1] = clk_names[REFCLK]; hw = clk_hw_register_mux(NULL, "mempll_byp", parent_names, 2, 0, gbase + REG_CLKSWITCH0, 1, 1, 0, &lock); if (IS_ERR(hw)) goto bg2_fail; clk_names[MEMPLL] = clk_hw_get_name(hw); parent_names[0] = clk_names[CPUPLL]; parent_names[1] = clk_names[REFCLK]; hw = clk_hw_register_mux(NULL, "cpupll_byp", parent_names, 2, 0, gbase + REG_CLKSWITCH0, 2, 1, 0, &lock); if (IS_ERR(hw)) goto bg2_fail; clk_names[CPUPLL] = clk_hw_get_name(hw); /* clock muxes */ parent_names[0] = clk_names[AVPLL_B3]; parent_names[1] = clk_names[AVPLL_A3]; hw = clk_hw_register_mux(NULL, clk_names[AUDIO1_PLL], parent_names, 2, 0, gbase + REG_CLKSELECT2, 29, 1, 0, &lock); if (IS_ERR(hw)) goto bg2_fail; parent_names[0] = clk_names[VIDEO0_PLL]; parent_names[1] = clk_names[VIDEO_EXT0]; hw = clk_hw_register_mux(NULL, clk_names[VIDEO0_IN], parent_names, 2, 0, gbase + REG_CLKSELECT3, 4, 1, 0, &lock); if (IS_ERR(hw)) goto bg2_fail; parent_names[0] = clk_names[VIDEO1_PLL]; parent_names[1] = clk_names[VIDEO_EXT0]; hw = clk_hw_register_mux(NULL, clk_names[VIDEO1_IN], parent_names, 2, 0, gbase + REG_CLKSELECT3, 6, 1, 0, &lock); if (IS_ERR(hw)) goto bg2_fail; parent_names[0] = clk_names[AVPLL_A2]; parent_names[1] = clk_names[AVPLL_B2]; hw = clk_hw_register_mux(NULL, clk_names[VIDEO1_PLL], parent_names, 2, 0, gbase + REG_CLKSELECT3, 7, 1, 0, &lock); if (IS_ERR(hw)) goto bg2_fail; parent_names[0] = clk_names[VIDEO2_PLL]; parent_names[1] = clk_names[VIDEO_EXT0]; hw = clk_hw_register_mux(NULL, clk_names[VIDEO2_IN], parent_names, 2, 0, gbase + REG_CLKSELECT3, 9, 1, 0, &lock); if (IS_ERR(hw)) goto bg2_fail; parent_names[0] = clk_names[AVPLL_B1]; parent_names[1] = clk_names[AVPLL_A5]; hw = clk_hw_register_mux(NULL, clk_names[VIDEO2_PLL], parent_names, 2, 0, gbase + REG_CLKSELECT3, 10, 1, 0, &lock); if (IS_ERR(hw)) goto bg2_fail; /* clock divider cells */ for (n = 0; n < ARRAY_SIZE(bg2_divs); n++) { const struct berlin2_div_data *dd = &bg2_divs[n]; int k; for (k = 0; k < dd->num_parents; k++) parent_names[k] = clk_names[dd->parent_ids[k]]; hws[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase, dd->name, dd->div_flags, parent_names, dd->num_parents, dd->flags, &lock); } /* clock gate cells */ for (n = 0; n < ARRAY_SIZE(bg2_gates); n++) { const struct berlin2_gate_data *gd = &bg2_gates[n]; hws[CLKID_GETH0 + n] = clk_hw_register_gate(NULL, gd->name, gd->parent_name, gd->flags, gbase + REG_CLKENABLE, gd->bit_idx, 0, &lock); } /* twdclk is derived from cpu/3 */ hws[CLKID_TWD] = clk_hw_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3); /* check for errors on leaf clocks */ for (n = 0; n < MAX_CLKS; n++) { if (!IS_ERR(hws[n])) continue; pr_err("%pOF: Unable to register leaf clock %d\n", np, n); goto bg2_fail; } /* register clk-provider */ of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); return; bg2_fail: iounmap(gbase); } CLK_OF_DECLARE(berlin2_clk, "marvell,berlin2-clk", berlin2_clock_setup);
linux-master
drivers/clk/berlin/bg2.c
// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2014 Marvell Technology Group Ltd. * * Alexandre Belloni <[email protected]> * Sebastian Hesselbarth <[email protected]> */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/slab.h> #include <dt-bindings/clock/berlin2q.h> #include "berlin2-div.h" #include "berlin2-pll.h" #include "common.h" #define REG_PINMUX0 0x0018 #define REG_PINMUX5 0x002c #define REG_SYSPLLCTL0 0x0030 #define REG_SYSPLLCTL4 0x0040 #define REG_CLKENABLE 0x00e8 #define REG_CLKSELECT0 0x00ec #define REG_CLKSELECT1 0x00f0 #define REG_CLKSELECT2 0x00f4 #define REG_CLKSWITCH0 0x00f8 #define REG_CLKSWITCH1 0x00fc #define REG_SW_GENERIC0 0x0110 #define REG_SW_GENERIC3 0x011c #define REG_SDIO0XIN_CLKCTL 0x0158 #define REG_SDIO1XIN_CLKCTL 0x015c #define MAX_CLKS 28 static struct clk_hw_onecell_data *clk_data; static DEFINE_SPINLOCK(lock); static void __iomem *gbase; static void __iomem *cpupll_base; enum { REFCLK, SYSPLL, CPUPLL, AVPLL_B1, AVPLL_B2, AVPLL_B3, AVPLL_B4, AVPLL_B5, AVPLL_B6, AVPLL_B7, AVPLL_B8, }; static const char *clk_names[] = { [REFCLK] = "refclk", [SYSPLL] = "syspll", [CPUPLL] = "cpupll", [AVPLL_B1] = "avpll_b1", [AVPLL_B2] = "avpll_b2", [AVPLL_B3] = "avpll_b3", [AVPLL_B4] = "avpll_b4", [AVPLL_B5] = "avpll_b5", [AVPLL_B6] = "avpll_b6", [AVPLL_B7] = "avpll_b7", [AVPLL_B8] = "avpll_b8", }; static const struct berlin2_pll_map bg2q_pll_map __initconst = { .vcodiv = {1, 0, 2, 0, 3, 4, 0, 6, 8}, .mult = 1, .fbdiv_shift = 7, .rfdiv_shift = 2, .divsel_shift = 9, }; static const u8 default_parent_ids[] = { SYSPLL, AVPLL_B4, AVPLL_B5, AVPLL_B6, AVPLL_B7, SYSPLL }; static const struct berlin2_div_data bg2q_divs[] __initconst = { { .name = "sys", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 0), BERLIN2_PLL_SELECT(REG_CLKSELECT0, 0), BERLIN2_DIV_SELECT(REG_CLKSELECT0, 3), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 3), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 4), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 5), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = CLK_IGNORE_UNUSED, }, { .name = "drmfigo", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 17), BERLIN2_PLL_SELECT(REG_CLKSELECT0, 6), BERLIN2_DIV_SELECT(REG_CLKSELECT0, 9), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 6), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 7), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 8), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "cfg", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 1), BERLIN2_PLL_SELECT(REG_CLKSELECT0, 12), BERLIN2_DIV_SELECT(REG_CLKSELECT0, 15), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 9), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 10), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 11), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "gfx2d", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 4), BERLIN2_PLL_SELECT(REG_CLKSELECT0, 18), BERLIN2_DIV_SELECT(REG_CLKSELECT0, 21), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 12), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 13), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 14), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "zsp", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 6), BERLIN2_PLL_SELECT(REG_CLKSELECT0, 24), BERLIN2_DIV_SELECT(REG_CLKSELECT0, 27), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 15), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 16), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 17), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "perif", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 7), BERLIN2_PLL_SELECT(REG_CLKSELECT1, 0), BERLIN2_DIV_SELECT(REG_CLKSELECT1, 3), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 18), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 19), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 20), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = CLK_IGNORE_UNUSED, }, { .name = "pcube", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 2), BERLIN2_PLL_SELECT(REG_CLKSELECT1, 6), BERLIN2_DIV_SELECT(REG_CLKSELECT1, 9), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 21), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 22), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 23), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "vscope", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 3), BERLIN2_PLL_SELECT(REG_CLKSELECT1, 12), BERLIN2_DIV_SELECT(REG_CLKSELECT1, 15), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 24), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 25), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 26), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "nfc_ecc", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 19), BERLIN2_PLL_SELECT(REG_CLKSELECT1, 18), BERLIN2_DIV_SELECT(REG_CLKSELECT1, 21), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 27), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 28), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 29), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "vpp", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 21), BERLIN2_PLL_SELECT(REG_CLKSELECT1, 24), BERLIN2_DIV_SELECT(REG_CLKSELECT1, 27), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 30), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 31), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 0), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "app", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 20), BERLIN2_PLL_SELECT(REG_CLKSELECT2, 0), BERLIN2_DIV_SELECT(REG_CLKSELECT2, 3), BERLIN2_PLL_SWITCH(REG_CLKSWITCH1, 1), BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 2), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 3), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "sdio0xin", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_SINGLE_DIV(REG_SDIO0XIN_CLKCTL), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, { .name = "sdio1xin", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_SINGLE_DIV(REG_SDIO1XIN_CLKCTL), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = 0, }, }; static const struct berlin2_gate_data bg2q_gates[] __initconst = { { "gfx2daxi", "perif", 5 }, { "geth0", "perif", 8 }, { "sata", "perif", 9 }, { "ahbapb", "perif", 10, CLK_IGNORE_UNUSED }, { "usb0", "perif", 11 }, { "usb1", "perif", 12 }, { "usb2", "perif", 13 }, { "usb3", "perif", 14 }, { "pbridge", "perif", 15, CLK_IGNORE_UNUSED }, { "sdio", "perif", 16 }, { "nfc", "perif", 18 }, { "pcie", "perif", 22 }, }; static void __init berlin2q_clock_setup(struct device_node *np) { struct device_node *parent_np = of_get_parent(np); const char *parent_names[9]; struct clk *clk; struct clk_hw **hws; int n, ret; clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL); if (!clk_data) { of_node_put(parent_np); return; } clk_data->num = MAX_CLKS; hws = clk_data->hws; gbase = of_iomap(parent_np, 0); if (!gbase) { of_node_put(parent_np); pr_err("%pOF: Unable to map global base\n", np); return; } /* BG2Q CPU PLL is not part of global registers */ cpupll_base = of_iomap(parent_np, 1); of_node_put(parent_np); if (!cpupll_base) { pr_err("%pOF: Unable to map cpupll base\n", np); iounmap(gbase); return; } /* overwrite default clock names with DT provided ones */ clk = of_clk_get_by_name(np, clk_names[REFCLK]); if (!IS_ERR(clk)) { clk_names[REFCLK] = __clk_get_name(clk); clk_put(clk); } /* simple register PLLs */ ret = berlin2_pll_register(&bg2q_pll_map, gbase + REG_SYSPLLCTL0, clk_names[SYSPLL], clk_names[REFCLK], 0); if (ret) goto bg2q_fail; ret = berlin2_pll_register(&bg2q_pll_map, cpupll_base, clk_names[CPUPLL], clk_names[REFCLK], 0); if (ret) goto bg2q_fail; /* TODO: add BG2Q AVPLL */ /* * TODO: add reference clock bypass switches: * memPLLSWBypass, cpuPLLSWBypass, and sysPLLSWBypass */ /* clock divider cells */ for (n = 0; n < ARRAY_SIZE(bg2q_divs); n++) { const struct berlin2_div_data *dd = &bg2q_divs[n]; int k; for (k = 0; k < dd->num_parents; k++) parent_names[k] = clk_names[dd->parent_ids[k]]; hws[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase, dd->name, dd->div_flags, parent_names, dd->num_parents, dd->flags, &lock); } /* clock gate cells */ for (n = 0; n < ARRAY_SIZE(bg2q_gates); n++) { const struct berlin2_gate_data *gd = &bg2q_gates[n]; hws[CLKID_GFX2DAXI + n] = clk_hw_register_gate(NULL, gd->name, gd->parent_name, gd->flags, gbase + REG_CLKENABLE, gd->bit_idx, 0, &lock); } /* cpuclk divider is fixed to 1 */ hws[CLKID_CPU] = clk_hw_register_fixed_factor(NULL, "cpu", clk_names[CPUPLL], 0, 1, 1); /* twdclk is derived from cpu/3 */ hws[CLKID_TWD] = clk_hw_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3); /* check for errors on leaf clocks */ for (n = 0; n < MAX_CLKS; n++) { if (!IS_ERR(hws[n])) continue; pr_err("%pOF: Unable to register leaf clock %d\n", np, n); goto bg2q_fail; } /* register clk-provider */ of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); return; bg2q_fail: iounmap(cpupll_base); iounmap(gbase); } CLK_OF_DECLARE(berlin2q_clk, "marvell,berlin2q-clk", berlin2q_clock_setup);
linux-master
drivers/clk/berlin/bg2q.c
// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2014 Marvell Technology Group Ltd. * * Alexandre Belloni <[email protected]> * Sebastian Hesselbarth <[email protected]> */ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/slab.h> #include <asm/div64.h> #include "berlin2-div.h" #include "berlin2-pll.h" struct berlin2_pll { struct clk_hw hw; void __iomem *base; struct berlin2_pll_map map; }; #define to_berlin2_pll(hw) container_of(hw, struct berlin2_pll, hw) #define SPLL_CTRL0 0x00 #define SPLL_CTRL1 0x04 #define SPLL_CTRL2 0x08 #define SPLL_CTRL3 0x0c #define SPLL_CTRL4 0x10 #define FBDIV_MASK 0x1ff #define RFDIV_MASK 0x1f #define DIVSEL_MASK 0xf /* * The output frequency formula for the pll is: * clkout = fbdiv / refdiv * parent / vcodiv */ static unsigned long berlin2_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct berlin2_pll *pll = to_berlin2_pll(hw); struct berlin2_pll_map *map = &pll->map; u32 val, fbdiv, rfdiv, vcodivsel, vcodiv; u64 rate = parent_rate; val = readl_relaxed(pll->base + SPLL_CTRL0); fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK; rfdiv = (val >> map->rfdiv_shift) & RFDIV_MASK; if (rfdiv == 0) { pr_warn("%s has zero rfdiv\n", clk_hw_get_name(hw)); rfdiv = 1; } val = readl_relaxed(pll->base + SPLL_CTRL1); vcodivsel = (val >> map->divsel_shift) & DIVSEL_MASK; vcodiv = map->vcodiv[vcodivsel]; if (vcodiv == 0) { pr_warn("%s has zero vcodiv (index %d)\n", clk_hw_get_name(hw), vcodivsel); vcodiv = 1; } rate *= fbdiv * map->mult; do_div(rate, rfdiv * vcodiv); return (unsigned long)rate; } static const struct clk_ops berlin2_pll_ops = { .recalc_rate = berlin2_pll_recalc_rate, }; int __init berlin2_pll_register(const struct berlin2_pll_map *map, void __iomem *base, const char *name, const char *parent_name, unsigned long flags) { struct clk_init_data init; struct berlin2_pll *pll; pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) return -ENOMEM; /* copy pll_map to allow __initconst */ memcpy(&pll->map, map, sizeof(*map)); pll->base = base; pll->hw.init = &init; init.name = name; init.ops = &berlin2_pll_ops; init.parent_names = &parent_name; init.num_parents = 1; init.flags = flags; return clk_hw_register(NULL, &pll->hw); }
linux-master
drivers/clk/berlin/berlin2-pll.c
// SPDX-License-Identifier: GPL-2.0 /* * Ingenic JZ4725B SoC CGU driver * * Copyright (C) 2018 Paul Cercueil * Author: Paul Cercueil <[email protected]> */ #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/of.h> #include <dt-bindings/clock/ingenic,jz4725b-cgu.h> #include "cgu.h" #include "pm.h" /* CGU register offsets */ #define CGU_REG_CPCCR 0x00 #define CGU_REG_LCR 0x04 #define CGU_REG_CPPCR 0x10 #define CGU_REG_CLKGR 0x20 #define CGU_REG_OPCR 0x24 #define CGU_REG_I2SCDR 0x60 #define CGU_REG_LPCDR 0x64 #define CGU_REG_MSCCDR 0x68 #define CGU_REG_SSICDR 0x74 #define CGU_REG_CIMCDR 0x78 /* bits within the LCR register */ #define LCR_SLEEP BIT(0) static struct ingenic_cgu *cgu; static const s8 pll_od_encoding[4] = { 0x0, 0x1, -1, 0x3, }; static const u8 jz4725b_cgu_cpccr_div_table[] = { 1, 2, 3, 4, 6, 8, }; static const u8 jz4725b_cgu_pll_half_div_table[] = { 2, 1, }; static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { /* External clocks */ [JZ4725B_CLK_EXT] = { "ext", CGU_CLK_EXT }, [JZ4725B_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT }, [JZ4725B_CLK_PLL] = { "pll", CGU_CLK_PLL, .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, .pll = { .reg = CGU_REG_CPPCR, .rate_multiplier = 1, .m_shift = 23, .m_bits = 9, .m_offset = 2, .n_shift = 18, .n_bits = 5, .n_offset = 2, .od_shift = 16, .od_bits = 2, .od_max = 4, .od_encoding = pll_od_encoding, .stable_bit = 10, .bypass_reg = CGU_REG_CPPCR, .bypass_bit = 9, .enable_bit = 8, }, }, /* Muxes & dividers */ [JZ4725B_CLK_PLL_HALF] = { "pll half", CGU_CLK_DIV, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0, jz4725b_cgu_pll_half_div_table, }, }, [JZ4725B_CLK_CCLK] = { "cclk", CGU_CLK_DIV, /* * Disabling the CPU clock or any parent clocks will hang the * system; mark it critical. */ .flags = CLK_IS_CRITICAL, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, jz4725b_cgu_cpccr_div_table, }, }, [JZ4725B_CLK_HCLK] = { "hclk", CGU_CLK_DIV, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, jz4725b_cgu_cpccr_div_table, }, }, [JZ4725B_CLK_PCLK] = { "pclk", CGU_CLK_DIV, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, jz4725b_cgu_cpccr_div_table, }, }, [JZ4725B_CLK_MCLK] = { "mclk", CGU_CLK_DIV, /* * Disabling MCLK or its parents will render DRAM * inaccessible; mark it critical. */ .flags = CLK_IS_CRITICAL, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, jz4725b_cgu_cpccr_div_table, }, }, [JZ4725B_CLK_IPU] = { "ipu", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0, jz4725b_cgu_cpccr_div_table, }, .gate = { CGU_REG_CLKGR, 13 }, }, [JZ4725B_CLK_LCD] = { "lcd", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 }, .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 9 }, }, [JZ4725B_CLK_I2S] = { "i2s", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 }, .mux = { CGU_REG_CPCCR, 31, 1 }, .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, }, [JZ4725B_CLK_SPI] = { "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 }, .mux = { CGU_REG_SSICDR, 31, 1 }, .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 4 }, }, [JZ4725B_CLK_MMC_MUX] = { "mmc_mux", CGU_CLK_DIV, .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 }, .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 }, }, [JZ4725B_CLK_UDC] = { "udc", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 }, .mux = { CGU_REG_CPCCR, 29, 1 }, .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, }, /* Gate-only clocks */ [JZ4725B_CLK_UART] = { "uart", CGU_CLK_GATE, .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 0 }, }, [JZ4725B_CLK_DMA] = { "dma", CGU_CLK_GATE, .parents = { JZ4725B_CLK_PCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 12 }, }, [JZ4725B_CLK_ADC] = { "adc", CGU_CLK_GATE, .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 7 }, }, [JZ4725B_CLK_I2C] = { "i2c", CGU_CLK_GATE, .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 3 }, }, [JZ4725B_CLK_AIC] = { "aic", CGU_CLK_GATE, .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 5 }, }, [JZ4725B_CLK_MMC0] = { "mmc0", CGU_CLK_GATE, .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 6 }, }, [JZ4725B_CLK_MMC1] = { "mmc1", CGU_CLK_GATE, .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 16 }, }, [JZ4725B_CLK_BCH] = { "bch", CGU_CLK_GATE, .parents = { JZ4725B_CLK_MCLK/* not sure */, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 11 }, }, [JZ4725B_CLK_TCU] = { "tcu", CGU_CLK_GATE, .parents = { JZ4725B_CLK_EXT/* not sure */, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 1 }, }, [JZ4725B_CLK_EXT512] = { "ext/512", CGU_CLK_FIXDIV, .parents = { JZ4725B_CLK_EXT }, /* Doc calls it EXT512, but it seems to be /256... */ .fixdiv = { 256 }, }, [JZ4725B_CLK_RTC] = { "rtc", CGU_CLK_MUX, .parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 }, .mux = { CGU_REG_OPCR, 2, 1}, }, [JZ4725B_CLK_UDC_PHY] = { "udc_phy", CGU_CLK_GATE, .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, .gate = { CGU_REG_OPCR, 6, true }, }, }; static void __init jz4725b_cgu_init(struct device_node *np) { int retval; cgu = ingenic_cgu_new(jz4725b_cgu_clocks, ARRAY_SIZE(jz4725b_cgu_clocks), np); if (!cgu) { pr_err("%s: failed to initialise CGU\n", __func__); return; } retval = ingenic_cgu_register_clocks(cgu); if (retval) pr_err("%s: failed to register CGU Clocks\n", __func__); ingenic_cgu_register_syscore_ops(cgu); } CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);
linux-master
drivers/clk/ingenic/jz4725b-cgu.c
// SPDX-License-Identifier: GPL-2.0 /* * JZ47xx SoCs TCU clocks driver * Copyright (C) 2019 Paul Cercueil <[email protected]> */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/clockchips.h> #include <linux/mfd/ingenic-tcu.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include <linux/slab.h> #include <linux/syscore_ops.h> #include <dt-bindings/clock/ingenic,tcu.h> /* 8 channels max + watchdog + OST */ #define TCU_CLK_COUNT 10 #undef pr_fmt #define pr_fmt(fmt) "ingenic-tcu-clk: " fmt enum tcu_clk_parent { TCU_PARENT_PCLK, TCU_PARENT_RTC, TCU_PARENT_EXT, }; struct ingenic_soc_info { unsigned int num_channels; bool has_ost; bool has_tcu_clk; bool allow_missing_tcu_clk; }; struct ingenic_tcu_clk_info { struct clk_init_data init_data; u8 gate_bit; u8 tcsr_reg; }; struct ingenic_tcu_clk { struct clk_hw hw; unsigned int idx; struct ingenic_tcu *tcu; const struct ingenic_tcu_clk_info *info; }; struct ingenic_tcu { const struct ingenic_soc_info *soc_info; struct regmap *map; struct clk *clk; struct clk_hw_onecell_data *clocks; }; static struct ingenic_tcu *ingenic_tcu; static inline struct ingenic_tcu_clk *to_tcu_clk(struct clk_hw *hw) { return container_of(hw, struct ingenic_tcu_clk, hw); } static int ingenic_tcu_enable(struct clk_hw *hw) { struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw); const struct ingenic_tcu_clk_info *info = tcu_clk->info; struct ingenic_tcu *tcu = tcu_clk->tcu; regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit)); return 0; } static void ingenic_tcu_disable(struct clk_hw *hw) { struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw); const struct ingenic_tcu_clk_info *info = tcu_clk->info; struct ingenic_tcu *tcu = tcu_clk->tcu; regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit)); } static int ingenic_tcu_is_enabled(struct clk_hw *hw) { struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw); const struct ingenic_tcu_clk_info *info = tcu_clk->info; unsigned int value; regmap_read(tcu_clk->tcu->map, TCU_REG_TSR, &value); return !(value & BIT(info->gate_bit)); } static bool ingenic_tcu_enable_regs(struct clk_hw *hw) { struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw); const struct ingenic_tcu_clk_info *info = tcu_clk->info; struct ingenic_tcu *tcu = tcu_clk->tcu; bool enabled = false; /* * According to the programming manual, a timer channel's registers can * only be accessed when the channel's stop bit is clear. */ enabled = !!ingenic_tcu_is_enabled(hw); regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit)); return enabled; } static void ingenic_tcu_disable_regs(struct clk_hw *hw) { struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw); const struct ingenic_tcu_clk_info *info = tcu_clk->info; struct ingenic_tcu *tcu = tcu_clk->tcu; regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit)); } static u8 ingenic_tcu_get_parent(struct clk_hw *hw) { struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw); const struct ingenic_tcu_clk_info *info = tcu_clk->info; unsigned int val = 0; int ret; ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &val); WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx); return ffs(val & TCU_TCSR_PARENT_CLOCK_MASK) - 1; } static int ingenic_tcu_set_parent(struct clk_hw *hw, u8 idx) { struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw); const struct ingenic_tcu_clk_info *info = tcu_clk->info; bool was_enabled; int ret; was_enabled = ingenic_tcu_enable_regs(hw); ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg, TCU_TCSR_PARENT_CLOCK_MASK, BIT(idx)); WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx); if (!was_enabled) ingenic_tcu_disable_regs(hw); return 0; } static unsigned long ingenic_tcu_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw); const struct ingenic_tcu_clk_info *info = tcu_clk->info; unsigned int prescale; int ret; ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &prescale); WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx); prescale = (prescale & TCU_TCSR_PRESCALE_MASK) >> TCU_TCSR_PRESCALE_LSB; return parent_rate >> (prescale * 2); } static u8 ingenic_tcu_get_prescale(unsigned long rate, unsigned long req_rate) { u8 prescale; for (prescale = 0; prescale < 5; prescale++) if ((rate >> (prescale * 2)) <= req_rate) return prescale; return 5; /* /1024 divider */ } static int ingenic_tcu_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { unsigned long rate = req->best_parent_rate; u8 prescale; if (req->rate > rate) { req->rate = rate; return 0; } prescale = ingenic_tcu_get_prescale(rate, req->rate); req->rate = rate >> (prescale * 2); return 0; } static int ingenic_tcu_set_rate(struct clk_hw *hw, unsigned long req_rate, unsigned long parent_rate) { struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw); const struct ingenic_tcu_clk_info *info = tcu_clk->info; u8 prescale = ingenic_tcu_get_prescale(parent_rate, req_rate); bool was_enabled; int ret; was_enabled = ingenic_tcu_enable_regs(hw); ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg, TCU_TCSR_PRESCALE_MASK, prescale << TCU_TCSR_PRESCALE_LSB); WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx); if (!was_enabled) ingenic_tcu_disable_regs(hw); return 0; } static const struct clk_ops ingenic_tcu_clk_ops = { .get_parent = ingenic_tcu_get_parent, .set_parent = ingenic_tcu_set_parent, .recalc_rate = ingenic_tcu_recalc_rate, .determine_rate = ingenic_tcu_determine_rate, .set_rate = ingenic_tcu_set_rate, .enable = ingenic_tcu_enable, .disable = ingenic_tcu_disable, .is_enabled = ingenic_tcu_is_enabled, }; static const char * const ingenic_tcu_timer_parents[] = { [TCU_PARENT_PCLK] = "pclk", [TCU_PARENT_RTC] = "rtc", [TCU_PARENT_EXT] = "ext", }; #define DEF_TIMER(_name, _gate_bit, _tcsr) \ { \ .init_data = { \ .name = _name, \ .parent_names = ingenic_tcu_timer_parents, \ .num_parents = ARRAY_SIZE(ingenic_tcu_timer_parents),\ .ops = &ingenic_tcu_clk_ops, \ .flags = CLK_SET_RATE_UNGATE, \ }, \ .gate_bit = _gate_bit, \ .tcsr_reg = _tcsr, \ } static const struct ingenic_tcu_clk_info ingenic_tcu_clk_info[] = { [TCU_CLK_TIMER0] = DEF_TIMER("timer0", 0, TCU_REG_TCSRc(0)), [TCU_CLK_TIMER1] = DEF_TIMER("timer1", 1, TCU_REG_TCSRc(1)), [TCU_CLK_TIMER2] = DEF_TIMER("timer2", 2, TCU_REG_TCSRc(2)), [TCU_CLK_TIMER3] = DEF_TIMER("timer3", 3, TCU_REG_TCSRc(3)), [TCU_CLK_TIMER4] = DEF_TIMER("timer4", 4, TCU_REG_TCSRc(4)), [TCU_CLK_TIMER5] = DEF_TIMER("timer5", 5, TCU_REG_TCSRc(5)), [TCU_CLK_TIMER6] = DEF_TIMER("timer6", 6, TCU_REG_TCSRc(6)), [TCU_CLK_TIMER7] = DEF_TIMER("timer7", 7, TCU_REG_TCSRc(7)), }; static const struct ingenic_tcu_clk_info ingenic_tcu_watchdog_clk_info = DEF_TIMER("wdt", 16, TCU_REG_WDT_TCSR); static const struct ingenic_tcu_clk_info ingenic_tcu_ost_clk_info = DEF_TIMER("ost", 15, TCU_REG_OST_TCSR); #undef DEF_TIMER static int __init ingenic_tcu_register_clock(struct ingenic_tcu *tcu, unsigned int idx, enum tcu_clk_parent parent, const struct ingenic_tcu_clk_info *info, struct clk_hw_onecell_data *clocks) { struct ingenic_tcu_clk *tcu_clk; int err; tcu_clk = kzalloc(sizeof(*tcu_clk), GFP_KERNEL); if (!tcu_clk) return -ENOMEM; tcu_clk->hw.init = &info->init_data; tcu_clk->idx = idx; tcu_clk->info = info; tcu_clk->tcu = tcu; /* Reset channel and clock divider, set default parent */ ingenic_tcu_enable_regs(&tcu_clk->hw); regmap_update_bits(tcu->map, info->tcsr_reg, 0xffff, BIT(parent)); ingenic_tcu_disable_regs(&tcu_clk->hw); err = clk_hw_register(NULL, &tcu_clk->hw); if (err) { kfree(tcu_clk); return err; } clocks->hws[idx] = &tcu_clk->hw; return 0; } static const struct ingenic_soc_info jz4740_soc_info = { .num_channels = 8, .has_ost = false, .has_tcu_clk = true, }; static const struct ingenic_soc_info jz4725b_soc_info = { .num_channels = 6, .has_ost = true, .has_tcu_clk = true, }; static const struct ingenic_soc_info jz4770_soc_info = { .num_channels = 8, .has_ost = true, .has_tcu_clk = false, }; static const struct ingenic_soc_info x1000_soc_info = { .num_channels = 8, .has_ost = false, /* X1000 has OST, but it not belong TCU */ .has_tcu_clk = true, .allow_missing_tcu_clk = true, }; static const struct of_device_id __maybe_unused ingenic_tcu_of_match[] __initconst = { { .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, }, { .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, }, { .compatible = "ingenic,jz4760-tcu", .data = &jz4770_soc_info, }, { .compatible = "ingenic,jz4770-tcu", .data = &jz4770_soc_info, }, { .compatible = "ingenic,x1000-tcu", .data = &x1000_soc_info, }, { /* sentinel */ } }; static int __init ingenic_tcu_probe(struct device_node *np) { const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np); struct ingenic_tcu *tcu; struct regmap *map; unsigned int i; int ret; map = device_node_to_regmap(np); if (IS_ERR(map)) return PTR_ERR(map); tcu = kzalloc(sizeof(*tcu), GFP_KERNEL); if (!tcu) return -ENOMEM; tcu->map = map; tcu->soc_info = id->data; if (tcu->soc_info->has_tcu_clk) { tcu->clk = of_clk_get_by_name(np, "tcu"); if (IS_ERR(tcu->clk)) { ret = PTR_ERR(tcu->clk); /* * Old device trees for some SoCs did not include the * TCU clock because this driver (incorrectly) didn't * use it. In this case we complain loudly and attempt * to continue without the clock, which might work if * booting with workarounds like "clk_ignore_unused". */ if (tcu->soc_info->allow_missing_tcu_clk && ret == -EINVAL) { pr_warn("TCU clock missing from device tree, please update your device tree\n"); tcu->clk = NULL; } else { pr_crit("Cannot get TCU clock from device tree\n"); goto err_free_tcu; } } else { ret = clk_prepare_enable(tcu->clk); if (ret) { pr_crit("Unable to enable TCU clock\n"); goto err_put_clk; } } } tcu->clocks = kzalloc(struct_size(tcu->clocks, hws, TCU_CLK_COUNT), GFP_KERNEL); if (!tcu->clocks) { ret = -ENOMEM; goto err_clk_disable; } tcu->clocks->num = TCU_CLK_COUNT; for (i = 0; i < tcu->soc_info->num_channels; i++) { ret = ingenic_tcu_register_clock(tcu, i, TCU_PARENT_EXT, &ingenic_tcu_clk_info[i], tcu->clocks); if (ret) { pr_crit("cannot register clock %d\n", i); goto err_unregister_timer_clocks; } } /* * We set EXT as the default parent clock for all the TCU clocks * except for the watchdog one, where we set the RTC clock as the * parent. Since the EXT and PCLK are much faster than the RTC clock, * the watchdog would kick after a maximum time of 5s, and we might * want a slower kicking time. */ ret = ingenic_tcu_register_clock(tcu, TCU_CLK_WDT, TCU_PARENT_RTC, &ingenic_tcu_watchdog_clk_info, tcu->clocks); if (ret) { pr_crit("cannot register watchdog clock\n"); goto err_unregister_timer_clocks; } if (tcu->soc_info->has_ost) { ret = ingenic_tcu_register_clock(tcu, TCU_CLK_OST, TCU_PARENT_EXT, &ingenic_tcu_ost_clk_info, tcu->clocks); if (ret) { pr_crit("cannot register ost clock\n"); goto err_unregister_watchdog_clock; } } ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, tcu->clocks); if (ret) { pr_crit("cannot add OF clock provider\n"); goto err_unregister_ost_clock; } ingenic_tcu = tcu; return 0; err_unregister_ost_clock: if (tcu->soc_info->has_ost) clk_hw_unregister(tcu->clocks->hws[i + 1]); err_unregister_watchdog_clock: clk_hw_unregister(tcu->clocks->hws[i]); err_unregister_timer_clocks: for (i = 0; i < tcu->clocks->num; i++) if (tcu->clocks->hws[i]) clk_hw_unregister(tcu->clocks->hws[i]); kfree(tcu->clocks); err_clk_disable: if (tcu->clk) clk_disable_unprepare(tcu->clk); err_put_clk: if (tcu->clk) clk_put(tcu->clk); err_free_tcu: kfree(tcu); return ret; } static int __maybe_unused tcu_pm_suspend(void) { struct ingenic_tcu *tcu = ingenic_tcu; if (tcu->clk) clk_disable(tcu->clk); return 0; } static void __maybe_unused tcu_pm_resume(void) { struct ingenic_tcu *tcu = ingenic_tcu; if (tcu->clk) clk_enable(tcu->clk); } static struct syscore_ops __maybe_unused tcu_pm_ops = { .suspend = tcu_pm_suspend, .resume = tcu_pm_resume, }; static void __init ingenic_tcu_init(struct device_node *np) { int ret = ingenic_tcu_probe(np); if (ret) pr_crit("Failed to initialize TCU clocks: %d\n", ret); if (IS_ENABLED(CONFIG_PM_SLEEP)) register_syscore_ops(&tcu_pm_ops); } CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-tcu", ingenic_tcu_init); CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-tcu", ingenic_tcu_init); CLK_OF_DECLARE_DRIVER(jz4760_cgu, "ingenic,jz4760-tcu", ingenic_tcu_init); CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-tcu", ingenic_tcu_init); CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-tcu", ingenic_tcu_init);
linux-master
drivers/clk/ingenic/tcu.c
// SPDX-License-Identifier: GPL-2.0 /* * JZ4760 SoC CGU driver * Copyright 2018, Paul Cercueil <[email protected]> */ #include <linux/bitops.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/of.h> #include <linux/clk.h> #include <dt-bindings/clock/ingenic,jz4760-cgu.h> #include "cgu.h" #include "pm.h" #define MHZ (1000 * 1000) /* * CPM registers offset address definition */ #define CGU_REG_CPCCR 0x00 #define CGU_REG_LCR 0x04 #define CGU_REG_CPPCR0 0x10 #define CGU_REG_CLKGR0 0x20 #define CGU_REG_OPCR 0x24 #define CGU_REG_CLKGR1 0x28 #define CGU_REG_CPPCR1 0x30 #define CGU_REG_USBPCR 0x3c #define CGU_REG_USBCDR 0x50 #define CGU_REG_I2SCDR 0x60 #define CGU_REG_LPCDR 0x64 #define CGU_REG_MSCCDR 0x68 #define CGU_REG_UHCCDR 0x6c #define CGU_REG_SSICDR 0x74 #define CGU_REG_CIMCDR 0x7c #define CGU_REG_GPSCDR 0x80 #define CGU_REG_PCMCDR 0x84 #define CGU_REG_GPUCDR 0x88 static const s8 pll_od_encoding[8] = { 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, }; static const u8 jz4760_cgu_cpccr_div_table[] = { 1, 2, 3, 4, 6, 8, }; static const u8 jz4760_cgu_pll_half_div_table[] = { 2, 1, }; static void jz4760_cgu_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info, unsigned long rate, unsigned long parent_rate, unsigned int *pm, unsigned int *pn, unsigned int *pod) { unsigned int m, n, od, m_max = (1 << pll_info->m_bits) - 1; /* The frequency after the N divider must be between 1 and 50 MHz. */ n = parent_rate / (1 * MHZ); /* The N divider must be >= 2. */ n = clamp_val(n, 2, 1 << pll_info->n_bits); rate /= MHZ; parent_rate /= MHZ; for (m = m_max; m >= m_max && n >= 2; n--) { m = rate * n / parent_rate; od = m & 1; m <<= od; } *pm = m; *pn = n + 1; *pod = 1 << od; } static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { /* External clocks */ [JZ4760_CLK_EXT] = { "ext", CGU_CLK_EXT }, [JZ4760_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT }, /* PLLs */ [JZ4760_CLK_PLL0] = { "pll0", CGU_CLK_PLL, .parents = { JZ4760_CLK_EXT }, .pll = { .reg = CGU_REG_CPPCR0, .rate_multiplier = 1, .m_shift = 23, .m_bits = 8, .m_offset = 0, .n_shift = 18, .n_bits = 4, .n_offset = 0, .od_shift = 16, .od_bits = 2, .od_max = 8, .od_encoding = pll_od_encoding, .bypass_reg = CGU_REG_CPPCR0, .bypass_bit = 9, .enable_bit = 8, .stable_bit = 10, .calc_m_n_od = jz4760_cgu_calc_m_n_od, }, }, [JZ4760_CLK_PLL1] = { /* TODO: PLL1 can depend on PLL0 */ "pll1", CGU_CLK_PLL, .parents = { JZ4760_CLK_EXT }, .pll = { .reg = CGU_REG_CPPCR1, .rate_multiplier = 1, .m_shift = 23, .m_bits = 8, .m_offset = 0, .n_shift = 18, .n_bits = 4, .n_offset = 0, .od_shift = 16, .od_bits = 2, .od_max = 8, .od_encoding = pll_od_encoding, .bypass_bit = -1, .enable_bit = 7, .stable_bit = 6, .calc_m_n_od = jz4760_cgu_calc_m_n_od, }, }, /* Main clocks */ [JZ4760_CLK_CCLK] = { "cclk", CGU_CLK_DIV, /* * Disabling the CPU clock or any parent clocks will hang the * system; mark it critical. */ .flags = CLK_IS_CRITICAL, .parents = { JZ4760_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, jz4760_cgu_cpccr_div_table, }, }, [JZ4760_CLK_HCLK] = { "hclk", CGU_CLK_DIV, .parents = { JZ4760_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, jz4760_cgu_cpccr_div_table, }, }, [JZ4760_CLK_SCLK] = { "sclk", CGU_CLK_DIV, .parents = { JZ4760_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, 0, jz4760_cgu_cpccr_div_table, }, }, [JZ4760_CLK_H2CLK] = { "h2clk", CGU_CLK_DIV, .parents = { JZ4760_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0, jz4760_cgu_cpccr_div_table, }, }, [JZ4760_CLK_MCLK] = { "mclk", CGU_CLK_DIV, /* * Disabling MCLK or its parents will render DRAM * inaccessible; mark it critical. */ .flags = CLK_IS_CRITICAL, .parents = { JZ4760_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, jz4760_cgu_cpccr_div_table, }, }, [JZ4760_CLK_PCLK] = { "pclk", CGU_CLK_DIV, .parents = { JZ4760_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, jz4760_cgu_cpccr_div_table, }, }, /* Divided clocks */ [JZ4760_CLK_PLL0_HALF] = { "pll0_half", CGU_CLK_DIV, .parents = { JZ4760_CLK_PLL0 }, .div = { CGU_REG_CPCCR, 21, 1, 1, 22, -1, -1, 0, jz4760_cgu_pll_half_div_table, }, }, /* Those divided clocks can connect to PLL0 or PLL1 */ [JZ4760_CLK_UHC] = { "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, .mux = { CGU_REG_UHCCDR, 31, 1 }, .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 24 }, }, [JZ4760_CLK_GPU] = { "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, .mux = { CGU_REG_GPUCDR, 31, 1 }, .div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 9 }, }, [JZ4760_CLK_LPCLK_DIV] = { "lpclk_div", CGU_CLK_DIV | CGU_CLK_MUX, .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, .mux = { CGU_REG_LPCDR, 29, 1 }, .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, }, [JZ4760_CLK_TVE] = { "tve", CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_EXT, }, .mux = { CGU_REG_LPCDR, 31, 1 }, .gate = { CGU_REG_CLKGR0, 27 }, }, [JZ4760_CLK_LPCLK] = { "lpclk", CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_TVE, }, .mux = { CGU_REG_LPCDR, 30, 1 }, .gate = { CGU_REG_CLKGR0, 28 }, }, [JZ4760_CLK_GPS] = { "gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, }, .mux = { CGU_REG_GPSCDR, 31, 1 }, .div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 22 }, }, /* Those divided clocks can connect to EXT, PLL0 or PLL1 */ [JZ4760_CLK_PCM] = { "pcm", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4760_CLK_EXT, -1, JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 }, .mux = { CGU_REG_PCMCDR, 30, 2 }, .div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1, BIT(0) }, .gate = { CGU_REG_CLKGR1, 8 }, }, [JZ4760_CLK_I2S] = { "i2s", CGU_CLK_DIV | CGU_CLK_MUX, .parents = { JZ4760_CLK_EXT, -1, JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 }, .mux = { CGU_REG_I2SCDR, 30, 2 }, .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1, BIT(0) }, }, [JZ4760_CLK_OTG] = { "usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4760_CLK_EXT, -1, JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 }, .mux = { CGU_REG_USBCDR, 30, 2 }, .div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 2 }, }, /* Those divided clocks can connect to EXT or PLL0 */ [JZ4760_CLK_MMC_MUX] = { "mmc_mux", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, }, .mux = { CGU_REG_MSCCDR, 31, 1 }, .div = { CGU_REG_MSCCDR, 0, 1, 6, -1, -1, -1, BIT(0) }, }, [JZ4760_CLK_SSI_MUX] = { "ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX, .parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, }, .mux = { CGU_REG_SSICDR, 31, 1 }, .div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1, BIT(0) }, }, /* These divided clock can connect to PLL0 only */ [JZ4760_CLK_CIM] = { "cim", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4760_CLK_PLL0_HALF }, .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 26 }, }, /* Gate-only clocks */ [JZ4760_CLK_SSI0] = { "ssi0", CGU_CLK_GATE, .parents = { JZ4760_CLK_SSI_MUX, }, .gate = { CGU_REG_CLKGR0, 4 }, }, [JZ4760_CLK_SSI1] = { "ssi1", CGU_CLK_GATE, .parents = { JZ4760_CLK_SSI_MUX, }, .gate = { CGU_REG_CLKGR0, 19 }, }, [JZ4760_CLK_SSI2] = { "ssi2", CGU_CLK_GATE, .parents = { JZ4760_CLK_SSI_MUX, }, .gate = { CGU_REG_CLKGR0, 20 }, }, [JZ4760_CLK_DMA] = { "dma", CGU_CLK_GATE, .parents = { JZ4760_CLK_H2CLK, }, .gate = { CGU_REG_CLKGR0, 21 }, }, [JZ4760_CLK_MDMA] = { "mdma", CGU_CLK_GATE, .parents = { JZ4760_CLK_HCLK, }, .gate = { CGU_REG_CLKGR0, 25 }, }, [JZ4760_CLK_BDMA] = { "bdma", CGU_CLK_GATE, .parents = { JZ4760_CLK_HCLK, }, .gate = { CGU_REG_CLKGR1, 0 }, }, [JZ4760_CLK_I2C0] = { "i2c0", CGU_CLK_GATE, .parents = { JZ4760_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 5 }, }, [JZ4760_CLK_I2C1] = { "i2c1", CGU_CLK_GATE, .parents = { JZ4760_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 6 }, }, [JZ4760_CLK_UART0] = { "uart0", CGU_CLK_GATE, .parents = { JZ4760_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 15 }, }, [JZ4760_CLK_UART1] = { "uart1", CGU_CLK_GATE, .parents = { JZ4760_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 16 }, }, [JZ4760_CLK_UART2] = { "uart2", CGU_CLK_GATE, .parents = { JZ4760_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 17 }, }, [JZ4760_CLK_UART3] = { "uart3", CGU_CLK_GATE, .parents = { JZ4760_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 18 }, }, [JZ4760_CLK_IPU] = { "ipu", CGU_CLK_GATE, .parents = { JZ4760_CLK_HCLK, }, .gate = { CGU_REG_CLKGR0, 29 }, }, [JZ4760_CLK_ADC] = { "adc", CGU_CLK_GATE, .parents = { JZ4760_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 14 }, }, [JZ4760_CLK_AIC] = { "aic", CGU_CLK_GATE, .parents = { JZ4760_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 8 }, }, [JZ4760_CLK_VPU] = { "vpu", CGU_CLK_GATE, .parents = { JZ4760_CLK_HCLK, }, .gate = { CGU_REG_LCR, 30, false, 150 }, }, [JZ4760_CLK_MMC0] = { "mmc0", CGU_CLK_GATE, .parents = { JZ4760_CLK_MMC_MUX, }, .gate = { CGU_REG_CLKGR0, 3 }, }, [JZ4760_CLK_MMC1] = { "mmc1", CGU_CLK_GATE, .parents = { JZ4760_CLK_MMC_MUX, }, .gate = { CGU_REG_CLKGR0, 11 }, }, [JZ4760_CLK_MMC2] = { "mmc2", CGU_CLK_GATE, .parents = { JZ4760_CLK_MMC_MUX, }, .gate = { CGU_REG_CLKGR0, 12 }, }, [JZ4760_CLK_UHC_PHY] = { "uhc_phy", CGU_CLK_GATE, .parents = { JZ4760_CLK_UHC, }, .gate = { CGU_REG_OPCR, 5 }, }, [JZ4760_CLK_OTG_PHY] = { "usb_phy", CGU_CLK_GATE, .parents = { JZ4760_CLK_OTG }, .gate = { CGU_REG_OPCR, 7, true, 50 }, }, /* Custom clocks */ [JZ4760_CLK_EXT512] = { "ext/512", CGU_CLK_FIXDIV, .parents = { JZ4760_CLK_EXT }, .fixdiv = { 512 }, }, [JZ4760_CLK_RTC] = { "rtc", CGU_CLK_MUX, .parents = { JZ4760_CLK_EXT512, JZ4760_CLK_OSC32K, }, .mux = { CGU_REG_OPCR, 2, 1}, }, }; static void __init jz4760_cgu_init(struct device_node *np) { struct ingenic_cgu *cgu; int retval; cgu = ingenic_cgu_new(jz4760_cgu_clocks, ARRAY_SIZE(jz4760_cgu_clocks), np); if (!cgu) { pr_err("%s: failed to initialise CGU\n", __func__); return; } retval = ingenic_cgu_register_clocks(cgu); if (retval) pr_err("%s: failed to register CGU Clocks\n", __func__); ingenic_cgu_register_syscore_ops(cgu); } /* We only probe via devicetree, no need for a platform driver */ CLK_OF_DECLARE_DRIVER(jz4760_cgu, "ingenic,jz4760-cgu", jz4760_cgu_init); /* JZ4760B has some small differences, but we don't implement them. */ CLK_OF_DECLARE_DRIVER(jz4760b_cgu, "ingenic,jz4760b-cgu", jz4760_cgu_init);
linux-master
drivers/clk/ingenic/jz4760-cgu.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Ingenic SoC CGU driver * * Copyright (c) 2013-2015 Imagination Technologies * Author: Paul Burton <[email protected]> */ #include <linux/bitops.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/math64.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/time.h> #include "cgu.h" #define MHZ (1000 * 1000) static inline const struct ingenic_cgu_clk_info * to_clk_info(struct ingenic_clk *clk) { return &clk->cgu->clock_info[clk->idx]; } /** * ingenic_cgu_gate_get() - get the value of clock gate register bit * @cgu: reference to the CGU whose registers should be read * @info: info struct describing the gate bit * * Retrieves the state of the clock gate bit described by info. The * caller must hold cgu->lock. * * Return: true if the gate bit is set, else false. */ static inline bool ingenic_cgu_gate_get(struct ingenic_cgu *cgu, const struct ingenic_cgu_gate_info *info) { return !!(readl(cgu->base + info->reg) & BIT(info->bit)) ^ info->clear_to_gate; } /** * ingenic_cgu_gate_set() - set the value of clock gate register bit * @cgu: reference to the CGU whose registers should be modified * @info: info struct describing the gate bit * @val: non-zero to gate a clock, otherwise zero * * Sets the given gate bit in order to gate or ungate a clock. * * The caller must hold cgu->lock. */ static inline void ingenic_cgu_gate_set(struct ingenic_cgu *cgu, const struct ingenic_cgu_gate_info *info, bool val) { u32 clkgr = readl(cgu->base + info->reg); if (val ^ info->clear_to_gate) clkgr |= BIT(info->bit); else clkgr &= ~BIT(info->bit); writel(clkgr, cgu->base + info->reg); } /* * PLL operations */ static unsigned long ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); struct ingenic_cgu *cgu = ingenic_clk->cgu; const struct ingenic_cgu_pll_info *pll_info; unsigned m, n, od, od_enc = 0; bool bypass; u32 ctl; BUG_ON(clk_info->type != CGU_CLK_PLL); pll_info = &clk_info->pll; ctl = readl(cgu->base + pll_info->reg); m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); m += pll_info->m_offset; n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); n += pll_info->n_offset; if (pll_info->od_bits > 0) { od_enc = ctl >> pll_info->od_shift; od_enc &= GENMASK(pll_info->od_bits - 1, 0); } if (pll_info->bypass_bit >= 0) { ctl = readl(cgu->base + pll_info->bypass_reg); bypass = !!(ctl & BIT(pll_info->bypass_bit)); if (bypass) return parent_rate; } for (od = 0; od < pll_info->od_max; od++) if (pll_info->od_encoding[od] == od_enc) break; /* if od_max = 0, od_bits should be 0 and od is fixed to 1. */ if (pll_info->od_max == 0) BUG_ON(pll_info->od_bits != 0); else BUG_ON(od == pll_info->od_max); od++; return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, n * od); } static void ingenic_pll_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info, unsigned long rate, unsigned long parent_rate, unsigned int *pm, unsigned int *pn, unsigned int *pod) { unsigned int m, n, od = 1; /* * The frequency after the input divider must be between 10 and 50 MHz. * The highest divider yields the best resolution. */ n = parent_rate / (10 * MHZ); n = min_t(unsigned int, n, 1 << pll_info->n_bits); n = max_t(unsigned int, n, pll_info->n_offset); m = (rate / MHZ) * od * n / (parent_rate / MHZ); m = min_t(unsigned int, m, 1 << pll_info->m_bits); m = max_t(unsigned int, m, pll_info->m_offset); *pm = m; *pn = n; *pod = od; } static unsigned long ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info, unsigned long rate, unsigned long parent_rate, unsigned int *pm, unsigned int *pn, unsigned int *pod) { const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; unsigned int m, n, od; if (pll_info->calc_m_n_od) (*pll_info->calc_m_n_od)(pll_info, rate, parent_rate, &m, &n, &od); else ingenic_pll_calc_m_n_od(pll_info, rate, parent_rate, &m, &n, &od); if (pm) *pm = m; if (pn) *pn = n; if (pod) *pod = od; return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, n * od); } static long ingenic_pll_round_rate(struct clk_hw *hw, unsigned long req_rate, unsigned long *prate) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); return ingenic_pll_calc(clk_info, req_rate, *prate, NULL, NULL, NULL); } static inline int ingenic_pll_check_stable(struct ingenic_cgu *cgu, const struct ingenic_cgu_pll_info *pll_info) { u32 ctl; if (pll_info->stable_bit < 0) return 0; return readl_poll_timeout(cgu->base + pll_info->reg, ctl, ctl & BIT(pll_info->stable_bit), 0, 100 * USEC_PER_MSEC); } static int ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, unsigned long parent_rate) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); struct ingenic_cgu *cgu = ingenic_clk->cgu; const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; unsigned long rate, flags; unsigned int m, n, od; int ret = 0; u32 ctl; rate = ingenic_pll_calc(clk_info, req_rate, parent_rate, &m, &n, &od); if (rate != req_rate) pr_info("ingenic-cgu: request '%s' rate %luHz, actual %luHz\n", clk_info->name, req_rate, rate); spin_lock_irqsave(&cgu->lock, flags); ctl = readl(cgu->base + pll_info->reg); ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift); ctl |= (m - pll_info->m_offset) << pll_info->m_shift; ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift); ctl |= (n - pll_info->n_offset) << pll_info->n_shift; if (pll_info->od_bits > 0) { ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; } writel(ctl, cgu->base + pll_info->reg); if (pll_info->set_rate_hook) pll_info->set_rate_hook(pll_info, rate, parent_rate); /* If the PLL is enabled, verify that it's stable */ if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit))) ret = ingenic_pll_check_stable(cgu, pll_info); spin_unlock_irqrestore(&cgu->lock, flags); return ret; } static int ingenic_pll_enable(struct clk_hw *hw) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); struct ingenic_cgu *cgu = ingenic_clk->cgu; const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; unsigned long flags; int ret; u32 ctl; if (pll_info->enable_bit < 0) return 0; spin_lock_irqsave(&cgu->lock, flags); if (pll_info->bypass_bit >= 0) { ctl = readl(cgu->base + pll_info->bypass_reg); ctl &= ~BIT(pll_info->bypass_bit); writel(ctl, cgu->base + pll_info->bypass_reg); } ctl = readl(cgu->base + pll_info->reg); ctl |= BIT(pll_info->enable_bit); writel(ctl, cgu->base + pll_info->reg); ret = ingenic_pll_check_stable(cgu, pll_info); spin_unlock_irqrestore(&cgu->lock, flags); return ret; } static void ingenic_pll_disable(struct clk_hw *hw) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); struct ingenic_cgu *cgu = ingenic_clk->cgu; const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; unsigned long flags; u32 ctl; if (pll_info->enable_bit < 0) return; spin_lock_irqsave(&cgu->lock, flags); ctl = readl(cgu->base + pll_info->reg); ctl &= ~BIT(pll_info->enable_bit); writel(ctl, cgu->base + pll_info->reg); spin_unlock_irqrestore(&cgu->lock, flags); } static int ingenic_pll_is_enabled(struct clk_hw *hw) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); struct ingenic_cgu *cgu = ingenic_clk->cgu; const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; u32 ctl; if (pll_info->enable_bit < 0) return true; ctl = readl(cgu->base + pll_info->reg); return !!(ctl & BIT(pll_info->enable_bit)); } static const struct clk_ops ingenic_pll_ops = { .recalc_rate = ingenic_pll_recalc_rate, .round_rate = ingenic_pll_round_rate, .set_rate = ingenic_pll_set_rate, .enable = ingenic_pll_enable, .disable = ingenic_pll_disable, .is_enabled = ingenic_pll_is_enabled, }; /* * Operations for all non-PLL clocks */ static u8 ingenic_clk_get_parent(struct clk_hw *hw) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); struct ingenic_cgu *cgu = ingenic_clk->cgu; u32 reg; u8 i, hw_idx, idx = 0; if (clk_info->type & CGU_CLK_MUX) { reg = readl(cgu->base + clk_info->mux.reg); hw_idx = (reg >> clk_info->mux.shift) & GENMASK(clk_info->mux.bits - 1, 0); /* * Convert the hardware index to the parent index by skipping * over any -1's in the parents array. */ for (i = 0; i < hw_idx; i++) { if (clk_info->parents[i] != -1) idx++; } } return idx; } static int ingenic_clk_set_parent(struct clk_hw *hw, u8 idx) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); struct ingenic_cgu *cgu = ingenic_clk->cgu; unsigned long flags; u8 curr_idx, hw_idx, num_poss; u32 reg, mask; if (clk_info->type & CGU_CLK_MUX) { /* * Convert the parent index to the hardware index by adding * 1 for any -1 in the parents array preceding the given * index. That is, we want the index of idx'th entry in * clk_info->parents which does not equal -1. */ hw_idx = curr_idx = 0; num_poss = 1 << clk_info->mux.bits; for (; hw_idx < num_poss; hw_idx++) { if (clk_info->parents[hw_idx] == -1) continue; if (curr_idx == idx) break; curr_idx++; } /* idx should always be a valid parent */ BUG_ON(curr_idx != idx); mask = GENMASK(clk_info->mux.bits - 1, 0); mask <<= clk_info->mux.shift; spin_lock_irqsave(&cgu->lock, flags); /* write the register */ reg = readl(cgu->base + clk_info->mux.reg); reg &= ~mask; reg |= hw_idx << clk_info->mux.shift; writel(reg, cgu->base + clk_info->mux.reg); spin_unlock_irqrestore(&cgu->lock, flags); return 0; } return idx ? -EINVAL : 0; } static unsigned long ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); struct ingenic_cgu *cgu = ingenic_clk->cgu; unsigned long rate = parent_rate; u32 div_reg, div; u8 parent; if (clk_info->type & CGU_CLK_DIV) { parent = ingenic_clk_get_parent(hw); if (!(clk_info->div.bypass_mask & BIT(parent))) { div_reg = readl(cgu->base + clk_info->div.reg); div = (div_reg >> clk_info->div.shift) & GENMASK(clk_info->div.bits - 1, 0); if (clk_info->div.div_table) div = clk_info->div.div_table[div]; else div = (div + 1) * clk_info->div.div; rate /= div; } } else if (clk_info->type & CGU_CLK_FIXDIV) { rate /= clk_info->fixdiv.div; } return rate; } static unsigned int ingenic_clk_calc_hw_div(const struct ingenic_cgu_clk_info *clk_info, unsigned int div) { unsigned int i, best_i = 0, best = (unsigned int)-1; for (i = 0; i < (1 << clk_info->div.bits) && clk_info->div.div_table[i]; i++) { if (clk_info->div.div_table[i] >= div && clk_info->div.div_table[i] < best) { best = clk_info->div.div_table[i]; best_i = i; if (div == best) break; } } return best_i; } static unsigned ingenic_clk_calc_div(struct clk_hw *hw, const struct ingenic_cgu_clk_info *clk_info, unsigned long parent_rate, unsigned long req_rate) { unsigned int div, hw_div; u8 parent; parent = ingenic_clk_get_parent(hw); if (clk_info->div.bypass_mask & BIT(parent)) return 1; /* calculate the divide */ div = DIV_ROUND_UP(parent_rate, req_rate); if (clk_info->div.div_table) { hw_div = ingenic_clk_calc_hw_div(clk_info, div); return clk_info->div.div_table[hw_div]; } /* Impose hardware constraints */ div = clamp_t(unsigned int, div, clk_info->div.div, clk_info->div.div << clk_info->div.bits); /* * If the divider value itself must be divided before being written to * the divider register, we must ensure we don't have any bits set that * would be lost as a result of doing so. */ div = DIV_ROUND_UP(div, clk_info->div.div); div *= clk_info->div.div; return div; } static int ingenic_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); unsigned int div = 1; if (clk_info->type & CGU_CLK_DIV) div = ingenic_clk_calc_div(hw, clk_info, req->best_parent_rate, req->rate); else if (clk_info->type & CGU_CLK_FIXDIV) div = clk_info->fixdiv.div; else if (clk_hw_can_set_rate_parent(hw)) req->best_parent_rate = req->rate; req->rate = DIV_ROUND_UP(req->best_parent_rate, div); return 0; } static inline int ingenic_clk_check_stable(struct ingenic_cgu *cgu, const struct ingenic_cgu_clk_info *clk_info) { u32 reg; return readl_poll_timeout(cgu->base + clk_info->div.reg, reg, !(reg & BIT(clk_info->div.busy_bit)), 0, 100 * USEC_PER_MSEC); } static int ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate, unsigned long parent_rate) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); struct ingenic_cgu *cgu = ingenic_clk->cgu; unsigned long rate, flags; unsigned int hw_div, div; u32 reg, mask; int ret = 0; if (clk_info->type & CGU_CLK_DIV) { div = ingenic_clk_calc_div(hw, clk_info, parent_rate, req_rate); rate = DIV_ROUND_UP(parent_rate, div); if (rate != req_rate) return -EINVAL; if (clk_info->div.div_table) hw_div = ingenic_clk_calc_hw_div(clk_info, div); else hw_div = ((div / clk_info->div.div) - 1); spin_lock_irqsave(&cgu->lock, flags); reg = readl(cgu->base + clk_info->div.reg); /* update the divide */ mask = GENMASK(clk_info->div.bits - 1, 0); reg &= ~(mask << clk_info->div.shift); reg |= hw_div << clk_info->div.shift; /* clear the stop bit */ if (clk_info->div.stop_bit != -1) reg &= ~BIT(clk_info->div.stop_bit); /* set the change enable bit */ if (clk_info->div.ce_bit != -1) reg |= BIT(clk_info->div.ce_bit); /* update the hardware */ writel(reg, cgu->base + clk_info->div.reg); /* wait for the change to take effect */ if (clk_info->div.busy_bit != -1) ret = ingenic_clk_check_stable(cgu, clk_info); spin_unlock_irqrestore(&cgu->lock, flags); return ret; } return -EINVAL; } static int ingenic_clk_enable(struct clk_hw *hw) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); struct ingenic_cgu *cgu = ingenic_clk->cgu; unsigned long flags; if (clk_info->type & CGU_CLK_GATE) { /* ungate the clock */ spin_lock_irqsave(&cgu->lock, flags); ingenic_cgu_gate_set(cgu, &clk_info->gate, false); spin_unlock_irqrestore(&cgu->lock, flags); if (clk_info->gate.delay_us) udelay(clk_info->gate.delay_us); } return 0; } static void ingenic_clk_disable(struct clk_hw *hw) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); struct ingenic_cgu *cgu = ingenic_clk->cgu; unsigned long flags; if (clk_info->type & CGU_CLK_GATE) { /* gate the clock */ spin_lock_irqsave(&cgu->lock, flags); ingenic_cgu_gate_set(cgu, &clk_info->gate, true); spin_unlock_irqrestore(&cgu->lock, flags); } } static int ingenic_clk_is_enabled(struct clk_hw *hw) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); struct ingenic_cgu *cgu = ingenic_clk->cgu; int enabled = 1; if (clk_info->type & CGU_CLK_GATE) enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate); return enabled; } static const struct clk_ops ingenic_clk_ops = { .get_parent = ingenic_clk_get_parent, .set_parent = ingenic_clk_set_parent, .recalc_rate = ingenic_clk_recalc_rate, .determine_rate = ingenic_clk_determine_rate, .set_rate = ingenic_clk_set_rate, .enable = ingenic_clk_enable, .disable = ingenic_clk_disable, .is_enabled = ingenic_clk_is_enabled, }; /* * Setup functions. */ static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx) { const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx]; struct clk_init_data clk_init; struct ingenic_clk *ingenic_clk = NULL; struct clk *clk, *parent; const char *parent_names[4]; unsigned caps, i, num_possible; int err = -EINVAL; BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names)); if (clk_info->type == CGU_CLK_EXT) { clk = of_clk_get_by_name(cgu->np, clk_info->name); if (IS_ERR(clk)) { pr_err("%s: no external clock '%s' provided\n", __func__, clk_info->name); err = -ENODEV; goto out; } err = clk_register_clkdev(clk, clk_info->name, NULL); if (err) { clk_put(clk); goto out; } cgu->clocks.clks[idx] = clk; return 0; } if (!clk_info->type) { pr_err("%s: no clock type specified for '%s'\n", __func__, clk_info->name); goto out; } ingenic_clk = kzalloc(sizeof(*ingenic_clk), GFP_KERNEL); if (!ingenic_clk) { err = -ENOMEM; goto out; } ingenic_clk->hw.init = &clk_init; ingenic_clk->cgu = cgu; ingenic_clk->idx = idx; clk_init.name = clk_info->name; clk_init.flags = clk_info->flags; clk_init.parent_names = parent_names; caps = clk_info->type; if (caps & CGU_CLK_DIV) { caps &= ~CGU_CLK_DIV; } else if (!(caps & CGU_CLK_CUSTOM)) { /* pass rate changes to the parent clock */ clk_init.flags |= CLK_SET_RATE_PARENT; } if (caps & (CGU_CLK_MUX | CGU_CLK_CUSTOM)) { clk_init.num_parents = 0; if (caps & CGU_CLK_MUX) num_possible = 1 << clk_info->mux.bits; else num_possible = ARRAY_SIZE(clk_info->parents); for (i = 0; i < num_possible; i++) { if (clk_info->parents[i] == -1) continue; parent = cgu->clocks.clks[clk_info->parents[i]]; parent_names[clk_init.num_parents] = __clk_get_name(parent); clk_init.num_parents++; } BUG_ON(!clk_init.num_parents); BUG_ON(clk_init.num_parents > ARRAY_SIZE(parent_names)); } else { BUG_ON(clk_info->parents[0] == -1); clk_init.num_parents = 1; parent = cgu->clocks.clks[clk_info->parents[0]]; parent_names[0] = __clk_get_name(parent); } if (caps & CGU_CLK_CUSTOM) { clk_init.ops = clk_info->custom.clk_ops; caps &= ~CGU_CLK_CUSTOM; if (caps) { pr_err("%s: custom clock may not be combined with type 0x%x\n", __func__, caps); goto out; } } else if (caps & CGU_CLK_PLL) { clk_init.ops = &ingenic_pll_ops; caps &= ~CGU_CLK_PLL; if (caps) { pr_err("%s: PLL may not be combined with type 0x%x\n", __func__, caps); goto out; } } else { clk_init.ops = &ingenic_clk_ops; } /* nothing to do for gates or fixed dividers */ caps &= ~(CGU_CLK_GATE | CGU_CLK_FIXDIV); if (caps & CGU_CLK_MUX) { if (!(caps & CGU_CLK_MUX_GLITCHFREE)) clk_init.flags |= CLK_SET_PARENT_GATE; caps &= ~(CGU_CLK_MUX | CGU_CLK_MUX_GLITCHFREE); } if (caps) { pr_err("%s: unknown clock type 0x%x\n", __func__, caps); goto out; } clk = clk_register(NULL, &ingenic_clk->hw); if (IS_ERR(clk)) { pr_err("%s: failed to register clock '%s'\n", __func__, clk_info->name); err = PTR_ERR(clk); goto out; } err = clk_register_clkdev(clk, clk_info->name, NULL); if (err) goto out; cgu->clocks.clks[idx] = clk; out: if (err) kfree(ingenic_clk); return err; } struct ingenic_cgu * ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, unsigned num_clocks, struct device_node *np) { struct ingenic_cgu *cgu; cgu = kzalloc(sizeof(*cgu), GFP_KERNEL); if (!cgu) goto err_out; cgu->base = of_iomap(np, 0); if (!cgu->base) { pr_err("%s: failed to map CGU registers\n", __func__); goto err_out_free; } cgu->np = np; cgu->clock_info = clock_info; cgu->clocks.clk_num = num_clocks; spin_lock_init(&cgu->lock); return cgu; err_out_free: kfree(cgu); err_out: return NULL; } int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu) { unsigned i; int err; cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *), GFP_KERNEL); if (!cgu->clocks.clks) { err = -ENOMEM; goto err_out; } for (i = 0; i < cgu->clocks.clk_num; i++) { err = ingenic_register_clock(cgu, i); if (err) goto err_out_unregister; } err = of_clk_add_provider(cgu->np, of_clk_src_onecell_get, &cgu->clocks); if (err) goto err_out_unregister; return 0; err_out_unregister: for (i = 0; i < cgu->clocks.clk_num; i++) { if (!cgu->clocks.clks[i]) continue; if (cgu->clock_info[i].type & CGU_CLK_EXT) clk_put(cgu->clocks.clks[i]); else clk_unregister(cgu->clocks.clks[i]); } kfree(cgu->clocks.clks); err_out: return err; }
linux-master
drivers/clk/ingenic/cgu.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Ingenic JZ4740 SoC CGU driver * * Copyright (c) 2015 Imagination Technologies * Author: Paul Burton <[email protected]> */ #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/of.h> #include <dt-bindings/clock/ingenic,jz4740-cgu.h> #include "cgu.h" #include "pm.h" /* CGU register offsets */ #define CGU_REG_CPCCR 0x00 #define CGU_REG_LCR 0x04 #define CGU_REG_CPPCR 0x10 #define CGU_REG_CLKGR 0x20 #define CGU_REG_SCR 0x24 #define CGU_REG_I2SCDR 0x60 #define CGU_REG_LPCDR 0x64 #define CGU_REG_MSCCDR 0x68 #define CGU_REG_UHCCDR 0x6c #define CGU_REG_SSICDR 0x74 /* bits within a PLL control register */ #define PLLCTL_M_SHIFT 23 #define PLLCTL_M_MASK (0x1ff << PLLCTL_M_SHIFT) #define PLLCTL_N_SHIFT 18 #define PLLCTL_N_MASK (0x1f << PLLCTL_N_SHIFT) #define PLLCTL_OD_SHIFT 16 #define PLLCTL_OD_MASK (0x3 << PLLCTL_OD_SHIFT) #define PLLCTL_STABLE (1 << 10) #define PLLCTL_BYPASS (1 << 9) #define PLLCTL_ENABLE (1 << 8) /* bits within the LCR register */ #define LCR_SLEEP (1 << 0) /* bits within the CLKGR register */ #define CLKGR_UDC (1 << 11) static struct ingenic_cgu *cgu; static const s8 pll_od_encoding[4] = { 0x0, 0x1, -1, 0x3, }; static const u8 jz4740_cgu_cpccr_div_table[] = { 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, }; static const u8 jz4740_cgu_pll_half_div_table[] = { 2, 1, }; static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { /* External clocks */ [JZ4740_CLK_EXT] = { "ext", CGU_CLK_EXT }, [JZ4740_CLK_RTC] = { "rtc", CGU_CLK_EXT }, [JZ4740_CLK_PLL] = { "pll", CGU_CLK_PLL, .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, .pll = { .reg = CGU_REG_CPPCR, .rate_multiplier = 1, .m_shift = 23, .m_bits = 9, .m_offset = 2, .n_shift = 18, .n_bits = 5, .n_offset = 2, .od_shift = 16, .od_bits = 2, .od_max = 4, .od_encoding = pll_od_encoding, .stable_bit = 10, .bypass_reg = CGU_REG_CPPCR, .bypass_bit = 9, .enable_bit = 8, }, }, /* Muxes & dividers */ [JZ4740_CLK_PLL_HALF] = { "pll half", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0, jz4740_cgu_pll_half_div_table, }, }, [JZ4740_CLK_CCLK] = { "cclk", CGU_CLK_DIV, /* * Disabling the CPU clock or any parent clocks will hang the * system; mark it critical. */ .flags = CLK_IS_CRITICAL, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, jz4740_cgu_cpccr_div_table, }, }, [JZ4740_CLK_HCLK] = { "hclk", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, jz4740_cgu_cpccr_div_table, }, }, [JZ4740_CLK_PCLK] = { "pclk", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, jz4740_cgu_cpccr_div_table, }, }, [JZ4740_CLK_MCLK] = { "mclk", CGU_CLK_DIV, /* * Disabling MCLK or its parents will render DRAM * inaccessible; mark it critical. */ .flags = CLK_IS_CRITICAL, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, jz4740_cgu_cpccr_div_table, }, }, [JZ4740_CLK_LCD] = { "lcd", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1, 0, jz4740_cgu_cpccr_div_table, }, .gate = { CGU_REG_CLKGR, 10 }, }, [JZ4740_CLK_LCD_PCLK] = { "lcd_pclk", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, }, [JZ4740_CLK_I2S] = { "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 }, .mux = { CGU_REG_CPCCR, 31, 1 }, .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 6 }, }, [JZ4740_CLK_SPI] = { "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 }, .mux = { CGU_REG_SSICDR, 31, 1 }, .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 4 }, }, [JZ4740_CLK_MMC] = { "mmc", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 7 }, }, [JZ4740_CLK_UHC] = { "uhc", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 14 }, }, [JZ4740_CLK_UDC] = { "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 }, .mux = { CGU_REG_CPCCR, 29, 1 }, .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, .gate = { CGU_REG_SCR, 6, true }, }, /* Gate-only clocks */ [JZ4740_CLK_UART0] = { "uart0", CGU_CLK_GATE, .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 0 }, }, [JZ4740_CLK_UART1] = { "uart1", CGU_CLK_GATE, .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 15 }, }, [JZ4740_CLK_DMA] = { "dma", CGU_CLK_GATE, .parents = { JZ4740_CLK_PCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 12 }, }, [JZ4740_CLK_IPU] = { "ipu", CGU_CLK_GATE, .parents = { JZ4740_CLK_PCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 13 }, }, [JZ4740_CLK_ADC] = { "adc", CGU_CLK_GATE, .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 8 }, }, [JZ4740_CLK_I2C] = { "i2c", CGU_CLK_GATE, .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 3 }, }, [JZ4740_CLK_AIC] = { "aic", CGU_CLK_GATE, .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 5 }, }, [JZ4740_CLK_TCU] = { "tcu", CGU_CLK_GATE, .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 1 }, }, }; static void __init jz4740_cgu_init(struct device_node *np) { int retval; cgu = ingenic_cgu_new(jz4740_cgu_clocks, ARRAY_SIZE(jz4740_cgu_clocks), np); if (!cgu) { pr_err("%s: failed to initialise CGU\n", __func__); return; } retval = ingenic_cgu_register_clocks(cgu); if (retval) pr_err("%s: failed to register CGU Clocks\n", __func__); ingenic_cgu_register_syscore_ops(cgu); } CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);
linux-master
drivers/clk/ingenic/jz4740-cgu.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Ingenic JZ4780 SoC CGU driver * * Copyright (c) 2013-2015 Imagination Technologies * Author: Paul Burton <[email protected]> * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <[email protected]> */ #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/of.h> #include <dt-bindings/clock/ingenic,jz4780-cgu.h> #include "cgu.h" #include "pm.h" /* CGU register offsets */ #define CGU_REG_CLOCKCONTROL 0x00 #define CGU_REG_LCR 0x04 #define CGU_REG_APLL 0x10 #define CGU_REG_MPLL 0x14 #define CGU_REG_EPLL 0x18 #define CGU_REG_VPLL 0x1c #define CGU_REG_CLKGR0 0x20 #define CGU_REG_OPCR 0x24 #define CGU_REG_CLKGR1 0x28 #define CGU_REG_DDRCDR 0x2c #define CGU_REG_VPUCDR 0x30 #define CGU_REG_USBPCR 0x3c #define CGU_REG_USBRDT 0x40 #define CGU_REG_USBVBFIL 0x44 #define CGU_REG_USBPCR1 0x48 #define CGU_REG_LP0CDR 0x54 #define CGU_REG_I2SCDR 0x60 #define CGU_REG_LP1CDR 0x64 #define CGU_REG_MSC0CDR 0x68 #define CGU_REG_UHCCDR 0x6c #define CGU_REG_SSICDR 0x74 #define CGU_REG_CIMCDR 0x7c #define CGU_REG_PCMCDR 0x84 #define CGU_REG_GPUCDR 0x88 #define CGU_REG_HDMICDR 0x8c #define CGU_REG_MSC1CDR 0xa4 #define CGU_REG_MSC2CDR 0xa8 #define CGU_REG_BCHCDR 0xac #define CGU_REG_CLOCKSTATUS 0xd4 /* bits within the OPCR register */ #define OPCR_SPENDN0 BIT(7) #define OPCR_SPENDN1 BIT(6) /* bits within the USBPCR register */ #define USBPCR_USB_MODE BIT(31) #define USBPCR_IDPULLUP_MASK (0x3 << 28) #define USBPCR_COMMONONN BIT(25) #define USBPCR_VBUSVLDEXT BIT(24) #define USBPCR_VBUSVLDEXTSEL BIT(23) #define USBPCR_POR BIT(22) #define USBPCR_SIDDQ BIT(21) #define USBPCR_OTG_DISABLE BIT(20) #define USBPCR_COMPDISTUNE_MASK (0x7 << 17) #define USBPCR_OTGTUNE_MASK (0x7 << 14) #define USBPCR_SQRXTUNE_MASK (0x7 << 11) #define USBPCR_TXFSLSTUNE_MASK (0xf << 7) #define USBPCR_TXPREEMPHTUNE BIT(6) #define USBPCR_TXHSXVTUNE_MASK (0x3 << 4) #define USBPCR_TXVREFTUNE_MASK 0xf /* bits within the USBPCR1 register */ #define USBPCR1_REFCLKSEL_SHIFT 26 #define USBPCR1_REFCLKSEL_MASK (0x3 << USBPCR1_REFCLKSEL_SHIFT) #define USBPCR1_REFCLKSEL_CORE (0x2 << USBPCR1_REFCLKSEL_SHIFT) #define USBPCR1_REFCLKDIV_SHIFT 24 #define USBPCR1_REFCLKDIV_MASK (0x3 << USBPCR1_REFCLKDIV_SHIFT) #define USBPCR1_REFCLKDIV_19_2 (0x3 << USBPCR1_REFCLKDIV_SHIFT) #define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT) #define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT) #define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT) #define USBPCR1_USB_SEL BIT(28) #define USBPCR1_WORD_IF0 BIT(19) #define USBPCR1_WORD_IF1 BIT(18) /* bits within the USBRDT register */ #define USBRDT_VBFIL_LD_EN BIT(25) #define USBRDT_USBRDT_MASK 0x7fffff /* bits within the USBVBFIL register */ #define USBVBFIL_IDDIGFIL_SHIFT 16 #define USBVBFIL_IDDIGFIL_MASK (0xffff << USBVBFIL_IDDIGFIL_SHIFT) #define USBVBFIL_USBVBFIL_MASK (0xffff) /* bits within the LCR register */ #define LCR_PD_SCPU BIT(31) #define LCR_SCPUS BIT(27) /* bits within the CLKGR1 register */ #define CLKGR1_CORE1 BIT(15) static struct ingenic_cgu *cgu; static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { u32 usbpcr1; unsigned refclk_div; usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK; switch (refclk_div) { case USBPCR1_REFCLKDIV_12: return 12000000; case USBPCR1_REFCLKDIV_24: return 24000000; case USBPCR1_REFCLKDIV_48: return 48000000; case USBPCR1_REFCLKDIV_19_2: return 19200000; } return parent_rate; } static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate, unsigned long *parent_rate) { if (req_rate < 15600000) return 12000000; if (req_rate < 21600000) return 19200000; if (req_rate < 36000000) return 24000000; return 48000000; } static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate, unsigned long parent_rate) { unsigned long flags; u32 usbpcr1, div_bits; switch (req_rate) { case 12000000: div_bits = USBPCR1_REFCLKDIV_12; break; case 19200000: div_bits = USBPCR1_REFCLKDIV_19_2; break; case 24000000: div_bits = USBPCR1_REFCLKDIV_24; break; case 48000000: div_bits = USBPCR1_REFCLKDIV_48; break; default: return -EINVAL; } spin_lock_irqsave(&cgu->lock, flags); usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK; usbpcr1 |= div_bits; writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); spin_unlock_irqrestore(&cgu->lock, flags); return 0; } static int jz4780_otg_phy_enable(struct clk_hw *hw) { void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr); writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr); return 0; } static void jz4780_otg_phy_disable(struct clk_hw *hw) { void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr); writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr); } static int jz4780_otg_phy_is_enabled(struct clk_hw *hw) { void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; return (readl(reg_opcr) & OPCR_SPENDN0) && !(readl(reg_usbpcr) & USBPCR_SIDDQ) && !(readl(reg_usbpcr) & USBPCR_OTG_DISABLE); } static const struct clk_ops jz4780_otg_phy_ops = { .recalc_rate = jz4780_otg_phy_recalc_rate, .round_rate = jz4780_otg_phy_round_rate, .set_rate = jz4780_otg_phy_set_rate, .enable = jz4780_otg_phy_enable, .disable = jz4780_otg_phy_disable, .is_enabled = jz4780_otg_phy_is_enabled, }; static int jz4780_core1_enable(struct clk_hw *hw) { struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); struct ingenic_cgu *cgu = ingenic_clk->cgu; const unsigned int timeout = 5000; unsigned long flags; int retval; u32 lcr, clkgr1; spin_lock_irqsave(&cgu->lock, flags); lcr = readl(cgu->base + CGU_REG_LCR); lcr &= ~LCR_PD_SCPU; writel(lcr, cgu->base + CGU_REG_LCR); clkgr1 = readl(cgu->base + CGU_REG_CLKGR1); clkgr1 &= ~CLKGR1_CORE1; writel(clkgr1, cgu->base + CGU_REG_CLKGR1); spin_unlock_irqrestore(&cgu->lock, flags); /* wait for the CPU to be powered up */ retval = readl_poll_timeout(cgu->base + CGU_REG_LCR, lcr, !(lcr & LCR_SCPUS), 10, timeout); if (retval == -ETIMEDOUT) { pr_err("%s: Wait for power up core1 timeout\n", __func__); return retval; } return 0; } static const struct clk_ops jz4780_core1_ops = { .enable = jz4780_core1_enable, }; static const s8 pll_od_encoding[16] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, }; static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { /* External clocks */ [JZ4780_CLK_EXCLK] = { "ext", CGU_CLK_EXT }, [JZ4780_CLK_RTCLK] = { "rtc", CGU_CLK_EXT }, /* PLLs */ #define DEF_PLL(name) { \ .reg = CGU_REG_ ## name, \ .rate_multiplier = 1, \ .m_shift = 19, \ .m_bits = 13, \ .m_offset = 1, \ .n_shift = 13, \ .n_bits = 6, \ .n_offset = 1, \ .od_shift = 9, \ .od_bits = 4, \ .od_max = 16, \ .od_encoding = pll_od_encoding, \ .stable_bit = 6, \ .bypass_reg = CGU_REG_ ## name, \ .bypass_bit = 1, \ .enable_bit = 0, \ } [JZ4780_CLK_APLL] = { "apll", CGU_CLK_PLL, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .pll = DEF_PLL(APLL), }, [JZ4780_CLK_MPLL] = { "mpll", CGU_CLK_PLL, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .pll = DEF_PLL(MPLL), }, [JZ4780_CLK_EPLL] = { "epll", CGU_CLK_PLL, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .pll = DEF_PLL(EPLL), }, [JZ4780_CLK_VPLL] = { "vpll", CGU_CLK_PLL, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .pll = DEF_PLL(VPLL), }, #undef DEF_PLL /* Custom (SoC-specific) OTG PHY */ [JZ4780_CLK_OTGPHY] = { "otg_phy", CGU_CLK_CUSTOM, .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 }, .custom = { &jz4780_otg_phy_ops }, }, /* Muxes & dividers */ [JZ4780_CLK_SCLKA] = { "sclk_a", CGU_CLK_MUX, .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK, JZ4780_CLK_RTCLK }, .mux = { CGU_REG_CLOCKCONTROL, 30, 2 }, }, [JZ4780_CLK_CPUMUX] = { "cpumux", CGU_CLK_MUX, .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, JZ4780_CLK_EPLL }, .mux = { CGU_REG_CLOCKCONTROL, 28, 2 }, }, [JZ4780_CLK_CPU] = { "cpu", CGU_CLK_DIV, /* * Disabling the CPU clock or any parent clocks will hang the * system; mark it critical. */ .flags = CLK_IS_CRITICAL, .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CLOCKCONTROL, 0, 1, 4, 22, -1, -1 }, }, [JZ4780_CLK_L2CACHE] = { "l2cache", CGU_CLK_DIV, /* * The L2 cache clock is critical if caches are enabled and * disabling it or any parent clocks will hang the system. */ .flags = CLK_IS_CRITICAL, .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CLOCKCONTROL, 4, 1, 4, -1, -1, -1 }, }, [JZ4780_CLK_AHB0] = { "ahb0", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, JZ4780_CLK_EPLL }, .mux = { CGU_REG_CLOCKCONTROL, 26, 2 }, .div = { CGU_REG_CLOCKCONTROL, 8, 1, 4, 21, -1, -1 }, }, [JZ4780_CLK_AHB2PMUX] = { "ahb2_apb_mux", CGU_CLK_MUX, .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, JZ4780_CLK_RTCLK }, .mux = { CGU_REG_CLOCKCONTROL, 24, 2 }, }, [JZ4780_CLK_AHB2] = { "ahb2", CGU_CLK_DIV, .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, .div = { CGU_REG_CLOCKCONTROL, 12, 1, 4, 20, -1, -1 }, }, [JZ4780_CLK_PCLK] = { "pclk", CGU_CLK_DIV, .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, .div = { CGU_REG_CLOCKCONTROL, 16, 1, 4, 20, -1, -1 }, }, [JZ4780_CLK_DDR] = { "ddr", CGU_CLK_MUX | CGU_CLK_DIV, /* * Disabling DDR clock or its parents will render DRAM * inaccessible; mark it critical. */ .flags = CLK_IS_CRITICAL, .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 }, .mux = { CGU_REG_DDRCDR, 30, 2 }, .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, }, [JZ4780_CLK_VPU] = { "vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, JZ4780_CLK_EPLL, -1 }, .mux = { CGU_REG_VPUCDR, 30, 2 }, .div = { CGU_REG_VPUCDR, 0, 1, 4, 29, 28, 27 }, .gate = { CGU_REG_CLKGR1, 2 }, }, [JZ4780_CLK_I2SPLL] = { "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 }, .mux = { CGU_REG_I2SCDR, 30, 1 }, .div = { CGU_REG_I2SCDR, 0, 1, 8, 29, 28, 27 }, }, [JZ4780_CLK_I2S] = { "i2s", CGU_CLK_MUX, .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -1 }, .mux = { CGU_REG_I2SCDR, 31, 1 }, }, [JZ4780_CLK_LCD0PIXCLK] = { "lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, JZ4780_CLK_VPLL, -1 }, .mux = { CGU_REG_LP0CDR, 30, 2 }, .div = { CGU_REG_LP0CDR, 0, 1, 8, 28, 27, 26 }, }, [JZ4780_CLK_LCD1PIXCLK] = { "lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, JZ4780_CLK_VPLL, -1 }, .mux = { CGU_REG_LP1CDR, 30, 2 }, .div = { CGU_REG_LP1CDR, 0, 1, 8, 28, 27, 26 }, }, [JZ4780_CLK_MSCMUX] = { "msc_mux", CGU_CLK_MUX, .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 }, .mux = { CGU_REG_MSC0CDR, 30, 2 }, }, [JZ4780_CLK_MSC0] = { "msc0", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR0, 3 }, }, [JZ4780_CLK_MSC1] = { "msc1", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR0, 11 }, }, [JZ4780_CLK_MSC2] = { "msc2", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, .div = { CGU_REG_MSC2CDR, 0, 2, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR0, 12 }, }, [JZ4780_CLK_UHC] = { "uhc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, JZ4780_CLK_EPLL, JZ4780_CLK_OTGPHY }, .mux = { CGU_REG_UHCCDR, 30, 2 }, .div = { CGU_REG_UHCCDR, 0, 1, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR0, 24 }, }, [JZ4780_CLK_SSIPLL] = { "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 }, .mux = { CGU_REG_SSICDR, 30, 1 }, .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 }, }, [JZ4780_CLK_SSI] = { "ssi", CGU_CLK_MUX, .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -1 }, .mux = { CGU_REG_SSICDR, 31, 1 }, }, [JZ4780_CLK_CIMMCLK] = { "cim_mclk", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 }, .mux = { CGU_REG_CIMCDR, 31, 1 }, .div = { CGU_REG_CIMCDR, 0, 1, 8, 30, 29, 28 }, }, [JZ4780_CLK_PCMPLL] = { "pcm_pll", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, JZ4780_CLK_EPLL, JZ4780_CLK_VPLL }, .mux = { CGU_REG_PCMCDR, 29, 2 }, .div = { CGU_REG_PCMCDR, 0, 1, 8, 28, 27, 26 }, }, [JZ4780_CLK_PCM] = { "pcm", CGU_CLK_MUX | CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -1 }, .mux = { CGU_REG_PCMCDR, 31, 1 }, .gate = { CGU_REG_CLKGR1, 3 }, }, [JZ4780_CLK_GPU] = { "gpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, JZ4780_CLK_EPLL }, .mux = { CGU_REG_GPUCDR, 30, 2 }, .div = { CGU_REG_GPUCDR, 0, 1, 4, 29, 28, 27 }, .gate = { CGU_REG_CLKGR1, 4 }, }, [JZ4780_CLK_HDMI] = { "hdmi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, JZ4780_CLK_VPLL, -1 }, .mux = { CGU_REG_HDMICDR, 30, 2 }, .div = { CGU_REG_HDMICDR, 0, 1, 8, 29, 28, 26 }, .gate = { CGU_REG_CLKGR1, 9 }, }, [JZ4780_CLK_BCH] = { "bch", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, JZ4780_CLK_EPLL }, .mux = { CGU_REG_BCHCDR, 30, 2 }, .div = { CGU_REG_BCHCDR, 0, 1, 4, 29, 28, 27 }, .gate = { CGU_REG_CLKGR0, 1 }, }, [JZ4780_CLK_EXCLK_DIV512] = { "exclk_div512", CGU_CLK_FIXDIV, .parents = { JZ4780_CLK_EXCLK }, .fixdiv = { 512 }, }, [JZ4780_CLK_RTC] = { "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK_DIV512, JZ4780_CLK_RTCLK }, .mux = { CGU_REG_OPCR, 2, 1}, }, /* Gate-only clocks */ [JZ4780_CLK_NEMC] = { "nemc", CGU_CLK_GATE, .parents = { JZ4780_CLK_AHB2, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 0 }, }, [JZ4780_CLK_OTG0] = { "otg0", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 2 }, }, [JZ4780_CLK_SSI0] = { "ssi0", CGU_CLK_GATE, .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 4 }, }, [JZ4780_CLK_SMB0] = { "smb0", CGU_CLK_GATE, .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 5 }, }, [JZ4780_CLK_SMB1] = { "smb1", CGU_CLK_GATE, .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 6 }, }, [JZ4780_CLK_SCC] = { "scc", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 7 }, }, [JZ4780_CLK_AIC] = { "aic", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 8 }, }, [JZ4780_CLK_TSSI0] = { "tssi0", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 9 }, }, [JZ4780_CLK_OWI] = { "owi", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 10 }, }, [JZ4780_CLK_KBC] = { "kbc", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 13 }, }, [JZ4780_CLK_SADC] = { "sadc", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 14 }, }, [JZ4780_CLK_UART0] = { "uart0", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 15 }, }, [JZ4780_CLK_UART1] = { "uart1", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 16 }, }, [JZ4780_CLK_UART2] = { "uart2", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 17 }, }, [JZ4780_CLK_UART3] = { "uart3", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 18 }, }, [JZ4780_CLK_SSI1] = { "ssi1", CGU_CLK_GATE, .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 19 }, }, [JZ4780_CLK_SSI2] = { "ssi2", CGU_CLK_GATE, .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 20 }, }, [JZ4780_CLK_PDMA] = { "pdma", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 21 }, }, [JZ4780_CLK_GPS] = { "gps", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 22 }, }, [JZ4780_CLK_MAC] = { "mac", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 23 }, }, [JZ4780_CLK_SMB2] = { "smb2", CGU_CLK_GATE, .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 24 }, }, [JZ4780_CLK_CIM] = { "cim", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 26 }, }, [JZ4780_CLK_LCD] = { "lcd", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 28 }, }, [JZ4780_CLK_TVE] = { "tve", CGU_CLK_GATE, .parents = { JZ4780_CLK_LCD, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 27 }, }, [JZ4780_CLK_IPU] = { "ipu", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 29 }, }, [JZ4780_CLK_DDR0] = { "ddr0", CGU_CLK_GATE, .parents = { JZ4780_CLK_DDR, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 30 }, }, [JZ4780_CLK_DDR1] = { "ddr1", CGU_CLK_GATE, .parents = { JZ4780_CLK_DDR, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 31 }, }, [JZ4780_CLK_SMB3] = { "smb3", CGU_CLK_GATE, .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 0 }, }, [JZ4780_CLK_TSSI1] = { "tssi1", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 1 }, }, [JZ4780_CLK_COMPRESS] = { "compress", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 5 }, }, [JZ4780_CLK_AIC1] = { "aic1", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 6 }, }, [JZ4780_CLK_GPVLC] = { "gpvlc", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 7 }, }, [JZ4780_CLK_OTG1] = { "otg1", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 8 }, }, [JZ4780_CLK_UART4] = { "uart4", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 10 }, }, [JZ4780_CLK_AHBMON] = { "ahb_mon", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 11 }, }, [JZ4780_CLK_SMB4] = { "smb4", CGU_CLK_GATE, .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 12 }, }, [JZ4780_CLK_DES] = { "des", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 13 }, }, [JZ4780_CLK_X2D] = { "x2d", CGU_CLK_GATE, .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 14 }, }, [JZ4780_CLK_CORE1] = { "core1", CGU_CLK_CUSTOM, .parents = { JZ4780_CLK_CPU, -1, -1, -1 }, .custom = { &jz4780_core1_ops }, }, }; static void __init jz4780_cgu_init(struct device_node *np) { int retval; cgu = ingenic_cgu_new(jz4780_cgu_clocks, ARRAY_SIZE(jz4780_cgu_clocks), np); if (!cgu) { pr_err("%s: failed to initialise CGU\n", __func__); return; } retval = ingenic_cgu_register_clocks(cgu); if (retval) { pr_err("%s: failed to register CGU Clocks\n", __func__); return; } ingenic_cgu_register_syscore_ops(cgu); } CLK_OF_DECLARE_DRIVER(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init);
linux-master
drivers/clk/ingenic/jz4780-cgu.c
// SPDX-License-Identifier: GPL-2.0 /* * X1000 SoC CGU driver * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <[email protected]> */ #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/of.h> #include <linux/rational.h> #include <dt-bindings/clock/ingenic,x1000-cgu.h> #include "cgu.h" #include "pm.h" /* CGU register offsets */ #define CGU_REG_CPCCR 0x00 #define CGU_REG_APLL 0x10 #define CGU_REG_MPLL 0x14 #define CGU_REG_CLKGR 0x20 #define CGU_REG_OPCR 0x24 #define CGU_REG_DDRCDR 0x2c #define CGU_REG_USBPCR 0x3c #define CGU_REG_USBPCR1 0x48 #define CGU_REG_USBCDR 0x50 #define CGU_REG_MACCDR 0x54 #define CGU_REG_I2SCDR 0x60 #define CGU_REG_LPCDR 0x64 #define CGU_REG_MSC0CDR 0x68 #define CGU_REG_I2SCDR1 0x70 #define CGU_REG_SSICDR 0x74 #define CGU_REG_CIMCDR 0x7c #define CGU_REG_PCMCDR 0x84 #define CGU_REG_MSC1CDR 0xa4 #define CGU_REG_CMP_INTR 0xb0 #define CGU_REG_CMP_INTRE 0xb4 #define CGU_REG_DRCG 0xd0 #define CGU_REG_CPCSR 0xd4 #define CGU_REG_PCMCDR1 0xe0 #define CGU_REG_MACPHYC 0xe8 /* bits within the OPCR register */ #define OPCR_SPENDN0 BIT(7) #define OPCR_SPENDN1 BIT(6) /* bits within the USBPCR register */ #define USBPCR_SIDDQ BIT(21) #define USBPCR_OTG_DISABLE BIT(20) /* bits within the USBPCR1 register */ #define USBPCR1_REFCLKSEL_SHIFT 26 #define USBPCR1_REFCLKSEL_MASK (0x3 << USBPCR1_REFCLKSEL_SHIFT) #define USBPCR1_REFCLKSEL_CORE (0x2 << USBPCR1_REFCLKSEL_SHIFT) #define USBPCR1_REFCLKDIV_SHIFT 24 #define USBPCR1_REFCLKDIV_MASK (0x3 << USBPCR1_REFCLKDIV_SHIFT) #define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT) #define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT) #define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT) static struct ingenic_cgu *cgu; static unsigned long x1000_otg_phy_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { u32 usbpcr1; unsigned refclk_div; usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK; switch (refclk_div) { case USBPCR1_REFCLKDIV_12: return 12000000; case USBPCR1_REFCLKDIV_24: return 24000000; case USBPCR1_REFCLKDIV_48: return 48000000; } return parent_rate; } static long x1000_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate, unsigned long *parent_rate) { if (req_rate < 18000000) return 12000000; if (req_rate < 36000000) return 24000000; return 48000000; } static int x1000_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate, unsigned long parent_rate) { unsigned long flags; u32 usbpcr1, div_bits; switch (req_rate) { case 12000000: div_bits = USBPCR1_REFCLKDIV_12; break; case 24000000: div_bits = USBPCR1_REFCLKDIV_24; break; case 48000000: div_bits = USBPCR1_REFCLKDIV_48; break; default: return -EINVAL; } spin_lock_irqsave(&cgu->lock, flags); usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK; usbpcr1 |= div_bits; writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); spin_unlock_irqrestore(&cgu->lock, flags); return 0; } static int x1000_usb_phy_enable(struct clk_hw *hw) { void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr); writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr); return 0; } static void x1000_usb_phy_disable(struct clk_hw *hw) { void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr); writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr); } static int x1000_usb_phy_is_enabled(struct clk_hw *hw) { void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; return (readl(reg_opcr) & OPCR_SPENDN0) && !(readl(reg_usbpcr) & USBPCR_SIDDQ) && !(readl(reg_usbpcr) & USBPCR_OTG_DISABLE); } static const struct clk_ops x1000_otg_phy_ops = { .recalc_rate = x1000_otg_phy_recalc_rate, .round_rate = x1000_otg_phy_round_rate, .set_rate = x1000_otg_phy_set_rate, .enable = x1000_usb_phy_enable, .disable = x1000_usb_phy_disable, .is_enabled = x1000_usb_phy_is_enabled, }; static void x1000_i2spll_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info, unsigned long rate, unsigned long parent_rate, unsigned int *pm, unsigned int *pn, unsigned int *pod) { const unsigned long m_max = GENMASK(pll_info->m_bits - 1, 0); const unsigned long n_max = GENMASK(pll_info->n_bits - 1, 0); unsigned long m, n; rational_best_approximation(rate, parent_rate, m_max, n_max, &m, &n); /* n should not be less than 2*m */ if (n < 2 * m) n = 2 * m; *pm = m; *pn = n; *pod = 1; } static void x1000_i2spll_set_rate_hook(const struct ingenic_cgu_pll_info *pll_info, unsigned long rate, unsigned long parent_rate) { /* * Writing 0 causes I2SCDR1.I2SDIV_D to be automatically recalculated * based on the current value of I2SCDR.I2SDIV_N, which is needed for * the divider to function correctly. */ writel(0, cgu->base + CGU_REG_I2SCDR1); } static const s8 pll_od_encoding[8] = { 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, }; static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { /* External clocks */ [X1000_CLK_EXCLK] = { "ext", CGU_CLK_EXT }, [X1000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT }, /* PLLs */ [X1000_CLK_APLL] = { "apll", CGU_CLK_PLL, .parents = { X1000_CLK_EXCLK }, .pll = { .reg = CGU_REG_APLL, .rate_multiplier = 1, .m_shift = 24, .m_bits = 7, .m_offset = 1, .n_shift = 18, .n_bits = 5, .n_offset = 1, .od_shift = 16, .od_bits = 2, .od_max = 8, .od_encoding = pll_od_encoding, .bypass_reg = CGU_REG_APLL, .bypass_bit = 9, .enable_bit = 8, .stable_bit = 10, }, }, [X1000_CLK_MPLL] = { "mpll", CGU_CLK_PLL, .parents = { X1000_CLK_EXCLK }, .pll = { .reg = CGU_REG_MPLL, .rate_multiplier = 1, .m_shift = 24, .m_bits = 7, .m_offset = 1, .n_shift = 18, .n_bits = 5, .n_offset = 1, .od_shift = 16, .od_bits = 2, .od_max = 8, .od_encoding = pll_od_encoding, .bypass_reg = CGU_REG_MPLL, .bypass_bit = 6, .enable_bit = 7, .stable_bit = 0, }, }, /* Custom (SoC-specific) OTG PHY */ [X1000_CLK_OTGPHY] = { "otg_phy", CGU_CLK_CUSTOM, .parents = { -1, -1, X1000_CLK_EXCLK, -1 }, .custom = { &x1000_otg_phy_ops }, }, /* Muxes & dividers */ [X1000_CLK_SCLKA] = { "sclk_a", CGU_CLK_MUX, .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 }, .mux = { CGU_REG_CPCCR, 30, 2 }, }, [X1000_CLK_CPUMUX] = { "cpu_mux", CGU_CLK_MUX, .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 }, .mux = { CGU_REG_CPCCR, 28, 2 }, }, [X1000_CLK_CPU] = { "cpu", CGU_CLK_DIV | CGU_CLK_GATE, /* * Disabling the CPU clock or any parent clocks will hang the * system; mark it critical. */ .flags = CLK_IS_CRITICAL, .parents = { X1000_CLK_CPUMUX }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, .gate = { CGU_REG_CLKGR, 30 }, }, [X1000_CLK_L2CACHE] = { "l2cache", CGU_CLK_DIV, /* * The L2 cache clock is critical if caches are enabled and * disabling it or any parent clocks will hang the system. */ .flags = CLK_IS_CRITICAL, .parents = { X1000_CLK_CPUMUX }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, }, [X1000_CLK_AHB0] = { "ahb0", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 }, .mux = { CGU_REG_CPCCR, 26, 2 }, .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 }, }, [X1000_CLK_AHB2PMUX] = { "ahb2_apb_mux", CGU_CLK_MUX, .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 }, .mux = { CGU_REG_CPCCR, 24, 2 }, }, [X1000_CLK_AHB2] = { "ahb2", CGU_CLK_DIV, .parents = { X1000_CLK_AHB2PMUX }, .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 }, }, [X1000_CLK_PCLK] = { "pclk", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { X1000_CLK_AHB2PMUX }, .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 }, .gate = { CGU_REG_CLKGR, 28 }, }, [X1000_CLK_DDR] = { "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, /* * Disabling DDR clock or its parents will render DRAM * inaccessible; mark it critical. */ .flags = CLK_IS_CRITICAL, .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 }, .mux = { CGU_REG_DDRCDR, 30, 2 }, .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, .gate = { CGU_REG_CLKGR, 31 }, }, [X1000_CLK_MAC] = { "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, .mux = { CGU_REG_MACCDR, 31, 1 }, .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR, 25 }, }, [X1000_CLK_I2SPLLMUX] = { "i2s_pll_mux", CGU_CLK_MUX, .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, .mux = { CGU_REG_I2SCDR, 31, 1 }, }, [X1000_CLK_I2SPLL] = { "i2s_pll", CGU_CLK_PLL, .parents = { X1000_CLK_I2SPLLMUX }, .pll = { .reg = CGU_REG_I2SCDR, .rate_multiplier = 1, .m_shift = 13, .m_bits = 9, .n_shift = 0, .n_bits = 13, .calc_m_n_od = x1000_i2spll_calc_m_n_od, .set_rate_hook = x1000_i2spll_set_rate_hook, }, }, [X1000_CLK_I2S] = { "i2s", CGU_CLK_MUX, .parents = { X1000_CLK_EXCLK, -1, -1, X1000_CLK_I2SPLL }, /* * NOTE: the mux is at bit 30; bit 29 enables the M/N divider. * Therefore, the divider is disabled when EXCLK is selected. */ .mux = { CGU_REG_I2SCDR, 29, 2 }, }, [X1000_CLK_LCD] = { "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, .mux = { CGU_REG_LPCDR, 31, 1 }, .div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 }, .gate = { CGU_REG_CLKGR, 23 }, }, [X1000_CLK_MSCMUX] = { "msc_mux", CGU_CLK_MUX, .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, .mux = { CGU_REG_MSC0CDR, 31, 1 }, }, [X1000_CLK_MSC0] = { "msc0", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { X1000_CLK_MSCMUX }, .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR, 4 }, }, [X1000_CLK_MSC1] = { "msc1", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { X1000_CLK_MSCMUX, -1, -1, -1 }, .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR, 5 }, }, [X1000_CLK_OTG] = { "otg", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { X1000_CLK_EXCLK, -1, X1000_CLK_APLL, X1000_CLK_MPLL }, .mux = { CGU_REG_USBCDR, 30, 2 }, .div = { CGU_REG_USBCDR, 0, 1, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR, 3 }, }, [X1000_CLK_SSIPLL] = { "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, .mux = { CGU_REG_SSICDR, 31, 1 }, .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 }, }, [X1000_CLK_SSIPLL_DIV2] = { "ssi_pll_div2", CGU_CLK_FIXDIV, .parents = { X1000_CLK_SSIPLL }, .fixdiv = { 2 }, }, [X1000_CLK_SSIMUX] = { "ssi_mux", CGU_CLK_MUX, .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2 }, .mux = { CGU_REG_SSICDR, 30, 1 }, }, [X1000_CLK_EXCLK_DIV512] = { "exclk_div512", CGU_CLK_FIXDIV, .parents = { X1000_CLK_EXCLK }, .fixdiv = { 512 }, }, [X1000_CLK_RTC] = { "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE, .parents = { X1000_CLK_EXCLK_DIV512, X1000_CLK_RTCLK }, .mux = { CGU_REG_OPCR, 2, 1}, .gate = { CGU_REG_CLKGR, 27 }, }, /* Gate-only clocks */ [X1000_CLK_EMC] = { "emc", CGU_CLK_GATE, .parents = { X1000_CLK_AHB2 }, .gate = { CGU_REG_CLKGR, 0 }, }, [X1000_CLK_EFUSE] = { "efuse", CGU_CLK_GATE, .parents = { X1000_CLK_AHB2 }, .gate = { CGU_REG_CLKGR, 1 }, }, [X1000_CLK_SFC] = { "sfc", CGU_CLK_GATE, .parents = { X1000_CLK_SSIPLL }, .gate = { CGU_REG_CLKGR, 2 }, }, [X1000_CLK_I2C0] = { "i2c0", CGU_CLK_GATE, .parents = { X1000_CLK_PCLK }, .gate = { CGU_REG_CLKGR, 7 }, }, [X1000_CLK_I2C1] = { "i2c1", CGU_CLK_GATE, .parents = { X1000_CLK_PCLK }, .gate = { CGU_REG_CLKGR, 8 }, }, [X1000_CLK_I2C2] = { "i2c2", CGU_CLK_GATE, .parents = { X1000_CLK_PCLK }, .gate = { CGU_REG_CLKGR, 9 }, }, [X1000_CLK_AIC] = { "aic", CGU_CLK_GATE, .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 11 }, }, [X1000_CLK_UART0] = { "uart0", CGU_CLK_GATE, .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 14 }, }, [X1000_CLK_UART1] = { "uart1", CGU_CLK_GATE, .parents = { X1000_CLK_EXCLK}, .gate = { CGU_REG_CLKGR, 15 }, }, [X1000_CLK_UART2] = { "uart2", CGU_CLK_GATE, .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 16 }, }, [X1000_CLK_TCU] = { "tcu", CGU_CLK_GATE, .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 18 }, }, [X1000_CLK_SSI] = { "ssi", CGU_CLK_GATE, .parents = { X1000_CLK_SSIMUX }, .gate = { CGU_REG_CLKGR, 19 }, }, [X1000_CLK_OST] = { "ost", CGU_CLK_GATE, .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 20 }, }, [X1000_CLK_PDMA] = { "pdma", CGU_CLK_GATE, .parents = { X1000_CLK_EXCLK }, .gate = { CGU_REG_CLKGR, 21 }, }, }; static void __init x1000_cgu_init(struct device_node *np) { int retval; cgu = ingenic_cgu_new(x1000_cgu_clocks, ARRAY_SIZE(x1000_cgu_clocks), np); if (!cgu) { pr_err("%s: failed to initialise CGU\n", __func__); return; } retval = ingenic_cgu_register_clocks(cgu); if (retval) { pr_err("%s: failed to register CGU Clocks\n", __func__); return; } ingenic_cgu_register_syscore_ops(cgu); } /* * CGU has some children devices, this is useful for probing children devices * in the case where the device node is compatible with "simple-mfd". */ CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);
linux-master
drivers/clk/ingenic/x1000-cgu.c
// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Paul Cercueil <[email protected]> */ #include "cgu.h" #include "pm.h" #include <linux/io.h> #include <linux/syscore_ops.h> #define CGU_REG_LCR 0x04 #define LCR_LOW_POWER_MODE BIT(0) static void __iomem * __maybe_unused ingenic_cgu_base; static int __maybe_unused ingenic_cgu_pm_suspend(void) { u32 val = readl(ingenic_cgu_base + CGU_REG_LCR); writel(val | LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR); return 0; } static void __maybe_unused ingenic_cgu_pm_resume(void) { u32 val = readl(ingenic_cgu_base + CGU_REG_LCR); writel(val & ~LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR); } static struct syscore_ops __maybe_unused ingenic_cgu_pm_ops = { .suspend = ingenic_cgu_pm_suspend, .resume = ingenic_cgu_pm_resume, }; void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu) { if (IS_ENABLED(CONFIG_PM_SLEEP)) { ingenic_cgu_base = cgu->base; register_syscore_ops(&ingenic_cgu_pm_ops); } }
linux-master
drivers/clk/ingenic/pm.c
// SPDX-License-Identifier: GPL-2.0 /* * Ingenic JZ4755 SoC CGU driver * Heavily based on JZ4725b CGU driver * * Copyright (C) 2022 Siarhei Volkau * Author: Siarhei Volkau <[email protected]> */ #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/of.h> #include <dt-bindings/clock/ingenic,jz4755-cgu.h> #include "cgu.h" #include "pm.h" /* CGU register offsets */ #define CGU_REG_CPCCR 0x00 #define CGU_REG_CPPCR 0x10 #define CGU_REG_CLKGR 0x20 #define CGU_REG_OPCR 0x24 #define CGU_REG_I2SCDR 0x60 #define CGU_REG_LPCDR 0x64 #define CGU_REG_MSCCDR 0x68 #define CGU_REG_SSICDR 0x74 #define CGU_REG_CIMCDR 0x7C static struct ingenic_cgu *cgu; static const s8 pll_od_encoding[4] = { 0x0, 0x1, -1, 0x3, }; static const u8 jz4755_cgu_cpccr_div_table[] = { 1, 2, 3, 4, 6, 8, }; static const u8 jz4755_cgu_pll_half_div_table[] = { 2, 1, }; static const struct ingenic_cgu_clk_info jz4755_cgu_clocks[] = { /* External clocks */ [JZ4755_CLK_EXT] = { "ext", CGU_CLK_EXT }, [JZ4755_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT }, [JZ4755_CLK_PLL] = { "pll", CGU_CLK_PLL, .parents = { JZ4755_CLK_EXT, }, .pll = { .reg = CGU_REG_CPPCR, .rate_multiplier = 1, .m_shift = 23, .m_bits = 9, .m_offset = 2, .n_shift = 18, .n_bits = 5, .n_offset = 2, .od_shift = 16, .od_bits = 2, .od_max = 4, .od_encoding = pll_od_encoding, .stable_bit = 10, .bypass_reg = CGU_REG_CPPCR, .bypass_bit = 9, .enable_bit = 8, }, }, /* Muxes & dividers */ [JZ4755_CLK_PLL_HALF] = { "pll half", CGU_CLK_DIV, .parents = { JZ4755_CLK_PLL, }, .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0, jz4755_cgu_pll_half_div_table, }, }, [JZ4755_CLK_EXT_HALF] = { "ext half", CGU_CLK_DIV, .parents = { JZ4755_CLK_EXT, }, .div = { CGU_REG_CPCCR, 30, 1, 1, -1, -1, -1, 0, NULL, }, }, [JZ4755_CLK_CCLK] = { "cclk", CGU_CLK_DIV, .parents = { JZ4755_CLK_PLL, }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, jz4755_cgu_cpccr_div_table, }, }, [JZ4755_CLK_H0CLK] = { "hclk", CGU_CLK_DIV, .parents = { JZ4755_CLK_PLL, }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, jz4755_cgu_cpccr_div_table, }, }, [JZ4755_CLK_PCLK] = { "pclk", CGU_CLK_DIV, .parents = { JZ4755_CLK_PLL, }, .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, jz4755_cgu_cpccr_div_table, }, }, [JZ4755_CLK_MCLK] = { "mclk", CGU_CLK_DIV, .parents = { JZ4755_CLK_PLL, }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, jz4755_cgu_cpccr_div_table, }, }, [JZ4755_CLK_H1CLK] = { "h1clk", CGU_CLK_DIV, .parents = { JZ4755_CLK_PLL, }, .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0, jz4755_cgu_cpccr_div_table, }, }, [JZ4755_CLK_UDC] = { "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, }, .mux = { CGU_REG_CPCCR, 29, 1 }, .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 10 }, }, [JZ4755_CLK_LCD] = { "lcd", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4755_CLK_PLL_HALF, }, .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 9 }, }, [JZ4755_CLK_MMC] = { "mmc", CGU_CLK_DIV, .parents = { JZ4755_CLK_PLL_HALF, }, .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 }, }, [JZ4755_CLK_I2S] = { "i2s", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, }, .mux = { CGU_REG_CPCCR, 31, 1 }, .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, }, [JZ4755_CLK_SPI] = { "spi", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4755_CLK_PLL_HALF, }, .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 4 }, }, [JZ4755_CLK_TVE] = { "tve", CGU_CLK_MUX | CGU_CLK_GATE, .parents = { JZ4755_CLK_LCD, JZ4755_CLK_EXT, }, .mux = { CGU_REG_LPCDR, 31, 1 }, .gate = { CGU_REG_CLKGR, 18 }, }, [JZ4755_CLK_RTC] = { "rtc", CGU_CLK_MUX | CGU_CLK_GATE, .parents = { JZ4755_CLK_EXT512, JZ4755_CLK_OSC32K, }, .mux = { CGU_REG_OPCR, 2, 1}, .gate = { CGU_REG_CLKGR, 2 }, }, [JZ4755_CLK_CIM] = { "cim", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4755_CLK_PLL_HALF, }, .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 8 }, }, /* Gate-only clocks */ [JZ4755_CLK_UART0] = { "uart0", CGU_CLK_GATE, .parents = { JZ4755_CLK_EXT_HALF, }, .gate = { CGU_REG_CLKGR, 0 }, }, [JZ4755_CLK_UART1] = { "uart1", CGU_CLK_GATE, .parents = { JZ4755_CLK_EXT_HALF, }, .gate = { CGU_REG_CLKGR, 14 }, }, [JZ4755_CLK_UART2] = { "uart2", CGU_CLK_GATE, .parents = { JZ4755_CLK_EXT_HALF, }, .gate = { CGU_REG_CLKGR, 15 }, }, [JZ4755_CLK_ADC] = { "adc", CGU_CLK_GATE, .parents = { JZ4755_CLK_EXT_HALF, }, .gate = { CGU_REG_CLKGR, 7 }, }, [JZ4755_CLK_AIC] = { "aic", CGU_CLK_GATE, .parents = { JZ4755_CLK_EXT_HALF, }, .gate = { CGU_REG_CLKGR, 5 }, }, [JZ4755_CLK_I2C] = { "i2c", CGU_CLK_GATE, .parents = { JZ4755_CLK_EXT_HALF, }, .gate = { CGU_REG_CLKGR, 3 }, }, [JZ4755_CLK_BCH] = { "bch", CGU_CLK_GATE, .parents = { JZ4755_CLK_H1CLK, }, .gate = { CGU_REG_CLKGR, 11 }, }, [JZ4755_CLK_TCU] = { "tcu", CGU_CLK_GATE, .parents = { JZ4755_CLK_EXT, }, .gate = { CGU_REG_CLKGR, 1 }, }, [JZ4755_CLK_DMA] = { "dma", CGU_CLK_GATE, .parents = { JZ4755_CLK_PCLK, }, .gate = { CGU_REG_CLKGR, 12 }, }, [JZ4755_CLK_MMC0] = { "mmc0", CGU_CLK_GATE, .parents = { JZ4755_CLK_MMC, }, .gate = { CGU_REG_CLKGR, 6 }, }, [JZ4755_CLK_MMC1] = { "mmc1", CGU_CLK_GATE, .parents = { JZ4755_CLK_MMC, }, .gate = { CGU_REG_CLKGR, 16 }, }, [JZ4755_CLK_AUX_CPU] = { "aux_cpu", CGU_CLK_GATE, .parents = { JZ4755_CLK_H1CLK, }, .gate = { CGU_REG_CLKGR, 24 }, }, [JZ4755_CLK_AHB1] = { "ahb1", CGU_CLK_GATE, .parents = { JZ4755_CLK_H1CLK, }, .gate = { CGU_REG_CLKGR, 23 }, }, [JZ4755_CLK_IDCT] = { "idct", CGU_CLK_GATE, .parents = { JZ4755_CLK_H1CLK, }, .gate = { CGU_REG_CLKGR, 22 }, }, [JZ4755_CLK_DB] = { "db", CGU_CLK_GATE, .parents = { JZ4755_CLK_H1CLK, }, .gate = { CGU_REG_CLKGR, 21 }, }, [JZ4755_CLK_ME] = { "me", CGU_CLK_GATE, .parents = { JZ4755_CLK_H1CLK, }, .gate = { CGU_REG_CLKGR, 20 }, }, [JZ4755_CLK_MC] = { "mc", CGU_CLK_GATE, .parents = { JZ4755_CLK_H1CLK, }, .gate = { CGU_REG_CLKGR, 19 }, }, [JZ4755_CLK_TSSI] = { "tssi", CGU_CLK_GATE, .parents = { JZ4755_CLK_EXT_HALF/* not sure */, }, .gate = { CGU_REG_CLKGR, 17 }, }, [JZ4755_CLK_IPU] = { "ipu", CGU_CLK_GATE, .parents = { JZ4755_CLK_PLL_HALF/* not sure */, }, .gate = { CGU_REG_CLKGR, 13 }, }, [JZ4755_CLK_EXT512] = { "ext/512", CGU_CLK_FIXDIV, .parents = { JZ4755_CLK_EXT, }, .fixdiv = { 512 }, }, [JZ4755_CLK_UDC_PHY] = { "udc_phy", CGU_CLK_GATE, .parents = { JZ4755_CLK_EXT_HALF, }, .gate = { CGU_REG_OPCR, 6, true }, }, }; static void __init jz4755_cgu_init(struct device_node *np) { int retval; cgu = ingenic_cgu_new(jz4755_cgu_clocks, ARRAY_SIZE(jz4755_cgu_clocks), np); if (!cgu) { pr_err("%s: failed to initialise CGU\n", __func__); return; } retval = ingenic_cgu_register_clocks(cgu); if (retval) pr_err("%s: failed to register CGU Clocks\n", __func__); ingenic_cgu_register_syscore_ops(cgu); } /* * CGU has some children devices, this is useful for probing children devices * in the case where the device node is compatible with "simple-mfd". */ CLK_OF_DECLARE_DRIVER(jz4755_cgu, "ingenic,jz4755-cgu", jz4755_cgu_init);
linux-master
drivers/clk/ingenic/jz4755-cgu.c
// SPDX-License-Identifier: GPL-2.0 /* * JZ4770 SoC CGU driver * Copyright 2018, Paul Cercueil <[email protected]> */ #include <linux/bitops.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/of.h> #include <dt-bindings/clock/ingenic,jz4770-cgu.h> #include "cgu.h" #include "pm.h" /* * CPM registers offset address definition */ #define CGU_REG_CPCCR 0x00 #define CGU_REG_LCR 0x04 #define CGU_REG_CPPCR0 0x10 #define CGU_REG_CLKGR0 0x20 #define CGU_REG_OPCR 0x24 #define CGU_REG_CLKGR1 0x28 #define CGU_REG_CPPCR1 0x30 #define CGU_REG_USBPCR1 0x48 #define CGU_REG_USBCDR 0x50 #define CGU_REG_I2SCDR 0x60 #define CGU_REG_LPCDR 0x64 #define CGU_REG_MSC0CDR 0x68 #define CGU_REG_UHCCDR 0x6c #define CGU_REG_SSICDR 0x74 #define CGU_REG_CIMCDR 0x7c #define CGU_REG_GPSCDR 0x80 #define CGU_REG_PCMCDR 0x84 #define CGU_REG_GPUCDR 0x88 #define CGU_REG_MSC1CDR 0xA4 #define CGU_REG_MSC2CDR 0xA8 #define CGU_REG_BCHCDR 0xAC /* bits within the OPCR register */ #define OPCR_SPENDH BIT(5) /* UHC PHY suspend */ /* bits within the USBPCR1 register */ #define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */ static struct ingenic_cgu *cgu; static int jz4770_uhc_phy_enable(struct clk_hw *hw) { void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; writel(readl(reg_opcr) & ~OPCR_SPENDH, reg_opcr); writel(readl(reg_usbpcr1) | USBPCR1_UHC_POWER, reg_usbpcr1); return 0; } static void jz4770_uhc_phy_disable(struct clk_hw *hw) { void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; writel(readl(reg_usbpcr1) & ~USBPCR1_UHC_POWER, reg_usbpcr1); writel(readl(reg_opcr) | OPCR_SPENDH, reg_opcr); } static int jz4770_uhc_phy_is_enabled(struct clk_hw *hw) { void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; return !(readl(reg_opcr) & OPCR_SPENDH) && (readl(reg_usbpcr1) & USBPCR1_UHC_POWER); } static const struct clk_ops jz4770_uhc_phy_ops = { .enable = jz4770_uhc_phy_enable, .disable = jz4770_uhc_phy_disable, .is_enabled = jz4770_uhc_phy_is_enabled, }; static const s8 pll_od_encoding[8] = { 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, }; static const u8 jz4770_cgu_cpccr_div_table[] = { 1, 2, 3, 4, 6, 8, 12, }; static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { /* External clocks */ [JZ4770_CLK_EXT] = { "ext", CGU_CLK_EXT }, [JZ4770_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT }, /* PLLs */ [JZ4770_CLK_PLL0] = { "pll0", CGU_CLK_PLL, .parents = { JZ4770_CLK_EXT }, .pll = { .reg = CGU_REG_CPPCR0, .rate_multiplier = 1, .m_shift = 24, .m_bits = 7, .m_offset = 1, .n_shift = 18, .n_bits = 5, .n_offset = 1, .od_shift = 16, .od_bits = 2, .od_max = 8, .od_encoding = pll_od_encoding, .bypass_reg = CGU_REG_CPPCR0, .bypass_bit = 9, .enable_bit = 8, .stable_bit = 10, }, }, [JZ4770_CLK_PLL1] = { /* TODO: PLL1 can depend on PLL0 */ "pll1", CGU_CLK_PLL, .parents = { JZ4770_CLK_EXT }, .pll = { .reg = CGU_REG_CPPCR1, .rate_multiplier = 1, .m_shift = 24, .m_bits = 7, .m_offset = 1, .n_shift = 18, .n_bits = 5, .n_offset = 1, .od_shift = 16, .od_bits = 2, .od_max = 8, .od_encoding = pll_od_encoding, .bypass_bit = -1, .enable_bit = 7, .stable_bit = 6, }, }, /* Main clocks */ [JZ4770_CLK_CCLK] = { "cclk", CGU_CLK_DIV, /* * Disabling the CPU clock or any parent clocks will hang the * system; mark it critical. */ .flags = CLK_IS_CRITICAL, .parents = { JZ4770_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, }, }, [JZ4770_CLK_H0CLK] = { "h0clk", CGU_CLK_DIV, .parents = { JZ4770_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, }, }, [JZ4770_CLK_H1CLK] = { "h1clk", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4770_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, }, .gate = { CGU_REG_CLKGR1, 7 }, }, [JZ4770_CLK_H2CLK] = { "h2clk", CGU_CLK_DIV, .parents = { JZ4770_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, }, }, [JZ4770_CLK_C1CLK] = { "c1clk", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4770_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, }, .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle }, [JZ4770_CLK_PCLK] = { "pclk", CGU_CLK_DIV, .parents = { JZ4770_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, jz4770_cgu_cpccr_div_table, }, }, /* Those divided clocks can connect to PLL0 or PLL1 */ [JZ4770_CLK_MMC0_MUX] = { "mmc0_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, .mux = { CGU_REG_MSC0CDR, 30, 1 }, .div = { CGU_REG_MSC0CDR, 0, 1, 7, -1, -1, 31 }, .gate = { CGU_REG_MSC0CDR, 31 }, }, [JZ4770_CLK_MMC1_MUX] = { "mmc1_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, .mux = { CGU_REG_MSC1CDR, 30, 1 }, .div = { CGU_REG_MSC1CDR, 0, 1, 7, -1, -1, 31 }, .gate = { CGU_REG_MSC1CDR, 31 }, }, [JZ4770_CLK_MMC2_MUX] = { "mmc2_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, .mux = { CGU_REG_MSC2CDR, 30, 1 }, .div = { CGU_REG_MSC2CDR, 0, 1, 7, -1, -1, 31 }, .gate = { CGU_REG_MSC2CDR, 31 }, }, [JZ4770_CLK_CIM] = { "cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, .mux = { CGU_REG_CIMCDR, 31, 1 }, .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 26 }, }, [JZ4770_CLK_UHC] = { "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, .mux = { CGU_REG_UHCCDR, 29, 1 }, .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 24 }, }, [JZ4770_CLK_GPU] = { "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, -1 }, .mux = { CGU_REG_GPUCDR, 31, 1 }, .div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 9 }, }, [JZ4770_CLK_BCH] = { "bch", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, .mux = { CGU_REG_BCHCDR, 31, 1 }, .div = { CGU_REG_BCHCDR, 0, 1, 3, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 1 }, }, [JZ4770_CLK_LPCLK_MUX] = { "lpclk", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, .mux = { CGU_REG_LPCDR, 29, 1 }, .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 28 }, }, [JZ4770_CLK_GPS] = { "gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, .mux = { CGU_REG_GPSCDR, 31, 1 }, .div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 22 }, }, /* Those divided clocks can connect to EXT, PLL0 or PLL1 */ [JZ4770_CLK_SSI_MUX] = { "ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX, .parents = { JZ4770_CLK_EXT, -1, JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, .mux = { CGU_REG_SSICDR, 30, 2 }, .div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1 }, }, [JZ4770_CLK_PCM_MUX] = { "pcm_mux", CGU_CLK_DIV | CGU_CLK_MUX, .parents = { JZ4770_CLK_EXT, -1, JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, .mux = { CGU_REG_PCMCDR, 30, 2 }, .div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1 }, }, [JZ4770_CLK_I2S] = { "i2s", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4770_CLK_EXT, -1, JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, .mux = { CGU_REG_I2SCDR, 30, 2 }, .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 13 }, }, [JZ4770_CLK_OTG] = { "usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, .parents = { JZ4770_CLK_EXT, -1, JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, .mux = { CGU_REG_USBCDR, 30, 2 }, .div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 2 }, }, /* Gate-only clocks */ [JZ4770_CLK_SSI0] = { "ssi0", CGU_CLK_GATE, .parents = { JZ4770_CLK_SSI_MUX, }, .gate = { CGU_REG_CLKGR0, 4 }, }, [JZ4770_CLK_SSI1] = { "ssi1", CGU_CLK_GATE, .parents = { JZ4770_CLK_SSI_MUX, }, .gate = { CGU_REG_CLKGR0, 19 }, }, [JZ4770_CLK_SSI2] = { "ssi2", CGU_CLK_GATE, .parents = { JZ4770_CLK_SSI_MUX, }, .gate = { CGU_REG_CLKGR0, 20 }, }, [JZ4770_CLK_PCM0] = { "pcm0", CGU_CLK_GATE, .parents = { JZ4770_CLK_PCM_MUX, }, .gate = { CGU_REG_CLKGR1, 8 }, }, [JZ4770_CLK_PCM1] = { "pcm1", CGU_CLK_GATE, .parents = { JZ4770_CLK_PCM_MUX, }, .gate = { CGU_REG_CLKGR1, 10 }, }, [JZ4770_CLK_DMA] = { "dma", CGU_CLK_GATE, .parents = { JZ4770_CLK_H2CLK, }, .gate = { CGU_REG_CLKGR0, 21 }, }, [JZ4770_CLK_BDMA] = { "bdma", CGU_CLK_GATE, .parents = { JZ4770_CLK_H2CLK, }, .gate = { CGU_REG_CLKGR1, 0 }, }, [JZ4770_CLK_I2C0] = { "i2c0", CGU_CLK_GATE, .parents = { JZ4770_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 5 }, }, [JZ4770_CLK_I2C1] = { "i2c1", CGU_CLK_GATE, .parents = { JZ4770_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 6 }, }, [JZ4770_CLK_I2C2] = { "i2c2", CGU_CLK_GATE, .parents = { JZ4770_CLK_EXT, }, .gate = { CGU_REG_CLKGR1, 15 }, }, [JZ4770_CLK_UART0] = { "uart0", CGU_CLK_GATE, .parents = { JZ4770_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 15 }, }, [JZ4770_CLK_UART1] = { "uart1", CGU_CLK_GATE, .parents = { JZ4770_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 16 }, }, [JZ4770_CLK_UART2] = { "uart2", CGU_CLK_GATE, .parents = { JZ4770_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 17 }, }, [JZ4770_CLK_UART3] = { "uart3", CGU_CLK_GATE, .parents = { JZ4770_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 18 }, }, [JZ4770_CLK_IPU] = { "ipu", CGU_CLK_GATE, .parents = { JZ4770_CLK_H0CLK, }, .gate = { CGU_REG_CLKGR0, 29 }, }, [JZ4770_CLK_ADC] = { "adc", CGU_CLK_GATE, .parents = { JZ4770_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 14 }, }, [JZ4770_CLK_AIC] = { "aic", CGU_CLK_GATE, .parents = { JZ4770_CLK_EXT, }, .gate = { CGU_REG_CLKGR0, 8 }, }, [JZ4770_CLK_AUX] = { "aux", CGU_CLK_GATE, .parents = { JZ4770_CLK_C1CLK, }, .gate = { CGU_REG_CLKGR1, 14 }, }, [JZ4770_CLK_VPU] = { "vpu", CGU_CLK_GATE, .parents = { JZ4770_CLK_H1CLK, }, .gate = { CGU_REG_LCR, 30, false, 150 }, }, [JZ4770_CLK_MMC0] = { "mmc0", CGU_CLK_GATE, .parents = { JZ4770_CLK_MMC0_MUX, }, .gate = { CGU_REG_CLKGR0, 3 }, }, [JZ4770_CLK_MMC1] = { "mmc1", CGU_CLK_GATE, .parents = { JZ4770_CLK_MMC1_MUX, }, .gate = { CGU_REG_CLKGR0, 11 }, }, [JZ4770_CLK_MMC2] = { "mmc2", CGU_CLK_GATE, .parents = { JZ4770_CLK_MMC2_MUX, }, .gate = { CGU_REG_CLKGR0, 12 }, }, [JZ4770_CLK_OTG_PHY] = { "usb_phy", CGU_CLK_GATE, .parents = { JZ4770_CLK_OTG }, .gate = { CGU_REG_OPCR, 7, true, 50 }, }, /* Custom clocks */ [JZ4770_CLK_UHC_PHY] = { "uhc_phy", CGU_CLK_CUSTOM, .parents = { JZ4770_CLK_UHC, -1, -1, -1 }, .custom = { &jz4770_uhc_phy_ops }, }, [JZ4770_CLK_EXT512] = { "ext/512", CGU_CLK_FIXDIV, .parents = { JZ4770_CLK_EXT }, .fixdiv = { 512 }, }, [JZ4770_CLK_RTC] = { "rtc", CGU_CLK_MUX, .parents = { JZ4770_CLK_EXT512, JZ4770_CLK_OSC32K, }, .mux = { CGU_REG_OPCR, 2, 1}, }, }; static void __init jz4770_cgu_init(struct device_node *np) { int retval; cgu = ingenic_cgu_new(jz4770_cgu_clocks, ARRAY_SIZE(jz4770_cgu_clocks), np); if (!cgu) { pr_err("%s: failed to initialise CGU\n", __func__); return; } retval = ingenic_cgu_register_clocks(cgu); if (retval) pr_err("%s: failed to register CGU Clocks\n", __func__); ingenic_cgu_register_syscore_ops(cgu); } /* We only probe via devicetree, no need for a platform driver */ CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);
linux-master
drivers/clk/ingenic/jz4770-cgu.c
// SPDX-License-Identifier: GPL-2.0 /* * X1830 SoC CGU driver * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <[email protected]> */ #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/of.h> #include <dt-bindings/clock/ingenic,x1830-cgu.h> #include "cgu.h" #include "pm.h" /* CGU register offsets */ #define CGU_REG_CPCCR 0x00 #define CGU_REG_CPPCR 0x0c #define CGU_REG_APLL 0x10 #define CGU_REG_MPLL 0x14 #define CGU_REG_CLKGR0 0x20 #define CGU_REG_OPCR 0x24 #define CGU_REG_CLKGR1 0x28 #define CGU_REG_DDRCDR 0x2c #define CGU_REG_USBPCR 0x3c #define CGU_REG_USBRDT 0x40 #define CGU_REG_USBVBFIL 0x44 #define CGU_REG_USBPCR1 0x48 #define CGU_REG_MACCDR 0x54 #define CGU_REG_EPLL 0x58 #define CGU_REG_I2SCDR 0x60 #define CGU_REG_LPCDR 0x64 #define CGU_REG_MSC0CDR 0x68 #define CGU_REG_I2SCDR1 0x70 #define CGU_REG_SSICDR 0x74 #define CGU_REG_CIMCDR 0x7c #define CGU_REG_MSC1CDR 0xa4 #define CGU_REG_CMP_INTR 0xb0 #define CGU_REG_CMP_INTRE 0xb4 #define CGU_REG_DRCG 0xd0 #define CGU_REG_CPCSR 0xd4 #define CGU_REG_VPLL 0xe0 #define CGU_REG_MACPHYC 0xe8 /* bits within the OPCR register */ #define OPCR_GATE_USBPHYCLK BIT(23) #define OPCR_SPENDN0 BIT(7) #define OPCR_SPENDN1 BIT(6) /* bits within the USBPCR register */ #define USBPCR_SIDDQ BIT(21) #define USBPCR_OTG_DISABLE BIT(20) static struct ingenic_cgu *cgu; static int x1830_usb_phy_enable(struct clk_hw *hw) { void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; writel((readl(reg_opcr) | OPCR_SPENDN0) & ~OPCR_GATE_USBPHYCLK, reg_opcr); writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr); return 0; } static void x1830_usb_phy_disable(struct clk_hw *hw) { void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; writel((readl(reg_opcr) & ~OPCR_SPENDN0) | OPCR_GATE_USBPHYCLK, reg_opcr); writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr); } static int x1830_usb_phy_is_enabled(struct clk_hw *hw) { void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; return (readl(reg_opcr) & OPCR_SPENDN0) && !(readl(reg_usbpcr) & USBPCR_SIDDQ) && !(readl(reg_usbpcr) & USBPCR_OTG_DISABLE); } static const struct clk_ops x1830_otg_phy_ops = { .enable = x1830_usb_phy_enable, .disable = x1830_usb_phy_disable, .is_enabled = x1830_usb_phy_is_enabled, }; static const s8 pll_od_encoding[64] = { 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, -1, -1, -1, -1, -1, -1, -1, 0x4, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0x5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0x6, }; static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { /* External clocks */ [X1830_CLK_EXCLK] = { "ext", CGU_CLK_EXT }, [X1830_CLK_RTCLK] = { "rtc", CGU_CLK_EXT }, /* PLLs */ [X1830_CLK_APLL] = { "apll", CGU_CLK_PLL, .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, .pll = { .reg = CGU_REG_APLL, .rate_multiplier = 2, .m_shift = 20, .m_bits = 9, .m_offset = 1, .n_shift = 14, .n_bits = 6, .n_offset = 1, .od_shift = 11, .od_bits = 3, .od_max = 64, .od_encoding = pll_od_encoding, .bypass_reg = CGU_REG_CPPCR, .bypass_bit = 30, .enable_bit = 0, .stable_bit = 3, }, }, [X1830_CLK_MPLL] = { "mpll", CGU_CLK_PLL, .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, .pll = { .reg = CGU_REG_MPLL, .rate_multiplier = 2, .m_shift = 20, .m_bits = 9, .m_offset = 1, .n_shift = 14, .n_bits = 6, .n_offset = 1, .od_shift = 11, .od_bits = 3, .od_max = 64, .od_encoding = pll_od_encoding, .bypass_reg = CGU_REG_CPPCR, .bypass_bit = 28, .enable_bit = 0, .stable_bit = 3, }, }, [X1830_CLK_EPLL] = { "epll", CGU_CLK_PLL, .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, .pll = { .reg = CGU_REG_EPLL, .rate_multiplier = 2, .m_shift = 20, .m_bits = 9, .m_offset = 1, .n_shift = 14, .n_bits = 6, .n_offset = 1, .od_shift = 11, .od_bits = 3, .od_max = 64, .od_encoding = pll_od_encoding, .bypass_reg = CGU_REG_CPPCR, .bypass_bit = 24, .enable_bit = 0, .stable_bit = 3, }, }, [X1830_CLK_VPLL] = { "vpll", CGU_CLK_PLL, .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, .pll = { .reg = CGU_REG_VPLL, .rate_multiplier = 2, .m_shift = 20, .m_bits = 9, .m_offset = 1, .n_shift = 14, .n_bits = 6, .n_offset = 1, .od_shift = 11, .od_bits = 3, .od_max = 64, .od_encoding = pll_od_encoding, .bypass_reg = CGU_REG_CPPCR, .bypass_bit = 26, .enable_bit = 0, .stable_bit = 3, }, }, /* Custom (SoC-specific) OTG PHY */ [X1830_CLK_OTGPHY] = { "otg_phy", CGU_CLK_CUSTOM, .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, .custom = { &x1830_otg_phy_ops }, }, /* Muxes & dividers */ [X1830_CLK_SCLKA] = { "sclk_a", CGU_CLK_MUX, .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 }, .mux = { CGU_REG_CPCCR, 30, 2 }, }, [X1830_CLK_CPUMUX] = { "cpu_mux", CGU_CLK_MUX, .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, .mux = { CGU_REG_CPCCR, 28, 2 }, }, [X1830_CLK_CPU] = { "cpu", CGU_CLK_DIV | CGU_CLK_GATE, .flags = CLK_IS_CRITICAL, .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, .gate = { CGU_REG_CLKGR1, 15 }, }, [X1830_CLK_L2CACHE] = { "l2cache", CGU_CLK_DIV, /* * The L2 cache clock is critical if caches are enabled and * disabling it or any parent clocks will hang the system. */ .flags = CLK_IS_CRITICAL, .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, }, [X1830_CLK_AHB0] = { "ahb0", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, .mux = { CGU_REG_CPCCR, 26, 2 }, .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 }, }, [X1830_CLK_AHB2PMUX] = { "ahb2_apb_mux", CGU_CLK_MUX, .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, .mux = { CGU_REG_CPCCR, 24, 2 }, }, [X1830_CLK_AHB2] = { "ahb2", CGU_CLK_DIV, .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 }, }, [X1830_CLK_PCLK] = { "pclk", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 }, .gate = { CGU_REG_CLKGR1, 14 }, }, [X1830_CLK_DDR] = { "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, /* * Disabling DDR clock or its parents will render DRAM * inaccessible; mark it critical. */ .flags = CLK_IS_CRITICAL, .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, .mux = { CGU_REG_DDRCDR, 30, 2 }, .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, .gate = { CGU_REG_CLKGR0, 31 }, }, [X1830_CLK_MAC] = { "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, X1830_CLK_VPLL, X1830_CLK_EPLL }, .mux = { CGU_REG_MACCDR, 30, 2 }, .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR1, 4 }, }, [X1830_CLK_LCD] = { "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, X1830_CLK_VPLL, X1830_CLK_EPLL }, .mux = { CGU_REG_LPCDR, 30, 2 }, .div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 }, .gate = { CGU_REG_CLKGR1, 9 }, }, [X1830_CLK_MSCMUX] = { "msc_mux", CGU_CLK_MUX, .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, X1830_CLK_VPLL, X1830_CLK_EPLL }, .mux = { CGU_REG_MSC0CDR, 30, 2 }, }, [X1830_CLK_MSC0] = { "msc0", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { X1830_CLK_MSCMUX, -1, -1, -1 }, .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR0, 4 }, }, [X1830_CLK_MSC1] = { "msc1", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { X1830_CLK_MSCMUX, -1, -1, -1 }, .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 }, .gate = { CGU_REG_CLKGR0, 5 }, }, [X1830_CLK_SSIPLL] = { "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, X1830_CLK_VPLL, X1830_CLK_EPLL }, .mux = { CGU_REG_SSICDR, 30, 2 }, .div = { CGU_REG_SSICDR, 0, 1, 8, 28, 27, 26 }, }, [X1830_CLK_SSIPLL_DIV2] = { "ssi_pll_div2", CGU_CLK_FIXDIV, .parents = { X1830_CLK_SSIPLL }, .fixdiv = { 2 }, }, [X1830_CLK_SSIMUX] = { "ssi_mux", CGU_CLK_MUX, .parents = { X1830_CLK_EXCLK, X1830_CLK_SSIPLL_DIV2, -1, -1 }, .mux = { CGU_REG_SSICDR, 29, 1 }, }, [X1830_CLK_EXCLK_DIV512] = { "exclk_div512", CGU_CLK_FIXDIV, .parents = { X1830_CLK_EXCLK }, .fixdiv = { 512 }, }, [X1830_CLK_RTC] = { "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE, .parents = { X1830_CLK_EXCLK_DIV512, X1830_CLK_RTCLK }, .mux = { CGU_REG_OPCR, 2, 1}, .gate = { CGU_REG_CLKGR0, 29 }, }, /* Gate-only clocks */ [X1830_CLK_EMC] = { "emc", CGU_CLK_GATE, .parents = { X1830_CLK_AHB2, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 0 }, }, [X1830_CLK_EFUSE] = { "efuse", CGU_CLK_GATE, .parents = { X1830_CLK_AHB2, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 1 }, }, [X1830_CLK_OTG] = { "otg", CGU_CLK_GATE, .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 3 }, }, [X1830_CLK_SSI0] = { "ssi0", CGU_CLK_GATE, .parents = { X1830_CLK_SSIMUX, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 6 }, }, [X1830_CLK_SMB0] = { "smb0", CGU_CLK_GATE, .parents = { X1830_CLK_PCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 7 }, }, [X1830_CLK_SMB1] = { "smb1", CGU_CLK_GATE, .parents = { X1830_CLK_PCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 8 }, }, [X1830_CLK_SMB2] = { "smb2", CGU_CLK_GATE, .parents = { X1830_CLK_PCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 9 }, }, [X1830_CLK_UART0] = { "uart0", CGU_CLK_GATE, .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 14 }, }, [X1830_CLK_UART1] = { "uart1", CGU_CLK_GATE, .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 15 }, }, [X1830_CLK_SSI1] = { "ssi1", CGU_CLK_GATE, .parents = { X1830_CLK_SSIMUX, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 19 }, }, [X1830_CLK_SFC] = { "sfc", CGU_CLK_GATE, .parents = { X1830_CLK_SSIPLL, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 20 }, }, [X1830_CLK_PDMA] = { "pdma", CGU_CLK_GATE, .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 21 }, }, [X1830_CLK_TCU] = { "tcu", CGU_CLK_GATE, .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR0, 30 }, }, [X1830_CLK_DTRNG] = { "dtrng", CGU_CLK_GATE, .parents = { X1830_CLK_PCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 1 }, }, [X1830_CLK_OST] = { "ost", CGU_CLK_GATE, .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, .gate = { CGU_REG_CLKGR1, 11 }, }, }; static void __init x1830_cgu_init(struct device_node *np) { int retval; cgu = ingenic_cgu_new(x1830_cgu_clocks, ARRAY_SIZE(x1830_cgu_clocks), np); if (!cgu) { pr_err("%s: failed to initialise CGU\n", __func__); return; } retval = ingenic_cgu_register_clocks(cgu); if (retval) { pr_err("%s: failed to register CGU Clocks\n", __func__); return; } ingenic_cgu_register_syscore_ops(cgu); } /* * CGU has some children devices, this is useful for probing children devices * in the case where the device node is compatible with "simple-mfd". */ CLK_OF_DECLARE_DRIVER(x1830_cgu, "ingenic,x1830-cgu", x1830_cgu_init);
linux-master
drivers/clk/ingenic/x1830-cgu.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012 Freescale Semiconductor, Inc. */ #include <linux/clk/mxs.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> #include "clk.h" static void __iomem *clkctrl; static void __iomem *digctrl; #define CLKCTRL clkctrl #define DIGCTRL digctrl #define PLLCTRL0 (CLKCTRL + 0x0000) #define CPU (CLKCTRL + 0x0020) #define HBUS (CLKCTRL + 0x0030) #define XBUS (CLKCTRL + 0x0040) #define XTAL (CLKCTRL + 0x0050) #define PIX (CLKCTRL + 0x0060) #define SSP (CLKCTRL + 0x0070) #define GPMI (CLKCTRL + 0x0080) #define SPDIF (CLKCTRL + 0x0090) #define EMI (CLKCTRL + 0x00a0) #define SAIF (CLKCTRL + 0x00c0) #define TV (CLKCTRL + 0x00d0) #define ETM (CLKCTRL + 0x00e0) #define FRAC (CLKCTRL + 0x00f0) #define CLKSEQ (CLKCTRL + 0x0110) #define BP_CPU_INTERRUPT_WAIT 12 #define BP_CLKSEQ_BYPASS_SAIF 0 #define BP_CLKSEQ_BYPASS_SSP 5 #define BP_SAIF_DIV_FRAC_EN 16 #define BP_FRAC_IOFRAC 24 static void __init clk_misc_init(void) { u32 val; /* Gate off cpu clock in WFI for power saving */ writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); /* Clear BYPASS for SAIF */ writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR); /* SAIF has to use frac div for functional operation */ val = readl_relaxed(SAIF); val |= 1 << BP_SAIF_DIV_FRAC_EN; writel_relaxed(val, SAIF); /* * Source ssp clock from ref_io than ref_xtal, * as ref_xtal only provides 24 MHz as maximum. */ writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR); /* * 480 MHz seems too high to be ssp clock source directly, * so set frac to get a 288 MHz ref_io. */ writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR); writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET); } static const char *const sel_pll[] __initconst = { "pll", "ref_xtal", }; static const char *const sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; static const char *const sel_pix[] __initconst = { "ref_pix", "ref_xtal", }; static const char *const sel_io[] __initconst = { "ref_io", "ref_xtal", }; static const char *const cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", }; static const char *const emi_sels[] __initconst = { "emi_pll", "emi_xtal", }; enum imx23_clk { ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel, lcdif_sel, gpmi_sel, ssp_sel, emi_sel, cpu, etm_sel, cpu_pll, cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll, emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div, clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif, lcdif, etm, usb, usb_phy, clk_max }; static struct clk *clks[clk_max]; static struct clk_onecell_data clk_data; static enum imx23_clk clks_init_on[] __initdata = { cpu, hbus, xbus, emi, uart, }; static void __init mx23_clocks_init(struct device_node *np) { struct device_node *dcnp; u32 i; dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl"); digctrl = of_iomap(dcnp, 0); WARN_ON(!digctrl); of_node_put(dcnp); clkctrl = of_iomap(np, 0); WARN_ON(!clkctrl); clk_misc_init(); clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll)); clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix)); clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io)); clks[ssp_sel] = mxs_clk_mux("ssp_sel", CLKSEQ, 5, 1, sel_io, ARRAY_SIZE(sel_io)); clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 6, 1, emi_sels, ARRAY_SIZE(emi_sels)); clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 7, 1, cpu_sels, ARRAY_SIZE(cpu_sels)); clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu)); clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28); clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29); clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31); clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29); clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29); clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29); clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28); clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29); clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29); clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29); clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750); clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768); clks[adc] = mxs_clk_fixed_factor("adc", "clk32k", 1, 16); clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4); clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26); clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28); clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30); clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); clks[ssp] = mxs_clk_gate("ssp", "ssp_div", SSP, 31); clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31); clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31); clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31); clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31); clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31); clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); clks[usb] = mxs_clk_gate("usb", "usb_phy", DIGCTRL, 2); clks[usb_phy] = clk_register_gate(NULL, "usb_phy", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock); for (i = 0; i < ARRAY_SIZE(clks); i++) if (IS_ERR(clks[i])) { pr_err("i.MX23 clk %d: register failed with %ld\n", i, PTR_ERR(clks[i])); return; } clk_data.clks = clks; clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clks[clks_init_on[i]]); } CLK_OF_DECLARE(imx23_clkctrl, "fsl,imx23-clkctrl", mx23_clocks_init);
linux-master
drivers/clk/mxs/clk-imx23.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012 Freescale Semiconductor, Inc. */ #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/io.h> #include <linux/slab.h> #include "clk.h" /** * struct clk_pll - mxs pll clock * @hw: clk_hw for the pll * @base: base address of the pll * @power: the shift of power bit * @rate: the clock rate of the pll * * The mxs pll is a fixed rate clock with power and gate control, * and the shift of gate bit is always 31. */ struct clk_pll { struct clk_hw hw; void __iomem *base; u8 power; unsigned long rate; }; #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) static int clk_pll_prepare(struct clk_hw *hw) { struct clk_pll *pll = to_clk_pll(hw); writel_relaxed(1 << pll->power, pll->base + SET); udelay(10); return 0; } static void clk_pll_unprepare(struct clk_hw *hw) { struct clk_pll *pll = to_clk_pll(hw); writel_relaxed(1 << pll->power, pll->base + CLR); } static int clk_pll_enable(struct clk_hw *hw) { struct clk_pll *pll = to_clk_pll(hw); writel_relaxed(1 << 31, pll->base + CLR); return 0; } static void clk_pll_disable(struct clk_hw *hw) { struct clk_pll *pll = to_clk_pll(hw); writel_relaxed(1 << 31, pll->base + SET); } static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pll *pll = to_clk_pll(hw); return pll->rate; } static const struct clk_ops clk_pll_ops = { .prepare = clk_pll_prepare, .unprepare = clk_pll_unprepare, .enable = clk_pll_enable, .disable = clk_pll_disable, .recalc_rate = clk_pll_recalc_rate, }; struct clk *mxs_clk_pll(const char *name, const char *parent_name, void __iomem *base, u8 power, unsigned long rate) { struct clk_pll *pll; struct clk *clk; struct clk_init_data init; pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &clk_pll_ops; init.flags = 0; init.parent_names = (parent_name ? &parent_name: NULL); init.num_parents = (parent_name ? 1 : 0); pll->base = base; pll->rate = rate; pll->power = power; pll->hw.init = &init; clk = clk_register(NULL, &pll->hw); if (IS_ERR(clk)) kfree(pll); return clk; }
linux-master
drivers/clk/mxs/clk-pll.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012 Freescale Semiconductor, Inc. */ #include <linux/clk/mxs.h> #include <linux/clkdev.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> #include "clk.h" static void __iomem *clkctrl; #define CLKCTRL clkctrl #define PLL0CTRL0 (CLKCTRL + 0x0000) #define PLL1CTRL0 (CLKCTRL + 0x0020) #define PLL2CTRL0 (CLKCTRL + 0x0040) #define CPU (CLKCTRL + 0x0050) #define HBUS (CLKCTRL + 0x0060) #define XBUS (CLKCTRL + 0x0070) #define XTAL (CLKCTRL + 0x0080) #define SSP0 (CLKCTRL + 0x0090) #define SSP1 (CLKCTRL + 0x00a0) #define SSP2 (CLKCTRL + 0x00b0) #define SSP3 (CLKCTRL + 0x00c0) #define GPMI (CLKCTRL + 0x00d0) #define SPDIF (CLKCTRL + 0x00e0) #define EMI (CLKCTRL + 0x00f0) #define SAIF0 (CLKCTRL + 0x0100) #define SAIF1 (CLKCTRL + 0x0110) #define LCDIF (CLKCTRL + 0x0120) #define ETM (CLKCTRL + 0x0130) #define ENET (CLKCTRL + 0x0140) #define FLEXCAN (CLKCTRL + 0x0160) #define FRAC0 (CLKCTRL + 0x01b0) #define FRAC1 (CLKCTRL + 0x01c0) #define CLKSEQ (CLKCTRL + 0x01d0) #define BP_CPU_INTERRUPT_WAIT 12 #define BP_SAIF_DIV_FRAC_EN 16 #define BP_ENET_DIV_TIME 21 #define BP_ENET_SLEEP 31 #define BP_CLKSEQ_BYPASS_SAIF0 0 #define BP_CLKSEQ_BYPASS_SSP0 3 #define BP_FRAC0_IO1FRAC 16 #define BP_FRAC0_IO0FRAC 24 static void __iomem *digctrl; #define DIGCTRL digctrl #define BP_SAIF_CLKMUX 10 /* * HW_SAIF_CLKMUX_SEL: * DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1 * clock pins selected for SAIF1 input clocks. * CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and * SAIF0 clock inputs selected for SAIF1 input clocks. * EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input * clocks. * EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input * clocks. */ int mxs_saif_clkmux_select(unsigned int clkmux) { if (clkmux > 0x3) return -EINVAL; writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR); writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET); return 0; } static void __init clk_misc_init(void) { u32 val; /* Gate off cpu clock in WFI for power saving */ writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); /* 0 is a bad default value for a divider */ writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET); /* Clear BYPASS for SAIF */ writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR); /* SAIF has to use frac div for functional operation */ val = readl_relaxed(SAIF0); val |= 1 << BP_SAIF_DIV_FRAC_EN; writel_relaxed(val, SAIF0); val = readl_relaxed(SAIF1); val |= 1 << BP_SAIF_DIV_FRAC_EN; writel_relaxed(val, SAIF1); /* Extra fec clock setting */ val = readl_relaxed(ENET); val &= ~(1 << BP_ENET_SLEEP); writel_relaxed(val, ENET); /* * Source ssp clock from ref_io than ref_xtal, * as ref_xtal only provides 24 MHz as maximum. */ writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR); /* * 480 MHz seems too high to be ssp clock source directly, * so set frac0 to get a 288 MHz ref_io0 and ref_io1. */ val = readl_relaxed(FRAC0); val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC)); val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC); writel_relaxed(val, FRAC0); } static const char *const sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; static const char *const sel_io0[] __initconst = { "ref_io0", "ref_xtal", }; static const char *const sel_io1[] __initconst = { "ref_io1", "ref_xtal", }; static const char *const sel_pix[] __initconst = { "ref_pix", "ref_xtal", }; static const char *const sel_gpmi[] __initconst = { "ref_gpmi", "ref_xtal", }; static const char *const sel_pll0[] __initconst = { "pll0", "ref_xtal", }; static const char *const cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", }; static const char *const emi_sels[] __initconst = { "emi_pll", "emi_xtal", }; static const char *const ptp_sels[] __initconst = { "ref_xtal", "pll0", }; enum imx28_clk { ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, ref_pix, ref_hsadc, ref_gpmi, saif0_sel, saif1_sel, gpmi_sel, ssp0_sel, ssp1_sel, ssp2_sel, ssp3_sel, emi_sel, etm_sel, lcdif_sel, cpu, ptp_sel, cpu_pll, cpu_xtal, hbus, xbus, ssp0_div, ssp1_div, ssp2_div, ssp3_div, gpmi_div, emi_pll, emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div, clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0, ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm, fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out, clk_max }; static struct clk *clks[clk_max]; static struct clk_onecell_data clk_data; static enum imx28_clk clks_init_on[] __initdata = { cpu, hbus, xbus, emi, uart, }; static void __init mx28_clocks_init(struct device_node *np) { struct device_node *dcnp; u32 i; dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl"); digctrl = of_iomap(dcnp, 0); WARN_ON(!digctrl); of_node_put(dcnp); clkctrl = of_iomap(np, 0); WARN_ON(!clkctrl); clk_misc_init(); clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1); clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2); clks[saif0_sel] = mxs_clk_mux("saif0_sel", CLKSEQ, 0, 1, sel_pll0, ARRAY_SIZE(sel_pll0)); clks[saif1_sel] = mxs_clk_mux("saif1_sel", CLKSEQ, 1, 1, sel_pll0, ARRAY_SIZE(sel_pll0)); clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi)); clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0)); clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0)); clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1)); clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1)); clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels)); clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu)); clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix)); clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels)); clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels)); clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28); clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31); clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31); clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29); clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29); clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29); clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29); clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29); clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28); clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29); clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29); clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29); clks[ptp] = mxs_clk_div("ptp", "ptp_sel", ENET, 21, 6, 27); clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29); clks[saif1_div] = mxs_clk_frac("saif1_div", "saif1_sel", SAIF1, 0, 16, 29); clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750); clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768); clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16); clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll0", 1, 4); clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26); clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31); clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31); clks[ssp2] = mxs_clk_gate("ssp2", "ssp2_div", SSP2, 31); clks[ssp3] = mxs_clk_gate("ssp3", "ssp3_div", SSP3, 31); clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31); clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31); clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31); clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31); clks[saif1] = mxs_clk_gate("saif1", "saif1_div", SAIF1, 31); clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31); clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30); clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30); clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28); clks[usb0] = mxs_clk_gate("usb0", "usb0_phy", DIGCTRL, 2); clks[usb1] = mxs_clk_gate("usb1", "usb1_phy", DIGCTRL, 16); clks[usb0_phy] = clk_register_gate(NULL, "usb0_phy", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock); clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock); clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock); for (i = 0; i < ARRAY_SIZE(clks); i++) if (IS_ERR(clks[i])) { pr_err("i.MX28 clk %d: register failed with %ld\n", i, PTR_ERR(clks[i])); return; } clk_data.clks = clks; clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); clk_register_clkdev(clks[enet_out], NULL, "enet_out"); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clks[clks_init_on[i]]); } CLK_OF_DECLARE(imx28_clkctrl, "fsl,imx28-clkctrl", mx28_clocks_init);
linux-master
drivers/clk/mxs/clk-imx28.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012 Freescale Semiconductor, Inc. */ #include <linux/err.h> #include <linux/io.h> #include <linux/jiffies.h> #include <linux/spinlock.h> #include "clk.h" DEFINE_SPINLOCK(mxs_lock); int mxs_clk_wait(void __iomem *reg, u8 shift) { unsigned long timeout = jiffies + msecs_to_jiffies(10); while (readl_relaxed(reg) & (1 << shift)) if (time_after(jiffies, timeout)) return -ETIMEDOUT; return 0; }
linux-master
drivers/clk/mxs/clk.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012 DENX Software Engineering, GmbH * * Pulled from code: * Portions copyright (C) 2003 Russell King, PXA MMCI Driver * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver * * Copyright 2008 Embedded Alley Solutions, Inc. * Copyright 2009-2011 Freescale Semiconductor, Inc. */ #include <linux/kernel.h> #include <linux/init.h> #include <linux/clk.h> #include <linux/module.h> #include <linux/device.h> #include <linux/io.h> #include <linux/spi/mxs-spi.h> void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate) { unsigned int ssp_clk, ssp_sck; u32 clock_divide, clock_rate; u32 val; ssp_clk = clk_get_rate(ssp->clk); for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) { clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide); clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0; if (clock_rate <= 255) break; } if (clock_divide > 254) { dev_err(ssp->dev, "%s: cannot set clock to %d\n", __func__, rate); return; } ssp_sck = ssp_clk / clock_divide / (1 + clock_rate); val = readl(ssp->base + HW_SSP_TIMING(ssp)); val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE); val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE); val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE); writel(val, ssp->base + HW_SSP_TIMING(ssp)); ssp->clk_rate = ssp_sck; dev_dbg(ssp->dev, "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n", __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate); } EXPORT_SYMBOL_GPL(mxs_ssp_set_clk_rate);
linux-master
drivers/clk/mxs/clk-ssp.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012 Freescale Semiconductor, Inc. */ #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/io.h> #include <linux/slab.h> #include "clk.h" /** * struct clk_ref - mxs reference clock * @hw: clk_hw for the reference clock * @reg: register address * @idx: the index of the reference clock within the same register * * The mxs reference clock sources from pll. Every 4 reference clocks share * one register space, and @idx is used to identify them. Each reference * clock has a gate control and a fractional * divider. The rate is calculated * as pll rate * (18 / FRAC), where FRAC = 18 ~ 35. */ struct clk_ref { struct clk_hw hw; void __iomem *reg; u8 idx; }; #define to_clk_ref(_hw) container_of(_hw, struct clk_ref, hw) static int clk_ref_enable(struct clk_hw *hw) { struct clk_ref *ref = to_clk_ref(hw); writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR); return 0; } static void clk_ref_disable(struct clk_hw *hw) { struct clk_ref *ref = to_clk_ref(hw); writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET); } static unsigned long clk_ref_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_ref *ref = to_clk_ref(hw); u64 tmp = parent_rate; u8 frac = (readl_relaxed(ref->reg) >> (ref->idx * 8)) & 0x3f; tmp *= 18; do_div(tmp, frac); return tmp; } static long clk_ref_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { unsigned long parent_rate = *prate; u64 tmp = parent_rate; u8 frac; tmp = tmp * 18 + rate / 2; do_div(tmp, rate); frac = tmp; if (frac < 18) frac = 18; else if (frac > 35) frac = 35; tmp = parent_rate; tmp *= 18; do_div(tmp, frac); return tmp; } static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_ref *ref = to_clk_ref(hw); unsigned long flags; u64 tmp = parent_rate; u32 val; u8 frac, shift = ref->idx * 8; tmp = tmp * 18 + rate / 2; do_div(tmp, rate); frac = tmp; if (frac < 18) frac = 18; else if (frac > 35) frac = 35; spin_lock_irqsave(&mxs_lock, flags); val = readl_relaxed(ref->reg); val &= ~(0x3f << shift); val |= frac << shift; writel_relaxed(val, ref->reg); spin_unlock_irqrestore(&mxs_lock, flags); return 0; } static const struct clk_ops clk_ref_ops = { .enable = clk_ref_enable, .disable = clk_ref_disable, .recalc_rate = clk_ref_recalc_rate, .round_rate = clk_ref_round_rate, .set_rate = clk_ref_set_rate, }; struct clk *mxs_clk_ref(const char *name, const char *parent_name, void __iomem *reg, u8 idx) { struct clk_ref *ref; struct clk *clk; struct clk_init_data init; ref = kzalloc(sizeof(*ref), GFP_KERNEL); if (!ref) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &clk_ref_ops; init.flags = 0; init.parent_names = (parent_name ? &parent_name: NULL); init.num_parents = (parent_name ? 1 : 0); ref->reg = reg; ref->idx = idx; ref->hw.init = &init; clk = clk_register(NULL, &ref->hw); if (IS_ERR(clk)) kfree(ref); return clk; }
linux-master
drivers/clk/mxs/clk-ref.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012 Freescale Semiconductor, Inc. */ #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/slab.h> #include "clk.h" /** * struct clk_div - mxs integer divider clock * @divider: the parent class * @ops: pointer to clk_ops of parent class * @reg: register address * @busy: busy bit shift * * The mxs divider clock is a subclass of basic clk_divider with an * addtional busy bit. */ struct clk_div { struct clk_divider divider; const struct clk_ops *ops; void __iomem *reg; u8 busy; }; static inline struct clk_div *to_clk_div(struct clk_hw *hw) { struct clk_divider *divider = to_clk_divider(hw); return container_of(divider, struct clk_div, divider); } static unsigned long clk_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_div *div = to_clk_div(hw); return div->ops->recalc_rate(&div->divider.hw, parent_rate); } static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_div *div = to_clk_div(hw); return div->ops->round_rate(&div->divider.hw, rate, prate); } static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_div *div = to_clk_div(hw); int ret; ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); if (!ret) ret = mxs_clk_wait(div->reg, div->busy); return ret; } static const struct clk_ops clk_div_ops = { .recalc_rate = clk_div_recalc_rate, .round_rate = clk_div_round_rate, .set_rate = clk_div_set_rate, }; struct clk *mxs_clk_div(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy) { struct clk_div *div; struct clk *clk; struct clk_init_data init; div = kzalloc(sizeof(*div), GFP_KERNEL); if (!div) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &clk_div_ops; init.flags = CLK_SET_RATE_PARENT; init.parent_names = (parent_name ? &parent_name: NULL); init.num_parents = (parent_name ? 1 : 0); div->reg = reg; div->busy = busy; div->divider.reg = reg; div->divider.shift = shift; div->divider.width = width; div->divider.flags = CLK_DIVIDER_ONE_BASED; div->divider.lock = &mxs_lock; div->divider.hw.init = &init; div->ops = &clk_divider_ops; clk = clk_register(NULL, &div->divider.hw); if (IS_ERR(clk)) kfree(div); return clk; }
linux-master
drivers/clk/mxs/clk-div.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012 Freescale Semiconductor, Inc. */ #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/io.h> #include <linux/slab.h> #include "clk.h" /** * struct clk_frac - mxs fractional divider clock * @hw: clk_hw for the fractional divider clock * @reg: register address * @shift: the divider bit shift * @width: the divider bit width * @busy: busy bit shift * * The clock is an adjustable fractional divider with a busy bit to wait * when the divider is adjusted. */ struct clk_frac { struct clk_hw hw; void __iomem *reg; u8 shift; u8 width; u8 busy; }; #define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw) static unsigned long clk_frac_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_frac *frac = to_clk_frac(hw); u32 div; u64 tmp_rate; div = readl_relaxed(frac->reg) >> frac->shift; div &= (1 << frac->width) - 1; tmp_rate = (u64)parent_rate * div; return tmp_rate >> frac->width; } static long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_frac *frac = to_clk_frac(hw); unsigned long parent_rate = *prate; u32 div; u64 tmp, tmp_rate, result; if (rate > parent_rate) return -EINVAL; tmp = rate; tmp <<= frac->width; do_div(tmp, parent_rate); div = tmp; if (!div) return -EINVAL; tmp_rate = (u64)parent_rate * div; result = tmp_rate >> frac->width; if ((result << frac->width) < tmp_rate) result += 1; return result; } static int clk_frac_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_frac *frac = to_clk_frac(hw); unsigned long flags; u32 div, val; u64 tmp; if (rate > parent_rate) return -EINVAL; tmp = rate; tmp <<= frac->width; do_div(tmp, parent_rate); div = tmp; if (!div) return -EINVAL; spin_lock_irqsave(&mxs_lock, flags); val = readl_relaxed(frac->reg); val &= ~(((1 << frac->width) - 1) << frac->shift); val |= div << frac->shift; writel_relaxed(val, frac->reg); spin_unlock_irqrestore(&mxs_lock, flags); return mxs_clk_wait(frac->reg, frac->busy); } static const struct clk_ops clk_frac_ops = { .recalc_rate = clk_frac_recalc_rate, .round_rate = clk_frac_round_rate, .set_rate = clk_frac_set_rate, }; struct clk *mxs_clk_frac(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, u8 busy) { struct clk_frac *frac; struct clk *clk; struct clk_init_data init; frac = kzalloc(sizeof(*frac), GFP_KERNEL); if (!frac) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &clk_frac_ops; init.flags = CLK_SET_RATE_PARENT; init.parent_names = (parent_name ? &parent_name: NULL); init.num_parents = (parent_name ? 1 : 0); frac->reg = reg; frac->shift = shift; frac->width = width; frac->busy = busy; frac->hw.init = &init; clk = clk_register(NULL, &frac->hw); if (IS_ERR(clk)) kfree(frac); return clk; }
linux-master
drivers/clk/mxs/clk-frac.c
// SPDX-License-Identifier: GPL-2.0 // // Spreadtrum clock infrastructure // // Copyright (C) 2017 Spreadtrum, Inc. // Author: Chunyan Zhang <[email protected]> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of_address.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include "common.h" static const struct regmap_config sprdclk_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .fast_io = true, }; static void sprd_clk_set_regmap(const struct sprd_clk_desc *desc, struct regmap *regmap) { int i; struct sprd_clk_common *cclk; for (i = 0; i < desc->num_clk_clks; i++) { cclk = desc->clk_clks[i]; if (!cclk) continue; cclk->regmap = regmap; } } int sprd_clk_regmap_init(struct platform_device *pdev, const struct sprd_clk_desc *desc) { void __iomem *base; struct device *dev = &pdev->dev; struct device_node *node = dev->of_node, *np; struct regmap *regmap; struct resource *res; struct regmap_config reg_config = sprdclk_regmap_config; if (of_property_present(node, "sprd,syscon")) { regmap = syscon_regmap_lookup_by_phandle(node, "sprd,syscon"); if (IS_ERR(regmap)) { pr_err("%s: failed to get syscon regmap\n", __func__); return PTR_ERR(regmap); } } else if (of_device_is_compatible(np = of_get_parent(node), "syscon") || (of_node_put(np), 0)) { regmap = device_node_to_regmap(np); of_node_put(np); if (IS_ERR(regmap)) { dev_err(dev, "failed to get regmap from its parent.\n"); return PTR_ERR(regmap); } } else { base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(base)) return PTR_ERR(base); reg_config.max_register = resource_size(res) - reg_config.reg_stride; regmap = devm_regmap_init_mmio(&pdev->dev, base, &reg_config); if (IS_ERR(regmap)) { pr_err("failed to init regmap\n"); return PTR_ERR(regmap); } } sprd_clk_set_regmap(desc, regmap); return 0; } EXPORT_SYMBOL_GPL(sprd_clk_regmap_init); int sprd_clk_probe(struct device *dev, struct clk_hw_onecell_data *clkhw) { int i, ret; struct clk_hw *hw; for (i = 0; i < clkhw->num; i++) { const char *name; hw = clkhw->hws[i]; if (!hw) continue; name = hw->init->name; ret = devm_clk_hw_register(dev, hw); if (ret) { dev_err(dev, "Couldn't register clock %d - %s\n", i, name); return ret; } } ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clkhw); if (ret) dev_err(dev, "Failed to add clock provider\n"); return ret; } EXPORT_SYMBOL_GPL(sprd_clk_probe); MODULE_LICENSE("GPL v2");
linux-master
drivers/clk/sprd/common.c
// SPDX-License-Identifier: GPL-2.0 // // Spreadtrum gate clock driver // // Copyright (C) 2017 Spreadtrum, Inc. // Author: Chunyan Zhang <[email protected]> #include <linux/clk-provider.h> #include <linux/regmap.h> #include "gate.h" static void clk_gate_toggle(const struct sprd_gate *sg, bool en) { const struct sprd_clk_common *common = &sg->common; unsigned int reg; bool set = sg->flags & CLK_GATE_SET_TO_DISABLE ? true : false; set ^= en; regmap_read(common->regmap, common->reg, &reg); if (set) reg |= sg->enable_mask; else reg &= ~sg->enable_mask; regmap_write(common->regmap, common->reg, reg); } static void clk_sc_gate_toggle(const struct sprd_gate *sg, bool en) { const struct sprd_clk_common *common = &sg->common; bool set = sg->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; unsigned int offset; set ^= en; /* * Each set/clear gate clock has three registers: * common->reg - base register * common->reg + offset - set register * common->reg + 2 * offset - clear register */ offset = set ? sg->sc_offset : sg->sc_offset * 2; regmap_write(common->regmap, common->reg + offset, sg->enable_mask); } static void sprd_gate_disable(struct clk_hw *hw) { struct sprd_gate *sg = hw_to_sprd_gate(hw); clk_gate_toggle(sg, false); } static int sprd_gate_enable(struct clk_hw *hw) { struct sprd_gate *sg = hw_to_sprd_gate(hw); clk_gate_toggle(sg, true); return 0; } static void sprd_sc_gate_disable(struct clk_hw *hw) { struct sprd_gate *sg = hw_to_sprd_gate(hw); clk_sc_gate_toggle(sg, false); } static int sprd_sc_gate_enable(struct clk_hw *hw) { struct sprd_gate *sg = hw_to_sprd_gate(hw); clk_sc_gate_toggle(sg, true); return 0; } static int sprd_pll_sc_gate_prepare(struct clk_hw *hw) { struct sprd_gate *sg = hw_to_sprd_gate(hw); clk_sc_gate_toggle(sg, true); udelay(sg->udelay); return 0; } static int sprd_gate_is_enabled(struct clk_hw *hw) { struct sprd_gate *sg = hw_to_sprd_gate(hw); struct sprd_clk_common *common = &sg->common; struct clk_hw *parent; unsigned int reg; if (sg->flags & SPRD_GATE_NON_AON) { parent = clk_hw_get_parent(hw); if (!parent || !clk_hw_is_enabled(parent)) return 0; } regmap_read(common->regmap, common->reg, &reg); if (sg->flags & CLK_GATE_SET_TO_DISABLE) reg ^= sg->enable_mask; reg &= sg->enable_mask; return reg ? 1 : 0; } const struct clk_ops sprd_gate_ops = { .disable = sprd_gate_disable, .enable = sprd_gate_enable, .is_enabled = sprd_gate_is_enabled, }; EXPORT_SYMBOL_GPL(sprd_gate_ops); const struct clk_ops sprd_sc_gate_ops = { .disable = sprd_sc_gate_disable, .enable = sprd_sc_gate_enable, .is_enabled = sprd_gate_is_enabled, }; EXPORT_SYMBOL_GPL(sprd_sc_gate_ops); const struct clk_ops sprd_pll_sc_gate_ops = { .unprepare = sprd_sc_gate_disable, .prepare = sprd_pll_sc_gate_prepare, .is_enabled = sprd_gate_is_enabled, }; EXPORT_SYMBOL_GPL(sprd_pll_sc_gate_ops);
linux-master
drivers/clk/sprd/gate.c
// SPDX-License-Identifier: GPL-2.0 /* * Unisoc UMS512 clock driver * * Copyright (C) 2022 Unisoc, Inc. * Author: Xiaolong Zhang <[email protected]> */ #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/io.h> #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <dt-bindings/clock/sprd,ums512-clk.h> #include "common.h" #include "composite.h" #include "div.h" #include "gate.h" #include "mux.h" #include "pll.h" #define UMS512_MUX_FLAG \ (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT) /* pll gate clock */ /* some pll clocks configure CLK_IGNORE_UNUSED because hw dvfs does not call * clock interface. hw dvfs can not gate the pll clock. */ static CLK_FIXED_FACTOR_FW_NAME(clk_26m_aud, "clk-26m-aud", "ext-26m", 1, 1, 0); static CLK_FIXED_FACTOR_FW_NAME(clk_13m, "clk-13m", "ext-26m", 2, 1, 0); static CLK_FIXED_FACTOR_FW_NAME(clk_6m5, "clk-6m5", "ext-26m", 4, 1, 0); static CLK_FIXED_FACTOR_FW_NAME(clk_4m3, "clk-4m3", "ext-26m", 6, 1, 0); static CLK_FIXED_FACTOR_FW_NAME(clk_2m, "clk-2m", "ext-26m", 13, 1, 0); static CLK_FIXED_FACTOR_FW_NAME(clk_1m, "clk-1m", "ext-26m", 26, 1, 0); static CLK_FIXED_FACTOR_FW_NAME(clk_250k, "clk-250k", "ext-26m", 104, 1, 0); static CLK_FIXED_FACTOR_FW_NAME(rco_25m, "rco-25m", "rco-100m", 4, 1, 0); static CLK_FIXED_FACTOR_FW_NAME(rco_4m, "rco-4m", "rco-100m", 25, 1, 0); static CLK_FIXED_FACTOR_FW_NAME(rco_2m, "rco-2m", "rco-100m", 50, 1, 0); static SPRD_PLL_SC_GATE_CLK_FW_NAME(isppll_gate, "isppll-gate", "ext-26m", 0x8c, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98, 0x1000, BIT(0), 0, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x9c, 0x1000, BIT(0), 0, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0xa0, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(twpll_gate, "twpll-gate", "ext-26m", 0xa4, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(rpll_gate, "rpll-gate", "ext-26m", 0xac, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(cppll_gate, "cppll-gate", "ext-26m", 0xe4, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x190, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x194, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x198, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); static struct sprd_clk_common *ums512_pmu_gate_clks[] = { /* address base is 0x327e0000 */ &isppll_gate.common, &dpll0_gate.common, &dpll1_gate.common, &lpll_gate.common, &twpll_gate.common, &gpll_gate.common, &rpll_gate.common, &cppll_gate.common, &mpll0_gate.common, &mpll1_gate.common, &mpll2_gate.common, }; static struct clk_hw_onecell_data ums512_pmu_gate_hws = { .hws = { [CLK_26M_AUD] = &clk_26m_aud.hw, [CLK_13M] = &clk_13m.hw, [CLK_6M5] = &clk_6m5.hw, [CLK_4M3] = &clk_4m3.hw, [CLK_2M] = &clk_2m.hw, [CLK_1M] = &clk_1m.hw, [CLK_250K] = &clk_250k.hw, [CLK_RCO_25M] = &rco_25m.hw, [CLK_RCO_4M] = &rco_4m.hw, [CLK_RCO_2M] = &rco_2m.hw, [CLK_ISPPLL_GATE] = &isppll_gate.common.hw, [CLK_DPLL0_GATE] = &dpll0_gate.common.hw, [CLK_DPLL1_GATE] = &dpll1_gate.common.hw, [CLK_LPLL_GATE] = &lpll_gate.common.hw, [CLK_TWPLL_GATE] = &twpll_gate.common.hw, [CLK_GPLL_GATE] = &gpll_gate.common.hw, [CLK_RPLL_GATE] = &rpll_gate.common.hw, [CLK_CPPLL_GATE] = &cppll_gate.common.hw, [CLK_MPLL0_GATE] = &mpll0_gate.common.hw, [CLK_MPLL1_GATE] = &mpll1_gate.common.hw, [CLK_MPLL2_GATE] = &mpll2_gate.common.hw, }, .num = CLK_PMU_GATE_NUM, }; static struct sprd_clk_desc ums512_pmu_gate_desc = { .clk_clks = ums512_pmu_gate_clks, .num_clk_clks = ARRAY_SIZE(ums512_pmu_gate_clks), .hw_clks = &ums512_pmu_gate_hws, }; /* pll clock at g0 */ static const u64 itable_dpll0[7] = { 6, 0, 0, 1173000000ULL, 1475000000ULL, 1855000000ULL, 1866000000ULL }; static struct clk_bit_field f_dpll0[PLL_FACT_MAX] = { { .shift = 18, .width = 1 }, /* lock_done */ { .shift = 0, .width = 1 }, /* div_s */ { .shift = 67, .width = 1 }, /* mod_en */ { .shift = 1, .width = 1 }, /* sdm_en */ { .shift = 0, .width = 0 }, /* refin */ { .shift = 4, .width = 3 }, /* icp */ { .shift = 7, .width = 11 }, /* n */ { .shift = 55, .width = 7 }, /* nint */ { .shift = 32, .width = 23}, /* kint */ { .shift = 0, .width = 0 }, /* prediv */ { .shift = 0, .width = 0 }, /* postdiv */ }; static SPRD_PLL_HW(dpll0, "dpll0", &dpll0_gate.common.hw, 0x4, 3, itable_dpll0, f_dpll0, 240, 1000, 1000, 0, 0); static CLK_FIXED_FACTOR_HW(dpll0_58m31, "dpll0-58m31", &dpll0.common.hw, 32, 1, 0); static struct sprd_clk_common *ums512_g0_pll_clks[] = { /* address base is 0x32390000 */ &dpll0.common, }; static struct clk_hw_onecell_data ums512_g0_pll_hws = { .hws = { [CLK_DPLL0] = &dpll0.common.hw, [CLK_DPLL0_58M31] = &dpll0_58m31.hw, }, .num = CLK_ANLG_PHY_G0_NUM, }; static struct sprd_clk_desc ums512_g0_pll_desc = { .clk_clks = ums512_g0_pll_clks, .num_clk_clks = ARRAY_SIZE(ums512_g0_pll_clks), .hw_clks = &ums512_g0_pll_hws, }; /* pll clock at g2 */ static const u64 itable_mpll[8] = { 7, 0, 1400000000ULL, 1600000000ULL, 1800000000ULL, 2000000000ULL, 2200000000ULL, 2500000000ULL }; static struct clk_bit_field f_mpll[PLL_FACT_MAX] = { { .shift = 17, .width = 1 }, /* lock_done */ { .shift = 0, .width = 1 }, /* div_s */ { .shift = 67, .width = 1 }, /* mod_en */ { .shift = 1, .width = 1 }, /* sdm_en */ { .shift = 0, .width = 0 }, /* refin */ { .shift = 2, .width = 3 }, /* icp */ { .shift = 5, .width = 11 }, /* n */ { .shift = 55, .width = 7 }, /* nint */ { .shift = 32, .width = 23}, /* kint */ { .shift = 0, .width = 0 }, /* prediv */ { .shift = 77, .width = 1 }, /* postdiv */ }; static SPRD_PLL_HW(mpll1, "mpll1", &mpll1_gate.common.hw, 0x0, 3, itable_mpll, f_mpll, 240, 1000, 1000, 1, 1200000000); static CLK_FIXED_FACTOR_HW(mpll1_63m38, "mpll1-63m38", &mpll1.common.hw, 32, 1, 0); static struct sprd_clk_common *ums512_g2_pll_clks[] = { /* address base is 0x323B0000 */ &mpll1.common, }; static struct clk_hw_onecell_data ums512_g2_pll_hws = { .hws = { [CLK_MPLL1] = &mpll1.common.hw, [CLK_MPLL1_63M38] = &mpll1_63m38.hw, }, .num = CLK_ANLG_PHY_G2_NUM, }; static struct sprd_clk_desc ums512_g2_pll_desc = { .clk_clks = ums512_g2_pll_clks, .num_clk_clks = ARRAY_SIZE(ums512_g2_pll_clks), .hw_clks = &ums512_g2_pll_hws, }; /* pll at g3 */ static const u64 itable[8] = { 7, 0, 0, 900000000ULL, 1100000000ULL, 1300000000ULL, 1500000000ULL, 1600000000ULL }; static struct clk_bit_field f_pll[PLL_FACT_MAX] = { { .shift = 18, .width = 1 }, /* lock_done */ { .shift = 0, .width = 1 }, /* div_s */ { .shift = 67, .width = 1 }, /* mod_en */ { .shift = 1, .width = 1 }, /* sdm_en */ { .shift = 0, .width = 0 }, /* refin */ { .shift = 2, .width = 3 }, /* icp */ { .shift = 5, .width = 11 }, /* n */ { .shift = 55, .width = 7 }, /* nint */ { .shift = 32, .width = 23}, /* kint */ { .shift = 0, .width = 0 }, /* prediv */ { .shift = 77, .width = 1 }, /* postdiv */ }; static SPRD_PLL_FW_NAME(rpll, "rpll", "ext-26m", 0x0, 3, itable, f_pll, 240, 1000, 1000, 1, 750000000); static SPRD_SC_GATE_CLK_FW_NAME(audio_gate, "audio-gate", "ext-26m", 0x24, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); static struct clk_bit_field f_mpll2[PLL_FACT_MAX] = { { .shift = 16, .width = 1 }, /* lock_done */ { .shift = 0, .width = 1 }, /* div_s */ { .shift = 67, .width = 1 }, /* mod_en */ { .shift = 1, .width = 1 }, /* sdm_en */ { .shift = 0, .width = 0 }, /* refin */ { .shift = 2, .width = 3 }, /* icp */ { .shift = 5, .width = 11 }, /* n */ { .shift = 55, .width = 7 }, /* nint */ { .shift = 32, .width = 23}, /* kint */ { .shift = 0, .width = 0 }, /* prediv */ { .shift = 77, .width = 1 }, /* postdiv */ }; static SPRD_PLL_HW(mpll0, "mpll0", &mpll0_gate.common.hw, 0x54, 3, itable_mpll, f_mpll, 240, 1000, 1000, 1, 1200000000); static CLK_FIXED_FACTOR_HW(mpll0_56m88, "mpll0-56m88", &mpll0.common.hw, 32, 1, 0); static const u64 itable_mpll2[6] = { 5, 1200000000ULL, 1400000000ULL, 1600000000ULL, 1800000000ULL, 2000000000ULL }; static SPRD_PLL_HW(mpll2, "mpll2", &mpll2_gate.common.hw, 0x9c, 3, itable_mpll2, f_mpll2, 240, 1000, 1000, 1, 1000000000); static CLK_FIXED_FACTOR_HW(mpll2_47m13, "mpll2-47m13", &mpll2.common.hw, 32, 1, 0); static struct sprd_clk_common *ums512_g3_pll_clks[] = { /* address base is 0x323c0000 */ &rpll.common, &audio_gate.common, &mpll0.common, &mpll2.common, }; static struct clk_hw_onecell_data ums512_g3_pll_hws = { .hws = { [CLK_RPLL] = &rpll.common.hw, [CLK_AUDIO_GATE] = &audio_gate.common.hw, [CLK_MPLL0] = &mpll0.common.hw, [CLK_MPLL0_56M88] = &mpll0_56m88.hw, [CLK_MPLL2] = &mpll2.common.hw, [CLK_MPLL2_47M13] = &mpll2_47m13.hw, }, .num = CLK_ANLG_PHY_G3_NUM, }; static struct sprd_clk_desc ums512_g3_pll_desc = { .clk_clks = ums512_g3_pll_clks, .num_clk_clks = ARRAY_SIZE(ums512_g3_pll_clks), .hw_clks = &ums512_g3_pll_hws, }; /* pll clock at gc */ static SPRD_PLL_FW_NAME(twpll, "twpll", "ext-26m", 0x0, 3, itable, f_pll, 240, 1000, 1000, 1, 750000000); static CLK_FIXED_FACTOR_HW(twpll_768m, "twpll-768m", &twpll.common.hw, 2, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_384m, "twpll-384m", &twpll.common.hw, 4, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_192m, "twpll-192m", &twpll.common.hw, 8, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_96m, "twpll-96m", &twpll.common.hw, 16, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_48m, "twpll-48m", &twpll.common.hw, 32, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_24m, "twpll-24m", &twpll.common.hw, 64, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_12m, "twpll-12m", &twpll.common.hw, 128, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_512m, "twpll-512m", &twpll.common.hw, 3, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_256m, "twpll-256m", &twpll.common.hw, 6, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_128m, "twpll-128m", &twpll.common.hw, 12, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_64m, "twpll-64m", &twpll.common.hw, 24, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_307m2, "twpll-307m2", &twpll.common.hw, 5, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_219m4, "twpll-219m4", &twpll.common.hw, 7, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_170m6, "twpll-170m6", &twpll.common.hw, 9, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_153m6, "twpll-153m6", &twpll.common.hw, 10, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_76m8, "twpll-76m8", &twpll.common.hw, 20, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_51m2, "twpll-51m2", &twpll.common.hw, 30, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_38m4, "twpll-38m4", &twpll.common.hw, 40, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_19m2, "twpll-19m2", &twpll.common.hw, 80, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_12m29, "twpll-12m29", &twpll.common.hw, 125, 1, 0); static SPRD_PLL_FW_NAME(lpll, "lpll", "ext-26m", 0x18, 3, itable, f_pll, 240, 1000, 1000, 1, 750000000); static CLK_FIXED_FACTOR_HW(lpll_614m4, "lpll-614m4", &lpll.common.hw, 2, 1, 0); static CLK_FIXED_FACTOR_HW(lpll_409m6, "lpll-409m6", &lpll.common.hw, 3, 1, 0); static CLK_FIXED_FACTOR_HW(lpll_245m76, "lpll-245m76", &lpll.common.hw, 5, 1, 0); static CLK_FIXED_FACTOR_HW(lpll_30m72, "lpll-30m72", &lpll.common.hw, 40, 1, 0); static SPRD_PLL_FW_NAME(isppll, "isppll", "ext-26m", 0x30, 3, itable, f_pll, 240, 1000, 1000, 1, 750000000); static CLK_FIXED_FACTOR_HW(isppll_468m, "isppll-468m", &isppll.common.hw, 2, 1, 0); static CLK_FIXED_FACTOR_HW(isppll_78m, "isppll-78m", &isppll.common.hw, 12, 1, 0); static SPRD_PLL_HW(gpll, "gpll", &gpll_gate.common.hw, 0x48, 3, itable, f_pll, 240, 1000, 1000, 1, 750000000); static CLK_FIXED_FACTOR_HW(gpll_40m, "gpll-40m", &gpll.common.hw, 20, 1, 0); static SPRD_PLL_HW(cppll, "cppll", &cppll_gate.common.hw, 0x60, 3, itable, f_pll, 240, 1000, 1000, 1, 750000000); static CLK_FIXED_FACTOR_HW(cppll_39m32, "cppll-39m32", &cppll.common.hw, 26, 1, 0); static struct sprd_clk_common *ums512_gc_pll_clks[] = { /* address base is 0x323e0000 */ &twpll.common, &lpll.common, &isppll.common, &gpll.common, &cppll.common, }; static struct clk_hw_onecell_data ums512_gc_pll_hws = { .hws = { [CLK_TWPLL] = &twpll.common.hw, [CLK_TWPLL_768M] = &twpll_768m.hw, [CLK_TWPLL_384M] = &twpll_384m.hw, [CLK_TWPLL_192M] = &twpll_192m.hw, [CLK_TWPLL_96M] = &twpll_96m.hw, [CLK_TWPLL_48M] = &twpll_48m.hw, [CLK_TWPLL_24M] = &twpll_24m.hw, [CLK_TWPLL_12M] = &twpll_12m.hw, [CLK_TWPLL_512M] = &twpll_512m.hw, [CLK_TWPLL_256M] = &twpll_256m.hw, [CLK_TWPLL_128M] = &twpll_128m.hw, [CLK_TWPLL_64M] = &twpll_64m.hw, [CLK_TWPLL_307M2] = &twpll_307m2.hw, [CLK_TWPLL_219M4] = &twpll_219m4.hw, [CLK_TWPLL_170M6] = &twpll_170m6.hw, [CLK_TWPLL_153M6] = &twpll_153m6.hw, [CLK_TWPLL_76M8] = &twpll_76m8.hw, [CLK_TWPLL_51M2] = &twpll_51m2.hw, [CLK_TWPLL_38M4] = &twpll_38m4.hw, [CLK_TWPLL_19M2] = &twpll_19m2.hw, [CLK_TWPLL_12M29] = &twpll_12m29.hw, [CLK_LPLL] = &lpll.common.hw, [CLK_LPLL_614M4] = &lpll_614m4.hw, [CLK_LPLL_409M6] = &lpll_409m6.hw, [CLK_LPLL_245M76] = &lpll_245m76.hw, [CLK_LPLL_30M72] = &lpll_30m72.hw, [CLK_ISPPLL] = &isppll.common.hw, [CLK_ISPPLL_468M] = &isppll_468m.hw, [CLK_ISPPLL_78M] = &isppll_78m.hw, [CLK_GPLL] = &gpll.common.hw, [CLK_GPLL_40M] = &gpll_40m.hw, [CLK_CPPLL] = &cppll.common.hw, [CLK_CPPLL_39M32] = &cppll_39m32.hw, }, .num = CLK_ANLG_PHY_GC_NUM, }; static struct sprd_clk_desc ums512_gc_pll_desc = { .clk_clks = ums512_gc_pll_clks, .num_clk_clks = ARRAY_SIZE(ums512_gc_pll_clks), .hw_clks = &ums512_gc_pll_hws, }; /* ap ahb gates */ static SPRD_SC_GATE_CLK_FW_NAME(dsi_eb, "dsi-eb", "ext-26m", 0x0, 0x1000, BIT(0), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(dispc_eb, "dispc-eb", "ext-26m", 0x0, 0x1000, BIT(1), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(vsp_eb, "vsp-eb", "ext-26m", 0x0, 0x1000, BIT(2), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(vdma_eb, "vdma-eb", "ext-26m", 0x0, 0x1000, BIT(3), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(dma_pub_eb, "dma-pub-eb", "ext-26m", 0x0, 0x1000, BIT(4), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(dma_sec_eb, "dma-sec-eb", "ext-26m", 0x0, 0x1000, BIT(5), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(ipi_eb, "ipi-eb", "ext-26m", 0x0, 0x1000, BIT(6), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(ahb_ckg_eb, "ahb-ckg-eb", "ext-26m", 0x0, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(bm_clk_eb, "bm-clk-eb", "ext-26m", 0x0, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); static struct sprd_clk_common *ums512_apahb_gate[] = { /* address base is 0x20100000 */ &dsi_eb.common, &dispc_eb.common, &vsp_eb.common, &vdma_eb.common, &dma_pub_eb.common, &dma_sec_eb.common, &ipi_eb.common, &ahb_ckg_eb.common, &bm_clk_eb.common, }; static struct clk_hw_onecell_data ums512_apahb_gate_hws = { .hws = { [CLK_DSI_EB] = &dsi_eb.common.hw, [CLK_DISPC_EB] = &dispc_eb.common.hw, [CLK_VSP_EB] = &vsp_eb.common.hw, [CLK_VDMA_EB] = &vdma_eb.common.hw, [CLK_DMA_PUB_EB] = &dma_pub_eb.common.hw, [CLK_DMA_SEC_EB] = &dma_sec_eb.common.hw, [CLK_IPI_EB] = &ipi_eb.common.hw, [CLK_AHB_CKG_EB] = &ahb_ckg_eb.common.hw, [CLK_BM_CLK_EB] = &bm_clk_eb.common.hw, }, .num = CLK_AP_AHB_GATE_NUM, }; static struct sprd_clk_desc ums512_apahb_gate_desc = { .clk_clks = ums512_apahb_gate, .num_clk_clks = ARRAY_SIZE(ums512_apahb_gate), .hw_clks = &ums512_apahb_gate_hws, }; /* ap clks */ static const struct clk_parent_data ap_apb_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_64m.hw }, { .hw = &twpll_96m.hw }, { .hw = &twpll_128m.hw }, }; static SPRD_MUX_CLK_DATA(ap_apb_clk, "ap-apb-clk", ap_apb_parents, 0x20, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data ipi_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_64m.hw }, { .hw = &twpll_96m.hw }, { .hw = &twpll_128m.hw }, }; static SPRD_MUX_CLK_DATA(ipi_clk, "ipi-clk", ipi_parents, 0x24, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data ap_uart_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_48m.hw }, { .hw = &twpll_51m2.hw }, { .hw = &twpll_96m.hw }, }; static SPRD_COMP_CLK_DATA(ap_uart0_clk, "ap-uart0-clk", ap_uart_parents, 0x28, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_uart1_clk, "ap-uart1-clk", ap_uart_parents, 0x2c, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_uart2_clk, "ap-uart2-clk", ap_uart_parents, 0x30, 0, 2, 8, 3, 0); static const struct clk_parent_data i2c_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_48m.hw }, { .hw = &twpll_51m2.hw }, { .hw = &twpll_153m6.hw }, }; static SPRD_COMP_CLK_DATA(ap_i2c0_clk, "ap-i2c0-clk", i2c_parents, 0x34, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_i2c1_clk, "ap-i2c1-clk", i2c_parents, 0x38, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_i2c2_clk, "ap-i2c2-clk", i2c_parents, 0x3c, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_i2c3_clk, "ap-i2c3-clk", i2c_parents, 0x40, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_i2c4_clk, "ap-i2c4-clk", i2c_parents, 0x44, 0, 2, 8, 3, 0); static const struct clk_parent_data spi_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, { .hw = &twpll_192m.hw }, }; static SPRD_COMP_CLK_DATA(ap_spi0_clk, "ap-spi0-clk", spi_parents, 0x48, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_spi1_clk, "ap-spi1-clk", spi_parents, 0x4c, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_spi2_clk, "ap-spi2-clk", spi_parents, 0x50, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_spi3_clk, "ap-spi3-clk", spi_parents, 0x54, 0, 2, 8, 3, 0); static const struct clk_parent_data iis_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, }; static SPRD_COMP_CLK_DATA(ap_iis0_clk, "ap-iis0-clk", iis_parents, 0x58, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_iis1_clk, "ap-iis1-clk", iis_parents, 0x5c, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_iis2_clk, "ap-iis2-clk", iis_parents, 0x60, 0, 2, 8, 3, 0); static const struct clk_parent_data sim_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_51m2.hw }, { .hw = &twpll_64m.hw }, { .hw = &twpll_96m.hw }, { .hw = &twpll_128m.hw }, }; static SPRD_COMP_CLK_DATA(ap_sim_clk, "ap-sim-clk", sim_parents, 0x64, 0, 3, 8, 3, 0); static const struct clk_parent_data ap_ce_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_96m.hw }, { .hw = &twpll_192m.hw }, { .hw = &twpll_256m.hw }, }; static SPRD_MUX_CLK_DATA(ap_ce_clk, "ap-ce-clk", ap_ce_parents, 0x68, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data sdio_parents[] = { { .hw = &clk_1m.hw }, { .fw_name = "ext-26m" }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, { .hw = &rpll.common.hw }, { .hw = &lpll_409m6.hw }, }; static SPRD_MUX_CLK_DATA(sdio0_2x_clk, "sdio0-2x", sdio_parents, 0x80, 0, 3, UMS512_MUX_FLAG); static SPRD_MUX_CLK_DATA(sdio1_2x_clk, "sdio1-2x", sdio_parents, 0x88, 0, 3, UMS512_MUX_FLAG); static SPRD_MUX_CLK_DATA(emmc_2x_clk, "emmc-2x", sdio_parents, 0x90, 0, 3, UMS512_MUX_FLAG); static const struct clk_parent_data vsp_parents[] = { { .hw = &twpll_256m.hw }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, }; static SPRD_MUX_CLK_DATA(vsp_clk, "vsp-clk", vsp_parents, 0x98, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data dispc0_parents[] = { { .hw = &twpll_153m6.hw }, { .hw = &twpll_192m.hw }, { .hw = &twpll_256m.hw }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, }; static SPRD_MUX_CLK_DATA(dispc0_clk, "dispc0-clk", dispc0_parents, 0x9c, 0, 3, UMS512_MUX_FLAG); static const struct clk_parent_data dispc0_dpi_parents[] = { { .hw = &twpll_96m.hw }, { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, { .hw = &twpll_192m.hw }, }; static SPRD_COMP_CLK_DATA(dispc0_dpi_clk, "dispc0-dpi-clk", dispc0_dpi_parents, 0xa0, 0, 3, 8, 4, 0); static const struct clk_parent_data dsi_apb_parents[] = { { .hw = &twpll_96m.hw }, { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, { .hw = &twpll_192m.hw }, }; static SPRD_MUX_CLK_DATA(dsi_apb_clk, "dsi-apb-clk", dsi_apb_parents, 0xa4, 0, 2, UMS512_MUX_FLAG); static SPRD_GATE_CLK_FW_NAME(dsi_rxesc, "dsi-rxesc", "ext-26m", 0xa8, BIT(16), 0, 0); static SPRD_GATE_CLK_FW_NAME(dsi_lanebyte, "dsi-lanebyte", "ext-26m", 0xac, BIT(16), 0, 0); static const struct clk_parent_data vdsp_parents[] = { { .hw = &twpll_256m.hw }, { .hw = &twpll_384m.hw }, { .hw = &twpll_512m.hw }, { .hw = &lpll_614m4.hw }, { .hw = &twpll_768m.hw }, { .hw = &isppll.common.hw }, }; static SPRD_MUX_CLK_DATA(vdsp_clk, "vdsp-clk", vdsp_parents, 0xb0, 0, 3, UMS512_MUX_FLAG); static SPRD_DIV_CLK_HW(vdsp_m_clk, "vdsp-m-clk", &vdsp_clk.common.hw, 0xb4, 8, 2, 0); static struct sprd_clk_common *ums512_ap_clks[] = { /* address base is 0x20200000 */ &ap_apb_clk.common, &ipi_clk.common, &ap_uart0_clk.common, &ap_uart1_clk.common, &ap_uart2_clk.common, &ap_i2c0_clk.common, &ap_i2c1_clk.common, &ap_i2c2_clk.common, &ap_i2c3_clk.common, &ap_i2c4_clk.common, &ap_spi0_clk.common, &ap_spi1_clk.common, &ap_spi2_clk.common, &ap_spi3_clk.common, &ap_iis0_clk.common, &ap_iis1_clk.common, &ap_iis2_clk.common, &ap_sim_clk.common, &ap_ce_clk.common, &sdio0_2x_clk.common, &sdio1_2x_clk.common, &emmc_2x_clk.common, &vsp_clk.common, &dispc0_clk.common, &dispc0_dpi_clk.common, &dsi_apb_clk.common, &dsi_rxesc.common, &dsi_lanebyte.common, &vdsp_clk.common, &vdsp_m_clk.common, }; static struct clk_hw_onecell_data ums512_ap_clk_hws = { .hws = { [CLK_AP_APB] = &ap_apb_clk.common.hw, [CLK_IPI] = &ipi_clk.common.hw, [CLK_AP_UART0] = &ap_uart0_clk.common.hw, [CLK_AP_UART1] = &ap_uart1_clk.common.hw, [CLK_AP_UART2] = &ap_uart2_clk.common.hw, [CLK_AP_I2C0] = &ap_i2c0_clk.common.hw, [CLK_AP_I2C1] = &ap_i2c1_clk.common.hw, [CLK_AP_I2C2] = &ap_i2c2_clk.common.hw, [CLK_AP_I2C3] = &ap_i2c3_clk.common.hw, [CLK_AP_I2C4] = &ap_i2c4_clk.common.hw, [CLK_AP_SPI0] = &ap_spi0_clk.common.hw, [CLK_AP_SPI1] = &ap_spi1_clk.common.hw, [CLK_AP_SPI2] = &ap_spi2_clk.common.hw, [CLK_AP_SPI3] = &ap_spi3_clk.common.hw, [CLK_AP_IIS0] = &ap_iis0_clk.common.hw, [CLK_AP_IIS1] = &ap_iis1_clk.common.hw, [CLK_AP_IIS2] = &ap_iis2_clk.common.hw, [CLK_AP_SIM] = &ap_sim_clk.common.hw, [CLK_AP_CE] = &ap_ce_clk.common.hw, [CLK_SDIO0_2X] = &sdio0_2x_clk.common.hw, [CLK_SDIO1_2X] = &sdio1_2x_clk.common.hw, [CLK_EMMC_2X] = &emmc_2x_clk.common.hw, [CLK_VSP] = &vsp_clk.common.hw, [CLK_DISPC0] = &dispc0_clk.common.hw, [CLK_DISPC0_DPI] = &dispc0_dpi_clk.common.hw, [CLK_DSI_APB] = &dsi_apb_clk.common.hw, [CLK_DSI_RXESC] = &dsi_rxesc.common.hw, [CLK_DSI_LANEBYTE] = &dsi_lanebyte.common.hw, [CLK_VDSP] = &vdsp_clk.common.hw, [CLK_VDSP_M] = &vdsp_m_clk.common.hw, }, .num = CLK_AP_CLK_NUM, }; static struct sprd_clk_desc ums512_ap_clk_desc = { .clk_clks = ums512_ap_clks, .num_clk_clks = ARRAY_SIZE(ums512_ap_clks), .hw_clks = &ums512_ap_clk_hws, }; /* aon apb clks */ static const struct clk_parent_data aon_apb_parents[] = { { .hw = &rco_4m.hw }, { .fw_name = "ext-4m" }, { .hw = &clk_13m.hw }, { .hw = &rco_25m.hw }, { .fw_name = "ext-26m" }, { .hw = &twpll_96m.hw }, { .fw_name = "rco-100m" }, { .hw = &twpll_128m.hw }, }; static SPRD_COMP_CLK_DATA(aon_apb_clk, "aon-apb-clk", aon_apb_parents, 0x220, 0, 3, 8, 2, 0); static const struct clk_parent_data adi_parents[] = { { .hw = &rco_4m.hw }, { .fw_name = "ext-26m" }, { .hw = &rco_25m.hw }, { .hw = &twpll_38m4.hw }, { .hw = &twpll_51m2.hw }, }; static SPRD_MUX_CLK_DATA(adi_clk, "adi-clk", adi_parents, 0x224, 0, 3, UMS512_MUX_FLAG); static const struct clk_parent_data aux_parents[] = { { .fw_name = "ext-32k" }, { .fw_name = "ext-26m" }, { .hw = &clk_26m_aud.hw }, { .hw = &rco_25m.hw }, { .hw = &cppll_39m32.hw }, { .hw = &mpll0_56m88.hw }, { .hw = &mpll1_63m38.hw }, { .hw = &mpll2_47m13.hw }, { .hw = &dpll0_58m31.hw }, { .hw = &gpll_40m.hw }, { .hw = &twpll_48m.hw }, }; static const struct clk_parent_data aux1_parents[] = { { .fw_name = "ext-32k" }, { .fw_name = "ext-26m" }, { .hw = &clk_26m_aud.hw }, { .hw = &rco_25m.hw }, { .hw = &cppll_39m32.hw }, { .hw = &mpll0_56m88.hw }, { .hw = &mpll1_63m38.hw }, { .hw = &mpll2_47m13.hw }, { .hw = &dpll0_58m31.hw }, { .hw = &gpll_40m.hw }, { .hw = &twpll_19m2.hw }, { .hw = &lpll_30m72.hw }, { .hw = &rpll.common.hw }, { .hw = &twpll_12m29.hw }, }; static SPRD_COMP_CLK_DATA(aux0_clk, "aux0-clk", aux_parents, 0x228, 0, 5, 8, 4, 0); static SPRD_COMP_CLK_DATA(aux1_clk, "aux1-clk", aux1_parents, 0x22c, 0, 5, 8, 4, 0); static SPRD_COMP_CLK_DATA(aux2_clk, "aux2-clk", aux_parents, 0x230, 0, 5, 8, 4, 0); static SPRD_COMP_CLK_DATA(probe_clk, "probe-clk", aux_parents, 0x234, 0, 5, 8, 4, 0); static const struct clk_parent_data pwm_parents[] = { { .fw_name = "ext-32k" }, { .fw_name = "ext-26m" }, { .hw = &rco_4m.hw }, { .hw = &rco_25m.hw }, { .hw = &twpll_48m.hw }, }; static SPRD_MUX_CLK_DATA(pwm0_clk, "pwm0-clk", pwm_parents, 0x238, 0, 3, UMS512_MUX_FLAG); static SPRD_MUX_CLK_DATA(pwm1_clk, "pwm1-clk", pwm_parents, 0x23c, 0, 3, UMS512_MUX_FLAG); static SPRD_MUX_CLK_DATA(pwm2_clk, "pwm2-clk", pwm_parents, 0x240, 0, 3, UMS512_MUX_FLAG); static SPRD_MUX_CLK_DATA(pwm3_clk, "pwm3-clk", pwm_parents, 0x244, 0, 3, UMS512_MUX_FLAG); static const struct clk_parent_data efuse_parents[] = { { .hw = &rco_25m.hw }, { .fw_name = "ext-26m" }, }; static SPRD_MUX_CLK_DATA(efuse_clk, "efuse-clk", efuse_parents, 0x248, 0, 1, UMS512_MUX_FLAG); static const struct clk_parent_data uart_parents[] = { { .hw = &rco_4m.hw }, { .fw_name = "ext-26m" }, { .hw = &twpll_48m.hw }, { .hw = &twpll_51m2.hw }, { .hw = &twpll_96m.hw }, { .fw_name = "rco-100m" }, { .hw = &twpll_128m.hw }, }; static SPRD_MUX_CLK_DATA(uart0_clk, "uart0-clk", uart_parents, 0x24c, 0, 3, UMS512_MUX_FLAG); static SPRD_MUX_CLK_DATA(uart1_clk, "uart1-clk", uart_parents, 0x250, 0, 3, UMS512_MUX_FLAG); static const struct clk_parent_data thm_parents[] = { { .fw_name = "ext-32m" }, { .hw = &clk_250k.hw }, }; static SPRD_MUX_CLK_DATA(thm0_clk, "thm0-clk", thm_parents, 0x260, 0, 1, UMS512_MUX_FLAG); static SPRD_MUX_CLK_DATA(thm1_clk, "thm1-clk", thm_parents, 0x264, 0, 1, UMS512_MUX_FLAG); static SPRD_MUX_CLK_DATA(thm2_clk, "thm2-clk", thm_parents, 0x268, 0, 1, UMS512_MUX_FLAG); static SPRD_MUX_CLK_DATA(thm3_clk, "thm3-clk", thm_parents, 0x26c, 0, 1, UMS512_MUX_FLAG); static const struct clk_parent_data aon_i2c_parents[] = { { .hw = &rco_4m.hw }, { .fw_name = "ext-26m" }, { .hw = &twpll_48m.hw }, { .hw = &twpll_51m2.hw }, { .fw_name = "rco-100m" }, { .hw = &twpll_153m6.hw }, }; static SPRD_MUX_CLK_DATA(aon_i2c_clk, "aon-i2c-clk", aon_i2c_parents, 0x27c, 0, 3, UMS512_MUX_FLAG); static const struct clk_parent_data aon_iis_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, }; static SPRD_MUX_CLK_DATA(aon_iis_clk, "aon-iis-clk", aon_iis_parents, 0x280, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data scc_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_48m.hw }, { .hw = &twpll_51m2.hw }, { .hw = &twpll_96m.hw }, }; static SPRD_MUX_CLK_DATA(scc_clk, "scc-clk", scc_parents, 0x284, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data apcpu_dap_parents[] = { { .fw_name = "ext-26m" }, { .hw = &rco_4m.hw }, { .hw = &twpll_76m8.hw }, { .fw_name = "rco-100m" }, { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, }; static SPRD_MUX_CLK_DATA(apcpu_dap_clk, "apcpu-dap-clk", apcpu_dap_parents, 0x288, 0, 3, UMS512_MUX_FLAG); static SPRD_GATE_CLK_FW_NAME(apcpu_dap_mtck, "apcpu-dap-mtck", "ext-26m", 0x28c, BIT(16), 0, 0); static const struct clk_parent_data apcpu_ts_parents[] = { { .fw_name = "ext-32m" }, { .fw_name = "ext-26m" }, { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, }; static SPRD_MUX_CLK_DATA(apcpu_ts_clk, "apcpu-ts-clk", apcpu_ts_parents, 0x290, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data debug_ts_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_76m8.hw }, { .hw = &twpll_128m.hw }, { .hw = &twpll_192m.hw }, }; static SPRD_MUX_CLK_DATA(debug_ts_clk, "debug-ts-clk", debug_ts_parents, 0x294, 0, 2, UMS512_MUX_FLAG); static SPRD_GATE_CLK_FW_NAME(dsi_test_s, "dsi-test-s", "ext-26m", 0x298, BIT(16), 0, 0); static const struct clk_parent_data djtag_tck_parents[] = { { .hw = &rco_4m.hw }, { .fw_name = "ext-26m" }, }; static SPRD_MUX_CLK_DATA(djtag_tck_clk, "djtag-tck-clk", djtag_tck_parents, 0x2b4, 0, 1, UMS512_MUX_FLAG); static SPRD_GATE_CLK_FW_NAME(djtag_tck_hw, "djtag-tck-hw", "ext-26m", 0x2b8, BIT(16), 0, 0); static const struct clk_parent_data aon_tmr_parents[] = { { .hw = &rco_4m.hw }, { .hw = &rco_25m.hw }, { .fw_name = "ext-26m" }, }; static SPRD_MUX_CLK_DATA(aon_tmr_clk, "aon-tmr-clk", aon_tmr_parents, 0x2c0, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data aon_pmu_parents[] = { { .fw_name = "ext-32k" }, { .hw = &rco_4m.hw }, { .fw_name = "ext-4m" }, }; static SPRD_MUX_CLK_DATA(aon_pmu_clk, "aon-pmu-clk", aon_pmu_parents, 0x2c8, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data debounce_parents[] = { { .fw_name = "ext-32k" }, { .hw = &rco_4m.hw }, { .hw = &rco_25m.hw }, { .fw_name = "ext-26m" }, }; static SPRD_MUX_CLK_DATA(debounce_clk, "debounce-clk", debounce_parents, 0x2cc, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data apcpu_pmu_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_76m8.hw }, { .fw_name = "rco-100m" }, { .hw = &twpll_128m.hw }, }; static SPRD_MUX_CLK_DATA(apcpu_pmu_clk, "apcpu-pmu-clk", apcpu_pmu_parents, 0x2d0, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data top_dvfs_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_96m.hw }, { .fw_name = "rco-100m" }, { .hw = &twpll_128m.hw }, }; static SPRD_MUX_CLK_DATA(top_dvfs_clk, "top-dvfs-clk", top_dvfs_parents, 0x2d8, 0, 2, UMS512_MUX_FLAG); static SPRD_GATE_CLK_FW_NAME(otg_utmi, "otg-utmi", "ext-26m", 0x2dc, BIT(16), 0, 0); static const struct clk_parent_data otg_ref_parents[] = { { .hw = &twpll_12m.hw }, { .fw_name = "ext-26m" }, }; static SPRD_MUX_CLK_DATA(otg_ref_clk, "otg-ref-clk", otg_ref_parents, 0x2e0, 0, 1, UMS512_MUX_FLAG); static const struct clk_parent_data cssys_parents[] = { { .hw = &rco_25m.hw }, { .fw_name = "ext-26m" }, { .fw_name = "rco-100m" }, { .hw = &twpll_153m6.hw }, { .hw = &twpll_384m.hw }, { .hw = &twpll_512m.hw }, }; static SPRD_COMP_CLK_DATA(cssys_clk, "cssys-clk", cssys_parents, 0x2e4, 0, 3, 8, 2, 0); static SPRD_DIV_CLK_HW(cssys_pub_clk, "cssys-pub-clk", &cssys_clk.common.hw, 0x2e8, 8, 2, 0); static SPRD_DIV_CLK_HW(cssys_apb_clk, "cssys-apb-clk", &cssys_clk.common.hw, 0x2ec, 8, 3, 0); static const struct clk_parent_data ap_axi_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_76m8.hw }, { .hw = &twpll_128m.hw }, { .hw = &twpll_256m.hw }, }; static SPRD_MUX_CLK_DATA(ap_axi_clk, "ap-axi-clk", ap_axi_parents, 0x2f0, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data ap_mm_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_96m.hw }, { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, }; static SPRD_MUX_CLK_DATA(ap_mm_clk, "ap-mm-clk", ap_mm_parents, 0x2f4, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data sdio2_2x_parents[] = { { .hw = &clk_1m.hw }, { .fw_name = "ext-26m" }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, { .hw = &rpll.common.hw }, { .hw = &lpll_409m6.hw }, }; static SPRD_MUX_CLK_DATA(sdio2_2x_clk, "sdio2-2x-clk", sdio2_2x_parents, 0x2f8, 0, 3, UMS512_MUX_FLAG); static const struct clk_parent_data analog_io_apb_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_48m.hw }, }; static SPRD_COMP_CLK_DATA(analog_io_apb, "analog-io-apb", analog_io_apb_parents, 0x300, 0, 1, 8, 2, 0); static const struct clk_parent_data dmc_ref_parents[] = { { .hw = &clk_6m5.hw }, { .hw = &clk_13m.hw }, { .fw_name = "ext-26m" }, }; static SPRD_MUX_CLK_DATA(dmc_ref_clk, "dmc-ref-clk", dmc_ref_parents, 0x304, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data emc_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_384m.hw }, { .hw = &twpll_512m.hw }, { .hw = &twpll_768m.hw }, }; static SPRD_MUX_CLK_DATA(emc_clk, "emc-clk", emc_parents, 0x30c, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data usb_parents[] = { { .hw = &rco_25m.hw }, { .fw_name = "ext-26m" }, { .hw = &twpll_192m.hw }, { .hw = &twpll_96m.hw }, { .fw_name = "rco-100m" }, { .hw = &twpll_128m.hw }, }; static SPRD_COMP_CLK_DATA(usb_clk, "usb-clk", usb_parents, 0x310, 0, 3, 8, 2, 0); static const struct clk_parent_data pmu_26m_parents[] = { { .hw = &rco_25m.hw }, { .fw_name = "ext-26m" }, }; static SPRD_MUX_CLK_DATA(pmu_26m_clk, "26m-pmu-clk", pmu_26m_parents, 0x318, 0, 1, UMS512_MUX_FLAG); static struct sprd_clk_common *ums512_aon_apb[] = { /* address base is 0x32080200 */ &aon_apb_clk.common, &adi_clk.common, &aux0_clk.common, &aux1_clk.common, &aux2_clk.common, &probe_clk.common, &pwm0_clk.common, &pwm1_clk.common, &pwm2_clk.common, &pwm3_clk.common, &efuse_clk.common, &uart0_clk.common, &uart1_clk.common, &thm0_clk.common, &thm1_clk.common, &thm2_clk.common, &thm3_clk.common, &aon_i2c_clk.common, &aon_iis_clk.common, &scc_clk.common, &apcpu_dap_clk.common, &apcpu_dap_mtck.common, &apcpu_ts_clk.common, &debug_ts_clk.common, &dsi_test_s.common, &djtag_tck_clk.common, &djtag_tck_hw.common, &aon_tmr_clk.common, &aon_pmu_clk.common, &debounce_clk.common, &apcpu_pmu_clk.common, &top_dvfs_clk.common, &otg_utmi.common, &otg_ref_clk.common, &cssys_clk.common, &cssys_pub_clk.common, &cssys_apb_clk.common, &ap_axi_clk.common, &ap_mm_clk.common, &sdio2_2x_clk.common, &analog_io_apb.common, &dmc_ref_clk.common, &emc_clk.common, &usb_clk.common, &pmu_26m_clk.common, }; static struct clk_hw_onecell_data ums512_aon_apb_hws = { .hws = { [CLK_AON_APB] = &aon_apb_clk.common.hw, [CLK_ADI] = &adi_clk.common.hw, [CLK_AUX0] = &aux0_clk.common.hw, [CLK_AUX1] = &aux1_clk.common.hw, [CLK_AUX2] = &aux2_clk.common.hw, [CLK_PROBE] = &probe_clk.common.hw, [CLK_PWM0] = &pwm0_clk.common.hw, [CLK_PWM1] = &pwm1_clk.common.hw, [CLK_PWM2] = &pwm2_clk.common.hw, [CLK_PWM3] = &pwm3_clk.common.hw, [CLK_EFUSE] = &efuse_clk.common.hw, [CLK_UART0] = &uart0_clk.common.hw, [CLK_UART1] = &uart1_clk.common.hw, [CLK_THM0] = &thm0_clk.common.hw, [CLK_THM1] = &thm1_clk.common.hw, [CLK_THM2] = &thm2_clk.common.hw, [CLK_THM3] = &thm3_clk.common.hw, [CLK_AON_I2C] = &aon_i2c_clk.common.hw, [CLK_AON_IIS] = &aon_iis_clk.common.hw, [CLK_SCC] = &scc_clk.common.hw, [CLK_APCPU_DAP] = &apcpu_dap_clk.common.hw, [CLK_APCPU_DAP_MTCK] = &apcpu_dap_mtck.common.hw, [CLK_APCPU_TS] = &apcpu_ts_clk.common.hw, [CLK_DEBUG_TS] = &debug_ts_clk.common.hw, [CLK_DSI_TEST_S] = &dsi_test_s.common.hw, [CLK_DJTAG_TCK] = &djtag_tck_clk.common.hw, [CLK_DJTAG_TCK_HW] = &djtag_tck_hw.common.hw, [CLK_AON_TMR] = &aon_tmr_clk.common.hw, [CLK_AON_PMU] = &aon_pmu_clk.common.hw, [CLK_DEBOUNCE] = &debounce_clk.common.hw, [CLK_APCPU_PMU] = &apcpu_pmu_clk.common.hw, [CLK_TOP_DVFS] = &top_dvfs_clk.common.hw, [CLK_OTG_UTMI] = &otg_utmi.common.hw, [CLK_OTG_REF] = &otg_ref_clk.common.hw, [CLK_CSSYS] = &cssys_clk.common.hw, [CLK_CSSYS_PUB] = &cssys_pub_clk.common.hw, [CLK_CSSYS_APB] = &cssys_apb_clk.common.hw, [CLK_AP_AXI] = &ap_axi_clk.common.hw, [CLK_AP_MM] = &ap_mm_clk.common.hw, [CLK_SDIO2_2X] = &sdio2_2x_clk.common.hw, [CLK_ANALOG_IO_APB] = &analog_io_apb.common.hw, [CLK_DMC_REF_CLK] = &dmc_ref_clk.common.hw, [CLK_EMC] = &emc_clk.common.hw, [CLK_USB] = &usb_clk.common.hw, [CLK_26M_PMU] = &pmu_26m_clk.common.hw, }, .num = CLK_AON_APB_NUM, }; static struct sprd_clk_desc ums512_aon_apb_desc = { .clk_clks = ums512_aon_apb, .num_clk_clks = ARRAY_SIZE(ums512_aon_apb), .hw_clks = &ums512_aon_apb_hws, }; /* aon apb gates */ static SPRD_SC_GATE_CLK_FW_NAME(rc100m_cal_eb, "rc100m-cal-eb", "ext-26m", 0x0, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(djtag_tck_eb, "djtag-tck-eb", "ext-26m", 0x0, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(djtag_eb, "djtag-eb", "ext-26m", 0x0, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(aux0_eb, "aux0-eb", "ext-26m", 0x0, 0x1000, BIT(4), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(aux1_eb, "aux1-eb", "ext-26m", 0x0, 0x1000, BIT(5), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(aux2_eb, "aux2-eb", "ext-26m", 0x0, 0x1000, BIT(6), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(probe_eb, "probe-eb", "ext-26m", 0x0, 0x1000, BIT(7), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(mm_eb, "mm-eb", "ext-26m", 0x0, 0x1000, BIT(9), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(gpu_eb, "gpu-eb", "ext-26m", 0x0, 0x1000, BIT(11), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(mspi_eb, "mspi-eb", "ext-26m", 0x0, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(apcpu_dap_eb, "apcpu-dap-eb", "ext-26m", 0x0, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(aon_cssys_eb, "aon-cssys-eb", "ext-26m", 0x0, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(cssys_apb_eb, "cssys-apb-eb", "ext-26m", 0x0, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(cssys_pub_eb, "cssys-pub-eb", "ext-26m", 0x0, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(sdphy_cfg_eb, "sdphy-cfg-eb", "ext-26m", 0x0, 0x1000, BIT(19), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(sdphy_ref_eb, "sdphy-ref-eb", "ext-26m", 0x0, 0x1000, BIT(20), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(efuse_eb, "efuse-eb", "ext-26m", 0x4, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(gpio_eb, "gpio-eb", "ext-26m", 0x4, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(mbox_eb, "mbox-eb", "ext-26m", 0x4, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(kpd_eb, "kpd-eb", "ext-26m", 0x4, 0x1000, BIT(3), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(aon_syst_eb, "aon-syst-eb", "ext-26m", 0x4, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_syst_eb, "ap-syst-eb", "ext-26m", 0x4, 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(aon_tmr_eb, "aon-tmr-eb", "ext-26m", 0x4, 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(otg_utmi_eb, "otg-utmi-eb", "ext-26m", 0x4, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(otg_phy_eb, "otg-phy-eb", "ext-26m", 0x4, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(splk_eb, "splk-eb", "ext-26m", 0x4, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(pin_eb, "pin-eb", "ext-26m", 0x4, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ana_eb, "ana-eb", "ext-26m", 0x4, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(apcpu_ts0_eb, "apcpu-ts0-eb", "ext-26m", 0x4, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(apb_busmon_eb, "apb-busmon-eb", "ext-26m", 0x4, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(aon_iis_eb, "aon-iis-eb", "ext-26m", 0x4, 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(scc_eb, "scc-eb", "ext-26m", 0x4, 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(thm0_eb, "thm0-eb", "ext-26m", 0x8, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(thm1_eb, "thm1-eb", "ext-26m", 0x8, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(thm2_eb, "thm2-eb", "ext-26m", 0x8, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(asim_top_eb, "asim-top", "ext-26m", 0x8, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(i2c_eb, "i2c-eb", "ext-26m", 0x8, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(pmu_eb, "pmu-eb", "ext-26m", 0x8, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(adi_eb, "adi-eb", "ext-26m", 0x8, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(eic_eb, "eic-eb", "ext-26m", 0x8, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_intc0_eb, "ap-intc0-eb", "ext-26m", 0x8, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_intc1_eb, "ap-intc1-eb", "ext-26m", 0x8, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_intc2_eb, "ap-intc2-eb", "ext-26m", 0x8, 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_intc3_eb, "ap-intc3-eb", "ext-26m", 0x8, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_intc4_eb, "ap-intc4-eb", "ext-26m", 0x8, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_intc5_eb, "ap-intc5-eb", "ext-26m", 0x8, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(audcp_intc_eb, "audcp-intc-eb", "ext-26m", 0x8, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr0_eb, "ap-tmr0-eb", "ext-26m", 0x8, 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr1_eb, "ap-tmr1-eb", "ext-26m", 0x8, 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr2_eb, "ap-tmr2-eb", "ext-26m", 0x8, 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(pwm0_eb, "pwm0-eb", "ext-26m", 0x8, 0x1000, BIT(25), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(pwm1_eb, "pwm1-eb", "ext-26m", 0x8, 0x1000, BIT(26), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(pwm2_eb, "pwm2-eb", "ext-26m", 0x8, 0x1000, BIT(27), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(pwm3_eb, "pwm3-eb", "ext-26m", 0x8, 0x1000, BIT(28), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_wdg_eb, "ap-wdg-eb", "ext-26m", 0x8, 0x1000, BIT(29), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(apcpu_wdg_eb, "apcpu-wdg-eb", "ext-26m", 0x8, 0x1000, BIT(30), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(serdes_eb, "serdes-eb", "ext-26m", 0x8, 0x1000, BIT(31), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(arch_rtc_eb, "arch-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(kpd_rtc_eb, "kpd-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(aon_syst_rtc_eb, "aon-syst-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_syst_rtc_eb, "ap-syst-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(aon_tmr_rtc_eb, "aon-tmr-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(eic_rtc_eb, "eic-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(eic_rtcdv5_eb, "eic-rtcdv5-eb", "ext-26m", 0x18, 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_wdg_rtc_eb, "ap-wdg-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ac_wdg_rtc_eb, "ac-wdg-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr0_rtc_eb, "ap-tmr0-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr1_rtc_eb, "ap-tmr1-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr2_rtc_eb, "ap-tmr2-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(dcxo_lc_rtc_eb, "dcxo-lc-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(bb_cal_rtc_eb, "bb-cal-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_emmc_rtc_eb, "ap-emmc-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_sdio0_rtc_eb, "ap-sdio0-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_sdio1_rtc_eb, "ap-sdio1-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_sdio2_rtc_eb, "ap-sdio2-rtc-eb", "ext-26m", 0x18, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(dsi_csi_test_eb, "dsi-csi-test-eb", "ext-26m", 0x138, 0x1000, BIT(8), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(djtag_tck_en, "djtag-tck-en", "ext-26m", 0x138, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(dphy_ref_eb, "dphy-ref-eb", "ext-26m", 0x138, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(dmc_ref_eb, "dmc-ref-eb", "ext-26m", 0x138, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(otg_ref_eb, "otg-ref-eb", "ext-26m", 0x138, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(tsen_eb, "tsen-eb", "ext-26m", 0x138, 0x1000, BIT(13), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(tmr_eb, "tmr-eb", "ext-26m", 0x138, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(rc100m_ref_eb, "rc100m-ref-eb", "ext-26m", 0x138, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(rc100m_fdk_eb, "rc100m-fdk-eb", "ext-26m", 0x138, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(debounce_eb, "debounce-eb", "ext-26m", 0x138, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(det_32k_eb, "det-32k-eb", "ext-26m", 0x138, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(top_cssys_en, "top-cssys-en", "ext-26m", 0x13c, 0x1000, BIT(0), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(ap_axi_en, "ap-axi-en", "ext-26m", 0x13c, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(sdio0_2x_en, "sdio0-2x-en", "ext-26m", 0x13c, 0x1000, BIT(2), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(sdio0_1x_en, "sdio0-1x-en", "ext-26m", 0x13c, 0x1000, BIT(3), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(sdio1_2x_en, "sdio1-2x-en", "ext-26m", 0x13c, 0x1000, BIT(4), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(sdio1_1x_en, "sdio1-1x-en", "ext-26m", 0x13c, 0x1000, BIT(5), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(sdio2_2x_en, "sdio2-2x-en", "ext-26m", 0x13c, 0x1000, BIT(6), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(sdio2_1x_en, "sdio2-1x-en", "ext-26m", 0x13c, 0x1000, BIT(7), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(emmc_2x_en, "emmc-2x-en", "ext-26m", 0x13c, 0x1000, BIT(8), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(emmc_1x_en, "emmc-1x-en", "ext-26m", 0x13c, 0x1000, BIT(9), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(pll_test_en, "pll-test-en", "ext-26m", 0x13c, 0x1000, BIT(14), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(cphy_cfg_en, "cphy-cfg-en", "ext-26m", 0x13c, 0x1000, BIT(15), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(debug_ts_en, "debug-ts-en", "ext-26m", 0x13c, 0x1000, BIT(18), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(access_aud_en, "access-aud-en", "ext-26m", 0x14c, 0x1000, BIT(0), 0, 0); static struct sprd_clk_common *ums512_aon_gate[] = { /* address base is 0x327d0000 */ &rc100m_cal_eb.common, &djtag_tck_eb.common, &djtag_eb.common, &aux0_eb.common, &aux1_eb.common, &aux2_eb.common, &probe_eb.common, &mm_eb.common, &gpu_eb.common, &mspi_eb.common, &apcpu_dap_eb.common, &aon_cssys_eb.common, &cssys_apb_eb.common, &cssys_pub_eb.common, &sdphy_cfg_eb.common, &sdphy_ref_eb.common, &efuse_eb.common, &gpio_eb.common, &mbox_eb.common, &kpd_eb.common, &aon_syst_eb.common, &ap_syst_eb.common, &aon_tmr_eb.common, &otg_utmi_eb.common, &otg_phy_eb.common, &splk_eb.common, &pin_eb.common, &ana_eb.common, &apcpu_ts0_eb.common, &apb_busmon_eb.common, &aon_iis_eb.common, &scc_eb.common, &thm0_eb.common, &thm1_eb.common, &thm2_eb.common, &asim_top_eb.common, &i2c_eb.common, &pmu_eb.common, &adi_eb.common, &eic_eb.common, &ap_intc0_eb.common, &ap_intc1_eb.common, &ap_intc2_eb.common, &ap_intc3_eb.common, &ap_intc4_eb.common, &ap_intc5_eb.common, &audcp_intc_eb.common, &ap_tmr0_eb.common, &ap_tmr1_eb.common, &ap_tmr2_eb.common, &pwm0_eb.common, &pwm1_eb.common, &pwm2_eb.common, &pwm3_eb.common, &ap_wdg_eb.common, &apcpu_wdg_eb.common, &serdes_eb.common, &arch_rtc_eb.common, &kpd_rtc_eb.common, &aon_syst_rtc_eb.common, &ap_syst_rtc_eb.common, &aon_tmr_rtc_eb.common, &eic_rtc_eb.common, &eic_rtcdv5_eb.common, &ap_wdg_rtc_eb.common, &ac_wdg_rtc_eb.common, &ap_tmr0_rtc_eb.common, &ap_tmr1_rtc_eb.common, &ap_tmr2_rtc_eb.common, &dcxo_lc_rtc_eb.common, &bb_cal_rtc_eb.common, &ap_emmc_rtc_eb.common, &ap_sdio0_rtc_eb.common, &ap_sdio1_rtc_eb.common, &ap_sdio2_rtc_eb.common, &dsi_csi_test_eb.common, &djtag_tck_en.common, &dphy_ref_eb.common, &dmc_ref_eb.common, &otg_ref_eb.common, &tsen_eb.common, &tmr_eb.common, &rc100m_ref_eb.common, &rc100m_fdk_eb.common, &debounce_eb.common, &det_32k_eb.common, &top_cssys_en.common, &ap_axi_en.common, &sdio0_2x_en.common, &sdio0_1x_en.common, &sdio1_2x_en.common, &sdio1_1x_en.common, &sdio2_2x_en.common, &sdio2_1x_en.common, &emmc_2x_en.common, &emmc_1x_en.common, &pll_test_en.common, &cphy_cfg_en.common, &debug_ts_en.common, &access_aud_en.common, }; static struct clk_hw_onecell_data ums512_aon_gate_hws = { .hws = { [CLK_RC100M_CAL_EB] = &rc100m_cal_eb.common.hw, [CLK_DJTAG_TCK_EB] = &djtag_tck_eb.common.hw, [CLK_DJTAG_EB] = &djtag_eb.common.hw, [CLK_AUX0_EB] = &aux0_eb.common.hw, [CLK_AUX1_EB] = &aux1_eb.common.hw, [CLK_AUX2_EB] = &aux2_eb.common.hw, [CLK_PROBE_EB] = &probe_eb.common.hw, [CLK_MM_EB] = &mm_eb.common.hw, [CLK_GPU_EB] = &gpu_eb.common.hw, [CLK_MSPI_EB] = &mspi_eb.common.hw, [CLK_APCPU_DAP_EB] = &apcpu_dap_eb.common.hw, [CLK_AON_CSSYS_EB] = &aon_cssys_eb.common.hw, [CLK_CSSYS_APB_EB] = &cssys_apb_eb.common.hw, [CLK_CSSYS_PUB_EB] = &cssys_pub_eb.common.hw, [CLK_SDPHY_CFG_EB] = &sdphy_cfg_eb.common.hw, [CLK_SDPHY_REF_EB] = &sdphy_ref_eb.common.hw, [CLK_EFUSE_EB] = &efuse_eb.common.hw, [CLK_GPIO_EB] = &gpio_eb.common.hw, [CLK_MBOX_EB] = &mbox_eb.common.hw, [CLK_KPD_EB] = &kpd_eb.common.hw, [CLK_AON_SYST_EB] = &aon_syst_eb.common.hw, [CLK_AP_SYST_EB] = &ap_syst_eb.common.hw, [CLK_AON_TMR_EB] = &aon_tmr_eb.common.hw, [CLK_OTG_UTMI_EB] = &otg_utmi_eb.common.hw, [CLK_OTG_PHY_EB] = &otg_phy_eb.common.hw, [CLK_SPLK_EB] = &splk_eb.common.hw, [CLK_PIN_EB] = &pin_eb.common.hw, [CLK_ANA_EB] = &ana_eb.common.hw, [CLK_APCPU_TS0_EB] = &apcpu_ts0_eb.common.hw, [CLK_APB_BUSMON_EB] = &apb_busmon_eb.common.hw, [CLK_AON_IIS_EB] = &aon_iis_eb.common.hw, [CLK_SCC_EB] = &scc_eb.common.hw, [CLK_THM0_EB] = &thm0_eb.common.hw, [CLK_THM1_EB] = &thm1_eb.common.hw, [CLK_THM2_EB] = &thm2_eb.common.hw, [CLK_ASIM_TOP_EB] = &asim_top_eb.common.hw, [CLK_I2C_EB] = &i2c_eb.common.hw, [CLK_PMU_EB] = &pmu_eb.common.hw, [CLK_ADI_EB] = &adi_eb.common.hw, [CLK_EIC_EB] = &eic_eb.common.hw, [CLK_AP_INTC0_EB] = &ap_intc0_eb.common.hw, [CLK_AP_INTC1_EB] = &ap_intc1_eb.common.hw, [CLK_AP_INTC2_EB] = &ap_intc2_eb.common.hw, [CLK_AP_INTC3_EB] = &ap_intc3_eb.common.hw, [CLK_AP_INTC4_EB] = &ap_intc4_eb.common.hw, [CLK_AP_INTC5_EB] = &ap_intc5_eb.common.hw, [CLK_AUDCP_INTC_EB] = &audcp_intc_eb.common.hw, [CLK_AP_TMR0_EB] = &ap_tmr0_eb.common.hw, [CLK_AP_TMR1_EB] = &ap_tmr1_eb.common.hw, [CLK_AP_TMR2_EB] = &ap_tmr2_eb.common.hw, [CLK_PWM0_EB] = &pwm0_eb.common.hw, [CLK_PWM1_EB] = &pwm1_eb.common.hw, [CLK_PWM2_EB] = &pwm2_eb.common.hw, [CLK_PWM3_EB] = &pwm3_eb.common.hw, [CLK_AP_WDG_EB] = &ap_wdg_eb.common.hw, [CLK_APCPU_WDG_EB] = &apcpu_wdg_eb.common.hw, [CLK_SERDES_EB] = &serdes_eb.common.hw, [CLK_ARCH_RTC_EB] = &arch_rtc_eb.common.hw, [CLK_KPD_RTC_EB] = &kpd_rtc_eb.common.hw, [CLK_AON_SYST_RTC_EB] = &aon_syst_rtc_eb.common.hw, [CLK_AP_SYST_RTC_EB] = &ap_syst_rtc_eb.common.hw, [CLK_AON_TMR_RTC_EB] = &aon_tmr_rtc_eb.common.hw, [CLK_EIC_RTC_EB] = &eic_rtc_eb.common.hw, [CLK_EIC_RTCDV5_EB] = &eic_rtcdv5_eb.common.hw, [CLK_AP_WDG_RTC_EB] = &ap_wdg_rtc_eb.common.hw, [CLK_AC_WDG_RTC_EB] = &ac_wdg_rtc_eb.common.hw, [CLK_AP_TMR0_RTC_EB] = &ap_tmr0_rtc_eb.common.hw, [CLK_AP_TMR1_RTC_EB] = &ap_tmr1_rtc_eb.common.hw, [CLK_AP_TMR2_RTC_EB] = &ap_tmr2_rtc_eb.common.hw, [CLK_DCXO_LC_RTC_EB] = &dcxo_lc_rtc_eb.common.hw, [CLK_BB_CAL_RTC_EB] = &bb_cal_rtc_eb.common.hw, [CLK_AP_EMMC_RTC_EB] = &ap_emmc_rtc_eb.common.hw, [CLK_AP_SDIO0_RTC_EB] = &ap_sdio0_rtc_eb.common.hw, [CLK_AP_SDIO1_RTC_EB] = &ap_sdio1_rtc_eb.common.hw, [CLK_AP_SDIO2_RTC_EB] = &ap_sdio2_rtc_eb.common.hw, [CLK_DSI_CSI_TEST_EB] = &dsi_csi_test_eb.common.hw, [CLK_DJTAG_TCK_EN] = &djtag_tck_en.common.hw, [CLK_DPHY_REF_EB] = &dphy_ref_eb.common.hw, [CLK_DMC_REF_EB] = &dmc_ref_eb.common.hw, [CLK_OTG_REF_EB] = &otg_ref_eb.common.hw, [CLK_TSEN_EB] = &tsen_eb.common.hw, [CLK_TMR_EB] = &tmr_eb.common.hw, [CLK_RC100M_REF_EB] = &rc100m_ref_eb.common.hw, [CLK_RC100M_FDK_EB] = &rc100m_fdk_eb.common.hw, [CLK_DEBOUNCE_EB] = &debounce_eb.common.hw, [CLK_DET_32K_EB] = &det_32k_eb.common.hw, [CLK_TOP_CSSYS_EB] = &top_cssys_en.common.hw, [CLK_AP_AXI_EN] = &ap_axi_en.common.hw, [CLK_SDIO0_2X_EN] = &sdio0_2x_en.common.hw, [CLK_SDIO0_1X_EN] = &sdio0_1x_en.common.hw, [CLK_SDIO1_2X_EN] = &sdio1_2x_en.common.hw, [CLK_SDIO1_1X_EN] = &sdio1_1x_en.common.hw, [CLK_SDIO2_2X_EN] = &sdio2_2x_en.common.hw, [CLK_SDIO2_1X_EN] = &sdio2_1x_en.common.hw, [CLK_EMMC_2X_EN] = &emmc_2x_en.common.hw, [CLK_EMMC_1X_EN] = &emmc_1x_en.common.hw, [CLK_PLL_TEST_EN] = &pll_test_en.common.hw, [CLK_CPHY_CFG_EN] = &cphy_cfg_en.common.hw, [CLK_DEBUG_TS_EN] = &debug_ts_en.common.hw, [CLK_ACCESS_AUD_EN] = &access_aud_en.common.hw, }, .num = CLK_AON_APB_GATE_NUM, }; static struct sprd_clk_desc ums512_aon_gate_desc = { .clk_clks = ums512_aon_gate, .num_clk_clks = ARRAY_SIZE(ums512_aon_gate), .hw_clks = &ums512_aon_gate_hws, }; /* audcp apb gates */ /* Audcp apb clocks configure CLK_IGNORE_UNUSED because these clocks may be * controlled by audcp sys at the same time. It may be cause an execption if * kernel gates these clock. */ static SPRD_SC_GATE_CLK_HW(audcp_wdg_eb, "audcp-wdg-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(1), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_rtc_wdg_eb, "audcp-rtc-wdg-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(2), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_tmr0_eb, "audcp-tmr0-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(5), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_tmr1_eb, "audcp-tmr1-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(6), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static struct sprd_clk_common *ums512_audcpapb_gate[] = { /* address base is 0x3350d000 */ &audcp_wdg_eb.common, &audcp_rtc_wdg_eb.common, &audcp_tmr0_eb.common, &audcp_tmr1_eb.common, }; static struct clk_hw_onecell_data ums512_audcpapb_gate_hws = { .hws = { [CLK_AUDCP_WDG_EB] = &audcp_wdg_eb.common.hw, [CLK_AUDCP_RTC_WDG_EB] = &audcp_rtc_wdg_eb.common.hw, [CLK_AUDCP_TMR0_EB] = &audcp_tmr0_eb.common.hw, [CLK_AUDCP_TMR1_EB] = &audcp_tmr1_eb.common.hw, }, .num = CLK_AUDCP_APB_GATE_NUM, }; static const struct sprd_clk_desc ums512_audcpapb_gate_desc = { .clk_clks = ums512_audcpapb_gate, .num_clk_clks = ARRAY_SIZE(ums512_audcpapb_gate), .hw_clks = &ums512_audcpapb_gate_hws, }; /* audcp ahb gates */ /* Audcp aphb clocks configure CLK_IGNORE_UNUSED because these clocks may be * controlled by audcp sys at the same time. It may be cause an execption if * kernel gates these clock. */ static SPRD_SC_GATE_CLK_HW(audcp_iis0_eb, "audcp-iis0-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(0), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_iis1_eb, "audcp-iis1-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(1), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_iis2_eb, "audcp-iis2-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(2), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_uart_eb, "audcp-uart-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(4), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_dma_cp_eb, "audcp-dma-cp-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(5), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_dma_ap_eb, "audcp-dma-ap-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(6), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_src48k_eb, "audcp-src48k-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(10), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_mcdt_eb, "audcp-mcdt-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(12), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_vbcifd_eb, "audcp-vbcifd-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(13), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_vbc_eb, "audcp-vbc-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(14), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_splk_eb, "audcp-splk-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(15), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_icu_eb, "audcp-icu-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(16), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(dma_ap_ashb_eb, "dma-ap-ashb-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(17), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(dma_cp_ashb_eb, "dma-cp-ashb-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(18), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_aud_eb, "audcp-aud-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(19), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_vbc_24m_eb, "audcp-vbc-24m-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(21), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_tmr_26m_eb, "audcp-tmr-26m-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(22), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static SPRD_SC_GATE_CLK_HW(audcp_dvfs_ashb_eb, "audcp-dvfs-ashb-eb", &access_aud_en.common.hw, 0x0, 0x100, BIT(23), CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); static struct sprd_clk_common *ums512_audcpahb_gate[] = { /* address base is 0x335e0000 */ &audcp_iis0_eb.common, &audcp_iis1_eb.common, &audcp_iis2_eb.common, &audcp_uart_eb.common, &audcp_dma_cp_eb.common, &audcp_dma_ap_eb.common, &audcp_src48k_eb.common, &audcp_mcdt_eb.common, &audcp_vbcifd_eb.common, &audcp_vbc_eb.common, &audcp_splk_eb.common, &audcp_icu_eb.common, &dma_ap_ashb_eb.common, &dma_cp_ashb_eb.common, &audcp_aud_eb.common, &audcp_vbc_24m_eb.common, &audcp_tmr_26m_eb.common, &audcp_dvfs_ashb_eb.common, }; static struct clk_hw_onecell_data ums512_audcpahb_gate_hws = { .hws = { [CLK_AUDCP_IIS0_EB] = &audcp_iis0_eb.common.hw, [CLK_AUDCP_IIS1_EB] = &audcp_iis1_eb.common.hw, [CLK_AUDCP_IIS2_EB] = &audcp_iis2_eb.common.hw, [CLK_AUDCP_UART_EB] = &audcp_uart_eb.common.hw, [CLK_AUDCP_DMA_CP_EB] = &audcp_dma_cp_eb.common.hw, [CLK_AUDCP_DMA_AP_EB] = &audcp_dma_ap_eb.common.hw, [CLK_AUDCP_SRC48K_EB] = &audcp_src48k_eb.common.hw, [CLK_AUDCP_MCDT_EB] = &audcp_mcdt_eb.common.hw, [CLK_AUDCP_VBCIFD_EB] = &audcp_vbcifd_eb.common.hw, [CLK_AUDCP_VBC_EB] = &audcp_vbc_eb.common.hw, [CLK_AUDCP_SPLK_EB] = &audcp_splk_eb.common.hw, [CLK_AUDCP_ICU_EB] = &audcp_icu_eb.common.hw, [CLK_AUDCP_DMA_AP_ASHB_EB] = &dma_ap_ashb_eb.common.hw, [CLK_AUDCP_DMA_CP_ASHB_EB] = &dma_cp_ashb_eb.common.hw, [CLK_AUDCP_AUD_EB] = &audcp_aud_eb.common.hw, [CLK_AUDCP_VBC_24M_EB] = &audcp_vbc_24m_eb.common.hw, [CLK_AUDCP_TMR_26M_EB] = &audcp_tmr_26m_eb.common.hw, [CLK_AUDCP_DVFS_ASHB_EB] = &audcp_dvfs_ashb_eb.common.hw, }, .num = CLK_AUDCP_AHB_GATE_NUM, }; static const struct sprd_clk_desc ums512_audcpahb_gate_desc = { .clk_clks = ums512_audcpahb_gate, .num_clk_clks = ARRAY_SIZE(ums512_audcpahb_gate), .hw_clks = &ums512_audcpahb_gate_hws, }; /* gpu clocks */ static SPRD_GATE_CLK_HW(gpu_core_gate, "gpu-core-gate", &gpu_eb.common.hw, 0x4, BIT(0), 0, 0); static const struct clk_parent_data gpu_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_384m.hw }, { .hw = &twpll_512m.hw }, { .hw = &lpll_614m4.hw }, { .hw = &twpll_768m.hw }, { .hw = &gpll.common.hw }, }; static SPRD_COMP_CLK_DATA(gpu_core_clk, "gpu-core-clk", gpu_parents, 0x4, 4, 3, 8, 3, 0); static SPRD_GATE_CLK_HW(gpu_mem_gate, "gpu-mem-gate", &gpu_eb.common.hw, 0x8, BIT(0), 0, 0); static SPRD_COMP_CLK_DATA(gpu_mem_clk, "gpu-mem-clk", gpu_parents, 0x8, 4, 3, 8, 3, 0); static SPRD_GATE_CLK_HW(gpu_sys_gate, "gpu-sys-gate", &gpu_eb.common.hw, 0xc, BIT(0), 0, 0); static SPRD_DIV_CLK_HW(gpu_sys_clk, "gpu-sys-clk", &gpu_eb.common.hw, 0xc, 4, 3, 0); static struct sprd_clk_common *ums512_gpu_clk[] = { /* address base is 0x60100000 */ &gpu_core_gate.common, &gpu_core_clk.common, &gpu_mem_gate.common, &gpu_mem_clk.common, &gpu_sys_gate.common, &gpu_sys_clk.common, }; static struct clk_hw_onecell_data ums512_gpu_clk_hws = { .hws = { [CLK_GPU_CORE_EB] = &gpu_core_gate.common.hw, [CLK_GPU_CORE] = &gpu_core_clk.common.hw, [CLK_GPU_MEM_EB] = &gpu_mem_gate.common.hw, [CLK_GPU_MEM] = &gpu_mem_clk.common.hw, [CLK_GPU_SYS_EB] = &gpu_sys_gate.common.hw, [CLK_GPU_SYS] = &gpu_sys_clk.common.hw, }, .num = CLK_GPU_CLK_NUM, }; static struct sprd_clk_desc ums512_gpu_clk_desc = { .clk_clks = ums512_gpu_clk, .num_clk_clks = ARRAY_SIZE(ums512_gpu_clk), .hw_clks = &ums512_gpu_clk_hws, }; /* mm clocks */ static const struct clk_parent_data mm_ahb_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_96m.hw }, { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, }; static SPRD_MUX_CLK_DATA(mm_ahb_clk, "mm-ahb-clk", mm_ahb_parents, 0x20, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data mm_mtx_parents[] = { { .hw = &twpll_76m8.hw }, { .hw = &twpll_128m.hw }, { .hw = &twpll_256m.hw }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, { .hw = &isppll_468m.hw }, { .hw = &twpll_512m.hw }, }; static SPRD_MUX_CLK_DATA(mm_mtx_clk, "mm-mtx-clk", mm_mtx_parents, 0x24, 0, 3, UMS512_MUX_FLAG); static const struct clk_parent_data sensor_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_48m.hw }, { .hw = &twpll_76m8.hw }, { .hw = &twpll_96m.hw }, }; static SPRD_COMP_CLK_DATA(sensor0_clk, "sensor0-clk", sensor_parents, 0x28, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(sensor1_clk, "sensor1-clk", sensor_parents, 0x2c, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(sensor2_clk, "sensor2-clk", sensor_parents, 0x30, 0, 2, 8, 3, 0); static const struct clk_parent_data cpp_parents[] = { { .hw = &twpll_76m8.hw }, { .hw = &twpll_128m.hw }, { .hw = &twpll_256m.hw }, { .hw = &twpll_384m.hw }, }; static SPRD_MUX_CLK_DATA(cpp_clk, "cpp-clk", cpp_parents, 0x34, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data jpg_parents[] = { { .hw = &twpll_76m8.hw }, { .hw = &twpll_128m.hw }, { .hw = &twpll_256m.hw }, { .hw = &twpll_384m.hw }, }; static SPRD_MUX_CLK_DATA(jpg_clk, "jpg-clk", jpg_parents, 0x38, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data fd_parents[] = { { .hw = &twpll_76m8.hw }, { .hw = &twpll_192m.hw }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, }; static SPRD_MUX_CLK_DATA(fd_clk, "fd-clk", fd_parents, 0x3c, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data dcam_if_parents[] = { { .hw = &twpll_192m.hw }, { .hw = &twpll_256m.hw }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, { .hw = &isppll_468m.hw }, }; static SPRD_MUX_CLK_DATA(dcam_if_clk, "dcam-if-clk", dcam_if_parents, 0x40, 0, 3, UMS512_MUX_FLAG); static const struct clk_parent_data dcam_axi_parents[] = { { .hw = &twpll_256m.hw }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, { .hw = &isppll_468m.hw }, }; static SPRD_MUX_CLK_DATA(dcam_axi_clk, "dcam-axi-clk", dcam_axi_parents, 0x44, 0, 2, UMS512_MUX_FLAG); static const struct clk_parent_data isp_parents[] = { { .hw = &twpll_256m.hw }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, { .hw = &isppll_468m.hw }, { .hw = &twpll_512m.hw }, }; static SPRD_MUX_CLK_DATA(isp_clk, "isp-clk", isp_parents, 0x48, 0, 3, UMS512_MUX_FLAG); static SPRD_GATE_CLK_HW(mipi_csi0, "mipi-csi0", &mm_eb.common.hw, 0x4c, BIT(16), CLK_IGNORE_UNUSED, 0); static SPRD_GATE_CLK_HW(mipi_csi1, "mipi-csi1", &mm_eb.common.hw, 0x50, BIT(16), CLK_IGNORE_UNUSED, 0); static SPRD_GATE_CLK_HW(mipi_csi2, "mipi-csi2", &mm_eb.common.hw, 0x54, BIT(16), CLK_IGNORE_UNUSED, 0); static struct sprd_clk_common *ums512_mm_clk[] = { /* address base is 0x62100000 */ &mm_ahb_clk.common, &mm_mtx_clk.common, &sensor0_clk.common, &sensor1_clk.common, &sensor2_clk.common, &cpp_clk.common, &jpg_clk.common, &fd_clk.common, &dcam_if_clk.common, &dcam_axi_clk.common, &isp_clk.common, &mipi_csi0.common, &mipi_csi1.common, &mipi_csi2.common, }; static struct clk_hw_onecell_data ums512_mm_clk_hws = { .hws = { [CLK_MM_AHB] = &mm_ahb_clk.common.hw, [CLK_MM_MTX] = &mm_mtx_clk.common.hw, [CLK_SENSOR0] = &sensor0_clk.common.hw, [CLK_SENSOR1] = &sensor1_clk.common.hw, [CLK_SENSOR2] = &sensor2_clk.common.hw, [CLK_CPP] = &cpp_clk.common.hw, [CLK_JPG] = &jpg_clk.common.hw, [CLK_FD] = &fd_clk.common.hw, [CLK_DCAM_IF] = &dcam_if_clk.common.hw, [CLK_DCAM_AXI] = &dcam_axi_clk.common.hw, [CLK_ISP] = &isp_clk.common.hw, [CLK_MIPI_CSI0] = &mipi_csi0.common.hw, [CLK_MIPI_CSI1] = &mipi_csi1.common.hw, [CLK_MIPI_CSI2] = &mipi_csi2.common.hw, }, .num = CLK_MM_CLK_NUM, }; static struct sprd_clk_desc ums512_mm_clk_desc = { .clk_clks = ums512_mm_clk, .num_clk_clks = ARRAY_SIZE(ums512_mm_clk), .hw_clks = &ums512_mm_clk_hws, }; /* mm gate clocks */ static SPRD_SC_GATE_CLK_HW(mm_cpp_eb, "mm-cpp-eb", &mm_eb.common.hw, 0x0, 0x1000, BIT(0), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_jpg_eb, "mm-jpg-eb", &mm_eb.common.hw, 0x0, 0x1000, BIT(1), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_dcam_eb, "mm-dcam-eb", &mm_eb.common.hw, 0x0, 0x1000, BIT(2), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_isp_eb, "mm-isp-eb", &mm_eb.common.hw, 0x0, 0x1000, BIT(3), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_csi2_eb, "mm-csi2-eb", &mm_eb.common.hw, 0x0, 0x1000, BIT(4), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_csi1_eb, "mm-csi1-eb", &mm_eb.common.hw, 0x0, 0x1000, BIT(5), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_csi0_eb, "mm-csi0-eb", &mm_eb.common.hw, 0x0, 0x1000, BIT(6), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_ckg_eb, "mm-ckg-eb", &mm_eb.common.hw, 0x0, 0x1000, BIT(7), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_isp_ahb_eb, "mm-isp-ahb-eb", &mm_eb.common.hw, 0x0, 0x1000, BIT(8), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_dvfs_eb, "mm-dvfs-eb", &mm_eb.common.hw, 0x0, 0x1000, BIT(9), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_fd_eb, "mm-fd-eb", &mm_eb.common.hw, 0x0, 0x1000, BIT(10), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_sensor2_en, "mm-sensor2-en", &mm_eb.common.hw, 0x8, 0x1000, BIT(0), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_sensor1_en, "mm-sensor1-en", &mm_eb.common.hw, 0x8, 0x1000, BIT(1), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_sensor0_en, "mm-sensor0-en", &mm_eb.common.hw, 0x8, 0x1000, BIT(2), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_mipi_csi2_en, "mm-mipi-csi2-en", &mm_eb.common.hw, 0x8, 0x1000, BIT(3), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_mipi_csi1_en, "mm-mipi-csi1-en", &mm_eb.common.hw, 0x8, 0x1000, BIT(4), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_mipi_csi0_en, "mm-mipi-csi0-en", &mm_eb.common.hw, 0x8, 0x1000, BIT(5), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_dcam_axi_en, "mm-dcam-axi-en", &mm_eb.common.hw, 0x8, 0x1000, BIT(6), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_isp_axi_en, "mm-isp-axi-en", &mm_eb.common.hw, 0x8, 0x1000, BIT(7), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_cphy_en, "mm-cphy-en", &mm_eb.common.hw, 0x8, 0x1000, BIT(8), 0, 0); static struct sprd_clk_common *ums512_mm_gate_clk[] = { /* address base is 0x62200000 */ &mm_cpp_eb.common, &mm_jpg_eb.common, &mm_dcam_eb.common, &mm_isp_eb.common, &mm_csi2_eb.common, &mm_csi1_eb.common, &mm_csi0_eb.common, &mm_ckg_eb.common, &mm_isp_ahb_eb.common, &mm_dvfs_eb.common, &mm_fd_eb.common, &mm_sensor2_en.common, &mm_sensor1_en.common, &mm_sensor0_en.common, &mm_mipi_csi2_en.common, &mm_mipi_csi1_en.common, &mm_mipi_csi0_en.common, &mm_dcam_axi_en.common, &mm_isp_axi_en.common, &mm_cphy_en.common, }; static struct clk_hw_onecell_data ums512_mm_gate_clk_hws = { .hws = { [CLK_MM_CPP_EB] = &mm_cpp_eb.common.hw, [CLK_MM_JPG_EB] = &mm_jpg_eb.common.hw, [CLK_MM_DCAM_EB] = &mm_dcam_eb.common.hw, [CLK_MM_ISP_EB] = &mm_isp_eb.common.hw, [CLK_MM_CSI2_EB] = &mm_csi2_eb.common.hw, [CLK_MM_CSI1_EB] = &mm_csi1_eb.common.hw, [CLK_MM_CSI0_EB] = &mm_csi0_eb.common.hw, [CLK_MM_CKG_EB] = &mm_ckg_eb.common.hw, [CLK_ISP_AHB_EB] = &mm_isp_ahb_eb.common.hw, [CLK_MM_DVFS_EB] = &mm_dvfs_eb.common.hw, [CLK_MM_FD_EB] = &mm_fd_eb.common.hw, [CLK_MM_SENSOR2_EB] = &mm_sensor2_en.common.hw, [CLK_MM_SENSOR1_EB] = &mm_sensor1_en.common.hw, [CLK_MM_SENSOR0_EB] = &mm_sensor0_en.common.hw, [CLK_MM_MIPI_CSI2_EB] = &mm_mipi_csi2_en.common.hw, [CLK_MM_MIPI_CSI1_EB] = &mm_mipi_csi1_en.common.hw, [CLK_MM_MIPI_CSI0_EB] = &mm_mipi_csi0_en.common.hw, [CLK_DCAM_AXI_EB] = &mm_dcam_axi_en.common.hw, [CLK_ISP_AXI_EB] = &mm_isp_axi_en.common.hw, [CLK_MM_CPHY_EB] = &mm_cphy_en.common.hw, }, .num = CLK_MM_GATE_CLK_NUM, }; static struct sprd_clk_desc ums512_mm_gate_clk_desc = { .clk_clks = ums512_mm_gate_clk, .num_clk_clks = ARRAY_SIZE(ums512_mm_gate_clk), .hw_clks = &ums512_mm_gate_clk_hws, }; /* ap apb gates */ static SPRD_SC_GATE_CLK_FW_NAME(sim0_eb, "sim0-eb", "ext-26m", 0x0, 0x1000, BIT(0), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(iis0_eb, "iis0-eb", "ext-26m", 0x0, 0x1000, BIT(1), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(iis1_eb, "iis1-eb", "ext-26m", 0x0, 0x1000, BIT(2), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(iis2_eb, "iis2-eb", "ext-26m", 0x0, 0x1000, BIT(3), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(apb_reg_eb, "apb-reg-eb", "ext-26m", 0x0, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(spi0_eb, "spi0-eb", "ext-26m", 0x0, 0x1000, BIT(5), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(spi1_eb, "spi1-eb", "ext-26m", 0x0, 0x1000, BIT(6), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(spi2_eb, "spi2-eb", "ext-26m", 0x0, 0x1000, BIT(7), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(spi3_eb, "spi3-eb", "ext-26m", 0x0, 0x1000, BIT(8), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(i2c0_eb, "i2c0-eb", "ext-26m", 0x0, 0x1000, BIT(9), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(i2c1_eb, "i2c1-eb", "ext-26m", 0x0, 0x1000, BIT(10), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(i2c2_eb, "i2c2-eb", "ext-26m", 0x0, 0x1000, BIT(11), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(i2c3_eb, "i2c3-eb", "ext-26m", 0x0, 0x1000, BIT(12), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(i2c4_eb, "i2c4-eb", "ext-26m", 0x0, 0x1000, BIT(13), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(uart0_eb, "uart0-eb", "ext-26m", 0x0, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(uart1_eb, "uart1-eb", "ext-26m", 0x0, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(uart2_eb, "uart2-eb", "ext-26m", 0x0, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(sim0_32k_eb, "sim0-32k-eb", "ext-26m", 0x0, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(spi0_lfin_eb, "spi0-lfin-eb", "ext-26m", 0x0, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(spi1_lfin_eb, "spi1-lfin-eb", "ext-26m", 0x0, 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(spi2_lfin_eb, "spi2-lfin-eb", "ext-26m", 0x0, 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(spi3_lfin_eb, "spi3-lfin-eb", "ext-26m", 0x0, 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(sdio0_eb, "sdio0-eb", "ext-26m", 0x0, 0x1000, BIT(22), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(sdio1_eb, "sdio1-eb", "ext-26m", 0x0, 0x1000, BIT(23), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(sdio2_eb, "sdio2-eb", "ext-26m", 0x0, 0x1000, BIT(24), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(emmc_eb, "emmc-eb", "ext-26m", 0x0, 0x1000, BIT(25), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(sdio0_32k_eb, "sdio0-32k-eb", "ext-26m", 0x0, 0x1000, BIT(26), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(sdio1_32k_eb, "sdio1-32k-eb", "ext-26m", 0x0, 0x1000, BIT(27), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(sdio2_32k_eb, "sdio2-32k-eb", "ext-26m", 0x0, 0x1000, BIT(28), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(emmc_32k_eb, "emmc-32k-eb", "ext-26m", 0x0, 0x1000, BIT(29), 0, 0); static struct sprd_clk_common *ums512_apapb_gate[] = { /* address base is 0x71000000 */ &sim0_eb.common, &iis0_eb.common, &iis1_eb.common, &iis2_eb.common, &apb_reg_eb.common, &spi0_eb.common, &spi1_eb.common, &spi2_eb.common, &spi3_eb.common, &i2c0_eb.common, &i2c1_eb.common, &i2c2_eb.common, &i2c3_eb.common, &i2c4_eb.common, &uart0_eb.common, &uart1_eb.common, &uart2_eb.common, &sim0_32k_eb.common, &spi0_lfin_eb.common, &spi1_lfin_eb.common, &spi2_lfin_eb.common, &spi3_lfin_eb.common, &sdio0_eb.common, &sdio1_eb.common, &sdio2_eb.common, &emmc_eb.common, &sdio0_32k_eb.common, &sdio1_32k_eb.common, &sdio2_32k_eb.common, &emmc_32k_eb.common, }; static struct clk_hw_onecell_data ums512_apapb_gate_hws = { .hws = { [CLK_SIM0_EB] = &sim0_eb.common.hw, [CLK_IIS0_EB] = &iis0_eb.common.hw, [CLK_IIS1_EB] = &iis1_eb.common.hw, [CLK_IIS2_EB] = &iis2_eb.common.hw, [CLK_APB_REG_EB] = &apb_reg_eb.common.hw, [CLK_SPI0_EB] = &spi0_eb.common.hw, [CLK_SPI1_EB] = &spi1_eb.common.hw, [CLK_SPI2_EB] = &spi2_eb.common.hw, [CLK_SPI3_EB] = &spi3_eb.common.hw, [CLK_I2C0_EB] = &i2c0_eb.common.hw, [CLK_I2C1_EB] = &i2c1_eb.common.hw, [CLK_I2C2_EB] = &i2c2_eb.common.hw, [CLK_I2C3_EB] = &i2c3_eb.common.hw, [CLK_I2C4_EB] = &i2c4_eb.common.hw, [CLK_UART0_EB] = &uart0_eb.common.hw, [CLK_UART1_EB] = &uart1_eb.common.hw, [CLK_UART2_EB] = &uart2_eb.common.hw, [CLK_SIM0_32K_EB] = &sim0_32k_eb.common.hw, [CLK_SPI0_LFIN_EB] = &spi0_lfin_eb.common.hw, [CLK_SPI1_LFIN_EB] = &spi1_lfin_eb.common.hw, [CLK_SPI2_LFIN_EB] = &spi2_lfin_eb.common.hw, [CLK_SPI3_LFIN_EB] = &spi3_lfin_eb.common.hw, [CLK_SDIO0_EB] = &sdio0_eb.common.hw, [CLK_SDIO1_EB] = &sdio1_eb.common.hw, [CLK_SDIO2_EB] = &sdio2_eb.common.hw, [CLK_EMMC_EB] = &emmc_eb.common.hw, [CLK_SDIO0_32K_EB] = &sdio0_32k_eb.common.hw, [CLK_SDIO1_32K_EB] = &sdio1_32k_eb.common.hw, [CLK_SDIO2_32K_EB] = &sdio2_32k_eb.common.hw, [CLK_EMMC_32K_EB] = &emmc_32k_eb.common.hw, }, .num = CLK_AP_APB_GATE_NUM, }; static struct sprd_clk_desc ums512_apapb_gate_desc = { .clk_clks = ums512_apapb_gate, .num_clk_clks = ARRAY_SIZE(ums512_apapb_gate), .hw_clks = &ums512_apapb_gate_hws, }; static const struct of_device_id sprd_ums512_clk_ids[] = { { .compatible = "sprd,ums512-pmu-gate", /* 0x327e0000 */ .data = &ums512_pmu_gate_desc }, { .compatible = "sprd,ums512-g0-pll", /* 0x32390000 */ .data = &ums512_g0_pll_desc }, { .compatible = "sprd,ums512-g2-pll", /* 0x323b0000 */ .data = &ums512_g2_pll_desc }, { .compatible = "sprd,ums512-g3-pll", /* 0x323c0000 */ .data = &ums512_g3_pll_desc }, { .compatible = "sprd,ums512-gc-pll", /* 0x323e0000 */ .data = &ums512_gc_pll_desc }, { .compatible = "sprd,ums512-apahb-gate", /* 0x20100000 */ .data = &ums512_apahb_gate_desc }, { .compatible = "sprd,ums512-ap-clk", /* 0x20200000 */ .data = &ums512_ap_clk_desc }, { .compatible = "sprd,ums512-aonapb-clk", /* 0x32080200 */ .data = &ums512_aon_apb_desc }, { .compatible = "sprd,ums512-aon-gate", /* 0x327d0000 */ .data = &ums512_aon_gate_desc }, { .compatible = "sprd,ums512-audcpapb-gate", /* 0x3350d000 */ .data = &ums512_audcpapb_gate_desc }, { .compatible = "sprd,ums512-audcpahb-gate", /* 0x335e0000 */ .data = &ums512_audcpahb_gate_desc }, { .compatible = "sprd,ums512-gpu-clk", /* 0x60100000 */ .data = &ums512_gpu_clk_desc }, { .compatible = "sprd,ums512-mm-clk", /* 0x62100000 */ .data = &ums512_mm_clk_desc }, { .compatible = "sprd,ums512-mm-gate-clk", /* 0x62200000 */ .data = &ums512_mm_gate_clk_desc }, { .compatible = "sprd,ums512-apapb-gate", /* 0x71000000 */ .data = &ums512_apapb_gate_desc }, { } }; MODULE_DEVICE_TABLE(of, sprd_ums512_clk_ids); static int ums512_clk_probe(struct platform_device *pdev) { const struct sprd_clk_desc *desc; int ret; desc = device_get_match_data(&pdev->dev); if (!desc) return -ENODEV; ret = sprd_clk_regmap_init(pdev, desc); if (ret) return ret; return sprd_clk_probe(&pdev->dev, desc->hw_clks); } static struct platform_driver ums512_clk_driver = { .probe = ums512_clk_probe, .driver = { .name = "ums512-clk", .of_match_table = sprd_ums512_clk_ids, }, }; module_platform_driver(ums512_clk_driver); MODULE_DESCRIPTION("Unisoc UMS512 Clock Driver"); MODULE_LICENSE("GPL");
linux-master
drivers/clk/sprd/ums512-clk.c
// SPDX-License-Identifier: GPL-2.0 // // Spreadtrum divider clock driver // // Copyright (C) 2017 Spreadtrum, Inc. // Author: Chunyan Zhang <[email protected]> #include <linux/clk-provider.h> #include "div.h" static long sprd_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { struct sprd_div *cd = hw_to_sprd_div(hw); return divider_round_rate(&cd->common.hw, rate, parent_rate, NULL, cd->div.width, 0); } unsigned long sprd_div_helper_recalc_rate(struct sprd_clk_common *common, const struct sprd_div_internal *div, unsigned long parent_rate) { unsigned long val; unsigned int reg; regmap_read(common->regmap, common->reg, &reg); val = reg >> div->shift; val &= (1 << div->width) - 1; return divider_recalc_rate(&common->hw, parent_rate, val, NULL, 0, div->width); } EXPORT_SYMBOL_GPL(sprd_div_helper_recalc_rate); static unsigned long sprd_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct sprd_div *cd = hw_to_sprd_div(hw); return sprd_div_helper_recalc_rate(&cd->common, &cd->div, parent_rate); } int sprd_div_helper_set_rate(const struct sprd_clk_common *common, const struct sprd_div_internal *div, unsigned long rate, unsigned long parent_rate) { unsigned long val; unsigned int reg; val = divider_get_val(rate, parent_rate, NULL, div->width, 0); regmap_read(common->regmap, common->reg, &reg); reg &= ~GENMASK(div->width + div->shift - 1, div->shift); regmap_write(common->regmap, common->reg, reg | (val << div->shift)); return 0; } EXPORT_SYMBOL_GPL(sprd_div_helper_set_rate); static int sprd_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct sprd_div *cd = hw_to_sprd_div(hw); return sprd_div_helper_set_rate(&cd->common, &cd->div, rate, parent_rate); } const struct clk_ops sprd_div_ops = { .recalc_rate = sprd_div_recalc_rate, .round_rate = sprd_div_round_rate, .set_rate = sprd_div_set_rate, }; EXPORT_SYMBOL_GPL(sprd_div_ops);
linux-master
drivers/clk/sprd/div.c
// SPDX-License-Identifier: GPL-2.0 // // Spreatrum SC9860 clock driver // // Copyright (C) 2017 Spreadtrum, Inc. // Author: Chunyan Zhang <[email protected]> #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <dt-bindings/clock/sprd,sc9860-clk.h> #include "common.h" #include "composite.h" #include "div.h" #include "gate.h" #include "mux.h" #include "pll.h" static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m", 6, 1, 0); static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m", 13, 1, 0); static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m", 26, 1, 0); static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m", 104, 1, 0); static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m", 1, 1, 0); static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m", 1, 1, 0); static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m", 4, 1, 0); static CLK_FIXED_FACTOR(fac_rco_4m, "rco-4m", "ext-rc0-100m", 25, 1, 0); static CLK_FIXED_FACTOR(fac_rco_2m, "rco-2m", "ext-rc0-100m", 50, 1, 0); static CLK_FIXED_FACTOR(fac_3k2, "fac-3k2", "ext-32k", 10, 1, 0); static CLK_FIXED_FACTOR(fac_1k, "fac-1k", "ext-32k", 32, 1, 0); static SPRD_SC_GATE_CLK(mpll0_gate, "mpll0-gate", "ext-26m", 0xb0, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(mpll1_gate, "mpll1-gate", "ext-26m", 0xb0, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(dpll0_gate, "dpll0-gate", "ext-26m", 0xb4, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(dpll1_gate, "dpll1-gate", "ext-26m", 0xb4, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ltepll0_gate, "ltepll0-gate", "ext-26m", 0xb8, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(twpll_gate, "twpll-gate", "ext-26m", 0xbc, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ltepll1_gate, "ltepll1-gate", "ext-26m", 0x10c, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(rpll0_gate, "rpll0-gate", "ext-26m", 0x16c, 0x1000, BIT(2), 0, 0); static SPRD_SC_GATE_CLK(rpll1_gate, "rpll1-gate", "ext-26m", 0x16c, 0x1000, BIT(18), 0, 0); static SPRD_SC_GATE_CLK(cppll_gate, "cppll-gate", "ext-26m", 0x2b4, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(gpll_gate, "gpll-gate", "ext-26m", 0x32c, 0x1000, BIT(0), CLK_IGNORE_UNUSED, CLK_GATE_SET_TO_DISABLE); static struct sprd_clk_common *sc9860_pmu_gate_clks[] = { /* address base is 0x402b0000 */ &mpll0_gate.common, &mpll1_gate.common, &dpll0_gate.common, &dpll1_gate.common, &ltepll0_gate.common, &twpll_gate.common, &ltepll1_gate.common, &rpll0_gate.common, &rpll1_gate.common, &cppll_gate.common, &gpll_gate.common, }; static struct clk_hw_onecell_data sc9860_pmu_gate_hws = { .hws = { [CLK_FAC_4M] = &fac_4m.hw, [CLK_FAC_2M] = &fac_2m.hw, [CLK_FAC_1M] = &fac_1m.hw, [CLK_FAC_250K] = &fac_250k.hw, [CLK_FAC_RPLL0_26M] = &fac_rpll0_26m.hw, [CLK_FAC_RPLL1_26M] = &fac_rpll1_26m.hw, [CLK_FAC_RCO25M] = &fac_rco_25m.hw, [CLK_FAC_RCO4M] = &fac_rco_4m.hw, [CLK_FAC_RCO2M] = &fac_rco_2m.hw, [CLK_FAC_3K2] = &fac_3k2.hw, [CLK_FAC_1K] = &fac_1k.hw, [CLK_MPLL0_GATE] = &mpll0_gate.common.hw, [CLK_MPLL1_GATE] = &mpll1_gate.common.hw, [CLK_DPLL0_GATE] = &dpll0_gate.common.hw, [CLK_DPLL1_GATE] = &dpll1_gate.common.hw, [CLK_LTEPLL0_GATE] = &ltepll0_gate.common.hw, [CLK_TWPLL_GATE] = &twpll_gate.common.hw, [CLK_LTEPLL1_GATE] = &ltepll1_gate.common.hw, [CLK_RPLL0_GATE] = &rpll0_gate.common.hw, [CLK_RPLL1_GATE] = &rpll1_gate.common.hw, [CLK_CPPLL_GATE] = &cppll_gate.common.hw, [CLK_GPLL_GATE] = &gpll_gate.common.hw, }, .num = CLK_PMU_GATE_NUM, }; static const struct sprd_clk_desc sc9860_pmu_gate_desc = { .clk_clks = sc9860_pmu_gate_clks, .num_clk_clks = ARRAY_SIZE(sc9860_pmu_gate_clks), .hw_clks = &sc9860_pmu_gate_hws, }; /* GPLL/LPLL/DPLL/RPLL/CPLL */ static const u64 itable1[4] = {3, 780000000, 988000000, 1196000000}; /* TWPLL/MPLL0/MPLL1 */ static const u64 itable2[4] = {3, 1638000000, 2080000000, 2600000000UL}; static const struct clk_bit_field f_mpll0[PLL_FACT_MAX] = { { .shift = 20, .width = 1 }, /* lock_done */ { .shift = 19, .width = 1 }, /* div_s */ { .shift = 18, .width = 1 }, /* mod_en */ { .shift = 17, .width = 1 }, /* sdm_en */ { .shift = 0, .width = 0 }, /* refin */ { .shift = 11, .width = 2 }, /* ibias */ { .shift = 0, .width = 7 }, /* n */ { .shift = 57, .width = 7 }, /* nint */ { .shift = 32, .width = 23}, /* kint */ { .shift = 0, .width = 0 }, /* prediv */ { .shift = 56, .width = 1 }, /* postdiv */ }; static SPRD_PLL_WITH_ITABLE_K_FVCO(mpll0_clk, "mpll0", "mpll0-gate", 0x24, 2, itable2, f_mpll0, 200, 1000, 1000, 1, 1300000000); static const struct clk_bit_field f_mpll1[PLL_FACT_MAX] = { { .shift = 20, .width = 1 }, /* lock_done */ { .shift = 19, .width = 1 }, /* div_s */ { .shift = 18, .width = 1 }, /* mod_en */ { .shift = 17, .width = 1 }, /* sdm_en */ { .shift = 0, .width = 0 }, /* refin */ { .shift = 11, .width = 2 }, /* ibias */ { .shift = 0, .width = 7 }, /* n */ { .shift = 57, .width = 7 }, /* nint */ { .shift = 32, .width = 23}, /* kint */ { .shift = 56, .width = 1 }, /* prediv */ { .shift = 0, .width = 0 }, /* postdiv */ }; static SPRD_PLL_WITH_ITABLE_1K(mpll1_clk, "mpll1", "mpll1-gate", 0x2c, 2, itable2, f_mpll1, 200); static const struct clk_bit_field f_dpll[PLL_FACT_MAX] = { { .shift = 16, .width = 1 }, /* lock_done */ { .shift = 15, .width = 1 }, /* div_s */ { .shift = 14, .width = 1 }, /* mod_en */ { .shift = 13, .width = 1 }, /* sdm_en */ { .shift = 0, .width = 0 }, /* refin */ { .shift = 8, .width = 2 }, /* ibias */ { .shift = 0, .width = 7 }, /* n */ { .shift = 57, .width = 7 }, /* nint */ { .shift = 32, .width = 23}, /* kint */ { .shift = 0, .width = 0 }, /* prediv */ { .shift = 0, .width = 0 }, /* postdiv */ }; static SPRD_PLL_WITH_ITABLE_1K(dpll0_clk, "dpll0", "dpll0-gate", 0x34, 2, itable1, f_dpll, 200); static SPRD_PLL_WITH_ITABLE_1K(dpll1_clk, "dpll1", "dpll1-gate", 0x3c, 2, itable1, f_dpll, 200); static const struct clk_bit_field f_rpll[PLL_FACT_MAX] = { { .shift = 0, .width = 1 }, /* lock_done */ { .shift = 3, .width = 1 }, /* div_s */ { .shift = 80, .width = 1 }, /* mod_en */ { .shift = 81, .width = 1 }, /* sdm_en */ { .shift = 0, .width = 0 }, /* refin */ { .shift = 14, .width = 2 }, /* ibias */ { .shift = 16, .width = 7 }, /* n */ { .shift = 4, .width = 7 }, /* nint */ { .shift = 32, .width = 23}, /* kint */ { .shift = 0, .width = 0 }, /* prediv */ { .shift = 0, .width = 0 }, /* postdiv */ }; static SPRD_PLL_WITH_ITABLE_1K(rpll0_clk, "rpll0", "rpll0-gate", 0x44, 3, itable1, f_rpll, 200); static SPRD_PLL_WITH_ITABLE_1K(rpll1_clk, "rpll1", "rpll1-gate", 0x50, 3, itable1, f_rpll, 200); static const struct clk_bit_field f_twpll[PLL_FACT_MAX] = { { .shift = 21, .width = 1 }, /* lock_done */ { .shift = 20, .width = 1 }, /* div_s */ { .shift = 19, .width = 1 }, /* mod_en */ { .shift = 18, .width = 1 }, /* sdm_en */ { .shift = 0, .width = 0 }, /* refin */ { .shift = 13, .width = 2 }, /* ibias */ { .shift = 0, .width = 7 }, /* n */ { .shift = 57, .width = 7 }, /* nint */ { .shift = 32, .width = 23}, /* kint */ { .shift = 0, .width = 0 }, /* prediv */ { .shift = 0, .width = 0 }, /* postdiv */ }; static SPRD_PLL_WITH_ITABLE_1K(twpll_clk, "twpll", "twpll-gate", 0x5c, 2, itable2, f_twpll, 200); static const struct clk_bit_field f_ltepll[PLL_FACT_MAX] = { { .shift = 31, .width = 1 }, /* lock_done */ { .shift = 27, .width = 1 }, /* div_s */ { .shift = 26, .width = 1 }, /* mod_en */ { .shift = 25, .width = 1 }, /* sdm_en */ { .shift = 0, .width = 0 }, /* refin */ { .shift = 20, .width = 2 }, /* ibias */ { .shift = 0, .width = 7 }, /* n */ { .shift = 57, .width = 7 }, /* nint */ { .shift = 32, .width = 23}, /* kint */ { .shift = 0, .width = 0 }, /* prediv */ { .shift = 0, .width = 0 }, /* postdiv */ }; static SPRD_PLL_WITH_ITABLE_1K(ltepll0_clk, "ltepll0", "ltepll0-gate", 0x64, 2, itable1, f_ltepll, 200); static SPRD_PLL_WITH_ITABLE_1K(ltepll1_clk, "ltepll1", "ltepll1-gate", 0x6c, 2, itable1, f_ltepll, 200); static const struct clk_bit_field f_gpll[PLL_FACT_MAX] = { { .shift = 18, .width = 1 }, /* lock_done */ { .shift = 15, .width = 1 }, /* div_s */ { .shift = 14, .width = 1 }, /* mod_en */ { .shift = 13, .width = 1 }, /* sdm_en */ { .shift = 0, .width = 0 }, /* refin */ { .shift = 8, .width = 2 }, /* ibias */ { .shift = 0, .width = 7 }, /* n */ { .shift = 57, .width = 7 }, /* nint */ { .shift = 32, .width = 23}, /* kint */ { .shift = 0, .width = 0 }, /* prediv */ { .shift = 17, .width = 1 }, /* postdiv */ }; static SPRD_PLL_WITH_ITABLE_K_FVCO(gpll_clk, "gpll", "gpll-gate", 0x9c, 2, itable1, f_gpll, 200, 1000, 1000, 1, 600000000); static const struct clk_bit_field f_cppll[PLL_FACT_MAX] = { { .shift = 17, .width = 1 }, /* lock_done */ { .shift = 15, .width = 1 }, /* div_s */ { .shift = 14, .width = 1 }, /* mod_en */ { .shift = 13, .width = 1 }, /* sdm_en */ { .shift = 0, .width = 0 }, /* refin */ { .shift = 8, .width = 2 }, /* ibias */ { .shift = 0, .width = 7 }, /* n */ { .shift = 57, .width = 7 }, /* nint */ { .shift = 32, .width = 23}, /* kint */ { .shift = 0, .width = 0 }, /* prediv */ { .shift = 0, .width = 0 }, /* postdiv */ }; static SPRD_PLL_WITH_ITABLE_1K(cppll_clk, "cppll", "cppll-gate", 0xc4, 2, itable1, f_cppll, 200); static CLK_FIXED_FACTOR(gpll_42m5, "gpll-42m5", "gpll", 20, 1, 0); static CLK_FIXED_FACTOR(twpll_768m, "twpll-768m", "twpll", 2, 1, 0); static CLK_FIXED_FACTOR(twpll_384m, "twpll-384m", "twpll", 4, 1, 0); static CLK_FIXED_FACTOR(twpll_192m, "twpll-192m", "twpll", 8, 1, 0); static CLK_FIXED_FACTOR(twpll_96m, "twpll-96m", "twpll", 16, 1, 0); static CLK_FIXED_FACTOR(twpll_48m, "twpll-48m", "twpll", 32, 1, 0); static CLK_FIXED_FACTOR(twpll_24m, "twpll-24m", "twpll", 64, 1, 0); static CLK_FIXED_FACTOR(twpll_12m, "twpll-12m", "twpll", 128, 1, 0); static CLK_FIXED_FACTOR(twpll_512m, "twpll-512m", "twpll", 3, 1, 0); static CLK_FIXED_FACTOR(twpll_256m, "twpll-256m", "twpll", 6, 1, 0); static CLK_FIXED_FACTOR(twpll_128m, "twpll-128m", "twpll", 12, 1, 0); static CLK_FIXED_FACTOR(twpll_64m, "twpll-64m", "twpll", 24, 1, 0); static CLK_FIXED_FACTOR(twpll_307m2, "twpll-307m2", "twpll", 5, 1, 0); static CLK_FIXED_FACTOR(twpll_153m6, "twpll-153m6", "twpll", 10, 1, 0); static CLK_FIXED_FACTOR(twpll_76m8, "twpll-76m8", "twpll", 20, 1, 0); static CLK_FIXED_FACTOR(twpll_51m2, "twpll-51m2", "twpll", 30, 1, 0); static CLK_FIXED_FACTOR(twpll_38m4, "twpll-38m4", "twpll", 40, 1, 0); static CLK_FIXED_FACTOR(twpll_19m2, "twpll-19m2", "twpll", 80, 1, 0); static CLK_FIXED_FACTOR(l0_614m4, "l0-614m4", "ltepll0", 2, 1, 0); static CLK_FIXED_FACTOR(l0_409m6, "l0-409m6", "ltepll0", 3, 1, 0); static CLK_FIXED_FACTOR(l0_38m, "l0-38m", "ltepll0", 32, 1, 0); static CLK_FIXED_FACTOR(l1_38m, "l1-38m", "ltepll1", 32, 1, 0); static CLK_FIXED_FACTOR(rpll0_192m, "rpll0-192m", "rpll0", 6, 1, 0); static CLK_FIXED_FACTOR(rpll0_96m, "rpll0-96m", "rpll0", 12, 1, 0); static CLK_FIXED_FACTOR(rpll0_48m, "rpll0-48m", "rpll0", 24, 1, 0); static CLK_FIXED_FACTOR(rpll1_468m, "rpll1-468m", "rpll1", 2, 1, 0); static CLK_FIXED_FACTOR(rpll1_192m, "rpll1-192m", "rpll1", 6, 1, 0); static CLK_FIXED_FACTOR(rpll1_96m, "rpll1-96m", "rpll1", 12, 1, 0); static CLK_FIXED_FACTOR(rpll1_64m, "rpll1-64m", "rpll1", 18, 1, 0); static CLK_FIXED_FACTOR(rpll1_48m, "rpll1-48m", "rpll1", 24, 1, 0); static CLK_FIXED_FACTOR(dpll0_50m, "dpll0-50m", "dpll0", 16, 1, 0); static CLK_FIXED_FACTOR(dpll1_50m, "dpll1-50m", "dpll1", 16, 1, 0); static CLK_FIXED_FACTOR(cppll_50m, "cppll-50m", "cppll", 18, 1, 0); static CLK_FIXED_FACTOR(m0_39m, "m0-39m", "mpll0", 32, 1, 0); static CLK_FIXED_FACTOR(m1_63m, "m1-63m", "mpll1", 32, 1, 0); static struct sprd_clk_common *sc9860_pll_clks[] = { /* address base is 0x40400000 */ &mpll0_clk.common, &mpll1_clk.common, &dpll0_clk.common, &dpll1_clk.common, &rpll0_clk.common, &rpll1_clk.common, &twpll_clk.common, &ltepll0_clk.common, &ltepll1_clk.common, &gpll_clk.common, &cppll_clk.common, }; static struct clk_hw_onecell_data sc9860_pll_hws = { .hws = { [CLK_MPLL0] = &mpll0_clk.common.hw, [CLK_MPLL1] = &mpll1_clk.common.hw, [CLK_DPLL0] = &dpll0_clk.common.hw, [CLK_DPLL1] = &dpll1_clk.common.hw, [CLK_RPLL0] = &rpll0_clk.common.hw, [CLK_RPLL1] = &rpll1_clk.common.hw, [CLK_TWPLL] = &twpll_clk.common.hw, [CLK_LTEPLL0] = &ltepll0_clk.common.hw, [CLK_LTEPLL1] = &ltepll1_clk.common.hw, [CLK_GPLL] = &gpll_clk.common.hw, [CLK_CPPLL] = &cppll_clk.common.hw, [CLK_GPLL_42M5] = &gpll_42m5.hw, [CLK_TWPLL_768M] = &twpll_768m.hw, [CLK_TWPLL_384M] = &twpll_384m.hw, [CLK_TWPLL_192M] = &twpll_192m.hw, [CLK_TWPLL_96M] = &twpll_96m.hw, [CLK_TWPLL_48M] = &twpll_48m.hw, [CLK_TWPLL_24M] = &twpll_24m.hw, [CLK_TWPLL_12M] = &twpll_12m.hw, [CLK_TWPLL_512M] = &twpll_512m.hw, [CLK_TWPLL_256M] = &twpll_256m.hw, [CLK_TWPLL_128M] = &twpll_128m.hw, [CLK_TWPLL_64M] = &twpll_64m.hw, [CLK_TWPLL_307M2] = &twpll_307m2.hw, [CLK_TWPLL_153M6] = &twpll_153m6.hw, [CLK_TWPLL_76M8] = &twpll_76m8.hw, [CLK_TWPLL_51M2] = &twpll_51m2.hw, [CLK_TWPLL_38M4] = &twpll_38m4.hw, [CLK_TWPLL_19M2] = &twpll_19m2.hw, [CLK_L0_614M4] = &l0_614m4.hw, [CLK_L0_409M6] = &l0_409m6.hw, [CLK_L0_38M] = &l0_38m.hw, [CLK_L1_38M] = &l1_38m.hw, [CLK_RPLL0_192M] = &rpll0_192m.hw, [CLK_RPLL0_96M] = &rpll0_96m.hw, [CLK_RPLL0_48M] = &rpll0_48m.hw, [CLK_RPLL1_468M] = &rpll1_468m.hw, [CLK_RPLL1_192M] = &rpll1_192m.hw, [CLK_RPLL1_96M] = &rpll1_96m.hw, [CLK_RPLL1_64M] = &rpll1_64m.hw, [CLK_RPLL1_48M] = &rpll1_48m.hw, [CLK_DPLL0_50M] = &dpll0_50m.hw, [CLK_DPLL1_50M] = &dpll1_50m.hw, [CLK_CPPLL_50M] = &cppll_50m.hw, [CLK_M0_39M] = &m0_39m.hw, [CLK_M1_63M] = &m1_63m.hw, }, .num = CLK_PLL_NUM, }; static const struct sprd_clk_desc sc9860_pll_desc = { .clk_clks = sc9860_pll_clks, .num_clk_clks = ARRAY_SIZE(sc9860_pll_clks), .hw_clks = &sc9860_pll_hws, }; #define SC9860_MUX_FLAG \ (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT) static const char * const ap_apb_parents[] = { "ext-26m", "twpll-64m", "twpll-96m", "twpll-128m" }; static SPRD_MUX_CLK(ap_apb, "ap-apb", ap_apb_parents, 0x20, 0, 1, SC9860_MUX_FLAG); static const char * const ap_apb_usb3[] = { "ext-32k", "twpll-24m" }; static SPRD_MUX_CLK(ap_usb3, "ap-usb3", ap_apb_usb3, 0x2c, 0, 1, SC9860_MUX_FLAG); static const char * const uart_parents[] = { "ext-26m", "twpll-48m", "twpll-51m2", "twpll-96m" }; static SPRD_COMP_CLK(uart0_clk, "uart0", uart_parents, 0x30, 0, 2, 8, 3, 0); static SPRD_COMP_CLK(uart1_clk, "uart1", uart_parents, 0x34, 0, 2, 8, 3, 0); static SPRD_COMP_CLK(uart2_clk, "uart2", uart_parents, 0x38, 0, 2, 8, 3, 0); static SPRD_COMP_CLK(uart3_clk, "uart3", uart_parents, 0x3c, 0, 2, 8, 3, 0); static SPRD_COMP_CLK(uart4_clk, "uart4", uart_parents, 0x40, 0, 2, 8, 3, 0); static const char * const i2c_parents[] = { "ext-26m", "twpll-48m", "twpll-51m2", "twpll-153m6" }; static SPRD_COMP_CLK(i2c0_clk, "i2c0", i2c_parents, 0x44, 0, 2, 8, 3, 0); static SPRD_COMP_CLK(i2c1_clk, "i2c1", i2c_parents, 0x48, 0, 2, 8, 3, 0); static SPRD_COMP_CLK(i2c2_clk, "i2c2", i2c_parents, 0x4c, 0, 2, 8, 3, 0); static SPRD_COMP_CLK(i2c3_clk, "i2c3", i2c_parents, 0x50, 0, 2, 8, 3, 0); static SPRD_COMP_CLK(i2c4_clk, "i2c4", i2c_parents, 0x54, 0, 2, 8, 3, 0); static SPRD_COMP_CLK(i2c5_clk, "i2c5", i2c_parents, 0x58, 0, 2, 8, 3, 0); static const char * const spi_parents[] = { "ext-26m", "twpll-128m", "twpll-153m6", "twpll-192m" }; static SPRD_COMP_CLK(spi0_clk, "spi0", spi_parents, 0x5c, 0, 2, 8, 3, 0); static SPRD_COMP_CLK(spi1_clk, "spi1", spi_parents, 0x60, 0, 2, 8, 3, 0); static SPRD_COMP_CLK(spi2_clk, "spi2", spi_parents, 0x64, 0, 2, 8, 3, 0); static SPRD_COMP_CLK(spi3_clk, "spi3", spi_parents, 0x68, 0, 2, 8, 3, 0); static const char * const iis_parents[] = { "ext-26m", "twpll-128m", "twpll-153m6" }; static SPRD_COMP_CLK(iis0_clk, "iis0", iis_parents, 0x6c, 0, 2, 8, 6, 0); static SPRD_COMP_CLK(iis1_clk, "iis1", iis_parents, 0x70, 0, 2, 8, 6, 0); static SPRD_COMP_CLK(iis2_clk, "iis2", iis_parents, 0x74, 0, 2, 8, 6, 0); static SPRD_COMP_CLK(iis3_clk, "iis3", iis_parents, 0x78, 0, 2, 8, 6, 0); static struct sprd_clk_common *sc9860_ap_clks[] = { /* address base is 0x20000000 */ &ap_apb.common, &ap_usb3.common, &uart0_clk.common, &uart1_clk.common, &uart2_clk.common, &uart3_clk.common, &uart4_clk.common, &i2c0_clk.common, &i2c1_clk.common, &i2c2_clk.common, &i2c3_clk.common, &i2c4_clk.common, &i2c5_clk.common, &spi0_clk.common, &spi1_clk.common, &spi2_clk.common, &spi3_clk.common, &iis0_clk.common, &iis1_clk.common, &iis2_clk.common, &iis3_clk.common, }; static struct clk_hw_onecell_data sc9860_ap_clk_hws = { .hws = { [CLK_AP_APB] = &ap_apb.common.hw, [CLK_AP_USB3] = &ap_usb3.common.hw, [CLK_UART0] = &uart0_clk.common.hw, [CLK_UART1] = &uart1_clk.common.hw, [CLK_UART2] = &uart2_clk.common.hw, [CLK_UART3] = &uart3_clk.common.hw, [CLK_UART4] = &uart4_clk.common.hw, [CLK_I2C0] = &i2c0_clk.common.hw, [CLK_I2C1] = &i2c1_clk.common.hw, [CLK_I2C2] = &i2c2_clk.common.hw, [CLK_I2C3] = &i2c3_clk.common.hw, [CLK_I2C4] = &i2c4_clk.common.hw, [CLK_I2C5] = &i2c5_clk.common.hw, [CLK_SPI0] = &spi0_clk.common.hw, [CLK_SPI1] = &spi1_clk.common.hw, [CLK_SPI2] = &spi2_clk.common.hw, [CLK_SPI3] = &spi3_clk.common.hw, [CLK_IIS0] = &iis0_clk.common.hw, [CLK_IIS1] = &iis1_clk.common.hw, [CLK_IIS2] = &iis2_clk.common.hw, [CLK_IIS3] = &iis3_clk.common.hw, }, .num = CLK_AP_CLK_NUM, }; static const struct sprd_clk_desc sc9860_ap_clk_desc = { .clk_clks = sc9860_ap_clks, .num_clk_clks = ARRAY_SIZE(sc9860_ap_clks), .hw_clks = &sc9860_ap_clk_hws, }; static const char * const aon_apb_parents[] = { "rco-25m", "ext-26m", "ext-rco-100m", "twpll-96m", "twpll-128m", "twpll-153m6" }; static SPRD_COMP_CLK(aon_apb, "aon-apb", aon_apb_parents, 0x230, 0, 3, 8, 2, 0); static const char * const aux_parents[] = { "ext-32k", "rpll0-26m", "rpll1-26m", "ext-26m", "cppll-50m", "rco-25m", "dpll0-50m", "dpll1-50m", "gpll-42m5", "twpll-48m", "m0-39m", "m1-63m", "l0-38m", "l1-38m" }; static SPRD_COMP_CLK(aux0_clk, "aux0", aux_parents, 0x238, 0, 5, 8, 4, 0); static SPRD_COMP_CLK(aux1_clk, "aux1", aux_parents, 0x23c, 0, 5, 8, 4, 0); static SPRD_COMP_CLK(aux2_clk, "aux2", aux_parents, 0x240, 0, 5, 8, 4, 0); static SPRD_COMP_CLK(probe_clk, "probe", aux_parents, 0x244, 0, 5, 8, 4, 0); static const char * const sp_ahb_parents[] = { "rco-4m", "ext-26m", "ext-rco-100m", "twpll-96m", "twpll-128m", "twpll-153m6" }; static SPRD_COMP_CLK(sp_ahb, "sp-ahb", sp_ahb_parents, 0x2d0, 0, 3, 8, 2, 0); static const char * const cci_parents[] = { "ext-26m", "twpll-384m", "l0-614m4", "twpll-768m" }; static SPRD_COMP_CLK(cci_clk, "cci", cci_parents, 0x300, 0, 2, 8, 2, 0); static SPRD_COMP_CLK(gic_clk, "gic", cci_parents, 0x304, 0, 2, 8, 2, 0); static SPRD_COMP_CLK(cssys_clk, "cssys", cci_parents, 0x310, 0, 2, 8, 2, 0); static const char * const sdio_2x_parents[] = { "fac-1m", "ext-26m", "twpll-307m2", "twpll-384m", "l0-409m6" }; static SPRD_COMP_CLK(sdio0_2x, "sdio0-2x", sdio_2x_parents, 0x328, 0, 3, 8, 4, 0); static SPRD_COMP_CLK(sdio1_2x, "sdio1-2x", sdio_2x_parents, 0x330, 0, 3, 8, 4, 0); static SPRD_COMP_CLK(sdio2_2x, "sdio2-2x", sdio_2x_parents, 0x338, 0, 3, 8, 4, 0); static SPRD_COMP_CLK(emmc_2x, "emmc-2x", sdio_2x_parents, 0x340, 0, 3, 8, 4, 0); static SPRD_DIV_CLK(sdio0_1x, "sdio0-1x", "sdio0-2x", 0x32c, 8, 1, 0); static SPRD_DIV_CLK(sdio1_1x, "sdio1-1x", "sdio1-2x", 0x334, 8, 1, 0); static SPRD_DIV_CLK(sdio2_1x, "sdio2-1x", "sdio2-2x", 0x33c, 8, 1, 0); static SPRD_DIV_CLK(emmc_1x, "emmc-1x", "emmc-2x", 0x344, 8, 1, 0); static const char * const adi_parents[] = { "rco-4m", "ext-26m", "rco-25m", "twpll-38m4", "twpll-51m2" }; static SPRD_MUX_CLK(adi_clk, "adi", adi_parents, 0x234, 0, 3, SC9860_MUX_FLAG); static const char * const pwm_parents[] = { "ext-32k", "ext-26m", "rco-4m", "rco-25m", "twpll-48m" }; static SPRD_MUX_CLK(pwm0_clk, "pwm0", pwm_parents, 0x248, 0, 3, SC9860_MUX_FLAG); static SPRD_MUX_CLK(pwm1_clk, "pwm1", pwm_parents, 0x24c, 0, 3, SC9860_MUX_FLAG); static SPRD_MUX_CLK(pwm2_clk, "pwm2", pwm_parents, 0x250, 0, 3, SC9860_MUX_FLAG); static SPRD_MUX_CLK(pwm3_clk, "pwm3", pwm_parents, 0x254, 0, 3, SC9860_MUX_FLAG); static const char * const efuse_parents[] = { "rco-25m", "ext-26m" }; static SPRD_MUX_CLK(efuse_clk, "efuse", efuse_parents, 0x258, 0, 1, SC9860_MUX_FLAG); static const char * const cm3_uart_parents[] = { "rco-4m", "ext-26m", "rco-100m", "twpll-48m", "twpll-51m2", "twpll-96m", "twpll-128m" }; static SPRD_MUX_CLK(cm3_uart0, "cm3-uart0", cm3_uart_parents, 0x25c, 0, 3, SC9860_MUX_FLAG); static SPRD_MUX_CLK(cm3_uart1, "cm3-uart1", cm3_uart_parents, 0x260, 0, 3, SC9860_MUX_FLAG); static const char * const thm_parents[] = { "ext-32k", "fac-250k" }; static SPRD_MUX_CLK(thm_clk, "thm", thm_parents, 0x270, 0, 1, SC9860_MUX_FLAG); static const char * const cm3_i2c_parents[] = { "rco-4m", "ext-26m", "rco-100m", "twpll-48m", "twpll-51m2", "twpll-153m6" }; static SPRD_MUX_CLK(cm3_i2c0, "cm3-i2c0", cm3_i2c_parents, 0x274, 0, 3, SC9860_MUX_FLAG); static SPRD_MUX_CLK(cm3_i2c1, "cm3-i2c1", cm3_i2c_parents, 0x278, 0, 3, SC9860_MUX_FLAG); static SPRD_MUX_CLK(aon_i2c, "aon-i2c", cm3_i2c_parents, 0x280, 0, 3, SC9860_MUX_FLAG); static const char * const cm4_spi_parents[] = { "ext-26m", "twpll-96m", "rco-100m", "twpll-128m", "twpll-153m6", "twpll-192m" }; static SPRD_MUX_CLK(cm4_spi, "cm4-spi", cm4_spi_parents, 0x27c, 0, 3, SC9860_MUX_FLAG); static SPRD_MUX_CLK(avs_clk, "avs", uart_parents, 0x284, 0, 2, SC9860_MUX_FLAG); static const char * const ca53_dap_parents[] = { "ext-26m", "rco-4m", "rco-100m", "twpll-76m8", "twpll-128m", "twpll-153m6" }; static SPRD_MUX_CLK(ca53_dap, "ca53-dap", ca53_dap_parents, 0x288, 0, 3, SC9860_MUX_FLAG); static const char * const ca53_ts_parents[] = { "ext-32k", "ext-26m", "clk-twpll-128m", "clk-twpll-153m6" }; static SPRD_MUX_CLK(ca53_ts, "ca53-ts", ca53_ts_parents, 0x290, 0, 2, SC9860_MUX_FLAG); static const char * const djtag_tck_parents[] = { "rco-4m", "ext-26m" }; static SPRD_MUX_CLK(djtag_tck, "djtag-tck", djtag_tck_parents, 0x2c8, 0, 1, SC9860_MUX_FLAG); static const char * const pmu_parents[] = { "ext-32k", "rco-4m", "clk-4m" }; static SPRD_MUX_CLK(pmu_clk, "pmu", pmu_parents, 0x2e0, 0, 2, SC9860_MUX_FLAG); static const char * const pmu_26m_parents[] = { "rco-25m", "ext-26m" }; static SPRD_MUX_CLK(pmu_26m, "pmu-26m", pmu_26m_parents, 0x2e4, 0, 1, SC9860_MUX_FLAG); static const char * const debounce_parents[] = { "ext-32k", "rco-4m", "rco-25m", "ext-26m" }; static SPRD_MUX_CLK(debounce_clk, "debounce", debounce_parents, 0x2e8, 0, 2, SC9860_MUX_FLAG); static const char * const otg2_ref_parents[] = { "twpll-12m", "twpll-24m" }; static SPRD_MUX_CLK(otg2_ref, "otg2-ref", otg2_ref_parents, 0x2f4, 0, 1, SC9860_MUX_FLAG); static const char * const usb3_ref_parents[] = { "twpll-24m", "twpll-19m2", "twpll-48m" }; static SPRD_MUX_CLK(usb3_ref, "usb3-ref", usb3_ref_parents, 0x2f8, 0, 2, SC9860_MUX_FLAG); static const char * const ap_axi_parents[] = { "ext-26m", "twpll-76m8", "twpll-128m", "twpll-256m" }; static SPRD_MUX_CLK(ap_axi, "ap-axi", ap_axi_parents, 0x324, 0, 2, SC9860_MUX_FLAG); static struct sprd_clk_common *sc9860_aon_prediv[] = { /* address base is 0x402d0000 */ &aon_apb.common, &aux0_clk.common, &aux1_clk.common, &aux2_clk.common, &probe_clk.common, &sp_ahb.common, &cci_clk.common, &gic_clk.common, &cssys_clk.common, &sdio0_2x.common, &sdio1_2x.common, &sdio2_2x.common, &emmc_2x.common, &sdio0_1x.common, &sdio1_1x.common, &sdio2_1x.common, &emmc_1x.common, &adi_clk.common, &pwm0_clk.common, &pwm1_clk.common, &pwm2_clk.common, &pwm3_clk.common, &efuse_clk.common, &cm3_uart0.common, &cm3_uart1.common, &thm_clk.common, &cm3_i2c0.common, &cm3_i2c1.common, &cm4_spi.common, &aon_i2c.common, &avs_clk.common, &ca53_dap.common, &ca53_ts.common, &djtag_tck.common, &pmu_clk.common, &pmu_26m.common, &debounce_clk.common, &otg2_ref.common, &usb3_ref.common, &ap_axi.common, }; static struct clk_hw_onecell_data sc9860_aon_prediv_hws = { .hws = { [CLK_AON_APB] = &aon_apb.common.hw, [CLK_AUX0] = &aux0_clk.common.hw, [CLK_AUX1] = &aux1_clk.common.hw, [CLK_AUX2] = &aux2_clk.common.hw, [CLK_PROBE] = &probe_clk.common.hw, [CLK_SP_AHB] = &sp_ahb.common.hw, [CLK_CCI] = &cci_clk.common.hw, [CLK_GIC] = &gic_clk.common.hw, [CLK_CSSYS] = &cssys_clk.common.hw, [CLK_SDIO0_2X] = &sdio0_2x.common.hw, [CLK_SDIO1_2X] = &sdio1_2x.common.hw, [CLK_SDIO2_2X] = &sdio2_2x.common.hw, [CLK_EMMC_2X] = &emmc_2x.common.hw, [CLK_SDIO0_1X] = &sdio0_1x.common.hw, [CLK_SDIO1_1X] = &sdio1_1x.common.hw, [CLK_SDIO2_1X] = &sdio2_1x.common.hw, [CLK_EMMC_1X] = &emmc_1x.common.hw, [CLK_ADI] = &adi_clk.common.hw, [CLK_PWM0] = &pwm0_clk.common.hw, [CLK_PWM1] = &pwm1_clk.common.hw, [CLK_PWM2] = &pwm2_clk.common.hw, [CLK_PWM3] = &pwm3_clk.common.hw, [CLK_EFUSE] = &efuse_clk.common.hw, [CLK_CM3_UART0] = &cm3_uart0.common.hw, [CLK_CM3_UART1] = &cm3_uart1.common.hw, [CLK_THM] = &thm_clk.common.hw, [CLK_CM3_I2C0] = &cm3_i2c0.common.hw, [CLK_CM3_I2C1] = &cm3_i2c1.common.hw, [CLK_CM4_SPI] = &cm4_spi.common.hw, [CLK_AON_I2C] = &aon_i2c.common.hw, [CLK_AVS] = &avs_clk.common.hw, [CLK_CA53_DAP] = &ca53_dap.common.hw, [CLK_CA53_TS] = &ca53_ts.common.hw, [CLK_DJTAG_TCK] = &djtag_tck.common.hw, [CLK_PMU] = &pmu_clk.common.hw, [CLK_PMU_26M] = &pmu_26m.common.hw, [CLK_DEBOUNCE] = &debounce_clk.common.hw, [CLK_OTG2_REF] = &otg2_ref.common.hw, [CLK_USB3_REF] = &usb3_ref.common.hw, [CLK_AP_AXI] = &ap_axi.common.hw, }, .num = CLK_AON_PREDIV_NUM, }; static const struct sprd_clk_desc sc9860_aon_prediv_desc = { .clk_clks = sc9860_aon_prediv, .num_clk_clks = ARRAY_SIZE(sc9860_aon_prediv), .hw_clks = &sc9860_aon_prediv_hws, }; static SPRD_SC_GATE_CLK(usb3_eb, "usb3-eb", "ap-axi", 0x0, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(usb3_suspend, "usb3-suspend", "ap-axi", 0x0, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(usb3_ref_eb, "usb3-ref-eb", "ap-axi", 0x0, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(dma_eb, "dma-eb", "ap-axi", 0x0, 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(sdio0_eb, "sdio0-eb", "ap-axi", 0x0, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(sdio1_eb, "sdio1-eb", "ap-axi", 0x0, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(sdio2_eb, "sdio2-eb", "ap-axi", 0x0, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(emmc_eb, "emmc-eb", "ap-axi", 0x0, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(rom_eb, "rom-eb", "ap-axi", 0x0, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(busmon_eb, "busmon-eb", "ap-axi", 0x0, 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(cc63s_eb, "cc63s-eb", "ap-axi", 0x0, 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(cc63p_eb, "cc63p-eb", "ap-axi", 0x0, 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ce0_eb, "ce0-eb", "ap-axi", 0x0, 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ce1_eb, "ce1-eb", "ap-axi", 0x0, 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0); static struct sprd_clk_common *sc9860_apahb_gate[] = { /* address base is 0x20210000 */ &usb3_eb.common, &usb3_suspend.common, &usb3_ref_eb.common, &dma_eb.common, &sdio0_eb.common, &sdio1_eb.common, &sdio2_eb.common, &emmc_eb.common, &rom_eb.common, &busmon_eb.common, &cc63s_eb.common, &cc63p_eb.common, &ce0_eb.common, &ce1_eb.common, }; static struct clk_hw_onecell_data sc9860_apahb_gate_hws = { .hws = { [CLK_USB3_EB] = &usb3_eb.common.hw, [CLK_USB3_SUSPEND_EB] = &usb3_suspend.common.hw, [CLK_USB3_REF_EB] = &usb3_ref_eb.common.hw, [CLK_DMA_EB] = &dma_eb.common.hw, [CLK_SDIO0_EB] = &sdio0_eb.common.hw, [CLK_SDIO1_EB] = &sdio1_eb.common.hw, [CLK_SDIO2_EB] = &sdio2_eb.common.hw, [CLK_EMMC_EB] = &emmc_eb.common.hw, [CLK_ROM_EB] = &rom_eb.common.hw, [CLK_BUSMON_EB] = &busmon_eb.common.hw, [CLK_CC63S_EB] = &cc63s_eb.common.hw, [CLK_CC63P_EB] = &cc63p_eb.common.hw, [CLK_CE0_EB] = &ce0_eb.common.hw, [CLK_CE1_EB] = &ce1_eb.common.hw, }, .num = CLK_APAHB_GATE_NUM, }; static const struct sprd_clk_desc sc9860_apahb_gate_desc = { .clk_clks = sc9860_apahb_gate, .num_clk_clks = ARRAY_SIZE(sc9860_apahb_gate), .hw_clks = &sc9860_apahb_gate_hws, }; static SPRD_SC_GATE_CLK(avs_lit_eb, "avs-lit-eb", "aon-apb", 0x0, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(avs_big_eb, "avs-big-eb", "aon-apb", 0x0, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_intc5_eb, "ap-intc5-eb", "aon-apb", 0x0, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(gpio_eb, "gpio-eb", "aon-apb", 0x0, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(pwm0_eb, "pwm0-eb", "aon-apb", 0x0, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(pwm1_eb, "pwm1-eb", "aon-apb", 0x0, 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(pwm2_eb, "pwm2-eb", "aon-apb", 0x0, 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(pwm3_eb, "pwm3-eb", "aon-apb", 0x0, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(kpd_eb, "kpd-eb", "aon-apb", 0x0, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(aon_sys_eb, "aon-sys-eb", "aon-apb", 0x0, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_sys_eb, "ap-sys-eb", "aon-apb", 0x0, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(aon_tmr_eb, "aon-tmr-eb", "aon-apb", 0x0, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_tmr0_eb, "ap-tmr0-eb", "aon-apb", 0x0, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(efuse_eb, "efuse-eb", "aon-apb", 0x0, 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(eic_eb, "eic-eb", "aon-apb", 0x0, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(pub1_reg_eb, "pub1-reg-eb", "aon-apb", 0x0, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(adi_eb, "adi-eb", "aon-apb", 0x0, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_intc0_eb, "ap-intc0-eb", "aon-apb", 0x0, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_intc1_eb, "ap-intc1-eb", "aon-apb", 0x0, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_intc2_eb, "ap-intc2-eb", "aon-apb", 0x0, 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_intc3_eb, "ap-intc3-eb", "aon-apb", 0x0, 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_intc4_eb, "ap-intc4-eb", "aon-apb", 0x0, 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(splk_eb, "splk-eb", "aon-apb", 0x0, 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(mspi_eb, "mspi-eb", "aon-apb", 0x0, 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(pub0_reg_eb, "pub0-reg-eb", "aon-apb", 0x0, 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(pin_eb, "pin-eb", "aon-apb", 0x0, 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(aon_ckg_eb, "aon-ckg-eb", "aon-apb", 0x0, 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(gpu_eb, "gpu-eb", "aon-apb", 0x0, 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(apcpu_ts0_eb, "apcpu-ts0-eb", "aon-apb", 0x0, 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(apcpu_ts1_eb, "apcpu-ts1-eb", "aon-apb", 0x0, 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(dap_eb, "dap-eb", "aon-apb", 0x0, 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(i2c_eb, "i2c-eb", "aon-apb", 0x0, 0x1000, BIT(31), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(pmu_eb, "pmu-eb", "aon-apb", 0x4, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(thm_eb, "thm-eb", "aon-apb", 0x4, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(aux0_eb, "aux0-eb", "aon-apb", 0x4, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(aux1_eb, "aux1-eb", "aon-apb", 0x4, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(aux2_eb, "aux2-eb", "aon-apb", 0x4, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(probe_eb, "probe-eb", "aon-apb", 0x4, 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(gpu0_avs_eb, "gpu0-avs-eb", "aon-apb", 0x4, 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(gpu1_avs_eb, "gpu1-avs-eb", "aon-apb", 0x4, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(apcpu_wdg_eb, "apcpu-wdg-eb", "aon-apb", 0x4, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_tmr1_eb, "ap-tmr1-eb", "aon-apb", 0x4, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_tmr2_eb, "ap-tmr2-eb", "aon-apb", 0x4, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(disp_emc_eb, "disp-emc-eb", "aon-apb", 0x4, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(zip_emc_eb, "zip-emc-eb", "aon-apb", 0x4, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(gsp_emc_eb, "gsp-emc-eb", "aon-apb", 0x4, 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(osc_aon_eb, "osc-aon-eb", "aon-apb", 0x4, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(lvds_trx_eb, "lvds-trx-eb", "aon-apb", 0x4, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(lvds_tcxo_eb, "lvds-tcxo-eb", "aon-apb", 0x4, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(mdar_eb, "mdar-eb", "aon-apb", 0x4, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(rtc4m0_cal_eb, "rtc4m0-cal-eb", "aon-apb", 0x4, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(rct100m_cal_eb, "rct100m-cal-eb", "aon-apb", 0x4, 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(djtag_eb, "djtag-eb", "aon-apb", 0x4, 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(mbox_eb, "mbox-eb", "aon-apb", 0x4, 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(aon_dma_eb, "aon-dma-eb", "aon-apb", 0x4, 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(dbg_emc_eb, "dbg-emc-eb", "aon-apb", 0x4, 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(lvds_pll_div_en, "lvds-pll-div-en", "aon-apb", 0x4, 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(def_eb, "def-eb", "aon-apb", 0x4, 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(aon_apb_rsv0, "aon-apb-rsv0", "aon-apb", 0x4, 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(orp_jtag_eb, "orp-jtag-eb", "aon-apb", 0x4, 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(vsp_eb, "vsp-eb", "aon-apb", 0x4, 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(cam_eb, "cam-eb", "aon-apb", 0x4, 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(disp_eb, "disp-eb", "aon-apb", 0x4, 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(dbg_axi_if_eb, "dbg-axi-if-eb", "aon-apb", 0x4, 0x1000, BIT(31), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(sdio0_2x_en, "sdio0-2x-en", "aon-apb", 0x13c, 0x1000, BIT(2), 0, 0); static SPRD_SC_GATE_CLK(sdio1_2x_en, "sdio1-2x-en", "aon-apb", 0x13c, 0x1000, BIT(4), 0, 0); static SPRD_SC_GATE_CLK(sdio2_2x_en, "sdio2-2x-en", "aon-apb", 0x13c, 0x1000, BIT(6), 0, 0); static SPRD_SC_GATE_CLK(emmc_2x_en, "emmc-2x-en", "aon-apb", 0x13c, 0x1000, BIT(9), 0, 0); static SPRD_SC_GATE_CLK(arch_rtc_eb, "arch-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(kpb_rtc_eb, "kpb-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(aon_syst_rtc_eb, "aon-syst-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_syst_rtc_eb, "ap-syst-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(aon_tmr_rtc_eb, "aon-tmr-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_tmr0_rtc_eb, "ap-tmr0-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(eic_rtc_eb, "eic-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(eic_rtcdv5_eb, "eic-rtcdv5-eb", "aon-apb", 0x10, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_wdg_rtc_eb, "ap-wdg-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_tmr1_rtc_eb, "ap-tmr1-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_tmr2_rtc_eb, "ap-tmr2-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(dcxo_tmr_rtc_eb, "dcxo-tmr-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(bb_cal_rtc_eb, "bb-cal-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(avs_big_rtc_eb, "avs-big-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(avs_lit_rtc_eb, "avs-lit-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(avs_gpu0_rtc_eb, "avs-gpu0-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(avs_gpu1_rtc_eb, "avs-gpu1-rtc-eb", "aon-apb", 0x10, 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(gpu_ts_eb, "gpu-ts-eb", "aon-apb", 0x10, 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(rtcdv10_eb, "rtcdv10-eb", "aon-apb", 0x10, 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0); static struct sprd_clk_common *sc9860_aon_gate[] = { /* address base is 0x402e0000 */ &avs_lit_eb.common, &avs_big_eb.common, &ap_intc5_eb.common, &gpio_eb.common, &pwm0_eb.common, &pwm1_eb.common, &pwm2_eb.common, &pwm3_eb.common, &kpd_eb.common, &aon_sys_eb.common, &ap_sys_eb.common, &aon_tmr_eb.common, &ap_tmr0_eb.common, &efuse_eb.common, &eic_eb.common, &pub1_reg_eb.common, &adi_eb.common, &ap_intc0_eb.common, &ap_intc1_eb.common, &ap_intc2_eb.common, &ap_intc3_eb.common, &ap_intc4_eb.common, &splk_eb.common, &mspi_eb.common, &pub0_reg_eb.common, &pin_eb.common, &aon_ckg_eb.common, &gpu_eb.common, &apcpu_ts0_eb.common, &apcpu_ts1_eb.common, &dap_eb.common, &i2c_eb.common, &pmu_eb.common, &thm_eb.common, &aux0_eb.common, &aux1_eb.common, &aux2_eb.common, &probe_eb.common, &gpu0_avs_eb.common, &gpu1_avs_eb.common, &apcpu_wdg_eb.common, &ap_tmr1_eb.common, &ap_tmr2_eb.common, &disp_emc_eb.common, &zip_emc_eb.common, &gsp_emc_eb.common, &osc_aon_eb.common, &lvds_trx_eb.common, &lvds_tcxo_eb.common, &mdar_eb.common, &rtc4m0_cal_eb.common, &rct100m_cal_eb.common, &djtag_eb.common, &mbox_eb.common, &aon_dma_eb.common, &dbg_emc_eb.common, &lvds_pll_div_en.common, &def_eb.common, &aon_apb_rsv0.common, &orp_jtag_eb.common, &vsp_eb.common, &cam_eb.common, &disp_eb.common, &dbg_axi_if_eb.common, &sdio0_2x_en.common, &sdio1_2x_en.common, &sdio2_2x_en.common, &emmc_2x_en.common, &arch_rtc_eb.common, &kpb_rtc_eb.common, &aon_syst_rtc_eb.common, &ap_syst_rtc_eb.common, &aon_tmr_rtc_eb.common, &ap_tmr0_rtc_eb.common, &eic_rtc_eb.common, &eic_rtcdv5_eb.common, &ap_wdg_rtc_eb.common, &ap_tmr1_rtc_eb.common, &ap_tmr2_rtc_eb.common, &dcxo_tmr_rtc_eb.common, &bb_cal_rtc_eb.common, &avs_big_rtc_eb.common, &avs_lit_rtc_eb.common, &avs_gpu0_rtc_eb.common, &avs_gpu1_rtc_eb.common, &gpu_ts_eb.common, &rtcdv10_eb.common, }; static struct clk_hw_onecell_data sc9860_aon_gate_hws = { .hws = { [CLK_AVS_LIT_EB] = &avs_lit_eb.common.hw, [CLK_AVS_BIG_EB] = &avs_big_eb.common.hw, [CLK_AP_INTC5_EB] = &ap_intc5_eb.common.hw, [CLK_GPIO_EB] = &gpio_eb.common.hw, [CLK_PWM0_EB] = &pwm0_eb.common.hw, [CLK_PWM1_EB] = &pwm1_eb.common.hw, [CLK_PWM2_EB] = &pwm2_eb.common.hw, [CLK_PWM3_EB] = &pwm3_eb.common.hw, [CLK_KPD_EB] = &kpd_eb.common.hw, [CLK_AON_SYS_EB] = &aon_sys_eb.common.hw, [CLK_AP_SYS_EB] = &ap_sys_eb.common.hw, [CLK_AON_TMR_EB] = &aon_tmr_eb.common.hw, [CLK_AP_TMR0_EB] = &ap_tmr0_eb.common.hw, [CLK_EFUSE_EB] = &efuse_eb.common.hw, [CLK_EIC_EB] = &eic_eb.common.hw, [CLK_PUB1_REG_EB] = &pub1_reg_eb.common.hw, [CLK_ADI_EB] = &adi_eb.common.hw, [CLK_AP_INTC0_EB] = &ap_intc0_eb.common.hw, [CLK_AP_INTC1_EB] = &ap_intc1_eb.common.hw, [CLK_AP_INTC2_EB] = &ap_intc2_eb.common.hw, [CLK_AP_INTC3_EB] = &ap_intc3_eb.common.hw, [CLK_AP_INTC4_EB] = &ap_intc4_eb.common.hw, [CLK_SPLK_EB] = &splk_eb.common.hw, [CLK_MSPI_EB] = &mspi_eb.common.hw, [CLK_PUB0_REG_EB] = &pub0_reg_eb.common.hw, [CLK_PIN_EB] = &pin_eb.common.hw, [CLK_AON_CKG_EB] = &aon_ckg_eb.common.hw, [CLK_GPU_EB] = &gpu_eb.common.hw, [CLK_APCPU_TS0_EB] = &apcpu_ts0_eb.common.hw, [CLK_APCPU_TS1_EB] = &apcpu_ts1_eb.common.hw, [CLK_DAP_EB] = &dap_eb.common.hw, [CLK_I2C_EB] = &i2c_eb.common.hw, [CLK_PMU_EB] = &pmu_eb.common.hw, [CLK_THM_EB] = &thm_eb.common.hw, [CLK_AUX0_EB] = &aux0_eb.common.hw, [CLK_AUX1_EB] = &aux1_eb.common.hw, [CLK_AUX2_EB] = &aux2_eb.common.hw, [CLK_PROBE_EB] = &probe_eb.common.hw, [CLK_GPU0_AVS_EB] = &gpu0_avs_eb.common.hw, [CLK_GPU1_AVS_EB] = &gpu1_avs_eb.common.hw, [CLK_APCPU_WDG_EB] = &apcpu_wdg_eb.common.hw, [CLK_AP_TMR1_EB] = &ap_tmr1_eb.common.hw, [CLK_AP_TMR2_EB] = &ap_tmr2_eb.common.hw, [CLK_DISP_EMC_EB] = &disp_emc_eb.common.hw, [CLK_ZIP_EMC_EB] = &zip_emc_eb.common.hw, [CLK_GSP_EMC_EB] = &gsp_emc_eb.common.hw, [CLK_OSC_AON_EB] = &osc_aon_eb.common.hw, [CLK_LVDS_TRX_EB] = &lvds_trx_eb.common.hw, [CLK_LVDS_TCXO_EB] = &lvds_tcxo_eb.common.hw, [CLK_MDAR_EB] = &mdar_eb.common.hw, [CLK_RTC4M0_CAL_EB] = &rtc4m0_cal_eb.common.hw, [CLK_RCT100M_CAL_EB] = &rct100m_cal_eb.common.hw, [CLK_DJTAG_EB] = &djtag_eb.common.hw, [CLK_MBOX_EB] = &mbox_eb.common.hw, [CLK_AON_DMA_EB] = &aon_dma_eb.common.hw, [CLK_DBG_EMC_EB] = &dbg_emc_eb.common.hw, [CLK_LVDS_PLL_DIV_EN] = &lvds_pll_div_en.common.hw, [CLK_DEF_EB] = &def_eb.common.hw, [CLK_AON_APB_RSV0] = &aon_apb_rsv0.common.hw, [CLK_ORP_JTAG_EB] = &orp_jtag_eb.common.hw, [CLK_VSP_EB] = &vsp_eb.common.hw, [CLK_CAM_EB] = &cam_eb.common.hw, [CLK_DISP_EB] = &disp_eb.common.hw, [CLK_DBG_AXI_IF_EB] = &dbg_axi_if_eb.common.hw, [CLK_SDIO0_2X_EN] = &sdio0_2x_en.common.hw, [CLK_SDIO1_2X_EN] = &sdio1_2x_en.common.hw, [CLK_SDIO2_2X_EN] = &sdio2_2x_en.common.hw, [CLK_EMMC_2X_EN] = &emmc_2x_en.common.hw, [CLK_ARCH_RTC_EB] = &arch_rtc_eb.common.hw, [CLK_KPB_RTC_EB] = &kpb_rtc_eb.common.hw, [CLK_AON_SYST_RTC_EB] = &aon_syst_rtc_eb.common.hw, [CLK_AP_SYST_RTC_EB] = &ap_syst_rtc_eb.common.hw, [CLK_AON_TMR_RTC_EB] = &aon_tmr_rtc_eb.common.hw, [CLK_AP_TMR0_RTC_EB] = &ap_tmr0_rtc_eb.common.hw, [CLK_EIC_RTC_EB] = &eic_rtc_eb.common.hw, [CLK_EIC_RTCDV5_EB] = &eic_rtcdv5_eb.common.hw, [CLK_AP_WDG_RTC_EB] = &ap_wdg_rtc_eb.common.hw, [CLK_AP_TMR1_RTC_EB] = &ap_tmr1_rtc_eb.common.hw, [CLK_AP_TMR2_RTC_EB] = &ap_tmr2_rtc_eb.common.hw, [CLK_DCXO_TMR_RTC_EB] = &dcxo_tmr_rtc_eb.common.hw, [CLK_BB_CAL_RTC_EB] = &bb_cal_rtc_eb.common.hw, [CLK_AVS_BIG_RTC_EB] = &avs_big_rtc_eb.common.hw, [CLK_AVS_LIT_RTC_EB] = &avs_lit_rtc_eb.common.hw, [CLK_AVS_GPU0_RTC_EB] = &avs_gpu0_rtc_eb.common.hw, [CLK_AVS_GPU1_RTC_EB] = &avs_gpu1_rtc_eb.common.hw, [CLK_GPU_TS_EB] = &gpu_ts_eb.common.hw, [CLK_RTCDV10_EB] = &rtcdv10_eb.common.hw, }, .num = CLK_AON_GATE_NUM, }; static const struct sprd_clk_desc sc9860_aon_gate_desc = { .clk_clks = sc9860_aon_gate, .num_clk_clks = ARRAY_SIZE(sc9860_aon_gate), .hw_clks = &sc9860_aon_gate_hws, }; static const u8 mcu_table[] = { 0, 1, 2, 3, 4, 8 }; static const char * const lit_mcu_parents[] = { "ext-26m", "twpll-512m", "twpll-768m", "ltepll0", "twpll", "mpll0" }; static SPRD_COMP_CLK_TABLE(lit_mcu, "lit-mcu", lit_mcu_parents, 0x20, mcu_table, 0, 4, 4, 3, 0); static const char * const big_mcu_parents[] = { "ext-26m", "twpll-512m", "twpll-768m", "ltepll0", "twpll", "mpll1" }; static SPRD_COMP_CLK_TABLE(big_mcu, "big-mcu", big_mcu_parents, 0x24, mcu_table, 0, 4, 4, 3, 0); static struct sprd_clk_common *sc9860_aonsecure_clk[] = { /* address base is 0x40880000 */ &lit_mcu.common, &big_mcu.common, }; static struct clk_hw_onecell_data sc9860_aonsecure_clk_hws = { .hws = { [CLK_LIT_MCU] = &lit_mcu.common.hw, [CLK_BIG_MCU] = &big_mcu.common.hw, }, .num = CLK_AONSECURE_NUM, }; static const struct sprd_clk_desc sc9860_aonsecure_clk_desc = { .clk_clks = sc9860_aonsecure_clk, .num_clk_clks = ARRAY_SIZE(sc9860_aonsecure_clk), .hw_clks = &sc9860_aonsecure_clk_hws, }; static SPRD_SC_GATE_CLK(agcp_iis0_eb, "agcp-iis0-eb", "aon-apb", 0x0, 0x100, BIT(0), 0, 0); static SPRD_SC_GATE_CLK(agcp_iis1_eb, "agcp-iis1-eb", "aon-apb", 0x0, 0x100, BIT(1), 0, 0); static SPRD_SC_GATE_CLK(agcp_iis2_eb, "agcp-iis2-eb", "aon-apb", 0x0, 0x100, BIT(2), 0, 0); static SPRD_SC_GATE_CLK(agcp_iis3_eb, "agcp-iis3-eb", "aon-apb", 0x0, 0x100, BIT(3), 0, 0); static SPRD_SC_GATE_CLK(agcp_uart_eb, "agcp-uart-eb", "aon-apb", 0x0, 0x100, BIT(4), 0, 0); static SPRD_SC_GATE_CLK(agcp_dmacp_eb, "agcp-dmacp-eb", "aon-apb", 0x0, 0x100, BIT(5), 0, 0); static SPRD_SC_GATE_CLK(agcp_dmaap_eb, "agcp-dmaap-eb", "aon-apb", 0x0, 0x100, BIT(6), 0, 0); static SPRD_SC_GATE_CLK(agcp_arc48k_eb, "agcp-arc48k-eb", "aon-apb", 0x0, 0x100, BIT(10), 0, 0); static SPRD_SC_GATE_CLK(agcp_src44p1k_eb, "agcp-src44p1k-eb", "aon-apb", 0x0, 0x100, BIT(11), 0, 0); static SPRD_SC_GATE_CLK(agcp_mcdt_eb, "agcp-mcdt-eb", "aon-apb", 0x0, 0x100, BIT(12), 0, 0); static SPRD_SC_GATE_CLK(agcp_vbcifd_eb, "agcp-vbcifd-eb", "aon-apb", 0x0, 0x100, BIT(13), 0, 0); static SPRD_SC_GATE_CLK(agcp_vbc_eb, "agcp-vbc-eb", "aon-apb", 0x0, 0x100, BIT(14), 0, 0); static SPRD_SC_GATE_CLK(agcp_spinlock_eb, "agcp-spinlock-eb", "aon-apb", 0x0, 0x100, BIT(15), 0, 0); static SPRD_SC_GATE_CLK(agcp_icu_eb, "agcp-icu-eb", "aon-apb", 0x0, 0x100, BIT(16), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(agcp_ap_ashb_eb, "agcp-ap-ashb-eb", "aon-apb", 0x0, 0x100, BIT(17), 0, 0); static SPRD_SC_GATE_CLK(agcp_cp_ashb_eb, "agcp-cp-ashb-eb", "aon-apb", 0x0, 0x100, BIT(18), 0, 0); static SPRD_SC_GATE_CLK(agcp_aud_eb, "agcp-aud-eb", "aon-apb", 0x0, 0x100, BIT(19), 0, 0); static SPRD_SC_GATE_CLK(agcp_audif_eb, "agcp-audif-eb", "aon-apb", 0x0, 0x100, BIT(20), 0, 0); static struct sprd_clk_common *sc9860_agcp_gate[] = { /* address base is 0x415e0000 */ &agcp_iis0_eb.common, &agcp_iis1_eb.common, &agcp_iis2_eb.common, &agcp_iis3_eb.common, &agcp_uart_eb.common, &agcp_dmacp_eb.common, &agcp_dmaap_eb.common, &agcp_arc48k_eb.common, &agcp_src44p1k_eb.common, &agcp_mcdt_eb.common, &agcp_vbcifd_eb.common, &agcp_vbc_eb.common, &agcp_spinlock_eb.common, &agcp_icu_eb.common, &agcp_ap_ashb_eb.common, &agcp_cp_ashb_eb.common, &agcp_aud_eb.common, &agcp_audif_eb.common, }; static struct clk_hw_onecell_data sc9860_agcp_gate_hws = { .hws = { [CLK_AGCP_IIS0_EB] = &agcp_iis0_eb.common.hw, [CLK_AGCP_IIS1_EB] = &agcp_iis1_eb.common.hw, [CLK_AGCP_IIS2_EB] = &agcp_iis2_eb.common.hw, [CLK_AGCP_IIS3_EB] = &agcp_iis3_eb.common.hw, [CLK_AGCP_UART_EB] = &agcp_uart_eb.common.hw, [CLK_AGCP_DMACP_EB] = &agcp_dmacp_eb.common.hw, [CLK_AGCP_DMAAP_EB] = &agcp_dmaap_eb.common.hw, [CLK_AGCP_ARC48K_EB] = &agcp_arc48k_eb.common.hw, [CLK_AGCP_SRC44P1K_EB] = &agcp_src44p1k_eb.common.hw, [CLK_AGCP_MCDT_EB] = &agcp_mcdt_eb.common.hw, [CLK_AGCP_VBCIFD_EB] = &agcp_vbcifd_eb.common.hw, [CLK_AGCP_VBC_EB] = &agcp_vbc_eb.common.hw, [CLK_AGCP_SPINLOCK_EB] = &agcp_spinlock_eb.common.hw, [CLK_AGCP_ICU_EB] = &agcp_icu_eb.common.hw, [CLK_AGCP_AP_ASHB_EB] = &agcp_ap_ashb_eb.common.hw, [CLK_AGCP_CP_ASHB_EB] = &agcp_cp_ashb_eb.common.hw, [CLK_AGCP_AUD_EB] = &agcp_aud_eb.common.hw, [CLK_AGCP_AUDIF_EB] = &agcp_audif_eb.common.hw, }, .num = CLK_AGCP_GATE_NUM, }; static const struct sprd_clk_desc sc9860_agcp_gate_desc = { .clk_clks = sc9860_agcp_gate, .num_clk_clks = ARRAY_SIZE(sc9860_agcp_gate), .hw_clks = &sc9860_agcp_gate_hws, }; static const char * const gpu_parents[] = { "twpll-512m", "twpll-768m", "gpll" }; static SPRD_COMP_CLK(gpu_clk, "gpu", gpu_parents, 0x20, 0, 2, 8, 4, 0); static struct sprd_clk_common *sc9860_gpu_clk[] = { /* address base is 0x60200000 */ &gpu_clk.common, }; static struct clk_hw_onecell_data sc9860_gpu_clk_hws = { .hws = { [CLK_GPU] = &gpu_clk.common.hw, }, .num = CLK_GPU_NUM, }; static const struct sprd_clk_desc sc9860_gpu_clk_desc = { .clk_clks = sc9860_gpu_clk, .num_clk_clks = ARRAY_SIZE(sc9860_gpu_clk), .hw_clks = &sc9860_gpu_clk_hws, }; static const char * const ahb_parents[] = { "ext-26m", "twpll-96m", "twpll-128m", "twpll-153m6" }; static SPRD_MUX_CLK(ahb_vsp, "ahb-vsp", ahb_parents, 0x20, 0, 2, SC9860_MUX_FLAG); static const char * const vsp_parents[] = { "twpll-76m8", "twpll-128m", "twpll-256m", "twpll-307m2", "twpll-384m" }; static SPRD_COMP_CLK(vsp_clk, "vsp", vsp_parents, 0x24, 0, 3, 8, 2, 0); static const char * const dispc_parents[] = { "twpll-76m8", "twpll-128m", "twpll-256m", "twpll-307m2" }; static SPRD_COMP_CLK(vsp_enc, "vsp-enc", dispc_parents, 0x28, 0, 2, 8, 2, 0); static const char * const vpp_parents[] = { "twpll-96m", "twpll-153m6", "twpll-192m", "twpll-256m" }; static SPRD_MUX_CLK(vpp_clk, "vpp", vpp_parents, 0x2c, 0, 2, SC9860_MUX_FLAG); static const char * const vsp_26m_parents[] = { "ext-26m" }; static SPRD_MUX_CLK(vsp_26m, "vsp-26m", vsp_26m_parents, 0x30, 0, 1, SC9860_MUX_FLAG); static struct sprd_clk_common *sc9860_vsp_clk[] = { /* address base is 0x61000000 */ &ahb_vsp.common, &vsp_clk.common, &vsp_enc.common, &vpp_clk.common, &vsp_26m.common, }; static struct clk_hw_onecell_data sc9860_vsp_clk_hws = { .hws = { [CLK_AHB_VSP] = &ahb_vsp.common.hw, [CLK_VSP] = &vsp_clk.common.hw, [CLK_VSP_ENC] = &vsp_enc.common.hw, [CLK_VPP] = &vpp_clk.common.hw, [CLK_VSP_26M] = &vsp_26m.common.hw, }, .num = CLK_VSP_NUM, }; static const struct sprd_clk_desc sc9860_vsp_clk_desc = { .clk_clks = sc9860_vsp_clk, .num_clk_clks = ARRAY_SIZE(sc9860_vsp_clk), .hw_clks = &sc9860_vsp_clk_hws, }; static SPRD_SC_GATE_CLK(vsp_dec_eb, "vsp-dec-eb", "ahb-vsp", 0x0, 0x1000, BIT(0), 0, 0); static SPRD_SC_GATE_CLK(vsp_ckg_eb, "vsp-ckg-eb", "ahb-vsp", 0x0, 0x1000, BIT(1), 0, 0); static SPRD_SC_GATE_CLK(vsp_mmu_eb, "vsp-mmu-eb", "ahb-vsp", 0x0, 0x1000, BIT(2), 0, 0); static SPRD_SC_GATE_CLK(vsp_enc_eb, "vsp-enc-eb", "ahb-vsp", 0x0, 0x1000, BIT(3), 0, 0); static SPRD_SC_GATE_CLK(vpp_eb, "vpp-eb", "ahb-vsp", 0x0, 0x1000, BIT(4), 0, 0); static SPRD_SC_GATE_CLK(vsp_26m_eb, "vsp-26m-eb", "ahb-vsp", 0x0, 0x1000, BIT(5), 0, 0); static SPRD_GATE_CLK(vsp_axi_gate, "vsp-axi-gate", "ahb-vsp", 0x8, BIT(0), 0, 0); static SPRD_GATE_CLK(vsp_enc_gate, "vsp-enc-gate", "ahb-vsp", 0x8, BIT(1), 0, 0); static SPRD_GATE_CLK(vpp_axi_gate, "vpp-axi-gate", "ahb-vsp", 0x8, BIT(2), 0, 0); static SPRD_GATE_CLK(vsp_bm_gate, "vsp-bm-gate", "ahb-vsp", 0x8, BIT(8), 0, 0); static SPRD_GATE_CLK(vsp_enc_bm_gate, "vsp-enc-bm-gate", "ahb-vsp", 0x8, BIT(9), 0, 0); static SPRD_GATE_CLK(vpp_bm_gate, "vpp-bm-gate", "ahb-vsp", 0x8, BIT(10), 0, 0); static struct sprd_clk_common *sc9860_vsp_gate[] = { /* address base is 0x61100000 */ &vsp_dec_eb.common, &vsp_ckg_eb.common, &vsp_mmu_eb.common, &vsp_enc_eb.common, &vpp_eb.common, &vsp_26m_eb.common, &vsp_axi_gate.common, &vsp_enc_gate.common, &vpp_axi_gate.common, &vsp_bm_gate.common, &vsp_enc_bm_gate.common, &vpp_bm_gate.common, }; static struct clk_hw_onecell_data sc9860_vsp_gate_hws = { .hws = { [CLK_VSP_DEC_EB] = &vsp_dec_eb.common.hw, [CLK_VSP_CKG_EB] = &vsp_ckg_eb.common.hw, [CLK_VSP_MMU_EB] = &vsp_mmu_eb.common.hw, [CLK_VSP_ENC_EB] = &vsp_enc_eb.common.hw, [CLK_VPP_EB] = &vpp_eb.common.hw, [CLK_VSP_26M_EB] = &vsp_26m_eb.common.hw, [CLK_VSP_AXI_GATE] = &vsp_axi_gate.common.hw, [CLK_VSP_ENC_GATE] = &vsp_enc_gate.common.hw, [CLK_VPP_AXI_GATE] = &vpp_axi_gate.common.hw, [CLK_VSP_BM_GATE] = &vsp_bm_gate.common.hw, [CLK_VSP_ENC_BM_GATE] = &vsp_enc_bm_gate.common.hw, [CLK_VPP_BM_GATE] = &vpp_bm_gate.common.hw, }, .num = CLK_VSP_GATE_NUM, }; static const struct sprd_clk_desc sc9860_vsp_gate_desc = { .clk_clks = sc9860_vsp_gate, .num_clk_clks = ARRAY_SIZE(sc9860_vsp_gate), .hw_clks = &sc9860_vsp_gate_hws, }; static SPRD_MUX_CLK(ahb_cam, "ahb-cam", ahb_parents, 0x20, 0, 2, SC9860_MUX_FLAG); static const char * const sensor_parents[] = { "ext-26m", "twpll-48m", "twpll-76m8", "twpll-96m" }; static SPRD_COMP_CLK(sensor0_clk, "sensor0", sensor_parents, 0x24, 0, 2, 8, 3, 0); static SPRD_COMP_CLK(sensor1_clk, "sensor1", sensor_parents, 0x28, 0, 2, 8, 3, 0); static SPRD_COMP_CLK(sensor2_clk, "sensor2", sensor_parents, 0x2c, 0, 2, 8, 3, 0); static SPRD_GATE_CLK(mipi_csi0_eb, "mipi-csi0-eb", "ahb-cam", 0x4c, BIT(16), 0, 0); static SPRD_GATE_CLK(mipi_csi1_eb, "mipi-csi1-eb", "ahb-cam", 0x50, BIT(16), 0, 0); static struct sprd_clk_common *sc9860_cam_clk[] = { /* address base is 0x62000000 */ &ahb_cam.common, &sensor0_clk.common, &sensor1_clk.common, &sensor2_clk.common, &mipi_csi0_eb.common, &mipi_csi1_eb.common, }; static struct clk_hw_onecell_data sc9860_cam_clk_hws = { .hws = { [CLK_AHB_CAM] = &ahb_cam.common.hw, [CLK_SENSOR0] = &sensor0_clk.common.hw, [CLK_SENSOR1] = &sensor1_clk.common.hw, [CLK_SENSOR2] = &sensor2_clk.common.hw, [CLK_MIPI_CSI0_EB] = &mipi_csi0_eb.common.hw, [CLK_MIPI_CSI1_EB] = &mipi_csi1_eb.common.hw, }, .num = CLK_CAM_NUM, }; static const struct sprd_clk_desc sc9860_cam_clk_desc = { .clk_clks = sc9860_cam_clk, .num_clk_clks = ARRAY_SIZE(sc9860_cam_clk), .hw_clks = &sc9860_cam_clk_hws, }; static SPRD_SC_GATE_CLK(dcam0_eb, "dcam0-eb", "ahb-cam", 0x0, 0x1000, BIT(0), 0, 0); static SPRD_SC_GATE_CLK(dcam1_eb, "dcam1-eb", "ahb-cam", 0x0, 0x1000, BIT(1), 0, 0); static SPRD_SC_GATE_CLK(isp0_eb, "isp0-eb", "ahb-cam", 0x0, 0x1000, BIT(2), 0, 0); static SPRD_SC_GATE_CLK(csi0_eb, "csi0-eb", "ahb-cam", 0x0, 0x1000, BIT(3), 0, 0); static SPRD_SC_GATE_CLK(csi1_eb, "csi1-eb", "ahb-cam", 0x0, 0x1000, BIT(4), 0, 0); static SPRD_SC_GATE_CLK(jpg0_eb, "jpg0-eb", "ahb-cam", 0x0, 0x1000, BIT(5), 0, 0); static SPRD_SC_GATE_CLK(jpg1_eb, "jpg1-eb", "ahb-cam", 0x0, 0x1000, BIT(6), 0, 0); static SPRD_SC_GATE_CLK(cam_ckg_eb, "cam-ckg-eb", "ahb-cam", 0x0, 0x1000, BIT(7), 0, 0); static SPRD_SC_GATE_CLK(cam_mmu_eb, "cam-mmu-eb", "ahb-cam", 0x0, 0x1000, BIT(8), 0, 0); static SPRD_SC_GATE_CLK(isp1_eb, "isp1-eb", "ahb-cam", 0x0, 0x1000, BIT(9), 0, 0); static SPRD_SC_GATE_CLK(cpp_eb, "cpp-eb", "ahb-cam", 0x0, 0x1000, BIT(10), 0, 0); static SPRD_SC_GATE_CLK(mmu_pf_eb, "mmu-pf-eb", "ahb-cam", 0x0, 0x1000, BIT(11), 0, 0); static SPRD_SC_GATE_CLK(isp2_eb, "isp2-eb", "ahb-cam", 0x0, 0x1000, BIT(12), 0, 0); static SPRD_SC_GATE_CLK(dcam2isp_if_eb, "dcam2isp-if-eb", "ahb-cam", 0x0, 0x1000, BIT(13), 0, 0); static SPRD_SC_GATE_CLK(isp2dcam_if_eb, "isp2dcam-if-eb", "ahb-cam", 0x0, 0x1000, BIT(14), 0, 0); static SPRD_SC_GATE_CLK(isp_lclk_eb, "isp-lclk-eb", "ahb-cam", 0x0, 0x1000, BIT(15), 0, 0); static SPRD_SC_GATE_CLK(isp_iclk_eb, "isp-iclk-eb", "ahb-cam", 0x0, 0x1000, BIT(16), 0, 0); static SPRD_SC_GATE_CLK(isp_mclk_eb, "isp-mclk-eb", "ahb-cam", 0x0, 0x1000, BIT(17), 0, 0); static SPRD_SC_GATE_CLK(isp_pclk_eb, "isp-pclk-eb", "ahb-cam", 0x0, 0x1000, BIT(18), 0, 0); static SPRD_SC_GATE_CLK(isp_isp2dcam_eb, "isp-isp2dcam-eb", "ahb-cam", 0x0, 0x1000, BIT(19), 0, 0); static SPRD_SC_GATE_CLK(dcam0_if_eb, "dcam0-if-eb", "ahb-cam", 0x0, 0x1000, BIT(20), 0, 0); static SPRD_SC_GATE_CLK(clk26m_if_eb, "clk26m-if-eb", "ahb-cam", 0x0, 0x1000, BIT(21), 0, 0); static SPRD_GATE_CLK(cphy0_gate, "cphy0-gate", "ahb-cam", 0x8, BIT(0), 0, 0); static SPRD_GATE_CLK(mipi_csi0_gate, "mipi-csi0-gate", "ahb-cam", 0x8, BIT(1), 0, 0); static SPRD_GATE_CLK(cphy1_gate, "cphy1-gate", "ahb-cam", 0x8, BIT(2), 0, 0); static SPRD_GATE_CLK(mipi_csi1, "mipi-csi1", "ahb-cam", 0x8, BIT(3), 0, 0); static SPRD_GATE_CLK(dcam0_axi_gate, "dcam0-axi-gate", "ahb-cam", 0x8, BIT(4), 0, 0); static SPRD_GATE_CLK(dcam1_axi_gate, "dcam1-axi-gate", "ahb-cam", 0x8, BIT(5), 0, 0); static SPRD_GATE_CLK(sensor0_gate, "sensor0-gate", "ahb-cam", 0x8, BIT(6), 0, 0); static SPRD_GATE_CLK(sensor1_gate, "sensor1-gate", "ahb-cam", 0x8, BIT(7), 0, 0); static SPRD_GATE_CLK(jpg0_axi_gate, "jpg0-axi-gate", "ahb-cam", 0x8, BIT(8), 0, 0); static SPRD_GATE_CLK(gpg1_axi_gate, "gpg1-axi-gate", "ahb-cam", 0x8, BIT(9), 0, 0); static SPRD_GATE_CLK(isp0_axi_gate, "isp0-axi-gate", "ahb-cam", 0x8, BIT(10), 0, 0); static SPRD_GATE_CLK(isp1_axi_gate, "isp1-axi-gate", "ahb-cam", 0x8, BIT(11), 0, 0); static SPRD_GATE_CLK(isp2_axi_gate, "isp2-axi-gate", "ahb-cam", 0x8, BIT(12), 0, 0); static SPRD_GATE_CLK(cpp_axi_gate, "cpp-axi-gate", "ahb-cam", 0x8, BIT(13), 0, 0); static SPRD_GATE_CLK(d0_if_axi_gate, "d0-if-axi-gate", "ahb-cam", 0x8, BIT(14), 0, 0); static SPRD_GATE_CLK(d2i_if_axi_gate, "d2i-if-axi-gate", "ahb-cam", 0x8, BIT(15), 0, 0); static SPRD_GATE_CLK(i2d_if_axi_gate, "i2d-if-axi-gate", "ahb-cam", 0x8, BIT(16), 0, 0); static SPRD_GATE_CLK(spare_axi_gate, "spare-axi-gate", "ahb-cam", 0x8, BIT(17), 0, 0); static SPRD_GATE_CLK(sensor2_gate, "sensor2-gate", "ahb-cam", 0x8, BIT(18), 0, 0); static SPRD_SC_GATE_CLK(d0if_in_d_en, "d0if-in-d-en", "ahb-cam", 0x28, 0x1000, BIT(0), 0, 0); static SPRD_SC_GATE_CLK(d1if_in_d_en, "d1if-in-d-en", "ahb-cam", 0x28, 0x1000, BIT(1), 0, 0); static SPRD_SC_GATE_CLK(d0if_in_d2i_en, "d0if-in-d2i-en", "ahb-cam", 0x28, 0x1000, BIT(2), 0, 0); static SPRD_SC_GATE_CLK(d1if_in_d2i_en, "d1if-in-d2i-en", "ahb-cam", 0x28, 0x1000, BIT(3), 0, 0); static SPRD_SC_GATE_CLK(ia_in_d2i_en, "ia-in-d2i-en", "ahb-cam", 0x28, 0x1000, BIT(4), 0, 0); static SPRD_SC_GATE_CLK(ib_in_d2i_en, "ib-in-d2i-en", "ahb-cam", 0x28, 0x1000, BIT(5), 0, 0); static SPRD_SC_GATE_CLK(ic_in_d2i_en, "ic-in-d2i-en", "ahb-cam", 0x28, 0x1000, BIT(6), 0, 0); static SPRD_SC_GATE_CLK(ia_in_i_en, "ia-in-i-en", "ahb-cam", 0x28, 0x1000, BIT(7), 0, 0); static SPRD_SC_GATE_CLK(ib_in_i_en, "ib-in-i-en", "ahb-cam", 0x28, 0x1000, BIT(8), 0, 0); static SPRD_SC_GATE_CLK(ic_in_i_en, "ic-in-i-en", "ahb-cam", 0x28, 0x1000, BIT(9), 0, 0); static struct sprd_clk_common *sc9860_cam_gate[] = { /* address base is 0x62100000 */ &dcam0_eb.common, &dcam1_eb.common, &isp0_eb.common, &csi0_eb.common, &csi1_eb.common, &jpg0_eb.common, &jpg1_eb.common, &cam_ckg_eb.common, &cam_mmu_eb.common, &isp1_eb.common, &cpp_eb.common, &mmu_pf_eb.common, &isp2_eb.common, &dcam2isp_if_eb.common, &isp2dcam_if_eb.common, &isp_lclk_eb.common, &isp_iclk_eb.common, &isp_mclk_eb.common, &isp_pclk_eb.common, &isp_isp2dcam_eb.common, &dcam0_if_eb.common, &clk26m_if_eb.common, &cphy0_gate.common, &mipi_csi0_gate.common, &cphy1_gate.common, &mipi_csi1.common, &dcam0_axi_gate.common, &dcam1_axi_gate.common, &sensor0_gate.common, &sensor1_gate.common, &jpg0_axi_gate.common, &gpg1_axi_gate.common, &isp0_axi_gate.common, &isp1_axi_gate.common, &isp2_axi_gate.common, &cpp_axi_gate.common, &d0_if_axi_gate.common, &d2i_if_axi_gate.common, &i2d_if_axi_gate.common, &spare_axi_gate.common, &sensor2_gate.common, &d0if_in_d_en.common, &d1if_in_d_en.common, &d0if_in_d2i_en.common, &d1if_in_d2i_en.common, &ia_in_d2i_en.common, &ib_in_d2i_en.common, &ic_in_d2i_en.common, &ia_in_i_en.common, &ib_in_i_en.common, &ic_in_i_en.common, }; static struct clk_hw_onecell_data sc9860_cam_gate_hws = { .hws = { [CLK_DCAM0_EB] = &dcam0_eb.common.hw, [CLK_DCAM1_EB] = &dcam1_eb.common.hw, [CLK_ISP0_EB] = &isp0_eb.common.hw, [CLK_CSI0_EB] = &csi0_eb.common.hw, [CLK_CSI1_EB] = &csi1_eb.common.hw, [CLK_JPG0_EB] = &jpg0_eb.common.hw, [CLK_JPG1_EB] = &jpg1_eb.common.hw, [CLK_CAM_CKG_EB] = &cam_ckg_eb.common.hw, [CLK_CAM_MMU_EB] = &cam_mmu_eb.common.hw, [CLK_ISP1_EB] = &isp1_eb.common.hw, [CLK_CPP_EB] = &cpp_eb.common.hw, [CLK_MMU_PF_EB] = &mmu_pf_eb.common.hw, [CLK_ISP2_EB] = &isp2_eb.common.hw, [CLK_DCAM2ISP_IF_EB] = &dcam2isp_if_eb.common.hw, [CLK_ISP2DCAM_IF_EB] = &isp2dcam_if_eb.common.hw, [CLK_ISP_LCLK_EB] = &isp_lclk_eb.common.hw, [CLK_ISP_ICLK_EB] = &isp_iclk_eb.common.hw, [CLK_ISP_MCLK_EB] = &isp_mclk_eb.common.hw, [CLK_ISP_PCLK_EB] = &isp_pclk_eb.common.hw, [CLK_ISP_ISP2DCAM_EB] = &isp_isp2dcam_eb.common.hw, [CLK_DCAM0_IF_EB] = &dcam0_if_eb.common.hw, [CLK_CLK26M_IF_EB] = &clk26m_if_eb.common.hw, [CLK_CPHY0_GATE] = &cphy0_gate.common.hw, [CLK_MIPI_CSI0_GATE] = &mipi_csi0_gate.common.hw, [CLK_CPHY1_GATE] = &cphy1_gate.common.hw, [CLK_MIPI_CSI1] = &mipi_csi1.common.hw, [CLK_DCAM0_AXI_GATE] = &dcam0_axi_gate.common.hw, [CLK_DCAM1_AXI_GATE] = &dcam1_axi_gate.common.hw, [CLK_SENSOR0_GATE] = &sensor0_gate.common.hw, [CLK_SENSOR1_GATE] = &sensor1_gate.common.hw, [CLK_JPG0_AXI_GATE] = &jpg0_axi_gate.common.hw, [CLK_GPG1_AXI_GATE] = &gpg1_axi_gate.common.hw, [CLK_ISP0_AXI_GATE] = &isp0_axi_gate.common.hw, [CLK_ISP1_AXI_GATE] = &isp1_axi_gate.common.hw, [CLK_ISP2_AXI_GATE] = &isp2_axi_gate.common.hw, [CLK_CPP_AXI_GATE] = &cpp_axi_gate.common.hw, [CLK_D0_IF_AXI_GATE] = &d0_if_axi_gate.common.hw, [CLK_D2I_IF_AXI_GATE] = &d2i_if_axi_gate.common.hw, [CLK_I2D_IF_AXI_GATE] = &i2d_if_axi_gate.common.hw, [CLK_SPARE_AXI_GATE] = &spare_axi_gate.common.hw, [CLK_SENSOR2_GATE] = &sensor2_gate.common.hw, [CLK_D0IF_IN_D_EN] = &d0if_in_d_en.common.hw, [CLK_D1IF_IN_D_EN] = &d1if_in_d_en.common.hw, [CLK_D0IF_IN_D2I_EN] = &d0if_in_d2i_en.common.hw, [CLK_D1IF_IN_D2I_EN] = &d1if_in_d2i_en.common.hw, [CLK_IA_IN_D2I_EN] = &ia_in_d2i_en.common.hw, [CLK_IB_IN_D2I_EN] = &ib_in_d2i_en.common.hw, [CLK_IC_IN_D2I_EN] = &ic_in_d2i_en.common.hw, [CLK_IA_IN_I_EN] = &ia_in_i_en.common.hw, [CLK_IB_IN_I_EN] = &ib_in_i_en.common.hw, [CLK_IC_IN_I_EN] = &ic_in_i_en.common.hw, }, .num = CLK_CAM_GATE_NUM, }; static const struct sprd_clk_desc sc9860_cam_gate_desc = { .clk_clks = sc9860_cam_gate, .num_clk_clks = ARRAY_SIZE(sc9860_cam_gate), .hw_clks = &sc9860_cam_gate_hws, }; static SPRD_MUX_CLK(ahb_disp, "ahb-disp", ahb_parents, 0x20, 0, 2, SC9860_MUX_FLAG); static SPRD_COMP_CLK(dispc0_dpi, "dispc0-dpi", dispc_parents, 0x34, 0, 2, 8, 2, 0); static SPRD_COMP_CLK(dispc1_dpi, "dispc1-dpi", dispc_parents, 0x40, 0, 2, 8, 2, 0); static struct sprd_clk_common *sc9860_disp_clk[] = { /* address base is 0x63000000 */ &ahb_disp.common, &dispc0_dpi.common, &dispc1_dpi.common, }; static struct clk_hw_onecell_data sc9860_disp_clk_hws = { .hws = { [CLK_AHB_DISP] = &ahb_disp.common.hw, [CLK_DISPC0_DPI] = &dispc0_dpi.common.hw, [CLK_DISPC1_DPI] = &dispc1_dpi.common.hw, }, .num = CLK_DISP_NUM, }; static const struct sprd_clk_desc sc9860_disp_clk_desc = { .clk_clks = sc9860_disp_clk, .num_clk_clks = ARRAY_SIZE(sc9860_disp_clk), .hw_clks = &sc9860_disp_clk_hws, }; static SPRD_SC_GATE_CLK(dispc0_eb, "dispc0-eb", "ahb-disp", 0x0, 0x1000, BIT(0), 0, 0); static SPRD_SC_GATE_CLK(dispc1_eb, "dispc1-eb", "ahb-disp", 0x0, 0x1000, BIT(1), 0, 0); static SPRD_SC_GATE_CLK(dispc_mmu_eb, "dispc-mmu-eb", "ahb-disp", 0x0, 0x1000, BIT(2), 0, 0); static SPRD_SC_GATE_CLK(gsp0_eb, "gsp0-eb", "ahb-disp", 0x0, 0x1000, BIT(3), 0, 0); static SPRD_SC_GATE_CLK(gsp1_eb, "gsp1-eb", "ahb-disp", 0x0, 0x1000, BIT(4), 0, 0); static SPRD_SC_GATE_CLK(gsp0_mmu_eb, "gsp0-mmu-eb", "ahb-disp", 0x0, 0x1000, BIT(5), 0, 0); static SPRD_SC_GATE_CLK(gsp1_mmu_eb, "gsp1-mmu-eb", "ahb-disp", 0x0, 0x1000, BIT(6), 0, 0); static SPRD_SC_GATE_CLK(dsi0_eb, "dsi0-eb", "ahb-disp", 0x0, 0x1000, BIT(7), 0, 0); static SPRD_SC_GATE_CLK(dsi1_eb, "dsi1-eb", "ahb-disp", 0x0, 0x1000, BIT(8), 0, 0); static SPRD_SC_GATE_CLK(disp_ckg_eb, "disp-ckg-eb", "ahb-disp", 0x0, 0x1000, BIT(9), 0, 0); static SPRD_SC_GATE_CLK(disp_gpu_eb, "disp-gpu-eb", "ahb-disp", 0x0, 0x1000, BIT(10), 0, 0); static SPRD_SC_GATE_CLK(gpu_mtx_eb, "gpu-mtx-eb", "ahb-disp", 0x0, 0x1000, BIT(13), 0, 0); static SPRD_SC_GATE_CLK(gsp_mtx_eb, "gsp-mtx-eb", "ahb-disp", 0x0, 0x1000, BIT(14), 0, 0); static SPRD_SC_GATE_CLK(tmc_mtx_eb, "tmc-mtx-eb", "ahb-disp", 0x0, 0x1000, BIT(15), 0, 0); static SPRD_SC_GATE_CLK(dispc_mtx_eb, "dispc-mtx-eb", "ahb-disp", 0x0, 0x1000, BIT(16), 0, 0); static SPRD_GATE_CLK(dphy0_gate, "dphy0-gate", "ahb-disp", 0x8, BIT(0), 0, 0); static SPRD_GATE_CLK(dphy1_gate, "dphy1-gate", "ahb-disp", 0x8, BIT(1), 0, 0); static SPRD_GATE_CLK(gsp0_a_gate, "gsp0-a-gate", "ahb-disp", 0x8, BIT(2), 0, 0); static SPRD_GATE_CLK(gsp1_a_gate, "gsp1-a-gate", "ahb-disp", 0x8, BIT(3), 0, 0); static SPRD_GATE_CLK(gsp0_f_gate, "gsp0-f-gate", "ahb-disp", 0x8, BIT(4), 0, 0); static SPRD_GATE_CLK(gsp1_f_gate, "gsp1-f-gate", "ahb-disp", 0x8, BIT(5), 0, 0); static SPRD_GATE_CLK(d_mtx_f_gate, "d-mtx-f-gate", "ahb-disp", 0x8, BIT(6), 0, 0); static SPRD_GATE_CLK(d_mtx_a_gate, "d-mtx-a-gate", "ahb-disp", 0x8, BIT(7), 0, 0); static SPRD_GATE_CLK(d_noc_f_gate, "d-noc-f-gate", "ahb-disp", 0x8, BIT(8), 0, 0); static SPRD_GATE_CLK(d_noc_a_gate, "d-noc-a-gate", "ahb-disp", 0x8, BIT(9), 0, 0); static SPRD_GATE_CLK(gsp_mtx_f_gate, "gsp-mtx-f-gate", "ahb-disp", 0x8, BIT(10), 0, 0); static SPRD_GATE_CLK(gsp_mtx_a_gate, "gsp-mtx-a-gate", "ahb-disp", 0x8, BIT(11), 0, 0); static SPRD_GATE_CLK(gsp_noc_f_gate, "gsp-noc-f-gate", "ahb-disp", 0x8, BIT(12), 0, 0); static SPRD_GATE_CLK(gsp_noc_a_gate, "gsp-noc-a-gate", "ahb-disp", 0x8, BIT(13), 0, 0); static SPRD_GATE_CLK(dispm0idle_gate, "dispm0idle-gate", "ahb-disp", 0x8, BIT(14), 0, 0); static SPRD_GATE_CLK(gspm0idle_gate, "gspm0idle-gate", "ahb-disp", 0x8, BIT(15), 0, 0); static struct sprd_clk_common *sc9860_disp_gate[] = { /* address base is 0x63100000 */ &dispc0_eb.common, &dispc1_eb.common, &dispc_mmu_eb.common, &gsp0_eb.common, &gsp1_eb.common, &gsp0_mmu_eb.common, &gsp1_mmu_eb.common, &dsi0_eb.common, &dsi1_eb.common, &disp_ckg_eb.common, &disp_gpu_eb.common, &gpu_mtx_eb.common, &gsp_mtx_eb.common, &tmc_mtx_eb.common, &dispc_mtx_eb.common, &dphy0_gate.common, &dphy1_gate.common, &gsp0_a_gate.common, &gsp1_a_gate.common, &gsp0_f_gate.common, &gsp1_f_gate.common, &d_mtx_f_gate.common, &d_mtx_a_gate.common, &d_noc_f_gate.common, &d_noc_a_gate.common, &gsp_mtx_f_gate.common, &gsp_mtx_a_gate.common, &gsp_noc_f_gate.common, &gsp_noc_a_gate.common, &dispm0idle_gate.common, &gspm0idle_gate.common, }; static struct clk_hw_onecell_data sc9860_disp_gate_hws = { .hws = { [CLK_DISPC0_EB] = &dispc0_eb.common.hw, [CLK_DISPC1_EB] = &dispc1_eb.common.hw, [CLK_DISPC_MMU_EB] = &dispc_mmu_eb.common.hw, [CLK_GSP0_EB] = &gsp0_eb.common.hw, [CLK_GSP1_EB] = &gsp1_eb.common.hw, [CLK_GSP0_MMU_EB] = &gsp0_mmu_eb.common.hw, [CLK_GSP1_MMU_EB] = &gsp1_mmu_eb.common.hw, [CLK_DSI0_EB] = &dsi0_eb.common.hw, [CLK_DSI1_EB] = &dsi1_eb.common.hw, [CLK_DISP_CKG_EB] = &disp_ckg_eb.common.hw, [CLK_DISP_GPU_EB] = &disp_gpu_eb.common.hw, [CLK_GPU_MTX_EB] = &gpu_mtx_eb.common.hw, [CLK_GSP_MTX_EB] = &gsp_mtx_eb.common.hw, [CLK_TMC_MTX_EB] = &tmc_mtx_eb.common.hw, [CLK_DISPC_MTX_EB] = &dispc_mtx_eb.common.hw, [CLK_DPHY0_GATE] = &dphy0_gate.common.hw, [CLK_DPHY1_GATE] = &dphy1_gate.common.hw, [CLK_GSP0_A_GATE] = &gsp0_a_gate.common.hw, [CLK_GSP1_A_GATE] = &gsp1_a_gate.common.hw, [CLK_GSP0_F_GATE] = &gsp0_f_gate.common.hw, [CLK_GSP1_F_GATE] = &gsp1_f_gate.common.hw, [CLK_D_MTX_F_GATE] = &d_mtx_f_gate.common.hw, [CLK_D_MTX_A_GATE] = &d_mtx_a_gate.common.hw, [CLK_D_NOC_F_GATE] = &d_noc_f_gate.common.hw, [CLK_D_NOC_A_GATE] = &d_noc_a_gate.common.hw, [CLK_GSP_MTX_F_GATE] = &gsp_mtx_f_gate.common.hw, [CLK_GSP_MTX_A_GATE] = &gsp_mtx_a_gate.common.hw, [CLK_GSP_NOC_F_GATE] = &gsp_noc_f_gate.common.hw, [CLK_GSP_NOC_A_GATE] = &gsp_noc_a_gate.common.hw, [CLK_DISPM0IDLE_GATE] = &dispm0idle_gate.common.hw, [CLK_GSPM0IDLE_GATE] = &gspm0idle_gate.common.hw, }, .num = CLK_DISP_GATE_NUM, }; static const struct sprd_clk_desc sc9860_disp_gate_desc = { .clk_clks = sc9860_disp_gate, .num_clk_clks = ARRAY_SIZE(sc9860_disp_gate), .hw_clks = &sc9860_disp_gate_hws, }; static SPRD_SC_GATE_CLK(sim0_eb, "sim0-eb", "ap-apb", 0x0, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(iis0_eb, "iis0-eb", "ap-apb", 0x0, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(iis1_eb, "iis1-eb", "ap-apb", 0x0, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(iis2_eb, "iis2-eb", "ap-apb", 0x0, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(iis3_eb, "iis3-eb", "ap-apb", 0x0, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(spi0_eb, "spi0-eb", "ap-apb", 0x0, 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(spi1_eb, "spi1-eb", "ap-apb", 0x0, 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(spi2_eb, "spi2-eb", "ap-apb", 0x0, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(i2c0_eb, "i2c0-eb", "ap-apb", 0x0, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(i2c1_eb, "i2c1-eb", "ap-apb", 0x0, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(i2c2_eb, "i2c2-eb", "ap-apb", 0x0, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(i2c3_eb, "i2c3-eb", "ap-apb", 0x0, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(i2c4_eb, "i2c4-eb", "ap-apb", 0x0, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(i2c5_eb, "i2c5-eb", "ap-apb", 0x0, 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(uart0_eb, "uart0-eb", "ap-apb", 0x0, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(uart1_eb, "uart1-eb", "ap-apb", 0x0, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(uart2_eb, "uart2-eb", "ap-apb", 0x0, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(uart3_eb, "uart3-eb", "ap-apb", 0x0, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(uart4_eb, "uart4-eb", "ap-apb", 0x0, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(ap_ckg_eb, "ap-ckg-eb", "ap-apb", 0x0, 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK(spi3_eb, "spi3-eb", "ap-apb", 0x0, 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); static struct sprd_clk_common *sc9860_apapb_gate[] = { /* address base is 0x70b00000 */ &sim0_eb.common, &iis0_eb.common, &iis1_eb.common, &iis2_eb.common, &iis3_eb.common, &spi0_eb.common, &spi1_eb.common, &spi2_eb.common, &i2c0_eb.common, &i2c1_eb.common, &i2c2_eb.common, &i2c3_eb.common, &i2c4_eb.common, &i2c5_eb.common, &uart0_eb.common, &uart1_eb.common, &uart2_eb.common, &uart3_eb.common, &uart4_eb.common, &ap_ckg_eb.common, &spi3_eb.common, }; static struct clk_hw_onecell_data sc9860_apapb_gate_hws = { .hws = { [CLK_SIM0_EB] = &sim0_eb.common.hw, [CLK_IIS0_EB] = &iis0_eb.common.hw, [CLK_IIS1_EB] = &iis1_eb.common.hw, [CLK_IIS2_EB] = &iis2_eb.common.hw, [CLK_IIS3_EB] = &iis3_eb.common.hw, [CLK_SPI0_EB] = &spi0_eb.common.hw, [CLK_SPI1_EB] = &spi1_eb.common.hw, [CLK_SPI2_EB] = &spi2_eb.common.hw, [CLK_I2C0_EB] = &i2c0_eb.common.hw, [CLK_I2C1_EB] = &i2c1_eb.common.hw, [CLK_I2C2_EB] = &i2c2_eb.common.hw, [CLK_I2C3_EB] = &i2c3_eb.common.hw, [CLK_I2C4_EB] = &i2c4_eb.common.hw, [CLK_I2C5_EB] = &i2c5_eb.common.hw, [CLK_UART0_EB] = &uart0_eb.common.hw, [CLK_UART1_EB] = &uart1_eb.common.hw, [CLK_UART2_EB] = &uart2_eb.common.hw, [CLK_UART3_EB] = &uart3_eb.common.hw, [CLK_UART4_EB] = &uart4_eb.common.hw, [CLK_AP_CKG_EB] = &ap_ckg_eb.common.hw, [CLK_SPI3_EB] = &spi3_eb.common.hw, }, .num = CLK_APAPB_GATE_NUM, }; static const struct sprd_clk_desc sc9860_apapb_gate_desc = { .clk_clks = sc9860_apapb_gate, .num_clk_clks = ARRAY_SIZE(sc9860_apapb_gate), .hw_clks = &sc9860_apapb_gate_hws, }; static const struct of_device_id sprd_sc9860_clk_ids[] = { { .compatible = "sprd,sc9860-pmu-gate", /* 0x402b */ .data = &sc9860_pmu_gate_desc }, { .compatible = "sprd,sc9860-pll", /* 0x4040 */ .data = &sc9860_pll_desc }, { .compatible = "sprd,sc9860-ap-clk", /* 0x2000 */ .data = &sc9860_ap_clk_desc }, { .compatible = "sprd,sc9860-aon-prediv", /* 0x402d */ .data = &sc9860_aon_prediv_desc }, { .compatible = "sprd,sc9860-apahb-gate", /* 0x2021 */ .data = &sc9860_apahb_gate_desc }, { .compatible = "sprd,sc9860-aon-gate", /* 0x402e */ .data = &sc9860_aon_gate_desc }, { .compatible = "sprd,sc9860-aonsecure-clk", /* 0x4088 */ .data = &sc9860_aonsecure_clk_desc }, { .compatible = "sprd,sc9860-agcp-gate", /* 0x415e */ .data = &sc9860_agcp_gate_desc }, { .compatible = "sprd,sc9860-gpu-clk", /* 0x6020 */ .data = &sc9860_gpu_clk_desc }, { .compatible = "sprd,sc9860-vsp-clk", /* 0x6100 */ .data = &sc9860_vsp_clk_desc }, { .compatible = "sprd,sc9860-vsp-gate", /* 0x6110 */ .data = &sc9860_vsp_gate_desc }, { .compatible = "sprd,sc9860-cam-clk", /* 0x6200 */ .data = &sc9860_cam_clk_desc }, { .compatible = "sprd,sc9860-cam-gate", /* 0x6210 */ .data = &sc9860_cam_gate_desc }, { .compatible = "sprd,sc9860-disp-clk", /* 0x6300 */ .data = &sc9860_disp_clk_desc }, { .compatible = "sprd,sc9860-disp-gate", /* 0x6310 */ .data = &sc9860_disp_gate_desc }, { .compatible = "sprd,sc9860-apapb-gate", /* 0x70b0 */ .data = &sc9860_apapb_gate_desc }, { } }; MODULE_DEVICE_TABLE(of, sprd_sc9860_clk_ids); static int sc9860_clk_probe(struct platform_device *pdev) { const struct of_device_id *match; const struct sprd_clk_desc *desc; int ret; match = of_match_node(sprd_sc9860_clk_ids, pdev->dev.of_node); if (!match) { pr_err("%s: of_match_node() failed", __func__); return -ENODEV; } desc = match->data; ret = sprd_clk_regmap_init(pdev, desc); if (ret) return ret; return sprd_clk_probe(&pdev->dev, desc->hw_clks); } static struct platform_driver sc9860_clk_driver = { .probe = sc9860_clk_probe, .driver = { .name = "sc9860-clk", .of_match_table = sprd_sc9860_clk_ids, }, }; module_platform_driver(sc9860_clk_driver); MODULE_DESCRIPTION("Spreadtrum SC9860 Clock Driver"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:sc9860-clk");
linux-master
drivers/clk/sprd/sc9860-clk.c
// SPDX-License-Identifier: GPL-2.0 // // Spreadtrum composite clock driver // // Copyright (C) 2017 Spreadtrum, Inc. // Author: Chunyan Zhang <[email protected]> #include <linux/clk-provider.h> #include "composite.h" static int sprd_comp_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct sprd_comp *cc = hw_to_sprd_comp(hw); return divider_determine_rate(hw, req, NULL, cc->div.width, 0); } static unsigned long sprd_comp_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct sprd_comp *cc = hw_to_sprd_comp(hw); return sprd_div_helper_recalc_rate(&cc->common, &cc->div, parent_rate); } static int sprd_comp_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct sprd_comp *cc = hw_to_sprd_comp(hw); return sprd_div_helper_set_rate(&cc->common, &cc->div, rate, parent_rate); } static u8 sprd_comp_get_parent(struct clk_hw *hw) { struct sprd_comp *cc = hw_to_sprd_comp(hw); return sprd_mux_helper_get_parent(&cc->common, &cc->mux); } static int sprd_comp_set_parent(struct clk_hw *hw, u8 index) { struct sprd_comp *cc = hw_to_sprd_comp(hw); return sprd_mux_helper_set_parent(&cc->common, &cc->mux, index); } const struct clk_ops sprd_comp_ops = { .get_parent = sprd_comp_get_parent, .set_parent = sprd_comp_set_parent, .determine_rate = sprd_comp_determine_rate, .recalc_rate = sprd_comp_recalc_rate, .set_rate = sprd_comp_set_rate, }; EXPORT_SYMBOL_GPL(sprd_comp_ops);
linux-master
drivers/clk/sprd/composite.c
// SPDX-License-Identifier: GPL-2.0 // // Spreadtrum multiplexer clock driver // // Copyright (C) 2017 Spreadtrum, Inc. // Author: Chunyan Zhang <[email protected]> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include "mux.h" u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common, const struct sprd_mux_ssel *mux) { unsigned int reg; u8 parent; int num_parents; int i; regmap_read(common->regmap, common->reg, &reg); parent = reg >> mux->shift; parent &= (1 << mux->width) - 1; if (!mux->table) return parent; num_parents = clk_hw_get_num_parents(&common->hw); for (i = 0; i < num_parents - 1; i++) if (parent >= mux->table[i] && parent < mux->table[i + 1]) return i; return num_parents - 1; } EXPORT_SYMBOL_GPL(sprd_mux_helper_get_parent); static u8 sprd_mux_get_parent(struct clk_hw *hw) { struct sprd_mux *cm = hw_to_sprd_mux(hw); return sprd_mux_helper_get_parent(&cm->common, &cm->mux); } int sprd_mux_helper_set_parent(const struct sprd_clk_common *common, const struct sprd_mux_ssel *mux, u8 index) { unsigned int reg; if (mux->table) index = mux->table[index]; regmap_read(common->regmap, common->reg, &reg); reg &= ~GENMASK(mux->width + mux->shift - 1, mux->shift); regmap_write(common->regmap, common->reg, reg | (index << mux->shift)); return 0; } EXPORT_SYMBOL_GPL(sprd_mux_helper_set_parent); static int sprd_mux_set_parent(struct clk_hw *hw, u8 index) { struct sprd_mux *cm = hw_to_sprd_mux(hw); return sprd_mux_helper_set_parent(&cm->common, &cm->mux, index); } const struct clk_ops sprd_mux_ops = { .get_parent = sprd_mux_get_parent, .set_parent = sprd_mux_set_parent, .determine_rate = __clk_mux_determine_rate, }; EXPORT_SYMBOL_GPL(sprd_mux_ops);
linux-master
drivers/clk/sprd/mux.c
// SPDX-License-Identifier: GPL-2.0-only /* * Unisoc SC9863A clock driver * * Copyright (C) 2019 Unisoc, Inc. * Author: Chunyan Zhang <[email protected]> */ #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/io.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <dt-bindings/clock/sprd,sc9863a-clk.h> #include "common.h" #include "composite.h" #include "div.h" #include "gate.h" #include "mux.h" #include "pll.h" /* mpll*_gate clocks control cpu cores, they were enabled by default */ static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98, 0x1000, BIT(0), 0, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c, 0x1000, BIT(0), 0, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8, 0x1000, BIT(0), 0, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc, 0x1000, BIT(0), 0, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); static SPRD_PLL_SC_GATE_CLK_FW_NAME(isppll_gate, "isppll-gate", "ext-26m", 0x1e8, 0x1000, BIT(0), 0, 0, 240); static struct sprd_clk_common *sc9863a_pmu_gate_clks[] = { /* address base is 0x402b0000 */ &mpll0_gate.common, &dpll0_gate.common, &lpll_gate.common, &gpll_gate.common, &dpll1_gate.common, &mpll1_gate.common, &mpll2_gate.common, &isppll_gate.common, }; static struct clk_hw_onecell_data sc9863a_pmu_gate_hws = { .hws = { [CLK_MPLL0_GATE] = &mpll0_gate.common.hw, [CLK_DPLL0_GATE] = &dpll0_gate.common.hw, [CLK_LPLL_GATE] = &lpll_gate.common.hw, [CLK_GPLL_GATE] = &gpll_gate.common.hw, [CLK_DPLL1_GATE] = &dpll1_gate.common.hw, [CLK_MPLL1_GATE] = &mpll1_gate.common.hw, [CLK_MPLL2_GATE] = &mpll2_gate.common.hw, [CLK_ISPPLL_GATE] = &isppll_gate.common.hw, }, .num = CLK_PMU_APB_NUM, }; static const struct sprd_clk_desc sc9863a_pmu_gate_desc = { .clk_clks = sc9863a_pmu_gate_clks, .num_clk_clks = ARRAY_SIZE(sc9863a_pmu_gate_clks), .hw_clks = &sc9863a_pmu_gate_hws, }; static const u64 itable[5] = {4, 1000000000, 1200000000, 1400000000, 1600000000}; static const struct clk_bit_field f_twpll[PLL_FACT_MAX] = { { .shift = 95, .width = 1 }, /* lock_done */ { .shift = 0, .width = 1 }, /* div_s */ { .shift = 1, .width = 1 }, /* mod_en */ { .shift = 2, .width = 1 }, /* sdm_en */ { .shift = 0, .width = 0 }, /* refin */ { .shift = 3, .width = 3 }, /* ibias */ { .shift = 8, .width = 11 }, /* n */ { .shift = 55, .width = 7 }, /* nint */ { .shift = 32, .width = 23}, /* kint */ { .shift = 0, .width = 0 }, /* prediv */ { .shift = 0, .width = 0 }, /* postdiv */ }; static SPRD_PLL_FW_NAME(twpll, "twpll", "ext-26m", 0x4, 3, itable, f_twpll, 240, 1000, 1000, 0, 0); static CLK_FIXED_FACTOR_HW(twpll_768m, "twpll-768m", &twpll.common.hw, 2, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_384m, "twpll-384m", &twpll.common.hw, 4, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_192m, "twpll-192m", &twpll.common.hw, 8, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_96m, "twpll-96m", &twpll.common.hw, 16, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_48m, "twpll-48m", &twpll.common.hw, 32, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_24m, "twpll-24m", &twpll.common.hw, 64, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_12m, "twpll-12m", &twpll.common.hw, 128, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_512m, "twpll-512m", &twpll.common.hw, 3, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_256m, "twpll-256m", &twpll.common.hw, 6, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_128m, "twpll-128m", &twpll.common.hw, 12, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_64m, "twpll-64m", &twpll.common.hw, 24, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_307m2, "twpll-307m2", &twpll.common.hw, 5, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_219m4, "twpll-219m4", &twpll.common.hw, 7, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_170m6, "twpll-170m6", &twpll.common.hw, 9, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_153m6, "twpll-153m6", &twpll.common.hw, 10, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_76m8, "twpll-76m8", &twpll.common.hw, 20, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_51m2, "twpll-51m2", &twpll.common.hw, 30, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_38m4, "twpll-38m4", &twpll.common.hw, 40, 1, 0); static CLK_FIXED_FACTOR_HW(twpll_19m2, "twpll-19m2", &twpll.common.hw, 80, 1, 0); static const struct clk_bit_field f_lpll[PLL_FACT_MAX] = { { .shift = 95, .width = 1 }, /* lock_done */ { .shift = 0, .width = 1 }, /* div_s */ { .shift = 1, .width = 1 }, /* mod_en */ { .shift = 2, .width = 1 }, /* sdm_en */ { .shift = 0, .width = 0 }, /* refin */ { .shift = 6, .width = 2 }, /* ibias */ { .shift = 8, .width = 11 }, /* n */ { .shift = 55, .width = 7 }, /* nint */ { .shift = 32, .width = 23}, /* kint */ { .shift = 0, .width = 0 }, /* prediv */ { .shift = 0, .width = 0 }, /* postdiv */ }; static SPRD_PLL_HW(lpll, "lpll", &lpll_gate.common.hw, 0x20, 3, itable, f_lpll, 240, 1000, 1000, 0, 0); static CLK_FIXED_FACTOR_HW(lpll_409m6, "lpll-409m6", &lpll.common.hw, 3, 1, 0); static CLK_FIXED_FACTOR_HW(lpll_245m76, "lpll-245m76", &lpll.common.hw, 5, 1, 0); static const struct clk_bit_field f_gpll[PLL_FACT_MAX] = { { .shift = 95, .width = 1 }, /* lock_done */ { .shift = 0, .width = 1 }, /* div_s */ { .shift = 1, .width = 1 }, /* mod_en */ { .shift = 2, .width = 1 }, /* sdm_en */ { .shift = 0, .width = 0 }, /* refin */ { .shift = 6, .width = 2 }, /* ibias */ { .shift = 8, .width = 11 }, /* n */ { .shift = 55, .width = 7 }, /* nint */ { .shift = 32, .width = 23}, /* kint */ { .shift = 0, .width = 0 }, /* prediv */ { .shift = 80, .width = 1 }, /* postdiv */ }; static SPRD_PLL_HW(gpll, "gpll", &gpll_gate.common.hw, 0x38, 3, itable, f_gpll, 240, 1000, 1000, 1, 400000000); static SPRD_PLL_HW(isppll, "isppll", &isppll_gate.common.hw, 0x50, 3, itable, f_gpll, 240, 1000, 1000, 0, 0); static CLK_FIXED_FACTOR_HW(isppll_468m, "isppll-468m", &isppll.common.hw, 2, 1, 0); static struct sprd_clk_common *sc9863a_pll_clks[] = { /* address base is 0x40353000 */ &twpll.common, &lpll.common, &gpll.common, &isppll.common, }; static struct clk_hw_onecell_data sc9863a_pll_hws = { .hws = { [CLK_TWPLL] = &twpll.common.hw, [CLK_TWPLL_768M] = &twpll_768m.hw, [CLK_TWPLL_384M] = &twpll_384m.hw, [CLK_TWPLL_192M] = &twpll_192m.hw, [CLK_TWPLL_96M] = &twpll_96m.hw, [CLK_TWPLL_48M] = &twpll_48m.hw, [CLK_TWPLL_24M] = &twpll_24m.hw, [CLK_TWPLL_12M] = &twpll_12m.hw, [CLK_TWPLL_512M] = &twpll_512m.hw, [CLK_TWPLL_256M] = &twpll_256m.hw, [CLK_TWPLL_128M] = &twpll_128m.hw, [CLK_TWPLL_64M] = &twpll_64m.hw, [CLK_TWPLL_307M2] = &twpll_307m2.hw, [CLK_TWPLL_219M4] = &twpll_219m4.hw, [CLK_TWPLL_170M6] = &twpll_170m6.hw, [CLK_TWPLL_153M6] = &twpll_153m6.hw, [CLK_TWPLL_76M8] = &twpll_76m8.hw, [CLK_TWPLL_51M2] = &twpll_51m2.hw, [CLK_TWPLL_38M4] = &twpll_38m4.hw, [CLK_TWPLL_19M2] = &twpll_19m2.hw, [CLK_LPLL] = &lpll.common.hw, [CLK_LPLL_409M6] = &lpll_409m6.hw, [CLK_LPLL_245M76] = &lpll_245m76.hw, [CLK_GPLL] = &gpll.common.hw, [CLK_ISPPLL] = &isppll.common.hw, [CLK_ISPPLL_468M] = &isppll_468m.hw, }, .num = CLK_ANLG_PHY_G1_NUM, }; static const struct sprd_clk_desc sc9863a_pll_desc = { .clk_clks = sc9863a_pll_clks, .num_clk_clks = ARRAY_SIZE(sc9863a_pll_clks), .hw_clks = &sc9863a_pll_hws, }; static const u64 itable_mpll[6] = {5, 1000000000, 1200000000, 1400000000, 1600000000, 1800000000}; static SPRD_PLL_HW(mpll0, "mpll0", &mpll0_gate.common.hw, 0x0, 3, itable_mpll, f_gpll, 240, 1000, 1000, 1, 1000000000); static SPRD_PLL_HW(mpll1, "mpll1", &mpll1_gate.common.hw, 0x18, 3, itable_mpll, f_gpll, 240, 1000, 1000, 1, 1000000000); static SPRD_PLL_HW(mpll2, "mpll2", &mpll2_gate.common.hw, 0x30, 3, itable_mpll, f_gpll, 240, 1000, 1000, 1, 1000000000); static CLK_FIXED_FACTOR_HW(mpll2_675m, "mpll2-675m", &mpll2.common.hw, 2, 1, 0); static struct sprd_clk_common *sc9863a_mpll_clks[] = { /* address base is 0x40359000 */ &mpll0.common, &mpll1.common, &mpll2.common, }; static struct clk_hw_onecell_data sc9863a_mpll_hws = { .hws = { [CLK_MPLL0] = &mpll0.common.hw, [CLK_MPLL1] = &mpll1.common.hw, [CLK_MPLL2] = &mpll2.common.hw, [CLK_MPLL2_675M] = &mpll2_675m.hw, }, .num = CLK_ANLG_PHY_G4_NUM, }; static const struct sprd_clk_desc sc9863a_mpll_desc = { .clk_clks = sc9863a_mpll_clks, .num_clk_clks = ARRAY_SIZE(sc9863a_mpll_clks), .hw_clks = &sc9863a_mpll_hws, }; static SPRD_SC_GATE_CLK_FW_NAME(audio_gate, "audio-gate", "ext-26m", 0x4, 0x1000, BIT(8), 0, 0); static SPRD_PLL_FW_NAME(rpll, "rpll", "ext-26m", 0x10, 3, itable, f_lpll, 240, 1000, 1000, 0, 0); static CLK_FIXED_FACTOR_HW(rpll_390m, "rpll-390m", &rpll.common.hw, 2, 1, 0); static CLK_FIXED_FACTOR_HW(rpll_260m, "rpll-260m", &rpll.common.hw, 3, 1, 0); static CLK_FIXED_FACTOR_HW(rpll_195m, "rpll-195m", &rpll.common.hw, 4, 1, 0); static CLK_FIXED_FACTOR_HW(rpll_26m, "rpll-26m", &rpll.common.hw, 30, 1, 0); static struct sprd_clk_common *sc9863a_rpll_clks[] = { /* address base is 0x4035c000 */ &audio_gate.common, &rpll.common, }; static struct clk_hw_onecell_data sc9863a_rpll_hws = { .hws = { [CLK_AUDIO_GATE] = &audio_gate.common.hw, [CLK_RPLL] = &rpll.common.hw, [CLK_RPLL_390M] = &rpll_390m.hw, [CLK_RPLL_260M] = &rpll_260m.hw, [CLK_RPLL_195M] = &rpll_195m.hw, [CLK_RPLL_26M] = &rpll_26m.hw, }, .num = CLK_ANLG_PHY_G5_NUM, }; static const struct sprd_clk_desc sc9863a_rpll_desc = { .clk_clks = sc9863a_rpll_clks, .num_clk_clks = ARRAY_SIZE(sc9863a_rpll_clks), .hw_clks = &sc9863a_rpll_hws, }; static const u64 itable_dpll[5] = {4, 1211000000, 1320000000, 1570000000, 1866000000}; static SPRD_PLL_HW(dpll0, "dpll0", &dpll0_gate.common.hw, 0x0, 3, itable_dpll, f_lpll, 240, 1000, 1000, 0, 0); static SPRD_PLL_HW(dpll1, "dpll1", &dpll1_gate.common.hw, 0x18, 3, itable_dpll, f_lpll, 240, 1000, 1000, 0, 0); static CLK_FIXED_FACTOR_HW(dpll0_933m, "dpll0-933m", &dpll0.common.hw, 2, 1, 0); static CLK_FIXED_FACTOR_HW(dpll0_622m3, "dpll0-622m3", &dpll0.common.hw, 3, 1, 0); static CLK_FIXED_FACTOR_HW(dpll1_400m, "dpll1-400m", &dpll0.common.hw, 4, 1, 0); static CLK_FIXED_FACTOR_HW(dpll1_266m7, "dpll1-266m7", &dpll0.common.hw, 6, 1, 0); static CLK_FIXED_FACTOR_HW(dpll1_123m1, "dpll1-123m1", &dpll0.common.hw, 13, 1, 0); static CLK_FIXED_FACTOR_HW(dpll1_50m, "dpll1-50m", &dpll0.common.hw, 32, 1, 0); static struct sprd_clk_common *sc9863a_dpll_clks[] = { /* address base is 0x40363000 */ &dpll0.common, &dpll1.common, }; static struct clk_hw_onecell_data sc9863a_dpll_hws = { .hws = { [CLK_DPLL0] = &dpll0.common.hw, [CLK_DPLL1] = &dpll1.common.hw, [CLK_DPLL0_933M] = &dpll0_933m.hw, [CLK_DPLL0_622M3] = &dpll0_622m3.hw, [CLK_DPLL0_400M] = &dpll1_400m.hw, [CLK_DPLL0_266M7] = &dpll1_266m7.hw, [CLK_DPLL0_123M1] = &dpll1_123m1.hw, [CLK_DPLL0_50M] = &dpll1_50m.hw, }, .num = CLK_ANLG_PHY_G7_NUM, }; static const struct sprd_clk_desc sc9863a_dpll_desc = { .clk_clks = sc9863a_dpll_clks, .num_clk_clks = ARRAY_SIZE(sc9863a_dpll_clks), .hw_clks = &sc9863a_dpll_hws, }; static CLK_FIXED_FACTOR_FW_NAME(clk_6m5, "clk-6m5", "ext-26m", 4, 1, 0); static CLK_FIXED_FACTOR_FW_NAME(clk_4m3, "clk-4m3", "ext-26m", 6, 1, 0); static CLK_FIXED_FACTOR_FW_NAME(clk_2m, "clk-2m", "ext-26m", 13, 1, 0); static CLK_FIXED_FACTOR_FW_NAME(clk_250k, "clk-250k", "ext-26m", 104, 1, 0); static CLK_FIXED_FACTOR_FW_NAME(rco_25m, "rco-25m", "rco-100m", 4, 1, 0); static CLK_FIXED_FACTOR_FW_NAME(rco_4m, "rco-4m", "rco-100m", 25, 1, 0); static CLK_FIXED_FACTOR_FW_NAME(rco_2m, "rco-2m", "rco-100m", 50, 1, 0); #define SC9863A_MUX_FLAG \ (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT) static CLK_FIXED_FACTOR_FW_NAME(clk_13m, "clk-13m", "ext-26m", 2, 1, 0); static const struct clk_parent_data emc_clk_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_384m.hw }, { .hw = &twpll_512m.hw }, { .hw = &twpll_768m.hw }, { .hw = &twpll.common.hw }, }; static SPRD_MUX_CLK_DATA(emc_clk, "emc-clk", emc_clk_parents, 0x220, 0, 3, SC9863A_MUX_FLAG); static const struct clk_parent_data aon_apb_parents[] = { { .hw = &rco_4m.hw }, { .hw = &rco_25m.hw }, { .fw_name = "ext-26m" }, { .hw = &twpll_96m.hw }, { .fw_name = "rco-100m" }, { .hw = &twpll_128m.hw }, }; static SPRD_COMP_CLK_DATA(aon_apb, "aon-apb", aon_apb_parents, 0x224, 0, 3, 8, 2, 0); static const struct clk_parent_data adi_parents[] = { { .hw = &rco_4m.hw }, { .hw = &rco_25m.hw }, { .fw_name = "ext-26m" }, { .hw = &twpll_38m4.hw }, { .hw = &twpll_51m2.hw }, }; static SPRD_MUX_CLK_DATA(adi_clk, "adi-clk", adi_parents, 0x228, 0, 3, SC9863A_MUX_FLAG); static const struct clk_parent_data aux_parents[] = { { .fw_name = "ext-32k" }, { .hw = &rpll_26m.hw }, { .fw_name = "ext-26m" }, }; static SPRD_COMP_CLK_DATA(aux0_clk, "aux0-clk", aux_parents, 0x22c, 0, 5, 8, 4, 0); static SPRD_COMP_CLK_DATA(aux1_clk, "aux1-clk", aux_parents, 0x230, 0, 5, 8, 4, 0); static SPRD_COMP_CLK_DATA(aux2_clk, "aux2-clk", aux_parents, 0x234, 0, 5, 8, 4, 0); static SPRD_COMP_CLK_DATA(probe_clk, "probe-clk", aux_parents, 0x238, 0, 5, 8, 4, 0); static const struct clk_parent_data pwm_parents[] = { { .fw_name = "ext-32k" }, { .hw = &rpll_26m.hw }, { .fw_name = "ext-26m" }, { .hw = &twpll_48m.hw }, }; static SPRD_MUX_CLK_DATA(pwm0_clk, "pwm0-clk", pwm_parents, 0x23c, 0, 2, SC9863A_MUX_FLAG); static SPRD_MUX_CLK_DATA(pwm1_clk, "pwm1-clk", pwm_parents, 0x240, 0, 2, SC9863A_MUX_FLAG); static SPRD_MUX_CLK_DATA(pwm2_clk, "pwm2-clk", pwm_parents, 0x244, 0, 2, SC9863A_MUX_FLAG); static const struct clk_parent_data aon_thm_parents[] = { { .fw_name = "ext-32k" }, { .hw = &clk_250k.hw }, }; static SPRD_MUX_CLK_DATA(aon_thm_clk, "aon-thm-clk", aon_thm_parents, 0x25c, 0, 1, SC9863A_MUX_FLAG); static const struct clk_parent_data audif_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_38m4.hw }, { .hw = &twpll_51m2.hw }, }; static SPRD_MUX_CLK_DATA(audif_clk, "audif-clk", audif_parents, 0x264, 0, 2, SC9863A_MUX_FLAG); static const struct clk_parent_data cpu_dap_parents[] = { { .hw = &rco_4m.hw }, { .hw = &rco_25m.hw }, { .fw_name = "ext-26m" }, { .hw = &twpll_76m8.hw }, { .fw_name = "rco-100m" }, { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, }; static SPRD_MUX_CLK_DATA(cpu_dap_clk, "cpu-dap-clk", cpu_dap_parents, 0x26c, 0, 3, SC9863A_MUX_FLAG); static const struct clk_parent_data cpu_ts_parents[] = { { .fw_name = "ext-32k" }, { .fw_name = "ext-26m" }, { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, }; static SPRD_MUX_CLK_DATA(cpu_ts_clk, "cpu-ts-clk", cpu_ts_parents, 0x274, 0, 2, SC9863A_MUX_FLAG); static const struct clk_parent_data djtag_tck_parents[] = { { .hw = &rco_4m.hw }, { .fw_name = "ext-26m" }, }; static SPRD_MUX_CLK_DATA(djtag_tck_clk, "djtag-tck-clk", djtag_tck_parents, 0x28c, 0, 1, SC9863A_MUX_FLAG); static const struct clk_parent_data emc_ref_parents[] = { { .hw = &clk_6m5.hw }, { .hw = &clk_13m.hw }, { .fw_name = "ext-26m" }, }; static SPRD_MUX_CLK_DATA(emc_ref_clk, "emc-ref-clk", emc_ref_parents, 0x29c, 0, 2, SC9863A_MUX_FLAG); static const struct clk_parent_data cssys_parents[] = { { .hw = &rco_4m.hw }, { .fw_name = "ext-26m" }, { .hw = &twpll_96m.hw }, { .fw_name = "rco-100m" }, { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, { .hw = &twpll_384m.hw }, { .hw = &twpll_512m.hw }, { .hw = &mpll2_675m.hw }, }; static SPRD_COMP_CLK_DATA(cssys_clk, "cssys-clk", cssys_parents, 0x2a0, 0, 4, 8, 2, 0); static const struct clk_parent_data aon_pmu_parents[] = { { .fw_name = "ext-32k" }, { .hw = &rco_4m.hw }, { .fw_name = "ext-4m" }, }; static SPRD_MUX_CLK_DATA(aon_pmu_clk, "aon-pmu-clk", aon_pmu_parents, 0x2a8, 0, 2, SC9863A_MUX_FLAG); static const struct clk_parent_data pmu_26m_parents[] = { { .hw = &rco_4m.hw }, { .hw = &rco_25m.hw }, { .fw_name = "ext-26m" }, }; static SPRD_MUX_CLK_DATA(pmu_26m_clk, "26m-pmu-clk", pmu_26m_parents, 0x2ac, 0, 2, SC9863A_MUX_FLAG); static const struct clk_parent_data aon_tmr_parents[] = { { .hw = &rco_4m.hw }, { .fw_name = "ext-26m" }, }; static SPRD_MUX_CLK_DATA(aon_tmr_clk, "aon-tmr-clk", aon_tmr_parents, 0x2b0, 0, 1, SC9863A_MUX_FLAG); static const struct clk_parent_data power_cpu_parents[] = { { .fw_name = "ext-26m" }, { .hw = &rco_25m.hw }, { .fw_name = "rco-100m" }, { .hw = &twpll_128m.hw }, }; static SPRD_MUX_CLK_DATA(power_cpu_clk, "power-cpu-clk", power_cpu_parents, 0x2c4, 0, 2, SC9863A_MUX_FLAG); static const struct clk_parent_data ap_axi_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_76m8.hw }, { .hw = &twpll_128m.hw }, { .hw = &twpll_256m.hw }, }; static SPRD_MUX_CLK_DATA(ap_axi, "ap-axi", ap_axi_parents, 0x2c8, 0, 2, SC9863A_MUX_FLAG); static const struct clk_parent_data sdio_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, { .hw = &rpll_390m.hw }, { .hw = &dpll1_400m.hw }, { .hw = &lpll_409m6.hw }, }; static SPRD_MUX_CLK_DATA(sdio0_2x, "sdio0-2x", sdio_parents, 0x2cc, 0, 3, SC9863A_MUX_FLAG); static SPRD_MUX_CLK_DATA(sdio1_2x, "sdio1-2x", sdio_parents, 0x2d4, 0, 3, SC9863A_MUX_FLAG); static SPRD_MUX_CLK_DATA(sdio2_2x, "sdio2-2x", sdio_parents, 0x2dc, 0, 3, SC9863A_MUX_FLAG); static SPRD_MUX_CLK_DATA(emmc_2x, "emmc-2x", sdio_parents, 0x2e4, 0, 3, SC9863A_MUX_FLAG); static const struct clk_parent_data dpu_parents[] = { { .hw = &twpll_153m6.hw }, { .hw = &twpll_192m.hw }, { .hw = &twpll_256m.hw }, { .hw = &twpll_384m.hw }, }; static SPRD_MUX_CLK_DATA(dpu_clk, "dpu", dpu_parents, 0x2f4, 0, 2, SC9863A_MUX_FLAG); static const struct clk_parent_data dpu_dpi_parents[] = { { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, { .hw = &twpll_192m.hw }, }; static SPRD_COMP_CLK_DATA(dpu_dpi, "dpu-dpi", dpu_dpi_parents, 0x2f8, 0, 2, 8, 4, 0); static const struct clk_parent_data otg_ref_parents[] = { { .hw = &twpll_12m.hw }, { .fw_name = "ext-26m" }, }; static SPRD_MUX_CLK_DATA(otg_ref_clk, "otg-ref-clk", otg_ref_parents, 0x308, 0, 1, SC9863A_MUX_FLAG); static const struct clk_parent_data sdphy_apb_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_48m.hw }, }; static SPRD_MUX_CLK_DATA(sdphy_apb_clk, "sdphy-apb-clk", sdphy_apb_parents, 0x330, 0, 1, SC9863A_MUX_FLAG); static const struct clk_parent_data alg_io_apb_parents[] = { { .hw = &rco_4m.hw }, { .fw_name = "ext-26m" }, { .hw = &twpll_48m.hw }, { .hw = &twpll_96m.hw }, }; static SPRD_MUX_CLK_DATA(alg_io_apb_clk, "alg-io-apb-clk", alg_io_apb_parents, 0x33c, 0, 1, SC9863A_MUX_FLAG); static const struct clk_parent_data gpu_parents[] = { { .hw = &twpll_153m6.hw }, { .hw = &twpll_192m.hw }, { .hw = &twpll_256m.hw }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, { .hw = &twpll_512m.hw }, { .hw = &gpll.common.hw }, }; static SPRD_COMP_CLK_DATA(gpu_core, "gpu-core", gpu_parents, 0x344, 0, 3, 8, 2, 0); static SPRD_COMP_CLK_DATA(gpu_soc, "gpu-soc", gpu_parents, 0x348, 0, 3, 8, 2, 0); static const struct clk_parent_data mm_emc_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_384m.hw }, { .hw = &isppll_468m.hw }, { .hw = &twpll_512m.hw }, }; static SPRD_MUX_CLK_DATA(mm_emc, "mm-emc", mm_emc_parents, 0x350, 0, 2, SC9863A_MUX_FLAG); static const struct clk_parent_data mm_ahb_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_96m.hw }, { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, }; static SPRD_MUX_CLK_DATA(mm_ahb, "mm-ahb", mm_ahb_parents, 0x354, 0, 2, SC9863A_MUX_FLAG); static const struct clk_parent_data bpc_clk_parents[] = { { .hw = &twpll_192m.hw }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, { .hw = &isppll_468m.hw }, { .hw = &dpll0_622m3.hw }, }; static SPRD_MUX_CLK_DATA(bpc_clk, "bpc-clk", bpc_clk_parents, 0x358, 0, 3, SC9863A_MUX_FLAG); static const struct clk_parent_data dcam_if_parents[] = { { .hw = &twpll_192m.hw }, { .hw = &twpll_256m.hw }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, }; static SPRD_MUX_CLK_DATA(dcam_if_clk, "dcam-if-clk", dcam_if_parents, 0x35c, 0, 2, SC9863A_MUX_FLAG); static const struct clk_parent_data isp_parents[] = { { .hw = &twpll_128m.hw }, { .hw = &twpll_256m.hw }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, { .hw = &isppll_468m.hw }, }; static SPRD_MUX_CLK_DATA(isp_clk, "isp-clk", isp_parents, 0x360, 0, 3, SC9863A_MUX_FLAG); static const struct clk_parent_data jpg_parents[] = { { .hw = &twpll_76m8.hw }, { .hw = &twpll_128m.hw }, { .hw = &twpll_256m.hw }, { .hw = &twpll_307m2.hw }, }; static SPRD_MUX_CLK_DATA(jpg_clk, "jpg-clk", jpg_parents, 0x364, 0, 2, SC9863A_MUX_FLAG); static SPRD_MUX_CLK_DATA(cpp_clk, "cpp-clk", jpg_parents, 0x368, 0, 2, SC9863A_MUX_FLAG); static const struct clk_parent_data sensor_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_48m.hw }, { .hw = &twpll_76m8.hw }, { .hw = &twpll_96m.hw }, }; static SPRD_COMP_CLK_DATA(sensor0_clk, "sensor0-clk", sensor_parents, 0x36c, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(sensor1_clk, "sensor1-clk", sensor_parents, 0x370, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(sensor2_clk, "sensor2-clk", sensor_parents, 0x374, 0, 2, 8, 3, 0); static const struct clk_parent_data mm_vemc_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, { .hw = &isppll_468m.hw }, }; static SPRD_MUX_CLK_DATA(mm_vemc, "mm-vemc", mm_vemc_parents, 0x378, 0, 2, SC9863A_MUX_FLAG); static SPRD_MUX_CLK_DATA(mm_vahb, "mm-vahb", mm_ahb_parents, 0x37c, 0, 2, SC9863A_MUX_FLAG); static const struct clk_parent_data vsp_parents[] = { { .hw = &twpll_76m8.hw }, { .hw = &twpll_128m.hw }, { .hw = &twpll_256m.hw }, { .hw = &twpll_307m2.hw }, { .hw = &twpll_384m.hw }, }; static SPRD_MUX_CLK_DATA(clk_vsp, "vsp-clk", vsp_parents, 0x380, 0, 3, SC9863A_MUX_FLAG); static const struct clk_parent_data core_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_512m.hw }, { .hw = &twpll_768m.hw }, { .hw = &lpll.common.hw }, { .hw = &dpll0.common.hw }, { .hw = &mpll2.common.hw }, { .hw = &mpll0.common.hw }, { .hw = &mpll1.common.hw }, }; static SPRD_COMP_CLK_DATA(core0_clk, "core0-clk", core_parents, 0xa20, 0, 3, 8, 3, 0); static SPRD_COMP_CLK_DATA(core1_clk, "core1-clk", core_parents, 0xa24, 0, 3, 8, 3, 0); static SPRD_COMP_CLK_DATA(core2_clk, "core2-clk", core_parents, 0xa28, 0, 3, 8, 3, 0); static SPRD_COMP_CLK_DATA(core3_clk, "core3-clk", core_parents, 0xa2c, 0, 3, 8, 3, 0); static SPRD_COMP_CLK_DATA(core4_clk, "core4-clk", core_parents, 0xa30, 0, 3, 8, 3, 0); static SPRD_COMP_CLK_DATA(core5_clk, "core5-clk", core_parents, 0xa34, 0, 3, 8, 3, 0); static SPRD_COMP_CLK_DATA(core6_clk, "core6-clk", core_parents, 0xa38, 0, 3, 8, 3, 0); static SPRD_COMP_CLK_DATA(core7_clk, "core7-clk", core_parents, 0xa3c, 0, 3, 8, 3, 0); static SPRD_COMP_CLK_DATA(scu_clk, "scu-clk", core_parents, 0xa40, 0, 3, 8, 3, 0); static SPRD_DIV_CLK_HW(ace_clk, "ace-clk", &scu_clk.common.hw, 0xa44, 8, 3, 0); static SPRD_DIV_CLK_HW(axi_periph_clk, "axi-periph-clk", &scu_clk.common.hw, 0xa48, 8, 3, 0); static SPRD_DIV_CLK_HW(axi_acp_clk, "axi-acp-clk", &scu_clk.common.hw, 0xa4c, 8, 3, 0); static const struct clk_parent_data atb_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_384m.hw }, { .hw = &twpll_512m.hw }, { .hw = &mpll2.common.hw }, }; static SPRD_COMP_CLK_DATA(atb_clk, "atb-clk", atb_parents, 0xa50, 0, 2, 8, 3, 0); static SPRD_DIV_CLK_HW(debug_apb_clk, "debug-apb-clk", &atb_clk.common.hw, 0xa54, 8, 3, 0); static const struct clk_parent_data gic_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_153m6.hw }, { .hw = &twpll_384m.hw }, { .hw = &twpll_512m.hw }, }; static SPRD_COMP_CLK_DATA(gic_clk, "gic-clk", gic_parents, 0xa58, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(periph_clk, "periph-clk", gic_parents, 0xa5c, 0, 2, 8, 3, 0); static struct sprd_clk_common *sc9863a_aon_clks[] = { /* address base is 0x402d0000 */ &emc_clk.common, &aon_apb.common, &adi_clk.common, &aux0_clk.common, &aux1_clk.common, &aux2_clk.common, &probe_clk.common, &pwm0_clk.common, &pwm1_clk.common, &pwm2_clk.common, &aon_thm_clk.common, &audif_clk.common, &cpu_dap_clk.common, &cpu_ts_clk.common, &djtag_tck_clk.common, &emc_ref_clk.common, &cssys_clk.common, &aon_pmu_clk.common, &pmu_26m_clk.common, &aon_tmr_clk.common, &power_cpu_clk.common, &ap_axi.common, &sdio0_2x.common, &sdio1_2x.common, &sdio2_2x.common, &emmc_2x.common, &dpu_clk.common, &dpu_dpi.common, &otg_ref_clk.common, &sdphy_apb_clk.common, &alg_io_apb_clk.common, &gpu_core.common, &gpu_soc.common, &mm_emc.common, &mm_ahb.common, &bpc_clk.common, &dcam_if_clk.common, &isp_clk.common, &jpg_clk.common, &cpp_clk.common, &sensor0_clk.common, &sensor1_clk.common, &sensor2_clk.common, &mm_vemc.common, &mm_vahb.common, &clk_vsp.common, &core0_clk.common, &core1_clk.common, &core2_clk.common, &core3_clk.common, &core4_clk.common, &core5_clk.common, &core6_clk.common, &core7_clk.common, &scu_clk.common, &ace_clk.common, &axi_periph_clk.common, &axi_acp_clk.common, &atb_clk.common, &debug_apb_clk.common, &gic_clk.common, &periph_clk.common, }; static struct clk_hw_onecell_data sc9863a_aon_clk_hws = { .hws = { [CLK_13M] = &clk_13m.hw, [CLK_6M5] = &clk_6m5.hw, [CLK_4M3] = &clk_4m3.hw, [CLK_2M] = &clk_2m.hw, [CLK_250K] = &clk_250k.hw, [CLK_RCO_25M] = &rco_25m.hw, [CLK_RCO_4M] = &rco_4m.hw, [CLK_RCO_2M] = &rco_2m.hw, [CLK_EMC] = &emc_clk.common.hw, [CLK_AON_APB] = &aon_apb.common.hw, [CLK_ADI] = &adi_clk.common.hw, [CLK_AUX0] = &aux0_clk.common.hw, [CLK_AUX1] = &aux1_clk.common.hw, [CLK_AUX2] = &aux2_clk.common.hw, [CLK_PROBE] = &probe_clk.common.hw, [CLK_PWM0] = &pwm0_clk.common.hw, [CLK_PWM1] = &pwm1_clk.common.hw, [CLK_PWM2] = &pwm2_clk.common.hw, [CLK_AON_THM] = &aon_thm_clk.common.hw, [CLK_AUDIF] = &audif_clk.common.hw, [CLK_CPU_DAP] = &cpu_dap_clk.common.hw, [CLK_CPU_TS] = &cpu_ts_clk.common.hw, [CLK_DJTAG_TCK] = &djtag_tck_clk.common.hw, [CLK_EMC_REF] = &emc_ref_clk.common.hw, [CLK_CSSYS] = &cssys_clk.common.hw, [CLK_AON_PMU] = &aon_pmu_clk.common.hw, [CLK_PMU_26M] = &pmu_26m_clk.common.hw, [CLK_AON_TMR] = &aon_tmr_clk.common.hw, [CLK_POWER_CPU] = &power_cpu_clk.common.hw, [CLK_AP_AXI] = &ap_axi.common.hw, [CLK_SDIO0_2X] = &sdio0_2x.common.hw, [CLK_SDIO1_2X] = &sdio1_2x.common.hw, [CLK_SDIO2_2X] = &sdio2_2x.common.hw, [CLK_EMMC_2X] = &emmc_2x.common.hw, [CLK_DPU] = &dpu_clk.common.hw, [CLK_DPU_DPI] = &dpu_dpi.common.hw, [CLK_OTG_REF] = &otg_ref_clk.common.hw, [CLK_SDPHY_APB] = &sdphy_apb_clk.common.hw, [CLK_ALG_IO_APB] = &alg_io_apb_clk.common.hw, [CLK_GPU_CORE] = &gpu_core.common.hw, [CLK_GPU_SOC] = &gpu_soc.common.hw, [CLK_MM_EMC] = &mm_emc.common.hw, [CLK_MM_AHB] = &mm_ahb.common.hw, [CLK_BPC] = &bpc_clk.common.hw, [CLK_DCAM_IF] = &dcam_if_clk.common.hw, [CLK_ISP] = &isp_clk.common.hw, [CLK_JPG] = &jpg_clk.common.hw, [CLK_CPP] = &cpp_clk.common.hw, [CLK_SENSOR0] = &sensor0_clk.common.hw, [CLK_SENSOR1] = &sensor1_clk.common.hw, [CLK_SENSOR2] = &sensor2_clk.common.hw, [CLK_MM_VEMC] = &mm_vemc.common.hw, [CLK_MM_VAHB] = &mm_vahb.common.hw, [CLK_VSP] = &clk_vsp.common.hw, [CLK_CORE0] = &core0_clk.common.hw, [CLK_CORE1] = &core1_clk.common.hw, [CLK_CORE2] = &core2_clk.common.hw, [CLK_CORE3] = &core3_clk.common.hw, [CLK_CORE4] = &core4_clk.common.hw, [CLK_CORE5] = &core5_clk.common.hw, [CLK_CORE6] = &core6_clk.common.hw, [CLK_CORE7] = &core7_clk.common.hw, [CLK_SCU] = &scu_clk.common.hw, [CLK_ACE] = &ace_clk.common.hw, [CLK_AXI_PERIPH] = &axi_periph_clk.common.hw, [CLK_AXI_ACP] = &axi_acp_clk.common.hw, [CLK_ATB] = &atb_clk.common.hw, [CLK_DEBUG_APB] = &debug_apb_clk.common.hw, [CLK_GIC] = &gic_clk.common.hw, [CLK_PERIPH] = &periph_clk.common.hw, }, .num = CLK_AON_CLK_NUM, }; static const struct sprd_clk_desc sc9863a_aon_clk_desc = { .clk_clks = sc9863a_aon_clks, .num_clk_clks = ARRAY_SIZE(sc9863a_aon_clks), .hw_clks = &sc9863a_aon_clk_hws, }; static const struct clk_parent_data ap_apb_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_64m.hw }, { .hw = &twpll_96m.hw }, { .hw = &twpll_128m.hw }, }; static SPRD_MUX_CLK_DATA(ap_apb, "ap-apb", ap_apb_parents, 0x20, 0, 2, SC9863A_MUX_FLAG); static const struct clk_parent_data ap_ce_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_256m.hw }, }; static SPRD_COMP_CLK_DATA(ap_ce, "ap-ce", ap_ce_parents, 0x24, 0, 1, 8, 3, 0); static const struct clk_parent_data nandc_ecc_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_256m.hw }, { .hw = &twpll_307m2.hw }, }; static SPRD_COMP_CLK_DATA(nandc_ecc, "nandc-ecc", nandc_ecc_parents, 0x28, 0, 2, 8, 3, 0); static const struct clk_parent_data nandc_26m_parents[] = { { .fw_name = "ext-32k" }, { .fw_name = "ext-26m" }, }; static SPRD_MUX_CLK_DATA(nandc_26m, "nandc-26m", nandc_26m_parents, 0x2c, 0, 1, SC9863A_MUX_FLAG); static SPRD_MUX_CLK_DATA(emmc_32k, "emmc-32k", nandc_26m_parents, 0x30, 0, 1, SC9863A_MUX_FLAG); static SPRD_MUX_CLK_DATA(sdio0_32k, "sdio0-32k", nandc_26m_parents, 0x34, 0, 1, SC9863A_MUX_FLAG); static SPRD_MUX_CLK_DATA(sdio1_32k, "sdio1-32k", nandc_26m_parents, 0x38, 0, 1, SC9863A_MUX_FLAG); static SPRD_MUX_CLK_DATA(sdio2_32k, "sdio2-32k", nandc_26m_parents, 0x3c, 0, 1, SC9863A_MUX_FLAG); static SPRD_GATE_CLK_HW(otg_utmi, "otg-utmi", &aon_apb.common.hw, 0x40, BIT(16), 0, 0); static const struct clk_parent_data ap_uart_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_48m.hw }, { .hw = &twpll_51m2.hw }, { .hw = &twpll_96m.hw }, }; static SPRD_COMP_CLK_DATA(ap_uart0, "ap-uart0", ap_uart_parents, 0x44, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_uart1, "ap-uart1", ap_uart_parents, 0x48, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_uart2, "ap-uart2", ap_uart_parents, 0x4c, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_uart3, "ap-uart3", ap_uart_parents, 0x50, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_uart4, "ap-uart4", ap_uart_parents, 0x54, 0, 2, 8, 3, 0); static const struct clk_parent_data i2c_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_48m.hw }, { .hw = &twpll_51m2.hw }, { .hw = &twpll_153m6.hw }, }; static SPRD_COMP_CLK_DATA(ap_i2c0, "ap-i2c0", i2c_parents, 0x58, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_i2c1, "ap-i2c1", i2c_parents, 0x5c, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_i2c2, "ap-i2c2", i2c_parents, 0x60, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_i2c3, "ap-i2c3", i2c_parents, 0x64, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_i2c4, "ap-i2c4", i2c_parents, 0x68, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_i2c5, "ap-i2c5", i2c_parents, 0x6c, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_i2c6, "ap-i2c6", i2c_parents, 0x70, 0, 2, 8, 3, 0); static const struct clk_parent_data spi_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, { .hw = &twpll_192m.hw }, }; static SPRD_COMP_CLK_DATA(ap_spi0, "ap-spi0", spi_parents, 0x74, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_spi1, "ap-spi1", spi_parents, 0x78, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_spi2, "ap-spi2", spi_parents, 0x7c, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_spi3, "ap-spi3", spi_parents, 0x80, 0, 2, 8, 3, 0); static const struct clk_parent_data iis_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_128m.hw }, { .hw = &twpll_153m6.hw }, }; static SPRD_COMP_CLK_DATA(ap_iis0, "ap-iis0", iis_parents, 0x84, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_iis1, "ap-iis1", iis_parents, 0x88, 0, 2, 8, 3, 0); static SPRD_COMP_CLK_DATA(ap_iis2, "ap-iis2", iis_parents, 0x8c, 0, 2, 8, 3, 0); static const struct clk_parent_data sim0_parents[] = { { .fw_name = "ext-26m" }, { .hw = &twpll_51m2.hw }, { .hw = &twpll_64m.hw }, { .hw = &twpll_96m.hw }, { .hw = &twpll_128m.hw }, }; static SPRD_COMP_CLK_DATA(sim0, "sim0", sim0_parents, 0x90, 0, 3, 8, 3, 0); static const struct clk_parent_data sim0_32k_parents[] = { { .fw_name = "ext-32k" }, { .fw_name = "ext-26m" }, }; static SPRD_MUX_CLK_DATA(sim0_32k, "sim0-32k", sim0_32k_parents, 0x94, 0, 1, SC9863A_MUX_FLAG); static struct sprd_clk_common *sc9863a_ap_clks[] = { /* address base is 0x21500000 */ &ap_apb.common, &ap_ce.common, &nandc_ecc.common, &nandc_26m.common, &emmc_32k.common, &sdio0_32k.common, &sdio1_32k.common, &sdio2_32k.common, &otg_utmi.common, &ap_uart0.common, &ap_uart1.common, &ap_uart2.common, &ap_uart3.common, &ap_uart4.common, &ap_i2c0.common, &ap_i2c1.common, &ap_i2c2.common, &ap_i2c3.common, &ap_i2c4.common, &ap_i2c5.common, &ap_i2c6.common, &ap_spi0.common, &ap_spi1.common, &ap_spi2.common, &ap_spi3.common, &ap_iis0.common, &ap_iis1.common, &ap_iis2.common, &sim0.common, &sim0_32k.common, }; static struct clk_hw_onecell_data sc9863a_ap_clk_hws = { .hws = { [CLK_AP_APB] = &ap_apb.common.hw, [CLK_AP_CE] = &ap_ce.common.hw, [CLK_NANDC_ECC] = &nandc_ecc.common.hw, [CLK_NANDC_26M] = &nandc_26m.common.hw, [CLK_EMMC_32K] = &emmc_32k.common.hw, [CLK_SDIO0_32K] = &sdio0_32k.common.hw, [CLK_SDIO1_32K] = &sdio1_32k.common.hw, [CLK_SDIO2_32K] = &sdio2_32k.common.hw, [CLK_OTG_UTMI] = &otg_utmi.common.hw, [CLK_AP_UART0] = &ap_uart0.common.hw, [CLK_AP_UART1] = &ap_uart1.common.hw, [CLK_AP_UART2] = &ap_uart2.common.hw, [CLK_AP_UART3] = &ap_uart3.common.hw, [CLK_AP_UART4] = &ap_uart4.common.hw, [CLK_AP_I2C0] = &ap_i2c0.common.hw, [CLK_AP_I2C1] = &ap_i2c1.common.hw, [CLK_AP_I2C2] = &ap_i2c2.common.hw, [CLK_AP_I2C3] = &ap_i2c3.common.hw, [CLK_AP_I2C4] = &ap_i2c4.common.hw, [CLK_AP_I2C5] = &ap_i2c5.common.hw, [CLK_AP_I2C6] = &ap_i2c6.common.hw, [CLK_AP_SPI0] = &ap_spi0.common.hw, [CLK_AP_SPI1] = &ap_spi1.common.hw, [CLK_AP_SPI2] = &ap_spi2.common.hw, [CLK_AP_SPI3] = &ap_spi3.common.hw, [CLK_AP_IIS0] = &ap_iis0.common.hw, [CLK_AP_IIS1] = &ap_iis1.common.hw, [CLK_AP_IIS2] = &ap_iis2.common.hw, [CLK_SIM0] = &sim0.common.hw, [CLK_SIM0_32K] = &sim0_32k.common.hw, }, .num = CLK_AP_CLK_NUM, }; static const struct sprd_clk_desc sc9863a_ap_clk_desc = { .clk_clks = sc9863a_ap_clks, .num_clk_clks = ARRAY_SIZE(sc9863a_ap_clks), .hw_clks = &sc9863a_ap_clk_hws, }; static SPRD_SC_GATE_CLK_HW(otg_eb, "otg-eb", &ap_axi.common.hw, 0x0, 0x1000, BIT(4), 0, 0); static SPRD_SC_GATE_CLK_HW(dma_eb, "dma-eb", &ap_axi.common.hw, 0x0, 0x1000, BIT(5), 0, 0); static SPRD_SC_GATE_CLK_HW(ce_eb, "ce-eb", &ap_axi.common.hw, 0x0, 0x1000, BIT(6), 0, 0); static SPRD_SC_GATE_CLK_HW(nandc_eb, "nandc-eb", &ap_axi.common.hw, 0x0, 0x1000, BIT(7), 0, 0); static SPRD_SC_GATE_CLK_HW(sdio0_eb, "sdio0-eb", &ap_axi.common.hw, 0x0, 0x1000, BIT(8), 0, 0); static SPRD_SC_GATE_CLK_HW(sdio1_eb, "sdio1-eb", &ap_axi.common.hw, 0x0, 0x1000, BIT(9), 0, 0); static SPRD_SC_GATE_CLK_HW(sdio2_eb, "sdio2-eb", &ap_axi.common.hw, 0x0, 0x1000, BIT(10), 0, 0); static SPRD_SC_GATE_CLK_HW(emmc_eb, "emmc-eb", &ap_axi.common.hw, 0x0, 0x1000, BIT(11), 0, 0); static SPRD_SC_GATE_CLK_HW(emmc_32k_eb, "emmc-32k-eb", &ap_axi.common.hw, 0x0, 0x1000, BIT(27), 0, 0); static SPRD_SC_GATE_CLK_HW(sdio0_32k_eb, "sdio0-32k-eb", &ap_axi.common.hw, 0x0, 0x1000, BIT(28), 0, 0); static SPRD_SC_GATE_CLK_HW(sdio1_32k_eb, "sdio1-32k-eb", &ap_axi.common.hw, 0x0, 0x1000, BIT(29), 0, 0); static SPRD_SC_GATE_CLK_HW(sdio2_32k_eb, "sdio2-32k-eb", &ap_axi.common.hw, 0x0, 0x1000, BIT(30), 0, 0); static SPRD_SC_GATE_CLK_HW(nandc_26m_eb, "nandc-26m-eb", &ap_axi.common.hw, 0x0, 0x1000, BIT(31), 0, 0); static SPRD_SC_GATE_CLK_HW(dma_eb2, "dma-eb2", &ap_axi.common.hw, 0x18, 0x1000, BIT(0), 0, 0); static SPRD_SC_GATE_CLK_HW(ce_eb2, "ce-eb2", &ap_axi.common.hw, 0x18, 0x1000, BIT(1), 0, 0); static struct sprd_clk_common *sc9863a_apahb_gate_clks[] = { /* address base is 0x20e00000 */ &otg_eb.common, &dma_eb.common, &ce_eb.common, &nandc_eb.common, &sdio0_eb.common, &sdio1_eb.common, &sdio2_eb.common, &emmc_eb.common, &emmc_32k_eb.common, &sdio0_32k_eb.common, &sdio1_32k_eb.common, &sdio2_32k_eb.common, &nandc_26m_eb.common, &dma_eb2.common, &ce_eb2.common, }; static struct clk_hw_onecell_data sc9863a_apahb_gate_hws = { .hws = { [CLK_OTG_EB] = &otg_eb.common.hw, [CLK_DMA_EB] = &dma_eb.common.hw, [CLK_CE_EB] = &ce_eb.common.hw, [CLK_NANDC_EB] = &nandc_eb.common.hw, [CLK_SDIO0_EB] = &sdio0_eb.common.hw, [CLK_SDIO1_EB] = &sdio1_eb.common.hw, [CLK_SDIO2_EB] = &sdio2_eb.common.hw, [CLK_EMMC_EB] = &emmc_eb.common.hw, [CLK_EMMC_32K_EB] = &emmc_32k_eb.common.hw, [CLK_SDIO0_32K_EB] = &sdio0_32k_eb.common.hw, [CLK_SDIO1_32K_EB] = &sdio1_32k_eb.common.hw, [CLK_SDIO2_32K_EB] = &sdio2_32k_eb.common.hw, [CLK_NANDC_26M_EB] = &nandc_26m_eb.common.hw, [CLK_DMA_EB2] = &dma_eb2.common.hw, [CLK_CE_EB2] = &ce_eb2.common.hw, }, .num = CLK_AP_AHB_GATE_NUM, }; static const struct sprd_clk_desc sc9863a_apahb_gate_desc = { .clk_clks = sc9863a_apahb_gate_clks, .num_clk_clks = ARRAY_SIZE(sc9863a_apahb_gate_clks), .hw_clks = &sc9863a_apahb_gate_hws, }; /* aon gate clocks */ static SPRD_SC_GATE_CLK_HW(gpio_eb, "gpio-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(3), 0, 0); static SPRD_SC_GATE_CLK_HW(pwm0_eb, "pwm0-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(4), 0, 0); static SPRD_SC_GATE_CLK_HW(pwm1_eb, "pwm1-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(pwm2_eb, "pwm2-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(6), 0, 0); static SPRD_SC_GATE_CLK_HW(pwm3_eb, "pwm3-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(7), 0, 0); static SPRD_SC_GATE_CLK_HW(kpd_eb, "kpd-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(8), 0, 0); static SPRD_SC_GATE_CLK_HW(aon_syst_eb, "aon-syst-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ap_syst_eb, "ap-syst-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(aon_tmr_eb, "aon-tmr-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(efuse_eb, "efuse-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(eic_eb, "eic-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(intc_eb, "intc-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(adi_eb, "adi-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(audif_eb, "audif-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(17), 0, 0); static SPRD_SC_GATE_CLK_HW(aud_eb, "aud-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(18), 0, 0); static SPRD_SC_GATE_CLK_HW(vbc_eb, "vbc-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(19), 0, 0); static SPRD_SC_GATE_CLK_HW(pin_eb, "pin-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ap_wdg_eb, "ap-wdg-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(24), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_eb, "mm-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(aon_apb_ckg_eb, "aon-apb-ckg-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ca53_ts0_eb, "ca53-ts0-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ca53_ts1_eb, "ca53-ts1-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ca53_dap_eb, "ca53-dap-eb", &aon_apb.common.hw, 0x0, 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(pmu_eb, "pmu-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(thm_eb, "thm-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(aux0_eb, "aux0-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(aux1_eb, "aux1-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(3), 0, 0); static SPRD_SC_GATE_CLK_HW(aux2_eb, "aux2-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(probe_eb, "probe-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(5), 0, 0); static SPRD_SC_GATE_CLK_HW(emc_ref_eb, "emc-ref-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ca53_wdg_eb, "ca53-wdg-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ap_tmr1_eb, "ap-tmr1-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(9), 0, 0); static SPRD_SC_GATE_CLK_HW(ap_tmr2_eb, "ap-tmr2-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(10), 0, 0); static SPRD_SC_GATE_CLK_HW(disp_emc_eb, "disp-emc-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(11), 0, 0); static SPRD_SC_GATE_CLK_HW(zip_emc_eb, "zip-emc-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(12), 0, 0); static SPRD_SC_GATE_CLK_HW(gsp_emc_eb, "gsp-emc-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(13), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_vsp_eb, "mm-vsp-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(14), 0, 0); static SPRD_SC_GATE_CLK_HW(mdar_eb, "mdar-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(17), 0, 0); static SPRD_SC_GATE_CLK_HW(rtc4m0_cal_eb, "rtc4m0-cal-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(18), 0, 0); static SPRD_SC_GATE_CLK_HW(rtc4m1_cal_eb, "rtc4m1-cal-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(19), 0, 0); static SPRD_SC_GATE_CLK_HW(djtag_eb, "djtag-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(20), 0, 0); static SPRD_SC_GATE_CLK_HW(mbox_eb, "mbox-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(21), 0, 0); static SPRD_SC_GATE_CLK_HW(aon_dma_eb, "aon-dma-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(22), 0, 0); static SPRD_SC_GATE_CLK_HW(aon_apb_def_eb, "aon-apb-def-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(25), 0, 0); static SPRD_SC_GATE_CLK_HW(ca5_ts0_eb, "ca5-ts0-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(26), 0, 0); static SPRD_SC_GATE_CLK_HW(dbg_eb, "dbg-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(28), 0, 0); static SPRD_SC_GATE_CLK_HW(dbg_emc_eb, "dbg-emc-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(29), 0, 0); static SPRD_SC_GATE_CLK_HW(cross_trig_eb, "cross-trig-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(30), 0, 0); static SPRD_SC_GATE_CLK_HW(serdes_dphy_eb, "serdes-dphy-eb", &aon_apb.common.hw, 0x4, 0x1000, BIT(31), 0, 0); static SPRD_SC_GATE_CLK_HW(arch_rtc_eb, "arch-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(kpd_rtc_eb, "kpd-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(1), 0, 0); static SPRD_SC_GATE_CLK_HW(aon_syst_rtc_eb, "aon-syst-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ap_syst_rtc_eb, "ap-syst-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(aon_tmr_rtc_eb, "aon-tmr-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ap_tmr0_rtc_eb, "ap-tmr0-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(5), 0, 0); static SPRD_SC_GATE_CLK_HW(eic_rtc_eb, "eic-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(eic_rtcdv5_eb, "eic-rtcdv5-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ap_wdg_rtc_eb, "ap-wdg-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ca53_wdg_rtc_eb, "ca53-wdg-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(thm_rtc_eb, "thm-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(10), 0, 0); static SPRD_SC_GATE_CLK_HW(athma_rtc_eb, "athma-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(11), 0, 0); static SPRD_SC_GATE_CLK_HW(gthma_rtc_eb, "gthma-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(12), 0, 0); static SPRD_SC_GATE_CLK_HW(athma_rtc_a_eb, "athma-rtc-a-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(13), 0, 0); static SPRD_SC_GATE_CLK_HW(gthma_rtc_a_eb, "gthma-rtc-a-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(14), 0, 0); static SPRD_SC_GATE_CLK_HW(ap_tmr1_rtc_eb, "ap-tmr1-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(15), 0, 0); static SPRD_SC_GATE_CLK_HW(ap_tmr2_rtc_eb, "ap-tmr2-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(16), 0, 0); static SPRD_SC_GATE_CLK_HW(dxco_lc_rtc_eb, "dxco-lc-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(17), 0, 0); static SPRD_SC_GATE_CLK_HW(bb_cal_rtc_eb, "bb-cal-rtc-eb", &aon_apb.common.hw, 0x10, 0x1000, BIT(18), 0, 0); static SPRD_SC_GATE_CLK_HW(gpu_eb, "gpu-eb", &aon_apb.common.hw, 0x50, 0x1000, BIT(0), 0, 0); static SPRD_SC_GATE_CLK_HW(disp_eb, "disp-eb", &aon_apb.common.hw, 0x50, 0x1000, BIT(2), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_emc_eb, "mm-emc-eb", &aon_apb.common.hw, 0x50, 0x1000, BIT(3), 0, 0); static SPRD_SC_GATE_CLK_HW(power_cpu_eb, "power-cpu-eb", &aon_apb.common.hw, 0x50, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(hw_i2c_eb, "hw-i2c-eb", &aon_apb.common.hw, 0x50, 0x1000, BIT(11), 0, 0); static SPRD_SC_GATE_CLK_HW(mm_vsp_emc_eb, "mm-vsp-emc-eb", &aon_apb.common.hw, 0x50, 0x1000, BIT(14), 0, 0); static SPRD_SC_GATE_CLK_HW(vsp_eb, "vsp-eb", &aon_apb.common.hw, 0x50, 0x1000, BIT(16), 0, 0); static SPRD_SC_GATE_CLK_HW(cssys_eb, "cssys-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(4), 0, 0); static SPRD_SC_GATE_CLK_HW(dmc_eb, "dmc-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(rosc_eb, "rosc-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(7), 0, 0); static SPRD_SC_GATE_CLK_HW(s_d_cfg_eb, "s-d-cfg-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(8), 0, 0); static SPRD_SC_GATE_CLK_HW(s_d_ref_eb, "s-d-ref-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(9), 0, 0); static SPRD_SC_GATE_CLK_HW(b_dma_eb, "b-dma-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(10), 0, 0); static SPRD_SC_GATE_CLK_HW(anlg_eb, "anlg-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(anlg_apb_eb, "anlg-apb-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(13), 0, 0); static SPRD_SC_GATE_CLK_HW(bsmtmr_eb, "bsmtmr-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(14), 0, 0); static SPRD_SC_GATE_CLK_HW(ap_axi_eb, "ap-axi-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ap_intc0_eb, "ap-intc0-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ap_intc1_eb, "ap-intc1-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ap_intc2_eb, "ap-intc2-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ap_intc3_eb, "ap-intc3-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ap_intc4_eb, "ap-intc4-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(ap_intc5_eb, "ap-intc5-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_HW(scc_eb, "scc-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(22), 0, 0); static SPRD_SC_GATE_CLK_HW(dphy_cfg_eb, "dphy-cfg-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(23), 0, 0); static SPRD_SC_GATE_CLK_HW(dphy_ref_eb, "dphy-ref-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(24), 0, 0); static SPRD_SC_GATE_CLK_HW(cphy_cfg_eb, "cphy-cfg-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(25), 0, 0); static SPRD_SC_GATE_CLK_HW(otg_ref_eb, "otg-ref-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(26), 0, 0); static SPRD_SC_GATE_CLK_HW(serdes_eb, "serdes-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(27), 0, 0); static SPRD_SC_GATE_CLK_HW(aon_ap_emc_eb, "aon-ap-emc-eb", &aon_apb.common.hw, 0xb0, 0x1000, BIT(28), 0, 0); static struct sprd_clk_common *sc9863a_aonapb_gate_clks[] = { /* address base is 0x402e0000 */ &gpio_eb.common, &pwm0_eb.common, &pwm1_eb.common, &pwm2_eb.common, &pwm3_eb.common, &kpd_eb.common, &aon_syst_eb.common, &ap_syst_eb.common, &aon_tmr_eb.common, &efuse_eb.common, &eic_eb.common, &intc_eb.common, &adi_eb.common, &audif_eb.common, &aud_eb.common, &vbc_eb.common, &pin_eb.common, &ap_wdg_eb.common, &mm_eb.common, &aon_apb_ckg_eb.common, &ca53_ts0_eb.common, &ca53_ts1_eb.common, &ca53_dap_eb.common, &pmu_eb.common, &thm_eb.common, &aux0_eb.common, &aux1_eb.common, &aux2_eb.common, &probe_eb.common, &emc_ref_eb.common, &ca53_wdg_eb.common, &ap_tmr1_eb.common, &ap_tmr2_eb.common, &disp_emc_eb.common, &zip_emc_eb.common, &gsp_emc_eb.common, &mm_vsp_eb.common, &mdar_eb.common, &rtc4m0_cal_eb.common, &rtc4m1_cal_eb.common, &djtag_eb.common, &mbox_eb.common, &aon_dma_eb.common, &aon_apb_def_eb.common, &ca5_ts0_eb.common, &dbg_eb.common, &dbg_emc_eb.common, &cross_trig_eb.common, &serdes_dphy_eb.common, &arch_rtc_eb.common, &kpd_rtc_eb.common, &aon_syst_rtc_eb.common, &ap_syst_rtc_eb.common, &aon_tmr_rtc_eb.common, &ap_tmr0_rtc_eb.common, &eic_rtc_eb.common, &eic_rtcdv5_eb.common, &ap_wdg_rtc_eb.common, &ca53_wdg_rtc_eb.common, &thm_rtc_eb.common, &athma_rtc_eb.common, &gthma_rtc_eb.common, &athma_rtc_a_eb.common, &gthma_rtc_a_eb.common, &ap_tmr1_rtc_eb.common, &ap_tmr2_rtc_eb.common, &dxco_lc_rtc_eb.common, &bb_cal_rtc_eb.common, &gpu_eb.common, &disp_eb.common, &mm_emc_eb.common, &power_cpu_eb.common, &hw_i2c_eb.common, &mm_vsp_emc_eb.common, &vsp_eb.common, &cssys_eb.common, &dmc_eb.common, &rosc_eb.common, &s_d_cfg_eb.common, &s_d_ref_eb.common, &b_dma_eb.common, &anlg_eb.common, &anlg_apb_eb.common, &bsmtmr_eb.common, &ap_axi_eb.common, &ap_intc0_eb.common, &ap_intc1_eb.common, &ap_intc2_eb.common, &ap_intc3_eb.common, &ap_intc4_eb.common, &ap_intc5_eb.common, &scc_eb.common, &dphy_cfg_eb.common, &dphy_ref_eb.common, &cphy_cfg_eb.common, &otg_ref_eb.common, &serdes_eb.common, &aon_ap_emc_eb.common, }; static struct clk_hw_onecell_data sc9863a_aonapb_gate_hws = { .hws = { [CLK_GPIO_EB] = &gpio_eb.common.hw, [CLK_PWM0_EB] = &pwm0_eb.common.hw, [CLK_PWM1_EB] = &pwm1_eb.common.hw, [CLK_PWM2_EB] = &pwm2_eb.common.hw, [CLK_PWM3_EB] = &pwm3_eb.common.hw, [CLK_KPD_EB] = &kpd_eb.common.hw, [CLK_AON_SYST_EB] = &aon_syst_eb.common.hw, [CLK_AP_SYST_EB] = &ap_syst_eb.common.hw, [CLK_AON_TMR_EB] = &aon_tmr_eb.common.hw, [CLK_EFUSE_EB] = &efuse_eb.common.hw, [CLK_EIC_EB] = &eic_eb.common.hw, [CLK_INTC_EB] = &intc_eb.common.hw, [CLK_ADI_EB] = &adi_eb.common.hw, [CLK_AUDIF_EB] = &audif_eb.common.hw, [CLK_AUD_EB] = &aud_eb.common.hw, [CLK_VBC_EB] = &vbc_eb.common.hw, [CLK_PIN_EB] = &pin_eb.common.hw, [CLK_AP_WDG_EB] = &ap_wdg_eb.common.hw, [CLK_MM_EB] = &mm_eb.common.hw, [CLK_AON_APB_CKG_EB] = &aon_apb_ckg_eb.common.hw, [CLK_CA53_TS0_EB] = &ca53_ts0_eb.common.hw, [CLK_CA53_TS1_EB] = &ca53_ts1_eb.common.hw, [CLK_CS53_DAP_EB] = &ca53_dap_eb.common.hw, [CLK_PMU_EB] = &pmu_eb.common.hw, [CLK_THM_EB] = &thm_eb.common.hw, [CLK_AUX0_EB] = &aux0_eb.common.hw, [CLK_AUX1_EB] = &aux1_eb.common.hw, [CLK_AUX2_EB] = &aux2_eb.common.hw, [CLK_PROBE_EB] = &probe_eb.common.hw, [CLK_EMC_REF_EB] = &emc_ref_eb.common.hw, [CLK_CA53_WDG_EB] = &ca53_wdg_eb.common.hw, [CLK_AP_TMR1_EB] = &ap_tmr1_eb.common.hw, [CLK_AP_TMR2_EB] = &ap_tmr2_eb.common.hw, [CLK_DISP_EMC_EB] = &disp_emc_eb.common.hw, [CLK_ZIP_EMC_EB] = &zip_emc_eb.common.hw, [CLK_GSP_EMC_EB] = &gsp_emc_eb.common.hw, [CLK_MM_VSP_EB] = &mm_vsp_eb.common.hw, [CLK_MDAR_EB] = &mdar_eb.common.hw, [CLK_RTC4M0_CAL_EB] = &rtc4m0_cal_eb.common.hw, [CLK_RTC4M1_CAL_EB] = &rtc4m1_cal_eb.common.hw, [CLK_DJTAG_EB] = &djtag_eb.common.hw, [CLK_MBOX_EB] = &mbox_eb.common.hw, [CLK_AON_DMA_EB] = &aon_dma_eb.common.hw, [CLK_AON_APB_DEF_EB] = &aon_apb_def_eb.common.hw, [CLK_CA5_TS0_EB] = &ca5_ts0_eb.common.hw, [CLK_DBG_EB] = &dbg_eb.common.hw, [CLK_DBG_EMC_EB] = &dbg_emc_eb.common.hw, [CLK_CROSS_TRIG_EB] = &cross_trig_eb.common.hw, [CLK_SERDES_DPHY_EB] = &serdes_dphy_eb.common.hw, [CLK_ARCH_RTC_EB] = &arch_rtc_eb.common.hw, [CLK_KPD_RTC_EB] = &kpd_rtc_eb.common.hw, [CLK_AON_SYST_RTC_EB] = &aon_syst_rtc_eb.common.hw, [CLK_AP_SYST_RTC_EB] = &ap_syst_rtc_eb.common.hw, [CLK_AON_TMR_RTC_EB] = &aon_tmr_rtc_eb.common.hw, [CLK_AP_TMR0_RTC_EB] = &ap_tmr0_rtc_eb.common.hw, [CLK_EIC_RTC_EB] = &eic_rtc_eb.common.hw, [CLK_EIC_RTCDV5_EB] = &eic_rtcdv5_eb.common.hw, [CLK_AP_WDG_RTC_EB] = &ap_wdg_rtc_eb.common.hw, [CLK_CA53_WDG_RTC_EB] = &ca53_wdg_rtc_eb.common.hw, [CLK_THM_RTC_EB] = &thm_rtc_eb.common.hw, [CLK_ATHMA_RTC_EB] = &athma_rtc_eb.common.hw, [CLK_GTHMA_RTC_EB] = &gthma_rtc_eb.common.hw, [CLK_ATHMA_RTC_A_EB] = &athma_rtc_a_eb.common.hw, [CLK_GTHMA_RTC_A_EB] = &gthma_rtc_a_eb.common.hw, [CLK_AP_TMR1_RTC_EB] = &ap_tmr1_rtc_eb.common.hw, [CLK_AP_TMR2_RTC_EB] = &ap_tmr2_rtc_eb.common.hw, [CLK_DXCO_LC_RTC_EB] = &dxco_lc_rtc_eb.common.hw, [CLK_BB_CAL_RTC_EB] = &bb_cal_rtc_eb.common.hw, [CLK_GNU_EB] = &gpu_eb.common.hw, [CLK_DISP_EB] = &disp_eb.common.hw, [CLK_MM_EMC_EB] = &mm_emc_eb.common.hw, [CLK_POWER_CPU_EB] = &power_cpu_eb.common.hw, [CLK_HW_I2C_EB] = &hw_i2c_eb.common.hw, [CLK_MM_VSP_EMC_EB] = &mm_vsp_emc_eb.common.hw, [CLK_VSP_EB] = &vsp_eb.common.hw, [CLK_CSSYS_EB] = &cssys_eb.common.hw, [CLK_DMC_EB] = &dmc_eb.common.hw, [CLK_ROSC_EB] = &rosc_eb.common.hw, [CLK_S_D_CFG_EB] = &s_d_cfg_eb.common.hw, [CLK_S_D_REF_EB] = &s_d_ref_eb.common.hw, [CLK_B_DMA_EB] = &b_dma_eb.common.hw, [CLK_ANLG_EB] = &anlg_eb.common.hw, [CLK_ANLG_APB_EB] = &anlg_apb_eb.common.hw, [CLK_BSMTMR_EB] = &bsmtmr_eb.common.hw, [CLK_AP_AXI_EB] = &ap_axi_eb.common.hw, [CLK_AP_INTC0_EB] = &ap_intc0_eb.common.hw, [CLK_AP_INTC1_EB] = &ap_intc1_eb.common.hw, [CLK_AP_INTC2_EB] = &ap_intc2_eb.common.hw, [CLK_AP_INTC3_EB] = &ap_intc3_eb.common.hw, [CLK_AP_INTC4_EB] = &ap_intc4_eb.common.hw, [CLK_AP_INTC5_EB] = &ap_intc5_eb.common.hw, [CLK_SCC_EB] = &scc_eb.common.hw, [CLK_DPHY_CFG_EB] = &dphy_cfg_eb.common.hw, [CLK_DPHY_REF_EB] = &dphy_ref_eb.common.hw, [CLK_CPHY_CFG_EB] = &cphy_cfg_eb.common.hw, [CLK_OTG_REF_EB] = &otg_ref_eb.common.hw, [CLK_SERDES_EB] = &serdes_eb.common.hw, [CLK_AON_AP_EMC_EB] = &aon_ap_emc_eb.common.hw, }, .num = CLK_AON_APB_GATE_NUM, }; static const struct sprd_clk_desc sc9863a_aonapb_gate_desc = { .clk_clks = sc9863a_aonapb_gate_clks, .num_clk_clks = ARRAY_SIZE(sc9863a_aonapb_gate_clks), .hw_clks = &sc9863a_aonapb_gate_hws, }; /* mm gate clocks */ static SPRD_SC_GATE_CLK_HW(mahb_ckg_eb, "mahb-ckg-eb", &mm_ahb.common.hw, 0x0, 0x1000, BIT(0), 0, 0); static SPRD_SC_GATE_CLK_HW(mdcam_eb, "mdcam-eb", &mm_ahb.common.hw, 0x0, 0x1000, BIT(1), 0, 0); static SPRD_SC_GATE_CLK_HW(misp_eb, "misp-eb", &mm_ahb.common.hw, 0x0, 0x1000, BIT(2), 0, 0); static SPRD_SC_GATE_CLK_HW(mahbcsi_eb, "mahbcsi-eb", &mm_ahb.common.hw, 0x0, 0x1000, BIT(3), 0, 0); static SPRD_SC_GATE_CLK_HW(mcsi_s_eb, "mcsi-s-eb", &mm_ahb.common.hw, 0x0, 0x1000, BIT(4), 0, 0); static SPRD_SC_GATE_CLK_HW(mcsi_t_eb, "mcsi-t-eb", &mm_ahb.common.hw, 0x0, 0x1000, BIT(5), 0, 0); static SPRD_GATE_CLK_HW(dcam_axi_eb, "dcam-axi-eb", &mm_ahb.common.hw, 0x8, BIT(0), 0, 0); static SPRD_GATE_CLK_HW(isp_axi_eb, "isp-axi-eb", &mm_ahb.common.hw, 0x8, BIT(1), 0, 0); static SPRD_GATE_CLK_HW(mcsi_eb, "mcsi-eb", &mm_ahb.common.hw, 0x8, BIT(2), 0, 0); static SPRD_GATE_CLK_HW(mcsi_s_ckg_eb, "mcsi-s-ckg-eb", &mm_ahb.common.hw, 0x8, BIT(3), 0, 0); static SPRD_GATE_CLK_HW(mcsi_t_ckg_eb, "mcsi-t-ckg-eb", &mm_ahb.common.hw, 0x8, BIT(4), 0, 0); static SPRD_GATE_CLK_HW(sensor0_eb, "sensor0-eb", &mm_ahb.common.hw, 0x8, BIT(5), 0, 0); static SPRD_GATE_CLK_HW(sensor1_eb, "sensor1-eb", &mm_ahb.common.hw, 0x8, BIT(6), 0, 0); static SPRD_GATE_CLK_HW(sensor2_eb, "sensor2-eb", &mm_ahb.common.hw, 0x8, BIT(7), 0, 0); static SPRD_GATE_CLK_HW(mcphy_cfg_eb, "mcphy-cfg-eb", &mm_ahb.common.hw, 0x8, BIT(8), 0, 0); static struct sprd_clk_common *sc9863a_mm_gate_clks[] = { /* address base is 0x60800000 */ &mahb_ckg_eb.common, &mdcam_eb.common, &misp_eb.common, &mahbcsi_eb.common, &mcsi_s_eb.common, &mcsi_t_eb.common, &dcam_axi_eb.common, &isp_axi_eb.common, &mcsi_eb.common, &mcsi_s_ckg_eb.common, &mcsi_t_ckg_eb.common, &sensor0_eb.common, &sensor1_eb.common, &sensor2_eb.common, &mcphy_cfg_eb.common, }; static struct clk_hw_onecell_data sc9863a_mm_gate_hws = { .hws = { [CLK_MAHB_CKG_EB] = &mahb_ckg_eb.common.hw, [CLK_MDCAM_EB] = &mdcam_eb.common.hw, [CLK_MISP_EB] = &misp_eb.common.hw, [CLK_MAHBCSI_EB] = &mahbcsi_eb.common.hw, [CLK_MCSI_S_EB] = &mcsi_s_eb.common.hw, [CLK_MCSI_T_EB] = &mcsi_t_eb.common.hw, [CLK_DCAM_AXI_EB] = &dcam_axi_eb.common.hw, [CLK_ISP_AXI_EB] = &isp_axi_eb.common.hw, [CLK_MCSI_EB] = &mcsi_eb.common.hw, [CLK_MCSI_S_CKG_EB] = &mcsi_s_ckg_eb.common.hw, [CLK_MCSI_T_CKG_EB] = &mcsi_t_ckg_eb.common.hw, [CLK_SENSOR0_EB] = &sensor0_eb.common.hw, [CLK_SENSOR1_EB] = &sensor1_eb.common.hw, [CLK_SENSOR2_EB] = &sensor2_eb.common.hw, [CLK_MCPHY_CFG_EB] = &mcphy_cfg_eb.common.hw, }, .num = CLK_MM_GATE_NUM, }; static const struct sprd_clk_desc sc9863a_mm_gate_desc = { .clk_clks = sc9863a_mm_gate_clks, .num_clk_clks = ARRAY_SIZE(sc9863a_mm_gate_clks), .hw_clks = &sc9863a_mm_gate_hws, }; /* camera sensor clocks */ static SPRD_GATE_CLK_HW(mipi_csi_clk, "mipi-csi-clk", &mahb_ckg_eb.common.hw, 0x20, BIT(16), 0, SPRD_GATE_NON_AON); static SPRD_GATE_CLK_HW(mipi_csi_s_clk, "mipi-csi-s-clk", &mahb_ckg_eb.common.hw, 0x24, BIT(16), 0, SPRD_GATE_NON_AON); static SPRD_GATE_CLK_HW(mipi_csi_m_clk, "mipi-csi-m-clk", &mahb_ckg_eb.common.hw, 0x28, BIT(16), 0, SPRD_GATE_NON_AON); static struct sprd_clk_common *sc9863a_mm_clk_clks[] = { /* address base is 0x60900000 */ &mipi_csi_clk.common, &mipi_csi_s_clk.common, &mipi_csi_m_clk.common, }; static struct clk_hw_onecell_data sc9863a_mm_clk_hws = { .hws = { [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, [CLK_MIPI_CSI_S] = &mipi_csi_s_clk.common.hw, [CLK_MIPI_CSI_M] = &mipi_csi_m_clk.common.hw, }, .num = CLK_MM_CLK_NUM, }; static const struct sprd_clk_desc sc9863a_mm_clk_desc = { .clk_clks = sc9863a_mm_clk_clks, .num_clk_clks = ARRAY_SIZE(sc9863a_mm_clk_clks), .hw_clks = &sc9863a_mm_clk_hws, }; static SPRD_SC_GATE_CLK_FW_NAME(sim0_eb, "sim0-eb", "ext-26m", 0x0, 0x1000, BIT(0), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(iis0_eb, "iis0-eb", "ext-26m", 0x0, 0x1000, BIT(1), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(iis1_eb, "iis1-eb", "ext-26m", 0x0, 0x1000, BIT(2), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(iis2_eb, "iis2-eb", "ext-26m", 0x0, 0x1000, BIT(3), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(spi0_eb, "spi0-eb", "ext-26m", 0x0, 0x1000, BIT(5), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(spi1_eb, "spi1-eb", "ext-26m", 0x0, 0x1000, BIT(6), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(spi2_eb, "spi2-eb", "ext-26m", 0x0, 0x1000, BIT(7), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(i2c0_eb, "i2c0-eb", "ext-26m", 0x0, 0x1000, BIT(8), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(i2c1_eb, "i2c1-eb", "ext-26m", 0x0, 0x1000, BIT(9), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(i2c2_eb, "i2c2-eb", "ext-26m", 0x0, 0x1000, BIT(10), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(i2c3_eb, "i2c3-eb", "ext-26m", 0x0, 0x1000, BIT(11), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(i2c4_eb, "i2c4-eb", "ext-26m", 0x0, 0x1000, BIT(12), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(uart0_eb, "uart0-eb", "ext-26m", 0x0, 0x1000, BIT(13), 0, 0); /* uart1_eb is for console, don't gate even if unused */ static SPRD_SC_GATE_CLK_FW_NAME(uart1_eb, "uart1-eb", "ext-26m", 0x0, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); static SPRD_SC_GATE_CLK_FW_NAME(uart2_eb, "uart2-eb", "ext-26m", 0x0, 0x1000, BIT(15), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(uart3_eb, "uart3-eb", "ext-26m", 0x0, 0x1000, BIT(16), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(uart4_eb, "uart4-eb", "ext-26m", 0x0, 0x1000, BIT(17), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(sim0_32k_eb, "sim0_32k-eb", "ext-26m", 0x0, 0x1000, BIT(18), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(spi3_eb, "spi3-eb", "ext-26m", 0x0, 0x1000, BIT(19), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(i2c5_eb, "i2c5-eb", "ext-26m", 0x0, 0x1000, BIT(20), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(i2c6_eb, "i2c6-eb", "ext-26m", 0x0, 0x1000, BIT(21), 0, 0); static struct sprd_clk_common *sc9863a_apapb_gate[] = { /* address base is 0x71300000 */ &sim0_eb.common, &iis0_eb.common, &iis1_eb.common, &iis2_eb.common, &spi0_eb.common, &spi1_eb.common, &spi2_eb.common, &i2c0_eb.common, &i2c1_eb.common, &i2c2_eb.common, &i2c3_eb.common, &i2c4_eb.common, &uart0_eb.common, &uart1_eb.common, &uart2_eb.common, &uart3_eb.common, &uart4_eb.common, &sim0_32k_eb.common, &spi3_eb.common, &i2c5_eb.common, &i2c6_eb.common, }; static struct clk_hw_onecell_data sc9863a_apapb_gate_hws = { .hws = { [CLK_SIM0_EB] = &sim0_eb.common.hw, [CLK_IIS0_EB] = &iis0_eb.common.hw, [CLK_IIS1_EB] = &iis1_eb.common.hw, [CLK_IIS2_EB] = &iis2_eb.common.hw, [CLK_SPI0_EB] = &spi0_eb.common.hw, [CLK_SPI1_EB] = &spi1_eb.common.hw, [CLK_SPI2_EB] = &spi2_eb.common.hw, [CLK_I2C0_EB] = &i2c0_eb.common.hw, [CLK_I2C1_EB] = &i2c1_eb.common.hw, [CLK_I2C2_EB] = &i2c2_eb.common.hw, [CLK_I2C3_EB] = &i2c3_eb.common.hw, [CLK_I2C4_EB] = &i2c4_eb.common.hw, [CLK_UART0_EB] = &uart0_eb.common.hw, [CLK_UART1_EB] = &uart1_eb.common.hw, [CLK_UART2_EB] = &uart2_eb.common.hw, [CLK_UART3_EB] = &uart3_eb.common.hw, [CLK_UART4_EB] = &uart4_eb.common.hw, [CLK_SIM0_32K_EB] = &sim0_32k_eb.common.hw, [CLK_SPI3_EB] = &spi3_eb.common.hw, [CLK_I2C5_EB] = &i2c5_eb.common.hw, [CLK_I2C6_EB] = &i2c6_eb.common.hw, }, .num = CLK_AP_APB_GATE_NUM, }; static const struct sprd_clk_desc sc9863a_apapb_gate_desc = { .clk_clks = sc9863a_apapb_gate, .num_clk_clks = ARRAY_SIZE(sc9863a_apapb_gate), .hw_clks = &sc9863a_apapb_gate_hws, }; static const struct of_device_id sprd_sc9863a_clk_ids[] = { { .compatible = "sprd,sc9863a-ap-clk", /* 0x21500000 */ .data = &sc9863a_ap_clk_desc }, { .compatible = "sprd,sc9863a-pmu-gate", /* 0x402b0000 */ .data = &sc9863a_pmu_gate_desc }, { .compatible = "sprd,sc9863a-pll", /* 0x40353000 */ .data = &sc9863a_pll_desc }, { .compatible = "sprd,sc9863a-mpll", /* 0x40359000 */ .data = &sc9863a_mpll_desc }, { .compatible = "sprd,sc9863a-rpll", /* 0x4035c000 */ .data = &sc9863a_rpll_desc }, { .compatible = "sprd,sc9863a-dpll", /* 0x40363000 */ .data = &sc9863a_dpll_desc }, { .compatible = "sprd,sc9863a-aon-clk", /* 0x402d0000 */ .data = &sc9863a_aon_clk_desc }, { .compatible = "sprd,sc9863a-apahb-gate", /* 0x20e00000 */ .data = &sc9863a_apahb_gate_desc }, { .compatible = "sprd,sc9863a-aonapb-gate", /* 0x402e0000 */ .data = &sc9863a_aonapb_gate_desc }, { .compatible = "sprd,sc9863a-mm-gate", /* 0x60800000 */ .data = &sc9863a_mm_gate_desc }, { .compatible = "sprd,sc9863a-mm-clk", /* 0x60900000 */ .data = &sc9863a_mm_clk_desc }, { .compatible = "sprd,sc9863a-apapb-gate", /* 0x71300000 */ .data = &sc9863a_apapb_gate_desc }, { } }; MODULE_DEVICE_TABLE(of, sprd_sc9863a_clk_ids); static int sc9863a_clk_probe(struct platform_device *pdev) { const struct sprd_clk_desc *desc; int ret; desc = device_get_match_data(&pdev->dev); if (!desc) return -ENODEV; ret = sprd_clk_regmap_init(pdev, desc); if (ret) return ret; return sprd_clk_probe(&pdev->dev, desc->hw_clks); } static struct platform_driver sc9863a_clk_driver = { .probe = sc9863a_clk_probe, .driver = { .name = "sc9863a-clk", .of_match_table = sprd_sc9863a_clk_ids, }, }; module_platform_driver(sc9863a_clk_driver); MODULE_DESCRIPTION("Spreadtrum SC9863A Clock Driver"); MODULE_LICENSE("GPL v2");
linux-master
drivers/clk/sprd/sc9863a-clk.c
// SPDX-License-Identifier: GPL-2.0 // // Spreadtrum pll clock driver // // Copyright (C) 2015~2017 Spreadtrum, Inc. // Author: Chunyan Zhang <[email protected]> #include <linux/delay.h> #include <linux/err.h> #include <linux/regmap.h> #include <linux/slab.h> #include "pll.h" #define CLK_PLL_1M 1000000 #define CLK_PLL_10M (CLK_PLL_1M * 10) #define pindex(pll, member) \ (pll->factors[member].shift / (8 * sizeof(pll->regs_num))) #define pshift(pll, member) \ (pll->factors[member].shift % (8 * sizeof(pll->regs_num))) #define pwidth(pll, member) \ pll->factors[member].width #define pmask(pll, member) \ ((pwidth(pll, member)) ? \ GENMASK(pwidth(pll, member) + pshift(pll, member) - 1, \ pshift(pll, member)) : 0) #define pinternal(pll, cfg, member) \ (cfg[pindex(pll, member)] & pmask(pll, member)) #define pinternal_val(pll, cfg, member) \ (pinternal(pll, cfg, member) >> pshift(pll, member)) static inline unsigned int sprd_pll_read(const struct sprd_pll *pll, u8 index) { const struct sprd_clk_common *common = &pll->common; unsigned int val = 0; if (WARN_ON(index >= pll->regs_num)) return 0; regmap_read(common->regmap, common->reg + index * 4, &val); return val; } static inline void sprd_pll_write(const struct sprd_pll *pll, u8 index, u32 msk, u32 val) { const struct sprd_clk_common *common = &pll->common; unsigned int offset, reg; int ret = 0; if (WARN_ON(index >= pll->regs_num)) return; offset = common->reg + index * 4; ret = regmap_read(common->regmap, offset, &reg); if (!ret) regmap_write(common->regmap, offset, (reg & ~msk) | val); } static unsigned long pll_get_refin(const struct sprd_pll *pll) { u32 shift, mask, index, refin_id = 3; const unsigned long refin[4] = { 2, 4, 13, 26 }; if (pwidth(pll, PLL_REFIN)) { index = pindex(pll, PLL_REFIN); shift = pshift(pll, PLL_REFIN); mask = pmask(pll, PLL_REFIN); refin_id = (sprd_pll_read(pll, index) & mask) >> shift; if (refin_id > 3) refin_id = 3; } return refin[refin_id]; } static u32 pll_get_ibias(u64 rate, const u64 *table) { u32 i, num = table[0]; /* table[0] indicates the number of items in this table */ for (i = 0; i < num; i++) if (rate <= table[i + 1]) break; return i == num ? num - 1 : i; } static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll, unsigned long parent_rate) { u32 *cfg; u32 i, mask, regs_num = pll->regs_num; unsigned long rate, nint, kint = 0; u64 refin; u16 k1, k2; cfg = kcalloc(regs_num, sizeof(*cfg), GFP_KERNEL); if (!cfg) return parent_rate; for (i = 0; i < regs_num; i++) cfg[i] = sprd_pll_read(pll, i); refin = pll_get_refin(pll); if (pinternal(pll, cfg, PLL_PREDIV)) refin = refin * 2; if (pwidth(pll, PLL_POSTDIV) && ((pll->fflag == 1 && pinternal(pll, cfg, PLL_POSTDIV)) || (!pll->fflag && !pinternal(pll, cfg, PLL_POSTDIV)))) refin = refin / 2; if (!pinternal(pll, cfg, PLL_DIV_S)) { rate = refin * pinternal_val(pll, cfg, PLL_N) * CLK_PLL_10M; } else { nint = pinternal_val(pll, cfg, PLL_NINT); if (pinternal(pll, cfg, PLL_SDM_EN)) kint = pinternal_val(pll, cfg, PLL_KINT); mask = pmask(pll, PLL_KINT); k1 = pll->k1; k2 = pll->k2; rate = DIV_ROUND_CLOSEST_ULL(refin * kint * k1, ((mask >> __ffs(mask)) + 1)) * k2 + refin * nint * CLK_PLL_1M; } kfree(cfg); return rate; } #define SPRD_PLL_WRITE_CHECK(pll, i, mask, val) \ (((sprd_pll_read(pll, i) & mask) == val) ? 0 : (-EFAULT)) static int _sprd_pll_set_rate(const struct sprd_pll *pll, unsigned long rate, unsigned long parent_rate) { struct reg_cfg *cfg; int ret = 0; u32 mask, shift, width, ibias_val, index; u32 regs_num = pll->regs_num, i = 0; unsigned long kint, nint; u64 tmp, refin, fvco = rate; cfg = kcalloc(regs_num, sizeof(*cfg), GFP_KERNEL); if (!cfg) return -ENOMEM; refin = pll_get_refin(pll); mask = pmask(pll, PLL_PREDIV); index = pindex(pll, PLL_PREDIV); width = pwidth(pll, PLL_PREDIV); if (width && (sprd_pll_read(pll, index) & mask)) refin = refin * 2; mask = pmask(pll, PLL_POSTDIV); index = pindex(pll, PLL_POSTDIV); width = pwidth(pll, PLL_POSTDIV); cfg[index].msk = mask; if (width && ((pll->fflag == 1 && fvco <= pll->fvco) || (pll->fflag == 0 && fvco > pll->fvco))) cfg[index].val |= mask; if (width && fvco <= pll->fvco) fvco = fvco * 2; mask = pmask(pll, PLL_DIV_S); index = pindex(pll, PLL_DIV_S); cfg[index].val |= mask; cfg[index].msk |= mask; mask = pmask(pll, PLL_SDM_EN); index = pindex(pll, PLL_SDM_EN); cfg[index].val |= mask; cfg[index].msk |= mask; nint = do_div(fvco, refin * CLK_PLL_1M); mask = pmask(pll, PLL_NINT); index = pindex(pll, PLL_NINT); shift = pshift(pll, PLL_NINT); cfg[index].val |= (nint << shift) & mask; cfg[index].msk |= mask; mask = pmask(pll, PLL_KINT); index = pindex(pll, PLL_KINT); width = pwidth(pll, PLL_KINT); shift = pshift(pll, PLL_KINT); tmp = fvco - refin * nint * CLK_PLL_1M; tmp = do_div(tmp, 10000) * ((mask >> shift) + 1); kint = DIV_ROUND_CLOSEST_ULL(tmp, refin * 100); cfg[index].val |= (kint << shift) & mask; cfg[index].msk |= mask; ibias_val = pll_get_ibias(fvco, pll->itable); mask = pmask(pll, PLL_IBIAS); index = pindex(pll, PLL_IBIAS); shift = pshift(pll, PLL_IBIAS); cfg[index].val |= ibias_val << shift & mask; cfg[index].msk |= mask; for (i = 0; i < regs_num; i++) { if (cfg[i].msk) { sprd_pll_write(pll, i, cfg[i].msk, cfg[i].val); ret |= SPRD_PLL_WRITE_CHECK(pll, i, cfg[i].msk, cfg[i].val); } } if (!ret) udelay(pll->udelay); kfree(cfg); return ret; } static unsigned long sprd_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct sprd_pll *pll = hw_to_sprd_pll(hw); return _sprd_pll_recalc_rate(pll, parent_rate); } static int sprd_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct sprd_pll *pll = hw_to_sprd_pll(hw); return _sprd_pll_set_rate(pll, rate, parent_rate); } static int sprd_pll_clk_prepare(struct clk_hw *hw) { struct sprd_pll *pll = hw_to_sprd_pll(hw); udelay(pll->udelay); return 0; } static long sprd_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { return rate; } const struct clk_ops sprd_pll_ops = { .prepare = sprd_pll_clk_prepare, .recalc_rate = sprd_pll_recalc_rate, .round_rate = sprd_pll_round_rate, .set_rate = sprd_pll_set_rate, }; EXPORT_SYMBOL_GPL(sprd_pll_ops);
linux-master
drivers/clk/sprd/pll.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <[email protected]> */ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include <soc/at91/atmel-sfr.h> #include "pmc.h" /* * The purpose of this clock is to generate a 480 MHz signal. A different * rate can't be configured. */ #define UTMI_RATE 480000000 struct clk_utmi { struct clk_hw hw; struct regmap *regmap_pmc; struct regmap *regmap_sfr; struct at91_clk_pms pms; }; #define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw) static inline bool clk_utmi_ready(struct regmap *regmap) { unsigned int status; regmap_read(regmap, AT91_PMC_SR, &status); return status & AT91_PMC_LOCKU; } static int clk_utmi_prepare(struct clk_hw *hw) { struct clk_hw *hw_parent; struct clk_utmi *utmi = to_clk_utmi(hw); unsigned int uckr = AT91_PMC_UPLLEN | AT91_PMC_UPLLCOUNT | AT91_PMC_BIASEN; unsigned int utmi_ref_clk_freq; unsigned long parent_rate; /* * If mainck rate is different from 12 MHz, we have to configure the * FREQ field of the SFR_UTMICKTRIM register to generate properly * the utmi clock. */ hw_parent = clk_hw_get_parent(hw); parent_rate = clk_hw_get_rate(hw_parent); switch (parent_rate) { case 12000000: utmi_ref_clk_freq = 0; break; case 16000000: utmi_ref_clk_freq = 1; break; case 24000000: utmi_ref_clk_freq = 2; break; /* * Not supported on SAMA5D2 but it's not an issue since MAINCK * maximum value is 24 MHz. */ case 48000000: utmi_ref_clk_freq = 3; break; default: pr_err("UTMICK: unsupported mainck rate\n"); return -EINVAL; } if (utmi->regmap_sfr) { regmap_update_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM, AT91_UTMICKTRIM_FREQ, utmi_ref_clk_freq); } else if (utmi_ref_clk_freq) { pr_err("UTMICK: sfr node required\n"); return -EINVAL; } regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, uckr, uckr); while (!clk_utmi_ready(utmi->regmap_pmc)) cpu_relax(); return 0; } static int clk_utmi_is_prepared(struct clk_hw *hw) { struct clk_utmi *utmi = to_clk_utmi(hw); return clk_utmi_ready(utmi->regmap_pmc); } static void clk_utmi_unprepare(struct clk_hw *hw) { struct clk_utmi *utmi = to_clk_utmi(hw); regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, AT91_PMC_UPLLEN, 0); } static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { /* UTMI clk rate is fixed. */ return UTMI_RATE; } static int clk_utmi_save_context(struct clk_hw *hw) { struct clk_utmi *utmi = to_clk_utmi(hw); utmi->pms.status = clk_utmi_is_prepared(hw); return 0; } static void clk_utmi_restore_context(struct clk_hw *hw) { struct clk_utmi *utmi = to_clk_utmi(hw); if (utmi->pms.status) clk_utmi_prepare(hw); } static const struct clk_ops utmi_ops = { .prepare = clk_utmi_prepare, .unprepare = clk_utmi_unprepare, .is_prepared = clk_utmi_is_prepared, .recalc_rate = clk_utmi_recalc_rate, .save_context = clk_utmi_save_context, .restore_context = clk_utmi_restore_context, }; static struct clk_hw * __init at91_clk_register_utmi_internal(struct regmap *regmap_pmc, struct regmap *regmap_sfr, const char *name, const char *parent_name, struct clk_hw *parent_hw, const struct clk_ops *ops, unsigned long flags) { struct clk_utmi *utmi; struct clk_hw *hw; struct clk_init_data init = {}; int ret; if (!(parent_name || parent_hw)) return ERR_PTR(-EINVAL); utmi = kzalloc(sizeof(*utmi), GFP_KERNEL); if (!utmi) return ERR_PTR(-ENOMEM); init.name = name; init.ops = ops; if (parent_hw) { init.parent_hws = parent_hw ? (const struct clk_hw **)&parent_hw : NULL; init.num_parents = parent_hw ? 1 : 0; } else { init.parent_names = parent_name ? &parent_name : NULL; init.num_parents = parent_name ? 1 : 0; } init.flags = flags; utmi->hw.init = &init; utmi->regmap_pmc = regmap_pmc; utmi->regmap_sfr = regmap_sfr; hw = &utmi->hw; ret = clk_hw_register(NULL, &utmi->hw); if (ret) { kfree(utmi); hw = ERR_PTR(ret); } return hw; } struct clk_hw * __init at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr, const char *name, const char *parent_name, struct clk_hw *parent_hw) { return at91_clk_register_utmi_internal(regmap_pmc, regmap_sfr, name, parent_name, parent_hw, &utmi_ops, CLK_SET_RATE_GATE); } static int clk_utmi_sama7g5_prepare(struct clk_hw *hw) { struct clk_utmi *utmi = to_clk_utmi(hw); struct clk_hw *hw_parent; unsigned long parent_rate; unsigned int val; hw_parent = clk_hw_get_parent(hw); parent_rate = clk_hw_get_rate(hw_parent); switch (parent_rate) { case 16000000: val = 0; break; case 20000000: val = 2; break; case 24000000: val = 3; break; case 32000000: val = 5; break; default: pr_err("UTMICK: unsupported main_xtal rate\n"); return -EINVAL; } regmap_write(utmi->regmap_pmc, AT91_PMC_XTALF, val); return 0; } static int clk_utmi_sama7g5_is_prepared(struct clk_hw *hw) { struct clk_utmi *utmi = to_clk_utmi(hw); struct clk_hw *hw_parent; unsigned long parent_rate; unsigned int val; hw_parent = clk_hw_get_parent(hw); parent_rate = clk_hw_get_rate(hw_parent); regmap_read(utmi->regmap_pmc, AT91_PMC_XTALF, &val); switch (val & 0x7) { case 0: if (parent_rate == 16000000) return 1; break; case 2: if (parent_rate == 20000000) return 1; break; case 3: if (parent_rate == 24000000) return 1; break; case 5: if (parent_rate == 32000000) return 1; break; default: break; } return 0; } static int clk_utmi_sama7g5_save_context(struct clk_hw *hw) { struct clk_utmi *utmi = to_clk_utmi(hw); utmi->pms.status = clk_utmi_sama7g5_is_prepared(hw); return 0; } static void clk_utmi_sama7g5_restore_context(struct clk_hw *hw) { struct clk_utmi *utmi = to_clk_utmi(hw); if (utmi->pms.status) clk_utmi_sama7g5_prepare(hw); } static const struct clk_ops sama7g5_utmi_ops = { .prepare = clk_utmi_sama7g5_prepare, .is_prepared = clk_utmi_sama7g5_is_prepared, .recalc_rate = clk_utmi_recalc_rate, .save_context = clk_utmi_sama7g5_save_context, .restore_context = clk_utmi_sama7g5_restore_context, }; struct clk_hw * __init at91_clk_sama7g5_register_utmi(struct regmap *regmap_pmc, const char *name, const char *parent_name, struct clk_hw *parent_hw) { return at91_clk_register_utmi_internal(regmap_pmc, NULL, name, parent_name, parent_hw, &sama7g5_utmi_ops, 0); }
linux-master
drivers/clk/at91/clk-utmi.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <[email protected]> */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/mfd/syscon.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/syscore_ops.h> #include <asm/proc-fns.h> #include "pmc.h" #define PMC_MAX_IDS 128 #define PMC_MAX_PCKS 8 int of_at91_get_clk_range(struct device_node *np, const char *propname, struct clk_range *range) { u32 min, max; int ret; ret = of_property_read_u32_index(np, propname, 0, &min); if (ret) return ret; ret = of_property_read_u32_index(np, propname, 1, &max); if (ret) return ret; if (range) { range->min = min; range->max = max; } return 0; } EXPORT_SYMBOL_GPL(of_at91_get_clk_range); struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data) { unsigned int type = clkspec->args[0]; unsigned int idx = clkspec->args[1]; struct pmc_data *pmc_data = data; switch (type) { case PMC_TYPE_CORE: if (idx < pmc_data->ncore) return pmc_data->chws[idx]; break; case PMC_TYPE_SYSTEM: if (idx < pmc_data->nsystem) return pmc_data->shws[idx]; break; case PMC_TYPE_PERIPHERAL: if (idx < pmc_data->nperiph) return pmc_data->phws[idx]; break; case PMC_TYPE_GCK: if (idx < pmc_data->ngck) return pmc_data->ghws[idx]; break; case PMC_TYPE_PROGRAMMABLE: if (idx < pmc_data->npck) return pmc_data->pchws[idx]; break; default: break; } pr_err("%s: invalid type (%u) or index (%u)\n", __func__, type, idx); return ERR_PTR(-EINVAL); } struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, unsigned int nperiph, unsigned int ngck, unsigned int npck) { unsigned int num_clks = ncore + nsystem + nperiph + ngck + npck; struct pmc_data *pmc_data; pmc_data = kzalloc(struct_size(pmc_data, hwtable, num_clks), GFP_KERNEL); if (!pmc_data) return NULL; pmc_data->ncore = ncore; pmc_data->chws = pmc_data->hwtable; pmc_data->nsystem = nsystem; pmc_data->shws = pmc_data->chws + ncore; pmc_data->nperiph = nperiph; pmc_data->phws = pmc_data->shws + nsystem; pmc_data->ngck = ngck; pmc_data->ghws = pmc_data->phws + nperiph; pmc_data->npck = npck; pmc_data->pchws = pmc_data->ghws + ngck; return pmc_data; } #ifdef CONFIG_PM /* Address in SECURAM that say if we suspend to backup mode. */ static void __iomem *at91_pmc_backup_suspend; static int at91_pmc_suspend(void) { unsigned int backup; if (!at91_pmc_backup_suspend) return 0; backup = readl_relaxed(at91_pmc_backup_suspend); if (!backup) return 0; return clk_save_context(); } static void at91_pmc_resume(void) { unsigned int backup; if (!at91_pmc_backup_suspend) return; backup = readl_relaxed(at91_pmc_backup_suspend); if (!backup) return; clk_restore_context(); } static struct syscore_ops pmc_syscore_ops = { .suspend = at91_pmc_suspend, .resume = at91_pmc_resume, }; static const struct of_device_id pmc_dt_ids[] = { { .compatible = "atmel,sama5d2-pmc" }, { .compatible = "microchip,sama7g5-pmc", }, { /* sentinel */ } }; static int __init pmc_register_ops(void) { struct device_node *np; np = of_find_matching_node(NULL, pmc_dt_ids); if (!np) return -ENODEV; if (!of_device_is_available(np)) { of_node_put(np); return -ENODEV; } of_node_put(np); np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); if (!np) return -ENODEV; if (!of_device_is_available(np)) { of_node_put(np); return -ENODEV; } of_node_put(np); at91_pmc_backup_suspend = of_iomap(np, 0); if (!at91_pmc_backup_suspend) { pr_warn("%s(): unable to map securam\n", __func__); return -ENOMEM; } register_syscore_ops(&pmc_syscore_ops); return 0; } /* This has to happen before arch_initcall because of the tcb_clksrc driver */ postcore_initcall(pmc_register_ops); #endif
linux-master
drivers/clk/at91/pmc.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <[email protected]> */ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "pmc.h" #define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw) struct clk_plldiv { struct clk_hw hw; struct regmap *regmap; }; static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_plldiv *plldiv = to_clk_plldiv(hw); unsigned int mckr; regmap_read(plldiv->regmap, AT91_PMC_MCKR, &mckr); if (mckr & AT91_PMC_PLLADIV2) return parent_rate / 2; return parent_rate; } static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { unsigned long div; if (rate > *parent_rate) return *parent_rate; div = *parent_rate / 2; if (rate < div) return div; if (rate - div < *parent_rate - rate) return div; return *parent_rate; } static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_plldiv *plldiv = to_clk_plldiv(hw); if ((parent_rate != rate) && (parent_rate / 2 != rate)) return -EINVAL; regmap_update_bits(plldiv->regmap, AT91_PMC_MCKR, AT91_PMC_PLLADIV2, parent_rate != rate ? AT91_PMC_PLLADIV2 : 0); return 0; } static const struct clk_ops plldiv_ops = { .recalc_rate = clk_plldiv_recalc_rate, .round_rate = clk_plldiv_round_rate, .set_rate = clk_plldiv_set_rate, }; struct clk_hw * __init at91_clk_register_plldiv(struct regmap *regmap, const char *name, const char *parent_name) { struct clk_plldiv *plldiv; struct clk_hw *hw; struct clk_init_data init; int ret; plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL); if (!plldiv) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &plldiv_ops; init.parent_names = parent_name ? &parent_name : NULL; init.num_parents = parent_name ? 1 : 0; init.flags = CLK_SET_RATE_GATE; plldiv->hw.init = &init; plldiv->regmap = regmap; hw = &plldiv->hw; ret = clk_hw_register(NULL, &plldiv->hw); if (ret) { kfree(plldiv); hw = ERR_PTR(ret); } return hw; }
linux-master
drivers/clk/at91/clk-plldiv.c
// SPDX-License-Identifier: GPL-2.0 #include <linux/clk-provider.h> #include <linux/mfd/syscon.h> #include <linux/slab.h> #include <dt-bindings/clock/at91.h> #include "pmc.h" static DEFINE_SPINLOCK(at91sam9n12_mck_lock); static const struct clk_master_characteristics mck_characteristics = { .output = { .min = 0, .max = 133333333 }, .divisors = { 1, 2, 4, 3 }, .have_div3_pres = 1, }; static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 }; static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 }; static const struct clk_range plla_outputs[] = { { .min = 745000000, .max = 800000000 }, { .min = 695000000, .max = 750000000 }, { .min = 645000000, .max = 700000000 }, { .min = 595000000, .max = 650000000 }, { .min = 545000000, .max = 600000000 }, { .min = 495000000, .max = 555000000 }, { .min = 445000000, .max = 500000000 }, { .min = 400000000, .max = 450000000 }, }; static const struct clk_pll_characteristics plla_characteristics = { .input = { .min = 2000000, .max = 32000000 }, .num_output = ARRAY_SIZE(plla_outputs), .output = plla_outputs, .icpll = plla_icpll, .out = plla_out, }; static u8 pllb_out[] = { 0 }; static const struct clk_range pllb_outputs[] = { { .min = 30000000, .max = 100000000 }, }; static const struct clk_pll_characteristics pllb_characteristics = { .input = { .min = 2000000, .max = 32000000 }, .num_output = ARRAY_SIZE(pllb_outputs), .output = pllb_outputs, .out = pllb_out, }; static const struct { char *n; char *p; unsigned long flags; u8 id; } at91sam9n12_systemck[] = { /* * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, { .n = "lcdck", .p = "masterck_div", .id = 3 }, { .n = "uhpck", .p = "usbck", .id = 6 }, { .n = "udpck", .p = "usbck", .id = 7 }, { .n = "pck0", .p = "prog0", .id = 8 }, { .n = "pck1", .p = "prog1", .id = 9 }, }; static const struct clk_pcr_layout at91sam9n12_pcr_layout = { .offset = 0x10c, .cmd = BIT(12), .pid_mask = GENMASK(5, 0), .div_mask = GENMASK(17, 16), }; struct pck { char *n; u8 id; }; static const struct pck at91sam9n12_periphck[] = { { .n = "pioAB_clk", .id = 2, }, { .n = "pioCD_clk", .id = 3, }, { .n = "fuse_clk", .id = 4, }, { .n = "usart0_clk", .id = 5, }, { .n = "usart1_clk", .id = 6, }, { .n = "usart2_clk", .id = 7, }, { .n = "usart3_clk", .id = 8, }, { .n = "twi0_clk", .id = 9, }, { .n = "twi1_clk", .id = 10, }, { .n = "mci0_clk", .id = 12, }, { .n = "spi0_clk", .id = 13, }, { .n = "spi1_clk", .id = 14, }, { .n = "uart0_clk", .id = 15, }, { .n = "uart1_clk", .id = 16, }, { .n = "tcb_clk", .id = 17, }, { .n = "pwm_clk", .id = 18, }, { .n = "adc_clk", .id = 19, }, { .n = "dma0_clk", .id = 20, }, { .n = "uhphs_clk", .id = 22, }, { .n = "udphs_clk", .id = 23, }, { .n = "lcdc_clk", .id = 25, }, { .n = "sha_clk", .id = 27, }, { .n = "ssc0_clk", .id = 28, }, { .n = "aes_clk", .id = 29, }, { .n = "trng_clk", .id = 30, }, }; static void __init at91sam9n12_pmc_setup(struct device_node *np) { struct clk_range range = CLK_RANGE(0, 0); const char *slck_name, *mainxtal_name; struct pmc_data *at91sam9n12_pmc; const char *parent_names[6]; struct regmap *regmap; struct clk_hw *hw; int i; bool bypass; i = of_property_match_string(np, "clock-names", "slow_clk"); if (i < 0) return; slck_name = of_clk_get_parent_name(np, i); i = of_property_match_string(np, "clock-names", "main_xtal"); if (i < 0) return; mainxtal_name = of_clk_get_parent_name(np, i); regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; at91sam9n12_pmc = pmc_data_allocate(PMC_PLLBCK + 1, nck(at91sam9n12_systemck), 31, 0, 2); if (!at91sam9n12_pmc) return; hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 50000000); if (IS_ERR(hw)) goto err_free; bypass = of_property_read_bool(np, "atmel,osc-bypass"); hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, bypass); if (IS_ERR(hw)) goto err_free; parent_names[0] = "main_rc_osc"; parent_names[1] = "main_osc"; hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2); if (IS_ERR(hw)) goto err_free; at91sam9n12_pmc->chws[PMC_MAIN] = hw; hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, &at91rm9200_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); if (IS_ERR(hw)) goto err_free; at91sam9n12_pmc->chws[PMC_PLLACK] = hw; hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1, &at91rm9200_pll_layout, &pllb_characteristics); if (IS_ERR(hw)) goto err_free; at91sam9n12_pmc->chws[PMC_PLLBCK] = hw; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "pllbck"; hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, parent_names, NULL, &at91sam9x5_master_layout, &mck_characteristics, &at91sam9n12_mck_lock); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_master_div(regmap, "masterck_div", "masterck_pres", NULL, &at91sam9x5_master_layout, &mck_characteristics, &at91sam9n12_mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; at91sam9n12_pmc->chws[PMC_MCK] = hw; hw = at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck"); if (IS_ERR(hw)) goto err_free; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "pllbck"; parent_names[4] = "masterck_div"; for (i = 0; i < 2; i++) { char name[6]; snprintf(name, sizeof(name), "prog%d", i); hw = at91_clk_register_programmable(regmap, name, parent_names, NULL, 5, i, &at91sam9x5_programmable_layout, NULL); if (IS_ERR(hw)) goto err_free; at91sam9n12_pmc->pchws[i] = hw; } for (i = 0; i < ARRAY_SIZE(at91sam9n12_systemck); i++) { hw = at91_clk_register_system(regmap, at91sam9n12_systemck[i].n, at91sam9n12_systemck[i].p, NULL, at91sam9n12_systemck[i].id, at91sam9n12_systemck[i].flags); if (IS_ERR(hw)) goto err_free; at91sam9n12_pmc->shws[at91sam9n12_systemck[i].id] = hw; } for (i = 0; i < ARRAY_SIZE(at91sam9n12_periphck); i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &at91sam9n12_pcr_layout, at91sam9n12_periphck[i].n, "masterck_div", NULL, at91sam9n12_periphck[i].id, &range, INT_MIN, 0); if (IS_ERR(hw)) goto err_free; at91sam9n12_pmc->phws[at91sam9n12_periphck[i].id] = hw; } of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9n12_pmc); return; err_free: kfree(at91sam9n12_pmc); } /* * The TCB is used as the clocksource so its clock is needed early. This means * this can't be a platform driver. */ CLK_OF_DECLARE(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", at91sam9n12_pmc_setup);
linux-master
drivers/clk/at91/at91sam9n12.c
// SPDX-License-Identifier: GPL-2.0 #include <linux/clk-provider.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include <linux/slab.h> #include "pmc.h" #define MASTER_SOURCE_MAX 4 #define PERIPHERAL_AT91RM9200 0 #define PERIPHERAL_AT91SAM9X5 1 #define PERIPHERAL_MAX 64 #define PERIPHERAL_ID_MIN 2 #define PROG_SOURCE_MAX 5 #define PROG_ID_MAX 7 #define SYSTEM_MAX_ID 31 #define GCK_INDEX_DT_AUDIO_PLL 5 static DEFINE_SPINLOCK(mck_lock); #ifdef CONFIG_HAVE_AT91_AUDIO_PLL static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np) { struct clk_hw *hw; const char *name = np->name; const char *parent_name; struct regmap *regmap; struct device_node *parent_np; parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; parent_name = of_clk_get_parent_name(np, 0); hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name); if (IS_ERR(hw)) return; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); } CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup, "atmel,sama5d2-clk-audio-pll-frac", of_sama5d2_clk_audio_pll_frac_setup); static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np) { struct clk_hw *hw; const char *name = np->name; const char *parent_name; struct regmap *regmap; struct device_node *parent_np; parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; parent_name = of_clk_get_parent_name(np, 0); hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name); if (IS_ERR(hw)) return; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); } CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup, "atmel,sama5d2-clk-audio-pll-pad", of_sama5d2_clk_audio_pll_pad_setup); static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np) { struct clk_hw *hw; const char *name = np->name; const char *parent_name; struct regmap *regmap; struct device_node *parent_np; parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; parent_name = of_clk_get_parent_name(np, 0); hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name); if (IS_ERR(hw)) return; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); } CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup, "atmel,sama5d2-clk-audio-pll-pmc", of_sama5d2_clk_audio_pll_pmc_setup); #endif /* CONFIG_HAVE_AT91_AUDIO_PLL */ static const struct clk_pcr_layout dt_pcr_layout = { .offset = 0x10c, .cmd = BIT(12), .pid_mask = GENMASK(5, 0), .div_mask = GENMASK(17, 16), .gckcss_mask = GENMASK(10, 8), }; #ifdef CONFIG_HAVE_AT91_GENERATED_CLK #define GENERATED_SOURCE_MAX 6 #define GCK_ID_I2S0 54 #define GCK_ID_I2S1 55 #define GCK_ID_CLASSD 59 static void __init of_sama5d2_clk_generated_setup(struct device_node *np) { int num; u32 id; const char *name; struct clk_hw *hw; unsigned int num_parents; const char *parent_names[GENERATED_SOURCE_MAX]; struct device_node *gcknp, *parent_np; struct clk_range range = CLK_RANGE(0, 0); struct regmap *regmap; num_parents = of_clk_get_parent_count(np); if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX) return; of_clk_parent_fill(np, parent_names, num_parents); num = of_get_child_count(np); if (!num || num > PERIPHERAL_MAX) return; parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; for_each_child_of_node(np, gcknp) { int chg_pid = INT_MIN; if (of_property_read_u32(gcknp, "reg", &id)) continue; if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX) continue; if (of_property_read_string(np, "clock-output-names", &name)) name = gcknp->name; of_at91_get_clk_range(gcknp, "atmel,clk-output-range", &range); if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") && (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 || id == GCK_ID_CLASSD)) chg_pid = GCK_INDEX_DT_AUDIO_PLL; hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, &dt_pcr_layout, name, parent_names, NULL, NULL, num_parents, id, &range, chg_pid); if (IS_ERR(hw)) continue; of_clk_add_hw_provider(gcknp, of_clk_hw_simple_get, hw); } } CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated", of_sama5d2_clk_generated_setup); #endif /* CONFIG_HAVE_AT91_GENERATED_CLK */ #ifdef CONFIG_HAVE_AT91_H32MX static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np) { struct clk_hw *hw; const char *name = np->name; const char *parent_name; struct regmap *regmap; struct device_node *parent_np; parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; parent_name = of_clk_get_parent_name(np, 0); hw = at91_clk_register_h32mx(regmap, name, parent_name); if (IS_ERR(hw)) return; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); } CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx", of_sama5d4_clk_h32mx_setup); #endif /* CONFIG_HAVE_AT91_H32MX */ #ifdef CONFIG_HAVE_AT91_I2S_MUX_CLK #define I2S_BUS_NR 2 static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np) { struct regmap *regmap_sfr; u8 bus_id; const char *parent_names[2]; struct device_node *i2s_mux_np; struct clk_hw *hw; int ret; regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr"); if (IS_ERR(regmap_sfr)) return; for_each_child_of_node(np, i2s_mux_np) { if (of_property_read_u8(i2s_mux_np, "reg", &bus_id)) continue; if (bus_id > I2S_BUS_NR) continue; ret = of_clk_parent_fill(i2s_mux_np, parent_names, 2); if (ret != 2) continue; hw = at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name, parent_names, 2, bus_id); if (IS_ERR(hw)) continue; of_clk_add_hw_provider(i2s_mux_np, of_clk_hw_simple_get, hw); } } CLK_OF_DECLARE(sama5d2_clk_i2s_mux, "atmel,sama5d2-clk-i2s-mux", of_sama5d2_clk_i2s_mux_setup); #endif /* CONFIG_HAVE_AT91_I2S_MUX_CLK */ static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np) { struct clk_hw *hw; const char *name = np->name; const char *parent_name; struct regmap *regmap; bool bypass; struct device_node *parent_np; of_property_read_string(np, "clock-output-names", &name); bypass = of_property_read_bool(np, "atmel,osc-bypass"); parent_name = of_clk_get_parent_name(np, 0); parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; hw = at91_clk_register_main_osc(regmap, name, parent_name, NULL, bypass); if (IS_ERR(hw)) return; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); } CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc", of_at91rm9200_clk_main_osc_setup); static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np) { struct clk_hw *hw; u32 frequency = 0; u32 accuracy = 0; const char *name = np->name; struct regmap *regmap; struct device_node *parent_np; of_property_read_string(np, "clock-output-names", &name); of_property_read_u32(np, "clock-frequency", &frequency); of_property_read_u32(np, "clock-accuracy", &accuracy); parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; hw = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy); if (IS_ERR(hw)) return; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); } CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc", of_at91sam9x5_clk_main_rc_osc_setup); static void __init of_at91rm9200_clk_main_setup(struct device_node *np) { struct clk_hw *hw; const char *parent_name; const char *name = np->name; struct regmap *regmap; struct device_node *parent_np; parent_name = of_clk_get_parent_name(np, 0); of_property_read_string(np, "clock-output-names", &name); parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; hw = at91_clk_register_rm9200_main(regmap, name, parent_name, NULL); if (IS_ERR(hw)) return; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); } CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main", of_at91rm9200_clk_main_setup); static void __init of_at91sam9x5_clk_main_setup(struct device_node *np) { struct clk_hw *hw; const char *parent_names[2]; unsigned int num_parents; const char *name = np->name; struct regmap *regmap; struct device_node *parent_np; num_parents = of_clk_get_parent_count(np); if (num_parents == 0 || num_parents > 2) return; of_clk_parent_fill(np, parent_names, num_parents); parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; of_property_read_string(np, "clock-output-names", &name); hw = at91_clk_register_sam9x5_main(regmap, name, parent_names, NULL, num_parents); if (IS_ERR(hw)) return; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); } CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main", of_at91sam9x5_clk_main_setup); static struct clk_master_characteristics * __init of_at91_clk_master_get_characteristics(struct device_node *np) { struct clk_master_characteristics *characteristics; characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL); if (!characteristics) return NULL; if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output)) goto out_free_characteristics; of_property_read_u32_array(np, "atmel,clk-divisors", characteristics->divisors, 4); characteristics->have_div3_pres = of_property_read_bool(np, "atmel,master-clk-have-div3-pres"); return characteristics; out_free_characteristics: kfree(characteristics); return NULL; } static void __init of_at91_clk_master_setup(struct device_node *np, const struct clk_master_layout *layout) { struct clk_hw *hw; unsigned int num_parents; const char *parent_names[MASTER_SOURCE_MAX]; const char *name = np->name; struct clk_master_characteristics *characteristics; struct regmap *regmap; struct device_node *parent_np; num_parents = of_clk_get_parent_count(np); if (num_parents == 0 || num_parents > MASTER_SOURCE_MAX) return; of_clk_parent_fill(np, parent_names, num_parents); of_property_read_string(np, "clock-output-names", &name); characteristics = of_at91_clk_master_get_characteristics(np); if (!characteristics) return; parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents, parent_names, NULL, layout, characteristics, &mck_lock); if (IS_ERR(hw)) goto out_free_characteristics; hw = at91_clk_register_master_div(regmap, name, "masterck_pres", NULL, layout, characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto out_free_characteristics; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); return; out_free_characteristics: kfree(characteristics); } static void __init of_at91rm9200_clk_master_setup(struct device_node *np) { of_at91_clk_master_setup(np, &at91rm9200_master_layout); } CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master", of_at91rm9200_clk_master_setup); static void __init of_at91sam9x5_clk_master_setup(struct device_node *np) { of_at91_clk_master_setup(np, &at91sam9x5_master_layout); } CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master", of_at91sam9x5_clk_master_setup); static void __init of_at91_clk_periph_setup(struct device_node *np, u8 type) { int num; u32 id; struct clk_hw *hw; const char *parent_name; const char *name; struct device_node *periphclknp; struct regmap *regmap; struct device_node *parent_np; parent_name = of_clk_get_parent_name(np, 0); if (!parent_name) return; num = of_get_child_count(np); if (!num || num > PERIPHERAL_MAX) return; parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; for_each_child_of_node(np, periphclknp) { if (of_property_read_u32(periphclknp, "reg", &id)) continue; if (id >= PERIPHERAL_MAX) continue; if (of_property_read_string(np, "clock-output-names", &name)) name = periphclknp->name; if (type == PERIPHERAL_AT91RM9200) { hw = at91_clk_register_peripheral(regmap, name, parent_name, NULL, id); } else { struct clk_range range = CLK_RANGE(0, 0); unsigned long flags = 0; of_at91_get_clk_range(periphclknp, "atmel,clk-output-range", &range); /* * mpddr_clk feed DDR controller and is enabled by * bootloader thus we need to keep it enabled in case * there is no Linux consumer for it. */ if (!strcmp(periphclknp->name, "mpddr_clk")) flags = CLK_IS_CRITICAL; hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &dt_pcr_layout, name, parent_name, NULL, id, &range, INT_MIN, flags); } if (IS_ERR(hw)) continue; of_clk_add_hw_provider(periphclknp, of_clk_hw_simple_get, hw); } } static void __init of_at91rm9200_clk_periph_setup(struct device_node *np) { of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200); } CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral", of_at91rm9200_clk_periph_setup); static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np) { of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5); } CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral", of_at91sam9x5_clk_periph_setup); static struct clk_pll_characteristics * __init of_at91_clk_pll_get_characteristics(struct device_node *np) { int i; int offset; u32 tmp; int num_output; u32 num_cells; struct clk_range input; struct clk_range *output; u8 *out = NULL; u16 *icpll = NULL; struct clk_pll_characteristics *characteristics; if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input)) return NULL; if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells", &num_cells)) return NULL; if (num_cells < 2 || num_cells > 4) return NULL; if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp)) return NULL; num_output = tmp / (sizeof(u32) * num_cells); characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL); if (!characteristics) return NULL; output = kcalloc(num_output, sizeof(*output), GFP_KERNEL); if (!output) goto out_free_characteristics; if (num_cells > 2) { out = kcalloc(num_output, sizeof(*out), GFP_KERNEL); if (!out) goto out_free_output; } if (num_cells > 3) { icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL); if (!icpll) goto out_free_output; } for (i = 0; i < num_output; i++) { offset = i * num_cells; if (of_property_read_u32_index(np, "atmel,pll-clk-output-ranges", offset, &tmp)) goto out_free_output; output[i].min = tmp; if (of_property_read_u32_index(np, "atmel,pll-clk-output-ranges", offset + 1, &tmp)) goto out_free_output; output[i].max = tmp; if (num_cells == 2) continue; if (of_property_read_u32_index(np, "atmel,pll-clk-output-ranges", offset + 2, &tmp)) goto out_free_output; out[i] = tmp; if (num_cells == 3) continue; if (of_property_read_u32_index(np, "atmel,pll-clk-output-ranges", offset + 3, &tmp)) goto out_free_output; icpll[i] = tmp; } characteristics->input = input; characteristics->num_output = num_output; characteristics->output = output; characteristics->out = out; characteristics->icpll = icpll; return characteristics; out_free_output: kfree(icpll); kfree(out); kfree(output); out_free_characteristics: kfree(characteristics); return NULL; } static void __init of_at91_clk_pll_setup(struct device_node *np, const struct clk_pll_layout *layout) { u32 id; struct clk_hw *hw; struct regmap *regmap; const char *parent_name; const char *name = np->name; struct device_node *parent_np; struct clk_pll_characteristics *characteristics; if (of_property_read_u32(np, "reg", &id)) return; parent_name = of_clk_get_parent_name(np, 0); of_property_read_string(np, "clock-output-names", &name); parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; characteristics = of_at91_clk_pll_get_characteristics(np); if (!characteristics) return; hw = at91_clk_register_pll(regmap, name, parent_name, id, layout, characteristics); if (IS_ERR(hw)) goto out_free_characteristics; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); return; out_free_characteristics: kfree(characteristics); } static void __init of_at91rm9200_clk_pll_setup(struct device_node *np) { of_at91_clk_pll_setup(np, &at91rm9200_pll_layout); } CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll", of_at91rm9200_clk_pll_setup); static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np) { of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout); } CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll", of_at91sam9g45_clk_pll_setup); static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np) { of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout); } CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb", of_at91sam9g20_clk_pllb_setup); static void __init of_sama5d3_clk_pll_setup(struct device_node *np) { of_at91_clk_pll_setup(np, &sama5d3_pll_layout); } CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll", of_sama5d3_clk_pll_setup); static void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np) { struct clk_hw *hw; const char *parent_name; const char *name = np->name; struct regmap *regmap; struct device_node *parent_np; parent_name = of_clk_get_parent_name(np, 0); of_property_read_string(np, "clock-output-names", &name); parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; hw = at91_clk_register_plldiv(regmap, name, parent_name); if (IS_ERR(hw)) return; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); } CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv", of_at91sam9x5_clk_plldiv_setup); static void __init of_at91_clk_prog_setup(struct device_node *np, const struct clk_programmable_layout *layout, u32 *mux_table) { int num; u32 id; struct clk_hw *hw; unsigned int num_parents; const char *parent_names[PROG_SOURCE_MAX]; const char *name; struct device_node *progclknp, *parent_np; struct regmap *regmap; num_parents = of_clk_get_parent_count(np); if (num_parents == 0 || num_parents > PROG_SOURCE_MAX) return; of_clk_parent_fill(np, parent_names, num_parents); num = of_get_child_count(np); if (!num || num > (PROG_ID_MAX + 1)) return; parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; for_each_child_of_node(np, progclknp) { if (of_property_read_u32(progclknp, "reg", &id)) continue; if (of_property_read_string(np, "clock-output-names", &name)) name = progclknp->name; hw = at91_clk_register_programmable(regmap, name, parent_names, NULL, num_parents, id, layout, mux_table); if (IS_ERR(hw)) continue; of_clk_add_hw_provider(progclknp, of_clk_hw_simple_get, hw); } } static void __init of_at91rm9200_clk_prog_setup(struct device_node *np) { of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout, NULL); } CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable", of_at91rm9200_clk_prog_setup); static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np) { of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout, NULL); } CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable", of_at91sam9g45_clk_prog_setup); static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np) { of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout, NULL); } CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable", of_at91sam9x5_clk_prog_setup); static void __init of_at91sam9260_clk_slow_setup(struct device_node *np) { struct clk_hw *hw; const char *parent_names[2]; unsigned int num_parents; const char *name = np->name; struct regmap *regmap; struct device_node *parent_np; num_parents = of_clk_get_parent_count(np); if (num_parents != 2) return; of_clk_parent_fill(np, parent_names, num_parents); parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; of_property_read_string(np, "clock-output-names", &name); hw = at91_clk_register_sam9260_slow(regmap, name, parent_names, num_parents); if (IS_ERR(hw)) return; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); } CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow", of_at91sam9260_clk_slow_setup); #ifdef CONFIG_HAVE_AT91_SMD #define SMD_SOURCE_MAX 2 static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np) { struct clk_hw *hw; unsigned int num_parents; const char *parent_names[SMD_SOURCE_MAX]; const char *name = np->name; struct regmap *regmap; struct device_node *parent_np; num_parents = of_clk_get_parent_count(np); if (num_parents == 0 || num_parents > SMD_SOURCE_MAX) return; of_clk_parent_fill(np, parent_names, num_parents); of_property_read_string(np, "clock-output-names", &name); parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; hw = at91sam9x5_clk_register_smd(regmap, name, parent_names, num_parents); if (IS_ERR(hw)) return; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); } CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd", of_at91sam9x5_clk_smd_setup); #endif /* CONFIG_HAVE_AT91_SMD */ static void __init of_at91rm9200_clk_sys_setup(struct device_node *np) { int num; u32 id; struct clk_hw *hw; const char *name; struct device_node *sysclknp, *parent_np; const char *parent_name; struct regmap *regmap; num = of_get_child_count(np); if (num > (SYSTEM_MAX_ID + 1)) return; parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; for_each_child_of_node(np, sysclknp) { unsigned long flags = 0; if (of_property_read_u32(sysclknp, "reg", &id)) continue; if (of_property_read_string(np, "clock-output-names", &name)) name = sysclknp->name; parent_name = of_clk_get_parent_name(sysclknp, 0); /* * ddrck feeds DDR controller and is enabled by bootloader thus * we need to keep it enabled in case there is no Linux consumer * for it. */ if (!strcmp(sysclknp->name, "ddrck")) flags = CLK_IS_CRITICAL; hw = at91_clk_register_system(regmap, name, parent_name, NULL, id, flags); if (IS_ERR(hw)) continue; of_clk_add_hw_provider(sysclknp, of_clk_hw_simple_get, hw); } } CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system", of_at91rm9200_clk_sys_setup); #ifdef CONFIG_HAVE_AT91_USB_CLK #define USB_SOURCE_MAX 2 static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np) { struct clk_hw *hw; unsigned int num_parents; const char *parent_names[USB_SOURCE_MAX]; const char *name = np->name; struct regmap *regmap; struct device_node *parent_np; num_parents = of_clk_get_parent_count(np); if (num_parents == 0 || num_parents > USB_SOURCE_MAX) return; of_clk_parent_fill(np, parent_names, num_parents); of_property_read_string(np, "clock-output-names", &name); parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; hw = at91sam9x5_clk_register_usb(regmap, name, parent_names, num_parents); if (IS_ERR(hw)) return; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); } CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb", of_at91sam9x5_clk_usb_setup); static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np) { struct clk_hw *hw; const char *parent_name; const char *name = np->name; struct regmap *regmap; struct device_node *parent_np; parent_name = of_clk_get_parent_name(np, 0); if (!parent_name) return; of_property_read_string(np, "clock-output-names", &name); parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; hw = at91sam9n12_clk_register_usb(regmap, name, parent_name); if (IS_ERR(hw)) return; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); } CLK_OF_DECLARE(at91sam9n12_clk_usb, "atmel,at91sam9n12-clk-usb", of_at91sam9n12_clk_usb_setup); static void __init of_at91rm9200_clk_usb_setup(struct device_node *np) { struct clk_hw *hw; const char *parent_name; const char *name = np->name; u32 divisors[4] = {0, 0, 0, 0}; struct regmap *regmap; struct device_node *parent_np; parent_name = of_clk_get_parent_name(np, 0); if (!parent_name) return; of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4); if (!divisors[0]) return; of_property_read_string(np, "clock-output-names", &name); parent_np = of_get_parent(np); regmap = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap)) return; hw = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors); if (IS_ERR(hw)) return; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); } CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb", of_at91rm9200_clk_usb_setup); #endif /* CONFIG_HAVE_AT91_USB_CLK */ #ifdef CONFIG_HAVE_AT91_UTMI static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np) { struct clk_hw *hw; const char *parent_name; const char *name = np->name; struct regmap *regmap_pmc, *regmap_sfr; struct device_node *parent_np; parent_name = of_clk_get_parent_name(np, 0); of_property_read_string(np, "clock-output-names", &name); parent_np = of_get_parent(np); regmap_pmc = syscon_node_to_regmap(parent_np); of_node_put(parent_np); if (IS_ERR(regmap_pmc)) return; /* * If the device supports different mainck rates, this value has to be * set in the UTMI Clock Trimming register. * - 9x5: mainck supports several rates but it is indicated that a * 12 MHz is needed in case of USB. * - sama5d3 and sama5d2: mainck supports several rates. Configuring * the FREQ field of the UTMI Clock Trimming register is mandatory. * - sama5d4: mainck is at 12 MHz. * * We only need to retrieve sama5d3 or sama5d2 sfr regmap. */ regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr"); if (IS_ERR(regmap_sfr)) { regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr"); if (IS_ERR(regmap_sfr)) regmap_sfr = NULL; } hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name, NULL); if (IS_ERR(hw)) return; of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); } CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi", of_at91sam9x5_clk_utmi_setup); #endif /* CONFIG_HAVE_AT91_UTMI */
linux-master
drivers/clk/at91/dt-compat.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <[email protected]> */ #include <linux/bitops.h> #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "pmc.h" DEFINE_SPINLOCK(pmc_pcr_lock); #define PERIPHERAL_ID_MIN 2 #define PERIPHERAL_ID_MAX 31 #define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX)) #define PERIPHERAL_MAX_SHIFT 3 struct clk_peripheral { struct clk_hw hw; struct regmap *regmap; u32 id; }; #define to_clk_peripheral(hw) container_of(hw, struct clk_peripheral, hw) struct clk_sam9x5_peripheral { struct clk_hw hw; struct regmap *regmap; struct clk_range range; spinlock_t *lock; u32 id; u32 div; const struct clk_pcr_layout *layout; struct at91_clk_pms pms; bool auto_div; int chg_pid; }; #define to_clk_sam9x5_peripheral(hw) \ container_of(hw, struct clk_sam9x5_peripheral, hw) static int clk_peripheral_enable(struct clk_hw *hw) { struct clk_peripheral *periph = to_clk_peripheral(hw); int offset = AT91_PMC_PCER; u32 id = periph->id; if (id < PERIPHERAL_ID_MIN) return 0; if (id > PERIPHERAL_ID_MAX) offset = AT91_PMC_PCER1; regmap_write(periph->regmap, offset, PERIPHERAL_MASK(id)); return 0; } static void clk_peripheral_disable(struct clk_hw *hw) { struct clk_peripheral *periph = to_clk_peripheral(hw); int offset = AT91_PMC_PCDR; u32 id = periph->id; if (id < PERIPHERAL_ID_MIN) return; if (id > PERIPHERAL_ID_MAX) offset = AT91_PMC_PCDR1; regmap_write(periph->regmap, offset, PERIPHERAL_MASK(id)); } static int clk_peripheral_is_enabled(struct clk_hw *hw) { struct clk_peripheral *periph = to_clk_peripheral(hw); int offset = AT91_PMC_PCSR; unsigned int status; u32 id = periph->id; if (id < PERIPHERAL_ID_MIN) return 1; if (id > PERIPHERAL_ID_MAX) offset = AT91_PMC_PCSR1; regmap_read(periph->regmap, offset, &status); return status & PERIPHERAL_MASK(id) ? 1 : 0; } static const struct clk_ops peripheral_ops = { .enable = clk_peripheral_enable, .disable = clk_peripheral_disable, .is_enabled = clk_peripheral_is_enabled, }; struct clk_hw * __init at91_clk_register_peripheral(struct regmap *regmap, const char *name, const char *parent_name, struct clk_hw *parent_hw, u32 id) { struct clk_peripheral *periph; struct clk_init_data init = {}; struct clk_hw *hw; int ret; if (!name || !(parent_name || parent_hw) || id > PERIPHERAL_ID_MAX) return ERR_PTR(-EINVAL); periph = kzalloc(sizeof(*periph), GFP_KERNEL); if (!periph) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &peripheral_ops; if (parent_hw) init.parent_hws = (const struct clk_hw **)&parent_hw; else init.parent_names = &parent_name; init.num_parents = 1; init.flags = 0; periph->id = id; periph->hw.init = &init; periph->regmap = regmap; hw = &periph->hw; ret = clk_hw_register(NULL, &periph->hw); if (ret) { kfree(periph); hw = ERR_PTR(ret); } return hw; } static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph) { struct clk_hw *parent; unsigned long parent_rate; int shift = 0; if (!periph->auto_div) return; if (periph->range.max) { parent = clk_hw_get_parent_by_index(&periph->hw, 0); parent_rate = clk_hw_get_rate(parent); if (!parent_rate) return; for (; shift < PERIPHERAL_MAX_SHIFT; shift++) { if (parent_rate >> shift <= periph->range.max) break; } } periph->auto_div = false; periph->div = shift; } static int clk_sam9x5_peripheral_set(struct clk_sam9x5_peripheral *periph, unsigned int status) { unsigned long flags; unsigned int enable = status ? AT91_PMC_PCR_EN : 0; if (periph->id < PERIPHERAL_ID_MIN) return 0; spin_lock_irqsave(periph->lock, flags); regmap_write(periph->regmap, periph->layout->offset, (periph->id & periph->layout->pid_mask)); regmap_update_bits(periph->regmap, periph->layout->offset, periph->layout->div_mask | periph->layout->cmd | enable, field_prep(periph->layout->div_mask, periph->div) | periph->layout->cmd | enable); spin_unlock_irqrestore(periph->lock, flags); return 0; } static int clk_sam9x5_peripheral_enable(struct clk_hw *hw) { struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); return clk_sam9x5_peripheral_set(periph, 1); } static void clk_sam9x5_peripheral_disable(struct clk_hw *hw) { struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); unsigned long flags; if (periph->id < PERIPHERAL_ID_MIN) return; spin_lock_irqsave(periph->lock, flags); regmap_write(periph->regmap, periph->layout->offset, (periph->id & periph->layout->pid_mask)); regmap_update_bits(periph->regmap, periph->layout->offset, AT91_PMC_PCR_EN | periph->layout->cmd, periph->layout->cmd); spin_unlock_irqrestore(periph->lock, flags); } static int clk_sam9x5_peripheral_is_enabled(struct clk_hw *hw) { struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); unsigned long flags; unsigned int status; if (periph->id < PERIPHERAL_ID_MIN) return 1; spin_lock_irqsave(periph->lock, flags); regmap_write(periph->regmap, periph->layout->offset, (periph->id & periph->layout->pid_mask)); regmap_read(periph->regmap, periph->layout->offset, &status); spin_unlock_irqrestore(periph->lock, flags); return !!(status & AT91_PMC_PCR_EN); } static unsigned long clk_sam9x5_peripheral_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); unsigned long flags; unsigned int status; if (periph->id < PERIPHERAL_ID_MIN) return parent_rate; spin_lock_irqsave(periph->lock, flags); regmap_write(periph->regmap, periph->layout->offset, (periph->id & periph->layout->pid_mask)); regmap_read(periph->regmap, periph->layout->offset, &status); spin_unlock_irqrestore(periph->lock, flags); if (status & AT91_PMC_PCR_EN) { periph->div = field_get(periph->layout->div_mask, status); periph->auto_div = false; } else { clk_sam9x5_peripheral_autodiv(periph); } return parent_rate >> periph->div; } static void clk_sam9x5_peripheral_best_diff(struct clk_rate_request *req, struct clk_hw *parent, unsigned long parent_rate, u32 shift, long *best_diff, long *best_rate) { unsigned long tmp_rate = parent_rate >> shift; unsigned long tmp_diff = abs(req->rate - tmp_rate); if (*best_diff < 0 || *best_diff >= tmp_diff) { *best_rate = tmp_rate; *best_diff = tmp_diff; req->best_parent_rate = parent_rate; req->best_parent_hw = parent; } } static int clk_sam9x5_peripheral_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); struct clk_hw *parent = clk_hw_get_parent(hw); unsigned long parent_rate = clk_hw_get_rate(parent); unsigned long tmp_rate; long best_rate = LONG_MIN; long best_diff = LONG_MIN; u32 shift; if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) return parent_rate; /* Fist step: check the available dividers. */ for (shift = 0; shift <= PERIPHERAL_MAX_SHIFT; shift++) { tmp_rate = parent_rate >> shift; if (periph->range.max && tmp_rate > periph->range.max) continue; clk_sam9x5_peripheral_best_diff(req, parent, parent_rate, shift, &best_diff, &best_rate); if (!best_diff || best_rate <= req->rate) break; } if (periph->chg_pid < 0) goto end; /* Step two: try to request rate from parent. */ parent = clk_hw_get_parent_by_index(hw, periph->chg_pid); if (!parent) goto end; for (shift = 0; shift <= PERIPHERAL_MAX_SHIFT; shift++) { struct clk_rate_request req_parent; clk_hw_forward_rate_request(hw, req, parent, &req_parent, req->rate << shift); if (__clk_determine_rate(parent, &req_parent)) continue; clk_sam9x5_peripheral_best_diff(req, parent, req_parent.rate, shift, &best_diff, &best_rate); if (!best_diff) break; } end: if (best_rate < 0 || (periph->range.max && best_rate > periph->range.max)) return -EINVAL; pr_debug("PCK: %s, best_rate = %ld, parent clk: %s @ %ld\n", __func__, best_rate, __clk_get_name((req->best_parent_hw)->clk), req->best_parent_rate); req->rate = best_rate; return 0; } static long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { int shift = 0; unsigned long best_rate; unsigned long best_diff; unsigned long cur_rate = *parent_rate; unsigned long cur_diff; struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) return *parent_rate; if (periph->range.max) { for (; shift <= PERIPHERAL_MAX_SHIFT; shift++) { cur_rate = *parent_rate >> shift; if (cur_rate <= periph->range.max) break; } } if (rate >= cur_rate) return cur_rate; best_diff = cur_rate - rate; best_rate = cur_rate; for (; shift <= PERIPHERAL_MAX_SHIFT; shift++) { cur_rate = *parent_rate >> shift; if (cur_rate < rate) cur_diff = rate - cur_rate; else cur_diff = cur_rate - rate; if (cur_diff < best_diff) { best_diff = cur_diff; best_rate = cur_rate; } if (!best_diff || cur_rate < rate) break; } return best_rate; } static int clk_sam9x5_peripheral_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { int shift; struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) { if (parent_rate == rate) return 0; else return -EINVAL; } if (periph->range.max && rate > periph->range.max) return -EINVAL; for (shift = 0; shift <= PERIPHERAL_MAX_SHIFT; shift++) { if (parent_rate >> shift == rate) { periph->auto_div = false; periph->div = shift; return 0; } } return -EINVAL; } static int clk_sam9x5_peripheral_save_context(struct clk_hw *hw) { struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); periph->pms.status = clk_sam9x5_peripheral_is_enabled(hw); return 0; } static void clk_sam9x5_peripheral_restore_context(struct clk_hw *hw) { struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); if (periph->pms.status) clk_sam9x5_peripheral_set(periph, periph->pms.status); } static const struct clk_ops sam9x5_peripheral_ops = { .enable = clk_sam9x5_peripheral_enable, .disable = clk_sam9x5_peripheral_disable, .is_enabled = clk_sam9x5_peripheral_is_enabled, .recalc_rate = clk_sam9x5_peripheral_recalc_rate, .round_rate = clk_sam9x5_peripheral_round_rate, .set_rate = clk_sam9x5_peripheral_set_rate, .save_context = clk_sam9x5_peripheral_save_context, .restore_context = clk_sam9x5_peripheral_restore_context, }; static const struct clk_ops sam9x5_peripheral_chg_ops = { .enable = clk_sam9x5_peripheral_enable, .disable = clk_sam9x5_peripheral_disable, .is_enabled = clk_sam9x5_peripheral_is_enabled, .recalc_rate = clk_sam9x5_peripheral_recalc_rate, .determine_rate = clk_sam9x5_peripheral_determine_rate, .set_rate = clk_sam9x5_peripheral_set_rate, .save_context = clk_sam9x5_peripheral_save_context, .restore_context = clk_sam9x5_peripheral_restore_context, }; struct clk_hw * __init at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock, const struct clk_pcr_layout *layout, const char *name, const char *parent_name, struct clk_hw *parent_hw, u32 id, const struct clk_range *range, int chg_pid, unsigned long flags) { struct clk_sam9x5_peripheral *periph; struct clk_init_data init = {}; struct clk_hw *hw; int ret; if (!name || !(parent_name || parent_hw)) return ERR_PTR(-EINVAL); periph = kzalloc(sizeof(*periph), GFP_KERNEL); if (!periph) return ERR_PTR(-ENOMEM); init.name = name; if (parent_hw) init.parent_hws = (const struct clk_hw **)&parent_hw; else init.parent_names = &parent_name; init.num_parents = 1; init.flags = flags; if (chg_pid < 0) { init.ops = &sam9x5_peripheral_ops; } else { init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT; init.ops = &sam9x5_peripheral_chg_ops; } periph->id = id; periph->hw.init = &init; periph->div = 0; periph->regmap = regmap; periph->lock = lock; if (layout->div_mask) periph->auto_div = true; periph->layout = layout; periph->range = *range; periph->chg_pid = chg_pid; hw = &periph->hw; ret = clk_hw_register(NULL, &periph->hw); if (ret) { kfree(periph); hw = ERR_PTR(ret); } else { clk_sam9x5_peripheral_autodiv(periph); } return hw; }
linux-master
drivers/clk/at91/clk-peripheral.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <[email protected]> */ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "pmc.h" #define PLL_STATUS_MASK(id) (1 << (1 + (id))) #define PLL_REG(id) (AT91_CKGR_PLLAR + ((id) * 4)) #define PLL_DIV_MASK 0xff #define PLL_DIV_MAX PLL_DIV_MASK #define PLL_DIV(reg) ((reg) & PLL_DIV_MASK) #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \ (layout)->mul_mask) #define PLL_MUL_MIN 2 #define PLL_MUL_MASK(layout) ((layout)->mul_mask) #define PLL_MUL_MAX(layout) (PLL_MUL_MASK(layout) + 1) #define PLL_ICPR_SHIFT(id) ((id) * 16) #define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id)) #define PLL_MAX_COUNT 0x3f #define PLL_COUNT_SHIFT 8 #define PLL_OUT_SHIFT 14 #define PLL_MAX_ID 1 #define to_clk_pll(hw) container_of(hw, struct clk_pll, hw) struct clk_pll { struct clk_hw hw; struct regmap *regmap; u8 id; u8 div; u8 range; u16 mul; const struct clk_pll_layout *layout; const struct clk_pll_characteristics *characteristics; struct at91_clk_pms pms; }; static inline bool clk_pll_ready(struct regmap *regmap, int id) { unsigned int status; regmap_read(regmap, AT91_PMC_SR, &status); return status & PLL_STATUS_MASK(id) ? 1 : 0; } static int clk_pll_prepare(struct clk_hw *hw) { struct clk_pll *pll = to_clk_pll(hw); struct regmap *regmap = pll->regmap; const struct clk_pll_layout *layout = pll->layout; const struct clk_pll_characteristics *characteristics = pll->characteristics; u8 id = pll->id; u32 mask = PLL_STATUS_MASK(id); int offset = PLL_REG(id); u8 out = 0; unsigned int pllr; unsigned int status; u8 div; u16 mul; regmap_read(regmap, offset, &pllr); div = PLL_DIV(pllr); mul = PLL_MUL(pllr, layout); regmap_read(regmap, AT91_PMC_SR, &status); if ((status & mask) && (div == pll->div && mul == pll->mul)) return 0; if (characteristics->out) out = characteristics->out[pll->range]; if (characteristics->icpll) regmap_update_bits(regmap, AT91_PMC_PLLICPR, PLL_ICPR_MASK(id), characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id)); regmap_update_bits(regmap, offset, layout->pllr_mask, pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) | (out << PLL_OUT_SHIFT) | ((pll->mul & layout->mul_mask) << layout->mul_shift)); while (!clk_pll_ready(regmap, pll->id)) cpu_relax(); return 0; } static int clk_pll_is_prepared(struct clk_hw *hw) { struct clk_pll *pll = to_clk_pll(hw); return clk_pll_ready(pll->regmap, pll->id); } static void clk_pll_unprepare(struct clk_hw *hw) { struct clk_pll *pll = to_clk_pll(hw); unsigned int mask = pll->layout->pllr_mask; regmap_update_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask); } static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pll *pll = to_clk_pll(hw); if (!pll->div || !pll->mul) return 0; return (parent_rate / pll->div) * (pll->mul + 1); } static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate, unsigned long parent_rate, u32 *div, u32 *mul, u32 *index) { const struct clk_pll_layout *layout = pll->layout; const struct clk_pll_characteristics *characteristics = pll->characteristics; unsigned long bestremainder = ULONG_MAX; unsigned long maxdiv, mindiv, tmpdiv; long bestrate = -ERANGE; unsigned long bestdiv; unsigned long bestmul; int i = 0; /* Check if parent_rate is a valid input rate */ if (parent_rate < characteristics->input.min) return -ERANGE; /* * Calculate minimum divider based on the minimum multiplier, the * parent_rate and the requested rate. * Should always be 2 according to the input and output characteristics * of the PLL blocks. */ mindiv = (parent_rate * PLL_MUL_MIN) / rate; if (!mindiv) mindiv = 1; if (parent_rate > characteristics->input.max) { tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max); if (tmpdiv > PLL_DIV_MAX) return -ERANGE; if (tmpdiv > mindiv) mindiv = tmpdiv; } /* * Calculate the maximum divider which is limited by PLL register * layout (limited by the MUL or DIV field size). */ maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX(layout), rate); if (maxdiv > PLL_DIV_MAX) maxdiv = PLL_DIV_MAX; /* * Iterate over the acceptable divider values to find the best * divider/multiplier pair (the one that generates the closest * rate to the requested one). */ for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) { unsigned long remainder; unsigned long tmprate; unsigned long tmpmul; /* * Calculate the multiplier associated with the current * divider that provide the closest rate to the requested one. */ tmpmul = DIV_ROUND_CLOSEST(rate, parent_rate / tmpdiv); tmprate = (parent_rate / tmpdiv) * tmpmul; if (tmprate > rate) remainder = tmprate - rate; else remainder = rate - tmprate; /* * Compare the remainder with the best remainder found until * now and elect a new best multiplier/divider pair if the * current remainder is smaller than the best one. */ if (remainder < bestremainder) { bestremainder = remainder; bestdiv = tmpdiv; bestmul = tmpmul; bestrate = tmprate; } /* * We've found a perfect match! * Stop searching now and use this multiplier/divider pair. */ if (!remainder) break; } /* We haven't found any multiplier/divider pair => return -ERANGE */ if (bestrate < 0) return bestrate; /* Check if bestrate is a valid output rate */ for (i = 0; i < characteristics->num_output; i++) { if (bestrate >= characteristics->output[i].min && bestrate <= characteristics->output[i].max) break; } if (i >= characteristics->num_output) return -ERANGE; if (div) *div = bestdiv; if (mul) *mul = bestmul - 1; if (index) *index = i; return bestrate; } static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { struct clk_pll *pll = to_clk_pll(hw); return clk_pll_get_best_div_mul(pll, rate, *parent_rate, NULL, NULL, NULL); } static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_pll *pll = to_clk_pll(hw); long ret; u32 div; u32 mul; u32 index; ret = clk_pll_get_best_div_mul(pll, rate, parent_rate, &div, &mul, &index); if (ret < 0) return ret; pll->range = index; pll->div = div; pll->mul = mul; return 0; } static int clk_pll_save_context(struct clk_hw *hw) { struct clk_pll *pll = to_clk_pll(hw); struct clk_hw *parent_hw = clk_hw_get_parent(hw); pll->pms.parent_rate = clk_hw_get_rate(parent_hw); pll->pms.rate = clk_pll_recalc_rate(&pll->hw, pll->pms.parent_rate); pll->pms.status = clk_pll_ready(pll->regmap, PLL_REG(pll->id)); return 0; } static void clk_pll_restore_context(struct clk_hw *hw) { struct clk_pll *pll = to_clk_pll(hw); unsigned long calc_rate; unsigned int pllr, pllr_out, pllr_count; u8 out = 0; if (pll->characteristics->out) out = pll->characteristics->out[pll->range]; regmap_read(pll->regmap, PLL_REG(pll->id), &pllr); calc_rate = (pll->pms.parent_rate / PLL_DIV(pllr)) * (PLL_MUL(pllr, pll->layout) + 1); pllr_count = (pllr >> PLL_COUNT_SHIFT) & PLL_MAX_COUNT; pllr_out = (pllr >> PLL_OUT_SHIFT) & out; if (pll->pms.rate != calc_rate || pll->pms.status != clk_pll_ready(pll->regmap, PLL_REG(pll->id)) || pllr_count != PLL_MAX_COUNT || (out && pllr_out != out)) pr_warn("PLLAR was not configured properly by firmware\n"); } static const struct clk_ops pll_ops = { .prepare = clk_pll_prepare, .unprepare = clk_pll_unprepare, .is_prepared = clk_pll_is_prepared, .recalc_rate = clk_pll_recalc_rate, .round_rate = clk_pll_round_rate, .set_rate = clk_pll_set_rate, .save_context = clk_pll_save_context, .restore_context = clk_pll_restore_context, }; struct clk_hw * __init at91_clk_register_pll(struct regmap *regmap, const char *name, const char *parent_name, u8 id, const struct clk_pll_layout *layout, const struct clk_pll_characteristics *characteristics) { struct clk_pll *pll; struct clk_hw *hw; struct clk_init_data init; int offset = PLL_REG(id); unsigned int pllr; int ret; if (id > PLL_MAX_ID) return ERR_PTR(-EINVAL); pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &pll_ops; init.parent_names = &parent_name; init.num_parents = 1; init.flags = CLK_SET_RATE_GATE; pll->id = id; pll->hw.init = &init; pll->layout = layout; pll->characteristics = characteristics; pll->regmap = regmap; regmap_read(regmap, offset, &pllr); pll->div = PLL_DIV(pllr); pll->mul = PLL_MUL(pllr, layout); hw = &pll->hw; ret = clk_hw_register(NULL, &pll->hw); if (ret) { kfree(pll); hw = ERR_PTR(ret); } return hw; } const struct clk_pll_layout at91rm9200_pll_layout = { .pllr_mask = 0x7FFFFFF, .mul_shift = 16, .mul_mask = 0x7FF, }; const struct clk_pll_layout at91sam9g45_pll_layout = { .pllr_mask = 0xFFFFFF, .mul_shift = 16, .mul_mask = 0xFF, }; const struct clk_pll_layout at91sam9g20_pllb_layout = { .pllr_mask = 0x3FFFFF, .mul_shift = 16, .mul_mask = 0x3F, }; const struct clk_pll_layout sama5d3_pll_layout = { .pllr_mask = 0x1FFFFFF, .mul_shift = 18, .mul_mask = 0x7F, };
linux-master
drivers/clk/at91/clk-pll.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * drivers/clk/at91/sckc.c * * Copyright (C) 2013 Boris BREZILLON <[email protected]> */ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/delay.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/io.h> #define SLOW_CLOCK_FREQ 32768 #define SLOWCK_SW_CYCLES 5 #define SLOWCK_SW_TIME_USEC ((SLOWCK_SW_CYCLES * USEC_PER_SEC) / \ SLOW_CLOCK_FREQ) #define AT91_SCKC_CR 0x00 struct clk_slow_bits { u32 cr_rcen; u32 cr_osc32en; u32 cr_osc32byp; u32 cr_oscsel; }; struct clk_slow_osc { struct clk_hw hw; void __iomem *sckcr; const struct clk_slow_bits *bits; unsigned long startup_usec; }; #define to_clk_slow_osc(hw) container_of(hw, struct clk_slow_osc, hw) struct clk_sama5d4_slow_osc { struct clk_hw hw; void __iomem *sckcr; const struct clk_slow_bits *bits; unsigned long startup_usec; bool prepared; }; #define to_clk_sama5d4_slow_osc(hw) container_of(hw, struct clk_sama5d4_slow_osc, hw) struct clk_slow_rc_osc { struct clk_hw hw; void __iomem *sckcr; const struct clk_slow_bits *bits; unsigned long frequency; unsigned long accuracy; unsigned long startup_usec; }; #define to_clk_slow_rc_osc(hw) container_of(hw, struct clk_slow_rc_osc, hw) struct clk_sam9x5_slow { struct clk_hw hw; void __iomem *sckcr; const struct clk_slow_bits *bits; u8 parent; }; #define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw) static int clk_slow_osc_prepare(struct clk_hw *hw) { struct clk_slow_osc *osc = to_clk_slow_osc(hw); void __iomem *sckcr = osc->sckcr; u32 tmp = readl(sckcr); if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en)) return 0; writel(tmp | osc->bits->cr_osc32en, sckcr); if (system_state < SYSTEM_RUNNING) udelay(osc->startup_usec); else usleep_range(osc->startup_usec, osc->startup_usec + 1); return 0; } static void clk_slow_osc_unprepare(struct clk_hw *hw) { struct clk_slow_osc *osc = to_clk_slow_osc(hw); void __iomem *sckcr = osc->sckcr; u32 tmp = readl(sckcr); if (tmp & osc->bits->cr_osc32byp) return; writel(tmp & ~osc->bits->cr_osc32en, sckcr); } static int clk_slow_osc_is_prepared(struct clk_hw *hw) { struct clk_slow_osc *osc = to_clk_slow_osc(hw); void __iomem *sckcr = osc->sckcr; u32 tmp = readl(sckcr); if (tmp & osc->bits->cr_osc32byp) return 1; return !!(tmp & osc->bits->cr_osc32en); } static const struct clk_ops slow_osc_ops = { .prepare = clk_slow_osc_prepare, .unprepare = clk_slow_osc_unprepare, .is_prepared = clk_slow_osc_is_prepared, }; static struct clk_hw * __init at91_clk_register_slow_osc(void __iomem *sckcr, const char *name, const struct clk_parent_data *parent_data, unsigned long startup, bool bypass, const struct clk_slow_bits *bits) { struct clk_slow_osc *osc; struct clk_hw *hw; struct clk_init_data init = {}; int ret; if (!sckcr || !name || !parent_data) return ERR_PTR(-EINVAL); osc = kzalloc(sizeof(*osc), GFP_KERNEL); if (!osc) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &slow_osc_ops; init.parent_data = parent_data; init.num_parents = 1; init.flags = CLK_IGNORE_UNUSED; osc->hw.init = &init; osc->sckcr = sckcr; osc->startup_usec = startup; osc->bits = bits; if (bypass) writel((readl(sckcr) & ~osc->bits->cr_osc32en) | osc->bits->cr_osc32byp, sckcr); hw = &osc->hw; ret = clk_hw_register(NULL, &osc->hw); if (ret) { kfree(osc); hw = ERR_PTR(ret); } return hw; } static void at91_clk_unregister_slow_osc(struct clk_hw *hw) { struct clk_slow_osc *osc = to_clk_slow_osc(hw); clk_hw_unregister(hw); kfree(osc); } static unsigned long clk_slow_rc_osc_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw); return osc->frequency; } static unsigned long clk_slow_rc_osc_recalc_accuracy(struct clk_hw *hw, unsigned long parent_acc) { struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw); return osc->accuracy; } static int clk_slow_rc_osc_prepare(struct clk_hw *hw) { struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw); void __iomem *sckcr = osc->sckcr; writel(readl(sckcr) | osc->bits->cr_rcen, sckcr); if (system_state < SYSTEM_RUNNING) udelay(osc->startup_usec); else usleep_range(osc->startup_usec, osc->startup_usec + 1); return 0; } static void clk_slow_rc_osc_unprepare(struct clk_hw *hw) { struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw); void __iomem *sckcr = osc->sckcr; writel(readl(sckcr) & ~osc->bits->cr_rcen, sckcr); } static int clk_slow_rc_osc_is_prepared(struct clk_hw *hw) { struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw); return !!(readl(osc->sckcr) & osc->bits->cr_rcen); } static const struct clk_ops slow_rc_osc_ops = { .prepare = clk_slow_rc_osc_prepare, .unprepare = clk_slow_rc_osc_unprepare, .is_prepared = clk_slow_rc_osc_is_prepared, .recalc_rate = clk_slow_rc_osc_recalc_rate, .recalc_accuracy = clk_slow_rc_osc_recalc_accuracy, }; static struct clk_hw * __init at91_clk_register_slow_rc_osc(void __iomem *sckcr, const char *name, unsigned long frequency, unsigned long accuracy, unsigned long startup, const struct clk_slow_bits *bits) { struct clk_slow_rc_osc *osc; struct clk_hw *hw; struct clk_init_data init; int ret; if (!sckcr || !name) return ERR_PTR(-EINVAL); osc = kzalloc(sizeof(*osc), GFP_KERNEL); if (!osc) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &slow_rc_osc_ops; init.parent_names = NULL; init.num_parents = 0; init.flags = CLK_IGNORE_UNUSED; osc->hw.init = &init; osc->sckcr = sckcr; osc->bits = bits; osc->frequency = frequency; osc->accuracy = accuracy; osc->startup_usec = startup; hw = &osc->hw; ret = clk_hw_register(NULL, &osc->hw); if (ret) { kfree(osc); hw = ERR_PTR(ret); } return hw; } static void at91_clk_unregister_slow_rc_osc(struct clk_hw *hw) { struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw); clk_hw_unregister(hw); kfree(osc); } static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index) { struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw); void __iomem *sckcr = slowck->sckcr; u32 tmp; if (index > 1) return -EINVAL; tmp = readl(sckcr); if ((!index && !(tmp & slowck->bits->cr_oscsel)) || (index && (tmp & slowck->bits->cr_oscsel))) return 0; if (index) tmp |= slowck->bits->cr_oscsel; else tmp &= ~slowck->bits->cr_oscsel; writel(tmp, sckcr); if (system_state < SYSTEM_RUNNING) udelay(SLOWCK_SW_TIME_USEC); else usleep_range(SLOWCK_SW_TIME_USEC, SLOWCK_SW_TIME_USEC + 1); return 0; } static u8 clk_sam9x5_slow_get_parent(struct clk_hw *hw) { struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw); return !!(readl(slowck->sckcr) & slowck->bits->cr_oscsel); } static const struct clk_ops sam9x5_slow_ops = { .determine_rate = clk_hw_determine_rate_no_reparent, .set_parent = clk_sam9x5_slow_set_parent, .get_parent = clk_sam9x5_slow_get_parent, }; static struct clk_hw * __init at91_clk_register_sam9x5_slow(void __iomem *sckcr, const char *name, const struct clk_hw **parent_hws, int num_parents, const struct clk_slow_bits *bits) { struct clk_sam9x5_slow *slowck; struct clk_hw *hw; struct clk_init_data init = {}; int ret; if (!sckcr || !name || !parent_hws || !num_parents) return ERR_PTR(-EINVAL); slowck = kzalloc(sizeof(*slowck), GFP_KERNEL); if (!slowck) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &sam9x5_slow_ops; init.parent_hws = parent_hws; init.num_parents = num_parents; init.flags = 0; slowck->hw.init = &init; slowck->sckcr = sckcr; slowck->bits = bits; slowck->parent = !!(readl(sckcr) & slowck->bits->cr_oscsel); hw = &slowck->hw; ret = clk_hw_register(NULL, &slowck->hw); if (ret) { kfree(slowck); hw = ERR_PTR(ret); } return hw; } static void at91_clk_unregister_sam9x5_slow(struct clk_hw *hw) { struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw); clk_hw_unregister(hw); kfree(slowck); } static void __init at91sam9x5_sckc_register(struct device_node *np, unsigned int rc_osc_startup_us, const struct clk_slow_bits *bits) { void __iomem *regbase = of_iomap(np, 0); struct device_node *child = NULL; const char *xtal_name; struct clk_hw *slow_rc, *slow_osc, *slowck; static struct clk_parent_data parent_data = { .name = "slow_xtal", }; const struct clk_hw *parent_hws[2]; bool bypass; int ret; if (!regbase) return; slow_rc = at91_clk_register_slow_rc_osc(regbase, "slow_rc_osc", 32768, 50000000, rc_osc_startup_us, bits); if (IS_ERR(slow_rc)) return; xtal_name = of_clk_get_parent_name(np, 0); if (!xtal_name) { /* DT backward compatibility */ child = of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow-osc"); if (!child) goto unregister_slow_rc; xtal_name = of_clk_get_parent_name(child, 0); bypass = of_property_read_bool(child, "atmel,osc-bypass"); child = of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow"); } else { bypass = of_property_read_bool(np, "atmel,osc-bypass"); } if (!xtal_name) goto unregister_slow_rc; parent_data.fw_name = xtal_name; slow_osc = at91_clk_register_slow_osc(regbase, "slow_osc", &parent_data, 1200000, bypass, bits); if (IS_ERR(slow_osc)) goto unregister_slow_rc; parent_hws[0] = slow_rc; parent_hws[1] = slow_osc; slowck = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_hws, 2, bits); if (IS_ERR(slowck)) goto unregister_slow_osc; /* DT backward compatibility */ if (child) ret = of_clk_add_hw_provider(child, of_clk_hw_simple_get, slowck); else ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, slowck); if (WARN_ON(ret)) goto unregister_slowck; return; unregister_slowck: at91_clk_unregister_sam9x5_slow(slowck); unregister_slow_osc: at91_clk_unregister_slow_osc(slow_osc); unregister_slow_rc: at91_clk_unregister_slow_rc_osc(slow_rc); } static const struct clk_slow_bits at91sam9x5_bits = { .cr_rcen = BIT(0), .cr_osc32en = BIT(1), .cr_osc32byp = BIT(2), .cr_oscsel = BIT(3), }; static void __init of_at91sam9x5_sckc_setup(struct device_node *np) { at91sam9x5_sckc_register(np, 75, &at91sam9x5_bits); } CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc", of_at91sam9x5_sckc_setup); static void __init of_sama5d3_sckc_setup(struct device_node *np) { at91sam9x5_sckc_register(np, 500, &at91sam9x5_bits); } CLK_OF_DECLARE(sama5d3_clk_sckc, "atmel,sama5d3-sckc", of_sama5d3_sckc_setup); static const struct clk_slow_bits at91sam9x60_bits = { .cr_osc32en = BIT(1), .cr_osc32byp = BIT(2), .cr_oscsel = BIT(24), }; static void __init of_sam9x60_sckc_setup(struct device_node *np) { void __iomem *regbase = of_iomap(np, 0); struct clk_hw_onecell_data *clk_data; struct clk_hw *slow_rc, *slow_osc; const char *xtal_name; const struct clk_hw *parent_hws[2]; static struct clk_parent_data parent_data = { .name = "slow_xtal", }; bool bypass; int ret; if (!regbase) return; slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL, "slow_rc_osc", NULL, 0, 32768, 93750000); if (IS_ERR(slow_rc)) return; xtal_name = of_clk_get_parent_name(np, 0); if (!xtal_name) goto unregister_slow_rc; parent_data.fw_name = xtal_name; bypass = of_property_read_bool(np, "atmel,osc-bypass"); slow_osc = at91_clk_register_slow_osc(regbase, "slow_osc", &parent_data, 5000000, bypass, &at91sam9x60_bits); if (IS_ERR(slow_osc)) goto unregister_slow_rc; clk_data = kzalloc(struct_size(clk_data, hws, 2), GFP_KERNEL); if (!clk_data) goto unregister_slow_osc; /* MD_SLCK and TD_SLCK. */ clk_data->num = 2; clk_data->hws[0] = clk_hw_register_fixed_rate_parent_hw(NULL, "md_slck", slow_rc, 0, 32768); if (IS_ERR(clk_data->hws[0])) goto clk_data_free; parent_hws[0] = slow_rc; parent_hws[1] = slow_osc; clk_data->hws[1] = at91_clk_register_sam9x5_slow(regbase, "td_slck", parent_hws, 2, &at91sam9x60_bits); if (IS_ERR(clk_data->hws[1])) goto unregister_md_slck; ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); if (WARN_ON(ret)) goto unregister_td_slck; return; unregister_td_slck: at91_clk_unregister_sam9x5_slow(clk_data->hws[1]); unregister_md_slck: clk_hw_unregister(clk_data->hws[0]); clk_data_free: kfree(clk_data); unregister_slow_osc: at91_clk_unregister_slow_osc(slow_osc); unregister_slow_rc: clk_hw_unregister(slow_rc); } CLK_OF_DECLARE(sam9x60_clk_sckc, "microchip,sam9x60-sckc", of_sam9x60_sckc_setup); static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw) { struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw); if (osc->prepared) return 0; /* * Assume that if it has already been selected (for example by the * bootloader), enough time has already passed. */ if ((readl(osc->sckcr) & osc->bits->cr_oscsel)) { osc->prepared = true; return 0; } if (system_state < SYSTEM_RUNNING) udelay(osc->startup_usec); else usleep_range(osc->startup_usec, osc->startup_usec + 1); osc->prepared = true; return 0; } static int clk_sama5d4_slow_osc_is_prepared(struct clk_hw *hw) { struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw); return osc->prepared; } static const struct clk_ops sama5d4_slow_osc_ops = { .prepare = clk_sama5d4_slow_osc_prepare, .is_prepared = clk_sama5d4_slow_osc_is_prepared, }; static const struct clk_slow_bits at91sama5d4_bits = { .cr_oscsel = BIT(3), }; static void __init of_sama5d4_sckc_setup(struct device_node *np) { void __iomem *regbase = of_iomap(np, 0); struct clk_hw *slow_rc, *slowck; struct clk_sama5d4_slow_osc *osc; struct clk_init_data init = {}; const char *xtal_name; const struct clk_hw *parent_hws[2]; static struct clk_parent_data parent_data = { .name = "slow_xtal", }; int ret; if (!regbase) return; slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL, "slow_rc_osc", NULL, 0, 32768, 250000000); if (IS_ERR(slow_rc)) return; xtal_name = of_clk_get_parent_name(np, 0); if (!xtal_name) goto unregister_slow_rc; parent_data.fw_name = xtal_name; osc = kzalloc(sizeof(*osc), GFP_KERNEL); if (!osc) goto unregister_slow_rc; init.name = "slow_osc"; init.ops = &sama5d4_slow_osc_ops; init.parent_data = &parent_data; init.num_parents = 1; init.flags = CLK_IGNORE_UNUSED; osc->hw.init = &init; osc->sckcr = regbase; osc->startup_usec = 1200000; osc->bits = &at91sama5d4_bits; ret = clk_hw_register(NULL, &osc->hw); if (ret) goto free_slow_osc_data; parent_hws[0] = slow_rc; parent_hws[1] = &osc->hw; slowck = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_hws, 2, &at91sama5d4_bits); if (IS_ERR(slowck)) goto unregister_slow_osc; ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, slowck); if (WARN_ON(ret)) goto unregister_slowck; return; unregister_slowck: at91_clk_unregister_sam9x5_slow(slowck); unregister_slow_osc: clk_hw_unregister(&osc->hw); free_slow_osc_data: kfree(osc); unregister_slow_rc: clk_hw_unregister(slow_rc); } CLK_OF_DECLARE(sama5d4_clk_sckc, "atmel,sama5d4-sckc", of_sama5d4_sckc_setup);
linux-master
drivers/clk/at91/sckc.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <[email protected]> */ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/at91_pmc.h> #include <linux/delay.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "pmc.h" #define SLOW_CLOCK_FREQ 32768 #define MAINF_DIV 16 #define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \ SLOW_CLOCK_FREQ) #define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ) #define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT #define MOR_KEY_MASK (0xff << 16) #define clk_main_parent_select(s) (((s) & \ (AT91_PMC_MOSCEN | \ AT91_PMC_OSCBYPASS)) ? 1 : 0) struct clk_main_osc { struct clk_hw hw; struct regmap *regmap; struct at91_clk_pms pms; }; #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw) struct clk_main_rc_osc { struct clk_hw hw; struct regmap *regmap; unsigned long frequency; unsigned long accuracy; struct at91_clk_pms pms; }; #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw) struct clk_rm9200_main { struct clk_hw hw; struct regmap *regmap; }; #define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw) struct clk_sam9x5_main { struct clk_hw hw; struct regmap *regmap; struct at91_clk_pms pms; u8 parent; }; #define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw) static inline bool clk_main_osc_ready(struct regmap *regmap) { unsigned int status; regmap_read(regmap, AT91_PMC_SR, &status); return status & AT91_PMC_MOSCS; } static int clk_main_osc_prepare(struct clk_hw *hw) { struct clk_main_osc *osc = to_clk_main_osc(hw); struct regmap *regmap = osc->regmap; u32 tmp; regmap_read(regmap, AT91_CKGR_MOR, &tmp); tmp &= ~MOR_KEY_MASK; if (tmp & AT91_PMC_OSCBYPASS) return 0; if (!(tmp & AT91_PMC_MOSCEN)) { tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY; regmap_write(regmap, AT91_CKGR_MOR, tmp); } while (!clk_main_osc_ready(regmap)) cpu_relax(); return 0; } static void clk_main_osc_unprepare(struct clk_hw *hw) { struct clk_main_osc *osc = to_clk_main_osc(hw); struct regmap *regmap = osc->regmap; u32 tmp; regmap_read(regmap, AT91_CKGR_MOR, &tmp); if (tmp & AT91_PMC_OSCBYPASS) return; if (!(tmp & AT91_PMC_MOSCEN)) return; tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN); regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_KEY); } static int clk_main_osc_is_prepared(struct clk_hw *hw) { struct clk_main_osc *osc = to_clk_main_osc(hw); struct regmap *regmap = osc->regmap; u32 tmp, status; regmap_read(regmap, AT91_CKGR_MOR, &tmp); if (tmp & AT91_PMC_OSCBYPASS) return 1; regmap_read(regmap, AT91_PMC_SR, &status); return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp); } static int clk_main_osc_save_context(struct clk_hw *hw) { struct clk_main_osc *osc = to_clk_main_osc(hw); osc->pms.status = clk_main_osc_is_prepared(hw); return 0; } static void clk_main_osc_restore_context(struct clk_hw *hw) { struct clk_main_osc *osc = to_clk_main_osc(hw); if (osc->pms.status) clk_main_osc_prepare(hw); } static const struct clk_ops main_osc_ops = { .prepare = clk_main_osc_prepare, .unprepare = clk_main_osc_unprepare, .is_prepared = clk_main_osc_is_prepared, .save_context = clk_main_osc_save_context, .restore_context = clk_main_osc_restore_context, }; struct clk_hw * __init at91_clk_register_main_osc(struct regmap *regmap, const char *name, const char *parent_name, struct clk_parent_data *parent_data, bool bypass) { struct clk_main_osc *osc; struct clk_init_data init = {}; struct clk_hw *hw; int ret; if (!name || !(parent_name || parent_data)) return ERR_PTR(-EINVAL); osc = kzalloc(sizeof(*osc), GFP_KERNEL); if (!osc) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &main_osc_ops; if (parent_data) init.parent_data = (const struct clk_parent_data *)parent_data; else init.parent_names = &parent_name; init.num_parents = 1; init.flags = CLK_IGNORE_UNUSED; osc->hw.init = &init; osc->regmap = regmap; if (bypass) regmap_update_bits(regmap, AT91_CKGR_MOR, MOR_KEY_MASK | AT91_PMC_OSCBYPASS, AT91_PMC_OSCBYPASS | AT91_PMC_KEY); hw = &osc->hw; ret = clk_hw_register(NULL, &osc->hw); if (ret) { kfree(osc); hw = ERR_PTR(ret); } return hw; } static bool clk_main_rc_osc_ready(struct regmap *regmap) { unsigned int status; regmap_read(regmap, AT91_PMC_SR, &status); return !!(status & AT91_PMC_MOSCRCS); } static int clk_main_rc_osc_prepare(struct clk_hw *hw) { struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); struct regmap *regmap = osc->regmap; unsigned int mor; regmap_read(regmap, AT91_CKGR_MOR, &mor); if (!(mor & AT91_PMC_MOSCRCEN)) regmap_update_bits(regmap, AT91_CKGR_MOR, MOR_KEY_MASK | AT91_PMC_MOSCRCEN, AT91_PMC_MOSCRCEN | AT91_PMC_KEY); while (!clk_main_rc_osc_ready(regmap)) cpu_relax(); return 0; } static void clk_main_rc_osc_unprepare(struct clk_hw *hw) { struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); struct regmap *regmap = osc->regmap; unsigned int mor; regmap_read(regmap, AT91_CKGR_MOR, &mor); if (!(mor & AT91_PMC_MOSCRCEN)) return; regmap_update_bits(regmap, AT91_CKGR_MOR, MOR_KEY_MASK | AT91_PMC_MOSCRCEN, AT91_PMC_KEY); } static int clk_main_rc_osc_is_prepared(struct clk_hw *hw) { struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); struct regmap *regmap = osc->regmap; unsigned int mor, status; regmap_read(regmap, AT91_CKGR_MOR, &mor); regmap_read(regmap, AT91_PMC_SR, &status); return (mor & AT91_PMC_MOSCRCEN) && (status & AT91_PMC_MOSCRCS); } static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); return osc->frequency; } static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw, unsigned long parent_acc) { struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); return osc->accuracy; } static int clk_main_rc_osc_save_context(struct clk_hw *hw) { struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); osc->pms.status = clk_main_rc_osc_is_prepared(hw); return 0; } static void clk_main_rc_osc_restore_context(struct clk_hw *hw) { struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); if (osc->pms.status) clk_main_rc_osc_prepare(hw); } static const struct clk_ops main_rc_osc_ops = { .prepare = clk_main_rc_osc_prepare, .unprepare = clk_main_rc_osc_unprepare, .is_prepared = clk_main_rc_osc_is_prepared, .recalc_rate = clk_main_rc_osc_recalc_rate, .recalc_accuracy = clk_main_rc_osc_recalc_accuracy, .save_context = clk_main_rc_osc_save_context, .restore_context = clk_main_rc_osc_restore_context, }; struct clk_hw * __init at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name, u32 frequency, u32 accuracy) { struct clk_main_rc_osc *osc; struct clk_init_data init; struct clk_hw *hw; int ret; if (!name || !frequency) return ERR_PTR(-EINVAL); osc = kzalloc(sizeof(*osc), GFP_KERNEL); if (!osc) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &main_rc_osc_ops; init.parent_names = NULL; init.num_parents = 0; init.flags = CLK_IGNORE_UNUSED; osc->hw.init = &init; osc->regmap = regmap; osc->frequency = frequency; osc->accuracy = accuracy; hw = &osc->hw; ret = clk_hw_register(NULL, hw); if (ret) { kfree(osc); hw = ERR_PTR(ret); } return hw; } static int clk_main_probe_frequency(struct regmap *regmap) { unsigned long prep_time, timeout; unsigned int mcfr; timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT); do { prep_time = jiffies; regmap_read(regmap, AT91_CKGR_MCFR, &mcfr); if (mcfr & AT91_PMC_MAINRDY) return 0; if (system_state < SYSTEM_RUNNING) udelay(MAINF_LOOP_MIN_WAIT); else usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT); } while (time_before(prep_time, timeout)); return -ETIMEDOUT; } static unsigned long clk_main_recalc_rate(struct regmap *regmap, unsigned long parent_rate) { unsigned int mcfr; if (parent_rate) return parent_rate; pr_warn("Main crystal frequency not set, using approximate value\n"); regmap_read(regmap, AT91_CKGR_MCFR, &mcfr); if (!(mcfr & AT91_PMC_MAINRDY)) return 0; return ((mcfr & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV; } static int clk_rm9200_main_prepare(struct clk_hw *hw) { struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); return clk_main_probe_frequency(clkmain->regmap); } static int clk_rm9200_main_is_prepared(struct clk_hw *hw) { struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); unsigned int status; regmap_read(clkmain->regmap, AT91_CKGR_MCFR, &status); return !!(status & AT91_PMC_MAINRDY); } static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); return clk_main_recalc_rate(clkmain->regmap, parent_rate); } static const struct clk_ops rm9200_main_ops = { .prepare = clk_rm9200_main_prepare, .is_prepared = clk_rm9200_main_is_prepared, .recalc_rate = clk_rm9200_main_recalc_rate, }; struct clk_hw * __init at91_clk_register_rm9200_main(struct regmap *regmap, const char *name, const char *parent_name, struct clk_hw *parent_hw) { struct clk_rm9200_main *clkmain; struct clk_init_data init = {}; struct clk_hw *hw; int ret; if (!name) return ERR_PTR(-EINVAL); if (!(parent_name || parent_hw)) return ERR_PTR(-EINVAL); clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL); if (!clkmain) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &rm9200_main_ops; if (parent_hw) init.parent_hws = (const struct clk_hw **)&parent_hw; else init.parent_names = &parent_name; init.num_parents = 1; init.flags = 0; clkmain->hw.init = &init; clkmain->regmap = regmap; hw = &clkmain->hw; ret = clk_hw_register(NULL, &clkmain->hw); if (ret) { kfree(clkmain); hw = ERR_PTR(ret); } return hw; } static inline bool clk_sam9x5_main_ready(struct regmap *regmap) { unsigned int status; regmap_read(regmap, AT91_PMC_SR, &status); return !!(status & AT91_PMC_MOSCSELS); } static int clk_sam9x5_main_prepare(struct clk_hw *hw) { struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); struct regmap *regmap = clkmain->regmap; while (!clk_sam9x5_main_ready(regmap)) cpu_relax(); return clk_main_probe_frequency(regmap); } static int clk_sam9x5_main_is_prepared(struct clk_hw *hw) { struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); return clk_sam9x5_main_ready(clkmain->regmap); } static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); return clk_main_recalc_rate(clkmain->regmap, parent_rate); } static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index) { struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); struct regmap *regmap = clkmain->regmap; unsigned int tmp; if (index > 1) return -EINVAL; regmap_read(regmap, AT91_CKGR_MOR, &tmp); if (index && !(tmp & AT91_PMC_MOSCSEL)) tmp = AT91_PMC_MOSCSEL; else if (!index && (tmp & AT91_PMC_MOSCSEL)) tmp = 0; else return 0; regmap_update_bits(regmap, AT91_CKGR_MOR, AT91_PMC_MOSCSEL | MOR_KEY_MASK, tmp | AT91_PMC_KEY); while (!clk_sam9x5_main_ready(regmap)) cpu_relax(); return 0; } static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw) { struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); unsigned int status; regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status); return clk_main_parent_select(status); } static int clk_sam9x5_main_save_context(struct clk_hw *hw) { struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); clkmain->pms.status = clk_main_rc_osc_is_prepared(&clkmain->hw); clkmain->pms.parent = clk_sam9x5_main_get_parent(&clkmain->hw); return 0; } static void clk_sam9x5_main_restore_context(struct clk_hw *hw) { struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); int ret; ret = clk_sam9x5_main_set_parent(hw, clkmain->pms.parent); if (ret) return; if (clkmain->pms.status) clk_sam9x5_main_prepare(hw); } static const struct clk_ops sam9x5_main_ops = { .prepare = clk_sam9x5_main_prepare, .is_prepared = clk_sam9x5_main_is_prepared, .recalc_rate = clk_sam9x5_main_recalc_rate, .determine_rate = clk_hw_determine_rate_no_reparent, .set_parent = clk_sam9x5_main_set_parent, .get_parent = clk_sam9x5_main_get_parent, .save_context = clk_sam9x5_main_save_context, .restore_context = clk_sam9x5_main_restore_context, }; struct clk_hw * __init at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name, const char **parent_names, struct clk_hw **parent_hws, int num_parents) { struct clk_sam9x5_main *clkmain; struct clk_init_data init = {}; unsigned int status; struct clk_hw *hw; int ret; if (!name) return ERR_PTR(-EINVAL); if (!(parent_hws || parent_names) || !num_parents) return ERR_PTR(-EINVAL); clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL); if (!clkmain) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &sam9x5_main_ops; if (parent_hws) init.parent_hws = (const struct clk_hw **)parent_hws; else init.parent_names = parent_names; init.num_parents = num_parents; init.flags = CLK_SET_PARENT_GATE; clkmain->hw.init = &init; clkmain->regmap = regmap; regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status); clkmain->parent = clk_main_parent_select(status); hw = &clkmain->hw; ret = clk_hw_register(NULL, &clkmain->hw); if (ret) { kfree(clkmain); hw = ERR_PTR(ret); } return hw; }
linux-master
drivers/clk/at91/clk-main.c
// SPDX-License-Identifier: GPL-2.0 #include <linux/clk-provider.h> #include <linux/mfd/syscon.h> #include <linux/slab.h> #include <dt-bindings/clock/at91.h> #include "pmc.h" static DEFINE_SPINLOCK(mck_lock); static const struct clk_master_characteristics mck_characteristics = { .output = { .min = 124000000, .max = 166000000 }, .divisors = { 1, 2, 4, 3 }, }; static u8 plla_out[] = { 0 }; static u16 plla_icpll[] = { 0 }; static const struct clk_range plla_outputs[] = { { .min = 600000000, .max = 1200000000 }, }; static const struct clk_pll_characteristics plla_characteristics = { .input = { .min = 12000000, .max = 24000000 }, .num_output = ARRAY_SIZE(plla_outputs), .output = plla_outputs, .icpll = plla_icpll, .out = plla_out, }; static const struct clk_pcr_layout sama5d2_pcr_layout = { .offset = 0x10c, .cmd = BIT(12), .gckcss_mask = GENMASK(10, 8), .pid_mask = GENMASK(6, 0), }; static const struct { char *n; char *p; unsigned long flags; u8 id; } sama5d2_systemck[] = { /* * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, { .n = "lcdck", .p = "masterck_div", .id = 3 }, { .n = "uhpck", .p = "usbck", .id = 6 }, { .n = "udpck", .p = "usbck", .id = 7 }, { .n = "pck0", .p = "prog0", .id = 8 }, { .n = "pck1", .p = "prog1", .id = 9 }, { .n = "pck2", .p = "prog2", .id = 10 }, { .n = "iscck", .p = "masterck_div", .id = 18 }, }; static const struct { char *n; u8 id; struct clk_range r; } sama5d2_periph32ck[] = { { .n = "macb0_clk", .id = 5, .r = { .min = 0, .max = 83000000 }, }, { .n = "tdes_clk", .id = 11, .r = { .min = 0, .max = 83000000 }, }, { .n = "matrix1_clk", .id = 14, }, { .n = "hsmc_clk", .id = 17, }, { .n = "pioA_clk", .id = 18, .r = { .min = 0, .max = 83000000 }, }, { .n = "flx0_clk", .id = 19, .r = { .min = 0, .max = 83000000 }, }, { .n = "flx1_clk", .id = 20, .r = { .min = 0, .max = 83000000 }, }, { .n = "flx2_clk", .id = 21, .r = { .min = 0, .max = 83000000 }, }, { .n = "flx3_clk", .id = 22, .r = { .min = 0, .max = 83000000 }, }, { .n = "flx4_clk", .id = 23, .r = { .min = 0, .max = 83000000 }, }, { .n = "uart0_clk", .id = 24, .r = { .min = 0, .max = 83000000 }, }, { .n = "uart1_clk", .id = 25, .r = { .min = 0, .max = 83000000 }, }, { .n = "uart2_clk", .id = 26, .r = { .min = 0, .max = 83000000 }, }, { .n = "uart3_clk", .id = 27, .r = { .min = 0, .max = 83000000 }, }, { .n = "uart4_clk", .id = 28, .r = { .min = 0, .max = 83000000 }, }, { .n = "twi0_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, }, { .n = "twi1_clk", .id = 30, .r = { .min = 0, .max = 83000000 }, }, { .n = "spi0_clk", .id = 33, .r = { .min = 0, .max = 83000000 }, }, { .n = "spi1_clk", .id = 34, .r = { .min = 0, .max = 83000000 }, }, { .n = "tcb0_clk", .id = 35, .r = { .min = 0, .max = 83000000 }, }, { .n = "tcb1_clk", .id = 36, .r = { .min = 0, .max = 83000000 }, }, { .n = "pwm_clk", .id = 38, .r = { .min = 0, .max = 83000000 }, }, { .n = "adc_clk", .id = 40, .r = { .min = 0, .max = 83000000 }, }, { .n = "uhphs_clk", .id = 41, .r = { .min = 0, .max = 83000000 }, }, { .n = "udphs_clk", .id = 42, .r = { .min = 0, .max = 83000000 }, }, { .n = "ssc0_clk", .id = 43, .r = { .min = 0, .max = 83000000 }, }, { .n = "ssc1_clk", .id = 44, .r = { .min = 0, .max = 83000000 }, }, { .n = "trng_clk", .id = 47, .r = { .min = 0, .max = 83000000 }, }, { .n = "pdmic_clk", .id = 48, .r = { .min = 0, .max = 83000000 }, }, { .n = "securam_clk", .id = 51, }, { .n = "i2s0_clk", .id = 54, .r = { .min = 0, .max = 83000000 }, }, { .n = "i2s1_clk", .id = 55, .r = { .min = 0, .max = 83000000 }, }, { .n = "can0_clk", .id = 56, .r = { .min = 0, .max = 83000000 }, }, { .n = "can1_clk", .id = 57, .r = { .min = 0, .max = 83000000 }, }, { .n = "ptc_clk", .id = 58, .r = { .min = 0, .max = 83000000 }, }, { .n = "classd_clk", .id = 59, .r = { .min = 0, .max = 83000000 }, }, }; static const struct { char *n; unsigned long flags; u8 id; } sama5d2_periphck[] = { { .n = "dma0_clk", .id = 6, }, { .n = "dma1_clk", .id = 7, }, { .n = "aes_clk", .id = 9, }, { .n = "aesb_clk", .id = 10, }, { .n = "sha_clk", .id = 12, }, /* * mpddr_clk feeds DDR controller and is enabled by bootloader thus we * need to keep it enabled in case there is no Linux consumer for it. */ { .n = "mpddr_clk", .id = 13, .flags = CLK_IS_CRITICAL }, { .n = "matrix0_clk", .id = 15, }, { .n = "sdmmc0_hclk", .id = 31, }, { .n = "sdmmc1_hclk", .id = 32, }, { .n = "lcdc_clk", .id = 45, }, { .n = "isc_clk", .id = 46, }, { .n = "qspi0_clk", .id = 52, }, { .n = "qspi1_clk", .id = 53, }, }; static const struct { char *n; u8 id; struct clk_range r; int chg_pid; } sama5d2_gck[] = { { .n = "flx0_gclk", .id = 19, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, { .n = "flx1_gclk", .id = 20, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, { .n = "flx2_gclk", .id = 21, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, { .n = "flx3_gclk", .id = 22, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, { .n = "flx4_gclk", .id = 23, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, { .n = "uart0_gclk", .id = 24, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, { .n = "uart1_gclk", .id = 25, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, { .n = "uart2_gclk", .id = 26, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, { .n = "uart3_gclk", .id = 27, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, { .n = "uart4_gclk", .id = 28, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, { .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, }, { .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, }, { .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, }, { .n = "tcb1_gclk", .id = 36, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, }, { .n = "pwm_gclk", .id = 38, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, }, { .n = "isc_gclk", .id = 46, .chg_pid = INT_MIN, }, { .n = "pdmic_gclk", .id = 48, .chg_pid = INT_MIN, }, { .n = "i2s0_gclk", .id = 54, .chg_pid = 5, }, { .n = "i2s1_gclk", .id = 55, .chg_pid = 5, }, { .n = "can0_gclk", .id = 56, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, }, { .n = "can1_gclk", .id = 57, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, }, { .n = "classd_gclk", .id = 59, .chg_pid = 5, .r = { .min = 0, .max = 100000000 }, }, }; static const struct clk_programmable_layout sama5d2_programmable_layout = { .pres_mask = 0xff, .pres_shift = 4, .css_mask = 0x7, .have_slck_mck = 0, .is_pres_direct = 1, }; static void __init sama5d2_pmc_setup(struct device_node *np) { struct clk_range range = CLK_RANGE(0, 0); const char *slck_name, *mainxtal_name; struct pmc_data *sama5d2_pmc; const char *parent_names[6]; struct regmap *regmap, *regmap_sfr; struct clk_hw *hw; int i; bool bypass; i = of_property_match_string(np, "clock-names", "slow_clk"); if (i < 0) return; slck_name = of_clk_get_parent_name(np, i); i = of_property_match_string(np, "clock-names", "main_xtal"); if (i < 0) return; mainxtal_name = of_clk_get_parent_name(np, i); regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; sama5d2_pmc = pmc_data_allocate(PMC_AUDIOPINCK + 1, nck(sama5d2_systemck), nck(sama5d2_periph32ck), nck(sama5d2_gck), 3); if (!sama5d2_pmc) return; hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 100000000); if (IS_ERR(hw)) goto err_free; bypass = of_property_read_bool(np, "atmel,osc-bypass"); hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, bypass); if (IS_ERR(hw)) goto err_free; parent_names[0] = "main_rc_osc"; parent_names[1] = "main_osc"; hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2); if (IS_ERR(hw)) goto err_free; sama5d2_pmc->chws[PMC_MAIN] = hw; hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, &sama5d3_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); if (IS_ERR(hw)) goto err_free; sama5d2_pmc->chws[PMC_PLLACK] = hw; hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck", "mainck"); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck", "audiopll_fracck"); if (IS_ERR(hw)) goto err_free; sama5d2_pmc->chws[PMC_AUDIOPINCK] = hw; hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck", "audiopll_fracck"); if (IS_ERR(hw)) goto err_free; sama5d2_pmc->chws[PMC_AUDIOPLLCK] = hw; regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr"); if (IS_ERR(regmap_sfr)) regmap_sfr = NULL; hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck", NULL); if (IS_ERR(hw)) goto err_free; sama5d2_pmc->chws[PMC_UTMI] = hw; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, parent_names, NULL, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_master_div(regmap, "masterck_div", "masterck_pres", NULL, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; sama5d2_pmc->chws[PMC_MCK] = hw; hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div"); if (IS_ERR(hw)) goto err_free; sama5d2_pmc->chws[PMC_MCK2] = hw; parent_names[0] = "plladivck"; parent_names[1] = "utmick"; hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); if (IS_ERR(hw)) goto err_free; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; parent_names[4] = "masterck_div"; parent_names[5] = "audiopll_pmcck"; for (i = 0; i < 3; i++) { char name[6]; snprintf(name, sizeof(name), "prog%d", i); hw = at91_clk_register_programmable(regmap, name, parent_names, NULL, 6, i, &sama5d2_programmable_layout, NULL); if (IS_ERR(hw)) goto err_free; sama5d2_pmc->pchws[i] = hw; } for (i = 0; i < ARRAY_SIZE(sama5d2_systemck); i++) { hw = at91_clk_register_system(regmap, sama5d2_systemck[i].n, sama5d2_systemck[i].p, NULL, sama5d2_systemck[i].id, sama5d2_systemck[i].flags); if (IS_ERR(hw)) goto err_free; sama5d2_pmc->shws[sama5d2_systemck[i].id] = hw; } for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_periphck[i].n, "masterck_div", NULL, sama5d2_periphck[i].id, &range, INT_MIN, sama5d2_periphck[i].flags); if (IS_ERR(hw)) goto err_free; sama5d2_pmc->phws[sama5d2_periphck[i].id] = hw; } for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_periph32ck[i].n, "h32mxck", NULL, sama5d2_periph32ck[i].id, &sama5d2_periph32ck[i].r, INT_MIN, 0); if (IS_ERR(hw)) goto err_free; sama5d2_pmc->phws[sama5d2_periph32ck[i].id] = hw; } parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; parent_names[4] = "masterck_div"; parent_names[5] = "audiopll_pmcck"; for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) { hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_gck[i].n, parent_names, NULL, NULL, 6, sama5d2_gck[i].id, &sama5d2_gck[i].r, sama5d2_gck[i].chg_pid); if (IS_ERR(hw)) goto err_free; sama5d2_pmc->ghws[sama5d2_gck[i].id] = hw; } if (regmap_sfr) { parent_names[0] = "i2s0_clk"; parent_names[1] = "i2s0_gclk"; hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk", parent_names, 2, 0); if (IS_ERR(hw)) goto err_free; sama5d2_pmc->chws[PMC_I2S0_MUX] = hw; parent_names[0] = "i2s1_clk"; parent_names[1] = "i2s1_gclk"; hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk", parent_names, 2, 1); if (IS_ERR(hw)) goto err_free; sama5d2_pmc->chws[PMC_I2S1_MUX] = hw; } of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d2_pmc); return; err_free: kfree(sama5d2_pmc); } CLK_OF_DECLARE(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);
linux-master
drivers/clk/at91/sama5d2.c
// SPDX-License-Identifier: GPL-2.0 #include <linux/clk-provider.h> #include <linux/mfd/syscon.h> #include <linux/slab.h> #include <dt-bindings/clock/at91.h> #include "pmc.h" static DEFINE_SPINLOCK(mck_lock); static const struct clk_master_characteristics mck_characteristics = { .output = { .min = 0, .max = 133333333 }, .divisors = { 1, 2, 4, 3 }, .have_div3_pres = 1, }; static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 }; static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 }; static const struct clk_range plla_outputs[] = { { .min = 745000000, .max = 800000000 }, { .min = 695000000, .max = 750000000 }, { .min = 645000000, .max = 700000000 }, { .min = 595000000, .max = 650000000 }, { .min = 545000000, .max = 600000000 }, { .min = 495000000, .max = 555000000 }, { .min = 445000000, .max = 500000000 }, { .min = 400000000, .max = 450000000 }, }; static const struct clk_pll_characteristics plla_characteristics = { .input = { .min = 2000000, .max = 32000000 }, .num_output = ARRAY_SIZE(plla_outputs), .output = plla_outputs, .icpll = plla_icpll, .out = plla_out, }; static const struct { char *n; char *p; unsigned long flags; u8 id; } at91sam9x5_systemck[] = { /* * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, { .n = "smdck", .p = "smdclk", .id = 4 }, { .n = "uhpck", .p = "usbck", .id = 6 }, { .n = "udpck", .p = "usbck", .id = 7 }, { .n = "pck0", .p = "prog0", .id = 8 }, { .n = "pck1", .p = "prog1", .id = 9 }, }; static const struct clk_pcr_layout at91sam9x5_pcr_layout = { .offset = 0x10c, .cmd = BIT(12), .pid_mask = GENMASK(5, 0), .div_mask = GENMASK(17, 16), }; struct pck { char *n; u8 id; }; static const struct pck at91sam9x5_periphck[] = { { .n = "pioAB_clk", .id = 2, }, { .n = "pioCD_clk", .id = 3, }, { .n = "smd_clk", .id = 4, }, { .n = "usart0_clk", .id = 5, }, { .n = "usart1_clk", .id = 6, }, { .n = "usart2_clk", .id = 7, }, { .n = "twi0_clk", .id = 9, }, { .n = "twi1_clk", .id = 10, }, { .n = "twi2_clk", .id = 11, }, { .n = "mci0_clk", .id = 12, }, { .n = "spi0_clk", .id = 13, }, { .n = "spi1_clk", .id = 14, }, { .n = "uart0_clk", .id = 15, }, { .n = "uart1_clk", .id = 16, }, { .n = "tcb0_clk", .id = 17, }, { .n = "pwm_clk", .id = 18, }, { .n = "adc_clk", .id = 19, }, { .n = "dma0_clk", .id = 20, }, { .n = "dma1_clk", .id = 21, }, { .n = "uhphs_clk", .id = 22, }, { .n = "udphs_clk", .id = 23, }, { .n = "mci1_clk", .id = 26, }, { .n = "ssc0_clk", .id = 28, }, }; static const struct pck at91sam9g15_periphck[] = { { .n = "lcdc_clk", .id = 25, }, { /* sentinel */} }; static const struct pck at91sam9g25_periphck[] = { { .n = "usart3_clk", .id = 8, }, { .n = "macb0_clk", .id = 24, }, { .n = "isi_clk", .id = 25, }, { /* sentinel */} }; static const struct pck at91sam9g35_periphck[] = { { .n = "macb0_clk", .id = 24, }, { .n = "lcdc_clk", .id = 25, }, { /* sentinel */} }; static const struct pck at91sam9x25_periphck[] = { { .n = "usart3_clk", .id = 8, }, { .n = "macb0_clk", .id = 24, }, { .n = "macb1_clk", .id = 27, }, { .n = "can0_clk", .id = 29, }, { .n = "can1_clk", .id = 30, }, { /* sentinel */} }; static const struct pck at91sam9x35_periphck[] = { { .n = "macb0_clk", .id = 24, }, { .n = "lcdc_clk", .id = 25, }, { .n = "can0_clk", .id = 29, }, { .n = "can1_clk", .id = 30, }, { /* sentinel */} }; static void __init at91sam9x5_pmc_setup(struct device_node *np, const struct pck *extra_pcks, bool has_lcdck) { struct clk_range range = CLK_RANGE(0, 0); const char *slck_name, *mainxtal_name; struct pmc_data *at91sam9x5_pmc; const char *parent_names[6]; struct regmap *regmap; struct clk_hw *hw; int i; bool bypass; i = of_property_match_string(np, "clock-names", "slow_clk"); if (i < 0) return; slck_name = of_clk_get_parent_name(np, i); i = of_property_match_string(np, "clock-names", "main_xtal"); if (i < 0) return; mainxtal_name = of_clk_get_parent_name(np, i); regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; at91sam9x5_pmc = pmc_data_allocate(PMC_PLLACK + 1, nck(at91sam9x5_systemck), 31, 0, 2); if (!at91sam9x5_pmc) return; hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 50000000); if (IS_ERR(hw)) goto err_free; bypass = of_property_read_bool(np, "atmel,osc-bypass"); hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, bypass); if (IS_ERR(hw)) goto err_free; parent_names[0] = "main_rc_osc"; parent_names[1] = "main_osc"; hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2); if (IS_ERR(hw)) goto err_free; at91sam9x5_pmc->chws[PMC_MAIN] = hw; hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, &at91rm9200_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); if (IS_ERR(hw)) goto err_free; at91sam9x5_pmc->chws[PMC_PLLACK] = hw; hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); if (IS_ERR(hw)) goto err_free; at91sam9x5_pmc->chws[PMC_UTMI] = hw; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, parent_names, NULL, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_master_div(regmap, "masterck_div", "masterck_pres", NULL, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; at91sam9x5_pmc->chws[PMC_MCK] = hw; parent_names[0] = "plladivck"; parent_names[1] = "utmick"; hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); if (IS_ERR(hw)) goto err_free; hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2); if (IS_ERR(hw)) goto err_free; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; parent_names[4] = "masterck_div"; for (i = 0; i < 2; i++) { char name[6]; snprintf(name, sizeof(name), "prog%d", i); hw = at91_clk_register_programmable(regmap, name, parent_names, NULL, 5, i, &at91sam9x5_programmable_layout, NULL); if (IS_ERR(hw)) goto err_free; at91sam9x5_pmc->pchws[i] = hw; } for (i = 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) { hw = at91_clk_register_system(regmap, at91sam9x5_systemck[i].n, at91sam9x5_systemck[i].p, NULL, at91sam9x5_systemck[i].id, at91sam9x5_systemck[i].flags); if (IS_ERR(hw)) goto err_free; at91sam9x5_pmc->shws[at91sam9x5_systemck[i].id] = hw; } if (has_lcdck) { hw = at91_clk_register_system(regmap, "lcdck", "masterck_div", NULL, 3, 0); if (IS_ERR(hw)) goto err_free; at91sam9x5_pmc->shws[3] = hw; } for (i = 0; i < ARRAY_SIZE(at91sam9x5_periphck); i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &at91sam9x5_pcr_layout, at91sam9x5_periphck[i].n, "masterck_div", NULL, at91sam9x5_periphck[i].id, &range, INT_MIN, 0); if (IS_ERR(hw)) goto err_free; at91sam9x5_pmc->phws[at91sam9x5_periphck[i].id] = hw; } for (i = 0; extra_pcks[i].id; i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &at91sam9x5_pcr_layout, extra_pcks[i].n, "masterck_div", NULL, extra_pcks[i].id, &range, INT_MIN, 0); if (IS_ERR(hw)) goto err_free; at91sam9x5_pmc->phws[extra_pcks[i].id] = hw; } of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9x5_pmc); return; err_free: kfree(at91sam9x5_pmc); } static void __init at91sam9g15_pmc_setup(struct device_node *np) { at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true); } CLK_OF_DECLARE(at91sam9g15_pmc, "atmel,at91sam9g15-pmc", at91sam9g15_pmc_setup); static void __init at91sam9g25_pmc_setup(struct device_node *np) { at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false); } CLK_OF_DECLARE(at91sam9g25_pmc, "atmel,at91sam9g25-pmc", at91sam9g25_pmc_setup); static void __init at91sam9g35_pmc_setup(struct device_node *np) { at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true); } CLK_OF_DECLARE(at91sam9g35_pmc, "atmel,at91sam9g35-pmc", at91sam9g35_pmc_setup); static void __init at91sam9x25_pmc_setup(struct device_node *np) { at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false); } CLK_OF_DECLARE(at91sam9x25_pmc, "atmel,at91sam9x25-pmc", at91sam9x25_pmc_setup); static void __init at91sam9x35_pmc_setup(struct device_node *np) { at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true); } CLK_OF_DECLARE(at91sam9x35_pmc, "atmel,at91sam9x35-pmc", at91sam9x35_pmc_setup);
linux-master
drivers/clk/at91/at91sam9x5.c
// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2018 Microchip Technology Inc, * Codrin Ciubotariu <[email protected]> * * */ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include <linux/slab.h> #include <soc/at91/atmel-sfr.h> #include "pmc.h" struct clk_i2s_mux { struct clk_hw hw; struct regmap *regmap; u8 bus_id; }; #define to_clk_i2s_mux(hw) container_of(hw, struct clk_i2s_mux, hw) static u8 clk_i2s_mux_get_parent(struct clk_hw *hw) { struct clk_i2s_mux *mux = to_clk_i2s_mux(hw); u32 val; regmap_read(mux->regmap, AT91_SFR_I2SCLKSEL, &val); return (val & BIT(mux->bus_id)) >> mux->bus_id; } static int clk_i2s_mux_set_parent(struct clk_hw *hw, u8 index) { struct clk_i2s_mux *mux = to_clk_i2s_mux(hw); return regmap_update_bits(mux->regmap, AT91_SFR_I2SCLKSEL, BIT(mux->bus_id), index << mux->bus_id); } static const struct clk_ops clk_i2s_mux_ops = { .get_parent = clk_i2s_mux_get_parent, .set_parent = clk_i2s_mux_set_parent, .determine_rate = __clk_mux_determine_rate, }; struct clk_hw * __init at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, const char * const *parent_names, unsigned int num_parents, u8 bus_id) { struct clk_init_data init = {}; struct clk_i2s_mux *i2s_ck; int ret; i2s_ck = kzalloc(sizeof(*i2s_ck), GFP_KERNEL); if (!i2s_ck) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &clk_i2s_mux_ops; init.parent_names = parent_names; init.num_parents = num_parents; i2s_ck->hw.init = &init; i2s_ck->bus_id = bus_id; i2s_ck->regmap = regmap; ret = clk_hw_register(NULL, &i2s_ck->hw); if (ret) { kfree(i2s_ck); return ERR_PTR(ret); } return &i2s_ck->hw; }
linux-master
drivers/clk/at91/clk-i2s-mux.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <[email protected]> */ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "pmc.h" #define MASTER_PRES_MASK 0x7 #define MASTER_PRES_MAX MASTER_PRES_MASK #define MASTER_DIV_SHIFT 8 #define MASTER_DIV_MASK 0x7 #define PMC_MCR_CSS_SHIFT (16) #define MASTER_MAX_ID 4 #define to_clk_master(hw) container_of(hw, struct clk_master, hw) struct clk_master { struct clk_hw hw; struct regmap *regmap; spinlock_t *lock; const struct clk_master_layout *layout; const struct clk_master_characteristics *characteristics; struct at91_clk_pms pms; u32 *mux_table; u32 mckr; int chg_pid; u8 id; u8 parent; u8 div; u32 safe_div; }; /* MCK div reference to be used by notifier. */ static struct clk_master *master_div; static inline bool clk_master_ready(struct clk_master *master) { unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY; unsigned int status; regmap_read(master->regmap, AT91_PMC_SR, &status); return !!(status & bit); } static int clk_master_prepare(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); unsigned long flags; spin_lock_irqsave(master->lock, flags); while (!clk_master_ready(master)) cpu_relax(); spin_unlock_irqrestore(master->lock, flags); return 0; } static int clk_master_is_prepared(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); unsigned long flags; bool status; spin_lock_irqsave(master->lock, flags); status = clk_master_ready(master); spin_unlock_irqrestore(master->lock, flags); return status; } static unsigned long clk_master_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { u8 div; unsigned long flags, rate = parent_rate; struct clk_master *master = to_clk_master(hw); const struct clk_master_layout *layout = master->layout; const struct clk_master_characteristics *characteristics = master->characteristics; unsigned int mckr; spin_lock_irqsave(master->lock, flags); regmap_read(master->regmap, master->layout->offset, &mckr); spin_unlock_irqrestore(master->lock, flags); mckr &= layout->mask; div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; rate /= characteristics->divisors[div]; if (rate < characteristics->output.min) pr_warn("master clk div is underclocked"); else if (rate > characteristics->output.max) pr_warn("master clk div is overclocked"); return rate; } static int clk_master_div_save_context(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); struct clk_hw *parent_hw = clk_hw_get_parent(hw); unsigned long flags; unsigned int mckr, div; spin_lock_irqsave(master->lock, flags); regmap_read(master->regmap, master->layout->offset, &mckr); spin_unlock_irqrestore(master->lock, flags); mckr &= master->layout->mask; div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; div = master->characteristics->divisors[div]; master->pms.parent_rate = clk_hw_get_rate(parent_hw); master->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div); return 0; } static void clk_master_div_restore_context(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); unsigned long flags; unsigned int mckr; u8 div; spin_lock_irqsave(master->lock, flags); regmap_read(master->regmap, master->layout->offset, &mckr); spin_unlock_irqrestore(master->lock, flags); mckr &= master->layout->mask; div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; div = master->characteristics->divisors[div]; if (div != DIV_ROUND_CLOSEST(master->pms.parent_rate, master->pms.rate)) pr_warn("MCKR DIV not configured properly by firmware!\n"); } static const struct clk_ops master_div_ops = { .prepare = clk_master_prepare, .is_prepared = clk_master_is_prepared, .recalc_rate = clk_master_div_recalc_rate, .save_context = clk_master_div_save_context, .restore_context = clk_master_div_restore_context, }; /* This function must be called with lock acquired. */ static int clk_master_div_set(struct clk_master *master, unsigned long parent_rate, int div) { const struct clk_master_characteristics *characteristics = master->characteristics; unsigned long rate = parent_rate; unsigned int max_div = 0, div_index = 0, max_div_index = 0; unsigned int i, mckr, tmp; int ret; for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { if (!characteristics->divisors[i]) break; if (div == characteristics->divisors[i]) div_index = i; if (max_div < characteristics->divisors[i]) { max_div = characteristics->divisors[i]; max_div_index = i; } } if (div > max_div) div_index = max_div_index; ret = regmap_read(master->regmap, master->layout->offset, &mckr); if (ret) return ret; mckr &= master->layout->mask; tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; if (tmp == div_index) return 0; rate /= characteristics->divisors[div_index]; if (rate < characteristics->output.min) pr_warn("master clk div is underclocked"); else if (rate > characteristics->output.max) pr_warn("master clk div is overclocked"); mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT); mckr |= (div_index << MASTER_DIV_SHIFT); ret = regmap_write(master->regmap, master->layout->offset, mckr); if (ret) return ret; while (!clk_master_ready(master)) cpu_relax(); master->div = characteristics->divisors[div_index]; return 0; } static unsigned long clk_master_div_recalc_rate_chg(struct clk_hw *hw, unsigned long parent_rate) { struct clk_master *master = to_clk_master(hw); return DIV_ROUND_CLOSEST_ULL(parent_rate, master->div); } static void clk_master_div_restore_context_chg(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); unsigned long flags; int ret; spin_lock_irqsave(master->lock, flags); ret = clk_master_div_set(master, master->pms.parent_rate, DIV_ROUND_CLOSEST(master->pms.parent_rate, master->pms.rate)); spin_unlock_irqrestore(master->lock, flags); if (ret) pr_warn("Failed to restore MCK DIV clock\n"); } static const struct clk_ops master_div_ops_chg = { .prepare = clk_master_prepare, .is_prepared = clk_master_is_prepared, .recalc_rate = clk_master_div_recalc_rate_chg, .save_context = clk_master_div_save_context, .restore_context = clk_master_div_restore_context_chg, }; static int clk_master_div_notifier_fn(struct notifier_block *notifier, unsigned long code, void *data) { const struct clk_master_characteristics *characteristics = master_div->characteristics; struct clk_notifier_data *cnd = data; unsigned long flags, new_parent_rate, new_rate; unsigned int mckr, div, new_div = 0; int ret, i; long tmp_diff; long best_diff = -1; spin_lock_irqsave(master_div->lock, flags); switch (code) { case PRE_RATE_CHANGE: /* * We want to avoid any overclocking of MCK DIV domain. To do * this we set a safe divider (the underclocking is not of * interest as we can go as low as 32KHz). The relation * b/w this clock and its parents are as follows: * * FRAC PLL -> DIV PLL -> MCK DIV * * With the proper safe divider we should be good even with FRAC * PLL at its maximum value. */ ret = regmap_read(master_div->regmap, master_div->layout->offset, &mckr); if (ret) { ret = NOTIFY_STOP_MASK; goto unlock; } mckr &= master_div->layout->mask; div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; /* Switch to safe divider. */ clk_master_div_set(master_div, cnd->old_rate * characteristics->divisors[div], master_div->safe_div); break; case POST_RATE_CHANGE: /* * At this point we want to restore MCK DIV domain to its maximum * allowed rate. */ ret = regmap_read(master_div->regmap, master_div->layout->offset, &mckr); if (ret) { ret = NOTIFY_STOP_MASK; goto unlock; } mckr &= master_div->layout->mask; div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; new_parent_rate = cnd->new_rate * characteristics->divisors[div]; for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { if (!characteristics->divisors[i]) break; new_rate = DIV_ROUND_CLOSEST_ULL(new_parent_rate, characteristics->divisors[i]); tmp_diff = characteristics->output.max - new_rate; if (tmp_diff < 0) continue; if (best_diff < 0 || best_diff > tmp_diff) { new_div = characteristics->divisors[i]; best_diff = tmp_diff; } if (!tmp_diff) break; } if (!new_div) { ret = NOTIFY_STOP_MASK; goto unlock; } /* Update the div to preserve MCK DIV clock rate. */ clk_master_div_set(master_div, new_parent_rate, new_div); ret = NOTIFY_OK; break; default: ret = NOTIFY_DONE; break; } unlock: spin_unlock_irqrestore(master_div->lock, flags); return ret; } static struct notifier_block clk_master_div_notifier = { .notifier_call = clk_master_div_notifier_fn, }; static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, struct clk_hw *parent, unsigned long parent_rate, long *best_rate, long *best_diff, u32 div) { unsigned long tmp_rate, tmp_diff; if (div == MASTER_PRES_MAX) tmp_rate = parent_rate / 3; else tmp_rate = parent_rate >> div; tmp_diff = abs(req->rate - tmp_rate); if (*best_diff < 0 || *best_diff >= tmp_diff) { *best_rate = tmp_rate; *best_diff = tmp_diff; req->best_parent_rate = parent_rate; req->best_parent_hw = parent; } } static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_master *master = to_clk_master(hw); const struct clk_master_characteristics *characteristics = master->characteristics; unsigned long flags; unsigned int val, pres; spin_lock_irqsave(master->lock, flags); regmap_read(master->regmap, master->layout->offset, &val); spin_unlock_irqrestore(master->lock, flags); val &= master->layout->mask; pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres) pres = 3; else pres = (1 << pres); return DIV_ROUND_CLOSEST_ULL(parent_rate, pres); } static u8 clk_master_pres_get_parent(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); unsigned long flags; unsigned int mckr; spin_lock_irqsave(master->lock, flags); regmap_read(master->regmap, master->layout->offset, &mckr); spin_unlock_irqrestore(master->lock, flags); mckr &= master->layout->mask; return mckr & AT91_PMC_CSS; } static int clk_master_pres_save_context(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); struct clk_hw *parent_hw = clk_hw_get_parent(hw); unsigned long flags; unsigned int val, pres; spin_lock_irqsave(master->lock, flags); regmap_read(master->regmap, master->layout->offset, &val); spin_unlock_irqrestore(master->lock, flags); val &= master->layout->mask; pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres) pres = 3; else pres = (1 << pres); master->pms.parent = val & AT91_PMC_CSS; master->pms.parent_rate = clk_hw_get_rate(parent_hw); master->pms.rate = DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres); return 0; } static void clk_master_pres_restore_context(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); unsigned long flags; unsigned int val, pres; spin_lock_irqsave(master->lock, flags); regmap_read(master->regmap, master->layout->offset, &val); spin_unlock_irqrestore(master->lock, flags); val &= master->layout->mask; pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres) pres = 3; else pres = (1 << pres); if (master->pms.rate != DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres) || (master->pms.parent != (val & AT91_PMC_CSS))) pr_warn("MCKR PRES was not configured properly by firmware!\n"); } static const struct clk_ops master_pres_ops = { .prepare = clk_master_prepare, .is_prepared = clk_master_is_prepared, .recalc_rate = clk_master_pres_recalc_rate, .get_parent = clk_master_pres_get_parent, .save_context = clk_master_pres_save_context, .restore_context = clk_master_pres_restore_context, }; static struct clk_hw * __init at91_clk_register_master_internal(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, struct clk_hw **parent_hws, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, const struct clk_ops *ops, spinlock_t *lock, u32 flags) { struct clk_master *master; struct clk_init_data init = {}; struct clk_hw *hw; unsigned int mckr; unsigned long irqflags; int ret; if (!name || !num_parents || !(parent_names || parent_hws) || !lock) return ERR_PTR(-EINVAL); master = kzalloc(sizeof(*master), GFP_KERNEL); if (!master) return ERR_PTR(-ENOMEM); init.name = name; init.ops = ops; if (parent_hws) init.parent_hws = (const struct clk_hw **)parent_hws; else init.parent_names = parent_names; init.num_parents = num_parents; init.flags = flags; master->hw.init = &init; master->layout = layout; master->characteristics = characteristics; master->regmap = regmap; master->lock = lock; if (ops == &master_div_ops_chg) { spin_lock_irqsave(master->lock, irqflags); regmap_read(master->regmap, master->layout->offset, &mckr); spin_unlock_irqrestore(master->lock, irqflags); mckr &= layout->mask; mckr = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; master->div = characteristics->divisors[mckr]; } hw = &master->hw; ret = clk_hw_register(NULL, &master->hw); if (ret) { kfree(master); hw = ERR_PTR(ret); } return hw; } struct clk_hw * __init at91_clk_register_master_pres(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, struct clk_hw **parent_hws, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, spinlock_t *lock) { return at91_clk_register_master_internal(regmap, name, num_parents, parent_names, parent_hws, layout, characteristics, &master_pres_ops, lock, CLK_SET_RATE_GATE); } struct clk_hw * __init at91_clk_register_master_div(struct regmap *regmap, const char *name, const char *parent_name, struct clk_hw *parent_hw, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, spinlock_t *lock, u32 flags, u32 safe_div) { const struct clk_ops *ops; struct clk_hw *hw; if (flags & CLK_SET_RATE_GATE) ops = &master_div_ops; else ops = &master_div_ops_chg; hw = at91_clk_register_master_internal(regmap, name, 1, parent_name ? &parent_name : NULL, parent_hw ? &parent_hw : NULL, layout, characteristics, ops, lock, flags); if (!IS_ERR(hw) && safe_div) { master_div = to_clk_master(hw); master_div->safe_div = safe_div; clk_notifier_register(hw->clk, &clk_master_div_notifier); } return hw; } static unsigned long clk_sama7g5_master_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_master *master = to_clk_master(hw); return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div)); } static int clk_sama7g5_master_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct clk_master *master = to_clk_master(hw); struct clk_hw *parent; long best_rate = LONG_MIN, best_diff = LONG_MIN; unsigned long parent_rate; unsigned int div, i; /* First: check the dividers of MCR. */ for (i = 0; i < clk_hw_get_num_parents(hw); i++) { parent = clk_hw_get_parent_by_index(hw, i); if (!parent) continue; parent_rate = clk_hw_get_rate(parent); if (!parent_rate) continue; for (div = 0; div < MASTER_PRES_MAX + 1; div++) { clk_sama7g5_master_best_diff(req, parent, parent_rate, &best_rate, &best_diff, div); if (!best_diff) break; } if (!best_diff) break; } /* Second: try to request rate form changeable parent. */ if (master->chg_pid < 0) goto end; parent = clk_hw_get_parent_by_index(hw, master->chg_pid); if (!parent) goto end; for (div = 0; div < MASTER_PRES_MAX + 1; div++) { struct clk_rate_request req_parent; unsigned long req_rate; if (div == MASTER_PRES_MAX) req_rate = req->rate * 3; else req_rate = req->rate << div; clk_hw_forward_rate_request(hw, req, parent, &req_parent, req_rate); if (__clk_determine_rate(parent, &req_parent)) continue; clk_sama7g5_master_best_diff(req, parent, req_parent.rate, &best_rate, &best_diff, div); if (!best_diff) break; } end: pr_debug("MCK: %s, best_rate = %ld, parent clk: %s @ %ld\n", __func__, best_rate, __clk_get_name((req->best_parent_hw)->clk), req->best_parent_rate); if (best_rate < 0) return -EINVAL; req->rate = best_rate; return 0; } static u8 clk_sama7g5_master_get_parent(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); unsigned long flags; u8 index; spin_lock_irqsave(master->lock, flags); index = clk_mux_val_to_index(&master->hw, master->mux_table, 0, master->parent); spin_unlock_irqrestore(master->lock, flags); return index; } static int clk_sama7g5_master_set_parent(struct clk_hw *hw, u8 index) { struct clk_master *master = to_clk_master(hw); unsigned long flags; if (index >= clk_hw_get_num_parents(hw)) return -EINVAL; spin_lock_irqsave(master->lock, flags); master->parent = clk_mux_index_to_val(master->mux_table, 0, index); spin_unlock_irqrestore(master->lock, flags); return 0; } static void clk_sama7g5_master_set(struct clk_master *master, unsigned int status) { unsigned long flags; unsigned int val, cparent; unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0; unsigned int parent = master->parent << PMC_MCR_CSS_SHIFT; unsigned int div = master->div << MASTER_DIV_SHIFT; spin_lock_irqsave(master->lock, flags); regmap_write(master->regmap, AT91_PMC_MCR_V2, AT91_PMC_MCR_V2_ID(master->id)); regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV | AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK, enable | parent | div | AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID(master->id)); cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; /* Wait here only if parent is being changed. */ while ((cparent != master->parent) && !clk_master_ready(master)) cpu_relax(); spin_unlock_irqrestore(master->lock, flags); } static int clk_sama7g5_master_enable(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); clk_sama7g5_master_set(master, 1); return 0; } static void clk_sama7g5_master_disable(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); unsigned long flags; spin_lock_irqsave(master->lock, flags); regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, AT91_PMC_MCR_V2_EN | AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK, AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID(master->id)); spin_unlock_irqrestore(master->lock, flags); } static int clk_sama7g5_master_is_enabled(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); unsigned long flags; unsigned int val; spin_lock_irqsave(master->lock, flags); regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); spin_unlock_irqrestore(master->lock, flags); return !!(val & AT91_PMC_MCR_V2_EN); } static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_master *master = to_clk_master(hw); unsigned long div, flags; div = DIV_ROUND_CLOSEST(parent_rate, rate); if ((div > (1 << (MASTER_PRES_MAX - 1))) || (div & (div - 1))) return -EINVAL; if (div == 3) div = MASTER_PRES_MAX; else if (div) div = ffs(div) - 1; spin_lock_irqsave(master->lock, flags); master->div = div; spin_unlock_irqrestore(master->lock, flags); return 0; } static int clk_sama7g5_master_save_context(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); master->pms.status = clk_sama7g5_master_is_enabled(hw); return 0; } static void clk_sama7g5_master_restore_context(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); if (master->pms.status) clk_sama7g5_master_set(master, master->pms.status); } static const struct clk_ops sama7g5_master_ops = { .enable = clk_sama7g5_master_enable, .disable = clk_sama7g5_master_disable, .is_enabled = clk_sama7g5_master_is_enabled, .recalc_rate = clk_sama7g5_master_recalc_rate, .determine_rate = clk_sama7g5_master_determine_rate, .set_rate = clk_sama7g5_master_set_rate, .get_parent = clk_sama7g5_master_get_parent, .set_parent = clk_sama7g5_master_set_parent, .save_context = clk_sama7g5_master_save_context, .restore_context = clk_sama7g5_master_restore_context, }; struct clk_hw * __init at91_clk_sama7g5_register_master(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, struct clk_hw **parent_hws, u32 *mux_table, spinlock_t *lock, u8 id, bool critical, int chg_pid) { struct clk_master *master; struct clk_hw *hw; struct clk_init_data init = {}; unsigned long flags; unsigned int val; int ret; if (!name || !num_parents || !(parent_names || parent_hws) || !mux_table || !lock || id > MASTER_MAX_ID) return ERR_PTR(-EINVAL); master = kzalloc(sizeof(*master), GFP_KERNEL); if (!master) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &sama7g5_master_ops; if (parent_hws) init.parent_hws = (const struct clk_hw **)parent_hws; else init.parent_names = parent_names; init.num_parents = num_parents; init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; if (chg_pid >= 0) init.flags |= CLK_SET_RATE_PARENT; if (critical) init.flags |= CLK_IS_CRITICAL; master->hw.init = &init; master->regmap = regmap; master->id = id; master->chg_pid = chg_pid; master->lock = lock; master->mux_table = mux_table; spin_lock_irqsave(master->lock, flags); regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT; spin_unlock_irqrestore(master->lock, flags); hw = &master->hw; ret = clk_hw_register(NULL, &master->hw); if (ret) { kfree(master); hw = ERR_PTR(ret); } return hw; } const struct clk_master_layout at91rm9200_master_layout = { .mask = 0x31F, .pres_shift = 2, .offset = AT91_PMC_MCKR, }; const struct clk_master_layout at91sam9x5_master_layout = { .mask = 0x373, .pres_shift = 4, .offset = AT91_PMC_MCKR, };
linux-master
drivers/clk/at91/clk-master.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <[email protected]> */ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "pmc.h" #define SAM9X5_USB_DIV_SHIFT 8 #define SAM9X5_USB_MAX_DIV 0xf #define RM9200_USB_DIV_SHIFT 28 #define RM9200_USB_DIV_TAB_SIZE 4 #define SAM9X5_USBS_MASK GENMASK(0, 0) #define SAM9X60_USBS_MASK GENMASK(1, 0) struct at91sam9x5_clk_usb { struct clk_hw hw; struct regmap *regmap; struct at91_clk_pms pms; u32 usbs_mask; u8 num_parents; }; #define to_at91sam9x5_clk_usb(hw) \ container_of(hw, struct at91sam9x5_clk_usb, hw) struct at91rm9200_clk_usb { struct clk_hw hw; struct regmap *regmap; u32 divisors[4]; }; #define to_at91rm9200_clk_usb(hw) \ container_of(hw, struct at91rm9200_clk_usb, hw) static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); unsigned int usbr; u8 usbdiv; regmap_read(usb->regmap, AT91_PMC_USB, &usbr); usbdiv = (usbr & AT91_PMC_OHCIUSBDIV) >> SAM9X5_USB_DIV_SHIFT; return DIV_ROUND_CLOSEST(parent_rate, (usbdiv + 1)); } static int at91sam9x5_clk_usb_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct clk_hw *parent; long best_rate = -EINVAL; unsigned long tmp_rate; int best_diff = -1; int tmp_diff; int i; for (i = 0; i < clk_hw_get_num_parents(hw); i++) { int div; parent = clk_hw_get_parent_by_index(hw, i); if (!parent) continue; for (div = 1; div < SAM9X5_USB_MAX_DIV + 2; div++) { unsigned long tmp_parent_rate; tmp_parent_rate = req->rate * div; tmp_parent_rate = clk_hw_round_rate(parent, tmp_parent_rate); if (!tmp_parent_rate) continue; tmp_rate = DIV_ROUND_CLOSEST(tmp_parent_rate, div); if (tmp_rate < req->rate) tmp_diff = req->rate - tmp_rate; else tmp_diff = tmp_rate - req->rate; if (best_diff < 0 || best_diff > tmp_diff) { best_rate = tmp_rate; best_diff = tmp_diff; req->best_parent_rate = tmp_parent_rate; req->best_parent_hw = parent; } if (!best_diff || tmp_rate < req->rate) break; } if (!best_diff) break; } if (best_rate < 0) return best_rate; req->rate = best_rate; return 0; } static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index) { struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); if (index >= usb->num_parents) return -EINVAL; regmap_update_bits(usb->regmap, AT91_PMC_USB, usb->usbs_mask, index); return 0; } static u8 at91sam9x5_clk_usb_get_parent(struct clk_hw *hw) { struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); unsigned int usbr; regmap_read(usb->regmap, AT91_PMC_USB, &usbr); return usbr & usb->usbs_mask; } static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); unsigned long div; if (!rate) return -EINVAL; div = DIV_ROUND_CLOSEST(parent_rate, rate); if (div > SAM9X5_USB_MAX_DIV + 1 || !div) return -EINVAL; regmap_update_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_OHCIUSBDIV, (div - 1) << SAM9X5_USB_DIV_SHIFT); return 0; } static int at91sam9x5_usb_save_context(struct clk_hw *hw) { struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); struct clk_hw *parent_hw = clk_hw_get_parent(hw); usb->pms.parent = at91sam9x5_clk_usb_get_parent(hw); usb->pms.parent_rate = clk_hw_get_rate(parent_hw); usb->pms.rate = at91sam9x5_clk_usb_recalc_rate(hw, usb->pms.parent_rate); return 0; } static void at91sam9x5_usb_restore_context(struct clk_hw *hw) { struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); int ret; ret = at91sam9x5_clk_usb_set_parent(hw, usb->pms.parent); if (ret) return; at91sam9x5_clk_usb_set_rate(hw, usb->pms.rate, usb->pms.parent_rate); } static const struct clk_ops at91sam9x5_usb_ops = { .recalc_rate = at91sam9x5_clk_usb_recalc_rate, .determine_rate = at91sam9x5_clk_usb_determine_rate, .get_parent = at91sam9x5_clk_usb_get_parent, .set_parent = at91sam9x5_clk_usb_set_parent, .set_rate = at91sam9x5_clk_usb_set_rate, .save_context = at91sam9x5_usb_save_context, .restore_context = at91sam9x5_usb_restore_context, }; static int at91sam9n12_clk_usb_enable(struct clk_hw *hw) { struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); regmap_update_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_USBS, AT91_PMC_USBS); return 0; } static void at91sam9n12_clk_usb_disable(struct clk_hw *hw) { struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); regmap_update_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_USBS, 0); } static int at91sam9n12_clk_usb_is_enabled(struct clk_hw *hw) { struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); unsigned int usbr; regmap_read(usb->regmap, AT91_PMC_USB, &usbr); return usbr & AT91_PMC_USBS; } static const struct clk_ops at91sam9n12_usb_ops = { .enable = at91sam9n12_clk_usb_enable, .disable = at91sam9n12_clk_usb_disable, .is_enabled = at91sam9n12_clk_usb_is_enabled, .recalc_rate = at91sam9x5_clk_usb_recalc_rate, .determine_rate = at91sam9x5_clk_usb_determine_rate, .set_rate = at91sam9x5_clk_usb_set_rate, }; static struct clk_hw * __init _at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, const char **parent_names, u8 num_parents, u32 usbs_mask) { struct at91sam9x5_clk_usb *usb; struct clk_hw *hw; struct clk_init_data init; int ret; usb = kzalloc(sizeof(*usb), GFP_KERNEL); if (!usb) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &at91sam9x5_usb_ops; init.parent_names = parent_names; init.num_parents = num_parents; init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT; usb->hw.init = &init; usb->regmap = regmap; usb->usbs_mask = usbs_mask; usb->num_parents = num_parents; hw = &usb->hw; ret = clk_hw_register(NULL, &usb->hw); if (ret) { kfree(usb); hw = ERR_PTR(ret); } return hw; } struct clk_hw * __init at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, const char **parent_names, u8 num_parents) { return _at91sam9x5_clk_register_usb(regmap, name, parent_names, num_parents, SAM9X5_USBS_MASK); } struct clk_hw * __init sam9x60_clk_register_usb(struct regmap *regmap, const char *name, const char **parent_names, u8 num_parents) { return _at91sam9x5_clk_register_usb(regmap, name, parent_names, num_parents, SAM9X60_USBS_MASK); } struct clk_hw * __init at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name, const char *parent_name) { struct at91sam9x5_clk_usb *usb; struct clk_hw *hw; struct clk_init_data init; int ret; usb = kzalloc(sizeof(*usb), GFP_KERNEL); if (!usb) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &at91sam9n12_usb_ops; init.parent_names = &parent_name; init.num_parents = 1; init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT; usb->hw.init = &init; usb->regmap = regmap; hw = &usb->hw; ret = clk_hw_register(NULL, &usb->hw); if (ret) { kfree(usb); hw = ERR_PTR(ret); } return hw; } static unsigned long at91rm9200_clk_usb_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw); unsigned int pllbr; u8 usbdiv; regmap_read(usb->regmap, AT91_CKGR_PLLBR, &pllbr); usbdiv = (pllbr & AT91_PMC_USBDIV) >> RM9200_USB_DIV_SHIFT; if (usb->divisors[usbdiv]) return parent_rate / usb->divisors[usbdiv]; return 0; } static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw); struct clk_hw *parent = clk_hw_get_parent(hw); unsigned long bestrate = 0; int bestdiff = -1; unsigned long tmprate; int tmpdiff; int i = 0; for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) { unsigned long tmp_parent_rate; if (!usb->divisors[i]) continue; tmp_parent_rate = rate * usb->divisors[i]; tmp_parent_rate = clk_hw_round_rate(parent, tmp_parent_rate); tmprate = DIV_ROUND_CLOSEST(tmp_parent_rate, usb->divisors[i]); if (tmprate < rate) tmpdiff = rate - tmprate; else tmpdiff = tmprate - rate; if (bestdiff < 0 || bestdiff > tmpdiff) { bestrate = tmprate; bestdiff = tmpdiff; *parent_rate = tmp_parent_rate; } if (!bestdiff) break; } return bestrate; } static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { int i; struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw); unsigned long div; if (!rate) return -EINVAL; div = DIV_ROUND_CLOSEST(parent_rate, rate); for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) { if (usb->divisors[i] == div) { regmap_update_bits(usb->regmap, AT91_CKGR_PLLBR, AT91_PMC_USBDIV, i << RM9200_USB_DIV_SHIFT); return 0; } } return -EINVAL; } static const struct clk_ops at91rm9200_usb_ops = { .recalc_rate = at91rm9200_clk_usb_recalc_rate, .round_rate = at91rm9200_clk_usb_round_rate, .set_rate = at91rm9200_clk_usb_set_rate, }; struct clk_hw * __init at91rm9200_clk_register_usb(struct regmap *regmap, const char *name, const char *parent_name, const u32 *divisors) { struct at91rm9200_clk_usb *usb; struct clk_hw *hw; struct clk_init_data init; int ret; usb = kzalloc(sizeof(*usb), GFP_KERNEL); if (!usb) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &at91rm9200_usb_ops; init.parent_names = &parent_name; init.num_parents = 1; init.flags = CLK_SET_RATE_PARENT; usb->hw.init = &init; usb->regmap = regmap; memcpy(usb->divisors, divisors, sizeof(usb->divisors)); hw = &usb->hw; ret = clk_hw_register(NULL, &usb->hw); if (ret) { kfree(usb); hw = ERR_PTR(ret); } return hw; }
linux-master
drivers/clk/at91/clk-usb.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * clk-h32mx.c * * Copyright (C) 2014 Atmel * * Alexandre Belloni <[email protected]> */ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/regmap.h> #include <linux/mfd/syscon.h> #include "pmc.h" #define H32MX_MAX_FREQ 90000000 struct clk_sama5d4_h32mx { struct clk_hw hw; struct regmap *regmap; }; #define to_clk_sama5d4_h32mx(hw) container_of(hw, struct clk_sama5d4_h32mx, hw) static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw); unsigned int mckr; regmap_read(h32mxclk->regmap, AT91_PMC_MCKR, &mckr); if (mckr & AT91_PMC_H32MXDIV) return parent_rate / 2; if (parent_rate > H32MX_MAX_FREQ) pr_warn("H32MX clock is too fast\n"); return parent_rate; } static long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { unsigned long div; if (rate > *parent_rate) return *parent_rate; div = *parent_rate / 2; if (rate < div) return div; if (rate - div < *parent_rate - rate) return div; return *parent_rate; } static int clk_sama5d4_h32mx_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw); u32 mckr = 0; if (parent_rate != rate && (parent_rate / 2) != rate) return -EINVAL; if ((parent_rate / 2) == rate) mckr = AT91_PMC_H32MXDIV; regmap_update_bits(h32mxclk->regmap, AT91_PMC_MCKR, AT91_PMC_H32MXDIV, mckr); return 0; } static const struct clk_ops h32mx_ops = { .recalc_rate = clk_sama5d4_h32mx_recalc_rate, .round_rate = clk_sama5d4_h32mx_round_rate, .set_rate = clk_sama5d4_h32mx_set_rate, }; struct clk_hw * __init at91_clk_register_h32mx(struct regmap *regmap, const char *name, const char *parent_name) { struct clk_sama5d4_h32mx *h32mxclk; struct clk_init_data init; int ret; h32mxclk = kzalloc(sizeof(*h32mxclk), GFP_KERNEL); if (!h32mxclk) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &h32mx_ops; init.parent_names = parent_name ? &parent_name : NULL; init.num_parents = parent_name ? 1 : 0; init.flags = CLK_SET_RATE_GATE; h32mxclk->hw.init = &init; h32mxclk->regmap = regmap; ret = clk_hw_register(NULL, &h32mxclk->hw); if (ret) { kfree(h32mxclk); return ERR_PTR(ret); } return &h32mxclk->hw; }
linux-master
drivers/clk/at91/clk-h32mx.c
// SPDX-License-Identifier: GPL-2.0 #include <linux/clk-provider.h> #include <linux/mfd/syscon.h> #include <linux/slab.h> #include <dt-bindings/clock/at91.h> #include "pmc.h" static DEFINE_SPINLOCK(sam9rl_mck_lock); static const struct clk_master_characteristics sam9rl_mck_characteristics = { .output = { .min = 0, .max = 94000000 }, .divisors = { 1, 2, 4, 0 }, }; static u8 sam9rl_plla_out[] = { 0, 2 }; static const struct clk_range sam9rl_plla_outputs[] = { { .min = 80000000, .max = 200000000 }, { .min = 190000000, .max = 240000000 }, }; static const struct clk_pll_characteristics sam9rl_plla_characteristics = { .input = { .min = 1000000, .max = 32000000 }, .num_output = ARRAY_SIZE(sam9rl_plla_outputs), .output = sam9rl_plla_outputs, .out = sam9rl_plla_out, }; static const struct { char *n; char *p; u8 id; } at91sam9rl_systemck[] = { { .n = "pck0", .p = "prog0", .id = 8 }, { .n = "pck1", .p = "prog1", .id = 9 }, }; static const struct { char *n; u8 id; } at91sam9rl_periphck[] = { { .n = "pioA_clk", .id = 2, }, { .n = "pioB_clk", .id = 3, }, { .n = "pioC_clk", .id = 4, }, { .n = "pioD_clk", .id = 5, }, { .n = "usart0_clk", .id = 6, }, { .n = "usart1_clk", .id = 7, }, { .n = "usart2_clk", .id = 8, }, { .n = "usart3_clk", .id = 9, }, { .n = "mci0_clk", .id = 10, }, { .n = "twi0_clk", .id = 11, }, { .n = "twi1_clk", .id = 12, }, { .n = "spi0_clk", .id = 13, }, { .n = "ssc0_clk", .id = 14, }, { .n = "ssc1_clk", .id = 15, }, { .n = "tc0_clk", .id = 16, }, { .n = "tc1_clk", .id = 17, }, { .n = "tc2_clk", .id = 18, }, { .n = "pwm_clk", .id = 19, }, { .n = "adc_clk", .id = 20, }, { .n = "dma0_clk", .id = 21, }, { .n = "udphs_clk", .id = 22, }, { .n = "lcd_clk", .id = 23, }, }; static void __init at91sam9rl_pmc_setup(struct device_node *np) { const char *slck_name, *mainxtal_name; struct pmc_data *at91sam9rl_pmc; const char *parent_names[6]; struct regmap *regmap; struct clk_hw *hw; int i; i = of_property_match_string(np, "clock-names", "slow_clk"); if (i < 0) return; slck_name = of_clk_get_parent_name(np, i); i = of_property_match_string(np, "clock-names", "main_xtal"); if (i < 0) return; mainxtal_name = of_clk_get_parent_name(np, i); regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; at91sam9rl_pmc = pmc_data_allocate(PMC_PLLACK + 1, nck(at91sam9rl_systemck), nck(at91sam9rl_periphck), 0, 2); if (!at91sam9rl_pmc) return; hw = at91_clk_register_rm9200_main(regmap, "mainck", mainxtal_name, NULL); if (IS_ERR(hw)) goto err_free; at91sam9rl_pmc->chws[PMC_MAIN] = hw; hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, &at91rm9200_pll_layout, &sam9rl_plla_characteristics); if (IS_ERR(hw)) goto err_free; at91sam9rl_pmc->chws[PMC_PLLACK] = hw; hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); if (IS_ERR(hw)) goto err_free; at91sam9rl_pmc->chws[PMC_UTMI] = hw; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "pllack"; parent_names[3] = "utmick"; hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, parent_names, NULL, &at91rm9200_master_layout, &sam9rl_mck_characteristics, &sam9rl_mck_lock); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_master_div(regmap, "masterck_div", "masterck_pres", NULL, &at91rm9200_master_layout, &sam9rl_mck_characteristics, &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; at91sam9rl_pmc->chws[PMC_MCK] = hw; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "pllack"; parent_names[3] = "utmick"; parent_names[4] = "masterck_div"; for (i = 0; i < 2; i++) { char name[6]; snprintf(name, sizeof(name), "prog%d", i); hw = at91_clk_register_programmable(regmap, name, parent_names, NULL, 5, i, &at91rm9200_programmable_layout, NULL); if (IS_ERR(hw)) goto err_free; at91sam9rl_pmc->pchws[i] = hw; } for (i = 0; i < ARRAY_SIZE(at91sam9rl_systemck); i++) { hw = at91_clk_register_system(regmap, at91sam9rl_systemck[i].n, at91sam9rl_systemck[i].p, NULL, at91sam9rl_systemck[i].id, 0); if (IS_ERR(hw)) goto err_free; at91sam9rl_pmc->shws[at91sam9rl_systemck[i].id] = hw; } for (i = 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) { hw = at91_clk_register_peripheral(regmap, at91sam9rl_periphck[i].n, "masterck_div", NULL, at91sam9rl_periphck[i].id); if (IS_ERR(hw)) goto err_free; at91sam9rl_pmc->phws[at91sam9rl_periphck[i].id] = hw; } of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9rl_pmc); return; err_free: kfree(at91sam9rl_pmc); } CLK_OF_DECLARE(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup);
linux-master
drivers/clk/at91/at91sam9rl.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2016 Atmel Corporation, * Songjun Wu <[email protected]>, * Nicolas Ferre <[email protected]> * Copyright (C) 2017 Free Electrons, * Quentin Schulz <[email protected]> * * The Sama5d2 SoC has two audio PLLs (PMC and PAD) that shares the same parent * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of * its own parent. PMC and PAD can then divide the FRAC rate to best match the * asked rate. * * Traits of FRAC clock: * enable - clk_enable writes nd, fracr parameters and enables PLL * rate - rate is adjustable. * clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22)) * parent - fixed parent. No clk_set_parent support * * Traits of PMC clock: * enable - clk_enable writes qdpmc, and enables PMC output * rate - rate is adjustable. * clk->rate = parent->rate / (qdpmc + 1) * parent - fixed parent. No clk_set_parent support * * Traits of PAD clock: * enable - clk_enable writes divisors and enables PAD output * rate - rate is adjustable. * clk->rate = parent->rate / (qdaudio * div)) * parent - fixed parent. No clk_set_parent support */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include <linux/slab.h> #include "pmc.h" #define AUDIO_PLL_DIV_FRAC BIT(22) #define AUDIO_PLL_ND_MAX (AT91_PMC_AUDIO_PLL_ND_MASK >> \ AT91_PMC_AUDIO_PLL_ND_OFFSET) #define AUDIO_PLL_QDPAD(qd, div) ((AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(qd) & \ AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK) | \ (AT91_PMC_AUDIO_PLL_QDPAD_DIV(div) & \ AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK)) #define AUDIO_PLL_QDPMC_MAX (AT91_PMC_AUDIO_PLL_QDPMC_MASK >> \ AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) #define AUDIO_PLL_FOUT_MIN 620000000UL #define AUDIO_PLL_FOUT_MAX 700000000UL struct clk_audio_frac { struct clk_hw hw; struct regmap *regmap; u32 fracr; u8 nd; }; struct clk_audio_pad { struct clk_hw hw; struct regmap *regmap; u8 qdaudio; u8 div; }; struct clk_audio_pmc { struct clk_hw hw; struct regmap *regmap; u8 qdpmc; }; #define to_clk_audio_frac(hw) container_of(hw, struct clk_audio_frac, hw) #define to_clk_audio_pad(hw) container_of(hw, struct clk_audio_pad, hw) #define to_clk_audio_pmc(hw) container_of(hw, struct clk_audio_pmc, hw) static int clk_audio_pll_frac_enable(struct clk_hw *hw) { struct clk_audio_frac *frac = to_clk_audio_frac(hw); regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, AT91_PMC_AUDIO_PLL_RESETN, 0); regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, AT91_PMC_AUDIO_PLL_RESETN, AT91_PMC_AUDIO_PLL_RESETN); regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL1, AT91_PMC_AUDIO_PLL_FRACR_MASK, frac->fracr); /* * reset and enable have to be done in 2 separated writes * for AT91_PMC_AUDIO_PLL0 */ regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, AT91_PMC_AUDIO_PLL_PLLEN | AT91_PMC_AUDIO_PLL_ND_MASK, AT91_PMC_AUDIO_PLL_PLLEN | AT91_PMC_AUDIO_PLL_ND(frac->nd)); return 0; } static int clk_audio_pll_pad_enable(struct clk_hw *hw) { struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL1, AT91_PMC_AUDIO_PLL_QDPAD_MASK, AUDIO_PLL_QDPAD(apad_ck->qdaudio, apad_ck->div)); regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0, AT91_PMC_AUDIO_PLL_PADEN, AT91_PMC_AUDIO_PLL_PADEN); return 0; } static int clk_audio_pll_pmc_enable(struct clk_hw *hw) { struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0, AT91_PMC_AUDIO_PLL_PMCEN | AT91_PMC_AUDIO_PLL_QDPMC_MASK, AT91_PMC_AUDIO_PLL_PMCEN | AT91_PMC_AUDIO_PLL_QDPMC(apmc_ck->qdpmc)); return 0; } static void clk_audio_pll_frac_disable(struct clk_hw *hw) { struct clk_audio_frac *frac = to_clk_audio_frac(hw); regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, AT91_PMC_AUDIO_PLL_PLLEN, 0); /* do it in 2 separated writes */ regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, AT91_PMC_AUDIO_PLL_RESETN, 0); } static void clk_audio_pll_pad_disable(struct clk_hw *hw) { struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0, AT91_PMC_AUDIO_PLL_PADEN, 0); } static void clk_audio_pll_pmc_disable(struct clk_hw *hw) { struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0, AT91_PMC_AUDIO_PLL_PMCEN, 0); } static unsigned long clk_audio_pll_fout(unsigned long parent_rate, unsigned long nd, unsigned long fracr) { unsigned long long fr = (unsigned long long)parent_rate * fracr; pr_debug("A PLL: %s, fr = %llu\n", __func__, fr); fr = DIV_ROUND_CLOSEST_ULL(fr, AUDIO_PLL_DIV_FRAC); pr_debug("A PLL: %s, fr = %llu\n", __func__, fr); return parent_rate * (nd + 1) + fr; } static unsigned long clk_audio_pll_frac_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_audio_frac *frac = to_clk_audio_frac(hw); unsigned long fout; fout = clk_audio_pll_fout(parent_rate, frac->nd, frac->fracr); pr_debug("A PLL: %s, fout = %lu (nd = %u, fracr = %lu)\n", __func__, fout, frac->nd, (unsigned long)frac->fracr); return fout; } static unsigned long clk_audio_pll_pad_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); unsigned long apad_rate = 0; if (apad_ck->qdaudio && apad_ck->div) apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div); pr_debug("A PLL/PAD: %s, apad_rate = %lu (div = %u, qdaudio = %u)\n", __func__, apad_rate, apad_ck->div, apad_ck->qdaudio); return apad_rate; } static unsigned long clk_audio_pll_pmc_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); unsigned long apmc_rate = 0; apmc_rate = parent_rate / (apmc_ck->qdpmc + 1); pr_debug("A PLL/PMC: %s, apmc_rate = %lu (qdpmc = %u)\n", __func__, apmc_rate, apmc_ck->qdpmc); return apmc_rate; } static int clk_audio_pll_frac_compute_frac(unsigned long rate, unsigned long parent_rate, unsigned long *nd, unsigned long *fracr) { unsigned long long tmp, rem; if (!rate) return -EINVAL; tmp = rate; rem = do_div(tmp, parent_rate); if (!tmp || tmp >= AUDIO_PLL_ND_MAX) return -EINVAL; *nd = tmp - 1; tmp = rem * AUDIO_PLL_DIV_FRAC; tmp = DIV_ROUND_CLOSEST_ULL(tmp, parent_rate); if (tmp > AT91_PMC_AUDIO_PLL_FRACR_MASK) return -EINVAL; /* we can cast here as we verified the bounds just above */ *fracr = (unsigned long)tmp; return 0; } static int clk_audio_pll_frac_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { unsigned long fracr, nd; int ret; pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, req->rate, req->best_parent_rate); req->rate = clamp(req->rate, AUDIO_PLL_FOUT_MIN, AUDIO_PLL_FOUT_MAX); req->min_rate = max(req->min_rate, AUDIO_PLL_FOUT_MIN); req->max_rate = min(req->max_rate, AUDIO_PLL_FOUT_MAX); ret = clk_audio_pll_frac_compute_frac(req->rate, req->best_parent_rate, &nd, &fracr); if (ret) return ret; req->rate = clk_audio_pll_fout(req->best_parent_rate, nd, fracr); req->best_parent_hw = clk_hw_get_parent(hw); pr_debug("A PLL: %s, best_rate = %lu (nd = %lu, fracr = %lu)\n", __func__, req->rate, nd, fracr); return 0; } static long clk_audio_pll_pad_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { struct clk_hw *pclk = clk_hw_get_parent(hw); long best_rate = -EINVAL; unsigned long best_parent_rate; unsigned long tmp_qd; u32 div; long tmp_rate; int tmp_diff; int best_diff = -1; pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate, *parent_rate); /* * Rate divisor is actually made of two different divisors, multiplied * between themselves before dividing the rate. * tmp_qd goes from 1 to 31 and div is either 2 or 3. * In order to avoid testing twice the rate divisor (e.g. divisor 12 can * be found with (tmp_qd, div) = (2, 6) or (3, 4)), we remove any loop * for a rate divisor when div is 2 and tmp_qd is a multiple of 3. * We cannot inverse it (condition div is 3 and tmp_qd is even) or we * would miss some rate divisor that aren't reachable with div being 2 * (e.g. rate divisor 90 is made with div = 3 and tmp_qd = 30, thus * tmp_qd is even so we skip it because we think div 2 could make this * rate divisor which isn't possible since tmp_qd has to be <= 31). */ for (tmp_qd = 1; tmp_qd < AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX; tmp_qd++) for (div = 2; div <= 3; div++) { if (div == 2 && tmp_qd % 3 == 0) continue; best_parent_rate = clk_hw_round_rate(pclk, rate * tmp_qd * div); tmp_rate = best_parent_rate / (div * tmp_qd); tmp_diff = abs(rate - tmp_rate); if (best_diff < 0 || best_diff > tmp_diff) { *parent_rate = best_parent_rate; best_rate = tmp_rate; best_diff = tmp_diff; } } pr_debug("A PLL/PAD: %s, best_rate = %ld, best_parent_rate = %lu\n", __func__, best_rate, best_parent_rate); return best_rate; } static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { struct clk_hw *pclk = clk_hw_get_parent(hw); long best_rate = -EINVAL; unsigned long best_parent_rate = 0; u32 tmp_qd = 0, div; long tmp_rate; int tmp_diff; int best_diff = -1; pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate, *parent_rate); if (!rate) return 0; best_parent_rate = clk_round_rate(pclk->clk, 1); div = max(best_parent_rate / rate, 1UL); for (; div <= AUDIO_PLL_QDPMC_MAX; div++) { best_parent_rate = clk_round_rate(pclk->clk, rate * div); tmp_rate = best_parent_rate / div; tmp_diff = abs(rate - tmp_rate); if (best_diff < 0 || best_diff > tmp_diff) { *parent_rate = best_parent_rate; best_rate = tmp_rate; best_diff = tmp_diff; tmp_qd = div; if (!best_diff) break; /* got exact match */ } } pr_debug("A PLL/PMC: %s, best_rate = %ld, best_parent_rate = %lu (qd = %d)\n", __func__, best_rate, *parent_rate, tmp_qd - 1); return best_rate; } static int clk_audio_pll_frac_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_audio_frac *frac = to_clk_audio_frac(hw); unsigned long fracr, nd; int ret; pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate, parent_rate); if (rate < AUDIO_PLL_FOUT_MIN || rate > AUDIO_PLL_FOUT_MAX) return -EINVAL; ret = clk_audio_pll_frac_compute_frac(rate, parent_rate, &nd, &fracr); if (ret) return ret; frac->nd = nd; frac->fracr = fracr; return 0; } static int clk_audio_pll_pad_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); u8 tmp_div; pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate, parent_rate); if (!rate) return -EINVAL; tmp_div = parent_rate / rate; if (tmp_div % 3 == 0) { apad_ck->qdaudio = tmp_div / 3; apad_ck->div = 3; } else { apad_ck->qdaudio = tmp_div / 2; apad_ck->div = 2; } return 0; } static int clk_audio_pll_pmc_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); if (!rate) return -EINVAL; pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate, parent_rate); apmc_ck->qdpmc = parent_rate / rate - 1; return 0; } static const struct clk_ops audio_pll_frac_ops = { .enable = clk_audio_pll_frac_enable, .disable = clk_audio_pll_frac_disable, .recalc_rate = clk_audio_pll_frac_recalc_rate, .determine_rate = clk_audio_pll_frac_determine_rate, .set_rate = clk_audio_pll_frac_set_rate, }; static const struct clk_ops audio_pll_pad_ops = { .enable = clk_audio_pll_pad_enable, .disable = clk_audio_pll_pad_disable, .recalc_rate = clk_audio_pll_pad_recalc_rate, .round_rate = clk_audio_pll_pad_round_rate, .set_rate = clk_audio_pll_pad_set_rate, }; static const struct clk_ops audio_pll_pmc_ops = { .enable = clk_audio_pll_pmc_enable, .disable = clk_audio_pll_pmc_disable, .recalc_rate = clk_audio_pll_pmc_recalc_rate, .round_rate = clk_audio_pll_pmc_round_rate, .set_rate = clk_audio_pll_pmc_set_rate, }; struct clk_hw * __init at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name, const char *parent_name) { struct clk_audio_frac *frac_ck; struct clk_init_data init = {}; int ret; frac_ck = kzalloc(sizeof(*frac_ck), GFP_KERNEL); if (!frac_ck) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &audio_pll_frac_ops; init.parent_names = &parent_name; init.num_parents = 1; init.flags = CLK_SET_RATE_GATE; frac_ck->hw.init = &init; frac_ck->regmap = regmap; ret = clk_hw_register(NULL, &frac_ck->hw); if (ret) { kfree(frac_ck); return ERR_PTR(ret); } return &frac_ck->hw; } struct clk_hw * __init at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name, const char *parent_name) { struct clk_audio_pad *apad_ck; struct clk_init_data init; int ret; apad_ck = kzalloc(sizeof(*apad_ck), GFP_KERNEL); if (!apad_ck) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &audio_pll_pad_ops; init.parent_names = &parent_name; init.num_parents = 1; init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT; apad_ck->hw.init = &init; apad_ck->regmap = regmap; ret = clk_hw_register(NULL, &apad_ck->hw); if (ret) { kfree(apad_ck); return ERR_PTR(ret); } return &apad_ck->hw; } struct clk_hw * __init at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name, const char *parent_name) { struct clk_audio_pmc *apmc_ck; struct clk_init_data init; int ret; apmc_ck = kzalloc(sizeof(*apmc_ck), GFP_KERNEL); if (!apmc_ck) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &audio_pll_pmc_ops; init.parent_names = &parent_name; init.num_parents = 1; init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT; apmc_ck->hw.init = &init; apmc_ck->regmap = regmap; ret = clk_hw_register(NULL, &apmc_ck->hw); if (ret) { kfree(apmc_ck); return ERR_PTR(ret); } return &apmc_ck->hw; }
linux-master
drivers/clk/at91/clk-audio-pll.c
// SPDX-License-Identifier: GPL-2.0 #include <linux/clk-provider.h> #include <linux/mfd/syscon.h> #include <linux/slab.h> #include <dt-bindings/clock/at91.h> #include "pmc.h" static DEFINE_SPINLOCK(mck_lock); static const struct clk_master_characteristics mck_characteristics = { .output = { .min = 0, .max = 166000000 }, .divisors = { 1, 2, 4, 3 }, }; static u8 plla_out[] = { 0 }; static u16 plla_icpll[] = { 0 }; static const struct clk_range plla_outputs[] = { { .min = 400000000, .max = 1000000000 }, }; static const struct clk_pll_characteristics plla_characteristics = { .input = { .min = 8000000, .max = 50000000 }, .num_output = ARRAY_SIZE(plla_outputs), .output = plla_outputs, .icpll = plla_icpll, .out = plla_out, }; static const struct clk_pcr_layout sama5d3_pcr_layout = { .offset = 0x10c, .cmd = BIT(12), .pid_mask = GENMASK(6, 0), .div_mask = GENMASK(17, 16), }; static const struct { char *n; char *p; unsigned long flags; u8 id; } sama5d3_systemck[] = { /* * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, { .n = "lcdck", .p = "masterck_div", .id = 3 }, { .n = "smdck", .p = "smdclk", .id = 4 }, { .n = "uhpck", .p = "usbck", .id = 6 }, { .n = "udpck", .p = "usbck", .id = 7 }, { .n = "pck0", .p = "prog0", .id = 8 }, { .n = "pck1", .p = "prog1", .id = 9 }, { .n = "pck2", .p = "prog2", .id = 10 }, }; static const struct { char *n; u8 id; struct clk_range r; unsigned long flags; } sama5d3_periphck[] = { { .n = "dbgu_clk", .id = 2, }, { .n = "hsmc_clk", .id = 5, }, { .n = "pioA_clk", .id = 6, }, { .n = "pioB_clk", .id = 7, }, { .n = "pioC_clk", .id = 8, }, { .n = "pioD_clk", .id = 9, }, { .n = "pioE_clk", .id = 10, }, { .n = "usart0_clk", .id = 12, .r = { .min = 0, .max = 83000000 }, }, { .n = "usart1_clk", .id = 13, .r = { .min = 0, .max = 83000000 }, }, { .n = "usart2_clk", .id = 14, .r = { .min = 0, .max = 83000000 }, }, { .n = "usart3_clk", .id = 15, .r = { .min = 0, .max = 83000000 }, }, { .n = "uart0_clk", .id = 16, .r = { .min = 0, .max = 83000000 }, }, { .n = "uart1_clk", .id = 17, .r = { .min = 0, .max = 83000000 }, }, { .n = "twi0_clk", .id = 18, .r = { .min = 0, .max = 41500000 }, }, { .n = "twi1_clk", .id = 19, .r = { .min = 0, .max = 41500000 }, }, { .n = "twi2_clk", .id = 20, .r = { .min = 0, .max = 41500000 }, }, { .n = "mci0_clk", .id = 21, }, { .n = "mci1_clk", .id = 22, }, { .n = "mci2_clk", .id = 23, }, { .n = "spi0_clk", .id = 24, .r = { .min = 0, .max = 166000000 }, }, { .n = "spi1_clk", .id = 25, .r = { .min = 0, .max = 166000000 }, }, { .n = "tcb0_clk", .id = 26, .r = { .min = 0, .max = 166000000 }, }, { .n = "tcb1_clk", .id = 27, .r = { .min = 0, .max = 166000000 }, }, { .n = "pwm_clk", .id = 28, }, { .n = "adc_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, }, { .n = "dma0_clk", .id = 30, }, { .n = "dma1_clk", .id = 31, }, { .n = "uhphs_clk", .id = 32, }, { .n = "udphs_clk", .id = 33, }, { .n = "macb0_clk", .id = 34, }, { .n = "macb1_clk", .id = 35, }, { .n = "lcdc_clk", .id = 36, }, { .n = "isi_clk", .id = 37, }, { .n = "ssc0_clk", .id = 38, .r = { .min = 0, .max = 83000000 }, }, { .n = "ssc1_clk", .id = 39, .r = { .min = 0, .max = 83000000 }, }, { .n = "can0_clk", .id = 40, .r = { .min = 0, .max = 83000000 }, }, { .n = "can1_clk", .id = 41, .r = { .min = 0, .max = 83000000 }, }, { .n = "sha_clk", .id = 42, }, { .n = "aes_clk", .id = 43, }, { .n = "tdes_clk", .id = 44, }, { .n = "trng_clk", .id = 45, }, { .n = "fuse_clk", .id = 48, }, /* * mpddr_clk feeds DDR controller and is enabled by bootloader thus we * need to keep it enabled in case there is no Linux consumer for it. */ { .n = "mpddr_clk", .id = 49, .flags = CLK_IS_CRITICAL }, }; static void __init sama5d3_pmc_setup(struct device_node *np) { const char *slck_name, *mainxtal_name; struct pmc_data *sama5d3_pmc; const char *parent_names[5]; struct regmap *regmap; struct clk_hw *hw; int i; bool bypass; i = of_property_match_string(np, "clock-names", "slow_clk"); if (i < 0) return; slck_name = of_clk_get_parent_name(np, i); i = of_property_match_string(np, "clock-names", "main_xtal"); if (i < 0) return; mainxtal_name = of_clk_get_parent_name(np, i); regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; sama5d3_pmc = pmc_data_allocate(PMC_PLLACK + 1, nck(sama5d3_systemck), nck(sama5d3_periphck), 0, 3); if (!sama5d3_pmc) return; hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 50000000); if (IS_ERR(hw)) goto err_free; bypass = of_property_read_bool(np, "atmel,osc-bypass"); hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, bypass); if (IS_ERR(hw)) goto err_free; parent_names[0] = "main_rc_osc"; parent_names[1] = "main_osc"; hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, &sama5d3_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); if (IS_ERR(hw)) goto err_free; sama5d3_pmc->chws[PMC_PLLACK] = hw; hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); if (IS_ERR(hw)) goto err_free; sama5d3_pmc->chws[PMC_UTMI] = hw; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, parent_names, NULL, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_master_div(regmap, "masterck_div", "masterck_pres", NULL, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; sama5d3_pmc->chws[PMC_MCK] = hw; parent_names[0] = "plladivck"; parent_names[1] = "utmick"; hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); if (IS_ERR(hw)) goto err_free; hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2); if (IS_ERR(hw)) goto err_free; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; parent_names[4] = "masterck_div"; for (i = 0; i < 3; i++) { char name[6]; snprintf(name, sizeof(name), "prog%d", i); hw = at91_clk_register_programmable(regmap, name, parent_names, NULL, 5, i, &at91sam9x5_programmable_layout, NULL); if (IS_ERR(hw)) goto err_free; sama5d3_pmc->pchws[i] = hw; } for (i = 0; i < ARRAY_SIZE(sama5d3_systemck); i++) { hw = at91_clk_register_system(regmap, sama5d3_systemck[i].n, sama5d3_systemck[i].p, NULL, sama5d3_systemck[i].id, sama5d3_systemck[i].flags); if (IS_ERR(hw)) goto err_free; sama5d3_pmc->shws[sama5d3_systemck[i].id] = hw; } for (i = 0; i < ARRAY_SIZE(sama5d3_periphck); i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d3_pcr_layout, sama5d3_periphck[i].n, "masterck_div", NULL, sama5d3_periphck[i].id, &sama5d3_periphck[i].r, INT_MIN, sama5d3_periphck[i].flags); if (IS_ERR(hw)) goto err_free; sama5d3_pmc->phws[sama5d3_periphck[i].id] = hw; } of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d3_pmc); return; err_free: kfree(sama5d3_pmc); } /* * The TCB is used as the clocksource so its clock is needed early. This means * this can't be a platform driver. */ CLK_OF_DECLARE(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup);
linux-master
drivers/clk/at91/sama5d3.c
// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019 Microchip Technology Inc. * */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "pmc.h" #define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0) #define PMC_PLL_CTRL1_MUL_MSK GENMASK(31, 24) #define PMC_PLL_CTRL1_FRACR_MSK GENMASK(21, 0) #define PLL_DIV_MAX (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1) #define UPLL_DIV 2 #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1) #define FCORE_MIN (600000000) #define FCORE_MAX (1200000000) #define PLL_MAX_ID 7 struct sam9x60_pll_core { struct regmap *regmap; spinlock_t *lock; const struct clk_pll_characteristics *characteristics; const struct clk_pll_layout *layout; struct clk_hw hw; u8 id; }; struct sam9x60_frac { struct sam9x60_pll_core core; struct at91_clk_pms pms; u32 frac; u16 mul; }; struct sam9x60_div { struct sam9x60_pll_core core; struct at91_clk_pms pms; u8 div; u8 safe_div; }; #define to_sam9x60_pll_core(hw) container_of(hw, struct sam9x60_pll_core, hw) #define to_sam9x60_frac(core) container_of(core, struct sam9x60_frac, core) #define to_sam9x60_div(core) container_of(core, struct sam9x60_div, core) static struct sam9x60_div *notifier_div; static inline bool sam9x60_pll_ready(struct regmap *regmap, int id) { unsigned int status; regmap_read(regmap, AT91_PMC_PLL_ISR0, &status); return !!(status & BIT(id)); } static bool sam9x60_frac_pll_ready(struct regmap *regmap, u8 id) { return sam9x60_pll_ready(regmap, id); } static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_frac *frac = to_sam9x60_frac(core); return parent_rate * (frac->mul + 1) + DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22)); } static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) { struct sam9x60_frac *frac = to_sam9x60_frac(core); struct regmap *regmap = core->regmap; unsigned int val, cfrac, cmul; unsigned long flags; spin_lock_irqsave(core->lock, flags); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, core->id); regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val); cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift; cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift; if (sam9x60_frac_pll_ready(regmap, core->id) && (cmul == frac->mul && cfrac == frac->frac)) goto unlock; /* Recommended value for PMC_PLL_ACR */ if (core->characteristics->upll) val = AT91_PMC_PLL_ACR_DEFAULT_UPLL; else val = AT91_PMC_PLL_ACR_DEFAULT_PLLA; regmap_write(regmap, AT91_PMC_PLL_ACR, val); regmap_write(regmap, AT91_PMC_PLL_CTRL1, (frac->mul << core->layout->mul_shift) | (frac->frac << core->layout->frac_shift)); if (core->characteristics->upll) { /* Enable the UTMI internal bandgap */ val |= AT91_PMC_PLL_ACR_UTMIBG; regmap_write(regmap, AT91_PMC_PLL_ACR, val); udelay(10); /* Enable the UTMI internal regulator */ val |= AT91_PMC_PLL_ACR_UTMIVR; regmap_write(regmap, AT91_PMC_PLL_ACR, val); udelay(10); } regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, AT91_PMC_PLL_UPDT_UPDATE | core->id); regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL, AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, AT91_PMC_PLL_UPDT_UPDATE | core->id); while (!sam9x60_pll_ready(regmap, core->id)) cpu_relax(); unlock: spin_unlock_irqrestore(core->lock, flags); return 0; } static int sam9x60_frac_pll_prepare(struct clk_hw *hw) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); return sam9x60_frac_pll_set(core); } static void sam9x60_frac_pll_unprepare(struct clk_hw *hw) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct regmap *regmap = core->regmap; unsigned long flags; spin_lock_irqsave(core->lock, flags); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, core->id); regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, AT91_PMC_PLL_CTRL0_ENPLL, 0); if (core->characteristics->upll) regmap_update_bits(regmap, AT91_PMC_PLL_ACR, AT91_PMC_PLL_ACR_UTMIBG | AT91_PMC_PLL_ACR_UTMIVR, 0); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, AT91_PMC_PLL_UPDT_UPDATE | core->id); spin_unlock_irqrestore(core->lock, flags); } static int sam9x60_frac_pll_is_prepared(struct clk_hw *hw) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); return sam9x60_pll_ready(core->regmap, core->id); } static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core, unsigned long rate, unsigned long parent_rate, bool update) { struct sam9x60_frac *frac = to_sam9x60_frac(core); unsigned long tmprate, remainder; unsigned long nmul = 0; unsigned long nfrac = 0; if (rate < FCORE_MIN || rate > FCORE_MAX) return -ERANGE; /* * Calculate the multiplier associated with the current * divider that provide the closest rate to the requested one. */ nmul = mult_frac(rate, 1, parent_rate); tmprate = mult_frac(parent_rate, nmul, 1); remainder = rate - tmprate; if (remainder) { nfrac = DIV_ROUND_CLOSEST_ULL((u64)remainder * (1 << 22), parent_rate); tmprate += DIV_ROUND_CLOSEST_ULL((u64)nfrac * parent_rate, (1 << 22)); } /* Check if resulted rate is a valid. */ if (tmprate < FCORE_MIN || tmprate > FCORE_MAX) return -ERANGE; if (update) { frac->mul = nmul - 1; frac->frac = nfrac; } return tmprate; } static long sam9x60_frac_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); return sam9x60_frac_pll_compute_mul_frac(core, rate, *parent_rate, false); } static int sam9x60_frac_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true); } static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_frac *frac = to_sam9x60_frac(core); struct regmap *regmap = core->regmap; unsigned long irqflags; unsigned int val, cfrac, cmul; long ret; ret = sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true); if (ret <= 0) return ret; spin_lock_irqsave(core->lock, irqflags); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, core->id); regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val); cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift; cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift; if (cmul == frac->mul && cfrac == frac->frac) goto unlock; regmap_write(regmap, AT91_PMC_PLL_CTRL1, (frac->mul << core->layout->mul_shift) | (frac->frac << core->layout->frac_shift)); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, AT91_PMC_PLL_UPDT_UPDATE | core->id); regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL, AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, AT91_PMC_PLL_UPDT_UPDATE | core->id); while (!sam9x60_pll_ready(regmap, core->id)) cpu_relax(); unlock: spin_unlock_irqrestore(core->lock, irqflags); return ret; } static int sam9x60_frac_pll_save_context(struct clk_hw *hw) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_frac *frac = to_sam9x60_frac(core); frac->pms.status = sam9x60_pll_ready(core->regmap, core->id); return 0; } static void sam9x60_frac_pll_restore_context(struct clk_hw *hw) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_frac *frac = to_sam9x60_frac(core); if (frac->pms.status) sam9x60_frac_pll_set(core); } static const struct clk_ops sam9x60_frac_pll_ops = { .prepare = sam9x60_frac_pll_prepare, .unprepare = sam9x60_frac_pll_unprepare, .is_prepared = sam9x60_frac_pll_is_prepared, .recalc_rate = sam9x60_frac_pll_recalc_rate, .round_rate = sam9x60_frac_pll_round_rate, .set_rate = sam9x60_frac_pll_set_rate, .save_context = sam9x60_frac_pll_save_context, .restore_context = sam9x60_frac_pll_restore_context, }; static const struct clk_ops sam9x60_frac_pll_ops_chg = { .prepare = sam9x60_frac_pll_prepare, .unprepare = sam9x60_frac_pll_unprepare, .is_prepared = sam9x60_frac_pll_is_prepared, .recalc_rate = sam9x60_frac_pll_recalc_rate, .round_rate = sam9x60_frac_pll_round_rate, .set_rate = sam9x60_frac_pll_set_rate_chg, .save_context = sam9x60_frac_pll_save_context, .restore_context = sam9x60_frac_pll_restore_context, }; /* This function should be called with spinlock acquired. */ static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div, bool enable) { struct regmap *regmap = core->regmap; u32 ena_msk = enable ? core->layout->endiv_mask : 0; u32 ena_val = enable ? (1 << core->layout->endiv_shift) : 0; regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, core->layout->div_mask | ena_msk, (div << core->layout->div_shift) | ena_val); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, AT91_PMC_PLL_UPDT_UPDATE | core->id); while (!sam9x60_pll_ready(regmap, core->id)) cpu_relax(); } static int sam9x60_div_pll_set(struct sam9x60_pll_core *core) { struct sam9x60_div *div = to_sam9x60_div(core); struct regmap *regmap = core->regmap; unsigned long flags; unsigned int val, cdiv; spin_lock_irqsave(core->lock, flags); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, core->id); regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; /* Stop if enabled an nothing changed. */ if (!!(val & core->layout->endiv_mask) && cdiv == div->div) goto unlock; sam9x60_div_pll_set_div(core, div->div, 1); unlock: spin_unlock_irqrestore(core->lock, flags); return 0; } static int sam9x60_div_pll_prepare(struct clk_hw *hw) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); return sam9x60_div_pll_set(core); } static void sam9x60_div_pll_unprepare(struct clk_hw *hw) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct regmap *regmap = core->regmap; unsigned long flags; spin_lock_irqsave(core->lock, flags); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, core->id); regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, core->layout->endiv_mask, 0); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, AT91_PMC_PLL_UPDT_UPDATE | core->id); spin_unlock_irqrestore(core->lock, flags); } static int sam9x60_div_pll_is_prepared(struct clk_hw *hw) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct regmap *regmap = core->regmap; unsigned long flags; unsigned int val; spin_lock_irqsave(core->lock, flags); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, core->id); regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); spin_unlock_irqrestore(core->lock, flags); return !!(val & core->layout->endiv_mask); } static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_div *div = to_sam9x60_div(core); return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1)); } static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core, unsigned long *parent_rate, unsigned long rate) { const struct clk_pll_characteristics *characteristics = core->characteristics; struct clk_hw *parent = clk_hw_get_parent(&core->hw); unsigned long tmp_rate, tmp_parent_rate, tmp_diff; long best_diff = -1, best_rate = -EINVAL; u32 divid; if (!rate) return 0; if (rate < characteristics->output[0].min || rate > characteristics->output[0].max) return -ERANGE; for (divid = 1; divid < core->layout->div_mask; divid++) { tmp_parent_rate = clk_hw_round_rate(parent, rate * divid); if (!tmp_parent_rate) continue; tmp_rate = DIV_ROUND_CLOSEST_ULL(tmp_parent_rate, divid); tmp_diff = abs(rate - tmp_rate); if (best_diff < 0 || best_diff > tmp_diff) { *parent_rate = tmp_parent_rate; best_rate = tmp_rate; best_diff = tmp_diff; } if (!best_diff) break; } if (best_rate < characteristics->output[0].min || best_rate > characteristics->output[0].max) return -ERANGE; return best_rate; } static long sam9x60_div_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); return sam9x60_div_pll_compute_div(core, parent_rate, rate); } static int sam9x60_div_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_div *div = to_sam9x60_div(core); div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; return 0; } static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_div *div = to_sam9x60_div(core); struct regmap *regmap = core->regmap; unsigned long irqflags; unsigned int val, cdiv; div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; spin_lock_irqsave(core->lock, irqflags); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, core->id); regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; /* Stop if nothing changed. */ if (cdiv == div->div) goto unlock; sam9x60_div_pll_set_div(core, div->div, 0); unlock: spin_unlock_irqrestore(core->lock, irqflags); return 0; } static int sam9x60_div_pll_save_context(struct clk_hw *hw) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_div *div = to_sam9x60_div(core); div->pms.status = sam9x60_div_pll_is_prepared(hw); return 0; } static void sam9x60_div_pll_restore_context(struct clk_hw *hw) { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_div *div = to_sam9x60_div(core); if (div->pms.status) sam9x60_div_pll_set(core); } static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier, unsigned long code, void *data) { struct sam9x60_div *div = notifier_div; struct sam9x60_pll_core core = div->core; struct regmap *regmap = core.regmap; unsigned long irqflags; u32 val, cdiv; int ret = NOTIFY_DONE; if (code != PRE_RATE_CHANGE) return ret; /* * We switch to safe divider to avoid overclocking of other domains * feed by us while the frac PLL (our parent) is changed. */ div->div = div->safe_div; spin_lock_irqsave(core.lock, irqflags); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, core.id); regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); cdiv = (val & core.layout->div_mask) >> core.layout->div_shift; /* Stop if nothing changed. */ if (cdiv == div->safe_div) goto unlock; sam9x60_div_pll_set_div(&core, div->div, 0); ret = NOTIFY_OK; unlock: spin_unlock_irqrestore(core.lock, irqflags); return ret; } static struct notifier_block sam9x60_div_pll_notifier = { .notifier_call = sam9x60_div_pll_notifier_fn, }; static const struct clk_ops sam9x60_div_pll_ops = { .prepare = sam9x60_div_pll_prepare, .unprepare = sam9x60_div_pll_unprepare, .is_prepared = sam9x60_div_pll_is_prepared, .recalc_rate = sam9x60_div_pll_recalc_rate, .round_rate = sam9x60_div_pll_round_rate, .set_rate = sam9x60_div_pll_set_rate, .save_context = sam9x60_div_pll_save_context, .restore_context = sam9x60_div_pll_restore_context, }; static const struct clk_ops sam9x60_div_pll_ops_chg = { .prepare = sam9x60_div_pll_prepare, .unprepare = sam9x60_div_pll_unprepare, .is_prepared = sam9x60_div_pll_is_prepared, .recalc_rate = sam9x60_div_pll_recalc_rate, .round_rate = sam9x60_div_pll_round_rate, .set_rate = sam9x60_div_pll_set_rate_chg, .save_context = sam9x60_div_pll_save_context, .restore_context = sam9x60_div_pll_restore_context, }; struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, struct clk_hw *parent_hw, u8 id, const struct clk_pll_characteristics *characteristics, const struct clk_pll_layout *layout, u32 flags) { struct sam9x60_frac *frac; struct clk_hw *hw; struct clk_init_data init = {}; unsigned long parent_rate, irqflags; unsigned int val; int ret; if (id > PLL_MAX_ID || !lock || !parent_hw) return ERR_PTR(-EINVAL); frac = kzalloc(sizeof(*frac), GFP_KERNEL); if (!frac) return ERR_PTR(-ENOMEM); init.name = name; if (parent_name) init.parent_names = &parent_name; else init.parent_hws = (const struct clk_hw **)&parent_hw; init.num_parents = 1; if (flags & CLK_SET_RATE_GATE) init.ops = &sam9x60_frac_pll_ops; else init.ops = &sam9x60_frac_pll_ops_chg; init.flags = flags; frac->core.id = id; frac->core.hw.init = &init; frac->core.characteristics = characteristics; frac->core.layout = layout; frac->core.regmap = regmap; frac->core.lock = lock; spin_lock_irqsave(frac->core.lock, irqflags); if (sam9x60_pll_ready(regmap, id)) { regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, id); regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val); frac->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val); frac->frac = FIELD_GET(PMC_PLL_CTRL1_FRACR_MSK, val); } else { /* * This means the PLL is not setup by bootloaders. In this * case we need to set the minimum rate for it. Otherwise * a clock child of this PLL may be enabled before setting * its rate leading to enabling this PLL with unsupported * rate. This will lead to PLL not being locked at all. */ parent_rate = clk_hw_get_rate(parent_hw); if (!parent_rate) { hw = ERR_PTR(-EINVAL); goto free; } ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN, parent_rate, true); if (ret < 0) { hw = ERR_PTR(ret); goto free; } } spin_unlock_irqrestore(frac->core.lock, irqflags); hw = &frac->core.hw; ret = clk_hw_register(NULL, hw); if (ret) { kfree(frac); hw = ERR_PTR(ret); } return hw; free: spin_unlock_irqrestore(frac->core.lock, irqflags); kfree(frac); return hw; } struct clk_hw * __init sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, struct clk_hw *parent_hw, u8 id, const struct clk_pll_characteristics *characteristics, const struct clk_pll_layout *layout, u32 flags, u32 safe_div) { struct sam9x60_div *div; struct clk_hw *hw; struct clk_init_data init = {}; unsigned long irqflags; unsigned int val; int ret; /* We only support one changeable PLL. */ if (id > PLL_MAX_ID || !lock || (safe_div && notifier_div)) return ERR_PTR(-EINVAL); if (safe_div >= PLL_DIV_MAX) safe_div = PLL_DIV_MAX - 1; div = kzalloc(sizeof(*div), GFP_KERNEL); if (!div) return ERR_PTR(-ENOMEM); init.name = name; if (parent_hw) init.parent_hws = (const struct clk_hw **)&parent_hw; else init.parent_names = &parent_name; init.num_parents = 1; if (flags & CLK_SET_RATE_GATE) init.ops = &sam9x60_div_pll_ops; else init.ops = &sam9x60_div_pll_ops_chg; init.flags = flags; div->core.id = id; div->core.hw.init = &init; div->core.characteristics = characteristics; div->core.layout = layout; div->core.regmap = regmap; div->core.lock = lock; div->safe_div = safe_div; spin_lock_irqsave(div->core.lock, irqflags); regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, id); regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); div->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val); spin_unlock_irqrestore(div->core.lock, irqflags); hw = &div->core.hw; ret = clk_hw_register(NULL, hw); if (ret) { kfree(div); hw = ERR_PTR(ret); } else if (div->safe_div) { notifier_div = div; clk_notifier_register(hw->clk, &sam9x60_div_pll_notifier); } return hw; }
linux-master
drivers/clk/at91/clk-sam9x60-pll.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * drivers/clk/at91/clk-slow.c * * Copyright (C) 2013 Boris BREZILLON <[email protected]> */ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "pmc.h" struct clk_sam9260_slow { struct clk_hw hw; struct regmap *regmap; }; #define to_clk_sam9260_slow(hw) container_of(hw, struct clk_sam9260_slow, hw) static u8 clk_sam9260_slow_get_parent(struct clk_hw *hw) { struct clk_sam9260_slow *slowck = to_clk_sam9260_slow(hw); unsigned int status; regmap_read(slowck->regmap, AT91_PMC_SR, &status); return status & AT91_PMC_OSCSEL ? 1 : 0; } static const struct clk_ops sam9260_slow_ops = { .get_parent = clk_sam9260_slow_get_parent, }; struct clk_hw * __init at91_clk_register_sam9260_slow(struct regmap *regmap, const char *name, const char **parent_names, int num_parents) { struct clk_sam9260_slow *slowck; struct clk_hw *hw; struct clk_init_data init; int ret; if (!name) return ERR_PTR(-EINVAL); if (!parent_names || !num_parents) return ERR_PTR(-EINVAL); slowck = kzalloc(sizeof(*slowck), GFP_KERNEL); if (!slowck) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &sam9260_slow_ops; init.parent_names = parent_names; init.num_parents = num_parents; init.flags = 0; slowck->hw.init = &init; slowck->regmap = regmap; hw = &slowck->hw; ret = clk_hw_register(NULL, &slowck->hw); if (ret) { kfree(slowck); hw = ERR_PTR(ret); } return hw; }
linux-master
drivers/clk/at91/clk-slow.c
// SPDX-License-Identifier: GPL-2.0 /* * SAMA7G5 PMC code. * * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries * * Author: Claudiu Beznea <[email protected]> * */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/mfd/syscon.h> #include <linux/slab.h> #include <dt-bindings/clock/at91.h> #include "pmc.h" #define SAMA7G5_INIT_TABLE(_table, _count) \ do { \ u8 _i; \ for (_i = 0; _i < (_count); _i++) \ (_table)[_i] = _i; \ } while (0) #define SAMA7G5_FILL_TABLE(_to, _from, _count) \ do { \ u8 _i; \ for (_i = 0; _i < (_count); _i++) { \ (_to)[_i] = (_from)[_i]; \ } \ } while (0) static DEFINE_SPINLOCK(pmc_pll_lock); static DEFINE_SPINLOCK(pmc_mck0_lock); static DEFINE_SPINLOCK(pmc_mckX_lock); /* * PLL clocks identifiers * @PLL_ID_CPU: CPU PLL identifier * @PLL_ID_SYS: System PLL identifier * @PLL_ID_DDR: DDR PLL identifier * @PLL_ID_IMG: Image subsystem PLL identifier * @PLL_ID_BAUD: Baud PLL identifier * @PLL_ID_AUDIO: Audio PLL identifier * @PLL_ID_ETH: Ethernet PLL identifier */ enum pll_ids { PLL_ID_CPU, PLL_ID_SYS, PLL_ID_DDR, PLL_ID_IMG, PLL_ID_BAUD, PLL_ID_AUDIO, PLL_ID_ETH, PLL_ID_MAX, }; /* * PLL component identifier * @PLL_COMPID_FRAC: Fractional PLL component identifier * @PLL_COMPID_DIV0: 1st PLL divider component identifier * @PLL_COMPID_DIV1: 2nd PLL divider component identifier */ enum pll_component_id { PLL_COMPID_FRAC, PLL_COMPID_DIV0, PLL_COMPID_DIV1, }; /* * PLL type identifiers * @PLL_TYPE_FRAC: fractional PLL identifier * @PLL_TYPE_DIV: divider PLL identifier */ enum pll_type { PLL_TYPE_FRAC, PLL_TYPE_DIV, }; /* Layout for fractional PLLs. */ static const struct clk_pll_layout pll_layout_frac = { .mul_mask = GENMASK(31, 24), .frac_mask = GENMASK(21, 0), .mul_shift = 24, .frac_shift = 0, }; /* Layout for DIVPMC dividers. */ static const struct clk_pll_layout pll_layout_divpmc = { .div_mask = GENMASK(7, 0), .endiv_mask = BIT(29), .div_shift = 0, .endiv_shift = 29, }; /* Layout for DIVIO dividers. */ static const struct clk_pll_layout pll_layout_divio = { .div_mask = GENMASK(19, 12), .endiv_mask = BIT(30), .div_shift = 12, .endiv_shift = 30, }; /* * CPU PLL output range. * Notice: The upper limit has been setup to 1000000002 due to hardware * block which cannot output exactly 1GHz. */ static const struct clk_range cpu_pll_outputs[] = { { .min = 2343750, .max = 1000000002 }, }; /* PLL output range. */ static const struct clk_range pll_outputs[] = { { .min = 2343750, .max = 1200000000 }, }; /* CPU PLL characteristics. */ static const struct clk_pll_characteristics cpu_pll_characteristics = { .input = { .min = 12000000, .max = 50000000 }, .num_output = ARRAY_SIZE(cpu_pll_outputs), .output = cpu_pll_outputs, }; /* PLL characteristics. */ static const struct clk_pll_characteristics pll_characteristics = { .input = { .min = 12000000, .max = 50000000 }, .num_output = ARRAY_SIZE(pll_outputs), .output = pll_outputs, }; /* * SAMA7G5 PLL possible parents * @SAMA7G5_PLL_PARENT_MAINCK: MAINCK is PLL a parent * @SAMA7G5_PLL_PARENT_MAIN_XTAL: MAIN XTAL is a PLL parent * @SAMA7G5_PLL_PARENT_FRACCK: Frac PLL is a PLL parent (for PLL dividers) */ enum sama7g5_pll_parent { SAMA7G5_PLL_PARENT_MAINCK, SAMA7G5_PLL_PARENT_MAIN_XTAL, SAMA7G5_PLL_PARENT_FRACCK, }; /* * PLL clocks description * @n: clock name * @l: clock layout * @c: clock characteristics * @hw: pointer to clk_hw * @t: clock type * @f: clock flags * @p: clock parent * @eid: export index in sama7g5->chws[] array * @safe_div: intermediate divider need to be set on PRE_RATE_CHANGE * notification */ static struct sama7g5_pll { const char *n; const struct clk_pll_layout *l; const struct clk_pll_characteristics *c; struct clk_hw *hw; unsigned long f; enum sama7g5_pll_parent p; u8 t; u8 eid; u8 safe_div; } sama7g5_plls[][PLL_ID_MAX] = { [PLL_ID_CPU] = { [PLL_COMPID_FRAC] = { .n = "cpupll_fracck", .p = SAMA7G5_PLL_PARENT_MAINCK, .l = &pll_layout_frac, .c = &cpu_pll_characteristics, .t = PLL_TYPE_FRAC, /* * This feeds cpupll_divpmcck which feeds CPU. It should * not be disabled. */ .f = CLK_IS_CRITICAL, }, [PLL_COMPID_DIV0] = { .n = "cpupll_divpmcck", .p = SAMA7G5_PLL_PARENT_FRACCK, .l = &pll_layout_divpmc, .c = &cpu_pll_characteristics, .t = PLL_TYPE_DIV, /* This feeds CPU. It should not be disabled. */ .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, .eid = PMC_CPUPLL, /* * Safe div=15 should be safe even for switching b/w 1GHz and * 90MHz (frac pll might go up to 1.2GHz). */ .safe_div = 15, }, }, [PLL_ID_SYS] = { [PLL_COMPID_FRAC] = { .n = "syspll_fracck", .p = SAMA7G5_PLL_PARENT_MAINCK, .l = &pll_layout_frac, .c = &pll_characteristics, .t = PLL_TYPE_FRAC, /* * This feeds syspll_divpmcck which may feed critical parts * of the systems like timers. Therefore it should not be * disabled. */ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, [PLL_COMPID_DIV0] = { .n = "syspll_divpmcck", .p = SAMA7G5_PLL_PARENT_FRACCK, .l = &pll_layout_divpmc, .c = &pll_characteristics, .t = PLL_TYPE_DIV, /* * This may feed critical parts of the systems like timers. * Therefore it should not be disabled. */ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, .eid = PMC_SYSPLL, }, }, [PLL_ID_DDR] = { [PLL_COMPID_FRAC] = { .n = "ddrpll_fracck", .p = SAMA7G5_PLL_PARENT_MAINCK, .l = &pll_layout_frac, .c = &pll_characteristics, .t = PLL_TYPE_FRAC, /* * This feeds ddrpll_divpmcck which feeds DDR. It should not * be disabled. */ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, [PLL_COMPID_DIV0] = { .n = "ddrpll_divpmcck", .p = SAMA7G5_PLL_PARENT_FRACCK, .l = &pll_layout_divpmc, .c = &pll_characteristics, .t = PLL_TYPE_DIV, /* This feeds DDR. It should not be disabled. */ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, }, [PLL_ID_IMG] = { [PLL_COMPID_FRAC] = { .n = "imgpll_fracck", .p = SAMA7G5_PLL_PARENT_MAINCK, .l = &pll_layout_frac, .c = &pll_characteristics, .t = PLL_TYPE_FRAC, .f = CLK_SET_RATE_GATE, }, [PLL_COMPID_DIV0] = { .n = "imgpll_divpmcck", .p = SAMA7G5_PLL_PARENT_FRACCK, .l = &pll_layout_divpmc, .c = &pll_characteristics, .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, }, }, [PLL_ID_BAUD] = { [PLL_COMPID_FRAC] = { .n = "baudpll_fracck", .p = SAMA7G5_PLL_PARENT_MAINCK, .l = &pll_layout_frac, .c = &pll_characteristics, .t = PLL_TYPE_FRAC, .f = CLK_SET_RATE_GATE, }, [PLL_COMPID_DIV0] = { .n = "baudpll_divpmcck", .p = SAMA7G5_PLL_PARENT_FRACCK, .l = &pll_layout_divpmc, .c = &pll_characteristics, .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, }, }, [PLL_ID_AUDIO] = { [PLL_COMPID_FRAC] = { .n = "audiopll_fracck", .p = SAMA7G5_PLL_PARENT_MAIN_XTAL, .l = &pll_layout_frac, .c = &pll_characteristics, .t = PLL_TYPE_FRAC, .f = CLK_SET_RATE_GATE, }, [PLL_COMPID_DIV0] = { .n = "audiopll_divpmcck", .p = SAMA7G5_PLL_PARENT_FRACCK, .l = &pll_layout_divpmc, .c = &pll_characteristics, .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, .eid = PMC_AUDIOPMCPLL, }, [PLL_COMPID_DIV1] = { .n = "audiopll_diviock", .p = SAMA7G5_PLL_PARENT_FRACCK, .l = &pll_layout_divio, .c = &pll_characteristics, .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, .eid = PMC_AUDIOIOPLL, }, }, [PLL_ID_ETH] = { [PLL_COMPID_FRAC] = { .n = "ethpll_fracck", .p = SAMA7G5_PLL_PARENT_MAIN_XTAL, .l = &pll_layout_frac, .c = &pll_characteristics, .t = PLL_TYPE_FRAC, .f = CLK_SET_RATE_GATE, }, [PLL_COMPID_DIV0] = { .n = "ethpll_divpmcck", .p = SAMA7G5_PLL_PARENT_FRACCK, .l = &pll_layout_divpmc, .c = &pll_characteristics, .t = PLL_TYPE_DIV, .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, }, }, }; /* Used to create an array entry identifying a PLL by its components. */ #define PLL_IDS_TO_ARR_ENTRY(_id, _comp) { PLL_ID_##_id, PLL_COMPID_##_comp} /* * Master clock (MCK[1..4]) description * @n: clock name * @ep: extra parents names array (entry formed by PLL components * identifiers (see enum pll_component_id)) * @hw: pointer to clk_hw * @ep_chg_id: index in parents array that specifies the changeable * parent * @ep_count: extra parents count * @ep_mux_table: mux table for extra parents * @id: clock id * @eid: export index in sama7g5->chws[] array * @c: true if clock is critical and cannot be disabled */ static struct { const char *n; struct { int pll_id; int pll_compid; } ep[4]; struct clk_hw *hw; int ep_chg_id; u8 ep_count; u8 ep_mux_table[4]; u8 id; u8 eid; u8 c; } sama7g5_mckx[] = { { .n = "mck0", }, /* Dummy entry for MCK0 to store hw in probe. */ { .n = "mck1", .id = 1, .ep = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), }, .ep_mux_table = { 5, }, .ep_count = 1, .ep_chg_id = INT_MIN, .eid = PMC_MCK1, .c = 1, }, { .n = "mck2", .id = 2, .ep = { PLL_IDS_TO_ARR_ENTRY(DDR, DIV0), }, .ep_mux_table = { 6, }, .ep_count = 1, .ep_chg_id = INT_MIN, .c = 1, }, { .n = "mck3", .id = 3, .ep = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(DDR, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), }, .ep_mux_table = { 5, 6, 7, }, .ep_count = 3, .ep_chg_id = 5, }, { .n = "mck4", .id = 4, .ep = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), }, .ep_mux_table = { 5, }, .ep_count = 1, .ep_chg_id = INT_MIN, .c = 1, }, }; /* * System clock description * @n: clock name * @id: clock id */ static const struct { const char *n; u8 id; } sama7g5_systemck[] = { { .n = "pck0", .id = 8, }, { .n = "pck1", .id = 9, }, { .n = "pck2", .id = 10, }, { .n = "pck3", .id = 11, }, { .n = "pck4", .id = 12, }, { .n = "pck5", .id = 13, }, { .n = "pck6", .id = 14, }, { .n = "pck7", .id = 15, }, }; /* Mux table for programmable clocks. */ static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, }; /* * Peripheral clock parent hw identifier (used to index in sama7g5_mckx[]) * @PCK_PARENT_HW_MCK0: pck parent hw identifier is MCK0 * @PCK_PARENT_HW_MCK1: pck parent hw identifier is MCK1 * @PCK_PARENT_HW_MCK2: pck parent hw identifier is MCK2 * @PCK_PARENT_HW_MCK3: pck parent hw identifier is MCK3 * @PCK_PARENT_HW_MCK4: pck parent hw identifier is MCK4 * @PCK_PARENT_HW_MAX: max identifier */ enum sama7g5_pck_parent_hw_id { PCK_PARENT_HW_MCK0, PCK_PARENT_HW_MCK1, PCK_PARENT_HW_MCK2, PCK_PARENT_HW_MCK3, PCK_PARENT_HW_MCK4, PCK_PARENT_HW_MAX, }; /* * Peripheral clock description * @n: clock name * @p: clock parent hw id * @r: clock range values * @id: clock id * @chgp: index in parent array of the changeable parent */ static struct { const char *n; enum sama7g5_pck_parent_hw_id p; struct clk_range r; u8 chgp; u8 id; } sama7g5_periphck[] = { { .n = "pioA_clk", .p = PCK_PARENT_HW_MCK0, .id = 11, }, { .n = "securam_clk", .p = PCK_PARENT_HW_MCK0, .id = 18, }, { .n = "sfr_clk", .p = PCK_PARENT_HW_MCK1, .id = 19, }, { .n = "hsmc_clk", .p = PCK_PARENT_HW_MCK1, .id = 21, }, { .n = "xdmac0_clk", .p = PCK_PARENT_HW_MCK1, .id = 22, }, { .n = "xdmac1_clk", .p = PCK_PARENT_HW_MCK1, .id = 23, }, { .n = "xdmac2_clk", .p = PCK_PARENT_HW_MCK1, .id = 24, }, { .n = "acc_clk", .p = PCK_PARENT_HW_MCK1, .id = 25, }, { .n = "aes_clk", .p = PCK_PARENT_HW_MCK1, .id = 27, }, { .n = "tzaesbasc_clk", .p = PCK_PARENT_HW_MCK1, .id = 28, }, { .n = "asrc_clk", .p = PCK_PARENT_HW_MCK1, .id = 30, .r = { .max = 200000000, }, }, { .n = "cpkcc_clk", .p = PCK_PARENT_HW_MCK0, .id = 32, }, { .n = "csi_clk", .p = PCK_PARENT_HW_MCK3, .id = 33, .r = { .max = 266000000, }, .chgp = 1, }, { .n = "csi2dc_clk", .p = PCK_PARENT_HW_MCK3, .id = 34, .r = { .max = 266000000, }, .chgp = 1, }, { .n = "eic_clk", .p = PCK_PARENT_HW_MCK1, .id = 37, }, { .n = "flex0_clk", .p = PCK_PARENT_HW_MCK1, .id = 38, }, { .n = "flex1_clk", .p = PCK_PARENT_HW_MCK1, .id = 39, }, { .n = "flex2_clk", .p = PCK_PARENT_HW_MCK1, .id = 40, }, { .n = "flex3_clk", .p = PCK_PARENT_HW_MCK1, .id = 41, }, { .n = "flex4_clk", .p = PCK_PARENT_HW_MCK1, .id = 42, }, { .n = "flex5_clk", .p = PCK_PARENT_HW_MCK1, .id = 43, }, { .n = "flex6_clk", .p = PCK_PARENT_HW_MCK1, .id = 44, }, { .n = "flex7_clk", .p = PCK_PARENT_HW_MCK1, .id = 45, }, { .n = "flex8_clk", .p = PCK_PARENT_HW_MCK1, .id = 46, }, { .n = "flex9_clk", .p = PCK_PARENT_HW_MCK1, .id = 47, }, { .n = "flex10_clk", .p = PCK_PARENT_HW_MCK1, .id = 48, }, { .n = "flex11_clk", .p = PCK_PARENT_HW_MCK1, .id = 49, }, { .n = "gmac0_clk", .p = PCK_PARENT_HW_MCK1, .id = 51, }, { .n = "gmac1_clk", .p = PCK_PARENT_HW_MCK1, .id = 52, }, { .n = "icm_clk", .p = PCK_PARENT_HW_MCK1, .id = 55, }, { .n = "isc_clk", .p = PCK_PARENT_HW_MCK3, .id = 56, .r = { .max = 266000000, }, .chgp = 1, }, { .n = "i2smcc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 57, .r = { .max = 200000000, }, }, { .n = "i2smcc1_clk", .p = PCK_PARENT_HW_MCK1, .id = 58, .r = { .max = 200000000, }, }, { .n = "matrix_clk", .p = PCK_PARENT_HW_MCK1, .id = 60, }, { .n = "mcan0_clk", .p = PCK_PARENT_HW_MCK1, .id = 61, .r = { .max = 200000000, }, }, { .n = "mcan1_clk", .p = PCK_PARENT_HW_MCK1, .id = 62, .r = { .max = 200000000, }, }, { .n = "mcan2_clk", .p = PCK_PARENT_HW_MCK1, .id = 63, .r = { .max = 200000000, }, }, { .n = "mcan3_clk", .p = PCK_PARENT_HW_MCK1, .id = 64, .r = { .max = 200000000, }, }, { .n = "mcan4_clk", .p = PCK_PARENT_HW_MCK1, .id = 65, .r = { .max = 200000000, }, }, { .n = "mcan5_clk", .p = PCK_PARENT_HW_MCK1, .id = 66, .r = { .max = 200000000, }, }, { .n = "pdmc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 68, .r = { .max = 200000000, }, }, { .n = "pdmc1_clk", .p = PCK_PARENT_HW_MCK1, .id = 69, .r = { .max = 200000000, }, }, { .n = "pit64b0_clk", .p = PCK_PARENT_HW_MCK1, .id = 70, }, { .n = "pit64b1_clk", .p = PCK_PARENT_HW_MCK1, .id = 71, }, { .n = "pit64b2_clk", .p = PCK_PARENT_HW_MCK1, .id = 72, }, { .n = "pit64b3_clk", .p = PCK_PARENT_HW_MCK1, .id = 73, }, { .n = "pit64b4_clk", .p = PCK_PARENT_HW_MCK1, .id = 74, }, { .n = "pit64b5_clk", .p = PCK_PARENT_HW_MCK1, .id = 75, }, { .n = "pwm_clk", .p = PCK_PARENT_HW_MCK1, .id = 77, }, { .n = "qspi0_clk", .p = PCK_PARENT_HW_MCK1, .id = 78, }, { .n = "qspi1_clk", .p = PCK_PARENT_HW_MCK1, .id = 79, }, { .n = "sdmmc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 80, }, { .n = "sdmmc1_clk", .p = PCK_PARENT_HW_MCK1, .id = 81, }, { .n = "sdmmc2_clk", .p = PCK_PARENT_HW_MCK1, .id = 82, }, { .n = "sha_clk", .p = PCK_PARENT_HW_MCK1, .id = 83, }, { .n = "spdifrx_clk", .p = PCK_PARENT_HW_MCK1, .id = 84, .r = { .max = 200000000, }, }, { .n = "spdiftx_clk", .p = PCK_PARENT_HW_MCK1, .id = 85, .r = { .max = 200000000, }, }, { .n = "ssc0_clk", .p = PCK_PARENT_HW_MCK1, .id = 86, .r = { .max = 200000000, }, }, { .n = "ssc1_clk", .p = PCK_PARENT_HW_MCK1, .id = 87, .r = { .max = 200000000, }, }, { .n = "tcb0_ch0_clk", .p = PCK_PARENT_HW_MCK1, .id = 88, .r = { .max = 200000000, }, }, { .n = "tcb0_ch1_clk", .p = PCK_PARENT_HW_MCK1, .id = 89, .r = { .max = 200000000, }, }, { .n = "tcb0_ch2_clk", .p = PCK_PARENT_HW_MCK1, .id = 90, .r = { .max = 200000000, }, }, { .n = "tcb1_ch0_clk", .p = PCK_PARENT_HW_MCK1, .id = 91, .r = { .max = 200000000, }, }, { .n = "tcb1_ch1_clk", .p = PCK_PARENT_HW_MCK1, .id = 92, .r = { .max = 200000000, }, }, { .n = "tcb1_ch2_clk", .p = PCK_PARENT_HW_MCK1, .id = 93, .r = { .max = 200000000, }, }, { .n = "tcpca_clk", .p = PCK_PARENT_HW_MCK1, .id = 94, }, { .n = "tcpcb_clk", .p = PCK_PARENT_HW_MCK1, .id = 95, }, { .n = "tdes_clk", .p = PCK_PARENT_HW_MCK1, .id = 96, }, { .n = "trng_clk", .p = PCK_PARENT_HW_MCK1, .id = 97, }, { .n = "udphsa_clk", .p = PCK_PARENT_HW_MCK1, .id = 104, }, { .n = "udphsb_clk", .p = PCK_PARENT_HW_MCK1, .id = 105, }, { .n = "uhphs_clk", .p = PCK_PARENT_HW_MCK1, .id = 106, }, }; /* * Generic clock description * @n: clock name * @pp: PLL parents (entry formed by PLL components identifiers * (see enum pll_component_id)) * @pp_mux_table: PLL parents mux table * @r: clock output range * @pp_chg_id: id in parent array of changeable PLL parent * @pp_count: PLL parents count * @id: clock id */ static const struct { const char *n; struct { int pll_id; int pll_compid; } pp[8]; const char pp_mux_table[8]; struct clk_range r; int pp_chg_id; u8 pp_count; u8 id; } sama7g5_gck[] = { { .n = "adc_gclk", .id = 26, .r = { .max = 100000000, }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), }, .pp_mux_table = { 5, 7, 9, }, .pp_count = 3, .pp_chg_id = INT_MIN, }, { .n = "asrc_gclk", .id = 30, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), }, .pp_mux_table = { 9, }, .pp_count = 1, .pp_chg_id = 3, }, { .n = "csi_gclk", .id = 33, .r = { .max = 27000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(DDR, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), }, .pp_mux_table = { 6, 7, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "flex0_gclk", .id = 38, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "flex1_gclk", .id = 39, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "flex2_gclk", .id = 40, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "flex3_gclk", .id = 41, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "flex4_gclk", .id = 42, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "flex5_gclk", .id = 43, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "flex6_gclk", .id = 44, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "flex7_gclk", .id = 45, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "flex8_gclk", .id = 46, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "flex9_gclk", .id = 47, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "flex10_gclk", .id = 48, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "flex11_gclk", .id = 49, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "gmac0_gclk", .id = 51, .r = { .max = 125000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), }, .pp_mux_table = { 10, }, .pp_count = 1, .pp_chg_id = 3, }, { .n = "gmac1_gclk", .id = 52, .r = { .max = 50000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), }, .pp_mux_table = { 10, }, .pp_count = 1, .pp_chg_id = INT_MIN, }, { .n = "gmac0_tsu_gclk", .id = 53, .r = { .max = 300000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), }, .pp_mux_table = { 9, 10, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "gmac1_tsu_gclk", .id = 54, .r = { .max = 300000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), }, .pp_mux_table = { 9, 10, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "i2smcc0_gclk", .id = 57, .r = { .max = 100000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), }, .pp_mux_table = { 5, 9, }, .pp_count = 2, .pp_chg_id = 4, }, { .n = "i2smcc1_gclk", .id = 58, .r = { .max = 100000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), }, .pp_mux_table = { 5, 9, }, .pp_count = 2, .pp_chg_id = 4, }, { .n = "mcan0_gclk", .id = 61, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "mcan1_gclk", .id = 62, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "mcan2_gclk", .id = 63, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "mcan3_gclk", .id = 64, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "mcan4_gclk", .id = 65, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "mcan5_gclk", .id = 66, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "pdmc0_gclk", .id = 68, .r = { .max = 50000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), }, .pp_mux_table = { 5, 9, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "pdmc1_gclk", .id = 69, .r = { .max = 50000000, }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), }, .pp_mux_table = { 5, 9, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "pit64b0_gclk", .id = 70, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), }, .pp_mux_table = { 5, 7, 8, 9, 10, }, .pp_count = 5, .pp_chg_id = INT_MIN, }, { .n = "pit64b1_gclk", .id = 71, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), }, .pp_mux_table = { 5, 7, 8, 9, 10, }, .pp_count = 5, .pp_chg_id = INT_MIN, }, { .n = "pit64b2_gclk", .id = 72, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), }, .pp_mux_table = { 5, 7, 8, 9, 10, }, .pp_count = 5, .pp_chg_id = INT_MIN, }, { .n = "pit64b3_gclk", .id = 73, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), }, .pp_mux_table = { 5, 7, 8, 9, 10, }, .pp_count = 5, .pp_chg_id = INT_MIN, }, { .n = "pit64b4_gclk", .id = 74, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), }, .pp_mux_table = { 5, 7, 8, 9, 10, }, .pp_count = 5, .pp_chg_id = INT_MIN, }, { .n = "pit64b5_gclk", .id = 75, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), }, .pp_mux_table = { 5, 7, 8, 9, 10, }, .pp_count = 5, .pp_chg_id = INT_MIN, }, { .n = "qspi0_gclk", .id = 78, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "qspi1_gclk", .id = 79, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "sdmmc0_gclk", .id = 80, .r = { .max = 208000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = 4, }, { .n = "sdmmc1_gclk", .id = 81, .r = { .max = 208000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = 4, }, { .n = "sdmmc2_gclk", .id = 82, .r = { .max = 208000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), }, .pp_mux_table = { 5, 8, }, .pp_count = 2, .pp_chg_id = 4, }, { .n = "spdifrx_gclk", .id = 84, .r = { .max = 150000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), }, .pp_mux_table = { 5, 9, }, .pp_count = 2, .pp_chg_id = 4, }, { .n = "spdiftx_gclk", .id = 85, .r = { .max = 25000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), }, .pp_mux_table = { 5, 9, }, .pp_count = 2, .pp_chg_id = 4, }, { .n = "tcb0_ch0_gclk", .id = 88, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), }, .pp_mux_table = { 5, 7, 8, 9, 10, }, .pp_count = 5, .pp_chg_id = INT_MIN, }, { .n = "tcb1_ch0_gclk", .id = 91, .r = { .max = 200000000 }, .pp = { PLL_IDS_TO_ARR_ENTRY(SYS, DIV0), PLL_IDS_TO_ARR_ENTRY(IMG, DIV0), PLL_IDS_TO_ARR_ENTRY(BAUD, DIV0), PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(ETH, DIV0), }, .pp_mux_table = { 5, 7, 8, 9, 10, }, .pp_count = 5, .pp_chg_id = INT_MIN, }, { .n = "tcpca_gclk", .id = 94, .r = { .max = 32768, }, .pp_chg_id = INT_MIN, }, { .n = "tcpcb_gclk", .id = 95, .r = { .max = 32768, }, .pp_chg_id = INT_MIN, }, }; /* MCK0 characteristics. */ static const struct clk_master_characteristics mck0_characteristics = { .output = { .min = 32768, .max = 200000000 }, .divisors = { 1, 2, 4, 3, 5 }, .have_div3_pres = 1, }; /* MCK0 layout. */ static const struct clk_master_layout mck0_layout = { .mask = 0x773, .pres_shift = 4, .offset = 0x28, }; /* Programmable clock layout. */ static const struct clk_programmable_layout programmable_layout = { .pres_mask = 0xff, .pres_shift = 8, .css_mask = 0x1f, .have_slck_mck = 0, .is_pres_direct = 1, }; /* Peripheral clock layout. */ static const struct clk_pcr_layout sama7g5_pcr_layout = { .offset = 0x88, .cmd = BIT(31), .gckcss_mask = GENMASK(12, 8), .pid_mask = GENMASK(6, 0), }; static void __init sama7g5_pmc_setup(struct device_node *np) { const char *main_xtal_name = "main_xtal"; struct pmc_data *sama7g5_pmc; void **alloc_mem = NULL; int alloc_mem_size = 0; struct regmap *regmap; struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; struct clk_hw *td_slck_hw, *md_slck_hw; static struct clk_parent_data parent_data; struct clk_hw *parent_hws[10]; bool bypass; int i, j; td_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "td_slck")); md_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "md_slck")); main_xtal_hw = __clk_get_hw(of_clk_get_by_name(np, main_xtal_name)); if (!td_slck_hw || !md_slck_hw || !main_xtal_hw) return; regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; sama7g5_pmc = pmc_data_allocate(PMC_MCK1 + 1, nck(sama7g5_systemck), nck(sama7g5_periphck), nck(sama7g5_gck), 8); if (!sama7g5_pmc) return; alloc_mem = kmalloc(sizeof(void *) * (ARRAY_SIZE(sama7g5_mckx) + ARRAY_SIZE(sama7g5_gck)), GFP_KERNEL); if (!alloc_mem) goto err_free; main_rc_hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 50000000); if (IS_ERR(main_rc_hw)) goto err_free; bypass = of_property_read_bool(np, "atmel,osc-bypass"); parent_data.name = main_xtal_name; parent_data.fw_name = main_xtal_name; main_osc_hw = at91_clk_register_main_osc(regmap, "main_osc", NULL, &parent_data, bypass); if (IS_ERR(main_osc_hw)) goto err_free; parent_hws[0] = main_rc_hw; parent_hws[1] = main_osc_hw; hw = at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_hws, 2); if (IS_ERR(hw)) goto err_free; sama7g5_pmc->chws[PMC_MAIN] = hw; for (i = 0; i < PLL_ID_MAX; i++) { for (j = 0; j < 3; j++) { struct clk_hw *parent_hw; if (!sama7g5_plls[i][j].n) continue; switch (sama7g5_plls[i][j].t) { case PLL_TYPE_FRAC: switch (sama7g5_plls[i][j].p) { case SAMA7G5_PLL_PARENT_MAINCK: parent_hw = sama7g5_pmc->chws[PMC_MAIN]; break; case SAMA7G5_PLL_PARENT_MAIN_XTAL: parent_hw = main_xtal_hw; break; default: /* Should not happen. */ parent_hw = NULL; break; } hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sama7g5_plls[i][j].n, NULL, parent_hw, i, sama7g5_plls[i][j].c, sama7g5_plls[i][j].l, sama7g5_plls[i][j].f); break; case PLL_TYPE_DIV: hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, sama7g5_plls[i][j].n, NULL, sama7g5_plls[i][0].hw, i, sama7g5_plls[i][j].c, sama7g5_plls[i][j].l, sama7g5_plls[i][j].f, sama7g5_plls[i][j].safe_div); break; default: continue; } if (IS_ERR(hw)) goto err_free; sama7g5_plls[i][j].hw = hw; if (sama7g5_plls[i][j].eid) sama7g5_pmc->chws[sama7g5_plls[i][j].eid] = hw; } } hw = at91_clk_register_master_div(regmap, "mck0", NULL, sama7g5_plls[PLL_ID_CPU][1].hw, &mck0_layout, &mck0_characteristics, &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); if (IS_ERR(hw)) goto err_free; sama7g5_mckx[PCK_PARENT_HW_MCK0].hw = sama7g5_pmc->chws[PMC_MCK] = hw; parent_hws[0] = md_slck_hw; parent_hws[1] = td_slck_hw; parent_hws[2] = sama7g5_pmc->chws[PMC_MAIN]; for (i = PCK_PARENT_HW_MCK1; i < ARRAY_SIZE(sama7g5_mckx); i++) { u8 num_parents = 3 + sama7g5_mckx[i].ep_count; struct clk_hw *tmp_parent_hws[8]; u32 *mux_table; mux_table = kmalloc_array(num_parents, sizeof(*mux_table), GFP_KERNEL); if (!mux_table) goto err_free; SAMA7G5_INIT_TABLE(mux_table, 3); SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, sama7g5_mckx[i].ep_count); for (j = 0; j < sama7g5_mckx[i].ep_count; j++) { u8 pll_id = sama7g5_mckx[i].ep[j].pll_id; u8 pll_compid = sama7g5_mckx[i].ep[j].pll_compid; tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw; } SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws, sama7g5_mckx[i].ep_count); hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n, num_parents, NULL, parent_hws, mux_table, &pmc_mckX_lock, sama7g5_mckx[i].id, sama7g5_mckx[i].c, sama7g5_mckx[i].ep_chg_id); if (IS_ERR(hw)) goto err_free; alloc_mem[alloc_mem_size++] = mux_table; sama7g5_mckx[i].hw = hw; if (sama7g5_mckx[i].eid) sama7g5_pmc->chws[sama7g5_mckx[i].eid] = hw; } hw = at91_clk_sama7g5_register_utmi(regmap, "utmick", NULL, main_xtal_hw); if (IS_ERR(hw)) goto err_free; sama7g5_pmc->chws[PMC_UTMI] = hw; parent_hws[0] = md_slck_hw; parent_hws[1] = td_slck_hw; parent_hws[2] = sama7g5_pmc->chws[PMC_MAIN]; parent_hws[3] = sama7g5_plls[PLL_ID_SYS][PLL_COMPID_DIV0].hw; parent_hws[4] = sama7g5_plls[PLL_ID_DDR][PLL_COMPID_DIV0].hw; parent_hws[5] = sama7g5_plls[PLL_ID_IMG][PLL_COMPID_DIV0].hw; parent_hws[6] = sama7g5_plls[PLL_ID_BAUD][PLL_COMPID_DIV0].hw; parent_hws[7] = sama7g5_plls[PLL_ID_AUDIO][PLL_COMPID_DIV0].hw; parent_hws[8] = sama7g5_plls[PLL_ID_ETH][PLL_COMPID_DIV0].hw; for (i = 0; i < 8; i++) { char name[6]; snprintf(name, sizeof(name), "prog%d", i); hw = at91_clk_register_programmable(regmap, name, NULL, parent_hws, 9, i, &programmable_layout, sama7g5_prog_mux_table); if (IS_ERR(hw)) goto err_free; sama7g5_pmc->pchws[i] = hw; } for (i = 0; i < ARRAY_SIZE(sama7g5_systemck); i++) { hw = at91_clk_register_system(regmap, sama7g5_systemck[i].n, NULL, sama7g5_pmc->pchws[i], sama7g5_systemck[i].id, 0); if (IS_ERR(hw)) goto err_free; sama7g5_pmc->shws[sama7g5_systemck[i].id] = hw; } for (i = 0; i < ARRAY_SIZE(sama7g5_periphck); i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama7g5_pcr_layout, sama7g5_periphck[i].n, NULL, sama7g5_mckx[sama7g5_periphck[i].p].hw, sama7g5_periphck[i].id, &sama7g5_periphck[i].r, sama7g5_periphck[i].chgp ? 0 : INT_MIN, 0); if (IS_ERR(hw)) goto err_free; sama7g5_pmc->phws[sama7g5_periphck[i].id] = hw; } parent_hws[0] = md_slck_hw; parent_hws[1] = td_slck_hw; parent_hws[2] = sama7g5_pmc->chws[PMC_MAIN]; for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) { u8 num_parents = 3 + sama7g5_gck[i].pp_count; struct clk_hw *tmp_parent_hws[8]; u32 *mux_table; mux_table = kmalloc_array(num_parents, sizeof(*mux_table), GFP_KERNEL); if (!mux_table) goto err_free; SAMA7G5_INIT_TABLE(mux_table, 3); SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, sama7g5_gck[i].pp_count); for (j = 0; j < sama7g5_gck[i].pp_count; j++) { u8 pll_id = sama7g5_gck[i].pp[j].pll_id; u8 pll_compid = sama7g5_gck[i].pp[j].pll_compid; tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw; } SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws, sama7g5_gck[i].pp_count); hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, &sama7g5_pcr_layout, sama7g5_gck[i].n, NULL, parent_hws, mux_table, num_parents, sama7g5_gck[i].id, &sama7g5_gck[i].r, sama7g5_gck[i].pp_chg_id); if (IS_ERR(hw)) goto err_free; sama7g5_pmc->ghws[sama7g5_gck[i].id] = hw; alloc_mem[alloc_mem_size++] = mux_table; } of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama7g5_pmc); return; err_free: if (alloc_mem) { for (i = 0; i < alloc_mem_size; i++) kfree(alloc_mem[i]); kfree(alloc_mem); } kfree(sama7g5_pmc); } /* Some clks are used for a clocksource */ CLK_OF_DECLARE(sama7g5_pmc, "microchip,sama7g5-pmc", sama7g5_pmc_setup);
linux-master
drivers/clk/at91/sama7g5.c
// SPDX-License-Identifier: GPL-2.0 #include <linux/clk-provider.h> #include <linux/mfd/syscon.h> #include <linux/slab.h> #include <dt-bindings/clock/at91.h> #include "pmc.h" static DEFINE_SPINLOCK(pmc_pll_lock); static DEFINE_SPINLOCK(mck_lock); static const struct clk_master_characteristics mck_characteristics = { .output = { .min = 140000000, .max = 200000000 }, .divisors = { 1, 2, 4, 3 }, .have_div3_pres = 1, }; static const struct clk_master_layout sam9x60_master_layout = { .mask = 0x373, .pres_shift = 4, .offset = 0x28, }; static const struct clk_range plla_outputs[] = { { .min = 2343750, .max = 1200000000 }, }; static const struct clk_pll_characteristics plla_characteristics = { .input = { .min = 12000000, .max = 48000000 }, .num_output = ARRAY_SIZE(plla_outputs), .output = plla_outputs, }; static const struct clk_range upll_outputs[] = { { .min = 300000000, .max = 500000000 }, }; static const struct clk_pll_characteristics upll_characteristics = { .input = { .min = 12000000, .max = 48000000 }, .num_output = ARRAY_SIZE(upll_outputs), .output = upll_outputs, .upll = true, }; static const struct clk_pll_layout pll_frac_layout = { .mul_mask = GENMASK(31, 24), .frac_mask = GENMASK(21, 0), .mul_shift = 24, .frac_shift = 0, }; static const struct clk_pll_layout pll_div_layout = { .div_mask = GENMASK(7, 0), .endiv_mask = BIT(29), .div_shift = 0, .endiv_shift = 29, }; static const struct clk_programmable_layout sam9x60_programmable_layout = { .pres_mask = 0xff, .pres_shift = 8, .css_mask = 0x1f, .have_slck_mck = 0, .is_pres_direct = 1, }; static const struct clk_pcr_layout sam9x60_pcr_layout = { .offset = 0x88, .cmd = BIT(31), .gckcss_mask = GENMASK(12, 8), .pid_mask = GENMASK(6, 0), }; static const struct { char *n; char *p; unsigned long flags; u8 id; } sam9x60_systemck[] = { /* * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, { .n = "uhpck", .p = "usbck", .id = 6 }, { .n = "pck0", .p = "prog0", .id = 8 }, { .n = "pck1", .p = "prog1", .id = 9 }, { .n = "qspick", .p = "masterck_div", .id = 19 }, }; static const struct { char *n; unsigned long flags; u8 id; } sam9x60_periphck[] = { { .n = "pioA_clk", .id = 2, }, { .n = "pioB_clk", .id = 3, }, { .n = "pioC_clk", .id = 4, }, { .n = "flex0_clk", .id = 5, }, { .n = "flex1_clk", .id = 6, }, { .n = "flex2_clk", .id = 7, }, { .n = "flex3_clk", .id = 8, }, { .n = "flex6_clk", .id = 9, }, { .n = "flex7_clk", .id = 10, }, { .n = "flex8_clk", .id = 11, }, { .n = "sdmmc0_clk", .id = 12, }, { .n = "flex4_clk", .id = 13, }, { .n = "flex5_clk", .id = 14, }, { .n = "flex9_clk", .id = 15, }, { .n = "flex10_clk", .id = 16, }, { .n = "tcb0_clk", .id = 17, }, { .n = "pwm_clk", .id = 18, }, { .n = "adc_clk", .id = 19, }, { .n = "dma0_clk", .id = 20, }, { .n = "matrix_clk", .id = 21, }, { .n = "uhphs_clk", .id = 22, }, { .n = "udphs_clk", .id = 23, }, { .n = "macb0_clk", .id = 24, }, { .n = "lcd_clk", .id = 25, }, { .n = "sdmmc1_clk", .id = 26, }, { .n = "macb1_clk", .id = 27, }, { .n = "ssc_clk", .id = 28, }, { .n = "can0_clk", .id = 29, }, { .n = "can1_clk", .id = 30, }, { .n = "flex11_clk", .id = 32, }, { .n = "flex12_clk", .id = 33, }, { .n = "i2s_clk", .id = 34, }, { .n = "qspi_clk", .id = 35, }, { .n = "gfx2d_clk", .id = 36, }, { .n = "pit64b_clk", .id = 37, }, { .n = "trng_clk", .id = 38, }, { .n = "aes_clk", .id = 39, }, { .n = "tdes_clk", .id = 40, }, { .n = "sha_clk", .id = 41, }, { .n = "classd_clk", .id = 42, }, { .n = "isi_clk", .id = 43, }, { .n = "pioD_clk", .id = 44, }, { .n = "tcb1_clk", .id = 45, }, { .n = "dbgu_clk", .id = 47, }, /* * mpddr_clk feeds DDR controller and is enabled by bootloader thus we * need to keep it enabled in case there is no Linux consumer for it. */ { .n = "mpddr_clk", .id = 49, .flags = CLK_IS_CRITICAL }, }; static const struct { char *n; u8 id; struct clk_range r; } sam9x60_gck[] = { { .n = "flex0_gclk", .id = 5, }, { .n = "flex1_gclk", .id = 6, }, { .n = "flex2_gclk", .id = 7, }, { .n = "flex3_gclk", .id = 8, }, { .n = "flex6_gclk", .id = 9, }, { .n = "flex7_gclk", .id = 10, }, { .n = "flex8_gclk", .id = 11, }, { .n = "sdmmc0_gclk", .id = 12, .r = { .min = 0, .max = 105000000 }, }, { .n = "flex4_gclk", .id = 13, }, { .n = "flex5_gclk", .id = 14, }, { .n = "flex9_gclk", .id = 15, }, { .n = "flex10_gclk", .id = 16, }, { .n = "tcb0_gclk", .id = 17, }, { .n = "adc_gclk", .id = 19, }, { .n = "lcd_gclk", .id = 25, .r = { .min = 0, .max = 140000000 }, }, { .n = "sdmmc1_gclk", .id = 26, .r = { .min = 0, .max = 105000000 }, }, { .n = "flex11_gclk", .id = 32, }, { .n = "flex12_gclk", .id = 33, }, { .n = "i2s_gclk", .id = 34, .r = { .min = 0, .max = 105000000 }, }, { .n = "pit64b_gclk", .id = 37, }, { .n = "classd_gclk", .id = 42, .r = { .min = 0, .max = 100000000 }, }, { .n = "tcb1_gclk", .id = 45, }, { .n = "dbgu_gclk", .id = 47, }, }; static void __init sam9x60_pmc_setup(struct device_node *np) { struct clk_range range = CLK_RANGE(0, 0); const char *td_slck_name, *md_slck_name, *mainxtal_name; struct pmc_data *sam9x60_pmc; const char *parent_names[6]; struct clk_hw *main_osc_hw; struct regmap *regmap; struct clk_hw *hw; int i; i = of_property_match_string(np, "clock-names", "td_slck"); if (i < 0) return; td_slck_name = of_clk_get_parent_name(np, i); i = of_property_match_string(np, "clock-names", "md_slck"); if (i < 0) return; md_slck_name = of_clk_get_parent_name(np, i); i = of_property_match_string(np, "clock-names", "main_xtal"); if (i < 0) return; mainxtal_name = of_clk_get_parent_name(np, i); regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; sam9x60_pmc = pmc_data_allocate(PMC_PLLACK + 1, nck(sam9x60_systemck), nck(sam9x60_periphck), nck(sam9x60_gck), 8); if (!sam9x60_pmc) return; hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 50000000); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 0); if (IS_ERR(hw)) goto err_free; main_osc_hw = hw; parent_names[0] = "main_rc_osc"; parent_names[1] = "main_osc"; hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2); if (IS_ERR(hw)) goto err_free; sam9x60_pmc->chws[PMC_MAIN] = hw; hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck", "mainck", sam9x60_pmc->chws[PMC_MAIN], 0, &plla_characteristics, &pll_frac_layout, /* * This feeds pllack_divck which * feeds CPU. It should not be * disabled. */ CLK_IS_CRITICAL | CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck", "pllack_fracck", NULL, 0, &plla_characteristics, &pll_div_layout, /* * This feeds CPU. It should not * be disabled. */ CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; sam9x60_pmc->chws[PMC_PLLACK] = hw; hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck", "main_osc", main_osc_hw, 1, &upll_characteristics, &pll_frac_layout, CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck", "upllck_fracck", NULL, 1, &upll_characteristics, &pll_div_layout, CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, 0); if (IS_ERR(hw)) goto err_free; sam9x60_pmc->chws[PMC_UTMI] = hw; parent_names[0] = md_slck_name; parent_names[1] = "mainck"; parent_names[2] = "pllack_divck"; hw = at91_clk_register_master_pres(regmap, "masterck_pres", 3, parent_names, NULL, &sam9x60_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_master_div(regmap, "masterck_div", "masterck_pres", NULL, &sam9x60_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; sam9x60_pmc->chws[PMC_MCK] = hw; parent_names[0] = "pllack_divck"; parent_names[1] = "upllck_divck"; parent_names[2] = "main_osc"; hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); if (IS_ERR(hw)) goto err_free; parent_names[0] = md_slck_name; parent_names[1] = td_slck_name; parent_names[2] = "mainck"; parent_names[3] = "masterck_div"; parent_names[4] = "pllack_divck"; parent_names[5] = "upllck_divck"; for (i = 0; i < 2; i++) { char name[6]; snprintf(name, sizeof(name), "prog%d", i); hw = at91_clk_register_programmable(regmap, name, parent_names, NULL, 6, i, &sam9x60_programmable_layout, NULL); if (IS_ERR(hw)) goto err_free; sam9x60_pmc->pchws[i] = hw; } for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) { hw = at91_clk_register_system(regmap, sam9x60_systemck[i].n, sam9x60_systemck[i].p, NULL, sam9x60_systemck[i].id, sam9x60_systemck[i].flags); if (IS_ERR(hw)) goto err_free; sam9x60_pmc->shws[sam9x60_systemck[i].id] = hw; } for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sam9x60_pcr_layout, sam9x60_periphck[i].n, "masterck_div", NULL, sam9x60_periphck[i].id, &range, INT_MIN, sam9x60_periphck[i].flags); if (IS_ERR(hw)) goto err_free; sam9x60_pmc->phws[sam9x60_periphck[i].id] = hw; } for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) { hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, &sam9x60_pcr_layout, sam9x60_gck[i].n, parent_names, NULL, NULL, 6, sam9x60_gck[i].id, &sam9x60_gck[i].r, INT_MIN); if (IS_ERR(hw)) goto err_free; sam9x60_pmc->ghws[sam9x60_gck[i].id] = hw; } of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x60_pmc); return; err_free: kfree(sam9x60_pmc); } /* Some clks are used for a clocksource */ CLK_OF_DECLARE(sam9x60_pmc, "microchip,sam9x60-pmc", sam9x60_pmc_setup);
linux-master
drivers/clk/at91/sam9x60.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <[email protected]> */ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "pmc.h" #define SMD_DIV_SHIFT 8 #define SMD_MAX_DIV 0xf struct at91sam9x5_clk_smd { struct clk_hw hw; struct regmap *regmap; }; #define to_at91sam9x5_clk_smd(hw) \ container_of(hw, struct at91sam9x5_clk_smd, hw) static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); unsigned int smdr; u8 smddiv; regmap_read(smd->regmap, AT91_PMC_SMD, &smdr); smddiv = (smdr & AT91_PMC_SMD_DIV) >> SMD_DIV_SHIFT; return parent_rate / (smddiv + 1); } static int at91sam9x5_clk_smd_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { unsigned long div; unsigned long bestrate; unsigned long tmp; if (req->rate >= req->best_parent_rate) { req->rate = req->best_parent_rate; return 0; } div = req->best_parent_rate / req->rate; if (div > SMD_MAX_DIV) { req->rate = req->best_parent_rate / (SMD_MAX_DIV + 1); return 0; } bestrate = req->best_parent_rate / div; tmp = req->best_parent_rate / (div + 1); if (bestrate - req->rate > req->rate - tmp) bestrate = tmp; req->rate = bestrate; return 0; } static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index) { struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); if (index > 1) return -EINVAL; regmap_update_bits(smd->regmap, AT91_PMC_SMD, AT91_PMC_SMDS, index ? AT91_PMC_SMDS : 0); return 0; } static u8 at91sam9x5_clk_smd_get_parent(struct clk_hw *hw) { struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); unsigned int smdr; regmap_read(smd->regmap, AT91_PMC_SMD, &smdr); return smdr & AT91_PMC_SMDS; } static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); unsigned long div = parent_rate / rate; if (parent_rate % rate || div < 1 || div > (SMD_MAX_DIV + 1)) return -EINVAL; regmap_update_bits(smd->regmap, AT91_PMC_SMD, AT91_PMC_SMD_DIV, (div - 1) << SMD_DIV_SHIFT); return 0; } static const struct clk_ops at91sam9x5_smd_ops = { .recalc_rate = at91sam9x5_clk_smd_recalc_rate, .determine_rate = at91sam9x5_clk_smd_determine_rate, .get_parent = at91sam9x5_clk_smd_get_parent, .set_parent = at91sam9x5_clk_smd_set_parent, .set_rate = at91sam9x5_clk_smd_set_rate, }; struct clk_hw * __init at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name, const char **parent_names, u8 num_parents) { struct at91sam9x5_clk_smd *smd; struct clk_hw *hw; struct clk_init_data init; int ret; smd = kzalloc(sizeof(*smd), GFP_KERNEL); if (!smd) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &at91sam9x5_smd_ops; init.parent_names = parent_names; init.num_parents = num_parents; init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; smd->hw.init = &init; smd->regmap = regmap; hw = &smd->hw; ret = clk_hw_register(NULL, &smd->hw); if (ret) { kfree(smd); hw = ERR_PTR(ret); } return hw; }
linux-master
drivers/clk/at91/clk-smd.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <[email protected]> */ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "pmc.h" #define PROG_ID_MAX 7 #define PROG_STATUS_MASK(id) (1 << ((id) + 8)) #define PROG_PRES(layout, pckr) ((pckr >> layout->pres_shift) & layout->pres_mask) #define PROG_MAX_RM9200_CSS 3 struct clk_programmable { struct clk_hw hw; struct regmap *regmap; u32 *mux_table; u8 id; const struct clk_programmable_layout *layout; struct at91_clk_pms pms; }; #define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw) static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_programmable *prog = to_clk_programmable(hw); const struct clk_programmable_layout *layout = prog->layout; unsigned int pckr; unsigned long rate; regmap_read(prog->regmap, AT91_PMC_PCKR(prog->id), &pckr); if (layout->is_pres_direct) rate = parent_rate / (PROG_PRES(layout, pckr) + 1); else rate = parent_rate >> PROG_PRES(layout, pckr); return rate; } static int clk_programmable_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct clk_programmable *prog = to_clk_programmable(hw); const struct clk_programmable_layout *layout = prog->layout; struct clk_hw *parent; long best_rate = -EINVAL; unsigned long parent_rate; unsigned long tmp_rate = 0; int shift; int i; for (i = 0; i < clk_hw_get_num_parents(hw); i++) { parent = clk_hw_get_parent_by_index(hw, i); if (!parent) continue; parent_rate = clk_hw_get_rate(parent); if (layout->is_pres_direct) { for (shift = 0; shift <= layout->pres_mask; shift++) { tmp_rate = parent_rate / (shift + 1); if (tmp_rate <= req->rate) break; } } else { for (shift = 0; shift < layout->pres_mask; shift++) { tmp_rate = parent_rate >> shift; if (tmp_rate <= req->rate) break; } } if (tmp_rate > req->rate) continue; if (best_rate < 0 || (req->rate - tmp_rate) < (req->rate - best_rate)) { best_rate = tmp_rate; req->best_parent_rate = parent_rate; req->best_parent_hw = parent; } if (!best_rate) break; } if (best_rate < 0) return best_rate; req->rate = best_rate; return 0; } static int clk_programmable_set_parent(struct clk_hw *hw, u8 index) { struct clk_programmable *prog = to_clk_programmable(hw); const struct clk_programmable_layout *layout = prog->layout; unsigned int mask = layout->css_mask; unsigned int pckr = index; if (layout->have_slck_mck) mask |= AT91_PMC_CSSMCK_MCK; if (prog->mux_table) pckr = clk_mux_index_to_val(prog->mux_table, 0, index); if (index > layout->css_mask) { if (index > PROG_MAX_RM9200_CSS && !layout->have_slck_mck) return -EINVAL; pckr |= AT91_PMC_CSSMCK_MCK; } regmap_update_bits(prog->regmap, AT91_PMC_PCKR(prog->id), mask, pckr); return 0; } static u8 clk_programmable_get_parent(struct clk_hw *hw) { struct clk_programmable *prog = to_clk_programmable(hw); const struct clk_programmable_layout *layout = prog->layout; unsigned int pckr; u8 ret; regmap_read(prog->regmap, AT91_PMC_PCKR(prog->id), &pckr); ret = pckr & layout->css_mask; if (layout->have_slck_mck && (pckr & AT91_PMC_CSSMCK_MCK) && !ret) ret = PROG_MAX_RM9200_CSS + 1; if (prog->mux_table) ret = clk_mux_val_to_index(&prog->hw, prog->mux_table, 0, ret); return ret; } static int clk_programmable_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_programmable *prog = to_clk_programmable(hw); const struct clk_programmable_layout *layout = prog->layout; unsigned long div = parent_rate / rate; int shift = 0; if (!div) return -EINVAL; if (layout->is_pres_direct) { shift = div - 1; if (shift > layout->pres_mask) return -EINVAL; } else { shift = fls(div) - 1; if (div != (1 << shift)) return -EINVAL; if (shift >= layout->pres_mask) return -EINVAL; } regmap_update_bits(prog->regmap, AT91_PMC_PCKR(prog->id), layout->pres_mask << layout->pres_shift, shift << layout->pres_shift); return 0; } static int clk_programmable_save_context(struct clk_hw *hw) { struct clk_programmable *prog = to_clk_programmable(hw); struct clk_hw *parent_hw = clk_hw_get_parent(hw); prog->pms.parent = clk_programmable_get_parent(hw); prog->pms.parent_rate = clk_hw_get_rate(parent_hw); prog->pms.rate = clk_programmable_recalc_rate(hw, prog->pms.parent_rate); return 0; } static void clk_programmable_restore_context(struct clk_hw *hw) { struct clk_programmable *prog = to_clk_programmable(hw); int ret; ret = clk_programmable_set_parent(hw, prog->pms.parent); if (ret) return; clk_programmable_set_rate(hw, prog->pms.rate, prog->pms.parent_rate); } static const struct clk_ops programmable_ops = { .recalc_rate = clk_programmable_recalc_rate, .determine_rate = clk_programmable_determine_rate, .get_parent = clk_programmable_get_parent, .set_parent = clk_programmable_set_parent, .set_rate = clk_programmable_set_rate, .save_context = clk_programmable_save_context, .restore_context = clk_programmable_restore_context, }; struct clk_hw * __init at91_clk_register_programmable(struct regmap *regmap, const char *name, const char **parent_names, struct clk_hw **parent_hws, u8 num_parents, u8 id, const struct clk_programmable_layout *layout, u32 *mux_table) { struct clk_programmable *prog; struct clk_hw *hw; struct clk_init_data init = {}; int ret; if (id > PROG_ID_MAX || !(parent_names || parent_hws)) return ERR_PTR(-EINVAL); prog = kzalloc(sizeof(*prog), GFP_KERNEL); if (!prog) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &programmable_ops; if (parent_hws) init.parent_hws = (const struct clk_hw **)parent_hws; else init.parent_names = parent_names; init.num_parents = num_parents; init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; prog->id = id; prog->layout = layout; prog->hw.init = &init; prog->regmap = regmap; prog->mux_table = mux_table; hw = &prog->hw; ret = clk_hw_register(NULL, &prog->hw); if (ret) { kfree(prog); hw = ERR_PTR(ret); } return hw; } const struct clk_programmable_layout at91rm9200_programmable_layout = { .pres_mask = 0x7, .pres_shift = 2, .css_mask = 0x3, .have_slck_mck = 0, .is_pres_direct = 0, }; const struct clk_programmable_layout at91sam9g45_programmable_layout = { .pres_mask = 0x7, .pres_shift = 2, .css_mask = 0x3, .have_slck_mck = 1, .is_pres_direct = 0, }; const struct clk_programmable_layout at91sam9x5_programmable_layout = { .pres_mask = 0x7, .pres_shift = 4, .css_mask = 0x7, .have_slck_mck = 0, .is_pres_direct = 0, };
linux-master
drivers/clk/at91/clk-programmable.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2015 Atmel Corporation, * Nicolas Ferre <[email protected]> * * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON. */ #include <linux/bitfield.h> #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "pmc.h" #define GENERATED_MAX_DIV 255 struct clk_generated { struct clk_hw hw; struct regmap *regmap; struct clk_range range; spinlock_t *lock; u32 *mux_table; u32 id; u32 gckdiv; const struct clk_pcr_layout *layout; struct at91_clk_pms pms; u8 parent_id; int chg_pid; }; #define to_clk_generated(hw) \ container_of(hw, struct clk_generated, hw) static int clk_generated_set(struct clk_generated *gck, int status) { unsigned long flags; unsigned int enable = status ? AT91_PMC_PCR_GCKEN : 0; spin_lock_irqsave(gck->lock, flags); regmap_write(gck->regmap, gck->layout->offset, (gck->id & gck->layout->pid_mask)); regmap_update_bits(gck->regmap, gck->layout->offset, AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask | gck->layout->cmd | enable, field_prep(gck->layout->gckcss_mask, gck->parent_id) | gck->layout->cmd | FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) | enable); spin_unlock_irqrestore(gck->lock, flags); return 0; } static int clk_generated_enable(struct clk_hw *hw) { struct clk_generated *gck = to_clk_generated(hw); pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", __func__, gck->gckdiv, gck->parent_id); clk_generated_set(gck, 1); return 0; } static void clk_generated_disable(struct clk_hw *hw) { struct clk_generated *gck = to_clk_generated(hw); unsigned long flags; spin_lock_irqsave(gck->lock, flags); regmap_write(gck->regmap, gck->layout->offset, (gck->id & gck->layout->pid_mask)); regmap_update_bits(gck->regmap, gck->layout->offset, gck->layout->cmd | AT91_PMC_PCR_GCKEN, gck->layout->cmd); spin_unlock_irqrestore(gck->lock, flags); } static int clk_generated_is_enabled(struct clk_hw *hw) { struct clk_generated *gck = to_clk_generated(hw); unsigned long flags; unsigned int status; spin_lock_irqsave(gck->lock, flags); regmap_write(gck->regmap, gck->layout->offset, (gck->id & gck->layout->pid_mask)); regmap_read(gck->regmap, gck->layout->offset, &status); spin_unlock_irqrestore(gck->lock, flags); return !!(status & AT91_PMC_PCR_GCKEN); } static unsigned long clk_generated_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_generated *gck = to_clk_generated(hw); return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1); } static void clk_generated_best_diff(struct clk_rate_request *req, struct clk_hw *parent, unsigned long parent_rate, u32 div, int *best_diff, long *best_rate) { unsigned long tmp_rate; int tmp_diff; if (!div) tmp_rate = parent_rate; else tmp_rate = parent_rate / div; if (tmp_rate < req->min_rate || tmp_rate > req->max_rate) return; tmp_diff = abs(req->rate - tmp_rate); if (*best_diff < 0 || *best_diff >= tmp_diff) { *best_rate = tmp_rate; *best_diff = tmp_diff; req->best_parent_rate = parent_rate; req->best_parent_hw = parent; } } static int clk_generated_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct clk_generated *gck = to_clk_generated(hw); struct clk_hw *parent = NULL; long best_rate = -EINVAL; unsigned long min_rate, parent_rate; int best_diff = -1; int i; u32 div; /* do not look for a rate that is outside of our range */ if (gck->range.max && req->rate > gck->range.max) req->rate = gck->range.max; if (gck->range.min && req->rate < gck->range.min) req->rate = gck->range.min; for (i = 0; i < clk_hw_get_num_parents(hw); i++) { if (gck->chg_pid == i) continue; parent = clk_hw_get_parent_by_index(hw, i); if (!parent) continue; parent_rate = clk_hw_get_rate(parent); min_rate = DIV_ROUND_CLOSEST(parent_rate, GENERATED_MAX_DIV + 1); if (!parent_rate || (gck->range.max && min_rate > gck->range.max)) continue; div = DIV_ROUND_CLOSEST(parent_rate, req->rate); if (div > GENERATED_MAX_DIV + 1) div = GENERATED_MAX_DIV + 1; clk_generated_best_diff(req, parent, parent_rate, div, &best_diff, &best_rate); if (!best_diff) break; } /* * The audio_pll rate can be modified, unlike the five others clocks * that should never be altered. * The audio_pll can technically be used by multiple consumers. However, * with the rate locking, the first consumer to enable to clock will be * the one definitely setting the rate of the clock. * Since audio IPs are most likely to request the same rate, we enforce * that the only clks able to modify gck rate are those of audio IPs. */ if (gck->chg_pid < 0) goto end; parent = clk_hw_get_parent_by_index(hw, gck->chg_pid); if (!parent) goto end; for (div = 1; div < GENERATED_MAX_DIV + 2; div++) { struct clk_rate_request req_parent; clk_hw_forward_rate_request(hw, req, parent, &req_parent, req->rate * div); if (__clk_determine_rate(parent, &req_parent)) continue; clk_generated_best_diff(req, parent, req_parent.rate, div, &best_diff, &best_rate); if (!best_diff) break; } end: pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n", __func__, best_rate, __clk_get_name((req->best_parent_hw)->clk), req->best_parent_rate); if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max)) return -EINVAL; req->rate = best_rate; return 0; } /* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */ static int clk_generated_set_parent(struct clk_hw *hw, u8 index) { struct clk_generated *gck = to_clk_generated(hw); if (index >= clk_hw_get_num_parents(hw)) return -EINVAL; if (gck->mux_table) gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index); else gck->parent_id = index; return 0; } static u8 clk_generated_get_parent(struct clk_hw *hw) { struct clk_generated *gck = to_clk_generated(hw); return gck->parent_id; } /* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */ static int clk_generated_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_generated *gck = to_clk_generated(hw); u32 div; if (!rate) return -EINVAL; if (gck->range.max && rate > gck->range.max) return -EINVAL; div = DIV_ROUND_CLOSEST(parent_rate, rate); if (div > GENERATED_MAX_DIV + 1 || !div) return -EINVAL; gck->gckdiv = div - 1; return 0; } static int clk_generated_save_context(struct clk_hw *hw) { struct clk_generated *gck = to_clk_generated(hw); gck->pms.status = clk_generated_is_enabled(&gck->hw); return 0; } static void clk_generated_restore_context(struct clk_hw *hw) { struct clk_generated *gck = to_clk_generated(hw); if (gck->pms.status) clk_generated_set(gck, gck->pms.status); } static const struct clk_ops generated_ops = { .enable = clk_generated_enable, .disable = clk_generated_disable, .is_enabled = clk_generated_is_enabled, .recalc_rate = clk_generated_recalc_rate, .determine_rate = clk_generated_determine_rate, .get_parent = clk_generated_get_parent, .set_parent = clk_generated_set_parent, .set_rate = clk_generated_set_rate, .save_context = clk_generated_save_context, .restore_context = clk_generated_restore_context, }; /** * clk_generated_startup - Initialize a given clock to its default parent and * divisor parameter. * * @gck: Generated clock to set the startup parameters for. * * Take parameters from the hardware and update local clock configuration * accordingly. */ static void clk_generated_startup(struct clk_generated *gck) { u32 tmp; unsigned long flags; spin_lock_irqsave(gck->lock, flags); regmap_write(gck->regmap, gck->layout->offset, (gck->id & gck->layout->pid_mask)); regmap_read(gck->regmap, gck->layout->offset, &tmp); spin_unlock_irqrestore(gck->lock, flags); gck->parent_id = field_get(gck->layout->gckcss_mask, tmp); gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp); } struct clk_hw * __init at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, const struct clk_pcr_layout *layout, const char *name, const char **parent_names, struct clk_hw **parent_hws, u32 *mux_table, u8 num_parents, u8 id, const struct clk_range *range, int chg_pid) { struct clk_generated *gck; struct clk_init_data init = {}; struct clk_hw *hw; int ret; if (!(parent_names || parent_hws)) return ERR_PTR(-ENOMEM); gck = kzalloc(sizeof(*gck), GFP_KERNEL); if (!gck) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &generated_ops; if (parent_hws) init.parent_hws = (const struct clk_hw **)parent_hws; else init.parent_names = parent_names; init.num_parents = num_parents; init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; if (chg_pid >= 0) init.flags |= CLK_SET_RATE_PARENT; gck->id = id; gck->hw.init = &init; gck->regmap = regmap; gck->lock = lock; gck->range = *range; gck->chg_pid = chg_pid; gck->layout = layout; gck->mux_table = mux_table; clk_generated_startup(gck); hw = &gck->hw; ret = clk_hw_register(NULL, &gck->hw); if (ret) { kfree(gck); hw = ERR_PTR(ret); } return hw; }
linux-master
drivers/clk/at91/clk-generated.c
// SPDX-License-Identifier: GPL-2.0 #include <linux/clk-provider.h> #include <linux/mfd/syscon.h> #include <linux/slab.h> #include <dt-bindings/clock/at91.h> #include "pmc.h" static DEFINE_SPINLOCK(mck_lock); static const struct clk_master_characteristics mck_characteristics = { .output = { .min = 125000000, .max = 200000000 }, .divisors = { 1, 2, 4, 3 }, }; static u8 plla_out[] = { 0 }; static u16 plla_icpll[] = { 0 }; static const struct clk_range plla_outputs[] = { { .min = 600000000, .max = 1200000000 }, }; static const struct clk_pll_characteristics plla_characteristics = { .input = { .min = 12000000, .max = 12000000 }, .num_output = ARRAY_SIZE(plla_outputs), .output = plla_outputs, .icpll = plla_icpll, .out = plla_out, }; static const struct clk_pcr_layout sama5d4_pcr_layout = { .offset = 0x10c, .cmd = BIT(12), .pid_mask = GENMASK(6, 0), }; static const struct { char *n; char *p; unsigned long flags; u8 id; } sama5d4_systemck[] = { /* * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, { .n = "lcdck", .p = "masterck_div", .id = 3 }, { .n = "smdck", .p = "smdclk", .id = 4 }, { .n = "uhpck", .p = "usbck", .id = 6 }, { .n = "udpck", .p = "usbck", .id = 7 }, { .n = "pck0", .p = "prog0", .id = 8 }, { .n = "pck1", .p = "prog1", .id = 9 }, { .n = "pck2", .p = "prog2", .id = 10 }, }; static const struct { char *n; u8 id; } sama5d4_periph32ck[] = { { .n = "pioD_clk", .id = 5 }, { .n = "usart0_clk", .id = 6 }, { .n = "usart1_clk", .id = 7 }, { .n = "icm_clk", .id = 9 }, { .n = "aes_clk", .id = 12 }, { .n = "tdes_clk", .id = 14 }, { .n = "sha_clk", .id = 15 }, { .n = "matrix1_clk", .id = 17 }, { .n = "hsmc_clk", .id = 22 }, { .n = "pioA_clk", .id = 23 }, { .n = "pioB_clk", .id = 24 }, { .n = "pioC_clk", .id = 25 }, { .n = "pioE_clk", .id = 26 }, { .n = "uart0_clk", .id = 27 }, { .n = "uart1_clk", .id = 28 }, { .n = "usart2_clk", .id = 29 }, { .n = "usart3_clk", .id = 30 }, { .n = "usart4_clk", .id = 31 }, { .n = "twi0_clk", .id = 32 }, { .n = "twi1_clk", .id = 33 }, { .n = "twi2_clk", .id = 34 }, { .n = "mci0_clk", .id = 35 }, { .n = "mci1_clk", .id = 36 }, { .n = "spi0_clk", .id = 37 }, { .n = "spi1_clk", .id = 38 }, { .n = "spi2_clk", .id = 39 }, { .n = "tcb0_clk", .id = 40 }, { .n = "tcb1_clk", .id = 41 }, { .n = "tcb2_clk", .id = 42 }, { .n = "pwm_clk", .id = 43 }, { .n = "adc_clk", .id = 44 }, { .n = "dbgu_clk", .id = 45 }, { .n = "uhphs_clk", .id = 46 }, { .n = "udphs_clk", .id = 47 }, { .n = "ssc0_clk", .id = 48 }, { .n = "ssc1_clk", .id = 49 }, { .n = "trng_clk", .id = 53 }, { .n = "macb0_clk", .id = 54 }, { .n = "macb1_clk", .id = 55 }, { .n = "fuse_clk", .id = 57 }, { .n = "securam_clk", .id = 59 }, { .n = "smd_clk", .id = 61 }, { .n = "twi3_clk", .id = 62 }, { .n = "catb_clk", .id = 63 }, }; static const struct { char *n; unsigned long flags; u8 id; } sama5d4_periphck[] = { { .n = "dma0_clk", .id = 8 }, { .n = "cpkcc_clk", .id = 10 }, { .n = "aesb_clk", .id = 13 }, /* * mpddr_clk feeds DDR controller and is enabled by bootloader thus we * need to keep it enabled in case there is no Linux consumer for it. */ { .n = "mpddr_clk", .id = 16, .flags = CLK_IS_CRITICAL }, { .n = "matrix0_clk", .id = 18 }, { .n = "vdec_clk", .id = 19 }, { .n = "dma1_clk", .id = 50 }, { .n = "lcdc_clk", .id = 51 }, { .n = "isi_clk", .id = 52 }, }; static void __init sama5d4_pmc_setup(struct device_node *np) { struct clk_range range = CLK_RANGE(0, 0); const char *slck_name, *mainxtal_name; struct pmc_data *sama5d4_pmc; const char *parent_names[5]; struct regmap *regmap; struct clk_hw *hw; int i; bool bypass; i = of_property_match_string(np, "clock-names", "slow_clk"); if (i < 0) return; slck_name = of_clk_get_parent_name(np, i); i = of_property_match_string(np, "clock-names", "main_xtal"); if (i < 0) return; mainxtal_name = of_clk_get_parent_name(np, i); regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; sama5d4_pmc = pmc_data_allocate(PMC_PLLACK + 1, nck(sama5d4_systemck), nck(sama5d4_periph32ck), 0, 3); if (!sama5d4_pmc) return; hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 100000000); if (IS_ERR(hw)) goto err_free; bypass = of_property_read_bool(np, "atmel,osc-bypass"); hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, bypass); if (IS_ERR(hw)) goto err_free; parent_names[0] = "main_rc_osc"; parent_names[1] = "main_osc"; hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, &sama5d3_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); if (IS_ERR(hw)) goto err_free; sama5d4_pmc->chws[PMC_PLLACK] = hw; hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); if (IS_ERR(hw)) goto err_free; sama5d4_pmc->chws[PMC_UTMI] = hw; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, parent_names, NULL, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_master_div(regmap, "masterck_div", "masterck_pres", NULL, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; sama5d4_pmc->chws[PMC_MCK] = hw; hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div"); if (IS_ERR(hw)) goto err_free; sama5d4_pmc->chws[PMC_MCK2] = hw; parent_names[0] = "plladivck"; parent_names[1] = "utmick"; hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); if (IS_ERR(hw)) goto err_free; parent_names[0] = "plladivck"; parent_names[1] = "utmick"; hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2); if (IS_ERR(hw)) goto err_free; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; parent_names[4] = "masterck_div"; for (i = 0; i < 3; i++) { char name[6]; snprintf(name, sizeof(name), "prog%d", i); hw = at91_clk_register_programmable(regmap, name, parent_names, NULL, 5, i, &at91sam9x5_programmable_layout, NULL); if (IS_ERR(hw)) goto err_free; sama5d4_pmc->pchws[i] = hw; } for (i = 0; i < ARRAY_SIZE(sama5d4_systemck); i++) { hw = at91_clk_register_system(regmap, sama5d4_systemck[i].n, sama5d4_systemck[i].p, NULL, sama5d4_systemck[i].id, sama5d4_systemck[i].flags); if (IS_ERR(hw)) goto err_free; sama5d4_pmc->shws[sama5d4_systemck[i].id] = hw; } for (i = 0; i < ARRAY_SIZE(sama5d4_periphck); i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d4_pcr_layout, sama5d4_periphck[i].n, "masterck_div", NULL, sama5d4_periphck[i].id, &range, INT_MIN, sama5d4_periphck[i].flags); if (IS_ERR(hw)) goto err_free; sama5d4_pmc->phws[sama5d4_periphck[i].id] = hw; } for (i = 0; i < ARRAY_SIZE(sama5d4_periph32ck); i++) { hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d4_pcr_layout, sama5d4_periph32ck[i].n, "h32mxck", NULL, sama5d4_periph32ck[i].id, &range, INT_MIN, 0); if (IS_ERR(hw)) goto err_free; sama5d4_pmc->phws[sama5d4_periph32ck[i].id] = hw; } of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d4_pmc); return; err_free: kfree(sama5d4_pmc); } CLK_OF_DECLARE(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup);
linux-master
drivers/clk/at91/sama5d4.c
// SPDX-License-Identifier: GPL-2.0 #include <linux/clk-provider.h> #include <linux/mfd/syscon.h> #include <linux/slab.h> #include <dt-bindings/clock/at91.h> #include "pmc.h" struct sck { char *n; char *p; u8 id; }; struct pck { char *n; u8 id; }; struct at91sam926x_data { const struct clk_pll_layout *plla_layout; const struct clk_pll_characteristics *plla_characteristics; const struct clk_pll_layout *pllb_layout; const struct clk_pll_characteristics *pllb_characteristics; const struct clk_master_characteristics *mck_characteristics; const struct sck *sck; const struct pck *pck; u8 num_sck; u8 num_pck; u8 num_progck; bool has_slck; }; static DEFINE_SPINLOCK(at91sam9260_mck_lock); static const struct clk_master_characteristics sam9260_mck_characteristics = { .output = { .min = 0, .max = 105000000 }, .divisors = { 1, 2, 4, 0 }, }; static u8 sam9260_plla_out[] = { 0, 2 }; static u16 sam9260_plla_icpll[] = { 1, 1 }; static const struct clk_range sam9260_plla_outputs[] = { { .min = 80000000, .max = 160000000 }, { .min = 150000000, .max = 240000000 }, }; static const struct clk_pll_characteristics sam9260_plla_characteristics = { .input = { .min = 1000000, .max = 32000000 }, .num_output = ARRAY_SIZE(sam9260_plla_outputs), .output = sam9260_plla_outputs, .icpll = sam9260_plla_icpll, .out = sam9260_plla_out, }; static u8 sam9260_pllb_out[] = { 1 }; static u16 sam9260_pllb_icpll[] = { 1 }; static const struct clk_range sam9260_pllb_outputs[] = { { .min = 70000000, .max = 130000000 }, }; static const struct clk_pll_characteristics sam9260_pllb_characteristics = { .input = { .min = 1000000, .max = 5000000 }, .num_output = ARRAY_SIZE(sam9260_pllb_outputs), .output = sam9260_pllb_outputs, .icpll = sam9260_pllb_icpll, .out = sam9260_pllb_out, }; static const struct sck at91sam9260_systemck[] = { { .n = "uhpck", .p = "usbck", .id = 6 }, { .n = "udpck", .p = "usbck", .id = 7 }, { .n = "pck0", .p = "prog0", .id = 8 }, { .n = "pck1", .p = "prog1", .id = 9 }, }; static const struct pck at91sam9260_periphck[] = { { .n = "pioA_clk", .id = 2 }, { .n = "pioB_clk", .id = 3 }, { .n = "pioC_clk", .id = 4 }, { .n = "adc_clk", .id = 5 }, { .n = "usart0_clk", .id = 6 }, { .n = "usart1_clk", .id = 7 }, { .n = "usart2_clk", .id = 8 }, { .n = "mci0_clk", .id = 9 }, { .n = "udc_clk", .id = 10 }, { .n = "twi0_clk", .id = 11 }, { .n = "spi0_clk", .id = 12 }, { .n = "spi1_clk", .id = 13 }, { .n = "ssc0_clk", .id = 14 }, { .n = "tc0_clk", .id = 17 }, { .n = "tc1_clk", .id = 18 }, { .n = "tc2_clk", .id = 19 }, { .n = "ohci_clk", .id = 20 }, { .n = "macb0_clk", .id = 21 }, { .n = "isi_clk", .id = 22 }, { .n = "usart3_clk", .id = 23 }, { .n = "uart0_clk", .id = 24 }, { .n = "uart1_clk", .id = 25 }, { .n = "tc3_clk", .id = 26 }, { .n = "tc4_clk", .id = 27 }, { .n = "tc5_clk", .id = 28 }, }; static struct at91sam926x_data at91sam9260_data = { .plla_layout = &at91rm9200_pll_layout, .plla_characteristics = &sam9260_plla_characteristics, .pllb_layout = &at91rm9200_pll_layout, .pllb_characteristics = &sam9260_pllb_characteristics, .mck_characteristics = &sam9260_mck_characteristics, .sck = at91sam9260_systemck, .num_sck = ARRAY_SIZE(at91sam9260_systemck), .pck = at91sam9260_periphck, .num_pck = ARRAY_SIZE(at91sam9260_periphck), .num_progck = 2, .has_slck = true, }; static const struct clk_master_characteristics sam9g20_mck_characteristics = { .output = { .min = 0, .max = 133000000 }, .divisors = { 1, 2, 4, 6 }, }; static u8 sam9g20_plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 }; static u16 sam9g20_plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 }; static const struct clk_range sam9g20_plla_outputs[] = { { .min = 745000000, .max = 800000000 }, { .min = 695000000, .max = 750000000 }, { .min = 645000000, .max = 700000000 }, { .min = 595000000, .max = 650000000 }, { .min = 545000000, .max = 600000000 }, { .min = 495000000, .max = 550000000 }, { .min = 445000000, .max = 500000000 }, { .min = 400000000, .max = 450000000 }, }; static const struct clk_pll_characteristics sam9g20_plla_characteristics = { .input = { .min = 2000000, .max = 32000000 }, .num_output = ARRAY_SIZE(sam9g20_plla_outputs), .output = sam9g20_plla_outputs, .icpll = sam9g20_plla_icpll, .out = sam9g20_plla_out, }; static u8 sam9g20_pllb_out[] = { 0 }; static u16 sam9g20_pllb_icpll[] = { 0 }; static const struct clk_range sam9g20_pllb_outputs[] = { { .min = 30000000, .max = 100000000 }, }; static const struct clk_pll_characteristics sam9g20_pllb_characteristics = { .input = { .min = 2000000, .max = 32000000 }, .num_output = ARRAY_SIZE(sam9g20_pllb_outputs), .output = sam9g20_pllb_outputs, .icpll = sam9g20_pllb_icpll, .out = sam9g20_pllb_out, }; static struct at91sam926x_data at91sam9g20_data = { .plla_layout = &at91sam9g45_pll_layout, .plla_characteristics = &sam9g20_plla_characteristics, .pllb_layout = &at91sam9g20_pllb_layout, .pllb_characteristics = &sam9g20_pllb_characteristics, .mck_characteristics = &sam9g20_mck_characteristics, .sck = at91sam9260_systemck, .num_sck = ARRAY_SIZE(at91sam9260_systemck), .pck = at91sam9260_periphck, .num_pck = ARRAY_SIZE(at91sam9260_periphck), .num_progck = 2, .has_slck = true, }; static const struct clk_master_characteristics sam9261_mck_characteristics = { .output = { .min = 0, .max = 94000000 }, .divisors = { 1, 2, 4, 0 }, }; static const struct clk_range sam9261_plla_outputs[] = { { .min = 80000000, .max = 200000000 }, { .min = 190000000, .max = 240000000 }, }; static const struct clk_pll_characteristics sam9261_plla_characteristics = { .input = { .min = 1000000, .max = 32000000 }, .num_output = ARRAY_SIZE(sam9261_plla_outputs), .output = sam9261_plla_outputs, .icpll = sam9260_plla_icpll, .out = sam9260_plla_out, }; static u8 sam9261_pllb_out[] = { 1 }; static u16 sam9261_pllb_icpll[] = { 1 }; static const struct clk_range sam9261_pllb_outputs[] = { { .min = 70000000, .max = 130000000 }, }; static const struct clk_pll_characteristics sam9261_pllb_characteristics = { .input = { .min = 1000000, .max = 5000000 }, .num_output = ARRAY_SIZE(sam9261_pllb_outputs), .output = sam9261_pllb_outputs, .icpll = sam9261_pllb_icpll, .out = sam9261_pllb_out, }; static const struct sck at91sam9261_systemck[] = { { .n = "uhpck", .p = "usbck", .id = 6 }, { .n = "udpck", .p = "usbck", .id = 7 }, { .n = "pck0", .p = "prog0", .id = 8 }, { .n = "pck1", .p = "prog1", .id = 9 }, { .n = "pck2", .p = "prog2", .id = 10 }, { .n = "pck3", .p = "prog3", .id = 11 }, { .n = "hclk0", .p = "masterck_div", .id = 16 }, { .n = "hclk1", .p = "masterck_div", .id = 17 }, }; static const struct pck at91sam9261_periphck[] = { { .n = "pioA_clk", .id = 2, }, { .n = "pioB_clk", .id = 3, }, { .n = "pioC_clk", .id = 4, }, { .n = "usart0_clk", .id = 6, }, { .n = "usart1_clk", .id = 7, }, { .n = "usart2_clk", .id = 8, }, { .n = "mci0_clk", .id = 9, }, { .n = "udc_clk", .id = 10, }, { .n = "twi0_clk", .id = 11, }, { .n = "spi0_clk", .id = 12, }, { .n = "spi1_clk", .id = 13, }, { .n = "ssc0_clk", .id = 14, }, { .n = "ssc1_clk", .id = 15, }, { .n = "ssc2_clk", .id = 16, }, { .n = "tc0_clk", .id = 17, }, { .n = "tc1_clk", .id = 18, }, { .n = "tc2_clk", .id = 19, }, { .n = "ohci_clk", .id = 20, }, { .n = "lcd_clk", .id = 21, }, }; static struct at91sam926x_data at91sam9261_data = { .plla_layout = &at91rm9200_pll_layout, .plla_characteristics = &sam9261_plla_characteristics, .pllb_layout = &at91rm9200_pll_layout, .pllb_characteristics = &sam9261_pllb_characteristics, .mck_characteristics = &sam9261_mck_characteristics, .sck = at91sam9261_systemck, .num_sck = ARRAY_SIZE(at91sam9261_systemck), .pck = at91sam9261_periphck, .num_pck = ARRAY_SIZE(at91sam9261_periphck), .num_progck = 4, }; static const struct clk_master_characteristics sam9263_mck_characteristics = { .output = { .min = 0, .max = 120000000 }, .divisors = { 1, 2, 4, 0 }, }; static const struct clk_range sam9263_pll_outputs[] = { { .min = 80000000, .max = 200000000 }, { .min = 190000000, .max = 240000000 }, }; static const struct clk_pll_characteristics sam9263_pll_characteristics = { .input = { .min = 1000000, .max = 32000000 }, .num_output = ARRAY_SIZE(sam9263_pll_outputs), .output = sam9263_pll_outputs, .icpll = sam9260_plla_icpll, .out = sam9260_plla_out, }; static const struct sck at91sam9263_systemck[] = { { .n = "uhpck", .p = "usbck", .id = 6 }, { .n = "udpck", .p = "usbck", .id = 7 }, { .n = "pck0", .p = "prog0", .id = 8 }, { .n = "pck1", .p = "prog1", .id = 9 }, { .n = "pck2", .p = "prog2", .id = 10 }, { .n = "pck3", .p = "prog3", .id = 11 }, }; static const struct pck at91sam9263_periphck[] = { { .n = "pioA_clk", .id = 2, }, { .n = "pioB_clk", .id = 3, }, { .n = "pioCDE_clk", .id = 4, }, { .n = "usart0_clk", .id = 7, }, { .n = "usart1_clk", .id = 8, }, { .n = "usart2_clk", .id = 9, }, { .n = "mci0_clk", .id = 10, }, { .n = "mci1_clk", .id = 11, }, { .n = "can_clk", .id = 12, }, { .n = "twi0_clk", .id = 13, }, { .n = "spi0_clk", .id = 14, }, { .n = "spi1_clk", .id = 15, }, { .n = "ssc0_clk", .id = 16, }, { .n = "ssc1_clk", .id = 17, }, { .n = "ac97_clk", .id = 18, }, { .n = "tcb_clk", .id = 19, }, { .n = "pwm_clk", .id = 20, }, { .n = "macb0_clk", .id = 21, }, { .n = "g2de_clk", .id = 23, }, { .n = "udc_clk", .id = 24, }, { .n = "isi_clk", .id = 25, }, { .n = "lcd_clk", .id = 26, }, { .n = "dma_clk", .id = 27, }, { .n = "ohci_clk", .id = 29, }, }; static struct at91sam926x_data at91sam9263_data = { .plla_layout = &at91rm9200_pll_layout, .plla_characteristics = &sam9263_pll_characteristics, .pllb_layout = &at91rm9200_pll_layout, .pllb_characteristics = &sam9263_pll_characteristics, .mck_characteristics = &sam9263_mck_characteristics, .sck = at91sam9263_systemck, .num_sck = ARRAY_SIZE(at91sam9263_systemck), .pck = at91sam9263_periphck, .num_pck = ARRAY_SIZE(at91sam9263_periphck), .num_progck = 4, }; static void __init at91sam926x_pmc_setup(struct device_node *np, struct at91sam926x_data *data) { const char *slowxtal_name, *mainxtal_name; struct pmc_data *at91sam9260_pmc; u32 usb_div[] = { 1, 2, 4, 0 }; const char *parent_names[6]; const char *slck_name; struct regmap *regmap; struct clk_hw *hw; int i; bool bypass; i = of_property_match_string(np, "clock-names", "slow_xtal"); if (i < 0) return; slowxtal_name = of_clk_get_parent_name(np, i); i = of_property_match_string(np, "clock-names", "main_xtal"); if (i < 0) return; mainxtal_name = of_clk_get_parent_name(np, i); regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; at91sam9260_pmc = pmc_data_allocate(PMC_PLLBCK + 1, ndck(data->sck, data->num_sck), ndck(data->pck, data->num_pck), 0, data->num_progck); if (!at91sam9260_pmc) return; bypass = of_property_read_bool(np, "atmel,osc-bypass"); hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, bypass); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL); if (IS_ERR(hw)) goto err_free; at91sam9260_pmc->chws[PMC_MAIN] = hw; if (data->has_slck) { hw = clk_hw_register_fixed_rate_with_accuracy(NULL, "slow_rc_osc", NULL, 0, 32768, 50000000); if (IS_ERR(hw)) goto err_free; parent_names[0] = "slow_rc_osc"; parent_names[1] = "slow_xtal"; hw = at91_clk_register_sam9260_slow(regmap, "slck", parent_names, 2); if (IS_ERR(hw)) goto err_free; at91sam9260_pmc->chws[PMC_SLOW] = hw; slck_name = "slck"; } else { slck_name = slowxtal_name; } hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, data->plla_layout, data->plla_characteristics); if (IS_ERR(hw)) goto err_free; at91sam9260_pmc->chws[PMC_PLLACK] = hw; hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1, data->pllb_layout, data->pllb_characteristics); if (IS_ERR(hw)) goto err_free; at91sam9260_pmc->chws[PMC_PLLBCK] = hw; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "pllack"; parent_names[3] = "pllbck"; hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, parent_names, NULL, &at91rm9200_master_layout, data->mck_characteristics, &at91sam9260_mck_lock); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_master_div(regmap, "masterck_div", "masterck_pres", NULL, &at91rm9200_master_layout, data->mck_characteristics, &at91sam9260_mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; at91sam9260_pmc->chws[PMC_MCK] = hw; hw = at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div); if (IS_ERR(hw)) goto err_free; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "pllack"; parent_names[3] = "pllbck"; for (i = 0; i < data->num_progck; i++) { char name[6]; snprintf(name, sizeof(name), "prog%d", i); hw = at91_clk_register_programmable(regmap, name, parent_names, NULL, 4, i, &at91rm9200_programmable_layout, NULL); if (IS_ERR(hw)) goto err_free; at91sam9260_pmc->pchws[i] = hw; } for (i = 0; i < data->num_sck; i++) { hw = at91_clk_register_system(regmap, data->sck[i].n, data->sck[i].p, NULL, data->sck[i].id, 0); if (IS_ERR(hw)) goto err_free; at91sam9260_pmc->shws[data->sck[i].id] = hw; } for (i = 0; i < data->num_pck; i++) { hw = at91_clk_register_peripheral(regmap, data->pck[i].n, "masterck_div", NULL, data->pck[i].id); if (IS_ERR(hw)) goto err_free; at91sam9260_pmc->phws[data->pck[i].id] = hw; } of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9260_pmc); return; err_free: kfree(at91sam9260_pmc); } static void __init at91sam9260_pmc_setup(struct device_node *np) { at91sam926x_pmc_setup(np, &at91sam9260_data); } CLK_OF_DECLARE(at91sam9260_pmc, "atmel,at91sam9260-pmc", at91sam9260_pmc_setup); static void __init at91sam9261_pmc_setup(struct device_node *np) { at91sam926x_pmc_setup(np, &at91sam9261_data); } CLK_OF_DECLARE(at91sam9261_pmc, "atmel,at91sam9261-pmc", at91sam9261_pmc_setup); static void __init at91sam9263_pmc_setup(struct device_node *np) { at91sam926x_pmc_setup(np, &at91sam9263_data); } CLK_OF_DECLARE(at91sam9263_pmc, "atmel,at91sam9263-pmc", at91sam9263_pmc_setup); static void __init at91sam9g20_pmc_setup(struct device_node *np) { at91sam926x_pmc_setup(np, &at91sam9g20_data); } CLK_OF_DECLARE(at91sam9g20_pmc, "atmel,at91sam9g20-pmc", at91sam9g20_pmc_setup);
linux-master
drivers/clk/at91/at91sam9260.c
// SPDX-License-Identifier: GPL-2.0 #include <linux/clk-provider.h> #include <linux/mfd/syscon.h> #include <linux/slab.h> #include <dt-bindings/clock/at91.h> #include "pmc.h" static DEFINE_SPINLOCK(rm9200_mck_lock); struct sck { char *n; char *p; u8 id; }; struct pck { char *n; u8 id; }; static const struct clk_master_characteristics rm9200_mck_characteristics = { .output = { .min = 0, .max = 80000000 }, .divisors = { 1, 2, 3, 4 }, }; static u8 rm9200_pll_out[] = { 0, 2 }; static const struct clk_range rm9200_pll_outputs[] = { { .min = 80000000, .max = 160000000 }, { .min = 150000000, .max = 180000000 }, }; static const struct clk_pll_characteristics rm9200_pll_characteristics = { .input = { .min = 1000000, .max = 32000000 }, .num_output = ARRAY_SIZE(rm9200_pll_outputs), .output = rm9200_pll_outputs, .out = rm9200_pll_out, }; static const struct sck at91rm9200_systemck[] = { { .n = "udpck", .p = "usbck", .id = 1 }, { .n = "uhpck", .p = "usbck", .id = 4 }, { .n = "pck0", .p = "prog0", .id = 8 }, { .n = "pck1", .p = "prog1", .id = 9 }, { .n = "pck2", .p = "prog2", .id = 10 }, { .n = "pck3", .p = "prog3", .id = 11 }, }; static const struct pck at91rm9200_periphck[] = { { .n = "pioA_clk", .id = 2 }, { .n = "pioB_clk", .id = 3 }, { .n = "pioC_clk", .id = 4 }, { .n = "pioD_clk", .id = 5 }, { .n = "usart0_clk", .id = 6 }, { .n = "usart1_clk", .id = 7 }, { .n = "usart2_clk", .id = 8 }, { .n = "usart3_clk", .id = 9 }, { .n = "mci0_clk", .id = 10 }, { .n = "udc_clk", .id = 11 }, { .n = "twi0_clk", .id = 12 }, { .n = "spi0_clk", .id = 13 }, { .n = "ssc0_clk", .id = 14 }, { .n = "ssc1_clk", .id = 15 }, { .n = "ssc2_clk", .id = 16 }, { .n = "tc0_clk", .id = 17 }, { .n = "tc1_clk", .id = 18 }, { .n = "tc2_clk", .id = 19 }, { .n = "tc3_clk", .id = 20 }, { .n = "tc4_clk", .id = 21 }, { .n = "tc5_clk", .id = 22 }, { .n = "ohci_clk", .id = 23 }, { .n = "macb0_clk", .id = 24 }, }; static void __init at91rm9200_pmc_setup(struct device_node *np) { const char *slowxtal_name, *mainxtal_name; struct pmc_data *at91rm9200_pmc; u32 usb_div[] = { 1, 2, 0, 0 }; const char *parent_names[6]; struct regmap *regmap; struct clk_hw *hw; int i; bool bypass; i = of_property_match_string(np, "clock-names", "slow_xtal"); if (i < 0) return; slowxtal_name = of_clk_get_parent_name(np, i); i = of_property_match_string(np, "clock-names", "main_xtal"); if (i < 0) return; mainxtal_name = of_clk_get_parent_name(np, i); regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; at91rm9200_pmc = pmc_data_allocate(PMC_PLLBCK + 1, nck(at91rm9200_systemck), nck(at91rm9200_periphck), 0, 4); if (!at91rm9200_pmc) return; bypass = of_property_read_bool(np, "atmel,osc-bypass"); hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, bypass); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL); if (IS_ERR(hw)) goto err_free; at91rm9200_pmc->chws[PMC_MAIN] = hw; hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, &at91rm9200_pll_layout, &rm9200_pll_characteristics); if (IS_ERR(hw)) goto err_free; at91rm9200_pmc->chws[PMC_PLLACK] = hw; hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1, &at91rm9200_pll_layout, &rm9200_pll_characteristics); if (IS_ERR(hw)) goto err_free; at91rm9200_pmc->chws[PMC_PLLBCK] = hw; parent_names[0] = slowxtal_name; parent_names[1] = "mainck"; parent_names[2] = "pllack"; parent_names[3] = "pllbck"; hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, parent_names, NULL, &at91rm9200_master_layout, &rm9200_mck_characteristics, &rm9200_mck_lock); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_master_div(regmap, "masterck_div", "masterck_pres", NULL, &at91rm9200_master_layout, &rm9200_mck_characteristics, &rm9200_mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; at91rm9200_pmc->chws[PMC_MCK] = hw; hw = at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div); if (IS_ERR(hw)) goto err_free; parent_names[0] = slowxtal_name; parent_names[1] = "mainck"; parent_names[2] = "pllack"; parent_names[3] = "pllbck"; for (i = 0; i < 4; i++) { char name[6]; snprintf(name, sizeof(name), "prog%d", i); hw = at91_clk_register_programmable(regmap, name, parent_names, NULL, 4, i, &at91rm9200_programmable_layout, NULL); if (IS_ERR(hw)) goto err_free; at91rm9200_pmc->pchws[i] = hw; } for (i = 0; i < ARRAY_SIZE(at91rm9200_systemck); i++) { hw = at91_clk_register_system(regmap, at91rm9200_systemck[i].n, at91rm9200_systemck[i].p, NULL, at91rm9200_systemck[i].id, 0); if (IS_ERR(hw)) goto err_free; at91rm9200_pmc->shws[at91rm9200_systemck[i].id] = hw; } for (i = 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) { hw = at91_clk_register_peripheral(regmap, at91rm9200_periphck[i].n, "masterck_div", NULL, at91rm9200_periphck[i].id); if (IS_ERR(hw)) goto err_free; at91rm9200_pmc->phws[at91rm9200_periphck[i].id] = hw; } of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91rm9200_pmc); return; err_free: kfree(at91rm9200_pmc); } /* * While the TCB can be used as the clocksource, the system timer is most likely * to be used instead. However, the pinctrl driver doesn't support probe * deferring properly. Once this is fixed, this can be switched to a platform * driver. */ CLK_OF_DECLARE(at91rm9200_pmc, "atmel,at91rm9200-pmc", at91rm9200_pmc_setup);
linux-master
drivers/clk/at91/at91rm9200.c
// SPDX-License-Identifier: GPL-2.0 #include <linux/clk-provider.h> #include <linux/mfd/syscon.h> #include <linux/slab.h> #include <dt-bindings/clock/at91.h> #include "pmc.h" static DEFINE_SPINLOCK(at91sam9g45_mck_lock); static const struct clk_master_characteristics mck_characteristics = { .output = { .min = 0, .max = 133333333 }, .divisors = { 1, 2, 4, 3 }, }; static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 }; static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 }; static const struct clk_range plla_outputs[] = { { .min = 745000000, .max = 800000000 }, { .min = 695000000, .max = 750000000 }, { .min = 645000000, .max = 700000000 }, { .min = 595000000, .max = 650000000 }, { .min = 545000000, .max = 600000000 }, { .min = 495000000, .max = 555000000 }, { .min = 445000000, .max = 500000000 }, { .min = 400000000, .max = 450000000 }, }; static const struct clk_pll_characteristics plla_characteristics = { .input = { .min = 2000000, .max = 32000000 }, .num_output = ARRAY_SIZE(plla_outputs), .output = plla_outputs, .icpll = plla_icpll, .out = plla_out, }; static const struct { char *n; char *p; unsigned long flags; u8 id; } at91sam9g45_systemck[] = { /* * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, { .n = "uhpck", .p = "usbck", .id = 6 }, { .n = "pck0", .p = "prog0", .id = 8 }, { .n = "pck1", .p = "prog1", .id = 9 }, }; struct pck { char *n; u8 id; }; static const struct pck at91sam9g45_periphck[] = { { .n = "pioA_clk", .id = 2, }, { .n = "pioB_clk", .id = 3, }, { .n = "pioC_clk", .id = 4, }, { .n = "pioDE_clk", .id = 5, }, { .n = "trng_clk", .id = 6, }, { .n = "usart0_clk", .id = 7, }, { .n = "usart1_clk", .id = 8, }, { .n = "usart2_clk", .id = 9, }, { .n = "usart3_clk", .id = 10, }, { .n = "mci0_clk", .id = 11, }, { .n = "twi0_clk", .id = 12, }, { .n = "twi1_clk", .id = 13, }, { .n = "spi0_clk", .id = 14, }, { .n = "spi1_clk", .id = 15, }, { .n = "ssc0_clk", .id = 16, }, { .n = "ssc1_clk", .id = 17, }, { .n = "tcb0_clk", .id = 18, }, { .n = "pwm_clk", .id = 19, }, { .n = "adc_clk", .id = 20, }, { .n = "dma0_clk", .id = 21, }, { .n = "uhphs_clk", .id = 22, }, { .n = "lcd_clk", .id = 23, }, { .n = "ac97_clk", .id = 24, }, { .n = "macb0_clk", .id = 25, }, { .n = "isi_clk", .id = 26, }, { .n = "udphs_clk", .id = 27, }, { .n = "aestdessha_clk", .id = 28, }, { .n = "mci1_clk", .id = 29, }, { .n = "vdec_clk", .id = 30, }, }; static void __init at91sam9g45_pmc_setup(struct device_node *np) { const char *slck_name, *mainxtal_name; struct pmc_data *at91sam9g45_pmc; const char *parent_names[6]; struct regmap *regmap; struct clk_hw *hw; int i; bool bypass; i = of_property_match_string(np, "clock-names", "slow_clk"); if (i < 0) return; slck_name = of_clk_get_parent_name(np, i); i = of_property_match_string(np, "clock-names", "main_xtal"); if (i < 0) return; mainxtal_name = of_clk_get_parent_name(np, i); regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) return; at91sam9g45_pmc = pmc_data_allocate(PMC_PLLACK + 1, nck(at91sam9g45_systemck), nck(at91sam9g45_periphck), 0, 2); if (!at91sam9g45_pmc) return; bypass = of_property_read_bool(np, "atmel,osc-bypass"); hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, bypass); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL); if (IS_ERR(hw)) goto err_free; at91sam9g45_pmc->chws[PMC_MAIN] = hw; hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, &at91rm9200_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); if (IS_ERR(hw)) goto err_free; at91sam9g45_pmc->chws[PMC_PLLACK] = hw; hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); if (IS_ERR(hw)) goto err_free; at91sam9g45_pmc->chws[PMC_UTMI] = hw; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, parent_names, NULL, &at91rm9200_master_layout, &mck_characteristics, &at91sam9g45_mck_lock); if (IS_ERR(hw)) goto err_free; hw = at91_clk_register_master_div(regmap, "masterck_div", "masterck_pres", NULL, &at91rm9200_master_layout, &mck_characteristics, &at91sam9g45_mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; at91sam9g45_pmc->chws[PMC_MCK] = hw; parent_names[0] = "plladivck"; parent_names[1] = "utmick"; hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); if (IS_ERR(hw)) goto err_free; parent_names[0] = slck_name; parent_names[1] = "mainck"; parent_names[2] = "plladivck"; parent_names[3] = "utmick"; parent_names[4] = "masterck_div"; for (i = 0; i < 2; i++) { char name[6]; snprintf(name, sizeof(name), "prog%d", i); hw = at91_clk_register_programmable(regmap, name, parent_names, NULL, 5, i, &at91sam9g45_programmable_layout, NULL); if (IS_ERR(hw)) goto err_free; at91sam9g45_pmc->pchws[i] = hw; } for (i = 0; i < ARRAY_SIZE(at91sam9g45_systemck); i++) { hw = at91_clk_register_system(regmap, at91sam9g45_systemck[i].n, at91sam9g45_systemck[i].p, NULL, at91sam9g45_systemck[i].id, at91sam9g45_systemck[i].flags); if (IS_ERR(hw)) goto err_free; at91sam9g45_pmc->shws[at91sam9g45_systemck[i].id] = hw; } for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) { hw = at91_clk_register_peripheral(regmap, at91sam9g45_periphck[i].n, "masterck_div", NULL, at91sam9g45_periphck[i].id); if (IS_ERR(hw)) goto err_free; at91sam9g45_pmc->phws[at91sam9g45_periphck[i].id] = hw; } of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9g45_pmc); return; err_free: kfree(at91sam9g45_pmc); } /* * The TCB is used as the clocksource so its clock is needed early. This means * this can't be a platform driver. */ CLK_OF_DECLARE(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", at91sam9g45_pmc_setup);
linux-master
drivers/clk/at91/at91sam9g45.c
// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2013 Boris BREZILLON <[email protected]> */ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/clk/at91_pmc.h> #include <linux/of.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "pmc.h" #define SYSTEM_MAX_ID 31 #define SYSTEM_MAX_NAME_SZ 32 #define to_clk_system(hw) container_of(hw, struct clk_system, hw) struct clk_system { struct clk_hw hw; struct regmap *regmap; struct at91_clk_pms pms; u8 id; }; static inline int is_pck(int id) { return (id >= 8) && (id <= 15); } static inline bool clk_system_ready(struct regmap *regmap, int id) { unsigned int status; regmap_read(regmap, AT91_PMC_SR, &status); return !!(status & (1 << id)); } static int clk_system_prepare(struct clk_hw *hw) { struct clk_system *sys = to_clk_system(hw); regmap_write(sys->regmap, AT91_PMC_SCER, 1 << sys->id); if (!is_pck(sys->id)) return 0; while (!clk_system_ready(sys->regmap, sys->id)) cpu_relax(); return 0; } static void clk_system_unprepare(struct clk_hw *hw) { struct clk_system *sys = to_clk_system(hw); regmap_write(sys->regmap, AT91_PMC_SCDR, 1 << sys->id); } static int clk_system_is_prepared(struct clk_hw *hw) { struct clk_system *sys = to_clk_system(hw); unsigned int status; regmap_read(sys->regmap, AT91_PMC_SCSR, &status); if (!(status & (1 << sys->id))) return 0; if (!is_pck(sys->id)) return 1; regmap_read(sys->regmap, AT91_PMC_SR, &status); return !!(status & (1 << sys->id)); } static int clk_system_save_context(struct clk_hw *hw) { struct clk_system *sys = to_clk_system(hw); sys->pms.status = clk_system_is_prepared(hw); return 0; } static void clk_system_restore_context(struct clk_hw *hw) { struct clk_system *sys = to_clk_system(hw); if (sys->pms.status) clk_system_prepare(&sys->hw); } static const struct clk_ops system_ops = { .prepare = clk_system_prepare, .unprepare = clk_system_unprepare, .is_prepared = clk_system_is_prepared, .save_context = clk_system_save_context, .restore_context = clk_system_restore_context, }; struct clk_hw * __init at91_clk_register_system(struct regmap *regmap, const char *name, const char *parent_name, struct clk_hw *parent_hw, u8 id, unsigned long flags) { struct clk_system *sys; struct clk_hw *hw; struct clk_init_data init = {}; int ret; if (!(parent_name || parent_hw) || id > SYSTEM_MAX_ID) return ERR_PTR(-EINVAL); sys = kzalloc(sizeof(*sys), GFP_KERNEL); if (!sys) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &system_ops; if (parent_hw) init.parent_hws = (const struct clk_hw **)&parent_hw; else init.parent_names = &parent_name; init.num_parents = 1; init.flags = CLK_SET_RATE_PARENT | flags; sys->id = id; sys->hw.init = &init; sys->regmap = regmap; hw = &sys->hw; ret = clk_hw_register(NULL, &sys->hw); if (ret) { kfree(sys); hw = ERR_PTR(ret); } return hw; }
linux-master
drivers/clk/at91/clk-system.c
// SPDX-License-Identifier: GPL-2.0 /* * r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software * Reset * * Copyright (C) 2016-2019 Glider bvba * Copyright (C) 2018-2019 Renesas Electronics Corp. * * Based on r8a7795-cpg-mssr.c * * Copyright (C) 2015 Glider bvba * Copyright (C) 2015 Renesas Electronics Corp. */ #include <linux/device.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/soc/renesas/rcar-rst.h> #include <dt-bindings/clock/r8a7796-cpg-mssr.h> #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A7796_CLK_OSC, /* External Input Clocks */ CLK_EXTAL, CLK_EXTALR, /* Internal Core Clocks */ CLK_MAIN, CLK_PLL0, CLK_PLL1, CLK_PLL2, CLK_PLL3, CLK_PLL4, CLK_PLL1_DIV2, CLK_PLL1_DIV4, CLK_S0, CLK_S1, CLK_S2, CLK_S3, CLK_SDSRC, CLK_SSPSRC, CLK_RPCSRC, CLK_RINT, /* Module Clocks */ MOD_CLK_BASE }; static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("extalr", CLK_EXTALR), /* Internal Core Clocks */ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), DEF_GEN3_Z("zg", R8A7796_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24), DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1), DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1), DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1), DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1), DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1), DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1), DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1), DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1), DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1), DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1), DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1), DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1), DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1), DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1), DEF_GEN3_SDH("sd0h", R8A7796_CLK_SD0H, CLK_SDSRC, 0x074), DEF_GEN3_SDH("sd1h", R8A7796_CLK_SD1H, CLK_SDSRC, 0x078), DEF_GEN3_SDH("sd2h", R8A7796_CLK_SD2H, CLK_SDSRC, 0x268), DEF_GEN3_SDH("sd3h", R8A7796_CLK_SD3H, CLK_SDSRC, 0x26c), DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, R8A7796_CLK_SD0H, 0x074), DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, R8A7796_CLK_SD1H, 0x078), DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268), DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c), DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7796_CLK_RPC), DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1), DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A7796_CLK_CPEX, CLK_EXTAL, 2, 1), DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244), DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250), DEF_GEN3_OSC("osc", R8A7796_CLK_OSC, CLK_EXTAL, 8), DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), }; static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = { DEF_MOD("3dge", 112, R8A7796_CLK_ZG), DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1), DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6), DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2), DEF_MOD("tmu2", 123, R8A7796_CLK_S3D2), DEF_MOD("tmu1", 124, R8A7796_CLK_S3D2), DEF_MOD("tmu0", 125, R8A7796_CLK_CP), DEF_MOD("scif5", 202, R8A7796_CLK_S3D4), DEF_MOD("scif4", 203, R8A7796_CLK_S3D4), DEF_MOD("scif3", 204, R8A7796_CLK_S3D4), DEF_MOD("scif1", 206, R8A7796_CLK_S3D4), DEF_MOD("scif0", 207, R8A7796_CLK_S3D4), DEF_MOD("msiof3", 208, R8A7796_CLK_MSO), DEF_MOD("msiof2", 209, R8A7796_CLK_MSO), DEF_MOD("msiof1", 210, R8A7796_CLK_MSO), DEF_MOD("msiof0", 211, R8A7796_CLK_MSO), DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S3D1), DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S3D1), DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3), DEF_MOD("sceg-pub", 229, R8A7796_CLK_CR), DEF_MOD("cmt3", 300, R8A7796_CLK_R), DEF_MOD("cmt2", 301, R8A7796_CLK_R), DEF_MOD("cmt1", 302, R8A7796_CLK_R), DEF_MOD("cmt0", 303, R8A7796_CLK_R), DEF_MOD("tpu0", 304, R8A7796_CLK_S3D4), DEF_MOD("scif2", 310, R8A7796_CLK_S3D4), DEF_MOD("sdif3", 311, R8A7796_CLK_SD3), DEF_MOD("sdif2", 312, R8A7796_CLK_SD2), DEF_MOD("sdif1", 313, R8A7796_CLK_SD1), DEF_MOD("sdif0", 314, R8A7796_CLK_SD0), DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1), DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1), DEF_MOD("usb3-if0", 328, R8A7796_CLK_S3D1), DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1), DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1), DEF_MOD("rwdt", 402, R8A7796_CLK_R), DEF_MOD("intc-ex", 407, R8A7796_CLK_CP), DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3), DEF_MOD("audmac1", 501, R8A7796_CLK_S1D2), DEF_MOD("audmac0", 502, R8A7796_CLK_S1D2), DEF_MOD("drif31", 508, R8A7796_CLK_S3D2), DEF_MOD("drif30", 509, R8A7796_CLK_S3D2), DEF_MOD("drif21", 510, R8A7796_CLK_S3D2), DEF_MOD("drif20", 511, R8A7796_CLK_S3D2), DEF_MOD("drif11", 512, R8A7796_CLK_S3D2), DEF_MOD("drif10", 513, R8A7796_CLK_S3D2), DEF_MOD("drif01", 514, R8A7796_CLK_S3D2), DEF_MOD("drif00", 515, R8A7796_CLK_S3D2), DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1), DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1), DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1), DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1), DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1), DEF_MOD("thermal", 522, R8A7796_CLK_CP), DEF_MOD("pwm", 523, R8A7796_CLK_S0D12), DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2), DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2), DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2), DEF_MOD("fcpvb0", 607, R8A7796_CLK_S0D1), DEF_MOD("fcpvi0", 611, R8A7796_CLK_S0D1), DEF_MOD("fcpf0", 615, R8A7796_CLK_S0D1), DEF_MOD("fcpci0", 617, R8A7796_CLK_S0D2), DEF_MOD("fcpcs", 619, R8A7796_CLK_S0D2), DEF_MOD("vspd2", 621, R8A7796_CLK_S0D2), DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2), DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2), DEF_MOD("vspb", 626, R8A7796_CLK_S0D1), DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1), DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2), DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2), DEF_MOD("hsusb", 704, R8A7796_CLK_S3D2), DEF_MOD("cmm2", 709, R8A7796_CLK_S2D1), DEF_MOD("cmm1", 710, R8A7796_CLK_S2D1), DEF_MOD("cmm0", 711, R8A7796_CLK_S2D1), DEF_MOD("csi20", 714, R8A7796_CLK_CSI0), DEF_MOD("csi40", 716, R8A7796_CLK_CSI0), DEF_MOD("du2", 722, R8A7796_CLK_S2D1), DEF_MOD("du1", 723, R8A7796_CLK_S2D1), DEF_MOD("du0", 724, R8A7796_CLK_S2D1), DEF_MOD("lvds", 727, R8A7796_CLK_S2D1), DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI), DEF_MOD("mlp", 802, R8A7796_CLK_S2D1), DEF_MOD("vin7", 804, R8A7796_CLK_S0D2), DEF_MOD("vin6", 805, R8A7796_CLK_S0D2), DEF_MOD("vin5", 806, R8A7796_CLK_S0D2), DEF_MOD("vin4", 807, R8A7796_CLK_S0D2), DEF_MOD("vin3", 808, R8A7796_CLK_S0D2), DEF_MOD("vin2", 809, R8A7796_CLK_S0D2), DEF_MOD("vin1", 810, R8A7796_CLK_S0D2), DEF_MOD("vin0", 811, R8A7796_CLK_S0D2), DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6), DEF_MOD("imr1", 822, R8A7796_CLK_S0D2), DEF_MOD("imr0", 823, R8A7796_CLK_S0D2), DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4), DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4), DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4), DEF_MOD("gpio4", 908, R8A7796_CLK_S3D4), DEF_MOD("gpio3", 909, R8A7796_CLK_S3D4), DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4), DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4), DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4), DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2), DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4), DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4), DEF_MOD("rpc-if", 917, R8A7796_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6), DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6), DEF_MOD("adg", 922, R8A7796_CLK_S0D4), DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP), DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6), DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6), DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2), DEF_MOD("i2c1", 930, R8A7796_CLK_S3D2), DEF_MOD("i2c0", 931, R8A7796_CLK_S3D2), DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4), DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4), DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), }; static const unsigned int r8a7796_crit_mod_clks[] __initconst = { MOD_CLK_ID(402), /* RWDT */ MOD_CLK_ID(408), /* INTC-AP (GIC) */ }; /* * CPG Clock Data */ /* * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC * 14 13 19 17 (MHz) *------------------------------------------------------------------------- * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16 * 0 0 1 0 Prohibited setting * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19 * 0 1 1 0 Prohibited setting * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24 * 1 0 1 0 Prohibited setting * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32 * 1 1 1 0 Prohibited setting * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32 */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ (((md) & BIT(13)) >> 11) | \ (((md) & BIT(19)) >> 18) | \ (((md) & BIT(17)) >> 17)) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ { 1, 192, 1, 192, 1, 16, }, { 1, 192, 1, 128, 1, 16, }, { 0, /* Prohibited setting */ }, { 1, 192, 1, 192, 1, 16, }, { 1, 160, 1, 160, 1, 19, }, { 1, 160, 1, 106, 1, 19, }, { 0, /* Prohibited setting */ }, { 1, 160, 1, 160, 1, 19, }, { 1, 128, 1, 128, 1, 24, }, { 1, 128, 1, 84, 1, 24, }, { 0, /* Prohibited setting */ }, { 1, 128, 1, 128, 1, 24, }, { 2, 192, 1, 192, 1, 32, }, { 2, 192, 1, 128, 1, 32, }, { 0, /* Prohibited setting */ }, { 2, 192, 1, 192, 1, 32, }, }; /* * Fixups for R-Car M3-W+ */ static const unsigned int r8a77961_mod_nullify[] __initconst = { MOD_CLK_ID(617), /* FCPCI0 */ }; static int __init r8a7796_cpg_mssr_init(struct device *dev) { const struct rcar_gen3_cpg_pll_config *cpg_pll_config; u32 cpg_mode; int error; error = rcar_rst_read_mode_pins(&cpg_mode); if (error) return error; cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; if (!cpg_pll_config->extal_div) { dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); return -EINVAL; } if (of_device_is_compatible(dev->of_node, "renesas,r8a77961-cpg-mssr")) mssr_mod_nullify(r8a7796_mod_clks, ARRAY_SIZE(r8a7796_mod_clks), r8a77961_mod_nullify, ARRAY_SIZE(r8a77961_mod_nullify)); return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); } const struct cpg_mssr_info r8a7796_cpg_mssr_info __initconst = { /* Core Clocks */ .core_clks = r8a7796_core_clks, .num_core_clks = ARRAY_SIZE(r8a7796_core_clks), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Module Clocks */ .mod_clks = r8a7796_mod_clks, .num_mod_clks = ARRAY_SIZE(r8a7796_mod_clks), .num_hw_mod_clks = 12 * 32, /* Critical Module Clocks */ .crit_mod_clks = r8a7796_crit_mod_clks, .num_crit_mod_clks = ARRAY_SIZE(r8a7796_crit_mod_clks), /* Callbacks */ .init = r8a7796_cpg_mssr_init, .cpg_clk_register = rcar_gen3_cpg_clk_register, };
linux-master
drivers/clk/renesas/r8a7796-cpg-mssr.c
// SPDX-License-Identifier: GPL-2.0 /* * R-Car Gen3 Clock Pulse Generator * * Copyright (C) 2015-2018 Glider bvba * Copyright (C) 2019 Renesas Electronics Corp. * * Based on clk-rcar-gen3.c * * Copyright (C) 2015 Renesas Electronics Corp. */ #include <linux/bug.h> #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/device.h> #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> #include <linux/pm.h> #include <linux/slab.h> #include <linux/sys_soc.h> #include "renesas-cpg-mssr.h" #include "rcar-cpg-lib.h" #include "rcar-gen3-cpg.h" #define CPG_PLLECR 0x00d0 /* PLL Enable Control Register */ #define CPG_PLLECR_PLLST(n) BIT(8 + (n)) /* PLLn Circuit Status */ #define CPG_PLL0CR 0x00d8 /* PLLn Control Registers */ #define CPG_PLL2CR 0x002c #define CPG_PLL4CR 0x01f4 #define CPG_PLLnCR_STC_MASK GENMASK(30, 24) /* PLL Circuit Mult. Ratio */ #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */ /* PLL Clocks */ struct cpg_pll_clk { struct clk_hw hw; void __iomem *pllcr_reg; void __iomem *pllecr_reg; unsigned int fixed_mult; u32 pllecr_pllst_mask; }; #define to_pll_clk(_hw) container_of(_hw, struct cpg_pll_clk, hw) static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct cpg_pll_clk *pll_clk = to_pll_clk(hw); unsigned int mult; u32 val; val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1; return parent_rate * mult * pll_clk->fixed_mult; } static int cpg_pll_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct cpg_pll_clk *pll_clk = to_pll_clk(hw); unsigned int min_mult, max_mult, mult; unsigned long prate; prate = req->best_parent_rate * pll_clk->fixed_mult; min_mult = max(div64_ul(req->min_rate, prate), 1ULL); max_mult = min(div64_ul(req->max_rate, prate), 128ULL); if (max_mult < min_mult) return -EINVAL; mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); mult = clamp(mult, min_mult, max_mult); req->rate = prate * mult; return 0; } static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct cpg_pll_clk *pll_clk = to_pll_clk(hw); unsigned int mult, i; u32 val; mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult); mult = clamp(mult, 1U, 128U); val = readl(pll_clk->pllcr_reg); val &= ~CPG_PLLnCR_STC_MASK; val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK); writel(val, pll_clk->pllcr_reg); for (i = 1000; i; i--) { if (readl(pll_clk->pllecr_reg) & pll_clk->pllecr_pllst_mask) return 0; cpu_relax(); } return -ETIMEDOUT; } static const struct clk_ops cpg_pll_clk_ops = { .recalc_rate = cpg_pll_clk_recalc_rate, .determine_rate = cpg_pll_clk_determine_rate, .set_rate = cpg_pll_clk_set_rate, }; static struct clk * __init cpg_pll_clk_register(const char *name, const char *parent_name, void __iomem *base, unsigned int mult, unsigned int offset, unsigned int index) { struct cpg_pll_clk *pll_clk; struct clk_init_data init = {}; struct clk *clk; pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); if (!pll_clk) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &cpg_pll_clk_ops; init.parent_names = &parent_name; init.num_parents = 1; pll_clk->hw.init = &init; pll_clk->pllcr_reg = base + offset; pll_clk->pllecr_reg = base + CPG_PLLECR; pll_clk->fixed_mult = mult; /* PLL refclk x (setting + 1) x mult */ pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index); clk = clk_register(NULL, &pll_clk->hw); if (IS_ERR(clk)) kfree(pll_clk); return clk; } /* * Z Clock & Z2 Clock * * Traits of this clock: * prepare - clk_prepare only ensures that parents are prepared * enable - clk_enable only ensures that parents are enabled * rate - rate is adjustable. * clk->rate = (parent->rate * mult / 32 ) / fixed_div * parent - fixed parent. No clk_set_parent support */ #define CPG_FRQCRB 0x00000004 #define CPG_FRQCRB_KICK BIT(31) #define CPG_FRQCRC 0x000000e0 struct cpg_z_clk { struct clk_hw hw; void __iomem *reg; void __iomem *kick_reg; unsigned long max_rate; /* Maximum rate for normal mode */ unsigned int fixed_div; u32 mask; }; #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct cpg_z_clk *zclk = to_z_clk(hw); unsigned int mult; u32 val; val = readl(zclk->reg) & zclk->mask; mult = 32 - (val >> __ffs(zclk->mask)); return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * zclk->fixed_div); } static int cpg_z_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct cpg_z_clk *zclk = to_z_clk(hw); unsigned int min_mult, max_mult, mult; unsigned long rate, prate; rate = min(req->rate, req->max_rate); if (rate <= zclk->max_rate) { /* Set parent rate to initial value for normal modes */ prate = zclk->max_rate; } else { /* Set increased parent rate for boost modes */ prate = rate; } req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), prate * zclk->fixed_div); prate = req->best_parent_rate / zclk->fixed_div; min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); if (max_mult < min_mult) return -EINVAL; mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate); mult = clamp(mult, min_mult, max_mult); req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); return 0; } static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct cpg_z_clk *zclk = to_z_clk(hw); unsigned int mult; unsigned int i; mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, parent_rate); mult = clamp(mult, 1U, 32U); if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) return -EBUSY; cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); /* * Set KICK bit in FRQCRB to update hardware setting and wait for * clock change completion. */ cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK); /* * Note: There is no HW information about the worst case latency. * * Using experimental measurements, it seems that no more than * ~10 iterations are needed, independently of the CPU rate. * Since this value might be dependent on external xtal rate, pll1 * rate or even the other emulation clocks rate, use 1000 as a * "super" safe value. */ for (i = 1000; i; i--) { if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) return 0; cpu_relax(); } return -ETIMEDOUT; } static const struct clk_ops cpg_z_clk_ops = { .recalc_rate = cpg_z_clk_recalc_rate, .determine_rate = cpg_z_clk_determine_rate, .set_rate = cpg_z_clk_set_rate, }; static struct clk * __init __cpg_z_clk_register(const char *name, const char *parent_name, void __iomem *reg, unsigned int div, unsigned int offset, unsigned int fcr, unsigned int flags) { struct clk_init_data init = {}; struct cpg_z_clk *zclk; struct clk *clk; zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); if (!zclk) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &cpg_z_clk_ops; init.flags = flags; init.parent_names = &parent_name; init.num_parents = 1; zclk->reg = reg + fcr; zclk->kick_reg = reg + CPG_FRQCRB; zclk->hw.init = &init; zclk->mask = GENMASK(offset + 4, offset); zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ clk = clk_register(NULL, &zclk->hw); if (IS_ERR(clk)) { kfree(zclk); return clk; } zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) / zclk->fixed_div; return clk; } static struct clk * __init cpg_z_clk_register(const char *name, const char *parent_name, void __iomem *reg, unsigned int div, unsigned int offset) { return __cpg_z_clk_register(name, parent_name, reg, div, offset, CPG_FRQCRC, CLK_SET_RATE_PARENT); } static struct clk * __init cpg_zg_clk_register(const char *name, const char *parent_name, void __iomem *reg, unsigned int div, unsigned int offset) { return __cpg_z_clk_register(name, parent_name, reg, div, offset, CPG_FRQCRB, 0); } static const struct clk_div_table cpg_rpcsrc_div_table[] = { { 2, 5 }, { 3, 6 }, { 0, 0 }, }; static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata; static unsigned int cpg_clk_extalr __initdata; static u32 cpg_mode __initdata; static u32 cpg_quirks __initdata; #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ static const struct soc_device_attribute cpg_quirks_match[] __initconst = { { .soc_id = "r8a7796", .revision = "ES1.0", .data = (void *)(RCKCR_CKSEL), }, { /* sentinel */ } }; struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core, const struct cpg_mssr_info *info, struct clk **clks, void __iomem *base, struct raw_notifier_head *notifiers) { const struct clk *parent; unsigned int mult = 1; unsigned int div = 1; u32 value; parent = clks[core->parent & 0xffff]; /* some types use high bits */ if (IS_ERR(parent)) return ERR_CAST(parent); switch (core->type) { case CLK_TYPE_GEN3_MAIN: div = cpg_pll_config->extal_div; break; case CLK_TYPE_GEN3_PLL0: /* * PLL0 is implemented as a custom clock, to change the * multiplier when cpufreq changes between normal and boost * modes. */ return cpg_pll_clk_register(core->name, __clk_get_name(parent), base, 2, CPG_PLL0CR, 0); case CLK_TYPE_GEN3_PLL1: mult = cpg_pll_config->pll1_mult; div = cpg_pll_config->pll1_div; break; case CLK_TYPE_GEN3_PLL2: /* * PLL2 is implemented as a custom clock, to change the * multiplier when cpufreq changes between normal and boost * modes. */ return cpg_pll_clk_register(core->name, __clk_get_name(parent), base, 2, CPG_PLL2CR, 2); case CLK_TYPE_GEN3_PLL3: mult = cpg_pll_config->pll3_mult; div = cpg_pll_config->pll3_div; break; case CLK_TYPE_GEN3_PLL4: /* * PLL4 is a configurable multiplier clock. Register it as a * fixed factor clock for now as there's no generic multiplier * clock implementation and we currently have no need to change * the multiplier value. */ value = readl(base + CPG_PLL4CR); mult = (((value >> 24) & 0x7f) + 1) * 2; break; case CLK_TYPE_GEN3_SDH: return cpg_sdh_clk_register(core->name, base + core->offset, __clk_get_name(parent), notifiers); case CLK_TYPE_GEN3_SD: return cpg_sd_clk_register(core->name, base + core->offset, __clk_get_name(parent)); case CLK_TYPE_GEN3_R: if (cpg_quirks & RCKCR_CKSEL) { struct cpg_simple_notifier *csn; csn = kzalloc(sizeof(*csn), GFP_KERNEL); if (!csn) return ERR_PTR(-ENOMEM); csn->reg = base + CPG_RCKCR; /* * RINT is default. * Only if EXTALR is populated, we switch to it. */ value = readl(csn->reg) & 0x3f; if (clk_get_rate(clks[cpg_clk_extalr])) { parent = clks[cpg_clk_extalr]; value |= CPG_RCKCR_CKSEL; } writel(value, csn->reg); cpg_simple_notifier_register(notifiers, csn); break; } /* Select parent clock of RCLK by MD28 */ if (cpg_mode & BIT(28)) parent = clks[cpg_clk_extalr]; break; case CLK_TYPE_GEN3_MDSEL: /* * Clock selectable between two parents and two fixed dividers * using a mode pin */ if (cpg_mode & BIT(core->offset)) { div = core->div & 0xffff; } else { parent = clks[core->parent >> 16]; if (IS_ERR(parent)) return ERR_CAST(parent); div = core->div >> 16; } mult = 1; break; case CLK_TYPE_GEN3_Z: return cpg_z_clk_register(core->name, __clk_get_name(parent), base, core->div, core->offset); case CLK_TYPE_GEN3_ZG: return cpg_zg_clk_register(core->name, __clk_get_name(parent), base, core->div, core->offset); case CLK_TYPE_GEN3_OSC: /* * Clock combining OSC EXTAL predivider and a fixed divider */ div = cpg_pll_config->osc_prediv * core->div; break; case CLK_TYPE_GEN3_RCKSEL: /* * Clock selectable between two parents and two fixed dividers * using RCKCR.CKSEL */ if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) { div = core->div & 0xffff; } else { parent = clks[core->parent >> 16]; if (IS_ERR(parent)) return ERR_CAST(parent); div = core->div >> 16; } break; case CLK_TYPE_GEN3_RPCSRC: return clk_register_divider_table(NULL, core->name, __clk_get_name(parent), 0, base + CPG_RPCCKCR, 3, 2, 0, cpg_rpcsrc_div_table, &cpg_lock); case CLK_TYPE_GEN3_E3_RPCSRC: /* * Register RPCSRC as fixed factor clock based on the * MD[4:1] pins and CPG_RPCCKCR[4:3] register value for * which has been set prior to booting the kernel. */ value = (readl(base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3; switch (value) { case 0: div = 5; break; case 1: div = 3; break; case 2: parent = clks[core->parent >> 16]; if (IS_ERR(parent)) return ERR_CAST(parent); div = core->div; break; case 3: default: div = 2; break; } break; case CLK_TYPE_GEN3_RPC: return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR, __clk_get_name(parent), notifiers); case CLK_TYPE_GEN3_RPCD2: return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR, __clk_get_name(parent)); default: return ERR_PTR(-EINVAL); } return clk_register_fixed_factor(NULL, core->name, __clk_get_name(parent), 0, mult, div); } int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, unsigned int clk_extalr, u32 mode) { const struct soc_device_attribute *attr; cpg_pll_config = config; cpg_clk_extalr = clk_extalr; cpg_mode = mode; attr = soc_device_match(cpg_quirks_match); if (attr) cpg_quirks = (uintptr_t)attr->data; pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks); spin_lock_init(&cpg_lock); return 0; }
linux-master
drivers/clk/renesas/rcar-gen3-cpg.c
// SPDX-License-Identifier: GPL-2.0 /* * r8a7742 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2020 Renesas Electronics Corp. */ #include <linux/device.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/soc/renesas/rcar-rst.h> #include <dt-bindings/clock/r8a7742-cpg-mssr.h> #include "renesas-cpg-mssr.h" #include "rcar-gen2-cpg.h" enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A7742_CLK_OSC, /* External Input Clocks */ CLK_EXTAL, CLK_USB_EXTAL, /* Internal Core Clocks */ CLK_MAIN, CLK_PLL0, CLK_PLL1, CLK_PLL3, CLK_PLL1_DIV2, /* Module Clocks */ MOD_CLK_BASE }; static const struct cpg_core_clk r8a7742_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("usb_extal", CLK_USB_EXTAL), /* Internal Core Clocks */ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), /* Core Clock Outputs */ DEF_BASE("z", R8A7742_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0), DEF_BASE("lb", R8A7742_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1), DEF_BASE("sdh", R8A7742_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), DEF_BASE("sd0", R8A7742_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), DEF_BASE("sd1", R8A7742_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1), DEF_BASE("qspi", R8A7742_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), DEF_BASE("rcan", R8A7742_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL), DEF_FIXED("z2", R8A7742_CLK_Z2, CLK_PLL1, 2, 1), DEF_FIXED("zg", R8A7742_CLK_ZG, CLK_PLL1, 3, 1), DEF_FIXED("zx", R8A7742_CLK_ZX, CLK_PLL1, 3, 1), DEF_FIXED("zs", R8A7742_CLK_ZS, CLK_PLL1, 6, 1), DEF_FIXED("hp", R8A7742_CLK_HP, CLK_PLL1, 12, 1), DEF_FIXED("b", R8A7742_CLK_B, CLK_PLL1, 12, 1), DEF_FIXED("p", R8A7742_CLK_P, CLK_PLL1, 24, 1), DEF_FIXED("cl", R8A7742_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("m2", R8A7742_CLK_M2, CLK_PLL1, 8, 1), DEF_FIXED("zb3", R8A7742_CLK_ZB3, CLK_PLL3, 4, 1), DEF_FIXED("zb3d2", R8A7742_CLK_ZB3D2, CLK_PLL3, 8, 1), DEF_FIXED("ddr", R8A7742_CLK_DDR, CLK_PLL3, 8, 1), DEF_FIXED("mp", R8A7742_CLK_MP, CLK_PLL1_DIV2, 15, 1), DEF_FIXED("cp", R8A7742_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("r", R8A7742_CLK_R, CLK_PLL1, 49152, 1), DEF_FIXED("osc", R8A7742_CLK_OSC, CLK_PLL1, 12288, 1), DEF_DIV6P1("sd2", R8A7742_CLK_SD2, CLK_PLL1_DIV2, 0x078), DEF_DIV6P1("sd3", R8A7742_CLK_SD3, CLK_PLL1_DIV2, 0x26c), DEF_DIV6P1("mmc0", R8A7742_CLK_MMC0, CLK_PLL1_DIV2, 0x240), DEF_DIV6P1("mmc1", R8A7742_CLK_MMC1, CLK_PLL1_DIV2, 0x244), }; static const struct mssr_mod_clk r8a7742_mod_clks[] __initconst = { DEF_MOD("msiof0", 0, R8A7742_CLK_MP), DEF_MOD("vcp1", 100, R8A7742_CLK_ZS), DEF_MOD("vcp0", 101, R8A7742_CLK_ZS), DEF_MOD("vpc1", 102, R8A7742_CLK_ZS), DEF_MOD("vpc0", 103, R8A7742_CLK_ZS), DEF_MOD("tmu1", 111, R8A7742_CLK_P), DEF_MOD("3dg", 112, R8A7742_CLK_ZG), DEF_MOD("2d-dmac", 115, R8A7742_CLK_ZS), DEF_MOD("fdp1-2", 117, R8A7742_CLK_ZS), DEF_MOD("fdp1-1", 118, R8A7742_CLK_ZS), DEF_MOD("fdp1-0", 119, R8A7742_CLK_ZS), DEF_MOD("tmu3", 121, R8A7742_CLK_P), DEF_MOD("tmu2", 122, R8A7742_CLK_P), DEF_MOD("cmt0", 124, R8A7742_CLK_R), DEF_MOD("tmu0", 125, R8A7742_CLK_CP), DEF_MOD("vsp1du1", 127, R8A7742_CLK_ZS), DEF_MOD("vsp1du0", 128, R8A7742_CLK_ZS), DEF_MOD("vspr", 130, R8A7742_CLK_ZS), DEF_MOD("vsps", 131, R8A7742_CLK_ZS), DEF_MOD("scifa2", 202, R8A7742_CLK_MP), DEF_MOD("scifa1", 203, R8A7742_CLK_MP), DEF_MOD("scifa0", 204, R8A7742_CLK_MP), DEF_MOD("msiof2", 205, R8A7742_CLK_MP), DEF_MOD("scifb0", 206, R8A7742_CLK_MP), DEF_MOD("scifb1", 207, R8A7742_CLK_MP), DEF_MOD("msiof1", 208, R8A7742_CLK_MP), DEF_MOD("msiof3", 215, R8A7742_CLK_MP), DEF_MOD("scifb2", 216, R8A7742_CLK_MP), DEF_MOD("sys-dmac1", 218, R8A7742_CLK_ZS), DEF_MOD("sys-dmac0", 219, R8A7742_CLK_ZS), DEF_MOD("iic2", 300, R8A7742_CLK_HP), DEF_MOD("tpu0", 304, R8A7742_CLK_CP), DEF_MOD("mmcif1", 305, R8A7742_CLK_MMC1), DEF_MOD("scif2", 310, R8A7742_CLK_P), DEF_MOD("sdhi3", 311, R8A7742_CLK_SD3), DEF_MOD("sdhi2", 312, R8A7742_CLK_SD2), DEF_MOD("sdhi1", 313, R8A7742_CLK_SD1), DEF_MOD("sdhi0", 314, R8A7742_CLK_SD0), DEF_MOD("mmcif0", 315, R8A7742_CLK_MMC0), DEF_MOD("iic0", 318, R8A7742_CLK_HP), DEF_MOD("pciec", 319, R8A7742_CLK_MP), DEF_MOD("iic1", 323, R8A7742_CLK_HP), DEF_MOD("usb3.0", 328, R8A7742_CLK_MP), DEF_MOD("cmt1", 329, R8A7742_CLK_R), DEF_MOD("usbhs-dmac0", 330, R8A7742_CLK_HP), DEF_MOD("usbhs-dmac1", 331, R8A7742_CLK_HP), DEF_MOD("rwdt", 402, R8A7742_CLK_R), DEF_MOD("irqc", 407, R8A7742_CLK_CP), DEF_MOD("intc-sys", 408, R8A7742_CLK_ZS), DEF_MOD("audio-dmac1", 501, R8A7742_CLK_HP), DEF_MOD("audio-dmac0", 502, R8A7742_CLK_HP), DEF_MOD("thermal", 522, CLK_EXTAL), DEF_MOD("pwm", 523, R8A7742_CLK_P), DEF_MOD("usb-ehci", 703, R8A7742_CLK_MP), DEF_MOD("usbhs", 704, R8A7742_CLK_HP), DEF_MOD("hscif1", 716, R8A7742_CLK_ZS), DEF_MOD("hscif0", 717, R8A7742_CLK_ZS), DEF_MOD("scif1", 720, R8A7742_CLK_P), DEF_MOD("scif0", 721, R8A7742_CLK_P), DEF_MOD("du2", 722, R8A7742_CLK_ZX), DEF_MOD("du1", 723, R8A7742_CLK_ZX), DEF_MOD("du0", 724, R8A7742_CLK_ZX), DEF_MOD("lvds1", 725, R8A7742_CLK_ZX), DEF_MOD("lvds0", 726, R8A7742_CLK_ZX), DEF_MOD("r-gp2d", 807, R8A7742_CLK_ZX), DEF_MOD("vin3", 808, R8A7742_CLK_ZG), DEF_MOD("vin2", 809, R8A7742_CLK_ZG), DEF_MOD("vin1", 810, R8A7742_CLK_ZG), DEF_MOD("vin0", 811, R8A7742_CLK_ZG), DEF_MOD("etheravb", 812, R8A7742_CLK_HP), DEF_MOD("ether", 813, R8A7742_CLK_P), DEF_MOD("sata1", 814, R8A7742_CLK_ZS), DEF_MOD("sata0", 815, R8A7742_CLK_ZS), DEF_MOD("imr-x2-1", 820, R8A7742_CLK_ZG), DEF_MOD("imr-x2-0", 821, R8A7742_CLK_HP), DEF_MOD("imr-lsx2-1", 822, R8A7742_CLK_P), DEF_MOD("imr-lsx2-0", 823, R8A7742_CLK_ZS), DEF_MOD("gpio5", 907, R8A7742_CLK_CP), DEF_MOD("gpio4", 908, R8A7742_CLK_CP), DEF_MOD("gpio3", 909, R8A7742_CLK_CP), DEF_MOD("gpio2", 910, R8A7742_CLK_CP), DEF_MOD("gpio1", 911, R8A7742_CLK_CP), DEF_MOD("gpio0", 912, R8A7742_CLK_CP), DEF_MOD("can1", 915, R8A7742_CLK_P), DEF_MOD("can0", 916, R8A7742_CLK_P), DEF_MOD("qspi_mod", 917, R8A7742_CLK_QSPI), DEF_MOD("iicdvfs", 926, R8A7742_CLK_CP), DEF_MOD("i2c3", 928, R8A7742_CLK_HP), DEF_MOD("i2c2", 929, R8A7742_CLK_HP), DEF_MOD("i2c1", 930, R8A7742_CLK_HP), DEF_MOD("i2c0", 931, R8A7742_CLK_HP), DEF_MOD("ssi-all", 1005, R8A7742_CLK_P), DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), DEF_MOD("scu-all", 1017, R8A7742_CLK_P), DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), }; static const unsigned int r8a7742_crit_mod_clks[] __initconst = { MOD_CLK_ID(402), /* RWDT */ MOD_CLK_ID(408), /* INTC-SYS (GIC) */ }; /* * CPG Clock Data */ /* * MD EXTAL PLL0 PLL1 PLL3 * 14 13 19 (MHz) *1 *1 *--------------------------------------------------- * 0 0 0 15 x172/2 x208/2 x106 * 0 0 1 15 x172/2 x208/2 x88 * 0 1 0 20 x130/2 x156/2 x80 * 0 1 1 20 x130/2 x156/2 x66 * 1 0 0 26 / 2 x200/2 x240/2 x122 * 1 0 1 26 / 2 x200/2 x240/2 x102 * 1 1 0 30 / 2 x172/2 x208/2 x106 * 1 1 1 30 / 2 x172/2 x208/2 x88 * * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2) */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ (((md) & BIT(13)) >> 12) | \ (((md) & BIT(19)) >> 19)) static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = { /* EXTAL div PLL1 mult PLL3 mult */ { 1, 208, 106, }, { 1, 208, 88, }, { 1, 156, 80, }, { 1, 156, 66, }, { 2, 240, 122, }, { 2, 240, 102, }, { 2, 208, 106, }, { 2, 208, 88, }, }; static int __init r8a7742_cpg_mssr_init(struct device *dev) { const struct rcar_gen2_cpg_pll_config *cpg_pll_config; u32 cpg_mode; int error; error = rcar_rst_read_mode_pins(&cpg_mode); if (error) return error; cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode); } const struct cpg_mssr_info r8a7742_cpg_mssr_info __initconst = { /* Core Clocks */ .core_clks = r8a7742_core_clks, .num_core_clks = ARRAY_SIZE(r8a7742_core_clks), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Module Clocks */ .mod_clks = r8a7742_mod_clks, .num_mod_clks = ARRAY_SIZE(r8a7742_mod_clks), .num_hw_mod_clks = 12 * 32, /* Critical Module Clocks */ .crit_mod_clks = r8a7742_crit_mod_clks, .num_crit_mod_clks = ARRAY_SIZE(r8a7742_crit_mod_clks), /* Callbacks */ .init = r8a7742_cpg_mssr_init, .cpg_clk_register = rcar_gen2_cpg_clk_register, };
linux-master
drivers/clk/renesas/r8a7742-cpg-mssr.c
// SPDX-License-Identifier: GPL-2.0 /* * r8a77470 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2018 Renesas Electronics Corp. */ #include <linux/device.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/soc/renesas/rcar-rst.h> #include <dt-bindings/clock/r8a77470-cpg-mssr.h> #include "renesas-cpg-mssr.h" #include "rcar-gen2-cpg.h" enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A77470_CLK_OSC, /* External Input Clocks */ CLK_EXTAL, CLK_USB_EXTAL, /* Internal Core Clocks */ CLK_MAIN, CLK_PLL0, CLK_PLL1, CLK_PLL3, CLK_PLL1_DIV2, /* Module Clocks */ MOD_CLK_BASE }; static const struct cpg_core_clk r8a77470_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("usb_extal", CLK_USB_EXTAL), /* Internal Core Clocks */ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), /* Core Clock Outputs */ DEF_BASE("sdh", R8A77470_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), DEF_BASE("sd0", R8A77470_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), DEF_BASE("sd1", R8A77470_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1), DEF_BASE("qspi", R8A77470_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), DEF_BASE("rcan", R8A77470_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL), DEF_FIXED("z2", R8A77470_CLK_Z2, CLK_PLL0, 1, 1), DEF_FIXED("zx", R8A77470_CLK_ZX, CLK_PLL1, 3, 1), DEF_FIXED("zs", R8A77470_CLK_ZS, CLK_PLL1, 6, 1), DEF_FIXED("hp", R8A77470_CLK_HP, CLK_PLL1, 12, 1), DEF_FIXED("b", R8A77470_CLK_B, CLK_PLL1, 12, 1), DEF_FIXED("lb", R8A77470_CLK_LB, CLK_PLL1, 24, 1), DEF_FIXED("p", R8A77470_CLK_P, CLK_PLL1, 24, 1), DEF_FIXED("cl", R8A77470_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cp", R8A77470_CLK_CP, CLK_PLL1, 48, 1), DEF_FIXED("m2", R8A77470_CLK_M2, CLK_PLL1, 8, 1), DEF_FIXED("zb3", R8A77470_CLK_ZB3, CLK_PLL3, 4, 1), DEF_FIXED("mp", R8A77470_CLK_MP, CLK_PLL1_DIV2, 15, 1), DEF_FIXED("cpex", R8A77470_CLK_CPEX, CLK_EXTAL, 2, 1), DEF_FIXED("r", R8A77470_CLK_R, CLK_PLL1, 49152, 1), DEF_FIXED("osc", R8A77470_CLK_OSC, CLK_PLL1, 12288, 1), DEF_DIV6P1("sd2", R8A77470_CLK_SD2, CLK_PLL1_DIV2, 0x078), }; static const struct mssr_mod_clk r8a77470_mod_clks[] __initconst = { DEF_MOD("msiof0", 0, R8A77470_CLK_MP), DEF_MOD("vcp0", 101, R8A77470_CLK_ZS), DEF_MOD("vpc0", 103, R8A77470_CLK_ZS), DEF_MOD("tmu1", 111, R8A77470_CLK_P), DEF_MOD("3dg", 112, R8A77470_CLK_ZS), DEF_MOD("2d-dmac", 115, R8A77470_CLK_ZS), DEF_MOD("fdp1-0", 119, R8A77470_CLK_ZS), DEF_MOD("tmu3", 121, R8A77470_CLK_P), DEF_MOD("tmu2", 122, R8A77470_CLK_P), DEF_MOD("cmt0", 124, R8A77470_CLK_R), DEF_MOD("vsp1du0", 128, R8A77470_CLK_ZS), DEF_MOD("vsps", 131, R8A77470_CLK_ZS), DEF_MOD("msiof2", 205, R8A77470_CLK_MP), DEF_MOD("msiof1", 208, R8A77470_CLK_MP), DEF_MOD("sys-dmac1", 218, R8A77470_CLK_ZS), DEF_MOD("sys-dmac0", 219, R8A77470_CLK_ZS), DEF_MOD("sdhi2", 312, R8A77470_CLK_SD2), DEF_MOD("sdhi1", 313, R8A77470_CLK_SD1), DEF_MOD("sdhi0", 314, R8A77470_CLK_SD0), DEF_MOD("usbhs-dmac0-ch1", 326, R8A77470_CLK_HP), DEF_MOD("usbhs-dmac1-ch1", 327, R8A77470_CLK_HP), DEF_MOD("cmt1", 329, R8A77470_CLK_R), DEF_MOD("usbhs-dmac0-ch0", 330, R8A77470_CLK_HP), DEF_MOD("usbhs-dmac1-ch0", 331, R8A77470_CLK_HP), DEF_MOD("rwdt", 402, R8A77470_CLK_R), DEF_MOD("irqc", 407, R8A77470_CLK_CP), DEF_MOD("intc-sys", 408, R8A77470_CLK_ZS), DEF_MOD("audio-dmac0", 502, R8A77470_CLK_HP), DEF_MOD("pwm", 523, R8A77470_CLK_P), DEF_MOD("usb-ehci-0", 703, R8A77470_CLK_MP), DEF_MOD("usbhs-0", 704, R8A77470_CLK_HP), DEF_MOD("usb-ehci-1", 705, R8A77470_CLK_MP), DEF_MOD("usbhs-1", 706, R8A77470_CLK_HP), DEF_MOD("hscif2", 713, R8A77470_CLK_ZS), DEF_MOD("scif5", 714, R8A77470_CLK_P), DEF_MOD("scif4", 715, R8A77470_CLK_P), DEF_MOD("hscif1", 716, R8A77470_CLK_ZS), DEF_MOD("hscif0", 717, R8A77470_CLK_ZS), DEF_MOD("scif3", 718, R8A77470_CLK_P), DEF_MOD("scif2", 719, R8A77470_CLK_P), DEF_MOD("scif1", 720, R8A77470_CLK_P), DEF_MOD("scif0", 721, R8A77470_CLK_P), DEF_MOD("du1", 723, R8A77470_CLK_ZX), DEF_MOD("du0", 724, R8A77470_CLK_ZX), DEF_MOD("ipmmu-sgx", 800, R8A77470_CLK_ZX), DEF_MOD("etheravb", 812, R8A77470_CLK_HP), DEF_MOD("ether", 813, R8A77470_CLK_P), DEF_MOD("gpio5", 907, R8A77470_CLK_CP), DEF_MOD("gpio4", 908, R8A77470_CLK_CP), DEF_MOD("gpio3", 909, R8A77470_CLK_CP), DEF_MOD("gpio2", 910, R8A77470_CLK_CP), DEF_MOD("gpio1", 911, R8A77470_CLK_CP), DEF_MOD("gpio0", 912, R8A77470_CLK_CP), DEF_MOD("can1", 915, R8A77470_CLK_P), DEF_MOD("can0", 916, R8A77470_CLK_P), DEF_MOD("qspi_mod-1", 917, R8A77470_CLK_QSPI), DEF_MOD("qspi_mod-0", 918, R8A77470_CLK_QSPI), DEF_MOD("i2c4", 927, R8A77470_CLK_HP), DEF_MOD("i2c3", 928, R8A77470_CLK_HP), DEF_MOD("i2c2", 929, R8A77470_CLK_HP), DEF_MOD("i2c1", 930, R8A77470_CLK_HP), DEF_MOD("i2c0", 931, R8A77470_CLK_HP), DEF_MOD("ssi-all", 1005, R8A77470_CLK_P), DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), DEF_MOD("scu-all", 1017, R8A77470_CLK_P), DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), }; static const unsigned int r8a77470_crit_mod_clks[] __initconst = { MOD_CLK_ID(402), /* RWDT */ MOD_CLK_ID(408), /* INTC-SYS (GIC) */ }; /* * CPG Clock Data */ /* * MD EXTAL PLL0 PLL1 PLL3 * 14 13 (MHz) *1 *2 *--------------------------------------------------- * 0 0 20 x80 x78 x50 * 0 1 26 x60 x60 x56 * 1 0 Prohibited setting * 1 1 30 x52 x52 x50 * * *1 : Table 7.4 indicates VCO output (PLL0 = VCO) * *2 : Table 7.4 indicates VCO output (PLL1 = VCO) */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ (((md) & BIT(13)) >> 13)) static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = { /* EXTAL div PLL1 mult x2 PLL3 mult */ { 1, 156, 50, }, { 1, 120, 56, }, { /* Invalid*/ }, { 1, 104, 50, }, }; static int __init r8a77470_cpg_mssr_init(struct device *dev) { const struct rcar_gen2_cpg_pll_config *cpg_pll_config; u32 cpg_mode; int error; error = rcar_rst_read_mode_pins(&cpg_mode); if (error) return error; cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode); } const struct cpg_mssr_info r8a77470_cpg_mssr_info __initconst = { /* Core Clocks */ .core_clks = r8a77470_core_clks, .num_core_clks = ARRAY_SIZE(r8a77470_core_clks), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Module Clocks */ .mod_clks = r8a77470_mod_clks, .num_mod_clks = ARRAY_SIZE(r8a77470_mod_clks), .num_hw_mod_clks = 12 * 32, /* Critical Module Clocks */ .crit_mod_clks = r8a77470_crit_mod_clks, .num_crit_mod_clks = ARRAY_SIZE(r8a77470_crit_mod_clks), /* Callbacks */ .init = r8a77470_cpg_mssr_init, .cpg_clk_register = rcar_gen2_cpg_clk_register, };
linux-master
drivers/clk/renesas/r8a77470-cpg-mssr.c
// SPDX-License-Identifier: GPL-2.0 /* * r8a774b1 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2019 Renesas Electronics Corp. * * Based on r8a7796-cpg-mssr.c * * Copyright (C) 2016 Glider bvba */ #include <linux/device.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/soc/renesas/rcar-rst.h> #include <dt-bindings/clock/r8a774b1-cpg-mssr.h> #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A774B1_CLK_CANFD, /* External Input Clocks */ CLK_EXTAL, CLK_EXTALR, /* Internal Core Clocks */ CLK_MAIN, CLK_PLL0, CLK_PLL1, CLK_PLL3, CLK_PLL4, CLK_PLL1_DIV2, CLK_PLL1_DIV4, CLK_S0, CLK_S1, CLK_S2, CLK_S3, CLK_SDSRC, CLK_RPCSRC, CLK_RINT, /* Module Clocks */ MOD_CLK_BASE }; static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("extalr", CLK_EXTALR), /* Internal Core Clocks */ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), DEF_GEN3_Z("zg", R8A774B1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24), DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774B1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), DEF_FIXED("zx", R8A774B1_CLK_ZX, CLK_PLL1_DIV2, 2, 1), DEF_FIXED("s0d1", R8A774B1_CLK_S0D1, CLK_S0, 1, 1), DEF_FIXED("s0d2", R8A774B1_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A774B1_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A774B1_CLK_S0D4, CLK_S0, 4, 1), DEF_FIXED("s0d6", R8A774B1_CLK_S0D6, CLK_S0, 6, 1), DEF_FIXED("s0d8", R8A774B1_CLK_S0D8, CLK_S0, 8, 1), DEF_FIXED("s0d12", R8A774B1_CLK_S0D12, CLK_S0, 12, 1), DEF_FIXED("s1d2", R8A774B1_CLK_S1D2, CLK_S1, 2, 1), DEF_FIXED("s1d4", R8A774B1_CLK_S1D4, CLK_S1, 4, 1), DEF_FIXED("s2d1", R8A774B1_CLK_S2D1, CLK_S2, 1, 1), DEF_FIXED("s2d2", R8A774B1_CLK_S2D2, CLK_S2, 2, 1), DEF_FIXED("s2d4", R8A774B1_CLK_S2D4, CLK_S2, 4, 1), DEF_FIXED("s3d1", R8A774B1_CLK_S3D1, CLK_S3, 1, 1), DEF_FIXED("s3d2", R8A774B1_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A774B1_CLK_S3D4, CLK_S3, 4, 1), DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074), DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078), DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268), DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c), DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074), DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078), DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268), DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c), DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774B1_CLK_RPC), DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A774B1_CLK_CPEX, CLK_EXTAL, 2, 1), DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244), DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), DEF_DIV6P1("mso", R8A774B1_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("hdmi", R8A774B1_CLK_HDMI, CLK_PLL1_DIV4, 0x250), DEF_GEN3_OSC("osc", R8A774B1_CLK_OSC, CLK_EXTAL, 8), DEF_BASE("r", R8A774B1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), }; static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = { DEF_MOD("3dge", 112, R8A774B1_CLK_ZG), DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6), DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2), DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2), DEF_MOD("tmu1", 124, R8A774B1_CLK_S3D2), DEF_MOD("tmu0", 125, R8A774B1_CLK_CP), DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1), DEF_MOD("scif5", 202, R8A774B1_CLK_S3D4), DEF_MOD("scif4", 203, R8A774B1_CLK_S3D4), DEF_MOD("scif3", 204, R8A774B1_CLK_S3D4), DEF_MOD("scif1", 206, R8A774B1_CLK_S3D4), DEF_MOD("scif0", 207, R8A774B1_CLK_S3D4), DEF_MOD("msiof3", 208, R8A774B1_CLK_MSO), DEF_MOD("msiof2", 209, R8A774B1_CLK_MSO), DEF_MOD("msiof1", 210, R8A774B1_CLK_MSO), DEF_MOD("msiof0", 211, R8A774B1_CLK_MSO), DEF_MOD("sys-dmac2", 217, R8A774B1_CLK_S3D1), DEF_MOD("sys-dmac1", 218, R8A774B1_CLK_S3D1), DEF_MOD("sys-dmac0", 219, R8A774B1_CLK_S0D3), DEF_MOD("cmt3", 300, R8A774B1_CLK_R), DEF_MOD("cmt2", 301, R8A774B1_CLK_R), DEF_MOD("cmt1", 302, R8A774B1_CLK_R), DEF_MOD("cmt0", 303, R8A774B1_CLK_R), DEF_MOD("tpu0", 304, R8A774B1_CLK_S3D4), DEF_MOD("scif2", 310, R8A774B1_CLK_S3D4), DEF_MOD("sdif3", 311, R8A774B1_CLK_SD3), DEF_MOD("sdif2", 312, R8A774B1_CLK_SD2), DEF_MOD("sdif1", 313, R8A774B1_CLK_SD1), DEF_MOD("sdif0", 314, R8A774B1_CLK_SD0), DEF_MOD("pcie1", 318, R8A774B1_CLK_S3D1), DEF_MOD("pcie0", 319, R8A774B1_CLK_S3D1), DEF_MOD("usb3-if0", 328, R8A774B1_CLK_S3D1), DEF_MOD("usb-dmac0", 330, R8A774B1_CLK_S3D1), DEF_MOD("usb-dmac1", 331, R8A774B1_CLK_S3D1), DEF_MOD("rwdt", 402, R8A774B1_CLK_R), DEF_MOD("intc-ex", 407, R8A774B1_CLK_CP), DEF_MOD("intc-ap", 408, R8A774B1_CLK_S0D3), DEF_MOD("audmac1", 501, R8A774B1_CLK_S1D2), DEF_MOD("audmac0", 502, R8A774B1_CLK_S1D2), DEF_MOD("hscif4", 516, R8A774B1_CLK_S3D1), DEF_MOD("hscif3", 517, R8A774B1_CLK_S3D1), DEF_MOD("hscif2", 518, R8A774B1_CLK_S3D1), DEF_MOD("hscif1", 519, R8A774B1_CLK_S3D1), DEF_MOD("hscif0", 520, R8A774B1_CLK_S3D1), DEF_MOD("thermal", 522, R8A774B1_CLK_CP), DEF_MOD("pwm", 523, R8A774B1_CLK_S0D12), DEF_MOD("fcpvd1", 602, R8A774B1_CLK_S0D2), DEF_MOD("fcpvd0", 603, R8A774B1_CLK_S0D2), DEF_MOD("fcpvb0", 607, R8A774B1_CLK_S0D1), DEF_MOD("fcpvi0", 611, R8A774B1_CLK_S0D1), DEF_MOD("fcpf0", 615, R8A774B1_CLK_S0D1), DEF_MOD("fcpcs", 619, R8A774B1_CLK_S0D2), DEF_MOD("vspd1", 622, R8A774B1_CLK_S0D2), DEF_MOD("vspd0", 623, R8A774B1_CLK_S0D2), DEF_MOD("vspb", 626, R8A774B1_CLK_S0D1), DEF_MOD("vspi0", 631, R8A774B1_CLK_S0D1), DEF_MOD("ehci1", 702, R8A774B1_CLK_S3D2), DEF_MOD("ehci0", 703, R8A774B1_CLK_S3D2), DEF_MOD("hsusb", 704, R8A774B1_CLK_S3D2), DEF_MOD("csi20", 714, R8A774B1_CLK_CSI0), DEF_MOD("csi40", 716, R8A774B1_CLK_CSI0), DEF_MOD("du3", 721, R8A774B1_CLK_S2D1), DEF_MOD("du1", 723, R8A774B1_CLK_S2D1), DEF_MOD("du0", 724, R8A774B1_CLK_S2D1), DEF_MOD("lvds", 727, R8A774B1_CLK_S2D1), DEF_MOD("hdmi0", 729, R8A774B1_CLK_HDMI), DEF_MOD("vin7", 804, R8A774B1_CLK_S0D2), DEF_MOD("vin6", 805, R8A774B1_CLK_S0D2), DEF_MOD("vin5", 806, R8A774B1_CLK_S0D2), DEF_MOD("vin4", 807, R8A774B1_CLK_S0D2), DEF_MOD("vin3", 808, R8A774B1_CLK_S0D2), DEF_MOD("vin2", 809, R8A774B1_CLK_S0D2), DEF_MOD("vin1", 810, R8A774B1_CLK_S0D2), DEF_MOD("vin0", 811, R8A774B1_CLK_S0D2), DEF_MOD("etheravb", 812, R8A774B1_CLK_S0D6), DEF_MOD("sata0", 815, R8A774B1_CLK_S3D2), DEF_MOD("gpio7", 905, R8A774B1_CLK_S3D4), DEF_MOD("gpio6", 906, R8A774B1_CLK_S3D4), DEF_MOD("gpio5", 907, R8A774B1_CLK_S3D4), DEF_MOD("gpio4", 908, R8A774B1_CLK_S3D4), DEF_MOD("gpio3", 909, R8A774B1_CLK_S3D4), DEF_MOD("gpio2", 910, R8A774B1_CLK_S3D4), DEF_MOD("gpio1", 911, R8A774B1_CLK_S3D4), DEF_MOD("gpio0", 912, R8A774B1_CLK_S3D4), DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2), DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4), DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4), DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6), DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6), DEF_MOD("adg", 922, R8A774B1_CLK_S0D4), DEF_MOD("iic-pmic", 926, R8A774B1_CLK_CP), DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6), DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6), DEF_MOD("i2c2", 929, R8A774B1_CLK_S3D2), DEF_MOD("i2c1", 930, R8A774B1_CLK_S3D2), DEF_MOD("i2c0", 931, R8A774B1_CLK_S3D2), DEF_MOD("ssi-all", 1005, R8A774B1_CLK_S3D4), DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), DEF_MOD("scu-all", 1017, R8A774B1_CLK_S3D4), DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), }; static const unsigned int r8a774b1_crit_mod_clks[] __initconst = { MOD_CLK_ID(402), /* RWDT */ MOD_CLK_ID(408), /* INTC-AP (GIC) */ }; /* * CPG Clock Data */ /* * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC * 14 13 19 17 (MHz) *----------------------------------------------------------------- * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16 * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16 * 0 0 1 0 Prohibited setting * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16 * 0 1 0 0 20 x 1 x150 x160 x160 x120 /19 * 0 1 0 1 20 x 1 x150 x160 x106 x120 /19 * 0 1 1 0 Prohibited setting * 0 1 1 1 20 x 1 x150 x160 x160 x120 /19 * 1 0 0 0 25 x 1 x120 x128 x128 x96 /24 * 1 0 0 1 25 x 1 x120 x128 x84 x96 /24 * 1 0 1 0 Prohibited setting * 1 0 1 1 25 x 1 x120 x128 x128 x96 /24 * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32 * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32 * 1 1 1 0 Prohibited setting * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32 */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ (((md) & BIT(13)) >> 11) | \ (((md) & BIT(19)) >> 18) | \ (((md) & BIT(17)) >> 17)) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ { 1, 192, 1, 192, 1, 16, }, { 1, 192, 1, 128, 1, 16, }, { 0, /* Prohibited setting */ }, { 1, 192, 1, 192, 1, 16, }, { 1, 160, 1, 160, 1, 19, }, { 1, 160, 1, 106, 1, 19, }, { 0, /* Prohibited setting */ }, { 1, 160, 1, 160, 1, 19, }, { 1, 128, 1, 128, 1, 24, }, { 1, 128, 1, 84, 1, 24, }, { 0, /* Prohibited setting */ }, { 1, 128, 1, 128, 1, 24, }, { 2, 192, 1, 192, 1, 32, }, { 2, 192, 1, 128, 1, 32, }, { 0, /* Prohibited setting */ }, { 2, 192, 1, 192, 1, 32, }, }; static int __init r8a774b1_cpg_mssr_init(struct device *dev) { const struct rcar_gen3_cpg_pll_config *cpg_pll_config; u32 cpg_mode; int error; error = rcar_rst_read_mode_pins(&cpg_mode); if (error) return error; cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; if (!cpg_pll_config->extal_div) { dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); return -EINVAL; } return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); } const struct cpg_mssr_info r8a774b1_cpg_mssr_info __initconst = { /* Core Clocks */ .core_clks = r8a774b1_core_clks, .num_core_clks = ARRAY_SIZE(r8a774b1_core_clks), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Module Clocks */ .mod_clks = r8a774b1_mod_clks, .num_mod_clks = ARRAY_SIZE(r8a774b1_mod_clks), .num_hw_mod_clks = 12 * 32, /* Critical Module Clocks */ .crit_mod_clks = r8a774b1_crit_mod_clks, .num_crit_mod_clks = ARRAY_SIZE(r8a774b1_crit_mod_clks), /* Callbacks */ .init = r8a774b1_cpg_mssr_init, .cpg_clk_register = rcar_gen3_cpg_clk_register, };
linux-master
drivers/clk/renesas/r8a774b1-cpg-mssr.c
// SPDX-License-Identifier: GPL-2.0 /* * R7S9210 Clock Pulse Generator / Module Standby * * Based on r8a7795-cpg-mssr.c * * Copyright (C) 2018 Chris Brandt * Copyright (C) 2018 Renesas Electronics Corp. * */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/io.h> #include <dt-bindings/clock/r7s9210-cpg-mssr.h> #include "renesas-cpg-mssr.h" #define CPG_FRQCR 0x00 static u8 cpg_mode; /* Internal Clock ratio table */ static const struct { unsigned int i; unsigned int g; unsigned int b; unsigned int p1; /* p0 is always 32 */; } ratio_tab[5] = { /* I, G, B, P1 */ { 2, 4, 8, 16}, /* FRQCR = 0x012 */ { 4, 4, 8, 16}, /* FRQCR = 0x112 */ { 8, 4, 8, 16}, /* FRQCR = 0x212 */ { 16, 8, 16, 16}, /* FRQCR = 0x322 */ { 16, 16, 32, 32}, /* FRQCR = 0x333 */ }; enum rz_clk_types { CLK_TYPE_RZA_MAIN = CLK_TYPE_CUSTOM, CLK_TYPE_RZA_PLL, }; enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R7S9210_CLK_P0, /* External Input Clocks */ CLK_EXTAL, /* Internal Core Clocks */ CLK_MAIN, CLK_PLL, /* Module Clocks */ MOD_CLK_BASE }; static struct cpg_core_clk r7s9210_early_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), /* Internal Core Clocks */ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_RZA_MAIN, CLK_EXTAL), DEF_BASE(".pll", CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN), /* Core Clock Outputs */ DEF_FIXED("p1c", R7S9210_CLK_P1C, CLK_PLL, 16, 1), }; static const struct mssr_mod_clk r7s9210_early_mod_clks[] __initconst = { DEF_MOD_STB("ostm2", 34, R7S9210_CLK_P1C), DEF_MOD_STB("ostm1", 35, R7S9210_CLK_P1C), DEF_MOD_STB("ostm0", 36, R7S9210_CLK_P1C), }; static struct cpg_core_clk r7s9210_core_clks[] = { /* Core Clock Outputs */ DEF_FIXED("i", R7S9210_CLK_I, CLK_PLL, 2, 1), DEF_FIXED("g", R7S9210_CLK_G, CLK_PLL, 4, 1), DEF_FIXED("b", R7S9210_CLK_B, CLK_PLL, 8, 1), DEF_FIXED("p1", R7S9210_CLK_P1, CLK_PLL, 16, 1), DEF_FIXED("p0", R7S9210_CLK_P0, CLK_PLL, 32, 1), }; static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = { DEF_MOD_STB("scif4", 43, R7S9210_CLK_P1C), DEF_MOD_STB("scif3", 44, R7S9210_CLK_P1C), DEF_MOD_STB("scif2", 45, R7S9210_CLK_P1C), DEF_MOD_STB("scif1", 46, R7S9210_CLK_P1C), DEF_MOD_STB("scif0", 47, R7S9210_CLK_P1C), DEF_MOD_STB("usb1", 60, R7S9210_CLK_B), DEF_MOD_STB("usb0", 61, R7S9210_CLK_B), DEF_MOD_STB("ether1", 64, R7S9210_CLK_B), DEF_MOD_STB("ether0", 65, R7S9210_CLK_B), DEF_MOD_STB("spibsc", 83, R7S9210_CLK_P1), DEF_MOD_STB("i2c3", 84, R7S9210_CLK_P1), DEF_MOD_STB("i2c2", 85, R7S9210_CLK_P1), DEF_MOD_STB("i2c1", 86, R7S9210_CLK_P1), DEF_MOD_STB("i2c0", 87, R7S9210_CLK_P1), DEF_MOD_STB("spi2", 95, R7S9210_CLK_P1), DEF_MOD_STB("spi1", 96, R7S9210_CLK_P1), DEF_MOD_STB("spi0", 97, R7S9210_CLK_P1), DEF_MOD_STB("sdhi11", 100, R7S9210_CLK_B), DEF_MOD_STB("sdhi10", 101, R7S9210_CLK_B), DEF_MOD_STB("sdhi01", 102, R7S9210_CLK_B), DEF_MOD_STB("sdhi00", 103, R7S9210_CLK_B), }; /* The clock dividers in the table vary based on DT and register settings */ static void __init r7s9210_update_clk_table(struct clk *extal_clk, void __iomem *base) { int i; u16 frqcr; u8 index; /* If EXTAL is above 12MHz, then we know it is Mode 1 */ if (clk_get_rate(extal_clk) > 12000000) cpg_mode = 1; frqcr = readl(base + CPG_FRQCR) & 0xFFF; if (frqcr == 0x012) index = 0; else if (frqcr == 0x112) index = 1; else if (frqcr == 0x212) index = 2; else if (frqcr == 0x322) index = 3; else if (frqcr == 0x333) index = 4; else BUG_ON(1); /* Illegal FRQCR value */ for (i = 0; i < ARRAY_SIZE(r7s9210_core_clks); i++) { switch (r7s9210_core_clks[i].id) { case R7S9210_CLK_I: r7s9210_core_clks[i].div = ratio_tab[index].i; break; case R7S9210_CLK_G: r7s9210_core_clks[i].div = ratio_tab[index].g; break; case R7S9210_CLK_B: r7s9210_core_clks[i].div = ratio_tab[index].b; break; case R7S9210_CLK_P1: case R7S9210_CLK_P1C: r7s9210_core_clks[i].div = ratio_tab[index].p1; break; case R7S9210_CLK_P0: r7s9210_core_clks[i].div = 32; break; } } } static struct clk * __init rza2_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core, const struct cpg_mssr_info *info, struct clk **clks, void __iomem *base, struct raw_notifier_head *notifiers) { struct clk *parent; unsigned int mult = 1; unsigned int div = 1; parent = clks[core->parent]; if (IS_ERR(parent)) return ERR_CAST(parent); switch (core->id) { case CLK_MAIN: break; case CLK_PLL: if (cpg_mode) mult = 44; /* Divider 1 is 1/2 */ else mult = 88; /* Divider 1 is 1 */ break; default: return ERR_PTR(-EINVAL); } if (core->id == CLK_MAIN) r7s9210_update_clk_table(parent, base); return clk_register_fixed_factor(NULL, core->name, __clk_get_name(parent), 0, mult, div); } const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = { /* Early Clocks */ .early_core_clks = r7s9210_early_core_clks, .num_early_core_clks = ARRAY_SIZE(r7s9210_early_core_clks), .early_mod_clks = r7s9210_early_mod_clks, .num_early_mod_clks = ARRAY_SIZE(r7s9210_early_mod_clks), /* Core Clocks */ .core_clks = r7s9210_core_clks, .num_core_clks = ARRAY_SIZE(r7s9210_core_clks), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Module Clocks */ .mod_clks = r7s9210_mod_clks, .num_mod_clks = ARRAY_SIZE(r7s9210_mod_clks), .num_hw_mod_clks = 11 * 32, /* includes STBCR0 which doesn't exist */ /* Callbacks */ .cpg_clk_register = rza2_cpg_clk_register, /* RZ/A2 has Standby Control Registers */ .reg_layout = CLK_REG_LAYOUT_RZ_A, }; static void __init r7s9210_cpg_mssr_early_init(struct device_node *np) { cpg_mssr_early_init(np, &r7s9210_cpg_mssr_info); } CLK_OF_DECLARE_DRIVER(cpg_mstp_clks, "renesas,r7s9210-cpg-mssr", r7s9210_cpg_mssr_early_init);
linux-master
drivers/clk/renesas/r7s9210-cpg-mssr.c
// SPDX-License-Identifier: GPL-2.0 /* * r8a7779 Core CPG Clocks * * Copyright (C) 2013, 2014 Horms Solutions Ltd. * * Contact: Simon Horman <[email protected]> */ #include <linux/clk-provider.h> #include <linux/clk/renesas.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/soc/renesas/rcar-rst.h> #include <dt-bindings/clock/r8a7779-clock.h> #define CPG_NUM_CLOCKS (R8A7779_CLK_OUT + 1) /* ----------------------------------------------------------------------------- * CPG Clock Data */ /* * MD1 = 1 MD1 = 0 * (PLLA = 1500) (PLLA = 1600) * (MHz) (MHz) *------------------------------------------------+-------------------- * clkz 1000 (2/3) 800 (1/2) * clkzs 250 (1/6) 200 (1/8) * clki 750 (1/2) 800 (1/2) * clks 250 (1/6) 200 (1/8) * clks1 125 (1/12) 100 (1/16) * clks3 187.5 (1/8) 200 (1/8) * clks4 93.7 (1/16) 100 (1/16) * clkp 62.5 (1/24) 50 (1/32) * clkg 62.5 (1/24) 66.6 (1/24) * clkb, CLKOUT * (MD2 = 0) 62.5 (1/24) 66.6 (1/24) * (MD2 = 1) 41.6 (1/36) 50 (1/32) */ #define CPG_CLK_CONFIG_INDEX(md) (((md) & (BIT(2)|BIT(1))) >> 1) struct cpg_clk_config { unsigned int z_mult; unsigned int z_div; unsigned int zs_and_s_div; unsigned int s1_div; unsigned int p_div; unsigned int b_and_out_div; }; static const struct cpg_clk_config cpg_clk_configs[4] __initconst = { { 1, 2, 8, 16, 32, 24 }, { 2, 3, 6, 12, 24, 24 }, { 1, 2, 8, 16, 32, 32 }, { 2, 3, 6, 12, 24, 36 }, }; /* * MD PLLA Ratio * 12 11 *------------------------ * 0 0 x42 * 0 1 x48 * 1 0 x56 * 1 1 x64 */ #define CPG_PLLA_MULT_INDEX(md) (((md) & (BIT(12)|BIT(11))) >> 11) static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 }; /* ----------------------------------------------------------------------------- * Initialization */ static struct clk * __init r8a7779_cpg_register_clock(struct device_node *np, const struct cpg_clk_config *config, unsigned int plla_mult, const char *name) { const char *parent_name = "plla"; unsigned int mult = 1; unsigned int div = 1; if (!strcmp(name, "plla")) { parent_name = of_clk_get_parent_name(np, 0); mult = plla_mult; } else if (!strcmp(name, "z")) { div = config->z_div; mult = config->z_mult; } else if (!strcmp(name, "zs") || !strcmp(name, "s")) { div = config->zs_and_s_div; } else if (!strcmp(name, "s1")) { div = config->s1_div; } else if (!strcmp(name, "p")) { div = config->p_div; } else if (!strcmp(name, "b") || !strcmp(name, "out")) { div = config->b_and_out_div; } else { return ERR_PTR(-EINVAL); } return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div); } static void __init r8a7779_cpg_clocks_init(struct device_node *np) { const struct cpg_clk_config *config; struct clk_onecell_data *data; struct clk **clks; unsigned int i, plla_mult; int num_clks; u32 mode; if (rcar_rst_read_mode_pins(&mode)) return; num_clks = of_property_count_strings(np, "clock-output-names"); if (num_clks < 0) { pr_err("%s: failed to count clocks\n", __func__); return; } data = kzalloc(sizeof(*data), GFP_KERNEL); clks = kcalloc(CPG_NUM_CLOCKS, sizeof(*clks), GFP_KERNEL); if (data == NULL || clks == NULL) { /* We're leaking memory on purpose, there's no point in cleaning * up as the system won't boot anyway. */ return; } data->clks = clks; data->clk_num = num_clks; config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)]; plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)]; for (i = 0; i < num_clks; ++i) { const char *name; struct clk *clk; of_property_read_string_index(np, "clock-output-names", i, &name); clk = r8a7779_cpg_register_clock(np, config, plla_mult, name); if (IS_ERR(clk)) pr_err("%s: failed to register %pOFn %s clock (%ld)\n", __func__, np, name, PTR_ERR(clk)); else data->clks[i] = clk; } of_clk_add_provider(np, of_clk_src_onecell_get, data); cpg_mstp_add_clk_domain(np); } CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks", r8a7779_cpg_clocks_init);
linux-master
drivers/clk/renesas/clk-r8a7779.c
// SPDX-License-Identifier: GPL-2.0 /* * RZ/G2L CPG driver * * Copyright (C) 2021 Renesas Electronics Corp. */ #include <linux/clk-provider.h> #include <linux/device.h> #include <linux/init.h> #include <linux/kernel.h> #include <dt-bindings/clock/r9a07g044-cpg.h> #include <dt-bindings/clock/r9a07g054-cpg.h> #include "rzg2l-cpg.h" enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A, /* External Input Clocks */ CLK_EXTAL, /* Internal Core Clocks */ CLK_OSC_DIV1000, CLK_PLL1, CLK_PLL2, CLK_PLL2_DIV2, CLK_PLL2_DIV2_8, CLK_PLL2_DIV2_10, CLK_PLL3, CLK_PLL3_400, CLK_PLL3_533, CLK_M2_DIV2, CLK_PLL3_DIV2, CLK_PLL3_DIV2_2, CLK_PLL3_DIV2_4, CLK_PLL3_DIV2_4_2, CLK_SEL_PLL3_3, CLK_DIV_PLL3_C, CLK_PLL4, CLK_PLL5, CLK_PLL5_FOUTPOSTDIV, CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUT3, CLK_PLL5_250, CLK_PLL6, CLK_PLL6_250, CLK_P1_DIV2, CLK_PLL2_800, CLK_PLL2_SDHI_533, CLK_PLL2_SDHI_400, CLK_PLL2_SDHI_266, CLK_SD0_DIV4, CLK_SD1_DIV4, CLK_SEL_GPU2, CLK_SEL_PLL5_4, CLK_DSI_DIV, CLK_PLL2_533, CLK_PLL2_533_DIV2, CLK_DIV_DSI_LPCLK, /* Module Clocks */ MOD_CLK_BASE, }; /* Divider tables */ static const struct clk_div_table dtable_1_8[] = { {0, 1}, {1, 2}, {2, 4}, {3, 8}, {0, 0}, }; static const struct clk_div_table dtable_1_32[] = { {0, 1}, {1, 2}, {2, 4}, {3, 8}, {4, 32}, {0, 0}, }; static const struct clk_div_table dtable_16_128[] = { {0, 16}, {1, 32}, {2, 64}, {3, 128}, {0, 0}, }; /* Mux clock tables */ static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" }; static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; static const struct { struct cpg_core_clk common[56]; #ifdef CONFIG_CLK_R9A07G054 struct cpg_core_clk drp[0]; #endif } core_clks __initconst = { .common = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), /* Internal Core Clocks */ DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1), DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3), DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6), DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2), DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), DEF_FIXED(".pll2_533_div2", CLK_PLL2_533_DIV2, CLK_PLL2_533, 1, 2), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2), DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32), DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2), DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), DEF_MUX_RO(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, sel_gpu2), DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL), DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2), DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4), DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2, DIVDSILPCLK, dtable_16_128), /* Core output clk */ DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8), DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32), DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2), DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32), DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2), DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32), DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2), DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, sel_shdi), DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, sel_shdi), DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8), DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1), DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2), DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2), DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT), DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1), DEF_FIXED("M4", R9A07G044_CLK_M4, CLK_DIV_DSI_LPCLK, 1, 1), }, #ifdef CONFIG_CLK_R9A07G054 .drp = { }, #endif }; static const struct { struct rzg2l_mod_clk common[79]; #ifdef CONFIG_CLK_R9A07G054 struct rzg2l_mod_clk drp[0]; #endif } mod_clks = { .common = { DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1, 0x514, 0), DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2, 0x518, 0), DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, 0x518, 1), DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1, 0x52c, 0), DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2, 0x52c, 1), DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0, 0x534, 0), DEF_MOD("ostm1_pclk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0, 0x534, 1), DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, 0x534, 2), DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0, 0x538, 0), DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0, 0x540, 0), DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0, 0x544, 0), DEF_MOD("poeg_b_clkp", R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0, 0x544, 1), DEF_MOD("poeg_c_clkp", R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0, 0x544, 2), DEF_MOD("poeg_d_clkp", R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0, 0x544, 3), DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0, 0x548, 0), DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK, 0x548, 1), DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0, 0x548, 2), DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK, 0x548, 3), DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1, 0x550, 0), DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0, 0x550, 1), DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1), DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0, 0x554, 2), DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1, 0x554, 3), DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4), DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5), DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1, 0x554, 6), DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1, 0x554, 7), DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G, 0x558, 0), DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1, 0x558, 1), DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, 0x558, 2), DEF_MOD("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2, 0x564, 0), DEF_MOD("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2, 0x564, 1), DEF_MOD("cru_pclk", R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT, 0x564, 2), DEF_MOD("cru_aclk", R9A07G044_CRU_ACLK, R9A07G044_CLK_M0, 0x564, 3), DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1, 0x568, 0), DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2, 0x568, 1), DEF_MOD("dsi_aclk", R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1, 0x568, 2), DEF_MOD("dsi_pclk", R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2, 0x568, 3), DEF_MOD("dsi_vclk", R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3, 0x568, 4), DEF_MOD("dsi_lpclk", R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4, 0x568, 5), DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0, 0x56c, 0), DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT, 0x56c, 0), DEF_MOD("lcdc_clk_d", R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3, 0x56c, 1), DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0, 0x570, 0), DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0, 0x570, 1), DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0, 0x570, 2), DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0, 0x570, 3), DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0, 0x570, 4), DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0, 0x570, 5), DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0, 0x570, 6), DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0, 0x570, 7), DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1, 0x578, 0), DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1, 0x578, 1), DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1, 0x578, 2), DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1, 0x578, 3), DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0, 0x57c, 0), DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT, 0x57c, 0), DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0, 0x57c, 1), DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT, 0x57c, 1), DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0, 0x580, 0), DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0, 0x580, 1), DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0, 0x580, 2), DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0, 0x580, 3), DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0, 0x584, 0), DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0, 0x584, 1), DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0, 0x584, 2), DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0, 0x584, 3), DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0, 0x584, 4), DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0, 0x588, 0), DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0, 0x588, 1), DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0, 0x590, 0), DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0, 0x590, 1), DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0, 0x590, 2), DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0, 0x594, 0), DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK, 0x598, 0), DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU, 0x5a8, 0), DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0, 0x5a8, 1), DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU, 0x5ac, 0), }, #ifdef CONFIG_CLK_R9A07G054 .drp = { }, #endif }; static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1), DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0), DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0), DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1), DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0), DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2), DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0), DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0), DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0), DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1), DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2), DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3), DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0), DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1), DEF_RST(R9A07G044_SPI_RST, 0x850, 0), DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0), DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1), DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2), DEF_RST(R9A07G044_CRU_CMN_RSTB, 0x864, 0), DEF_RST(R9A07G044_CRU_PRESETN, 0x864, 1), DEF_RST(R9A07G044_CRU_ARESETN, 0x864, 2), DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0), DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1), DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2), DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0), DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0), DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1), DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2), DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3), DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0), DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1), DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2), DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3), DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0), DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1), DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0), DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1), DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2), DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3), DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0), DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1), DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2), DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3), DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4), DEF_RST(R9A07G044_SCI0_RST, 0x888, 0), DEF_RST(R9A07G044_SCI1_RST, 0x888, 1), DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0), DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1), DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2), DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0), DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1), DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0), DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2), DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0), DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1), DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0), }; static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A07G044_GIC600_GICCLK, MOD_CLK_BASE + R9A07G044_IA55_CLK, MOD_CLK_BASE + R9A07G044_DMAC_ACLK, }; static const unsigned int r9a07g044_no_pm_mod_clks[] = { MOD_CLK_BASE + R9A07G044_CRU_SYSCLK, MOD_CLK_BASE + R9A07G044_CRU_VCLK, }; #ifdef CONFIG_CLK_R9A07G044 const struct rzg2l_cpg_info r9a07g044_cpg_info = { /* Core Clocks */ .core_clks = core_clks.common, .num_core_clks = ARRAY_SIZE(core_clks.common), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Critical Module Clocks */ .crit_mod_clks = r9a07g044_crit_mod_clks, .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), /* Module Clocks */ .mod_clks = mod_clks.common, .num_mod_clks = ARRAY_SIZE(mod_clks.common), .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1, /* No PM Module Clocks */ .no_pm_mod_clks = r9a07g044_no_pm_mod_clks, .num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks), /* Resets */ .resets = r9a07g044_resets, .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */ .has_clk_mon_regs = true, }; #endif #ifdef CONFIG_CLK_R9A07G054 const struct rzg2l_cpg_info r9a07g054_cpg_info = { /* Core Clocks */ .core_clks = core_clks.common, .num_core_clks = ARRAY_SIZE(core_clks.common) + ARRAY_SIZE(core_clks.drp), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Critical Module Clocks */ .crit_mod_clks = r9a07g044_crit_mod_clks, .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), /* Module Clocks */ .mod_clks = mod_clks.common, .num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp), .num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1, /* No PM Module Clocks */ .no_pm_mod_clks = r9a07g044_no_pm_mod_clks, .num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks), /* Resets */ .resets = r9a07g044_resets, .num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */ .has_clk_mon_regs = true, }; #endif
linux-master
drivers/clk/renesas/r9a07g044-cpg.c
// SPDX-License-Identifier: GPL-2.0 /* * r8a77980 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2018 Renesas Electronics Corp. * Copyright (C) 2018 Cogent Embedded, Inc. * * Based on r8a7795-cpg-mssr.c * * Copyright (C) 2015 Glider bvba */ #include <linux/device.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/soc/renesas/rcar-rst.h> #include <linux/sys_soc.h> #include <dt-bindings/clock/r8a77980-cpg-mssr.h> #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A77980_CLK_OSC, /* External Input Clocks */ CLK_EXTAL, CLK_EXTALR, /* Internal Core Clocks */ CLK_MAIN, CLK_PLL1, CLK_PLL2, CLK_PLL3, CLK_PLL1_DIV2, CLK_PLL1_DIV4, CLK_S0, CLK_S1, CLK_S2, CLK_S3, CLK_SDSRC, CLK_RPCSRC, CLK_OCO, /* Module Clocks */ MOD_CLK_BASE }; static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("extalr", CLK_EXTALR), /* Internal Core Clocks */ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_RATE(".oco", CLK_OCO, 32768), /* Core Clock Outputs */ DEF_FIXED("z2", R8A77980_CLK_Z2, CLK_PLL2, 4, 1), DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1), DEF_FIXED("zx", R8A77980_CLK_ZX, CLK_PLL1_DIV2, 2, 1), DEF_FIXED("s0d1", R8A77980_CLK_S0D1, CLK_S0, 1, 1), DEF_FIXED("s0d2", R8A77980_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A77980_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A77980_CLK_S0D4, CLK_S0, 4, 1), DEF_FIXED("s0d6", R8A77980_CLK_S0D6, CLK_S0, 6, 1), DEF_FIXED("s0d12", R8A77980_CLK_S0D12, CLK_S0, 12, 1), DEF_FIXED("s0d24", R8A77980_CLK_S0D24, CLK_S0, 24, 1), DEF_FIXED("s1d1", R8A77980_CLK_S1D1, CLK_S1, 1, 1), DEF_FIXED("s1d2", R8A77980_CLK_S1D2, CLK_S1, 2, 1), DEF_FIXED("s1d4", R8A77980_CLK_S1D4, CLK_S1, 4, 1), DEF_FIXED("s2d1", R8A77980_CLK_S2D1, CLK_S2, 1, 1), DEF_FIXED("s2d2", R8A77980_CLK_S2D2, CLK_S2, 2, 1), DEF_FIXED("s2d4", R8A77980_CLK_S2D4, CLK_S2, 4, 1), DEF_FIXED("s3d1", R8A77980_CLK_S3D1, CLK_S3, 1, 1), DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1), DEF_GEN3_SDH("sd0h", R8A77980_CLK_SD0H, CLK_SDSRC, 0x0074), DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, R8A77980_CLK_SD0H, 0x0074), DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77980_CLK_RPC), DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A77980_CLK_CPEX, CLK_EXTAL, 2, 1), DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244), DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8), DEF_GEN3_MDSEL("r", R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), }; static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6), DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6), DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6), DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6), DEF_MOD("tmu0", 125, R8A77980_CLK_CP), DEF_MOD("scif4", 203, R8A77980_CLK_S3D4), DEF_MOD("scif3", 204, R8A77980_CLK_S3D4), DEF_MOD("scif1", 206, R8A77980_CLK_S3D4), DEF_MOD("scif0", 207, R8A77980_CLK_S3D4), DEF_MOD("msiof3", 208, R8A77980_CLK_MSO), DEF_MOD("msiof2", 209, R8A77980_CLK_MSO), DEF_MOD("msiof1", 210, R8A77980_CLK_MSO), DEF_MOD("msiof0", 211, R8A77980_CLK_MSO), DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3), DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3), DEF_MOD("cmt3", 300, R8A77980_CLK_R), DEF_MOD("cmt2", 301, R8A77980_CLK_R), DEF_MOD("cmt1", 302, R8A77980_CLK_R), DEF_MOD("cmt0", 303, R8A77980_CLK_R), DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4), DEF_MOD("sdif", 314, R8A77980_CLK_SD0), DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2), DEF_MOD("rwdt", 402, R8A77980_CLK_R), DEF_MOD("intc-ex", 407, R8A77980_CLK_CP), DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3), DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1), DEF_MOD("hscif2", 518, R8A77980_CLK_S3D1), DEF_MOD("hscif1", 519, R8A77980_CLK_S3D1), DEF_MOD("hscif0", 520, R8A77980_CLK_S3D1), DEF_MOD("imp4", 521, R8A77980_CLK_S1D1), DEF_MOD("thermal", 522, R8A77980_CLK_CP), DEF_MOD("pwm", 523, R8A77980_CLK_S0D12), DEF_MOD("impdma1", 526, R8A77980_CLK_S1D1), DEF_MOD("impdma0", 527, R8A77980_CLK_S1D1), DEF_MOD("imp-ocv4", 528, R8A77980_CLK_S1D1), DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1), DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1), DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1), DEF_MOD("vin15", 604, R8A77980_CLK_S2D1), DEF_MOD("vin14", 605, R8A77980_CLK_S2D1), DEF_MOD("vin13", 608, R8A77980_CLK_S2D1), DEF_MOD("vin12", 612, R8A77980_CLK_S2D1), DEF_MOD("vin11", 618, R8A77980_CLK_S2D1), DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1), DEF_MOD("vin10", 625, R8A77980_CLK_S2D1), DEF_MOD("vin9", 627, R8A77980_CLK_S2D1), DEF_MOD("vin8", 628, R8A77980_CLK_S2D1), DEF_MOD("csi41", 715, R8A77980_CLK_CSI0), DEF_MOD("csi40", 716, R8A77980_CLK_CSI0), DEF_MOD("du0", 724, R8A77980_CLK_S2D1), DEF_MOD("lvds", 727, R8A77980_CLK_S2D1), DEF_MOD("vin7", 804, R8A77980_CLK_S2D1), DEF_MOD("vin6", 805, R8A77980_CLK_S2D1), DEF_MOD("vin5", 806, R8A77980_CLK_S2D1), DEF_MOD("vin4", 807, R8A77980_CLK_S2D1), DEF_MOD("vin3", 808, R8A77980_CLK_S2D1), DEF_MOD("vin2", 809, R8A77980_CLK_S2D1), DEF_MOD("vin1", 810, R8A77980_CLK_S2D1), DEF_MOD("vin0", 811, R8A77980_CLK_S2D1), DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2), DEF_MOD("gether", 813, R8A77980_CLK_S3D2), DEF_MOD("imp3", 824, R8A77980_CLK_S1D1), DEF_MOD("imp2", 825, R8A77980_CLK_S1D1), DEF_MOD("imp1", 826, R8A77980_CLK_S1D1), DEF_MOD("imp0", 827, R8A77980_CLK_S1D1), DEF_MOD("imp-ocv1", 828, R8A77980_CLK_S1D1), DEF_MOD("imp-ocv0", 829, R8A77980_CLK_S1D1), DEF_MOD("impram", 830, R8A77980_CLK_S1D1), DEF_MOD("impcnn", 831, R8A77980_CLK_S1D1), DEF_MOD("gpio5", 907, R8A77980_CLK_CP), DEF_MOD("gpio4", 908, R8A77980_CLK_CP), DEF_MOD("gpio3", 909, R8A77980_CLK_CP), DEF_MOD("gpio2", 910, R8A77980_CLK_CP), DEF_MOD("gpio1", 911, R8A77980_CLK_CP), DEF_MOD("gpio0", 912, R8A77980_CLK_CP), DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2), DEF_MOD("rpc-if", 917, R8A77980_CLK_RPCD2), DEF_MOD("i2c5", 919, R8A77980_CLK_S0D6), DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6), DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6), DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2), DEF_MOD("i2c1", 930, R8A77980_CLK_S3D2), DEF_MOD("i2c0", 931, R8A77980_CLK_S3D2), }; static const unsigned int r8a77980_crit_mod_clks[] __initconst = { MOD_CLK_ID(402), /* RWDT */ MOD_CLK_ID(408), /* INTC-AP (GIC) */ }; /* * CPG Clock Data */ /* * MD EXTAL PLL2 PLL1 PLL3 OSC * 14 13 (MHz) * -------------------------------------------------------- * 0 0 16.66 x 1 x240 x192 x192 /16 * 0 1 20 x 1 x200 x160 x160 /19 * 1 0 27 x 1 x148 x118 x118 /26 * 1 1 33.33 / 2 x240 x192 x192 /32 */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ (((md) & BIT(13)) >> 13)) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = { /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ { 1, 192, 1, 192, 1, 16, }, { 1, 160, 1, 160, 1, 19, }, { 1, 118, 1, 118, 1, 26, }, { 2, 192, 1, 192, 1, 32, }, }; static int __init r8a77980_cpg_mssr_init(struct device *dev) { const struct rcar_gen3_cpg_pll_config *cpg_pll_config; u32 cpg_mode; int error; error = rcar_rst_read_mode_pins(&cpg_mode); if (error) return error; cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); } const struct cpg_mssr_info r8a77980_cpg_mssr_info __initconst = { /* Core Clocks */ .core_clks = r8a77980_core_clks, .num_core_clks = ARRAY_SIZE(r8a77980_core_clks), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Module Clocks */ .mod_clks = r8a77980_mod_clks, .num_mod_clks = ARRAY_SIZE(r8a77980_mod_clks), .num_hw_mod_clks = 12 * 32, /* Critical Module Clocks */ .crit_mod_clks = r8a77980_crit_mod_clks, .num_crit_mod_clks = ARRAY_SIZE(r8a77980_crit_mod_clks), /* Callbacks */ .init = r8a77980_cpg_mssr_init, .cpg_clk_register = rcar_gen3_cpg_clk_register, };
linux-master
drivers/clk/renesas/r8a77980-cpg-mssr.c
// SPDX-License-Identifier: GPL-2.0 /* * sh73a0 Core CPG Clocks * * Copyright (C) 2014 Ulrich Hecht */ #include <linux/clk-provider.h> #include <linux/clk/renesas.h> #include <linux/init.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/slab.h> #include <linux/spinlock.h> struct sh73a0_cpg { struct clk_onecell_data data; spinlock_t lock; }; #define CPG_FRQCRA 0x00 #define CPG_FRQCRB 0x04 #define CPG_SD0CKCR 0x74 #define CPG_SD1CKCR 0x78 #define CPG_SD2CKCR 0x7c #define CPG_PLLECR 0xd0 #define CPG_PLL0CR 0xd8 #define CPG_PLL1CR 0x28 #define CPG_PLL2CR 0x2c #define CPG_PLL3CR 0xdc #define CPG_CKSCR 0xc0 #define CPG_DSI0PHYCR 0x6c #define CPG_DSI1PHYCR 0x70 #define CLK_ENABLE_ON_INIT BIT(0) struct div4_clk { const char *name; const char *parent; unsigned int reg; unsigned int shift; }; static const struct div4_clk div4_clks[] = { { "zg", "pll0", CPG_FRQCRA, 16 }, { "m3", "pll1", CPG_FRQCRA, 12 }, { "b", "pll1", CPG_FRQCRA, 8 }, { "m1", "pll1", CPG_FRQCRA, 4 }, { "m2", "pll1", CPG_FRQCRA, 0 }, { "zx", "pll1", CPG_FRQCRB, 12 }, { "hp", "pll1", CPG_FRQCRB, 4 }, { NULL, NULL, 0, 0 }, }; static const struct clk_div_table div4_div_table[] = { { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 7 }, { 0, 0 } }; static const struct clk_div_table z_div_table[] = { /* ZSEL == 0 */ { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, { 4, 1 }, { 5, 1 }, { 6, 1 }, { 7, 1 }, { 8, 1 }, { 9, 1 }, { 10, 1 }, { 11, 1 }, { 12, 1 }, { 13, 1 }, { 14, 1 }, { 15, 1 }, /* ZSEL == 1 */ { 16, 2 }, { 17, 3 }, { 18, 4 }, { 19, 6 }, { 20, 8 }, { 21, 12 }, { 22, 16 }, { 24, 24 }, { 27, 48 }, { 0, 0 } }; static struct clk * __init sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg, void __iomem *base, const char *name) { const struct clk_div_table *table = NULL; unsigned int shift, reg, width; const char *parent_name = NULL; unsigned int mult = 1; unsigned int div = 1; if (!strcmp(name, "main")) { /* extal1, extal1_div2, extal2, extal2_div2 */ u32 parent_idx = (readl(base + CPG_CKSCR) >> 28) & 3; parent_name = of_clk_get_parent_name(np, parent_idx >> 1); div = (parent_idx & 1) + 1; } else if (!strncmp(name, "pll", 3)) { void __iomem *enable_reg = base; u32 enable_bit = name[3] - '0'; parent_name = "main"; switch (enable_bit) { case 0: enable_reg += CPG_PLL0CR; break; case 1: enable_reg += CPG_PLL1CR; break; case 2: enable_reg += CPG_PLL2CR; break; case 3: enable_reg += CPG_PLL3CR; break; default: return ERR_PTR(-EINVAL); } if (readl(base + CPG_PLLECR) & BIT(enable_bit)) { mult = ((readl(enable_reg) >> 24) & 0x3f) + 1; /* handle CFG bit for PLL1 and PLL2 */ if (enable_bit == 1 || enable_bit == 2) if (readl(enable_reg) & BIT(20)) mult *= 2; } } else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) { u32 phy_no = name[3] - '0'; void __iomem *dsi_reg = base + (phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR); parent_name = phy_no ? "dsi1pck" : "dsi0pck"; mult = readl(dsi_reg); if (!(mult & 0x8000)) mult = 1; else mult = (mult & 0x3f) + 1; } else if (!strcmp(name, "z")) { parent_name = "pll0"; table = z_div_table; reg = CPG_FRQCRB; shift = 24; width = 5; } else { const struct div4_clk *c; for (c = div4_clks; c->name; c++) { if (!strcmp(name, c->name)) { parent_name = c->parent; table = div4_div_table; reg = c->reg; shift = c->shift; width = 4; break; } } if (!c->name) return ERR_PTR(-EINVAL); } if (!table) { return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div); } else { return clk_register_divider_table(NULL, name, parent_name, 0, base + reg, shift, width, 0, table, &cpg->lock); } } static void __init sh73a0_cpg_clocks_init(struct device_node *np) { struct sh73a0_cpg *cpg; void __iomem *base; struct clk **clks; unsigned int i; int num_clks; num_clks = of_property_count_strings(np, "clock-output-names"); if (num_clks < 0) { pr_err("%s: failed to count clocks\n", __func__); return; } cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); if (cpg == NULL || clks == NULL) { /* We're leaking memory on purpose, there's no point in cleaning * up as the system won't boot anyway. */ return; } spin_lock_init(&cpg->lock); cpg->data.clks = clks; cpg->data.clk_num = num_clks; base = of_iomap(np, 0); if (WARN_ON(base == NULL)) return; /* Set SDHI clocks to a known state */ writel(0x108, base + CPG_SD0CKCR); writel(0x108, base + CPG_SD1CKCR); writel(0x108, base + CPG_SD2CKCR); for (i = 0; i < num_clks; ++i) { const char *name; struct clk *clk; of_property_read_string_index(np, "clock-output-names", i, &name); clk = sh73a0_cpg_register_clock(np, cpg, base, name); if (IS_ERR(clk)) pr_err("%s: failed to register %pOFn %s clock (%ld)\n", __func__, np, name, PTR_ERR(clk)); else cpg->data.clks[i] = clk; } of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); } CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks", sh73a0_cpg_clocks_init);
linux-master
drivers/clk/renesas/clk-sh73a0.c
// SPDX-License-Identifier: GPL-2.0 /* * r8a774c0 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2018 Renesas Electronics Corp. * * Based on r8a77990-cpg-mssr.c * * Copyright (C) 2015 Glider bvba * Copyright (C) 2015 Renesas Electronics Corp. */ #include <linux/device.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/soc/renesas/rcar-rst.h> #include <dt-bindings/clock/r8a774c0-cpg-mssr.h> #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A774C0_CLK_CANFD, /* External Input Clocks */ CLK_EXTAL, /* Internal Core Clocks */ CLK_MAIN, CLK_PLL0, CLK_PLL1, CLK_PLL3, CLK_PLL0D4, CLK_PLL0D6, CLK_PLL0D8, CLK_PLL0D20, CLK_PLL0D24, CLK_PLL1D2, CLK_PE, CLK_S0, CLK_S1, CLK_S2, CLK_S3, CLK_SDSRC, CLK_RPCSRC, CLK_RINT, CLK_OCO, /* Module Clocks */ MOD_CLK_BASE }; static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), /* Internal Core Clocks */ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100), DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1), DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1), DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1), DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1), DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1), DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1), DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1), DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1), DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1), DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1), DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), /* Core Clock Outputs */ DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1), DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1), DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8), DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1), DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1), DEF_FIXED("s0d1", R8A774C0_CLK_S0D1, CLK_S0, 1, 1), DEF_FIXED("s0d3", R8A774C0_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d6", R8A774C0_CLK_S0D6, CLK_S0, 6, 1), DEF_FIXED("s0d12", R8A774C0_CLK_S0D12, CLK_S0, 12, 1), DEF_FIXED("s0d24", R8A774C0_CLK_S0D24, CLK_S0, 24, 1), DEF_FIXED("s1d1", R8A774C0_CLK_S1D1, CLK_S1, 1, 1), DEF_FIXED("s1d2", R8A774C0_CLK_S1D2, CLK_S1, 2, 1), DEF_FIXED("s1d4", R8A774C0_CLK_S1D4, CLK_S1, 4, 1), DEF_FIXED("s2d1", R8A774C0_CLK_S2D1, CLK_S2, 1, 1), DEF_FIXED("s2d2", R8A774C0_CLK_S2D2, CLK_S2, 2, 1), DEF_FIXED("s2d4", R8A774C0_CLK_S2D4, CLK_S2, 4, 1), DEF_FIXED("s3d1", R8A774C0_CLK_S3D1, CLK_S3, 1, 1), DEF_FIXED("s3d2", R8A774C0_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A774C0_CLK_S3D4, CLK_S3, 4, 1), DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774C0_CLK_RPC), DEF_GEN3_SDH("sd0h", R8A774C0_CLK_SD0H, CLK_SDSRC, 0x0074), DEF_GEN3_SDH("sd1h", R8A774C0_CLK_SD1H, CLK_SDSRC, 0x0078), DEF_GEN3_SDH("sd3h", R8A774C0_CLK_SD3H, CLK_SDSRC, 0x026c), DEF_GEN3_SD("sd0", R8A774C0_CLK_SD0, R8A774C0_CLK_SD0H, 0x0074), DEF_GEN3_SD("sd1", R8A774C0_CLK_SD1, R8A774C0_CLK_SD1H, 0x0078), DEF_GEN3_SD("sd3", R8A774C0_CLK_SD3, R8A774C0_CLK_SD3H, 0x026c), DEF_FIXED("cl", R8A774C0_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cp", R8A774C0_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A774C0_CLK_CPEX, CLK_EXTAL, 4, 1), DEF_DIV6_RO("osc", R8A774C0_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), DEF_GEN3_PE("s0d6c", R8A774C0_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2), DEF_GEN3_PE("s3d1c", R8A774C0_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), DEF_GEN3_PE("s3d2c", R8A774C0_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), DEF_GEN3_PE("s3d4c", R8A774C0_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), DEF_DIV6P1("canfd", R8A774C0_CLK_CANFD, CLK_PLL0D6, 0x244), DEF_DIV6P1("csi0", R8A774C0_CLK_CSI0, CLK_PLL1D2, 0x00c), DEF_DIV6P1("mso", R8A774C0_CLK_MSO, CLK_PLL1D2, 0x014), DEF_GEN3_RCKSEL("r", R8A774C0_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4), }; static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = { DEF_MOD("tmu4", 121, R8A774C0_CLK_S0D6C), DEF_MOD("tmu3", 122, R8A774C0_CLK_S3D2C), DEF_MOD("tmu2", 123, R8A774C0_CLK_S3D2C), DEF_MOD("tmu1", 124, R8A774C0_CLK_S3D2C), DEF_MOD("tmu0", 125, R8A774C0_CLK_CP), DEF_MOD("scif5", 202, R8A774C0_CLK_S3D4C), DEF_MOD("scif4", 203, R8A774C0_CLK_S3D4C), DEF_MOD("scif3", 204, R8A774C0_CLK_S3D4C), DEF_MOD("scif1", 206, R8A774C0_CLK_S3D4C), DEF_MOD("scif0", 207, R8A774C0_CLK_S3D4C), DEF_MOD("msiof3", 208, R8A774C0_CLK_MSO), DEF_MOD("msiof2", 209, R8A774C0_CLK_MSO), DEF_MOD("msiof1", 210, R8A774C0_CLK_MSO), DEF_MOD("msiof0", 211, R8A774C0_CLK_MSO), DEF_MOD("sys-dmac2", 217, R8A774C0_CLK_S3D1), DEF_MOD("sys-dmac1", 218, R8A774C0_CLK_S3D1), DEF_MOD("sys-dmac0", 219, R8A774C0_CLK_S3D1), DEF_MOD("cmt3", 300, R8A774C0_CLK_R), DEF_MOD("cmt2", 301, R8A774C0_CLK_R), DEF_MOD("cmt1", 302, R8A774C0_CLK_R), DEF_MOD("cmt0", 303, R8A774C0_CLK_R), DEF_MOD("scif2", 310, R8A774C0_CLK_S3D4C), DEF_MOD("sdif3", 311, R8A774C0_CLK_SD3), DEF_MOD("sdif1", 313, R8A774C0_CLK_SD1), DEF_MOD("sdif0", 314, R8A774C0_CLK_SD0), DEF_MOD("pcie0", 319, R8A774C0_CLK_S3D1), DEF_MOD("usb3-if0", 328, R8A774C0_CLK_S3D1), DEF_MOD("usb-dmac0", 330, R8A774C0_CLK_S3D1), DEF_MOD("usb-dmac1", 331, R8A774C0_CLK_S3D1), DEF_MOD("rwdt", 402, R8A774C0_CLK_R), DEF_MOD("intc-ex", 407, R8A774C0_CLK_CP), DEF_MOD("intc-ap", 408, R8A774C0_CLK_S0D3), DEF_MOD("audmac0", 502, R8A774C0_CLK_S1D2), DEF_MOD("hscif4", 516, R8A774C0_CLK_S3D1C), DEF_MOD("hscif3", 517, R8A774C0_CLK_S3D1C), DEF_MOD("hscif2", 518, R8A774C0_CLK_S3D1C), DEF_MOD("hscif1", 519, R8A774C0_CLK_S3D1C), DEF_MOD("hscif0", 520, R8A774C0_CLK_S3D1C), DEF_MOD("thermal", 522, R8A774C0_CLK_CP), DEF_MOD("pwm", 523, R8A774C0_CLK_S3D4C), DEF_MOD("fcpvd1", 602, R8A774C0_CLK_S1D2), DEF_MOD("fcpvd0", 603, R8A774C0_CLK_S1D2), DEF_MOD("fcpvb0", 607, R8A774C0_CLK_S0D1), DEF_MOD("fcpvi0", 611, R8A774C0_CLK_S0D1), DEF_MOD("fcpf0", 615, R8A774C0_CLK_S0D1), DEF_MOD("fcpcs", 619, R8A774C0_CLK_S0D1), DEF_MOD("vspd1", 622, R8A774C0_CLK_S1D2), DEF_MOD("vspd0", 623, R8A774C0_CLK_S1D2), DEF_MOD("vspb", 626, R8A774C0_CLK_S0D1), DEF_MOD("vspi0", 631, R8A774C0_CLK_S0D1), DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D2), DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D2), DEF_MOD("csi40", 716, R8A774C0_CLK_CSI0), DEF_MOD("du1", 723, R8A774C0_CLK_S1D1), DEF_MOD("du0", 724, R8A774C0_CLK_S1D1), DEF_MOD("lvds", 727, R8A774C0_CLK_S2D1), DEF_MOD("vin5", 806, R8A774C0_CLK_S1D2), DEF_MOD("vin4", 807, R8A774C0_CLK_S1D2), DEF_MOD("etheravb", 812, R8A774C0_CLK_S3D2), DEF_MOD("gpio6", 906, R8A774C0_CLK_S3D4), DEF_MOD("gpio5", 907, R8A774C0_CLK_S3D4), DEF_MOD("gpio4", 908, R8A774C0_CLK_S3D4), DEF_MOD("gpio3", 909, R8A774C0_CLK_S3D4), DEF_MOD("gpio2", 910, R8A774C0_CLK_S3D4), DEF_MOD("gpio1", 911, R8A774C0_CLK_S3D4), DEF_MOD("gpio0", 912, R8A774C0_CLK_S3D4), DEF_MOD("can-fd", 914, R8A774C0_CLK_S3D2), DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4), DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4), DEF_MOD("rpc-if", 917, R8A774C0_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2), DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2), DEF_MOD("adg", 922, R8A774C0_CLK_ZA2), DEF_MOD("iic-pmic", 926, R8A774C0_CLK_CP), DEF_MOD("i2c4", 927, R8A774C0_CLK_S3D2), DEF_MOD("i2c3", 928, R8A774C0_CLK_S3D2), DEF_MOD("i2c2", 929, R8A774C0_CLK_S3D2), DEF_MOD("i2c1", 930, R8A774C0_CLK_S3D2), DEF_MOD("i2c0", 931, R8A774C0_CLK_S3D2), DEF_MOD("i2c7", 1003, R8A774C0_CLK_S3D2), DEF_MOD("ssi-all", 1005, R8A774C0_CLK_S3D4), DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), DEF_MOD("scu-all", 1017, R8A774C0_CLK_S3D4), DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), }; static const unsigned int r8a774c0_crit_mod_clks[] __initconst = { MOD_CLK_ID(402), /* RWDT */ MOD_CLK_ID(408), /* INTC-AP (GIC) */ }; /* * CPG Clock Data */ /* * MD19 EXTAL (MHz) PLL0 PLL1 PLL3 *-------------------------------------------------------------------- * 0 48 x 1 x100/1 x100/3 x100/3 * 1 48 x 1 x100/1 x100/3 x58/3 */ #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = { /* EXTAL div PLL1 mult/div PLL3 mult/div */ { 1, 100, 3, 100, 3, }, { 1, 100, 3, 58, 3, }, }; static int __init r8a774c0_cpg_mssr_init(struct device *dev) { const struct rcar_gen3_cpg_pll_config *cpg_pll_config; u32 cpg_mode; int error; error = rcar_rst_read_mode_pins(&cpg_mode); if (error) return error; cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode); } const struct cpg_mssr_info r8a774c0_cpg_mssr_info __initconst = { /* Core Clocks */ .core_clks = r8a774c0_core_clks, .num_core_clks = ARRAY_SIZE(r8a774c0_core_clks), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Module Clocks */ .mod_clks = r8a774c0_mod_clks, .num_mod_clks = ARRAY_SIZE(r8a774c0_mod_clks), .num_hw_mod_clks = 12 * 32, /* Critical Module Clocks */ .crit_mod_clks = r8a774c0_crit_mod_clks, .num_crit_mod_clks = ARRAY_SIZE(r8a774c0_crit_mod_clks), /* Callbacks */ .init = r8a774c0_cpg_mssr_init, .cpg_clk_register = rcar_gen3_cpg_clk_register, };
linux-master
drivers/clk/renesas/r8a774c0-cpg-mssr.c
// SPDX-License-Identifier: GPL-2.0 /* * r8a7790 Common Clock Framework support * * Copyright (C) 2013 Renesas Solutions Corp. * * Contact: Laurent Pinchart <[email protected]> */ #include <linux/clk-provider.h> #include <linux/init.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/notifier.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/pm.h> #include <linux/slab.h> #include "clk-div6.h" #define CPG_DIV6_CKSTP BIT(8) #define CPG_DIV6_DIV(d) ((d) & 0x3f) #define CPG_DIV6_DIV_MASK 0x3f /** * struct div6_clock - CPG 6 bit divider clock * @hw: handle between common and hardware-specific interfaces * @reg: IO-remapped register * @div: divisor value (1-64) * @src_mask: Bitmask covering the register bits to select the parent clock * @nb: Notifier block to save/restore clock state for system resume * @parents: Array to map from valid parent clocks indices to hardware indices */ struct div6_clock { struct clk_hw hw; void __iomem *reg; unsigned int div; u32 src_mask; struct notifier_block nb; u8 parents[]; }; #define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw) static int cpg_div6_clock_enable(struct clk_hw *hw) { struct div6_clock *clock = to_div6_clock(hw); u32 val; val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) | CPG_DIV6_DIV(clock->div - 1); writel(val, clock->reg); return 0; } static void cpg_div6_clock_disable(struct clk_hw *hw) { struct div6_clock *clock = to_div6_clock(hw); u32 val; val = readl(clock->reg); val |= CPG_DIV6_CKSTP; /* * DIV6 clocks require the divisor field to be non-zero when stopping * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be * re-enabled later if the divisor field is changed when stopping the * clock */ if (!(val & CPG_DIV6_DIV_MASK)) val |= CPG_DIV6_DIV_MASK; writel(val, clock->reg); } static int cpg_div6_clock_is_enabled(struct clk_hw *hw) { struct div6_clock *clock = to_div6_clock(hw); return !(readl(clock->reg) & CPG_DIV6_CKSTP); } static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct div6_clock *clock = to_div6_clock(hw); return parent_rate / clock->div; } static unsigned int cpg_div6_clock_calc_div(unsigned long rate, unsigned long parent_rate) { unsigned int div; if (!rate) rate = 1; div = DIV_ROUND_CLOSEST(parent_rate, rate); return clamp(div, 1U, 64U); } static int cpg_div6_clock_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { unsigned long prate, calc_rate, diff, best_rate, best_prate; unsigned int num_parents = clk_hw_get_num_parents(hw); struct clk_hw *parent, *best_parent = NULL; unsigned int i, min_div, max_div, div; unsigned long min_diff = ULONG_MAX; for (i = 0; i < num_parents; i++) { parent = clk_hw_get_parent_by_index(hw, i); if (!parent) continue; prate = clk_hw_get_rate(parent); if (!prate) continue; min_div = max(DIV_ROUND_UP(prate, req->max_rate), 1UL); max_div = req->min_rate ? min(prate / req->min_rate, 64UL) : 64; if (max_div < min_div) continue; div = cpg_div6_clock_calc_div(req->rate, prate); div = clamp(div, min_div, max_div); calc_rate = prate / div; diff = calc_rate > req->rate ? calc_rate - req->rate : req->rate - calc_rate; if (diff < min_diff) { best_rate = calc_rate; best_parent = parent; best_prate = prate; min_diff = diff; } } if (!best_parent) return -EINVAL; req->best_parent_rate = best_prate; req->best_parent_hw = best_parent; req->rate = best_rate; return 0; } static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct div6_clock *clock = to_div6_clock(hw); unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate); u32 val; clock->div = div; val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK; /* Only program the new divisor if the clock isn't stopped. */ if (!(val & CPG_DIV6_CKSTP)) writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg); return 0; } static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) { struct div6_clock *clock = to_div6_clock(hw); unsigned int i; u8 hw_index; if (clock->src_mask == 0) return 0; hw_index = (readl(clock->reg) & clock->src_mask) >> __ffs(clock->src_mask); for (i = 0; i < clk_hw_get_num_parents(hw); i++) { if (clock->parents[i] == hw_index) return i; } pr_err("%s: %s DIV6 clock set to invalid parent %u\n", __func__, clk_hw_get_name(hw), hw_index); return 0; } static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index) { struct div6_clock *clock = to_div6_clock(hw); u32 src; if (index >= clk_hw_get_num_parents(hw)) return -EINVAL; src = clock->parents[index] << __ffs(clock->src_mask); writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg); return 0; } static const struct clk_ops cpg_div6_clock_ops = { .enable = cpg_div6_clock_enable, .disable = cpg_div6_clock_disable, .is_enabled = cpg_div6_clock_is_enabled, .get_parent = cpg_div6_clock_get_parent, .set_parent = cpg_div6_clock_set_parent, .recalc_rate = cpg_div6_clock_recalc_rate, .determine_rate = cpg_div6_clock_determine_rate, .set_rate = cpg_div6_clock_set_rate, }; static int cpg_div6_clock_notifier_call(struct notifier_block *nb, unsigned long action, void *data) { struct div6_clock *clock = container_of(nb, struct div6_clock, nb); switch (action) { case PM_EVENT_RESUME: /* * TODO: This does not yet support DIV6 clocks with multiple * parents, as the parent selection bits are not restored. * Fortunately so far such DIV6 clocks are found only on * R/SH-Mobile SoCs, while the resume functionality is only * needed on R-Car Gen3. */ if (__clk_get_enable_count(clock->hw.clk)) cpg_div6_clock_enable(&clock->hw); else cpg_div6_clock_disable(&clock->hw); return NOTIFY_OK; } return NOTIFY_DONE; } /** * cpg_div6_register - Register a DIV6 clock * @name: Name of the DIV6 clock * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8) * @parent_names: Array containing the names of the parent clocks * @reg: Mapped register used to control the DIV6 clock * @notifiers: Optional notifier chain to save/restore state for system resume */ struct clk * __init cpg_div6_register(const char *name, unsigned int num_parents, const char **parent_names, void __iomem *reg, struct raw_notifier_head *notifiers) { unsigned int valid_parents; struct clk_init_data init = {}; struct div6_clock *clock; struct clk *clk; unsigned int i; clock = kzalloc(struct_size(clock, parents, num_parents), GFP_KERNEL); if (!clock) return ERR_PTR(-ENOMEM); clock->reg = reg; /* * Read the divisor. Disabling the clock overwrites the divisor, so we * need to cache its value for the enable operation. */ clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; switch (num_parents) { case 1: /* fixed parent clock */ clock->src_mask = 0; break; case 4: /* clock with EXSRC bits 6-7 */ clock->src_mask = GENMASK(7, 6); break; case 8: /* VCLK with EXSRC bits 12-14 */ clock->src_mask = GENMASK(14, 12); break; default: pr_err("%s: invalid number of parents for DIV6 clock %s\n", __func__, name); clk = ERR_PTR(-EINVAL); goto free_clock; } /* Filter out invalid parents */ for (i = 0, valid_parents = 0; i < num_parents; i++) { if (parent_names[i]) { parent_names[valid_parents] = parent_names[i]; clock->parents[valid_parents] = i; valid_parents++; } } /* Register the clock. */ init.name = name; init.ops = &cpg_div6_clock_ops; init.parent_names = parent_names; init.num_parents = valid_parents; clock->hw.init = &init; clk = clk_register(NULL, &clock->hw); if (IS_ERR(clk)) goto free_clock; if (notifiers) { clock->nb.notifier_call = cpg_div6_clock_notifier_call; raw_notifier_chain_register(notifiers, &clock->nb); } return clk; free_clock: kfree(clock); return clk; } static void __init cpg_div6_clock_init(struct device_node *np) { unsigned int num_parents; const char **parent_names; const char *clk_name = np->name; void __iomem *reg; struct clk *clk; unsigned int i; num_parents = of_clk_get_parent_count(np); if (num_parents < 1) { pr_err("%s: no parent found for %pOFn DIV6 clock\n", __func__, np); return; } parent_names = kmalloc_array(num_parents, sizeof(*parent_names), GFP_KERNEL); if (!parent_names) return; reg = of_iomap(np, 0); if (reg == NULL) { pr_err("%s: failed to map %pOFn DIV6 clock register\n", __func__, np); goto error; } /* Parse the DT properties. */ of_property_read_string(np, "clock-output-names", &clk_name); for (i = 0; i < num_parents; i++) parent_names[i] = of_clk_get_parent_name(np, i); clk = cpg_div6_register(clk_name, num_parents, parent_names, reg, NULL); if (IS_ERR(clk)) { pr_err("%s: failed to register %pOFn DIV6 clock (%ld)\n", __func__, np, PTR_ERR(clk)); goto error; } of_clk_add_provider(np, of_clk_src_simple_get, clk); kfree(parent_names); return; error: if (reg) iounmap(reg); kfree(parent_names); } CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);
linux-master
drivers/clk/renesas/clk-div6.c
// SPDX-License-Identifier: GPL-2.0 /* * r8a7794 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2017 Glider bvba * * Based on clk-rcar-gen2.c * * Copyright (C) 2013 Ideas On Board SPRL */ #include <linux/device.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/soc/renesas/rcar-rst.h> #include <dt-bindings/clock/r8a7794-cpg-mssr.h> #include "renesas-cpg-mssr.h" #include "rcar-gen2-cpg.h" enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A7794_CLK_OSC, /* External Input Clocks */ CLK_EXTAL, CLK_USB_EXTAL, /* Internal Core Clocks */ CLK_MAIN, CLK_PLL0, CLK_PLL1, CLK_PLL3, CLK_PLL1_DIV2, /* Module Clocks */ MOD_CLK_BASE }; static const struct cpg_core_clk r8a7794_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("usb_extal", CLK_USB_EXTAL), /* Internal Core Clocks */ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), /* Core Clock Outputs */ DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1), DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), DEF_BASE("qspi", R8A7794_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), DEF_BASE("rcan", R8A7794_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL), DEF_FIXED("z2", R8A7794_CLK_Z2, CLK_PLL0, 1, 1), DEF_FIXED("zg", R8A7794_CLK_ZG, CLK_PLL1, 6, 1), DEF_FIXED("zx", R8A7794_CLK_ZX, CLK_PLL1, 3, 1), DEF_FIXED("zs", R8A7794_CLK_ZS, CLK_PLL1, 6, 1), DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1), DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1), DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1), DEF_FIXED("lb", R8A7794_CLK_LB, CLK_PLL1, 24, 1), DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1), DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cp", R8A7794_CLK_CP, CLK_PLL1, 48, 1), DEF_FIXED("m2", R8A7794_CLK_M2, CLK_PLL1, 8, 1), DEF_FIXED("zb3", R8A7794_CLK_ZB3, CLK_PLL3, 4, 1), DEF_FIXED("zb3d2", R8A7794_CLK_ZB3D2, CLK_PLL3, 8, 1), DEF_FIXED("ddr", R8A7794_CLK_DDR, CLK_PLL3, 8, 1), DEF_FIXED("mp", R8A7794_CLK_MP, CLK_PLL1_DIV2, 15, 1), DEF_FIXED("cpex", R8A7794_CLK_CPEX, CLK_EXTAL, 2, 1), DEF_FIXED("r", R8A7794_CLK_R, CLK_PLL1, 49152, 1), DEF_FIXED("osc", R8A7794_CLK_OSC, CLK_PLL1, 12288, 1), DEF_DIV6P1("sd2", R8A7794_CLK_SD2, CLK_PLL1_DIV2, 0x078), DEF_DIV6P1("sd3", R8A7794_CLK_SD3, CLK_PLL1_DIV2, 0x26c), DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240), }; static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = { DEF_MOD("msiof0", 0, R8A7794_CLK_MP), DEF_MOD("vcp0", 101, R8A7794_CLK_ZS), DEF_MOD("vpc0", 103, R8A7794_CLK_ZS), DEF_MOD("jpu", 106, R8A7794_CLK_M2), DEF_MOD("tmu1", 111, R8A7794_CLK_P), DEF_MOD("3dg", 112, R8A7794_CLK_ZG), DEF_MOD("2d-dmac", 115, R8A7794_CLK_ZS), DEF_MOD("fdp1-0", 119, R8A7794_CLK_ZS), DEF_MOD("tmu3", 121, R8A7794_CLK_P), DEF_MOD("tmu2", 122, R8A7794_CLK_P), DEF_MOD("cmt0", 124, R8A7794_CLK_R), DEF_MOD("tmu0", 125, R8A7794_CLK_CP), DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS), DEF_MOD("vsps", 131, R8A7794_CLK_ZS), DEF_MOD("scifa2", 202, R8A7794_CLK_MP), DEF_MOD("scifa1", 203, R8A7794_CLK_MP), DEF_MOD("scifa0", 204, R8A7794_CLK_MP), DEF_MOD("msiof2", 205, R8A7794_CLK_MP), DEF_MOD("scifb0", 206, R8A7794_CLK_MP), DEF_MOD("scifb1", 207, R8A7794_CLK_MP), DEF_MOD("msiof1", 208, R8A7794_CLK_MP), DEF_MOD("scifb2", 216, R8A7794_CLK_MP), DEF_MOD("sys-dmac1", 218, R8A7794_CLK_ZS), DEF_MOD("sys-dmac0", 219, R8A7794_CLK_ZS), DEF_MOD("tpu0", 304, R8A7794_CLK_CP), DEF_MOD("sdhi3", 311, R8A7794_CLK_SD3), DEF_MOD("sdhi2", 312, R8A7794_CLK_SD2), DEF_MOD("sdhi0", 314, R8A7794_CLK_SD0), DEF_MOD("mmcif0", 315, R8A7794_CLK_MMC0), DEF_MOD("iic0", 318, R8A7794_CLK_HP), DEF_MOD("iic1", 323, R8A7794_CLK_HP), DEF_MOD("cmt1", 329, R8A7794_CLK_R), DEF_MOD("usbhs-dmac0", 330, R8A7794_CLK_HP), DEF_MOD("usbhs-dmac1", 331, R8A7794_CLK_HP), DEF_MOD("rwdt", 402, R8A7794_CLK_R), DEF_MOD("irqc", 407, R8A7794_CLK_CP), DEF_MOD("intc-sys", 408, R8A7794_CLK_ZS), DEF_MOD("audio-dmac0", 502, R8A7794_CLK_HP), DEF_MOD("adsp_mod", 506, R8A7794_CLK_ADSP), DEF_MOD("pwm", 523, R8A7794_CLK_P), DEF_MOD("usb-ehci", 703, R8A7794_CLK_MP), DEF_MOD("usbhs", 704, R8A7794_CLK_HP), DEF_MOD("hscif2", 713, R8A7794_CLK_ZS), DEF_MOD("scif5", 714, R8A7794_CLK_P), DEF_MOD("scif4", 715, R8A7794_CLK_P), DEF_MOD("hscif1", 716, R8A7794_CLK_ZS), DEF_MOD("hscif0", 717, R8A7794_CLK_ZS), DEF_MOD("scif3", 718, R8A7794_CLK_P), DEF_MOD("scif2", 719, R8A7794_CLK_P), DEF_MOD("scif1", 720, R8A7794_CLK_P), DEF_MOD("scif0", 721, R8A7794_CLK_P), DEF_MOD("du1", 723, R8A7794_CLK_ZX), DEF_MOD("du0", 724, R8A7794_CLK_ZX), DEF_MOD("ipmmu-sgx", 800, R8A7794_CLK_ZX), DEF_MOD("mlb", 802, R8A7794_CLK_HP), DEF_MOD("vin1", 810, R8A7794_CLK_ZG), DEF_MOD("vin0", 811, R8A7794_CLK_ZG), DEF_MOD("etheravb", 812, R8A7794_CLK_HP), DEF_MOD("ether", 813, R8A7794_CLK_P), DEF_MOD("gyro-adc", 901, R8A7794_CLK_P), DEF_MOD("gpio6", 905, R8A7794_CLK_CP), DEF_MOD("gpio5", 907, R8A7794_CLK_CP), DEF_MOD("gpio4", 908, R8A7794_CLK_CP), DEF_MOD("gpio3", 909, R8A7794_CLK_CP), DEF_MOD("gpio2", 910, R8A7794_CLK_CP), DEF_MOD("gpio1", 911, R8A7794_CLK_CP), DEF_MOD("gpio0", 912, R8A7794_CLK_CP), DEF_MOD("can1", 915, R8A7794_CLK_P), DEF_MOD("can0", 916, R8A7794_CLK_P), DEF_MOD("qspi_mod", 917, R8A7794_CLK_QSPI), DEF_MOD("i2c5", 925, R8A7794_CLK_HP), DEF_MOD("i2c4", 927, R8A7794_CLK_HP), DEF_MOD("i2c3", 928, R8A7794_CLK_HP), DEF_MOD("i2c2", 929, R8A7794_CLK_HP), DEF_MOD("i2c1", 930, R8A7794_CLK_HP), DEF_MOD("i2c0", 931, R8A7794_CLK_HP), DEF_MOD("ssi-all", 1005, R8A7794_CLK_P), DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), DEF_MOD("scu-all", 1017, R8A7794_CLK_P), DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), DEF_MOD("scifa3", 1106, R8A7794_CLK_MP), DEF_MOD("scifa4", 1107, R8A7794_CLK_MP), DEF_MOD("scifa5", 1108, R8A7794_CLK_MP), }; static const unsigned int r8a7794_crit_mod_clks[] __initconst = { MOD_CLK_ID(402), /* RWDT */ MOD_CLK_ID(408), /* INTC-SYS (GIC) */ }; /* * CPG Clock Data */ /* * MD EXTAL PLL0 PLL1 PLL3 * 14 13 19 (MHz) *1 *2 *--------------------------------------------------- * 0 0 1 15 x200/3 x208/2 x88 * 0 1 1 20 x150/3 x156/2 x66 * 1 0 1 26 / 2 x230/3 x240/2 x102 * 1 1 1 30 / 2 x200/3 x208/2 x88 * * *1 : Table 7.5c indicates VCO output (PLL0 = VCO/3) * *2 : Table 7.5c indicates VCO output (PLL1 = VCO/2) */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ (((md) & BIT(13)) >> 13)) static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = { { 1, 208, 88, 200 }, { 1, 156, 66, 150 }, { 2, 240, 102, 230 }, { 2, 208, 88, 200 }, }; static int __init r8a7794_cpg_mssr_init(struct device *dev) { const struct rcar_gen2_cpg_pll_config *cpg_pll_config; u32 cpg_mode; int error; error = rcar_rst_read_mode_pins(&cpg_mode); if (error) return error; cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; return rcar_gen2_cpg_init(cpg_pll_config, 3, cpg_mode); } const struct cpg_mssr_info r8a7794_cpg_mssr_info __initconst = { /* Core Clocks */ .core_clks = r8a7794_core_clks, .num_core_clks = ARRAY_SIZE(r8a7794_core_clks), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Module Clocks */ .mod_clks = r8a7794_mod_clks, .num_mod_clks = ARRAY_SIZE(r8a7794_mod_clks), .num_hw_mod_clks = 12 * 32, /* Critical Module Clocks */ .crit_mod_clks = r8a7794_crit_mod_clks, .num_crit_mod_clks = ARRAY_SIZE(r8a7794_crit_mod_clks), /* Callbacks */ .init = r8a7794_cpg_mssr_init, .cpg_clk_register = rcar_gen2_cpg_clk_register, };
linux-master
drivers/clk/renesas/r8a7794-cpg-mssr.c
// SPDX-License-Identifier: GPL-2.0 /* * R-Car Gen3 Clock Pulse Generator Library * * Copyright (C) 2015-2018 Glider bvba * Copyright (C) 2019 Renesas Electronics Corp. * * Based on clk-rcar-gen3.c * * Copyright (C) 2015 Renesas Electronics Corp. */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/device.h> #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> #include <linux/pm.h> #include <linux/slab.h> #include <linux/sys_soc.h> #include "rcar-cpg-lib.h" spinlock_t cpg_lock; void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set) { unsigned long flags; u32 val; spin_lock_irqsave(&cpg_lock, flags); val = readl(reg); val &= ~clear; val |= set; writel(val, reg); spin_unlock_irqrestore(&cpg_lock, flags); }; static int cpg_simple_notifier_call(struct notifier_block *nb, unsigned long action, void *data) { struct cpg_simple_notifier *csn = container_of(nb, struct cpg_simple_notifier, nb); switch (action) { case PM_EVENT_SUSPEND: csn->saved = readl(csn->reg); return NOTIFY_OK; case PM_EVENT_RESUME: writel(csn->saved, csn->reg); return NOTIFY_OK; } return NOTIFY_DONE; } void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, struct cpg_simple_notifier *csn) { csn->nb.notifier_call = cpg_simple_notifier_call; raw_notifier_chain_register(notifiers, &csn->nb); } /* * SDn Clock */ #define SDnSRCFC_SHIFT 2 #define STPnHCK BIT(9 - SDnSRCFC_SHIFT) static const struct clk_div_table cpg_sdh_div_table[] = { { 0, 1 }, { 1, 2 }, { STPnHCK | 2, 4 }, { STPnHCK | 3, 8 }, { STPnHCK | 4, 16 }, { 0, 0 }, }; struct clk * __init cpg_sdh_clk_register(const char *name, void __iomem *sdnckcr, const char *parent_name, struct raw_notifier_head *notifiers) { struct cpg_simple_notifier *csn; struct clk *clk; csn = kzalloc(sizeof(*csn), GFP_KERNEL); if (!csn) return ERR_PTR(-ENOMEM); csn->reg = sdnckcr; clk = clk_register_divider_table(NULL, name, parent_name, 0, sdnckcr, SDnSRCFC_SHIFT, 8, 0, cpg_sdh_div_table, &cpg_lock); if (IS_ERR(clk)) { kfree(csn); return clk; } cpg_simple_notifier_register(notifiers, csn); return clk; } static const struct clk_div_table cpg_sd_div_table[] = { { 0, 2 }, { 1, 4 }, { 0, 0 }, }; struct clk * __init cpg_sd_clk_register(const char *name, void __iomem *sdnckcr, const char *parent_name) { return clk_register_divider_table(NULL, name, parent_name, 0, sdnckcr, 0, 2, 0, cpg_sd_div_table, &cpg_lock); } struct rpc_clock { struct clk_divider div; struct clk_gate gate; /* * One notifier covers both RPC and RPCD2 clocks as they are both * controlled by the same RPCCKCR register... */ struct cpg_simple_notifier csn; }; static const struct clk_div_table cpg_rpc_div_table[] = { { 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 }, }; struct clk * __init cpg_rpc_clk_register(const char *name, void __iomem *rpcckcr, const char *parent_name, struct raw_notifier_head *notifiers) { struct rpc_clock *rpc; struct clk *clk; rpc = kzalloc(sizeof(*rpc), GFP_KERNEL); if (!rpc) return ERR_PTR(-ENOMEM); rpc->div.reg = rpcckcr; rpc->div.width = 3; rpc->div.table = cpg_rpc_div_table; rpc->div.lock = &cpg_lock; rpc->gate.reg = rpcckcr; rpc->gate.bit_idx = 8; rpc->gate.flags = CLK_GATE_SET_TO_DISABLE; rpc->gate.lock = &cpg_lock; rpc->csn.reg = rpcckcr; clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, &rpc->div.hw, &clk_divider_ops, &rpc->gate.hw, &clk_gate_ops, CLK_SET_RATE_PARENT); if (IS_ERR(clk)) { kfree(rpc); return clk; } cpg_simple_notifier_register(notifiers, &rpc->csn); return clk; } struct rpcd2_clock { struct clk_fixed_factor fixed; struct clk_gate gate; }; struct clk * __init cpg_rpcd2_clk_register(const char *name, void __iomem *rpcckcr, const char *parent_name) { struct rpcd2_clock *rpcd2; struct clk *clk; rpcd2 = kzalloc(sizeof(*rpcd2), GFP_KERNEL); if (!rpcd2) return ERR_PTR(-ENOMEM); rpcd2->fixed.mult = 1; rpcd2->fixed.div = 2; rpcd2->gate.reg = rpcckcr; rpcd2->gate.bit_idx = 9; rpcd2->gate.flags = CLK_GATE_SET_TO_DISABLE; rpcd2->gate.lock = &cpg_lock; clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, &rpcd2->fixed.hw, &clk_fixed_factor_ops, &rpcd2->gate.hw, &clk_gate_ops, CLK_SET_RATE_PARENT); if (IS_ERR(clk)) kfree(rpcd2); return clk; }
linux-master
drivers/clk/renesas/rcar-cpg-lib.c
// SPDX-License-Identifier: GPL-2.0 /* * R-Car Gen2 Clock Pulse Generator * * Copyright (C) 2016 Cogent Embedded Inc. */ #include <linux/bug.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/device.h> #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> #include <linux/slab.h> #include <linux/sys_soc.h> #include "renesas-cpg-mssr.h" #include "rcar-gen2-cpg.h" #define CPG_FRQCRB 0x0004 #define CPG_FRQCRB_KICK BIT(31) #define CPG_SDCKCR 0x0074 #define CPG_PLL0CR 0x00d8 #define CPG_PLL0CR_STC_SHIFT 24 #define CPG_PLL0CR_STC_MASK (0x7f << CPG_PLL0CR_STC_SHIFT) #define CPG_FRQCRC 0x00e0 #define CPG_FRQCRC_ZFC_SHIFT 8 #define CPG_FRQCRC_ZFC_MASK (0x1f << CPG_FRQCRC_ZFC_SHIFT) #define CPG_ADSPCKCR 0x025c #define CPG_RCANCKCR 0x0270 static spinlock_t cpg_lock; /* * Z Clock * * Traits of this clock: * prepare - clk_prepare only ensures that parents are prepared * enable - clk_enable only ensures that parents are enabled * rate - rate is adjustable. clk->rate = parent->rate * mult / 32 * parent - fixed parent. No clk_set_parent support */ struct cpg_z_clk { struct clk_hw hw; void __iomem *reg; void __iomem *kick_reg; }; #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct cpg_z_clk *zclk = to_z_clk(hw); unsigned int mult; unsigned int val; val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT; mult = 32 - val; return div_u64((u64)parent_rate * mult, 32); } static int cpg_z_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { unsigned long prate = req->best_parent_rate; unsigned int min_mult, max_mult, mult; min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); if (max_mult < min_mult) return -EINVAL; mult = div64_ul(req->rate * 32ULL, prate); mult = clamp(mult, min_mult, max_mult); req->rate = div_u64((u64)prate * mult, 32); return 0; } static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct cpg_z_clk *zclk = to_z_clk(hw); unsigned int mult; u32 val, kick; unsigned int i; mult = div64_ul(rate * 32ULL, parent_rate); mult = clamp(mult, 1U, 32U); if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) return -EBUSY; val = readl(zclk->reg); val &= ~CPG_FRQCRC_ZFC_MASK; val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT; writel(val, zclk->reg); /* * Set KICK bit in FRQCRB to update hardware setting and wait for * clock change completion. */ kick = readl(zclk->kick_reg); kick |= CPG_FRQCRB_KICK; writel(kick, zclk->kick_reg); /* * Note: There is no HW information about the worst case latency. * * Using experimental measurements, it seems that no more than * ~10 iterations are needed, independently of the CPU rate. * Since this value might be dependent on external xtal rate, pll1 * rate or even the other emulation clocks rate, use 1000 as a * "super" safe value. */ for (i = 1000; i; i--) { if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) return 0; cpu_relax(); } return -ETIMEDOUT; } static const struct clk_ops cpg_z_clk_ops = { .recalc_rate = cpg_z_clk_recalc_rate, .determine_rate = cpg_z_clk_determine_rate, .set_rate = cpg_z_clk_set_rate, }; static struct clk * __init cpg_z_clk_register(const char *name, const char *parent_name, void __iomem *base) { struct clk_init_data init = {}; struct cpg_z_clk *zclk; struct clk *clk; zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); if (!zclk) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &cpg_z_clk_ops; init.parent_names = &parent_name; init.num_parents = 1; zclk->reg = base + CPG_FRQCRC; zclk->kick_reg = base + CPG_FRQCRB; zclk->hw.init = &init; clk = clk_register(NULL, &zclk->hw); if (IS_ERR(clk)) kfree(zclk); return clk; } static struct clk * __init cpg_rcan_clk_register(const char *name, const char *parent_name, void __iomem *base) { struct clk_fixed_factor *fixed; struct clk_gate *gate; struct clk *clk; fixed = kzalloc(sizeof(*fixed), GFP_KERNEL); if (!fixed) return ERR_PTR(-ENOMEM); fixed->mult = 1; fixed->div = 6; gate = kzalloc(sizeof(*gate), GFP_KERNEL); if (!gate) { kfree(fixed); return ERR_PTR(-ENOMEM); } gate->reg = base + CPG_RCANCKCR; gate->bit_idx = 8; gate->flags = CLK_GATE_SET_TO_DISABLE; gate->lock = &cpg_lock; clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, &fixed->hw, &clk_fixed_factor_ops, &gate->hw, &clk_gate_ops, 0); if (IS_ERR(clk)) { kfree(gate); kfree(fixed); } return clk; } /* ADSP divisors */ static const struct clk_div_table cpg_adsp_div_table[] = { { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 }, }; static struct clk * __init cpg_adsp_clk_register(const char *name, const char *parent_name, void __iomem *base) { struct clk_divider *div; struct clk_gate *gate; struct clk *clk; div = kzalloc(sizeof(*div), GFP_KERNEL); if (!div) return ERR_PTR(-ENOMEM); div->reg = base + CPG_ADSPCKCR; div->width = 4; div->table = cpg_adsp_div_table; div->lock = &cpg_lock; gate = kzalloc(sizeof(*gate), GFP_KERNEL); if (!gate) { kfree(div); return ERR_PTR(-ENOMEM); } gate->reg = base + CPG_ADSPCKCR; gate->bit_idx = 8; gate->flags = CLK_GATE_SET_TO_DISABLE; gate->lock = &cpg_lock; clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, &div->hw, &clk_divider_ops, &gate->hw, &clk_gate_ops, 0); if (IS_ERR(clk)) { kfree(gate); kfree(div); } return clk; } /* SDHI divisors */ static const struct clk_div_table cpg_sdh_div_table[] = { { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 }, }; static const struct clk_div_table cpg_sd01_div_table[] = { { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 }, }; static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata; static unsigned int cpg_pll0_div __initdata; static u32 cpg_mode __initdata; static u32 cpg_quirks __initdata; #define SD_SKIP_FIRST BIT(0) /* Skip first clock in SD table */ static const struct soc_device_attribute cpg_quirks_match[] __initconst = { { .soc_id = "r8a77470", .data = (void *)SD_SKIP_FIRST, }, { /* sentinel */ } }; struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core, const struct cpg_mssr_info *info, struct clk **clks, void __iomem *base, struct raw_notifier_head *notifiers) { const struct clk_div_table *table = NULL; const struct clk *parent; const char *parent_name; unsigned int mult = 1; unsigned int div = 1; unsigned int shift; parent = clks[core->parent]; if (IS_ERR(parent)) return ERR_CAST(parent); parent_name = __clk_get_name(parent); switch (core->type) { /* R-Car Gen2 */ case CLK_TYPE_GEN2_MAIN: div = cpg_pll_config->extal_div; break; case CLK_TYPE_GEN2_PLL0: /* * PLL0 is a configurable multiplier clock except on R-Car * V2H/E2. Register the PLL0 clock as a fixed factor clock for * now as there's no generic multiplier clock implementation and * we currently have no need to change the multiplier value. */ mult = cpg_pll_config->pll0_mult; div = cpg_pll0_div; if (!mult) { u32 pll0cr = readl(base + CPG_PLL0CR); mult = (((pll0cr & CPG_PLL0CR_STC_MASK) >> CPG_PLL0CR_STC_SHIFT) + 1) * 2; } break; case CLK_TYPE_GEN2_PLL1: mult = cpg_pll_config->pll1_mult / 2; break; case CLK_TYPE_GEN2_PLL3: mult = cpg_pll_config->pll3_mult; break; case CLK_TYPE_GEN2_Z: return cpg_z_clk_register(core->name, parent_name, base); case CLK_TYPE_GEN2_LB: div = cpg_mode & BIT(18) ? 36 : 24; break; case CLK_TYPE_GEN2_ADSP: return cpg_adsp_clk_register(core->name, parent_name, base); case CLK_TYPE_GEN2_SDH: table = cpg_sdh_div_table; shift = 8; break; case CLK_TYPE_GEN2_SD0: table = cpg_sd01_div_table; if (cpg_quirks & SD_SKIP_FIRST) table++; shift = 4; break; case CLK_TYPE_GEN2_SD1: table = cpg_sd01_div_table; if (cpg_quirks & SD_SKIP_FIRST) table++; shift = 0; break; case CLK_TYPE_GEN2_QSPI: div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) ? 8 : 10; break; case CLK_TYPE_GEN2_RCAN: return cpg_rcan_clk_register(core->name, parent_name, base); default: return ERR_PTR(-EINVAL); } if (!table) return clk_register_fixed_factor(NULL, core->name, parent_name, 0, mult, div); else return clk_register_divider_table(NULL, core->name, parent_name, 0, base + CPG_SDCKCR, shift, 4, 0, table, &cpg_lock); } int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config, unsigned int pll0_div, u32 mode) { const struct soc_device_attribute *attr; cpg_pll_config = config; cpg_pll0_div = pll0_div; cpg_mode = mode; attr = soc_device_match(cpg_quirks_match); if (attr) cpg_quirks = (uintptr_t)attr->data; pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks); spin_lock_init(&cpg_lock); return 0; }
linux-master
drivers/clk/renesas/rcar-gen2-cpg.c
// SPDX-License-Identifier: GPL-2.0 /* * r8a774a1 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2018 Renesas Electronics Corp. * * Based on r8a7796-cpg-mssr.c * * Copyright (C) 2016 Glider bvba */ #include <linux/device.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/soc/renesas/rcar-rst.h> #include <dt-bindings/clock/r8a774a1-cpg-mssr.h> #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A774A1_CLK_CANFD, /* External Input Clocks */ CLK_EXTAL, CLK_EXTALR, /* Internal Core Clocks */ CLK_MAIN, CLK_PLL0, CLK_PLL1, CLK_PLL2, CLK_PLL3, CLK_PLL4, CLK_PLL1_DIV2, CLK_PLL1_DIV4, CLK_S0, CLK_S1, CLK_S2, CLK_S3, CLK_SDSRC, CLK_RPCSRC, CLK_RINT, /* Module Clocks */ MOD_CLK_BASE }; static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("extalr", CLK_EXTALR), /* Internal Core Clocks */ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), DEF_GEN3_Z("zg", R8A774A1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24), DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), DEF_FIXED("zx", R8A774A1_CLK_ZX, CLK_PLL1_DIV2, 2, 1), DEF_FIXED("s0d1", R8A774A1_CLK_S0D1, CLK_S0, 1, 1), DEF_FIXED("s0d2", R8A774A1_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A774A1_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A774A1_CLK_S0D4, CLK_S0, 4, 1), DEF_FIXED("s0d6", R8A774A1_CLK_S0D6, CLK_S0, 6, 1), DEF_FIXED("s0d8", R8A774A1_CLK_S0D8, CLK_S0, 8, 1), DEF_FIXED("s0d12", R8A774A1_CLK_S0D12, CLK_S0, 12, 1), DEF_FIXED("s1d2", R8A774A1_CLK_S1D2, CLK_S1, 2, 1), DEF_FIXED("s1d4", R8A774A1_CLK_S1D4, CLK_S1, 4, 1), DEF_FIXED("s2d1", R8A774A1_CLK_S2D1, CLK_S2, 1, 1), DEF_FIXED("s2d2", R8A774A1_CLK_S2D2, CLK_S2, 2, 1), DEF_FIXED("s2d4", R8A774A1_CLK_S2D4, CLK_S2, 4, 1), DEF_FIXED("s3d1", R8A774A1_CLK_S3D1, CLK_S3, 1, 1), DEF_FIXED("s3d2", R8A774A1_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A774A1_CLK_S3D4, CLK_S3, 4, 1), DEF_GEN3_SDH("sd0h", R8A774A1_CLK_SD0H, CLK_SDSRC, 0x074), DEF_GEN3_SDH("sd1h", R8A774A1_CLK_SD1H, CLK_SDSRC, 0x078), DEF_GEN3_SDH("sd2h", R8A774A1_CLK_SD2H, CLK_SDSRC, 0x268), DEF_GEN3_SDH("sd3h", R8A774A1_CLK_SD3H, CLK_SDSRC, 0x26c), DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, R8A774A1_CLK_SD0H, 0x074), DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, R8A774A1_CLK_SD1H, 0x078), DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268), DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c), DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774A1_CLK_RPC), DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A774A1_CLK_CPEX, CLK_EXTAL, 2, 1), DEF_DIV6P1("canfd", R8A774A1_CLK_CANFD, CLK_PLL1_DIV4, 0x244), DEF_DIV6P1("csi0", R8A774A1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), DEF_DIV6P1("mso", R8A774A1_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("hdmi", R8A774A1_CLK_HDMI, CLK_PLL1_DIV4, 0x250), DEF_GEN3_OSC("osc", R8A774A1_CLK_OSC, CLK_EXTAL, 8), DEF_BASE("r", R8A774A1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), }; static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { DEF_MOD("3dge", 112, R8A774A1_CLK_ZG), DEF_MOD("tmu4", 121, R8A774A1_CLK_S0D6), DEF_MOD("tmu3", 122, R8A774A1_CLK_S3D2), DEF_MOD("tmu2", 123, R8A774A1_CLK_S3D2), DEF_MOD("tmu1", 124, R8A774A1_CLK_S3D2), DEF_MOD("tmu0", 125, R8A774A1_CLK_CP), DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1), DEF_MOD("scif5", 202, R8A774A1_CLK_S3D4), DEF_MOD("scif4", 203, R8A774A1_CLK_S3D4), DEF_MOD("scif3", 204, R8A774A1_CLK_S3D4), DEF_MOD("scif1", 206, R8A774A1_CLK_S3D4), DEF_MOD("scif0", 207, R8A774A1_CLK_S3D4), DEF_MOD("msiof3", 208, R8A774A1_CLK_MSO), DEF_MOD("msiof2", 209, R8A774A1_CLK_MSO), DEF_MOD("msiof1", 210, R8A774A1_CLK_MSO), DEF_MOD("msiof0", 211, R8A774A1_CLK_MSO), DEF_MOD("sys-dmac2", 217, R8A774A1_CLK_S3D1), DEF_MOD("sys-dmac1", 218, R8A774A1_CLK_S3D1), DEF_MOD("sys-dmac0", 219, R8A774A1_CLK_S0D3), DEF_MOD("cmt3", 300, R8A774A1_CLK_R), DEF_MOD("cmt2", 301, R8A774A1_CLK_R), DEF_MOD("cmt1", 302, R8A774A1_CLK_R), DEF_MOD("cmt0", 303, R8A774A1_CLK_R), DEF_MOD("scif2", 310, R8A774A1_CLK_S3D4), DEF_MOD("sdif3", 311, R8A774A1_CLK_SD3), DEF_MOD("sdif2", 312, R8A774A1_CLK_SD2), DEF_MOD("sdif1", 313, R8A774A1_CLK_SD1), DEF_MOD("sdif0", 314, R8A774A1_CLK_SD0), DEF_MOD("pcie1", 318, R8A774A1_CLK_S3D1), DEF_MOD("pcie0", 319, R8A774A1_CLK_S3D1), DEF_MOD("usb3-if0", 328, R8A774A1_CLK_S3D1), DEF_MOD("usb-dmac0", 330, R8A774A1_CLK_S3D1), DEF_MOD("usb-dmac1", 331, R8A774A1_CLK_S3D1), DEF_MOD("rwdt", 402, R8A774A1_CLK_R), DEF_MOD("intc-ex", 407, R8A774A1_CLK_CP), DEF_MOD("intc-ap", 408, R8A774A1_CLK_S0D3), DEF_MOD("audmac1", 501, R8A774A1_CLK_S1D2), DEF_MOD("audmac0", 502, R8A774A1_CLK_S1D2), DEF_MOD("hscif4", 516, R8A774A1_CLK_S3D1), DEF_MOD("hscif3", 517, R8A774A1_CLK_S3D1), DEF_MOD("hscif2", 518, R8A774A1_CLK_S3D1), DEF_MOD("hscif1", 519, R8A774A1_CLK_S3D1), DEF_MOD("hscif0", 520, R8A774A1_CLK_S3D1), DEF_MOD("thermal", 522, R8A774A1_CLK_CP), DEF_MOD("pwm", 523, R8A774A1_CLK_S0D12), DEF_MOD("fcpvd2", 601, R8A774A1_CLK_S0D2), DEF_MOD("fcpvd1", 602, R8A774A1_CLK_S0D2), DEF_MOD("fcpvd0", 603, R8A774A1_CLK_S0D2), DEF_MOD("fcpvb0", 607, R8A774A1_CLK_S0D1), DEF_MOD("fcpvi0", 611, R8A774A1_CLK_S0D1), DEF_MOD("fcpf0", 615, R8A774A1_CLK_S0D1), DEF_MOD("fcpci0", 617, R8A774A1_CLK_S0D2), DEF_MOD("fcpcs", 619, R8A774A1_CLK_S0D2), DEF_MOD("vspd2", 621, R8A774A1_CLK_S0D2), DEF_MOD("vspd1", 622, R8A774A1_CLK_S0D2), DEF_MOD("vspd0", 623, R8A774A1_CLK_S0D2), DEF_MOD("vspb", 626, R8A774A1_CLK_S0D1), DEF_MOD("vspi0", 631, R8A774A1_CLK_S0D1), DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D2), DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D2), DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D2), DEF_MOD("csi20", 714, R8A774A1_CLK_CSI0), DEF_MOD("csi40", 716, R8A774A1_CLK_CSI0), DEF_MOD("du2", 722, R8A774A1_CLK_S2D1), DEF_MOD("du1", 723, R8A774A1_CLK_S2D1), DEF_MOD("du0", 724, R8A774A1_CLK_S2D1), DEF_MOD("lvds", 727, R8A774A1_CLK_S2D1), DEF_MOD("hdmi0", 729, R8A774A1_CLK_HDMI), DEF_MOD("vin7", 804, R8A774A1_CLK_S0D2), DEF_MOD("vin6", 805, R8A774A1_CLK_S0D2), DEF_MOD("vin5", 806, R8A774A1_CLK_S0D2), DEF_MOD("vin4", 807, R8A774A1_CLK_S0D2), DEF_MOD("vin3", 808, R8A774A1_CLK_S0D2), DEF_MOD("vin2", 809, R8A774A1_CLK_S0D2), DEF_MOD("vin1", 810, R8A774A1_CLK_S0D2), DEF_MOD("vin0", 811, R8A774A1_CLK_S0D2), DEF_MOD("etheravb", 812, R8A774A1_CLK_S0D6), DEF_MOD("gpio7", 905, R8A774A1_CLK_S3D4), DEF_MOD("gpio6", 906, R8A774A1_CLK_S3D4), DEF_MOD("gpio5", 907, R8A774A1_CLK_S3D4), DEF_MOD("gpio4", 908, R8A774A1_CLK_S3D4), DEF_MOD("gpio3", 909, R8A774A1_CLK_S3D4), DEF_MOD("gpio2", 910, R8A774A1_CLK_S3D4), DEF_MOD("gpio1", 911, R8A774A1_CLK_S3D4), DEF_MOD("gpio0", 912, R8A774A1_CLK_S3D4), DEF_MOD("can-fd", 914, R8A774A1_CLK_S3D2), DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4), DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4), DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6), DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6), DEF_MOD("adg", 922, R8A774A1_CLK_S0D4), DEF_MOD("iic-pmic", 926, R8A774A1_CLK_CP), DEF_MOD("i2c4", 927, R8A774A1_CLK_S0D6), DEF_MOD("i2c3", 928, R8A774A1_CLK_S0D6), DEF_MOD("i2c2", 929, R8A774A1_CLK_S3D2), DEF_MOD("i2c1", 930, R8A774A1_CLK_S3D2), DEF_MOD("i2c0", 931, R8A774A1_CLK_S3D2), DEF_MOD("ssi-all", 1005, R8A774A1_CLK_S3D4), DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), DEF_MOD("scu-all", 1017, R8A774A1_CLK_S3D4), DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), }; static const unsigned int r8a774a1_crit_mod_clks[] __initconst = { MOD_CLK_ID(402), /* RWDT */ MOD_CLK_ID(408), /* INTC-AP (GIC) */ }; /* * CPG Clock Data */ /* * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC * 14 13 19 17 (MHz) *------------------------------------------------------------------------- * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16 * 0 0 1 0 Prohibited setting * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19 * 0 1 1 0 Prohibited setting * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24 * 1 0 1 0 Prohibited setting * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32 * 1 1 1 0 Prohibited setting * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32 */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ (((md) & BIT(13)) >> 11) | \ (((md) & BIT(19)) >> 18) | \ (((md) & BIT(17)) >> 17)) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ { 1, 192, 1, 192, 1, 16, }, { 1, 192, 1, 128, 1, 16, }, { 0, /* Prohibited setting */ }, { 1, 192, 1, 192, 1, 16, }, { 1, 160, 1, 160, 1, 19, }, { 1, 160, 1, 106, 1, 19, }, { 0, /* Prohibited setting */ }, { 1, 160, 1, 160, 1, 19, }, { 1, 128, 1, 128, 1, 24, }, { 1, 128, 1, 84, 1, 24, }, { 0, /* Prohibited setting */ }, { 1, 128, 1, 128, 1, 24, }, { 2, 192, 1, 192, 1, 32, }, { 2, 192, 1, 128, 1, 32, }, { 0, /* Prohibited setting */ }, { 2, 192, 1, 192, 1, 32, }, }; static int __init r8a774a1_cpg_mssr_init(struct device *dev) { const struct rcar_gen3_cpg_pll_config *cpg_pll_config; u32 cpg_mode; int error; error = rcar_rst_read_mode_pins(&cpg_mode); if (error) return error; cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; if (!cpg_pll_config->extal_div) { dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); return -EINVAL; } return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); } const struct cpg_mssr_info r8a774a1_cpg_mssr_info __initconst = { /* Core Clocks */ .core_clks = r8a774a1_core_clks, .num_core_clks = ARRAY_SIZE(r8a774a1_core_clks), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Module Clocks */ .mod_clks = r8a774a1_mod_clks, .num_mod_clks = ARRAY_SIZE(r8a774a1_mod_clks), .num_hw_mod_clks = 12 * 32, /* Critical Module Clocks */ .crit_mod_clks = r8a774a1_crit_mod_clks, .num_crit_mod_clks = ARRAY_SIZE(r8a774a1_crit_mod_clks), /* Callbacks */ .init = r8a774a1_cpg_mssr_init, .cpg_clk_register = rcar_gen3_cpg_clk_register, };
linux-master
drivers/clk/renesas/r8a774a1-cpg-mssr.c
// SPDX-License-Identifier: GPL-2.0 /* * RZ/G2UL CPG driver * * Copyright (C) 2022 Renesas Electronics Corp. */ #include <linux/clk-provider.h> #include <linux/device.h> #include <linux/init.h> #include <linux/kernel.h> #include <dt-bindings/clock/r9a07g043-cpg.h> #include "rzg2l-cpg.h" enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2, /* External Input Clocks */ CLK_EXTAL, /* Internal Core Clocks */ CLK_OSC_DIV1000, CLK_PLL1, CLK_PLL2, CLK_PLL2_DIV2, CLK_PLL2_DIV2_8, CLK_PLL2_DIV2_10, CLK_PLL3, CLK_PLL3_400, CLK_PLL3_533, CLK_PLL3_DIV2, CLK_PLL3_DIV2_4, CLK_PLL3_DIV2_4_2, CLK_SEL_PLL3_3, CLK_DIV_PLL3_C, #ifdef CONFIG_ARM64 CLK_PLL5, CLK_PLL5_500, CLK_PLL5_250, #endif CLK_PLL6, CLK_PLL6_250, CLK_P1_DIV2, CLK_PLL2_800, CLK_PLL2_SDHI_533, CLK_PLL2_SDHI_400, CLK_PLL2_SDHI_266, CLK_SD0_DIV4, CLK_SD1_DIV4, /* Module Clocks */ MOD_CLK_BASE, }; /* Divider tables */ static const struct clk_div_table dtable_1_8[] = { {0, 1}, {1, 2}, {2, 4}, {3, 8}, {0, 0}, }; static const struct clk_div_table dtable_1_32[] = { {0, 1}, {1, 2}, {2, 4}, {3, 8}, {4, 32}, {0, 0}, }; /* Mux clock tables */ static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), /* Internal Core Clocks */ DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1), DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2), DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32), #ifdef CONFIG_ARM64 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6), DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2), #endif DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), /* Core output clk */ DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8), DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32), DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2), DEF_FIXED("TSU", R9A07G043_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32), DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2), DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32), DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2), DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, sel_shdi), DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, sel_shdi), DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4), DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4), }; static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { #ifdef CONFIG_ARM64 DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1, 0x514, 0), DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2, 0x518, 0), DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1, 0x518, 1), #endif #ifdef CONFIG_RISCV DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2, 0x518, 0), DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1, 0x518, 1), #endif DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1, 0x52c, 0), DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, 0x52c, 1), DEF_MOD("ostm0_pclk", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0, 0x534, 0), DEF_MOD("ostm1_pclk", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0, 0x534, 1), DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, 0x534, 2), DEF_MOD("mtu_x_mck", R9A07G043_MTU_X_MCK_MTU3, R9A07G043_CLK_P0, 0x538, 0), DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0, 0x548, 0), DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK, 0x548, 1), DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1, 0x550, 0), DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0, 0x550, 1), DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1), DEF_MOD("sdhi0_clk_hs", R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0, 0x554, 2), DEF_MOD("sdhi0_aclk", R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1, 0x554, 3), DEF_MOD("sdhi1_imclk", R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4), DEF_MOD("sdhi1_imclk2", R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5), DEF_MOD("sdhi1_clk_hs", R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1, 0x554, 6), DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1, 0x554, 7), DEF_MOD("ssi0_pclk", R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0, 0x570, 0), DEF_MOD("ssi0_sfr", R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0, 0x570, 1), DEF_MOD("ssi1_pclk", R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0, 0x570, 2), DEF_MOD("ssi1_sfr", R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0, 0x570, 3), DEF_MOD("ssi2_pclk", R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0, 0x570, 4), DEF_MOD("ssi2_sfr", R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0, 0x570, 5), DEF_MOD("ssi3_pclk", R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0, 0x570, 6), DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0, 0x570, 7), DEF_MOD("usb0_host", R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1, 0x578, 0), DEF_MOD("usb1_host", R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1, 0x578, 1), DEF_MOD("usb0_func", R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1, 0x578, 2), DEF_MOD("usb_pclk", R9A07G043_USB_PCLK, R9A07G043_CLK_P1, 0x578, 3), DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0, 0x57c, 0), DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT, 0x57c, 0), DEF_COUPLED("eth1_axi", R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0, 0x57c, 1), DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT, 0x57c, 1), DEF_MOD("i2c0", R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0, 0x580, 0), DEF_MOD("i2c1", R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0, 0x580, 1), DEF_MOD("i2c2", R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0, 0x580, 2), DEF_MOD("i2c3", R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0, 0x580, 3), DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0, 0x584, 0), DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0, 0x584, 1), DEF_MOD("scif2", R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0, 0x584, 2), DEF_MOD("scif3", R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0, 0x584, 3), DEF_MOD("scif4", R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0, 0x584, 4), DEF_MOD("sci0", R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0, 0x588, 0), DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0, 0x588, 1), DEF_MOD("rspi0", R9A07G043_RSPI0_CLKB, R9A07G043_CLK_P0, 0x590, 0), DEF_MOD("rspi1", R9A07G043_RSPI1_CLKB, R9A07G043_CLK_P0, 0x590, 1), DEF_MOD("rspi2", R9A07G043_RSPI2_CLKB, R9A07G043_CLK_P0, 0x590, 2), DEF_MOD("canfd", R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0, 0x594, 0), DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, 0x598, 0), DEF_MOD("adc_adclk", R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU, 0x5a8, 0), DEF_MOD("adc_pclk", R9A07G043_ADC_PCLK, R9A07G043_CLK_P0, 0x5a8, 1), DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU, 0x5ac, 0), }; static struct rzg2l_reset r9a07g043_resets[] = { #ifdef CONFIG_ARM64 DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1), DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), #endif #ifdef CONFIG_RISCV DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0), #endif DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0), DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0), DEF_RST(R9A07G043_SPI_RST, 0x850, 0), DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0), DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1), DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2), DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3), DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0), DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1), DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2), DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3), DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0), DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1), DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0), DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1), DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2), DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3), DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0), DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1), DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2), DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3), DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4), DEF_RST(R9A07G043_SCI0_RST, 0x888, 0), DEF_RST(R9A07G043_SCI1_RST, 0x888, 1), DEF_RST(R9A07G043_RSPI0_RST, 0x890, 0), DEF_RST(R9A07G043_RSPI1_RST, 0x890, 1), DEF_RST(R9A07G043_RSPI2_RST, 0x890, 2), DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0), DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1), DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0), DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1), DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0), }; static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { #ifdef CONFIG_ARM64 MOD_CLK_BASE + R9A07G043_GIC600_GICCLK, MOD_CLK_BASE + R9A07G043_IA55_CLK, #endif #ifdef CONFIG_RISCV MOD_CLK_BASE + R9A07G043_IAX45_CLK, #endif MOD_CLK_BASE + R9A07G043_DMAC_ACLK, }; const struct rzg2l_cpg_info r9a07g043_cpg_info = { /* Core Clocks */ .core_clks = r9a07g043_core_clks, .num_core_clks = ARRAY_SIZE(r9a07g043_core_clks), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Critical Module Clocks */ .crit_mod_clks = r9a07g043_crit_mod_clks, .num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks), /* Module Clocks */ .mod_clks = r9a07g043_mod_clks, .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks), #ifdef CONFIG_ARM64 .num_hw_mod_clks = R9A07G043_TSU_PCLK + 1, #endif #ifdef CONFIG_RISCV .num_hw_mod_clks = R9A07G043_IAX45_PCLK + 1, #endif /* Resets */ .resets = r9a07g043_resets, #ifdef CONFIG_ARM64 .num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */ #endif #ifdef CONFIG_RISCV .num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */ #endif .has_clk_mon_regs = true, };
linux-master
drivers/clk/renesas/r9a07g043-cpg.c
// SPDX-License-Identifier: GPL-2.0 /* * r8a77970 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2017-2018 Cogent Embedded Inc. * * Based on r8a7795-cpg-mssr.c * * Copyright (C) 2015 Glider bvba */ #include <linux/clk-provider.h> #include <linux/device.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/soc/renesas/rcar-rst.h> #include <dt-bindings/clock/r8a77970-cpg-mssr.h> #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" #define CPG_SD0CKCR 0x0074 enum r8a77970_clk_types { CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE, CLK_TYPE_R8A77970_SD0, }; enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A77970_CLK_OSC, /* External Input Clocks */ CLK_EXTAL, CLK_EXTALR, /* Internal Core Clocks */ CLK_MAIN, CLK_PLL0, CLK_PLL1, CLK_PLL3, CLK_PLL1_DIV2, CLK_PLL1_DIV4, /* Module Clocks */ MOD_CLK_BASE }; static spinlock_t cpg_lock; static const struct clk_div_table cpg_sd0h_div_table[] = { { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 }, }; static const struct clk_div_table cpg_sd0_div_table[] = { { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 }, }; static const struct cpg_core_clk r8a77970_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("extalr", CLK_EXTALR), /* Internal Core Clocks */ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), /* Core Clock Outputs */ DEF_FIXED("z2", R8A77970_CLK_Z2, CLK_PLL1_DIV4, 1, 1), DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1), DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1), DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_PLL1_DIV2, 4, 1), DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_PLL1_DIV2, 8, 1), DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_PLL1_DIV2, 16, 1), DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1), DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H, CLK_PLL1_DIV2), DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2), DEF_FIXED("rpc", R8A77970_CLK_RPC, CLK_PLL1_DIV2, 5, 1), DEF_FIXED("rpcd2", R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1), DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A77970_CLK_CPEX, CLK_EXTAL, 2, 1), DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244), DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("csi0", R8A77970_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), DEF_FIXED("osc", R8A77970_CLK_OSC, CLK_PLL1_DIV2, 12*1024, 1), DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR, 1, 1), }; static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = { DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2), DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2), DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2), DEF_MOD("tmu1", 124, R8A77970_CLK_S2D2), DEF_MOD("tmu0", 125, R8A77970_CLK_CP), DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1), DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), DEF_MOD("msiof3", 208, R8A77970_CLK_MSO), DEF_MOD("msiof2", 209, R8A77970_CLK_MSO), DEF_MOD("msiof1", 210, R8A77970_CLK_MSO), DEF_MOD("msiof0", 211, R8A77970_CLK_MSO), DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), DEF_MOD("cmt3", 300, R8A77970_CLK_R), DEF_MOD("cmt2", 301, R8A77970_CLK_R), DEF_MOD("cmt1", 302, R8A77970_CLK_R), DEF_MOD("cmt0", 303, R8A77970_CLK_R), DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4), DEF_MOD("sd-if", 314, R8A77970_CLK_SD0), DEF_MOD("rwdt", 402, R8A77970_CLK_R), DEF_MOD("intc-ex", 407, R8A77970_CLK_CP), DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), DEF_MOD("thermal", 522, R8A77970_CLK_CP), DEF_MOD("pwm", 523, R8A77970_CLK_S2D4), DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1), DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1), DEF_MOD("csi40", 716, R8A77970_CLK_CSI0), DEF_MOD("du0", 724, R8A77970_CLK_S2D1), DEF_MOD("lvds", 727, R8A77970_CLK_S2D1), DEF_MOD("vin3", 808, R8A77970_CLK_S2D1), DEF_MOD("vin2", 809, R8A77970_CLK_S2D1), DEF_MOD("vin1", 810, R8A77970_CLK_S2D1), DEF_MOD("vin0", 811, R8A77970_CLK_S2D1), DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2), DEF_MOD("gpio5", 907, R8A77970_CLK_CP), DEF_MOD("gpio4", 908, R8A77970_CLK_CP), DEF_MOD("gpio3", 909, R8A77970_CLK_CP), DEF_MOD("gpio2", 910, R8A77970_CLK_CP), DEF_MOD("gpio1", 911, R8A77970_CLK_CP), DEF_MOD("gpio0", 912, R8A77970_CLK_CP), DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2), DEF_MOD("rpc-if", 917, R8A77970_CLK_RPC), DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2), DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2), DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2), DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2), DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2), }; static const unsigned int r8a77970_crit_mod_clks[] __initconst = { MOD_CLK_ID(402), /* RWDT */ MOD_CLK_ID(408), /* INTC-AP (GIC) */ }; /* * CPG Clock Data */ /* * MD EXTAL PLL0 PLL1 PLL3 * 14 13 19 (MHz) *------------------------------------------------- * 0 0 0 16.66 x 1 x192 x192 x96 * 0 0 1 16.66 x 1 x192 x192 x80 * 0 1 0 20 x 1 x160 x160 x80 * 0 1 1 20 x 1 x160 x160 x66 * 1 0 0 27 / 2 x236 x236 x118 * 1 0 1 27 / 2 x236 x236 x98 * 1 1 0 33.33 / 2 x192 x192 x96 * 1 1 1 33.33 / 2 x192 x192 x80 */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ (((md) & BIT(13)) >> 12) | \ (((md) & BIT(19)) >> 19)) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = { /* EXTAL div PLL1 mult/div PLL3 mult/div */ { 1, 192, 1, 96, 1, }, { 1, 192, 1, 80, 1, }, { 1, 160, 1, 80, 1, }, { 1, 160, 1, 66, 1, }, { 2, 236, 1, 118, 1, }, { 2, 236, 1, 98, 1, }, { 2, 192, 1, 96, 1, }, { 2, 192, 1, 80, 1, }, }; static int __init r8a77970_cpg_mssr_init(struct device *dev) { const struct rcar_gen3_cpg_pll_config *cpg_pll_config; u32 cpg_mode; int error; error = rcar_rst_read_mode_pins(&cpg_mode); if (error) return error; spin_lock_init(&cpg_lock); cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); } static struct clk * __init r8a77970_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core, const struct cpg_mssr_info *info, struct clk **clks, void __iomem *base, struct raw_notifier_head *notifiers) { const struct clk_div_table *table; const struct clk *parent; unsigned int shift; switch (core->type) { case CLK_TYPE_R8A77970_SD0H: table = cpg_sd0h_div_table; shift = 8; break; case CLK_TYPE_R8A77970_SD0: table = cpg_sd0_div_table; shift = 4; break; default: return rcar_gen3_cpg_clk_register(dev, core, info, clks, base, notifiers); } parent = clks[core->parent]; if (IS_ERR(parent)) return ERR_CAST(parent); return clk_register_divider_table(NULL, core->name, __clk_get_name(parent), 0, base + CPG_SD0CKCR, shift, 4, 0, table, &cpg_lock); } const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = { /* Core Clocks */ .core_clks = r8a77970_core_clks, .num_core_clks = ARRAY_SIZE(r8a77970_core_clks), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Module Clocks */ .mod_clks = r8a77970_mod_clks, .num_mod_clks = ARRAY_SIZE(r8a77970_mod_clks), .num_hw_mod_clks = 12 * 32, /* Critical Module Clocks */ .crit_mod_clks = r8a77970_crit_mod_clks, .num_crit_mod_clks = ARRAY_SIZE(r8a77970_crit_mod_clks), /* Callbacks */ .init = r8a77970_cpg_mssr_init, .cpg_clk_register = r8a77970_cpg_clk_register, };
linux-master
drivers/clk/renesas/r8a77970-cpg-mssr.c
// SPDX-License-Identifier: GPL-2.0 /* * RZ/V2M Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2022 Renesas Electronics Corp. * * Based on r9a07g044-cpg.c */ #include <linux/clk-provider.h> #include <linux/device.h> #include <linux/init.h> #include <linux/kernel.h> #include <dt-bindings/clock/r9a09g011-cpg.h> #include "rzg2l-cpg.h" #define RZV2M_SAMPLL4_CLK1 0x104 #define RZV2M_SAMPLL4_CLK2 0x108 #define PLL4_CONF (RZV2M_SAMPLL4_CLK1 << 22 | RZV2M_SAMPLL4_CLK2 << 12) #define DIV_A DDIV_PACK(0x200, 0, 3) #define DIV_B DDIV_PACK(0x204, 0, 2) #define DIV_D DDIV_PACK(0x204, 4, 2) #define DIV_E DDIV_PACK(0x204, 8, 1) #define DIV_W DDIV_PACK(0x328, 0, 3) #define SEL_B SEL_PLL_PACK(0x214, 0, 1) #define SEL_CSI0 SEL_PLL_PACK(0x330, 0, 1) #define SEL_CSI4 SEL_PLL_PACK(0x330, 4, 1) #define SEL_D SEL_PLL_PACK(0x214, 1, 1) #define SEL_E SEL_PLL_PACK(0x214, 2, 1) #define SEL_SDI SEL_PLL_PACK(0x300, 0, 1) #define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1) enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = 0, /* External Input Clocks */ CLK_EXTAL, /* Internal Core Clocks */ CLK_MAIN, CLK_MAIN_24, CLK_MAIN_2, CLK_PLL1, CLK_PLL2, CLK_PLL2_800, CLK_PLL2_400, CLK_PLL2_200, CLK_PLL2_100, CLK_PLL4, CLK_DIV_A, CLK_DIV_B, CLK_DIV_D, CLK_DIV_E, CLK_DIV_W, CLK_SEL_B, CLK_SEL_B_D2, CLK_SEL_CSI0, CLK_SEL_CSI4, CLK_SEL_D, CLK_SEL_E, CLK_SEL_SDI, CLK_SEL_W0, /* Module Clocks */ MOD_CLK_BASE }; /* Divider tables */ static const struct clk_div_table dtable_diva[] = { {0, 1}, {1, 2}, {2, 3}, {3, 4}, {4, 6}, {5, 12}, {6, 24}, {0, 0}, }; static const struct clk_div_table dtable_divb[] = { {0, 1}, {1, 2}, {2, 4}, {3, 8}, {0, 0}, }; static const struct clk_div_table dtable_divd[] = { {0, 1}, {1, 2}, {2, 4}, {0, 0}, }; static const struct clk_div_table dtable_divw[] = { {0, 6}, {1, 7}, {2, 8}, {3, 9}, {4, 10}, {5, 11}, {6, 12}, {0, 0}, }; /* Mux clock tables */ static const char * const sel_b[] = { ".main", ".divb" }; static const char * const sel_csi[] = { ".main_24", ".main" }; static const char * const sel_d[] = { ".main", ".divd" }; static const char * const sel_e[] = { ".main", ".dive" }; static const char * const sel_w[] = { ".main", ".divw" }; static const char * const sel_sdi[] = { ".main", ".pll2_200" }; static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), /* Internal Core Clocks */ DEF_FIXED(".main", CLK_MAIN, CLK_EXTAL, 1, 1), DEF_FIXED(".main_24", CLK_MAIN_24, CLK_MAIN, 1, 2), DEF_FIXED(".main_2", CLK_MAIN_2, CLK_MAIN, 1, 24), DEF_FIXED(".pll1", CLK_PLL1, CLK_MAIN_2, 498, 1), DEF_FIXED(".pll2", CLK_PLL2, CLK_MAIN_2, 800, 1), DEF_FIXED(".pll2_800", CLK_PLL2_800, CLK_PLL2, 1, 2), DEF_FIXED(".pll2_400", CLK_PLL2_400, CLK_PLL2_800, 1, 2), DEF_FIXED(".pll2_200", CLK_PLL2_200, CLK_PLL2_800, 1, 4), DEF_FIXED(".pll2_100", CLK_PLL2_100, CLK_PLL2_800, 1, 8), DEF_SAMPLL(".pll4", CLK_PLL4, CLK_MAIN_2, PLL4_CONF), DEF_DIV_RO(".diva", CLK_DIV_A, CLK_PLL1, DIV_A, dtable_diva), DEF_DIV_RO(".divb", CLK_DIV_B, CLK_PLL2_400, DIV_B, dtable_divb), DEF_DIV_RO(".divd", CLK_DIV_D, CLK_PLL2_200, DIV_D, dtable_divd), DEF_DIV_RO(".dive", CLK_DIV_E, CLK_PLL2_100, DIV_E, NULL), DEF_DIV_RO(".divw", CLK_DIV_W, CLK_PLL4, DIV_W, dtable_divw), DEF_MUX_RO(".selb", CLK_SEL_B, SEL_B, sel_b), DEF_MUX_RO(".seld", CLK_SEL_D, SEL_D, sel_d), DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e), DEF_MUX(".selsdi", CLK_SEL_SDI, SEL_SDI, sel_sdi), DEF_MUX(".selcsi0", CLK_SEL_CSI0, SEL_CSI0, sel_csi), DEF_MUX(".selcsi4", CLK_SEL_CSI4, SEL_CSI4, sel_csi), DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w), DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2), }; static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2), DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5), DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0), DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1), DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2), DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3), DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4), DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5), DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6), DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7), DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8), DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9), DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10), DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11), DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8), DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8), DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9), DEF_MOD("usb_aclk_h", R9A09G011_USB_ACLK_H, CLK_SEL_D, 0x40c, 4), DEF_MOD("usb_aclk_p", R9A09G011_USB_ACLK_P, CLK_SEL_D, 0x40c, 5), DEF_MOD("usb_pclk", R9A09G011_USB_PCLK, CLK_SEL_E, 0x40c, 6), DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12), DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12), DEF_MOD("cperi_grpb", R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E, 0x424, 0), DEF_MOD("tim_clk_8", R9A09G011_TIM8_CLK, CLK_MAIN_2, 0x424, 4), DEF_MOD("tim_clk_9", R9A09G011_TIM9_CLK, CLK_MAIN_2, 0x424, 5), DEF_MOD("tim_clk_10", R9A09G011_TIM10_CLK, CLK_MAIN_2, 0x424, 6), DEF_MOD("tim_clk_11", R9A09G011_TIM11_CLK, CLK_MAIN_2, 0x424, 7), DEF_MOD("tim_clk_12", R9A09G011_TIM12_CLK, CLK_MAIN_2, 0x424, 8), DEF_MOD("tim_clk_13", R9A09G011_TIM13_CLK, CLK_MAIN_2, 0x424, 9), DEF_MOD("tim_clk_14", R9A09G011_TIM14_CLK, CLK_MAIN_2, 0x424, 10), DEF_MOD("tim_clk_15", R9A09G011_TIM15_CLK, CLK_MAIN_2, 0x424, 11), DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12), DEF_MOD("cperi_grpc", R9A09G011_CPERI_GRPC_PCLK, CLK_SEL_E, 0x428, 0), DEF_MOD("tim_clk_16", R9A09G011_TIM16_CLK, CLK_MAIN_2, 0x428, 4), DEF_MOD("tim_clk_17", R9A09G011_TIM17_CLK, CLK_MAIN_2, 0x428, 5), DEF_MOD("tim_clk_18", R9A09G011_TIM18_CLK, CLK_MAIN_2, 0x428, 6), DEF_MOD("tim_clk_19", R9A09G011_TIM19_CLK, CLK_MAIN_2, 0x428, 7), DEF_MOD("tim_clk_20", R9A09G011_TIM20_CLK, CLK_MAIN_2, 0x428, 8), DEF_MOD("tim_clk_21", R9A09G011_TIM21_CLK, CLK_MAIN_2, 0x428, 9), DEF_MOD("tim_clk_22", R9A09G011_TIM22_CLK, CLK_MAIN_2, 0x428, 10), DEF_MOD("tim_clk_23", R9A09G011_TIM23_CLK, CLK_MAIN_2, 0x428, 11), DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12), DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13), DEF_MOD("cperi_grpf", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0), DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4), DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5), DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6), DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7), DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8), DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9), DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10), DEF_MOD("cperi_grpg", R9A09G011_CPERI_GRPG_PCLK, CLK_SEL_E, 0x438, 0), DEF_MOD("cperi_grph", R9A09G011_CPERI_GRPH_PCLK, CLK_SEL_E, 0x438, 1), DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4), DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5), DEF_MOD("csi0_clk", R9A09G011_CSI0_CLK, CLK_SEL_CSI0, 0x438, 8), DEF_MOD("csi4_clk", R9A09G011_CSI4_CLK, CLK_SEL_CSI4, 0x438, 12), DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0), }; static const struct rzg2l_reset r9a09g011_resets[] = { DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2), DEF_RST_MON(R9A09G011_SDI0_IXRST, 0x608, 0, 6), DEF_RST_MON(R9A09G011_SDI1_IXRST, 0x608, 1, 7), DEF_RST_MON(R9A09G011_EMM_IXRST, 0x608, 2, 8), DEF_RST(R9A09G011_USB_PRESET_N, 0x608, 7), DEF_RST(R9A09G011_USB_DRD_RESET, 0x608, 8), DEF_RST(R9A09G011_USB_ARESETN_P, 0x608, 9), DEF_RST(R9A09G011_USB_ARESETN_H, 0x608, 10), DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11), DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13), DEF_RST(R9A09G011_TIM_GPB_PRESETN, 0x614, 1), DEF_RST(R9A09G011_TIM_GPC_PRESETN, 0x614, 2), DEF_RST_MON(R9A09G011_PWM_GPF_PRESETN, 0x614, 5, 23), DEF_RST_MON(R9A09G011_CSI_GPG_PRESETN, 0x614, 6, 22), DEF_RST_MON(R9A09G011_CSI_GPH_PRESETN, 0x614, 7, 23), DEF_RST(R9A09G011_IIC_GPA_PRESETN, 0x614, 8), DEF_RST(R9A09G011_IIC_GPB_PRESETN, 0x614, 9), DEF_RST_MON(R9A09G011_WDT0_PRESETN, 0x614, 12, 19), }; static const unsigned int r9a09g011_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A09G011_CA53_CLK, MOD_CLK_BASE + R9A09G011_CPERI_GRPB_PCLK, MOD_CLK_BASE + R9A09G011_CPERI_GRPC_PCLK, MOD_CLK_BASE + R9A09G011_CPERI_GRPF_PCLK, MOD_CLK_BASE + R9A09G011_CPERI_GRPG_PCLK, MOD_CLK_BASE + R9A09G011_CPERI_GRPH_PCLK, MOD_CLK_BASE + R9A09G011_GIC_CLK, MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK, MOD_CLK_BASE + R9A09G011_URT_PCLK, }; const struct rzg2l_cpg_info r9a09g011_cpg_info = { /* Core Clocks */ .core_clks = r9a09g011_core_clks, .num_core_clks = ARRAY_SIZE(r9a09g011_core_clks), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Critical Module Clocks */ .crit_mod_clks = r9a09g011_crit_mod_clks, .num_crit_mod_clks = ARRAY_SIZE(r9a09g011_crit_mod_clks), /* Module Clocks */ .mod_clks = r9a09g011_mod_clks, .num_mod_clks = ARRAY_SIZE(r9a09g011_mod_clks), .num_hw_mod_clks = R9A09G011_CA53_CLK + 1, /* Resets */ .resets = r9a09g011_resets, .num_resets = ARRAY_SIZE(r9a09g011_resets), .has_clk_mon_regs = false, };
linux-master
drivers/clk/renesas/r9a09g011-cpg.c
// SPDX-License-Identifier: GPL-2.0 /* * Renesas Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2015 Glider bvba * * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c * * Copyright (C) 2013 Ideas On Board SPRL * Copyright (C) 2015 Renesas Electronics Corp. */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/clk/renesas.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/init.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/of_address.h> #include <linux/platform_device.h> #include <linux/pm_clock.h> #include <linux/pm_domain.h> #include <linux/psci.h> #include <linux/reset-controller.h> #include <linux/slab.h> #include <dt-bindings/clock/renesas-cpg-mssr.h> #include "renesas-cpg-mssr.h" #include "clk-div6.h" #ifdef DEBUG #define WARN_DEBUG(x) WARN_ON(x) #else #define WARN_DEBUG(x) do { } while (0) #endif /* * Module Standby and Software Reset register offets. * * If the registers exist, these are valid for SH-Mobile, R-Mobile, * R-Car Gen2, R-Car Gen3, and RZ/G1. * These are NOT valid for R-Car Gen1 and RZ/A1! */ /* * Module Stop Status Register offsets */ static const u16 mstpsr[] = { 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, 0x9A0, 0x9A4, 0x9A8, 0x9AC, }; static const u16 mstpsr_for_gen4[] = { 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C, 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C, 0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C, 0x2E60, 0x2E64, 0x2E68, 0x2E6C, 0x2E70, 0x2E74, }; /* * System Module Stop Control Register offsets */ static const u16 smstpcr[] = { 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, 0x990, 0x994, 0x998, 0x99C, }; static const u16 mstpcr_for_gen4[] = { 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C, 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C, 0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C, 0x2D60, 0x2D64, 0x2D68, 0x2D6C, 0x2D70, 0x2D74, }; /* * Standby Control Register offsets (RZ/A) * Base address is FRQCR register */ static const u16 stbcr[] = { 0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420, 0x424, 0x428, 0x42C, }; /* * Software Reset Register offsets */ static const u16 srcr[] = { 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC, 0x920, 0x924, 0x928, 0x92C, }; static const u16 srcr_for_gen4[] = { 0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C, 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C, 0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C, 0x2C60, 0x2C64, 0x2C68, 0x2C6C, 0x2C70, 0x2C74, }; /* * Software Reset Clearing Register offsets */ static const u16 srstclr[] = { 0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C, 0x960, 0x964, 0x968, 0x96C, }; static const u16 srstclr_for_gen4[] = { 0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C, 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC, 0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC, 0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC, 0x2CF0, 0x2CF4, }; /** * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby * and Software Reset Private Data * * @rcdev: Optional reset controller entity * @dev: CPG/MSSR device * @base: CPG/MSSR register block base address * @reg_layout: CPG/MSSR register layout * @rmw_lock: protects RMW register accesses * @np: Device node in DT for this CPG/MSSR module * @num_core_clks: Number of Core Clocks in clks[] * @num_mod_clks: Number of Module Clocks in clks[] * @last_dt_core_clk: ID of the last Core Clock exported to DT * @notifiers: Notifier chain to save/restore clock state for system resume * @status_regs: Pointer to status registers array * @control_regs: Pointer to control registers array * @reset_regs: Pointer to reset registers array * @reset_clear_regs: Pointer to reset clearing registers array * @smstpcr_saved: [].mask: Mask of SMSTPCR[] bits under our control * [].val: Saved values of SMSTPCR[] * @clks: Array containing all Core and Module Clocks */ struct cpg_mssr_priv { #ifdef CONFIG_RESET_CONTROLLER struct reset_controller_dev rcdev; #endif struct device *dev; void __iomem *base; enum clk_reg_layout reg_layout; spinlock_t rmw_lock; struct device_node *np; unsigned int num_core_clks; unsigned int num_mod_clks; unsigned int last_dt_core_clk; struct raw_notifier_head notifiers; const u16 *status_regs; const u16 *control_regs; const u16 *reset_regs; const u16 *reset_clear_regs; struct { u32 mask; u32 val; } smstpcr_saved[ARRAY_SIZE(mstpsr_for_gen4)]; struct clk *clks[]; }; static struct cpg_mssr_priv *cpg_mssr_priv; /** * struct mstp_clock - MSTP gating clock * @hw: handle between common and hardware-specific interfaces * @index: MSTP clock number * @priv: CPG/MSSR private data */ struct mstp_clock { struct clk_hw hw; u32 index; struct cpg_mssr_priv *priv; }; #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw) static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) { struct mstp_clock *clock = to_mstp_clock(hw); struct cpg_mssr_priv *priv = clock->priv; unsigned int reg = clock->index / 32; unsigned int bit = clock->index % 32; struct device *dev = priv->dev; u32 bitmask = BIT(bit); unsigned long flags; u32 value; int error; dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, enable ? "ON" : "OFF"); spin_lock_irqsave(&priv->rmw_lock, flags); if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { value = readb(priv->base + priv->control_regs[reg]); if (enable) value &= ~bitmask; else value |= bitmask; writeb(value, priv->base + priv->control_regs[reg]); /* dummy read to ensure write has completed */ readb(priv->base + priv->control_regs[reg]); barrier_data(priv->base + priv->control_regs[reg]); } else { value = readl(priv->base + priv->control_regs[reg]); if (enable) value &= ~bitmask; else value |= bitmask; writel(value, priv->base + priv->control_regs[reg]); } spin_unlock_irqrestore(&priv->rmw_lock, flags); if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) return 0; error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg], value, !(value & bitmask), 0, 10); if (error) dev_err(dev, "Failed to enable SMSTP %p[%d]\n", priv->base + priv->control_regs[reg], bit); return error; } static int cpg_mstp_clock_enable(struct clk_hw *hw) { return cpg_mstp_clock_endisable(hw, true); } static void cpg_mstp_clock_disable(struct clk_hw *hw) { cpg_mstp_clock_endisable(hw, false); } static int cpg_mstp_clock_is_enabled(struct clk_hw *hw) { struct mstp_clock *clock = to_mstp_clock(hw); struct cpg_mssr_priv *priv = clock->priv; u32 value; if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) value = readb(priv->base + priv->control_regs[clock->index / 32]); else value = readl(priv->base + priv->status_regs[clock->index / 32]); return !(value & BIT(clock->index % 32)); } static const struct clk_ops cpg_mstp_clock_ops = { .enable = cpg_mstp_clock_enable, .disable = cpg_mstp_clock_disable, .is_enabled = cpg_mstp_clock_is_enabled, }; static struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec, void *data) { unsigned int clkidx = clkspec->args[1]; struct cpg_mssr_priv *priv = data; struct device *dev = priv->dev; unsigned int idx; const char *type; struct clk *clk; int range_check; switch (clkspec->args[0]) { case CPG_CORE: type = "core"; if (clkidx > priv->last_dt_core_clk) { dev_err(dev, "Invalid %s clock index %u\n", type, clkidx); return ERR_PTR(-EINVAL); } clk = priv->clks[clkidx]; break; case CPG_MOD: type = "module"; if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { idx = MOD_CLK_PACK_10(clkidx); range_check = 7 - (clkidx % 10); } else { idx = MOD_CLK_PACK(clkidx); range_check = 31 - (clkidx % 100); } if (range_check < 0 || idx >= priv->num_mod_clks) { dev_err(dev, "Invalid %s clock index %u\n", type, clkidx); return ERR_PTR(-EINVAL); } clk = priv->clks[priv->num_core_clks + idx]; break; default: dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); return ERR_PTR(-EINVAL); } if (IS_ERR(clk)) dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx, PTR_ERR(clk)); else dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n", clkspec->args[0], clkspec->args[1], clk, clk_get_rate(clk)); return clk; } static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, const struct cpg_mssr_info *info, struct cpg_mssr_priv *priv) { struct clk *clk = ERR_PTR(-ENOTSUPP), *parent; struct device *dev = priv->dev; unsigned int id = core->id, div = core->div; const char *parent_name; WARN_DEBUG(id >= priv->num_core_clks); WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); if (!core->name) { /* Skip NULLified clock */ return; } switch (core->type) { case CLK_TYPE_IN: clk = of_clk_get_by_name(priv->np, core->name); break; case CLK_TYPE_FF: case CLK_TYPE_DIV6P1: case CLK_TYPE_DIV6_RO: WARN_DEBUG(core->parent >= priv->num_core_clks); parent = priv->clks[core->parent]; if (IS_ERR(parent)) { clk = parent; goto fail; } parent_name = __clk_get_name(parent); if (core->type == CLK_TYPE_DIV6_RO) /* Multiply with the DIV6 register value */ div *= (readl(priv->base + core->offset) & 0x3f) + 1; if (core->type == CLK_TYPE_DIV6P1) { clk = cpg_div6_register(core->name, 1, &parent_name, priv->base + core->offset, &priv->notifiers); } else { clk = clk_register_fixed_factor(NULL, core->name, parent_name, 0, core->mult, div); } break; case CLK_TYPE_FR: clk = clk_register_fixed_rate(NULL, core->name, NULL, 0, core->mult); break; default: if (info->cpg_clk_register) clk = info->cpg_clk_register(dev, core, info, priv->clks, priv->base, &priv->notifiers); else dev_err(dev, "%s has unsupported core clock type %u\n", core->name, core->type); break; } if (IS_ERR_OR_NULL(clk)) goto fail; dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); priv->clks[id] = clk; return; fail: dev_err(dev, "Failed to register %s clock %s: %ld\n", "core", core->name, PTR_ERR(clk)); } static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod, const struct cpg_mssr_info *info, struct cpg_mssr_priv *priv) { struct mstp_clock *clock = NULL; struct device *dev = priv->dev; unsigned int id = mod->id; struct clk_init_data init = {}; struct clk *parent, *clk; const char *parent_name; unsigned int i; WARN_DEBUG(id < priv->num_core_clks); WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); if (!mod->name) { /* Skip NULLified clock */ return; } parent = priv->clks[mod->parent]; if (IS_ERR(parent)) { clk = parent; goto fail; } clock = kzalloc(sizeof(*clock), GFP_KERNEL); if (!clock) { clk = ERR_PTR(-ENOMEM); goto fail; } init.name = mod->name; init.ops = &cpg_mstp_clock_ops; init.flags = CLK_SET_RATE_PARENT; parent_name = __clk_get_name(parent); init.parent_names = &parent_name; init.num_parents = 1; clock->index = id - priv->num_core_clks; clock->priv = priv; clock->hw.init = &init; for (i = 0; i < info->num_crit_mod_clks; i++) if (id == info->crit_mod_clks[i] && cpg_mstp_clock_is_enabled(&clock->hw)) { dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n", mod->name); init.flags |= CLK_IS_CRITICAL; break; } clk = clk_register(NULL, &clock->hw); if (IS_ERR(clk)) goto fail; dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); priv->clks[id] = clk; priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32); return; fail: dev_err(dev, "Failed to register %s clock %s: %ld\n", "module", mod->name, PTR_ERR(clk)); kfree(clock); } struct cpg_mssr_clk_domain { struct generic_pm_domain genpd; unsigned int num_core_pm_clks; unsigned int core_pm_clks[]; }; static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain; static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec, struct cpg_mssr_clk_domain *pd) { unsigned int i; if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2) return false; switch (clkspec->args[0]) { case CPG_CORE: for (i = 0; i < pd->num_core_pm_clks; i++) if (clkspec->args[1] == pd->core_pm_clks[i]) return true; return false; case CPG_MOD: return true; default: return false; } } int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev) { struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain; struct device_node *np = dev->of_node; struct of_phandle_args clkspec; struct clk *clk; int i = 0; int error; if (!pd) { dev_dbg(dev, "CPG/MSSR clock domain not yet available\n"); return -EPROBE_DEFER; } while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec)) { if (cpg_mssr_is_pm_clk(&clkspec, pd)) goto found; of_node_put(clkspec.np); i++; } return 0; found: clk = of_clk_get_from_provider(&clkspec); of_node_put(clkspec.np); if (IS_ERR(clk)) return PTR_ERR(clk); error = pm_clk_create(dev); if (error) goto fail_put; error = pm_clk_add_clk(dev, clk); if (error) goto fail_destroy; return 0; fail_destroy: pm_clk_destroy(dev); fail_put: clk_put(clk); return error; } void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev) { if (!pm_clk_no_clocks(dev)) pm_clk_destroy(dev); } static void cpg_mssr_genpd_remove(void *data) { pm_genpd_remove(data); } static int __init cpg_mssr_add_clk_domain(struct device *dev, const unsigned int *core_pm_clks, unsigned int num_core_pm_clks) { struct device_node *np = dev->of_node; struct generic_pm_domain *genpd; struct cpg_mssr_clk_domain *pd; size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]); int ret; pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL); if (!pd) return -ENOMEM; pd->num_core_pm_clks = num_core_pm_clks; memcpy(pd->core_pm_clks, core_pm_clks, pm_size); genpd = &pd->genpd; genpd->name = np->name; genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_ACTIVE_WAKEUP; genpd->attach_dev = cpg_mssr_attach_dev; genpd->detach_dev = cpg_mssr_detach_dev; ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false); if (ret) return ret; ret = devm_add_action_or_reset(dev, cpg_mssr_genpd_remove, genpd); if (ret) return ret; cpg_mssr_clk_domain = pd; return of_genpd_add_provider_simple(np, genpd); } #ifdef CONFIG_RESET_CONTROLLER #define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev) static int cpg_mssr_reset(struct reset_controller_dev *rcdev, unsigned long id) { struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); unsigned int reg = id / 32; unsigned int bit = id % 32; u32 bitmask = BIT(bit); dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); /* Reset module */ writel(bitmask, priv->base + priv->reset_regs[reg]); /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ udelay(35); /* Release module from reset state */ writel(bitmask, priv->base + priv->reset_clear_regs[reg]); return 0; } static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id) { struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); unsigned int reg = id / 32; unsigned int bit = id % 32; u32 bitmask = BIT(bit); dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); writel(bitmask, priv->base + priv->reset_regs[reg]); return 0; } static int cpg_mssr_deassert(struct reset_controller_dev *rcdev, unsigned long id) { struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); unsigned int reg = id / 32; unsigned int bit = id % 32; u32 bitmask = BIT(bit); dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); writel(bitmask, priv->base + priv->reset_clear_regs[reg]); return 0; } static int cpg_mssr_status(struct reset_controller_dev *rcdev, unsigned long id) { struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); unsigned int reg = id / 32; unsigned int bit = id % 32; u32 bitmask = BIT(bit); return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask); } static const struct reset_control_ops cpg_mssr_reset_ops = { .reset = cpg_mssr_reset, .assert = cpg_mssr_assert, .deassert = cpg_mssr_deassert, .status = cpg_mssr_status, }; static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev, const struct of_phandle_args *reset_spec) { struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); unsigned int unpacked = reset_spec->args[0]; unsigned int idx = MOD_CLK_PACK(unpacked); if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) { dev_err(priv->dev, "Invalid reset index %u\n", unpacked); return -EINVAL; } return idx; } static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) { priv->rcdev.ops = &cpg_mssr_reset_ops; priv->rcdev.of_node = priv->dev->of_node; priv->rcdev.of_reset_n_cells = 1; priv->rcdev.of_xlate = cpg_mssr_reset_xlate; priv->rcdev.nr_resets = priv->num_mod_clks; return devm_reset_controller_register(priv->dev, &priv->rcdev); } #else /* !CONFIG_RESET_CONTROLLER */ static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) { return 0; } #endif /* !CONFIG_RESET_CONTROLLER */ static const struct of_device_id cpg_mssr_match[] = { #ifdef CONFIG_CLK_R7S9210 { .compatible = "renesas,r7s9210-cpg-mssr", .data = &r7s9210_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A7742 { .compatible = "renesas,r8a7742-cpg-mssr", .data = &r8a7742_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A7743 { .compatible = "renesas,r8a7743-cpg-mssr", .data = &r8a7743_cpg_mssr_info, }, /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */ { .compatible = "renesas,r8a7744-cpg-mssr", .data = &r8a7743_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A7745 { .compatible = "renesas,r8a7745-cpg-mssr", .data = &r8a7745_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A77470 { .compatible = "renesas,r8a77470-cpg-mssr", .data = &r8a77470_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A774A1 { .compatible = "renesas,r8a774a1-cpg-mssr", .data = &r8a774a1_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A774B1 { .compatible = "renesas,r8a774b1-cpg-mssr", .data = &r8a774b1_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A774C0 { .compatible = "renesas,r8a774c0-cpg-mssr", .data = &r8a774c0_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A774E1 { .compatible = "renesas,r8a774e1-cpg-mssr", .data = &r8a774e1_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A7790 { .compatible = "renesas,r8a7790-cpg-mssr", .data = &r8a7790_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A7791 { .compatible = "renesas,r8a7791-cpg-mssr", .data = &r8a7791_cpg_mssr_info, }, /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */ { .compatible = "renesas,r8a7793-cpg-mssr", .data = &r8a7791_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A7792 { .compatible = "renesas,r8a7792-cpg-mssr", .data = &r8a7792_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A7794 { .compatible = "renesas,r8a7794-cpg-mssr", .data = &r8a7794_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A7795 { .compatible = "renesas,r8a7795-cpg-mssr", .data = &r8a7795_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A77960 { .compatible = "renesas,r8a7796-cpg-mssr", .data = &r8a7796_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A77961 { .compatible = "renesas,r8a77961-cpg-mssr", .data = &r8a7796_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A77965 { .compatible = "renesas,r8a77965-cpg-mssr", .data = &r8a77965_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A77970 { .compatible = "renesas,r8a77970-cpg-mssr", .data = &r8a77970_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A77980 { .compatible = "renesas,r8a77980-cpg-mssr", .data = &r8a77980_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A77990 { .compatible = "renesas,r8a77990-cpg-mssr", .data = &r8a77990_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A77995 { .compatible = "renesas,r8a77995-cpg-mssr", .data = &r8a77995_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A779A0 { .compatible = "renesas,r8a779a0-cpg-mssr", .data = &r8a779a0_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A779F0 { .compatible = "renesas,r8a779f0-cpg-mssr", .data = &r8a779f0_cpg_mssr_info, }, #endif #ifdef CONFIG_CLK_R8A779G0 { .compatible = "renesas,r8a779g0-cpg-mssr", .data = &r8a779g0_cpg_mssr_info, }, #endif { /* sentinel */ } }; static void cpg_mssr_del_clk_provider(void *data) { of_clk_del_provider(data); } #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW) static int cpg_mssr_suspend_noirq(struct device *dev) { struct cpg_mssr_priv *priv = dev_get_drvdata(dev); unsigned int reg; /* This is the best we can do to check for the presence of PSCI */ if (!psci_ops.cpu_suspend) return 0; /* Save module registers with bits under our control */ for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { if (priv->smstpcr_saved[reg].mask) priv->smstpcr_saved[reg].val = priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? readb(priv->base + priv->control_regs[reg]) : readl(priv->base + priv->control_regs[reg]); } /* Save core clocks */ raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL); return 0; } static int cpg_mssr_resume_noirq(struct device *dev) { struct cpg_mssr_priv *priv = dev_get_drvdata(dev); unsigned int reg; u32 mask, oldval, newval; int error; /* This is the best we can do to check for the presence of PSCI */ if (!psci_ops.cpu_suspend) return 0; /* Restore core clocks */ raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL); /* Restore module clocks */ for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { mask = priv->smstpcr_saved[reg].mask; if (!mask) continue; if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) oldval = readb(priv->base + priv->control_regs[reg]); else oldval = readl(priv->base + priv->control_regs[reg]); newval = oldval & ~mask; newval |= priv->smstpcr_saved[reg].val & mask; if (newval == oldval) continue; if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { writeb(newval, priv->base + priv->control_regs[reg]); /* dummy read to ensure write has completed */ readb(priv->base + priv->control_regs[reg]); barrier_data(priv->base + priv->control_regs[reg]); continue; } else writel(newval, priv->base + priv->control_regs[reg]); /* Wait until enabled clocks are really enabled */ mask &= ~priv->smstpcr_saved[reg].val; if (!mask) continue; error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg], oldval, !(oldval & mask), 0, 10); if (error) dev_warn(dev, "Failed to enable SMSTP%u[0x%x]\n", reg, oldval & mask); } return 0; } static const struct dev_pm_ops cpg_mssr_pm = { SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq, cpg_mssr_resume_noirq) }; #define DEV_PM_OPS &cpg_mssr_pm #else #define DEV_PM_OPS NULL #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ static int __init cpg_mssr_common_init(struct device *dev, struct device_node *np, const struct cpg_mssr_info *info) { struct cpg_mssr_priv *priv; unsigned int nclks, i; int error; if (info->init) { error = info->init(dev); if (error) return error; } nclks = info->num_total_core_clks + info->num_hw_mod_clks; priv = kzalloc(struct_size(priv, clks, nclks), GFP_KERNEL); if (!priv) return -ENOMEM; priv->np = np; priv->dev = dev; spin_lock_init(&priv->rmw_lock); priv->base = of_iomap(np, 0); if (!priv->base) { error = -ENOMEM; goto out_err; } priv->num_core_clks = info->num_total_core_clks; priv->num_mod_clks = info->num_hw_mod_clks; priv->last_dt_core_clk = info->last_dt_core_clk; RAW_INIT_NOTIFIER_HEAD(&priv->notifiers); priv->reg_layout = info->reg_layout; if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) { priv->status_regs = mstpsr; priv->control_regs = smstpcr; priv->reset_regs = srcr; priv->reset_clear_regs = srstclr; } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { priv->control_regs = stbcr; } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) { priv->status_regs = mstpsr_for_gen4; priv->control_regs = mstpcr_for_gen4; priv->reset_regs = srcr_for_gen4; priv->reset_clear_regs = srstclr_for_gen4; } else { error = -EINVAL; goto out_err; } for (i = 0; i < nclks; i++) priv->clks[i] = ERR_PTR(-ENOENT); error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv); if (error) goto out_err; cpg_mssr_priv = priv; return 0; out_err: if (priv->base) iounmap(priv->base); kfree(priv); return error; } void __init cpg_mssr_early_init(struct device_node *np, const struct cpg_mssr_info *info) { int error; int i; error = cpg_mssr_common_init(NULL, np, info); if (error) return; for (i = 0; i < info->num_early_core_clks; i++) cpg_mssr_register_core_clk(&info->early_core_clks[i], info, cpg_mssr_priv); for (i = 0; i < info->num_early_mod_clks; i++) cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info, cpg_mssr_priv); } static int __init cpg_mssr_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; const struct cpg_mssr_info *info; struct cpg_mssr_priv *priv; unsigned int i; int error; info = of_device_get_match_data(dev); if (!cpg_mssr_priv) { error = cpg_mssr_common_init(dev, dev->of_node, info); if (error) return error; } priv = cpg_mssr_priv; priv->dev = dev; dev_set_drvdata(dev, priv); for (i = 0; i < info->num_core_clks; i++) cpg_mssr_register_core_clk(&info->core_clks[i], info, priv); for (i = 0; i < info->num_mod_clks; i++) cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv); error = devm_add_action_or_reset(dev, cpg_mssr_del_clk_provider, np); if (error) return error; error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks, info->num_core_pm_clks); if (error) return error; /* Reset Controller not supported for Standby Control SoCs */ if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) return 0; error = cpg_mssr_reset_controller_register(priv); if (error) return error; return 0; } static struct platform_driver cpg_mssr_driver = { .driver = { .name = "renesas-cpg-mssr", .of_match_table = cpg_mssr_match, .pm = DEV_PM_OPS, }, }; static int __init cpg_mssr_init(void) { return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe); } subsys_initcall(cpg_mssr_init); void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks, unsigned int num_mod_clks, const unsigned int *clks, unsigned int n) { unsigned int i, j; for (i = 0, j = 0; i < num_mod_clks && j < n; i++) if (mod_clks[i].id == clks[j]) { mod_clks[i].name = NULL; j++; } } MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
linux-master
drivers/clk/renesas/renesas-cpg-mssr.c
// SPDX-License-Identifier: GPL-2.0 /* * r8a73a4 Core CPG Clocks * * Copyright (C) 2014 Ulrich Hecht */ #include <linux/clk-provider.h> #include <linux/clk/renesas.h> #include <linux/init.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/slab.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/spinlock.h> struct r8a73a4_cpg { struct clk_onecell_data data; spinlock_t lock; }; #define CPG_CKSCR 0xc0 #define CPG_FRQCRA 0x00 #define CPG_FRQCRB 0x04 #define CPG_FRQCRC 0xe0 #define CPG_PLL0CR 0xd8 #define CPG_PLL1CR 0x28 #define CPG_PLL2CR 0x2c #define CPG_PLL2HCR 0xe4 #define CPG_PLL2SCR 0xf4 #define CLK_ENABLE_ON_INIT BIT(0) struct div4_clk { const char *name; unsigned int reg; unsigned int shift; }; static struct div4_clk div4_clks[] = { { "i", CPG_FRQCRA, 20 }, { "m3", CPG_FRQCRA, 12 }, { "b", CPG_FRQCRA, 8 }, { "m1", CPG_FRQCRA, 4 }, { "m2", CPG_FRQCRA, 0 }, { "zx", CPG_FRQCRB, 12 }, { "zs", CPG_FRQCRB, 8 }, { "hp", CPG_FRQCRB, 4 }, { NULL, 0, 0 }, }; static const struct clk_div_table div4_div_table[] = { { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 } }; static struct clk * __init r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, void __iomem *base, const char *name) { const struct clk_div_table *table = NULL; const char *parent_name; unsigned int shift, reg; unsigned int mult = 1; unsigned int div = 1; if (!strcmp(name, "main")) { u32 ckscr = readl(base + CPG_CKSCR); switch ((ckscr >> 28) & 3) { case 0: /* extal1 */ parent_name = of_clk_get_parent_name(np, 0); break; case 1: /* extal1 / 2 */ parent_name = of_clk_get_parent_name(np, 0); div = 2; break; case 2: /* extal2 */ parent_name = of_clk_get_parent_name(np, 1); break; case 3: /* extal2 / 2 */ parent_name = of_clk_get_parent_name(np, 1); div = 2; break; } } else if (!strcmp(name, "pll0")) { /* PLL0/1 are configurable multiplier clocks. Register them as * fixed factor clocks for now as there's no generic multiplier * clock implementation and we currently have no need to change * the multiplier value. */ u32 value = readl(base + CPG_PLL0CR); parent_name = "main"; mult = ((value >> 24) & 0x7f) + 1; if (value & BIT(20)) div = 2; } else if (!strcmp(name, "pll1")) { u32 value = readl(base + CPG_PLL1CR); parent_name = "main"; /* XXX: enable bit? */ mult = ((value >> 24) & 0x7f) + 1; if (value & BIT(7)) div = 2; } else if (!strncmp(name, "pll2", 4)) { u32 value, cr; switch (name[4]) { case 0: cr = CPG_PLL2CR; break; case 's': cr = CPG_PLL2SCR; break; case 'h': cr = CPG_PLL2HCR; break; default: return ERR_PTR(-EINVAL); } value = readl(base + cr); switch ((value >> 5) & 7) { case 0: parent_name = "main"; div = 2; break; case 1: parent_name = "extal2"; div = 2; break; case 3: parent_name = "extal2"; div = 4; break; case 4: parent_name = "main"; break; case 5: parent_name = "extal2"; break; default: pr_warn("%s: unexpected parent of %s\n", __func__, name); return ERR_PTR(-EINVAL); } /* XXX: enable bit? */ mult = ((value >> 24) & 0x7f) + 1; } else if (!strcmp(name, "z") || !strcmp(name, "z2")) { u32 shift = 8; parent_name = "pll0"; if (name[1] == '2') { div = 2; shift = 0; } div *= 32; mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f); } else { struct div4_clk *c; for (c = div4_clks; c->name; c++) { if (!strcmp(name, c->name)) break; } if (!c->name) return ERR_PTR(-EINVAL); parent_name = "pll1"; table = div4_div_table; reg = c->reg; shift = c->shift; } if (!table) { return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div); } else { return clk_register_divider_table(NULL, name, parent_name, 0, base + reg, shift, 4, 0, table, &cpg->lock); } } static void __init r8a73a4_cpg_clocks_init(struct device_node *np) { struct r8a73a4_cpg *cpg; void __iomem *base; struct clk **clks; unsigned int i; int num_clks; num_clks = of_property_count_strings(np, "clock-output-names"); if (num_clks < 0) { pr_err("%s: failed to count clocks\n", __func__); return; } cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); if (cpg == NULL || clks == NULL) { /* We're leaking memory on purpose, there's no point in cleaning * up as the system won't boot anyway. */ return; } spin_lock_init(&cpg->lock); cpg->data.clks = clks; cpg->data.clk_num = num_clks; base = of_iomap(np, 0); if (WARN_ON(base == NULL)) return; for (i = 0; i < num_clks; ++i) { const char *name; struct clk *clk; of_property_read_string_index(np, "clock-output-names", i, &name); clk = r8a73a4_cpg_register_clock(np, cpg, base, name); if (IS_ERR(clk)) pr_err("%s: failed to register %pOFn %s clock (%ld)\n", __func__, np, name, PTR_ERR(clk)); else cpg->data.clks[i] = clk; } of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); } CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks", r8a73a4_cpg_clocks_init);
linux-master
drivers/clk/renesas/clk-r8a73a4.c
// SPDX-License-Identifier: GPL-2.0 /* * r8a7745 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2016 Cogent Embedded Inc. */ #include <linux/device.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/soc/renesas/rcar-rst.h> #include <dt-bindings/clock/r8a7745-cpg-mssr.h> #include "renesas-cpg-mssr.h" #include "rcar-gen2-cpg.h" enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A7745_CLK_OSC, /* External Input Clocks */ CLK_EXTAL, CLK_USB_EXTAL, /* Internal Core Clocks */ CLK_MAIN, CLK_PLL0, CLK_PLL1, CLK_PLL3, CLK_PLL1_DIV2, /* Module Clocks */ MOD_CLK_BASE }; static const struct cpg_core_clk r8a7745_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("usb_extal", CLK_USB_EXTAL), /* Internal Core Clocks */ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), /* Core Clock Outputs */ DEF_BASE("sdh", R8A7745_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), DEF_BASE("sd0", R8A7745_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), DEF_BASE("rcan", R8A7745_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL), DEF_FIXED("z2", R8A7745_CLK_Z2, CLK_PLL0, 1, 1), DEF_FIXED("zg", R8A7745_CLK_ZG, CLK_PLL1, 6, 1), DEF_FIXED("zx", R8A7745_CLK_ZX, CLK_PLL1, 3, 1), DEF_FIXED("zs", R8A7745_CLK_ZS, CLK_PLL1, 6, 1), DEF_FIXED("hp", R8A7745_CLK_HP, CLK_PLL1, 12, 1), DEF_FIXED("b", R8A7745_CLK_B, CLK_PLL1, 12, 1), DEF_FIXED("lb", R8A7745_CLK_LB, CLK_PLL1, 24, 1), DEF_FIXED("p", R8A7745_CLK_P, CLK_PLL1, 24, 1), DEF_FIXED("cl", R8A7745_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cp", R8A7745_CLK_CP, CLK_PLL1, 48, 1), DEF_FIXED("m2", R8A7745_CLK_M2, CLK_PLL1, 8, 1), DEF_FIXED("zb3", R8A7745_CLK_ZB3, CLK_PLL3, 4, 1), DEF_FIXED("zb3d2", R8A7745_CLK_ZB3D2, CLK_PLL3, 8, 1), DEF_FIXED("ddr", R8A7745_CLK_DDR, CLK_PLL3, 8, 1), DEF_FIXED("mp", R8A7745_CLK_MP, CLK_PLL1_DIV2, 15, 1), DEF_FIXED("cpex", R8A7745_CLK_CPEX, CLK_EXTAL, 2, 1), DEF_FIXED("r", R8A7745_CLK_R, CLK_PLL1, 49152, 1), DEF_FIXED("osc", R8A7745_CLK_OSC, CLK_PLL1, 12288, 1), DEF_DIV6P1("sd2", R8A7745_CLK_SD2, CLK_PLL1_DIV2, 0x078), DEF_DIV6P1("sd3", R8A7745_CLK_SD3, CLK_PLL1_DIV2, 0x26c), DEF_DIV6P1("mmc0", R8A7745_CLK_MMC0, CLK_PLL1_DIV2, 0x240), }; static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = { DEF_MOD("msiof0", 0, R8A7745_CLK_MP), DEF_MOD("vcp0", 101, R8A7745_CLK_ZS), DEF_MOD("vpc0", 103, R8A7745_CLK_ZS), DEF_MOD("tmu1", 111, R8A7745_CLK_P), DEF_MOD("3dg", 112, R8A7745_CLK_ZG), DEF_MOD("2d-dmac", 115, R8A7745_CLK_ZS), DEF_MOD("fdp1-0", 119, R8A7745_CLK_ZS), DEF_MOD("tmu3", 121, R8A7745_CLK_P), DEF_MOD("tmu2", 122, R8A7745_CLK_P), DEF_MOD("cmt0", 124, R8A7745_CLK_R), DEF_MOD("tmu0", 125, R8A7745_CLK_CP), DEF_MOD("vsp1du0", 128, R8A7745_CLK_ZS), DEF_MOD("vsps", 131, R8A7745_CLK_ZS), DEF_MOD("scifa2", 202, R8A7745_CLK_MP), DEF_MOD("scifa1", 203, R8A7745_CLK_MP), DEF_MOD("scifa0", 204, R8A7745_CLK_MP), DEF_MOD("msiof2", 205, R8A7745_CLK_MP), DEF_MOD("scifb0", 206, R8A7745_CLK_MP), DEF_MOD("scifb1", 207, R8A7745_CLK_MP), DEF_MOD("msiof1", 208, R8A7745_CLK_MP), DEF_MOD("scifb2", 216, R8A7745_CLK_MP), DEF_MOD("sys-dmac1", 218, R8A7745_CLK_ZS), DEF_MOD("sys-dmac0", 219, R8A7745_CLK_ZS), DEF_MOD("tpu0", 304, R8A7745_CLK_CP), DEF_MOD("sdhi3", 311, R8A7745_CLK_SD3), DEF_MOD("sdhi2", 312, R8A7745_CLK_SD2), DEF_MOD("sdhi0", 314, R8A7745_CLK_SD0), DEF_MOD("mmcif0", 315, R8A7745_CLK_MMC0), DEF_MOD("iic0", 318, R8A7745_CLK_HP), DEF_MOD("iic1", 323, R8A7745_CLK_HP), DEF_MOD("cmt1", 329, R8A7745_CLK_R), DEF_MOD("usbhs-dmac0", 330, R8A7745_CLK_HP), DEF_MOD("usbhs-dmac1", 331, R8A7745_CLK_HP), DEF_MOD("rwdt", 402, R8A7745_CLK_R), DEF_MOD("irqc", 407, R8A7745_CLK_CP), DEF_MOD("intc-sys", 408, R8A7745_CLK_ZS), DEF_MOD("audio-dmac0", 502, R8A7745_CLK_HP), DEF_MOD("pwm", 523, R8A7745_CLK_P), DEF_MOD("usb-ehci", 703, R8A7745_CLK_MP), DEF_MOD("usbhs", 704, R8A7745_CLK_HP), DEF_MOD("hscif2", 713, R8A7745_CLK_ZS), DEF_MOD("scif5", 714, R8A7745_CLK_P), DEF_MOD("scif4", 715, R8A7745_CLK_P), DEF_MOD("hscif1", 716, R8A7745_CLK_ZS), DEF_MOD("hscif0", 717, R8A7745_CLK_ZS), DEF_MOD("scif3", 718, R8A7745_CLK_P), DEF_MOD("scif2", 719, R8A7745_CLK_P), DEF_MOD("scif1", 720, R8A7745_CLK_P), DEF_MOD("scif0", 721, R8A7745_CLK_P), DEF_MOD("du1", 723, R8A7745_CLK_ZX), DEF_MOD("du0", 724, R8A7745_CLK_ZX), DEF_MOD("ipmmu-sgx", 800, R8A7745_CLK_ZX), DEF_MOD("vin1", 810, R8A7745_CLK_ZG), DEF_MOD("vin0", 811, R8A7745_CLK_ZG), DEF_MOD("etheravb", 812, R8A7745_CLK_HP), DEF_MOD("ether", 813, R8A7745_CLK_P), DEF_MOD("gpio6", 905, R8A7745_CLK_CP), DEF_MOD("gpio5", 907, R8A7745_CLK_CP), DEF_MOD("gpio4", 908, R8A7745_CLK_CP), DEF_MOD("gpio3", 909, R8A7745_CLK_CP), DEF_MOD("gpio2", 910, R8A7745_CLK_CP), DEF_MOD("gpio1", 911, R8A7745_CLK_CP), DEF_MOD("gpio0", 912, R8A7745_CLK_CP), DEF_MOD("can1", 915, R8A7745_CLK_P), DEF_MOD("can0", 916, R8A7745_CLK_P), DEF_MOD("qspi_mod", 917, R8A7745_CLK_QSPI), DEF_MOD("i2c5", 925, R8A7745_CLK_HP), DEF_MOD("i2c4", 927, R8A7745_CLK_HP), DEF_MOD("i2c3", 928, R8A7745_CLK_HP), DEF_MOD("i2c2", 929, R8A7745_CLK_HP), DEF_MOD("i2c1", 930, R8A7745_CLK_HP), DEF_MOD("i2c0", 931, R8A7745_CLK_HP), DEF_MOD("ssi-all", 1005, R8A7745_CLK_P), DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), DEF_MOD("scu-all", 1017, R8A7745_CLK_P), DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), DEF_MOD("scifa3", 1106, R8A7745_CLK_MP), DEF_MOD("scifa4", 1107, R8A7745_CLK_MP), DEF_MOD("scifa5", 1108, R8A7745_CLK_MP), }; static const unsigned int r8a7745_crit_mod_clks[] __initconst = { MOD_CLK_ID(402), /* RWDT */ MOD_CLK_ID(408), /* INTC-SYS (GIC) */ }; /* * CPG Clock Data */ /* * MD EXTAL PLL0 PLL1 PLL3 * 14 13 19 (MHz) *1 *2 *--------------------------------------------------- * 0 0 1 15 x200/3 x208/2 x88 * 0 1 1 20 x150/3 x156/2 x66 * 1 0 1 26 / 2 x230/3 x240/2 x102 * 1 1 1 30 / 2 x200/3 x208/2 x88 * * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3) * *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2) */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ (((md) & BIT(13)) >> 13)) static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = { /* EXTAL div PLL1 mult PLL3 mult PLL0 mult */ { 1, 208, 88, 200 }, { 1, 156, 66, 150 }, { 2, 240, 102, 230 }, { 2, 208, 88, 200 }, }; static int __init r8a7745_cpg_mssr_init(struct device *dev) { const struct rcar_gen2_cpg_pll_config *cpg_pll_config; u32 cpg_mode; int error; error = rcar_rst_read_mode_pins(&cpg_mode); if (error) return error; cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; return rcar_gen2_cpg_init(cpg_pll_config, 3, cpg_mode); } const struct cpg_mssr_info r8a7745_cpg_mssr_info __initconst = { /* Core Clocks */ .core_clks = r8a7745_core_clks, .num_core_clks = ARRAY_SIZE(r8a7745_core_clks), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Module Clocks */ .mod_clks = r8a7745_mod_clks, .num_mod_clks = ARRAY_SIZE(r8a7745_mod_clks), .num_hw_mod_clks = 12 * 32, /* Critical Module Clocks */ .crit_mod_clks = r8a7745_crit_mod_clks, .num_crit_mod_clks = ARRAY_SIZE(r8a7745_crit_mod_clks), /* Callbacks */ .init = r8a7745_cpg_mssr_init, .cpg_clk_register = rcar_gen2_cpg_clk_register, };
linux-master
drivers/clk/renesas/r8a7745-cpg-mssr.c
// SPDX-License-Identifier: GPL-2.0 /* * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2021 Renesas Electronics Corp. * * Based on r8a779a0-cpg-mssr.c */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/device.h> #include <linux/err.h> #include <linux/kernel.h> #include <linux/soc/renesas/rcar-rst.h> #include <dt-bindings/clock/r8a779f0-cpg-mssr.h> #include "renesas-cpg-mssr.h" #include "rcar-gen4-cpg.h" enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A779F0_CLK_R, /* External Input Clocks */ CLK_EXTAL, CLK_EXTALR, /* Internal Core Clocks */ CLK_MAIN, CLK_PLL1, CLK_PLL2, CLK_PLL3, CLK_PLL5, CLK_PLL6, CLK_PLL1_DIV2, CLK_PLL2_DIV2, CLK_PLL3_DIV2, CLK_PLL5_DIV2, CLK_PLL5_DIV4, CLK_PLL6_DIV2, CLK_S0, CLK_SASYNCPER, CLK_SDSRC, CLK_RPCSRC, CLK_OCO, /* Module Clocks */ MOD_CLK_BASE }; static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("extalr", CLK_EXTALR), /* Internal Core Clocks */ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN), DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN), DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1), DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1), DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1), DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5), DEF_RATE(".oco", CLK_OCO, 32768), DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), /* Core Clock Outputs */ DEF_GEN4_Z("z0", R8A779F0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0), DEF_GEN4_Z("z1", R8A779F0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 8), DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1), DEF_FIXED("cl16m", R8A779F0_CLK_CL16M, CLK_S0, 48, 1), DEF_FIXED("s0d2_mm", R8A779F0_CLK_S0D2_MM, CLK_S0, 2, 1), DEF_FIXED("s0d3_mm", R8A779F0_CLK_S0D3_MM, CLK_S0, 3, 1), DEF_FIXED("s0d4_mm", R8A779F0_CLK_S0D4_MM, CLK_S0, 4, 1), DEF_FIXED("cl16m_mm", R8A779F0_CLK_CL16M_MM, CLK_S0, 48, 1), DEF_FIXED("s0d2_rt", R8A779F0_CLK_S0D2_RT, CLK_S0, 2, 1), DEF_FIXED("s0d3_rt", R8A779F0_CLK_S0D3_RT, CLK_S0, 3, 1), DEF_FIXED("s0d4_rt", R8A779F0_CLK_S0D4_RT, CLK_S0, 4, 1), DEF_FIXED("s0d6_rt", R8A779F0_CLK_S0D6_RT, CLK_S0, 6, 1), DEF_FIXED("cl16m_rt", R8A779F0_CLK_CL16M_RT, CLK_S0, 48, 1), DEF_FIXED("s0d3_per", R8A779F0_CLK_S0D3_PER, CLK_S0, 3, 1), DEF_FIXED("s0d6_per", R8A779F0_CLK_S0D6_PER, CLK_S0, 6, 1), DEF_FIXED("s0d12_per", R8A779F0_CLK_S0D12_PER, CLK_S0, 12, 1), DEF_FIXED("s0d24_per", R8A779F0_CLK_S0D24_PER, CLK_S0, 24, 1), DEF_FIXED("cl16m_per", R8A779F0_CLK_CL16M_PER, CLK_S0, 48, 1), DEF_FIXED("s0d2_hsc", R8A779F0_CLK_S0D2_HSC, CLK_S0, 2, 1), DEF_FIXED("s0d3_hsc", R8A779F0_CLK_S0D3_HSC, CLK_S0, 3, 1), DEF_FIXED("s0d4_hsc", R8A779F0_CLK_S0D4_HSC, CLK_S0, 4, 1), DEF_FIXED("s0d6_hsc", R8A779F0_CLK_S0D6_HSC, CLK_S0, 6, 1), DEF_FIXED("s0d12_hsc", R8A779F0_CLK_S0D12_HSC, CLK_S0, 12, 1), DEF_FIXED("cl16m_hsc", R8A779F0_CLK_CL16M_HSC, CLK_S0, 48, 1), DEF_FIXED("s0d2_cc", R8A779F0_CLK_S0D2_CC, CLK_S0, 2, 1), DEF_FIXED("rsw2", R8A779F0_CLK_RSW2, CLK_PLL5_DIV2, 5, 1), DEF_FIXED("cbfusa", R8A779F0_CLK_CBFUSA, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1), DEF_FIXED("sasyncrt", R8A779F0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1), DEF_FIXED("sasyncperd1",R8A779F0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1), DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1), DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1), DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, 0x870), DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, 0x870), DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC), DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8), DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), }; static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("hscif0", 514, R8A779F0_CLK_SASYNCPERD1), DEF_MOD("hscif1", 515, R8A779F0_CLK_SASYNCPERD1), DEF_MOD("hscif2", 516, R8A779F0_CLK_SASYNCPERD1), DEF_MOD("hscif3", 517, R8A779F0_CLK_SASYNCPERD1), DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER), DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER), DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER), DEF_MOD("i2c3", 521, R8A779F0_CLK_S0D6_PER), DEF_MOD("i2c4", 522, R8A779F0_CLK_S0D6_PER), DEF_MOD("i2c5", 523, R8A779F0_CLK_S0D6_PER), DEF_MOD("msiof0", 618, R8A779F0_CLK_MSO), DEF_MOD("msiof1", 619, R8A779F0_CLK_MSO), DEF_MOD("msiof2", 620, R8A779F0_CLK_MSO), DEF_MOD("msiof3", 621, R8A779F0_CLK_MSO), DEF_MOD("pcie0", 624, R8A779F0_CLK_S0D2), DEF_MOD("pcie1", 625, R8A779F0_CLK_S0D2), DEF_MOD("scif0", 702, R8A779F0_CLK_SASYNCPERD4), DEF_MOD("scif1", 703, R8A779F0_CLK_SASYNCPERD4), DEF_MOD("scif3", 704, R8A779F0_CLK_SASYNCPERD4), DEF_MOD("scif4", 705, R8A779F0_CLK_SASYNCPERD4), DEF_MOD("sdhi0", 706, R8A779F0_CLK_SD0), DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER), DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), DEF_MOD("tmu0", 713, R8A779F0_CLK_SASYNCRT), DEF_MOD("tmu1", 714, R8A779F0_CLK_SASYNCPERD2), DEF_MOD("tmu2", 715, R8A779F0_CLK_SASYNCPERD2), DEF_MOD("tmu3", 716, R8A779F0_CLK_SASYNCPERD2), DEF_MOD("tmu4", 717, R8A779F0_CLK_SASYNCPERD2), DEF_MOD("wdt", 907, R8A779F0_CLK_R), DEF_MOD("cmt0", 910, R8A779F0_CLK_R), DEF_MOD("cmt1", 911, R8A779F0_CLK_R), DEF_MOD("cmt2", 912, R8A779F0_CLK_R), DEF_MOD("cmt3", 913, R8A779F0_CLK_R), DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M), DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M), DEF_MOD("rswitch2", 1505, R8A779F0_CLK_RSW2), DEF_MOD("ether-serdes", 1506, R8A779F0_CLK_S0D2_HSC), DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC), }; static const unsigned int r8a779f0_crit_mod_clks[] __initconst = { MOD_CLK_ID(907), /* WDT */ }; /* * CPG Clock Data */ /* * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC * 14 13 (MHz) * ------------------------------------------------------------------------ * 0 0 16 / 1 x200 x150 x200 n/a x200 x134 /15 * 0 1 20 / 1 x160 x120 x160 n/a x160 x106 /19 * 1 0 Prohibited setting * 1 1 40 / 2 x160 x120 x160 n/a x160 x106 /38 */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ (((md) & BIT(13)) >> 13)) static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ { 1, 200, 1, 150, 1, 200, 1, 0, 0, 200, 1, 134, 1, 15, }, { 1, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 19, }, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, { 2, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 38, }, }; static int __init r8a779f0_cpg_mssr_init(struct device *dev) { const struct rcar_gen4_cpg_pll_config *cpg_pll_config; u32 cpg_mode; int error; error = rcar_rst_read_mode_pins(&cpg_mode); if (error) return error; cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; if (!cpg_pll_config->extal_div) { dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); return -EINVAL; } return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); } const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = { /* Core Clocks */ .core_clks = r8a779f0_core_clks, .num_core_clks = ARRAY_SIZE(r8a779f0_core_clks), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, /* Module Clocks */ .mod_clks = r8a779f0_mod_clks, .num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks), .num_hw_mod_clks = 28 * 32, /* Critical Module Clocks */ .crit_mod_clks = r8a779f0_crit_mod_clks, .num_crit_mod_clks = ARRAY_SIZE(r8a779f0_crit_mod_clks), /* Callbacks */ .init = r8a779f0_cpg_mssr_init, .cpg_clk_register = rcar_gen4_cpg_clk_register, .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4, };
linux-master
drivers/clk/renesas/r8a779f0-cpg-mssr.c
// SPDX-License-Identifier: GPL-2.0 /* * R-Car Gen4 Clock Pulse Generator * * Copyright (C) 2021 Renesas Electronics Corp. * * Based on rcar-gen3-cpg.c * * Copyright (C) 2015-2018 Glider bvba * Copyright (C) 2019 Renesas Electronics Corp. */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/device.h> #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/slab.h> #include "renesas-cpg-mssr.h" #include "rcar-gen4-cpg.h" #include "rcar-cpg-lib.h" static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initdata; static unsigned int cpg_clk_extalr __initdata; static u32 cpg_mode __initdata; #define CPG_PLLECR 0x0820 /* PLL Enable Control Register */ #define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \ (n) > 3 ? (n) + 1 : n)) /* PLLn Circuit Status */ #define CPG_PLL1CR0 0x830 /* PLLn Control Registers */ #define CPG_PLL1CR1 0x8b0 #define CPG_PLL2CR0 0x834 #define CPG_PLL2CR1 0x8b8 #define CPG_PLL3CR0 0x83c #define CPG_PLL3CR1 0x8c0 #define CPG_PLL4CR0 0x844 #define CPG_PLL4CR1 0x8c8 #define CPG_PLL6CR0 0x84c #define CPG_PLL6CR1 0x8d8 #define CPG_PLLxCR0_KICK BIT(31) #define CPG_PLLxCR0_NI GENMASK(27, 20) /* Integer mult. factor */ #define CPG_PLLxCR0_SSMODE GENMASK(18, 16) /* PLL mode */ #define CPG_PLLxCR0_SSMODE_FM BIT(18) /* Fractional Multiplication */ #define CPG_PLLxCR0_SSMODE_DITH BIT(17) /* Frequency Dithering */ #define CPG_PLLxCR0_SSMODE_CENT BIT(16) /* Center (vs. Down) Spread Dithering */ #define CPG_PLLxCR0_SSFREQ GENMASK(14, 8) /* SSCG Modulation Frequency */ #define CPG_PLLxCR0_SSDEPT GENMASK(6, 0) /* SSCG Modulation Depth */ #define SSMODE_FM BIT(2) /* Fractional Multiplication */ #define SSMODE_DITHER BIT(1) /* Frequency Dithering */ #define SSMODE_CENTER BIT(0) /* Center (vs. Down) Spread Dithering */ /* PLL Clocks */ struct cpg_pll_clk { struct clk_hw hw; void __iomem *pllcr0_reg; void __iomem *pllecr_reg; u32 pllecr_pllst_mask; }; #define to_pll_clk(_hw) container_of(_hw, struct cpg_pll_clk, hw) static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct cpg_pll_clk *pll_clk = to_pll_clk(hw); unsigned int mult; mult = FIELD_GET(CPG_PLLxCR0_NI, readl(pll_clk->pllcr0_reg)) + 1; return parent_rate * mult * 2; } static int cpg_pll_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { unsigned int min_mult, max_mult, mult; unsigned long prate; prate = req->best_parent_rate * 2; min_mult = max(div64_ul(req->min_rate, prate), 1ULL); max_mult = min(div64_ul(req->max_rate, prate), 256ULL); if (max_mult < min_mult) return -EINVAL; mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); mult = clamp(mult, min_mult, max_mult); req->rate = prate * mult; return 0; } static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct cpg_pll_clk *pll_clk = to_pll_clk(hw); unsigned int mult; u32 val; mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * 2); mult = clamp(mult, 1U, 256U); if (readl(pll_clk->pllcr0_reg) & CPG_PLLxCR0_KICK) return -EBUSY; cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_NI, FIELD_PREP(CPG_PLLxCR0_NI, mult - 1)); /* * Set KICK bit in PLLxCR0 to update hardware setting and wait for * clock change completion. */ cpg_reg_modify(pll_clk->pllcr0_reg, 0, CPG_PLLxCR0_KICK); /* * Note: There is no HW information about the worst case latency. * * Using experimental measurements, it seems that no more than * ~45 µs are needed, independently of the CPU rate. * Since this value might be dependent on external xtal rate, pll * rate or even the other emulation clocks rate, use 1000 as a * "super" safe value. */ return readl_poll_timeout(pll_clk->pllecr_reg, val, val & pll_clk->pllecr_pllst_mask, 0, 1000); } static const struct clk_ops cpg_pll_clk_ops = { .recalc_rate = cpg_pll_clk_recalc_rate, .determine_rate = cpg_pll_clk_determine_rate, .set_rate = cpg_pll_clk_set_rate, }; static struct clk * __init cpg_pll_clk_register(const char *name, const char *parent_name, void __iomem *base, unsigned int cr0_offset, unsigned int cr1_offset, unsigned int index) { struct cpg_pll_clk *pll_clk; struct clk_init_data init = {}; struct clk *clk; pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); if (!pll_clk) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &cpg_pll_clk_ops; init.parent_names = &parent_name; init.num_parents = 1; pll_clk->hw.init = &init; pll_clk->pllcr0_reg = base + cr0_offset; pll_clk->pllecr_reg = base + CPG_PLLECR; pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index); /* Disable Fractional Multiplication and Frequency Dithering */ writel(0, base + cr1_offset); cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_SSMODE, 0); clk = clk_register(NULL, &pll_clk->hw); if (IS_ERR(clk)) kfree(pll_clk); return clk; } /* * Z0 Clock & Z1 Clock */ #define CPG_FRQCRB 0x00000804 #define CPG_FRQCRB_KICK BIT(31) #define CPG_FRQCRC 0x00000808 struct cpg_z_clk { struct clk_hw hw; void __iomem *reg; void __iomem *kick_reg; unsigned long max_rate; /* Maximum rate for normal mode */ unsigned int fixed_div; u32 mask; }; #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct cpg_z_clk *zclk = to_z_clk(hw); unsigned int mult; u32 val; val = readl(zclk->reg) & zclk->mask; mult = 32 - (val >> __ffs(zclk->mask)); return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * zclk->fixed_div); } static int cpg_z_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct cpg_z_clk *zclk = to_z_clk(hw); unsigned int min_mult, max_mult, mult; unsigned long rate, prate; rate = min(req->rate, req->max_rate); if (rate <= zclk->max_rate) { /* Set parent rate to initial value for normal modes */ prate = zclk->max_rate; } else { /* Set increased parent rate for boost modes */ prate = rate; } req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), prate * zclk->fixed_div); prate = req->best_parent_rate / zclk->fixed_div; min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); if (max_mult < min_mult) return -EINVAL; mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate); mult = clamp(mult, min_mult, max_mult); req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); return 0; } static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct cpg_z_clk *zclk = to_z_clk(hw); unsigned int mult; unsigned int i; mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, parent_rate); mult = clamp(mult, 1U, 32U); if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) return -EBUSY; cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); /* * Set KICK bit in FRQCRB to update hardware setting and wait for * clock change completion. */ cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK); /* * Note: There is no HW information about the worst case latency. * * Using experimental measurements, it seems that no more than * ~10 iterations are needed, independently of the CPU rate. * Since this value might be dependent on external xtal rate, pll1 * rate or even the other emulation clocks rate, use 1000 as a * "super" safe value. */ for (i = 1000; i; i--) { if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) return 0; cpu_relax(); } return -ETIMEDOUT; } static const struct clk_ops cpg_z_clk_ops = { .recalc_rate = cpg_z_clk_recalc_rate, .determine_rate = cpg_z_clk_determine_rate, .set_rate = cpg_z_clk_set_rate, }; static struct clk * __init cpg_z_clk_register(const char *name, const char *parent_name, void __iomem *reg, unsigned int div, unsigned int offset) { struct clk_init_data init = {}; struct cpg_z_clk *zclk; struct clk *clk; zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); if (!zclk) return ERR_PTR(-ENOMEM); init.name = name; init.ops = &cpg_z_clk_ops; init.flags = CLK_SET_RATE_PARENT; init.parent_names = &parent_name; init.num_parents = 1; zclk->reg = reg + CPG_FRQCRC; zclk->kick_reg = reg + CPG_FRQCRB; zclk->hw.init = &init; zclk->mask = GENMASK(offset + 4, offset); zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ clk = clk_register(NULL, &zclk->hw); if (IS_ERR(clk)) { kfree(zclk); return clk; } zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) / zclk->fixed_div; return clk; } /* * RPC Clocks */ static const struct clk_div_table cpg_rpcsrc_div_table[] = { { 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 }, }; struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core, const struct cpg_mssr_info *info, struct clk **clks, void __iomem *base, struct raw_notifier_head *notifiers) { const struct clk *parent; unsigned int mult = 1; unsigned int div = 1; u32 value; parent = clks[core->parent & 0xffff]; /* some types use high bits */ if (IS_ERR(parent)) return ERR_CAST(parent); switch (core->type) { case CLK_TYPE_GEN4_MAIN: div = cpg_pll_config->extal_div; break; case CLK_TYPE_GEN4_PLL1: mult = cpg_pll_config->pll1_mult; div = cpg_pll_config->pll1_div; break; case CLK_TYPE_GEN4_PLL2_VAR: /* * PLL2 is implemented as a custom clock, to change the * multiplier when cpufreq changes between normal and boost * modes. */ return cpg_pll_clk_register(core->name, __clk_get_name(parent), base, CPG_PLL2CR0, CPG_PLL2CR1, 2); case CLK_TYPE_GEN4_PLL2: mult = cpg_pll_config->pll2_mult; div = cpg_pll_config->pll2_div; break; case CLK_TYPE_GEN4_PLL3: mult = cpg_pll_config->pll3_mult; div = cpg_pll_config->pll3_div; break; case CLK_TYPE_GEN4_PLL4: mult = cpg_pll_config->pll4_mult; div = cpg_pll_config->pll4_div; break; case CLK_TYPE_GEN4_PLL5: mult = cpg_pll_config->pll5_mult; div = cpg_pll_config->pll5_div; break; case CLK_TYPE_GEN4_PLL6: mult = cpg_pll_config->pll6_mult; div = cpg_pll_config->pll6_div; break; case CLK_TYPE_GEN4_PLL2X_3X: value = readl(base + core->offset); mult = (((value >> 24) & 0x7f) + 1) * 2; break; case CLK_TYPE_GEN4_Z: return cpg_z_clk_register(core->name, __clk_get_name(parent), base, core->div, core->offset); case CLK_TYPE_GEN4_SDSRC: div = ((readl(base + SD0CKCR1) >> 29) & 0x03) + 4; break; case CLK_TYPE_GEN4_SDH: return cpg_sdh_clk_register(core->name, base + core->offset, __clk_get_name(parent), notifiers); case CLK_TYPE_GEN4_SD: return cpg_sd_clk_register(core->name, base + core->offset, __clk_get_name(parent)); case CLK_TYPE_GEN4_MDSEL: /* * Clock selectable between two parents and two fixed dividers * using a mode pin */ if (cpg_mode & BIT(core->offset)) { div = core->div & 0xffff; } else { parent = clks[core->parent >> 16]; if (IS_ERR(parent)) return ERR_CAST(parent); div = core->div >> 16; } mult = 1; break; case CLK_TYPE_GEN4_OSC: /* * Clock combining OSC EXTAL predivider and a fixed divider */ div = cpg_pll_config->osc_prediv * core->div; break; case CLK_TYPE_GEN4_RPCSRC: return clk_register_divider_table(NULL, core->name, __clk_get_name(parent), 0, base + CPG_RPCCKCR, 3, 2, 0, cpg_rpcsrc_div_table, &cpg_lock); case CLK_TYPE_GEN4_RPC: return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR, __clk_get_name(parent), notifiers); case CLK_TYPE_GEN4_RPCD2: return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR, __clk_get_name(parent)); default: return ERR_PTR(-EINVAL); } return clk_register_fixed_factor(NULL, core->name, __clk_get_name(parent), 0, mult, div); } int __init rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config, unsigned int clk_extalr, u32 mode) { cpg_pll_config = config; cpg_clk_extalr = clk_extalr; cpg_mode = mode; spin_lock_init(&cpg_lock); return 0; }
linux-master
drivers/clk/renesas/rcar-gen4-cpg.c