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tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc947.vhd | 4 | 1775 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc947.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00947ent IS
END c06s01b00x00p10n01i00947ent;
ARCHITECTURE c06s01b00x00p10n01i00947arch OF c06s01b00x00p10n01i00947ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
variable V1: BOOLEAN;
BEGIN
V1 := R1'(RE1=>TRUE).RE1;
-- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s01b00x00p10n01i00947 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00947arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug24326/tb_thingy9.vhdl | 2 | 353 | entity tb_thingy is
end tb_thingy;
architecture tb of tb_thingy is
component thingy is
generic (
a_a : integer
);
port (
x%x : in bit; -- <==
y_y : out bit
);
end component;
signal stimuli : bit;
signal response : bit;
begin
dut : thingy
generic map (
a_a => 42
)
port map (
x_x => stimuli,
y_y => response
);
end tb;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1341.vhd | 4 | 1777 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1341.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n01i01341ent IS
END c08s04b01x00p04n01i01341ent;
ARCHITECTURE c08s04b01x00p04n01i01341arch OF c08s04b01x00p04n01i01341ent IS
signal X : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
X <= 15 after 10 sec;
wait for 10 sec;
assert NOT( X=15 )
report "***PASSED TEST: c08s04b01x00p04n01i01341"
severity NOTE;
assert ( X=15 )
report "***FAILED TEST: c08s04b01x00p04n01i01341 - Predefined TIME unit sec as the base type of the time expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n01i01341arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/dispout01/tb_rec04.vhdl | 1 | 489 | entity tb_rec04 is
end tb_rec04;
library ieee;
use ieee.std_logic_1164.all;
use work.rec04_pkg.all;
architecture behav of tb_rec04 is
signal inp : std_logic;
signal r : myrec;
begin
dut: entity work.rec04
port map (inp => inp, o => r);
process
begin
inp <= '1';
wait for 1 ns;
assert r = (a => "0001", b => '0') severity failure;
inp <= '0';
wait for 1 ns;
assert r = (a => "1000", b => '1') severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_03.vhd | 4 | 1500 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
library ieee;
architecture test of inline_03 is
begin
process_3_a : process is
-- code from book:
use work.cpu_types;
variable data_word : cpu_types.word;
variable next_address : cpu_types.address;
-- end of code from book
begin
wait;
end process process_3_a;
----------------
process_3_b : process is
-- code from book:
use work.cpu_types.word, work.cpu_types.address;
variable data_word : word;
variable next_address : address;
-- end of code from book
begin
wait;
end process process_3_b;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/perf02-long/quant26bt_pos.vhd | 3 | 2202 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity quant26bt_pos is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0)
);
end quant26bt_pos;
architecture augh of quant26bt_pos is
-- Embedded RAM
type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("00000000000000000000000000111101", "00000000000000000000000000111100", "00000000000000000000000000111011", "00000000000000000000000000111010", "00000000000000000000000000111001", "00000000000000000000000000111000", "00000000000000000000000000110111", "00000000000000000000000000110110", "00000000000000000000000000110101", "00000000000000000000000000110100", "00000000000000000000000000110011", "00000000000000000000000000110010", "00000000000000000000000000110001", "00000000000000000000000000110000", "00000000000000000000000000101111", "00000000000000000000000000101110", "00000000000000000000000000101101", "00000000000000000000000000101100", "00000000000000000000000000101011", "00000000000000000000000000101010", "00000000000000000000000000101001", "00000000000000000000000000101000", "00000000000000000000000000100111", "00000000000000000000000000100110", "00000000000000000000000000100101", "00000000000000000000000000100100", "00000000000000000000000000100011", "00000000000000000000000000100010", "00000000000000000000000000100001", "00000000000000000000000000100000", "00000000000000000000000000100000", "00000000000000000000000000000000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_01.vhd | 4 | 1842 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
begin
process is
-- code from book:
type integer_file is file of integer;
file lookup_table_file : integer_file is "lookup-values";
-- end of code from book
begin
wait;
end process;
process is
-- code from book:
type file_open_kind is (read_mode, write_mode, append_mode);
-- end of code from book
begin
wait;
end process;
process is
type element_type is (t1, t2, t3);
-- code from book:
type file_type is file of element_type;
procedure read ( file f : file_type; value : out element_type );
function endfile ( file f : file_type ) return boolean;
-- end of code from book
procedure read ( file f : file_type; value : out element_type ) is
begin
end;
function endfile ( file f : file_type ) return boolean is
begin
end;
begin
wait;
end process;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball_wa.vhd | 4 | 1495 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ENTITY ball_wa IS
END ENTITY ball_wa;
ARCHITECTURE simple OF ball_wa IS
QUANTITY v: real;
QUANTITY s: real;
CONSTANT G: real := 9.81;
CONSTANT Air_Res: real := 0.1;
SIGNAL damping: real := -0.7;
signal v_at_impact : real:= 0.0;
signal impact: boolean;
BEGIN
if domain = quiescent_domain use
v == 0.0;
s == 30.0;
elsif impact use
v == damping*v_at_impact;
s == 0.0;
else
s'dot == v;
v'dot == -G;
end use;
process begin
wait until not s'above(0.0);
if v < -1.0e-9 then
v_at_impact <= v;
impact <= true, false after 1 us;
else
damping <= 0.0;
impact <= true;
end if;
end process;
break on impact;
END architecture simple;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_01.vhd | 4 | 1647 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_01.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_01 is
end entity ch_03_01;
architecture test of ch_03_01 is
signal en : bit := '0';
signal data_in : integer := 0;
begin
process_3_1_a : process (en, data_in) is
variable stored_value : integer := 0;
begin
-- code from book:
if en = '1' then
stored_value := data_in;
end if;
-- end of code from book
end process process_3_1_a;
stimulus : process is
begin
en <= '1' after 10 ns, '0' after 20 ns;
data_in <= 1 after 5 ns, 2 after 15 ns, 3 after 25 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/add_483.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_483 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_483;
architecture augh of add_483 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1849.vhd | 4 | 1675 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1849.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01849ent IS
END c07s01b00x00p08n01i01849ent;
ARCHITECTURE c07s01b00x00p08n01i01849arch OF c07s01b00x00p08n01i01849ent IS
type byte is range c07s01b00x00p08n01i01849arch to 3;
BEGIN
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01849 - Architecture body names are not permitted as primaries in a range expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01849arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket37/genbool.vhdl | 3 | 149 | entity genbool is
generic (val : boolean := False);
end genbool;
architecture behav of genbool is
begin
assert val severity failure;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc854.vhd | 4 | 10189 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc854.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00854pkg_b is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00854pkg_b;
package body c01s03b01x00p12n01i00854pkg_b is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00854pkg_b;
use work.c01s03b01x00p12n01i00854pkg_b.all;
package c01s03b01x00p12n01i00854pkg_a is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant dumy : bit_vector(zero to three) := "1010";
signal Sin1 : bit_vector(zero to five) ;
signal Sin2 : boolean_vector(zero to five) ;
signal Sin4 : severity_level_vector(zero to five) ;
signal Sin5 : integer_vector(zero to five) ;
signal Sin6 : real_vector(zero to five) ;
signal Sin7 : time_vector(zero to five) ;
signal Sin8 : natural_vector(zero to five) ;
signal Sin9 : positive_vector(zero to five) ;
signal Sin10: array_rec_std(zero to five) ;
end c01s03b01x00p12n01i00854pkg_a;
use work.c01s03b01x00p12n01i00854pkg_a.all;
use work.c01s03b01x00p12n01i00854pkg_b.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00854pkg_a.all;
use work.c01s03b01x00p12n01i00854pkg_b.all;
ENTITY c01s03b01x00p12n01i00854ent IS
END c01s03b01x00p12n01i00854ent;
ARCHITECTURE c01s03b01x00p12n01i00854arch OF c01s03b01x00p12n01i00854ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00854"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00854 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00854arch;
configuration c01s03b01x00p12n01i00854cfg of c01s03b01x00p12n01i00854ent is
for c01s03b01x00p12n01i00854arch
for K
for T5:test use configuration work.testbench;
end for;
for G(dumy'reverse_range(1))
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/mem02/tb_ram3.vhdl | 1 | 704 | entity tb_ram3 is
end tb_ram3;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ram3 is
signal val : std_logic_vector(7 downto 0);
signal waddr : std_logic_vector(2 downto 0);
signal wdat : std_logic;
signal clk : std_logic;
begin
dut: entity work.ram3
port map (waddr => waddr, wdat => wdat, val => val,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
waddr <= "000";
wdat <= '0';
pulse;
waddr <= "001";
wdat <= '1';
pulse;
assert (val and x"03") = x"02" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2406.vhd | 4 | 1776 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2406.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n05i02406ent IS
END c07s03b02x00p08n05i02406ent;
ARCHITECTURE c07s03b02x00p08n05i02406arch OF c07s03b02x00p08n05i02406ent IS
type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
signal S1 : ARRAY_TYPE(1 to 2) ;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= (others=>TRUE,TRUE); -- Failure_here
-- SEMANTIC ERROR: association cannot follow "others" association.
assert FALSE
report "***FAILED TEST: c07s03b02x00p08n05i02406 - Nothing may follow an others association."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n05i02406arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_06.vhd | 4 | 1525 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity mux2 is
port ( a, b, sel : in bit;
z : out bit );
end entity mux2;
--------------------------------------------------
architecture behavioral of mux2 is
constant prop_delay : time := 2 ns;
begin
slick_mux : process is
begin
case sel is
when '0' =>
z <= a after prop_delay;
wait on sel, a;
when '1' =>
z <= b after prop_delay;
wait on sel, b;
end case;
end process slick_mux;
end architecture behavioral;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue312/test.vhdl | 2 | 231 | package pkg is
generic (
type T
);
end package;
use work.pkg.all;
entity test is
end entity;
architecture tb of test is
package p is new package pkg
generic map (
T => integer
);
begin
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1935.vhd | 4 | 1945 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1935.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01935ent IS
END c07s02b01x00p01n04i01935ent;
ARCHITECTURE c07s02b01x00p01n04i01935arch OF c07s02b01x00p01n04i01935ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
z := (x nand y); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01935 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01935arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc278.vhd | 4 | 1984 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc278.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p07n01i00278ent IS
END c03s01b03x00p07n01i00278ent;
ARCHITECTURE c03s01b03x00p07n01i00278arch OF c03s01b03x00p07n01i00278ent IS
type twos_complement_integer is range -32768 to 32767;
type J is
range twos_complement_integer'low to twos_complement_integer'high
units -- Success_here
A;
B = 10 A;
C = 10 B;
D = 10 C;
end units;
BEGIN
TESTING: PROCESS
variable k : J := 31000 A;
BEGIN
k := 5 A;
assert NOT(k=5 A)
report "***PASSED TEST: c03s01b03x00p07n01i00278"
severity NOTE;
assert (k=5 A)
report "***FAILED TEST: c03s01b03x00p07n01i00278 - The bounds in the range constraint are not locally static expressions."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p07n01i00278arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc107.vhd | 4 | 1712 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc107.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n06i00107ent IS
port ( signal S : out bit) ;
END c04s03b02x00p29n06i00107ent;
ARCHITECTURE c04s03b02x00p29n06i00107arch OF c04s03b02x00p29n06i00107ent IS
BEGIN
TESTING: PROCESS
variable T : TIME := 10 ns;
BEGIN
if (S'LAST_ACTIVE = T) then -- Failure_here
end if;
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n06i00107 - The attribute LAST_ACTIVE of a signal of mode out cannot be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00107arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/gate_components.vhd | 4 | 1502 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- analyze into resource library graphics
package graphics_pkg is
attribute graphic_symbol : string;
attribute graphic_style : string;
end package graphics_pkg;
-- code from book
library ieee; use ieee.std_logic_1164.all;
library graphics;
package gate_components is
use graphics.graphics_pkg.graphic_symbol,
graphics.graphics_pkg.graphic_style;
component and2 is
generic ( prop_delay : delay_length );
port ( a, b : in std_logic; y : out std_logic );
end component and2;
attribute graphic_symbol of and2 : component is "and2";
attribute graphic_style of and2 : component is "color:default, weight:bold";
-- . . .
end package gate_components;
-- end code from book
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/synth60/leds_wrapper_arch_entity_inst.vhdl | 1 | 314 | architecture rtl_comp_inst of leds_wrapper is
begin
leds_comp_inst : entity work.leds(spin1)
port map(
clk => clk,
led1 => led1,
led2 => led2,
led3 => led3,
led4 => led4,
led5 => led5,
led6 => led6,
led7 => led7,
led8 => led8
);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/fsm01/tb_fsm_3s.vhdl | 1 | 887 | entity tb_fsm_3s is
end tb_fsm_3s;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_fsm_3s is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic;
signal done : std_logic;
begin
dut: entity work.fsm_3s
port map (
done => done,
d => din,
clk => clk,
rst => rst);
process
constant dat : std_logic_vector := b"101_101_1100";
constant res : std_logic_vector := b"001_001_0000";
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
din <= '0';
pulse;
assert done = '0' severity failure;
-- Test the whole sequence.
rst <= '0';
for i in dat'range loop
din <= dat (i);
pulse;
assert done = res(i) severity failure;
end loop;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue238/repro1.vhdl | 2 | 247 | ENTITY repro1 IS
TYPE foo_t IS RECORD
bar : bit_vector;
END RECORD foo_t;
END ENTITY repro1;
ARCHITECTURE bar OF repro1 IS
BEGIN
process
variable baz : foo_t(bar(1 DOWNTO 0));
begin
wait;
end process;
END ARCHITECTURE bar;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1078.vhd | 4 | 2149 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1078.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p01n02i01078ent IS
END c06s05b00x00p01n02i01078ent;
ARCHITECTURE c06s05b00x00p01n02i01078arch OF c06s05b00x00p01n02i01078ent IS
SUBTYPE bit_vector_4 is bit_vector ( 0 to 3 );
SUBTYPE bit_vector_8 is bit_vector ( 0 to 7 );
SIGNAL resultt : boolean;
procedure subprogram ( VARIABLE v : IN bit_vector_4; signal result : out boolean ) is
begin
if ( v = B"1010" ) then
result <= true;
else
result <= false;
end if;
end ;
BEGIN
TESTING: PROCESS
VARIABLE v_slice : bit_vector_8 := B"1010_1100";
BEGIN
subprogram ( v_slice ( 0 to 3 ), resultt );
wait for 1 ns;
assert NOT( resultt = true )
report "***PASSED TEST: c06s05b00x00p01n02i01078"
severity NOTE;
assert ( resultt = true )
report "***FAILED TEST: c06s05b00x00p01n02i01078 - A slice of a variable should still be a variable."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p01n02i01078arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug08/paren11.vhdl | 3 | 354 | entity paren11 is
end paren11;
architecture behav of paren11
is
begin
process
type string_acc is access string;
variable hel : string_acc := new string'("hello");
impure function a return string_acc is
begin
return hel;
end a;
constant b : natural := 2;
begin
assert a(b) = 'e';
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/sub_303.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_303 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_303;
architecture augh of sub_303 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2779.vhd | 4 | 1606 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2779.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ARRAY is
end ARRAY;
ENTITY c13s09b00x00p99n01i02779ent IS
END c13s09b00x00p99n01i02779ent;
ARCHITECTURE c13s09b00x00p99n01i02779arch OF c13s09b00x00p99n01i02779ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02779 - Reserved word ARRAY can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02779_arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1019.vhd | 4 | 2237 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1019.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n01i01019ent IS
port (p : in bit);
END c06s03b00x00p10n01i01019ent;
ARCHITECTURE c06s03b00x00p10n01i01019arch OF c06s03b00x00p10n01i01019ent IS
BEGIN
B1:Block
type chars is ('a', 'b', 'c', 'd', 'e');
begin
TESTING: PROCESS
variable c : chars;
variable All_done : boolean;
BEGIN
L1 : for LL1 in TRUE downto FALSE loop
NULL;
if L1.LL1 then -- Selected prefix is loop,
-- suffix is identifier that
-- refers to loop iteration id.
All_done := True;
end if;
end loop L1;
assert NOT(All_done=TRUE)
report "***PASSED TEST: c06s03b00x00p10n01i01019"
severity NOTE;
assert (All_done=TRUE)
report "***FAILED TEST: c06s03b00x00p10n01i01019 - Entity declaration does not occur in construct specifed by the prefix."
severity ERROR;
wait;
END PROCESS TESTING;
end block B1;
END c06s03b00x00p10n01i01019arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/rec01/pkg_rec01.vhdl | 1 | 195 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package rec01_pkg is
type myrec is record
a : unsigned (3 downto 0);
b : std_logic;
end record;
end rec01_pkg;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/perf02-long/qq4_code4_table.vhd | 3 | 1632 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity qq4_code4_table is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(3 downto 0)
);
end qq4_code4_table;
architecture augh of qq4_code4_table is
-- Embedded RAM
type ram_type is array (0 to 15) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("00000000000000000000000000000000", "11111111111111111011000000011000", "11111111111111111100110110100000", "11111111111111111101110011111000", "11111111111111111110011101110000", "11111111111111111110111101110000", "11111111111111111111010111101000", "11111111111111111111101101010000", "00000000000000000100111111101000", "00000000000000000011001001100000", "00000000000000000010001100001000", "00000000000000000001100010010000", "00000000000000000001000010010000", "00000000000000000000101000011000", "00000000000000000000010010110000", "00000000000000000000000000000000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue692/ent.vhdl | 1 | 231 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb is end entity;
architecture arch of tb is
signal reproducer: unsigned(15 downto 0);
begin
reproducer <= to_unsigned(integer(0.0), 10**7);
end arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1008/test.vhdl | 1 | 550 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
port(
addr_in : in std_logic_vector(11 downto 0);
dat_out : out std_logic_vector(63 downto 0)
);
end entity test;
architecture behaviour of test is
type ram_t is array(0 to (4096 / 8) - 1) of std_logic_vector(63 downto 0);
signal memory : ram_t := (others => (others => '0'));
signal idx : natural := 0;
begin
idx <= to_integer(unsigned(addr_in(11 downto 3)));
dat_out <= memory(idx);
end architecture behaviour;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc220.vhd | 4 | 1818 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc220.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p06n03i00220ent IS
type e is (EMIN,ETYP,EMAX);
END c03s01b01x00p06n03i00220ent;
ARCHITECTURE c03s01b01x00p06n03i00220arch OF c03s01b01x00p06n03i00220ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(e'pos(ETYP) < e'pos(EMAX))
report "***PASSED TEST: c03s01b01x00p06n03i00220"
severity NOTE;
assert (e'pos(ETYP) < e'pos(EMAX))
report "***FAILED TEST: c03s01b01x00p06n03i00220 - The position number of the value of each additional enumeration literal is one more than that of its predecessor in the list."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p06n03i00220arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket19/psl_test_cover2.vhd | 2 | 1252 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity psl_test_cover2 is
end entity psl_test_cover2;
architecture test of psl_test_cover2 is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 20 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING PSL_TEST_COVER test case";
report "================================";
s_write <= '0';
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait until rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait;
end process TestP;
-- -psl statements
-- psl default clock is rising_edge(s_clk);
-- cover directive seems not supported (ignored by GHDL)
-- psl cover {s_write ; not(s_read)};
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1765.vhd | 4 | 1711 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1765.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b02x00p02n01i01765ent IS
END c09s05b02x00p02n01i01765ent;
ARCHITECTURE c09s05b02x00p02n01i01765arch OF c09s05b02x00p02n01i01765ent IS
signal TS : integer;
signal B : bit;
BEGIN
with B select
TS <= transport 1 when '0',
transport 2 when '1'; -- Failure_here
-- option not allowed
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s05b02x00p02n01i01765 - Option is not allowed here."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s05b02x00p02n01i01765arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc656.vhd | 4 | 2318 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc656.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:55 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00656ent IS
END c03s04b01x00p01n01i00656ent;
ARCHITECTURE c03s04b01x00p01n01i00656arch OF c03s04b01x00p01n01i00656ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type real_vector is array (natural range <>) of real;
subtype real_vector_range is real_vector(hi_to_low_range);
constant C1 : real_vector_range := (others => 3.0);
type real_vector_range_file is file of real_vector_range;
BEGIN
TESTING: PROCESS
file filein : real_vector_range_file open write_mode is "iofile.05";
BEGIN
for i in 1 to 100 loop
write(filein,C1);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00656 - The output file will be verified by test s010106.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00656arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2212.vhd | 4 | 1836 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2212.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02212ent IS
END c07s02b06x00p01n01i02212ent;
ARCHITECTURE c07s02b06x00p01n01i02212arch OF c07s02b06x00p01n01i02212ent IS
BEGIN
TESTING: PROCESS
-- All different non-numeric type declarations.
-- enumerated types.
type SWITCH_LEVEL is ('0', '1', 'X');
-- Local declarations.
variable SWITCHV : SWITCH_LEVEL := '0';
variable k : integer;
BEGIN
k := SWITCHV rem '1';
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02212 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02212arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/synth27/dff.vhdl | 1 | 787 | library ieee;
use ieee.std_logic_1164.all;
entity dff is
generic(
formal_g : boolean := true
);
port(
reset : in std_logic;
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end entity dff;
architecture rtl of dff is
signal q_int : std_logic;
begin
dff_proc : process(clk, reset)
begin
if reset = '1' then
q_int <= '0';
elsif rising_edge(clk) then
q_int <= d;
end if;
end process dff_proc;
-- drive q_int to output port
q <= q_int;
formal_gen : if formal_g = true generate
begin
-- set all declarations to run on clk
default clock is rising_edge(clk);
d_in_check : assert always {d} |=> {q_int};
not_d_in_check : assert always {not d} |=> {not q_int};
end generate formal_gen;
end rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2182.vhd | 4 | 1792 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2182.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n02i02182ent IS
END c07s02b05x00p01n02i02182ent;
ARCHITECTURE c07s02b05x00p01n02i02182arch OF c07s02b05x00p01n02i02182ent IS
BEGIN
TESTING: PROCESS
variable k : real := 0.0;
variable m : real := 5.5;
BEGIN
k := - m;
assert NOT( k = - 5.5 )
report "***PASSED TEST: c07s02b05x00p01n02i02182"
severity NOTE;
assert ( k = - 5.5 )
report "***FAILED TEST: c07s02b05x00p01n02i02182 - For each of these unary operators, the operand and the result have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n02i02182arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2624.vhd | 4 | 1680 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2624.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02624ent IS
END c13s03b01x00p02n01i02624ent;
ARCHITECTURE c13s03b01x00p02n01i02624arch OF c13s03b01x00p02n01i02624ent IS
BEGIN
TESTING: PROCESS
variable k{k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02624 - Identifier can not contain '{'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02624arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1745.vhd | 4 | 1870 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1745.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p05n03i01745ent IS
END c09s05b00x00p05n03i01745ent;
ARCHITECTURE c09s05b00x00p05n03i01745arch OF c09s05b00x00p05n03i01745ent IS
signal A : bit := '0';
BEGIN
A <= transport '1' after 10 ns;
TESTING: PROCESS(A)
variable NEWTIME : TIME;
BEGIN
NEWTIME := now;
if ( now > 1 ns ) then
assert NOT( A= '1' and NEWTIME = 10 ns )
report "***PASSED TEST: c09s05b00x00p05n03i01745"
severity NOTE;
assert ( A= '1' and NEWTIME = 10 ns )
report "***FAILED TEST: c09s05b00x00p05n03i01745 - Transport specifies the transport delay."
severity ERROR;
end if;
END PROCESS TESTING;
END c09s05b00x00p05n03i01745arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue818/tc15.vhdl | 1 | 271 | entity tc15 is
end;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tc15 is
signal clk : std_logic;
signal tg : std_logic;
begin
process (clk) is
begin
if ?? (tg) and falling_edge(clk) then
null;
end if;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generators/led_bar_display.vhd | 4 | 2236 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- analyze into resource library device_lib
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity resistor is
port ( terminal p1, p2 : electrical );
end entity resistor;
architecture ideal of resistor is
begin
end architecture ideal;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity led is
port ( terminal anode, cathode : electrical );
end entity led;
architecture ideal of led is
begin
end architecture ideal;
-- code from book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity led_bar_display is
generic ( width : positive );
port ( terminal anodes : electrical_vector(1 to width);
terminal common_cathode : electrical );
end entity led_bar_display;
----------------------------------------------------------------
architecture device_level of led_bar_display is
component resistor is
port ( terminal p1, p2 : electrical );
end component resistor;
component led is
port ( terminal anode, cathode : electrical );
end component led;
begin
device_array : for segment in 1 to width generate
terminal led_anode : electrical;
begin
limiting_resistor : component resistor
port map ( p1 => anodes(segment), p2 => led_anode );
segment_led : component led
port map ( anode => led_anode, cathode => common_cathode );
end generate device_array;
end architecture device_level;
-- end code from book
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_12.vhd | 4 | 2452 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_12.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_12 is
end entity ch_05_12;
----------------------------------------------------------------
architecture test of ch_05_12 is
signal top_a, bottom_a : bit := '0';
signal top_y, bottom_y : bit;
begin
block_05_3_m : block is
port ( a : in bit; y : out bit := '1' );
port map ( a => top_a, y => top_y );
begin
-- code from book:
inv : process (a) is
begin
y <= inertial not a after 3 ns;
end process inv;
-- end of code from book
end block block_05_3_m;
----------------
block_05_3_n : block is
port ( a : in bit; y : out bit := '1' );
port map ( a => bottom_a, y => bottom_y);
begin
-- code from book:
inv : process (a) is
begin
y <= reject 2 ns inertial not a after 3 ns;
end process inv;
-- end of code from book
end block block_05_3_n;
----------------
stimulus_05_3_m_n : process is
begin
top_a <= '1' after 1 ns,
'0' after 6 ns,
'1' after 8 ns;
bottom_a <= '1' after 1 ns,
'0' after 6 ns,
'1' after 9 ns,
'0' after 11.5 ns,
'1' after 16 ns,
'0' after 18 ns,
'1' after 19 ns,
'0' after 20 ns;
wait;
end process stimulus_05_3_m_n;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_08.vhd | 4 | 3196 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_08.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
package bit_vector_signed_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
function "-" ( bv : bit_vector ) return bit_vector;
function "*" ( bv1, bv2 : bit_vector ) return bit_vector;
-- . . .
end package bit_vector_signed_arithmetic;
-- not in book
library bv_utilities;
use bv_utilities.bv_arithmetic;
-- end not in book
package body bit_vector_signed_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . .
-- not in book
begin
return bv_arithmetic."+"(bv1, bv2);
end function "+";
-- end not in book
function "-" ( bv : bit_vector ) return bit_vector is -- . . .
-- not in book
begin
return bv_arithmetic."-"(bv);
end function "-";
-- end not in book
function mult_unsigned ( bv1, bv2 : bit_vector ) return bit_vector is
-- . . .
begin
-- not in book
-- . . .
return bv_arithmetic.bv_multu(bv1, bv2);
-- end not in book
end function mult_unsigned;
function "*" ( bv1, bv2 : bit_vector ) return bit_vector is
begin
if bv1(bv1'left) = '0' and bv2(bv2'left) = '0' then
return mult_unsigned(bv1, bv2);
elsif bv1(bv1'left) = '0' and bv2(bv2'left) = '1' then
return -mult_unsigned(bv1, -bv2);
elsif bv1(bv1'left) = '1' and bv2(bv2'left) = '0' then
return -mult_unsigned(-bv1, bv2);
else
return mult_unsigned(-bv1, -bv2);
end if;
end function "*";
-- . . .
end package body bit_vector_signed_arithmetic;
-- not in book
entity fg_08_08 is
end entity fg_08_08;
library bv_utilities;
use bv_utilities.bit_vector_signed_arithmetic.all;
use std.textio.all;
architecture test of fg_08_08 is
begin
stimulus : process is
variable L : line;
begin
write(L, X"0002" + X"0005");
writeline(output, L);
write(L, X"0002" + X"FFFE");
writeline(output, L);
write(L, - X"0005");
writeline(output, L);
write(L, - X"FFFE");
writeline(output, L);
write(L, X"0002" * X"0005");
writeline(output, L);
write(L, X"0002" * X"FFFD");
writeline(output, L);
wait;
end process stimulus;
end architecture test;
-- end not in book
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc689.vhd | 4 | 2116 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc689.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:03 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00689ent IS
END c03s04b01x00p23n01i00689ent;
ARCHITECTURE c03s04b01x00p23n01i00689arch OF c03s04b01x00p23n01i00689ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of BIT;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.08";
-- Declare a variable.
constant CON : BIT := '1';
variable VAR : BIT := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00689 - The output file will tested by test file s010424.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00689arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue690/source.vhdl | 1 | 1528 | library ieee;
use ieee.std_logic_1164.all;
entity source is
generic(
type data_type;
procedure read(l: inout std.textio.line; value: out data_type; good: out boolean);
stm_file: string
);
port(
clk: in std_logic;
resetn: in std_logic;
data: out data_type;
valid: out std_logic;
ready: in std_logic;
valid_i: in std_logic := '1'
);
end entity source;
architecture behav of source is
file stimuli: std.textio.text open read_mode is stm_file;
type packet_t is record
data: data_type;
valid: std_logic;
end record;
impure function next_packet(file stimuli: std.textio.text) return packet_t is
variable stimuli_line: std.textio.line;
variable packet: packet_t;
variable good: boolean := false;
begin
while not std.textio.endfile(stimuli) and not good loop
std.textio.readline(stimuli, stimuli_line);
read(stimuli_line, packet.data, good);
end loop;
packet.valid := '1' when good else '0';
return packet;
end function;
signal packet: packet_t;
signal init: std_logic;
begin
process(clk) is
begin
if rising_edge(clk) then
if resetn = '0' then
packet.valid <= '0';
init <= '0';
else
if init = '0' or (packet.valid = '1' and valid_i = '1' and ready = '1') then
packet <= next_packet(stimuli);
init <= '1';
end if;
end if;
end if;
end process;
data <= packet.data;
valid <= packet.valid and valid_i;
end architecture behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/generics/entity-generic-defines-port-type.vhdl | 3 | 1012 | entity test_bench is
end test_bench;
entity generic_defines_port_type is
generic( width : natural );
port( input : in bit_vector( width - 1 downto 0 );
finished : in boolean );
end entity;
architecture only of generic_defines_port_type is
begin -- only
p: process( finished )
begin -- process p
if finished = true then
for i in input'range loop
assert input(i) = '1' report "TEST FAILED" severity FAILURE;
end loop; -- i
end if;
end process p;
end only;
architecture only of test_bench is
signal gdpt1_input : bit_vector( 3 downto 0 ) := "0000";
signal gdpt1_finished : boolean := false;
begin -- only
gdpt1: entity work.generic_defines_port_type
generic map ( width => 4 )
port map ( input => gdpt1_input, finished => gdpt1_finished );
doit: process
begin -- process doit
gdpt1_input <= "1111";
wait for 1 fs;
gdpt1_finished <= true;
wait for 1 fs;
report "TEST PASSED";
wait;
end process doit;
end only;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-frk.vhd | 4 | 3247 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tb-frk.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use std.textio.all;
architecture fork of test_bench is
use qsim.qsim_types.all;
use random.random.all;
constant num_outputs : positive := 4;
constant probabilities : probability_vector(1 to num_outputs - 1)
:= ( 0.2, 0.4, 0.1 );
signal source_arc : arc_type;
signal fork_arc : arc_vector(1 to num_outputs);
signal info_detail : info_detail_type := trace;
begin
source1 : entity qsim.source(behavior)
generic map ( name => "source1",
distribution => fixed, mean_inter_arrival_time => 100 ns,
seed => sample_seeds(1),
time_unit => ns,
info_file_name => "source1.dat" )
port map ( out_arc => source_arc,
info_detail => info_detail );
fork1 : entity qsim.fork(behavior)
generic map ( name => "fork1",
probabilities => probabilities,
seed => sample_seeds(2),
time_unit => ns,
info_file_name => "fork1.dat" )
port map ( in_arc => source_arc,
out_arc => fork_arc,
info_detail => info_detail );
source_monitor : process is
variable L : line;
begin
wait on source_arc;
write(L, string'("source_monitor: at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, source_arc.token, ns);
writeline(output, L);
end process source_monitor;
sinks : for index in 1 to num_outputs generate
constant index_string : string := integer'image(index);
begin
sink : entity qsim.sink(behavior)
generic map ( name => "sink" & index_string,
time_unit => ns,
info_file_name => "sink" & index_string & ".dat" )
port map ( in_arc => fork_arc(index),
info_detail => info_detail );
sink_monitor : process
variable L : line;
begin
wait on fork_arc(index);
write(L, string'("sink_monitor(" & index_string & "): at "));
write(L, now, unit => ns);
write(L, string'(", "));
write(L, fork_arc(index).token, ns);
writeline(output, L);
end process sink_monitor;
end generate sinks;
end architecture fork;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/func01/tb_func03.vhdl | 1 | 419 | entity tb_func03 is
end tb_func03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func03 is
signal a, b : std_logic_vector(7 downto 0);
begin
dut: entity work.func03
port map (a, b);
process
begin
a <= x"ff";
wait for 1 ns;
assert b = x"01" severity failure;
a <= x"ee";
wait for 1 ns;
assert b = x"00" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue578/generics.vhdl | 1 | 14333 | library ieee;
use ieee.std_logic_1164.all;
--use ieee.math_real.all;
use ieee.numeric_std.all;
package generics is
constant synthesis : boolean := true
-- synthesis translate_off
and false
-- synthesis translate_on
;
function sim_cond(cond : boolean) return boolean;
function istr(v : integer) return string;
function as_std_logic(v : boolean) return std_logic;
function rot_l(v : std_logic_vector; n : integer := 1) return std_logic_vector;
function rot_r(v : std_logic_vector; n : integer := 1) return std_logic_vector;
function sh_l(v : std_logic_vector; n : integer := 1) return std_logic_vector;
function sh_r(v : std_logic_vector; n : integer := 1) return std_logic_vector;
function log2_int(v : integer) return integer;
function log2(v : integer) return integer;
function is_log2(v : integer) return boolean;
function binary_flatten(v : std_logic_vector; n : integer) return std_logic_vector;
function min(a : integer; b : integer) return integer;
function max(a : integer; b : integer) return integer;
function find_first_bit(v : std_logic_vector) return integer;
function mask_first_bit(v : std_logic_vector) return std_logic_vector;
function next_multiple(v : integer; m : integer) return integer;
function reverse_vector(inp : std_logic_vector) return std_logic_vector;
function reorder_vector(inp : std_logic_vector) return std_logic_vector;
function htonl(inp : std_logic_vector) return std_logic_vector;
function ntohl(inp : std_logic_vector) return std_logic_vector;
function vector_all_valid(i : std_logic_vector) return boolean;
function to_integer(i : std_logic) return integer;
function integer_reverse_bits(i : integer; bits : integer) return integer;
function dbg_collapse16(d : in std_logic_vector) return std_logic_vector;
function bram_we_width(aw : integer) return integer;
function chr(sl: std_logic) return character;
function chr(i : integer) return character;
function chr(b : boolean) return character;
function vector_to_string(v : std_logic_vector) return string;
function vector_to_hex_string(v : std_logic_vector) return string;
function to_std_logic_vector(v : integer; size : integer) return std_logic_vector;
function popcnt(v : std_logic_vector) return integer;
function popcnt(v : integer; bits : integer) return integer;
function popcnt_x(v : std_logic_vector) return integer;
function maxlen_lfsr_advance(reg : std_logic_vector) return std_logic_vector;
function random_vector(len : integer; seed : integer) return std_logic_vector;
function random(max : integer; seed : integer) return integer;
function reverse_any_vector(a : in std_logic_vector) return std_logic_vector;
function sel(cond : boolean; if_true : integer; if_false : integer) return integer;
function sel(cond : boolean; if_true : std_logic_vector; if_false : std_logic_vector) return std_logic_vector;
function sel(cond : boolean; if_true : std_logic; if_false : std_logic) return std_logic;
function sel(cond : boolean; if_true : string; if_false : string) return string;
procedure clkp(signal clk : in std_logic; n : in integer);
function vector_mux(sel : std_logic_vector; i1 : std_logic_vector; i2 : std_logic_vector) return std_logic_vector;
function div_ceil(a : integer; b : integer) return integer;
function int_strlen(vv : integer) return natural;
end generics;
package body generics is
function chr(b : boolean) return character is
begin
if b then
return 't';
end if;
return 'f';
end function;
function chr(i : integer) return character is
variable s : string(1 to 10) := "0123456789";
begin
if i < 10 then
return s(i + 1);
else
return 'X';
end if;
end function;
function istr(v : integer) return string is
begin
return integer'image(v);
end function;
function as_std_logic(v : boolean) return std_logic is
begin
if v then return '1'; end if;
return '0';
end function;
function int_strlen(vv : integer) return natural is
variable ret : natural := 0;
variable v : integer := vv;
begin
if v < 0 then
ret := ret + 1;
v := -v;
end if;
while v >= 10 loop
v := v / 10;
ret := ret + 1;
end loop;
return ret + 1;
end function;
function rot_l(v : std_logic_vector; n : integer := 1) return std_logic_vector is
begin
return std_logic_vector(rotate_left(unsigned(v), n));
end function;
function rot_r(v : std_logic_vector; n : integer := 1) return std_logic_vector is
begin
return std_logic_vector(rotate_right(unsigned(v), n));
end function;
function sh_l(v : std_logic_vector; n : integer := 1) return std_logic_vector is
begin
return std_logic_vector(shift_left(unsigned(v), n));
end function;
function sh_r(v : std_logic_vector; n : integer := 1) return std_logic_vector is
begin
return std_logic_vector(shift_right(unsigned(v), n));
end function;
function log2(v : integer) return integer is
begin
return log2_int(v);
end function;
function is_log2(v : integer) return boolean is
begin
return 2 ** log2(v) = v;
end function;
function to_integer(i : std_logic) return integer is
begin
if i = '1' then
return 1;
elsif i = '0' then
return 0;
else
return -1;
end if;
end function;
function dbg_collapse16(d : in std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(0 to 15);
variable oi : integer;
begin
oi := 0;
ret := (others => '0');
for i in d'range loop
ret(oi) := ret(oi) xor d(i);
if oi < 15 then
oi := oi + 1;
else
oi := 0;
end if;
end loop;
return ret;
end function;
function random(max : integer; seed : integer) return integer is
begin
if max = 0 then return 0; end if;
return to_integer(unsigned(random_vector(log2_int(max) + 1, seed))) mod max;
end function;
function sel(cond : boolean; if_true : std_logic; if_false : std_logic) return std_logic is
begin
if cond then
return if_true;
end if;
return if_false;
end function;
function sel(cond : boolean; if_true : string; if_false : string) return string is
begin
if cond then
return if_true;
else
return if_false;
end if;
end function;
function div_ceil(a : integer; b : integer) return integer is
begin
return a / b + sel(a mod b /= 0, 1, 0);
end function;
function sim_cond(cond : boolean) return boolean is
begin
if synthesis then
return true;
else
return cond;
end if;
end function;
function integer_reverse_bits(i : integer; bits : integer) return integer is
variable m : std_logic_vector(0 to bits - 1);
begin
m := std_logic_vector(to_unsigned(i, bits));
m := reverse_any_vector(m);
return to_integer(unsigned(m));
end function;
function vector_mux(sel : std_logic_vector; i1 : std_logic_vector; i2 : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(0 to sel'length - 1);
begin
for i in 0 to sel'length - 1 loop
if sel(sel'left + i) = '1' then
ret(i) := i1(i1'left + i);
else
ret(i) := i2(i2'left + i);
end if;
end loop;
return ret;
end function;
procedure clkp(signal clk : in std_logic; n : in integer) is
begin
for i in 1 to n loop
wait until rising_edge(clk);
end loop;
wait for 1 ps;
end procedure;
function random_vector(len : integer; seed : integer) return std_logic_vector is
variable lfsr : std_logic_vector(0 to 7) := std_logic_vector(to_unsigned(seed, 8));
variable ret : std_logic_vector(0 to len - 1);
begin
for i in 0 to len / 8 loop
lfsr := maxlen_lfsr_advance(lfsr);
lfsr := maxlen_lfsr_advance(lfsr);
lfsr := maxlen_lfsr_advance(lfsr);
lfsr := maxlen_lfsr_advance(lfsr);
ret(i * 8 to min(ret'length, (i + 1) * 8) - 1) := lfsr(0 to min(8, ret'length - i * 8) - 1);
end loop;
return ret;
end function;
function sel(cond : boolean; if_true : integer; if_false : integer) return integer is
begin
if cond then return if_true; else return if_false; end if;
end function;
function sel(cond : boolean; if_true : std_logic_vector; if_false : std_logic_vector) return std_logic_vector is
begin
if cond then return if_true; else return if_false; end if;
end function;
function popcnt(v : integer; bits : integer) return integer is
begin
return popcnt(std_logic_vector(to_unsigned(v, bits)));
end function;
function reverse_any_vector (a: in std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(a'range);
alias aa: std_logic_vector(a'reverse_range) is a;
begin
for i in aa'range loop
result(i) := aa(i);
end loop;
return result;
end;
function maxlen_lfsr_advance(reg : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(reg'range);
begin
if ret'left > ret'right then
ret(reg'left downto 1) := reg(reg'left - 1 downto 0);
else
ret(1 to reg'right) := reg(0 to reg'right - 1);
end if;
if reg'length = 3 then
ret(0) := reg(2) xnor reg(1);
elsif reg'length = 4 then
ret(0) := reg(3) xnor reg(2);
elsif reg'length = 8 then
ret(0) := reg(7) xnor reg(5) xnor reg(4) xnor reg(3);
elsif reg'length = 57 then
ret(0) := reg(56) xnor reg(49);
else
assert false report "no matching shift register configured for length " & integer'image(reg'length) severity failure;
end if;
return ret;
end function;
function vector_all_valid(i : std_logic_vector) return boolean is
begin
for j in i'range loop
if i(j) /= '1' and i(j) /= '0' then
return false;
end if;
end loop;
return true;
end function;
function popcnt_x(v : std_logic_vector) return integer is
variable ret : integer;
begin
ret := 0;
for i in v'range loop
if v(i) = 'X' then
ret := ret + 1;
end if;
end loop;
return ret;
end function;
function popcnt(v : std_logic_vector) return integer is
variable res : integer;
begin
res := 0;
for i in v'range loop
if v(i) = '1' then
res := res + 1;
end if;
end loop;
return res;
end function;
function to_std_logic_vector(v : integer; size : integer) return std_logic_vector is
variable ret : std_logic_vector(size - 1 downto 0);
variable tmp : unsigned(size - 1 downto 0);
begin
tmp := to_unsigned(v, size);
return std_logic_vector(tmp);
end function;
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
function vector_to_hex_string(v : std_logic_vector) return string is
variable ret : string(1 to (v'length + 3) / 4);
type hchar_t is array(0 to 15) of character;
constant hchar : hchar_t := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'a', 'b', 'c', 'd', 'e', 'f');
variable off : integer := v'length mod 4;
begin
if off /= 0 then
ret(1) := hchar(to_integer(unsigned(v(0 to off - 1))));
end if;
for i in 0 to v'length / 4 - 1 loop
ret(i + sel(off = 0, 1, 2)) := hchar(to_integer(unsigned(v(off + i * 4 to off + i * 4 + 3))));
end loop;
return ret;
end function;
function vector_to_string(v : std_logic_vector) return string is
variable ret : string(1 to v'length);
variable at : integer;
begin
at := 1;
for i in v'range loop
ret(at) := chr(v(i));
at := at + 1;
end loop;
return ret;
-- for i in 0 to v'length - 1 loop
-- ret(i + 1) := chr(v(i));
-- end loop;
-- return ret;
end function;
function bram_we_width(aw : integer) return integer is
begin
if aw > 16 then
return 4;
elsif aw > 8 then
return 2;
else
return 1;
end if;
end function;
function htonl(inp : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(inp'range);
begin
ret(31 downto 24) := inp(7 downto 0);
ret(23 downto 16) := inp(15 downto 8);
ret(15 downto 8) := inp(23 downto 16);
ret(7 downto 0) := inp(31 downto 24);
return ret;
end function;
function ntohl(inp : std_logic_vector) return std_logic_vector is
begin
return htonl(inp);
end function;
function reorder_vector(inp : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(inp'reverse_range);
begin
return inp;
if inp'left < inp'right then
for i in inp'range loop
ret(inp'right - i) := inp(i);
end loop;
elsif inp'left > inp'right then
for i in inp'range loop
ret(inp'left - i) := inp(i);
end loop;
else
ret(inp'left) := inp(inp'left);
end if;
return ret;
end function;
function reverse_vector(inp : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(inp'reverse_range);
begin
for i in inp'range loop
ret(i) := inp(i);
end loop;
return ret;
end function;
function next_multiple(v : integer; m : integer) return integer is
begin
if v mod m = 0 then
return v;
else
return v + m - v mod m;
end if;
end function;
function mask_first_bit(v : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(v'range) := (others => '0');
begin
for i in 0 to v'length - 1 loop
if v(i) = '1' then
ret(i) := '1';
return ret;
end if;
end loop;
return ret;
end function;
function find_first_bit(v : std_logic_vector) return integer is
begin
for i in 0 to v'length - 1 loop
if v(i) = '1' then return i; end if;
end loop;
return 0;
end function;
function min(a : integer; b : integer) return integer is
begin
if a < b then
return a;
end if;
return b;
end function;
function max(a : integer; b : integer) return integer is
begin
if a > b then
return a;
end if;
return b;
end function;
function binary_flatten(v : std_logic_vector; n : integer) return std_logic_vector is
variable res : std_logic_vector(n - 1 downto 0) := (others => '0');
begin
for i in 0 to n - 1 loop
if unsigned(v) = to_unsigned(i, v'length) then
res(i) := '1';
return res;
end if;
end loop;
return res;
end function;
function log2_int(v : integer) return integer is
variable vv, ret : integer;
begin
vv := v;
ret := 0;
while vv > 1 loop
ret := ret + 1;
vv := vv / 2;
end loop;
if 2 ** ret = v then
return ret;
else
return ret + 1;
end if;
--return integer(ceil(log2(real(v))));
end function;
end generics;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/sns01/tb_add03.vhdl | 1 | 625 | entity tb_add03 is
end tb_add03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_add03 is
signal a, b : std_logic_vector(8 DOWNTO 0);
signal borrow : std_logic;
signal res : std_logic_vector(8 DOWNTO 0);
begin
dut: entity work.add03
port map (a, b, borrow, res);
process
begin
a <= b"00000_0100";
b <= b"00000_0001";
borrow <= '0';
wait for 1 ns;
assert res = b"00000_0011" severity failure;
a <= b"00000_0010";
b <= b"00000_0001";
borrow <= '1';
wait for 1 ns;
assert res = b"00000_0000" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_dc_xhuff_tbl_bits.vhd | 2 | 1451 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_dc_xhuff_tbl_bits is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_dc_xhuff_tbl_bits;
architecture augh of p_jinfo_dc_xhuff_tbl_bits is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc698.vhd | 4 | 2134 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc698.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:06 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00698ent IS
END c03s04b01x00p23n01i00698ent;
ARCHITECTURE c03s04b01x00p23n01i00698arch OF c03s04b01x00p23n01i00698ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of CHARACTER;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.08";
-- Declare a variable.
constant CON : CHARACTER := '1';
variable VAR : CHARACTER := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00698 - The output file will tested by test file s010430.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00698arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/brake_system.vhd | 4 | 1448 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
use work.automotive_valve_defs.all;
entity brake_system is
end entity brake_system;
-- end not in book
architecture structure of brake_system is
use work.automotive_valve_defs.all;
-- ... -- declarations of other components, terminals, etc
-- not in book
terminal master_reservoir, brake_line : valve_fluidic;
terminal brake_pedal : valve_translational;
-- end not in book
begin
pedal_valve : component automotive_valve
port map ( p1 => master_reservoir,
p2 => brake_line,
control => brake_pedal );
-- ... -- other component instances
end architecture structure;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-with-port-map.vhdl | 4 | 864 | entity forty_two is
port (
int_out : out integer);
end forty_two;
architecture only of forty_two is
begin -- only
process
begin -- process
int_out <= 42;
wait;
end process;
end only;
entity test_bench is
end test_bench;
architecture only of test_bench is
component forty_two_component
port (
c_int_out : out integer);
end component;
for ft0 : forty_two_component
use entity work.forty_two(only)
port map (
int_out => c_int_out);
signal int_signal : integer;
begin -- only
ft0 : component forty_two_component
port map (
c_int_out => int_signal );
test: process
begin -- process test
wait for 1 ms;
assert int_signal = 42 report "TEST FAILED" severity ERROR;
assert not(int_signal = 42) report "TEST PASSED" severity NOTE;
wait;
end process test;
end only;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_09.vhd | 4 | 1702 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_ap_a_09.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ap_a_09 is
end entity ap_a_09;
library ieee; use ieee.std_logic_1164.all;
architecture test of ap_a_09 is
signal a, b, c, d : integer := 0;
begin
b1 : block is
signal y : integer;
begin
-- code from book
y <= a + b + c + d;
-- end code from book
end block b1;
b2 : block is
signal y : integer;
begin
-- code from book
y <= ( a + b ) + ( c + d );
-- end code from book
end block b2;
stimulus : process is
begin
a <= 1; wait for 10 ns;
b <= 2; wait for 10 ns;
c <= 3; wait for 10 ns;
d <= 4; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue731/tbadder.vhdl | 1 | 529 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.env.all;
entity tbAdder is
end entity tbAdder;
architecture Bhv of tbAdder is
constant cWidth : natural := 8;
signal iA, iB : std_ulogic_vector(cWidth-1 downto 0) := (others => '0');
signal oRes : std_ulogic_vector(cWidth-1 downto 0);
signal oCarry : std_ulogic;
begin
UUT: entity work.Adder
generic map(
gWidth => cWidth
)
port map(
iA => iA,
iB => iB,
oCarry => oCarry,
oRes => oRes
);
end architecture Bhv;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/var01/tb_var05.vhdl | 1 | 847 | entity tb_var05 is
end tb_var05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var05 is
signal clk : std_logic;
signal sel : std_logic;
signal a, b : std_logic_vector (1 downto 0);
signal res : std_logic_vector (1 downto 0);
begin
dut: entity work.var05
port map (
sel => sel,
a => a,
b => b,
res => res);
process
begin
sel <= '1';
a <= "00";
b <= "11";
wait for 1 ns;
assert res = "11" severity failure;
sel <= '0';
a <= "00";
b <= "11";
wait for 1 ns;
assert res = "00" severity failure;
sel <= '0';
a <= "10";
b <= "01";
wait for 1 ns;
assert res = "10" severity failure;
sel <= '1';
a <= "10";
b <= "01";
wait for 1 ns;
assert res = "01" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2536.vhd | 4 | 1896 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2536.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p13n03i02536ent IS
END c07s03b05x00p13n03i02536ent;
ARCHITECTURE c07s03b05x00p13n03i02536arch OF c07s03b05x00p13n03i02536ent IS
type Memory is array (Integer range <>) of Integer;
subtype T1 is Memory (1 to 6) ;
subtype T2 is Memory (1 to 6) ;
subtype T3 is Memory (2 to 4) ;
BEGIN
TESTING: PROCESS
variable V1 : T1 ;
variable V2 : T3 := (2,3,6) ;
BEGIN
V1 := T2 (V2) ; -- Failure_here
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p13n03i02536 - A check is made that for each element of the operand there is a matching element of the target subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p13n03i02536arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2134.vhd | 4 | 2282 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2134.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02134ent IS
END c07s02b04x00p21n01i02134ent;
ARCHITECTURE c07s02b04x00p21n01i02134arch OF c07s02b04x00p21n01i02134ent IS
TYPE simple_record is record
data_1 : integer;
data_2 : integer;
end record;
TYPE record_v is array (integer range <>) of simple_record;
SUBTYPE record_null is record_v (1 to 0);
SUBTYPE record_1 is record_v (1 to 1);
BEGIN
TESTING: PROCESS
variable result : record_1;
variable l_operand : simple_record := (12,34) ;
variable r_operand : record_null;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result(1) = (12,34) )
report "***PASSED TEST: c07s02b04x00p21n01i02134"
severity NOTE;
assert ( result(1) = (12,34) )
report "***FAILED TEST: c07s02b04x00p21n01i02134 - Concatenation of null and RECORD element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02134arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2092.vhd | 4 | 2650 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2092.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02092ent IS
END c07s02b04x00p20n01i02092ent;
ARCHITECTURE c07s02b04x00p20n01i02092arch OF c07s02b04x00p20n01i02092ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4_up is boolean_v (1 to 4);
SUBTYPE boolean_8_up is boolean_v (1 to 8);
SUBTYPE boolean_4_dwn is boolean_v (4 downto 1);
BEGIN
TESTING: PROCESS
variable l_operand : boolean_4_up := (true, true, false, false);
variable r_operand : boolean_4_dwn:= (false, false, true, true);
variable result : boolean_8_up;
BEGIN
result := l_operand & r_operand;
assert ( result (1) = true )
report "result (1) /= true" severity FAILURE;
assert ( result (4) = false )
report "result (4) /= false" severity FAILURE;
assert ( result (5) = false )
report "result (5) /= false" severity FAILURE;
assert ( result (8) = true )
report "result (8) /= true" severity FAILURE;
assert NOT((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
report "***PASSED TEST: c07s02b04x00p20n01i02092"
severity NOTE;
assert ((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
report "***FAILED TEST: c07s02b04x00p20n01i02092 - Concatenated array should be ascending and the left bound is that of the first operand."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02092arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1212.vhd | 4 | 1784 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1212.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p25n02i01212ent IS
END c08s01b00x00p25n02i01212ent;
ARCHITECTURE c08s01b00x00p25n02i01212arch OF c08s01b00x00p25n02i01212ent IS
signal I : bit := '0';
BEGIN
TESTING: PROCESS
BEGIN
I <= '1' after 10 ns;
wait on I;
assert NOT( I = '1' )
report "***PASSED TEST: c08s01b00x00p25n02i01212"
severity NOTE;
assert ( I = '1' )
report "***FAILED TEST: c08s01b00x00p25n02i01212 - The condition clause assumes the default value TRUE when no condition clause is present."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p25n02i01212arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/string01/tb_string01.vhdl | 1 | 309 | entity tb_string01 is
end tb_string01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_string01 is
signal a : std_logic;
begin
dut: entity work.string01
port map (a);
process
begin
wait for 1 ns;
assert a = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3081.vhd | 4 | 4064 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3081.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b02x00p05n01i03081ent IS
END c12s06b02x00p05n01i03081ent;
ARCHITECTURE c12s06b02x00p05n01i03081arch OF c12s06b02x00p05n01i03081ent IS
-- Define the resolution function we'll be using.
function WIRED_OR( Inputs: BIT_VECTOR) return BIT is
constant FLoatValue :BIT := '0';
begin
for I in Inputs'Range loop
if Inputs(I) = '1' then
return '1';
end if;
end loop;
return '0';
end;
-- Define the subtype that has this resolution function.
subtype RBIT is WIRED_OR BIT;
-- This signal will have its 'ACTIVE flag monitored.
signal MONITOR : RBIT := '0';
-- This signal will be used to check MONITOR'ACTIVE whenever
-- we want to verify that is value is OK.
signal CHECK : RBIT := '0';
BEGIN
TESTING: PROCESS
variable testOK : integer := 0;
BEGIN
-- Perform a signal value change on both signals.
MONITOR <= not MONITOR after 10 ns;
CHECK <= not CHECK after 10 ns;
wait on CHECK;
-- Verify that the flags say what we want.
assert( not( MONITOR'STABLE ) );
if (MONITOR'STABLE) then
testOK := 1;
end if;
assert( MONITOR'EVENT );
if (not(MONITOR'EVENT)) then
testOK := 1;
end if;
assert( MONITOR'ACTIVE );
if (not(MONITOR'ACTIVE)) then
testOK := 1;
end if;
assert( not( MONITOR'QUIET ) );
if (MONITOR'QUIET) then
testOK := 1;
end if;
-- Perform no signal value change on MONITOR.
MONITOR <= MONITOR after 10 ns;
CHECK <= not CHECK after 10 ns;
wait on CHECK;
-- Verify that the flags say what we want.
assert( MONITOR'STABLE );
if (not(MONITOR'STABLE)) then
testOK := 1;
end if;
assert( not( MONITOR'EVENT ) );
if (MONITOR'EVENT) then
testOK := 1;
end if;
assert( MONITOR'ACTIVE );
if (not(MONITOR'ACTIVE)) then
testOK := 1;
end if;
assert( not( MONITOR'QUIET ) );
if (MONITOR'QUIET) then
testOK := 1;
end if;
-- Perform no activity at all on MONITOR.
CHECK <= not CHECK after 10 ns;
wait on CHECK;
-- Verify that the flags say what we want.
assert( MONITOR'STABLE );
if (not(MONITOR'STABLE)) then
testOK := 1;
end if;
assert( not( MONITOR'EVENT ) );
if (MONITOR'EVENT) then
testOK := 1;
end if;
assert( not( MONITOR'ACTIVE ) );
if (MONITOR'ACTIVE) then
testOK := 1;
end if;
assert( MONITOR'QUIET );
if (not(MONITOR'QUIET)) then
testOK := 1;
end if;
assert NOT( testOK = 0 )
report "***PASSED TEST: c12s06b02x00p05n01i03081"
severity NOTE;
assert ( testOK = 0 )
report "***FAILED TEST: c12s06b02x00p05n01i03081 - A signal should be active if one of its sources is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p05n01i03081arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1282/issue.vhdl | 1 | 269 | library ieee;
use ieee.std_logic_1164.all;
entity issue is
port (foo : in std_logic_vector (3 downto 0);
bar : out std_logic_vector (7 downto 0));
end issue;
architecture beh of issue is
begin
bar <= ('0' & foo, others=>'0');
end architecture beh;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_quad_opamp.vhd | 4 | 4254 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_quad_opamp is
end tb_quad_opamp ;
architecture TB_quad_opamp of tb_quad_opamp is
-- Component declarations
-- Signal declarations
terminal amp_out : electrical_vector(1 to 4);
terminal inm : electrical_vector(1 to 4);
terminal inp : electrical_vector(1 to 4);
begin
-- Signal assignments
-- Component instances
opamp_quad_slew1 : entity work.quad_opamp_wa(slew_limited)
port map(
n1 => inp,
n2 => inm,
output => amp_out
);
R4 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ELECTRICAL_REF,
p2 => amp_out(4)
);
v4 : entity work.v_pulse(ideal)
generic map(
period => 200 us,
width => 100 us,
delay => 10 us,
tp2i => 0.9 us,
ti2p => 0.70 us,
pulse => 5.0
)
port map(
pos => inm(1),
neg => ELECTRICAL_REF
);
R5 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ELECTRICAL_REF,
p2 => amp_out(3)
);
R6 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ELECTRICAL_REF,
p2 => amp_out(2)
);
R7 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ELECTRICAL_REF,
p2 => amp_out(1)
);
v5 : entity work.v_pulse(ideal)
generic map(
pulse => 5.0,
ti2p => 0.70 us,
tp2i => 0.9 us,
delay => 10 us,
width => 100 us,
period => 200 us
)
port map(
pos => inm(2),
neg => ELECTRICAL_REF
);
v6 : entity work.v_pulse(ideal)
generic map(
pulse => 5.0,
ti2p => 0.70 us,
tp2i => 0.9 us,
delay => 10 us,
width => 100 us,
period => 200 us
)
port map(
pos => inm(3),
neg => ELECTRICAL_REF
);
v7 : entity work.v_pulse(ideal)
generic map(
pulse => 5.0,
ti2p => 0.70 us,
tp2i => 0.9 us,
delay => 10 us,
width => 100 us,
period => 200 us
)
port map(
pos => inm(4),
neg => ELECTRICAL_REF
);
R8 : entity work.resistor(ideal)
generic map(
res => 10.0e-3
)
port map(
p1 => ELECTRICAL_REF,
p2 => inp(1)
);
R9 : entity work.resistor(ideal)
generic map(
res => 10.0e-3
)
port map(
p1 => ELECTRICAL_REF,
p2 => inp(2)
);
R10 : entity work.resistor(ideal)
generic map(
res => 10.0e-3
)
port map(
p1 => ELECTRICAL_REF,
p2 => inp(3)
);
R11 : entity work.resistor(ideal)
generic map(
res => 10.0e-3
)
port map(
p1 => ELECTRICAL_REF,
p2 => inp(4)
);
end TB_quad_opamp ;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc224.vhd | 4 | 1806 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc224.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p07n01i00224ent IS
END c03s01b01x00p07n01i00224ent;
ARCHITECTURE c03s01b01x00p07n01i00224arch OF c03s01b01x00p07n01i00224ent IS
type ENUM1 is (FF, GG);
type ENUM2 is (GG, HH);
type ENUM3 is (FALSE);
type ENUM4 is ('A', 'Z');
BEGIN
TESTING: PROCESS
BEGIN
if ('A' = 'Z') then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c03s01b01x00p07n01i00224"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c03s01b01x00p07n01i00224 - Literal cannot be determined."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p07n01i00224arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/mem01/tb_sram02.vhdl | 1 | 976 | entity tb_sram02 is
end tb_sram02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_sram02 is
signal addr : std_logic_vector(3 downto 0);
signal rdat : std_logic_vector(7 downto 0);
signal wdat : std_logic_vector(7 downto 0);
signal wen : std_logic;
signal clk : std_logic;
begin
dut: entity work.sram02
port map (clk_i => clk, addr_i => addr, data_i => wdat, data_o => rdat,
wen_i => wen);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
addr <= "0000";
wdat <= x"02";
wen <= '1';
pulse;
assert rdat = x"02" severity failure;
addr <= "0100";
wdat <= x"03";
wait for 1 ns;
assert rdat = x"02" severity failure;
pulse;
assert rdat = x"03" severity failure;
addr <= "0000";
wen <= '0';
pulse;
assert rdat = x"02" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/packages/simple_package_body_test.vhdl | 4 | 492 | package test_pkg is
function return_one
return integer;
end test_pkg;
package body test_pkg is
function return_one
return integer is
begin -- return_one
return 1;
end return_one;
end test_pkg;
use work.test_pkg.all;
entity test is
end test;
architecture only of test is
begin -- only
p: process
begin -- process p
assert ( return_one = 1 ) report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/fm_radio.vhd | 4 | 1333 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity fm_radio is
end entity fm_radio;
-- end not in book
architecture top_level of fm_radio is
terminal left_decoded, left_filtered : electrical;
terminal right_decoded, right_filtered : electrical;
-- ...
begin
left_pilot_filter : configuration work.notch_filter_down_to_device_level
port map ( input => left_decoded, output => left_filtered,
vdd => vdd, vss => vss, gnd => gnd );
-- ...
end architecture top_level;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2750.vhd | 4 | 1638 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2750.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p03n01i02750ent IS
END c13s07b00x00p03n01i02750ent;
ARCHITECTURE c13s07b00x00p03n01i02750arch OF c13s07b00x00p03n01i02750ent IS
BEGIN
TESTING: PROCESS
variable bit_str : bit_vector (1 to 8) := b"0101__0101";
BEGIN
assert FALSE
report "***FAILED TEST: c13s07b00x00p03n01i02750 - Consecutive underscores are not allowed in bit values."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p03n01i02750arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_04.vhd | 4 | 2356 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_ch_16_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_16_04 is
end entity ch_16_04;
----------------------------------------------------------------
architecture test of ch_16_04 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
-- code from book:
signal memory_data_bus : resolved_word bus;
disconnect memory_data_bus : resolved_word after 3 ns;
-- end of code from book
signal mem_sel, mem_write : boolean;
signal cache_data_bus : word;
begin
-- code from book:
mem_write_buffer : block (mem_sel and mem_write) is
begin
memory_data_bus <=
guarded reject 2 ns inertial cache_data_bus after 4 ns;
end block mem_write_buffer;
-- end of code from book
stimulus : process is
begin
cache_data_bus <= X"DDDDDDDD";
wait for 10 ns;
mem_sel <= true; mem_write <= true;
wait for 10 ns;
cache_data_bus <= X"AAAAAAAA";
wait for 10 ns;
mem_sel <= false; mem_write <= false;
wait for 10 ns;
cache_data_bus <= X"11111111";
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_23.vhd | 3 | 1942 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_23.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book:
entity and_or_inv is
port ( a1, a2, b1, b2 : in bit := '1';
y : out bit );
end entity and_or_inv;
-- end of code from book
architecture functional of and_or_inv is
begin
func : y <= not ((a1 and a2) or (b1 and b2));
end architecture functional;
entity ch_05_23 is
end entity ch_05_23;
library stimulus;
architecture test of ch_05_23 is
signal A, B, C, F : bit;
signal test_input : bit_vector(2 downto 0);
use stimulus.stimulus_generators.all;
begin
-- code from book:
f_cell : entity work.and_or_inv
port map (a1 => A, a2 => B, b1 => C, b2 => open, y => F);
-- end of code from book
stimulus_proc : all_possible_values( bv => test_input,
delay_between_values => 10 ns );
(A, B, C) <= test_input;
verifier :
postponed assert F = not ((A and B) or C)
report "function model produced unexpected result";
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_16.vhd | 4 | 2008 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity and2 is
port ( a, b : in std_ulogic; y : out std_ulogic );
end entity and2;
--------------------------------------------------
architecture detailed_delay of and2 is
signal result : std_ulogic;
begin
gate : process (a, b) is
begin
result <= a and b;
end process gate;
delay : process (result) is
begin
if result = '1' then
y <= reject 400 ps inertial '1' after 1.5 ns;
elsif result = '0' then
y <= reject 300 ps inertial '0' after 1.2 ns;
else
y <= reject 300 ps inertial 'X' after 500 ps;
end if;
end process delay;
end architecture detailed_delay;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue476/repro2/pixel_matrix_pkg.vhd | 2 | 1481 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pixel_column_pkg;
package pixel_matrix_pkg is
generic(
NBITS : natural;
NBR_OF_CHROMA : natural;
NBR_OF_ROW : natural;
NBR_OF_COL : natural;
package local_pixel_column_pkg is new pixel_column_pkg generic map (<>)
);
use local_pixel_column_pkg.all;
type TYPE_PIXEL_MATRIX is array (NBR_OF_COL-1 downto 0) of TYPE_PIXEL_COLUMN;
-- Note: this pkgs is used to propagate the functions that where defined for a (N x 1) array of pixel
-- to a (N x M) array of pixel
function std_logic_vector_to_pixel_matrix( in_vector : in std_logic_vector(NBR_OF_COL*NBR_OF_ROW*NBR_OF_CHROMA*NBITS-1 downto 0))
return TYPE_PIXEL_MATRIX;
end package pixel_matrix_pkg;
package body pixel_matrix_pkg is
function std_logic_vector_to_pixel_matrix( in_vector : in std_logic_vector(NBR_OF_COL*NBR_OF_ROW*NBR_OF_CHROMA*NBITS-1 downto 0))
return TYPE_PIXEL_MATRIX is
variable pixel_matrix : TYPE_PIXEL_MATRIX;
begin
for col in 0 to NBR_OF_COL-1 loop
pixel_matrix(col) := std_logic_vector_to_pixel_column(in_vector((col+1)*NBR_OF_ROW*NBR_OF_CHROMA*NBITS-1 downto col*NBR_OF_ROW*NBR_OF_CHROMA*NBITS));
end loop;
return pixel_matrix;
end function std_logic_vector_to_pixel_matrix;
end package body pixel_matrix_pkg;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/add_487.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_487 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_487;
architecture augh of add_487 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc527.vhd | 4 | 4172 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc527.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00527ent IS
END c03s03b00x00p03n04i00527ent;
ARCHITECTURE c03s03b00x00p03n04i00527arch OF c03s03b00x00p03n04i00527ent IS
BEGIN
TESTING : PROCESS
-- first index constraint method
type bv_ptr is access bit_vector(0 to 7);
variable v_bv_ptr1: bv_ptr := new bit_vector'("00000001");
variable v_bv_ptr2: bv_ptr;
variable v_bv_ptr3: bv_ptr := v_bv_ptr1;
-- second index constraint method
subtype tbus is bit_vector(1 to 8);
type bus_ptr is access tbus;
variable v_bv_ptr4: bus_ptr := new tbus'("10000000");
-- third index constraint method
type bus_ptr2 is access bit_vector;
variable v_bv_ptr5: bus_ptr2 := new bit_vector'("1111");
variable v_bv_ptr6: bus_ptr2 := new bit_vector(1 to 4);
variable OKtest : integer := 0;
BEGIN
assert v_bv_ptr1.all = "00000001";
if (v_bv_ptr1.all = "00000001") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr2 = null;
if (v_bv_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr3.all = "00000001";
if (v_bv_ptr3.all = "00000001") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr4.all = "10000000";
if (v_bv_ptr4.all = "10000000") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr5.all = "1111";
if (v_bv_ptr5.all = "1111") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr6.all = "0000";
if (v_bv_ptr6.all = "0000") then
OKtest := Oktest + 1;
end if;
v_bv_ptr2 := new bit_vector'("00110011");
assert v_bv_ptr2.all = "00110011";
if (v_bv_ptr6.all = "0000") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr1.all & v_bv_ptr3.all) = "0000000100000001";
if ((v_bv_ptr1.all & v_bv_ptr3.all) = "0000000100000001") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr1.all & v_bv_ptr2.all) = "0000000100110011";
if ((v_bv_ptr1.all & v_bv_ptr2.all) = "0000000100110011") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr5.all & v_bv_ptr6.all) = "11110000";
if ((v_bv_ptr5.all & v_bv_ptr6.all) = "11110000") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr5.all & v_bv_ptr1.all) = "111100000001";
if ((v_bv_ptr5.all & v_bv_ptr1.all) = "111100000001") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr6.all /= v_bv_ptr5.all) = true;
if ((v_bv_ptr6.all /= v_bv_ptr5.all) = true) then
OKtest := Oktest + 1;
end if;
deallocate(v_bv_ptr1);
deallocate(v_bv_ptr2);
deallocate(v_bv_ptr4);
deallocate(v_bv_ptr5);
deallocate(v_bv_ptr6);
assert NOT(OKtest = 12)
report "***PASSED TEST: c03s03b00x00p03n04i00527"
severity NOTE;
assert (OKtest = 12)
report "***FAILED TEST: c03s03b00x00p03n04i00527 - Bit Vector type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00527arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1058.vhd | 4 | 1895 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1058.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01058ent IS
END c06s04b00x00p03n02i01058ent;
ARCHITECTURE c06s04b00x00p03n02i01058arch OF c06s04b00x00p03n02i01058ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (EN1, EN2, EN3);
type A22 is array (ENUM1, ENUM1) of BOOLEAN;
variable V1: BOOLEAN;
variable V22: A22 ;
BEGIN
V1 := V22(EN1, EN2, EN3); -- ONE MORE
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01058 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01058arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc171.vhd | 4 | 1786 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc171.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n01i00171ent IS
port (ABus : in bit;
DBus : out bit;
MemReq : in bit;
BusReq : inout bit;
BusAck : buffer bit;
DataRdy : linkage bit);
constant Board : integer := 7 ;
END c04s03b03x01p03n01i00171ent;
ARCHITECTURE c04s03b03x01p03n01i00171arch OF c04s03b03x01p03n01i00171ent IS
alias SIGN1 : bit is BusReq; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c04s03b03x01p03n01i00171"
severity NOTE;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n01i00171arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/cmp_865.vhd | 2 | 381 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_865 is
port (
ne : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end cmp_865;
architecture augh of cmp_865 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3204.vhd | 4 | 2184 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3204.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library STD;
use STD.TEXTIO.all;
ENTITY c14s03b00x00p59n01i03204ent IS
END c14s03b00x00p59n01i03204ent;
ARCHITECTURE c14s03b00x00p59n01i03204arch OF c14s03b00x00p59n01i03204ent IS
BEGIN
TESTING: PROCESS
file F_out : Text open write_mode is "iofile.47";
variable L_out : Line;
type TA is array (INTEGER range <>) of TIME;
constant A : TA := (-1 fs, 37582 ns, 1 ms + 1 ns + 1 ps);
BEGIN
for i in A'RANGE loop
Write(L_out, A(i), UNIT=>fs, FIELD=>25);
WriteLine(F_out, L_out);
Write(L_out, A(i), UNIT=>ps, FIELD=>25);
WriteLine(F_out, L_out);
Write(L_out, A(i), UNIT=>ns, FIELD=>25);
WriteLine(F_out, L_out);
WriteLine(F_out, L_out);
end loop;
wait for 10 fs;
assert FALSE
report "***PASSED TEST: c14s03b00x00p59n01i03204 - This test will output an output file, and that file will be compared with s010401.ref file."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p59n01i03204arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1306.vhd | 4 | 1913 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1306.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01306ent IS
END c08s04b00x00p06n01i01306ent;
ARCHITECTURE c08s04b00x00p06n01i01306arch OF c08s04b00x00p06n01i01306ent IS
signal S1 : BIT := '1';
type REC_1 is record
RE_1:BIT;
RE_2:INTEGER;
end record;
signal S3 : REC_1;
BEGIN
TESTING: PROCESS
BEGIN
S3.RE_1 <= S1;
wait for 1 ns;
assert NOT(S3.RE_1 = '1')
report "***PASSED TEST: c08s04b00x00p06n01i01306"
severity NOTE;
assert (S3.RE_1 = '1')
report "***FAILED TEST: c08s04b00x00p06n01i01306 - A indexed name can be used on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01306arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue1262/tb.vhdl | 1 | 588 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb is
end entity;
architecture test of tb is
constant w : integer := 3;
package slv_tb_pkg is new work.slv generic map(N => w);
component ent
generic(
WIDTH: integer
);
port (
o_slv: out slv_tb_pkg.slv_t
);
end component ent;
signal s_out : std_logic_vector(w-1 downto 0);
begin
e : ent
generic map(
WIDTH => w
)
port map(
o_slv => s_out
);
process
begin
wait for 1 ns;
report integer'image(to_integer(unsigned(s_out)));
wait;
end process;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2657.vhd | 4 | 1590 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2657.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02657ent IS
END c13s03b01x00p02n01i02657ent;
ARCHITECTURE c13s03b01x00p02n01i02657arch OF c13s03b01x00p02n01i02657ent IS
BEGIN
TESTING: PROCESS
variable <k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02657 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02657arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2906.vhd | 4 | 1770 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2906.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02906ent IS
END c02s01b01x02p03n01i02906ent;
ARCHITECTURE c02s01b01x02p03n01i02906arch OF c02s01b01x02p03n01i02906ent IS
procedure proc1 (signal S1: in bit) is
variable V2 : boolean;
begin
-- Failure_here : attribute STABLE may not be read within a procedure
V2 := S1'stable;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02906 - The attribute STABLE of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02906arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue984/const_pkg.vhd | 1 | 107 | use work.types_pkg.all;
package const_pkg is
constant c : generic_type := (others => 5);
end package;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug041/foo.vhdl | 2 | 183 | entity foo is
end entity;
architecture fum of foo is
signal a: bit_vector (1 to 1);
signal b: bit_vector (1 to 1);
begin
a(1 to 1) <= b(1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/const01/const02.vhdl | 1 | 1460 | library ieee;
use ieee.std_logic_1164.all;
entity const02a is
generic (init : std_logic_vector(31 downto 0) := x"10203040");
port (o : out std_logic_vector(0 to 31));
end const02a;
architecture behav of const02a is
type slv_array is array (natural range <>) of std_logic_vector(7 downto 0);
function conv (v : std_logic_vector) return slv_array is
variable r : slv_array(0 to v'length / 8 - 1);
begin
for i in 0 to r'length-1 loop
r (i) := v(v'length - (i*8) - 1 downto v'length - (i*8) - 8);
end loop;
return r;
end conv;
constant res : slv_array (0 to 3) := conv (init);
begin
o (0 to 7) <= res (0);
o (8 to 15) <= res (1);
o (16 to 23) <= res (2);
o (24 to 31) <= res (3);
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity const02b is
generic (init : std_logic_vector(31 downto 0));
port (o : out std_logic_vector(0 to 31));
end const02b;
architecture behav of const02b is
begin
inst: entity work.const02a
generic map (init => init)
port map (o => o);
end behav;
library ieee;
use ieee.std_logic_1164.all;
package cst_pkg is
constant init : std_logic_vector(31 downto 0) := x"10203040";
end cst_pkg;
library ieee;
use ieee.std_logic_1164.all;
use work.cst_pkg.all;
entity const02 is
port (o : out std_logic_vector(0 to 31));
end const02;
architecture behav of const02 is
begin
inst: entity work.const02b
generic map (init => init)
port map (o => o);
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2479.vhd | 4 | 1817 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2479.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p13n04i02479ent IS
END c07s03b02x02p13n04i02479ent;
ARCHITECTURE c07s03b02x02p13n04i02479arch OF c07s03b02x02p13n04i02479ent IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(CA_DOWN'LEFT = 10)
report "***PASSED TEST: c07s03b02x02p13n04i02479"
severity NOTE;
assert (CA_DOWN'LEFT = 10)
report "***FAILED TEST: c07s03b02x02p13n04i02479 - S'LEFT did not return the correct value."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p13n04i02479arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1832.vhd | 4 | 1873 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1832.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01832ent IS
type small_int is range 0 to 7;
type byte is range 0 to 3;
END c07s01b00x00p08n01i01832ent;
ARCHITECTURE c07s01b00x00p08n01i01832arch OF c07s01b00x00p08n01i01832ent IS
function test return small_int is
begin
return c07s01b00x00p08n01i01832nt; -- entity name illegal here
end test;
signal s_int : small_int := 0;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= test after 5 ns;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01832 - Entity name are not permitted as primaries in a function return statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01832arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug085/foo.vhdl | 1 | 268 | entity foo is
end entity;
architecture fum of foo is
begin
process
begin
report "integer'high = " & integer'image(integer'high);
report "16#1FFFFFFFF# = "
& integer'image(16#1FFFFFFFF#);
wait;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1478.vhd | 4 | 1985 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1478.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p04n01i01478ent IS
END c08s08b00x00p04n01i01478ent;
ARCHITECTURE c08s08b00x00p04n01i01478arch OF c08s08b00x00p04n01i01478ent IS
BEGIN
TESTING: PROCESS
type i_array_type is array (1 to 5) of integer;
variable a1 : i_array_type := (others => 0);
BEGIN
case a1 is -- illegal, must be discrete
when 0 =>
assert false
report "Array allowed as case expression."
severity note ;
when others =>
assert false
report "Array allowed as case expression."
severity note ;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p04n01i01478 - Array type is not allowed in expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p04n01i01478arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1040.vhd | 4 | 1904 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1040.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01040ent IS
END c06s04b00x00p03n01i01040ent;
ARCHITECTURE c06s04b00x00p03n01i01040arch OF c06s04b00x00p03n01i01040ent IS
type A is array (1 to 10) of integer;
function foo (f:integer := 3) return A is
variable v: A := (1,2,3,4,5,6,7,8,9,10);
begin
return v;
end foo;
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
k := foo(3)(3);
assert NOT( k=3 )
report "***PASSED TEST: c06s04b00x00p03n01i01040"
severity NOTE;
assert ( k=3 )
report "***FAILED TEST: c06s04b00x00p03n01i01040 - The prefix of an indexed name must be appropriate for an array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01040arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2264.vhd | 4 | 1842 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2264.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p11n01i02264ent IS
END c07s02b06x00p11n01i02264ent;
ARCHITECTURE c07s02b06x00p11n01i02264arch OF c07s02b06x00p11n01i02264ent IS
BEGIN
TESTING: PROCESS
variable V1,V2,V3 : Integer ;
variable A : Integer := 10 ;
variable B : Integer := 5 ;
BEGIN
V1 := (-A)/B ;
V2 := A/(-B) ;
assert NOT(V1 = V2)
report "***PASSED TEST: c07s02b06x00p11n01i02264"
severity NOTE;
assert (V1 = V2)
report "***FAILED TEST: c07s02b06x00p11n01i02264 - Integer division satisfies the following identity: (-A)/B = -(A/B) = A/(-B)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p11n01i02264arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc434.vhd | 4 | 3226 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc434.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00434ent IS
END c03s02b01x01p19n01i00434ent;
ARCHITECTURE c03s02b01x01p19n01i00434arch OF c03s02b01x01p19n01i00434ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2real_cons_vector is array (row,column) of real;
constant C1 : s2real_cons_vector := (others => (others => 3.0));
function complex_scalar(s : s2real_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return s2real_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : s2real_cons_vector;
signal S2 : s2real_cons_vector;
signal S3 : s2real_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00434"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00434 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00434arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1185.vhd | 4 | 1619 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1185.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p02n01i01185ent IS
END c08s01b00x00p02n01i01185ent;
ARCHITECTURE c08s01b00x00p02n01i01185arch OF c08s01b00x00p02n01i01185ent IS
BEGIN
TESTING: PROCESS
variable i : integer := 0;
BEGIN
wait for 60 ns on i;
assert FALSE
report "***FAILED TEST: c08s01b00x00p02n01i01185 - Timeout clause before sensitivity clause."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p02n01i01185arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/receiver.vhd | 4 | 2393 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity receiver is
end entity receiver;
-- code from book
architecture behavioral of receiver is
-- . . . -- type declarations, etc
-- not in book
subtype packet_index_range is integer range 1 to 8;
type packet_array is array (packet_index_range) of bit;
-- end not in book
signal recovered_data : bit;
signal recovered_clock : bit;
-- . . .
procedure receive_packet ( signal rx_data : in bit;
signal rx_clock : in bit;
data_buffer : out packet_array ) is
begin
for index in packet_index_range loop
wait until rx_clock = '1';
data_buffer(index) := rx_data;
end loop;
end procedure receive_packet;
begin
packet_assembler : process is
variable packet : packet_array;
begin
-- . . .
receive_packet ( recovered_data, recovered_clock, packet );
-- . . .
end process packet_assembler;
-- . . .
-- not in book
data_generator : recovered_data <= '1' after 5 ns,
'0' after 15 ns,
'1' after 25 ns,
'0' after 35 ns,
'0' after 45 ns,
'1' after 55 ns,
'0' after 65 ns,
'1' after 75 ns;
clock_generator : process is
begin
recovered_clock <= '0' after 2 ns, '1' after 10 ns;
wait for 10 ns;
end process clock_generator;
-- end not in book
end architecture behavioral;
-- end code from book
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball.vhd | 4 | 1455 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.mechanical_systems.all;
entity ball is
end entity ball;
----------------------------------------------------------------
architecture bouncer of ball is
quantity v : velocity := 0.0;
quantity s : displacement := 10.0;
constant g : real := 9.81;
constant air_res : real := 0.1;
begin
if v'above(0.0) use
v'dot == -g - v**2*air_res;
else
v'dot == -g + v**2*air_res;
end use;
reversal_tester : process is
begin
wait on s'above(0.0);
break v => -v when s < 0.0;
end process reversal_tester;
s'dot == v;
end architecture bouncer;
| gpl-2.0 |
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