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tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_01.vhd
4
2058
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA entity inline_01 is end entity inline_01; ---------------------------------------------------------------- architecture test of inline_01 is type MVL4_ulogic is ('X', '0', '1', 'Z'); -- unresolved logic type -- code from book: type small_int is range 1 to 4; type small_array is array (small_int range <>) of -- . . . ; -- not in book MVL4_ulogic; -- end not in book -- end of code from book type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic; constant resolution_table : table := -- 'X' '0' '1' 'Z' -- ------------------ ( ( 'X', 'X', 'X', 'X' ), -- 'X' ( 'X', '0', 'X', '0' ), -- '0' ( 'X', 'X', '1', '1' ), -- '1' ( 'X', '0', '1', 'Z' ) ); -- 'Z' function resolve_MVL4 ( contribution : small_array ) return MVL4_ulogic is variable result : MVL4_ulogic := 'Z'; begin for index in contribution'range loop result := resolution_table(result, contribution(index)); end loop; return result; end function resolve_MVL4; subtype MVL4_logic is resolve_MVL4 MVL4_ulogic; signal s : MVL4_logic; begin driver_1 : s <= 'Z'; driver_2 : s <= 'Z'; driver_3 : s <= 'Z'; driver_4 : s <= 'Z'; driver_5 : s <= 'Z'; end architecture test;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_21a.vhd
4
1690
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library ieee_proposed; use ieee_proposed.electrical_systems.all; use ieee_proposed.mechanical_systems.all; entity inline_21a is end entity inline_21a; architecture test of inline_21a is -- code from book quantity d : displacement; limit d : displacement with 0.001; -- quantity drive_shaft_av, axle_av, wheel_av : angular_velocity; -- limit drive_shaft_av, axle_av, wheel_av : angular_velocity with 0.01; -- limit all : angular_velocity with 0.01; -- quantity input, preamp_out, mixer_out, agc_out : voltage; limit input, preamp_out : voltage with 1.0E-9; limit others : voltage with 1.0E-7; -- terminal bus1 : electrical_vector(1 to 8); terminal bus2 : electrical_vector(1 to 8); quantity v_bus across bus1 to bus2; limit v_bus : voltage_vector with 1.0E-3; -- end code from book begin end architecture test;
gpl-2.0
tgingold/ghdl
testsuite/gna/bug019/PoC/tb/common/my_config_ML505.vhdl
2
1808
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Package: Project specific configuration. -- -- Description: -- ------------------------------------ -- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl. -- -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library PoC; package my_config is -- Change these lines to setup configuration. constant MY_BOARD : string := "ML505"; -- ML505 - Xilinx Virtex 5 reference design board: XC5VLX50T constant MY_DEVICE : string := "None"; -- infer from MY_BOARD -- For internal use only constant MY_VERBOSE : boolean := FALSE; end package; package body my_config is end package body;
gpl-2.0
tgingold/ghdl
testsuite/gna/issue50/idct.d/add_173.vhd
2
800
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity add_173 is port ( result : out std_logic_vector(26 downto 0); in_a : in std_logic_vector(26 downto 0); in_b : in std_logic_vector(26 downto 0) ); end add_173; architecture augh of add_173 is signal carry_inA : std_logic_vector(28 downto 0); signal carry_inB : std_logic_vector(28 downto 0); signal carry_res : std_logic_vector(28 downto 0); begin -- To handle the CI input, the operation is '1' + CI -- If CI is not present, the operation is '1' + '0' carry_inA <= '0' & in_a & '1'; carry_inB <= '0' & in_b & '0'; -- Compute the result carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); -- Set the outputs result <= carry_res(27 downto 1); end architecture;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc114.vhd
4
3518
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc114.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- Package c04s03b02x00p29n10i00114pkg is type Apollo_string is array (INTEGER range 1 to 8) of CHARACTER; type V_REGISTER is array (INTEGER range 0 to 7) of BIT; end c04s03b02x00p29n10i00114pkg; use work.c04s03b02x00p29n10i00114pkg.all; ENTITY c04s03b02x00p29n10i00114ent IS port ( p23 : inout Boolean := FALSE; p24 : inout Bit := '0' ; p25 : inout Character := NUL ; p26 : inout SEVERITY_LEVEL := NOTE ; p27 : inout Integer := -1 ; p28 : inout Real := -1.0 ; p29 : inout TIME := 1 fs ; p30 : inout Natural := 0 ; p31 : inout Positive := 1 ; p32 : inout Apollo_string := "abcdefgh"; p33 : inout V_register := B"10010110" ); END c04s03b02x00p29n10i00114ent; ARCHITECTURE c04s03b02x00p29n10i00114arch OF c04s03b02x00p29n10i00114ent IS BEGIN TESTING: PROCESS BEGIN p23 <= not p23; p24 <= not p24; p25 <= character'succ(p25); p26 <= severity_level'succ(p26); p27 <= p27 + p27; p28 <= p28 + p28; p29 <= p29 + p29; p30 <= p30 + p30; p31 <= p31 + p31; p32(2) <= character'succ(p32(2)); p33(1) <= not p33(1); wait on p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33; assert NOT( p23 = TRUE and p24 = '1' and p25 = SOH and p26 = WARNING and p27 = -2 and p28 = -2.0 and p29 = 2 fs and p30 = 0 and p31 = 2 and p32 = "accdefgh"and p33 = B"11010110" ) report "***PASSED TEST: c04s03b02x00p29n10i00114" severity NOTE; assert ( p23 = TRUE and p24 = '1' and p25 = SOH and p26 = WARNING and p27 = -2 and p28 = -2.0 and p29 = 2 fs and p30 = 0 and p31 = 2 and p32 = "accdefgh"and p33 = B"11010110" ) report "***FAILED TEST: c04s03b02x00p29n10i00114 - Interface object update test failed." severity ERROR; wait; END PROCESS TESTING; END c04s03b02x00p29n10i00114arch;
gpl-2.0
tgingold/ghdl
testsuite/gna/bug083/repro.vhdl
1
2437
library ieee; use ieee.std_logic_1164.all; entity repro is end; architecture behav of repro is type t_axilite_write_address_channel is record --DUT inputs awaddr : std_logic_vector; awvalid : std_logic; awprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss] --DUT outputs awready : std_logic; end record; type t_axilite_write_data_channel is record --DUT inputs wdata : std_logic_vector; wstrb : std_logic_vector; wvalid : std_logic; --DUT outputs wready : std_logic; end record; type t_axilite_write_response_channel is record --DUT inputs bready : std_logic; --DUT outputs bresp : std_logic_vector(1 downto 0); bvalid : std_logic; end record; type t_axilite_read_address_channel is record --DUT inputs araddr : std_logic_vector; arvalid : std_logic; arprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss] --DUT outputs arready : std_logic; end record; type t_axilite_read_data_channel is record --DUT inputs rready : std_logic; --DUT outputs rdata : std_logic_vector; rresp : std_logic_vector(1 downto 0); rvalid : std_logic; end record; type t_axilite_if is record write_address_channel : t_axilite_write_address_channel; write_data_channel : t_axilite_write_data_channel; write_response_channel : t_axilite_write_response_channel; read_address_channel : t_axilite_read_address_channel; read_data_channel : t_axilite_read_data_channel; end record; function get_w return natural is begin return 32; end get_w; begin process constant addr_width : natural := get_w; constant data_width : natural := get_w; variable init_if : t_axilite_if ( write_address_channel( awaddr( addr_width -1 downto 0)), write_data_channel( wdata( data_width -1 downto 0), wstrb(( data_width/8) -1 downto 0)), read_address_channel( araddr( addr_width -1 downto 0)), read_data_channel( rdata( data_width -1 downto 0))); begin wait; end process; end behav;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc690.vhd
4
2584
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc690.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:03 1996 -- -- **************************** -- ENTITY c03s04b01x00p23n01i00690ent IS END c03s04b01x00p23n01i00690ent; ARCHITECTURE c03s04b01x00p23n01i00690arch OF c03s04b01x00p23n01i00690ent IS BEGIN TESTING: PROCESS -- Declare the type and the file. type DISTANCE is range 0 to 1E9 units -- Base units. A; -- angstrom -- Metric lengths. nm = 10 A; -- nanometer um = 1000 nm; -- micrometer (or micron) mm = 1000 um; -- millimeter cm = 10 mm; -- centimeter -- English lengths. mil = 254000 A; -- mil inch = 1000 mil; -- inch end units; type FilT is file of DISTANCE; -- Declare the actual file to write. file FILEV : FilT open write_mode is "iofile.53"; -- Declare a variable. constant CON : DISTANCE := 1 nm; variable VAR : DISTANCE := CON; BEGIN -- Write out the file. for I in 1 to 100 loop WRITE( FILEV,VAR ); end loop; assert FALSE report "***PASSED TEST: c03s04b01x00p23n01i00690 - The output file will tested by test file s010418.vhd" severity NOTE; wait; END PROCESS TESTING; END c03s04b01x00p23n01i00690arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/ashenden/compliant/ch_15_latch-b.vhd
4
1155
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_15_latch-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $ -- $Revision: 1.1.1.1 $ -- -- --------------------------------------------------------------------- architecture behavior of latch is begin q <= d after Tpd when To_bit(latch_en) = '1'; end architecture behavior;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc1348.vhd
4
4804
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1348.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s04b01x00p07n01i01348ent IS END c08s04b01x00p07n01i01348ent; ARCHITECTURE c08s04b01x00p07n01i01348arch OF c08s04b01x00p07n01i01348ent IS -- Local signals. signal S : BIT := '0'; BEGIN TESTING: PROCESS -- local variables. variable S_INITIAL : BIT; variable ShouldBeTime : TIME; variable k : integer := 0; BEGIN -- 0. Keep around the initial value of S. S_INITIAL := S; -- 1. When no preemption necessary, verify the results. S <= transport (not S) after 10 ns, (S) after 20 ns; -- a. Wait for first transaction. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); -- b. Wait for second transaction. ShouldBeTime := NOW + 10 ns; wait on S; assert (ShouldBeTime = NOW); assert (S = S_INITIAL); -- 2. Preempt a transaction which is to occur at the same time as second one. S_INITIAL := S; S <= transport (S) after 10 ns; S <= transport (not S) after 10 ns; -- Should preempt first transaction. -- a. Verify that the second transaction comes as expected. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); -- b. Verify that the first transaction has been preempted. ShouldBeTime := NOW + 10 ns; wait on S for 10 ns; if (ShouldBeTime /= now) then k := 1; end if; assert (ShouldBeTime = NOW); -- 3. Preempt a transaction which is to occur at a later time than second one. S_INITIAL := S; S <= transport (S) after 15 ns; S <= transport (not S) after 10 ns; -- Should preempt first transaction. -- a. Verify that the second transaction comes as expected. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); -- b. Verify that the first transaction has been preempted. ShouldBeTime := NOW + 10 ns; wait on S for 10 ns; if (ShouldBeTime /= now) then k := 1; end if; assert (ShouldBeTime = NOW); -- 4. Preempt multiple transactions. S_INITIAL := S; S <= transport (S) after 15 ns, (not S) after 30 ns; S <= transport (not S) after 10 ns, (S) after 20 ns; -- a. Verify that the second transactions come as expected. ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= not S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = (not S_INITIAL)); ShouldBeTime := NOW + 10 ns; wait on S; if (ShouldBeTime /= now or S /= S_INITIAL) then k := 1; end if; assert (ShouldBeTime = NOW); assert (S = S_INITIAL); -- b. Verify that the first transactions have been preempted. ShouldBeTime := NOW + 40 ns; wait on S for 40 ns; if (ShouldBeTime /= now) then k := 1; end if; assert (ShouldBeTime = NOW); assert NOT( k=0 ) report "***PASSED TEST: c08s04b01x00p07n01i01348" severity NOTE; assert ( k=0 ) report "***FAILED TEST: c08s04b01x00p07n01i01348 - The sequence of transactions is used to update the projected output waveform representing the current and future values of the driver associated with the signal assignment statement." severity ERROR; wait; END PROCESS TESTING; END c08s04b01x00p07n01i01348arch;
gpl-2.0
tgingold/ghdl
testsuite/gna/issue50/idct.d/mul_534.vhd
2
503
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity mul_534 is port ( result : out std_logic_vector(30 downto 0); in_a : in std_logic_vector(30 downto 0); in_b : in std_logic_vector(14 downto 0) ); end mul_534; architecture augh of mul_534 is signal tmp_res : signed(45 downto 0); begin -- The actual multiplication tmp_res <= signed(in_a) * signed(in_b); -- Set the output result <= std_logic_vector(tmp_res(30 downto 0)); end architecture;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc1931.vhd
4
3246
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1931.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b01x00p01n02i01931ent IS END c07s02b01x00p01n02i01931ent; ARCHITECTURE c07s02b01x00p01n02i01931arch OF c07s02b01x00p01n02i01931ent IS BEGIN TESTING: PROCESS BEGIN -- -- Test operators on one-dimesioned arrays of BIT -- ASSERT ( B"1100" AND B"1010" ) = B"1000" REPORT "ERROR: composite AND operator failed : BIT" SEVERITY FAILURE; ASSERT ( B"1100" OR B"1010" ) = B"1110" REPORT "ERROR: composite OR operator failed : BIT" SEVERITY FAILURE; ASSERT ( B"1100" NAND B"1010" ) = B"0111" REPORT "ERROR: composite NAND operator failed : BIT" SEVERITY FAILURE; ASSERT ( B"1100" NOR B"1010" ) = B"0001" REPORT "ERROR: composite NOR operator failed : BIT" SEVERITY FAILURE; ASSERT ( B"1100" XOR B"1010" ) = B"0110" REPORT "ERROR: composite XOR operator failed : BIT" SEVERITY FAILURE; ASSERT ( NOT B"1100" ) = B"0011" REPORT "ERROR: composite NOT operator failed : BIT" SEVERITY FAILURE; wait for 5 ns; assert NOT( (( B"1100" AND B"1010" ) = B"1000") and (( B"1100" OR B"1010" ) = B"1110") and (( B"1100" NAND B"1010" ) = B"0111") and (( B"1100" NOR B"1010" ) = B"0001") and (( B"1100" XOR B"1010" ) = B"0110") and (( NOT B"1100" ) = B"0011") ) report "***PASSED TEST: c07s02b01x00p01n02i01931" severity NOTE; assert ( (( B"1100" AND B"1010" ) = B"1000") and (( B"1100" OR B"1010" ) = B"1110") and (( B"1100" NAND B"1010" ) = B"0111") and (( B"1100" NOR B"1010" ) = B"0001") and (( B"1100" XOR B"1010" ) = B"0110") and (( NOT B"1100" ) = B"0011") ) report "***FAILED TEST: c07s02b01x00p01n02i01931 - Logical operators should be valid for any one-dimensional array type whose element type is BIT." severity ERROR; wait; END PROCESS TESTING; END c07s02b01x00p01n02i01931arch;
gpl-2.0
tgingold/ghdl
testsuite/synth/var01/tb_var01.vhdl
1
1046
entity tb_var01 is end tb_var01; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_var01 is signal clk : std_logic; signal mask : std_logic_vector (3 downto 0); signal val : std_logic_vector (31 downto 0); signal res : std_logic_vector (31 downto 0); begin dut: entity work.var01 port map ( clk => clk, mask => mask, val => val, res => res); process procedure pulse is begin clk <= '0'; wait for 1 ns; clk <= '1'; wait for 1 ns; end pulse; begin mask <= x"f"; val <= x"12_34_56_78"; pulse; assert res = x"12_34_56_78" report "res=" & to_hstring (res) severity failure; mask <= x"8"; val <= x"9a_00_00_00"; pulse; assert res = x"9a_34_56_78" severity failure; mask <= x"0"; val <= x"00_00_00_00"; pulse; assert res = x"9a_34_56_78" severity failure; mask <= x"5"; val <= x"00_bc_00_de"; pulse; assert res = x"9a_bc_56_de" severity failure; wait; end process; end behav;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2214.vhd
4
1899
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2214.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b06x00p01n01i02214ent IS END c07s02b06x00p01n01i02214ent; ARCHITECTURE c07s02b06x00p01n01i02214arch OF c07s02b06x00p01n01i02214ent IS BEGIN TESTING: PROCESS -- All different non-numeric type declarations. -- enumerated types. type SWITCH_LEVEL is ('0', '1', 'X'); subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1'; -- Local declarations. variable LOGICV : LOGIC_SWITCH := '0'; variable k : integer; BEGIN k := LOGICV rem '0'; assert FALSE report "***FAILED TEST: c07s02b06x00p01n01i02214 - Operators mod and rem are predefined for any integer type only." severity ERROR; wait; END PROCESS TESTING; END c07s02b06x00p01n01i02214arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3106.vhd
4
1991
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc3106.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c05s01b00x00p17n01i03106pkg is attribute p: POSITIVE; attribute p of c05s01b00x00p17n01i03106pkg : package is 10; end c05s01b00x00p17n01i03106pkg; use work.c05s01b00x00p17n01i03106pkg.all; ENTITY c05s01b00x00p17n01i03106ent IS END c05s01b00x00p17n01i03106ent; ARCHITECTURE c05s01b00x00p17n01i03106arch OF c05s01b00x00p17n01i03106ent IS BEGIN blk : block attribute p of c05s01b00x00p17n01i03106arch : architecture is 10; -- Failure_here begin end block blk; TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c05s01b00x00p17n01i03106 - The attribute specification for an attribute of a design unit does not appear immediately within the declarative part of that design unit." severity ERROR; wait; END PROCESS TESTING; END c05s01b00x00p17n01i03106arch;
gpl-2.0
tgingold/ghdl
testsuite/gna/issue328/t3.vhdl
1
264
entity t3 is end t3; library ieee; use ieee.std_logic_1164.all; architecture behav of t3 is signal s : std_logic; begin b: block port (p : out std_logic := '0'); port map (p => s); begin end block; assert s = '0' severity failure; end behav;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc3155.vhd
4
2712
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc3155.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c05s03b00x00p01n01i03155ent IS END c05s03b00x00p01n01i03155ent; ARCHITECTURE c05s03b00x00p01n01i03155arch OF c05s03b00x00p01n01i03155ent IS -- Define resolution function for SIG: function RESFUNC( S : BIT_VECTOR ) return BIT is begin for I in S'RANGE loop if (S(I) = '1') then return '1'; end if; end loop; return '0'; end RESFUNC; -- Define the signal. subtype RBIT is RESFUNC BIT; signal SIG : RBIT bus; -- Define the disconnect specification. disconnect SIG : RBIT after 0 ns; -- Define the GUARD signal. signal GUARD : BOOLEAN := FALSE; BEGIN -- Define the guarded signal assignment. L1: block( GUARD = TRUE ) begin SIG <= guarded '1'; end block L1; TESTING: PROCESS variable pass : integer := 0; BEGIN -- 1. Turn on the GUARD, verify that SIG gets toggled. GUARD <= TRUE; wait on SIG; assert( SIG = '1' ); if ( SIG = '1' ) then pass := pass + 1; end if; -- 2. Turn off the GUARD, verify that SIG gets turned OFF. GUARD <= FALSE; wait on SIG; assert( SIG = '0' ); if ( SIG = '0' ) then pass := pass + 1; end if; wait for 50 ns; assert NOT( pass = 2 ) report "***PASSED TEST: c05s03b00x00p01n01i03155" severity NOTE; assert ( pass = 2 ) report "***FAILED TEST: c05s03b00x00p01n01i03155 - Disconnect does not work properly." severity ERROR; wait; END PROCESS TESTING; END c05s03b00x00p01n01i03155arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc1748.vhd
4
4157
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1748.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c09s05b00x00p16n01i01748ent IS END c09s05b00x00p16n01i01748ent; ARCHITECTURE c09s05b00x00p16n01i01748arch OF c09s05b00x00p16n01i01748ent IS signal gate_1 : BIT; signal gate_2 : BIT; signal data_in : BIT; signal data_pass : BIT; signal data_latch : BIT; BEGIN gate_1 <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns; gate_2 <= gate_1 after 1 ns; data_in <= '1' after 5 ns, '0' after 25 ns, '1' after 35 ns, '0' after 36 ns, '1' after 37 ns, '0' after 38 ns, '1' after 39 ns, '0' after 40 ns, '1' after 41 ns, '0' after 42 ns; B: block ((gate_1 and gate_2) = '1') begin data_pass <= data_in; data_latch <= guarded data_in; end block; TESTING: PROCESS(data_pass,data_latch) variable ok : integer := 1; BEGIN if (now = 5 ns) then if not(data_pass'event and data_pass = '1' and data_latch'quiet and data_latch = '0') then ok := 0; end if; elsif (now = 11 ns) then if not(data_latch'event and data_latch = '1' and data_pass'quiet and data_pass = '1') then ok := 0; end if; elsif (now = 25 ns) then if not(data_latch'quiet and data_latch = '1' and data_pass'event and data_pass = '0') then ok := 0; end if; elsif (now = 31 ns) then if not(data_latch'event and data_latch = '0' and data_pass'quiet and data_pass = '0') then ok := 0; end if; elsif (now = 35 ns) then if not(data_latch'event and data_latch = '1' and data_pass'event and data_pass = '1') then ok := 0; end if; elsif (now = 36 ns) then if not(data_latch'event and data_latch = '0' and data_pass'event and data_pass = '0') then ok := 0; end if; elsif (now = 37 ns) then if not(data_latch'event and data_latch = '1' and data_pass'event and data_pass = '1') then ok := 0; end if; elsif (now = 38 ns) then if not(data_latch'event and data_latch = '0' and data_pass'event and data_pass = '0') then ok := 0; end if; elsif (now = 39 ns) then if not(data_latch'event and data_latch = '1' and data_pass'event and data_pass = '1') then ok := 0; end if; elsif (now = 40 ns) then if not(data_latch'quiet and data_latch = '1' and data_pass'event and data_pass = '0') then ok := 0; end if; elsif (now = 41 ns) then if not(data_latch'quiet and data_latch = '1' and data_pass'event and data_pass = '1') then ok := 0; end if; end if; if (now > 41 ns) then assert NOT( ok=1 ) report "***PASSED TEST: c09s05b00x00p16n01i01748" severity NOTE; assert ( ok=1 ) report "***FAILED TEST: c09s05b00x00p16n01i01748 - Concurrent signal assignment test failed." severity ERROR; end if; END PROCESS TESTING; END c09s05b00x00p16n01i01748arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_08.vhd
4
1482
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_17_ch_17_08.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $ -- $Revision: 1.1.1.1 $ -- -- --------------------------------------------------------------------- entity ch_17_08 is end entity ch_17_08; ---------------------------------------------------------------- architecture test of ch_17_08 is type T is (t1, t2, t3); -- code from book: type T_ptr is access T; procedure deallocate ( P : inout T_ptr ); -- end of code from book procedure deallocate ( P : inout T_ptr ) is begin null; end procedure deallocate; -- end of code from book begin end architecture test;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2344.vhd
4
1733
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2344.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b07x00p02n02i02344ent IS END c07s02b07x00p02n02i02344ent; ARCHITECTURE c07s02b07x00p02n02i02344arch OF c07s02b07x00p02n02i02344ent IS BEGIN TESTING: PROCESS type WORD is array(0 to 31) of BIT; type WORDPTR is access WORD; variable WORDPTRV : WORDPTR; variable INTV : INTEGER; BEGIN INTV := WORDPTRV ** 2; assert FALSE report "***FAILED TEST: c07s02b07x00p02n02i02344 - Exponent can only be of type Integer." severity ERROR; wait; END PROCESS TESTING; END c07s02b07x00p02n02i02344arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1713.vhd
4
1783
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1713.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c09s02b00x00p10n01i01713ent IS port (signal max : in natural); type word is array (natural range <>) of bit; subtype mem_array is word (0 to 7); END c09s02b00x00p10n01i01713ent; ARCHITECTURE c09s02b00x00p10n01i01713arch OF c09s02b00x00p10n01i01713ent IS signal idx : natural; signal mem : mem_array; BEGIN TESTING: PROCESS(mem_array'(others => '1')) BEGIN assert FALSE report "***FAILED TEST: c09s02b00x00p10n01i01713 - Process sensitivity list can not be a qualified aggregate." severity ERROR; END PROCESS TESTING; END c09s02b00x00p10n01i01713arch;
gpl-2.0
tgingold/ghdl
testsuite/gna/issue736/simple_fsm.vhdl
1
880
--Standard Library library ieee; --Standard Packages use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity simple_fsm is port ( clk : in std_logic; rst : in std_logic; valid : in std_logic; invalid : in std_logic ); end simple_fsm; architecture rtl of simple_fsm is type t_states is (e_IDLE, e_S1); signal p_state : t_states := e_IDLE; signal n_state : t_states; begin p_sync_fsm : process(clk) begin if rising_edge(clk) then if (rst = '1') then p_state <= e_IDLE; else p_state <= n_state; end if; end if; end process; p_comb_fsm : process (all) begin case p_state is when e_IDLE => n_state <= e_S1 when valid = '1' else e_IDLE; when e_S1 => n_state <= e_IDLE when (valid = '0' and invalid = '1') else e_S1; end case; end process; end rtl;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc437.vhd
4
3256
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc437.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY model IS PORT ( F1: OUT integer := 3; F2: INOUT integer := 3; F3: IN integer ); END model; architecture model of model is begin process begin wait for 1 ns; assert F3= 3 report"wrong initialization of F3 through type conversion" severity failure; assert F2 = 3 report"wrong initialization of F2 through type conversion" severity failure; wait; end process; end; ENTITY c03s02b01x01p19n01i00437ent IS END c03s02b01x01p19n01i00437ent; ARCHITECTURE c03s02b01x01p19n01i00437arch OF c03s02b01x01p19n01i00437ent IS type column is range 1 to 2; type row is range 1 to 8; type s2positive_cons_vector is array (row,column) of positive; constant C1 : s2positive_cons_vector := (others => (others => 1)); function complex_scalar(s : s2positive_cons_vector) return integer is begin return 3; end complex_scalar; function scalar_complex(s : integer) return s2positive_cons_vector is begin return C1; end scalar_complex; component model1 PORT ( F1: OUT integer; F2: INOUT integer; F3: IN integer ); end component; for T1 : model1 use entity work.model(model); signal S1 : s2positive_cons_vector; signal S2 : s2positive_cons_vector; signal S3 : s2positive_cons_vector := C1; BEGIN T1: model1 port map ( scalar_complex(F1) => S1, scalar_complex(F2) => complex_scalar(S2), F3 => complex_scalar(S3) ); TESTING: PROCESS BEGIN wait for 1 ns; assert NOT((S1 = C1) and (S2 = C1)) report "***PASSED TEST: c03s02b01x01p19n01i00437" severity NOTE; assert ((S1 = C1) and (S2 = C1)) report "***FAILED TEST: c03s02b01x01p19n01i00437 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype." severity ERROR; wait; END PROCESS TESTING; END c03s02b01x01p19n01i00437arch;
gpl-2.0
tgingold/ghdl
testsuite/synth/issue1307/line_delay.vhd
1
1663
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity line_delay is Port ( clk : in STD_LOGIC; ------------------------------- -- VGA data recovered from HDMI ------------------------------- in_blank : in std_logic; in_hsync : in std_logic; in_vsync : in std_logic; in_red : in std_logic_vector(7 downto 0); in_green : in std_logic_vector(7 downto 0); in_blue : in std_logic_vector(7 downto 0); ----------------------------------- -- VGA data to be converted to HDMI ----------------------------------- out_blank : out std_logic; out_hsync : out std_logic; out_vsync : out std_logic; out_red : out std_logic_vector(7 downto 0); out_green : out std_logic_vector(7 downto 0); out_blue : out std_logic_vector(7 downto 0)); end line_delay; architecture Behavioral of line_delay is type mem_block is array (0 to 511) of std_logic_vector(26 downto 0); signal mem_4 : mem_block := (others => (others => '0')); signal wr_addr : unsigned(8 downto 0) := (others =>'1'); signal mid_3 : std_logic_vector(26 downto 0) := (others =>'0'); begin process(clk) variable mem_4_out : std_logic_vector(26 downto 0); begin if rising_edge(clk) then mem_4_out := mem_4(to_integer(wr_addr)); out_green <= mem_4_out(18 downto 11); out_blue <= mem_4_out(10 downto 3); mem_4(to_integer(wr_addr)) <= mid_3; end if; end process; end Behavioral;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc2133.vhd
4
2378
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2133.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b04x00p21n01i02133ent IS END c07s02b04x00p21n01i02133ent; ARCHITECTURE c07s02b04x00p21n01i02133arch OF c07s02b04x00p21n01i02133ent IS TYPE simple_record is record data_1 : integer; data_2 : integer; end record; TYPE record_v is array (integer range <>) of simple_record; SUBTYPE record_5 is record_v (1 to 5); SUBTYPE record_4 is record_v (1 to 4); BEGIN TESTING: PROCESS variable result : record_5; variable l_operand : record_4 := ((12,34),(56,78),(12,34),(56,78)); variable r_operand : simple_record := (12,34); BEGIN -- -- The element is treated as an implicit single element array ! -- result := l_operand & r_operand; wait for 5 ns; assert NOT( result = ((12,34),(56,78),(12,34),(56,78),(12,34))) report "***PASSED TEST: c07s02b04x00p21n01i02133" severity NOTE; assert ( result = ((12,34),(56,78),(12,34),(56,78),(12,34))) report "***FAILED TEST: c07s02b04x00p21n01i02133 - Concatenation of element and RECORD array failed." severity ERROR; wait; END PROCESS TESTING; END c07s02b04x00p21n01i02133arch;
gpl-2.0
tgingold/ghdl
testsuite/gna/bug061/dictp08.vhdl
2
5539
library ieee; use ieee.std_logic_1164.all; package corelib_Dict is generic ( type KEY_TYPE; type VALUE_TYPE; function to_hash(d : in KEY_TYPE; size : positive) return natural; INIT_SIZE : natural := 128 ); type PT_DICT is protected procedure Set (constant key : in KEY_TYPE; constant data : in VALUE_TYPE); procedure Get (constant key : in KEY_TYPE; data : out VALUE_TYPE); impure function Get (constant key : KEY_TYPE) return VALUE_TYPE; procedure Del (constant key : in KEY_TYPE); procedure Clear; impure function HasKey (constant key : KEY_TYPE) return boolean; impure function Count return natural; end protected PT_DICT; procedure Merge(d0 : inout PT_DICT; d1 : inout PT_DICT; dout : inout PT_DICT); end package corelib_Dict; package body corelib_Dict is type t_key_ptr is access KEY_TYPE; type t_data_ptr is access VALUE_TYPE; type PT_DICT is protected body type t_entry; type t_entry_ptr is access t_entry; type t_entry is record key : t_key_ptr; data : t_data_ptr; last_entry : t_entry_ptr; next_entry : t_entry_ptr; end record t_entry; type t_entry_array is array (0 to INIT_SIZE-1) of t_entry_ptr; variable head : t_entry_array := (others => null); variable entry_count : integer_vector(0 to INIT_SIZE-1) := (others => 0); -- Private method to find entry stored in dictionary impure function Find (constant key : KEY_TYPE) return t_entry_ptr; impure function Find (constant key : KEY_TYPE) return t_entry_ptr is variable entry : t_entry_ptr := head(to_hash(key, INIT_SIZE)); begin while (entry /= null) loop if (entry.key.all = key) then return entry; end if; entry := entry.last_entry; end loop; return null; end function Find; procedure Set (constant key : in KEY_TYPE; constant data : in VALUE_TYPE) is variable addr : natural := 0; variable entry : t_entry_ptr := Find(key); begin if (entry = null) then addr := to_hash(key, INIT_SIZE); if (head(addr) /= null) then entry := new t_entry; entry.key := new KEY_TYPE'(key); entry.data := new VALUE_TYPE'(data); entry.last_entry := head(addr); entry.next_entry := null; head(addr) := entry; head(addr).last_entry.next_entry := head(addr); else head(addr) := new t_entry; head(addr).key := new KEY_TYPE'(key); head(addr).data := new VALUE_TYPE'(data); head(addr).last_entry := null; head(addr).next_entry := null; end if; entry_count(addr) := entry_count(addr) + 1; else entry.data.all := data; end if; end procedure Set; procedure Get (constant key : in KEY_TYPE; data : out VALUE_TYPE) is variable entry : t_entry_ptr := Find(key); begin assert entry /= null report PT_DICT'instance_name & ": ERROR: key not found" severity failure; data := entry.data.all; end procedure Get; impure function Get (constant key : KEY_TYPE) return VALUE_TYPE is variable entry : t_entry_ptr := Find(key); begin assert entry /= null report PT_DICT'instance_name & ": ERROR: key not found" severity failure; return entry.data.all; end function Get; procedure Del (constant key : in KEY_TYPE) is variable entry : t_entry_ptr := Find(key); variable addr : natural := 0; begin if (entry /= null) then addr := to_hash(key, INIT_SIZE); -- remove head entry if(entry.next_entry = null and entry.last_entry /= null) then entry.last_entry.next_entry := null; head(addr) := entry.last_entry; -- remove start entry elsif(entry.next_entry /= null and entry.last_entry = null) then entry.next_entry.last_entry := null; -- remove from between elsif(entry.next_entry /= null and entry.last_entry /= null) then entry.last_entry.next_entry := entry.next_entry; entry.next_entry.last_entry := entry.last_entry; else head(addr) := null; end if; deallocate(entry.key); deallocate(entry.data); deallocate(entry); entry_count(addr) := entry_count(addr) - 1; end if; end procedure Del; procedure Clear is variable entry : t_entry_ptr; variable entry_d : t_entry_ptr; begin for i in t_entry_array'range loop entry := head(i); while (entry /= null) loop entry_d := entry; Del(entry_d.key.all); entry := entry.last_entry; end loop; end loop; end procedure Clear; impure function HasKey (constant key : KEY_TYPE) return boolean is begin return Find(key) /= null; end function HasKey; impure function Count return natural is variable value : natural := 0; begin for i in entry_count'range loop value := value + entry_count(i); end loop; return value; end function Count; end protected body PT_DICT; procedure Merge(d0 : inout PT_DICT; d1 : inout PT_DICT; dout : inout PT_DICT) is begin end procedure Merge; end package body corelib_Dict;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_02.vhd
4
1882
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_04_tb_04_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity test_bench_04_02 is end entity test_bench_04_02; ---------------------------------------------------------------- architecture test_and_multiple_behavioral of test_bench_04_02 is -- code from book: signal count_value : bit_vector(7 downto 0); signal terminal_count : bit; -- end of code from book begin -- code from book: tc_gate : entity work.and_multiple(behavioral) port map ( i => count_value, y => terminal_count); -- end of code from book stumulus : process is begin wait for 10 ns; count_value <= "10000000"; wait for 10 ns; count_value <= "11111110"; wait for 10 ns; count_value <= "01111111"; wait for 10 ns; count_value <= "11111111"; wait for 10 ns; count_value <= "00000000"; wait for 10 ns; wait; end process stumulus; end architecture test_and_multiple_behavioral;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc404.vhd
4
2003
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc404.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b01x01p18n01i00404ent IS END c03s02b01x01p18n01i00404ent; ARCHITECTURE c03s02b01x01p18n01i00404arch OF c03s02b01x01p18n01i00404ent IS type MEM is array (positive range <>) of BIT; type ME1 is array (natural range <>) of Integer; subtype ME2 is ME1(0 to 3); subtype M1 is MEM (1 to 5) ; procedure F2 (X1 : in MEM) is begin assert NOT((X1'LOW = 1) and (X1'High = 5)) report "***PASSED TEST: c03s02b01x01p18n01i00404" SEVERITY NOTE; assert ((X1'LOW = 1) and (X1'High = 5)) report "***FAILED TEST: c03s02b01x01p18n01i00404 - The index ranges are obtained from the actual designator." SEVERITY ERROR; end F2; signal S1 : M1 := "01110" ; BEGIN TESTING: PROCESS BEGIN F2(S1) ; -- No_failure_here wait; END PROCESS TESTING; END c03s02b01x01p18n01i00404arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1355.vhd
4
1748
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1355.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s05b00x00p03n01i01355ent IS END c08s05b00x00p03n01i01355ent; ARCHITECTURE c08s05b00x00p03n01i01355arch OF c08s05b00x00p03n01i01355ent IS BEGIN BL : block begin L2 : for I in 1 to 3 generate TESTING: PROCESS BEGIN I := I + 1; assert FALSE report "***FAILED TEST: c08s05b00x00p03n01i01355 - The name of thetarget of the variable assignment statement must denote a variable" severity ERROR; wait; END PROCESS TESTING; end generate; end block; END c08s05b00x00p03n01i01355arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc327.vhd
4
1692
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc327.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b01x00p04n01i00327ent IS END c03s02b01x00p04n01i00327ent; ARCHITECTURE c03s02b01x00p04n01i00327arch OF c03s02b01x00p04n01i00327ent IS -- Failure_here: bad index format; need ranges, not constants. type er1 is array(5,2) of integer; BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c03s02b01x00p04n01i00327 - The index constraint in the constrained array definition is invalid." severity ERROR; wait; END PROCESS TESTING; END c03s02b01x00p04n01i00327arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc1658.vhd
4
2107
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1658.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity E is port ( S_in : in bit; S_out : out bit) ; end E; entity C1 is port ( A : bit; B :out bit) ; end C1; use work.c1; ENTITY c09s01b00x00p02n01i01658ent IS port ( B : bit ) ; END c09s01b00x00p02n01i01658ent; ARCHITECTURE c09s01b00x00p02n01i01658arch OF c09s01b00x00p02n01i01658ent IS BEGIN lab : block component C1 port ( A : bit; B : out bit ); end component ; -- C1 for all : C1 use entity work.E port map ( S_in => A, S_out => B ) ; type T1 is ('0', '1'); subtype T2 is integer range 0 to 7; signal S1 : real; alias S1_too : real is S1; attribute ATTR : T1; attribute ATTR of ALL : signal is '1'; begin TESTING: PROCESS BEGIN assert FALSE report "***PASSED TEST: c09s01b00x00p02n01i01658" severity NOTE; wait; END PROCESS TESTING; end block lab; END c09s01b00x00p02n01i01658arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc1942.vhd
4
3761
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1942.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b01x00p01n02i01942ent IS END c07s02b01x00p01n02i01942ent; ARCHITECTURE c07s02b01x00p01n02i01942arch OF c07s02b01x00p01n02i01942ent IS TYPE b4 IS ARRAY (1 TO 4) OF BOOLEAN; CONSTANT T : BOOLEAN := TRUE; CONSTANT F : BOOLEAN :=FALSE; BEGIN TESTING: PROCESS BEGIN -- -- Test operators on one-dimesioned arrays of BOOLEAN -- ASSERT ( b4'( T,T,F,F ) AND b4'( T,F,T,F ) ) = b4'( T,F,F,F ) REPORT "ERROR: composite AND operator failed : BOOLEAN" SEVERITY FAILURE; ASSERT ( b4'( T,T,F,F ) OR b4'( T,F,T,F ) ) = b4'( T,T,T,F ) REPORT "ERROR: composite OR operator failed : BOOLEAN" SEVERITY FAILURE; ASSERT ( b4'( T,T,F,F ) NAND b4'( T,F,T,F ) ) = b4'( F,T,T,T ) REPORT "ERROR: composite NAND operator failed : BOOLEAN" SEVERITY FAILURE; ASSERT ( b4'( T,T,F,F ) NOR b4'( T,F,T,F ) ) = b4'( F,F,F,T ) REPORT "ERROR: composite NOR operator failed : BOOLEAN" SEVERITY FAILURE; ASSERT ( b4'( T,T,F,F ) XOR b4'( T,F,T,F ) ) = b4'( F,T,T,F ) REPORT "ERROR: composite XOR operator failed : BOOLEAN" SEVERITY FAILURE; ASSERT ( NOT b4'( T,T,F,F ) ) = b4'( F,F,T,T ) REPORT "ERROR: composite NOT operator failed : BOOLEAN" SEVERITY FAILURE; wait for 5 ns; assert NOT( (( b4'( T,T,F,F ) AND b4'( T,F,T,F ) ) = b4'( T,F,F,F )) and (( b4'( T,T,F,F ) OR b4'( T,F,T,F ) ) = b4'( T,T,T,F )) and (( b4'( T,T,F,F ) NAND b4'( T,F,T,F ) ) = b4'( F,T,T,T )) and (( b4'( T,T,F,F ) NOR b4'( T,F,T,F ) ) = b4'( F,F,F,T )) and (( b4'( T,T,F,F ) XOR b4'( T,F,T,F ) ) = b4'( F,T,T,F )) and (( NOT b4'( T,T,F,F ) ) = b4'( F,F,T,T )) ) report "***PASSED TEST: c07s02b01x00p01n02i01942" severity NOTE; assert ( (( b4'( T,T,F,F ) AND b4'( T,F,T,F ) ) = b4'( T,F,F,F )) and (( b4'( T,T,F,F ) OR b4'( T,F,T,F ) ) = b4'( T,T,T,F )) and (( b4'( T,T,F,F ) NAND b4'( T,F,T,F ) ) = b4'( F,T,T,T )) and (( b4'( T,T,F,F ) NOR b4'( T,F,T,F ) ) = b4'( F,F,F,T )) and (( b4'( T,T,F,F ) XOR b4'( T,F,T,F ) ) = b4'( F,T,T,F )) and (( NOT b4'( T,T,F,F ) ) = b4'( F,F,T,T )) ) report "***FAILED TEST: c07s02b01x00p01n02i01942 - Logical operators should be valid for any one-dimensional array type whose element type is BOOLEAN." severity ERROR; wait; END PROCESS TESTING; END c07s02b01x00p01n02i01942arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1771.vhd
4
1832
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1771.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c09s05b02x00p11n01i01771ent IS END c09s05b02x00p11n01i01771ent; ARCHITECTURE c09s05b02x00p11n01i01771arch OF c09s05b02x00p11n01i01771ent IS type x is (Jan,Feb,Mar); signal y : x; signal Month_Num : integer; BEGIN with y select Month_num <= transport 1 when Jan, 2 when Feb, 3 when others, -- Failure_here -- choice 'others' is not last. 4 when Mar; TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c09s05b02x00p11n01i01771 - Choice of others should be the last alternative." severity ERROR; wait; END PROCESS TESTING; END c09s05b02x00p11n01i01771arch;
gpl-2.0
tgingold/ghdl
testsuite/gna/issue828/test2.vhdl
1
1069
library ieee; use ieee.std_logic_1164.all; entity test2 is port ( tx : out std_logic); end entity; architecture tb of test2 is begin process -- variable boolobj: boolean; -- ADDED procedure transmit(data: std_logic_vector; signal tx: out std_logic) is variable norm: std_logic_vector(data'length - 1 downto 0) := data; procedure send(value: std_logic) is begin tx <= value; wait for 10 ns; end procedure; begin -- report " boolobj = " & boolean'image(boolobj); -- ADDED for i in norm'reverse_range loop send(norm(i)); report integer'image(i); --- to_string(i); -- CHANGED end loop; end procedure; variable norm: std_logic_vector(7 downto 0); -- ADDED begin transmit(x"55", tx); for i in norm'reverse_range loop -- ADDED Loop statement report "i = " & integer'image(i); end loop; wait; end process; end architecture;
gpl-2.0
tgingold/ghdl
testsuite/gna/issue233/test.vhdl
2
248
ENTITY test1 IS PORT ( i : IN integer); END ENTITY test1; ENTITY test IS PORT ( o : OUT integer); END ENTITY test; ARCHITECTURE rtl OF test IS BEGIN test1_1 : ENTITY work.test1 PORT MAP ( i => o); END ARCHITECTURE rtl;
gpl-2.0
tgingold/ghdl
testsuite/synth/sns01/sns01.vhdl
1
363
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity sns01 is port (a : natural range 0 to 15; b : out unsigned (3 downto 0); clk : std_logic); end sns01; architecture behav of sns01 is begin process (clk) begin if rising_edge(clk) then b <= conv_unsigned (a, 4); end if; end process; end behav;
gpl-2.0
tgingold/ghdl
testsuite/gna/bug0105/econcat2_87.vhdl
1
459
entity econcat2_87 is end econcat2_87; architecture behav of econcat2_87 is constant c1 : string (21 downto 17) := "hello"; constant c2 : string (6 downto 1) := " world"; constant r : string := "" & c1 & "" & c2; begin process begin case True is when c1 & c2 = "hello world" => null; when false => null; end case; assert r'left = 21 severity failure; assert r'right = 11 severity failure; wait; end process; end;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc1403.vhd
4
1917
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1403.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s05b00x00p06n01i01403ent IS END c08s05b00x00p06n01i01403ent; ARCHITECTURE c08s05b00x00p06n01i01403arch OF c08s05b00x00p06n01i01403ent IS BEGIN TESTING: PROCESS variable T : INTEGER := 1; subtype ST is BIT_VECTOR(T to 10); variable OK : BIT_VECTOR(T+1 to 11); variable ILL : BIT_VECTOR(T to 11); variable V : ST; BEGIN V := OK; assert NOT(V = "0000000000") report "***PASSED TEST: c08s05b00x00p06n01i01403" severity NOTE; assert (V = "0000000000") report "***FAILED TEST: c08s05b00x00p06n01i01403 - Variable assignment scalar subtype check test failed." severity ERROR; wait; END PROCESS TESTING; END c08s05b00x00p06n01i01403arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass_wa.vhd
4
1446
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library ieee_proposed; use ieee_proposed.mechanical_systems.all; entity moving_mass_wa is port ( terminal external_attachment : translational ); end entity moving_mass_wa; ---------------------------------------------------------------- architecture behavioral of moving_mass_wa is constant mass : real := 10.0; constant stiffness : real := 2.0; constant damping : real := 5.0; quantity position across driving_force through external_attachment; quantity velocity : real; begin velocity == position'dot; driving_force == mass*velocity'dot + damping*velocity + stiffness*position; end architecture behavioral;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc445.vhd
4
3196
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc445.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY model IS PORT ( F1: OUT integer := 3; F2: INOUT integer := 3; F3: IN integer ); END model; architecture model of model is begin process begin wait for 1 ns; assert F3= 3 report"wrong initialization of F3 through type conversion" severity failure; assert F2 = 3 report"wrong initialization of F2 through type conversion" severity failure; wait; end process; end; ENTITY c03s02b01x01p19n01i00445ent IS END c03s02b01x01p19n01i00445ent; ARCHITECTURE c03s02b01x01p19n01i00445arch OF c03s02b01x01p19n01i00445ent IS type real_vector is array (natural range <>) of real; subtype real_vector_st is real_vector(0 to 15); constant C1 : real := 4.0; constant C70 : real_vector_st :=(others => C1); function complex_scalar(s : real_vector_st) return integer is begin return 3; end complex_scalar; function scalar_complex(s : integer) return real_vector_st is begin return C70; end scalar_complex; component model1 PORT ( F1: OUT integer; F2: INOUT integer; F3: IN integer ); end component; for T1 : model1 use entity work.model(model); signal S1 : real_vector_st; signal S2 : real_vector_st; signal S3 : real_vector_st := C70; BEGIN T1: model1 port map ( scalar_complex(F1) => S1, scalar_complex(F2) => complex_scalar(S2), F3 => complex_scalar(S3) ); TESTING: PROCESS BEGIN wait for 1 ns; assert NOT((S1 = C70) and (S2 = C70)) report "***PASSED TEST: c03s02b01x01p19n01i00445" severity NOTE; assert ((S1 = C70) and (S2 = C70)) report "***FAILED TEST: c03s02b01x01p19n01i00445 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype." severity ERROR; wait; END PROCESS TESTING; END c03s02b01x01p19n01i00445arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc885.vhd
4
2352
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc885.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c10s01b00x00p10n01i00885ent IS END c10s01b00x00p10n01i00885ent; ARCHITECTURE c10s01b00x00p10n01i00885arch OF c10s01b00x00p10n01i00885ent IS signal S: INTEGER := 356; BEGIN TESTING: PROCESS constant I: INTEGER := 105; -- loop parameter has same name variable k: integer := 0; BEGIN -- assign process constant I to S S <= I; wait for 1 ns; assert ( S = 105 ) report "constant not properly assigned to signal" severity FAILURE; -- loop parameter has same name as constant declared in process for I in 1 to 5 loop -- assign loop parameter I to S S <= I; wait for 1 ns; if ((S<1) or (S>5)) then k := 1; end if; assert ( ( S >= 1 ) and ( S <= 5 ) ) report "loop parameter not properly assigned to signal" severity FAILURE; end loop; assert NOT( k=0 ) report "***PASSED TEST: c10s01b00x00p10n01i00885" severity NOTE; assert ( k=0 ) report "***FAILED TEST: c10s01b00x00p10n01i00885 - A declaration region is formed by the text of a loop statement." severity ERROR; wait; END PROCESS TESTING; END c10s01b00x00p10n01i00885arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2991.vhd
4
1763
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2991.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c02s05b00x00p02n01i02991pkg is generic ( N : Natural := 2 ) ; -- Failure_here -- ERROR: GENERIC DECLARATIONS NOT ALLOWED IN PACKAGES end c02s05b00x00p02n01i02991pkg; ENTITY c02s05b00x00p02n01i02991ent IS END c02s05b00x00p02n01i02991ent; ARCHITECTURE c02s05b00x00p02n01i02991arch OF c02s05b00x00p02n01i02991ent IS BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c02s05b00x00p02n01i02991 - Generic declarations are not allowed in package declarations." severity ERROR; wait; END PROCESS TESTING; END c02s05b00x00p02n01i02991arch;
gpl-2.0
tgingold/ghdl
testsuite/gna/bug019/PoC/tb/common/strings_tb.vhdl
4
6819
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- Testbench: Tests global constants, functions and settings -- -- Authors: Patrick Lehmann -- -- Description: -- ------------------------------------ -- TODO -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= entity strings_tb is end strings_tb; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library PoC; use PoC.config.all; use PoC.utils.all; use PoC.strings.all; use PoC.simulation.all; architecture tb of strings_tb is constant raw_format_slv_dec_result0 : STRING := raw_format_slv_dec(STD_LOGIC_VECTOR'(x"12")); constant raw_format_slv_dec_result1 : STRING := raw_format_slv_dec(x"3456"); constant raw_format_slv_dec_result2 : STRING := raw_format_slv_dec(x"12345678"); constant raw_format_slv_dec_result3 : STRING := raw_format_slv_dec(x"A1B2C3D4E5F607A8"); constant str_length_result0 : INTEGER := str_length(""); constant str_length_result1 : INTEGER := str_length((1 to 3 => C_POC_NUL)); constant str_length_result2 : INTEGER := str_length("Hello"); constant str_length_result3 : INTEGER := str_length("Hello" & (1 to 3 => C_POC_NUL)); constant str_match_result0 : BOOLEAN := str_match("", ""); constant str_match_result1 : BOOLEAN := str_match("", (1 to 3 => C_POC_NUL)); constant str_match_result2 : BOOLEAN := str_match("Hello", "hello"); constant str_match_result3 : BOOLEAN := str_match("Hello", "Hello"); constant str_match_result4 : BOOLEAN := str_match("Hello World", "Hello"); constant str_match_result5 : BOOLEAN := str_match("Hello", "Hello World"); constant str_match_result6 : BOOLEAN := str_match("Hello", "Hello" & (1 to 3 => C_POC_NUL)); constant str_imatch_result0 : BOOLEAN := str_imatch("", ""); constant str_imatch_result1 : BOOLEAN := str_imatch("", (1 to 3 => C_POC_NUL)); constant str_imatch_result2 : BOOLEAN := str_imatch("Hello", "hello"); constant str_imatch_result3 : BOOLEAN := str_imatch("Hello", "Hello"); constant str_imatch_result4 : BOOLEAN := str_imatch("Hello World", "Hello"); constant str_imatch_result5 : BOOLEAN := str_imatch("Hello", "Hello World"); constant str_imatch_result6 : BOOLEAN := str_imatch("Hello", "Hello" & (1 to 3 => C_POC_NUL)); begin process begin -- raw_format_slv_dec tests tbAssert((raw_format_slv_dec_result0 = "18"), "raw_format_slv_dec(0x12)=" & raw_format_slv_dec_result0 & " Expected='18'"); tbAssert((raw_format_slv_dec_result1 = "13398"), "raw_format_slv_dec(0x3456)=" & raw_format_slv_dec_result1 & " Expected='13398'"); tbAssert((raw_format_slv_dec_result2 = "305419896"), "raw_format_slv_dec(0x12345678)=" & raw_format_slv_dec_result2 & " Expected='305419896'"); tbAssert((raw_format_slv_dec_result3 = "11651590505119483816"), "raw_format_slv_dec(0xA1b2c3d4e5f607a8)=" & raw_format_slv_dec_result3 & " Expected='11651590505119483816'"); -- str_length tests tbAssert((str_length_result0 = 0), "str_length('')=" & INTEGER'image(str_length_result0) & " Expected=0"); tbAssert((str_length_result1 = 0), "str_length('\0\0\0')=" & INTEGER'image(str_length_result1) & " Expected=0"); tbAssert((str_length_result2 = 5), "str_length('Hello')=" & INTEGER'image(str_length_result2) & " Expected=5"); tbAssert((str_length_result3 = 5), "str_length('Hello\0\0\0')=" & INTEGER'image(str_length_result3) & " Expected=5"); -- str_match tests tbAssert((str_match_result0 = TRUE), "str_match('', '')=" & BOOLEAN'image(str_match_result0) & " Expected=TRUE"); tbAssert((str_match_result1 = TRUE), "str_match('', '\0\0\0')=" & BOOLEAN'image(str_match_result1) & " Expected=TRUE"); tbAssert((str_match_result2 = FALSE), "str_match('Hello', 'hello')=" & BOOLEAN'image(str_match_result2) & " Expected=FALSE"); tbAssert((str_match_result3 = TRUE), "str_match('Hello', 'Hello')=" & BOOLEAN'image(str_match_result3) & " Expected=TRUE"); tbAssert((str_match_result4 = FALSE), "str_match('Hello World', 'Hello')=" & BOOLEAN'image(str_match_result4) & " Expected=FALSE"); tbAssert((str_match_result5 = FALSE), "str_match('Hello', 'Hello World')=" & BOOLEAN'image(str_match_result5) & " Expected=FALSE"); tbAssert((str_match_result6 = TRUE), "str_match('Hello', 'Hello\0\0\0')=" & BOOLEAN'image(str_match_result6) & " Expected=TRUE"); -- str_imatch tests tbAssert((str_imatch_result0 = TRUE), "str_imatch('', '')=" & BOOLEAN'image(str_imatch_result0) & " Expected=TRUE"); tbAssert((str_imatch_result1 = TRUE), "str_imatch('', '\0\0\0')=" & BOOLEAN'image(str_imatch_result1) & " Expected=TRUE"); tbAssert((str_imatch_result2 = TRUE), "str_imatch('Hello', 'hello')=" & BOOLEAN'image(str_imatch_result2) & " Expected=TRUE"); tbAssert((str_imatch_result3 = TRUE), "str_imatch('Hello', 'Hello')=" & BOOLEAN'image(str_imatch_result3) & " Expected=TRUE"); tbAssert((str_imatch_result4 = FALSE), "str_imatch('Hello World', 'Hello')=" & BOOLEAN'image(str_imatch_result4) & " Expected=FALSE"); tbAssert((str_imatch_result5 = FALSE), "str_imatch('Hello', 'Hello World')=" & BOOLEAN'image(str_imatch_result5) & " Expected=FALSE"); tbAssert((str_imatch_result6 = TRUE), "str_imatch('Hello', 'Hello\0\0\0')=" & BOOLEAN'image(str_imatch_result6) & " Expected=TRUE"); -- str_pos tests -- str_ipos tests -- str_find tests -- str_ifind tests -- str_replace tests -- str_substr tests -- str_ltrim tests -- str_rtrim tests -- str_trim tests -- str_toLower tests -- str_toUpper tests -- simulation completed -- Report overall simulation result tbPrintResult; wait; end process; end;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2615.vhd
4
1587
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2615.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c13s03b01x00p02n01i02615ent IS END c13s03b01x00p02n01i02615ent; ARCHITECTURE c13s03b01x00p02n01i02615arch OF c13s03b01x00p02n01i02615ent IS BEGIN TESTING: PROCESS variable k&k : integer := 0; BEGIN assert FALSE report "***FAILED TEST: c13s03b01x00p02n01i02615 - Identifier can not contain '&'." severity ERROR; wait; END PROCESS TESTING; END c13s03b01x00p02n01i02615arch;
gpl-2.0
tgingold/ghdl
testsuite/synth/func01/tb_func07.vhdl
1
510
entity tb_func07 is end tb_func07; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_func07 is signal v, r : std_ulogic_vector(7 downto 0); begin dut: entity work.func07 port map (v, r); process begin v <= "00000000"; wait for 1 ns; assert r = x"00" severity failure; v <= "00100100"; wait for 1 ns; assert r = x"02" severity failure; v <= "11100111"; wait for 1 ns; assert r = x"06" severity failure; wait; end process; end behav;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc850.vhd
4
10019
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc850.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c01s03b01x00p12n01i00850pkg_b is constant zero : integer ; constant one : integer ; constant two : integer ; constant three: integer ; constant four : integer ; constant five : integer ; constant six : integer ; constant seven: integer ; constant eight: integer ; constant nine : integer ; constant fifteen: integer; end c01s03b01x00p12n01i00850pkg_b; package body c01s03b01x00p12n01i00850pkg_b is constant zero : integer := 0; constant one : integer := 1; constant two : integer := 2; constant three: integer := 3; constant four : integer := 4; constant five : integer := 5; constant six : integer := 6; constant seven: integer := 7; constant eight: integer := 8; constant nine : integer := 9; constant fifteen:integer:= 15; end c01s03b01x00p12n01i00850pkg_b; use work.c01s03b01x00p12n01i00850pkg_b.all; package c01s03b01x00p12n01i00850pkg_a is constant low_number : integer := 0; constant hi_number : integer := 3; subtype hi_to_low_range is integer range low_number to hi_number; type boolean_vector is array (natural range <>) of boolean; type severity_level_vector is array (natural range <>) of severity_level; type integer_vector is array (natural range <>) of integer; type real_vector is array (natural range <>) of real; type time_vector is array (natural range <>) of time; type natural_vector is array (natural range <>) of natural; type positive_vector is array (natural range <>) of positive; type record_std_package is record a: boolean; b: bit; c:character; d:severity_level; e:integer; f:real; g:time; h:natural; i:positive; end record; type array_rec_std is array (natural range <>) of record_std_package; type four_value is ('Z','0','1','X'); --enumerated type constant C1 : boolean := true; constant C2 : bit := '1'; constant C3 : character := 's'; constant C4 : severity_level := note; constant C5 : integer := 3; constant C6 : real := 3.0; constant C7 : time := 3 ns; constant C8 : natural := 1; constant C9 : positive := 1; signal Sin1 : bit_vector(zero to five) ; signal Sin2 : boolean_vector(zero to five) ; signal Sin4 : severity_level_vector(zero to five) ; signal Sin5 : integer_vector(zero to five) ; signal Sin6 : real_vector(zero to five) ; signal Sin7 : time_vector(zero to five) ; signal Sin8 : natural_vector(zero to five) ; signal Sin9 : positive_vector(zero to five) ; signal Sin10: array_rec_std(zero to five) ; end c01s03b01x00p12n01i00850pkg_a; use work.c01s03b01x00p12n01i00850pkg_a.all; use work.c01s03b01x00p12n01i00850pkg_b.all; entity test is port( sigin1 : in boolean ; sigout1 : out boolean ; sigin2 : in bit ; sigout2 : out bit ; sigin4 : in severity_level ; sigout4 : out severity_level ; sigin5 : in integer ; sigout5 : out integer ; sigin6 : in real ; sigout6 : out real ; sigin7 : in time ; sigout7 : out time ; sigin8 : in natural ; sigout8 : out natural ; sigin9 : in positive ; sigout9 : out positive ; sigin10 : in record_std_package ; sigout10 : out record_std_package ); end; architecture test of test is begin sigout1 <= sigin1; sigout2 <= sigin2; sigout4 <= sigin4; sigout5 <= sigin5; sigout6 <= sigin6; sigout7 <= sigin7; sigout8 <= sigin8; sigout9 <= sigin9; sigout10 <= sigin10; end; configuration testbench of test is for test end for; end; use work.c01s03b01x00p12n01i00850pkg_a.all; use work.c01s03b01x00p12n01i00850pkg_b.all; ENTITY c01s03b01x00p12n01i00850ent IS END c01s03b01x00p12n01i00850ent; ARCHITECTURE c01s03b01x00p12n01i00850arch OF c01s03b01x00p12n01i00850ent IS component test port( sigin1 : in boolean ; sigout1 : out boolean ; sigin2 : in bit ; sigout2 : out bit ; sigin4 : in severity_level ; sigout4 : out severity_level ; sigin5 : in integer ; sigout5 : out integer ; sigin6 : in real ; sigout6 : out real ; sigin7 : in time ; sigout7 : out time ; sigin8 : in natural ; sigout8 : out natural ; sigin9 : in positive ; sigout9 : out positive ; sigin10 : in record_std_package ; sigout10 : out record_std_package ); end component; begin Sin1(zero) <='1'; Sin2(zero) <= true; Sin4(zero) <= note; Sin5(zero) <= 3; Sin6(zero) <= 3.0; Sin7(zero) <= 3 ns; Sin8(zero) <= 1; Sin9(zero) <= 1; Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9); K:block component test port( sigin1 : in boolean ; sigout1 : out boolean ; sigin2 : in bit ; sigout2 : out bit ; sigin4 : in severity_level ; sigout4 : out severity_level ; sigin5 : in integer ; sigout5 : out integer ; sigin6 : in real ; sigout6 : out real ; sigin7 : in time ; sigout7 : out time ; sigin8 : in natural ; sigout8 : out natural ; sigin9 : in positive ; sigout9 : out positive ; sigin10 : in record_std_package ; sigout10 : out record_std_package ); end component; BEGIN T5 : test port map ( Sin2(4),Sin2(5), Sin1(4),Sin1(5), Sin4(4),Sin4(5), Sin5(4),Sin5(5), Sin6(4),Sin6(5), Sin7(4),Sin7(5), Sin8(4),Sin8(5), Sin9(4),Sin9(5), Sin10(4),Sin10(5) ); G: for i in zero to three generate T1:test port map ( Sin2(i),Sin2(i+1), Sin1(i),Sin1(i+1), Sin4(i),Sin4(i+1), Sin5(i),Sin5(i+1), Sin6(i),Sin6(i+1), Sin7(i),Sin7(i+1), Sin8(i),Sin8(i+1), Sin9(i),Sin9(i+1), Sin10(i),Sin10(i+1) ); end generate; end block; TESTING: PROCESS BEGIN wait for 1 ns; assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure; assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure; assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure; assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure; assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure; assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure; assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure; assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure; assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure; assert NOT( Sin1(0) = sin1(5) and Sin2(0) = Sin2(5) and Sin4(0) = Sin4(5) and Sin5(0) = Sin5(5) and Sin6(0) = Sin6(5) and Sin7(0) = Sin7(5) and Sin8(0) = Sin8(5) and Sin9(0) = Sin9(5) and Sin10(0)= Sin10(0) ) report "***PASSED TEST: c01s03b01x00p12n01i00850" severity NOTE; assert ( Sin1(0) = sin1(5) and Sin2(0) = Sin2(5) and Sin4(0) = Sin4(5) and Sin5(0) = Sin5(5) and Sin6(0) = Sin6(5) and Sin7(0) = Sin7(5) and Sin8(0) = Sin8(5) and Sin9(0) = Sin9(5) and Sin10(0)= Sin10(0) ) report "***FAILED TEST: c01s03b01x00p12n01i00850 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index." severity ERROR; wait; END PROCESS TESTING; END c01s03b01x00p12n01i00850arch; configuration c01s03b01x00p12n01i00850cfg of c01s03b01x00p12n01i00850ent is for c01s03b01x00p12n01i00850arch for K for T5:test use configuration work.testbench; end for; for G(zero to three) for T1:test use configuration work.testbench; end for; end for; end for; end for; end;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc598.vhd
4
2080
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc598.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:40 1996 -- -- **************************** -- ENTITY c03s04b01x00p01n01i00598ent IS END c03s04b01x00p01n01i00598ent; ARCHITECTURE c03s04b01x00p01n01i00598arch OF c03s04b01x00p01n01i00598ent IS type time_cons_vector is array (15 downto 0) of time; type time_cons_vector_file is file of time_cons_vector; constant C19 : time_cons_vector := (others => 3 ns); BEGIN TESTING: PROCESS file filein : time_cons_vector_file open write_mode is "iofile.32"; BEGIN for i in 1 to 100 loop write(filein, C19); end loop; assert FALSE report "***PASSED TEST: c03s04b01x00p01n01i00598 - The output file will be verified by test s010246.vhd." severity NOTE; wait; END PROCESS TESTING; END c03s04b01x00p01n01i00598arch;
gpl-2.0
tgingold/ghdl
testsuite/gna/bug019/PoC/tb/common/my_config_ML605.vhdl
2
1809
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Package: Project specific configuration. -- -- Description: -- ------------------------------------ -- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl. -- -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library PoC; package my_config is -- Change these lines to setup configuration. constant MY_BOARD : string := "ML605"; -- ML605 - Xilinx Virtex 6 reference design board: XC6VLX240T constant MY_DEVICE : string := "None"; -- infer from MY_BOARD -- For internal use only constant MY_VERBOSE : boolean := FALSE; end package; package body my_config is end package body;
gpl-2.0
tgingold/ghdl
testsuite/synth/case02/tb_case01.vhdl
1
559
entity tb_case01 is end tb_case01; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_case01 is signal a : std_logic_vector (1 downto 0); signal o : std_logic_vector (1 downto 0); signal clk : std_logic; begin dut: entity work.case01 port map (a, clk, o); process procedure pulse is begin clk <= '0'; wait for 1 ns; clk <= '1'; wait for 1 ns; end pulse; begin a <= "00"; pulse; a <= "10"; pulse; assert o = "00" severity failure; wait; end process; end behav;
gpl-2.0
tgingold/ghdl
testsuite/gna/issue328/uncons1.vhdl
1
253
entity uncons1 is end; architecture behav of uncons1 is signal s1, s2 : bit; begin b : block -- port (p : bit_vector := (others => '1')); port (p : bit_vector := "01110"); port map (p(0) => s1, p(1) => s2); begin end block; end;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink.vhd
4
1292
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_19_sink.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- library qsim; use qsim.qsim_types.all; entity sink is generic ( name : string; time_unit : delay_length := ns; info_file_name : string := "info_file.dat" ); port ( in_arc : in arc_type; info_detail : in info_detail_type ); end sink;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc2136.vhd
4
2169
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2136.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b04x00p21n01i02136ent IS END c07s02b04x00p21n01i02136ent; ARCHITECTURE c07s02b04x00p21n01i02136arch OF c07s02b04x00p21n01i02136ent IS TYPE positive_v is array (integer range <>) of positive; SUBTYPE positive_5 is positive_v (1 to 5); SUBTYPE positive_4 is positive_v (1 to 4); BEGIN TESTING: PROCESS variable result : positive_5; variable l_operand : positive := 1 ; variable r_operand : positive_4 := ( 1 , 89 , 1 , 89 ); BEGIN -- -- The element is treated as an implicit single element array ! -- result := l_operand & r_operand; wait for 5 ns; assert NOT( result = ( 1 , 1 , 89 , 1 , 89 )) report "***PASSED TEST: c07s02b04x00p21n01i02136" severity NOTE; assert ( result = ( 1 , 1 , 89 , 1 , 89 )) report "***FAILED TEST: c07s02b04x00p21n01i02136 - Concatenation of element and POSITIVE array failed." severity ERROR; wait; END PROCESS TESTING; END c07s02b04x00p21n01i02136arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1061.vhd
4
1961
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1061.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s04b00x00p03n02i01061ent IS END c06s04b00x00p03n02i01061ent; ARCHITECTURE c06s04b00x00p03n02i01061arch OF c06s04b00x00p03n02i01061ent IS BEGIN TESTING: PROCESS type THREE is range 1 to 3; type ENUM1 is (EN1, EN2, EN3); type A11 is array (THREE) of BOOLEAN; type A32 is array (ENUM1, ENUM1) of A11; variable V1 : BOOLEAN; variable V32: A32 ; BEGIN V1 := V32(EN2)(2); -- ONE LESS -- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO -- INDEX POSITIONS IN TYPE DECLARATION assert FALSE report "***FAILED TEST: c06s04b00x00p03n02i01061 - The expresion should be the same type as the corresponding index." severity ERROR; wait; END PROCESS TESTING; END c06s04b00x00p03n02i01061arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc154.vhd
4
2361
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc154.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c04s03b02x02p16n01i00154pkg is procedure P1 (a : in integer; b: inout integer); function F1 (I1 : in integer) return real; function F2 (I2 : in real) return integer; end c04s03b02x02p16n01i00154pkg; package body c04s03b02x02p16n01i00154pkg is procedure P1 (a : in integer; b: inout integer) is begin b := a; end P1; function F1 (I1 : in integer) return real is begin return 10.0; end F1; function F2 (I2 : in real) return integer is begin return 10; end F2; end c04s03b02x02p16n01i00154pkg; use work.c04s03b02x02p16n01i00154pkg.all; ENTITY c04s03b02x02p16n01i00154ent IS END c04s03b02x02p16n01i00154ent; ARCHITECTURE c04s03b02x02p16n01i00154arch OF c04s03b02x02p16n01i00154ent IS BEGIN TESTING: PROCESS variable x : real := 1.0; BEGIN P1 (10, F1(b) => F2(x)); -- No_failure_here assert NOT(F2(x) = 10) report "***PASSED TEST: c04s03b02x02p16n01i00154" severity NOTE; assert (F2(x) = 10) report "***FAILED TEST: c04s03b02x02p16n01i00154 - Types of the actuals match those of the formals test failed.." severity ERROR; wait; END PROCESS TESTING; END c04s03b02x02p16n01i00154arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1889.vhd
4
1945
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1889.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s01b00x00p08n01i01889ent IS END c07s01b00x00p08n01i01889ent; ARCHITECTURE c07s01b00x00p08n01i01889arch OF c07s01b00x00p08n01i01889ent IS type small_int is range 0 to 7; type cmd_bus is array (small_int range <>) of small_int; signal ibus : cmd_bus(small_int); signal s_int : small_int; BEGIN blk : block (s_int = 0) begin end block blk; TESTING : PROCESS BEGIN s_int <= ibus'right(small_int'(blk)) after 5 ns; -- architecture body name illegal here wait for 5 ns; assert FALSE report "***FAILED TEST: c07s01b00x00p08n01i01889 - Block labels are not permitted as primaries in a qualified expression." severity ERROR; wait; END PROCESS TESTING; END c07s01b00x00p08n01i01889arch;
gpl-2.0
tgingold/ghdl
testsuite/synth/dff02/dff09.vhdl
1
473
library ieee; use ieee.std_logic_1164.all; entity dff09 is port (q : out std_logic_vector(3 downto 0); d : std_logic_vector(3 downto 0); clk : std_logic; rst : std_logic); end dff09; architecture behav of dff09 is begin process (clk, rst) is begin if rst = '1' then for i in q'range loop q(i) <= '0'; end loop; -- q <= x"0"; elsif rising_edge (clk) then q <= d; end if; end process; end behav;
gpl-2.0
tgingold/ghdl
testsuite/gna/bug019/PoC/src/common/utils.vhdl
3
29275
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Package: Common functions and types -- -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Description: -- ------------------------------------ -- For detailed documentation see below. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library PoC; use PoC.my_config.all; package utils is -- PoC settings -- ========================================================================== constant POC_VERBOSE : BOOLEAN := MY_VERBOSE; -- Environment -- ========================================================================== -- Distinguishes simulation from synthesis constant SIMULATION : BOOLEAN; -- deferred constant declaration -- Type declarations -- ========================================================================== --+ Vectors of primitive standard types +++++++++++++++++++++++++++++++++++++ type T_BOOLVEC is array(NATURAL range <>) of BOOLEAN; type T_INTVEC is array(NATURAL range <>) of INTEGER; type T_NATVEC is array(NATURAL range <>) of NATURAL; type T_POSVEC is array(NATURAL range <>) of POSITIVE; type T_REALVEC is array(NATURAL range <>) of REAL; --+ Integer subranges sometimes useful for speeding up simulation ++++++++++ subtype T_INT_8 is INTEGER range -128 to 127; subtype T_INT_16 is INTEGER range -32768 to 32767; subtype T_UINT_8 is INTEGER range 0 to 255; subtype T_UINT_16 is INTEGER range 0 to 65535; --+ Enums ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Intellectual Property (IP) type type T_IPSTYLE is (IPSTYLE_HARD, IPSTYLE_SOFT); -- Bit Order type T_BIT_ORDER is (LSB_FIRST, MSB_FIRST); -- Byte Order (Endian) type T_BYTE_ORDER is (LITTLE_ENDIAN, BIG_ENDIAN); -- rounding style type T_ROUNDING_STYLE is (ROUND_TO_NEAREST, ROUND_TO_ZERO, ROUND_TO_INF, ROUND_UP, ROUND_DOWN); type T_BCD is array(3 downto 0) of std_logic; type T_BCD_VECTOR is array(NATURAL range <>) of T_BCD; constant C_BCD_MINUS : T_BCD := "1010"; constant C_BCD_OFF : T_BCD := "1011"; -- Function declarations -- ========================================================================== --+ Division ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Calculates: ceil(a / b) function div_ceil(a : NATURAL; b : POSITIVE) return NATURAL; --+ Power +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- is input a power of 2? function is_pow2(int : NATURAL) return BOOLEAN; -- round to next power of 2 function ceil_pow2(int : NATURAL) return POSITIVE; -- round to previous power of 2 function floor_pow2(int : NATURAL) return NATURAL; --+ Logarithm ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Calculates: ceil(ld(arg)) function log2ceil(arg : positive) return natural; -- Calculates: max(1, ceil(ld(arg))) function log2ceilnz(arg : positive) return positive; -- Calculates: ceil(lg(arg)) function log10ceil(arg : POSITIVE) return NATURAL; -- Calculates: max(1, ceil(lg(arg))) function log10ceilnz(arg : POSITIVE) return POSITIVE; --+ if-then-else (ite) +++++++++++++++++++++++++++++++++++++++++++++++++++++ function ite(cond : BOOLEAN; value1 : BOOLEAN; value2 : BOOLEAN) return BOOLEAN; function ite(cond : BOOLEAN; value1 : INTEGER; value2 : INTEGER) return INTEGER; function ite(cond : BOOLEAN; value1 : REAL; value2 : REAL) return REAL; function ite(cond : BOOLEAN; value1 : STD_LOGIC; value2 : STD_LOGIC) return STD_LOGIC; function ite(cond : BOOLEAN; value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function ite(cond : BOOLEAN; value1 : BIT_VECTOR; value2 : BIT_VECTOR) return BIT_VECTOR; function ite(cond : BOOLEAN; value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED; function ite(cond : BOOLEAN; value1 : CHARACTER; value2 : CHARACTER) return CHARACTER; function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING; --+ Max / Min / Sum ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ function imin(arg1 : integer; arg2 : integer) return integer; -- Calculates: min(arg1, arg2) for integers function rmin(arg1 : real; arg2 : real) return real; -- Calculates: min(arg1, arg2) for reals function imin(vec : T_INTVEC) return INTEGER; -- Calculates: min(vec) for a integer vector function imin(vec : T_NATVEC) return NATURAL; -- Calculates: min(vec) for a natural vector function imin(vec : T_POSVEC) return POSITIVE; -- Calculates: min(vec) for a positive vector function rmin(vec : T_REALVEC) return real; -- Calculates: min(vec) of real vector function imax(arg1 : integer; arg2 : integer) return integer; -- Calculates: max(arg1, arg2) for integers function rmax(arg1 : real; arg2 : real) return real; -- Calculates: max(arg1, arg2) for reals function imax(vec : T_INTVEC) return INTEGER; -- Calculates: max(vec) for a integer vector function imax(vec : T_NATVEC) return NATURAL; -- Calculates: max(vec) for a natural vector function imax(vec : T_POSVEC) return POSITIVE; -- Calculates: max(vec) for a positive vector function rmax(vec : T_REALVEC) return real; -- Calculates: max(vec) of real vector function isum(vec : T_NATVEC) return NATURAL; -- Calculates: sum(vec) for a natural vector function isum(vec : T_POSVEC) return POSITIVE; -- Calculates: sum(vec) for a positive vector function isum(vec : T_INTVEC) return integer; -- Calculates: sum(vec) of integer vector function rsum(vec : T_REALVEC) return real; -- Calculates: sum(vec) of real vector --+ Conversions ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- to integer: to_int function to_int(bool : BOOLEAN; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER; function to_int(sl : STD_LOGIC; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER; -- to std_logic: to_sl function to_sl(Value : BOOLEAN) return STD_LOGIC; function to_sl(Value : CHARACTER) return STD_LOGIC; -- to std_logic_vector: to_slv function to_slv(Value : NATURAL; Size : POSITIVE) return STD_LOGIC_VECTOR; -- short for std_logic_vector(to_unsigned(Value, Size)) -- TODO: comment function to_index(slv : UNSIGNED; max : NATURAL := 0) return INTEGER; function to_index(slv : STD_LOGIC_VECTOR; max : NATURAL := 0) return INTEGER; -- is_* function is_sl(c : CHARACTER) return BOOLEAN; --+ Basic Vector Utilities +++++++++++++++++++++++++++++++++++++++++++++++++ -- Aggregate functions function slv_or (vec : STD_LOGIC_VECTOR) return STD_LOGIC; function slv_nor (vec : STD_LOGIC_VECTOR) return STD_LOGIC; function slv_and (vec : STD_LOGIC_VECTOR) return STD_LOGIC; function slv_nand(vec : STD_LOGIC_VECTOR) return STD_LOGIC; function slv_xor (vec : std_logic_vector) return std_logic; -- NO slv_xnor! This operation would not be well-defined as -- not xor(vec) /= vec_{n-1} xnor ... xnor vec_1 xnor vec_0 iff n is odd. -- Reverses the elements of the passed Vector. -- -- @synthesis supported -- function reverse(vec : std_logic_vector) return std_logic_vector; function reverse(vec : bit_vector) return bit_vector; function reverse(vec : unsigned) return unsigned; -- Resizes the vector to the specified length. The adjustment is make on -- on the 'high end of the vector. The 'low index remains as in the argument. -- If the result vector is larger, the extension uses the provided fill value -- (default: '0'). -- Use the resize functions of the numeric_std package for value-preserving -- resizes of the signed and unsigned data types. -- -- @synthesis supported -- function resize(vec : bit_vector; length : natural; fill : bit := '0') return bit_vector; function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector; -- Shift the index range of a vector by the specified offset. function move(vec : std_logic_vector; ofs : integer) return std_logic_vector; -- Shift the index range of a vector making vec'low = 0. function movez(vec : std_logic_vector) return std_logic_vector; function ascend(vec : std_logic_vector) return std_logic_vector; function descend(vec : std_logic_vector) return std_logic_vector; -- Least-Significant Set Bit (lssb): -- Computes a vector of the same length as the argument with -- at most one bit set at the rightmost '1' found in arg. -- -- @synthesis supported -- function lssb(arg : std_logic_vector) return std_logic_vector; function lssb(arg : bit_vector) return bit_vector; -- Returns the index of the least-significant set bit. -- -- @synthesis supported -- function lssb_idx(arg : std_logic_vector) return integer; function lssb_idx(arg : bit_vector) return integer; -- Most-Significant Set Bit (mssb): computes a vector of the same length -- with at most one bit set at the leftmost '1' found in arg. function mssb(arg : std_logic_vector) return std_logic_vector; function mssb(arg : bit_vector) return bit_vector; function mssb_idx(arg : std_logic_vector) return integer; function mssb_idx(arg : bit_vector) return integer; -- Swap sub vectors in vector (endian reversal) function swap(slv : STD_LOGIC_VECTOR; Size : POSITIVE) return STD_LOGIC_VECTOR; -- generate bit masks function genmask_high(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR; function genmask_low(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR; --+ Encodings ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- One-Hot-Code to Binary-Code. function onehot2bin(onehot : std_logic_vector) return unsigned; -- Converts Gray-Code into Binary-Code. -- -- @synthesis supported -- function gray2bin (gray_val : std_logic_vector) return std_logic_vector; -- Binary-Code to One-Hot-Code function bin2onehot(value : std_logic_vector) return std_logic_vector; -- Binary-Code to Gray-Code function bin2gray(value : std_logic_vector) return std_logic_vector; end package; package body utils is -- Environment -- ========================================================================== function is_simulation return boolean is variable ret : boolean; begin ret := false; --synthesis translate_off if Is_X('X') then ret := true; end if; --synthesis translate_on return ret; end function; -- deferred constant assignment constant SIMULATION : BOOLEAN := is_simulation; -- Divisions: div_* function div_ceil(a : NATURAL; b : POSITIVE) return NATURAL is -- calculates: ceil(a / b) begin return (a + (b - 1)) / b; end function; -- Power functions: *_pow2 -- ========================================================================== -- is input a power of 2? function is_pow2(int : NATURAL) return BOOLEAN is begin return ceil_pow2(int) = int; end function; -- round to next power of 2 function ceil_pow2(int : NATURAL) return POSITIVE is begin return 2 ** log2ceil(int); end function; -- round to previous power of 2 function floor_pow2(int : NATURAL) return NATURAL is variable temp : UNSIGNED(30 downto 0); begin temp := to_unsigned(int, 31); for i in temp'range loop if (temp(i) = '1') then return 2 ** i; end if; end loop; return 0; end function; -- Logarithms: log*ceil* -- ========================================================================== function log2ceil(arg : positive) return natural is variable tmp : positive; variable log : natural; begin if arg = 1 then return 0; end if; tmp := 1; log := 0; while arg > tmp loop tmp := tmp * 2; log := log + 1; end loop; return log; end function; function log2ceilnz(arg : positive) return positive is begin return imax(1, log2ceil(arg)); end function; function log10ceil(arg : positive) return natural is variable tmp : positive; variable log : natural; begin if arg = 1 then return 0; end if; tmp := 1; log := 0; while arg > tmp loop tmp := tmp * 10; log := log + 1; end loop; return log; end function; function log10ceilnz(arg : positive) return positive is begin return imax(1, log10ceil(arg)); end function; -- if-then-else (ite) -- ========================================================================== function ite(cond : BOOLEAN; value1 : BOOLEAN; value2 : BOOLEAN) return BOOLEAN is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : INTEGER; value2 : INTEGER) return INTEGER is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : REAL; value2 : REAL) return REAL is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : STD_LOGIC; value2 : STD_LOGIC) return STD_LOGIC is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : BIT_VECTOR; value2 : BIT_VECTOR) return BIT_VECTOR is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : CHARACTER; value2 : CHARACTER) return CHARACTER is begin if cond then return value1; else return value2; end if; end function; function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is begin if cond then return value1; else return value2; end if; end function; -- *min / *max / *sum -- ========================================================================== function imin(arg1 : integer; arg2 : integer) return integer is begin if arg1 < arg2 then return arg1; end if; return arg2; end function; function rmin(arg1 : real; arg2 : real) return real is begin if arg1 < arg2 then return arg1; end if; return arg2; end function; function imin(vec : T_INTVEC) return INTEGER is variable Result : INTEGER; begin Result := INTEGER'high; for i in vec'range loop if (vec(I) < Result) then Result := vec(I); end if; end loop; return Result; end function; function imin(vec : T_NATVEC) return NATURAL is variable Result : NATURAL; begin Result := NATURAL'high; for i in vec'range loop if (vec(I) < Result) then Result := vec(I); end if; end loop; return Result; end function; function imin(vec : T_POSVEC) return POSITIVE is variable Result : POSITIVE; begin Result := POSITIVE'high; for i in vec'range loop if (vec(I) < Result) then Result := vec(I); end if; end loop; return Result; end function; function rmin(vec : T_REALVEC) return REAL is variable Result : REAL; begin Result := REAL'high; for i in vec'range loop if vec(i) < Result then Result := vec(i); end if; end loop; return Result; end function; function imax(arg1 : integer; arg2 : integer) return integer is begin if arg1 > arg2 then return arg1; end if; return arg2; end function; function rmax(arg1 : real; arg2 : real) return real is begin if arg1 > arg2 then return arg1; end if; return arg2; end function; function imax(vec : T_INTVEC) return INTEGER is variable Result : INTEGER; begin Result := INTEGER'low; for i in vec'range loop if (vec(I) > Result) then Result := vec(I); end if; end loop; return Result; end function; function imax(vec : T_NATVEC) return NATURAL is variable Result : NATURAL; begin Result := NATURAL'low; for i in vec'range loop if (vec(I) > Result) then Result := vec(I); end if; end loop; return Result; end function; function imax(vec : T_POSVEC) return POSITIVE is variable Result : POSITIVE; begin Result := POSITIVE'low; for i in vec'range loop if (vec(I) > Result) then Result := vec(I); end if; end loop; return Result; end function; function rmax(vec : T_REALVEC) return REAL is variable Result : REAL; begin Result := REAL'low; for i in vec'range loop if vec(i) > Result then Result := vec(i); end if; end loop; return Result; end function; function isum(vec : T_INTVEC) return INTEGER is variable Result : INTEGER; begin Result := 0; for i in vec'range loop Result := Result + vec(i); end loop; return Result; end function; function isum(vec : T_NATVEC) return NATURAL is variable Result : NATURAL; begin Result := 0; for i in vec'range loop Result := Result + vec(I); end loop; return Result; end function; function isum(vec : T_POSVEC) return POSITIVE is variable Result : POSITIVE; begin Result := 0; for i in vec'range loop Result := Result + vec(I); end loop; return Result; end function; function rsum(vec : T_REALVEC) return REAL is variable Result : REAL; begin Result := 0.0; for i in vec'range loop Result := Result + vec(i); end loop; return Result; end function; -- Vector aggregate functions: slv_* -- ========================================================================== function slv_or(vec : STD_LOGIC_VECTOR) return STD_LOGIC is variable Result : STD_LOGIC; begin Result := '0'; for i in vec'range loop Result := Result or vec(i); end loop; return Result; end function; function slv_nor(vec : STD_LOGIC_VECTOR) return STD_LOGIC is begin return not slv_or(vec); end function; function slv_and(vec : STD_LOGIC_VECTOR) return STD_LOGIC is variable Result : STD_LOGIC; begin Result := '1'; for i in vec'range loop Result := Result and vec(i); end loop; return Result; end function; function slv_nand(vec : STD_LOGIC_VECTOR) return STD_LOGIC is begin return not slv_and(vec); end function; function slv_xor(vec : std_logic_vector) return std_logic is variable res : std_logic; begin res := '0'; for i in vec'range loop res := res xor vec(i); end loop; return res; end slv_xor; -- Convert to integer: to_int function to_int(bool : BOOLEAN; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER is begin return ite(bool, one, zero); end function; function to_int(sl : STD_LOGIC; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER is begin if (sl = '1') then return one; end if; return zero; end function; -- Convert to bit: to_sl -- ========================================================================== function to_sl(Value : BOOLEAN) return STD_LOGIC is begin return ite(Value, '1', '0'); end function; function to_sl(Value : CHARACTER) return STD_LOGIC is begin case Value is when 'U' => return 'U'; when '0' => return '0'; when '1' => return '1'; when 'Z' => return 'Z'; when 'W' => return 'W'; when 'L' => return 'L'; when 'H' => return 'H'; when '-' => return '-'; when OTHERS => return 'X'; end case; end function; -- Convert to vector: to_slv -- ========================================================================== -- short for std_logic_vector(to_unsigned(Value, Size)) -- the return value is guaranteed to have the range (Size-1 downto 0) function to_slv(Value : NATURAL; Size : POSITIVE) return STD_LOGIC_VECTOR is constant res : std_logic_vector(Size-1 downto 0) := std_logic_vector(to_unsigned(Value, Size)); begin return res; end function; function to_index(slv : UNSIGNED; max : NATURAL := 0) return INTEGER is variable res : integer; begin if (slv'length = 0) then return 0; end if; res := to_integer(slv); if SIMULATION and max > 0 then res := imin(res, max); end if; return res; end function; function to_index(slv : STD_LOGIC_VECTOR; max : NATURAL := 0) return INTEGER is begin return to_index(unsigned(slv), max); end function; -- is_* -- ========================================================================== function is_sl(c : CHARACTER) return BOOLEAN is begin case c is when 'U'|'X'|'0'|'1'|'Z'|'W'|'L'|'H'|'-' => return true; when OTHERS => return false; end case; end function; -- Reverse vector elements function reverse(vec : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(vec'range); begin for i in vec'low to vec'high loop res(vec'low + (vec'high-i)) := vec(i); end loop; return res; end function; function reverse(vec : bit_vector) return bit_vector is variable res : bit_vector(vec'range); begin res := to_bitvector(reverse(to_stdlogicvector(vec))); return res; end reverse; function reverse(vec : unsigned) return unsigned is begin return unsigned(reverse(std_logic_vector(vec))); end function; -- Swap sub vectors in vector -- ========================================================================== function swap(slv : STD_LOGIC_VECTOR; Size : POSITIVE) return STD_LOGIC_VECTOR IS CONSTANT SegmentCount : NATURAL := slv'length / Size; variable FromH : NATURAL; variable FromL : NATURAL; variable ToH : NATURAL; variable ToL : NATURAL; variable Result : STD_LOGIC_VECTOR(slv'length - 1 DOWNTO 0); begin for i in 0 TO SegmentCount - 1 loop FromH := ((I + 1) * Size) - 1; FromL := I * Size; ToH := ((SegmentCount - I) * Size) - 1; ToL := (SegmentCount - I - 1) * Size; Result(ToH DOWNTO ToL) := slv(FromH DOWNTO FromL); end loop; return Result; end function; -- generate bit masks -- ========================================================================== function genmask_high(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR IS begin if (Bits = 0) then return (MaskLength - 1 DOWNTO 0 => '0'); else return (MaskLength - 1 DOWNTO MaskLength - Bits + 1 => '1') & (MaskLength - Bits DOWNTO 0 => '0'); end if; end function; function genmask_low(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR is begin if (Bits = 0) then return (MaskLength - 1 DOWNTO 0 => '0'); else return (MaskLength - 1 DOWNTO Bits => '0') & (Bits - 1 DOWNTO 0 => '1'); end if; end function; -- binary encoding conversion functions -- ========================================================================== -- One-Hot-Code to Binary-Code function onehot2bin(onehot : std_logic_vector) return unsigned is variable res : unsigned(log2ceilnz(onehot'high+1)-1 downto 0); variable chk : natural; begin res := (others => '0'); chk := 0; for i in onehot'range loop if onehot(i) = '1' then res := res or to_unsigned(i, res'length); chk := chk + 1; end if; end loop; if SIMULATION and chk /= 1 then report "Broken 1-Hot-Code with "&integer'image(chk)&" bits set." severity error; end if; return res; end onehot2bin; -- Gray-Code to Binary-Code function gray2bin(gray_val : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(gray_val'range); begin -- gray2bin res(res'left) := gray_val(gray_val'left); for i in res'left-1 downto res'right loop res(i) := res(i+1) xor gray_val(i); end loop; return res; end gray2bin; -- Binary-Code to One-Hot-Code function bin2onehot(value : std_logic_vector) return std_logic_vector is variable result : std_logic_vector(2**value'length - 1 downto 0); begin result := (others => '0'); result(to_index(value)) := '1'; return result; end function; -- Binary-Code to Gray-Code function bin2gray(value : std_logic_vector) return std_logic_vector is variable result : std_logic_vector(value'range); begin result(result'left) := value(value'left); for i in (result'left - 1) downto result'right loop result(i) := value(i) xor value(i + 1); end loop; return result; end function; -- bit searching / bit indices -- ========================================================================== -- Least-Significant Set Bit (lssb): computes a vector of the same length with at most one bit set at the rightmost '1' found in arg. function lssb(arg : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(arg'range); begin res := arg and std_logic_vector(unsigned(not arg)+1); return res; end function; function lssb(arg : bit_vector) return bit_vector is variable res : bit_vector(arg'range); begin res := to_bitvector(lssb(to_stdlogicvector(arg))); return res; end lssb; -- Most-Significant Set Bit (mssb): computes a vector of the same length with at most one bit set at the leftmost '1' found in arg. function mssb(arg : std_logic_vector) return std_logic_vector is begin return reverse(lssb(reverse(arg))); end function; function mssb(arg : bit_vector) return bit_vector is begin return reverse(lssb(reverse(arg))); end mssb; -- Index of lssb function lssb_idx(arg : std_logic_vector) return integer is begin return to_integer(onehot2bin(lssb(arg))); end function; function lssb_idx(arg : bit_vector) return integer is variable slv : std_logic_vector(arg'range); begin slv := to_stdlogicvector(arg); return lssb_idx(slv); end lssb_idx; -- Index of mssb function mssb_idx(arg : std_logic_vector) return integer is begin return to_integer(onehot2bin(mssb(arg))); end function; function mssb_idx(arg : bit_vector) return integer is variable slv : std_logic_vector(arg'range); begin slv := to_stdlogicvector(arg); return mssb_idx(slv); end mssb_idx; function resize(vec : bit_vector; length : natural; fill : bit := '0') return bit_vector is constant high2b : natural := vec'low+length-1; constant highcp : natural := imin(vec'high, high2b); variable res_up : bit_vector(vec'low to high2b); variable res_dn : bit_vector(high2b downto vec'low); begin if vec'ascending then res_up := (others => fill); res_up(vec'low to highcp) := vec(vec'low to highcp); return res_up; else res_dn := (others => fill); res_dn(highcp downto vec'low) := vec(highcp downto vec'low); return res_dn; end if; end resize; function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector is constant high2b : natural := vec'low+length-1; constant highcp : natural := imin(vec'high, high2b); variable res_up : std_logic_vector(vec'low to high2b); variable res_dn : std_logic_vector(high2b downto vec'low); begin if vec'ascending then res_up := (others => fill); res_up(vec'low to highcp) := vec(vec'low to highcp); return res_up; else res_dn := (others => fill); res_dn(highcp downto vec'low) := vec(highcp downto vec'low); return res_dn; end if; end resize; -- Move vector boundaries -- ========================================================================== function move(vec : std_logic_vector; ofs : integer) return std_logic_vector is variable res_up : std_logic_vector(vec'low +ofs to vec'high+ofs); variable res_dn : std_logic_vector(vec'high+ofs downto vec'low +ofs); begin if vec'ascending then res_up := vec; return res_up; else res_dn := vec; return res_dn; end if; end move; function movez(vec : std_logic_vector) return std_logic_vector is begin return move(vec, -vec'low); end movez; function ascend(vec : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(vec'low to vec'high); begin res := vec; return res; end ascend; function descend(vec : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(vec'high downto vec'low); begin res := vec; return res; end descend; end package body;
gpl-2.0
tgingold/ghdl
testsuite/gna/issue50/idct.d/sub_503.vhd
2
800
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity sub_503 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(31 downto 0) ); end sub_503; architecture augh of sub_503 is signal carry_inA : std_logic_vector(33 downto 0); signal carry_inB : std_logic_vector(33 downto 0); signal carry_res : std_logic_vector(33 downto 0); begin -- To handle the CI input, the operation is '0' - CI -- If CI is not present, the operation is '0' - '0' carry_inA <= '0' & in_a & '0'; carry_inB <= '0' & in_b & '0'; -- Compute the result carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); -- Set the outputs result <= carry_res(32 downto 1); end architecture;
gpl-2.0
tgingold/ghdl
testsuite/synth/synth76/dff00.vhdl
2
606
library ieee; use ieee.std_logic_1164.all; entity dff01 is port (q : out std_logic_vector (3 downto 0); d : std_logic_vector (3 downto 0); en : std_logic; rst : std_logic; clk : std_logic); end dff01; architecture behav of dff01 is signal t : std_logic_vector (7 downto 0); signal a : std_logic_vector (3 downto 0); begin a <= d xor b"0101"; process (clk) is begin if rst = '1' then q <= x"0"; elsif rising_edge (clk) then if en = '1' then q <= d; t (7 downto 4) <= a; end if; end if; end process; end behav;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/character_array_read.vhdl
3
2080
-- Copyright (C) Clifton Labs. All rights reserved. -- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE -- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT -- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. CLIFTON LABS SHALL NOT BE -- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT -- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. -- By using or copying this Software, Licensee agrees to abide by the -- intellectual property laws, and all other applicable laws of the U.S., -- and the terms of this license. -- You may modify, distribute, and use the software contained in this -- package under the terms of the GNU General Public License as published -- by the Free Software Foundation; version 2 of the License. -- You should have received a copy of the GNU General Public License along -- with this software; if not, write to the Free Software Foundation, Inc., -- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA entity character_array_read is end character_array_read; architecture test0 of character_array_read is type character_array is array (natural range <>) of character; type character_array_file is file of character_array; signal k : integer := 0; begin doit: process file filein : character_array_file open read_mode is "character_array.file"; variable v : character_array(0 to 3); variable len : natural; begin assert(endfile(filein) = false) report "End of file reached before expected." severity failure; read(filein,v,len); assert(len = 4) report "FAILED TEST: character_array_read. Wrong length." severity failure; assert (v = ('1','a','$','+')) report "FAILED TEST: character_array_read. Incorrect characters read." severity failure; assert(endfile(filein)) severity failure; report "PASSED TEST: character_array_read." severity note; wait; end process; end test0;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_02.vhd
4
1606
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA entity inline_02 is end entity inline_02; ---------------------------------------------------------------- architecture test of inline_02 is signal sel : integer range 0 to 1 := 0; signal input_0 : integer := 0; signal input_1 : integer := 10; signal result : integer; begin process_1_b : process (sel, input_0, input_1) is begin -- code from book: if sel = 0 then result <= input_0; -- executed if sel = 0 else result <= input_1; -- executed if sel /= 0 end if; -- end of code from book end process process_1_b; stimulus : process is begin sel <= 1 after 40 ns; input_0 <= 1 after 10 ns, 2 after 30 ns, 3 after 50 ns; input_1 <= 11 after 15 ns, 12 after 35 ns, 13 after 55 ns; wait; end process stimulus; end architecture test;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc774.vhd
4
2254
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc774.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c01s01b01x02p09n01i00774ent_a IS port ( c1 : buffer integer ; c2 : in integer ); END c01s01b01x02p09n01i00774ent_a; ARCHITECTURE c01s01b01x02p09n01i00774arch_a OF c01s01b01x02p09n01i00774ent_a IS BEGIN c1 <= c2; END c01s01b01x02p09n01i00774arch_a; ENTITY c01s01b01x02p09n01i00774ent IS port ( p1 : in integer ; p2 : in integer ); END c01s01b01x02p09n01i00774ent; ARCHITECTURE c01s01b01x02p09n01i00774arch OF c01s01b01x02p09n01i00774ent IS component c01s01b01x02p09n01i00774ent_b port ( c1 : buffer integer ; c2 : in integer ); end component; for L : c01s01b01x02p09n01i00774ent_b use entity work.c01s01b01x02p09n01i00774ent_a(c01s01b01x02p09n01i00774arch_a); BEGIN L : c01s01b01x02p09n01i00774ent_b port map (p1, p2); --Failure here TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c01s01b01x02p09n01i00774 - An actual of mode in cannot be associated with a formal port of mode buffer." severity ERROR; wait; END PROCESS TESTING; END c01s01b01x02p09n01i00774arch;
gpl-2.0
tgingold/ghdl
testsuite/gna/bug042/centerconfig_generics_works.vhdl
2
2362
library ieee; use ieee.std_logic_1164.all; entity CenterConfig is generic ( -- Width of S_AXI data bus C_S_AXI_DATA_WIDTH : integer := 32; -- Width of S_AXI address bus C_S_AXI_ADDR_WIDTH : integer := 4 ); port ( center_height: out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); center_width: out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0) ); end entity CenterConfig; architecture foo of centerconfig is begin end architecture; library ieee; use ieee.std_logic_1164.all; entity instance is generic ( CENTERHEIGHT: integer := 32; -- 16; CENTERWIDTH: integer := 32; -- 16 C_S_AXI_DATA_WIDTH: integer := 32; C_S_AXI_ADDR_WIDTH: integer := 4 ); end entity; architecture fum of instance is -- constant CENTERHEIGHT: integer := 32; -- 16; -- constant CENTERWIDTH: integer := 32; -- 16; -- constant C_S_AXI_DATA_WIDTH: integer := 32; -- constant C_S_AXI_ADDR_WIDTH: integer := 4; component centerconfig is generic ( C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 4 ); port ( center_height: out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); center_width: out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0) ); end component; signal std_center_height: std_logic_vector (CENTERHEIGHT - 1 downto 0); signal std_center_width: std_logic_vector (CENTERWIDTH - 1 downto 0); begin Config: CenterConfig generic map ( C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ) port map ( --center_height(std_center_height'range) => std_center_height, center_height(std_center_height'LEFT downto std_center_height'RIGHT) => std_center_height, -- center_height(C_S_AXI_DATA_WIDTH-1 downto std_center_height'length) => open, -- not working, not elegant -- center_width(std_center_width'range) => std_center_width center_width(std_center_width'LEFT downto std_center_width'RIGHT) => std_center_width ); end architecture;
gpl-2.0
tgingold/ghdl
libraries/openieee/v93/std_logic_1164-body.vhdl
2
21289
-- This -*- vhdl -*- file was generated from std_logic_1164-body.proto -- This is an implementation of -*- vhdl -*- ieee.std_logic_1164 based only -- on the specifications. This file is part of GHDL. -- Copyright (C) 2015 Tristan Gingold -- -- GHDL is free software; you can redistribute it and/or modify it under -- the terms of the GNU General Public License as published by the Free -- Software Foundation; either version 2, or (at your option) any later -- version. -- -- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY -- WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- -- You should have received a copy of the GNU General Public License -- along with GCC; see the file COPYING2. If not see -- <http://www.gnu.org/licenses/>. -- This is a template file. To avoid errors and duplication, the python -- script build.py generate most of the bodies. package body std_logic_1164 is type table_1d is array (std_ulogic) of std_ulogic; type table_2d is array (std_ulogic, std_ulogic) of std_ulogic; constant resolution : table_2d := -- UX01ZWLH- ("UUUUUUUUU", -- U "UXXXXXXXX", -- X "UX0X0000X", -- 0 "UXX11111X", -- 1 "UX01ZWLHX", -- Z "UX01WWWWX", -- W "UX01LWLWX", -- L "UX01HWWHX", -- H "UXXXXXXXX" -- - ); function resolved (s : std_ulogic_vector) return std_ulogic is variable res : std_ulogic := 'Z'; begin for I in s'range loop res := resolution (res, s (I)); end loop; return res; end resolved; constant and_table : table_2d := -- UX01ZWLH- ("UU0UUU0UU", -- U "UX0XXX0XX", -- X "000000000", -- 0 "UX01XX01X", -- 1 "UX0XXX0XX", -- Z "UX0XXX0XX", -- W "000000000", -- L "UX01XX01X", -- H "UX0XXX0XX" -- - ); constant nand_table : table_2d := -- UX01ZWLH- ("UU1UUU1UU", -- U "UX1XXX1XX", -- X "111111111", -- 0 "UX10XX10X", -- 1 "UX1XXX1XX", -- Z "UX1XXX1XX", -- W "111111111", -- L "UX10XX10X", -- H "UX1XXX1XX" -- - ); constant or_table : table_2d := -- UX01ZWLH- ("UUU1UUU1U", -- U "UXX1XXX1X", -- X "UX01XX01X", -- 0 "111111111", -- 1 "UXX1XXX1X", -- Z "UXX1XXX1X", -- W "UX01XX01X", -- L "111111111", -- H "UXX1XXX1X" -- - ); constant nor_table : table_2d := -- UX01ZWLH- ("UUU0UUU0U", -- U "UXX0XXX0X", -- X "UX10XX10X", -- 0 "000000000", -- 1 "UXX0XXX0X", -- Z "UXX0XXX0X", -- W "UX10XX10X", -- L "000000000", -- H "UXX0XXX0X" -- - ); constant xor_table : table_2d := -- UX01ZWLH- ("UUUUUUUUU", -- U "UXXXXXXXX", -- X "UX01XX01X", -- 0 "UX10XX10X", -- 1 "UXXXXXXXX", -- Z "UXXXXXXXX", -- W "UX01XX01X", -- L "UX10XX10X", -- H "UXXXXXXXX" -- - ); constant xnor_table : table_2d := -- UX01ZWLH- ("UUUUUUUUU", -- U "UXXXXXXXX", -- X "UX10XX10X", -- 0 "UX01XX01X", -- 1 "UXXXXXXXX", -- Z "UXXXXXXXX", -- W "UX10XX10X", -- L "UX01XX01X", -- H "UXXXXXXXX" -- - ); constant not_table : table_1d := -- UX01ZWLH- "UX10XX10X"; function "and" (l : std_ulogic; r : std_ulogic) return UX01 is begin return and_table (l, r); end "and"; function "nand" (l : std_ulogic; r : std_ulogic) return UX01 is begin return nand_table (l, r); end "nand"; function "or" (l : std_ulogic; r : std_ulogic) return UX01 is begin return or_table (l, r); end "or"; function "nor" (l : std_ulogic; r : std_ulogic) return UX01 is begin return nor_table (l, r); end "nor"; function "xor" (l : std_ulogic; r : std_ulogic) return UX01 is begin return xor_table (l, r); end "xor"; function "xnor" (l : std_ulogic; r : std_ulogic) return UX01 is begin return xnor_table (l, r); end "xnor"; function "not" (l : std_ulogic) return UX01 is begin return not_table (l); end "not"; function "and" (l, r : std_ulogic_vector) return std_ulogic_vector is subtype res_type is std_ulogic_vector (1 to l'length); alias la : res_type is l; alias ra : std_ulogic_vector (1 to r'length) is r; variable res : res_type; begin if la'length /= ra'length then assert false report "arguments of overloaded 'and' operator are not of the same length" severity failure; else for I in res_type'range loop res (I) := and_table (la (I), ra (I)); end loop; end if; return res; end "and"; function "nand" (l, r : std_ulogic_vector) return std_ulogic_vector is subtype res_type is std_ulogic_vector (1 to l'length); alias la : res_type is l; alias ra : std_ulogic_vector (1 to r'length) is r; variable res : res_type; begin if la'length /= ra'length then assert false report "arguments of overloaded 'nand' operator are not of the same length" severity failure; else for I in res_type'range loop res (I) := nand_table (la (I), ra (I)); end loop; end if; return res; end "nand"; function "or" (l, r : std_ulogic_vector) return std_ulogic_vector is subtype res_type is std_ulogic_vector (1 to l'length); alias la : res_type is l; alias ra : std_ulogic_vector (1 to r'length) is r; variable res : res_type; begin if la'length /= ra'length then assert false report "arguments of overloaded 'or' operator are not of the same length" severity failure; else for I in res_type'range loop res (I) := or_table (la (I), ra (I)); end loop; end if; return res; end "or"; function "nor" (l, r : std_ulogic_vector) return std_ulogic_vector is subtype res_type is std_ulogic_vector (1 to l'length); alias la : res_type is l; alias ra : std_ulogic_vector (1 to r'length) is r; variable res : res_type; begin if la'length /= ra'length then assert false report "arguments of overloaded 'nor' operator are not of the same length" severity failure; else for I in res_type'range loop res (I) := nor_table (la (I), ra (I)); end loop; end if; return res; end "nor"; function "xor" (l, r : std_ulogic_vector) return std_ulogic_vector is subtype res_type is std_ulogic_vector (1 to l'length); alias la : res_type is l; alias ra : std_ulogic_vector (1 to r'length) is r; variable res : res_type; begin if la'length /= ra'length then assert false report "arguments of overloaded 'xor' operator are not of the same length" severity failure; else for I in res_type'range loop res (I) := xor_table (la (I), ra (I)); end loop; end if; return res; end "xor"; function "xnor" (l, r : std_ulogic_vector) return std_ulogic_vector is subtype res_type is std_ulogic_vector (1 to l'length); alias la : res_type is l; alias ra : std_ulogic_vector (1 to r'length) is r; variable res : res_type; begin if la'length /= ra'length then assert false report "arguments of overloaded 'xnor' operator are not of the same length" severity failure; else for I in res_type'range loop res (I) := xnor_table (la (I), ra (I)); end loop; end if; return res; end "xnor"; function "not" (l : std_ulogic_vector) return std_ulogic_vector is subtype res_type is std_ulogic_vector (1 to l'length); alias la : res_type is l; variable res : res_type; begin for I in res_type'range loop res (I) := not_table (la (I)); end loop; return res; end "not"; function "and" (l, r : std_logic_vector) return std_logic_vector is subtype res_type is std_logic_vector (1 to l'length); alias la : res_type is l; alias ra : std_logic_vector (1 to r'length) is r; variable res : res_type; begin if la'length /= ra'length then assert false report "arguments of overloaded 'and' operator are not of the same length" severity failure; else for I in res_type'range loop res (I) := and_table (la (I), ra (I)); end loop; end if; return res; end "and"; function "nand" (l, r : std_logic_vector) return std_logic_vector is subtype res_type is std_logic_vector (1 to l'length); alias la : res_type is l; alias ra : std_logic_vector (1 to r'length) is r; variable res : res_type; begin if la'length /= ra'length then assert false report "arguments of overloaded 'nand' operator are not of the same length" severity failure; else for I in res_type'range loop res (I) := nand_table (la (I), ra (I)); end loop; end if; return res; end "nand"; function "or" (l, r : std_logic_vector) return std_logic_vector is subtype res_type is std_logic_vector (1 to l'length); alias la : res_type is l; alias ra : std_logic_vector (1 to r'length) is r; variable res : res_type; begin if la'length /= ra'length then assert false report "arguments of overloaded 'or' operator are not of the same length" severity failure; else for I in res_type'range loop res (I) := or_table (la (I), ra (I)); end loop; end if; return res; end "or"; function "nor" (l, r : std_logic_vector) return std_logic_vector is subtype res_type is std_logic_vector (1 to l'length); alias la : res_type is l; alias ra : std_logic_vector (1 to r'length) is r; variable res : res_type; begin if la'length /= ra'length then assert false report "arguments of overloaded 'nor' operator are not of the same length" severity failure; else for I in res_type'range loop res (I) := nor_table (la (I), ra (I)); end loop; end if; return res; end "nor"; function "xor" (l, r : std_logic_vector) return std_logic_vector is subtype res_type is std_logic_vector (1 to l'length); alias la : res_type is l; alias ra : std_logic_vector (1 to r'length) is r; variable res : res_type; begin if la'length /= ra'length then assert false report "arguments of overloaded 'xor' operator are not of the same length" severity failure; else for I in res_type'range loop res (I) := xor_table (la (I), ra (I)); end loop; end if; return res; end "xor"; function "xnor" (l, r : std_logic_vector) return std_logic_vector is subtype res_type is std_logic_vector (1 to l'length); alias la : res_type is l; alias ra : std_logic_vector (1 to r'length) is r; variable res : res_type; begin if la'length /= ra'length then assert false report "arguments of overloaded 'xnor' operator are not of the same length" severity failure; else for I in res_type'range loop res (I) := xnor_table (la (I), ra (I)); end loop; end if; return res; end "xnor"; function "not" (l : std_logic_vector) return std_logic_vector is subtype res_type is std_logic_vector (1 to l'length); alias la : res_type is l; variable res : res_type; begin for I in res_type'range loop res (I) := not_table (la (I)); end loop; return res; end "not"; -- Conversion functions. -- The result range (for vectors) is S'Length - 1 downto 0. -- XMAP is return for values not in '0', '1', 'L', 'H'. function to_bit (s : std_ulogic; xmap : bit := '0') return bit is begin case s is when '0' | 'L' => return '0'; when '1' | 'H' => return '1'; when others => return xmap; end case; end to_bit; type bit_to_std_table is array (bit) of std_ulogic; constant bit_to_std : bit_to_std_table := "01"; function to_bitvector (s : std_ulogic_vector; xmap : bit := '0') return bit_vector is subtype res_range is natural range s'length - 1 downto 0; alias as : std_ulogic_vector (res_range) is s; variable res : bit_vector (res_range); variable b : bit; begin for I in res_range loop -- Inline for efficiency. case as (I) is when '0' | 'L' => b := '0'; when '1' | 'H' => b := '1'; when others => b := xmap; end case; res (I) := b; end loop; return res; end to_bitvector; function to_bitvector (s : std_logic_vector; xmap : bit := '0') return bit_vector is subtype res_range is natural range s'length - 1 downto 0; alias as : std_logic_vector (res_range) is s; variable res : bit_vector (res_range); variable b : bit; begin for I in res_range loop -- Inline for efficiency. case as (I) is when '0' | 'L' => b := '0'; when '1' | 'H' => b := '1'; when others => b := xmap; end case; res (I) := b; end loop; return res; end to_bitvector; function to_stdulogicvector (b : bit_vector) return std_ulogic_vector is subtype res_range is natural range b'length - 1 downto 0; alias ab : bit_vector (res_range) is b; variable res : std_ulogic_vector (res_range); begin for I in res_range loop res (I) := bit_to_std (ab (I)); end loop; return res; end to_stdulogicvector; function to_stdlogicvector (b : bit_vector) return std_logic_vector is subtype res_range is natural range b'length - 1 downto 0; alias ab : bit_vector (res_range) is b; variable res : std_logic_vector (res_range); begin for I in res_range loop res (I) := bit_to_std (ab (I)); end loop; return res; end to_stdlogicvector; function to_stdulogicvector (s : std_logic_vector) return std_ulogic_vector is subtype res_type is std_ulogic_vector (s'length - 1 downto 0); begin return res_type (s); end to_stdulogicvector; function to_stdlogicvector (s : std_ulogic_vector) return std_logic_vector is subtype res_type is std_logic_vector (s'length - 1 downto 0); begin return res_type (s); end to_stdlogicvector; function to_stdulogic (b : bit) return std_ulogic is begin return bit_to_std (b); end to_stdulogic; -- Normalization. type table_std_x01 is array (std_ulogic) of X01; constant std_to_x01 : table_std_x01 := ('U' | 'X' | 'Z' | 'W' | '-' => 'X', '0' | 'L' => '0', '1' | 'H' => '1'); type table_bit_x01 is array (bit) of X01; constant bit_to_x01 : table_bit_x01 := ('0' => '0', '1' => '1'); type table_std_x01z is array (std_ulogic) of X01Z; constant std_to_x01z : table_std_x01z := ('U' | 'X' | 'W' | '-' => 'X', '0' | 'L' => '0', '1' | 'H' => '1', 'Z' => 'Z'); type table_std_ux01 is array (std_ulogic) of UX01; constant std_to_ux01 : table_std_ux01 := ('U' => 'U', 'X' | 'Z' | 'W' | '-' => 'X', '0' | 'L' => '0', '1' | 'H' => '1'); function to_X01 (s : std_ulogic_vector) return std_ulogic_vector is subtype res_type is std_ulogic_vector (1 to s'length); alias sa : res_type is s; variable res : res_type; begin for i in res_type'range loop res (i) := std_to_x01 (sa (i)); end loop; return res; end to_X01; function to_X01 (s : std_logic_vector) return std_logic_vector is subtype res_type is std_logic_vector (1 to s'length); alias sa : res_type is s; variable res : res_type; begin for i in res_type'range loop res (i) := std_to_x01 (sa (i)); end loop; return res; end to_X01; function to_X01 (s : std_ulogic) return X01 is begin return std_to_x01 (s); end to_X01; function to_X01 (b : bit_vector) return std_ulogic_vector is subtype res_range is natural range 1 to b'length; alias ba : bit_vector (res_range) is b; variable res : std_ulogic_vector (res_range); begin for i in res_range loop res (i) := bit_to_x01 (ba (i)); end loop; return res; end to_X01; function to_X01 (b : bit_vector) return std_logic_vector is subtype res_range is natural range 1 to b'length; alias ba : bit_vector (res_range) is b; variable res : std_logic_vector (res_range); begin for i in res_range loop res (i) := bit_to_x01 (ba (i)); end loop; return res; end to_X01; function to_X01 (b : bit) return X01 is begin return bit_to_x01 (b); end to_X01; function to_X01Z (s : std_ulogic_vector) return std_ulogic_vector is subtype res_type is std_ulogic_vector (1 to s'length); alias sa : res_type is s; variable res : res_type; begin for i in res_type'range loop res (i) := std_to_x01z (sa (i)); end loop; return res; end to_X01Z; function to_X01Z (s : std_logic_vector) return std_logic_vector is subtype res_type is std_logic_vector (1 to s'length); alias sa : res_type is s; variable res : res_type; begin for i in res_type'range loop res (i) := std_to_x01z (sa (i)); end loop; return res; end to_X01Z; function to_X01Z (s : std_ulogic) return X01Z is begin return std_to_x01z (s); end to_X01Z; function to_X01Z (b : bit_vector) return std_ulogic_vector is subtype res_range is natural range 1 to b'length; alias ba : bit_vector (res_range) is b; variable res : std_ulogic_vector (res_range); begin for i in res_range loop res (i) := bit_to_x01 (ba (i)); end loop; return res; end to_X01Z; function to_X01Z (b : bit_vector) return std_logic_vector is subtype res_range is natural range 1 to b'length; alias ba : bit_vector (res_range) is b; variable res : std_logic_vector (res_range); begin for i in res_range loop res (i) := bit_to_x01 (ba (i)); end loop; return res; end to_X01Z; function to_X01Z (b : bit) return X01Z is begin return bit_to_x01 (b); end to_X01Z; function to_UX01 (s : std_ulogic_vector) return std_ulogic_vector is subtype res_type is std_ulogic_vector (1 to s'length); alias sa : res_type is s; variable res : res_type; begin for i in res_type'range loop res (i) := std_to_ux01 (sa (i)); end loop; return res; end to_UX01; function to_UX01 (s : std_logic_vector) return std_logic_vector is subtype res_type is std_logic_vector (1 to s'length); alias sa : res_type is s; variable res : res_type; begin for i in res_type'range loop res (i) := std_to_ux01 (sa (i)); end loop; return res; end to_UX01; function to_UX01 (s : std_ulogic) return UX01 is begin return std_to_ux01 (s); end to_UX01; function to_UX01 (b : bit_vector) return std_ulogic_vector is subtype res_range is natural range 1 to b'length; alias ba : bit_vector (res_range) is b; variable res : std_ulogic_vector (res_range); begin for i in res_range loop res (i) := bit_to_x01 (ba (i)); end loop; return res; end to_UX01; function to_UX01 (b : bit_vector) return std_logic_vector is subtype res_range is natural range 1 to b'length; alias ba : bit_vector (res_range) is b; variable res : std_logic_vector (res_range); begin for i in res_range loop res (i) := bit_to_x01 (ba (i)); end loop; return res; end to_UX01; function to_UX01 (b : bit) return UX01 is begin return bit_to_x01 (b); end to_UX01; function rising_edge (signal s : std_ulogic) return boolean is begin return s'event and to_x01 (s'last_value) = '0' and to_x01 (s) = '1'; end rising_edge; function falling_edge (signal s : std_ulogic) return boolean is begin return s'event and to_x01 (s'last_value) = '1' and to_x01 (s) = '0'; end falling_edge; type std_x_array is array (std_ulogic) of boolean; constant std_x : std_x_array := ('U' | 'X' | 'Z' | 'W' | '-' => true, '0' | '1' | 'L' | 'H' => false); function is_X (s : std_ulogic_vector) return boolean is begin for i in s'range loop if std_x (s (i)) then return true; end if; end loop; return false; end is_X; function is_X (s : std_logic_vector) return boolean is begin for i in s'range loop if std_x (s (i)) then return true; end if; end loop; return false; end is_X; function is_X (s : std_ulogic) return boolean is begin return std_x (s); end is_X; end std_logic_1164;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc3016.vhd
4
1887
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc3016.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- library WORK, STD; use STD.STANDARD.all; -- No_failure_here ENTITY c11s02b00x00p05n02i03016ent IS END c11s02b00x00p05n02i03016ent; ARCHITECTURE c11s02b00x00p05n02i03016arch OF c11s02b00x00p05n02i03016ent IS signal BV : BIT_VECTOR(0 to 7); BEGIN TESTING: PROCESS BEGIN BV <= "01010111" after 5 ns; wait for 10 ns; assert NOT( BV = "01010111" ) report "***PASSED TEST: c11s02b00x00p05n02i03016" severity NOTE; assert ( BV = "01010111" ) report "***FAILED TEST: c11s02b00x00p05n02i03016 - Library clause should appear as part of a context clause at the beginning of a design unit." severity ERROR; wait; END PROCESS TESTING; END c11s02b00x00p05n02i03016arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1439.vhd
4
1638
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1439.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s07b00x00p02n01i01439ent IS END c08s07b00x00p02n01i01439ent; ARCHITECTURE c08s07b00x00p02n01i01439arch OF c08s07b00x00p02n01i01439ent IS BEGIN process variable VAR_1: INTEGER := 3; begin if VAR_1 > 2 then NULL; en if; assert FALSE report "***FAILED TEST: c08s07b00x00p02n01i01439 - reserved word 'end if;' is misspelled" severity ERROR; wait; end process; END c08s07b00x00p02n01i01439arch;
gpl-2.0
tgingold/ghdl
testsuite/gna/issue818/tc1.vhdl
1
245
entity tc1 is end; library ieee; use ieee.std_logic_1164.all; architecture behav of tc1 is signal clk : std_logic; signal tg : std_logic; begin process (clk) is begin if ?? tg then null; end if; end process; end behav;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/simple-resolution-function.vhd
4
867
entity test is end test; architecture only of test is -- forward declaration of the function. function wired_or( s : bit_vector ) return bit; -- declare the subtype. subtype rbit is wired_or bit; -- declare the actual function. function wired_or( s : bit_vector ) return bit is begin report "resolution function called!" severity note; if ( (s(0) = '1') or (s(1) = '1')) then return '1'; end if; return '0'; end wired_or; -- declare a signal of that type. a resolved signal. signal s : rbit; begin -- a concurrent signal assignment. driver # 1. s <= '1'; testing: process begin -- verify that resolution function getting called. s <= '1' after 10 ns; wait on s; assert ( s = '1' ) report "TEST FAILED" severity failure; report "TEST PASSED"; wait; end process testing; end only;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc2480.vhd
4
1933
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2480.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s03b02x02p13n04i02480ent IS END c07s03b02x02p13n04i02480ent; ARCHITECTURE c07s03b02x02p13n04i02480arch OF c07s03b02x02p13n04i02480ent IS type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character; subtype CA_UP is UNCONSTRAINED_ARRAY (1 to 10); subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1); BEGIN TESTING: PROCESS BEGIN assert NOT((CA_DOWN'RIGHT = 1) and (CA_UP'RIGHT = 10)) report "***PASSED TEST: c07s03b02x02p13n04i02480" severity NOTE; assert ((CA_DOWN'RIGHT = 1) and (CA_UP'RIGHT = 10)) report "***FAILED TEST: c07s03b02x02p13n04i02480 - Rightmost bounds INCORRECT for positional aggregates." severity ERROR; wait; END PROCESS TESTING; END c07s03b02x02p13n04i02480arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc776.vhd
4
2170
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc776.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c01s01b01x02p09n01i00776ent_a IS port ( C1 : inout Bit ; C2 : buffer Bit ); END c01s01b01x02p09n01i00776ent_a; ARCHITECTURE c01s01b01x02p09n01i00776arch_a OF c01s01b01x02p09n01i00776ent_a IS BEGIN c1 <= c2; END c01s01b01x02p09n01i00776arch_a; ENTITY c01s01b01x02p09n01i00776ent IS port ( p1 : inout Bit ; p2 : buffer Bit ); END c01s01b01x02p09n01i00776ent; ARCHITECTURE c01s01b01x02p09n01i00776arch OF c01s01b01x02p09n01i00776ent IS component c01s01b01x02p09n01i00776ent_b port ( C1 : inout Bit ; C2 : buffer Bit ); end component; for L : c01s01b01x02p09n01i00776ent_b use entity work.c01s01b01x02p09n01i00776ent_a(c01s01b01x02p09n01i00776arch_a); BEGIN L : c01s01b01x02p09n01i00776ent_b port map (p1, p2); --Success here TESTING: PROCESS BEGIN assert FALSE report "***PASSED TEST: c01s01b01x02p09n01i00776" severity NOTE; wait; END PROCESS TESTING; END c01s01b01x02p09n01i00776arch;
gpl-2.0
tgingold/ghdl
testsuite/gna/bug0109/err.vhdl
1
852
library ieee; use ieee.std_logic_1164.all; use ieee.fixed_pkg.all; entity phz_calc is end entity phz_calc; architecture behavioral of phz_calc is function to_string (inp: sfixed) return string is variable image_str: string (1 to inp'length + 1); variable j: integer range 1 to image_str'length + 1; begin j := 1; for i in inp'range loop if i = -1 then image_str(j) := '.'; j := j + 1; end if; image_str(j) := character'VALUE(std_ulogic'IMAGE(inp(i))); j := j + 1; end loop; return image_str; end function; begin process variable z: sfixed (3 downto -3); begin z := to_sfixed(3.2,3,-3); report "z = " & to_string (z); wait; end process; end architecture behavioral;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_06.vhd
4
2210
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ap_a_fg_a_06.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $ -- $Revision: 1.1.1.1 $ -- -- --------------------------------------------------------------------- entity fg_a_06 is end entity fg_a_06; library ieee; use ieee.std_logic_1164.all; architecture test of fg_a_06 is -- code from book constant terminal_count : integer := 2**6 - 1; subtype counter_range is integer range 0 to terminal_count; signal count : counter_range; -- . . . -- end code from book signal clk, reset : std_ulogic; begin -- code from book counter6 : process (reset, clk) begin if reset = '0' then count <= 0; elsif rising_edge(clk) then if count < terminal_count then count <= count + 1; else count <= 0; end if; end if; end process counter6; -- end code from book stimulus : process is begin reset <= '1'; clk <= '0'; wait for 10 ns; clk <= '1', '0' after 10 ns; wait for 20 ns; clk <= '1', '0' after 10 ns; wait for 20 ns; clk <= '1', '0' after 10 ns; wait for 20 ns; reset <= '0', '1' after 30 ns; clk <= '1' after 10 ns, '0' after 20 ns; wait for 40 ns; for i in 1 to terminal_count + 10 loop clk <= '1', '0' after 10 ns; wait for 20 ns; end loop; wait; end process stimulus; end architecture test;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc2160.vhd
4
2035
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2160.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b04x00p22n01i02160ent IS END c07s02b04x00p22n01i02160ent; ARCHITECTURE c07s02b04x00p22n01i02160arch OF c07s02b04x00p22n01i02160ent IS TYPE boolean_v is array (integer range <>) of boolean; SUBTYPE boolean_2 is boolean_v (1 to 2); BEGIN TESTING: PROCESS variable result : boolean_2; variable l_operand : boolean := true; variable r_operand : boolean := false; BEGIN result := l_operand & r_operand; wait for 5 ns; assert NOT((result = (true,false)) and (result(1) = true)) report "***PASSED TEST: c07s02b04x00p22n01i02160" severity NOTE; assert ((result = (true,false)) and (result(1) = true)) report "***FAILED TEST: c07s02b04x00p22n01i02160 - Concatenation of element and element failed." severity ERROR; wait; END PROCESS TESTING; END c07s02b04x00p22n01i02160arch;
gpl-2.0
tgingold/ghdl
testsuite/gna/ticket62/repro.vhdl
3
310
entity ent is end; architecture behav of ent is shared variable v : integer; begin process begin v := 2; wait for 2 ns; assert v = 5 severity failure; wait; end process; process begin wait for 1 ns; assert v = 2 severity failure; v := 5; wait; end process; end;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2926.vhd
4
1846
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2926.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c02s02b00x00p04n01i02926ent IS END c02s02b00x00p04n01i02926ent; ARCHITECTURE c02s02b00x00p04n01i02926arch OF c02s02b00x00p04n01i02926ent IS function M return BOOLEAN; function M return BOOLEAN is component C -- Failure_here -- ERROR : component declaration not allowed in subprogram declarations port ( I : out REAL ) ; end component ; begin return FALSE; end M; BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c02s02b00x00p04n01i02926 - Component declarations are not allowed within subprogram declaration." severity ERROR; wait; END PROCESS TESTING; END c02s02b00x00p04n01i02926arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc794.vhd
4
1632
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc794.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c01s01b03x00p03n01i00794ent IS begin port ( isig : in bit; osig : out bit ); END c01s01b03x00p03n01i00794ent; ARCHITECTURE c01s01b03x00p03n01i00794arch OF c01s01b03x00p03n01i00794ent IS BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c01s01b03x00p03n01i00794 - Port clause is not permitted as an entity statement." severity ERROR; wait; END PROCESS TESTING; END c01s01b03x00p03n01i00794arch;
gpl-2.0
tgingold/ghdl
testsuite/gna/bug019/PoC/tb/io/uart/uart_rx_tb.vhdl
2
4072
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Module: uart_rx_tb -- -- Authors: Patrick Lehmann -- -- Description: -- ------------------------------------ -- Testbench for arith_counter_bcd -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; use PoC.vectors.all; use PoC.strings.all; use PoC.physical.all; use PoC.simulation.all; use PoC.uart.all; entity uart_rx_tb is end entity; architecture tb of uart_rx_tb is constant CLOCK_FREQ : FREQ := 100 MHz; constant BAUDRATE : BAUD := 4.2 MBd; signal Clock : STD_LOGIC; signal Reset : STD_LOGIC; signal BitClock : STD_LOGIC; signal BitClock_x8 : STD_LOGIC; signal UART_RX : STD_LOGIC; signal RX_Strobe : STD_LOGIC; signal RX_Data : T_SLV_8; function simGenerateWaveform_UART_Word(Data : T_SLV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is constant BIT_TIME : TIME := to_time(to_freq(Baudrate)); variable Result : T_SIM_WAVEFORM_SL(0 to 9) := (others => (Delay => BIT_TIME, Value => '-')); begin Result(0).Value := '0'; for i in Data'range loop Result(i + 1).Value := Data(i); end loop; Result(9).Value := '1'; return Result; end function; function simGenerateWaveform_UART_Stream(Data : T_SLVV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is variable Result : T_SIM_WAVEFORM_SL(0 to (Data'length * 10) - 1); begin for i in Data'range loop Result(i * 10 to ((i + 1) * 10) - 1) := simGenerateWaveform_UART_Word(Data(i), BAUDRATE); end loop; return Result; end function; constant DATA_STREAM : T_SLVV_8 := (x"12", x"45", x"FE", x"C4", x"02"); begin simGenerateClock(Clock, CLOCK_FREQ); simGenerateWaveform(Reset, simGenerateWaveform_Reset(Pause => 50 ns)); p1f: if true generate simGenerateWaveform(UART_RX, simGenerateWaveform_UART_Stream(DATA_STREAM, BAUDRATE), '1'); end generate; p1t: if false generate process constant wf : T_SIM_WAVEFORM_SL := simGenerateWaveform_UART_Stream(DATA_STREAM, BAUDRATE); begin simGenerateWaveform(UART_RX, wf, '1'); end process; end generate; bclk : entity PoC.uart_bclk generic map ( CLOCK_FREQ => CLOCK_FREQ, BAUDRATE => BAUDRATE ) port map ( clk => Clock, rst => Reset, bclk => BitClock, bclk_x8 => BitClock_x8 ); RX : entity PoC.uart_rx generic map ( OUT_REGS => FALSE ) port map ( clk => Clock, rst => Reset, bclk_x8 => BitClock_x8, dos => RX_Strobe, dout => RX_Data, rxd => UART_RX ); process begin for i in DATA_STREAM'range loop wait until rising_edge(Clock) and (RX_Strobe = '1'); report TIME'image(NOW) severity NOTE; tbAssert((RX_Data = DATA_STREAM(i)), "Data Byte " & INTEGER'image(i) & " received: " & to_string(RX_Data, 'h') & " expected: " & to_string(DATA_STREAM(i), 'h')); end loop; wait for 1 us; simStop; tbPrintResult; wait; end process; end architecture;
gpl-2.0
tgingold/ghdl
testsuite/synth/issue964/tb_ent.vhdl
1
947
entity tb_ent is end tb_ent; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_ent is signal clk : std_logic; signal dout : std_logic; signal enable : std_logic; signal reset : std_logic; begin dut: entity work.ent port map ( enable => enable, reset => reset, q => dout, clk => clk); process procedure pulse is begin clk <= '0'; wait for 1 ns; clk <= '1'; wait for 1 ns; end pulse; begin enable <= '1'; reset <= '1'; pulse; assert dout = '0' severity failure; enable <= '1'; reset <= '0'; pulse; assert dout = '1' severity failure; pulse; assert dout = '0' severity failure; pulse; assert dout = '1' severity failure; enable <= '0'; pulse; assert dout = '1' severity failure; enable <= '1'; pulse; assert dout = '0' severity failure; wait; end process; end behav;
gpl-2.0
tgingold/ghdl
testsuite/synth/output01/tb_output07.vhdl
1
677
library ieee; use ieee.std_logic_1164.all; entity tb_output07 is end tb_output07; architecture behav of tb_output07 is signal i : std_logic; signal clk : std_logic; signal o : std_logic_vector (1 downto 0); begin inst: entity work.output07 port map (clk => clk, i => i, o => o); process procedure pulse is begin wait for 1 ns; clk <= '1'; wait for 1 ns; clk <= '0'; end pulse; begin clk <= '0'; wait for 1 ns; assert o = "10" severity failure; i <= '1'; pulse; assert o = "01" severity failure; i <= '0'; pulse; assert o = "10" severity failure; wait; end process; end behav;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc2324.vhd
4
5916
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2324.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b07x00p01n01i02324ent IS END c07s02b07x00p01n01i02324ent; ARCHITECTURE c07s02b07x00p01n01i02324arch OF c07s02b07x00p01n01i02324ent IS BEGIN TESTING: PROCESS -- Local declarations. variable INTV1 : INTEGER; variable INTV2 : INTEGER; variable INTV3 : INTEGER; variable INTV4 : INTEGER; variable INTV5 : INTEGER; variable INTV6 : INTEGER; variable INTV7 : INTEGER; variable INTV8 : INTEGER; variable REALV1 : REAL; variable REALV2 : REAL; variable REALV3 : REAL; variable REALV4 : REAL; variable REALV5 : REAL; variable REALV6 : REAL; variable REALV7 : REAL; variable REALV8 : REAL; BEGIN -- Test absolute value of integer literals and variables. INTV1 := abs (-5); assert (INTV1 = 5) report "Assertion Violation(1)"; INTV2 := abs 5; assert (INTV2 = 5) report "Assertion Violation(2)"; INTV3 := abs 0; assert (INTV3 = 0) report "Assertion Violation(3)"; INTV4 := abs INTEGER'HIGH; assert (INTV4 = INTEGER'HIGH) report "Assertion Violation(4)"; INTV5 := -5; INTV5 := abs INTV5; assert (INTV5 = 5) report "Assertion Violation(5)"; INTV6 := 5; INTV6 := abs 5; assert (INTV6 = 5) report "Assertion Violation(6)"; INTV7 := 0; INTV7 := abs 0; assert (INTV7 = 0) report "Assertion Violation(7)"; INTV8 := INTEGER'HIGH; INTV8 := abs INTEGER'HIGH; assert (INTV8 = INTEGER'HIGH) report "Assertion Violation(8)"; -- Do the same for the predefined physical type TIME. assert (abs (-5 ns) = 5 ns) report "Assertion Violation(9)"; assert (abs 5 ns = 5 ns) report "Assertion Violation(10)"; assert (abs 0 fs = 0 fs) report "Assertion Violation(11)"; assert (abs TIME'HIGH = TIME'HIGH) report "Assertion Violation(12)"; -- Test absolute value of real literals and variables. REALV1 := abs (-5.0); assert (REALV1 = 5.0) report "Assertion Violation(13)"; REALV2 := abs 5.0; assert (REALV2 = 5.0) report "Assertion Violation(14)"; REALV3 := abs 0.0; assert (REALV3 = 0.0) report "Assertion Violation(15)"; REALV4 := abs REAL'HIGH; assert (REALV4 = REAL'HIGH) report "Assertion Violation(16)"; REALV5 := -5.0; REALV5 := abs REALV5; assert (REALV5 = 5.0) report "Assertion Violation(17)"; REALV6 := 5.0; REALV6 := abs 5.0; assert (REALV6 = 5.0) report "Assertion Violation(18)"; REALV7 := 0.0; REALV7 := abs 0.0; assert (REALV7 = 0.0) report "Assertion Violation(19)"; REALV8 := REAL'HIGH; REALV8 := abs REAL'HIGH; assert (REALV8 = REAL'HIGH) report "Assertion Violation(20)"; wait for 5 ns; assert NOT( (INTV1 = 5) and (INTV2 = 5) and (INTV3 = 0) and (INTV4 = INTEGER'HIGH) and (INTV5 = 5) and (INTV6 = 5) and (INTV7 = 0) and (INTV8 = INTEGER'HIGH) and (abs (-5 ns) = 5 ns) and (abs 5 ns = 5 ns) and (abs 0 fs = 0 fs) and (abs TIME'HIGH = TIME'HIGH) and (REALV1 = 5.0) and (REALV2 = 5.0) and (REALV3 = 0.0) and (REALV4 = REAL'HIGH) and (REALV5 = 5.0) and (REALV6 = 5.0) and (REALV7 = 0.0) and (REALV8 = REAL'HIGH) ) report "***PASSED TEST: c07s02b07x00p01n01i02324" severity NOTE; assert ( (INTV1 = 5) and (INTV2 = 5) and (INTV3 = 0) and (INTV4 = INTEGER'HIGH) and (INTV5 = 5) and (INTV6 = 5) and (INTV7 = 0) and (INTV8 = INTEGER'HIGH) and (abs (-5 ns) = 5 ns) and (abs 5 ns = 5 ns) and (abs 0 fs = 0 fs) and (abs TIME'HIGH = TIME'HIGH) and (REALV1 = 5.0) and (REALV2 = 5.0) and (REALV3 = 0.0) and (REALV4 = REAL'HIGH) and (REALV5 = 5.0) and (REALV6 = 5.0) and (REALV7 = 0.0) and (REALV8 = REAL'HIGH) ) report "***FAILED TEST: c07s02b07x00p01n01i02324 - Unary operator abs for any numeric type test failed." severity ERROR; wait; END PROCESS TESTING; END c07s02b07x00p01n01i02324arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc2332.vhd
4
1774
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2332.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b07x00p02n02i02332ent IS END c07s02b07x00p02n02i02332ent; ARCHITECTURE c07s02b07x00p02n02i02332arch OF c07s02b07x00p02n02i02332ent IS type NEW_INT is range INTEGER'LOW to INTEGER'HIGH; signal k : NEW_INT := 5; BEGIN TESTING: PROCESS BEGIN k <= 2 ** 2; wait for 1 ns; assert NOT(k=4) report "***PASSED TEST: c07s02b07x00p02n02i02332" severity NOTE; assert (k=4) report "***FAILED TEST: c07s02b07x00p02n02i02332 - Exponent can only be of type Integer." severity ERROR; wait; END PROCESS TESTING; END c07s02b07x00p02n02i02332arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1186.vhd
4
1626
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1186.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s01b00x00p02n01i01186ent IS END c08s01b00x00p02n01i01186ent; ARCHITECTURE c08s01b00x00p02n01i01186arch OF c08s01b00x00p02n01i01186ent IS BEGIN TESTING: PROCESS variable k : integer := 0; BEGIN wait for 60 ns until (k = 1); assert FALSE report "***FAILED TEST: c08s01b00x00p02n01i01186 - Timeout clause before condition clause." severity ERROR; wait; END PROCESS TESTING; END c08s01b00x00p02n01i01186arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc836.vhd
4
1985
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc836.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c01s03b01x00p02n01i00836ent IS END c01s03b01x00p02n01i00836ent; ARCHITECTURE c01s03b01x00p02n01i00836arch OF c01s03b01x00p02n01i00836ent IS BEGIN DE : block signal S1 : BOOLEAN; begin S1 <= true; end block DE; TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c01s03b01x00p02n01i00836 - Binding indications are not allowed in a configuration of a block." severity ERROR; wait; END PROCESS TESTING; END c01s03b01x00p02n01i00836arch; configuration c01s03b01x00p02n01i00836cfg of c01s03b01x00p02n01i00836ent is for c01s03b01x00p02n01i00836arch for DE use -- Failure_here : binding indications are not allowed in a -- configuration of a block entity work.entity0 open; end for; end c01s03b01x00p02n01i00836cfg;
gpl-2.0
tgingold/ghdl
testsuite/synth/issue1005/test2.vhdl
1
429
library ieee; use ieee.std_logic_1164.all; use std.env.stop; entity test2 is generic ( SIM : boolean := false ); port ( val : in std_ulogic ); end entity test2; architecture behaviour of test2 is begin process_0: process(all) begin if not SIM or val = '1' then null; else stop; end if; end process; end architecture behaviour;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1693.vhd
4
1882
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1693.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c09s02b00x00p03n01i01693ent IS port (B:BIT; C:out BIT) ; END c09s02b00x00p03n01i01693ent; ARCHITECTURE c09s02b00x00p03n01i01693arch OF c09s02b00x00p03n01i01693ent IS BEGIN process begin architecture B6 of E1 is -- Failure_here --SEMANTICS ERROR: body declarations may not be in a process statement. begin process begin null; end process; end B6; null; end process; TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c09s02b00x00p03n01i01693 - Body declarations are not allowed in process statements." severity ERROR; wait; END PROCESS TESTING; END c09s02b00x00p03n01i01693arch;
gpl-2.0
tgingold/ghdl
testsuite/synth/iassoc01/iassoc03.vhdl
1
536
use work.pkg.all; entity riassoc03 is port (v : nat_arr (1 to 2); res : out natural); end riassoc03; architecture behav of riassoc03 is begin process (v) variable t : natural; begin t := 0; for i in v'range loop t := t + v (i); end loop; res <= t; end process; end behav; entity iassoc03 is port (a, b : natural; res : out natural); end iassoc03; architecture behav of iassoc03 is begin inst : entity work.riassoc03 port map (v (1) => a, v (2) => b, res => res); end behav;
gpl-2.0
tgingold/ghdl
testsuite/synth/dispout01/rec09.vhdl
1
211
library ieee; use ieee.std_logic_1164.all; use work.rec09_pkg.all; entity rec09 is port (inp : std_logic; o : out myrec); end rec09; architecture behav of rec09 is begin o.b <= not inp; end behav;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1044.vhd
4
1852
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1044.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s04b00x00p03n01i01044ent IS END c06s04b00x00p03n01i01044ent; ARCHITECTURE c06s04b00x00p03n01i01044arch OF c06s04b00x00p03n01i01044ent IS BEGIN TESTING: PROCESS type THREE is range 1 to 3; type A1 is array (THREE) of BOOLEAN; type ONE is range 1 to 1; type A2 is array (ONE) of BOOLEAN; variable V1: BOOLEAN; BEGIN V1 := A1'(1=>TRUE, 2=>TRUE, 3=>TRUE)(2); -- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE assert FALSE report "***FAILED TEST: c06s04b00x00p03n01i01044 - Prefix of an indexed name cannot be an aggregate." severity ERROR; wait; END PROCESS TESTING; END c06s04b00x00p03n01i01044arch;
gpl-2.0
tgingold/ghdl
testsuite/synth/bug02/repro2.vhdl
1
572
library ieee; use ieee.std_logic_1164.all; entity repro2 is port ( clk_i : in std_logic; rst_n_i : in std_logic; vec_i : in std_logic_vector(0 to 0) ); end repro2; architecture rtl of repro2 is signal s_sel : natural range vec_i'range; signal s_true : std_logic; begin s_true <= '1'; process (clk_i) begin if rising_edge(clk_i) then for i in vec_i'range loop if s_true = '1' then s_sel <= i; exit; end if; end loop; end if; end process; end rtl;
gpl-2.0
tgingold/ghdl
testsuite/synth/arr02/tb_arr02.vhdl
1
874
entity tb_arr02 is end tb_arr02; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_arr02 is signal a : std_logic_vector (31 downto 0); signal sel : natural range 0 to 3; signal clk : std_logic; signal res : std_logic_vector (3 downto 0); begin dut: entity work.arr02 port map (a, sel, clk, res); process procedure pulse is begin clk <= '0'; wait for 1 ns; clk <= '1'; wait for 1 ns; end pulse; begin a <= x"a1b2c3d4"; sel <= 0; pulse; pulse; assert res = x"1" severity failure; sel <= 1; pulse; assert res = x"1" severity failure; sel <= 2; pulse; assert res = x"2" severity failure; sel <= 3; pulse; assert res = x"3" severity failure; sel <= 0; pulse; assert res = x"4" severity failure; wait; end process; end behav;
gpl-2.0
tgingold/ghdl
testsuite/gna/issue50/idct.d/sub_496.vhd
2
800
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity sub_496 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(31 downto 0) ); end sub_496; architecture augh of sub_496 is signal carry_inA : std_logic_vector(33 downto 0); signal carry_inB : std_logic_vector(33 downto 0); signal carry_res : std_logic_vector(33 downto 0); begin -- To handle the CI input, the operation is '0' - CI -- If CI is not present, the operation is '0' - '0' carry_inA <= '0' & in_a & '0'; carry_inB <= '0' & in_b & '0'; -- Compute the result carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); -- Set the outputs result <= carry_res(32 downto 1); end architecture;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/disputed/tc59.vhd
4
1822
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc59.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s03b01x01p05n01i00059ent IS END c04s03b01x01p05n01i00059ent; ARCHITECTURE c04s03b01x01p05n01i00059arch OF c04s03b01x01p05n01i00059ent IS signal S1 : integer := 10; BEGIN TESTING : PROCESS variable TimeCount : time := 0 ns; BEGIN S1 <= transport N1 after T1 ; -- No_failure_here wait for T1; assert NOT(S1'active and S1 = 20) report "***PASSED TEST:c04s03b01x01p05n01i00059" severity NOTE; assert (S1'active and S1 = 20) report "***FAILED TEST:c04s03b01x01p05n01i00059 - Generics constant test failed." severity ERROR; wait; END PROCESS TESTING; END c04s03b01x01p05n01i00059arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1060.vhd
4
1958
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1060.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s04b00x00p03n02i01060ent IS END c06s04b00x00p03n02i01060ent; ARCHITECTURE c06s04b00x00p03n02i01060arch OF c06s04b00x00p03n02i01060ent IS BEGIN TESTING: PROCESS type THREE is range 1 to 3; type ENUM1 is (EN1, EN2, EN3); type A22 is array (ENUM1, ENUM1) of BOOLEAN; type A31 is array (THREE) of A22; variable V1: BOOLEAN; variable V31: A31 ; BEGIN V1 := V31(2)(EN3, EN2, EN1); -- ONE MORE -- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO -- INDEX POSITIONS IN TYPE DECLARATION assert FALSE report "***FAILED TEST: c06s04b00x00p03n02i01060 - The expresion should be the same type as the corresponding index." severity ERROR; wait; END PROCESS TESTING; END c06s04b00x00p03n02i01060arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc2494.vhd
4
1921
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2494.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s03b03x00p04n02i02494ent IS END c07s03b03x00p04n02i02494ent; ARCHITECTURE c07s03b03x00p04n02i02494arch OF c07s03b03x00p04n02i02494ent IS BEGIN TESTING: PROCESS function check (x : integer) return integer is begin return (10 * x); end; variable q1: integer := 12; variable q2: integer ; BEGIN q2 := check (q1) + 24 - check (2); assert NOT( q2 = 124 ) report "***PASSED TEST: c07s03b03x00p04n02i02494" severity NOTE; assert ( q2=124 ) report "***FAILED TEST: c07s03b03x00p04n02i02494 - The actual parameter can be specified explicitly by an association element in the association list." severity ERROR; wait; END PROCESS TESTING; END c07s03b03x00p04n02i02494arch;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/compliant/tc2119.vhd
4
2119
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2119.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b04x00p20n01i02119ent IS END c07s02b04x00p20n01i02119ent; ARCHITECTURE c07s02b04x00p20n01i02119arch OF c07s02b04x00p20n01i02119ent IS TYPE integer_v is array (integer range <>) of integer; SUBTYPE integer_4 is integer_v (1 to 4); SUBTYPE integer_null is integer_v (1 to 0); BEGIN TESTING : PROCESS variable result : integer_4; variable l_operand : integer_null; variable r_operand : integer_4 := (123,789,123,789); BEGIN result := l_operand & r_operand; wait for 20 ns; assert NOT((result = (123,789,123,789)) and (result(1) = 123)) report "***PASSED TEST: c07s02b04x00p20n01i02119" severity NOTE; assert ((result = (123,789,123,789)) and (result(1) = 123)) report "***FAILED TEST: c07s02b04x00p20n01i02119 - Concatenation of null and INTEGER arrays failed." severity ERROR; wait; END PROCESS TESTING; END c07s02b04x00p20n01i02119arch;
gpl-2.0
tgingold/ghdl
testsuite/gna/issue984/tester_conf.vhd
1
269
use work.const_pkg.all; configuration tester_conf of tester is for a for checker : check use entity work.generic_check generic map ( i => c ); end for; end for; end configuration;
gpl-2.0
tgingold/ghdl
testsuite/gna/issue317/repro5.vhdl
1
1335
package repro5_gen is generic (type t; function id (a : t) return t); function id2 (p : t) return t; type prot is protected procedure Set (V : natural); impure function Get return Natural; end protected prot; end repro5_gen; package body repro5_gen is function id2 (p : t) return t is -- constant c : t := p; begin return id (p); end id2; type prot is protected body variable val : Natural; procedure Set (V : natural) is begin val := v; end Set; impure function Get return Natural is begin return val; end Get; end protected body prot; end repro5_gen; package repro5_sortnet_tb is generic ( DATA_BITS : positive; LEN : Positive ); subtype T_DATA is bit_vector(DATA_BITS - 1 downto 0); type T_DATA_VECTOR is array(1 to LEN) of T_DATA; function id (a : t_data_vector) return t_data_vector; package inst is new work.repro5_gen generic map (t => t_data_vector, id => id); end repro5_sortnet_tb; package body repro5_sortnet_tb is function id (a : t_data_vector) return t_data_vector is begin return a; end id; end repro5_sortnet_tb; entity repro5 is end repro5; architecture behav of repro5 is package tb is new work.repro5_sortnet_tb generic map (3, 4); begin end behav;
gpl-2.0
tgingold/ghdl
testsuite/gna/bug077/repro7.vhdl
1
552
entity repro7 is end repro7; architecture behav of repro7 is type my_rec is record a : bit; w : bit_vector; end record; procedure check (signal v : my_rec) is begin assert v.a = '0' and v.w = "01" severity failure; end check; procedure pack (signal a : bit; signal w : bit_vector) is begin check (v.a => a, v.w => w); end pack; signal sa : bit; signal sw : bit_vector (1 to 2); begin process begin sa <= '0'; sw <= "01"; wait for 0 ns; pack (sa, sw); wait; end process; end;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/active_filter.vhd
4
2141
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- not in book library ieee_proposed; use ieee_proposed.electrical_systems.all; entity resistor is port ( terminal node1, node2 : electrical ); end entity resistor; library ieee_proposed; use ieee_proposed.electrical_systems.all; entity capacitor is port ( terminal node1, node2 : electrical ); end entity capacitor; library ieee_proposed; use ieee_proposed.electrical_systems.all; entity LF353_opamp is port ( terminal plus, minus, output, pos_supply, neg_supply : electrical ); end entity LF353_opamp; library ieee_proposed; use ieee_proposed.electrical_systems.all; entity active_filter is end entity active_filter; -- end not in book library widget_parts, wasp_lib; architecture component_based of active_filter is -- declaration of signals, terminals, quantities, etc -- ... -- not in book terminal input, node2, node3, node4, node7, node15, Vdd, Vss : electrical; -- end not in book begin R1 : entity wasp_lib.resistor port map ( node1 => input, node2 => node2 ); C1 : entity widget_parts.capacitor port map ( node1 => node3, node2 => ground ); Amp1 : entity work.LF353_opamp port map ( plus => node4, minus => node7, output => node15, pos_supply => Vdd, neg_supply => Vss ); -- other component instantiations -- ... end architecture component_based;
gpl-2.0
tgingold/ghdl
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1045.vhd
4
1839
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1045.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s04b00x00p03n01i01045ent IS END c06s04b00x00p03n01i01045ent; ARCHITECTURE c06s04b00x00p03n01i01045arch OF c06s04b00x00p03n01i01045ent IS BEGIN TESTING: PROCESS type THREE is range 1 to 3; type A1 is array (THREE) of BOOLEAN; type ONE is range 1 to 1; type A2 is array (ONE) of BOOLEAN; variable V1: BOOLEAN; BEGIN V1 := A1'(others=>TRUE)(2); -- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE assert FALSE report "***FAILED TEST: c06s04b00x00p03n01i01045 - Prefix of an indexed name cannot be an aggregate." severity ERROR; wait; END PROCESS TESTING; END c06s04b00x00p03n01i01045arch;
gpl-2.0
tgingold/ghdl
testsuite/gna/issue317/OSVVM/SortListPkg_int.vhd
3
13743
-- -- File Name: SortListPkg_int.vhd -- Design Unit Name: SortListPkg_int -- Revision: STANDARD VERSION -- -- Maintainer: Jim Lewis email: [email protected] -- Contributor(s): -- Jim Lewis [email protected] -- -- Description: -- Sorting utility for array of scalars -- Uses protected type so as to shrink and expand the data structure -- -- Developed for: -- SynthWorks Design Inc. -- VHDL Training Classes -- 11898 SW 128th Ave. Tigard, Or 97223 -- http://www.SynthWorks.com -- -- Revision History: -- Date Version Description -- 06/2008: 0.1 Initial revision -- Numerous revisions for VHDL Testbenches and Verification -- 02/2009: 1.0 First Public Released Version -- 02/25/2009 1.1 Replaced reference to std_2008 with a reference to -- ieee_proposed.standard_additions.all ; -- 06/16/2010 1.2 Added EraseList parameter to to_array -- 3/2011 2.0 added inside as non protected type -- 6/2011 2.1 added sort as non protected type -- 4/2013 2013.04 No Changes -- 5/2013 2013.05 No changes of substance. -- Deleted extra variable declaration in procedure remove -- 1/2014 2014.01 Added RevSort. Added AllowDuplicate paramter to Add procedure -- 1/2015 2015.01 Changed Assert/Report to Alert -- 11/2016 2016.11 Revised Add. When AllowDuplicate, add a matching value last. -- -- -- -- Copyright (c) 2008 - 2016 by SynthWorks Design Inc. All rights reserved. -- -- Verbatim copies of this source file may be used and -- distributed without restriction. -- -- This source file is free software; you can redistribute it -- and/or modify it under the terms of the ARTISTIC License -- as published by The Perl Foundation; either version 2.0 of -- the License, or (at your option) any later version. -- -- This source is distributed in the hope that it will be -- useful, but WITHOUT ANY WARRANTY; without even the implied -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- PURPOSE. See the Artistic License for details. -- -- You should have received a copy of the license with this source. -- If not download it from, -- http://www.perlfoundation.org/artistic_license_2_0 -- use work.OsvvmGlobalPkg.all ; use work.AlertLogPkg.all ; use std.textio.all ; library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; use ieee.std_logic_textio.all ; -- comment out following 2 lines with VHDL-2008. Leave in for VHDL-2002 -- library ieee_proposed ; -- remove with VHDL-2008 -- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008 package SortListPkg_int is -- with VHDL-2008, convert package to generic package -- convert subtypes ElementType and ArrayofElementType to generics -- package SortListGenericPkg is subtype ElementType is integer ; subtype ArrayofElementType is integer_vector ; impure function inside (constant E : ElementType; constant A : in ArrayofElementType) return boolean ; impure function sort (constant A : in ArrayofElementType) return ArrayofElementType ; impure function revsort (constant A : in ArrayofElementType) return ArrayofElementType ; type SortListPType is protected procedure add ( constant A : in ElementType ; constant AllowDuplicate : Boolean := FALSE ) ; procedure add ( constant A : in ArrayofElementType ) ; procedure add ( constant A : in ArrayofElementType ; Min, Max : ElementType ) ; procedure add ( variable A : inout SortListPType ) ; -- Count items in list impure function count return integer ; impure function find_index ( constant A : ElementType) return integer ; impure function inside (constant A : ElementType) return boolean ; procedure insert ( constant A : in ElementType; constant index : in integer := 1 ) ; impure function get ( constant index : in integer := 1 ) return ElementType ; procedure erase ; impure function Empty return boolean ; procedure print ; procedure remove ( constant A : in ElementType ) ; procedure remove ( constant A : in ArrayofElementType ) ; procedure remove ( variable A : inout SortListPType ) ; impure function to_array (constant EraseList : boolean := FALSE) return ArrayofElementType ; impure function to_rev_array (constant EraseList : boolean := FALSE) return ArrayofElementType ; end protected SortListPType ; end SortListPkg_int ; --- /////////////////////////////////////////////////////////////////////////// --- /////////////////////////////////////////////////////////////////////////// --- /////////////////////////////////////////////////////////////////////////// package body SortListPkg_int is impure function inside (constant E : ElementType; constant A : in ArrayofElementType) return boolean is begin for i in A'range loop if E = A(i) then return TRUE ; end if ; end loop ; return FALSE ; end function inside ; type SortListPType is protected body type ListType ; type ListPointerType is access ListType ; type ListType is record A : ElementType ; -- item_num : integer ; NextPtr : ListPointerType ; -- PrevPtr : ListPointerType ; end record ; variable HeadPointer : ListPointerType := NULL ; -- variable TailPointer : ListPointerType := NULL ; procedure add ( constant A : in ElementType ; constant AllowDuplicate : Boolean := FALSE ) is variable CurPtr, tempPtr : ListPointerType ; begin if HeadPointer = NULL then HeadPointer := new ListType'(A, NULL) ; elsif A = HeadPointer.A then -- ignore duplicates if AllowDuplicate then tempPtr := HeadPointer ; HeadPointer := new ListType'(A, tempPtr) ; end if ; elsif A < HeadPointer.A then tempPtr := HeadPointer ; HeadPointer := new ListType'(A, tempPtr) ; else CurPtr := HeadPointer ; AddLoop : loop exit AddLoop when CurPtr.NextPtr = NULL ; exit AddLoop when A < CurPtr.NextPtr.A ; if A = CurPtr.NextPtr.A then -- if AllowDuplicate then -- changed s.t. insert at after match rather than before -- exit AddLoop ; -- insert -- else if not AllowDuplicate then return ; -- return without insert end if; end if ; CurPtr := CurPtr.NextPtr ; end loop AddLoop ; tempPtr := CurPtr.NextPtr ; CurPtr.NextPtr := new ListType'(A, tempPtr) ; end if ; end procedure add ; procedure add ( constant A : in ArrayofElementType ) is begin for i in A'range loop add(A(i)) ; end loop ; end procedure add ; procedure add ( constant A : in ArrayofElementType ; Min, Max : ElementType ) is begin for i in A'range loop if A(i) >= Min and A(i) <= Max then add(A(i)) ; end if ; end loop ; end procedure add ; procedure add ( variable A : inout SortListPType ) is begin for i in 1 to A.Count loop add(A.Get(i)) ; end loop ; end procedure add ; -- Count items in list impure function count return integer is variable result : positive := 1 ; variable CurPtr : ListPointerType ; begin if HeadPointer = NULL then return 0 ; else CurPtr := HeadPointer ; loop exit when CurPtr.NextPtr = NULL ; result := result + 1 ; CurPtr := CurPtr.NextPtr ; end loop ; return result ; end if ; end function count ; impure function find_index (constant A : ElementType) return integer is variable result : positive := 2 ; variable CurPtr : ListPointerType ; begin if HeadPointer = NULL then return 0 ; elsif A <= HeadPointer.A then return 1 ; else CurPtr := HeadPointer ; loop exit when CurPtr.NextPtr = NULL ; exit when A <= CurPtr.NextPtr.A ; result := result + 1 ; CurPtr := CurPtr.NextPtr ; end loop ; return result ; end if ; end function find_index ; impure function inside (constant A : ElementType) return boolean is variable CurPtr : ListPointerType ; begin if HeadPointer = NULL then return FALSE ; end if ; if A = HeadPointer.A then return TRUE ; else CurPtr := HeadPointer ; loop exit when CurPtr.NextPtr = NULL ; exit when A < CurPtr.NextPtr.A ; if A = CurPtr.NextPtr.A then return TRUE ; -- exit end if; CurPtr := CurPtr.NextPtr ; end loop ; end if ; return FALSE ; end function inside ; procedure insert( constant A : in ElementType; constant index : in integer := 1 ) is variable CurPtr, tempPtr : ListPointerType ; begin if index <= 1 then tempPtr := HeadPointer ; HeadPointer := new ListType'(A, tempPtr) ; else CurPtr := HeadPointer ; for i in 3 to index loop exit when CurPtr.NextPtr = NULL ; -- end of list CurPtr := CurPtr.NextPtr ; end loop ; tempPtr := CurPtr.NextPtr ; CurPtr.NextPtr := new ListType'(A, tempPtr) ; end if; end procedure insert ; impure function get ( constant index : in integer := 1 ) return ElementType is variable CurPtr : ListPointerType ; begin if index > Count then Alert(OSVVM_ALERTLOG_ID, "SortLIstPkg_int.get index out of range", FAILURE) ; return ElementType'left ; elsif HeadPointer = NULL then return ElementType'left ; elsif index <= 1 then return HeadPointer.A ; else CurPtr := HeadPointer ; for i in 2 to index loop CurPtr := CurPtr.NextPtr ; end loop ; return CurPtr.A ; end if; end function get ; procedure erase (variable CurPtr : inout ListPointerType ) is begin if CurPtr.NextPtr /= NULL then erase (CurPtr.NextPtr) ; end if ; deallocate (CurPtr) ; end procedure erase ; procedure erase is begin if HeadPointer /= NULL then erase(HeadPointer) ; -- deallocate (HeadPointer) ; HeadPointer := NULL ; end if; end procedure erase ; impure function Empty return boolean is begin return HeadPointer = NULL ; end Empty ; procedure print is variable buf : line ; variable CurPtr : ListPointerType ; begin if HeadPointer = NULL then write (buf, string'("( )")) ; else CurPtr := HeadPointer ; write (buf, string'("(")) ; loop write (buf, CurPtr.A) ; exit when CurPtr.NextPtr = NULL ; write (buf, string'(", ")) ; CurPtr := CurPtr.NextPtr ; end loop ; write (buf, string'(")")) ; end if ; writeline(OUTPUT, buf) ; end procedure print ; procedure remove ( constant A : in ElementType ) is variable CurPtr, tempPtr : ListPointerType ; begin if HeadPointer = NULL then return ; elsif A = HeadPointer.A then tempPtr := HeadPointer ; HeadPointer := HeadPointer.NextPtr ; deallocate (tempPtr) ; else CurPtr := HeadPointer ; loop exit when CurPtr.NextPtr = NULL ; if A = CurPtr.NextPtr.A then tempPtr := CurPtr.NextPtr ; CurPtr.NextPtr := CurPtr.NextPtr.NextPtr ; deallocate (tempPtr) ; exit ; end if ; exit when A < CurPtr.NextPtr.A ; CurPtr := CurPtr.NextPtr ; end loop ; end if ; end procedure remove ; procedure remove ( constant A : in ArrayofElementType ) is begin for i in A'range loop remove(A(i)) ; end loop ; end procedure remove ; procedure remove ( variable A : inout SortListPType ) is begin for i in 1 to A.Count loop remove(A.Get(i)) ; end loop ; end procedure remove ; impure function to_array (constant EraseList : boolean := FALSE) return ArrayofElementType is variable result : ArrayofElementType(1 to Count) ; begin for i in 1 to Count loop result(i) := Get(i) ; end loop ; if EraseList then erase ; end if ; return result ; end function to_array ; impure function to_rev_array (constant EraseList : boolean := FALSE) return ArrayofElementType is variable result : ArrayofElementType(Count downto 1) ; begin for i in 1 to Count loop result(i) := Get(i) ; end loop ; if EraseList then erase ; end if ; return result ; end function to_rev_array ; end protected body SortListPType ; impure function sort (constant A : in ArrayofElementType) return ArrayofElementType is variable Result : SortListPType ; begin for i in A'range loop Result.Add(A(i), TRUE) ; end loop ; return Result.to_array(EraseList => TRUE) ; end function sort ; impure function revsort (constant A : in ArrayofElementType) return ArrayofElementType is variable Result : SortListPType ; begin for i in A'range loop Result.Add(A(i), TRUE) ; end loop ; return Result.to_rev_array(EraseList => TRUE) ; end function revsort ; end SortListPkg_int ;
gpl-2.0