repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
huxiaolei/xapp1078_2014.4_zybo | design/work/project_2/project_2.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/7820e39a/hdl/src/vhdl/sequence.vhd | 30 | 22215 | -------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence;
architecture imp of sequence is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_eval_cond.vhd | 2 | 1136 | -- Copyright (c) 2016 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and-or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test initial conditional assignment evaluation
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_eval_cond is
port(
input : in std_logic;
output : out std_logic
);
end vhdl_eval_cond;
architecture rtl of vhdl_eval_cond is
begin
output <= '1' when input = '0' else '0';
end rtl;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_generic_default.vhd | 3 | 1104 | -- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for generics without a default value.
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_generic_default is
generic(value : std_logic);
port(a : out std_logic);
end vhdl_generic_default;
architecture test of vhdl_generic_default is
begin
a <= value;
end test;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_nand23_bit.vhd | 4 | 290 | library ieee;
use ieee.numeric_bit.all;
entity nand23 is
port (
a_i : in bit_vector (22 downto 0);
b_i : in bit_vector (22 downto 0);
c_o : out bit_vector (22 downto 0)
);
end entity nand23;
architecture rtl of nand23 is
begin
c_o <= a_i nand b_i;
end architecture rtl;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_notfunc_stdlogic.vhd | 4 | 336 | library ieee;
use ieee.std_logic_1164.all;
entity not_func is
port (
a_i : in std_logic;
c_o : out std_logic
);
end not_func;
architecture rtl of not_func is
function invert (
i : std_logic
) return std_logic is
begin
return not i;
end function invert;
begin
c_o <= invert(a_i);
end architecture rtl;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_test4.vhd | 2 | 492 | --
-- Author: Pawel Szostek ([email protected])
-- Date: 27.07.2011
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dummy is
port (o1: out std_logic_vector(7 downto 0);
o2: out std_logic_vector(7 downto 0);
o3: out std_logic_vector(7 downto 0)
);
end;
architecture behaviour of dummy is
begin
o1 <= (others => '0');
o2 <= (3 => '1', others => '0');
o3 <= (7=>'1', 6|5|4|3|2|1|0 => '0', others => '1'); --tricky
end;
| gpl-2.0 |
huxiaolei/xapp1078_2014.4_zybo | design/work/project_2/project_2.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/7820e39a/hdl/src/vhdl/lpf.vhd | 23 | 17838 | -------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0;
--use lib_cdc_v1_0.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml510/testbench.vhd | 1 | 17763 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2008 Jiri Gaisler, Jan Andersson, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal sysace_fpga_clk : std_ulogic := '0';
signal flash_we_b : std_ulogic;
signal flash_wait : std_ulogic;
signal flash_reset_b : std_ulogic;
signal flash_oe_b : std_ulogic;
signal flash_d : std_logic_vector(15 downto 0);
signal flash_clk : std_ulogic;
signal flash_ce_b : std_ulogic;
signal flash_adv_b : std_logic;
signal flash_a : std_logic_vector(21 downto 0);
signal sram_bw : std_ulogic;
signal sim_d : std_logic_vector(15 downto 0);
signal iosn : std_ulogic;
signal dimm1_ddr2_we_b : std_ulogic;
signal dimm1_ddr2_s_b : std_logic_vector(1 downto 0);
signal dimm1_ddr2_ras_b : std_ulogic;
signal dimm1_ddr2_pll_clkin_p : std_ulogic;
signal dimm1_ddr2_pll_clkin_n : std_ulogic;
signal dimm1_ddr2_odt : std_logic_vector(1 downto 0);
signal dimm1_ddr2_dqs_p : std_logic_vector(8 downto 0);
signal dimm1_ddr2_dqs_n : std_logic_vector(8 downto 0);
signal dimm1_ddr2_dqm : std_logic_vector(8 downto 0);
signal dimm1_ddr2_dq : std_logic_vector(71 downto 0);
signal dimm1_ddr2_dq2 : std_logic_vector(71 downto 0);
signal dimm1_ddr2_cke : std_logic_vector(1 downto 0);
signal dimm1_ddr2_cas_b : std_ulogic;
signal dimm1_ddr2_ba : std_logic_vector(2 downto 0);
signal dimm1_ddr2_a : std_logic_vector(13 downto 0);
signal dimm0_ddr2_we_b : std_ulogic;
signal dimm0_ddr2_s_b : std_logic_vector(1 downto 0);
signal dimm0_ddr2_ras_b : std_ulogic;
signal dimm0_ddr2_pll_clkin_p : std_ulogic;
signal dimm0_ddr2_pll_clkin_n : std_ulogic;
signal dimm0_ddr2_odt : std_logic_vector(1 downto 0);
signal dimm0_ddr2_dqs_p : std_logic_vector(8 downto 0);
signal dimm0_ddr2_dqs_n : std_logic_vector(8 downto 0);
signal dimm0_ddr2_dqm : std_logic_vector(8 downto 0);
signal dimm0_ddr2_dq : std_logic_vector(71 downto 0);
signal dimm0_ddr2_dq2 : std_logic_vector(71 downto 0);
signal dimm0_ddr2_cke : std_logic_vector(1 downto 0);
signal dimm0_ddr2_cas_b : std_ulogic;
signal dimm0_ddr2_ba : std_logic_vector(2 downto 0);
signal dimm0_ddr2_a : std_logic_vector(13 downto 0);
signal phy0_txer : std_ulogic;
signal phy0_txd : std_logic_vector(3 downto 0);
signal phy0_txctl_txen : std_ulogic;
signal phy0_txclk : std_ulogic;
signal phy0_rxer : std_ulogic;
signal phy0_rxd : std_logic_vector(3 downto 0);
signal phy0_rxctl_rxdv : std_ulogic;
signal phy0_rxclk : std_ulogic;
signal phy0_reset : std_ulogic;
signal phy0_mdio : std_logic;
signal phy0_mdc : std_ulogic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_mpd : std_logic_vector(15 downto 0);
signal dbg_led : std_logic_vector(3 downto 0);
signal opb_bus_error : std_ulogic;
signal plb_bus_error : std_ulogic;
signal dvi_xclk_p : std_ulogic;
signal dvi_xclk_n : std_ulogic;
signal dvi_v : std_ulogic;
signal dvi_reset_b : std_ulogic;
signal dvi_h : std_ulogic;
signal dvi_gpio1 : std_logic;
signal dvi_de : std_ulogic;
signal dvi_d : std_logic_vector(11 downto 0);
signal pci_p_trdy_b : std_logic;
signal pci_p_stop_b : std_logic;
signal pci_p_serr_b : std_logic;
signal pci_p_rst_b : std_logic;
signal pci_p_req_b : std_logic_vector(0 to 4);
signal pci_p_perr_b : std_logic;
signal pci_p_par : std_logic;
signal pci_p_lock_b : std_logic;
signal pci_p_irdy_b : std_logic;
signal pci_p_intd_b : std_logic;
signal pci_p_intc_b : std_logic;
signal pci_p_intb_b : std_logic;
signal pci_p_inta_b : std_logic;
signal pci_p_gnt_b : std_logic_vector(0 to 4);
signal pci_p_frame_b : std_logic;
signal pci_p_devsel_b : std_logic;
signal pci_p_clk5_r : std_ulogic;
signal pci_p_clk5 : std_ulogic;
signal pci_p_clk4_r : std_ulogic;
signal pci_p_clk3_r : std_ulogic;
signal pci_p_clk1_r : std_ulogic;
signal pci_p_clk0_r : std_ulogic;
signal pci_p_cbe_b : std_logic_vector(3 downto 0);
signal pci_p_ad : std_logic_vector(31 downto 0);
--signal pci_fpga_idsel : std_ulogic;
signal sbr_pwg_rsm_rstj : std_logic;
signal sbr_nmi_r : std_ulogic;
signal sbr_intr_r : std_ulogic;
signal sbr_ide_rst_b : std_logic;
signal iic_sda_dvi : std_logic;
signal iic_scl_dvi : std_logic;
signal fpga_sda : std_logic;
signal fpga_scl : std_logic;
signal iic_therm_b : std_ulogic;
signal iic_reset_b : std_ulogic;
signal iic_irq_b : std_ulogic;
signal iic_alert_b : std_ulogic;
signal spi_data_out : std_logic;
signal spi_data_in : std_logic;
signal spi_data_cs_b : std_ulogic;
signal spi_clk : std_ulogic;
signal uart1_txd : std_ulogic;
signal uart1_rxd : std_ulogic;
signal uart1_rts_b : std_ulogic;
signal uart1_cts_b : std_ulogic;
signal uart0_txd : std_ulogic;
signal uart0_rxd : std_ulogic;
signal uart0_rts_b : std_ulogic;
--signal uart0_cts_b : std_ulogic;
--signal test_mon_vrefp : std_ulogic;
signal test_mon_vp0_p : std_ulogic;
signal test_mon_vn0_n : std_ulogic;
--signal test_mon_avdd : std_ulogic;
signal data : std_logic_vector(31 downto 0);
signal phy0_rxdl : std_logic_vector(7 downto 0);
signal phy0_txdl : std_logic_vector(7 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
sysace_fpga_clk <= not sysace_fpga_clk after 15 ns;
pci_p_clk5 <= pci_p_clk5_r;
flash_wait <= 'L';
phy0_txdl <= "0000" & phy0_txd; phy0_rxd <= phy0_rxdl(3 downto 0);
sysace_mpd <= (others => 'H'); sysace_mpirq <= 'L';
dbg_led <= (others => 'H');
dvi_gpio1 <= 'H';
pci_p_trdy_b <= 'H'; pci_p_stop_b <= 'H';
pci_p_serr_b <= 'H'; pci_p_rst_b <= 'H';
pci_p_req_b <= (others => 'H'); pci_p_perr_b <= 'H';
pci_p_par <= 'H'; pci_p_lock_b <= 'H';
pci_p_irdy_b <= 'H'; pci_p_intd_b <= 'H';
pci_p_intc_b <= 'H'; pci_p_intb_b <= 'H';
pci_p_inta_b <= 'H'; pci_p_gnt_b <= (others => 'H');
pci_p_frame_b <= 'H'; pci_p_devsel_b <= 'H';
pci_p_cbe_b <= (others => 'H'); pci_p_ad <= (others => 'H');
-- pci_fpga_idsel <= 'H';
sbr_pwg_rsm_rstj <= 'H'; sbr_nmi_r <= 'H';
sbr_intr_r <= 'L'; sbr_ide_rst_b <= 'H';
iic_sda_dvi <= 'H'; iic_scl_dvi <= 'H';
fpga_sda <= 'H'; fpga_scl <= 'H';
iic_therm_b <= 'L'; iic_irq_b <= 'L'; iic_alert_b <= 'L';
spi_data_out <= 'H';
uart1_rxd <= 'H'; uart1_cts_b <= uart1_rts_b;
uart0_rxd <= 'H'; --uart0_cts_b <= uart0_rts_b;
test_mon_vp0_p <= 'H'; test_mon_vn0_n <= 'H';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map (sys_rst_in, sys_clk, sysace_fpga_clk,
-- Flash
flash_we_b, flash_wait, flash_reset_b, flash_oe_b,
flash_d, flash_clk, flash_ce_b, flash_adv_b, flash_a,
sram_bw, sim_d, iosn,
-- DDR2 slot 1
dimm1_ddr2_we_b, dimm1_ddr2_s_b, dimm1_ddr2_ras_b,
dimm1_ddr2_pll_clkin_p, dimm1_ddr2_pll_clkin_n,
dimm1_ddr2_odt, dimm1_ddr2_dqs_p, dimm1_ddr2_dqs_n,
dimm1_ddr2_dqm, dimm1_ddr2_dq, dimm1_ddr2_cke,
dimm1_ddr2_cas_b, dimm1_ddr2_ba, dimm1_ddr2_a,
-- DDR2 slot 0
dimm0_ddr2_we_b, dimm0_ddr2_s_b, dimm0_ddr2_ras_b,
dimm0_ddr2_pll_clkin_p, dimm0_ddr2_pll_clkin_n,
dimm0_ddr2_odt, dimm0_ddr2_dqs_p, dimm0_ddr2_dqs_n,
dimm0_ddr2_dqm, dimm0_ddr2_dq, dimm0_ddr2_cke,
dimm0_ddr2_cas_b, dimm0_ddr2_ba, dimm0_ddr2_a,
open,
-- Ethernet PHY
phy0_txer, phy0_txd, phy0_txctl_txen, phy0_txclk,
phy0_rxer, phy0_rxd, phy0_rxctl_rxdv, phy0_rxclk,
phy0_reset, phy0_mdio, phy0_mdc,
-- System ACE MPU
sysace_mpa, sysace_mpce, sysace_mpirq, sysace_mpoe,
sysace_mpwe, sysace_mpd,
-- GPIO/Green LEDs
dbg_led,
-- Red/Green LEDs
opb_bus_error, plb_bus_error,
-- LCD
-- fpga_lcd_rw, fpga_lcd_rs, fpga_lcd_e, fpga_lcd_db,
-- DVI
dvi_xclk_p, dvi_xclk_n, dvi_v, dvi_reset_b, dvi_h,
dvi_gpio1, dvi_de, dvi_d,
-- PCI
pci_p_trdy_b, pci_p_stop_b, pci_p_serr_b, pci_p_rst_b,
pci_p_req_b, pci_p_perr_b, pci_p_par, pci_p_lock_b,
pci_p_irdy_b, pci_p_intd_b, pci_p_intc_b, pci_p_intb_b,
pci_p_inta_b, pci_p_gnt_b, pci_p_frame_b, pci_p_devsel_b,
pci_p_clk5_r, pci_p_clk5, pci_p_clk4_r, pci_p_clk3_r,
pci_p_clk1_r, pci_p_clk0_r, pci_p_cbe_b, pci_p_ad,
-- pci_fpga_idsel,
sbr_pwg_rsm_rstj, sbr_nmi_r, sbr_intr_r, sbr_ide_rst_b,
-- IIC/SMBus and sideband signals
iic_sda_dvi, iic_scl_dvi, fpga_sda, fpga_scl, iic_therm_b,
iic_reset_b, iic_irq_b, iic_alert_b,
-- SPI
spi_data_out, spi_data_in, spi_data_cs_b, spi_clk,
-- UARTs
uart1_txd, uart1_rxd, uart1_rts_b, uart1_cts_b,
uart0_txd, uart0_rxd, uart0_rts_b--, --uart0_cts_b
-- System monitor
-- test_mon_vp0_p, test_mon_vn0_n
);
-- ddr2mem0: for i in 0 to (1 + 2*(CFG_DDR2SP_DATAWIDTH/64)) generate
-- u1 : HY5PS121621F
-- generic map (TimingCheckFlag => true, PUSCheckFlag => false,
-- index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i, bbits => CFG_DDR2SP_DATAWIDTH,
-- fname => sdramfile, fdelay => 0)
-- port map (DQ => dimm0_ddr2_dq2(i*16+15+32*(32/CFG_DDR2SP_DATAWIDTH) downto i*16+32*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQS => dimm0_ddr2_dqs_p(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQSB => dimm0_ddr2_dqs_n(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQS => dimm0_ddr2_dqs_p(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQSB => dimm0_ddr2_dqs_n(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDM => dimm0_ddr2_dqm(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- WEB => dimm0_ddr2_we_b, CASB => dimm0_ddr2_cas_b,
-- RASB => dimm0_ddr2_ras_b, CSB => dimm0_ddr2_s_b(0),
-- BA => dimm0_ddr2_ba(1 downto 0), ADDR => dimm0_ddr2_a(12 downto 0),
-- CKE => dimm0_ddr2_cke(0), CLK => dimm0_ddr2_pll_clkin_p,
-- CLKB => dimm0_ddr2_pll_clkin_n,
-- UDM => dimm0_ddr2_dqm(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)));
-- end generate;
ddr2mem0 : ddr2ram
generic map(width => CFG_DDR2SP_DATAWIDTH, abits => 14, babits => 3, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => dimm0_ddr2_pll_clkin_p, ckn => dimm0_ddr2_pll_clkin_n,
cke => dimm0_ddr2_cke(0), csn => dimm0_ddr2_s_b(0),
odt => gnd, rasn => dimm0_ddr2_ras_b,
casn => dimm0_ddr2_cas_b, wen => dimm0_ddr2_we_b,
dm => dimm0_ddr2_dqm(7 downto 8-CFG_DDR2SP_DATAWIDTH/8), ba => dimm0_ddr2_ba,
a => dimm0_ddr2_a, dq => dimm0_ddr2_dq2(63 downto 64-CFG_DDR2SP_DATAWIDTH),
dqs => dimm0_ddr2_dqs_p(7 downto 8-CFG_DDR2SP_DATAWIDTH/8),
dqsn =>dimm0_ddr2_dqs_n(7 downto 8-CFG_DDR2SP_DATAWIDTH/8));
-- ddr2mem1: for i in 0 to (1 + 2*(CFG_DDR2SP_DATAWIDTH/64)) generate
-- u1 : HY5PS121621F
-- generic map (TimingCheckFlag => true, PUSCheckFlag => false,
-- index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i, bbits => CFG_DDR2SP_DATAWIDTH,
-- fname => sdramfile, fdelay => 0)
-- port map (DQ => dimm1_ddr2_dq2(i*16+15+32*(32/CFG_DDR2SP_DATAWIDTH) downto i*16+32*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQS => dimm1_ddr2_dqs_p(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQSB => dimm1_ddr2_dqs_n(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQS => dimm1_ddr2_dqs_p(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQSB => dimm1_ddr2_dqs_n(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDM => dimm1_ddr2_dqm(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- WEB => dimm1_ddr2_we_b, CASB => dimm1_ddr2_cas_b,
-- RASB => dimm1_ddr2_ras_b, CSB => dimm1_ddr2_s_b(0),
-- BA => dimm1_ddr2_ba(1 downto 0), ADDR => dimm1_ddr2_a(12 downto 0),
-- CKE => dimm1_ddr2_cke(0), CLK => dimm1_ddr2_pll_clkin_p,
-- CLKB => dimm1_ddr2_pll_clkin_n,
-- UDM => dimm1_ddr2_dqm(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)));
-- end generate;
ddr2mem1 : ddr2ram
generic map(width => CFG_DDR2SP_DATAWIDTH, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => dimm1_ddr2_pll_clkin_p, ckn => dimm1_ddr2_pll_clkin_n,
cke => dimm1_ddr2_cke(0), csn => dimm1_ddr2_s_b(0),
odt => gnd, rasn => dimm1_ddr2_ras_b,
casn => dimm1_ddr2_cas_b, wen => dimm1_ddr2_we_b,
dm => dimm1_ddr2_dqm(CFG_DDR2SP_DATAWIDTH/8-1 downto 0), ba => dimm1_ddr2_ba(1 downto 0),
a => dimm1_ddr2_a(12 downto 0), dq => dimm1_ddr2_dq2(CFG_DDR2SP_DATAWIDTH-1 downto 0),
dqs => dimm1_ddr2_dqs_p(CFG_DDR2SP_DATAWIDTH/8-1 downto 0),
dqsn =>dimm1_ddr2_dqs_n(CFG_DDR2SP_DATAWIDTH/8-1 downto 0));
ddr2delay0 : delay_wire
generic map(data_width => dimm0_ddr2_dq'length, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => dimm0_ddr2_dq, b => dimm0_ddr2_dq2);
ddr2delay1 : delay_wire
generic map(data_width => dimm1_ddr2_dq'length, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => dimm1_ddr2_dq, b => dimm1_ddr2_dq2);
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (flash_a(romdepth-1 downto 0), flash_d(15 downto 0),
gnd, gnd, flash_ce_b, flash_we_b, flash_oe_b);
phy0_mdio <= 'H';
p0: phy
generic map (address => 7)
port map(phy0_reset, phy0_mdio, phy0_txclk, phy0_rxclk, phy0_rxdl,
phy0_rxctl_rxdv, phy0_rxer, open, open, phy0_txdl,
phy0_txctl_txen, phy0_txer, phy0_mdc, '0');
i0: i2c_slave_model
port map (iic_scl_dvi, iic_sda_dvi);
i1: i2c_slave_model
port map (fpga_scl, fpga_sda);
iuerr : process
begin
wait for 5000 ns;
if to_x01(opb_bus_error) = '0' then wait on opb_bus_error; end if;
assert (to_x01(opb_bus_error) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= flash_d & sim_d;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, opb_bus_error, flash_a(20 downto 1), data,
iosn, flash_oe_b, sram_bw, open);
flash_d <= buskeep(flash_d), (others => 'H') after 250 ns;
data <= buskeep(data), (others => 'H') after 250 ns;
end ;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/arith/mul32.vhd | 1 | 15088 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mul
-- File: mul.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implements signed/unsigned 32-bit multiply module,
-- producing a 64-bit result.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.multlib.all;
library gaisler;
use gaisler.arith.all;
library techmap;
use techmap.gencomp.all;
entity mul32 is
generic (
tech : integer := 0;
multype : integer range 0 to 3 := 0;
pipe : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
arch : integer range 0 to 3 := 0;
scantest: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
muli : in mul32_in_type;
mulo : out mul32_out_type;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1'
);
end;
architecture rtl of mul32 is
--attribute sync_set_reset : string;
--attribute sync_set_reset of rst : signal is "true";
constant m16x16 : integer := 0;
constant m32x8 : integer := 1;
constant m32x16 : integer := 2;
constant m32x32 : integer := 3;
constant MULTIPLIER : integer := multype;
constant MULPIPE : boolean := ((multype = 0) or (multype = 3)) and (pipe = 1);
constant MACEN : boolean := (multype = 0) and (mac = 1);
type mul_regtype is record
acc : std_logic_vector(63 downto 0);
state : std_logic_vector(1 downto 0);
start : std_logic;
ready : std_logic;
nready : std_logic;
end record;
type mac_regtype is record
mmac, xmac : std_logic;
msigned, xsigned : std_logic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant MULRES : mul_regtype := (
acc => (others => '0'),
state => (others => '0'),
start => '0',
ready => '0',
nready => '0');
constant MACRES : mac_regtype := (
mmac => '0',
xmac => '0',
msigned => '0',
xsigned => '0');
signal arst : std_ulogic;
signal rm, rmin : mul_regtype;
signal mm, mmin : mac_regtype;
signal ma, mb : std_logic_vector(32 downto 0);
signal prod : std_logic_vector(65 downto 0);
signal mreg : std_logic_vector(49 downto 0);
signal vcc : std_logic;
begin
vcc <= '1';
arst <= testrst when (ASYNC_RESET and scantest/=0 and testen/='0') else
rst when ASYNC_RESET else
'1';
mulcomb : process(rst, rm, muli, mreg, prod, mm)
variable mop1, mop2 : std_logic_vector(32 downto 0);
variable acc, acc1, acc2 : std_logic_vector(48 downto 0);
variable zero, rsigned, rmac : std_logic;
variable v : mul_regtype;
variable w : mac_regtype;
constant CZero: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
begin
v := rm; w := mm; v.start := muli.start; v.ready := '0'; v.nready := '0';
mop1 := muli.op1; mop2 := muli.op2;
acc1 := (others => '0'); acc2 := (others => '0'); zero := '0';
w.mmac := muli.mac; w.xmac := mm.mmac;
w.msigned := muli.signed; w.xsigned := mm.msigned;
if MULPIPE then rsigned := mm.xsigned; rmac := mm.xmac;
else rsigned := mm.msigned; rmac := mm.mmac; end if;
-- select input 2 to accumulator
case MULTIPLIER is
when m16x16 =>
acc2(32 downto 0) := mreg(32 downto 0);
when m32x8 =>
acc2(40 downto 0) := mreg(40 downto 0);
when m32x16 =>
acc2(48 downto 0) := mreg(48 downto 0);
when others => null;
end case;
-- state machine + inputs to multiplier and accumulator input 1
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
if MULPIPE and (rm.ready = '1' ) then
acc1(32 downto 0) := rm.acc(48 downto 16);
else acc1(32 downto 0) := '0' & rm.acc(63 downto 32); end if;
when m32x8 =>
mop1 := muli.op1;
mop2(8 downto 0) := '0' & muli.op2(7 downto 0);
acc1(40 downto 0) := '0' & rm.acc(63 downto 24);
when m32x16 =>
mop1 := muli.op1;
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
acc1(48 downto 0) := '0' & rm.acc(63 downto 16);
when others => null;
end case;
if (rm.start = '1') then v.state := "01"; end if;
when "01" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := '0' & muli.op2(15 downto 0);
if MULPIPE then acc1(32 downto 0) := '0' & rm.acc(63 downto 32); end if;
v.state := "10";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(15 downto 8);
v.state := "10";
when m32x16 =>
mop1 := muli.op1; mop2(16 downto 0) := muli.op2(32 downto 16);
v.state := "00";
when others => null;
end case;
when "10" =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := '0' & muli.op1(15 downto 0);
mop2(16 downto 0) := muli.op2(32 downto 16);
if MULPIPE then acc1 := (others => '0'); acc2 := (others => '0');
else acc1(32 downto 0) := rm.acc(48 downto 16); end if;
v.state := "11";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := '0' & muli.op2(23 downto 16);
acc1(40 downto 0) := rm.acc(48 downto 8);
v.state := "11";
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
mop1(16 downto 0) := muli.op1(32 downto 16);
mop2(16 downto 0) := muli.op2(32 downto 16);
if MULPIPE then acc1(32 downto 0) := rm.acc(48 downto 16);
else acc1(32 downto 0) := rm.acc(48 downto 16); end if;
v.state := "00";
when m32x8 =>
mop1 := muli.op1; mop2(8 downto 0) := muli.op2(32 downto 24);
acc1(40 downto 0) := rm.acc(56 downto 16);
v.state := "00";
when others => null;
end case;
end case;
-- optional UMAC/SMAC support
if MACEN then
if ((muli.mac and muli.signed) = '1') then
mop1(16) := muli.op1(15); mop2(16) := muli.op2(15);
end if;
if rmac = '1' then
acc1(32 downto 0) := muli.acc(32 downto 0);--muli.y(0) & muli.asr18;
if rsigned = '1' then acc2(39 downto 32) := (others => mreg(31));
else acc2(39 downto 32) := (others => '0'); end if;
end if;
acc1(39 downto 33) := muli.acc(39 downto 33);--muli.y(7 downto 1);
end if;
-- accumulator for iterative multiplication (and MAC)
-- pragma translate_off
if not (is_x(acc1 & acc2)) then
-- pragma translate_on
case MULTIPLIER is
when m16x16 =>
if MACEN then
acc(39 downto 0) := acc1(39 downto 0) + acc2(39 downto 0);
else
acc(32 downto 0) := acc1(32 downto 0) + acc2(32 downto 0);
end if;
when m32x8 =>
acc(40 downto 0) := acc1(40 downto 0) + acc2(40 downto 0);
when m32x16 =>
acc(48 downto 0) := acc1(48 downto 0) + acc2(48 downto 0);
when m32x32 =>
v.acc(31 downto 0) := prod(63 downto 32);
when others => null;
end case;
-- pragma translate_off
end if;
-- pragma translate_on
-- save intermediate result to accumulator
case rm.state is
when "00" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE and (rm.ready = '1' ) then
v.acc(48 downto 16) := acc(32 downto 0);
if rsigned = '1' then
v.acc(63 downto 49) := (others => acc(32));
end if;
else
v.acc(63 downto 32) := acc(31 downto 0);
end if;
when m32x8 => v.acc(63 downto 24) := acc(39 downto 0);
when m32x16 => v.acc(63 downto 16) := acc(47 downto 0);
when others => null;
end case;
when "01" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then v.acc := (others => '0');
else v.acc := CZero(31 downto 0) & mreg(31 downto 0); end if;
when m32x8 =>
v.acc := CZero(23 downto 0) & mreg(39 downto 0);
if muli.signed = '1' then v.acc(48 downto 40) := (others => acc(40)); end if;
when m32x16 =>
v.acc := CZero(15 downto 0) & mreg(47 downto 0); v.ready := '1';
if muli.signed = '1' then v.acc(63 downto 48) := (others => acc(48)); end if;
when others => null;
end case;
v.nready := '1';
when "10" =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then
v.acc := CZero(31 downto 0) & mreg(31 downto 0);
else
v.acc(48 downto 16) := acc(32 downto 0);
end if;
when m32x8 => v.acc(48 downto 8) := acc(40 downto 0);
if muli.signed = '1' then v.acc(56 downto 49) := (others => acc(40)); end if;
when others => null;
end case;
when others =>
case MULTIPLIER is
when m16x16 =>
if MULPIPE then
v.acc(48 downto 16) := acc(32 downto 0);
else
v.acc(48 downto 16) := acc(32 downto 0);
if rsigned = '1' then
v.acc(63 downto 49) := (others => acc(32));
end if;
end if;
v.ready := '1';
when m32x8 => v.acc(56 downto 16) := acc(40 downto 0); v.ready := '1';
if muli.signed = '1' then v.acc(63 downto 57) := (others => acc(40)); end if;
when others => null;
end case;
end case;
-- drive result and condition codes
if (muli.flush = '1') then v.state := "00"; v.start := '0'; end if;
if (not ASYNC_RESET) and (not RESET_ALL) and (rst = '0') then
v.nready := MULRES.nready; v.ready := MULRES.ready;
v.state := MULRES.state; v.start := MULRES.start;
end if;
rmin <= v; ma <= mop1; mb <= mop2; mmin <= w;
if MULPIPE then mulo.ready <= rm.ready; mulo.nready <= rm.nready;
else mulo.ready <= v.ready; mulo.nready <= v.nready; end if;
case MULTIPLIER is
when m16x16 =>
if rm.acc(31 downto 0) = CZero(31 downto 0) then zero := '1'; end if;
if MACEN and (rmac = '1') then
mulo.result(39 downto 0) <= acc(39 downto 0);
if rsigned = '1' then
mulo.result(63 downto 40) <= (others => acc(39));
else
mulo.result(63 downto 40) <= (others => '0');
end if;
else
mulo.result(39 downto 0) <= v.acc(39 downto 32) & rm.acc(31 downto 0);
mulo.result(63 downto 40) <= v.acc(63 downto 40);
end if;
mulo.icc <= rm.acc(31) & zero & "00";
when m32x8 =>
if (rm.acc(23 downto 0) = CZero(23 downto 0)) and
(v.acc(31 downto 24) = CZero(7 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 24) & rm.acc(23 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x16 =>
if (rm.acc(15 downto 0) = CZero(15 downto 0)) and
(v.acc(31 downto 16) = CZero(15 downto 0))
then zero := '1'; end if;
mulo.result <= v.acc(63 downto 16) & rm.acc(15 downto 0);
mulo.icc <= v.acc(31) & zero & "00";
when m32x32 =>
-- mulo.result <= rm.acc(31 downto 0) & prod(31 downto 0);
mulo.result <= prod(63 downto 0);
mulo.icc(1 downto 0) <= "00";
if prod(31 downto 0) = zero32 then mulo.icc(2) <= '1' ;
else mulo.icc(2) <= '0'; end if;
mulo.icc(3) <= prod(31);
when others => null;
mulo.result <= (others => '-');
mulo.icc <= (others => '-');
end case;
end process;
xm1616 : if MULTIPLIER = m16x16 generate
m1616 : techmult generic map (tech, arch, 17, 17, pipe+1, pipe)
port map (ma(16 downto 0), mb(16 downto 0), clk, holdn, vcc, prod(33 downto 0));
syncrregs : if not ASYNC_RESET generate
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
mm <= mmin;
mreg(33 downto 0) <= prod(33 downto 0);
end if;
if RESET_ALL and (rst = '0') then
mm <= MACRES;
mreg(33 downto 0) <= (others => '0');
end if;
end if;
end process;
end generate syncrregs;
asyncrregs : if ASYNC_RESET generate
reg : process(clk, arst)
begin
if (arst = '0') then
mm <= MACRES;
mreg(33 downto 0) <= (others => '0');
elsif rising_edge(clk) then
if (holdn = '1') then
mm <= mmin;
mreg(33 downto 0) <= prod(33 downto 0);
end if;
end if;
end process;
end generate asyncrregs;
mreg(49 downto 34) <= (others => '0');
prod(65 downto 34) <= (others => '0');
end generate;
xm3208 : if MULTIPLIER = m32x8 generate
m3208 : techmult generic map (tech, arch, 33, 8, 2, 1)
port map (ma(32 downto 0), mb(8 downto 0), clk, holdn, vcc, mreg(41 downto 0));
mm <= ('0', '0', '0', '0');
mreg(49 downto 42) <= (others => '0');
prod <= (others => '0');
end generate;
xm3216 : if MULTIPLIER = m32x16 generate
m3216 : techmult generic map (tech, arch, 33, 17, 2, 1)
port map (ma(32 downto 0), mb(16 downto 0), clk, holdn, vcc, mreg(49 downto 0));
mm <= ('0', '0', '0', '0');
prod <= (others => '0');
end generate;
xm3232 : if MULTIPLIER = m32x32 generate
m3232 : techmult generic map (tech, arch, 33, 33, pipe+1, pipe)
port map (ma(32 downto 0), mb(32 downto 0), clk, holdn, vcc, prod(65 downto 0));
mm <= ('0', '0', '0', '0');
mreg <= (others => '0');
end generate;
syncrregs : if not ASYNC_RESET generate
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') then rm <= rmin; end if;
if (rst = '0') then
if RESET_ALL then
rm <= MULRES;
else
rm.nready <= MULRES.nready; rm.ready <= MULRES.ready;
rm.state <= MULRES.state; rm.start <= MULRES.start;
end if;
end if;
end if;
end process;
end generate syncrregs;
asyncrregs : if ASYNC_RESET generate
reg : process(clk, arst)
begin
if (arst = '0') then
rm <= MULRES;
elsif rising_edge(clk) then
if (holdn = '1') then rm <= rmin; end if;
end if;
end process;
end generate asyncrregs;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ac701/config.vhd | 1 | 7403 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := artix7;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (8);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 0;
constant CFG_MIG_RANKS : integer := 1;
constant CFG_MIG_COLBITS : integer := 10;
constant CFG_MIG_ROWBITS : integer := 13;
constant CFG_MIG_BANKBITS: integer := 2;
constant CFG_MIG_HMASK : integer := 16#F00#;
-- Xilinx MIG Series 7
constant CFG_MIG_SERIES7 : integer := 1;
constant CFG_MIG_SERIES7_MODEL : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 32;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (7);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (8);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/srmmu/mmu.vhd | 1 | 20753 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: MMU
-- File: mmu.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: Leon3 MMU top level entity
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmu is
generic (
tech : integer range 0 to NTECH := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
mmudci : in mmudc_in_type;
mmudco : out mmudc_out_type;
mmuici : in mmuic_in_type;
mmuico : out mmuic_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type;
ramcclk : in std_ulogic := '0';
ramcin : in std_logic_vector(2*ramcbits-1 downto 0) := (others => '0');
ramcout : out std_logic_vector(2*ramcbits-1 downto 0)
);
end mmu;
architecture rtl of mmu is
constant MMUCTX_BITS : integer := M_CTX_SZ;
constant M_TLB_TYPE : integer range 0 to 1 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(1,2)); -- eather split or combined
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
type mmu_op is record
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
end record;
constant mmu_op_none : mmu_op := ('0', '0', '0');
type mmu_cmbpctrl is record
tlbowner : mmu_idcache;
tlbactive : std_logic;
op : mmu_op;
end record;
constant mmu_cmbpctrl_none : mmu_cmbpctrl := (id_icache, '0', mmu_op_none);
type mmu_rtype is record
cmb_s1 : mmu_cmbpctrl;
cmb_s2 : mmu_cmbpctrl;
splt_is1 : mmu_cmbpctrl;
splt_is2 : mmu_cmbpctrl;
splt_ds1 : mmu_cmbpctrl;
splt_ds2 : mmu_cmbpctrl;
twactive : std_logic; -- split tlb
twowner : mmu_idcache; -- split tlb
flush : std_logic;
mmctrl2 : mmctrl_type2;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : mmu_rtype := (
cmb_s1 => mmu_cmbpctrl_none,
cmb_s2 => mmu_cmbpctrl_none,
splt_is1 => mmu_cmbpctrl_none,
splt_is2 => mmu_cmbpctrl_none,
splt_ds1 => mmu_cmbpctrl_none,
splt_ds2 => mmu_cmbpctrl_none,
twactive => '0',
twowner => id_icache,
flush => '0',
mmctrl2 => mmctrl2_zero);
signal r, c : mmu_rtype;
-- tlb
component mmutlb
generic (
tech : integer range 0 to NTECH := 0;
entries : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
tlbi : in mmutlb_in_type;
tlbo : out mmutlb_out_type;
two : in mmutw_out_type;
twi : out mmutw_in_type;
ramcclk: in std_ulogic;
ramcin : in std_logic_vector(ramcbits-1 downto 0);
ramcout: out std_logic_vector(ramcbits-1 downto 0)
);
end component;
signal tlbi_a0 : mmutlb_in_type;
signal tlbi_a1 : mmutlb_in_type;
signal tlbo_a0 : mmutlb_out_type;
signal tlbo_a1 : mmutlb_out_type;
signal twi_a : mmutwi_a(1 downto 0);
signal two_a : mmutwo_a(1 downto 0);
-- table walk
component mmutw
generic (
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mmctrl1 : in mmctrl_type1;
twi : in mmutw_in_type;
two : out mmutw_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end component;
signal twi : mmutw_in_type;
signal two : mmutw_out_type;
signal mmctrl1 : mmctrl_type1;
begin
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
p0: process (rst, r, mmudci, mmuici, mcmmo, tlbo_a0, tlbo_a1, tlbi_a0, tlbi_a1, two_a, twi_a, two)
variable cmbtlbin : mmuidc_data_in_type;
variable cmbtlbout : mmutlb_out_type;
variable spltitlbin : mmuidc_data_in_type;
variable spltdtlbin : mmuidc_data_in_type;
variable spltitlbout : mmutlb_out_type;
variable spltdtlbout : mmutlb_out_type;
variable mmuico_transdata : mmuidc_data_out_type;
variable mmudco_transdata : mmuidc_data_out_type;
variable mmuico_grant : std_logic;
variable mmudco_grant : std_logic;
variable v : mmu_rtype;
variable twiv : mmutw_in_type;
variable twod, twoi : mmutw_out_type;
variable fault : mmutlbfault_out_type;
variable wbtransdata : mmuidc_data_out_type;
variable fs : mmctrl_fs_type;
variable fa : std_logic_vector(VA_I_SZ-1 downto 0);
begin
v := r;
wbtransdata.finish := '0';
wbtransdata.data := (others => '0');
wbtransdata.cache := '0';
wbtransdata.accexc := '0';
if (M_TLB_TYPE = 0) and (M_TLB_FASTWRITE /= 0) then
wbtransdata := tlbo_a1.wbtransdata;
end if;
cmbtlbin.data := (others => '0');
cmbtlbin.su := '0';
cmbtlbin.read := '0';
cmbtlbin.isid := id_dcache;
cmbtlbout.transdata.finish := '0';
cmbtlbout.transdata.data := (others => '0');
cmbtlbout.transdata.cache := '0';
cmbtlbout.transdata.accexc := '0';
cmbtlbout.fault.fault_pro := '0';
cmbtlbout.fault.fault_pri := '0';
cmbtlbout.fault.fault_access := '0';
cmbtlbout.fault.fault_mexc := '0';
cmbtlbout.fault.fault_trans := '0';
cmbtlbout.fault.fault_inv := '0';
cmbtlbout.fault.fault_lvl := (others => '0');
cmbtlbout.fault.fault_su := '0';
cmbtlbout.fault.fault_read := '0';
cmbtlbout.fault.fault_isid := id_dcache;
cmbtlbout.fault.fault_addr := (others => '0');
cmbtlbout.nexttrans := '0';
cmbtlbout.s1finished := '0';
mmuico_transdata.finish := '0';
mmuico_transdata.data := (others => '0');
mmuico_transdata.cache := '0';
mmuico_transdata.accexc := '0';
mmudco_transdata.finish := '0';
mmudco_transdata.data := (others => '0');
mmudco_transdata.cache := '0';
mmudco_transdata.accexc := '0';
mmuico_grant := '0';
mmudco_grant := '0';
twiv.walk_op_ur := '0';
twiv.areq_ur := '0';
twiv.data := (others => '0');
twiv.adata := (others => '0');
twiv.aaddr := (others => '0');
twod.finish := '0';
twod.data := (others => '0');
twod.addr := (others => '0');
twod.lvl := (others => '0');
twod.fault_mexc := '0';
twod.fault_trans := '0';
twod.fault_inv := '0';
twod.fault_lvl := (others => '0');
twoi.finish := '0';
twoi.data := (others => '0');
twoi.addr := (others => '0');
twoi.lvl := (others => '0');
twoi.fault_mexc := '0';
twoi.fault_trans := '0';
twoi.fault_inv := '0';
twoi.fault_lvl := (others => '0');
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
fault.fault_lvl := (others => '0');
fault.fault_su := '0';
fault.fault_read := '0';
fault.fault_isid := id_dcache;
fault.fault_addr := (others => '0');
fs.ow := '0';
fs.fav := '0';
fs.ft := (others => '0');
fs.at_ls := '0';
fs.at_id := '0';
fs.at_su := '0';
fs.l := (others => '0');
fs.ebe := (others => '0');
fa := (others => '0');
if M_TLB_TYPE = 0 then
spltitlbout := tlbo_a0;
spltdtlbout := tlbo_a1;
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
spltdtlbin := mmudci.transdata;
spltitlbin := mmuici.transdata;
mmudco_transdata := spltdtlbout.transdata;
mmuico_transdata := spltitlbout.transdata;
-- d-tlb
if ((not r.splt_ds1.tlbactive) or spltdtlbout.s1finished) = '1' then
v.splt_ds1.tlbactive := '0';
v.splt_ds1.op.trans_op := '0';
v.splt_ds1.op.flush_op := '0';
if mmudci.trans_op = '1' then
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
v.flush := '1';
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.flush_op := '1';
end if;
end if;
-- i-tlb
if ((not r.splt_is1.tlbactive) or spltitlbout.s1finished) = '1' then
v.splt_is1.tlbactive := '0';
v.splt_is1.op.trans_op := '0';
v.splt_is1.op.flush_op := '0';
if v.flush = '1' then
v.flush := '0';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.flush_op := '1';
elsif mmuici.trans_op = '1' then
mmuico_grant := '1';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.trans_op := '1';
end if;
end if;
if spltitlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
fault := spltitlbout.fault;
end if;
if spltdtlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
if (spltdtlbout.fault.fault_mexc or
spltdtlbout.fault.fault_trans or
spltdtlbout.fault.fault_inv or
spltdtlbout.fault.fault_pro or
spltdtlbout.fault.fault_pri or
spltdtlbout.fault.fault_access) = '1' then
fault := spltdtlbout.fault; -- overwrite icache fault
end if;
end if;
if spltitlbout.s1finished = '1' then
v.splt_is2 := r.splt_is1;
end if;
if spltdtlbout.s1finished = '1' then
v.splt_ds2 := r.splt_ds1;
end if;
if ( r.splt_is2.op.flush_op ) = '1' then
mmuico_transdata.finish := '0';
end if;
-- share tw
if two.finish = '1' then
v.twactive := '0';
end if;
if r.twowner = id_icache then
twiv := twi_a(0);
twoi.finish := two.finish;
else
twiv := twi_a(1);
twod.finish := two.finish;
end if;
if (v.twactive) = '0' then
if (twi_a(1).areq_ur or twi_a(1).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_dcache;
elsif (twi_a(0).areq_ur or twi_a(0).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_icache;
end if;
end if;
else
--# combined i/d cache: 1 tlb, 1 tw
-- share one tlb among i and d cache
cmbtlbout := tlbo_a0;
mmuico_grant := '0'; mmudco_grant := '0';
mmuico_transdata.finish := '0'; mmudco_transdata.finish := '0';
twiv := twi_a(0);
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
-- twod.finish := two.finish;
twoi.finish := two.finish;
if ((not v.cmb_s1.tlbactive) or cmbtlbout.s1finished) = '1' then
v.cmb_s1.tlbactive := '0';
v.cmb_s1.op.trans_op := '0';
v.cmb_s1.op.flush_op := '0';
if (mmudci.trans_op or mmudci.flush_op or mmuici.trans_op) = '1' then
v.cmb_s1.tlbactive := '1';
end if;
if mmuici.trans_op = '1' then
mmuico_grant := '1';
v.cmb_s1.tlbowner := id_icache;
v.cmb_s1.op.trans_op := '1';
elsif mmudci.trans_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.flush_op := '1';
end if;
end if;
if (r.cmb_s1.tlbactive and not r.cmb_s2.tlbactive) = '1' then
end if;
if cmbtlbout.s1finished = '1' then
v.cmb_s2 := r.cmb_s1;
end if;
if r.cmb_s1.tlbowner = id_dcache then
cmbtlbin := mmudci.transdata;
else
cmbtlbin := mmuici.transdata;
end if;
if r.cmb_s2.tlbowner = id_dcache then
mmudco_transdata := cmbtlbout.transdata;
else
mmuico_transdata := cmbtlbout.transdata;
end if;
if cmbtlbout.transdata.finish = '1' and (r.cmb_s2.op.flush_op = '0') then
fault := cmbtlbout.fault;
end if;
end if;
-- # fault status register
if (mmudci.fsread) = '1' then
v.mmctrl2.valid := '0'; v.mmctrl2.fs.fav := '0';
end if;
if (fault.fault_mexc) = '1' then
fs.ft := FS_FT_TRANS;
elsif (fault.fault_trans) = '1' then
fs.ft := FS_FT_INV;
elsif (fault.fault_inv) = '1' then
fs.ft := FS_FT_INV;
elsif (fault.fault_pri) = '1' then
fs.ft := FS_FT_PRI;
elsif (fault.fault_pro) = '1' then
fs.ft := FS_FT_PRO;
elsif (fault.fault_access) = '1' then
fs.ft := FS_FT_BUS;
else
fs.ft := FS_FT_NONE;
end if;
fs.ow := '0';
fs.l := fault.fault_lvl;
if fault.fault_isid = id_dcache then
fs.at_id := '0';
else
fs.at_id := '1';
end if;
fs.at_su := fault.fault_su;
fs.at_ls := not fault.fault_read;
fs.fav := '1';
fs.ebe := (others => '0');
fa := fault.fault_addr(VA_I_U downto VA_I_D);
if (fault.fault_mexc or
fault.fault_trans or
fault.fault_inv or
fault.fault_pro or
fault.fault_pri or
fault.fault_access) = '1' then
--# priority
if v.mmctrl2.valid = '1'then
if (fault.fault_mexc) = '1' then
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
if (r.mmctrl2.fs.ft /= FS_FT_INV) then
if fault.fault_isid = id_dcache then
-- dcache
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
-- icache
if (not r.mmctrl2.fs.at_id) = '0' then
fs.ow := '1';
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
end if;
end if;
end if;
end if;
else
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
v.mmctrl2.valid := '1';
end if;
if (fault.fault_isid) = id_dcache then
mmudco_transdata.accexc := '1';
else
mmuico_transdata.accexc := '1';
end if;
end if;
-- # reset
if ( not RESET_ALL ) and ( rst = '0' ) then
if M_TLB_TYPE = 0 then
v.splt_is1.tlbactive := RRES.splt_is1.tlbactive;
v.splt_is2.tlbactive := RRES.splt_is2.tlbactive;
v.splt_ds1.tlbactive := RRES.splt_ds1.tlbactive;
v.splt_ds2.tlbactive := RRES.splt_ds2.tlbactive;
v.splt_is1.op.trans_op := RRES.splt_is1.op.trans_op;
v.splt_is2.op.trans_op := RRES.splt_is2.op.trans_op;
v.splt_ds1.op.trans_op := RRES.splt_ds1.op.trans_op;
v.splt_ds2.op.trans_op := RRES.splt_ds2.op.trans_op;
v.splt_is1.op.flush_op := RRES.splt_is1.op.flush_op;
v.splt_is2.op.flush_op := RRES.splt_is2.op.flush_op;
v.splt_ds1.op.flush_op := RRES.splt_ds1.op.flush_op;
v.splt_ds2.op.flush_op := RRES.splt_ds2.op.flush_op;
else
v.cmb_s1.tlbactive := RRES.cmb_s1.tlbactive;
v.cmb_s2.tlbactive := RRES.cmb_s2.tlbactive;
v.cmb_s1.op.trans_op := RRES.cmb_s1.op.trans_op;
v.cmb_s2.op.trans_op := RRES.cmb_s2.op.trans_op;
v.cmb_s1.op.flush_op := RRES.cmb_s1.op.flush_op;
v.cmb_s2.op.flush_op := RRES.cmb_s2.op.flush_op;
end if;
v.flush := RRES.flush;
v.mmctrl2.valid := RRES.mmctrl2.valid;
v.twactive := RRES.twactive;
v.twowner := RRES.twowner;
end if;
-- drive signals
if M_TLB_TYPE = 0 then
tlbi_a0.trans_op <= r.splt_is1.op.trans_op;
tlbi_a0.flush_op <= r.splt_is1.op.flush_op;
tlbi_a0.transdata <= spltitlbin;
tlbi_a0.s2valid <= r.splt_is2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
tlbi_a1.trans_op <= r.splt_ds1.op.trans_op;
tlbi_a1.flush_op <= r.splt_ds1.op.flush_op;
tlbi_a1.transdata <= spltdtlbin;
tlbi_a1.s2valid <= r.splt_ds2.tlbactive;
tlbi_a1.mmctrl1 <= mmudci.mmctrl1;
tlbi_a1.wb_op <= mmudci.wb_op;
else
tlbi_a0.trans_op <= r.cmb_s1.op.trans_op;
tlbi_a0.flush_op <= r.cmb_s1.op.flush_op;
tlbi_a0.transdata <= cmbtlbin;
tlbi_a0.s2valid <= r.cmb_s2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
end if;
tlbi_a0.testin <= mmudci.testin;
tlbi_a1.testin <= mmudci.testin;
mmudco.transdata <= mmudco_transdata;
mmuico.transdata <= mmuico_transdata;
mmudco.grant <= mmudco_grant;
mmuico.grant <= mmuico_grant;
mmuico.tlbmiss <= twi_a(0).tlbmiss;
mmudco.mmctrl2 <= r.mmctrl2;
mmudco.wbtransdata <= wbtransdata;
twi <= twiv;
two_a(0) <= twoi;
two_a(1) <= twod;
mmctrl1 <= mmudci.mmctrl1;
c <= v;
end process p0;
tlbcomb0: if M_TLB_TYPE = 1 generate
-- i/d tlb
ctlb0 : mmutlb
generic map ( tech, M_ENT_C, 0, tlb_rep, mmupgsz, ramcbits )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0),
ramcclk, ramcin(ramcbits-1 downto 0), ramcout(ramcbits-1 downto 0));
mmudco.tlbmiss <= twi_a(0).tlbmiss;
ramcout(2*ramcbits-1 downto ramcbits) <= (others => '0');
end generate tlbcomb0;
tlbsplit0: if M_TLB_TYPE = 0 generate
-- i tlb
itlb0 : mmutlb
generic map ( tech, M_ENT_I, 0, tlb_rep, mmupgsz, ramcbits )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0),
ramcclk, ramcin(ramcbits-1 downto 0), ramcout(ramcbits-1 downto 0));
-- d tlb
dtlb0 : mmutlb
generic map ( tech, M_ENT_D, tlb_type, tlb_rep, mmupgsz, ramcbits )
port map (rst, clk, tlbi_a1, tlbo_a1, two_a(1), twi_a(1),
ramcclk, ramcin(2*ramcbits-1 downto ramcbits), ramcout(2*ramcbits-1 downto ramcbits));
mmudco.tlbmiss <= twi_a(1).tlbmiss;
end generate tlbsplit0;
-- table walk component
tw0 : mmutw
generic map ( mmupgsz )
port map (rst, clk, mmctrl1, twi, two, mcmmo, mcmmi);
-- pragma translate_off
chk : process
begin
assert not ((M_TLB_TYPE = 1) and (M_TLB_FASTWRITE /= 0)) report
"Fast writebuffer only supported for combined cache"
severity failure;
wait;
end process;
-- pragma translate_on
end rtl;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/ahbram.vhd | 1 | 9173 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbram
-- File: ahbram.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity ahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbram is
constant abits : integer := log2ext(kbytes) + 8 - maccsz/64;
constant dw : integer := maccsz;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2+maccsz/64, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits-1+log2(dw/8) downto 0);
size : std_logic_vector(2 downto 0);
prdata : std_logic_vector((dw-1)*pipe downto 0);
pwrite : std_ulogic;
pready : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type :=
(hwrite => '0', hready => '1', hsel => '0', addr => (others => '0'),
size => (others => '0'), prdata => (others => '0'), pwrite => '0',
pready => '1');
signal r, c : reg_type;
signal ramsel : std_logic_vector(dw/8-1 downto 0);
signal write : std_logic_vector(dw/8-1 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(dw-1 downto 0);
signal hwdata : std_logic_vector(dw-1 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(dw/8-1 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
variable hrdata : std_logic_vector(dw-1 downto 0);
variable seldata : std_logic_vector(dw-1 downto 0);
variable raddr : std_logic_vector(3 downto 2);
variable adsel : std_logic;
begin
v := r; v.hready := '1'; bs := (others => '0');
v.pready := r.hready;
if pipe=0 then
adsel := r.hwrite or not r.hready;
else
adsel := r.hwrite or r.pwrite;
v.hready := r.hready or not r.pwrite;
end if;
if adsel = '1' then
haddr := r.addr(abits-1+log2(dw/8) downto log2(dw/8));
else
haddr := ahbsi.haddr(abits-1+log2(dw/8) downto log2(dw/8));
bs := (others => '0');
end if;
raddr := (others => '0');
v.pwrite := '0';
if pipe/=0 and (r.hready='1' or r.pwrite='0') then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
if ahbsi.hready = '1' then
if pipe=0 then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.size := ahbsi.hsize(2 downto 0);
v.hwrite := ahbsi.hwrite and v.hsel;
if pipe = 1 and v.hsel = '1' and ahbsi.hwrite = '0' and (r.pready='1' or ahbsi.htrans(0)='0') then
v.hready := '0';
v.pwrite := r.hwrite;
end if;
end if;
if r.hwrite = '1' then
case r.size is
when HSIZE_BYTE =>
bs(bs'left-conv_integer(r.addr(log2(dw/16) downto 0))) := '1';
when HSIZE_HWORD =>
for i in 0 to dw/16-1 loop
if i = conv_integer(r.addr(log2(dw/16) downto 1)) then
bs(bs'left-i*2 downto bs'left-i*2-1) := (others => '1');
end if;
end loop; -- i
when HSIZE_WORD =>
if dw = 32 then bs := (others => '1');
else
for i in 0 to dw/32-1 loop
if i = conv_integer(r.addr(log2(dw/8)-1 downto 2)) then
bs(bs'left-i*4 downto bs'left-i*4-3) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_DWORD =>
if dw = 32 then null;
elsif dw = 64 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_4WORD =>
if dw < 128 then null;
elsif dw = 128 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when others => --HSIZE_8WORD
if dw < 256 then null;
else bs := (others => '1'); end if;
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
-- Duplicate read data on word basis, unless CORE_ACDM is enabled
if CORE_ACDM = 0 then
if dw = 32 then
seldata := ramdata;
elsif dw = 64 then
if r.size = HSIZE_DWORD then seldata := ramdata; else
if r.addr(2) = '0' then
seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else
seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0);
end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
end if;
elsif dw = 128 then
if r.size = HSIZE_4WORD then
seldata := ramdata;
elsif r.size = HSIZE_DWORD then
if r.addr(3) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
else
raddr := r.addr(3 downto 2);
case raddr is
when "00" => seldata(dw/4-1 downto 0) := ramdata(4*dw/4-1 downto 3*dw/4);
when "01" => seldata(dw/4-1 downto 0) := ramdata(3*dw/4-1 downto 2*dw/4);
when "10" => seldata(dw/4-1 downto 0) := ramdata(2*dw/4-1 downto 1*dw/4);
when others => seldata(dw/4-1 downto 0) := ramdata(dw/4-1 downto 0);
end case;
seldata(dw-1 downto dw/4) := seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0);
end if;
else
seldata := ahbselectdata(ramdata, r.addr(4 downto 2), r.size);
end if;
else
seldata := ramdata;
end if;
if pipe = 0 then
v.prdata := (others => '0');
hrdata := seldata;
else
v.prdata := seldata;
hrdata := r.prdata;
end if;
if (not RESET_ALL) and (rst = '0') then
v.hwrite := RES.hwrite; v.hready := RES.hready;
end if;
write <= bs; for i in 0 to dw/8-1 loop ramsel(i) <= v.hsel or r.hwrite; end loop;
ramaddr <= haddr; c <= v;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hready <= r.hready;
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
-- Select correct write data
hwdata <= ahbreaddata(ahbsi.hwdata, r.addr(4 downto 2),
conv_std_logic_vector(log2(dw/8), 3));
aram : syncrambw generic map (tech, abits, dw, scantest) port map (
clk, ramaddr, hwdata, ramdata, ramsel, write, ahbsi.testin);
reg : process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/outpad.vhd | 1 | 5685 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad
-- File: outpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity outpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of outpad is
signal padx, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
gen0 : if has_pads(tech) = 0 generate
pad <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when slew = 0 else i;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
um : if (tech = umc) generate
x0 : umc_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
saed : if (tech = saed32) generate
x0 : saed32_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
dar : if (tech = dare) generate
x0 : dare_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength) port map (padx, i, gnd, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, vcc);
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, vcc);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_outpad generic map (level, slew, voltage, strength)
port map(pad, i, cfgi(0), cfgi(1),
cfgi(19 downto 15), cfgi(14 downto 10), cfgi(9 downto 6), cfgi(5 downto 2));
end generate;
ut90nhbd : if (tech = ut90) generate
x0 : ut90nhbd_outpad generic map (level, slew, voltage, strength)
port map(pad, i, cfgi(0));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity outpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12; width : integer := 1);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of outpadv is
begin
v : for j in width-1 downto 0 generate
x0 : outpad generic map (tech, level, slew, voltage, strength)
port map (pad(j), i(j), cfgi);
end generate;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/cycloneiii/alt/adqsout.vhd | 3 | 5194 | library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic; -- gnd = disable
dqs_pad : out std_logic; -- DQS pad
dqsn_pad : out std_logic -- DQSN pad
);
end;
architecture rtl of adqsout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component cycloneiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component cycloneiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
port(
i : in std_logic := '0';
oe : in std_logic := '1';
--devoe : in std_logic := '1';
o : out std_logic;
obar : out std_logic--;
--seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dqs_reg, dqs_buf, dqsn_buf, dqs_oe_n : std_logic;
signal dqs_oe_reg, dqs_oe_reg_n, dqs_oct_reg : std_logic;
signal dqsn_oe_reg, dqsn_oe_reg_n, dqsn_oct_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQS output register --------------------------------------------------------------
dqs_reg0 : cycloneiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => dqs,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Outout enable and DQS ------------------------------------------------------------
-- ****** ????????? invert dqs_oe also ??????
dqs_oe_n <= not dqs_oe;
dqs_oe_reg0 : cycloneiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqs_oe_reg_n <= not dqs_oe_reg;
-- Out buffer (DQS) -----------------------------------------------------------------
dqs_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => dqs_reg,
oe => dqs_oe_reg_n,
--devoe => vcc,
o => dqs_pad,
obar => open
--seriesterminationcontrol => gnd,
);
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep3c25-eek/leon3mp.vhd | 1 | 34070 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2008 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.i2c.all;
use gaisler.spi.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- flash/ssram bus
address : out std_logic_vector(25 downto 1);
data : inout std_logic_vector(31 downto 0);
romsn : out std_ulogic;
oen : out std_logic;
writen : out std_logic;
rstoutn : out std_ulogic;
ssram_cen : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (0 to 3);
ssram_oen : out std_ulogic;
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
-- ssram_adsp_n : out std_ulogic;
-- ssram_adv_n : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
-- DDR
ddr_clk : out std_logic;
ddr_clkn : out std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- I/O port
gpio : in std_logic_vector(CFG_GRGPIO_WIDTH-3 downto 0);
-- Connections over HSMC connector
-- LCD touch panel display
hc_vd : out std_logic;
hc_hd : out std_logic;
hc_den : out std_logic;
hc_nclk : out std_logic;
hc_lcd_data : out std_logic_vector(7 downto 0);
hc_grest : out std_logic;
hc_scen : out std_logic;
hc_sda : inout std_logic;
hc_adc_penirq_n : in std_logic;
hc_adc_dout : in std_logic;
hc_adc_busy : in std_logic;
hc_adc_din : out std_logic;
hc_adc_dclk : out std_logic;
hc_adc_cs_n : out std_logic; -- Shared with video decoder
-- Shared by video decoder and audio codec
hc_i2c_sclk : out std_logic;
hc_i2c_sdat : inout std_logic;
-- Video decoder
hc_td_d : inout std_logic_vector(7 downto 0);
hc_td_hs : in std_logic;
hc_td_vs : in std_logic;
hc_td_27mhz : in std_logic;
hc_td_reset : out std_logic;
-- Audio codec
hc_aud_adclrck : out std_logic;
hc_aud_adcdat : in std_logic;
hc_aud_daclrck : out std_logic;
hc_aud_dacdat : out std_logic;
hc_aud_bclk : out std_logic;
hc_aud_xck : out std_logic;
-- SD card
hc_sd_dat : inout std_logic;
hc_sd_dat3 : inout std_logic;
hc_sd_cmd : inout std_logic;
hc_sd_clk : inout std_logic;
-- Ethernet PHY
hc_tx_d : out std_logic_vector(3 downto 0);
hc_rx_d : in std_logic_vector(3 downto 0);
hc_tx_clk : in std_logic;
hc_rx_clk : in std_logic;
hc_tx_en : out std_logic;
hc_rx_dv : in std_logic;
hc_rx_crs : in std_logic;
hc_rx_err : in std_logic;
hc_rx_col : in std_logic;
hc_mdio : inout std_logic;
hc_mdc : out std_logic;
hc_eth_reset_n : out std_logic;
-- RX232 (console/debug UART)
hc_uart_rxd : in std_logic;
hc_uart_txd : out std_logic;
-- PS/2
hc_ps2_dat : inout std_logic;
hc_ps2_clk : inout std_logic;
-- VGA/DAC
hc_vga_data : out std_logic_vector(9 downto 0);
hc_vga_clock : out std_ulogic;
hc_vga_hs : out std_ulogic;
hc_vga_vs : out std_ulogic;
hc_vga_blank : out std_ulogic;
hc_vga_sync : out std_ulogic;
-- I2C EEPROM
hc_id_i2cscl : out std_logic;
hc_id_i2cdat : inout std_logic
);
end;
architecture rtl of leon3mp is
component serializer
generic (
length : integer := 8 -- vector length
);
port (
clk : in std_ulogic;
sync : in std_ulogic;
ivec0 : in std_logic_vector((length-1) downto 0);
ivec1 : in std_logic_vector((length-1) downto 0);
ivec2 : in std_logic_vector((length-1) downto 0);
ovec : out std_logic_vector((length-1) downto 0)
);
end component;
component altera_eek_clkgen
generic (
clk0_mul : integer := 1;
clk0_div : integer := 1;
clk1_mul : integer := 1;
clk1_div : integer := 1;
clk_freq : integer := 25000);
port (
inclk0 : in std_ulogic;
clk0 : out std_ulogic;
clk0x3 : out std_ulogic;
clksel : in std_logic_vector(1 downto 0);
locked : out std_ulogic);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+
CFG_SVGA_ENABLE+CFG_GRETH;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rawrstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal ps2i : ps2_in_type;
signal ps2o : ps2_out_type;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal lcdo : apbvga_out_type;
signal lcd_data : std_logic_vector(7 downto 0);
signal lcd_den : std_ulogic;
signal lcd_grest : std_ulogic;
signal lcdspii : spi_in_type;
signal lcdspio : spi_out_type;
signal lcdslvsel : std_logic_vector(1 downto 0);
signal lcdclksel : std_logic_vector(1 downto 0);
signal lcdclk : std_ulogic;
signal lcdclk3x : std_ulogic;
signal lcdclklck : std_ulogic;
signal vgao : apbvga_out_type;
signal vga_data : std_logic_vector(9 downto 0);
signal vgaclksel : std_logic_vector(1 downto 0);
signal vgaclk : std_ulogic;
signal vgaclk3x : std_ulogic;
signal vgaclklck : std_ulogic;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
signal lclk, lclkout : std_ulogic;
signal dsubre : std_ulogic;
attribute syn_keep : boolean;
attribute syn_keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of lcdclk : signal is true;
attribute syn_keep of lcdclk3x : signal is true;
attribute syn_keep of vgaclk : signal is true;
attribute syn_keep of vgaclk3x : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock and lcdclklck and vgaclklck;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => 1,
freq => freq)
port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => ssram_clkl, pciclk => open,
cgi => cgi, cgo => cgo);
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn, rawrstn);
rstoutn <= resetn;
----------------------------------------------------------------------
--- AVOID BUS CONTENTION --------------------------------------------
----------------------------------------------------------------------
-- This design uses the ethernet PHY and we must therefore disable the
-- video decoder and stay away from the touch panel.
-- Video coder
hc_td_reset <= '0'; -- Video Decoder Reset
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (hc_uart_rxd, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (hc_uart_txd, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 :mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
sden => 0, ram16 => 1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
ssr0 : if CFG_SSCTRL = 1 generate
ssrctrl0 : ssrctrl generic map (hindex => 0, pindex => 0,
iomask => 0, ramaddr => 16#400#+16#600#*CFG_DDRSP,
bus16 => CFG_SSCTRLP16)
port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo(0), memi, memo);
end generate;
mg0 : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(25 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
-- ssram_adv_n_pad : outpad generic map (tech => padtech)
-- port map (ssram_adv_n, vcc(0));
-- ssram_adsp_n_pad : outpad generic map (tech => padtech)
-- port map (ssram_adsp_n, gnd(0));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, gnd(0));
ssrams_pad : outpad generic map ( tech => padtech)
port map (ssram_cen, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.oen);
ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.wrn);
ssram_wri_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 32)
port map (data(31 downto 0), memo.data(31 downto 0),
memo.vbdrive, memi.data(31 downto 0));
end generate;
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16, regoutput => 1)
port map (
resetn, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, open, gnd(0),
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
ddrsp1 : if (CFG_DDRSP = 0) generate
ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
end generate;
spimc: if CFG_SPIMCTRL = 1 generate -- SPI Memory Controller
spimctrl0 : spimctrl
generic map (hindex => 4,
hirq => 7,
faddr => 16#b00#,
fmask => 16#f00#,
ioaddr => 16#002#,
iomask => 16#fff#,
spliten => CFG_SPLIT,
oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(4), spmi, spmo);
miso_pad : inpad generic map (tech => padtech)
port map (hc_sd_dat, spmi.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (hc_sd_cmd, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (hc_sd_clk, spmo.sck);
slvsel0_pad : iopad generic map (tech => padtech)
port map (hc_sd_dat3, spmo.csn, spmo.cdcsnoen, spmi.cd);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
upads : if CFG_AHB_UART = 0 generate
u1i.rxd <= hc_uart_rxd; hc_uart_txd <= u1o.txd;
end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- Timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-3 generate
gpioi.din(i) <= gpio(i);
end generate;
gpioi.din(3) <= hc_adc_penirq_n;
gpioi.din(4) <= hc_adc_busy;
end generate;
ps2 : if CFG_PS2_ENABLE /= 0 generate -- PS/2 unit
ps20 : apbps2 generic map(pindex => 6, paddr => 6, pirq => 6)
port map(rstn, clkm, apbi, apbo(6), ps2i, ps2o);
end generate;
nops2 : if CFG_PS2_ENABLE = 0 generate
apbo(4) <= apb_none; ps2o <= ps2o_none;
end generate;
ps2clk_pad : iopad generic map (tech => padtech)
port map (hc_ps2_clk, ps2o.ps2_clk_o, ps2o.ps2_clk_oe, ps2i.ps2_clk_i);
ps2data_pad : iopad generic map (tech => padtech)
port map (hc_ps2_dat, ps2o.ps2_data_o, ps2o.ps2_data_oe, ps2i.ps2_data_i);
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 8, paddr => 8, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(8), i2ci, i2co);
-- The EEK does not use a bi-directional line for the I2C clock
i2ci.scl <= i2co.scloen; -- No clock stretch possible
-- When SCL output enable is activated the line should go low
i2c_scl_pad : outpad generic map (tech => padtech)
port map (hc_id_i2cscl, i2co.scloen);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (hc_id_i2cdat, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 7,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 1,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
miso_pad : iopad generic map (tech => padtech)
port map (hc_sd_dat, spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (hc_sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (hc_sd_clk, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (hc_sd_dat3, slvsel(0));
spii.spisel <= '1'; -- Master only
end generate spic;
-----------------------------------------------------------------------
-- LCD touch panel ---------------------------------------------------
-----------------------------------------------------------------------
lcd: if CFG_LCD_ENABLE /= 0 generate -- LCD
lcd0 : svgactrl generic map(memtech => memtech, pindex => 11, paddr => 11,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 30120, clk1 => 0, clk2 => 0, clk3 => 0, burstlen => 4)
port map(rstn, clkm, lcdclk, apbi, apbo(11), lcdo, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
lcdser0: serializer generic map (length => 8)
port map (lcdclk3x, lcdo.hsync, lcdo.video_out_b, lcdo.video_out_g,
lcdo.video_out_r, lcd_data);
lcdclksel <= "00";
lcdclkgen : altera_eek_clkgen
generic map (clk0_mul => 166, clk0_div => 250, clk1_mul => 9,
clk1_div => 50, clk_freq => BOARD_FREQ)
port map (lclk, lcdclk, lcdclk3x, lcdclksel, lcdclklck);
lcd_vert_sync_pad : outpad generic map (tech => padtech)
port map (hc_vd, lcdo.vsync);
lcd_horiz_sync_pad : outpad generic map (tech => padtech)
port map (hc_hd, lcdo.hsync);
lcd_video_out_pad : outpadv generic map (width => 8, tech => padtech)
port map (hc_lcd_data, lcd_data);
lcd_video_clock_pad : outpad generic map (tech => padtech)
port map (hc_nclk, lcdclk3x);
lcd_den <= lcdo.blank;
end generate;
nolcd : if CFG_LCD_ENABLE = 0 generate
apbo(11) <= apb_none; lcdo <= vgao_none;
lcd_den <= '0'; -- LCD RGB Data Enable
lcdclk <= '0'; lcdclk3x <= '0'; lcdclklck <= '1';
end generate;
lcd_den_pad : outpad generic map (tech => padtech)
port map (hc_den, lcd_den);
lcdsysreset: if CFG_LCD_ENABLE /= 0 or CFG_LCD3T_ENABLE /= 0 generate
lcd_grest <= rstn;
end generate;
lcdalwaysreset: if CFG_LCD_ENABLE = 0 and CFG_LCD3T_ENABLE = 0 generate
lcd_grest <= '0';
end generate lcdalwaysreset;
lcd_reset_pad : outpad generic map (tech => padtech) -- LCD Global Reset, active low
port map (hc_grest, lcd_grest);
touch3wire: if CFG_LCD3T_ENABLE /= 0 generate -- LCD 3-wire and touch panel interface
-- TODO:
-- Interrupt and busy signals not connected
touch3spi1 : spictrl
generic map (pindex => 12, paddr => 12, pmask => 16#fff#, pirq => 12,
fdepth => 2, slvselen => 1, slvselsz => 2, odmode => 0,
syncram => 0, ft => 0)
port map (rstn, clkm, apbi, apbo(12), lcdspii, lcdspio, lcdslvsel);
adc_miso_pad : inpad generic map (tech => padtech)
port map (hc_adc_dout, lcdspii.miso);
adc_mosi_pad : outpad generic map (tech => padtech)
port map (hc_adc_din, lcdspio.mosi);
lcd_adc_dclk_pad : outpad generic map (tech => padtech)
port map (hc_adc_dclk, lcdspio.sck);
hcd_sda_pad : iopad generic map (tech => padtech)
port map (hc_sda, lcdspio.mosi, lcdspio.mosioen, lcdspii.mosi);
lcdspii.spisel <= '1'; -- Master only
end generate;
notouch3wire: if CFG_LCD3T_ENABLE = 0 generate
lcdslvsel <= (others => '1');
apbo(12) <= apb_none;
end generate;
hc_adc_cs_n_pad : outpad generic map (tech => padtech)
port map (hc_adc_cs_n, lcdslvsel(0));
hc_scen_pad : outpad generic map (tech => padtech)
port map (hc_scen, lcdslvsel(1));
-----------------------------------------------------------------------
-- SVGA controller ----------------------------------------------------
-----------------------------------------------------------------------
svga : if CFG_SVGA_ENABLE /= 0 generate -- VGA DAC
svga0 : svgactrl generic map(memtech => memtech, pindex => 13, paddr => 13,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE,
clk0 => 40000, clk1 => 25000, clk2 => 0, clk3 => 0, burstlen => 4)
port map(rstn, clkm, vgaclk, apbi, apbo(13), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE),
vgaclksel);
svgaser0: serializer generic map (length => 8)
port map (vgaclk3x, vgao.hsync, vgao.video_out_b, vgao.video_out_g,
vgao.video_out_r, vga_data(9 downto 2));
vga_data(1 downto 0) <= (others => '0');
vgaclkgen : altera_eek_clkgen
generic map (clk0_mul => 1, clk0_div => 2, clk1_mul => 4,
clk1_div => 5, clk_freq => BOARD_FREQ)
port map (lclk, vgaclk, vgaclk3x, vgaclksel, vgaclklck);
vga_blank_pad : outpad generic map (tech => padtech)
port map (hc_vga_blank, vgao.blank);
vga_comp_sync_pad : outpad generic map (tech => padtech)
port map (hc_vga_sync, vgao.comp_sync);
vga_vert_sync_pad : outpad generic map (tech => padtech)
port map (hc_vga_vs, vgao.vsync);
vga_horiz_sync_pad : outpad generic map (tech => padtech)
port map (hc_vga_hs, vgao.hsync);
vga_video_out_pad : outpadv generic map (width => 10, tech => padtech)
port map (hc_vga_data, vga_data);
vga_video_clock_pad : outpad generic map (tech => padtech)
port map (hc_vga_clock, vgaclk3x);
end generate svga;
nosvga : if CFG_SVGA_ENABLE = 0 generate
apbo(13) <= apb_none; vgao <= vgao_none;
vgaclk <= '0'; vgaclk3x <= '0'; vgaclklck <= '1';
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH /= 0 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE,
pindex => 10, paddr => 10, pirq => 10, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(10), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (hc_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (hc_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (hc_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (hc_rx_d, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (hc_rx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (hc_rx_err, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (hc_rx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (hc_rx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (hc_tx_d, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (hc_tx_en, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (hc_mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (hc_eth_reset_n, rawrstn);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE+CFG_GRETH) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera Embedded Evaluation Kit Demonstration Design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/jtag/ahbjtag_bsd.vhd | 1 | 3337 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbjtag
-- File: ahbjtag.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: JTAG communication link with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use gaisler.libjtagcom.all;
use gaisler.jtag.all;
entity ahbjtag_bsd is
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
asel : in std_ulogic;
dsel : in std_ulogic;
tck : in std_ulogic;
regi : in std_ulogic;
shift : in std_ulogic;
rego : out std_ulogic
);
end;
architecture struct of ahbjtag_bsd is
-- Set REREAD to 1 to include support for re-read operation when host reads
-- out data register before jtagcom has completed the current AMBA access and
-- returned to state 'shft'.
constant REREAD : integer := 1;
constant REVISION : integer := REREAD;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal ltapi : tap_in_type;
signal ltapo : tap_out_type;
signal trst: std_ulogic;
begin
ahbmst0 : ahbmst
generic map (hindex => hindex, venid => VENDOR_GAISLER, devid => GAISLER_AHBJTAG, version => REVISION)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
jtagcom0 : jtagcom generic map (isel => 1, nsync => nsync, ainst => ainst, dinst => dinst, reread => REREAD)
port map (rst, clk, ltapo, ltapi, dmao, dmai, tck, trst);
ltapo.asel <= asel;
ltapo.dsel <= dsel;
ltapo.tck <= tck;
ltapo.tdi <= regi;
ltapo.shift <= shift;
ltapo.reset <= '0';
ltapo.inst <= (others => '0');
rego <= ltapi.tdo;
trst <= '1';
-- pragma translate_off
bootmsg : report_version
generic map ("ahbjtag AHB Debug JTAG rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/grlib/sparc/sparc_disas.vhd | 1 | 27693 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: sparc_disas
-- File: sparc_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.testlib.print;
use std.textio.all;
package sparc_disas is
function tostf(v:std_logic_vector) return string;
procedure print_insn(ndx: integer; pc, op, res : std_logic_vector(31 downto 0);
valid, trap, wr, rest : boolean);
procedure print_fpinsn(ndx: integer; pc, op : std_logic_vector(31 downto 0);
res : std_logic_vector(63 downto 0);
dpres, valid, trap, wr : boolean);
function ins2st(pc, op : std_logic_vector(31 downto 0)) return string;
end;
package body sparc_disas is
type base_type is (hex, dec);
subtype nibble is std_logic_vector(3 downto 0);
type pc_op_type is record
pc, op : std_logic_vector(31 downto 0);
end record;
function tostd(v:std_logic_vector) return string;
function tosth(v:std_logic_vector) return string;
function tostrd(n:integer) return string;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
type carr is array (0 to 9) of character;
constant darr : carr := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
function tostd(v:std_logic_vector) return string is
variable s : string(1 to 2);
variable val : integer;
begin
val := conv_integer(v); s(1) := darr(val / 10); s(2) := darr(val mod 10);
return(s);
end;
function tosth(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return(s);
end;
function tostf(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return("0x" & s);
end;
function tostrd(n:integer) return string is
variable len : integer := 0;
variable tmp : string(10 downto 1);
variable v : integer := n;
begin
for i in 0 to 9 loop
tmp(i+1) := darr(v mod 10);
if tmp(i+1) /= '0' then
len := i;
end if;
v := v/10;
end loop;
return(tmp(len+1 downto 1));
end;
function ireg2st(v : std_logic_vector) return string is
variable ctmp : character;
variable reg : std_logic_vector(4 downto 0);
begin
reg := v;
case reg(4 downto 3) is
when "00" => ctmp := 'g'; when "01" => ctmp := 'o';
when "10" => ctmp := 'l'; when "11" => ctmp := 'i';
when others => ctmp := 'X';
end case;
if v(4 downto 0) = "11110" then return("%fp");
elsif v(4 downto 0) = "01110" then return("%sp");
else return('%' & ctmp & tost('0' & reg(2 downto 0))); end if;
end;
function simm13dec(insn : pc_op_type; base : base_type; merge : boolean) return string is
variable simm : std_logic_vector(12 downto 0) := insn.op(12 downto 0);
variable rs1 : std_logic_vector(4 downto 0) := insn.op(18 downto 14);
variable i : std_ulogic := insn.op(13);
variable sig : character;
variable fill : std_logic_vector(31 downto 13) := (others => simm(12));
begin
if i = '0' then
return("");
else
if (simm(12) = '1') and (base = dec) then
sig := '-'; simm := (not simm) + 1;
else
sig := '+';
end if;
if base = dec then
if merge then
if rs1 = "00000" then
return(tost(simm));
else
return(sig & tost(simm));
end if;
else
if rs1 = "00000" then
return(tost(simm));
else
if sig = '-' then
return(", " & sig & tost(simm));
else
return(", " & tost(simm));
end if;
end if;
end if;
else
if rs1 = "00000" then
if simm(12) = '1' then return(tost(fill & simm));
else return(tost(simm)); end if;
else
if simm(12) = '1' then return(", " & tost(fill & simm));
else return(", " & tost(simm)); end if;
end if;
end if;
end if;
end;
function freg2(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%f" & tostd(rs2) &
", %f" & tostd(rd));
end;
function creg3(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%c" & tostd(rs1) & ", %c" & tostd(rs2) & ", %c" & tostd(rd));
end;
function freg3(insn : pc_op_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%f" & tostd(rs1) & ", %f" & tostd(rs2) & ", %f" & tostd(rd));
end;
function fregc(insn : pc_op_type) return string is
variable rs1, rs2 : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
return("%f" & tostd(rs1) & ", %f" & tostd(rs2));
end;
function regimm(insn : pc_op_type; base : base_type; merge : boolean) return string is
variable rs1, rs2 : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
i := insn.op(13);
if i = '0' then
if (rs1 = "00000") then
if (rs2 = "00000") then return("0");
else return(ireg2st(rs2)); end if;
else
if (rs2 = "00000") then return(ireg2st(rs1));
elsif merge then return(ireg2st(rs1) & " + " & ireg2st(rs2));
else return(ireg2st(rs1) & ", " & ireg2st(rs2)); end if;
end if;
else
if (rs1 = "00000") then return(simm13dec(insn, base, merge));
elsif insn.op(12 downto 0) = "0000000000000" then return(ireg2st(rs1));
else return(ireg2st(rs1) & simm13dec(insn, base, merge)); end if;
end if;
end;
function regres(insn : pc_op_type; base : base_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_ulogic;
begin
rd := insn.op(29 downto 25);
return(regimm(insn, base,false) & ", " & ireg2st(rd ));
end;
function branchop(insn : pc_op_type) return string is
variable simm : std_logic_vector(31 downto 0);
begin
case insn.op(28 downto 25) is
when "0000" => return("n");
when "0001" => return("e");
when "0010" => return("le");
when "0011" => return("l");
when "0100" => return("leu");
when "0101" => return("cs");
when "0110" => return("neg");
when "0111" => return("vs");
when "1000" => return("a");
when "1001" => return("ne");
when "1010" => return("g");
when "1011" => return("ge");
when "1100" => return("gu");
when "1101" => return("cc");
when "1110" => return("pos");
when "1111" => return("vc");
when others => return("XXX");
end case;
end;
function fbranchop(insn : pc_op_type) return string is
variable simm : std_logic_vector(31 downto 0);
begin
case insn.op(28 downto 25) is
when "0000" => return("n");
when "0001" => return("ne");
when "0010" => return("lg");
when "0011" => return("ul");
when "0100" => return("l");
when "0101" => return("ug");
when "0110" => return("g");
when "0111" => return("u");
when "1000" => return("a");
when "1001" => return("e");
when "1010" => return("ue");
when "1011" => return("ge");
when "1100" => return("uge");
when "1101" => return("le");
when "1110" => return("ule");
when "1111" => return("o");
when others => return("XXX");
end case;
end;
function ldparcp(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & "%c" & tost(rd));
end;
function ldparf(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & "%f" & tostd(rd));
end;
function ldpar(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & ireg2st(rd));
end;
function ldpara(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)) & ", " & ireg2st(rd));
end;
function ldpara_cas(insn : pc_op_type; rs1, rs2, rd : std_logic_vector; base : base_type) return string is
begin
return("[" & ireg2st(rs1) & "]" & " " & tost(insn.op(12 downto 5)) & ", " &
ireg2st(rs2) & ", " & ireg2st(rd));
end;
function stparc(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
if rd = "00000" then
return("[" & regimm(insn,dec,true) & "]");
else
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]");
end if;
end;
function stparcp(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("%c" & tost(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stparf(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return("%f" & tostd(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stpar(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stpara(insn : pc_op_type; rd : std_logic_vector; base : base_type) return string is
begin
return(ireg2st(rd) & ", [" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)));
end;
function ins2st(pc, op : std_logic_vector(31 downto 0)) return string is
constant STMAX : natural := 9;
constant bl2 : string(1 to 2) := (others => ' ');
constant bb : string(1 to 4) := (others => ' ');
variable op1 : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opf : std_logic_vector(8 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable addr : std_logic_vector(31 downto 0);
variable annul : std_ulogic;
variable i : std_ulogic;
variable simm : std_logic_vector(12 downto 0);
variable insn : pc_op_type;
begin
op1 := op(31 downto 30);
op2 := op(24 downto 22);
op3 := op(24 downto 19);
opf := op(13 downto 5);
cond := op(28 downto 25);
annul := op(29);
rs1 := op(18 downto 14);
rs2 := op(4 downto 0);
rd := op(29 downto 25);
i := op(13);
simm := op(12 downto 0);
insn.op := op;
insn.pc := pc;
case op1 is
when CALL =>
addr := pc + (op(29 downto 0) & "00");
return(tostf(pc) & bb & "call" & bl2 & tost(addr));
when FMT2 =>
case op2 is
when SETHI =>
if rd = "00000" then
return(tostf(pc) & bb & "nop");
else
return(tostf(pc) & bb & "sethi" & bl2 & "%hi(" &
tost(op(21 downto 0) & "0000000000") & "), " & ireg2st(rd));
end if;
when BICC | FBFCC =>
addr(31 downto 24) := (others => '0');
addr(1 downto 0) := (others => '0');
addr(23 downto 2) := op(21 downto 0);
if addr(23) = '1' then
addr(31 downto 24) := (others => '1');
else
addr(31 downto 24) := (others => '0');
end if;
addr := addr + pc;
if op2 = BICC then
if op(29) = '1' then
return(tostf(pc) & bb & 'b' & branchop(insn) & ",a" & bl2 &
tost(addr));
else
return(tostf(pc) & bb & 'b' & branchop(insn) & bl2 &
tost(addr));
end if;
else
if op(29) = '1' then
return(tostf(pc) & bb & "fb" & fbranchop(insn) & ",a" & bl2 &
tost(addr));
else
return(tostf(pc) & bb & "fb" & fbranchop(insn) & bl2 &
tost(addr));
end if;
end if;
-- when CBCCC => cptrap := '1';
when others => return(tostf(pc) & bb & "unimp");
end case;
when FMT3 =>
case op3 is
when IAND => return(tostf(pc) & bb & "and" & bl2 & regres(insn,hex));
when IADD => return(tostf(pc) & bb & "add" & bl2 & regres(insn,dec));
when IOR =>
if ((i = '0') and (rs1 = "00000") and (rs2 = "00000")) then
return(tostf(pc) & bb & "clr" & bl2 & ireg2st(rd));
elsif ((i = '1') and (simm = "0000000000000")) or (rs1 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regres(insn,hex));
else
return(tostf(pc) & bb & "or " & bl2 & regres(insn,hex));
end if;
when IXOR => return(tostf(pc) & bb & "xor" & bl2 & regres(insn,hex));
when ISUB => return(tostf(pc) & bb & "sub" & bl2 & regres(insn,dec));
when ANDN => return(tostf(pc) & bb & "andn" & bl2 & regres(insn,hex));
when ORN => return(tostf(pc) & bb & "orn" & bl2 & regres(insn,hex));
when IXNOR =>
if ((i = '0') and ((rs1 = rd) or (rs2 = "00000"))) then
return(tostf(pc) & bb & "not" & bl2 & ireg2st(rd));
else
return(tostf(pc) & bb & "xnor" & bl2 & ireg2st(rd));
end if;
when ADDX => return(tostf(pc) & bb & "addx" & bl2 & regres(insn,dec));
when SUBX => return(tostf(pc) & bb & "subx" & bl2 & regres(insn,dec));
when ADDCC => return(tostf(pc) & bb & "addcc" & bl2 & regres(insn,dec));
when ANDCC => return(tostf(pc) & bb & "andcc" & bl2 & regres(insn,hex));
when ORCC => return(tostf(pc) & bb & "orcc" & bl2 & regres(insn,hex));
when XORCC => return(tostf(pc) & bb & "xorcc" & bl2 & regres(insn,hex));
when SUBCC => return(tostf(pc) & bb & "subcc" & bl2 & regres(insn,dec));
when ANDNCC => return(tostf(pc) & bb & "andncc" & bl2 & regres(insn,hex));
when ORNCC => return(tostf(pc) & bb & "orncc" & bl2 & regres(insn,hex));
when XNORCC => return(tostf(pc) & bb & "xnorcc" & bl2 & regres(insn,hex));
when ADDXCC => return(tostf(pc) & bb & "addxcc" & bl2 & regres(insn,hex));
when UMAC => return(tostf(pc) & bb & "umac" & bl2 & regres(insn,dec));
when SMAC => return(tostf(pc) & bb & "smac" & bl2 & regres(insn,dec));
when UMUL => return(tostf(pc) & bb & "umul" & bl2 & regres(insn,dec));
when SMUL => return(tostf(pc) & bb & "smul" & bl2 & regres(insn,dec));
when UMULCC => return(tostf(pc) & bb & "umulcc" & bl2 & regres(insn,dec));
when SMULCC => return(tostf(pc) & bb & "smulcc" & bl2 & regres(insn,dec));
when SUBXCC => return(tostf(pc) & bb & "subxcc" & bl2 & regres(insn,dec));
when UDIV => return(tostf(pc) & bb & "udiv" & bl2 & regres(insn,dec));
when SDIV => return(tostf(pc) & bb & "sdiv" & bl2 & regres(insn,dec));
when UDIVCC => return(tostf(pc) & bb & "udivcc" & bl2 & regres(insn,dec));
when SDIVCC => return(tostf(pc) & bb & "sdivcc" & bl2 & regres(insn,dec));
when TADDCC => return(tostf(pc) & bb & "taddcc" & bl2 & regres(insn,dec));
when TSUBCC => return(tostf(pc) & bb & "tsubcc" & bl2 & regres(insn,dec));
when TADDCCTV => return(tostf(pc) & bb & "taddcctv" & bl2 & regres(insn,dec));
when TSUBCCTV => return(tostf(pc) & bb & "tsubcctv" & bl2 & regres(insn,dec));
when MULSCC => return(tostf(pc) & bb & "mulscc" & bl2 & regres(insn,dec));
when ISLL => return(tostf(pc) & bb & "sll" & bl2 & regres(insn,dec));
when ISRL => return(tostf(pc) & bb & "srl" & bl2 & regres(insn,dec));
when ISRA => return(tostf(pc) & bb & "sra" & bl2 & regres(insn,dec));
when RDY =>
if rs1 /= "00000" then
return(tostf(pc) & bb & "mov" & bl2 & "%asr" &
tostd(rs1) & ", " & ireg2st(rd));
else
return(tostf(pc) & bb & "mov" & bl2 & "%y, " & ireg2st(rd));
end if;
when RDPSR => return(tostf(pc) & bb & "mov" & bl2 & "%psr, " & ireg2st(rd));
when RDWIM => return(tostf(pc) & bb & "mov" & bl2 & "%wim, " & ireg2st(rd));
when RDTBR => return(tostf(pc) & bb & "mov" & bl2 & "%tbr, " & ireg2st(rd));
when WRY =>
if (rs1 = "00000") or (rs2 = "00000") then
if rd /= "00000" then
return(tostf(pc) & bb & "mov" & bl2
& regimm(insn,hex,false) & ", %asr" & tostd(rd));
else
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %y");
end if;
else
if rd /= "00000" then
return(tostf(pc) & bb & "wr " & bl2 & "%asr"
& regimm(insn,hex,false) & ", %asr" & tostd(rd));
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %y");
end if;
end if;
when WRPSR =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %psr");
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %psr");
end if;
when WRWIM =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %wim");
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %wim");
end if;
when WRTBR =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %tbr");
else
return(tostf(pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %tbr");
end if;
when JMPL =>
if (rd = "00000") then
if (i = '1') and (simm = "0000000001000") then
if (rs1 = "11111") then return(tostf(pc) & bb & "ret");
elsif (rs1 = "01111") then return(tostf(pc) & bb & "retl");
else return(tostf(pc) & bb & "jmp" & bl2 & regimm(insn,dec,true));
end if;
else return(tostf(pc) & bb & "jmp" & bl2 & regimm(insn,dec,true));
end if;
else return(tostf(pc) & bb & "jmpl" & bl2 & regres(insn,dec));
end if;
when TICC =>
return(tostf(pc) & bb & 't' & branchop(insn) & bl2 & regimm(insn,hex,false));
when FLUSH =>
return(tostf(pc) & bb & "flush" & bl2 & regimm(insn,hex,false));
when RETT =>
return(tostf(pc) & bb & "rett" & bl2 & regimm(insn,dec,true));
when RESTORE =>
if (rd = "00000") then
return(tostf(pc) & bb & "restore");
else
return(tostf(pc) & bb & "restore" & bl2 & regres(insn,hex));
end if;
when SAVE =>
if (rd = "00000") then return(tostf(pc) & bb & "save");
else return(tostf(pc) & bb & "save" & bl2 & regres(insn,dec)); end if;
when FPOP1 =>
case opf is
when FITOS => return(tostf(pc) & bb & "fitos" & bl2 & freg2(insn));
when FITOD => return(tostf(pc) & bb & "fitod" & bl2 & freg2(insn));
when FSTOI => return(tostf(pc) & bb & "fstoi" & bl2 & freg2(insn));
when FDTOI => return(tostf(pc) & bb & "fdtoi" & bl2 & freg2(insn));
when FSTOD => return(tostf(pc) & bb & "fstod" & bl2 & freg2(insn));
when FDTOS => return(tostf(pc) & bb & "fdtos" & bl2 & freg2(insn));
when FMOVS => return(tostf(pc) & bb & "fmovs" & bl2 & freg2(insn));
when FNEGS => return(tostf(pc) & bb & "fnegs" & bl2 & freg2(insn));
when FABSS => return(tostf(pc) & bb & "fabss" & bl2 & freg2(insn));
when FSQRTS => return(tostf(pc) & bb & "fsqrts" & bl2 & freg2(insn));
when FSQRTD => return(tostf(pc) & bb & "fsqrtd" & bl2 & freg2(insn));
when FADDS => return(tostf(pc) & bb & "fadds" & bl2 & freg3(insn));
when FADDD => return(tostf(pc) & bb & "faddd" & bl2 & freg3(insn));
when FSUBS => return(tostf(pc) & bb & "fsubs" & bl2 & freg3(insn));
when FSUBD => return(tostf(pc) & bb & "fsubd" & bl2 & freg3(insn));
when FMULS => return(tostf(pc) & bb & "fmuls" & bl2 & freg3(insn));
when FMULD => return(tostf(pc) & bb & "fmuld" & bl2 & freg3(insn));
when FSMULD => return(tostf(pc) & bb & "fsmuld" & bl2 & freg3(insn));
when FDIVS => return(tostf(pc) & bb & "fdivs" & bl2 & freg3(insn));
when FDIVD => return(tostf(pc) & bb & "fdivd" & bl2 & freg3(insn));
when others => return(tostf(pc) & bb & "unknown FOP1: " & tost(op));
end case;
when FPOP2 =>
case opf is
when FCMPS => return(tostf(pc) & bb & "fcmps" & bl2 & fregc(insn));
when FCMPD => return(tostf(pc) & bb & "fcmpd" & bl2 & fregc(insn));
when FCMPES => return(tostf(pc) & bb & "fcmpes" & bl2 & fregc(insn));
when FCMPED => return(tostf(pc) & bb & "fcmped" & bl2 & fregc(insn));
when others => return(tostf(pc) & bb & "unknown FOP2: " & tost(insn.op));
end case;
when CPOP1 =>
return(tostf(pc) & bb & "cpop1" & bl2 & tost("000"&opf) & ", " &creg3(insn));
when CPOP2 =>
return(tostf(pc) & bb & "cpop2" & bl2 & tost("000"&opf) & ", " &creg3(insn));
when others => return(tostf(pc) & bb & "unknown opcode: " & tost(insn.op));
end case;
when LDST =>
case op3 is
when STC =>
return(tostf(pc) & bb & "st" & bl2 & stparcp(insn, rd, dec));
when STF =>
return(tostf(pc) & bb & "st" & bl2 & stparf(insn, rd, dec));
when ST =>
if rd = "00000" then
return(tostf(pc) & bb & "clr" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bb & "st" & bl2 & stpar(insn, rd, dec));
end if;
when STB =>
if rd = "00000" then
return(tostf(pc) & bb & "clrb" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bb & "stb" & bl2 & stpar(insn, rd, dec));
end if;
when STH =>
if rd = "00000" then
return(tostf(pc) & bb & "clrh" & bl2 & stparc(insn, rd, dec));
else
return(tostf(pc) & bb & "sth" & bl2 & stpar(insn, rd, dec));
end if;
when STDC =>
return(tostf(pc) & bb & "std" & bl2 & stparcp(insn, rd, dec));
when STDF =>
return(tostf(pc) & bb & "std" & bl2 & stparf(insn, rd, dec));
when STCSR =>
return(tostf(pc) & bb & "st" & bl2 & "%csr, [" & regimm(insn,dec,true) & "]");
when STFSR =>
return(tostf(pc) & bb & "st" & bl2 & "%fsr, [" & regimm(insn,dec,true) & "]");
when STDCQ =>
return(tostf(pc) & bb & "std" & bl2 & "%cq, [" & regimm(insn,dec,true) & "]");
when STDFQ =>
return(tostf(pc) & bb & "std" & bl2 & "%fq, [" & regimm(insn,dec,true) & "]");
when ISTD =>
return(tostf(pc) & bb & "std" & bl2 & stpar(insn, rd, dec));
when STA =>
return(tostf(pc) & bb & "sta" & bl2 & stpara(insn, rd, dec));
when STBA =>
return(tostf(pc) & bb & "stba" & bl2 & stpara(insn, rd, dec));
when STHA =>
return(tostf(pc) & bb & "stha" & bl2 & stpara(insn, rd, dec));
when STDA =>
return(tostf(pc) & bb & "stda" & bl2 & stpara(insn, rd, dec));
when LDC =>
return(tostf(pc) & bb & "ld" & bl2 & ldparcp(insn, rd, dec));
when LDF =>
return(tostf(pc) & bb & "ld" & bl2 & ldparf(insn, rd, dec));
when LDCSR =>
return(tostf(pc) & bb & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %csr");
when LDFSR =>
return(tostf(pc) & bb & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %fsr");
when LD =>
return(tostf(pc) & bb & "ld" & bl2 & ldpar(insn, rd, dec));
when LDUB =>
return(tostf(pc) & bb & "ldub" & bl2 & ldpar(insn, rd, dec));
when LDUH =>
return(tostf(pc) & bb & "lduh" & bl2 & ldpar(insn, rd, dec));
when LDDC =>
return(tostf(pc) & bb & "ldd" & bl2 & ldparcp(insn, rd, dec));
when LDDF =>
return(tostf(pc) & bb & "ldd" & bl2 & ldparf(insn, rd, dec));
when LDD =>
return(tostf(pc) & bb & "ldd" & bl2 & ldpar(insn, rd, dec));
when LDSB =>
return(tostf(pc) & bb & "ldsb" & bl2 & ldpar(insn, rd, dec));
when LDSH =>
return(tostf(pc) & bb & "ldsh" & bl2 & ldpar(insn, rd, dec));
when LDSTUB =>
return(tostf(pc) & bb & "ldstub" & bl2 & ldpar(insn, rd, dec));
when SWAP =>
return(tostf(pc) & bb & "swap" & bl2 & ldpar(insn, rd, dec));
when LDA =>
return(tostf(pc) & bb & "lda" & bl2 & ldpara(insn, rd, dec));
when LDUBA =>
return(tostf(pc) & bb & "lduba" & bl2 & ldpara(insn, rd, dec));
when LDUHA =>
return(tostf(pc) & bb & "lduha" & bl2 & ldpara(insn, rd, dec));
when LDDA =>
return(tostf(pc) & bb & "ldda" & bl2 & ldpara(insn, rd, dec));
when LDSBA =>
return(tostf(pc) & bb & "ldsba" & bl2 & ldpara(insn, rd, dec));
when LDSHA =>
return(tostf(pc) & bb & "ldsha" & bl2 & ldpara(insn, rd, dec));
when LDSTUBA =>
return(tostf(pc) & bb & "ldstuba" & bl2 & ldpara(insn, rd, dec));
when SWAPA =>
return(tostf(pc) & bb & "swapa" & bl2 & ldpara(insn, rd, dec));
when CASA =>
return(tostf(pc) & bb & "casa" & bl2 & ldpara_cas(insn, rs1, rs2, rd, dec));
when others => return(tostf(pc) & bb & "unknown opcode: " & tost(op));
end case;
when others => return(tostf(pc) & bb & "unknown opcode: " & tost(op));
end case;
end;
procedure print_insn(ndx: integer; pc, op, res : std_logic_vector(31 downto 0);
valid, trap, wr, rest : boolean) is
begin
if valid then
if rest then grlib.testlib.print ("cpu" & tost(ndx) &": " & ins2st(pc, op) & " (restart)");
elsif trap then grlib.testlib.print ("cpu" & tost(ndx) &": " & ins2st(pc, op) & " (trapped)");
elsif wr then grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res) & "]");
else grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op)); end if;
end if;
end;
procedure print_fpinsn(ndx: integer; pc, op : std_logic_vector(31 downto 0);
res : std_logic_vector(63 downto 0);
dpres, valid, trap, wr : boolean) is
variable t : natural;
begin
if valid then
t := now / 1 ns;
if trap then grlib.testlib.print ("cpu" & tost(ndx) &": " & ins2st(pc, op) & " (trapped)");
elsif wr then
if dpres then grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res) & "]");
else grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op) & " [" & tost(res(63 downto 32)) & "]"); end if;
else grlib.testlib.print ("cpu" & tost(ndx) & ": " & ins2st(pc, op)); end if;
end if;
end;
end;
-- pragma translate_on
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/can/can_mc.in.vhd | 6 | 405 | -- CAN 2.0 interface
constant CFG_CAN : integer := CONFIG_CAN_ENABLE;
constant CFG_CAN_NUM : integer := CONFIG_CAN_NUM;
constant CFG_CANIO : integer := 16#CONFIG_CANIO#;
constant CFG_CANIRQ : integer := CONFIG_CANIRQ;
constant CFG_CANSEPIRQ: integer := CONFIG_CANSEPIRQ;
constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
constant CFG_CANFT : integer := CONFIG_CAN_FT;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/apbvga.vhd | 1 | 11932 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbvga
-- File: vga.vhd
-- Author: Marcus Hellqvist
-- Description: VGA controller
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use gaisler.charrom_package.all;
entity apbvga is
generic(
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port( rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
vgaclk : in std_ulogic; -- VGA clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type
);
end entity apbvga;
architecture rtl of apbvga is
type state_type is (s0,s1,s2);
constant RAM_DEPTH : integer := 12;
constant RAM_DATA_BITS : integer := 8;
constant MAX_FRAME : std_logic_vector((RAM_DEPTH-1) downto 0):= X"B90";
type ram_out_type is record
dataout2 : std_logic_vector((RAM_DATA_BITS -1) downto 0);
end record;
type vga_regs is record
video_out : std_logic_vector(23 downto 0);
hsync : std_ulogic;
vsync : std_ulogic;
csync : std_ulogic;
hcnt : std_logic_vector(9 downto 0);
vcnt : std_logic_vector(9 downto 0);
blank : std_ulogic;
linecnt : std_logic_vector(3 downto 0);
h_video_on : std_ulogic;
v_video_on : std_ulogic;
pixel : std_ulogic;
state : state_type;
rombit : std_logic_vector(2 downto 0);
romaddr : std_logic_vector(11 downto 0);
ramaddr2 : std_logic_vector((RAM_DEPTH -1) downto 0);
ramdatain2 : std_logic_vector((RAM_DATA_BITS -1) downto 0);
wstartaddr : std_logic_vector((RAM_DEPTH-1) downto 0);
raddr : std_logic_vector((RAM_DEPTH-1) downto 0);
tmp : std_logic_vector(RAM_DEPTH-1 downto 0);
end record;
type color_reg_type is record
bgcolor : std_logic_vector(23 downto 0);
txtcolor : std_logic_vector(23 downto 0);
end record;
type vmmu_reg_type is record
waddr : std_logic_vector((RAM_DEPTH-1) downto 0);
wstartaddr : std_logic_vector((RAM_DEPTH-1) downto 0);
ramaddr1 : std_logic_vector((RAM_DEPTH -1) downto 0);
ramdatain1 : std_logic_vector((RAM_DATA_BITS -1) downto 0);
ramenable1 : std_ulogic;
ramwrite1 : std_ulogic;
color : color_reg_type;
end record;
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_VGACTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant hmax : integer:= 799;
constant vmax : integer:= 524;
constant hvideo : integer:= 639;
constant vvideo : integer:= 480;
constant hfporch : integer:= 19;
constant vfporch : integer:= 11;
constant hbporch : integer:= 45;
constant vbporch : integer:= 31;
constant hsyncpulse : integer:= 96;
constant vsyncpulse : integer:= 2;
constant char_height : std_logic_vector(3 downto 0):="1100";
signal p,pin : vmmu_reg_type;
signal ramo : ram_out_type;
signal r,rin : vga_regs;
signal romdata : std_logic_vector(7 downto 0);
signal gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
comb1: process(rst,r,p,romdata,ramo)
variable v : vga_regs;
begin
v:=r;
v.wstartaddr := p.wstartaddr;
-- horizontal counter
if r.hcnt < conv_std_logic_vector(hmax,10) then
v.hcnt := r.hcnt +1;
else
v.hcnt := (others => '0');
end if;
-- vertical counter
if (r.vcnt >= conv_std_logic_vector(vmax,10)) and (r.hcnt >= conv_std_logic_vector(hmax,10)) then
v.vcnt := (others => '0');
elsif r.hcnt = conv_std_logic_vector(hmax,10) then
v.vcnt := r.vcnt +1;
end if;
-- horizontal pixel out
if r.hcnt <= conv_std_logic_vector(hvideo,10) then
v.h_video_on := '1';
else
v.h_video_on := '0';
end if;
-- vertical pixel out
if r.vcnt <= conv_std_logic_vector(vvideo,10) then
v.v_video_on := '1';
else
v.v_video_on := '0';
end if;
-- generate hsync
if (r.hcnt <= conv_std_logic_vector((hvideo+hfporch+hsyncpulse),10)) and
(r.hcnt >= conv_std_logic_vector((hvideo+hfporch),10)) then
v.hsync := '0';
else
v.hsync := '1';
end if;
-- generate vsync
if (r.vcnt <= conv_std_logic_vector((vvideo+vfporch+vsyncpulse),10)) and
(r.vcnt >= conv_std_logic_vector((vvideo+vfporch),10)) then
v.vsync := '0';
else
v.vsync := '1';
end if;
--generate csync & blank
v.csync := not (v.hsync xor v.vsync);
v.blank := v.h_video_on and v.v_video_on;
-- count line of character
if v.hcnt = conv_std_logic_vector(hvideo,10) then
if (r.linecnt = char_height) or (v.vcnt = conv_std_logic_vector(vmax,10)) then
v.linecnt := (others => '0');
else
v.linecnt := r.linecnt +1;
end if;
end if;
if v.blank = '1' then
case r.state is
when s0 => v.ramaddr2 := r.raddr;
v.raddr := r.raddr +1;
v.state := s1;
when s1 => v.romaddr := v.linecnt & ramo.dataout2;
v.state := s2;
when s2 => if r.rombit = "011" then
v.ramaddr2 := r.raddr;
v.raddr := r.raddr +1;
elsif r.rombit = "010" then
v.state := s1;
end if;
end case;
v.rombit := r.rombit - 1;
v.pixel := romdata(conv_integer(r.rombit));
end if;
-- read from same address char_height times
if v.raddr = (r.tmp + X"050") then
if (v.linecnt < char_height) then
v.raddr := r.tmp;
elsif v.raddr(11 downto 4) = X"FF" then --check for end of allowed memory(80x51)
v.raddr := (others => '0');
v.tmp := (others => '0');
else
v.tmp := r.tmp + X"050";
end if;
end if;
if v.v_video_on = '0' then
v.raddr := r.wstartaddr;
v.tmp := r.wstartaddr;
v.state := s0;
end if;
-- define pixel color
if v.pixel = '1'and v.blank = '1' then
v.video_out := p.color.txtcolor;
else
v.video_out := p.color.bgcolor;
end if;
if rst = '0' then
v.hcnt := conv_std_logic_Vector(hmax,10);
v.vcnt := conv_std_logic_Vector(vmax,10);
v.v_video_on := '0';
v.h_video_on := '0';
v.hsync := '0';
v.vsync := '0';
v.csync := '0';
v.blank := '0';
v.linecnt := (others => '0');
v.state := s0;
v.rombit := "111";
v.pixel := '0';
v.video_out := (others => '0');
v.raddr := (others => '0');
v.tmp := (others => '0');
v.ramaddr2 := (others => '0');
v.ramdatain2 := (others => '0');
end if;
-- update register
rin <= v;
-- drive outputs
vgao.hsync <= r.hsync;
vgao.vsync <= r.vsync;
vgao.comp_sync <= r.csync;
vgao.blank <= r.blank;
vgao.video_out_r <= r.video_out(23 downto 16);
vgao.video_out_g <= r.video_out(15 downto 8);
vgao.video_out_b <= r.video_out(7 downto 0);
vgao.bitdepth <= "11"; -- All data is valid
end process;
comb2: process(rst,r,p,apbi,ramo)
variable v : vmmu_reg_type;
variable rdata : std_logic_vector(31 downto 0);
begin
v := p;
v.ramenable1 := '0'; v.ramwrite1 := '0';
rdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" => if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
v.waddr := apbi.pwdata(19 downto 8);
v.ramdatain1 := apbi.pwdata(7 downto 0);
v.ramenable1 := '1';
v.ramwrite1 := '1';
v.ramaddr1 := apbi.pwdata(19 downto 8);
end if;
when "01" => if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
v.color.bgcolor := apbi.pwdata(23 downto 0);
end if;
when "10" => if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
v.color.txtcolor := apbi.pwdata(23 downto 0);
end if;
when others => null;
end case;
if (p.waddr - p.wstartaddr) >= MAX_FRAME then
if p.wstartaddr(11 downto 4) = X"FA" then --last position of allowed memory
v.wstartaddr := X"000";
else
v.wstartaddr := p.wstartaddr + X"050";
end if;
end if;
if rst = '0' then
v.waddr := (others => '0');
v.wstartaddr := (others => '0');
v.color.bgcolor := (others => '0');
v.color.txtcolor := (others => '1');
end if;
--update registers
pin <= v;
--drive outputs
apbo.prdata <= rdata;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
end process;
apbo.pconfig <= pconfig;
reg : process(clk)
begin
if clk'event and clk = '1' then
p <= pin;
end if;
end process;
reg2 : process(vgaclk)
begin
if vgaclk'event and vgaclk = '1' then
r <= rin;
end if;
end process;
rom0 : charrom port map(clk=>vgaclk, addr=>r.romaddr, data=>romdata);
ram0 : syncram_2p generic map (tech => memtech, abits => RAM_DEPTH,
dbits => RAM_DATA_BITS, sepclk => 1)
port map (
rclk => vgaclk, raddress => r.ramaddr2, dataout => ramo.dataout2, renable => vcc,
wclk => clk, waddress => p.ramaddr1, datain => p.ramdatain1, write => p.ramwrite1
);
-- ram0 : syncram_dp generic map (tech => memtech, abits => RAM_DEPTH, dbits => RAM_DATA_BITS)
-- port map ( clk1 => clk, address1 => p.ramaddr1, datain1 => p.ramdatain1,
-- dataout1 => open, enable1 => p.ramenable1, write1 => p.ramwrite1,
-- clk2 => vgaclk, address2 => r.ramaddr2, datain2 => r.ramdatain2,
-- dataout2 => ramo.dataout2, enable2 => gnd, write2 => gnd);
-- pragma translate_off
bootmsg : report_version
generic map ("apbvga" & tost(pindex) & ": APB VGA module rev 0");
-- pragma translate_on
end architecture;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml605/grlib_config.vhd | 1 | 2556 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: config
-- File: config.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: GRLIB Global configuration package. Can be overriden
-- by local config packages in template designs.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
package config is
-- AHBDW - AHB data with
--
-- Valid values are 32, 64, 128 and 256
--
-- The value here sets the width of the AMBA AHB data vectors for all
-- cores in the library.
--
constant CFG_AHBDW : integer := 64;
-- CORE_ACDM - Enable AMBA Compliant Data Muxing in cores
--
-- Valid values are 0 and 1
--
-- 0: All GRLIB cores that use the ahbread* programs defined in this package
-- will read their data from the low part of the AHB data vector.
--
-- 1: All GRLIB cores that use the ahbread* programs defined in this package
-- will select valid data, as defined in the AMBA AHB standard, from the
-- AHB data vectors based on the address input. If a core uses a function
-- that does not have the address input, a failure will be asserted.
--
constant CFG_AHB_ACDM : integer := 0;
-- GRLIB_CONFIG_ARRAY - Array of configuration values
--
-- The length of this array and the meaning of different positions is defined
-- in the grlib.config_types package.
constant GRLIB_CONFIG_ARRAY : grlib_config_array_type := (
grlib_debug_level => 0,
grlib_debug_mask => 0,
grlib_techmap_strict_ram => 0,
others => 0);
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/sim/delay_wire.vhd | 1 | 2510 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Delayed bidirectional wire
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity delay_wire is
generic(
data_width : integer := 1;
delay_atob : real := 0.0;
delay_btoa : real := 0.0
);
port(
a : inout std_logic_vector(data_width-1 downto 0);
b : inout std_logic_vector(data_width-1 downto 0);
x : in std_logic_vector(data_width-1 downto 0) := (others => '0')
);
end delay_wire;
architecture rtl of delay_wire is
signal a_dly,b_dly : std_logic_vector(data_width-1 downto 0) := (others => 'Z');
constant zvector : std_logic_vector(data_width-1 downto 0) := (others => 'Z');
function errinj(a,b: std_logic_vector) return std_logic_vector is
variable r: std_logic_vector(a'length-1 downto 0);
begin
r := a;
for k in a'length-1 downto 0 loop
if (a(k)='0' or a(k)='1') and b(k)='1' then
r(k) := not a(k);
end if;
end loop;
return r;
end;
begin
process(a)
begin
if a'event then
if b_dly = zvector then
a_dly <= transport a after delay_atob*1 ns;
else
a_dly <= (others => 'Z');
end if;
end if;
end process;
process(b)
begin
if b'event then
if a_dly = zvector then
b_dly <= transport errinj(b,x) after delay_btoa*1 ns;
else
b_dly <= (others => 'Z');
end if;
end if;
end process;
a <= b_dly; b <= a_dly;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/spi/spi2ahb.vhd | 1 | 2940 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb
-- File: spi2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.spi.all;
entity spi2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb;
architecture rtl of spi2ahb is
signal spi2ahbi : spi2ahb_in_type;
begin
bridge : spi2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter,
cpol => cpol,
cpha => cpha)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
spii => spii,
spio => spio,
spi2ahbi => spi2ahbi,
spi2ahbo => open);
spi2ahbi.en <= '1';
spi2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
spi2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
end architecture rtl;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/pci/ptf/pt_pkg.vhd | 1 | 29021 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Package: pt_pkg
-- File: pt_pkg.vhd
-- Author: Nils-Johan Wessman, Aeroflex Gaisler
-- Description: PCI Test Framework - Main package
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
--use grlib.amba.all;
--use grlib.testlib.all;
use grlib.stdlib.all;
package pt_pkg is
-----------------------------------------------------------------------------
-- Constants and PCI signal
-----------------------------------------------------------------------------
-- Constants for PCI commands
constant INT_ACK : std_logic_vector(3 downto 0) := "0000";
constant SPEC_CYCLE : std_logic_vector(3 downto 0) := "0001";
constant IO_READ : std_logic_vector(3 downto 0) := "0010";
constant IO_WRITE : std_logic_vector(3 downto 0) := "0011";
constant MEM_READ : std_logic_vector(3 downto 0) := "0110";
constant MEM_WRITE : std_logic_vector(3 downto 0) := "0111";
constant CONF_READ : std_logic_vector(3 downto 0) := "1010";
constant CONF_WRITE : std_logic_vector(3 downto 0) := "1011";
constant MEM_R_MULT : std_logic_vector(3 downto 0) := "1100";
constant DAC : std_logic_vector(3 downto 0) := "1101";
constant MEM_R_LINE : std_logic_vector(3 downto 0) := "1110";
constant MEM_W_INV : std_logic_vector(3 downto 0) := "1111";
type bar_type is array(0 to 5) of std_logic_vector(31 downto 0);
constant bar_init : bar_type := ((others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'));
type config_header_type is record
devid : std_logic_vector(15 downto 0);
vendid : std_logic_vector(15 downto 0);
status : std_logic_vector(15 downto 0);
command : std_logic_vector(15 downto 0);
class_code : std_logic_vector(23 downto 0);
revid : std_logic_vector(7 downto 0);
bist : std_logic_vector(7 downto 0);
header_type : std_logic_vector(7 downto 0);
lat_timer : std_logic_vector(7 downto 0);
cache_lsize : std_logic_vector(7 downto 0);
bar : bar_type;
cis_p : std_logic_vector(31 downto 0);
subid : std_logic_vector(15 downto 0);
subvendid : std_logic_vector(15 downto 0);
exp_rom_ba : std_logic_vector(31 downto 0);
max_lat : std_logic_vector(7 downto 0);
min_gnt : std_logic_vector(7 downto 0);
int_pin : std_logic_vector(7 downto 0);
int_line : std_logic_vector(7 downto 0);
end record;
constant config_init : config_header_type := (
devid => conv_std_logic_vector(16#0BAD#,16),
vendid => conv_std_logic_vector(16#AFFE#,16),
status => (others => '0'),
command => (others => '0'),
class_code => conv_std_logic_vector(16#050000#,24),
revid => conv_std_logic_vector(16#01#,8),
bist => (others => '0'),
header_type => (others => '0'),
lat_timer => (others => '0'),
cache_lsize => (others => '0'),
bar => bar_init,
cis_p => (others => '0'),
subid => (others => '0'),
subvendid => (others => '0'),
exp_rom_ba => (others => '0'),
max_lat => (others => '0'),
min_gnt => (others => '0'),
int_pin => (others => '0'),
int_line => (others => '0'));
-- These types defines the TB PCI bus
type pci_ad_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
par : std_logic;
end record;
constant ad_const : pci_ad_type := (
ad => (others => 'Z'),
cbe => (others => 'Z'),
par => 'Z');
type pci_ifc_type is record
frame : std_logic;
irdy : std_logic;
trdy : std_logic;
stop : std_logic;
devsel : std_logic;
idsel : std_logic_vector(20 downto 0);
lock : std_logic;
end record;
constant ifc_const : pci_ifc_type := (
frame => 'H',
irdy => 'H',
trdy => 'H',
stop => 'H',
lock => 'H',
idsel => (others => 'L'),
devsel => 'H');
type pci_err_type is record
perr : std_logic;
serr : std_logic;
end record;
constant err_const : pci_err_type := (
perr => 'H',
serr => 'H');
type pci_arb_type is record
req : std_logic_vector(20 downto 0);
gnt : std_logic_vector(20 downto 0);
end record;
constant arb_const : pci_arb_type := (
req => (others => 'H'),
gnt => (others => 'H'));
type pci_syst_type is record
clk : std_logic;
rst : std_logic;
end record;
constant syst_const : pci_syst_type := (
clk => 'H',
rst => 'H');
type pci_ext64_type is record
ad : std_logic_vector(63 downto 32);
cbe : std_logic_vector(7 downto 4);
par64 : std_logic;
req64 : std_logic;
ack64 : std_logic;
end record;
constant ext64_const : pci_ext64_type := (
ad => (others => 'Z'),
cbe => (others => 'Z'),
par64 => 'Z',
req64 => 'Z',
ack64 => 'Z');
--type pci_int_type is record
-- inta : std_logic;
-- intb : std_logic;
-- intc : std_logic;
-- intd : std_logic;
--end record;
--constant int_const : pci_int_type := (
-- inta => 'H',
-- intb => 'H',
-- intc => 'H',
-- intd => 'H');
constant int_const : std_logic_vector(3 downto 0) := "HHHH";
type pci_cache_type is record
sbo : std_logic;
sdone : std_logic;
end record;
constant cache_const : pci_cache_type := (
sbo => 'U',
sdone => 'U');
type pci_type is record
ad : pci_ad_type;
ifc : pci_ifc_type;
err : pci_err_type;
arb : pci_arb_type;
syst : pci_syst_type;
ext64 : pci_ext64_type;
--int : pci_int_type;
int : std_logic_vector(3 downto 0);
cache : pci_cache_type;
end record;
constant pci_idle : pci_type := ( ad_const, ifc_const, err_const, arb_const,
syst_const, ext64_const, int_const, cache_const);
-----------------------------------------------------------------------------
-- Types for PCI master
-----------------------------------------------------------------------------
type pt_pci_access_type is record
addr : std_logic_vector(31 downto 0);
cbe_cmd : std_logic_vector(3 downto 0);
data : std_logic_vector(31 downto 0);
cbe_data : std_logic_vector(3 downto 0);
ws : integer;
status : integer range 0 to 3;
id : integer;
debug : integer range 0 to 3;
last : boolean;
idle : boolean;
list_res : boolean;
valid : boolean;
parerr : integer range 0 to 2;
cod : integer range 0 to 2; -- Cancel on disconnect
end record;
type pt_pci_master_in_type is record
req : std_logic;
add : boolean;
remove : boolean;
rmall : boolean;
get_res : boolean;
add_res : boolean;
acc : pt_pci_access_type;
end record;
type pt_pci_master_out_type is record
ack : std_logic;
res_found : std_logic;
acc : pt_pci_access_type;
valid : boolean;
end record;
-----------------------------------------------------------------------------
-- PCI master procedures
-----------------------------------------------------------------------------
procedure pt_pci_master_sync_with_core(
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_idle_nb(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_idle(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
-----------------------------------------------------------------------------
-- Types for PCI target
-----------------------------------------------------------------------------
type pt_pci_response_type is record
addr : std_logic_vector(31 downto 0);
retry : integer;
ws : integer;
diswithout : integer;
diswith : integer;
abort : integer;
parerr : integer;
debug : integer;
valid : boolean;
end record;
type pt_pci_target_in_type is record
req : std_logic;
insert: std_logic;
remove: std_logic;
rmall : std_logic;
addr : std_logic_vector(31 downto 0);
resp : pt_pci_response_type;
end record;
type pt_pci_target_out_type is record
ack : std_logic;
resp : pt_pci_response_type;
valid : std_logic;
end record;
-----------------------------------------------------------------------------
-- PCI target procedures
-----------------------------------------------------------------------------
procedure pt_pci_target_sync_with_core(
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type);
procedure pt_insert_resp(
constant addr : std_logic_vector(31 downto 0);
constant retry : integer;
constant waits : integer;
constant discon: integer;
constant parerr: integer;
constant abort : integer;
constant debug : integer;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type);
procedure pt_remove_resp(
constant addr : std_logic_vector(31 downto 0);
constant rmall : boolean;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component pt_pci_master -- A PCI master that is accessed through a Testbench vector
generic (
slot : integer := 0; -- Slot number for this unit
tval : time := 7 ns); -- Output delay for signals that are driven by this unit
port (
pciin : in pci_type;
pciout : out pci_type;
dbgi : in pt_pci_master_in_type;
dbgo : out pt_pci_master_out_type
);
end component;
component pt_pci_target -- Represents a simple memory on the PCI bus
generic (
slot : integer := 0; -- Slot number for this unit
abits : integer := 10; -- Memory size. Size is 2^abits 32-bit words
bars : integer := 1; -- Number of bars for this target. Min 1, Max 6
resptime : integer := 2; -- The initial response time in clks for this target
latency : integer := 0; -- The latency in clks for every dataphase for a burst access
rbuf : integer := 8; -- The maximum no of words this target can transfer in a continuous burst
stopwd : boolean := true; -- Target disconnect type. true = disconnect WITH data, false = disconnect WITHOUT data
tval : time := 7 ns; -- Output delay for signals that are driven by this unit
conf : config_header_type := config_init; -- The reset condition of the configuration space of this target
dbglevel : integer := 1); -- Debug level. Higher value means more debug information
port (
pciin : in pci_type;
pciout : out pci_type;
dbgi : in pt_pci_target_in_type;
dbgo : out pt_pci_target_out_type
);
end component;
component pt_pci_arb
generic (
slots : integer := 5; -- The number of slots in the test system
tval : time := 7 ns); -- Output delay for signals that are driven by this unit
port (
systclk : in pci_syst_type;
ifcin : in pci_ifc_type;
arbin : in pci_arb_type;
arbout : out pci_arb_type);
end component;
--component pt_pci_monitor is
-- generic (dbglevel : integer := 1); -- Debug level. Higher value means more debug information
-- port (pciin : in pci_type);
--end component;
end package pt_pkg;
package body pt_pkg is
-----------------------------------------------------------------------------
-- PCI master procedures
-----------------------------------------------------------------------------
procedure pt_pci_master_sync_with_core(
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
dbgi.req <= '1';
wait until dbgo.ack = '1';
dbgi.req <= '0';
wait until dbgo.ack = '0';
end procedure pt_pci_master_sync_with_core;
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= addr;
dbgi.acc.cbe_cmd <= cbe_cmd;
dbgi.acc.data <= data;
dbgi.acc.cbe_data <= cbe_data;
dbgi.acc.ws <= waits;
dbgi.acc.last <= last;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= addr;
dbgi.acc.cbe_cmd <= cbe_cmd;
dbgi.acc.data <= data;
dbgi.acc.cbe_data <= cbe_data;
dbgi.acc.ws <= waits;
dbgi.acc.last <= last;
dbgi.acc.parerr <= parerr;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= addr;
dbgi.acc.cbe_cmd <= cbe_cmd;
dbgi.acc.data <= data;
dbgi.acc.cbe_data <= cbe_data;
dbgi.acc.ws <= waits;
dbgi.acc.last <= last;
dbgi.acc.parerr <= parerr;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= cod;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
pt_add_acc_nb(addr, cbe_cmd , data, cbe_data, waits, last, parerr, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
pt_add_acc_nb(addr, cbe_cmd , data, cbe_data, waits, last, parerr, cod, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
pt_add_acc_nb(addr, cbe_cmd , data, cbe_data, waits, last, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
procedure pt_add_idle_nb(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= waits;
dbgi.acc.idle <= true;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_idle(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
-- Add acc
pt_add_idle_nb(waits, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
-----------------------------------------------------------------------------
-- PCI target procedures
-----------------------------------------------------------------------------
procedure pt_pci_target_sync_with_core(
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type) is
begin
dbgi.req <= '1';
wait until dbgo.ack = '1';
dbgi.req <= '0';
wait until dbgo.ack = '0';
end procedure pt_pci_target_sync_with_core;
procedure pt_insert_resp(
constant addr : std_logic_vector(31 downto 0);
constant retry : integer;
constant waits : integer;
constant discon: integer;
constant parerr: integer;
constant abort : integer;
constant debug : integer;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type) is
begin
dbgi.insert <= '1';
dbgi.remove <= '0';
dbgi.resp.addr <= addr;
dbgi.resp.retry <= retry;
dbgi.resp.ws <= waits;
dbgi.resp.parerr <= parerr;
dbgi.resp.abort <= abort;
dbgi.resp.debug <= debug;
if discon = 1 then
dbgi.resp.diswith <= 1;
elsif discon = 2 then
dbgi.resp.diswithout <= 1;
else
dbgi.resp.diswith <= 0;
dbgi.resp.diswithout <= 0;
end if;
pt_pci_target_sync_with_core(dbgi, dbgo);
dbgi.insert <= '0';
end procedure;
procedure pt_remove_resp(
constant addr : std_logic_vector(31 downto 0);
constant rmall : boolean;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type) is
begin
dbgi.insert <= '0';
dbgi.remove <= '1';
if rmall = true then dbgi.rmall <= '1';
else dbgi.rmall <= '0'; end if;
dbgi.addr <= addr;
pt_pci_target_sync_with_core(dbgi, dbgo);
dbgi.remove <= '0';
dbgi.rmall <= '0';
end procedure;
end pt_pkg;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-avnet-xc2v1500/ahbrom.vhd | 3 | 8186 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 464;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03002040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"83480000";
when 16#0002D# => romdata <= X"8330600C";
when 16#0002E# => romdata <= X"80886001";
when 16#0002F# => romdata <= X"02800019";
when 16#00030# => romdata <= X"01000000";
when 16#00031# => romdata <= X"07000000";
when 16#00032# => romdata <= X"8610E118";
when 16#00033# => romdata <= X"C108C000";
when 16#00034# => romdata <= X"C118C000";
when 16#00035# => romdata <= X"C518C000";
when 16#00036# => romdata <= X"C918C000";
when 16#00037# => romdata <= X"CD18E008";
when 16#00038# => romdata <= X"D118C000";
when 16#00039# => romdata <= X"D518C000";
when 16#0003A# => romdata <= X"D918C000";
when 16#0003B# => romdata <= X"DD18C000";
when 16#0003C# => romdata <= X"E118C000";
when 16#0003D# => romdata <= X"E518C000";
when 16#0003E# => romdata <= X"E918C000";
when 16#0003F# => romdata <= X"ED18C000";
when 16#00040# => romdata <= X"F118C000";
when 16#00041# => romdata <= X"F518C000";
when 16#00042# => romdata <= X"F918C000";
when 16#00043# => romdata <= X"10800005";
when 16#00044# => romdata <= X"FD18C000";
when 16#00045# => romdata <= X"01000000";
when 16#00046# => romdata <= X"00000000";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"87444000";
when 16#00049# => romdata <= X"8730E01C";
when 16#0004A# => romdata <= X"8688E00F";
when 16#0004B# => romdata <= X"12800015";
when 16#0004C# => romdata <= X"03200000";
when 16#0004D# => romdata <= X"05040E00";
when 16#0004E# => romdata <= X"8410A2FF";
when 16#0004F# => romdata <= X"C4204000";
when 16#00050# => romdata <= X"0539AE1B";
when 16#00051# => romdata <= X"8410A265";
when 16#00052# => romdata <= X"C4206004";
when 16#00053# => romdata <= X"050003FC";
when 16#00054# => romdata <= X"C4206008";
when 16#00055# => romdata <= X"82103860";
when 16#00056# => romdata <= X"C4004000";
when 16#00057# => romdata <= X"8530A00C";
when 16#00058# => romdata <= X"03000004";
when 16#00059# => romdata <= X"82106009";
when 16#0005A# => romdata <= X"80A04002";
when 16#0005B# => romdata <= X"12800005";
when 16#0005C# => romdata <= X"03200000";
when 16#0005D# => romdata <= X"0539A81B";
when 16#0005E# => romdata <= X"8410A265";
when 16#0005F# => romdata <= X"C4204000";
when 16#00060# => romdata <= X"05000008";
when 16#00061# => romdata <= X"82100000";
when 16#00062# => romdata <= X"80A0E000";
when 16#00063# => romdata <= X"02800005";
when 16#00064# => romdata <= X"01000000";
when 16#00065# => romdata <= X"82004002";
when 16#00066# => romdata <= X"10BFFFFC";
when 16#00067# => romdata <= X"8620E001";
when 16#00068# => romdata <= X"3D1003FF";
when 16#00069# => romdata <= X"BC17A3E0";
when 16#0006A# => romdata <= X"BC278001";
when 16#0006B# => romdata <= X"9C27A060";
when 16#0006C# => romdata <= X"03100000";
when 16#0006D# => romdata <= X"81C04000";
when 16#0006E# => romdata <= X"01000000";
when 16#0006F# => romdata <= X"01000000";
when 16#00070# => romdata <= X"00000000";
when 16#00071# => romdata <= X"00000000";
when 16#00072# => romdata <= X"00000000";
when 16#00073# => romdata <= X"00000000";
when 16#00074# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep3c25/ahbrom.vhd | 28 | 6162 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060C0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03000040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"03200000";
when 16#0002D# => romdata <= X"84102233";
when 16#0002E# => romdata <= X"C4204000";
when 16#0002F# => romdata <= X"0539AE13";
when 16#00030# => romdata <= X"8410A260";
when 16#00031# => romdata <= X"C4206004";
when 16#00032# => romdata <= X"050003FC";
when 16#00033# => romdata <= X"C4206008";
when 16#00034# => romdata <= X"3D1003FF";
when 16#00035# => romdata <= X"BC17A3E0";
when 16#00036# => romdata <= X"9C27A060";
when 16#00037# => romdata <= X"03100000";
when 16#00038# => romdata <= X"81C04000";
when 16#00039# => romdata <= X"01000000";
when 16#0003A# => romdata <= X"01000000";
when 16#0003B# => romdata <= X"01000000";
when 16#0003C# => romdata <= X"01000000";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"01000000";
when 16#0003F# => romdata <= X"01000000";
when 16#00040# => romdata <= X"00000004";
when 16#00041# => romdata <= X"00000000";
when 16#00042# => romdata <= X"00000004";
when 16#00043# => romdata <= X"00000000";
when 16#00044# => romdata <= X"FFFFFFFC";
when 16#00045# => romdata <= X"00000000";
when 16#00046# => romdata <= X"FFFFFFFC";
when 16#00047# => romdata <= X"00000000";
when 16#00048# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/uart/dcom.in.vhd | 6 | 67 | -- DSU UART
constant CFG_AHB_UART : integer := CONFIG_DSU_UART;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/work/debug/grtestmod.vhd | 1 | 6775 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grtestmod
-- File: grtestmod.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Modified: Jan Andersson, Aeroflex Gaisler
-- Contact: [email protected]
-- Description: Test report module
--
-- See also the gaiser.sim.ahbrep module for a module connected via AHB for
-- for use internally on SoC.
--
-- This module supports a 16- or 32-bit interface as selected via the 'width'
-- generic.
--
-- In 32-bit mode the module has the following memory map:
--
-- 0x00 : sets and prints vendor id from data[31:24] and
-- device id from data[23:12]
-- 0x04 : asserts error number data[15:0]
-- 0x08 : calls subtest data[7:0]
-- 0x10 : prints *** GRLIB system test starting ***
-- 0x14 : prints Test passed / errors detected
-- 0x18 : prints Checkpoint data[15:0] with time stamp
--
-- In 16-bit mode the module has the following memory map:
--
-- 0x00 : sets vendor id from data[15:8] and MSbs of device id from data[7:0]
-- 0x04 : asserts error number data[15:0]
-- 0x08 : calls subtest data[7:0]
-- 0x0C : sets LSbs of device id from data[15:12], prints vendor and device id
-- 0x10 : prints *** GRLIB system test starting ***
-- 0x14 : prints Test passed / errors detected
-- 0x18 : prints Checkpoint data[15:0] with time stamp
--
-- The width is defined for the systest software via GRLIB_REPORTDEV_WIDTH
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
use std.textio.all;
entity grtestmod is
generic (
halt : integer := 0;
width : integer := 32);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : in std_ulogic;
address : in std_logic_vector(21 downto 2);
data : inout std_logic_vector(width-1 downto 0);
iosn : in std_ulogic;
oen : in std_ulogic;
writen : in std_ulogic;
brdyn : out std_ulogic := '1';
bexcn : out std_ulogic := '1';
state : out std_logic_vector(1 downto 0);
testdev : out std_logic_vector(19 downto 0);
subtest : out std_logic_vector(7 downto 0)
);
end;
architecture sim of grtestmod is
subtype msgtype is string(1 to 40);
constant ntests : integer := 2;
type msgarr is array (0 to ntests) of msgtype;
constant msg : msgarr := (
"*** Starting GRLIB system test *** ", -- 0
"Test completed OK, halting simulation ", -- 1
"Test FAILED " -- 2
);
signal ior, iow : std_ulogic;
signal addr : std_logic_vector(21 downto 2);
signal ldata : std_logic_vector(width-1 downto 0);
begin
ior <= iosn or oen;
iow <= iosn or writen;
data <= (others => 'Z');
addr <= to_X01(address) after 1 ns;
ldata <= to_X01(data) after 1 ns;
log : process(ior, iow) --, clk)
variable errno, errcnt, lsubtest, vendorid, deviceid : integer;
variable lstate: std_logic_vector(1 downto 0) := "00";
--variable addr : std_logic_vector(21 downto 2);
--variable ldata : std_logic_vector(width-1 downto 0);
begin
--if rising_edge(clk) then
-- addr := to_X01(address);
-- ldata := to_X01(data);
--end if;
if falling_edge (ior) then
brdyn <= '1', '0' after 100 ns;
if addr(15) = '1' then bexcn <= '1', '0' after 100 ns; end if;
elsif rising_edge (ior) then
brdyn <= '1'; bexcn <= '1';
elsif falling_edge(iow) then
brdyn <= '1', '0' after 100 ns;
if addr(15) = '1' then bexcn <= '1', '0' after 100 ns; end if;
elsif rising_edge(iow) then
brdyn <= '1'; bexcn <= '1';
-- addr := to_X01(address);
case addr(7 downto 2) is
when "000000" =>
if width = 32 then
vendorid := conv_integer(ldata(31*(width/32) downto 24*(width/32)));
deviceid := conv_integer(ldata(23*(width/32) downto 12*(width/32)));
print(iptable(vendorid).device_table(deviceid));
testdev <= conv_std_logic_vector(vendorid*256+deviceid,20);
else
vendorid := conv_integer(ldata(15 downto 8));
deviceid := 2**4*conv_integer(ldata(7 downto 0));
end if;
when "000001" =>
errno := conv_integer(ldata(15 downto 0));
if (halt = 0) then
assert false
report "test failed, error (" & tost(errno) & ")"
severity failure;
else
assert false
report "test failed, error (" & tost(errno) & ")"
severity warning;
end if;
lstate := "11";
when "000010" =>
lsubtest := conv_integer(ldata(7 downto 0));
call_subtest(vendorid, deviceid, lsubtest);
subtest <= conv_std_logic_vector(lsubtest,8);
when "000011" =>
if width = 16 then
deviceid := deviceid + conv_integer(ldata(15 downto 12));
print(iptable(vendorid).device_table(deviceid));
testdev <= conv_std_logic_vector(vendorid*256+deviceid,20);
end if;
when "000100" =>
print ("");
print ("**** GRLIB system test starting ****");
errcnt := 0;
if lstate="00" then lstate := "01"; end if;
when "000101" =>
if errcnt = 0 then
print ("Test passed, halting with IU error mode");
if lstate="01" then lstate := "10"; end if;
elsif errcnt = 1 then
print ("1 error detected, halting with IU error mode");
else
print (tost(errcnt) & " errors detected, halting with IU error mode");
end if;
print ("");
when "000110" =>
grlib.testlib.print("Checkpoint " & tost(conv_integer(ldata(15 downto 0))));
when others =>
end case;
end if;
state <= lstate;
end process;
end;
-- pragma translate_on
| gpl-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_sdd1/Output_Manager.vhd | 2 | 30131 | ----------------------------------------------------------------------------------
-- Company: Traducciones Magno
-- Engineer: Magno
--
-- Create Date: 23.03.2018 07:46:09
-- Design Name:
-- Module Name: Output_Manager - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Output_Manager is
Port( clk : in STD_LOGIC;
-- configuration received from DMA
DMA_In_Progress : out STD_LOGIC;
DMA_Transfer_End : in STD_LOGIC;
Header_Valid : in STD_LOGIC;
Header_BPP : in STD_LOGIC_VECTOR(1 downto 0);
-- data input from Probability Estimator
BPP_Bit_tready : out STD_LOGIC;
BPP_Bit_tuser : out STD_LOGIC_VECTOR(9 downto 0);
BPP_Bit_tvalid : in STD_LOGIC;
BPP_Bit_tdata : in STD_LOGIC;
-- data output to DMA
DMA_Data_tready : in STD_LOGIC;
DMA_Data_tvalid : out STD_LOGIC;
DMA_Data_tdata : out STD_LOGIC_VECTOR(7 downto 0) );
end Output_Manager;
architecture Behavioral of Output_Manager is
COMPONENT FIFO_B2B
Generic( FIFO_DEPTH : integer := 32;
PROG_FULL_TH : integer := 16 );
Port( clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din_tready : OUT STD_LOGIC;
din_tvalid : IN STD_LOGIC;
din_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dout_tready : IN STD_LOGIC;
dout_tvalid : OUT STD_LOGIC;
dout_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC );
END COMPONENT;
type TipoEstado is(WAIT_HEADER, SET_MODE7_BITPLANE, SET_2_BITPLANES, SET_4_BITPLANES, SET_8_BITPLANES,
BPP0_BIT_0, BPP0_BIT_1, BPP0_BIT_2, BPP0_BIT_3, BPP0_BIT_4, BPP0_BIT_5, BPP0_BIT_6, BPP0_BIT_7,
BPP0_BIT_0_WAIT, BPP0_BIT_1_WAIT, BPP0_BIT_2_WAIT, BPP0_BIT_3_WAIT, BPP0_BIT_4_WAIT, BPP0_BIT_5_WAIT, BPP0_BIT_6_WAIT, BPP0_BIT_7_WAIT,
BPP1_BIT_0, BPP1_BIT_1, BPP1_BIT_2, BPP1_BIT_3, BPP1_BIT_4, BPP1_BIT_5, BPP1_BIT_6, BPP1_BIT_7, BPP_BIT_STALL,
BPP1_BIT_0_WAIT, BPP1_BIT_1_WAIT, BPP1_BIT_2_WAIT, BPP1_BIT_3_WAIT, BPP1_BIT_4_WAIT, BPP1_BIT_5_WAIT, BPP1_BIT_6_WAIT, BPP1_BIT_7_WAIT,
MODE7_BIT_0, MODE7_BIT_1, MODE7_BIT_2, MODE7_BIT_3, MODE7_BIT_4, MODE7_BIT_5, MODE7_BIT_6, MODE7_BIT_7, MODE7_BIT_STALL,
MODE7_BIT_0_WAIT, MODE7_BIT_1_WAIT, MODE7_BIT_2_WAIT, MODE7_BIT_3_WAIT, MODE7_BIT_4_WAIT, MODE7_BIT_5_WAIT, MODE7_BIT_6_WAIT, MODE7_BIT_7_WAIT );
signal estado : TipoEstado := WAIT_HEADER;
signal BPP0_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP1_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP2_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP3_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP4_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP5_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP6_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP7_Byte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal BPP0_Previous : STD_LOGIC := '0';
signal BPP1_Previous : STD_LOGIC := '0';
signal BPP2_Previous : STD_LOGIC := '0';
signal BPP3_Previous : STD_LOGIC := '0';
signal BPP4_Previous : STD_LOGIC := '0';
signal BPP5_Previous : STD_LOGIC := '0';
signal BPP6_Previous : STD_LOGIC := '0';
signal BPP7_Previous : STD_LOGIC := '0';
signal Tile_Count : integer range 0 to 7 := 0;
signal Max_BPP : integer range 0 to 7 := 0;
signal Cnt_BPP : integer range 0 to 7 := 0;
signal Cnt_Pair : integer range 0 to 3 := 0;
signal Cnt_Even : integer range 0 to 1 := 0;
signal Flag_MODE7_Bitplane : STD_LOGIC := '0';
signal FIFO_Data_tready : STD_LOGIC := '0';
signal FIFO_Data_tready_n : STD_LOGIC := '1';
signal FIFO_Data_tvalid : STD_LOGIC := '0';
signal FIFO_Data_tdata : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal FSM_BPP_Bit_tready : STD_LOGIC := '0';
signal FSM_Reset : STD_LOGIC := '1';
signal FSM_DMA_In_Progress : STD_LOGIC := '0';
signal FSM_New_MODE7 : STD_LOGIC := '0';
signal FSM_Next_BPP0 : STD_LOGIC := '0';
signal FSM_Next_BPP1 : STD_LOGIC := '0';
signal FSM_Ready_BPP0 : STD_LOGIC := '0';
signal FSM_Ready_BPP1 : STD_LOGIC := '0';
signal FSM_Ready_BPP2 : STD_LOGIC := '0';
signal FSM_Ready_BPP3 : STD_LOGIC := '0';
signal FSM_Ready_BPP4 : STD_LOGIC := '0';
signal FSM_Ready_BPP5 : STD_LOGIC := '0';
signal FSM_Ready_BPP6 : STD_LOGIC := '0';
signal FSM_Ready_BPP7 : STD_LOGIC := '0';
signal FSM_Ready_MODE7 : STD_LOGIC := '0';
signal FSM_New_Tile : STD_LOGIC := '0';
begin
-- current bitplane results from concatenation of current even/odd bitplane and
-- number of BPP0/BPP1 to decode
Cnt_BPP <= Cnt_Pair + Cnt_Pair + Cnt_Even;
-- process for controlling data planes
Process( clk )
Begin
if rising_edge( clk ) then
if( FSM_Reset = '1' ) then
Max_BPP <= 0;
Cnt_Pair <= 0;
Tile_Count <= 0;
Flag_MODE7_Bitplane <= '0';
FSM_Ready_MODE7 <= '0';
BPP0_Previous <= '0';
BPP1_Previous <= '0';
BPP2_Previous <= '0';
BPP3_Previous <= '0';
BPP4_Previous <= '0';
BPP5_Previous <= '0';
BPP6_Previous <= '0';
BPP7_Previous <= '0';
BPP0_Byte <= X"00";
BPP1_Byte <= X"00";
BPP2_Byte <= X"00";
BPP3_Byte <= X"00";
BPP4_Byte <= X"00";
BPP5_Byte <= X"00";
BPP6_Byte <= X"00";
BPP7_Byte <= X"00";
FSM_Ready_BPP0 <= '0';
FSM_Ready_BPP2 <= '0';
FSM_Ready_BPP4 <= '0';
FSM_Ready_BPP6 <= '0';
FSM_Ready_BPP1 <= '0';
FSM_Ready_BPP3 <= '0';
FSM_Ready_BPP5 <= '0';
FSM_Ready_BPP7 <= '0';
else
-- set counter's maximum value
if( estado = SET_2_BITPLANES ) then
Max_BPP <= 0;
Cnt_Pair <= 0;
Tile_Count <= 0;
Flag_MODE7_Bitplane <= '0';
elsif( estado = SET_4_BITPLANES ) then
Max_BPP <= 1;
Cnt_Pair <= 0;
Tile_Count <= 0;
Flag_MODE7_Bitplane <= '0';
elsif( estado = SET_8_BITPLANES ) then
Max_BPP <= 3;
Cnt_Pair <= 0;
Tile_Count <= 0;
Flag_MODE7_Bitplane <= '0';
elsif( estado = SET_MODE7_BITPLANE ) then
Max_BPP <= 3;
Cnt_Pair <= 0;
Tile_Count <= 0;
Flag_MODE7_Bitplane <= '1';
end if;
-- when mode "11" (MODE7), each new pixel belongs to a different bitplane
if( Flag_MODE7_Bitplane = '1' ) then
if( FSM_New_MODE7 = '1' ) then
if( Cnt_Pair = Max_BPP ) then
Cnt_Pair <= 0;
else
Cnt_Pair <= Cnt_Pair + 1;
end if;
end if;
else
-- increment bitplane when each the pair BPP0/BPP1 has been complete
if( FSM_Next_BPP1 = '1' ) then
-- when 8 lines of 1 2BPP tile have been complete, change bitplane
if( Tile_Count = 7 ) then
if( Cnt_Pair = Max_BPP ) then
Cnt_Pair <= 0;
else
Cnt_Pair <= Cnt_Pair + 1;
end if;
Tile_Count <= 0;
else
Tile_Count <= Tile_Count + 1;
end if;
end if;
end if;
-- store last decoded bit in corresponding bitplane
if( BPP_Bit_tvalid = '1' ) then
case Cnt_BPP is
-- BPP0
when 0 =>
BPP0_Previous <= BPP0_Byte(7);
BPP0_Byte <= BPP0_Byte(6 downto 0) & BPP_Bit_tdata;
-- BPP1
when 1 =>
BPP1_Previous <= BPP1_Byte(7);
BPP1_Byte <= BPP1_Byte(6 downto 0) & BPP_Bit_tdata;
-- BPP2
when 2 =>
BPP2_Previous <= BPP2_Byte(7);
BPP2_Byte <= BPP2_Byte(6 downto 0) & BPP_Bit_tdata;
-- BPP3
when 3 =>
BPP3_Previous <= BPP3_Byte(7);
BPP3_Byte <= BPP3_Byte(6 downto 0) & BPP_Bit_tdata;
-- BPP4
when 4 =>
BPP4_Previous <= BPP4_Byte(7);
BPP4_Byte <= BPP4_Byte(6 downto 0) & BPP_Bit_tdata;
--BPP5
when 5 =>
BPP5_Previous <= BPP5_Byte(7);
BPP5_Byte <= BPP5_Byte(6 downto 0) & BPP_Bit_tdata;
-- BPP6
when 6 =>
BPP6_Previous <= BPP6_Byte(7);
BPP6_Byte <= BPP6_Byte(6 downto 0) & BPP_Bit_tdata;
-- BPP7
when 7 =>
BPP7_Previous <= BPP7_Byte(7);
BPP7_Byte <= BPP7_Byte(6 downto 0) & BPP_Bit_tdata;
end case;
end if;
-- when MODE7, a new byte is completed when BPP0 is asserted
FSM_Ready_MODE7 <= FSM_Next_BPP0 AND Flag_MODE7_Bitplane;
-- decide which BPP will go to output register when completed
if( FSM_Next_BPP0 = '1' ) then
case Cnt_BPP is
-- BPP0
when 0 =>
FSM_Ready_BPP0 <= '1';
FSM_Ready_BPP2 <= '0';
FSM_Ready_BPP4 <= '0';
FSM_Ready_BPP6 <= '0';
-- BPP2
when 2 =>
FSM_Ready_BPP0 <= '0';
FSM_Ready_BPP2 <= '1';
FSM_Ready_BPP4 <= '0';
FSM_Ready_BPP6 <= '0';
-- BPP4
when 4 =>
FSM_Ready_BPP0 <= '0';
FSM_Ready_BPP2 <= '0';
FSM_Ready_BPP4 <= '1';
FSM_Ready_BPP6 <= '0';
-- BPP6
when 6 =>
FSM_Ready_BPP0 <= '0';
FSM_Ready_BPP2 <= '0';
FSM_Ready_BPP4 <= '0';
FSM_Ready_BPP6 <= '1';
when others =>
FSM_Ready_BPP0 <= '0';
FSM_Ready_BPP2 <= '0';
FSM_Ready_BPP4 <= '0';
FSM_Ready_BPP6 <= '0';
end case;
FSM_Ready_BPP1 <= '0';
FSM_Ready_BPP3 <= '0';
FSM_Ready_BPP5 <= '0';
FSM_Ready_BPP7 <= '0';
elsif( FSM_Next_BPP1 = '1' ) then
case Cnt_BPP is
-- BPP1
when 1 =>
FSM_Ready_BPP1 <= '1';
FSM_Ready_BPP3 <= '0';
FSM_Ready_BPP5 <= '0';
FSM_Ready_BPP7 <= '0';
-- BPP3
when 3 =>
FSM_Ready_BPP1 <= '0';
FSM_Ready_BPP3 <= '1';
FSM_Ready_BPP5 <= '0';
FSM_Ready_BPP7 <= '0';
-- BPP5
when 5 =>
FSM_Ready_BPP1 <= '0';
FSM_Ready_BPP3 <= '0';
FSM_Ready_BPP5 <= '1';
FSM_Ready_BPP7 <= '0';
-- BPP7
when 7 =>
FSM_Ready_BPP1 <= '0';
FSM_Ready_BPP3 <= '0';
FSM_Ready_BPP5 <= '0';
FSM_Ready_BPP7 <= '1';
when others =>
FSM_Ready_BPP1 <= '0';
FSM_Ready_BPP3 <= '0';
FSM_Ready_BPP5 <= '0';
FSM_Ready_BPP7 <= '0';
end case;
FSM_Ready_BPP0 <= '0';
FSM_Ready_BPP2 <= '0';
FSM_Ready_BPP4 <= '0';
FSM_Ready_BPP6 <= '0';
else
FSM_Ready_BPP0 <= '0';
FSM_Ready_BPP2 <= '0';
FSM_Ready_BPP4 <= '0';
FSM_Ready_BPP6 <= '0';
FSM_Ready_BPP1 <= '0';
FSM_Ready_BPP3 <= '0';
FSM_Ready_BPP5 <= '0';
FSM_Ready_BPP7 <= '0';
end if;
end if;
end if;
End Process;
-- pre-calculate context bits and register them
Process( clk )
Begin
if rising_edge( clk ) then
if( FSM_Reset = '1' OR Header_Valid = '1' ) then
BPP_Bit_tuser <= (others => '0');
elsif( BPP_Bit_tvalid = '1' ) then
case Cnt_BPP is
-- BPP0
when 0 =>
-- in any mode, if last decoded bit was BPP0, next plane is BBP1
BPP_Bit_tuser(9) <= '1';
BPP_Bit_tuser(8) <= BPP1_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP1_Byte;
-- BPP1
when 1 =>
-- in 4BPP or 8BPP mode, next plane is BPP2 if a tile is about to start
-- BPP0/BPP1..(x6)..BPP0/BPP1/BPP2/BPP3..(x6)..BPP2/BPP3
-- BPP0/BPP1..(x6)..BPP0/BPP1/BPP2/BPP3..(x6)..BPP2/BPP3/BPP4/BPP5..(x6)..BPP4/BPP5/BPP6/BPP7..(x6)..BPP6/BPP7
if( Max_BPP > 0 AND FSM_New_Tile = '1' ) then
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP2_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP2_Byte;
-- in 2BPP mode, next plane is always BPP0; tile order is
-- BPP0/BPP1..(x6)..BPP0/BPP1
else
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP0_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP0_Byte;
end if;
-- BPP2
when 2 =>
-- in any mode, if last decoded bit was BPP2, next plane is BBP3
BPP_Bit_tuser(9) <= '1';
BPP_Bit_tuser(8) <= BPP3_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP3_Byte;
-- BPP3
when 3 =>
-- in 4BPP, next plane is BPP0 if a tile is about to start
-- BPP0/BPP1..(x6)..BPP0/BPP1/BPP2/BPP3..(x6)..BPP2/BPP3
if( Max_BPP = 1 AND FSM_New_Tile = '1' ) then
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP0_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP0_Byte;
-- in 8BPP mode or MODE7, next plane is BPP4 if a tile is about to start
-- BPP0/BPP1..(x6)..BPP0/BPP1/BPP2/BPP3..(x6)..BPP2/BPP3/BPP4/BPP5..(x6)..BPP4/BPP5/BPP6/BPP7..(x6)..BPP6/BPP7
elsif( Max_BPP = 3 AND FSM_New_Tile = '1' ) then
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP4_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP4_Byte;
-- in any other cases, next plane is BPP2
else
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP2_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP2_Byte;
end if;
-- BPP4
when 4 =>
-- in 8BPP or MODE7 mode, if last decoded bit was BPP4, next plane is BBP5
BPP_Bit_tuser(9) <= '1';
BPP_Bit_tuser(8) <= BPP5_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP5_Byte;
-- BPP5
when 5 =>
-- in 8BPP mode or MODE7, next plane is BPP6 if a tile is about to start
-- BPP0/BPP1..(x6)..BPP0/BPP1/BPP2/BPP3..(x6)..BPP2/BPP3/BPP4/BPP5..(x6)..BPP4/BPP5/BPP6/BPP7..(x6)..BPP6/BPP7
if( Max_BPP = 3 AND FSM_New_Tile = '1' ) then
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP6_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP6_Byte;
-- in any other cases, next plane is BPP4
else
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP4_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP4_Byte;
end if;
-- BPP6
when 6 =>
-- in 8BPP or MODE7 mode, if last decoded bit was BPP6, next plane is BBP7
BPP_Bit_tuser(9) <= '1';
BPP_Bit_tuser(8) <= BPP7_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP7_Byte;
-- BPP7
when 7 =>
-- in 8BPP mode or MODE7, next plane is BPP0 if a tile is about to start
-- BPP0/BPP1..(x6)..BPP0/BPP1/BPP2/BPP3..(x6)..BPP2/BPP3/BPP4/BPP5..(x6)..BPP4/BPP5/BPP6/BPP7..(x6)..BPP6/BPP7
if( Max_BPP = 3 AND FSM_New_Tile = '1' ) then
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP0_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP0_Byte;
-- in any other cases, next plane is BPP6
else
BPP_Bit_tuser(9) <= '0';
BPP_Bit_tuser(8) <= BPP6_Previous;
BPP_Bit_tuser(7 downto 0) <= BPP6_Byte;
end if;
end case;
end if;
end if;
End Process;
-- output data process
Process( FSM_Ready_BPP0, FSM_Ready_BPP1, FSM_Ready_BPP2, FSM_Ready_BPP3, FSM_Ready_BPP4,
FSM_Ready_BPP5, FSM_Ready_BPP6, FSM_Ready_BPP7, BPP0_Byte, BPP1_Byte, BPP2_Byte,
BPP3_Byte, BPP4_Byte, BPP5_Byte, BPP6_Byte, BPP7_Byte, FSM_Ready_MODE7 )
Begin
FIFO_Data_tdata <= X"00";
-- send data to output register
if( FSM_Ready_MODE7 = '1' ) then
FIFO_Data_tdata(0) <= BPP0_Byte(0);
FIFO_Data_tdata(1) <= BPP1_Byte(0);
FIFO_Data_tdata(2) <= BPP2_Byte(0);
FIFO_Data_tdata(3) <= BPP3_Byte(0);
FIFO_Data_tdata(4) <= BPP4_Byte(0);
FIFO_Data_tdata(5) <= BPP5_Byte(0);
FIFO_Data_tdata(6) <= BPP6_Byte(0);
FIFO_Data_tdata(7) <= BPP7_Byte(0);
end if;
if( FSM_Ready_BPP0 = '1' ) then
FIFO_Data_tdata <= BPP0_Byte;
end if;
if( FSM_Ready_BPP1 = '1' ) then
FIFO_Data_tdata <= BPP1_Byte;
end if;
if( FSM_Ready_BPP2 = '1' ) then
FIFO_Data_tdata <= BPP2_Byte;
end if;
if( FSM_Ready_BPP3 = '1' ) then
FIFO_Data_tdata <= BPP3_Byte;
end if;
if( FSM_Ready_BPP4 = '1' ) then
FIFO_Data_tdata <= BPP4_Byte;
end if;
if( FSM_Ready_BPP5 = '1' ) then
FIFO_Data_tdata <= BPP5_Byte;
end if;
if( FSM_Ready_BPP6 = '1' ) then
FIFO_Data_tdata <= BPP6_Byte;
end if;
if( FSM_Ready_BPP7 = '1' ) then
FIFO_Data_tdata <= BPP7_Byte;
end if;
End Process;
FIFO_Data_tvalid <= FSM_Ready_MODE7 OR FSM_Ready_BPP0 OR FSM_Ready_BPP1 OR FSM_Ready_BPP2 OR FSM_Ready_BPP3 OR
FSM_Ready_BPP4 OR FSM_Ready_BPP5 OR FSM_Ready_BPP6 OR FSM_Ready_BPP7;
-- output FIFO
Output_Data : FIFO_B2B
Generic map(32, 30)
Port map(clk => clk,
srst => FSM_Reset,
din_tready => FIFO_Data_tready,
din_tvalid => FIFO_Data_tvalid,
din_tdata => FIFO_Data_tdata,
dout_tready => DMA_Data_tready,
dout_tvalid => DMA_Data_tvalid,
dout_tdata => DMA_Data_tdata,
prog_full => FIFO_Data_tready_n);
-- output signalling
BPP_Bit_tready <= FSM_BPP_Bit_tready;
DMA_In_Progress <= FSM_DMA_In_Progress;
-- finite state machine to ask for BPP bits to Probability Estimator module
Process( clk )
Begin
if rising_edge( clk ) then
if (DMA_Transfer_End = '1') then
estado <= WAIT_HEADER;
else
case estado is
-- wait until header is read from input
when WAIT_HEADER =>
if( Header_Valid = '1' ) then
-- decode 2BPP tiles
if( Header_BPP = "00" ) then
estado <= SET_2_BITPLANES;
-- decode 8BPP tiles
elsif( Header_BPP = "10" ) then
estado <= SET_4_BITPLANES;
-- decode 4BPP tiles
elsif( Header_BPP = "01" ) then
estado <= SET_8_BITPLANES;
-- decode arbitrary data
else
estado <= SET_MODE7_BITPLANE;
end if;
end if;
-- initialize number of BPP0/BPP1 loops
when SET_2_BITPLANES =>
estado <= BPP0_BIT_0;
when SET_4_BITPLANES =>
estado <= BPP0_BIT_0;
when SET_8_BITPLANES =>
estado <= BPP0_BIT_0;
when SET_MODE7_BITPLANE =>
estado <= MODE7_BIT_0;
-- states to create BPP0 and BPP1
-- BPP0/BPP1 pixel 0
when BPP0_BIT_0 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_0_WAIT;
end if;
when BPP0_BIT_0_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_0;
end if;
when BPP1_BIT_0 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_0_WAIT;
end if;
when BPP1_BIT_0_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP0_BIT_1;
end if;
-- BPP0/BPP1 pixel 1
when BPP0_BIT_1 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_1_WAIT;
end if;
when BPP0_BIT_1_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_1;
end if;
when BPP1_BIT_1 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_1_WAIT;
end if;
when BPP1_BIT_1_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP0_BIT_2;
end if;
-- BPP0/BPP1 pixel 2
when BPP0_BIT_2 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_2_WAIT;
end if;
when BPP0_BIT_2_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_2;
end if;
when BPP1_BIT_2 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_2_WAIT;
end if;
when BPP1_BIT_2_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP0_BIT_3;
end if;
-- BPP0/BPP1 pixel 3
when BPP0_BIT_3 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_3_WAIT;
end if;
when BPP0_BIT_3_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_3;
end if;
when BPP1_BIT_3 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_3_WAIT;
end if;
when BPP1_BIT_3_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP0_BIT_4;
end if;
-- BPP0/BPP1 pixel 4
when BPP0_BIT_4 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_4_WAIT;
end if;
when BPP0_BIT_4_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_4;
end if;
when BPP1_BIT_4 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_4_WAIT;
end if;
when BPP1_BIT_4_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP0_BIT_5;
end if;
-- BPP0/BPP1 pixel 5
when BPP0_BIT_5 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_5_WAIT;
end if;
when BPP0_BIT_5_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_5;
end if;
when BPP1_BIT_5 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_5_WAIT;
end if;
when BPP1_BIT_5_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP0_BIT_6;
end if;
-- BPP0/BPP1 pixel 6
when BPP0_BIT_6 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_6_WAIT;
end if;
when BPP0_BIT_6_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_6;
end if;
when BPP1_BIT_6 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_6_WAIT;
end if;
when BPP1_BIT_6_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP0_BIT_7;
end if;
-- BPP0/BPP1 pixel 7
when BPP0_BIT_7 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP0_BIT_7_WAIT;
end if;
when BPP0_BIT_7_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= BPP1_BIT_7;
end if;
when BPP1_BIT_7 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= BPP1_BIT_7_WAIT;
end if;
when BPP1_BIT_7_WAIT =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
elsif( BPP_Bit_tvalid = '1' AND FIFO_Data_tready_n = '0' ) then
estado <= BPP0_BIT_0;
elsif( BPP_Bit_tvalid = '1' AND FIFO_Data_tready_n = '1' ) then
estado <= BPP_BIT_STALL;
end if;
-- wait until FIFO is ready to accept data
when BPP_BIT_STALL =>
if( FIFO_Data_tready_n = '0' ) then
estado <= BPP0_BIT_0;
end if;
-- states to create 8 bitplanes in 1 byte
when MODE7_BIT_0 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_0_WAIT;
end if;
when MODE7_BIT_0_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= MODE7_BIT_1;
end if;
when MODE7_BIT_1 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_1_WAIT;
end if;
when MODE7_BIT_1_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= MODE7_BIT_2;
end if;
when MODE7_BIT_2 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_2_WAIT;
end if;
when MODE7_BIT_2_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= MODE7_BIT_3;
end if;
when MODE7_BIT_3 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_3_WAIT;
end if;
when MODE7_BIT_3_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= MODE7_BIT_4;
end if;
when MODE7_BIT_4 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_4_WAIT;
end if;
when MODE7_BIT_4_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= MODE7_BIT_5;
end if;
when MODE7_BIT_5 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_5_WAIT;
end if;
when MODE7_BIT_5_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= MODE7_BIT_6;
end if;
when MODE7_BIT_6 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_6_WAIT;
end if;
when MODE7_BIT_6_WAIT =>
if( BPP_Bit_tvalid = '1') then
estado <= MODE7_BIT_7;
end if;
when MODE7_BIT_7 =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
else
estado <= MODE7_BIT_7_WAIT;
end if;
when MODE7_BIT_7_WAIT =>
if( DMA_Transfer_End = '1' ) then
estado <= WAIT_HEADER;
elsif( BPP_Bit_tvalid = '1' AND FIFO_Data_tready_n = '0' ) then
estado <= MODE7_BIT_0;
elsif( BPP_Bit_tvalid = '1' AND FIFO_Data_tready_n = '1' ) then
estado <= MODE7_BIT_STALL;
end if;
when MODE7_BIT_STALL =>
if( FIFO_Data_tready_n = '0' ) then
estado <= MODE7_BIT_0;
end if;
end case;
end if;
end if;
End Process;
-- reset output FIFO
FSM_Reset <= '1' when estado = WAIT_HEADER else '0';
-- signals that DMA is running, so data is being outputted from S-DD1
FSM_DMA_In_Progress <= '0' when estado = WAIT_HEADER else '1';
-- strobe to signal a byte for an even bitplane has just completed
with estado select
FSM_Next_BPP0 <= BPP_Bit_tvalid when BPP0_BIT_7_WAIT,
BPP_Bit_tvalid when MODE7_BIT_7_WAIT,
'0' when others;
-- strobe to signal a byte for an odd bitplane has just completed
with estado select
FSM_Next_BPP1 <= BPP_Bit_tvalid when BPP1_BIT_7_WAIT,
'0' when others;
-- strobe to signal a new BPP pixel for MODE7 byte
with estado select
FSM_New_MODE7 <= BPP_Bit_tvalid when MODE7_BIT_1_WAIT,
BPP_Bit_tvalid when MODE7_BIT_3_WAIT,
BPP_Bit_tvalid when MODE7_BIT_5_WAIT,
BPP_Bit_tvalid when MODE7_BIT_7_WAIT,
'0' when others;
-- 2BPP tile or one 8x8 mode7 tile is finished
FSM_New_Tile <= FSM_Next_BPP1 when Tile_Count = 7 else Flag_MODE7_Bitplane;
-- indicates is an even or odd plane is being processed
with estado select
Cnt_Even <= 1 when BPP1_BIT_0,
1 when BPP1_BIT_0_WAIT,
1 when BPP1_BIT_1,
1 when BPP1_BIT_1_WAIT,
1 when BPP1_BIT_2,
1 when BPP1_BIT_2_WAIT,
1 when BPP1_BIT_3,
1 when BPP1_BIT_3_WAIT,
1 when BPP1_BIT_4,
1 when BPP1_BIT_4_WAIT,
1 when BPP1_BIT_5,
1 when BPP1_BIT_5_WAIT,
1 when BPP1_BIT_6,
1 when BPP1_BIT_6_WAIT,
1 when BPP1_BIT_7,
1 when BPP1_BIT_7_WAIT,
1 when MODE7_BIT_1,
1 when MODE7_BIT_1_WAIT,
1 when MODE7_BIT_3,
1 when MODE7_BIT_3_WAIT,
1 when MODE7_BIT_5,
1 when MODE7_BIT_5_WAIT,
1 when MODE7_BIT_7,
1 when MODE7_BIT_7_WAIT,
0 when others;
-- strobe for registering data from previous module
with estado select
FSM_BPP_Bit_tready <= '1' when BPP0_BIT_0,
'1' when BPP1_BIT_0,
'1' when BPP0_BIT_1,
'1' when BPP1_BIT_1,
'1' when BPP0_BIT_2,
'1' when BPP1_BIT_2,
'1' when BPP0_BIT_3,
'1' when BPP1_BIT_3,
'1' when BPP0_BIT_4,
'1' when BPP1_BIT_4,
'1' when BPP0_BIT_5,
'1' when BPP1_BIT_5,
'1' when BPP0_BIT_6,
'1' when BPP1_BIT_6,
'1' when BPP0_BIT_7,
'1' when BPP1_BIT_7,
'1' when MODE7_BIT_0,
'1' when MODE7_BIT_1,
'1' when MODE7_BIT_2,
'1' when MODE7_BIT_3,
'1' when MODE7_BIT_4,
'1' when MODE7_BIT_5,
'1' when MODE7_BIT_6,
'1' when MODE7_BIT_7,
'0' when others;
end Behavioral;
| gpl-2.0 |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx | Frecuencimentro/CountEventsTB.vhd | 2 | 1073 | -- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
<port2> : IN std_logic_vector(3 downto 0);
<port3> : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL <signal1> : std_logic;
SIGNAL <signal2> : std_logic_vector(3 downto 0);
BEGIN
-- Component Instantiation
uut: <component name> PORT MAP(
<port1> => <signal1>,
<port3> => <signal2>
);
-- Test Bench Statements
tb : PROCESS
BEGIN
wait for 100 ns; -- wait until global set/reset completes
-- Add user defined stimulus here
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
| gpl-2.0 |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx | Frecuencimentro/Divisor.vhd | 1 | 1096 | ----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Divisor is
Port (
activacion: in STD_LOGIC;
entrada : in std_logic_vector (31 downto 0);
salida: out std_logic_vector (31 downto 0);
reset_cont: out std_logic);
end Divisor;
architecture Behavioral of Divisor is
signal sal: std_logic_vector (31 downto 0);
signal res: std_logic;
begin
process(activacion)
begin
if activacion='1' then
res<='1';
sal<=entrada;
else
res<='0';
end if;
end process;
salida<=sal;
reset_cont<=res;
end Behavioral; | gpl-2.0 |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx | Frecuencimentro/preesc_tb.vhd | 2 | 1659 | ----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY preesc_tb IS
END preesc_tb;
ARCHITECTURE behavior OF preesc_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT EscaladoPrePresentacion
PORT(
entrada_frec : IN std_logic_vector(31 downto 0);
salida_frec : OUT std_logic_vector(15 downto 0);
salida_uds : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal entrada_frec : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal salida_frec : std_logic_vector(15 downto 0):="0000000000000000";
signal salida_uds : std_logic_vector(1 downto 0):="00";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: EscaladoPrePresentacion PORT MAP (
entrada_frec => entrada_frec,
salida_frec => salida_frec,
salida_uds => salida_uds
);
-- Stimulus process
stim_proc: process
begin
entrada_frec<="00000000000000000100000100010000";
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx | Frecuencimentro/clkTB.vhd | 2 | 1619 | ----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clkTB IS
END clkTB;
ARCHITECTURE behavior OF clkTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT clk_mod
PORT(
entrada : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
signal entrada : std_logic := '0';
signal reset : std_logic := '0';
-- Salidas
signal salida : std_logic;
constant entrada_t : time := 20 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: clk_mod PORT MAP (
entrada => entrada,
reset => reset,
salida => salida
);
-- Definición del reloj.
entrada_process :process
begin
entrada <= '0';
wait for entrada_t / 2;
entrada <= '1';
wait for entrada_t / 2;
end process;
-- Procesamiento de estímulos.
estimulos: process
begin
reset <= '1'; -- Condiciones iniciales.
wait for 100 ns;
reset <= '0'; -- ¡A trabajar!
wait;
end process;
END; | gpl-2.0 |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx | Frecuencimentro/RelojEscaladoTB.vhd | 2 | 1096 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clk200Hz_tb IS
END clk200Hz_tb;
ARCHITECTURE behavior OF clk200Hz_tb IS
COMPONENT clk200Hz
PORT(
entrada : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
signal entrada : std_logic := '0';
signal reset : std_logic := '0';
-- Salidas
signal salida : std_logic;
constant entrada_t : time := 20 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: clk200Hz PORT MAP (
entrada => entrada,
reset => reset,
salida => salida
);
-- Definición del reloj.
entrada_process :process
begin
entrada <= '0';
wait for entrada_t / 2;
entrada <= '1';
wait for entrada_t / 2;
end process;
-- Procesamiento de estímulos.
estimulos: process
begin
reset <= '1'; -- Condiciones iniciales.
wait for 100 ns;
reset <= '0'; -- ¡A trabajar!
wait;
end process;
END; | gpl-2.0 |
Charlesworth/Albot | Albot VHDL/lpm_compare0.vhd | 1 | 3968 | -- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_compare
-- ============================================================
-- File Name: lpm_compare0.vhd
-- Megafunction Name(s):
-- lpm_compare
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare0 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
AleB : OUT STD_LOGIC
);
END lpm_compare0;
ARCHITECTURE SYN OF lpm_compare0 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_compare
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
AleB : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
AleB <= sub_wire0;
lpm_compare_component : lpm_compare
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 32
)
PORT MAP (
dataa => dataa,
datab => datab,
AleB => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "1"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: AleB 0 0 0 0 OUTPUT NODEFVAL AleB
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
-- Retrieval info: CONNECT: AleB 0 0 0 0 @AleB 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0_inst.vhd TRUE
| gpl-2.0 |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_phyAct.vhd | 3 | 4237 | -------------------------------------------------------------------------------
--
-- Title : OpenMAC_phyAct
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : OpenMAC_phyAct.vhd
-- Generated : Wed Jul 27 12:01:32 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-07-27 V0.01 zelenkaj First version
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {OpenMAC_phyAct} architecture {rtl}}
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity OpenMAC_phyAct is
generic(
iBlinkFreq_g : integer := 6 -- [Hz]
);
port(
clk : in std_logic;
rst : in std_logic;
tx_en : in std_logic;
rx_dv : in std_logic;
act_led : out std_logic
);
end OpenMAC_phyAct;
--}} End of automatically maintained section
architecture rtl of OpenMAC_phyAct is
constant iMaxCnt : integer := 50e6 / iBlinkFreq_g;
constant iLog2MaxCnt : integer := integer(ceil(log2(real(iMaxCnt))));
signal cnt : std_logic_vector(iLog2MaxCnt-1 downto 0);
signal cnt_tc : std_logic;
signal actTrig : std_logic;
signal actEnable : std_logic;
begin
act_led <= cnt(cnt'high) when actEnable = '1' else '0';
ledCntr : process(clk, rst)
begin
if rst = '1' then
actTrig <= '0';
actEnable <= '0';
elsif clk = '1' and clk'event then
--monoflop, of course no default value!
if actTrig = '1' and cnt_tc = '1' then
--counter overflow and activity within last cycle
actEnable <= '1';
elsif cnt_tc = '1' then
--counter overflow but no activity
actEnable <= '0';
end if;
--monoflop, of course no default value!
if cnt_tc = '1' then
--count cycle over, reset trigger
actTrig <= '0';
elsif tx_en = '1' or rx_dv = '1' then
--activity within cycle
actTrig <= '1';
end if;
end if;
end process;
theFreeRunCnt : process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
elsif clk = '1' and clk'event then
--nice, it may count for ever!
cnt <= cnt - 1;
end if;
end process;
cnt_tc <= '1' when cnt = 0 else '0'; --"counter overflow"
end rtl;
| gpl-2.0 |
todesking/exuberant-ctags | Test/test.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
gauravks/i210dummy | Examples/altera_nios2/ipcore/powerlink/src/openMAC_rmii2mii.vhd | 3 | 8911 | ------------------------------------------------------------------------------------------------------------------------
-- RMII to MII converter
-- ex: openMAC - openHUB - RMII2MII - MII PHY
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: Used DPR is specific to Altera/Xilinx. Use one of the following files:
-- OpenMAC_DPR_Altera.vhd
-- OpenMAC_DPR_Xilinx.vhd
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-09-13 V0.01 first version
-- 2010-11-15 V0.02 bug fix: increased size of rx fifo, because of errors with marvel 88e1111 mii phy
-- 2010-11-30 V0.03 bug fix: in case of no link some phys confuse tx fifo during tx => aclr fifo
-- 2011-05-06 V0.10 bug fix: use the RX_ER signal, it has important meaning!
-- 2011-07-23 V0.11 forward RxErr to RMII
-- 2011-10-13 V0.20 abuse openMAC_DMAFifo for the converter to use it in Altera/Xilinx easily
-- 2011-11-07 V0.21 increased fifo word size to be on the save side
-- 2011-11-18 V0.22 forward of RxErr not necessary
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rmii2mii is
port (
clk50 : in std_logic; --used by RMII as well!!!
rst : in std_logic;
--RMII (MAC)
rTxEn : in std_logic;
rTxDat : in std_logic_vector(1 downto 0);
rRxDv : out std_logic;
rRxDat : out std_logic_vector(1 downto 0);
rRxEr : out std_logic;
--MII (PHY)
mTxEn : out std_logic;
mTxDat : out std_logic_vector(3 downto 0);
mTxClk : in std_logic;
mRxDv : in std_logic;
mRxEr : in std_logic;
mRxDat : in std_logic_vector(3 downto 0);
mRxClk : in std_logic
);
end rmii2mii;
architecture rtl of rmii2mii is
constant DIBIT_SIZE : integer := 2;
constant NIBBLE_SIZE : integer := 4;
begin
TX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid, fifo_wrempty : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
--necessary for clr fifo
signal aclr, rTxEn_l : std_logic;
--convert dibits to nibble
signal sel_dibit : std_logic;
signal fifo_din_reg : std_logic_vector(rTxDat'range);
begin
fifo_din <= rTxDat & fifo_din_reg;
fifo_wr <= sel_dibit;
--convert dibits to nibble (to fit to fifo)
process(clk50, rst)
begin
if rst = '1' then
sel_dibit <= '0';
fifo_din_reg <= (others => '0');
elsif clk50 = '1' and clk50'event then
if rTxEn = '1' then
sel_dibit <= not sel_dibit;
if sel_dibit = '0' then
fifo_din_reg <= rTxDat;
end if;
else
sel_dibit <= '0';
end if;
end if;
end process;
mTxDat <= fifo_dout; --brauch ma net... when fifo_valid = '1' else (others => '0');
mTxEn <= fifo_valid;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
process(mTxClk, rst)
begin
if rst = '1' then
fifo_rd <= '0';
fifo_valid <= '0';
elsif mTxClk = '1' and mTxClk'event then
if fifo_rd = '0' and fifo_half = '1' then
fifo_rd <= '1';
elsif fifo_rd = '1' and fifo_empty = '1' then
fifo_rd <= '0';
end if;
if fifo_rd = '1' and fifo_rdUsedWord > conv_std_logic_vector(1, fifo_rdUsedWord'length) then
fifo_valid <= '1';
else
fifo_valid <= '0';
end if;
end if;
end process;
--abuse openMAC's DMA FIFO
theRMII2MII_TXFifo : entity work.openMAC_DMAfifo
generic map (
fifo_data_width_g => NIBBLE_SIZE,
fifo_word_size_g => 2**FIFO_NIBBLES_LOG2,
fifo_word_size_log2_g => FIFO_NIBBLES_LOG2
)
port map (
aclr => aclr,
rd_clk => mTxClk,
wr_clk => clk50,
--read port
rd_req => fifo_rd,
rd_data => fifo_dout,
rd_empty => fifo_empty,
rd_full => open,
rd_usedw => fifo_rdUsedWord,
--write port
wr_req => fifo_wr,
wr_data => fifo_din,
wr_empty => fifo_wrempty,
wr_full => fifo_full,
wr_usedw => fifo_wrUsedWord
);
--sync Mii Tx En (=fifo_valid) to wr clk
process(clk50, rst)
begin
if rst = '1' then
aclr <= '1'; --reset fifo
rTxEn_l <= '0';
elsif clk50 = '1' and clk50'event then
rTxEn_l <= rTxEn;
aclr <= '0'; --default
--clear the full fifo after TX on RMII side is done
if fifo_full = '1' and rTxEn_l = '1' and rTxEn = '0' then
aclr <= '1';
end if;
end if;
end process;
end block;
RX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
--convert nibble to dibits
signal sel_dibit : std_logic;
signal fifo_rd_s : std_logic;
begin
fifo_din <= mRxDat;
fifo_wr <= mRxDv and not mRxEr;
rRxDat <= fifo_dout(fifo_dout'right+1 downto 0) when sel_dibit = '1' else
fifo_dout(fifo_dout'left downto fifo_dout'left-1);
rRxDv <= fifo_valid;
fifo_rd <= fifo_rd_s and not sel_dibit;
process(clk50, rst)
begin
if rst = '1' then
sel_dibit <= '0';
elsif clk50 = '1' and clk50'event then
if fifo_rd_s = '1' or fifo_valid = '1' then
sel_dibit <= not sel_dibit;
else
sel_dibit <= '0';
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
rRxEr <= '0';
process(clk50, rst)
begin
if rst = '1' then
fifo_rd_s <= '0';
fifo_valid <= '0';
elsif clk50 = '1' and clk50'event then
if fifo_rd_s = '0' and fifo_half = '1' then
fifo_rd_s <= '1';
elsif fifo_rd_s = '1' and fifo_empty = '1' then
fifo_rd_s <= '0';
end if;
if fifo_rd_s = '1' then
fifo_valid <= '1';
else
fifo_valid <= '0';
end if;
end if;
end process;
--abuse openMAC's DMA FIFO
theMII2RMII_RXFifo : entity work.openMAC_DMAfifo
generic map (
fifo_data_width_g => NIBBLE_SIZE,
fifo_word_size_g => 2**FIFO_NIBBLES_LOG2,
fifo_word_size_log2_g => FIFO_NIBBLES_LOG2
)
port map (
aclr => rst,
rd_clk => clk50,
wr_clk => mRxClk,
--read port
rd_req => fifo_rd,
rd_data => fifo_dout,
rd_empty => fifo_empty,
rd_full => open,
rd_usedw => fifo_rdUsedWord,
--write port
wr_req => fifo_wr,
wr_data => fifo_din,
wr_empty => open,
wr_full => fifo_full,
wr_usedw => fifo_wrUsedWord
);
end block;
end rtl;
| gpl-2.0 |
bert/geda-gaf | gnetlist/examples/vams/vhdl/basic-vhdl/capacitor.vhdl | 15 | 320 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CAPACITOR IS
GENERIC ( v_init : REAL := 0.0;
c : REAL := 10.0e-12 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CAPACITOR;
| gpl-2.0 |
Charlesworth/Albot | Albot VHDL/lpm_counter1.vhd | 1 | 4361 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter1.vhd
-- Megafunction Name(s):
-- lpm_counter
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter1 IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
cnt_en : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END lpm_counter1;
ARCHITECTURE SYN OF lpm_counter1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
cnt_en : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(9 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 10
)
PORT MAP (
aclr => aclr,
clock => clock,
cnt_en => cnt_en,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASETV NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSETV NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "10"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL cnt_en
-- Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL q[9..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0
-- Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1_inst.vhd TRUE
| gpl-2.0 |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/axi_powerlink_v1_00_a/hdl/vhdl/openMAC_PHYMI.vhd | 3 | 5745 | ------------------------------------------------------------------------------------------------------------------------
-- Phy Management Interface for OpenMAC
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted to official version.
-- 2009-09-07 V0.02 zelenkaj Changed tristate port to In/Out and enable (Xilinx XPS doesn't like IO Ports...)
-- 2009-09-18 V0.03 zelenkaj Deleted NodeNr - isn't used by anyone...
-- 2011-11-28 V0.04 zelenkaj Changed reset level to high-active
-- 2012-07-30 V0.05 zelenkaj Omit internal tbuf
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY OpenMAC_MII IS
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Addr : IN std_logic_vector( 2 DOWNTO 0);
Sel : IN std_logic;
nBe : IN std_logic_vector( 1 DOWNTO 0);
nWr : IN std_logic;
Data_In : IN std_logic_vector(15 DOWNTO 0);
Data_Out : OUT std_logic_vector(15 DOWNTO 0);
Mii_Clk : OUT std_logic;
Mii_Di : IN std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic; --'1' ... Input / '0' ... Output!!!
nResetOut : OUT std_logic
);
END ENTITY OpenMAC_MII;
ARCHITECTURE struct OF OpenMAC_MII IS
SIGNAL ShiftReg : std_logic_vector (31 DOWNTO 0);
SIGNAL iMiiClk : std_logic;
SIGNAL ClkDiv : std_logic_vector (4 DOWNTO 0);
ALIAS Shift : std_logic IS ClkDiv(ClkDiv'high);
SIGNAL BitCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL BytCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL Run, SrBusy, nReset : std_logic;
SIGNAL M_Dout, M_Oe : std_logic;
BEGIN
Data_Out <= x"00" & nReset & x"0" & "00" & SrBusy WHEN Addr(0) = '0' ELSE
ShiftReg(15 DOWNTO 0);
Mii_Clk <= iMiiClk;
Mii_Do <= M_Dout;
Mii_Doe <= not M_Oe;
nresetout <= nReset;
p_Mii: PROCESS (Clk, Rst)
BEGIN
IF Rst = '1' THEN
iMiiClk <= '0'; Run <= '0'; SrBusy <= '0'; M_Oe <= '1'; M_Dout <= '1'; nReset <= '0';
BitCnt <= (OTHERS => '0'); BytCnt <= (OTHERS => '0');
ShiftReg <= x"0000ABCD"; ClkDiv <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Shift = '1' THEN ClkDiv <= conv_std_logic_vector( 8, ClkDiv'high + 1);
iMiiClk <= NOT iMiiClk;
ELSE ClkDiv <= ClkDiv - 1;
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '1' AND nBE(0) = '0' THEN nReset <= Data_In(7);
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '0' THEN
IF Addr(0) = '0' THEN
IF nBE(1) = '0' THEN ShiftReg(31 DOWNTO 24) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg(23 DOWNTO 16) <= Data_In( 7 DOWNTO 0);
SrBusy <= '1';
END IF;
ELSE
IF nBE(1) = '0' THEN ShiftReg(15 DOWNTO 8) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg( 7 DOWNTO 0) <= Data_In( 7 DOWNTO 0);
END IF;
END IF;
ELSE
IF Shift = '1' AND iMiiClk = '1' THEN
IF Run = '0' AND SrBusy = '1' THEN
Run <= '1';
BytCnt <= "111";
BitCnt <= "111";
ELSE
IF BytCnt(2) = '0' AND SrBusy = '1' THEN
M_Dout <= ShiftReg(31);
ShiftReg <= ShiftReg(30 DOWNTO 0) & Mii_Di; -- & Mii_Dio;
END IF;
BitCnt <= BitCnt - 1;
IF BitCnt = 0 THEN
BytCnt <= BytCnt - 1;
IF BytCnt = 0 THEN
SrBusy <= '0';
Run <= '0';
END IF;
END IF;
IF BytCnt = 2 AND BitCnt = 1 AND ShiftReg(31) = '0' THEN
M_Oe <= '0';
END IF;
END IF;
IF SrBusy = '0' OR Run = '0' THEN
M_Dout <= '1';
M_Oe <= '1';
END IF;
END IF;
END IF;
END IF;
END PROCESS p_Mii;
END struct; | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd | 2 | 5892 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating
-- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_xlnx_2Kx36_2clk IS
port (
din: IN std_logic_VECTOR(35 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(35 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
rd_data_count: OUT std_logic_VECTOR(11 downto 0);
wr_data_count: OUT std_logic_VECTOR(11 downto 0));
END fifo_xlnx_2Kx36_2clk;
ARCHITECTURE fifo_xlnx_2Kx36_2clk_a OF fifo_xlnx_2Kx36_2clk IS
-- synthesis translate_off
component wrapped_fifo_xlnx_2Kx36_2clk
port (
din: IN std_logic_VECTOR(35 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(35 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
rd_data_count: OUT std_logic_VECTOR(11 downto 0);
wr_data_count: OUT std_logic_VECTOR(11 downto 0));
end component;
-- Configuration specification
for all : wrapped_fifo_xlnx_2Kx36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral)
generic map(
c_has_int_clk => 0,
c_rd_freq => 1,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 1,
c_din_width => 36,
c_has_wr_data_count => 1,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 0,
c_dout_width => 36,
c_msgon_val => 1,
c_rd_depth => 2048,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 12,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 11,
c_use_fwft_data_count => 1,
c_has_almost_empty => 0,
c_rd_data_count_width => 12,
c_enable_rlocs => 0,
c_wr_pntr_width => 11,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 12,
c_preload_regs => 1,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 2046,
c_wr_depth => 2048,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_thresh_assert_val => 4,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 2047,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "2kx18",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_xlnx_2Kx36_2clk
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
rd_data_count => rd_data_count,
wr_data_count => wr_data_count);
-- synthesis translate_on
END fifo_xlnx_2Kx36_2clk_a;
| gpl-2.0 |
bert/geda-gaf | gnetlist/examples/vams/vhdl/basic-vhdl/spice_cs_arc.vhdl | 15 | 244 | ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
| gpl-2.0 |
Charlesworth/Albot | Albot VHDL/AddDiv.vhd | 1 | 510 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity bit_AddDiv is
port
(in_Bus : in std_logic_vector(7 downto 0);
out_bus : out std_logic_vector(7 downto 0);
WindowEnable : in std_logic;
clk : in std_logic;
U_enable : std_logic
);
end bit_AddDiv;
architecture str_AddDiv of bit_AddDiv is
begin
A_BUS: process(in_bus, WindowEnable, clk, U_enable)
begin
if (WindowEnable = '1') and (clk = '1') and (U_enable = '1')
then
out_bus <= in_bus;
end if;
end Process A_BUS;
end str_AddDiv;
| gpl-2.0 |
klyone/wishbone-gen | lib/wbgen2_dpssram.vhd | 1 | 3023 | library ieee;
use ieee.std_logic_1164.all;
--use work.genram_pkg.all;
--use work.common_components.all;
--library wbgen2;
use work.wbgen2_pkg.all;
entity wbgen2_dpssram is
generic (
g_data_width : natural := 32;
g_size : natural := 1024;
g_addr_width : natural := 10;
g_dual_clock : boolean := true;
g_use_bwsel : boolean := true);
port (
clk_a_i : in std_logic;
clk_b_i : in std_logic;
addr_a_i : in std_logic_vector(g_addr_width-1 downto 0);
addr_b_i : in std_logic_vector(g_addr_width-1 downto 0);
data_a_i : in std_logic_vector(g_data_width-1 downto 0);
data_b_i : in std_logic_vector(g_data_width-1 downto 0);
data_a_o : out std_logic_vector(g_data_width-1 downto 0);
data_b_o : out std_logic_vector(g_data_width-1 downto 0);
bwsel_a_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
bwsel_b_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
rd_a_i : in std_logic;
rd_b_i : in std_logic;
wr_a_i : in std_logic;
wr_b_i : in std_logic
);
end wbgen2_dpssram;
architecture syn of wbgen2_dpssram is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I > A) then
return(I-1);
end if;
end loop;
return(63);
end function f_log2_size;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector(g_data_width/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector(g_data_width/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
begin
wrapped_dpram: generic_dpram
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_use_bwsel,
g_dual_clock => g_dual_clock)
port map (
rst_n_i => '1',
clka_i => clk_a_i,
bwea_i => bwsel_a_i,
wea_i => wr_a_i,
aa_i => addr_a_i,
da_i => data_a_i,
qa_o => data_a_o,
clkb_i => clk_b_i,
bweb_i => bwsel_b_i,
web_i => wr_b_i,
ab_i => addr_b_i,
db_i => data_b_i,
qb_o => data_b_o);
end syn;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine/TEST_CTRL_TELEGRAM_CHECK/CTRL_TELEGRAM_CHECK.vhd | 4 | 24417 | -- CTRL_TELEGRAM_CHECK
-- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 02.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 28.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_TELEGRAM_CHECK is
Port (TELEGRAM_RUN : in std_logic; --Eingangsvariable, Naechstes Telegram
BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, Byte, 8bit
PARITY_OK : in std_logic; --Eingangsvariable, Paritaet i.O.
BYTE_CMPLT : in std_logic; --Eingangsvariable, BYTE komplett empfangen
PAUSE_END : in std_logic; --Eingangsvariable, Pause erkannt und beendet
TELEGRAM_STOP : in std_logic; --Eingangsvariable, nach Telegramm stoppen
ERROR_CTRL : in std_logic; --Eingangsvariable, Fehlerkontrolle
T_END : out std_logic; --Ausgangsvariable, Telegramm zu Ende
T_LENGTH : out std_logic_vector (7 downto 0); --Ausgangsvariable, Telegramlaenge, 8bit
T_TYPE : out std_logic_vector (3 downto 0); --Ausgangsvariable, Telegramtyp, 4bit
SEND_OUT : out std_logic; --Ausgangsvariable, Senden
PARITY_FAIL : out std_logic; --Ausgangsvariable, Paritaetsprüfung fehlerhaft
NO_ED : out std_logic; --Ausgangsvariable, kein Enddelimiter festgestellt
WORKING : out std_logic; --Ausgangsvariable, TELEGRAM_CHECK arbeitet
KNOWN_T : out std_logic; --Ausgangsvariable, Telegramm erkannt
UNKNOWN_BYTE : out std_logic; --Ausgangsvariable, BYTE nicht erkannt
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL_COUNT : in std_logic; --Eingangsvariable, Zähler anzeigen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_TELEGRAM_CHECK;
architecture Behavioral of CTRL_TELEGRAM_CHECK is
type TYPE_STATE is
(ST_TC_00, --Zustaende TELEGRAM_CHECK
ST_TC_01,
ST_TC_02,
ST_TC_03,
ST_TC_04,
ST_TC_05,
ST_TC_06,
ST_TC_07,
ST_TC_08,
ST_TC_09,
ST_TC_10,
ST_TC_11);
signal SV : TYPE_STATE := ST_TC_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_TC_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_TC_00; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit
signal n_COUNT : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit, neuer Wert
signal COUNT_M : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit, Ausgang Master
signal STATE_SV : std_logic_vector (7 downto 0) := x"00"; -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0) := x"00"; -- Folgezustand in 8 Bit, binär
begin
SREG_M_PROC: process (RESET, n_SV, n_COUNT, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_TC_00;
COUNT_M <= x"00";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then
SV_M <= n_SV;
COUNT_M <= n_COUNT;
else
SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, CLK) --Slave
begin
if (RESET = '1')
then
SV <= ST_TC_00;
COUNT <= x"00";
else
if falling_edge(CLK)
then
SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
TELEGRAM_CHECK_PROC: process (SV, COUNT, TELEGRAM_RUN, PAUSE_END, BYTE_CMPLT, PARITY_OK, BYTE_IN, TELEGRAM_STOP, ERROR_CTRL) --Telegramme erkennen und Ende Telegram erkennen und ausgeben
begin
case SV is
when ST_TC_00 =>
if (TELEGRAM_RUN = '1')
then
if (PAUSE_END = '1')
then
--TC01
n_COUNT <= COUNT; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_01; --Zustandsübergang
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if;
else --TELEGRAM_RUN = '0'
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if;
when ST_TC_01 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (BYTE_IN = x"10") --SD1 erkannt
then
--TC02
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02; --Zustandsübergang
else
if (BYTE_IN = x"68") --SD2 erkannt
then
--TC05
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03; --Zustandsübergang
else
if (BYTE_IN = x"A2") --SD3 erkannt
then
--TC08
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04; --Zustandsübergang
else
if (BYTE_IN = x"DC") --SD4 erkannt
then
--TC11
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05; --Zustandsübergang
else
if (BYTE_IN = x"E5") --SC erkannt
then
--TC14
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '1'; --Telgeram Ende
T_LENGTH <= COUNT;
T_TYPE <= "1000"; --SC
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsübergang
else
if (TELEGRAM_STOP = '1')
then
--TC15
n_COUNT <= COUNT; --Zaehler bleibt gleich
T_END <= '0'; --Telgeram Ende
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '1'; --Unbekanntes BYTE
n_SV <= ST_TC_06; --Zustandsübergang
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if; --TELEGRAM_STOP
end if; --BYTE_IN =x"E5"
end if; --BYTE_IN = x"DC"
end if; --BYTE_IN = x"A2"
end if; --BYTE_IN = x"68"
end if; --BYTE_IN = x"10"
else ----PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC01
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_01;
end if; --BYTE_CMPLT = '1'
when ST_TC_02 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"06")
then
if (BYTE_IN = x"16")
then
--TC04
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
end if; --BYTE_IN = x"16"
else --not COUNT = x"06"
--TC02
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02;
end if; --COUNT = x"06"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC03
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02;
end if; --BYTE_CMPLT = '1'
when ST_TC_03 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (BYTE_IN = x"16")
then
--TC07
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else
if (COUNT = x"FF") --255
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
else --not COUNT = x"FF"
--TC05
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03;
end if; --COUNT = x"FF"
end if; --BYTE_IN = x"16"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC06
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03;
end if; --BYTE_CMPLT = '1'
when ST_TC_04 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"0E") --14
then
if (BYTE_IN = x"16")
then
--TC10
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else --not BYTE_IN = x"16"
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
end if; --BYTE_IN = x"16"
else --not COUNT = x"0E"
--TC08
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04;
end if; --COUNT = x"0E"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC09
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04;
end if; --BYTE_CMPLT = '1'
when ST_TC_05 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"03")
then
--TC13
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else --not COUNT = x"03"
--TC11
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05;
end if; --COUNT = x"03"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC12
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05;
end if; --BYTE_CMPLT = '1'
when ST_TC_06 =>
if (TELEGRAM_STOP = '1')
then
--TC15
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '1'; --Kein bekanntes Startdelimiter-Byte gefunden
n_SV <= ST_TC_06;
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_07 =>
if (TELEGRAM_STOP = '1')
then
--TC16
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '1'; --Bekanntes Telegramm gefunden
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07;
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_08 =>
if (ERROR_CTRL = '1')
then
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_09; --Zustandsuebergang
else
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08;
end if;
when ST_TC_09 =>
if (ERROR_CTRL = '1')
then
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_09;
else
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_10 =>
if (ERROR_CTRL = '1')
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_11; --Zustandsuebergang
else
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10;
end if;
when ST_TC_11 =>
if (ERROR_CTRL = '1')
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_11;
else
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when others =>
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV, DISPL_COUNT, COUNT) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
if (DISPL_COUNT = '1')
then
-- Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT(0);
DISPL1_n_SV(1) <= COUNT(1);
DISPL1_n_SV(2) <= COUNT(2);
DISPL1_n_SV(3) <= COUNT(3);
DISPL2_n_SV(0) <= COUNT(4);
DISPL2_n_SV(1) <= COUNT(5);
DISPL2_n_SV(2) <= COUNT(6);
DISPL2_n_SV(3) <= COUNT(7);
else
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/Rueckfallposition_19_12_2012/PROFI_MON_25MHZ_CTRL_SRAM/CLOCK_SINGLE_RUN_SRC.vhd | 26 | 2585 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CLOCK_SINGLE_RUN_SRC is
Port ( CLK: in std_logic; -- (System) Takt
SINGLE: in std_logic; -- 1: Einzeltakt
RUN_R: in std_logic; -- 1: Dauerbetrieb
-- mit Eingangsregister
RESET: in std_logic; -- 1: Initialzustand soll angenommen werden
OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand
end CLOCK_SINGLE_RUN_SRC;
architecture Behavioral of CLOCK_SINGLE_RUN_SRC is
type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände
signal SV: TYPE_STATE; --Zustangsvariable
signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master
signal RUN_S: std_logic;
signal not_CLK : std_logic;
begin
NOT_CLK_PROC: process (CLK)
begin
not_CLK <= not CLK;
end process;
IREG_PROC: process (RUN_R, not_CLK)
begin
if (not_CLK'event and not_CLK = '1')
then RUN_S <= RUN_R;
end if;
end process;
IL_OL_PROC: process (SINGLE, RUN_S, SV)
begin
case SV is
when CSR_0 =>
if (SINGLE = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2;
else
if (RUN_S = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
end if;
when CSR_1 => OUT_NEXT_STATE <= '0';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
end if;
when CSR_2 => OUT_NEXT_STATE <= '1';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
when others => OUT_NEXT_STATE <= '0';
end case;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) -- Master
begin
if(RESET = '1')
then SV_M <= CSR_0;
else
if (CLK'event and CLK = '1')
then SV_M <= n_SV;
else SV_M <= SV_M;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave
begin
if(RESET = '1')
then SV <= CSR_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/Rueckfallposition_14_12_2012/TEST_CTRL_9P6_50MHZ_SCH/CLOCK_SINGLE_RUN_SRC.vhd | 12 | 2560 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CLOCK_SINGLE_RUN_SRC is
Port ( CLK: in std_logic; -- (System) Takt
SINGLE: in std_logic; -- 1: Einzeltakt
RUN_R: in std_logic; -- 1: Dauerbetrieb
-- mit Eingangsregister
RESET: in std_logic; -- 1: Initialzustand soll angenommen werden
OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand
end CLOCK_SINGLE_RUN_SRC;
architecture Behavioral of CLOCK_SINGLE_RUN_SRC is
type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände
signal SV: TYPE_STATE; --Zustangsvariable
signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master
signal RUN_S: std_logic;
signal not_CLK : std_logic;
begin
NOT_CLK_PROC: process (CLK)
begin
not_CLK <= not CLK;
end process;
IREG_PROC: process (RUN_R, not_CLK)
begin
if (not_CLK'event and not_CLK = '1')
then RUN_S <= RUN_R;
end if;
end process;
IL_OL_PROC: process (SINGLE, RUN_S, SV)
begin
case SV is
when CSR_0 =>
if (SINGLE = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2;
else
if (RUN_S = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
end if;
when CSR_1 => OUT_NEXT_STATE <= '0';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
end if;
when CSR_2 => OUT_NEXT_STATE <= '1';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
when others => OUT_NEXT_STATE <= '0';
end case;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) -- Master
begin
if(RESET = '1')
then SV_M <= CSR_0;
else
if (CLK'event and CLK = '1')
then SV_M <= n_SV;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave
begin
if(RESET = '1')
then SV <= CSR_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/PROFIBUS_MONITOR/CTRL_InAB_INPUT_VHDL.vhd | 4 | 27282 | -- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_InAB_INPUT_VHDL is
Port (InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
EN_BIT_i : out std_logic_vector (8 downto 0); --Ausgangsvariable, Enable Bit i, 9bit
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_CMPLT: out std_logic; --Ausgangsvariabel, Byte empfangen und komplett
PAUSE_END : out std_logic; --Ausgangssignal, Pause zu Ende
CLK : in std_logic; --Taktvariable
-- CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_InAB_INPUT_VHDL;
architecture Behavioral of CTRL_InAB_INPUT_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F);--15
signal SV : TYPE_STATE := ST_CTRL_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, Ausgang Master
signal COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal InAB_S : std_logic := '0'; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
--signal not_CLK : std_logic; --negierte Taktvariable
--signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal EN_BIT_0 : std_logic := '0'; --BIT0
signal EN_BIT_1 : std_logic := '0'; --BIT1
signal EN_BIT_2 : std_logic := '0'; --BIT2
signal EN_BIT_3 : std_logic := '0'; --BIT3
signal EN_BIT_4 : std_logic := '0'; --BIT4
signal EN_BIT_5 : std_logic := '0'; --BIT5
signal EN_BIT_6 : std_logic := '0'; --BIT6
signal EN_BIT_7 : std_logic := '0'; --BIT7
signal EN_BIT_8 : std_logic := '0'; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0) := x"00000"; --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT02 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT03 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT04 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT05 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT06 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT07 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT08 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT09 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT10 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT11 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT12 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT13 : std_logic_vector (15 downto 0) := x"0000";
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"D9B1";
constant long_CNTT13 : std_logic_vector := x"E5E6";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
---NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
--begin
-- not_CLK_IO <= not CLK_IO;
--end process;
IREG_PROC: process (InAB, InAB_S, CLK) --Eingangsregister
begin
if falling_edge(CLK) --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
COUNT_L_M <= x"00000";
COUNT_S_M <= x"0000";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_L_M, COUNT_S_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
COUNT_L <= x"00000";
COUNT_S <= x"0000";
else
if falling_edge(CLK)
then SV <= SV_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (InAB_S = '1')
then
if (COUNT_L = CNTS30) --156250 -- if (COUNT >=3)
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --not COUNT_L = CNTS30
--VAS01
PAUSE_END <= '0';
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
else --InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Zustandsuebgergang
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '1';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; --warte ab bis InAB wieder NUll wird
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end if;
else
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when ST_CTRL_04 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; --Zaehlschleife
end if;
when ST_CTRL_05 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; --Zaehlschleife
end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT11) --54687
then
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Error: Kein Stoppbit, vormals ST_CTRL_05
else --InAB_S = '1'
-- VAS13
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '1';
n_SV <= ST_CTRL_0E; --Stoppbit erkannt
end if; --InAB_S = '0'
else --not COUNT_S = CNTT11
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if; --COUNT_S = CNTT11
when ST_CTRL_0E =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (InAB_S = '1') --Startbot bisher ncoh nicht gefunden
then
if (COUNT_S = CNTT13) --64062
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else --not COUNT_S = CNTT13
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if; --COUNT_S = CNTT13
else --InAB_S = '0'
-- Startbit gefunden
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when others =>
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
--BYTE_IN_PROC: process (EN_BIT_0, EN_BIT_1, EN_BIT_2, EN_BIT_3, EN_BIT_4, EN_BIT_5, EN_BIT_6, EN_BIT_7, EN_BIT_8) --Umwandlung einzelnes Bit EIN_BIT_0_S bis 8_S in Vector EN_BIT_i
-- begin
EN_BIT_i(0) <= EN_BIT_0;
EN_BIT_i(1) <= EN_BIT_1;
EN_BIT_i(2) <= EN_BIT_2;
EN_BIT_i(3) <= EN_BIT_3;
EN_BIT_i(4) <= EN_BIT_4;
EN_BIT_i(5) <= EN_BIT_5;
EN_BIT_i(6) <= EN_BIT_6;
EN_BIT_i(7) <= EN_BIT_7;
EN_BIT_i(8) <= EN_BIT_8;
--end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/Rueckfallposition_14_12_2012/SRAM_25MHZ_255_BYTE/SRAM_25MHZ_255_BYTE.vhd | 4 | 10382 | -- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 07.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_OUT : out std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; --Chip Enable
UB1 : out std_logic; --Upper Byte Enable
LB1 : out std_logic; --Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT)
begin
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
ADR_DAT_OUT_PROC: process (n_COUNT_ADR, n_COUNT_DAT) --Ausgabe Adresse und Daten
begin
--Adressen
COUNT_ADR_OUT(0) <= n_COUNT_ADR(0);
COUNT_ADR_OUT(1) <= n_COUNT_ADR(1);
COUNT_ADR_OUT(2) <= n_COUNT_ADR(2);
COUNT_ADR_OUT(3) <= n_COUNT_ADR(3);
COUNT_ADR_OUT(4) <= n_COUNT_ADR(4);
COUNT_ADR_OUT(5) <= n_COUNT_ADR(5);
COUNT_ADR_OUT(6) <= n_COUNT_ADR(6);
COUNT_ADR_OUT(7) <= n_COUNT_ADR(7);
COUNT_ADR_OUT(8) <= n_COUNT_ADR(8);
COUNT_ADR_OUT(9) <= n_COUNT_ADR(9);
COUNT_ADR_OUT(10) <= n_COUNT_ADR(10);
COUNT_ADR_OUT(11) <= n_COUNT_ADR(11);
COUNT_ADR_OUT(12) <= n_COUNT_ADR(12);
COUNT_ADR_OUT(13) <= n_COUNT_ADR(13);
COUNT_ADR_OUT(14) <= n_COUNT_ADR(14);
COUNT_ADR_OUT(15) <= n_COUNT_ADR(15);
COUNT_ADR_OUT(16) <= n_COUNT_ADR(16);
COUNT_ADR_OUT(17) <= n_COUNT_ADR(17);
COUNT_ADR_OUT(18) <= n_COUNT_ADR(18);
--Daten
COUNT_DAT_OUT(0) <= n_COUNT_DAT(0);
COUNT_DAT_OUT(1) <= n_COUNT_DAT(1);
COUNT_DAT_OUT(2) <= n_COUNT_DAT(2);
COUNT_DAT_OUT(3) <= n_COUNT_DAT(3);
COUNT_DAT_OUT(4) <= n_COUNT_DAT(4);
COUNT_DAT_OUT(5) <= n_COUNT_DAT(5);
COUNT_DAT_OUT(6) <= n_COUNT_DAT(6);
COUNT_DAT_OUT(7) <= n_COUNT_DAT(7);
COUNT_DAT_OUT(8) <= n_COUNT_DAT(8);
COUNT_DAT_OUT(9) <= n_COUNT_DAT(9);
COUNT_DAT_OUT(10) <= n_COUNT_DAT(10);
COUNT_DAT_OUT(11) <= n_COUNT_DAT(11);
COUNT_DAT_OUT(12) <= n_COUNT_DAT(12);
COUNT_DAT_OUT(13) <= n_COUNT_DAT(13);
COUNT_DAT_OUT(14) <= n_COUNT_DAT(14);
COUNT_DAT_OUT(15) <= n_COUNT_DAT(15);
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/PROFIBUS_MONITOR/F_DIV50000_SRC.vhd | 38 | 917 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity F_DIV50000 is
Port ( F_IN : in std_logic; -- Eingangsfrequenz
F_OUT : out std_logic); -- Ausgangsfrequen
-- FOUT ändert sich mit der
-- 0/1-Flanke von F_IN
end F_DIV50000;
architecture Behavioral of F_DIV50000 is
signal COUNTER : integer;
-- Maximalwert: Teilungsfaktor - 1
begin
process (F_IN,COUNTER )
begin
if (F_IN'event and F_IN = '1')
then -- am Eingang des Frequenzteilers ist eine 0/1-Flanke aufgetreten
if COUNTER = 0
then COUNTER <= 49999; -- Teilungsfaktor -1
else COUNTER <= COUNTER -1;
end if;
end if;
if COUNTER < 25000 -- Teilungsfaktor / 2 (abgerundet)
then F_OUT <= '0';
else F_OUT <= '1';
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_CRLF/F_DIV50000_SRC.vhd | 38 | 917 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity F_DIV50000 is
Port ( F_IN : in std_logic; -- Eingangsfrequenz
F_OUT : out std_logic); -- Ausgangsfrequen
-- FOUT ändert sich mit der
-- 0/1-Flanke von F_IN
end F_DIV50000;
architecture Behavioral of F_DIV50000 is
signal COUNTER : integer;
-- Maximalwert: Teilungsfaktor - 1
begin
process (F_IN,COUNTER )
begin
if (F_IN'event and F_IN = '1')
then -- am Eingang des Frequenzteilers ist eine 0/1-Flanke aufgetreten
if COUNTER = 0
then COUNTER <= 49999; -- Teilungsfaktor -1
else COUNTER <= COUNTER -1;
end if;
end if;
if COUNTER < 25000 -- Teilungsfaktor / 2 (abgerundet)
then F_OUT <= '0';
else F_OUT <= '1';
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/Rueckfallposition_14_12_2012/TEST_CTRL_9P6_50MHZ_SCH/F_DIV50000_SRC.vhd | 38 | 917 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity F_DIV50000 is
Port ( F_IN : in std_logic; -- Eingangsfrequenz
F_OUT : out std_logic); -- Ausgangsfrequen
-- FOUT ändert sich mit der
-- 0/1-Flanke von F_IN
end F_DIV50000;
architecture Behavioral of F_DIV50000 is
signal COUNTER : integer;
-- Maximalwert: Teilungsfaktor - 1
begin
process (F_IN,COUNTER )
begin
if (F_IN'event and F_IN = '1')
then -- am Eingang des Frequenzteilers ist eine 0/1-Flanke aufgetreten
if COUNTER = 0
then COUNTER <= 49999; -- Teilungsfaktor -1
else COUNTER <= COUNTER -1;
end if;
end if;
if COUNTER < 25000 -- Teilungsfaktor / 2 (abgerundet)
then F_OUT <= '0';
else F_OUT <= '1';
end if;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine/PROFIBUS_MONITOR/DEB_50MZ_100MS_SRC.vhd | 38 | 2643 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50MZ_100MS_SRC;
architecture Behavioral of DEB_50MZ_100MS_SRC is
type SV_TYPE is (DEB0, DEB1);
signal SV, n_SV, SV_M : SV_TYPE;
signal COUNT_DEB, n_COUNT_DEB, COUNT_DEB_M: std_logic_vector (23 downto 0);
signal NOT_F_50MHZ : std_logic;
signal IN_DEB_S : std_logic;
constant CONST_DEB_max: std_logic_vector := x"4C4B40";
begin
IREG_PROC: process (IN_DEB, NOT_F_50MHZ)
begin
if (NOT_F_50MHZ'event and NOT_F_50MHZ = '1')
then IN_DEB_S <= IN_DEB;
end if;
end process;
SREG_M_PROC: process (F_50MHZ, n_SV, n_COUNT_DEB, SV_M)
begin
if (F_50MHZ'event and F_50MHZ = '1')
then
SV_M <= n_SV;
COUNT_DEB_M <= n_COUNT_DEB;
else
COUNT_DEB_M <= COUNT_DEB_M;
end if;
end process;
NOT_F_50MHZ_PROC: process (F_50MHZ)
begin
NOT_F_50MHZ <= not F_50MHZ;
end process;
SREG_S_PROC: process (NOT_F_50MHZ, SV_M, COUNT_DEB_M)
begin
if (NOT_F_50MHZ'event and NOT_F_50MHZ = '1')
then
SV <= SV_M;
COUNT_DEB <= COUNT_DEB_M;
end if;
end process;
IL_OL_PROC: process (IN_DEB_S, SV, COUNT_DEB)
begin
case SV is
when DEB0 =>
if (IN_DEB_S = '1')
then
if COUNT_DEB >= CONST_DEB_max
then
OUT_DEB <= '0';
n_COUNT_DEB <= x"000000";
n_SV <= DEB1;
else
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB+1;
n_SV <= DEB0;
end if;
else
if COUNT_DEB = x"000000"
then
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB0;
else
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB-1;
n_SV <= DEB0;
end if;
end if;
when DEB1 =>
if (IN_DEB_S = '1')
then
if COUNT_DEB >= CONST_DEB_max
then
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB1;
else
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB+1;
n_SV <= DEB1;
end if;
else
if COUNT_DEB = x"000000"
then
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB0;
else
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB-1;
n_SV <= DEB1;
end if;
end if;
when Others =>
OUT_DEB <= '0';
n_COUNT_DEB <= x"000000";
n_SV <= DEB0;
end case;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_TELEGRAM_FILTER/DEB_50MZ_100MS_SRC.vhd | 38 | 2643 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50MZ_100MS_SRC;
architecture Behavioral of DEB_50MZ_100MS_SRC is
type SV_TYPE is (DEB0, DEB1);
signal SV, n_SV, SV_M : SV_TYPE;
signal COUNT_DEB, n_COUNT_DEB, COUNT_DEB_M: std_logic_vector (23 downto 0);
signal NOT_F_50MHZ : std_logic;
signal IN_DEB_S : std_logic;
constant CONST_DEB_max: std_logic_vector := x"4C4B40";
begin
IREG_PROC: process (IN_DEB, NOT_F_50MHZ)
begin
if (NOT_F_50MHZ'event and NOT_F_50MHZ = '1')
then IN_DEB_S <= IN_DEB;
end if;
end process;
SREG_M_PROC: process (F_50MHZ, n_SV, n_COUNT_DEB, SV_M)
begin
if (F_50MHZ'event and F_50MHZ = '1')
then
SV_M <= n_SV;
COUNT_DEB_M <= n_COUNT_DEB;
else
COUNT_DEB_M <= COUNT_DEB_M;
end if;
end process;
NOT_F_50MHZ_PROC: process (F_50MHZ)
begin
NOT_F_50MHZ <= not F_50MHZ;
end process;
SREG_S_PROC: process (NOT_F_50MHZ, SV_M, COUNT_DEB_M)
begin
if (NOT_F_50MHZ'event and NOT_F_50MHZ = '1')
then
SV <= SV_M;
COUNT_DEB <= COUNT_DEB_M;
end if;
end process;
IL_OL_PROC: process (IN_DEB_S, SV, COUNT_DEB)
begin
case SV is
when DEB0 =>
if (IN_DEB_S = '1')
then
if COUNT_DEB >= CONST_DEB_max
then
OUT_DEB <= '0';
n_COUNT_DEB <= x"000000";
n_SV <= DEB1;
else
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB+1;
n_SV <= DEB0;
end if;
else
if COUNT_DEB = x"000000"
then
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB0;
else
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB-1;
n_SV <= DEB0;
end if;
end if;
when DEB1 =>
if (IN_DEB_S = '1')
then
if COUNT_DEB >= CONST_DEB_max
then
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB1;
else
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB+1;
n_SV <= DEB1;
end if;
else
if COUNT_DEB = x"000000"
then
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB0;
else
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB-1;
n_SV <= DEB1;
end if;
end if;
when Others =>
OUT_DEB <= '0';
n_COUNT_DEB <= x"000000";
n_SV <= DEB0;
end case;
end process;
end Behavioral;
| gpl-2.0 |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/Rueckfallposition_19_12_2012/PROFI_MON_25MHZ_CTRL_SRAM/DEB_50MZ_100MS_SRC.vhd | 38 | 2643 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50MZ_100MS_SRC;
architecture Behavioral of DEB_50MZ_100MS_SRC is
type SV_TYPE is (DEB0, DEB1);
signal SV, n_SV, SV_M : SV_TYPE;
signal COUNT_DEB, n_COUNT_DEB, COUNT_DEB_M: std_logic_vector (23 downto 0);
signal NOT_F_50MHZ : std_logic;
signal IN_DEB_S : std_logic;
constant CONST_DEB_max: std_logic_vector := x"4C4B40";
begin
IREG_PROC: process (IN_DEB, NOT_F_50MHZ)
begin
if (NOT_F_50MHZ'event and NOT_F_50MHZ = '1')
then IN_DEB_S <= IN_DEB;
end if;
end process;
SREG_M_PROC: process (F_50MHZ, n_SV, n_COUNT_DEB, SV_M)
begin
if (F_50MHZ'event and F_50MHZ = '1')
then
SV_M <= n_SV;
COUNT_DEB_M <= n_COUNT_DEB;
else
COUNT_DEB_M <= COUNT_DEB_M;
end if;
end process;
NOT_F_50MHZ_PROC: process (F_50MHZ)
begin
NOT_F_50MHZ <= not F_50MHZ;
end process;
SREG_S_PROC: process (NOT_F_50MHZ, SV_M, COUNT_DEB_M)
begin
if (NOT_F_50MHZ'event and NOT_F_50MHZ = '1')
then
SV <= SV_M;
COUNT_DEB <= COUNT_DEB_M;
end if;
end process;
IL_OL_PROC: process (IN_DEB_S, SV, COUNT_DEB)
begin
case SV is
when DEB0 =>
if (IN_DEB_S = '1')
then
if COUNT_DEB >= CONST_DEB_max
then
OUT_DEB <= '0';
n_COUNT_DEB <= x"000000";
n_SV <= DEB1;
else
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB+1;
n_SV <= DEB0;
end if;
else
if COUNT_DEB = x"000000"
then
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB0;
else
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB-1;
n_SV <= DEB0;
end if;
end if;
when DEB1 =>
if (IN_DEB_S = '1')
then
if COUNT_DEB >= CONST_DEB_max
then
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB1;
else
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB+1;
n_SV <= DEB1;
end if;
else
if COUNT_DEB = x"000000"
then
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB0;
else
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB-1;
n_SV <= DEB1;
end if;
end if;
when Others =>
OUT_DEB <= '0';
n_COUNT_DEB <= x"000000";
n_SV <= DEB0;
end case;
end process;
end Behavioral;
| gpl-2.0 |
bgunebakan/toyrobot | counter.vhd | 1 | 1400 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:30:59 12/18/2014
-- Design Name:
-- Module Name: counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Counter is
generic(n: POSITIVE := 10);
Port ( clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
Counter_output : out STD_LOGIC_VECTOR (n-1 downto 0));
end Counter;
architecture Behavioral of Counter is
signal count: STD_LOGIC_VECTOR(n-1 downto 0);
begin
process(clk,reset)
begin
if(reset='0') then
count <= (others => '0');
elsif(clk'event and clk='1') then
if(enable='1') then
count <= count+1;
end if;
end if;
end process;
Counter_output <= count;
end Behavioral;
| gpl-2.0 |
bgunebakan/toyrobot | TopDesign.vhd | 1 | 3420 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:11:22 12/18/2014
-- Design Name:
-- Module Name: TopDesign - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TopDesign is
Port ( pulse_pin : in STD_LOGIC;
Trigger_pin : out STD_LOGIC;
clk : in STD_LOGIC;
topselDispA : out STD_LOGIC;
topselDispB : out STD_LOGIC;
topselDispC : out STD_LOGIC;
topselDispD : out STD_LOGIC;
topsegA : out STD_LOGIC;
topsegB : out STD_LOGIC;
topsegC : out STD_LOGIC;
topsegD : out STD_LOGIC;
topsegE : out STD_LOGIC;
topsegF : out STD_LOGIC;
topsegG : out STD_LOGIC);
end TopDesign;
architecture Behavioral of TopDesign is
component Range_sensor
port(
fpgaclk : in STD_LOGIC;
triggerOut : out STD_LOGIC;
pulse: in STD_LOGIC;
meters: out STD_LOGIC_VECTOR(3 DOWNTO 0);
decimeters : out STD_LOGIC_VECTOR(3 DOWNTO 0);
centimeters : out STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
component segmentdriver
Port(
display_A: in STD_LOGIC_VECTOR (3 DOWNTO 0);
display_B: in STD_LOGIC_VECTOR (3 DOWNTO 0);
display_C: in STD_LOGIC_VECTOR (3 DOWNTO 0);
display_D: in STD_LOGIC_VECTOR (3 DOWNTO 0);
segA: out STD_LOGIC;
segB: out STD_LOGIC;
segC: out STD_LOGIC;
segD: out STD_LOGIC;
segE: out STD_LOGIC;
segF: out STD_LOGIC;
segG: out STD_LOGIC;
select_Display_A: out STD_LOGIC;
select_Display_B: out STD_LOGIC;
select_Display_C: out STD_LOGIC;
select_Display_D: out STD_LOGIC;
clk: in STD_LOGIC
);
end component;
SIGNAL Ai : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Bi : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Ci : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Di : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL sensor_meters :STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL sensor_decimeters :STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL sensor_centimeters :STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
uut2: segmentDriver PORT MAP(
display_A=>Ai,
display_B=>Bi,
display_C=>Ci,
display_D=>Di,
segA => topsegA,
segB => topsegB,
segC => topsegC,
segD => topsegD,
segE => topsegE,
segF => topsegF,
segG => topsegG,
select_Display_A => topselDispA,
select_Display_B => topselDispB,
select_Display_C => topselDispC,
select_Display_D => topselDispD,
clk => clk
);
uut4: Range_sensor PORT MAP(
fpgaclk => clk,
triggerOut => Trigger_pin,
pulse => pulse_pin,
meters => sensor_meters,
decimeters=> sensor_decimeters,
centimeters=> sensor_centimeters
);
Ai <= sensor_centimeters;
Bi <= sensor_decimeters;
Ci <= sensor_meters;
Di <="0000";
end Behavioral;
| gpl-2.0 |
vzh/geda-gaf | utils/netlist/docs/README.vhdl | 7 | 598 |
The VHDL backend
Written by Magnus Danielson and improved by Thomas Heidel
A few things you have to care about:
1. In order to generate valid component declarations, you
have to add an additional attribute to each pin.
"type=IN" or "type=OUT" or "type=INOUT"
2. The "device" attribute must be unique to a symbol!
The verilog symbols of the same type for example, have all
the same device attribute and will therefore not work.
3. Make sure your component-library picks up the vhdl symbols instead
of the verilog symbols Library paths that show up last are searched
first!
| gpl-2.0 |
vzh/geda-gaf | utils/netlist/examples/vams/vhdl/basic-vhdl/spice_cs_arc.vhdl | 15 | 244 | ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
| gpl-2.0 |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_sram_0_avalon_sram_slave_translator.vhd | 1 | 12680 | -- tracking_camera_system_sram_0_avalon_sram_slave_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_sram_0_avalon_sram_slave_translator is
generic (
AV_ADDRESS_W : integer := 18;
AV_DATA_W : integer := 16;
UAV_DATA_W : integer := 16;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 2;
UAV_BYTEENABLE_W : integer := 2;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 2;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 2;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- .readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(17 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(15 downto 0); -- .writedata
av_byteenable : out std_logic_vector(1 downto 0); -- .byteenable
av_readdatavalid : in std_logic := '0'; -- .readdatavalid
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(1 downto 0);
uav_clken : in std_logic := '0'
);
end entity tracking_camera_system_sram_0_avalon_sram_slave_translator;
architecture rtl of tracking_camera_system_sram_0_avalon_sram_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(17 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
sram_0_avalon_sram_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_readdatavalid => av_readdatavalid, -- .readdatavalid
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of tracking_camera_system_sram_0_avalon_sram_slave_translator
| gpl-2.0 |
pdNor/geany | tests/ctags/test.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/video_system_cpu_jtag_debug_module_translator.vhd | 1 | 12740 | -- video_system_cpu_jtag_debug_module_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.09.14:34:21
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity video_system_cpu_jtag_debug_module_translator is
generic (
AV_ADDRESS_W : integer := 9;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(31 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(8 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_begintransfer : out std_logic; -- .begintransfer
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_chipselect : out std_logic; -- .chipselect
av_debugaccess : out std_logic; -- .debugaccess
av_beginbursttransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(3 downto 0);
uav_clken : in std_logic := '0'
);
end entity video_system_cpu_jtag_debug_module_translator;
architecture rtl of video_system_cpu_jtag_debug_module_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(8 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_debugaccess : out std_logic; -- debugaccess
av_read : out std_logic; -- read
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
cpu_jtag_debug_module_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_begintransfer => av_begintransfer, -- .begintransfer
av_byteenable => av_byteenable, -- .byteenable
av_chipselect => av_chipselect, -- .chipselect
av_debugaccess => av_debugaccess, -- .debugaccess
av_read => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of video_system_cpu_jtag_debug_module_translator
| gpl-2.0 |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/hostinterface/src/hostInterfacePkg.vhd | 3 | 4125 | -------------------------------------------------------------------------------
--! @file hostInterfacePkg.vhd
--
--! @brief Host interface package
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package hostInterfacePkg is
-- constants
--! dword size
constant cDword : natural := 32;
--! word size
constant cWord : natural := 16;
--! byte size
constant cByte : natural := 8;
--! nible size
constant cNibble : natural := 4;
--! size of 32 bit std_logic_vector array
constant cArrayStd32ElementSize : natural := 32;
--! external synchronization config
constant cExtSyncConfigWidth : natural := 3;
constant cExtSyncEdgeConfigWidth : natural := 2;
constant cExtSyncEdgeRis : std_logic_vector
(cExtSyncEdgeConfigWidth-1 downto 0) := "01";
constant cExtSyncEdgeFal : std_logic_vector
(cExtSyncEdgeConfigWidth-1 downto 0) := "10";
constant cExtSyncEdgeAny : std_logic_vector
(cExtSyncEdgeConfigWidth-1 downto 0) := "11";
-- type
--! 32 bit std_logic_vector array type
type tArrayStd32 is
array (natural range <>) of std_logic_vector
(cArrayStd32ElementSize-1 downto 0);
-- function
--! convert arrayIn into std_logic_vector stream
function CONV_STDLOGICVECTOR (arrayIn : tArrayStd32; arrayLength : natural)
return std_logic_vector;
end hostInterfacePkg;
package body hostInterfacePkg is
-- function
function CONV_STDLOGICVECTOR (arrayIn : tArrayStd32; arrayLength : natural)
return std_logic_vector is
variable vTmpStream : std_logic_vector
(arrayLength*cArrayStd32ElementSize-1 downto 0);
variable vTmpElement : std_logic_vector
(cArrayStd32ElementSize-1 downto 0);
begin
for i in arrayLength downto 1 loop
--get current element
vTmpElement := arrayIn(arrayLength-i);
--write element into stream
vTmpStream
(i*cArrayStd32ElementSize-1 downto (i-1)*cArrayStd32ElementSize) :=
vTmpElement;
end loop;
return vTmpStream;
end function;
end package body;
| gpl-2.0 |
mauricioms/web-context | libs/ace-builds/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| gpl-2.0 |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/openmac/src/convRmiiToMii-rtl-ea.vhd | 3 | 11024 | -------------------------------------------------------------------------------
--! @file convRmiiToMii-rtl-ea.vhd
--
--! @brief RMII-to-MII converter
--
--! @details This is an RMII-to-MII converter to convert MII phy traces to RMII.
--! Example: MII PHY <--> RMII-to-MII converter <--> RMII MAC
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
entity convRmiiToMii is
port (
--! Reset
iRst : in std_logic;
--! RMII Clock
iClk : in std_logic;
--! RMII transmit path
iRmiiTx : in tRmiiPath;
--! RMII receive path
oRmiiRx : out tRmiiPath;
--! MII receive clock
iMiiRxClk : in std_logic;
--! MII receive path
iMiiRx : in tMiiPath;
--! MII receive error
iMiiRxError : in std_logic;
--! MII transmit clock
iMiiTxClk : in std_logic;
--! MII transmit path
oMiiTx : out tMiiPath
);
end convRmiiToMii;
architecture rtl of convRmiiToMii is
constant DIBIT_SIZE : integer := 2;
constant NIBBLE_SIZE : integer := 4;
begin
TX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid, txEnable_reg : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout, txData_reg : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
--necessary for clr fifo
signal aclr, rTxEn_l : std_logic;
--convert dibits to nibble
signal sel_dibit : std_logic;
signal fifo_din_reg : std_logic_vector(iRmiiTx.data'range);
begin
fifo_din <= iRmiiTx.data & fifo_din_reg;
fifo_wr <= sel_dibit;
--convert dibits to nibble (to fit to fifo)
process(iClk, iRst)
begin
if iRst = cActivated then
sel_dibit <= cInactivated;
fifo_din_reg <= (others => cInactivated);
elsif iClk = cActivated and iClk'event then
if iRmiiTx.enable = cActivated then
sel_dibit <= not sel_dibit;
if sel_dibit = cInactivated then
fifo_din_reg <= iRmiiTx.data;
end if;
else
sel_dibit <= cInactivated;
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
oMiiTx.data <= txData_reg;
oMiiTx.enable <= txEnable_reg;
process(iMiiTxClk, iRst)
begin
if iRst = cActivated then
fifo_rd <= cInactivated;
fifo_valid <= cInactivated;
txData_reg <= (others => cInactivated);
txEnable_reg <= cInactivated;
elsif iMiiTxClk = cActivated and iMiiTxClk'event then
txData_reg <= fifo_dout;
txEnable_reg <= fifo_valid;
if fifo_rd = cInactivated and fifo_half = cActivated then
fifo_rd <= cActivated;
elsif fifo_rd = cActivated and fifo_empty = cActivated then
fifo_rd <= cInactivated;
end if;
if fifo_rd = cActivated and fifo_rdUsedWord > std_logic_vector(to_unsigned(1, fifo_rdUsedWord'length)) then
fifo_valid <= cActivated;
else
fifo_valid <= cInactivated;
end if;
end if;
end process;
--! This is the asynchronous FIFO used to decouple RMII from MII.
TXFIFO : entity work.asyncFifo
generic map (
gDataWidth => NIBBLE_SIZE,
gWordSize => 2**FIFO_NIBBLES_LOG2,
gSyncStages => 2,
gMemRes => "ON"
)
port map (
iAclr => aclr,
iWrClk => iClk,
iWrReq => fifo_wr,
iWrData => fifo_din,
oWrEmpty => open,
oWrFull => fifo_full,
oWrUsedw => open,
iRdClk => iMiiTxClk,
iRdReq => fifo_rd,
oRdData => fifo_dout,
oRdEmpty => fifo_empty,
oRdFull => open,
oRdUsedw => fifo_rdUsedWord
);
--sync Mii Tx En (=fifo_valid) to wr clk
process(iClk, iRst)
begin
if iRst = cActivated then
aclr <= cActivated; --reset fifo
rTxEn_l <= cInactivated;
elsif iClk = cActivated and iClk'event then
rTxEn_l <= iRmiiTx.enable;
aclr <= cInactivated; --default
--clear the full fifo after TX on RMII side is done
if fifo_full = cActivated and rTxEn_l = cActivated and iRmiiTx.enable = cInactivated then
aclr <= cActivated;
end if;
end if;
end process;
end block;
RX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_empty, fifo_valid : std_logic;
signal rxDataValid_reg, fifo_rd : std_logic;
signal rxError_reg : std_logic;
signal fifo_wr : std_logic;
signal rxData_reg : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
--convert nibble to dibits
signal sel_dibit : std_logic;
signal fifo_rd_s : std_logic;
begin
process(iMiiRxClk, iRst)
begin
if iRst = cActivated then
rxData_reg <= (others => cInactivated);
rxDataValid_reg <= cInactivated;
rxError_reg <= cInactivated;
elsif iMiiRxClk = cActivated and iMiiRxClk'event then
rxData_reg <= iMiiRx.data;
rxDataValid_reg <= iMiiRx.enable;
rxError_reg <= iMiiRxError;
end if;
end process;
fifo_wr <= rxDataValid_reg and not rxError_reg;
oRmiiRx.data <= fifo_dout(fifo_dout'right+1 downto 0) when sel_dibit = cActivated else
fifo_dout(fifo_dout'left downto fifo_dout'left-1);
oRmiiRx.enable <= fifo_valid;
fifo_rd <= fifo_rd_s and not sel_dibit;
process(iClk, iRst)
begin
if iRst = cActivated then
sel_dibit <= cInactivated;
elsif iClk = cActivated and iClk'event then
if fifo_rd_s = cActivated or fifo_valid = cActivated then
sel_dibit <= not sel_dibit;
else
sel_dibit <= cInactivated;
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
process(iClk, iRst)
begin
if iRst = cActivated then
fifo_rd_s <= cInactivated;
fifo_valid <= cInactivated;
elsif iClk = cActivated and iClk'event then
if fifo_rd_s = cInactivated and fifo_half = cActivated then
fifo_rd_s <= cActivated;
elsif fifo_rd_s = cActivated and fifo_empty = cActivated then
fifo_rd_s <= cInactivated;
end if;
if fifo_rd_s = cActivated then
fifo_valid <= cActivated;
else
fifo_valid <= cInactivated;
end if;
end if;
end process;
--! This is the asynchronous FIFO used to decouple RMII from MII.
RXFIFO : entity work.asyncFifo
generic map (
gDataWidth => NIBBLE_SIZE,
gWordSize => 2**FIFO_NIBBLES_LOG2,
gSyncStages => 2,
gMemRes => "ON"
)
port map (
iAclr => iRst,
iWrClk => iMiiRxClk,
iWrReq => fifo_wr,
iWrData => rxData_reg,
oWrEmpty => open,
oWrFull => open,
oWrUsedw => open,
iRdClk => iClk,
iRdReq => fifo_rd,
oRdData => fifo_dout,
oRdEmpty => fifo_empty,
oRdFull => open,
oRdUsedw => fifo_rdUsedWord
);
end block;
end rtl;
| gpl-2.0 |
SonicFrog/ArchOrd | transmitter.vhdl | 1 | 1694 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity transmitter is
port (
start : in std_logic;
memdata : in std_logic_vector(7 downto 0);
memaddr : in std_logic_vector(7 downto 0);
acknum : in std_logic_vector(7 downto 0);
clk : in std_logic;
reset : in std_logic;
num : out std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0);
valid : out std_logic
);
end transmitter;
architecture synth of transmitter is
signal countNotZero : std_logic;
signal wordcount : std_logic_vector(7 downto 0);
signal next_wordcount : std_logic_vector(7 downto 0);
signal enable : std_logic;
signal lastack : std_logic_vector(7 downto 0);
begin
enable <= start or countNotZero;
countNotZero <= '0' when wordcount = 0 else '1';
num <= wordcount;
memaddr <= wordcount;
-- This processh handles changing the state synchronously
switch : process(clk, next_wordcount)
begin
if reset = '1' then
wordcount <= (others => '0');
elsif rising_edge(clk) then
wordcount <= next_wordcount;
end if;
end process;
-- This process handles the changing of the address of the word
count : process(clk, lastack, enable)
begin
next_wordcount <= wordcount;
if lastack + 4 = wordcount then
wordcount <= lastack + 1;
elsif enable = '1' then
next_wordcount <= wordcount + 1;
end if;
end process;
-- This process does stuff related to the ACK
ack : process(clk, acknum, ack)
begin
if reset = '1' then
lastack <= (others => '0');
elsif rising_edge(clk) then
if ack = '1' then
lastack <= acknum;
end if;
end if;
end process;
end architecture ; -- synth | gpl-2.0 |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/fifo/src/asyncFifo-rtl-a.vhd | 3 | 9787 | -------------------------------------------------------------------------------
--! @file asyncFifo-rtl-a.vhd
--
--! @brief The asynchronous Fifo architecture.
--
--! @details This is a generic dual clocked FIFO using the dpRam component as
--! memory.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
architecture rtl of asyncFifo is
--! Address width
constant cAddrWidth : natural := logDualis(gWordSize);
--! Type for DPRAM port commons
type tDpramPortCommon is record
clk : std_logic;
enable : std_logic;
address : std_logic_vector(cAddrWidth-1 downto 0);
end record;
--! Type for DPRAM port assignment
type tDpramPort is record
wrPort : tDpramPortCommon;
rdPort : tDpramPortCommon;
write : std_logic;
writedata : std_logic_vector(gDataWidth-1 downto 0);
readdata : std_logic_vector(gDataWidth-1 downto 0);
end record;
--! Type for control port
type tControlPort is record
clk : std_logic;
rst : std_logic;
request : std_logic;
otherPointer : std_logic_vector(cAddrWidth downto 0);
empty : std_logic;
full : std_logic;
pointer : std_logic_vector(cAddrWidth downto 0);
address : std_logic_vector(cAddrWidth-1 downto 0);
usedWord : std_logic_vector(cAddrWidth-1 downto 0);
end record;
--! Type for pointer synchronizers
type tPointerSyncPort is record
clk : std_logic;
rst : std_logic;
din : std_logic_vector(cAddrWidth downto 0);
dout : std_logic_vector(cAddrWidth downto 0);
end record;
--! DPRAM instance
signal inst_dpram : tDpramPort;
--! Write controller instance
signal inst_writeCtrl : tControlPort;
--! Read controller instance
signal inst_readCtrl : tControlPort;
--! Write pointer synchronizer instance
signal inst_writeSync : tPointerSyncPort;
--! Read pointer synchronizer instance
signal inst_readSync : tPointerSyncPort;
begin
assert (gMemRes = "ON")
report "This FIFO implementation only supports memory resources!"
severity warning;
---------------------------------------------------------------------------
-- Assign Outputs
---------------------------------------------------------------------------
-- Write port
oWrEmpty <= inst_writeCtrl.empty;
oWrFull <= inst_writeCtrl.full;
oWrUsedw <= inst_writeCtrl.usedWord;
-- Read port
oRdEmpty <= inst_readCtrl.empty;
oRdFull <= inst_readCtrl.full;
oRdUsedw <= inst_readCtrl.usedWord;
oRdData <= inst_dpram.readdata;
---------------------------------------------------------------------------
-- Map DPRAM instance
---------------------------------------------------------------------------
-- Write port
inst_dpram.wrPort.clk <= iWrClk;
inst_dpram.wrPort.enable <= inst_writeCtrl.request;
inst_dpram.write <= inst_writeCtrl.request;
inst_dpram.wrPort.address <= inst_writeCtrl.address;
inst_dpram.writedata <= iWrData;
-- Read port
inst_dpram.rdPort.clk <= iRdClk;
inst_dpram.rdPort.enable <= iRdReq;
inst_dpram.rdPort.address <= inst_readCtrl.address;
---------------------------------------------------------------------------
-- Map Write and Read controller instance
---------------------------------------------------------------------------
inst_readCtrl.clk <= iRdClk;
inst_readCtrl.rst <= iAclr;
inst_readCtrl.request <= iRdReq;
inst_readCtrl.otherPointer <= inst_writeSync.dout;
inst_writeCtrl.clk <= iWrClk;
inst_writeCtrl.rst <= iAclr;
inst_writeCtrl.request <= iWrReq and not inst_writeCtrl.full;
inst_writeCtrl.otherPointer <= inst_readSync.dout;
---------------------------------------------------------------------------
-- Map pointer synchronizers
---------------------------------------------------------------------------
inst_readSync.rst <= iAclr;
inst_readSync.clk <= iWrClk; -- synchronize read pointer to write clock
inst_readSync.din <= inst_readCtrl.pointer;
inst_writeSync.rst <= iAclr;
inst_writeSync.clk <= iRdClk; -- synchronize write pointer to read clock
inst_writeSync.din <= inst_writeCtrl.pointer;
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! This is the FIFO read controller.
FIFO_READ_CONTROL : entity work.fifoRead
generic map (
gAddrWidth => cAddrWidth
)
port map (
iClk => inst_readCtrl.clk,
iRst => inst_readCtrl.rst,
iRead => inst_readCtrl.request,
iWrPointer => inst_readCtrl.otherPointer,
oEmpty => inst_readCtrl.empty,
oFull => inst_readCtrl.full,
oPointer => inst_readCtrl.pointer,
oAddress => inst_readCtrl.address,
oUsedWord => inst_readCtrl.usedWord
);
--! This is the FIFO write controller.
FIFO_WRITE_CONTROL : entity work.fifoWrite
generic map (
gAddrWidth => cAddrWidth
)
port map (
iClk => inst_writeCtrl.clk,
iRst => inst_writeCtrl.rst,
iWrite => inst_writeCtrl.request,
iRdPointer => inst_writeCtrl.otherPointer,
oEmpty => inst_writeCtrl.empty,
oFull => inst_writeCtrl.full,
oPointer => inst_writeCtrl.pointer,
oAddress => inst_writeCtrl.address,
oUsedWord => inst_writeCtrl.usedWord
);
--! This is the FIFO buffer.
FIFO_BUFFER : entity work.dpRamSplxNbe
generic map (
gWordWidth => gDataWidth,
gNumberOfWords => gWordSize,
gInitFile => "UNUSED"
)
port map (
iClk_A => inst_dpram.wrPort.clk,
iEnable_A => inst_dpram.wrPort.enable,
iWriteEnable_A => inst_dpram.write,
iAddress_A => inst_dpram.wrPort.address,
iWritedata_A => inst_dpram.writedata,
iClk_B => inst_dpram.rdPort.clk,
iEnable_B => inst_dpram.rdPort.enable,
iAddress_B => inst_dpram.rdPort.address,
oReaddata_B => inst_dpram.readdata
);
--! This generate block instantiates multiple synchrinizers to transfer
--! the write and read pointers to the opposite clock domains.
GEN_POINTERSYNC : for i in cAddrWidth downto 0 generate
WRITESYNC : entity libcommon.synchronizer
generic map (
gStages => gSyncStages,
gInit => cInactivated
)
port map (
iArst => inst_writeSync.rst,
iClk => inst_writeSync.clk,
iAsync => inst_writeSync.din(i),
oSync => inst_writeSync.dout(i)
);
READSYNC : entity libcommon.synchronizer
generic map (
gStages => gSyncStages,
gInit => cInactivated
)
port map (
iArst => inst_readSync.rst,
iClk => inst_readSync.clk,
iAsync => inst_readSync.din(i),
oSync => inst_readSync.dout(i)
);
end generate GEN_POINTERSYNC;
end rtl;
| gpl-2.0 |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/xilinx/memory/src/dpRamSplx-rtl-a.vhd | 3 | 6977 | --! @file dpRamSplx-rtl-a.vhd
--
--! @brief Simplex Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the Simplex DPRAM intended for synthesis on Xilinx
--! platforms only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
architecture rtl of dpRamSplx is
--! Width configuration type
type tWidthConfig is (
sUnsupported,
sAsym_16_32,
sAsym_32_16,
sSym
);
--! Function to return width configuration.
function getWidthConfig (
wordWidthA : natural;
byteEnableWidthA : natural;
wordWidthB : natural
) return tWidthConfig is
begin
if wordWidthA = 16 and wordWidthB = 32 and byteEnableWidthA = 2 then
return sAsym_16_32;
elsif wordWidthA = 32 and wordWidthB = 16 and byteEnableWidthA = 4 then
return sAsym_32_16;
elsif wordWidthA = wordWidthB and byteEnableWidthA = wordWidthA/cByteLength then
return sSym;
else
return sUnsupported;
end if;
end function;
--! Width configuration
constant cWidthConfig : tWidthConfig := getWidthConfig(gWordWidthA, gByteenableWidthA, gWordWidthB);
--! Words of dpram
constant cDprWords : natural := minimum(gNumberOfWordsA, gNumberOfWordsB);
--! Word width of dpram
constant cDprWordWidth : natural := maximum(gWordWidthA, gWordWidthB);
--! Dpr write port address
signal writeAddress : std_logic_vector(logDualis(cDprWords)-1 downto 0);
--! Dpr write port enables
signal writeByteenable : std_logic_vector(cDprWordWidth/cByteLength-1 downto 0);
--! Dpr write port
signal writedata : std_logic_vector(cDprWordWidth-1 downto 0);
--! Dpr read port address
signal readAddress : std_logic_vector(logDualis(cDprWords)-1 downto 0);
--! Dpr read port
signal readdata : std_logic_vector(cDprWordWidth-1 downto 0);
begin
assert (cWidthConfig /= sUnsupported)
report "The width configuration is not supported!"
severity failure;
assert (gInitFile = "UNUSED")
report "Memory initialization is not supported in this architecture!"
severity warning;
assert (gWordWidthA*gNumberOfWordsA = gWordWidthB*gNumberOfWordsB)
report "Memory size of port A and B are different!"
severity failure;
--! Instantiate true dual ported ram entity
TRUEDPRAM : entity work.dpRam
generic map (
gWordWidth => cDprWordWidth,
gNumberOfWords => cDprWords,
gInitFile => "UNUSED"
)
port map (
iClk_A => iClk_A,
iEnable_A => iEnable_A,
iWriteEnable_A => iWriteEnable_A,
iAddress_A => writeAddress,
iByteenable_A => writeByteenable,
iWritedata_A => writedata,
oReaddata_A => open,
iClk_B => iClk_B,
iEnable_B => iEnable_B,
iWriteEnable_B => cInactivated,
iByteenable_B => (others => cInactivated),
iAddress_B => readAddress,
iWritedata_B => (others => cInactivated),
oReaddata_B => readdata
);
--! This generate block assigns the 16 bit write port and
--! the 32 bit read port.
WIDTHCFG_16_32 : if cWidthConfig = sAsym_16_32 generate
writeAddress <= iAddress_A(iAddress_A'left downto 1);
writeByteenable(3) <= iByteenable_A(1) and iAddress_A(0);
writeByteenable(2) <= iByteenable_A(0) and iAddress_A(0);
writeByteenable(1) <= iByteenable_A(1) and not iAddress_A(0);
writeByteenable(0) <= iByteenable_A(0) and not iAddress_A(0);
writedata <= iWritedata_A & iWritedata_A;
readAddress <= iAddress_B;
oReaddata_B <= readdata;
end generate WIDTHCFG_16_32;
--! This generate block assigns the 32 bit write port and
--! the 16 bit read port.
WIDTHCFG_32_16 : if cWidthConfig = sAsym_32_16 generate
writeAddress <= iAddress_A;
writeByteenable <= iByteenable_A;
writedata <= iWritedata_A;
readAddress <= iAddress_B(iAddress_B'left downto 1);
oReaddata_B <= readdata(31 downto 16) when iAddress_B(0) = cActivated else
readdata(15 downto 0);
end generate WIDTHCFG_32_16;
--! This generate block assigns the symmetric write and read ports.
WIDTHCFG_SYM : if cWidthConfig = sSym generate
writeAddress <= iAddress_A;
writeByteenable <= iByteenable_A;
writedata <= iWritedata_A;
readAddress <= iAddress_B;
oReaddata_B <= readdata;
end generate WIDTHCFG_SYM;
end architecture rtl;
| gpl-2.0 |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/xilinx/openmac/src/ipifMasterHandler-rtl-ea.vhd | 3 | 12619 | -------------------------------------------------------------------------------
--! @file ipifMasterHandler-rtl-ea.vhd
--
--! @brief IPIF Master handler
--
--! @details This is the IPIF master handler converting generic master interface
--! to IPIF.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity ipifMasterHandler is
generic (
--! Master address width
gMasterAddrWidth : natural := 31;
--! Master burst count width
gMasterBurstCountWidth : natural := 4;
--! IPIF address width
gIpifAddrWidth : natural := 32;
--! IPIF length width
gIpifLength : natural := 12
);
port (
--TODO: Add doxygen comments!
-- Common clock and reset
iRst : in std_logic;
iClk : in std_logic;
-- IPIF Master
iIpif_cmdAck : in std_logic;
iIpif_cmplt : in std_logic;
iIpif_error : in std_logic; --FIXME: Unused input
iIpif_rearbitrate : in std_logic; --FIXME: Unused input
iIpif_cmdTimeout : in std_logic; --FIXME: Unused input
oIpif_type : out std_logic;
oIpif_addr : out std_logic_vector(gIpifAddrWidth-1 downto 0);
oIpif_length : out std_logic_vector(gIpifLength-1 downto 0);
oIpif_be : out std_logic_vector(3 downto 0);
oIpif_lock : out std_logic;
oIpif_reset : out std_logic;
iIpif_rdData : in std_logic_vector(31 downto 0);
iIpif_rdRem : in std_logic_vector(3 downto 0); --FIXME: Unused input
oIpif_rdReq : out std_logic;
inIpif_rdSof : in std_logic;
inIpif_rdEof : in std_logic;
inIpif_rdSrcRdy : in std_logic;
inIpif_rdSrcDsc : in std_logic; --FIXME: Unused input
onIpif_rdDstRdy : out std_logic;
onIpif_rdDstDsc : out std_logic;
oIpif_wrData : out std_logic_vector(31 downto 0);
oIpif_wrRem : out std_logic_vector(3 downto 0);
oIpif_wrReq : out std_logic;
onIpif_wrSof : out std_logic;
onIpif_wrEof : out std_logic;
onIpif_wrSrcRdy : out std_logic;
onIpif_wrSrcDsc : out std_logic;
inIpif_wrDstRdy : in std_logic;
inIpif_wrDstDsc : in std_logic; --FIXME: Unused input
-- Generic master interface
iMasterRead : in std_logic;
iMasterWrite : in std_logic;
iMasterAddress : in std_logic_vector(gMasterAddrWidth-1 downto 0);
iMasterWritedata : in std_logic_vector(31 downto 0);
iMasterBurstcount : in std_logic_vector(gMasterBurstCountWidth-1 downto 0);
iMasterBurstcounter : in std_logic_vector(gMasterBurstCountWidth-1 downto 0);
oMasterReaddata : out std_logic_vector(31 downto 0);
oMasterWaitrequest : out std_logic;
oMasterReaddatavalid : out std_logic
);
end ipifMasterHandler;
architecture rtl of ipifMasterHandler is
--signals for requesting transfers
signal masterWrite : std_logic;
signal masterRead : std_logic;
signal nMasterEnable : std_logic;
signal masterWrite_l : std_logic;
signal masterRead_l : std_logic;
signal masterWrite_rise : std_logic;
signal masterRead_rise : std_logic;
signal masterWrite_fall : std_logic;
signal masterRead_fall : std_logic;
signal ipifWriteReq_reg : std_logic;
signal ipifWriteReq_next : std_logic;
signal ipifReadReq_reg : std_logic;
signal ipifReadReq_next : std_logic;
signal ipif_rdDstRdy : std_logic;
--signals for the transfer
type tTfState is (
sIdle,
sSof, sTf, sEof,
sSEof, --start/end of frame (single beat)
sWaitForCmplt
);
signal writeTf_reg : tTfState;
signal writeTf_next : tTfState;
signal readTf : tTfState;
begin
masterWrite <= iMasterWrite and not nMasterEnable;
masterRead <= iMasterRead and not nMasterEnable;
--reserved
oIpif_lock <= cInactivated;
oIpif_reset <= cInactivated;
--delay some signals..
del_proc : process(iClk, iRst)
begin
if iRst = cActivated then
masterWrite_l <= cInactivated;
masterRead_l <= cInactivated;
nMasterEnable <= cnActivated;
elsif rising_edge(iClk) then
masterWrite_l <= masterWrite;
masterRead_l <= masterRead;
if iIpif_cmplt = cActivated then
nMasterEnable <= cnActivated;
elsif masterWrite_fall = cActivated or masterRead_fall = cActivated then
nMasterEnable <= cnInactivated; --write/read done, wait for Mst_Cmplt
end if;
end if;
end process;
--generate pulse if write/read is asserted
masterWrite_rise <= cActivated when masterWrite_l = cInactivated and masterWrite = cActivated else
cInactivated;
masterRead_rise <= cActivated when masterRead_l = cInactivated and masterRead = cActivated else
cInactivated;
masterWrite_fall <= cActivated when masterWrite_l = cActivated and masterWrite = cInactivated else
cInactivated;
masterRead_fall <= cActivated when masterRead_l = cActivated and masterRead = cInactivated else
cInactivated;
--generate req qualifiers
req_proc : process(iClk, iRst)
begin
if iRst = cActivated then
ipifWriteReq_reg <= cInactivated;
ipifReadReq_reg <= cInactivated;
ipif_rdDstRdy <= cInactivated;
elsif rising_edge(iClk) then
ipifWriteReq_reg <= ipifWriteReq_next;
ipifReadReq_reg <= ipifReadReq_next;
if masterRead = cActivated then
ipif_rdDstRdy <= cActivated;
elsif readTf = sEof and inIpif_rdSrcRdy = cnActivated then
ipif_rdDstRdy <= cInactivated;
end if;
end if;
end process;
onIpif_rdDstRdy <= not ipif_rdDstRdy;
oIpif_rdReq <= ipifReadReq_reg;
oIpif_wrReq <= ipifWriteReq_reg;
oIpif_type <= cInactivated when iMasterBurstcount < 2 else --single beat
ipifReadReq_reg or ipifWriteReq_reg; --we are talking about bursts..
ipifWriteReq_next <= cInactivated when ipifWriteReq_reg = cActivated and iIpif_cmdAck = cActivated else
cActivated when ipifWriteReq_reg = cInactivated and masterWrite_rise = cActivated else
ipifWriteReq_reg;
ipifReadReq_next <= cInactivated when ipifReadReq_reg = cActivated and iIpif_cmdAck = cActivated else
cActivated when ipifReadReq_reg = cInactivated and masterRead_rise = cActivated else
ipifReadReq_reg;
--assign address, byteenable and burst size
comb_addrZeroPad : process(iMasterAddress)
begin
for i in oIpif_addr'range loop
if i <= iMasterAddress'high then
oIpif_addr(i) <= iMasterAddress(i);
else
oIpif_addr(i) <= cInactivated; --zero padding
end if;
end loop;
end process;
oIpif_be <= "1111";
oIpif_length <= conv_std_logic_vector(conv_integer(iMasterBurstcount),
oIpif_length'length - 2) & "00"; -- dword x 4 = byte
--write/read link
wrd_proc : process(iClk, iRst)
begin
if iRst = cActivated then
writeTf_reg <= sIdle;
elsif rising_edge(iClk) then
writeTf_reg <= writeTf_next;
end if;
end process;
--generate fsm for write and read transfers
writeTf_next <= sSEof when writeTf_reg = sIdle and ipifWriteReq_next = cActivated and (iMasterBurstcount <= 1 or iMasterBurstcount'length = 1) else
sSof when writeTf_reg = sIdle and ipifWriteReq_next = cActivated and iMasterBurstcount'length > 1 else
sEof when writeTf_reg = sSof and inIpif_wrDstRdy = cnActivated and iMasterBurstcount = 2 and iMasterBurstcount'length > 1 else
sTf when writeTf_reg = sSof and inIpif_wrDstRdy = cnActivated and iMasterBurstcount'length > 1 else
sEof when writeTf_reg = sTf and iMasterBurstcounter <= 2 and inIpif_wrDstRdy = cnActivated and iMasterBurstcount'length > 1 else
sWaitForCmplt when (writeTf_reg = sEof or writeTf_reg = sSEof) and inIpif_wrDstRdy = cnActivated else
sIdle when writeTf_reg = sWaitForCmplt and iIpif_cmplt = cActivated else
writeTf_reg;
readTf <= sSEof when inIpif_rdSof = cnActivated and inIpif_rdEof = cnActivated else
sSof when inIpif_rdSof = cnActivated else
sEof when inIpif_rdEof = cnActivated else
sTf when inIpif_rdSrcRdy = cnActivated else
sIdle;
--set write qualifiers
onIpif_wrSof <= cnActivated when writeTf_reg = sSof or writeTf_reg = sSEof else
cnInactivated;
onIpif_wrEof <= cnActivated when writeTf_reg = sEof or writeTf_reg = sSEof else
cnInactivated;
onIpif_wrSrcRdy <= cnActivated when writeTf_reg /= sIdle and writeTf_reg /= sWaitForCmplt else
cnInactivated;
onIpif_wrSrcDsc <= cnInactivated; --no support
oIpif_wrRem <= (others => cInactivated); --no support
--set read qualifiers
onIpif_rdDstDsc <= cnInactivated; --no support
--connect ipif with generic master
oMasterWaitrequest <= not iMasterWrite when inIpif_wrDstRdy = cnActivated else
not iMasterRead when ipifReadReq_reg = cActivated and iIpif_cmdAck = cActivated else cActivated;
oMasterReaddatavalid <= not inIpif_rdSrcRdy;
oIpif_wrData <= iMasterWritedata;
oMasterReaddata <= iIpif_rdData;
end rtl;
| gpl-2.0 |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_onchip_memory2_0_s1_translator.vhd | 1 | 12673 | -- tracking_camera_system_onchip_memory2_0_s1_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_onchip_memory2_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 12;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 1;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(11 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_chipselect : out std_logic; -- .chipselect
av_clken : out std_logic; -- .clken
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(3 downto 0);
uav_clken : in std_logic := '0'
);
end entity tracking_camera_system_onchip_memory2_0_s1_translator;
architecture rtl of tracking_camera_system_onchip_memory2_0_s1_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(11 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
onchip_memory2_0_s1_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_chipselect => av_chipselect, -- .chipselect
av_clken => av_clken, -- .clken
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of tracking_camera_system_onchip_memory2_0_s1_translator
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue1246/pkg_b.vhdl | 1 | 210 | package pkg_B is
generic (
B: integer := 2
);
procedure showB;
end pkg_B;
package body pkg_B is
procedure showB is
begin
report "B:" & integer'image(B);
end procedure showB;
end package body pkg_B;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1050/top.vhdl | 1 | 533 | library ieee;
use ieee.std_logic_1164.ALL;
entity child is
port (
O1: out std_logic;
O2: out std_logic
);
end entity child;
architecture rtl of child is
begin
O1 <= '0';
O2 <= '1';
end architecture rtl;
library ieee;
use ieee.std_logic_1164.ALL;
entity top is
port (
O: out std_logic
);
end entity top;
architecture rtl of top is
component child is
port (
O1: out std_logic;
O2: out std_logic
);
end component child;
begin
inst : child port map(O1 => O);
end architecture rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_01.vhd | 4 | 1320 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- analyze into resource library utilities
package utility_definitions is
constant word_size : natural := 16;
end package utility_definitions;
library utilities;
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
begin
process is
begin
report
-- code from book:
utilities.utility_definitions.word_size'simple_name
-- end of code from book
;
wait;
end process;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue735/ent.vhdl | 1 | 191 | entity ent is
end entity;
architecture impl of ent is
type bool_vector is array(0 downto 0) of boolean;
signal baz: bool_vector;
begin
assert baz(0)
severity note;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/subprg01/subprg02.vhdl | 1 | 629 | library ieee;
use ieee.std_logic_1164.all;
entity subprg02 is
port (a : std_logic_vector (3 downto 0);
n : natural range 0 to 1;
clk : std_logic;
na : out std_logic_vector (3 downto 0));
end subprg02;
architecture behav of subprg02 is
procedure neg (v : inout std_logic_vector(3 downto 0)) is
begin
v := not v;
end neg;
begin
process(clk)
type t_arr is array (natural range <>) of std_logic_vector(3 downto 0);
variable mem : t_arr (0 to 1);
begin
if rising_edge (clk) then
mem (n) := a;
neg (mem (n));
na <= mem (n);
end if;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1225/tb_top.vhdl | 1 | 861 | entity tb_top is
end tb_top;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_top is
signal clk : std_logic;
signal en : std_logic;
signal a, b : std_logic;
signal p, q : std_logic;
begin
dut: entity work.top
port map (clk, en, a, b, p, q);
process
procedure pulse is
begin
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
end pulse;
begin
clk <= '0';
a <= '1';
b <= '0';
en <= '0';
pulse;
assert p = '0' severity failure;
assert q = '0' severity failure;
a <= '1';
b <= '1';
en <= '0';
pulse;
assert p = '0' severity failure;
assert q = '1' severity failure;
a <= '1';
b <= '1';
en <= '1';
pulse;
assert p = '1' severity failure;
assert q = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/if01/tb_if01.vhdl | 1 | 621 | entity tb_if01 is
end tb_if01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_if01 is
signal c0, c1 : std_logic;
signal r : std_logic;
begin
dut: entity work.if01
port map (c0, c1, r);
process
begin
c0 <= '1';
c1 <= '0';
wait for 1 ns;
assert r = '0' severity failure;
c0 <= '0';
c1 <= '0';
wait for 1 ns;
assert r = '0' severity failure;
c0 <= '1';
c1 <= '1';
wait for 1 ns;
assert r = '1' severity failure;
c0 <= '0';
c1 <= '1';
wait for 1 ns;
assert r = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket69/repro.vhdl | 3 | 325 | library ieee;
use ieee.numeric_std.all;
entity ent is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture a of ent is
begin
main : process
variable a,b : unsigned(0 downto 0) := "1";
begin
assert a = b; -- Works
assert ieee.numeric_std."="(a, b);
wait;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc803.vhd | 4 | 1659 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc803.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b03x00p03n01i00803ent IS
begin
return; -- illegal location for return statement
END c01s01b03x00p03n01i00803ent;
ARCHITECTURE c01s01b03x00p03n01i00803arch OF c01s01b03x00p03n01i00803ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b03x00p03n01i00803 - Return statement can not appear in entity statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b03x00p03n01i00803arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_03.vhd | 4 | 2710 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_fg_09_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package cpu_types is
constant word_size : positive := 16;
constant address_size : positive := 32;
subtype word is bit_vector(word_size - 1 downto 0);
subtype address is bit_vector(address_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
end package cpu_types;
package bit_vector_unsigned_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
end package bit_vector_unsigned_arithmetic;
package body bit_vector_unsigned_arithmetic is
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
alias norm1 : bit_vector(1 to bv1'length) is bv1;
alias norm2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry : bit := '0';
begin
if bv1'length /= bv2'length then
report "arguments of different length" severity failure;
else
for index in norm1'reverse_range loop
result(index) := norm1(index) xor norm2(index) xor carry;
carry := ( norm1(index) and norm2(index) )
or ( carry and ( norm1(index) or norm2(index) ) );
end loop;
end if;
return result;
end function "+";
end package body bit_vector_unsigned_arithmetic;
-- code from book
package DMA_controller_types_and_utilities is
alias word is work.cpu_types.word;
alias address is work.cpu_types.address;
alias status_value is work.cpu_types.status_value;
alias "+" is work.bit_vector_unsigned_arithmetic."+"
[ bit_vector, bit_vector return bit_vector ];
-- . . .
end package DMA_controller_types_and_utilities;
-- end code from book
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2299.vhd | 4 | 2733 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2299.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p35n01i02299ent IS
END c07s02b06x00p35n01i02299ent;
ARCHITECTURE c07s02b06x00p35n01i02299arch OF c07s02b06x00p35n01i02299ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
BEGIN
-- Test simple user-defined physical type * integer expressions.
assert ((1 cm / 10.0) < 1 cm);
assert ((1 mm / 1000.0) < 1 mm);
assert ((1 um / 1000.0) < 1 um);
assert ((1 nm / 10.0) < 1 nm);
wait for 5 ns;
assert NOT( ((1 cm / 10.0) < 1 cm) and
((1 mm / 1000.0) < 1 mm)and
((1 um / 1000.0) < 1 um)and
((1 nm / 10.0) < 1 nm) )
report "***PASSED TEST: c07s02b06x00p35n01i02299"
severity NOTE;
assert ( ((1 cm / 10.0) < 1 cm) and
((1 mm / 1000.0) < 1 mm)and
((1 um / 1000.0) < 1 um)and
((1 nm / 10.0) < 1 nm) )
report "***FAILED TEST: c07s02b06x00p35n01i02299 - Division of an user-defined physical type by a real type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p35n01i02299arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1129.vhd | 4 | 2042 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1129.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p04n01i01129ent IS
END c06s05b00x00p04n01i01129ent;
ARCHITECTURE c06s05b00x00p04n01i01129arch OF c06s05b00x00p04n01i01129ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (M1, M2, M3, M4, M5);
type ENUM2 is (N1, N2, N3, N4, N5);
type FIVE1 is range 1 to 5;
type FIVE2 is range 1 to 5;
type A1B is array (ENUM1 range <>) of BOOLEAN;
subtype A1 is A1B(ENUM1);
type A2B is array (ENUM2 range <>) of A1;
variable V1: A1 ;
constant FIVE2_2: FIVE2 := 2;
constant FIVE2_4: FIVE2 := 4;
BEGIN
V1(M2 to M4) := V1(N1 to N5);
-- SEMANTIC ERROR: DISCRETE RANGE INCOMPATIBLE WITH INDEX TYPE
assert FALSE
report "***FAILED TEST: c06s05b00x00p04n01i01129 - Discrete range incompatible with index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p04n01i01129arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/dff02/tb_dff08d.vhdl | 1 | 994 | entity tb_dff08d is
end tb_dff08d;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff08d is
signal clk : std_logic;
signal rst : std_logic;
signal en : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff08d
port map (
q => dout,
d => din,
en => en,
clk => clk,
rst => rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
wait for 1 ns;
assert dout = x"aa" severity failure;
rst <= '1';
pulse;
assert dout = x"aa" severity failure;
rst <= '0';
din <= x"38";
pulse;
assert dout = x"38" severity failure;
din <= x"af";
pulse;
assert dout = x"af" severity failure;
en <= '1';
rst <= '1';
din <= x"b5";
pulse;
assert dout = x"aa" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc108.vhd | 4 | 1718 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc108.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n06i00108ent IS
port ( signal S : out bit) ;
END c04s03b02x00p29n06i00108ent;
ARCHITECTURE c04s03b02x00p29n06i00108arch OF c04s03b02x00p29n06i00108ent IS
BEGIN
TESTING: PROCESS
variable T : TIME := 10 ns;
BEGIN
if (S'LAST_VALUE = bit'('1')) then -- Failure_here
end if;
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n06i00108 - The attribute LAST_VALUE of a signal of mode out cannot be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00108arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_06.vhd | 4 | 2378 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
use std.textio.all;
architecture test of inline_06 is
subtype encoding_type is bit_vector(1 downto 0);
attribute encoding : encoding_type;
begin
process1 : process is
-- code from book:
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle [ return controller_state ] : literal is b"00";
attribute encoding of active [ return controller_state ] : literal is b"01";
attribute encoding of fail_safe [ return controller_state ] : literal is b"10";
-- end of code from book
variable L : line;
begin
write(L, string'("process1"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, active [ return controller_state ] ' encoding);
writeline(output, L);
write(L, fail_safe [ return controller_state ] ' encoding);
writeline(output, L);
wait;
end process process1;
process2 : process is
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle : literal is b"11";
variable L : line;
begin
write(L, string'("process2"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, idle [ return load_level ] ' encoding);
writeline(output, L);
wait;
end process process2;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue881/t87io.vhdl | 1 | 348 | entity t87io is
end;
use std.textio.all;
architecture behav of t87io is
constant t1 : time := 1 ns;
constant t2 : natural := time'pos (t1);
begin
assert t1 = 1000 ps;
process
variable v : natural;
begin
-- Time resolution must be ps
v := time'pos(ps);
assert v = 1 severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc707.vhd | 4 | 3430 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc707.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:08 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:44 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:46 1996 --
-- **************************** --
package c03s04b01x00p23n01i00707pkg is
type Waveform_element is record
Value: Bit;
At: Time;
end record;
type Signal_history is file of Waveform_element;
end c03s04b01x00p23n01i00707pkg;
use work.c03s04b01x00p23n01i00707pkg.all;
ENTITY c03s04b01x00p23n01i00707ent IS
END c03s04b01x00p23n01i00707ent;
ARCHITECTURE c03s04b01x00p23n01i00707arch OF c03s04b01x00p23n01i00707ent IS
BEGIN
TESTING: PROCESS
-- Declare the actual file to read.
file FILEV : Signal_history open read_mode is "iofile.58";
-- Declare a variable into which we will read.
constant con : Waveform_element := ('1',10 ns);
variable VAR : Waveform_element;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00707"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00707 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00707arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/vector.d/cmp_174.vhd | 2 | 376 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_174 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_174;
architecture augh of cmp_174 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc335.vhd | 4 | 1797 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc335.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p06n01i00335ent IS
END c03s02b01x00p06n01i00335ent;
ARCHITECTURE c03s02b01x00p06n01i00335arch OF c03s02b01x00p06n01i00335ent IS
type bit_vctor is array (1 to 1) of integer;
BEGIN
TESTING: PROCESS
variable k :bit_vctor;
BEGIN
k(1) := 56;
assert NOT(k(1)=56)
report "***PASSED TEST: c03s02b01x00p06n01i00335"
severity NOTE;
assert (k(1)=56)
report "***FAILED TEST: c03s02b01x00p06n01i00335 - The index constraint is a list of discrete ranges enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p06n01i00335arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_07a.vhd | 4 | 1793 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_07a is
end entity inline_07a;
----------------------------------------------------------------
architecture test of inline_07a is
begin
process is
-- code from book:
type value_cell;
type value_ptr is access value_cell;
type value_cell is record
value : real_vector(0 to 3);
next_cell : value_ptr;
end record value_cell;
variable value_list : value_ptr;
-- end of code from book
begin
-- code from book:
if value_list /= null then
-- . . . -- do something with the list
-- not in book
report "value_list /= null";
-- end not in book
end if;
value_list := new value_cell'( real_vector'(0.0, 5.0, 0.0, 42.0), value_list );
value_list := new value_cell'( real_vector'(3.3, 2.2, 0.27, 1.9), value_list );
value_list := new value_cell'( real_vector'(2.9, 0.1, 21.12, 8.3), value_list );
-- end of code from book
wait;
end process;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1441.vhd | 4 | 1635 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1441.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01441ent IS
END c08s07b00x00p02n01i01441ent;
ARCHITECTURE c08s07b00x00p02n01i01441arch OF c08s07b00x00p02n01i01441ent IS
begin
process
variable k : INTEGER := 1;
begin
if k = 1 then
NULL;
end if;
NULL;
elsif
NULL:
assert FALSE
report "***FAILED TEST: c08s07b00x00p02n01i01441 - missing semicolon after 'end if'"
severity ERROR;
wait;
end process;
END c08s07b00x00p02n01i01441arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug071/atod.vhdl | 1 | 1272 | entity atod is
end atod;
architecture behav of atod is
type real_array is array (natural range <>) of real;
constant csts : real_array :=
(1.0,
0.0,
-- Corner cases from
-- http://www.exploringbinary.com/
-- decimal-to-realing-point-needs-arbitrary-precision/
7.8459735791271921e65,
-- In binary:
-- 1.11011100 11010000 00001000 10011100 00010011 00010100 1110 e218
-- 1. d c d 0 0 8 9 c 1 3 1 4 e
3.571e266,
-- 1.01100010 01100100 01001100 01100001 11010100 00011010 1010 e885
-- 1. 6 2 6 4 4 c 6 1 d 4 1 a a
3.08984926168550152811E-32,
-- 1.01000000 11011110 01001000 01100111 01100110 01010011 1011 e-105
-- 1. 4 0 d e 4 8 6 7 6 6 5 3 b
7.4505805969238281e-09
-- 1.00000000 e-27
);
begin
process
variable v : real;
begin
for i in csts'range loop
report to_string (csts (i), "%a") severity note;
end loop;
v := csts (2);
assert to_string (v, "%.13a") = "0x1.dcd0089c1314ep+218" severity failure;
v := csts (3);
assert to_string (v, "%.13a") = "0x1.62644c61d41aap+885" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1179.vhd | 4 | 1565 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1179.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s00b00x00p01n02i01179ent IS
END c08s00b00x00p01n02i01179ent;
ARCHITECTURE c08s00b00x00p01n02i01179arch OF c08s00b00x00p01n02i01179ent IS
BEGIN
TESTING: PROCESS
BEGIN
for i in FALSE to TRUE loop
end loop;
assert FALSE
report "***PASSED TEST: c08s00b00x00p01n02i01179"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s00b00x00p01n02i01179arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2126.vhd | 4 | 2716 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2126.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02126ent IS
END c07s02b04x00p20n01i02126ent;
ARCHITECTURE c07s02b04x00p20n01i02126arch OF c07s02b04x00p20n01i02126ent IS
TYPE integer_v is array (integer range <>) of integer;
SUBTYPE integer_4 is integer_v (1 to 4);
SUBTYPE integer_8 is integer_v (1 to 8);
SUBTYPE integer_8_dwn is integer_v (8 downto 1);
BEGIN
TESTING: PROCESS
variable r_operand : integer_4 := ( 5,6,7,8 );
variable l_operand1: integer := 1;
variable l_operand2: integer := 2;
variable l_operand3: integer := 3;
variable l_operand4: integer := 4;
variable result : integer_8;
variable result_dwn: integer_8_dwn;
BEGIN
result_dwn := l_operand1 &
l_operand2 &
l_operand3 &
l_operand4 &
l_operand2 &
l_operand3 &
l_operand2 &
l_operand3;
assert (result_dwn = (1,2,3,4,2,3,2,3))
report "integer implicit array concatenation failed"
severity FAILURE;
assert NOT(result_dwn = (1,2,3,4,2,3,2,3))
report "***PASSED TEST: c07s02b04x00p20n01i02126"
severity NOTE;
assert (result_dwn = (1,2,3,4,2,3,2,3))
report "***FAILED TEST: c07s02b04x00p20n01i02126 - The left bound of this implicit array is the left bound of the index subtype of the array and its direction is ascending if the index subtype is ascending."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02126arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1131.vhd | 4 | 1988 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1131.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p04n01i01131ent IS
END c06s05b00x00p04n01i01131ent;
ARCHITECTURE c06s05b00x00p04n01i01131arch OF c06s05b00x00p04n01i01131ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (M1, M2, M3, M4, M5);
type ENUM2 is (N1, N2, N3, N4, N5);
type FIVE1 is range 1 to 5;
type FIVE2 is range 1 to 5;
type A1B is array (ENUM1 range <>) of BOOLEAN;
subtype A1 is A1B(ENUM1);
variable V1: A1 ;
constant FIVE2_2: FIVE2 := 2;
constant FIVE2_4: FIVE2 := 4;
BEGIN
V1(M2 to M4) := V1(N1 to M5);
-- SEMANTIC ERROR: DISCRETE RANGE INCOMPATIBLE WITH INDEX TYPE
assert FALSE
report "***FAILED TEST: c06s05b00x00p04n01i01131 - Discrete range incompatible with index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p04n01i01131arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/fsm_224.vhd | 2 | 124170 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity fsm_224 is
port (
clock : in std_logic;
reset : in std_logic;
out40 : out std_logic;
in2 : in std_logic;
in11 : in std_logic;
out146 : out std_logic;
out148 : out std_logic;
out150 : out std_logic;
out152 : out std_logic;
in12 : in std_logic;
out153 : out std_logic;
out154 : out std_logic;
in13 : in std_logic;
out156 : out std_logic;
out157 : out std_logic;
out160 : out std_logic;
out162 : out std_logic;
out165 : out std_logic;
out170 : out std_logic;
out171 : out std_logic;
out173 : out std_logic;
out175 : out std_logic;
out177 : out std_logic;
out180 : out std_logic;
out184 : out std_logic;
in14 : in std_logic;
out186 : out std_logic;
out189 : out std_logic;
out191 : out std_logic;
out192 : out std_logic;
out193 : out std_logic;
out197 : out std_logic;
out199 : out std_logic;
out201 : out std_logic;
out202 : out std_logic;
out205 : out std_logic;
out207 : out std_logic;
out208 : out std_logic;
out209 : out std_logic;
out210 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
in15 : in std_logic;
out221 : out std_logic;
out222 : out std_logic;
out224 : out std_logic;
out225 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out230 : out std_logic;
out231 : out std_logic;
out99 : out std_logic;
in6 : in std_logic;
out92 : out std_logic;
out232 : out std_logic;
in16 : in std_logic;
out234 : out std_logic;
out236 : out std_logic;
out239 : out std_logic;
out240 : out std_logic;
out241 : out std_logic;
out245 : out std_logic;
out246 : out std_logic;
out247 : out std_logic;
out251 : out std_logic;
out252 : out std_logic;
out253 : out std_logic;
out255 : out std_logic;
out256 : out std_logic;
out258 : out std_logic;
out259 : out std_logic;
in17 : in std_logic;
out263 : out std_logic;
out264 : out std_logic;
out266 : out std_logic;
in18 : in std_logic;
out267 : out std_logic;
out268 : out std_logic;
out270 : out std_logic;
out273 : out std_logic;
out275 : out std_logic;
out276 : out std_logic;
in19 : in std_logic;
out279 : out std_logic;
in20 : in std_logic;
out281 : out std_logic;
out282 : out std_logic;
in21 : in std_logic;
out283 : out std_logic;
out286 : out std_logic;
out289 : out std_logic;
out296 : out std_logic;
out297 : out std_logic;
out299 : out std_logic;
out300 : out std_logic;
out304 : out std_logic;
out305 : out std_logic;
in22 : in std_logic;
out306 : out std_logic;
out310 : out std_logic;
out311 : out std_logic;
out313 : out std_logic;
out314 : out std_logic;
in23 : in std_logic;
out316 : out std_logic;
out317 : out std_logic;
out320 : out std_logic;
out322 : out std_logic;
out324 : out std_logic;
out325 : out std_logic;
out326 : out std_logic;
out328 : out std_logic;
out332 : out std_logic;
out333 : out std_logic;
out334 : out std_logic;
out335 : out std_logic;
out338 : out std_logic;
out339 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out344 : out std_logic;
out93 : out std_logic;
out98 : out std_logic;
out85 : out std_logic;
out87 : out std_logic;
out88 : out std_logic;
out80 : out std_logic;
out82 : out std_logic;
out83 : out std_logic;
out84 : out std_logic;
in5 : in std_logic;
out77 : out std_logic;
out78 : out std_logic;
out71 : out std_logic;
out72 : out std_logic;
in4 : in std_logic;
out65 : out std_logic;
out67 : out std_logic;
out60 : out std_logic;
out64 : out std_logic;
in3 : in std_logic;
out59 : out std_logic;
out53 : out std_logic;
out55 : out std_logic;
out49 : out std_logic;
out44 : out std_logic;
out104 : out std_logic;
out107 : out std_logic;
out111 : out std_logic;
out112 : out std_logic;
out114 : out std_logic;
in7 : in std_logic;
out117 : out std_logic;
out119 : out std_logic;
out122 : out std_logic;
in8 : in std_logic;
out128 : out std_logic;
in9 : in std_logic;
out129 : out std_logic;
out130 : out std_logic;
out133 : out std_logic;
out134 : out std_logic;
out136 : out std_logic;
out137 : out std_logic;
in10 : in std_logic;
out139 : out std_logic;
out143 : out std_logic;
out144 : out std_logic;
out32 : out std_logic;
out35 : out std_logic;
out27 : out std_logic;
out25 : out std_logic;
out26 : out std_logic;
in1 : in std_logic;
out15 : out std_logic;
out16 : out std_logic;
out11 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out7 : out std_logic;
out1 : out std_logic;
out2 : out std_logic;
out3 : out std_logic;
out4 : out std_logic;
in0 : in std_logic;
in24 : in std_logic;
out346 : out std_logic;
out347 : out std_logic;
out348 : out std_logic;
out349 : out std_logic;
in25 : in std_logic;
out350 : out std_logic;
out351 : out std_logic;
out355 : out std_logic;
out356 : out std_logic;
out357 : out std_logic;
out358 : out std_logic;
out360 : out std_logic;
out362 : out std_logic;
out363 : out std_logic;
out364 : out std_logic;
out365 : out std_logic;
out366 : out std_logic;
out370 : out std_logic;
out371 : out std_logic;
out372 : out std_logic;
out373 : out std_logic;
out375 : out std_logic;
in26 : in std_logic;
out376 : out std_logic;
out378 : out std_logic;
out379 : out std_logic;
out381 : out std_logic;
out382 : out std_logic;
in27 : in std_logic;
out384 : out std_logic;
in28 : in std_logic;
out391 : out std_logic;
out395 : out std_logic;
out396 : out std_logic;
out401 : out std_logic;
out402 : out std_logic;
out403 : out std_logic;
out404 : out std_logic;
out405 : out std_logic;
out407 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
in29 : in std_logic;
out412 : out std_logic;
out414 : out std_logic;
out415 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out420 : out std_logic;
out422 : out std_logic;
out424 : out std_logic;
out425 : out std_logic;
out426 : out std_logic;
in30 : in std_logic;
out428 : out std_logic;
out429 : out std_logic;
out432 : out std_logic;
out433 : out std_logic;
out434 : out std_logic;
out437 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
in31 : in std_logic;
out443 : out std_logic;
in32 : in std_logic;
out445 : out std_logic;
out447 : out std_logic;
out448 : out std_logic;
out450 : out std_logic;
in33 : in std_logic;
out453 : out std_logic;
out455 : out std_logic;
out458 : out std_logic;
in34 : in std_logic;
out462 : out std_logic;
out464 : out std_logic;
out467 : out std_logic;
out468 : out std_logic;
out472 : out std_logic;
in35 : in std_logic;
out478 : out std_logic;
out479 : out std_logic;
out480 : out std_logic;
out487 : out std_logic;
out488 : out std_logic;
in36 : in std_logic;
out491 : out std_logic;
out496 : out std_logic;
out497 : out std_logic;
out498 : out std_logic;
out500 : out std_logic;
out504 : out std_logic;
out505 : out std_logic;
in37 : in std_logic;
out506 : out std_logic;
out508 : out std_logic;
in38 : in std_logic;
out510 : out std_logic;
out513 : out std_logic;
out514 : out std_logic;
out515 : out std_logic;
out517 : out std_logic;
out519 : out std_logic;
in39 : in std_logic;
out523 : out std_logic;
out526 : out std_logic;
out527 : out std_logic;
out528 : out std_logic;
out530 : out std_logic;
out531 : out std_logic;
out533 : out std_logic;
out534 : out std_logic;
out537 : out std_logic;
out538 : out std_logic;
out549 : out std_logic;
out558 : out std_logic;
out559 : out std_logic;
out561 : out std_logic;
in40 : in std_logic;
out566 : out std_logic;
out567 : out std_logic;
out568 : out std_logic;
out569 : out std_logic;
out570 : out std_logic;
out572 : out std_logic;
out574 : out std_logic;
out575 : out std_logic;
out577 : out std_logic;
in41 : in std_logic;
out578 : out std_logic;
out581 : out std_logic;
out589 : out std_logic;
out590 : out std_logic;
out595 : out std_logic;
out597 : out std_logic;
out599 : out std_logic;
out601 : out std_logic;
out602 : out std_logic;
out607 : out std_logic;
out610 : out std_logic;
out612 : out std_logic;
in42 : in std_logic;
out614 : out std_logic;
out621 : out std_logic;
out628 : out std_logic;
out635 : out std_logic;
out636 : out std_logic;
out638 : out std_logic;
out640 : out std_logic;
out643 : out std_logic;
out646 : out std_logic;
out649 : out std_logic;
out651 : out std_logic;
out656 : out std_logic;
in43 : in std_logic;
out658 : out std_logic;
out659 : out std_logic;
out661 : out std_logic;
out663 : out std_logic;
out664 : out std_logic;
in44 : in std_logic;
out667 : out std_logic;
out668 : out std_logic;
out670 : out std_logic;
out672 : out std_logic;
out674 : out std_logic;
in45 : in std_logic;
out679 : out std_logic;
out681 : out std_logic;
out683 : out std_logic;
out686 : out std_logic;
out688 : out std_logic;
out690 : out std_logic;
out692 : out std_logic;
out694 : out std_logic;
out696 : out std_logic;
out697 : out std_logic;
out698 : out std_logic;
out699 : out std_logic;
out700 : out std_logic;
out703 : out std_logic;
out704 : out std_logic;
out706 : out std_logic;
out708 : out std_logic;
out710 : out std_logic;
out712 : out std_logic;
out715 : out std_logic;
out718 : out std_logic;
in46 : in std_logic;
out722 : out std_logic;
out724 : out std_logic;
out726 : out std_logic;
out728 : out std_logic;
out731 : out std_logic;
out733 : out std_logic;
out734 : out std_logic;
out737 : out std_logic;
out739 : out std_logic;
out740 : out std_logic;
out743 : out std_logic;
out745 : out std_logic;
out746 : out std_logic;
in47 : in std_logic;
out749 : out std_logic;
out753 : out std_logic;
out755 : out std_logic;
out759 : out std_logic;
in48 : in std_logic;
out762 : out std_logic;
out764 : out std_logic;
out765 : out std_logic;
out767 : out std_logic;
out768 : out std_logic;
in49 : in std_logic;
out772 : out std_logic;
in50 : in std_logic;
out775 : out std_logic;
out776 : out std_logic;
out778 : out std_logic;
out783 : out std_logic;
out784 : out std_logic;
out787 : out std_logic;
out791 : out std_logic;
in51 : in std_logic;
out794 : out std_logic;
out795 : out std_logic;
in52 : in std_logic;
out799 : out std_logic;
out802 : out std_logic;
out806 : out std_logic;
out809 : out std_logic;
out812 : out std_logic;
out815 : out std_logic;
out826 : out std_logic;
out828 : out std_logic;
in53 : in std_logic;
in54 : in std_logic;
out843 : out std_logic;
out848 : out std_logic;
out852 : out std_logic;
in55 : in std_logic;
out855 : out std_logic;
out858 : out std_logic;
in56 : in std_logic;
out860 : out std_logic;
out861 : out std_logic;
out863 : out std_logic;
out866 : out std_logic;
out872 : out std_logic;
in57 : in std_logic;
out874 : out std_logic;
out876 : out std_logic;
out879 : out std_logic;
out882 : out std_logic;
out886 : out std_logic;
out887 : out std_logic;
in58 : in std_logic;
out888 : out std_logic;
out892 : out std_logic;
out894 : out std_logic;
out895 : out std_logic;
out896 : out std_logic;
out901 : out std_logic;
out902 : out std_logic;
out903 : out std_logic;
out905 : out std_logic;
out907 : out std_logic;
out918 : out std_logic;
out920 : out std_logic;
out921 : out std_logic;
out923 : out std_logic;
out925 : out std_logic;
out928 : out std_logic;
out929 : out std_logic;
out931 : out std_logic;
out933 : out std_logic;
out936 : out std_logic;
out937 : out std_logic;
out938 : out std_logic;
out939 : out std_logic;
out942 : out std_logic;
out943 : out std_logic;
out944 : out std_logic;
out947 : out std_logic;
out948 : out std_logic;
out949 : out std_logic;
out951 : out std_logic;
in59 : in std_logic;
out952 : out std_logic;
out953 : out std_logic;
out955 : out std_logic;
out956 : out std_logic;
out957 : out std_logic;
out958 : out std_logic;
in60 : in std_logic;
in61 : in std_logic;
out962 : out std_logic;
out963 : out std_logic;
out972 : out std_logic;
out973 : out std_logic;
out974 : out std_logic;
in62 : in std_logic;
out978 : out std_logic;
out979 : out std_logic;
out981 : out std_logic;
out982 : out std_logic;
out985 : out std_logic;
out986 : out std_logic;
out989 : out std_logic;
in63 : in std_logic;
in64 : in std_logic;
in65 : in std_logic;
in66 : in std_logic;
in67 : in std_logic;
in68 : in std_logic;
in69 : in std_logic;
in70 : in std_logic;
in71 : in std_logic;
in72 : in std_logic;
in73 : in std_logic;
in74 : in std_logic;
in75 : in std_logic;
in76 : in std_logic;
in77 : in std_logic;
in78 : in std_logic;
out990 : out std_logic;
out991 : out std_logic;
out993 : out std_logic;
out994 : out std_logic;
out996 : out std_logic;
out997 : out std_logic;
out998 : out std_logic;
out999 : out std_logic;
out1000 : out std_logic;
out1002 : out std_logic;
out1003 : out std_logic;
out1005 : out std_logic;
out1006 : out std_logic;
out1007 : out std_logic;
out1009 : out std_logic;
out1011 : out std_logic;
out1012 : out std_logic;
out1013 : out std_logic;
out1014 : out std_logic;
out1015 : out std_logic;
out1016 : out std_logic;
out1018 : out std_logic;
out1019 : out std_logic;
out1021 : out std_logic;
out1022 : out std_logic;
out1024 : out std_logic;
out1026 : out std_logic;
out1027 : out std_logic;
out1029 : out std_logic;
out1030 : out std_logic;
out1032 : out std_logic;
out1033 : out std_logic;
out1035 : out std_logic;
out1036 : out std_logic;
out1037 : out std_logic;
out1057 : out std_logic;
out1068 : out std_logic;
out1069 : out std_logic;
out1070 : out std_logic;
out1072 : out std_logic;
out1073 : out std_logic;
out1075 : out std_logic;
out1078 : out std_logic;
out1080 : out std_logic;
out1082 : out std_logic;
out1083 : out std_logic;
out1084 : out std_logic;
out1085 : out std_logic;
out1088 : out std_logic;
out1089 : out std_logic;
out1091 : out std_logic;
out1092 : out std_logic;
out1094 : out std_logic;
out1096 : out std_logic;
out1098 : out std_logic;
out1101 : out std_logic;
out1104 : out std_logic;
out1107 : out std_logic;
out1109 : out std_logic;
out1111 : out std_logic;
out1114 : out std_logic;
out1119 : out std_logic;
out1121 : out std_logic;
out1125 : out std_logic;
out1126 : out std_logic;
out1128 : out std_logic;
out1131 : out std_logic;
out1134 : out std_logic;
out1137 : out std_logic;
out1139 : out std_logic;
out1141 : out std_logic;
out1145 : out std_logic;
out1146 : out std_logic;
out1147 : out std_logic;
out1150 : out std_logic;
out1151 : out std_logic;
out1152 : out std_logic;
out1155 : out std_logic;
out1158 : out std_logic;
out1160 : out std_logic;
out1164 : out std_logic;
out1166 : out std_logic;
out1169 : out std_logic;
out1171 : out std_logic;
out1174 : out std_logic;
out1175 : out std_logic;
out1176 : out std_logic;
out1180 : out std_logic;
out1181 : out std_logic;
out1182 : out std_logic;
out1185 : out std_logic;
out1186 : out std_logic;
out1187 : out std_logic;
out1190 : out std_logic;
out1213 : out std_logic;
out1215 : out std_logic;
out1217 : out std_logic;
out1220 : out std_logic;
out1221 : out std_logic;
out1223 : out std_logic;
out1228 : out std_logic;
out1229 : out std_logic;
out1231 : out std_logic;
out1235 : out std_logic;
out1236 : out std_logic;
out1240 : out std_logic;
out1243 : out std_logic;
out1250 : out std_logic;
out1252 : out std_logic;
out1253 : out std_logic;
out1258 : out std_logic;
out1262 : out std_logic;
out1266 : out std_logic;
out1269 : out std_logic;
out1275 : out std_logic;
out1278 : out std_logic;
out1279 : out std_logic;
out1284 : out std_logic;
out1286 : out std_logic;
out1287 : out std_logic;
out1289 : out std_logic;
out1290 : out std_logic;
out1292 : out std_logic;
out1293 : out std_logic;
out1295 : out std_logic;
out1298 : out std_logic;
out1301 : out std_logic;
out1302 : out std_logic;
out1303 : out std_logic;
out1308 : out std_logic;
out1309 : out std_logic;
out1311 : out std_logic;
out1318 : out std_logic;
out1319 : out std_logic;
out1320 : out std_logic;
out1323 : out std_logic;
out1324 : out std_logic;
out1326 : out std_logic;
out1327 : out std_logic;
out1329 : out std_logic;
out1337 : out std_logic;
out1339 : out std_logic;
out1340 : out std_logic;
out1341 : out std_logic;
out1344 : out std_logic;
out1346 : out std_logic;
out1349 : out std_logic;
out1353 : out std_logic;
out1356 : out std_logic;
out1362 : out std_logic;
out1363 : out std_logic;
out1364 : out std_logic;
out1365 : out std_logic;
out1366 : out std_logic;
out1368 : out std_logic;
out1370 : out std_logic;
out1375 : out std_logic;
out1378 : out std_logic;
out1381 : out std_logic;
out1383 : out std_logic;
out1387 : out std_logic
);
end fsm_224;
architecture augh of fsm_224 is
signal state_cur : std_logic_vector(0 to 473) := (457 => '1', others => '0');
signal state_next : std_logic_vector(0 to 473) := (457 => '1', others => '0');
-- Buffers for outputs
signal out1057_buf : std_logic := '0';
signal out1057_bufn : std_logic;
signal out59_buf : std_logic := '0';
signal out59_bufn : std_logic;
signal out447_buf : std_logic := '0';
signal out447_bufn : std_logic;
signal out157_buf : std_logic := '0';
signal out157_bufn : std_logic;
signal out450_buf : std_logic := '0';
signal out450_bufn : std_logic;
signal out1012_buf : std_logic := '0';
signal out1012_bufn : std_logic;
signal out1072_buf : std_logic := '0';
signal out1072_bufn : std_logic;
signal out999_buf : std_logic := '0';
signal out999_bufn : std_logic;
signal out437_buf : std_logic := '0';
signal out437_bufn : std_logic;
signal out415_buf : std_logic := '0';
signal out415_bufn : std_logic;
signal out426_buf : std_logic := '0';
signal out426_bufn : std_logic;
signal out375_buf : std_logic := '0';
signal out375_bufn : std_logic;
signal out704_buf : std_logic := '0';
signal out704_bufn : std_logic;
signal out973_buf : std_logic := '0';
signal out973_bufn : std_logic;
signal out11_buf : std_logic := '0';
signal out11_bufn : std_logic;
signal out549_buf : std_logic := '0';
signal out549_bufn : std_logic;
signal out453_buf : std_logic := '0';
signal out453_bufn : std_logic;
signal out1231_buf : std_logic := '0';
signal out1231_bufn : std_logic;
signal out87_buf : std_logic := '0';
signal out87_bufn : std_logic;
signal out401_buf : std_logic := '0';
signal out401_bufn : std_logic;
signal out990_buf : std_logic := '0';
signal out990_bufn : std_logic;
signal out378_buf : std_logic := '0';
signal out378_bufn : std_logic;
signal out1302_buf : std_logic := '0';
signal out1302_bufn : std_logic;
signal out27_buf : std_logic := '0';
signal out27_bufn : std_logic;
signal out569_buf : std_logic := '0';
signal out569_bufn : std_logic;
signal out1030_buf : std_logic := '0';
signal out1030_bufn : std_logic;
signal out537_buf : std_logic := '0';
signal out537_bufn : std_logic;
signal out77_buf : std_logic := '0';
signal out77_bufn : std_logic;
signal out1318_buf : std_logic := '0';
signal out1318_bufn : std_logic;
signal out533_buf : std_logic := '0';
signal out533_bufn : std_logic;
signal out32_buf : std_logic := '0';
signal out32_bufn : std_logic;
signal out1027_buf : std_logic := '0';
signal out1027_bufn : std_logic;
signal out599_buf : std_logic := '0';
signal out599_bufn : std_logic;
signal out668_buf : std_logic := '0';
signal out668_bufn : std_logic;
signal out568_buf : std_logic := '0';
signal out568_bufn : std_logic;
signal out225_buf : std_logic := '0';
signal out225_bufn : std_logic;
signal out700_buf : std_logic := '0';
signal out700_bufn : std_logic;
signal out638_buf : std_logic := '0';
signal out638_bufn : std_logic;
signal out670_buf : std_logic := '0';
signal out670_bufn : std_logic;
signal out433_buf : std_logic := '0';
signal out433_bufn : std_logic;
signal out896_buf : std_logic := '0';
signal out896_bufn : std_logic;
signal out575_buf : std_logic := '0';
signal out575_bufn : std_logic;
signal out428_buf : std_logic := '0';
signal out428_bufn : std_logic;
signal out72_buf : std_logic := '0';
signal out72_bufn : std_logic;
signal out404_buf : std_logic := '0';
signal out404_bufn : std_logic;
signal out98_buf : std_logic := '0';
signal out98_bufn : std_logic;
signal out67_buf : std_logic := '0';
signal out67_bufn : std_logic;
signal out635_buf : std_logic := '0';
signal out635_bufn : std_logic;
signal out381_buf : std_logic := '0';
signal out381_bufn : std_logic;
signal out222_buf : std_logic := '0';
signal out222_bufn : std_logic;
signal out339_buf : std_logic := '0';
signal out339_bufn : std_logic;
signal out268_buf : std_logic := '0';
signal out268_bufn : std_logic;
signal out419_buf : std_logic := '0';
signal out419_bufn : std_logic;
signal out559_buf : std_logic := '0';
signal out559_bufn : std_logic;
signal out1002_buf : std_logic := '0';
signal out1002_bufn : std_logic;
signal out1006_buf : std_logic := '0';
signal out1006_bufn : std_logic;
signal out276_buf : std_logic := '0';
signal out276_bufn : std_logic;
signal out205_buf : std_logic := '0';
signal out205_bufn : std_logic;
signal out943_buf : std_logic := '0';
signal out943_bufn : std_logic;
signal out1080_buf : std_logic := '0';
signal out1080_bufn : std_logic;
signal out408_buf : std_logic := '0';
signal out408_bufn : std_logic;
signal out252_buf : std_logic := '0';
signal out252_bufn : std_logic;
signal out71_buf : std_logic := '0';
signal out71_bufn : std_logic;
signal out672_buf : std_logic := '0';
signal out672_bufn : std_logic;
signal out357_buf : std_logic := '0';
signal out357_bufn : std_logic;
signal out441_buf : std_logic := '0';
signal out441_bufn : std_logic;
signal out1084_buf : std_logic := '0';
signal out1084_bufn : std_logic;
signal out144_buf : std_logic := '0';
signal out144_bufn : std_logic;
signal out574_buf : std_logic := '0';
signal out574_bufn : std_logic;
signal out210_buf : std_logic := '0';
signal out210_bufn : std_logic;
signal out128_buf : std_logic := '0';
signal out128_bufn : std_logic;
signal out360_buf : std_logic := '0';
signal out360_bufn : std_logic;
signal out948_buf : std_logic := '0';
signal out948_bufn : std_logic;
signal out506_buf : std_logic := '0';
signal out506_bufn : std_logic;
signal out207_buf : std_logic := '0';
signal out207_bufn : std_logic;
signal out1083_buf : std_logic := '0';
signal out1083_bufn : std_logic;
signal out491_buf : std_logic := '0';
signal out491_bufn : std_logic;
signal out4_buf : std_logic := '0';
signal out4_bufn : std_logic;
signal out784_buf : std_logic := '0';
signal out784_bufn : std_logic;
signal out3_buf : std_logic := '0';
signal out3_bufn : std_logic;
signal out746_buf : std_logic := '0';
signal out746_bufn : std_logic;
signal out528_buf : std_logic := '0';
signal out528_bufn : std_logic;
signal out372_buf : std_logic := '0';
signal out372_bufn : std_logic;
signal out418_buf : std_logic := '0';
signal out418_bufn : std_logic;
signal out708_buf : std_logic := '0';
signal out708_bufn : std_logic;
signal out706_buf : std_logic := '0';
signal out706_bufn : std_logic;
signal out445_buf : std_logic := '0';
signal out445_bufn : std_logic;
signal out1021_buf : std_logic := '0';
signal out1021_bufn : std_logic;
signal out405_buf : std_logic := '0';
signal out405_bufn : std_logic;
signal out764_buf : std_logic := '0';
signal out764_bufn : std_logic;
signal out581_buf : std_logic := '0';
signal out581_bufn : std_logic;
signal out776_buf : std_logic := '0';
signal out776_bufn : std_logic;
signal out213_buf : std_logic := '0';
signal out213_bufn : std_logic;
signal out674_buf : std_logic := '0';
signal out674_bufn : std_logic;
signal out1326_buf : std_logic := '0';
signal out1326_bufn : std_logic;
signal out334_buf : std_logic := '0';
signal out334_bufn : std_logic;
signal out843_buf : std_logic := '0';
signal out843_bufn : std_logic;
signal out175_buf : std_logic := '0';
signal out175_bufn : std_logic;
signal out1036_buf : std_logic := '0';
signal out1036_bufn : std_logic;
signal out1015_buf : std_logic := '0';
signal out1015_bufn : std_logic;
signal out236_buf : std_logic := '0';
signal out236_bufn : std_logic;
signal out395_buf : std_logic := '0';
signal out395_bufn : std_logic;
signal out1340_buf : std_logic := '0';
signal out1340_bufn : std_logic;
signal out993_buf : std_logic := '0';
signal out993_bufn : std_logic;
signal out356_buf : std_logic := '0';
signal out356_bufn : std_logic;
signal out273_buf : std_logic := '0';
signal out273_bufn : std_logic;
signal out403_buf : std_logic := '0';
signal out403_bufn : std_logic;
signal out286_buf : std_logic := '0';
signal out286_bufn : std_logic;
signal out364_buf : std_logic := '0';
signal out364_bufn : std_logic;
signal out697_buf : std_logic := '0';
signal out697_bufn : std_logic;
signal out283_buf : std_logic := '0';
signal out283_bufn : std_logic;
signal out282_buf : std_logic := '0';
signal out282_bufn : std_logic;
signal out1319_buf : std_logic := '0';
signal out1319_bufn : std_logic;
signal out409_buf : std_logic := '0';
signal out409_bufn : std_logic;
signal out1092_buf : std_logic := '0';
signal out1092_bufn : std_logic;
signal out1075_buf : std_logic := '0';
signal out1075_bufn : std_logic;
signal out925_buf : std_logic := '0';
signal out925_bufn : std_logic;
signal out78_buf : std_logic := '0';
signal out78_bufn : std_logic;
signal out1089_buf : std_logic := '0';
signal out1089_bufn : std_logic;
signal out362_buf : std_logic := '0';
signal out362_bufn : std_logic;
signal out982_buf : std_logic := '0';
signal out982_bufn : std_logic;
signal out979_buf : std_logic := '0';
signal out979_bufn : std_logic;
signal out952_buf : std_logic := '0';
signal out952_bufn : std_logic;
signal out1109_buf : std_logic := '0';
signal out1109_bufn : std_logic;
signal out16_buf : std_logic := '0';
signal out16_bufn : std_logic;
signal out703_buf : std_logic := '0';
signal out703_bufn : std_logic;
signal out371_buf : std_logic := '0';
signal out371_bufn : std_logic;
signal out956_buf : std_logic := '0';
signal out956_bufn : std_logic;
signal out1107_buf : std_logic := '0';
signal out1107_bufn : std_logic;
signal out1033_buf : std_logic := '0';
signal out1033_bufn : std_logic;
signal out148_buf : std_logic := '0';
signal out148_bufn : std_logic;
signal out351_buf : std_logic := '0';
signal out351_bufn : std_logic;
signal out740_buf : std_logic := '0';
signal out740_bufn : std_logic;
signal out391_buf : std_logic := '0';
signal out391_bufn : std_logic;
signal out129_buf : std_logic := '0';
signal out129_bufn : std_logic;
signal out338_buf : std_logic := '0';
signal out338_bufn : std_logic;
signal out425_buf : std_logic := '0';
signal out425_bufn : std_logic;
signal out1078_buf : std_logic := '0';
signal out1078_bufn : std_logic;
signal out349_buf : std_logic := '0';
signal out349_bufn : std_logic;
signal out590_buf : std_logic := '0';
signal out590_bufn : std_logic;
signal out325_buf : std_logic := '0';
signal out325_bufn : std_logic;
signal out112_buf : std_logic := '0';
signal out112_bufn : std_logic;
signal out224_buf : std_logic := '0';
signal out224_bufn : std_logic;
signal out1220_buf : std_logic := '0';
signal out1220_bufn : std_logic;
signal out1250_buf : std_logic := '0';
signal out1250_bufn : std_logic;
signal out365_buf : std_logic := '0';
signal out365_bufn : std_logic;
signal out699_buf : std_logic := '0';
signal out699_bufn : std_logic;
signal out488_buf : std_logic := '0';
signal out488_bufn : std_logic;
signal out1069_buf : std_logic := '0';
signal out1069_bufn : std_logic;
signal out530_buf : std_logic := '0';
signal out530_bufn : std_logic;
signal out326_buf : std_logic := '0';
signal out326_bufn : std_logic;
signal out602_buf : std_logic := '0';
signal out602_bufn : std_logic;
signal out83_buf : std_logic := '0';
signal out83_bufn : std_logic;
signal out311_buf : std_logic := '0';
signal out311_bufn : std_logic;
signal out253_buf : std_logic := '0';
signal out253_bufn : std_logic;
signal out209_buf : std_logic := '0';
signal out209_bufn : std_logic;
signal out1240_buf : std_logic := '0';
signal out1240_bufn : std_logic;
signal out1018_buf : std_logic := '0';
signal out1018_bufn : std_logic;
signal out1152_buf : std_logic := '0';
signal out1152_bufn : std_logic;
signal out1236_buf : std_logic := '0';
signal out1236_bufn : std_logic;
signal out130_buf : std_logic := '0';
signal out130_bufn : std_logic;
signal out567_buf : std_logic := '0';
signal out567_bufn : std_logic;
signal out646_buf : std_logic := '0';
signal out646_bufn : std_logic;
-- Function calls: return IDs
signal funccall0 : natural range 0 to 18 := 0;
signal funccall0_next : natural range 0 to 18 := 0;
signal funccall1 : natural range 0 to 6 := 0;
signal funccall1_next : natural range 0 to 6 := 0;
signal funccall2 : natural range 0 to 2 := 0;
signal funccall2_next : natural range 0 to 2 := 0;
signal funccall3 : natural range 0 to 3 := 0;
signal funccall3_next : natural range 0 to 3 := 0;
signal funccall4 : natural range 0 to 1 := 0;
signal funccall4_next : natural range 0 to 1 := 0;
signal funccall5 : natural range 0 to 1 := 0;
signal funccall5_next : natural range 0 to 1 := 0;
signal funccall6 : natural range 0 to 1 := 0;
signal funccall6_next : natural range 0 to 1 := 0;
signal funccall7 : natural range 0 to 4 := 0;
signal funccall7_next : natural range 0 to 4 := 0;
signal funccall8 : natural range 0 to 1 := 0;
signal funccall8_next : natural range 0 to 1 := 0;
signal funccall9 : natural range 0 to 3 := 0;
signal funccall9_next : natural range 0 to 3 := 0;
-- A utility function to convert bool to std_logic
function to_stdl (b: boolean) return std_logic is
begin
if b = true then
return '1';
end if;
return '0';
end function;
begin
-- Sequential process
-- Set the current state
process (clock)
begin
if rising_edge(clock) then
-- Next state
state_cur <= state_next;
-- Buffers for outputs
out1057_buf <= out1057_bufn;
out59_buf <= out59_bufn;
out447_buf <= out447_bufn;
out157_buf <= out157_bufn;
out450_buf <= out450_bufn;
out1012_buf <= out1012_bufn;
out1072_buf <= out1072_bufn;
out999_buf <= out999_bufn;
out437_buf <= out437_bufn;
out415_buf <= out415_bufn;
out426_buf <= out426_bufn;
out375_buf <= out375_bufn;
out704_buf <= out704_bufn;
out973_buf <= out973_bufn;
out11_buf <= out11_bufn;
out549_buf <= out549_bufn;
out453_buf <= out453_bufn;
out1231_buf <= out1231_bufn;
out87_buf <= out87_bufn;
out401_buf <= out401_bufn;
out990_buf <= out990_bufn;
out378_buf <= out378_bufn;
out1302_buf <= out1302_bufn;
out27_buf <= out27_bufn;
out569_buf <= out569_bufn;
out1030_buf <= out1030_bufn;
out537_buf <= out537_bufn;
out77_buf <= out77_bufn;
out1318_buf <= out1318_bufn;
out533_buf <= out533_bufn;
out32_buf <= out32_bufn;
out1027_buf <= out1027_bufn;
out599_buf <= out599_bufn;
out668_buf <= out668_bufn;
out568_buf <= out568_bufn;
out225_buf <= out225_bufn;
out700_buf <= out700_bufn;
out638_buf <= out638_bufn;
out670_buf <= out670_bufn;
out433_buf <= out433_bufn;
out896_buf <= out896_bufn;
out575_buf <= out575_bufn;
out428_buf <= out428_bufn;
out72_buf <= out72_bufn;
out404_buf <= out404_bufn;
out98_buf <= out98_bufn;
out67_buf <= out67_bufn;
out635_buf <= out635_bufn;
out381_buf <= out381_bufn;
out222_buf <= out222_bufn;
out339_buf <= out339_bufn;
out268_buf <= out268_bufn;
out419_buf <= out419_bufn;
out559_buf <= out559_bufn;
out1002_buf <= out1002_bufn;
out1006_buf <= out1006_bufn;
out276_buf <= out276_bufn;
out205_buf <= out205_bufn;
out943_buf <= out943_bufn;
out1080_buf <= out1080_bufn;
out408_buf <= out408_bufn;
out252_buf <= out252_bufn;
out71_buf <= out71_bufn;
out672_buf <= out672_bufn;
out357_buf <= out357_bufn;
out441_buf <= out441_bufn;
out1084_buf <= out1084_bufn;
out144_buf <= out144_bufn;
out574_buf <= out574_bufn;
out210_buf <= out210_bufn;
out128_buf <= out128_bufn;
out360_buf <= out360_bufn;
out948_buf <= out948_bufn;
out506_buf <= out506_bufn;
out207_buf <= out207_bufn;
out1083_buf <= out1083_bufn;
out491_buf <= out491_bufn;
out4_buf <= out4_bufn;
out784_buf <= out784_bufn;
out3_buf <= out3_bufn;
out746_buf <= out746_bufn;
out528_buf <= out528_bufn;
out372_buf <= out372_bufn;
out418_buf <= out418_bufn;
out708_buf <= out708_bufn;
out706_buf <= out706_bufn;
out445_buf <= out445_bufn;
out1021_buf <= out1021_bufn;
out405_buf <= out405_bufn;
out764_buf <= out764_bufn;
out581_buf <= out581_bufn;
out776_buf <= out776_bufn;
out213_buf <= out213_bufn;
out674_buf <= out674_bufn;
out1326_buf <= out1326_bufn;
out334_buf <= out334_bufn;
out843_buf <= out843_bufn;
out175_buf <= out175_bufn;
out1036_buf <= out1036_bufn;
out1015_buf <= out1015_bufn;
out236_buf <= out236_bufn;
out395_buf <= out395_bufn;
out1340_buf <= out1340_bufn;
out993_buf <= out993_bufn;
out356_buf <= out356_bufn;
out273_buf <= out273_bufn;
out403_buf <= out403_bufn;
out286_buf <= out286_bufn;
out364_buf <= out364_bufn;
out697_buf <= out697_bufn;
out283_buf <= out283_bufn;
out282_buf <= out282_bufn;
out1319_buf <= out1319_bufn;
out409_buf <= out409_bufn;
out1092_buf <= out1092_bufn;
out1075_buf <= out1075_bufn;
out925_buf <= out925_bufn;
out78_buf <= out78_bufn;
out1089_buf <= out1089_bufn;
out362_buf <= out362_bufn;
out982_buf <= out982_bufn;
out979_buf <= out979_bufn;
out952_buf <= out952_bufn;
out1109_buf <= out1109_bufn;
out16_buf <= out16_bufn;
out703_buf <= out703_bufn;
out371_buf <= out371_bufn;
out956_buf <= out956_bufn;
out1107_buf <= out1107_bufn;
out1033_buf <= out1033_bufn;
out148_buf <= out148_bufn;
out351_buf <= out351_bufn;
out740_buf <= out740_bufn;
out391_buf <= out391_bufn;
out129_buf <= out129_bufn;
out338_buf <= out338_bufn;
out425_buf <= out425_bufn;
out1078_buf <= out1078_bufn;
out349_buf <= out349_bufn;
out590_buf <= out590_bufn;
out325_buf <= out325_bufn;
out112_buf <= out112_bufn;
out224_buf <= out224_bufn;
out1220_buf <= out1220_bufn;
out1250_buf <= out1250_bufn;
out365_buf <= out365_bufn;
out699_buf <= out699_bufn;
out488_buf <= out488_bufn;
out1069_buf <= out1069_bufn;
out530_buf <= out530_bufn;
out326_buf <= out326_bufn;
out602_buf <= out602_bufn;
out83_buf <= out83_bufn;
out311_buf <= out311_bufn;
out253_buf <= out253_bufn;
out209_buf <= out209_bufn;
out1240_buf <= out1240_bufn;
out1018_buf <= out1018_bufn;
out1152_buf <= out1152_bufn;
out1236_buf <= out1236_bufn;
out130_buf <= out130_bufn;
out567_buf <= out567_bufn;
out646_buf <= out646_bufn;
-- Function calls: return IDs
funccall0 <= funccall0_next;
funccall1 <= funccall1_next;
funccall2 <= funccall2_next;
funccall3 <= funccall3_next;
funccall4 <= funccall4_next;
funccall5 <= funccall5_next;
funccall6 <= funccall6_next;
funccall7 <= funccall7_next;
funccall8 <= funccall8_next;
funccall9 <= funccall9_next;
end if;
end process;
-- Function calls: The call IDs
-- Function 'read_byte'
funccall0_next <=
0 when ( state_cur(130) and in33 ) = '1' else
2 when ( state_cur(130) and not ( in33 ) ) = '1' else
18 when ( state_cur(137) and not ( in34 ) ) = '1' else
17 when ( state_cur(148) and in36 ) = '1' else
16 when ( state_cur(160) and in38 ) = '1' else
15 when ( state_cur(170) and in39 ) = '1' else
14 when ( state_cur(179) and in40 ) = '1' else
10 when ( state_cur(207) and to_stdl(funccall1 = 3) ) = '1' else
5 when ( state_cur(207) and to_stdl(funccall1 = 0) ) = '1' else
12 when state_cur(211) = '1' else
11 when ( state_cur(212) and in43 ) = '1' else
9 when state_cur(237) = '1' else
8 when state_cur(238) = '1' else
7 when state_cur(242) = '1' else
6 when state_cur(243) = '1' else
2 when ( state_cur(246) and not ( in46 ) ) = '1' else
3 when ( state_cur(249) and in47 ) = '1' else
4 when ( state_cur(249) and not ( in47 ) ) = '1' else
4 when ( state_cur(251) and in48 ) = '1' else
13 when ( state_cur(338) and in52 ) = '1' else
1 when ( state_cur(396) and to_stdl(funccall0 = 0) ) = '1' else
funccall0;
-- Function 'read_word'
funccall1_next <=
5 when ( state_cur(126) and not ( in32 ) and in31 ) = '1' else
4 when ( state_cur(126) and not ( in32 ) and not ( in31 ) and in30 ) = '1' else
3 when ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and in29 ) = '1' else
0 when ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and in28 ) = '1' else
6 when ( state_cur(137) and in34 ) = '1' else
2 when state_cur(244) = '1' else
1 when ( state_cur(396) and to_stdl(funccall0 = 5) ) = '1' else
funccall1;
-- Function 'pgetc'
funccall2_next <=
1 when state_cur(72) = '1' else
2 when ( state_cur(73) and not ( in20 ) ) = '1' else
0 when ( state_cur(78) and in23 ) = '1' else
funccall2;
-- Function 'buf_getb'
funccall3_next <=
0 when state_cur(15) = '1' else
3 when ( state_cur(25) and in6 ) = '1' else
1 when ( state_cur(30) and in8 ) = '1' else
2 when state_cur(270) = '1' else
funccall3;
-- Function 'buf_getv'
funccall4_next <=
0 when state_cur(254) = '1' else
1 when state_cur(256) = '1' else
funccall4;
-- Function 'huff_make_dhuff_tb_ac'
funccall5_next <=
0 when state_cur(259) = '1' else
1 when state_cur(260) = '1' else
funccall5;
-- Function 'huff_make_dhuff_tb_dc'
funccall6_next <=
1 when state_cur(258) = '1' else
0 when state_cur(333) = '1' else
funccall6;
-- Function 'WriteOneBlock'
funccall7_next <=
1 when state_cur(257) = '1' else
2 when state_cur(445) = '1' else
3 when state_cur(461) = '1' else
4 when state_cur(462) = '1' else
0 when state_cur(469) = '1' else
funccall7;
-- Function 'YuvToRgb'
funccall8_next <=
0 when state_cur(468) = '1' else
1 when state_cur(472) = '1' else
funccall8;
-- Function 'decode_block'
funccall9_next <=
0 when state_cur(418) = '1' else
1 when state_cur(458) = '1' else
2 when state_cur(470) = '1' else
3 when state_cur(471) = '1' else
funccall9;
-- Next state bits
state_next(0) <= (not reset) and ( ( state_cur(422) and in65 ) );
state_next(1) <= (not reset) and ( state_cur(385) );
state_next(2) <= (not reset) and ( state_cur(8) or state_cur(3) );
state_next(3) <= (not reset) and ( ( state_cur(2) and in0 ) );
state_next(4) <= (not reset) and ( state_cur(377) );
state_next(5) <= (not reset) and ( ( state_cur(6) and in1 ) );
state_next(6) <= (not reset) and ( ( state_cur(424) and not ( in67 ) ) );
state_next(7) <= (not reset) and ( ( state_cur(252) and not ( in49 ) ) or state_cur(202) );
state_next(8) <= (not reset) and ( ( state_cur(460) and in78 ) or ( state_cur(13) and not ( in2 ) ) or ( state_cur(6) and not ( in1 ) ) );
state_next(9) <= (not reset) and ( state_cur(327) );
state_next(10) <= (not reset) and ( state_cur(140) );
state_next(11) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 16) ) );
state_next(12) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 15) ) );
state_next(13) <= (not reset) and ( state_cur(14) or state_cur(7) or state_cur(5) );
state_next(14) <= (not reset) and ( ( state_cur(17) and not ( in3 ) ) );
state_next(15) <= (not reset) and ( ( state_cur(13) and in2 ) );
state_next(16) <= (not reset) and ( ( state_cur(82) and in24 ) );
state_next(17) <= (not reset) and ( state_cur(19) or state_cur(18) );
state_next(18) <= (not reset) and ( state_cur(466) or ( state_cur(23) and not ( in4 ) ) );
state_next(19) <= (not reset) and ( ( state_cur(17) and in3 ) );
state_next(20) <= (not reset) and ( ( state_cur(454) and in76 ) );
state_next(21) <= (not reset) and ( ( state_cur(121) and in26 ) );
state_next(22) <= (not reset) and ( ( state_cur(24) and not ( in5 ) ) );
state_next(23) <= (not reset) and ( state_cur(159) or state_cur(22) );
state_next(24) <= (not reset) and ( ( state_cur(25) and not ( in6 ) ) );
state_next(25) <= (not reset) and ( state_cur(28) or state_cur(26) );
state_next(26) <= (not reset) and ( ( state_cur(77) and to_stdl(funccall3 = 3) ) or ( state_cur(75) and to_stdl(funccall3 = 3) ) );
state_next(27) <= (not reset) and ( ( state_cur(29) and not ( in7 ) ) );
state_next(28) <= (not reset) and ( ( state_cur(77) and to_stdl(funccall3 = 2) ) or ( state_cur(75) and to_stdl(funccall3 = 2) ) );
state_next(29) <= (not reset) and ( ( state_cur(30) and not ( in8 ) ) );
state_next(30) <= (not reset) and ( state_cur(32) or state_cur(31) );
state_next(31) <= (not reset) and ( ( state_cur(77) and to_stdl(funccall3 = 1) ) or ( state_cur(75) and to_stdl(funccall3 = 1) ) );
state_next(32) <= (not reset) and ( ( state_cur(77) and to_stdl(funccall3 = 0) ) or ( state_cur(75) and to_stdl(funccall3 = 0) ) );
state_next(33) <= (not reset) and ( state_cur(369) );
state_next(34) <= (not reset) and ( state_cur(188) or state_cur(38) );
state_next(35) <= (not reset) and ( ( state_cur(40) and not ( in10 ) ) );
state_next(36) <= (not reset) and ( state_cur(444) );
state_next(37) <= (not reset) and ( state_cur(328) );
state_next(38) <= (not reset) and ( ( state_cur(39) and in9 ) );
state_next(39) <= (not reset) and ( ( state_cur(40) and in10 ) );
state_next(40) <= (not reset) and ( state_cur(42) or state_cur(34) );
state_next(41) <= (not reset) and ( ( state_cur(53) and not ( in14 ) ) );
state_next(42) <= (not reset) and ( ( state_cur(43) and in11 ) );
state_next(43) <= (not reset) and ( ( state_cur(427) and not ( in68 ) ) );
state_next(44) <= (not reset) and ( ( state_cur(45) and not ( in12 ) ) );
state_next(45) <= (not reset) and ( state_cur(48) or state_cur(46) );
state_next(46) <= (not reset) and ( ( state_cur(47) and in13 ) );
state_next(47) <= (not reset) and ( state_cur(49) or state_cur(44) );
state_next(48) <= (not reset) and ( ( state_cur(45) and in12 ) );
state_next(49) <= (not reset) and ( ( state_cur(333) ) or ( state_cur(258) ) );
state_next(50) <= (not reset) and ( state_cur(430) or state_cur(52) );
state_next(51) <= (not reset) and ( ( state_cur(54) and not ( in15 ) ) );
state_next(52) <= (not reset) and ( ( state_cur(53) and in14 ) );
state_next(53) <= (not reset) and ( ( state_cur(54) and in15 ) );
state_next(54) <= (not reset) and ( state_cur(57) or state_cur(50) );
state_next(55) <= (not reset) and ( state_cur(372) );
state_next(56) <= (not reset) and ( state_cur(266) );
state_next(57) <= (not reset) and ( ( state_cur(59) and in16 ) );
state_next(58) <= (not reset) and ( state_cur(56) );
state_next(59) <= (not reset) and ( ( state_cur(366) and not ( in53 ) ) );
state_next(60) <= (not reset) and ( state_cur(350) );
state_next(61) <= (not reset) and ( ( state_cur(471) ) or ( state_cur(470) ) or ( state_cur(458) ) or ( state_cur(418) ) );
state_next(62) <= (not reset) and ( state_cur(208) );
state_next(63) <= (not reset) and ( ( state_cur(64) and not ( in17 ) ) );
state_next(64) <= (not reset) and ( state_cur(67) or state_cur(65) );
state_next(65) <= (not reset) and ( ( state_cur(66) and in18 ) );
state_next(66) <= (not reset) and ( state_cur(68) or state_cur(63) );
state_next(67) <= (not reset) and ( ( state_cur(64) and in17 ) );
state_next(68) <= (not reset) and ( ( state_cur(260) ) or ( state_cur(259) ) );
state_next(69) <= (not reset) and ( ( state_cur(74) and not ( in21 ) ) );
state_next(70) <= (not reset) and ( ( state_cur(69) and in19 ) );
state_next(71) <= (not reset) and ( ( state_cur(80) and to_stdl(funccall2 = 2) ) or ( state_cur(79) and to_stdl(funccall2 = 2) ) );
state_next(72) <= (not reset) and ( ( state_cur(73) and in20 ) );
state_next(73) <= (not reset) and ( ( state_cur(74) and in21 ) );
state_next(74) <= (not reset) and ( state_cur(432) or state_cur(71) );
state_next(75) <= (not reset) and ( ( state_cur(76) and not ( in22 ) ) );
state_next(76) <= (not reset) and ( state_cur(81) or ( state_cur(78) and not ( in23 ) ) );
state_next(77) <= (not reset) and ( ( state_cur(76) and in22 ) );
state_next(78) <= (not reset) and ( ( state_cur(270) ) or ( state_cur(30) and in8 ) or ( state_cur(25) and in6 ) or ( state_cur(15) ) );
state_next(79) <= (not reset) and ( ( state_cur(454) and not ( in76 ) ) or ( state_cur(240) and in44 ) );
state_next(80) <= (not reset) and ( ( state_cur(240) and not ( in44 ) ) );
state_next(81) <= (not reset) and ( ( state_cur(80) and to_stdl(funccall2 = 0) ) or ( state_cur(79) and to_stdl(funccall2 = 0) ) );
state_next(82) <= (not reset) and ( state_cur(83) or state_cur(16) );
state_next(83) <= (not reset) and ( ( state_cur(105) and not ( in25 ) ) );
state_next(84) <= (not reset) and ( state_cur(302) );
state_next(85) <= (not reset) and ( state_cur(282) );
state_next(86) <= (not reset) and ( state_cur(388) );
state_next(87) <= (not reset) and ( state_cur(122) );
state_next(88) <= (not reset) and ( state_cur(112) );
state_next(89) <= (not reset) and ( state_cur(283) );
state_next(90) <= (not reset) and ( state_cur(89) );
state_next(91) <= (not reset) and ( state_cur(315) );
state_next(92) <= (not reset) and ( state_cur(292) );
state_next(93) <= (not reset) and ( state_cur(99) );
state_next(94) <= (not reset) and ( state_cur(93) );
state_next(95) <= (not reset) and ( state_cur(306) );
state_next(96) <= (not reset) and ( state_cur(317) );
state_next(97) <= (not reset) and ( state_cur(295) );
state_next(98) <= (not reset) and ( state_cur(296) );
state_next(99) <= (not reset) and ( state_cur(290) );
state_next(100) <= (not reset) and ( state_cur(98) );
state_next(101) <= (not reset) and ( state_cur(299) );
state_next(102) <= (not reset) and ( state_cur(106) );
state_next(103) <= (not reset) and ( state_cur(102) );
state_next(104) <= (not reset) and ( state_cur(300) );
state_next(105) <= (not reset) and ( state_cur(224) or state_cur(107) );
state_next(106) <= (not reset) and ( state_cur(104) );
state_next(107) <= (not reset) and ( ( state_cur(121) and not ( in26 ) ) );
state_next(108) <= (not reset) and ( state_cur(307) );
state_next(109) <= (not reset) and ( state_cur(436) );
state_next(110) <= (not reset) and ( state_cur(172) );
state_next(111) <= (not reset) and ( state_cur(314) );
state_next(112) <= (not reset) and ( state_cur(199) );
state_next(113) <= (not reset) and ( state_cur(303) );
state_next(114) <= (not reset) and ( state_cur(111) );
state_next(115) <= (not reset) and ( state_cur(96) );
state_next(116) <= (not reset) and ( state_cur(380) );
state_next(117) <= (not reset) and ( state_cur(345) );
state_next(118) <= (not reset) and ( state_cur(347) );
state_next(119) <= (not reset) and ( state_cur(337) );
state_next(120) <= (not reset) and ( state_cur(180) );
state_next(121) <= (not reset) and ( state_cur(321) or state_cur(223) );
state_next(122) <= (not reset) and ( state_cur(183) );
state_next(123) <= (not reset) and ( ( state_cur(80) and to_stdl(funccall2 = 1) ) or ( state_cur(79) and to_stdl(funccall2 = 1) ) );
state_next(124) <= (not reset) and ( state_cur(354) );
state_next(125) <= (not reset) and ( ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and not ( in28 ) and in27 ) );
state_next(126) <= (not reset) and ( state_cur(129) or state_cur(128) );
state_next(127) <= (not reset) and ( state_cur(171) );
state_next(128) <= (not reset) and ( state_cur(245) );
state_next(129) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 1) ) );
state_next(130) <= (not reset) and ( state_cur(234) or ( state_cur(179) and not ( in40 ) ) or ( state_cur(148) and not ( in36 ) ) or state_cur(134) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and not ( in28 ) and not ( in27 ) ) or state_cur(125) );
state_next(131) <= (not reset) and ( state_cur(273) );
state_next(132) <= (not reset) and ( ( state_cur(157) and in37 ) );
state_next(133) <= (not reset) and ( ( state_cur(453) and to_stdl(funccall4 = 0) ) or ( state_cur(131) and to_stdl(funccall4 = 0) ) or ( state_cur(70) and to_stdl(funccall4 = 0) ) );
state_next(134) <= (not reset) and ( ( state_cur(423) and not ( in66 ) ) );
state_next(135) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 18) ) );
state_next(136) <= (not reset) and ( ( state_cur(207) and to_stdl(funccall1 = 6) ) );
state_next(137) <= (not reset) and ( ( state_cur(138) and in35 ) );
state_next(138) <= (not reset) and ( state_cur(161) or state_cur(139) );
state_next(139) <= (not reset) and ( state_cur(136) or state_cur(135) );
state_next(140) <= (not reset) and ( state_cur(21) );
state_next(141) <= (not reset) and ( state_cur(331) );
state_next(142) <= (not reset) and ( state_cur(332) );
state_next(143) <= (not reset) and ( state_cur(463) );
state_next(144) <= (not reset) and ( state_cur(9) );
state_next(145) <= (not reset) and ( state_cur(110) );
state_next(146) <= (not reset) and ( state_cur(465) );
state_next(147) <= (not reset) and ( state_cur(10) );
state_next(148) <= (not reset) and ( state_cur(214) or state_cur(152) );
state_next(149) <= (not reset) and ( state_cur(319) );
state_next(150) <= (not reset) and ( state_cur(119) );
state_next(151) <= (not reset) and ( state_cur(166) );
state_next(152) <= (not reset) and ( ( state_cur(207) and to_stdl(funccall1 = 5) ) );
state_next(153) <= (not reset) and ( state_cur(151) );
state_next(154) <= (not reset) and ( ( state_cur(160) and not ( in38 ) ) );
state_next(155) <= (not reset) and ( state_cur(341) );
state_next(156) <= (not reset) and ( state_cur(335) );
state_next(157) <= (not reset) and ( state_cur(133) );
state_next(158) <= (not reset) and ( state_cur(186) or ( state_cur(126) and in32 ) );
state_next(159) <= (not reset) and ( state_cur(167) );
state_next(160) <= (not reset) and ( state_cur(163) or state_cur(11) );
state_next(161) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 17) ) );
state_next(162) <= (not reset) and ( state_cur(156) );
state_next(163) <= (not reset) and ( ( state_cur(170) and not ( in39 ) ) );
state_next(164) <= (not reset) and ( ( state_cur(439) and in71 ) );
state_next(165) <= (not reset) and ( ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) ) );
state_next(166) <= (not reset) and ( state_cur(361) );
state_next(167) <= (not reset) and ( ( state_cur(24) and in5 ) );
state_next(168) <= (not reset) and ( ( state_cur(29) and in7 ) );
state_next(169) <= (not reset) and ( state_cur(190) or state_cur(187) );
state_next(170) <= (not reset) and ( state_cur(255) or state_cur(12) );
state_next(171) <= (not reset) and ( state_cur(87) );
state_next(172) <= (not reset) and ( state_cur(322) );
state_next(173) <= (not reset) and ( state_cur(168) );
state_next(174) <= (not reset) and ( ( state_cur(433) and in70 ) or ( state_cur(59) and not ( in16 ) ) );
state_next(175) <= (not reset) and ( state_cur(456) );
state_next(176) <= (not reset) and ( state_cur(348) );
state_next(177) <= (not reset) and ( state_cur(192) );
state_next(178) <= (not reset) and ( state_cur(384) );
state_next(179) <= (not reset) and ( state_cur(184) or state_cur(154) );
state_next(180) <= (not reset) and ( state_cur(88) );
state_next(181) <= (not reset) and ( state_cur(455) );
state_next(182) <= (not reset) and ( state_cur(336) );
state_next(183) <= (not reset) and ( state_cur(124) );
state_next(184) <= (not reset) and ( ( state_cur(207) and to_stdl(funccall1 = 4) ) );
state_next(185) <= (not reset) and ( state_cur(194) );
state_next(186) <= (not reset) and ( ( state_cur(338) and not ( in52 ) ) );
state_next(187) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 13) ) );
state_next(188) <= (not reset) and ( state_cur(426) );
state_next(189) <= (not reset) and ( state_cur(343) );
state_next(190) <= (not reset) and ( ( state_cur(212) and not ( in43 ) ) );
state_next(191) <= (not reset) and ( ( state_cur(252) and in49 ) );
state_next(192) <= (not reset) and ( state_cur(473) );
state_next(193) <= (not reset) and ( state_cur(362) );
state_next(194) <= (not reset) and ( state_cur(176) );
state_next(195) <= (not reset) and ( state_cur(360) );
state_next(196) <= (not reset) and ( state_cur(86) );
state_next(197) <= (not reset) and ( state_cur(55) );
state_next(198) <= (not reset) and ( state_cur(371) );
state_next(199) <= (not reset) and ( state_cur(118) );
state_next(200) <= (not reset) and ( state_cur(376) );
state_next(201) <= (not reset) and ( state_cur(204) );
state_next(202) <= (not reset) and ( state_cur(191) );
state_next(203) <= (not reset) and ( state_cur(359) );
state_next(204) <= (not reset) and ( state_cur(182) );
state_next(205) <= (not reset) and ( ( state_cur(210) and not ( in42 ) ) );
state_next(206) <= (not reset) and ( ( state_cur(210) and in42 ) or ( state_cur(209) and not ( in41 ) ) );
state_next(207) <= (not reset) and ( state_cur(365) );
state_next(208) <= (not reset) and ( state_cur(344) );
state_next(209) <= (not reset) and ( state_cur(213) or state_cur(205) );
state_next(210) <= (not reset) and ( ( state_cur(209) and in41 ) );
state_next(211) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 11) ) );
state_next(212) <= (not reset) and ( state_cur(229) or state_cur(206) );
state_next(213) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 12) ) );
state_next(214) <= (not reset) and ( state_cur(353) );
state_next(215) <= (not reset) and ( state_cur(62) );
state_next(216) <= (not reset) and ( state_cur(178) );
state_next(217) <= (not reset) and ( state_cur(389) );
state_next(218) <= (not reset) and ( state_cur(373) );
state_next(219) <= (not reset) and ( state_cur(340) );
state_next(220) <= (not reset) and ( state_cur(374) );
state_next(221) <= (not reset) and ( state_cur(346) );
state_next(222) <= (not reset) and ( state_cur(370) );
state_next(223) <= (not reset) and ( state_cur(367) );
state_next(224) <= (not reset) and ( state_cur(185) );
state_next(225) <= (not reset) and ( state_cur(226) );
state_next(226) <= (not reset) and ( state_cur(227) );
state_next(227) <= (not reset) and ( state_cur(218) );
state_next(228) <= (not reset) and ( state_cur(230) );
state_next(229) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 10) ) );
state_next(230) <= (not reset) and ( state_cur(225) );
state_next(231) <= (not reset) and ( state_cur(233) );
state_next(232) <= (not reset) and ( state_cur(280) );
state_next(233) <= (not reset) and ( state_cur(232) );
state_next(234) <= (not reset) and ( ( state_cur(241) and not ( in45 ) ) );
state_next(235) <= (not reset) and ( state_cur(164) );
state_next(236) <= (not reset) and ( state_cur(165) );
state_next(237) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 8) ) );
state_next(238) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 7) ) );
state_next(239) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 9) ) );
state_next(240) <= (not reset) and ( state_cur(20) );
state_next(241) <= (not reset) and ( state_cur(247) or state_cur(239) );
state_next(242) <= (not reset) and ( ( state_cur(241) and in45 ) );
state_next(243) <= (not reset) and ( ( state_cur(207) and to_stdl(funccall1 = 2) ) );
state_next(244) <= (not reset) and ( ( state_cur(207) and to_stdl(funccall1 = 1) ) );
state_next(245) <= (not reset) and ( ( state_cur(246) and in46 ) );
state_next(246) <= (not reset) and ( ( state_cur(251) and not ( in48 ) ) );
state_next(247) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 6) ) );
state_next(248) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 3) ) );
state_next(249) <= (not reset) and ( state_cur(250) or state_cur(248) );
state_next(250) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 2) ) );
state_next(251) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 4) ) );
state_next(252) <= (not reset) and ( state_cur(253) );
state_next(253) <= (not reset) and ( ( state_cur(453) and to_stdl(funccall4 = 1) ) or ( state_cur(131) and to_stdl(funccall4 = 1) ) or ( state_cur(70) and to_stdl(funccall4 = 1) ) );
state_next(254) <= (not reset) and ( ( state_cur(23) and in4 ) );
state_next(255) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 14) ) );
state_next(256) <= (not reset) and ( ( state_cur(460) and not ( in78 ) ) );
state_next(257) <= (not reset) and ( ( state_cur(399) and in56 ) );
state_next(258) <= (not reset) and ( ( state_cur(35) and to_stdl(funccall6 = 0) ) );
state_next(259) <= (not reset) and ( ( state_cur(35) and to_stdl(funccall6 = 1) ) );
state_next(260) <= (not reset) and ( ( state_cur(51) and to_stdl(funccall5 = 0) ) );
state_next(261) <= (not reset) and ( ( state_cur(51) and to_stdl(funccall5 = 1) ) );
state_next(262) <= (not reset) and ( state_cur(391) or ( state_cur(262) and not (in50) ) );
state_next(263) <= (not reset) and ( ( state_cur(392) and not ( in55 ) ) or ( state_cur(263) and not (in50) ) );
state_next(264) <= (not reset) and ( state_cur(386) or ( state_cur(264) and not (in50) ) );
state_next(265) <= (not reset) and ( ( state_cur(423) and in66 ) or state_cur(397) or ( state_cur(265) and not (in51) ) );
state_next(266) <= (not reset) and ( state_cur(85) );
state_next(267) <= (not reset) and ( state_cur(58) );
state_next(268) <= (not reset) and ( state_cur(267) );
state_next(269) <= (not reset) and ( state_cur(268) );
state_next(270) <= (not reset) and ( state_cur(61) );
state_next(271) <= (not reset) and ( ( state_cur(256) ) or ( state_cur(254) ) );
state_next(272) <= (not reset) and ( state_cur(198) );
state_next(273) <= (not reset) and ( ( state_cur(69) and not ( in19 ) ) );
state_next(274) <= (not reset) and ( state_cur(272) );
state_next(275) <= (not reset) and ( ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ) );
state_next(276) <= (not reset) and ( state_cur(275) );
state_next(277) <= (not reset) and ( state_cur(269) );
state_next(278) <= (not reset) and ( state_cur(277) );
state_next(279) <= (not reset) and ( state_cur(274) );
state_next(280) <= (not reset) and ( state_cur(279) );
state_next(281) <= (not reset) and ( state_cur(84) );
state_next(282) <= (not reset) and ( state_cur(281) );
state_next(283) <= (not reset) and ( state_cur(92) );
state_next(284) <= (not reset) and ( state_cur(90) );
state_next(285) <= (not reset) and ( state_cur(284) );
state_next(286) <= (not reset) and ( state_cur(285) );
state_next(287) <= (not reset) and ( state_cur(286) );
state_next(288) <= (not reset) and ( state_cur(287) );
state_next(289) <= (not reset) and ( state_cur(288) );
state_next(290) <= (not reset) and ( state_cur(289) );
state_next(291) <= (not reset) and ( state_cur(91) );
state_next(292) <= (not reset) and ( state_cur(291) );
state_next(293) <= (not reset) and ( state_cur(94) );
state_next(294) <= (not reset) and ( state_cur(293) );
state_next(295) <= (not reset) and ( state_cur(294) );
state_next(296) <= (not reset) and ( state_cur(97) );
state_next(297) <= (not reset) and ( state_cur(100) );
state_next(298) <= (not reset) and ( state_cur(297) );
state_next(299) <= (not reset) and ( state_cur(298) );
state_next(300) <= (not reset) and ( state_cur(101) );
state_next(301) <= (not reset) and ( state_cur(103) );
state_next(302) <= (not reset) and ( state_cur(301) );
state_next(303) <= (not reset) and ( state_cur(357) );
state_next(304) <= (not reset) and ( state_cur(434) );
state_next(305) <= (not reset) and ( state_cur(425) );
state_next(306) <= (not reset) and ( state_cur(305) );
state_next(307) <= (not reset) and ( state_cur(304) );
state_next(308) <= (not reset) and ( state_cur(108) );
state_next(309) <= (not reset) and ( state_cur(308) );
state_next(310) <= (not reset) and ( state_cur(95) );
state_next(311) <= (not reset) and ( state_cur(310) );
state_next(312) <= (not reset) and ( state_cur(311) );
state_next(313) <= (not reset) and ( state_cur(309) );
state_next(314) <= (not reset) and ( state_cur(313) );
state_next(315) <= (not reset) and ( state_cur(114) );
state_next(316) <= (not reset) and ( state_cur(318) );
state_next(317) <= (not reset) and ( state_cur(312) );
state_next(318) <= (not reset) and ( state_cur(329) );
state_next(319) <= (not reset) and ( state_cur(316) );
state_next(320) <= (not reset) and ( state_cur(326) );
state_next(321) <= (not reset) and ( state_cur(115) );
state_next(322) <= (not reset) and ( state_cur(320) );
state_next(323) <= (not reset) and ( state_cur(330) );
state_next(324) <= (not reset) and ( ( state_cur(78) and in23 ) or ( state_cur(73) and not ( in20 ) ) or ( state_cur(72) ) );
state_next(325) <= (not reset) and ( state_cur(323) );
state_next(326) <= (not reset) and ( state_cur(325) );
state_next(327) <= (not reset) and ( state_cur(155) );
state_next(328) <= (not reset) and ( state_cur(145) );
state_next(329) <= (not reset) and ( state_cur(141) );
state_next(330) <= (not reset) and ( state_cur(142) );
state_next(331) <= (not reset) and ( state_cur(113) );
state_next(332) <= (not reset) and ( state_cur(438) );
state_next(333) <= (not reset) and ( state_cur(158) );
state_next(334) <= (not reset) and ( state_cur(197) );
state_next(335) <= (not reset) and ( state_cur(189) );
state_next(336) <= (not reset) and ( state_cur(203) );
state_next(337) <= (not reset) and ( state_cur(358) );
state_next(338) <= (not reset) and ( state_cur(169) );
state_next(339) <= (not reset) and ( state_cur(349) );
state_next(340) <= (not reset) and ( state_cur(177) );
state_next(341) <= (not reset) and ( state_cur(339) );
state_next(342) <= (not reset) and ( state_cur(382) );
state_next(343) <= (not reset) and ( state_cur(150) );
state_next(344) <= (not reset) and ( state_cur(442) );
state_next(345) <= (not reset) and ( state_cur(400) );
state_next(346) <= (not reset) and ( state_cur(200) );
state_next(347) <= (not reset) and ( state_cur(162) );
state_next(348) <= (not reset) and ( state_cur(193) );
state_next(349) <= (not reset) and ( state_cur(219) );
state_next(350) <= (not reset) and ( state_cur(37) );
state_next(351) <= (not reset) and ( state_cur(404) );
state_next(352) <= (not reset) and ( state_cur(1) );
state_next(353) <= (not reset) and ( ( state_cur(138) and not ( in35 ) ) );
state_next(354) <= (not reset) and ( ( state_cur(105) and in25 ) );
state_next(355) <= (not reset) and ( state_cur(175) );
state_next(356) <= (not reset) and ( state_cur(4) );
state_next(357) <= (not reset) and ( ( state_cur(82) and not ( in24 ) ) );
state_next(358) <= (not reset) and ( state_cur(117) );
state_next(359) <= (not reset) and ( state_cur(352) );
state_next(360) <= (not reset) and ( state_cur(368) );
state_next(361) <= (not reset) and ( state_cur(33) );
state_next(362) <= (not reset) and ( state_cur(356) );
state_next(363) <= (not reset) and ( ( state_cur(451) and in74 ) );
state_next(364) <= (not reset) and ( state_cur(228) );
state_next(365) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 5) ) or ( state_cur(244) ) or ( state_cur(137) and in34 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and in28 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and in29 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and in30 ) or ( state_cur(126) and not ( in32 ) and in31 ) );
state_next(366) <= (not reset) and ( state_cur(441) );
state_next(367) <= (not reset) and ( state_cur(201) );
state_next(368) <= (not reset) and ( state_cur(221) );
state_next(369) <= (not reset) and ( state_cur(231) );
state_next(370) <= (not reset) and ( state_cur(394) );
state_next(371) <= (not reset) and ( ( state_cur(2) and not ( in0 ) ) );
state_next(372) <= (not reset) and ( state_cur(375) );
state_next(373) <= (not reset) and ( state_cur(215) );
state_next(374) <= (not reset) and ( state_cur(217) );
state_next(375) <= (not reset) and ( state_cur(355) );
state_next(376) <= (not reset) and ( state_cur(381) );
state_next(377) <= (not reset) and ( state_cur(127) );
state_next(378) <= (not reset) and ( ( state_cur(428) and in69 ) or ( state_cur(43) and not ( in11 ) ) );
state_next(379) <= (not reset) and ( ( state_cur(47) and not ( in13 ) ) );
state_next(380) <= (not reset) and ( state_cur(351) );
state_next(381) <= (not reset) and ( state_cur(216) );
state_next(382) <= (not reset) and ( state_cur(195) );
state_next(383) <= (not reset) and ( ( state_cur(469) ) or ( state_cur(462) ) or ( state_cur(461) ) or ( state_cur(445) ) or ( state_cur(257) ) );
state_next(384) <= (not reset) and ( state_cur(196) );
state_next(385) <= (not reset) and ( state_cur(120) );
state_next(386) <= (not reset) and ( ( state_cur(263) and not ( not (in50) ) ) );
state_next(387) <= (not reset) and ( state_cur(342) );
state_next(388) <= (not reset) and ( state_cur(60) );
state_next(389) <= (not reset) and ( state_cur(235) );
state_next(390) <= (not reset) and ( ( state_cur(262) and not ( not (in50) ) ) );
state_next(391) <= (not reset) and ( state_cur(393) or ( state_cur(390) and in54 ) );
state_next(392) <= (not reset) and ( ( state_cur(390) and not ( in54 ) ) );
state_next(393) <= (not reset) and ( state_cur(395) or ( state_cur(392) and in55 ) );
state_next(394) <= (not reset) and ( state_cur(364) );
state_next(395) <= (not reset) and ( ( state_cur(416) and not ( in62 ) ) or ( state_cur(409) and not ( in59 ) ) );
state_next(396) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 0) ) or ( state_cur(338) and in52 ) or ( state_cur(251) and in48 ) or ( state_cur(249) and not ( in47 ) ) or ( state_cur(249) and in47 ) or ( state_cur(246) and not ( in46 ) ) or ( state_cur(243) ) or ( state_cur(242) ) or ( state_cur(238) ) or ( state_cur(237) ) or ( state_cur(212) and in43 ) or ( state_cur(211) ) or ( state_cur(207) and to_stdl(funccall1 = 0) ) or ( state_cur(207) and to_stdl(funccall1 = 3) ) or ( state_cur(179) and in40 ) or ( state_cur(170) and in39 ) or ( state_cur(160) and in38 ) or ( state_cur(148) and in36 ) or ( state_cur(137) and not ( in34 ) ) or ( state_cur(130) and not ( in33 ) ) or ( state_cur(130) and in33 ) );
state_next(397) <= (not reset) and ( ( state_cur(457) and not ( not (in77) ) ) or ( state_cur(264) and not ( not (in50) ) ) );
state_next(398) <= (not reset) and ( ( state_cur(399) and not ( in56 ) ) );
state_next(399) <= (not reset) and ( state_cur(401) or state_cur(276) );
state_next(400) <= (not reset) and ( state_cur(109) );
state_next(401) <= (not reset) and ( ( state_cur(403) and not ( in57 ) ) );
state_next(402) <= (not reset) and ( ( state_cur(439) and not ( in71 ) and to_stdl(funccall8 = 1) ) );
state_next(403) <= (not reset) and ( state_cur(405) or state_cur(402) );
state_next(404) <= (not reset) and ( state_cur(387) );
state_next(405) <= (not reset) and ( ( state_cur(278) and to_stdl(funccall9 = 3) ) );
state_next(406) <= (not reset) and ( ( state_cur(278) and to_stdl(funccall9 = 1) ) );
state_next(407) <= (not reset) and ( state_cur(408) or state_cur(406) );
state_next(408) <= (not reset) and ( ( state_cur(409) and in59 ) );
state_next(409) <= (not reset) and ( ( state_cur(417) and not ( in63 ) ) or state_cur(398) );
state_next(410) <= (not reset) and ( ( state_cur(411) and not ( in60 ) ) );
state_next(411) <= (not reset) and ( state_cur(412) or state_cur(236) );
state_next(412) <= (not reset) and ( ( state_cur(439) and not ( in71 ) and to_stdl(funccall8 = 0) ) );
state_next(413) <= (not reset) and ( ( state_cur(278) and to_stdl(funccall9 = 0) ) );
state_next(414) <= (not reset) and ( state_cur(415) or state_cur(413) );
state_next(415) <= (not reset) and ( ( state_cur(416) and in62 ) );
state_next(416) <= (not reset) and ( ( state_cur(417) and in63 ) or state_cur(410) );
state_next(417) <= (not reset) and ( ( state_cur(419) and not ( in64 ) ) );
state_next(418) <= (not reset) and ( ( state_cur(414) and in61 ) );
state_next(419) <= (not reset) and ( state_cur(421) or state_cur(420) );
state_next(420) <= (not reset) and ( ( state_cur(419) and in64 ) );
state_next(421) <= (not reset) and ( ( state_cur(422) and not ( in65 ) ) );
state_next(422) <= (not reset) and ( state_cur(261) or state_cur(0) );
state_next(423) <= (not reset) and ( ( state_cur(265) and not ( not (in51) ) ) );
state_next(424) <= (not reset) and ( state_cur(435) );
state_next(425) <= (not reset) and ( state_cur(146) );
state_next(426) <= (not reset) and ( ( state_cur(39) and not ( in9 ) ) );
state_next(427) <= (not reset) and ( state_cur(429) );
state_next(428) <= (not reset) and ( state_cur(378) );
state_next(429) <= (not reset) and ( state_cur(431) or ( state_cur(428) and not ( in69 ) ) or ( state_cur(427) and in68 ) );
state_next(430) <= (not reset) and ( state_cur(41) );
state_next(431) <= (not reset) and ( state_cur(379) );
state_next(432) <= (not reset) and ( state_cur(271) );
state_next(433) <= (not reset) and ( state_cur(174) );
state_next(434) <= (not reset) and ( state_cur(143) );
state_next(435) <= (not reset) and ( state_cur(173) or state_cur(27) );
state_next(436) <= (not reset) and ( state_cur(181) );
state_next(437) <= (not reset) and ( state_cur(443) or ( state_cur(157) and not ( in37 ) ) );
state_next(438) <= (not reset) and ( state_cur(334) );
state_next(439) <= (not reset) and ( state_cur(440) or state_cur(220) );
state_next(440) <= (not reset) and ( ( state_cur(472) ) or ( state_cur(468) ) );
state_next(441) <= (not reset) and ( ( state_cur(433) and not ( in70 ) ) or ( state_cur(366) and in53 ) or state_cur(36) );
state_next(442) <= (not reset) and ( state_cur(153) );
state_next(443) <= (not reset) and ( state_cur(132) );
state_next(444) <= (not reset) and ( ( state_cur(66) and not ( in18 ) ) );
state_next(445) <= (not reset) and ( ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 1) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 1) ) );
state_next(446) <= (not reset) and ( ( state_cur(449) and not ( in73 ) ) or ( state_cur(448) and not ( in72 ) ) );
state_next(447) <= (not reset) and ( state_cur(450) );
state_next(448) <= (not reset) and ( ( state_cur(449) and in73 ) );
state_next(449) <= (not reset) and ( state_cur(447) or state_cur(363) );
state_next(450) <= (not reset) and ( ( state_cur(448) and in72 ) );
state_next(451) <= (not reset) and ( ( state_cur(452) and in75 ) );
state_next(452) <= (not reset) and ( state_cur(446) or state_cur(383) );
state_next(453) <= (not reset) and ( state_cur(123) );
state_next(454) <= (not reset) and ( state_cur(324) );
state_next(455) <= (not reset) and ( state_cur(222) );
state_next(456) <= (not reset) and ( state_cur(149) );
state_next(457) <= reset or ( ( state_cur(457) and not (in77) ) );
state_next(458) <= (not reset) and ( ( state_cur(407) and in58 ) );
state_next(459) <= (not reset) and ( ( state_cur(424) and in67 ) );
state_next(460) <= (not reset) and ( state_cur(459) );
state_next(461) <= (not reset) and ( ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 2) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 2) ) );
state_next(462) <= (not reset) and ( ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 3) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 3) ) );
state_next(463) <= (not reset) and ( state_cur(464) );
state_next(464) <= (not reset) and ( state_cur(144) );
state_next(465) <= (not reset) and ( state_cur(467) );
state_next(466) <= (not reset) and ( state_cur(437) );
state_next(467) <= (not reset) and ( state_cur(147) );
state_next(468) <= (not reset) and ( ( state_cur(414) and not ( in61 ) ) );
state_next(469) <= (not reset) and ( ( state_cur(411) and in60 ) );
state_next(470) <= (not reset) and ( ( state_cur(407) and not ( in58 ) ) );
state_next(471) <= (not reset) and ( ( state_cur(278) and to_stdl(funccall9 = 2) ) );
state_next(472) <= (not reset) and ( ( state_cur(403) and in57 ) );
state_next(473) <= (not reset) and ( state_cur(116) );
-- Assignment of buffers for buffered outputs
out1057_bufn <= state_cur(127) or state_cur(425);
out59_bufn <= state_cur(305) or state_cur(377);
out447_bufn <= state_cur(382) or state_cur(111);
out157_bufn <= state_cur(28) or state_cur(26) or ( state_cur(25) and not ( in6 ) );
out450_bufn <= state_cur(194) or state_cur(96);
out1012_bufn <= state_cur(221) or state_cur(291);
out1072_bufn <= state_cur(351) or state_cur(308);
out999_bufn <= state_cur(196) or state_cur(286);
out437_bufn <= state_cur(94) or state_cur(172);
out415_bufn <= state_cur(330) or state_cur(98);
out426_bufn <= state_cur(321) or state_cur(223) or state_cur(224) or state_cur(107);
out375_bufn <= state_cur(360) or state_cur(315);
out704_bufn <= state_cur(356) or state_cur(193) or state_cur(311) or state_cur(310) or state_cur(95) or state_cur(362);
out973_bufn <= state_cur(275) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) );
out11_bufn <= state_cur(222) or state_cur(153) or state_cur(181) or state_cur(109) or state_cur(364) or state_cur(120) or state_cur(215) or state_cur(394) or state_cur(231) or state_cur(201) or state_cur(228) or state_cur(33) or state_cur(352) or state_cur(117) or state_cur(1) or state_cur(162) or state_cur(400) or state_cur(442) or state_cur(150) or state_cur(358) or state_cur(203) or state_cur(189) or state_cur(279) or state_cur(274) or state_cur(272) or state_cur(198) or state_cur(232) or state_cur(280) or state_cur(233) or state_cur(225) or state_cur(230) or state_cur(218) or state_cur(227) or state_cur(226) or state_cur(367) or state_cur(370) or state_cur(373) or state_cur(62) or state_cur(344) or state_cur(182) or state_cur(359) or state_cur(204) or state_cur(118) or state_cur(371) or state_cur(343) or state_cur(336) or state_cur(455) or state_cur(88) or state_cur(361) or state_cur(156) or state_cur(335) or state_cur(151) or state_cur(166) or state_cur(119) or state_cur(180) or state_cur(337) or state_cur(347) or state_cur(345) or state_cur(199) or state_cur(436) or state_cur(112) or state_cur(208) or state_cur(369) or state_cur(385);
out549_bufn <= state_cur(87) or state_cur(465);
out453_bufn <= state_cur(304) or state_cur(380);
out1231_bufn <= state_cur(261) or state_cur(0) or state_cur(421) or state_cur(420) or state_cur(415) or state_cur(413) or state_cur(412) or state_cur(236) or state_cur(408) or state_cur(406) or state_cur(405) or state_cur(402) or state_cur(401) or state_cur(276);
out87_bufn <= state_cur(147) or state_cur(467) or state_cur(312) or state_cur(10) or state_cur(465) or state_cur(21) or state_cur(96) or state_cur(317) or state_cur(140);
out401_bufn <= state_cur(4) or state_cur(306);
out990_bufn <= state_cur(316) or state_cur(281);
out378_bufn <= state_cur(376) or state_cur(292);
out1302_bufn <= state_cur(132) or state_cur(443) or ( state_cur(157) and not ( in37 ) );
out27_bufn <= ( state_cur(448) and in72 ) or ( state_cur(433) and not ( in70 ) ) or ( state_cur(366) and in53 ) or state_cur(36) or state_cur(431) or ( state_cur(428) and not ( in69 ) ) or ( state_cur(427) and in68 ) or state_cur(193) or state_cur(311) or state_cur(310) or state_cur(95) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ) or state_cur(362) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) ) or state_cur(186) or ( state_cur(126) and in32 ) or state_cur(136) or state_cur(135) or ( state_cur(64) and in17 ) or ( state_cur(45) and in12 ) or ( state_cur(77) and to_stdl(funccall3 = 1) ) or ( state_cur(75) and to_stdl(funccall3 = 1) ) or ( state_cur(77) and to_stdl(funccall3 = 3) ) or ( state_cur(75) and to_stdl(funccall3 = 3) ) or ( state_cur(2) and in0 );
out569_bufn <= ( state_cur(138) and not ( in35 ) ) or ( state_cur(207) and to_stdl(funccall1 = 5) );
out1030_bufn <= state_cur(438) or state_cur(101);
out537_bufn <= state_cur(293) or state_cur(110);
out77_bufn <= state_cur(144) or state_cur(464) or state_cur(143) or state_cur(155) or state_cur(114) or state_cur(313) or state_cur(309) or state_cur(308) or state_cur(108) or state_cur(304) or state_cur(434) or state_cur(301) or state_cur(103) or state_cur(101) or state_cur(298) or state_cur(297) or state_cur(100) or state_cur(97) or state_cur(294) or state_cur(293) or state_cur(94) or state_cur(291) or state_cur(91) or state_cur(289) or state_cur(288) or state_cur(287) or state_cur(286) or state_cur(285) or state_cur(284) or state_cur(90) or state_cur(92) or state_cur(281) or state_cur(84) or state_cur(277) or state_cur(269) or state_cur(268) or state_cur(267) or state_cur(58) or state_cur(85) or state_cur(9) or state_cur(463) or state_cur(111) or state_cur(314) or state_cur(307) or state_cur(104) or state_cur(300) or state_cur(102) or state_cur(106) or state_cur(299) or state_cur(98) or state_cur(290) or state_cur(296) or state_cur(295) or state_cur(93) or state_cur(99) or state_cur(292) or state_cur(315) or state_cur(89) or state_cur(283) or state_cur(282) or state_cur(302) or state_cur(56) or state_cur(266) or state_cur(327);
out1318_bufn <= ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 3) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 3) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 1) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 1) );
out533_bufn <= state_cur(219) or state_cur(9);
out32_bufn <= state_cur(305) or state_cur(176) or state_cur(317) or state_cur(377);
out1027_bufn <= state_cur(142) or state_cur(298);
out599_bufn <= ( state_cur(35) and to_stdl(funccall6 = 0) ) or state_cur(186) or ( state_cur(126) and in32 );
out668_bufn <= state_cur(84) or state_cur(456);
out568_bufn <= state_cur(261) or state_cur(0) or state_cur(421) or state_cur(420) or state_cur(415) or state_cur(413) or state_cur(412) or state_cur(236) or state_cur(401) or state_cur(276) or ( state_cur(207) and to_stdl(funccall1 = 4) ) or ( state_cur(207) and to_stdl(funccall1 = 5) );
out225_bufn <= ( state_cur(39) and not ( in9 ) ) or ( state_cur(53) and not ( in14 ) );
out700_bufn <= state_cur(143) or state_cur(473);
out638_bufn <= ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) );
out670_bufn <= state_cur(312) or state_cur(348);
out433_bufn <= state_cur(116) or state_cur(307);
out896_bufn <= ( state_cur(411) and in60 ) or ( state_cur(399) and in56 );
out575_bufn <= state_cur(163) or state_cur(11) or ( state_cur(160) and not ( in38 ) );
out428_bufn <= state_cur(197) or state_cur(104);
out72_bufn <= state_cur(144) or state_cur(464) or state_cur(143) or state_cur(155) or state_cur(114) or state_cur(313) or state_cur(309) or state_cur(308) or state_cur(108) or state_cur(304) or state_cur(434) or state_cur(301) or state_cur(103) or state_cur(101) or state_cur(298) or state_cur(297) or state_cur(100) or state_cur(97) or state_cur(294) or state_cur(293) or state_cur(94) or state_cur(291) or state_cur(91) or state_cur(289) or state_cur(288) or state_cur(287) or state_cur(286) or state_cur(285) or state_cur(284) or state_cur(90) or state_cur(92) or state_cur(281) or state_cur(84) or state_cur(277) or state_cur(269) or state_cur(268) or state_cur(267) or state_cur(58) or state_cur(85) or state_cur(9) or state_cur(463) or state_cur(111) or state_cur(314) or state_cur(307) or state_cur(104) or state_cur(300) or state_cur(102) or state_cur(106) or state_cur(299) or state_cur(98) or state_cur(290) or state_cur(296) or state_cur(295) or state_cur(93) or state_cur(99) or state_cur(292) or state_cur(315) or state_cur(89) or state_cur(283) or state_cur(282) or state_cur(302) or state_cur(56) or state_cur(266) or ( state_cur(82) and in24 ) or state_cur(327);
out404_bufn <= state_cur(115) or state_cur(312) or state_cur(185) or state_cur(176) or state_cur(194) or state_cur(348) or state_cur(96) or state_cur(317);
out98_bufn <= ( state_cur(396) and to_stdl(funccall0 = 15) ) or ( state_cur(396) and to_stdl(funccall0 = 16) );
out67_bufn <= ( state_cur(424) and in67 ) or ( state_cur(252) and not ( in49 ) ) or state_cur(202);
out635_bufn <= state_cur(165) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) );
out381_bufn <= state_cur(145) or state_cur(99);
out222_bufn <= ( state_cur(433) and not ( in70 ) ) or ( state_cur(366) and in53 ) or state_cur(36) or state_cur(41) or ( state_cur(64) and in17 ) or ( state_cur(53) and not ( in14 ) );
out339_bufn <= state_cur(273) or ( state_cur(76) and in22 ) or ( state_cur(76) and not ( in22 ) );
out268_bufn <= state_cur(41) or ( state_cur(53) and in14 );
out419_bufn <= state_cur(375) or state_cur(106);
out559_bufn <= ( state_cur(138) and not ( in35 ) ) or state_cur(353) or state_cur(214) or state_cur(152);
out1002_bufn <= state_cur(60) or state_cur(287);
out1006_bufn <= state_cur(37) or state_cur(289);
out276_bufn <= state_cur(318) or state_cur(266);
out205_bufn <= state_cur(116) or state_cur(149) or state_cur(334) or state_cur(387) or state_cur(60) or state_cur(342) or state_cur(196) or state_cur(195) or state_cur(216) or state_cur(351) or state_cur(381) or state_cur(355) or state_cur(375) or state_cur(221) or state_cur(368) or ( state_cur(82) and not ( in24 ) ) or state_cur(175) or state_cur(404) or state_cur(37) or state_cur(219) or state_cur(200) or state_cur(382) or state_cur(339) or state_cur(177) or state_cur(349) or state_cur(197) or state_cur(438) or state_cur(113) or state_cur(142) or state_cur(141) or state_cur(145) or state_cur(325) or state_cur(323) or state_cur(330) or state_cur(320) or state_cur(326) or state_cur(316) or state_cur(329) or state_cur(318) or state_cur(357) or state_cur(346) or state_cur(340) or state_cur(178) or state_cur(376) or state_cur(55) or state_cur(86) or state_cur(360) or state_cur(473) or state_cur(384) or state_cur(192) or state_cur(456) or state_cur(322) or state_cur(341) or state_cur(319) or state_cur(110) or state_cur(332) or state_cur(331) or state_cur(380) or state_cur(303) or state_cur(172) or state_cur(388) or state_cur(350) or state_cur(372) or state_cur(328);
out943_bufn <= state_cur(329) or state_cur(85);
out1080_bufn <= state_cur(193) or state_cur(311);
out408_bufn <= state_cur(322) or state_cur(295);
out252_bufn <= state_cur(431) or ( state_cur(428) and not ( in69 ) ) or ( state_cur(427) and in68 ) or ( state_cur(39) and not ( in9 ) ) or state_cur(426) or ( state_cur(45) and in12 );
out71_bufn <= state_cur(341) or state_cur(327);
out672_bufn <= state_cur(434) or state_cur(192);
out357_bufn <= state_cur(319) or state_cur(282);
out441_bufn <= state_cur(195) or state_cur(314);
out1084_bufn <= state_cur(387) or state_cur(313);
out144_bufn <= ( state_cur(78) and in23 ) or ( state_cur(73) and not ( in20 ) ) or ( state_cur(72) ) or ( state_cur(454) and in76 );
out574_bufn <= state_cur(184) or state_cur(154) or ( state_cur(170) and not ( in39 ) ) or ( state_cur(160) and not ( in38 ) );
out210_bufn <= ( state_cur(39) and not ( in9 ) ) or ( state_cur(40) and in10 );
out128_bufn <= state_cur(306) or ( state_cur(82) and in24 );
out360_bufn <= state_cur(288) or state_cur(388);
out948_bufn <= state_cur(141) or state_cur(58);
out506_bufn <= ( state_cur(453) and to_stdl(funccall4 = 1) ) or ( state_cur(131) and to_stdl(funccall4 = 1) ) or ( state_cur(70) and to_stdl(funccall4 = 1) ) or ( state_cur(453) and to_stdl(funccall4 = 0) ) or ( state_cur(131) and to_stdl(funccall4 = 0) ) or ( state_cur(70) and to_stdl(funccall4 = 0) );
out207_bufn <= state_cur(93) or state_cur(328);
out1083_bufn <= state_cur(342) or state_cur(309);
out491_bufn <= state_cur(146) or state_cur(171);
out4_bufn <= state_cur(147) or state_cur(467) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 3) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 3) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 2) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 2) ) or state_cur(446) or state_cur(383) or state_cur(447) or state_cur(363) or state_cur(450) or ( state_cur(449) and not ( in73 ) ) or ( state_cur(448) and not ( in72 ) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 1) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 1) ) or state_cur(132) or ( state_cur(433) and not ( in70 ) ) or ( state_cur(366) and in53 ) or state_cur(36) or state_cur(41) or state_cur(431) or ( state_cur(428) and not ( in69 ) ) or ( state_cur(427) and in68 ) or state_cur(146) or ( state_cur(265) and not ( not (in51) ) ) or ( state_cur(419) and in64 ) or ( state_cur(278) and to_stdl(funccall9 = 0) ) or ( state_cur(411) and not ( in60 ) ) or ( state_cur(278) and to_stdl(funccall9 = 1) ) or ( state_cur(439) and not ( in71 ) and to_stdl(funccall8 = 1) ) or ( state_cur(399) and not ( in56 ) ) or ( state_cur(396) and to_stdl(funccall0 = 0) ) or ( state_cur(338) and in52 ) or ( state_cur(251) and in48 ) or ( state_cur(249) and not ( in47 ) ) or ( state_cur(249) and in47 ) or ( state_cur(246) and not ( in46 ) ) or ( state_cur(243) ) or ( state_cur(242) ) or ( state_cur(238) ) or ( state_cur(237) ) or ( state_cur(212) and in43 ) or ( state_cur(211) ) or ( state_cur(207) and to_stdl(funccall1 = 0) ) or ( state_cur(207) and to_stdl(funccall1 = 3) ) or ( state_cur(179) and in40 ) or ( state_cur(170) and in39 ) or ( state_cur(160) and in38 ) or ( state_cur(148) and in36 ) or ( state_cur(137) and not ( in34 ) ) or ( state_cur(130) and not ( in33 ) ) or ( state_cur(130) and in33 ) or ( state_cur(390) and not ( in54 ) ) or ( state_cur(262) and not ( not (in50) ) ) or ( state_cur(428) and in69 ) or ( state_cur(43) and not ( in11 ) ) or ( state_cur(2) and not ( in0 ) ) or ( state_cur(396) and to_stdl(funccall0 = 5) ) or ( state_cur(244) ) or ( state_cur(137) and in34 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and in28 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and in29 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and in30 ) or ( state_cur(126) and not ( in32 ) and in31 ) or ( state_cur(105) and in25 ) or ( state_cur(78) and in23 ) or ( state_cur(73) and not ( in20 ) ) or ( state_cur(72) ) or state_cur(312) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ) or ( state_cur(396) and to_stdl(funccall0 = 9) ) or state_cur(164) or state_cur(374) or state_cur(365) or ( state_cur(210) and in42 ) or ( state_cur(209) and not ( in41 ) ) or ( state_cur(210) and not ( in42 ) ) or state_cur(191) or state_cur(176) or state_cur(426) or state_cur(194) or state_cur(124) or state_cur(348) or ( state_cur(433) and in70 ) or ( state_cur(59) and not ( in16 ) ) or state_cur(87) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) ) or state_cur(10) or state_cur(465) or state_cur(21) or state_cur(136) or state_cur(135) or state_cur(171) or state_cur(354) or state_cur(183) or state_cur(96) or state_cur(317) or state_cur(122) or ( state_cur(80) and to_stdl(funccall2 = 2) ) or ( state_cur(79) and to_stdl(funccall2 = 2) ) or ( state_cur(64) and in17 ) or ( state_cur(64) and not ( in17 ) ) or ( state_cur(54) and not ( in15 ) ) or state_cur(430) or state_cur(52) or ( state_cur(45) and in12 ) or ( state_cur(45) and not ( in12 ) ) or ( state_cur(40) and not ( in10 ) ) or state_cur(188) or state_cur(38) or ( state_cur(121) and in26 ) or ( state_cur(454) and in76 ) or ( state_cur(17) and in3 ) or ( state_cur(82) and in24 ) or ( state_cur(396) and to_stdl(funccall0 = 15) ) or ( state_cur(396) and to_stdl(funccall0 = 16) ) or state_cur(140) or ( state_cur(252) and not ( in49 ) ) or state_cur(202) or ( state_cur(6) and in1 ) or ( state_cur(2) and in0 ) or ( state_cur(422) and in65 );
out784_bufn <= state_cur(115) or state_cur(185);
out3_bufn <= ( state_cur(419) and in64 ) or ( state_cur(278) and to_stdl(funccall9 = 0) ) or ( state_cur(278) and to_stdl(funccall9 = 1) ) or ( state_cur(439) and not ( in71 ) and to_stdl(funccall8 = 1) ) or ( state_cur(422) and in65 );
out746_bufn <= state_cur(247) or state_cur(239) or state_cur(213) or state_cur(205);
out528_bufn <= state_cur(297) or state_cur(332);
out372_bufn <= state_cur(381) or state_cur(89);
out418_bufn <= state_cur(334) or state_cur(299);
out708_bufn <= state_cur(285) or state_cur(86);
out706_bufn <= state_cur(193) or state_cur(362);
out445_bufn <= state_cur(267) or state_cur(303);
out1021_bufn <= state_cur(323) or state_cur(100);
out405_bufn <= state_cur(193) or state_cur(115) or state_cur(312) or state_cur(311) or state_cur(310) or state_cur(95) or state_cur(185) or state_cur(176) or state_cur(362) or state_cur(194) or state_cur(348) or state_cur(96) or state_cur(317);
out764_bufn <= state_cur(284) or state_cur(178);
out581_bufn <= state_cur(253) or state_cur(133);
out776_bufn <= state_cur(91) or state_cur(346);
out213_bufn <= state_cur(184) or state_cur(154) or state_cur(255) or state_cur(12) or state_cur(68) or state_cur(63) or state_cur(57) or state_cur(50) or state_cur(49) or state_cur(44) or state_cur(42) or state_cur(34);
out674_bufn <= state_cur(90) or state_cur(384);
out1326_bufn <= state_cur(447) or state_cur(363) or ( state_cur(449) and in73 );
out334_bufn <= ( state_cur(270) ) or ( state_cur(30) and in8 ) or ( state_cur(25) and in6 ) or ( state_cur(15) ) or ( state_cur(76) and in22 ) or ( state_cur(76) and not ( in22 ) ) or ( state_cur(74) and in21 );
out843_bufn <= state_cur(275) or state_cur(165);
out175_bufn <= state_cur(32) or state_cur(31) or ( state_cur(30) and not ( in8 ) );
out1036_bufn <= state_cur(355) or state_cur(301);
out1015_bufn <= state_cur(320) or state_cur(294);
out236_bufn <= state_cur(378) or state_cur(429) or ( state_cur(427) and not ( in68 ) );
out395_bufn <= ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ) or state_cur(164) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) ) or state_cur(306);
out1340_bufn <= state_cur(446) or state_cur(383) or ( state_cur(452) and in75 );
out993_bufn <= state_cur(200) or state_cur(92);
out356_bufn <= state_cur(149) or state_cur(302);
out273_bufn <= state_cur(102) or state_cur(372);
out403_bufn <= state_cur(176) or state_cur(317);
out286_bufn <= state_cur(290) or state_cur(350);
out364_bufn <= state_cur(176) or state_cur(194) or state_cur(124) or state_cur(348) or state_cur(87) or state_cur(354) or state_cur(183) or state_cur(122);
out697_bufn <= state_cur(253) or state_cur(191) or ( state_cur(252) and in49 );
out283_bufn <= state_cur(174) or state_cur(441) or ( state_cur(366) and not ( in53 ) );
out282_bufn <= state_cur(331) or state_cur(56);
out1319_bufn <= ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 3) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 3) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 2) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 2) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 1) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 1) );
out409_bufn <= state_cur(326) or state_cur(296);
out1092_bufn <= state_cur(339) or state_cur(155);
out1075_bufn <= state_cur(356) or state_cur(95);
out925_bufn <= ( state_cur(51) and to_stdl(funccall5 = 0) ) or ( state_cur(35) and to_stdl(funccall6 = 1) );
out78_bufn <= state_cur(144) or state_cur(464) or state_cur(143) or state_cur(235) or state_cur(155) or state_cur(114) or state_cur(313) or state_cur(309) or state_cur(308) or state_cur(108) or state_cur(304) or state_cur(434) or state_cur(301) or state_cur(103) or state_cur(101) or state_cur(298) or state_cur(297) or state_cur(100) or state_cur(97) or state_cur(294) or state_cur(293) or state_cur(94) or state_cur(291) or state_cur(91) or state_cur(289) or state_cur(288) or state_cur(287) or state_cur(286) or state_cur(285) or state_cur(284) or state_cur(90) or state_cur(92) or state_cur(281) or state_cur(84) or state_cur(277) or state_cur(269) or state_cur(268) or state_cur(267) or state_cur(58) or state_cur(85) or state_cur(9) or state_cur(463) or state_cur(111) or state_cur(314) or state_cur(307) or state_cur(104) or state_cur(300) or state_cur(102) or state_cur(106) or state_cur(299) or state_cur(98) or state_cur(290) or state_cur(296) or state_cur(295) or state_cur(93) or state_cur(99) or state_cur(292) or state_cur(315) or state_cur(89) or state_cur(283) or state_cur(282) or state_cur(302) or state_cur(56) or state_cur(266) or state_cur(327);
out1089_bufn <= state_cur(368) or state_cur(114);
out362_bufn <= state_cur(124) or state_cur(87) or state_cur(171) or state_cur(354) or state_cur(183) or state_cur(122);
out982_bufn <= state_cur(357) or state_cur(277);
out979_bufn <= ( state_cur(82) and not ( in24 ) ) or state_cur(269);
out952_bufn <= state_cur(113) or state_cur(268);
out1109_bufn <= state_cur(464) or state_cur(177);
out16_bufn <= state_cur(459) or state_cur(440) or state_cur(220) or state_cur(161) or state_cur(139) or state_cur(83) or state_cur(16) or state_cur(19) or state_cur(18) or state_cur(14) or state_cur(7) or state_cur(5) or state_cur(8) or state_cur(3);
out703_bufn <= state_cur(310) or state_cur(362);
out371_bufn <= state_cur(216) or state_cur(283);
out956_bufn <= state_cur(271) or ( state_cur(256) ) or ( state_cur(254) );
out1107_bufn <= state_cur(144) or state_cur(349);
out1033_bufn <= state_cur(175) or state_cur(103);
out148_bufn <= state_cur(146) or ( state_cur(121) and in26 );
out351_bufn <= state_cur(321) or state_cur(223) or state_cur(224) or state_cur(107) or state_cur(83) or state_cur(16);
out740_bufn <= ( state_cur(396) and to_stdl(funccall0 = 0) ) or ( state_cur(338) and in52 ) or ( state_cur(251) and in48 ) or ( state_cur(249) and not ( in47 ) ) or ( state_cur(249) and in47 ) or ( state_cur(246) and not ( in46 ) ) or ( state_cur(243) ) or ( state_cur(242) ) or ( state_cur(238) ) or ( state_cur(237) ) or ( state_cur(212) and in43 ) or ( state_cur(211) ) or ( state_cur(207) and to_stdl(funccall1 = 0) ) or ( state_cur(207) and to_stdl(funccall1 = 3) ) or ( state_cur(179) and in40 ) or ( state_cur(170) and in39 ) or ( state_cur(160) and in38 ) or ( state_cur(148) and in36 ) or ( state_cur(137) and not ( in34 ) ) or ( state_cur(130) and not ( in33 ) ) or ( state_cur(130) and in33 ) or ( state_cur(396) and to_stdl(funccall0 = 5) ) or ( state_cur(244) ) or ( state_cur(137) and in34 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and in28 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and in29 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and in30 ) or ( state_cur(126) and not ( in32 ) and in31 ) or state_cur(365);
out391_bufn <= state_cur(127) or state_cur(4) or state_cur(425) or state_cur(306);
out129_bufn <= state_cur(356) or ( state_cur(82) and in24 );
out338_bufn <= ( state_cur(256) ) or ( state_cur(254) ) or ( state_cur(453) and to_stdl(funccall4 = 1) ) or ( state_cur(131) and to_stdl(funccall4 = 1) ) or ( state_cur(70) and to_stdl(funccall4 = 1) ) or state_cur(190) or state_cur(187) or state_cur(186) or ( state_cur(126) and in32 ) or ( state_cur(453) and to_stdl(funccall4 = 0) ) or ( state_cur(131) and to_stdl(funccall4 = 0) ) or ( state_cur(70) and to_stdl(funccall4 = 0) ) or state_cur(273) or ( state_cur(76) and in22 ) or ( state_cur(76) and not ( in22 ) );
out425_bufn <= state_cur(55) or state_cur(300);
out1078_bufn <= state_cur(311) or state_cur(310) or state_cur(95);
out349_bufn <= ( state_cur(80) and to_stdl(funccall2 = 1) ) or ( state_cur(79) and to_stdl(funccall2 = 1) ) or ( state_cur(80) and to_stdl(funccall2 = 0) ) or ( state_cur(79) and to_stdl(funccall2 = 0) );
out590_bufn <= state_cur(165) or state_cur(186) or ( state_cur(126) and in32 );
out325_bufn <= state_cur(273) or state_cur(432) or state_cur(71) or ( state_cur(80) and to_stdl(funccall2 = 2) ) or ( state_cur(79) and to_stdl(funccall2 = 2) );
out112_bufn <= state_cur(459) or state_cur(14) or state_cur(7) or state_cur(5);
out224_bufn <= ( state_cur(54) and in15 ) or ( state_cur(53) and not ( in14 ) );
out1220_bufn <= ( state_cur(265) and not ( not (in51) ) ) or ( state_cur(390) and not ( in54 ) );
out1250_bufn <= ( state_cur(407) and in58 ) or ( state_cur(414) and in61 );
out365_bufn <= ( state_cur(105) and in25 ) or state_cur(176) or state_cur(194) or state_cur(124) or state_cur(348) or state_cur(87) or state_cur(171) or state_cur(354) or state_cur(183) or state_cur(122);
out699_bufn <= ( state_cur(453) and to_stdl(funccall4 = 1) ) or ( state_cur(131) and to_stdl(funccall4 = 1) ) or ( state_cur(70) and to_stdl(funccall4 = 1) ) or state_cur(191) or ( state_cur(252) and in49 );
out488_bufn <= ( state_cur(105) and in25 ) or state_cur(171);
out1069_bufn <= state_cur(404) or state_cur(108);
out530_bufn <= state_cur(340) or state_cur(463);
out326_bufn <= ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 2) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 2) ) or ( state_cur(80) and to_stdl(funccall2 = 2) ) or ( state_cur(79) and to_stdl(funccall2 = 2) );
out602_bufn <= state_cur(255) or state_cur(12) or state_cur(163) or state_cur(11);
out83_bufn <= state_cur(147) or state_cur(467) or state_cur(146) or state_cur(10) or state_cur(465) or state_cur(21) or state_cur(140);
out311_bufn <= ( state_cur(433) and not ( in70 ) ) or ( state_cur(366) and in53 ) or state_cur(36) or state_cur(41) or ( state_cur(64) and in17 );
out253_bufn <= state_cur(431) or ( state_cur(428) and not ( in69 ) ) or ( state_cur(427) and in68 ) or state_cur(426) or ( state_cur(45) and in12 );
out209_bufn <= state_cur(426) or ( state_cur(39) and in9 );
out1240_bufn <= ( state_cur(417) and in63 ) or state_cur(410) or ( state_cur(417) and not ( in63 ) ) or state_cur(398);
out1018_bufn <= state_cur(325) or state_cur(97);
out1152_bufn <= state_cur(429) or state_cur(441);
out1236_bufn <= state_cur(408) or state_cur(406) or state_cur(405) or state_cur(402);
out130_bufn <= state_cur(356) or state_cur(186) or ( state_cur(126) and in32 ) or ( state_cur(82) and in24 );
out567_bufn <= ( state_cur(207) and to_stdl(funccall1 = 4) ) or ( state_cur(207) and to_stdl(funccall1 = 5) );
out646_bufn <= ( state_cur(29) and in7 ) or ( state_cur(24) and in5 );
-- Assignment of non-buffered outputs
out26 <=
state_cur(3);
out2 <=
state_cur(466) or state_cur(253) or state_cur(202) or state_cur(191) or state_cur(19) or state_cur(0);
out931 <=
state_cur(261);
out715 <=
state_cur(201);
out410 <=
state_cur(98);
out628 <=
state_cur(165);
out734 <=
state_cur(229) or state_cur(206);
out942 <=
state_cur(265);
out122 <=
state_cur(16);
out892 <=
state_cur(255);
out601 <=
state_cur(159);
out809 <=
state_cur(232);
out376 <=
state_cur(91);
out241 <=
state_cur(45);
out986 <=
state_cur(280);
out1323 <=
state_cur(446);
out455 <=
state_cur(117);
out53 <=
state_cur(377) or state_cur(354) or state_cur(306) or state_cur(305) or state_cur(140) or state_cur(4);
out733 <=
state_cur(206);
out229 <=
state_cur(41);
out901 <=
state_cur(469) or state_cur(462) or state_cur(461) or state_cur(445) or state_cur(257);
out60 <=
state_cur(425) or state_cur(377) or state_cur(306) or state_cur(305) or state_cur(127) or state_cur(4);
out228 <=
state_cur(444) or state_cur(441) or state_cur(430) or state_cur(68) or state_cur(67) or state_cur(57) or state_cur(41);
out160 <=
state_cur(25);
out561 <=
state_cur(150);
out743 <=
state_cur(208);
out921 <=
state_cur(259);
out382 <=
state_cur(93);
out566 <=
state_cur(151);
out99 <=
state_cur(255) or state_cur(163) or state_cur(12) or state_cur(11);
out765 <=
state_cur(217);
out366 <=
state_cur(88);
out1005 <=
state_cur(289);
out1119 <=
state_cur(345);
out1356 <=
state_cur(461);
out25 <=
state_cur(8) or state_cur(3);
out802 <=
state_cur(230);
out918 <=
state_cur(259) or state_cur(258);
out258 <=
state_cur(50);
out640 <=
state_cur(166);
out710 <=
state_cur(198);
out1014 <=
state_cur(294);
out505 <=
state_cur(443) or state_cur(437) or state_cur(133) or state_cur(132);
out1303 <=
state_cur(439);
out424 <=
state_cur(104);
out920 <=
state_cur(258);
out180 <=
state_cur(31);
out974 <=
state_cur(276);
out1339 <=
state_cur(450);
out300 <=
state_cur(64);
out472 <=
state_cur(123);
out143 <=
state_cur(324) or state_cur(20);
out1301 <=
state_cur(437);
out479 <=
state_cur(125);
out464 <=
state_cur(120);
out643 <=
state_cur(167);
out636 <=
state_cur(420) or state_cur(276) or state_cur(275) or state_cur(236) or state_cur(165);
out1022 <=
state_cur(297);
out153 <=
state_cur(23);
out263 <=
state_cur(51);
out690 <=
state_cur(213) or state_cur(187);
out712 <=
state_cur(199);
out828 <=
state_cur(235);
out772 <=
state_cur(220);
out342 <=
state_cur(76);
out40 <=
state_cur(465) or state_cur(425) or state_cur(306) or state_cur(127) or state_cur(87) or state_cur(4);
out1223 <=
state_cur(394);
out443 <=
state_cur(112);
out679 <=
state_cur(180);
out1073 <=
state_cur(309);
out150 <=
state_cur(21);
out299 <=
state_cur(68) or state_cur(63);
out1349 <=
state_cur(455);
out1383 <=
state_cur(471);
out572 <=
state_cur(153);
out1298 <=
state_cur(436);
out1311 <=
state_cur(442);
out607 <=
state_cur(161);
out737 <=
state_cur(207);
out510 <=
state_cur(396) or state_cur(365) or state_cur(207) or state_cur(134);
out165 <=
state_cur(28) or state_cur(26);
out462 <=
state_cur(119);
out514 <=
state_cur(136) or state_cur(135);
out531 <=
state_cur(143);
out872 <=
state_cur(243);
out791 <=
state_cur(226);
out417 <=
state_cur(101);
out297 <=
state_cur(63);
out1121 <=
state_cur(347);
out614 <=
state_cur(164);
out64 <=
state_cur(5);
out589 <=
state_cur(158);
out231 <=
state_cur(42);
out888 <=
state_cur(271) or state_cur(256) or state_cur(254);
out1324 <=
state_cur(447);
out1150 <=
state_cur(364);
out1295 <=
state_cur(435);
out152 <=
state_cur(159) or state_cur(22);
out310 <=
state_cur(444) or state_cur(67);
out694 <=
state_cur(189);
out718 <=
state_cur(202);
out759 <=
state_cur(214);
out722 <=
state_cur(203);
out1387 <=
state_cur(472);
out82 <=
state_cur(473) or state_cur(464) or state_cur(463) or state_cur(456) or state_cur(438) or state_cur(434) or state_cur(404) or state_cur(388) or
state_cur(387) or state_cur(384) or state_cur(382) or state_cur(381) or state_cur(380) or state_cur(376) or state_cur(375) or state_cur(372) or
state_cur(368) or state_cur(362) or state_cur(360) or state_cur(357) or state_cur(356) or state_cur(355) or state_cur(351) or state_cur(350) or
state_cur(349) or state_cur(348) or state_cur(346) or state_cur(342) or state_cur(341) or state_cur(340) or state_cur(339) or state_cur(334) or
state_cur(332) or state_cur(331) or state_cur(330) or state_cur(329) or state_cur(328) or state_cur(327) or state_cur(326) or state_cur(325) or
state_cur(323) or state_cur(322) or state_cur(321) or state_cur(320) or state_cur(319) or state_cur(318) or state_cur(317) or state_cur(316) or
state_cur(315) or state_cur(314) or state_cur(313) or state_cur(312) or state_cur(311) or state_cur(310) or state_cur(309) or state_cur(308) or
state_cur(307) or state_cur(304) or state_cur(303) or state_cur(302) or state_cur(301) or state_cur(300) or state_cur(299) or state_cur(298) or
state_cur(297) or state_cur(296) or state_cur(295) or state_cur(294) or state_cur(293) or state_cur(292) or state_cur(291) or state_cur(290) or
state_cur(289) or state_cur(288) or state_cur(287) or state_cur(286) or state_cur(285) or state_cur(284) or state_cur(283) or state_cur(282) or
state_cur(281) or state_cur(278) or state_cur(277) or state_cur(269) or state_cur(268) or state_cur(267) or state_cur(266) or state_cur(224) or
state_cur(221) or state_cur(219) or state_cur(216) or state_cur(200) or state_cur(197) or state_cur(196) or state_cur(195) or state_cur(194) or
state_cur(193) or state_cur(192) or state_cur(185) or state_cur(178) or state_cur(177) or state_cur(176) or state_cur(175) or state_cur(172) or
state_cur(155) or state_cur(149) or state_cur(145) or state_cur(144) or state_cur(143) or state_cur(142) or state_cur(141) or state_cur(116) or
state_cur(115) or state_cur(114) or state_cur(113) or state_cur(111) or state_cur(110) or state_cur(108) or state_cur(106) or state_cur(104) or
state_cur(103) or state_cur(102) or state_cur(101) or state_cur(100) or state_cur(99) or state_cur(98) or state_cur(97) or state_cur(96) or
state_cur(95) or state_cur(94) or state_cur(93) or state_cur(92) or state_cur(91) or state_cur(90) or state_cur(89) or state_cur(86) or
state_cur(85) or state_cur(84) or state_cur(60) or state_cur(58) or state_cur(56) or state_cur(55) or state_cur(37) or state_cur(16) or
state_cur(9);
out1139 <=
state_cur(361);
out558 <=
state_cur(147);
out696 <=
state_cur(190);
out1381 <=
state_cur(470);
out1293 <=
state_cur(435);
out519 <=
state_cur(139);
out1292 <=
state_cur(434);
out895 <=
state_cur(256);
out1176 <=
state_cur(429) or state_cur(379) or state_cur(378);
out170 <=
state_cur(173) or state_cur(27);
out434 <=
state_cur(109);
out341 <=
state_cur(77) or state_cur(75);
out1007 <=
state_cur(290);
out595 <=
state_cur(158);
out874 <=
state_cur(244);
out1364 <=
state_cur(464);
out621 <=
state_cur(164);
out962 <=
state_cur(273);
out767 <=
state_cur(374) or state_cur(220) or state_cur(217);
out523 <=
state_cur(139);
out350 <=
state_cur(81);
out745 <=
state_cur(209);
out863 <=
state_cur(241);
out958 <=
state_cur(272);
out1182 <=
state_cur(446) or state_cur(383);
out13 <=
state_cur(1);
out1 <=
state_cur(0);
out1101 <=
state_cur(336);
out1344 <=
state_cur(452);
out749 <=
state_cur(210);
out972 <=
state_cur(275);
out289 <=
state_cur(61);
out1290 <=
state_cur(432);
out985 <=
state_cur(279);
out279 <=
state_cur(57);
out517 <=
state_cur(138);
out1035 <=
state_cur(302);
out1000 <=
state_cur(287);
out1085 <=
state_cur(314);
out1289 <=
state_cur(431);
out85 <=
state_cur(377) or state_cur(305) or state_cur(124) or state_cur(10);
out35 <=
state_cur(306) or state_cur(183) or state_cur(171) or state_cur(147) or state_cur(146) or state_cur(4);
out304 <=
state_cur(65);
out347 <=
state_cur(80) or state_cur(79);
out1190 <=
state_cur(389);
out649 <=
state_cur(167);
out156 <=
state_cur(24);
out1228 <=
state_cur(396);
out266 <=
state_cur(51);
out651 <=
state_cur(168);
out866 <=
state_cur(242);
out508 <=
state_cur(133);
out1114 <=
state_cur(344);
out245 <=
state_cur(46);
out44 <=
state_cur(354) or state_cur(306) or state_cur(21) or state_cur(4);
out1174 <=
state_cur(431) or state_cur(378);
out80 <=
state_cur(9);
out134 <=
state_cur(17);
out1187 <=
state_cur(391) or state_cur(386);
out1032 <=
state_cur(301);
out1287 <=
state_cur(430);
out989 <=
state_cur(281);
out538 <=
state_cur(146);
out1104 <=
state_cur(337);
out981 <=
state_cur(278);
out1286 <=
state_cur(429);
out724 <=
state_cur(204);
out487 <=
state_cur(127);
out658 <=
state_cur(169);
out1215 <=
state_cur(393) or state_cur(390);
out407 <=
state_cur(97);
out534 <=
state_cur(144);
out1175 <=
state_cur(378);
out858 <=
state_cur(239);
out1284 <=
state_cur(429);
out402 <=
state_cur(356) or state_cur(171) or state_cur(146) or state_cur(95);
out755 <=
state_cur(212);
out255 <=
state_cur(48);
out93 <=
state_cur(11);
out467 <=
state_cur(122);
out379 <=
state_cur(92);
out664 <=
state_cur(174);
out429 <=
state_cur(106);
out322 <=
state_cur(123) or state_cur(81) or state_cur(71);
out949 <=
state_cur(268);
out826 <=
state_cur(389) or state_cur(235);
out681 <=
state_cur(181);
out905 <=
state_cur(462) or state_cur(461) or state_cur(445) or state_cur(257);
out15 <=
state_cur(2);
out794 <=
state_cur(227);
out795 <=
state_cur(228);
out139 <=
state_cur(19);
out193 <=
state_cur(35);
out1019 <=
state_cur(296);
out171 <=
state_cur(28);
out173 <=
state_cur(29);
out610 <=
state_cur(162);
out1279 <=
state_cur(427);
out440 <=
state_cur(111);
out480 <=
state_cur(134) or state_cur(125);
out860 <=
state_cur(239);
out1158 <=
state_cur(369);
out189 <=
state_cur(33);
out902 <=
state_cur(257);
out1134 <=
state_cur(358);
out799 <=
state_cur(229);
out955 <=
state_cur(270);
out1278 <=
state_cur(426);
out1098 <=
state_cur(335);
out963 <=
state_cur(274);
out373 <=
state_cur(90);
out728 <=
state_cur(213) or state_cur(205);
out1160 <=
state_cur(370);
out570 <=
state_cur(353) or state_cur(214) or state_cur(152);
out937 <=
state_cur(262);
out1275 <=
state_cur(426);
out114 <=
state_cur(14);
out812 <=
state_cur(233);
out787 <=
state_cur(225);
out7 <=
state_cur(421) or state_cur(420) or state_cur(415) or state_cur(413) or state_cur(412) or state_cur(408) or state_cur(406) or state_cur(405) or
state_cur(402) or state_cur(401) or state_cur(275) or state_cur(261) or state_cur(165) or state_cur(0);
out396 <=
state_cur(95);
out762 <=
state_cur(215);
out978 <=
state_cur(277);
out933 <=
state_cur(410) or state_cur(398) or state_cur(261);
out938 <=
state_cur(263);
out313 <=
state_cur(67);
out1131 <=
state_cur(356);
out778 <=
state_cur(222);
out848 <=
state_cur(236);
out882 <=
state_cur(251) or state_cur(250) or state_cur(248);
out1229 <=
state_cur(398);
out1180 <=
state_cur(450) or state_cur(383);
out1155 <=
state_cur(367);
out947 <=
state_cur(267);
out232 <=
state_cur(426) or state_cur(258) or state_cur(158) or state_cur(42);
out201 <=
state_cur(36);
out783 <=
state_cur(223);
out996 <=
state_cur(284);
out1094 <=
state_cur(333);
out420 <=
state_cur(102);
out107 <=
state_cur(12);
out1269 <=
state_cur(425);
out414 <=
state_cur(100);
out1011 <=
state_cur(292);
out333 <=
state_cur(123) or state_cur(72);
out296 <=
state_cur(62);
out335 <=
state_cur(73);
out726 <=
state_cur(205);
out1151 <=
state_cur(366);
out256 <=
state_cur(49);
out111 <=
state_cur(255) or state_cur(12);
out1068 <=
state_cur(307);
out202 <=
state_cur(174) or state_cur(36);
out1368 <=
state_cur(467);
out1181 <=
state_cur(383);
out1137 <=
state_cur(359);
out1308 <=
state_cur(441);
out768 <=
state_cur(218);
out500 <=
state_cur(131);
out14 <=
state_cur(455) or state_cur(442) or state_cur(436) or state_cur(400) or state_cur(394) or state_cur(385) or state_cur(373) or state_cur(370) or
state_cur(369) or state_cur(367) or state_cur(364) or state_cur(361) or state_cur(359) or state_cur(358) or state_cur(352) or state_cur(347) or
state_cur(345) or state_cur(344) or state_cur(343) or state_cur(337) or state_cur(336) or state_cur(335) or state_cur(280) or state_cur(279) or
state_cur(274) or state_cur(272) or state_cur(233) or state_cur(232) or state_cur(231) or state_cur(230) or state_cur(228) or state_cur(227) or
state_cur(226) or state_cur(225) or state_cur(223) or state_cur(222) or state_cur(218) or state_cur(215) or state_cur(208) or state_cur(204) or
state_cur(203) or state_cur(201) or state_cur(199) or state_cur(198) or state_cur(189) or state_cur(182) or state_cur(181) or state_cur(180) or
state_cur(166) or state_cur(162) or state_cur(156) or state_cur(153) or state_cur(151) or state_cur(150) or state_cur(120) or state_cur(119) or
state_cur(118) or state_cur(117) or state_cur(112) or state_cur(109) or state_cur(88) or state_cur(62) or state_cur(33) or state_cur(3) or
state_cur(1);
out1164 <=
state_cur(371);
out1125 <=
state_cur(352);
out1016 <=
state_cur(295);
out688 <=
state_cur(186);
out1026 <=
state_cur(299);
out1329 <=
state_cur(449);
out191 <=
state_cur(34);
out855 <=
state_cur(238);
out597 <=
state_cur(258) or state_cur(158);
out184 <=
state_cur(32) or state_cur(31);
out162 <=
state_cur(26);
out422 <=
state_cur(103);
out197 <=
state_cur(188) or state_cur(38) or state_cur(35);
out104 <=
state_cur(12);
out1266 <=
state_cur(423);
out117 <=
state_cur(15);
out1024 <=
state_cur(298);
out221 <=
state_cur(41);
out1088 <=
state_cur(315);
out1128 <=
state_cur(354);
out923 <=
state_cur(260) or state_cur(259);
out1029 <=
state_cur(300);
out137 <=
state_cur(19) or state_cur(18);
out515 <=
state_cur(136);
out991 <=
state_cur(282);
out1375 <=
state_cur(468);
out957 <=
state_cur(271);
out264 <=
state_cur(430) or state_cur(52) or state_cur(51);
out1262 <=
state_cur(421);
out663 <=
state_cur(173);
out1111 <=
state_cur(343);
out119 <=
state_cur(15);
out998 <=
state_cur(286);
out731 <=
state_cur(206);
out1366 <=
state_cur(466);
out320 <=
state_cur(453) or state_cur(131) or state_cur(70);
out208 <=
state_cur(38);
out994 <=
state_cur(283);
out136 <=
state_cur(18);
out1145 <=
state_cur(363);
out1126 <=
state_cur(353);
out478 <=
state_cur(124);
out753 <=
state_cur(211);
out1141 <=
state_cur(362);
out951 <=
state_cur(269);
out370 <=
state_cur(89);
out259 <=
state_cur(57) or state_cur(50);
out332 <=
state_cur(72);
out1370 <=
state_cur(472) or state_cur(468);
out281 <=
state_cur(58);
out234 <=
state_cur(429) or state_cur(426) or state_cur(379) or state_cur(188) or state_cur(49) or state_cur(48) or state_cur(42);
out314 <=
state_cur(68);
out1185 <=
state_cur(385);
out1353 <=
state_cur(459);
out907 <=
state_cur(257);
out1258 <=
state_cur(420);
out698 <=
state_cur(191);
out212 <=
state_cur(40);
out468 <=
state_cur(467) or state_cur(377) or state_cur(305) or state_cur(122);
out876 <=
state_cur(245);
out498 <=
state_cur(129);
out251 <=
state_cur(379) or state_cur(48);
out1009 <=
state_cur(291);
out656 <=
state_cur(168);
out612 <=
state_cur(163);
out177 <=
state_cur(30);
out944 <=
state_cur(266);
out894 <=
state_cur(255);
out928 <=
state_cur(261) or state_cur(260);
out267 <=
state_cur(52);
out384 <=
state_cur(94);
out1171 <=
state_cur(374);
out815 <=
state_cur(234);
out230 <=
state_cur(260) or state_cur(259) or state_cur(57) or state_cur(41);
out739 <=
state_cur(365) or state_cur(207);
out88 <=
state_cur(467) or state_cur(465) or state_cur(425) or state_cur(354) or state_cur(348) or state_cur(317) or state_cur(312) or state_cur(311) or
state_cur(310) or state_cur(194) or state_cur(193) or state_cur(185) or state_cur(183) or state_cur(176) or state_cur(171) or state_cur(147) or
state_cur(146) or state_cur(140) or state_cur(127) or state_cur(124) or state_cur(122) or state_cur(115) or state_cur(96) or state_cur(87) or
state_cur(21) or state_cur(10);
out997 <=
state_cur(285);
out1362 <=
state_cur(462);
out806 <=
state_cur(231);
out1037 <=
state_cur(304);
out1147 <=
state_cur(447) or state_cur(363);
out1253 <=
state_cur(471) or state_cur(470) or state_cur(458) or state_cur(418);
out1169 <=
state_cur(373);
out316 <=
state_cur(70);
out317 <=
state_cur(131) or state_cur(123) or state_cur(81) or state_cur(77) or state_cur(75) or state_cur(71) or state_cur(70);
out133 <=
state_cur(371) or state_cur(362) or state_cur(107) or state_cur(95) or state_cur(83) or state_cur(16);
out1252 <=
state_cur(418);
out1096 <=
state_cur(333);
out186 <=
state_cur(32);
out1346 <=
state_cur(453);
out1146 <=
state_cur(363);
out363 <=
state_cur(87);
out887 <=
state_cur(254);
out659 <=
state_cur(190) or state_cur(169);
out661 <=
state_cur(171);
out346 <=
state_cur(79);
out270 <=
state_cur(54);
out1363 <=
state_cur(463);
out886 <=
state_cur(253);
out1341 <=
state_cur(451);
out92 <=
state_cur(11);
out1213 <=
state_cur(390);
out324 <=
state_cur(71);
out578 <=
state_cur(156);
out344 <=
state_cur(77);
out929 <=
state_cur(260);
out355 <=
state_cur(84);
out953 <=
state_cur(270);
out146 <=
state_cur(324) or state_cur(261) or state_cur(20);
out1365 <=
state_cur(465);
out348 <=
state_cur(80);
out358 <=
state_cur(85);
out513 <=
state_cur(135);
out1217 <=
state_cur(391);
out305 <=
state_cur(67) or state_cur(65);
out903 <=
state_cur(461) or state_cur(257);
out239 <=
state_cur(44);
out497 <=
state_cur(134) or state_cur(129) or state_cur(128);
out1337 <=
state_cur(450);
out861 <=
state_cur(247) or state_cur(239);
out448 <=
state_cur(114);
out1070 <=
state_cur(308);
out527 <=
state_cur(140);
out247 <=
state_cur(47);
out1091 <=
state_cur(327);
out496 <=
state_cur(128);
out328 <=
state_cur(432) or state_cur(273) or state_cur(71);
out1186 <=
state_cur(386);
out1309 <=
state_cur(441);
out526 <=
state_cur(161) or state_cur(139);
out199 <=
state_cur(35);
out154 <=
state_cur(435) or state_cur(253) or state_cur(133) or state_cur(23);
out1243 <=
state_cur(410);
out55 <=
state_cur(377) or state_cur(306) or state_cur(305) or state_cur(4);
out1082 <=
state_cur(313);
out240 <=
state_cur(49) or state_cur(44);
out1320 <=
state_cur(445);
out458 <=
state_cur(118);
out879 <=
state_cur(247);
out936 <=
state_cur(264) or state_cur(263) or state_cur(262);
out84 <=
state_cur(10);
out1221 <=
state_cur(423) or state_cur(397) or state_cur(395) or state_cur(392);
out1003 <=
state_cur(288);
out192 <=
state_cur(42) or state_cur(34);
out692 <=
state_cur(188);
out852 <=
state_cur(237);
out275 <=
state_cur(56);
out775 <=
state_cur(440) or state_cur(220);
out412 <=
state_cur(99);
out306 <=
state_cur(66);
out1013 <=
state_cur(293);
out1235 <=
state_cur(400);
out577 <=
state_cur(184) or state_cur(163) or state_cur(154);
out1166 <=
state_cur(371);
out432 <=
state_cur(108);
out1327 <=
state_cur(448);
out1378 <=
state_cur(469);
out49 <=
state_cur(306) or state_cur(171) or state_cur(146) or state_cur(4);
out65 <=
state_cur(459) or state_cur(14) or state_cur(7) or state_cur(5);
out246 <=
state_cur(48) or state_cur(46);
out939 <=
state_cur(264);
out504 <=
state_cur(132);
out667 <=
state_cur(444) or state_cur(441) or state_cur(174);
out683 <=
state_cur(182);
out686 <=
state_cur(183);
-- Assignment of buffered outputs
out1057 <= out1057_buf;
out59 <= out59_buf;
out447 <= out447_buf;
out157 <= out157_buf;
out450 <= out450_buf;
out1012 <= out1012_buf;
out1072 <= out1072_buf;
out999 <= out999_buf;
out437 <= out437_buf;
out415 <= out415_buf;
out426 <= out426_buf;
out375 <= out375_buf;
out704 <= out704_buf;
out973 <= out973_buf;
out11 <= out11_buf;
out549 <= out549_buf;
out453 <= out453_buf;
out1231 <= out1231_buf;
out87 <= out87_buf;
out401 <= out401_buf;
out990 <= out990_buf;
out378 <= out378_buf;
out1302 <= out1302_buf;
out27 <= out27_buf;
out569 <= out569_buf;
out1030 <= out1030_buf;
out537 <= out537_buf;
out77 <= out77_buf;
out1318 <= out1318_buf;
out533 <= out533_buf;
out32 <= out32_buf;
out1027 <= out1027_buf;
out599 <= out599_buf;
out668 <= out668_buf;
out568 <= out568_buf;
out225 <= out225_buf;
out700 <= out700_buf;
out638 <= out638_buf;
out670 <= out670_buf;
out433 <= out433_buf;
out896 <= out896_buf;
out575 <= out575_buf;
out428 <= out428_buf;
out72 <= out72_buf;
out404 <= out404_buf;
out98 <= out98_buf;
out67 <= out67_buf;
out635 <= out635_buf;
out381 <= out381_buf;
out222 <= out222_buf;
out339 <= out339_buf;
out268 <= out268_buf;
out419 <= out419_buf;
out559 <= out559_buf;
out1002 <= out1002_buf;
out1006 <= out1006_buf;
out276 <= out276_buf;
out205 <= out205_buf;
out943 <= out943_buf;
out1080 <= out1080_buf;
out408 <= out408_buf;
out252 <= out252_buf;
out71 <= out71_buf;
out672 <= out672_buf;
out357 <= out357_buf;
out441 <= out441_buf;
out1084 <= out1084_buf;
out144 <= out144_buf;
out574 <= out574_buf;
out210 <= out210_buf;
out128 <= out128_buf;
out360 <= out360_buf;
out948 <= out948_buf;
out506 <= out506_buf;
out207 <= out207_buf;
out1083 <= out1083_buf;
out491 <= out491_buf;
out4 <= out4_buf;
out784 <= out784_buf;
out3 <= out3_buf;
out746 <= out746_buf;
out528 <= out528_buf;
out372 <= out372_buf;
out418 <= out418_buf;
out708 <= out708_buf;
out706 <= out706_buf;
out445 <= out445_buf;
out1021 <= out1021_buf;
out405 <= out405_buf;
out764 <= out764_buf;
out581 <= out581_buf;
out776 <= out776_buf;
out213 <= out213_buf;
out674 <= out674_buf;
out1326 <= out1326_buf;
out334 <= out334_buf;
out843 <= out843_buf;
out175 <= out175_buf;
out1036 <= out1036_buf;
out1015 <= out1015_buf;
out236 <= out236_buf;
out395 <= out395_buf;
out1340 <= out1340_buf;
out993 <= out993_buf;
out356 <= out356_buf;
out273 <= out273_buf;
out403 <= out403_buf;
out286 <= out286_buf;
out364 <= out364_buf;
out697 <= out697_buf;
out283 <= out283_buf;
out282 <= out282_buf;
out1319 <= out1319_buf;
out409 <= out409_buf;
out1092 <= out1092_buf;
out1075 <= out1075_buf;
out925 <= out925_buf;
out78 <= out78_buf;
out1089 <= out1089_buf;
out362 <= out362_buf;
out982 <= out982_buf;
out979 <= out979_buf;
out952 <= out952_buf;
out1109 <= out1109_buf;
out16 <= out16_buf;
out703 <= out703_buf;
out371 <= out371_buf;
out956 <= out956_buf;
out1107 <= out1107_buf;
out1033 <= out1033_buf;
out148 <= out148_buf;
out351 <= out351_buf;
out740 <= out740_buf;
out391 <= out391_buf;
out129 <= out129_buf;
out338 <= out338_buf;
out425 <= out425_buf;
out1078 <= out1078_buf;
out349 <= out349_buf;
out590 <= out590_buf;
out325 <= out325_buf;
out112 <= out112_buf;
out224 <= out224_buf;
out1220 <= out1220_buf;
out1250 <= out1250_buf;
out365 <= out365_buf;
out699 <= out699_buf;
out488 <= out488_buf;
out1069 <= out1069_buf;
out530 <= out530_buf;
out326 <= out326_buf;
out602 <= out602_buf;
out83 <= out83_buf;
out311 <= out311_buf;
out253 <= out253_buf;
out209 <= out209_buf;
out1240 <= out1240_buf;
out1018 <= out1018_buf;
out1152 <= out1152_buf;
out1236 <= out1236_buf;
out130 <= out130_buf;
out567 <= out567_buf;
out646 <= out646_buf;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc140.vhd | 4 | 2170 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc140.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p09n01i00140ent IS
PORT ( SIGNAL a : IN bit;
SIGNAL b : IN integer;
SIGNAL c : IN boolean;
SIGNAL d : IN time;
SIGNAL e : IN real;
SIGNAL oint : INOUT integer);
END c04s03b02x02p09n01i00140ent;
ARCHITECTURE c04s03b02x02p09n01i00140arch OF c04s03b02x02p09n01i00140ent IS
function funct1( fpar1:bit :='1';
fpar2:integer :=455;
fpar3:boolean :=true;
fpar4:time :=55.77 ns;
fpar5:real :=34.558) return integer is
begin
return 1;
end funct1;
BEGIN
TESTING: PROCESS
BEGIN
wait for 1 ns;
oint <= funct1(fpar3=>c,fpar2=>b,fpar1=>a,fpar4=>d,nosuch=>e);
assert FALSE
report "***FAILED TEST: c04s03b02x02p09n01i00140 - Named association parameter where name is not in formal parameter list."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p09n01i00140arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2940.vhd | 4 | 1680 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2940.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p07n03i02940ent IS
function func1 (i,l:integer) return boolean;
END c02s02b00x00p07n03i02940ent;
ARCHITECTURE c02s02b00x00p07n03i02940arch OF c02s02b00x00p07n03i02940ent IS
-- ERROR: non-existent body for function func1
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02940 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02940arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink-b.vhd | 4 | 4519 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_sink-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library math;
architecture behavior of sink is
begin
token_consumer : process is
variable number_of_tokens_consumed : natural := 0;
variable life_time : real; -- in time_unit
variable sum_of_life_times : real := 0.0; -- in time_unit
variable sum_of_squares_of_life_times : real := 0.0; --in time_unit**2
use std.textio.all;
file info_file : text;
variable L : line;
use math.math_real.sqrt;
procedure write_summary is
variable mean_life_time : real
:= sum_of_life_times / real(number_of_tokens_consumed);
variable std_dev_of_life_times : real
:= sqrt ( ( sum_of_squares_of_life_times
- sum_of_life_times**2 / real(number_of_tokens_consumed) )
/ real( number_of_tokens_consumed - 1 ) );
begin
write(L, string'("Summary information for sink "));
write(L, name);
write(L, string'(" up to time "));
write(L, now, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Number of tokens consumed = "));
write(L, natural(number_of_tokens_consumed));
writeline(info_file, L);
write(L, string'(" Mean life_time = "));
write(L, mean_life_time * time_unit, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Standard deviation of life_times = "));
write(L, std_dev_of_life_times * time_unit, unit => time_unit);
writeline(info_file, L);
writeline(info_file, L);
end procedure write_summary;
procedure write_trace is
begin
write(L, string'("Sink "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" consumed "));
write(L, in_arc.token, time_unit);
writeline(info_file, L);
end procedure write_trace;
begin
file_open(info_file, info_file_name, write_mode);
loop
wait on info_detail'transaction, in_arc;
if info_detail'active and info_detail = summary then
write_summary;
end if;
if in_arc'event then
number_of_tokens_consumed := number_of_tokens_consumed + 1;
life_time := real( (now - in_arc.token.creation_time) / time_unit );
sum_of_life_times := sum_of_life_times + life_time;
sum_of_squares_of_life_times := sum_of_squares_of_life_times + life_time ** 2;
if info_detail = trace then
write_trace;
end if;
end if;
end loop;
end process token_consumer;
end architecture behavior;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/limiter.vhd | 4 | 1617 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity limiter is
generic ( limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8 ); -- lower limit
port ( quantity input : in real;
quantity output : out real);
end entity limiter;
----------------------------------------------------------------
architecture simple of limiter is
constant slope : real := 1.0e-4;
begin
if input > limit_high use -- upper limit exceeded, so limit input signal
output == limit_high + slope*(input - limit_high);
elsif input < limit_low use -- lower limit exceeded, so limit input signal
output == limit_low + slope*(input - limit_low);
else -- no limit exceeded, so pass input signal as is
output == input;
end use;
break on input'above(limit_high), input'above(limit_low);
end architecture simple;
| gpl-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.