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|---|---|---|---|---|---|
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2313.vhd | 4 | 1680 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2313.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02313ent IS
END c07s02b07x00p01n01i02313ent;
ARCHITECTURE c07s02b07x00p01n01i02313arch OF c07s02b07x00p01n01i02313ent IS
BEGIN
TESTING: PROCESS
-- Local declarations.
variable BITV : BIT := '0';
BEGIN
BITV := ABS BITV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02313 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02313arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1035.vhd | 4 | 2054 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1035.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p02n01i01035ent IS
END c06s04b00x00p02n01i01035ent;
ARCHITECTURE c06s04b00x00p02n01i01035arch OF c06s04b00x00p02n01i01035ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type A2 is array (THREE, THREE) of BOOLEAN;
type A3 is array (THREE) of A1;
function F3(i : integer) return A3 is
variable AR3 : A3;
begin
return AR3;
end F3;
variable A : integer;
variable V : BOOLEAN;
BEGIN
V := F3(A)(1)(3); -- Indexed Name
assert NOT(V=false)
report "***PASSED TEST: c06s04b00x00p02n01i01035"
severity NOTE;
assert (V= false)
report "***FAILED TEST: c06s04b00x00p02n01i01035 - The prefix of an indexed name can be a indexed name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01035arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug040/cmp_868.vhd | 2 | 378 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_868 is
port (
eq : out std_logic;
in1 : in std_logic_vector(23 downto 0);
in0 : in std_logic_vector(23 downto 0)
);
end cmp_868;
architecture augh of cmp_868 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2368.vhd | 4 | 1750 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2368.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b01x00p01n01i02368ent IS
END c07s03b01x00p01n01i02368ent;
ARCHITECTURE c07s03b01x00p01n01i02368arch OF c07s03b01x00p01n01i02368ent IS
constant C1 : bit_vector(0 to 7) := "01010101" ;
BEGIN
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT( C1 = "01010101" )
report "***PASSED TEST: c07s03b01x00p01n01i02368"
severity NOTE;
assert ( C1 = "01010101" )
report "***FAILED TEST: c07s03b01x00p01n01i02368 - A literal is a bit string literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b01x00p01n01i02368arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket89/repro.vhdl | 3 | 350 | entity repro is
end repro;
architecture behav of repro is
signal s : natural;
begin -- behav
process (s) is
variable v : natural;
begin
v := s'delayed (0 ns);
end process;
process
begin
s <= 3;
wait for 1 ns;
s <= 4;
wait for 0 ns;
s <= 5;
wait for 0 ns;
s <= 5;
wait;
end process;
end behav;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_08.vhd | 4 | 1765 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_08.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_03_08 is
end entity test_bench_03_08;
architecture test_SR_flipflop_checking of test_bench_03_08 is
signal S, R, Q : bit := '0';
begin
dut : entity work.SR_flipflop(checking)
port map ( S => S, R => R, Q => Q );
stumulus : process is
begin
wait for 10 ns;
S <= '1'; wait for 10 ns;
S <= '0'; wait for 10 ns;
S <= '1'; wait for 10 ns;
S <= '0'; wait for 10 ns;
R <= '1'; wait for 10 ns;
R <= '0'; wait for 10 ns;
R <= '1'; wait for 10 ns;
R <= '0'; wait for 10 ns;
S <= '1'; R <= '1'; wait for 10 ns;
R <= '0'; wait for 10 ns;
S <= '0'; wait for 10 ns;
wait;
end process stumulus;
end architecture test_SR_flipflop_checking;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug037/utils.vhdl | 2 | 32199 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: Common functions and types
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.my_config.all;
package utils is
-- PoC settings
-- ==========================================================================
constant POC_VERBOSE : BOOLEAN := MY_VERBOSE;
-- Environment
-- ==========================================================================
-- Distinguishes simulation from synthesis
constant SIMULATION : BOOLEAN; -- deferred constant declaration
-- Type declarations
-- ==========================================================================
--+ Vectors of primitive standard types +++++++++++++++++++++++++++++++++++++
type T_BOOLVEC is array(NATURAL range <>) of BOOLEAN;
type T_INTVEC is array(NATURAL range <>) of INTEGER;
type T_NATVEC is array(NATURAL range <>) of NATURAL;
type T_POSVEC is array(NATURAL range <>) of POSITIVE;
type T_REALVEC is array(NATURAL range <>) of REAL;
--+ Integer subranges sometimes useful for speeding up simulation ++++++++++
subtype T_INT_8 is INTEGER range -128 to 127;
subtype T_INT_16 is INTEGER range -32768 to 32767;
subtype T_UINT_8 is INTEGER range 0 to 255;
subtype T_UINT_16 is INTEGER range 0 to 65535;
--+ Enums ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Intellectual Property (IP) type
type T_IPSTYLE is (IPSTYLE_HARD, IPSTYLE_SOFT);
-- Bit Order
type T_BIT_ORDER is (LSB_FIRST, MSB_FIRST);
-- Byte Order (Endian)
type T_BYTE_ORDER is (LITTLE_ENDIAN, BIG_ENDIAN);
-- rounding style
type T_ROUNDING_STYLE is (ROUND_TO_NEAREST, ROUND_TO_ZERO, ROUND_TO_INF, ROUND_UP, ROUND_DOWN);
type T_BCD is array(3 downto 0) of std_logic;
type T_BCD_VECTOR is array(NATURAL range <>) of T_BCD;
constant C_BCD_MINUS : T_BCD := "1010";
constant C_BCD_OFF : T_BCD := "1011";
-- Function declarations
-- ==========================================================================
--+ Division ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Calculates: ceil(a / b)
function div_ceil(a : NATURAL; b : POSITIVE) return NATURAL;
--+ Power +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- is input a power of 2?
function is_pow2(int : NATURAL) return BOOLEAN;
-- round to next power of 2
function ceil_pow2(int : NATURAL) return POSITIVE;
-- round to previous power of 2
function floor_pow2(int : NATURAL) return NATURAL;
--+ Logarithm ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Calculates: ceil(ld(arg))
function log2ceil(arg : positive) return natural;
-- Calculates: max(1, ceil(ld(arg)))
function log2ceilnz(arg : positive) return positive;
-- Calculates: ceil(lg(arg))
function log10ceil(arg : POSITIVE) return NATURAL;
-- Calculates: max(1, ceil(lg(arg)))
function log10ceilnz(arg : POSITIVE) return POSITIVE;
--+ if-then-else (ite) +++++++++++++++++++++++++++++++++++++++++++++++++++++
function ite(cond : BOOLEAN; value1 : BOOLEAN; value2 : BOOLEAN) return BOOLEAN;
function ite(cond : BOOLEAN; value1 : INTEGER; value2 : INTEGER) return INTEGER;
function ite(cond : BOOLEAN; value1 : REAL; value2 : REAL) return REAL;
function ite(cond : BOOLEAN; value1 : STD_LOGIC; value2 : STD_LOGIC) return STD_LOGIC;
function ite(cond : BOOLEAN; value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function ite(cond : BOOLEAN; value1 : BIT_VECTOR; value2 : BIT_VECTOR) return BIT_VECTOR;
function ite(cond : BOOLEAN; value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED;
function ite(cond : BOOLEAN; value1 : CHARACTER; value2 : CHARACTER) return CHARACTER;
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING;
--+ Max / Min / Sum ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
function imin(arg1 : integer; arg2 : integer) return integer; -- Calculates: min(arg1, arg2) for integers
alias rmin is IEEE.math_real.realmin[real, real return real];
-- function rmin(arg1 : real; arg2 : real) return real; -- Calculates: min(arg1, arg2) for reals
function imin(vec : T_INTVEC) return INTEGER; -- Calculates: min(vec) for a integer vector
function imin(vec : T_NATVEC) return NATURAL; -- Calculates: min(vec) for a natural vector
function imin(vec : T_POSVEC) return POSITIVE; -- Calculates: min(vec) for a positive vector
function rmin(vec : T_REALVEC) return real; -- Calculates: min(vec) of real vector
function imax(arg1 : integer; arg2 : integer) return integer; -- Calculates: max(arg1, arg2) for integers
alias rmax is IEEE.math_real.realmax[real, real return real];
-- function rmax(arg1 : real; arg2 : real) return real; -- Calculates: max(arg1, arg2) for reals
function imax(vec : T_INTVEC) return INTEGER; -- Calculates: max(vec) for a integer vector
function imax(vec : T_NATVEC) return NATURAL; -- Calculates: max(vec) for a natural vector
function imax(vec : T_POSVEC) return POSITIVE; -- Calculates: max(vec) for a positive vector
function rmax(vec : T_REALVEC) return real; -- Calculates: max(vec) of real vector
function isum(vec : T_NATVEC) return NATURAL; -- Calculates: sum(vec) for a natural vector
function isum(vec : T_POSVEC) return natural; -- Calculates: sum(vec) for a positive vector
function isum(vec : T_INTVEC) return integer; -- Calculates: sum(vec) of integer vector
function rsum(vec : T_REALVEC) return real; -- Calculates: sum(vec) of real vector
--+ Conversions ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- to integer: to_int
function to_int(bool : BOOLEAN; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER;
function to_int(sl : STD_LOGIC; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER;
-- to std_logic: to_sl
function to_sl(Value : BOOLEAN) return STD_LOGIC;
function to_sl(Value : CHARACTER) return STD_LOGIC;
-- to std_logic_vector: to_slv
function to_slv(Value : NATURAL; Size : POSITIVE) return STD_LOGIC_VECTOR; -- short for std_logic_vector(to_unsigned(Value, Size))
-- TODO: comment
function to_index(slv : UNSIGNED; max : NATURAL := 0) return INTEGER;
function to_index(slv : STD_LOGIC_VECTOR; max : NATURAL := 0) return INTEGER;
-- is_*
function is_sl(c : CHARACTER) return BOOLEAN;
--+ Basic Vector Utilities +++++++++++++++++++++++++++++++++++++++++++++++++
-- Aggregate functions
function slv_or (vec : STD_LOGIC_VECTOR) return STD_LOGIC;
function slv_nor (vec : STD_LOGIC_VECTOR) return STD_LOGIC;
function slv_and (vec : STD_LOGIC_VECTOR) return STD_LOGIC;
function slv_nand(vec : STD_LOGIC_VECTOR) return STD_LOGIC;
function slv_xor (vec : std_logic_vector) return std_logic;
-- NO slv_xnor! This operation would not be well-defined as
-- not xor(vec) /= vec_{n-1} xnor ... xnor vec_1 xnor vec_0 iff n is odd.
-- Reverses the elements of the passed Vector.
--
-- @synthesis supported
--
function reverse(vec : std_logic_vector) return std_logic_vector;
function reverse(vec : bit_vector) return bit_vector;
function reverse(vec : unsigned) return unsigned;
-- scale a value into a range [Minimum, Maximum]
function scale(Value : INTEGER; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function scale(Value : REAL; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL;
-- Resizes the vector to the specified length. The adjustment is make on
-- on the 'high end of the vector. The 'low index remains as in the argument.
-- If the result vector is larger, the extension uses the provided fill value
-- (default: '0').
-- Use the resize functions of the numeric_std package for value-preserving
-- resizes of the signed and unsigned data types.
--
-- @synthesis supported
--
function resize(vec : bit_vector; length : natural; fill : bit := '0')
return bit_vector;
function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0')
return std_logic_vector;
-- Shift the index range of a vector by the specified offset.
function move(vec : std_logic_vector; ofs : integer) return std_logic_vector;
-- Shift the index range of a vector making vec'low = 0.
function movez(vec : std_logic_vector) return std_logic_vector;
function ascend(vec : std_logic_vector) return std_logic_vector;
function descend(vec : std_logic_vector) return std_logic_vector;
-- Least-Significant Set Bit (lssb):
-- Computes a vector of the same length as the argument with
-- at most one bit set at the rightmost '1' found in arg.
--
-- @synthesis supported
--
function lssb(arg : std_logic_vector) return std_logic_vector;
function lssb(arg : bit_vector) return bit_vector;
-- Returns the index of the least-significant set bit.
--
-- @synthesis supported
--
function lssb_idx(arg : std_logic_vector) return integer;
function lssb_idx(arg : bit_vector) return integer;
-- Most-Significant Set Bit (mssb): computes a vector of the same length
-- with at most one bit set at the leftmost '1' found in arg.
function mssb(arg : std_logic_vector) return std_logic_vector;
function mssb(arg : bit_vector) return bit_vector;
function mssb_idx(arg : std_logic_vector) return integer;
function mssb_idx(arg : bit_vector) return integer;
-- Swap sub vectors in vector (endian reversal)
function swap(slv : STD_LOGIC_VECTOR; Size : POSITIVE) return STD_LOGIC_VECTOR;
-- generate bit masks
function genmask_high(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR;
function genmask_low(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR;
--+ Encodings ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- One-Hot-Code to Binary-Code.
function onehot2bin(onehot : std_logic_vector) return unsigned;
-- Converts Gray-Code into Binary-Code.
--
-- @synthesis supported
--
function gray2bin (gray_val : std_logic_vector) return std_logic_vector;
-- Binary-Code to One-Hot-Code
function bin2onehot(value : std_logic_vector) return std_logic_vector;
-- Binary-Code to Gray-Code
function bin2gray(value : std_logic_vector) return std_logic_vector;
end package;
package body utils is
-- Environment
-- ==========================================================================
function is_simulation return boolean is
variable ret : boolean;
begin
ret := false;
--synthesis translate_off
if Is_X('X') then ret := true; end if;
--synthesis translate_on
return ret;
end function;
-- deferred constant assignment
constant SIMULATION : BOOLEAN := is_simulation;
-- Divisions: div_*
function div_ceil(a : NATURAL; b : POSITIVE) return NATURAL is -- calculates: ceil(a / b)
begin
return (a + (b - 1)) / b;
end function;
-- Power functions: *_pow2
-- ==========================================================================
-- is input a power of 2?
function is_pow2(int : NATURAL) return BOOLEAN is
begin
return ceil_pow2(int) = int;
end function;
-- round to next power of 2
function ceil_pow2(int : NATURAL) return POSITIVE is
begin
return 2 ** log2ceil(int);
end function;
-- round to previous power of 2
function floor_pow2(int : NATURAL) return NATURAL is
variable temp : UNSIGNED(30 downto 0);
begin
temp := to_unsigned(int, 31);
for i in temp'range loop
if (temp(i) = '1') then
return 2 ** i;
end if;
end loop;
return 0;
end function;
-- Logarithms: log*ceil*
-- ==========================================================================
function log2ceil(arg : positive) return natural is
variable tmp : positive;
variable log : natural;
begin
if arg = 1 then return 0; end if;
tmp := 1;
log := 0;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
function log2ceilnz(arg : positive) return positive is
begin
return imax(1, log2ceil(arg));
end function;
function log10ceil(arg : positive) return natural is
variable tmp : positive;
variable log : natural;
begin
if arg = 1 then return 0; end if;
tmp := 1;
log := 0;
while arg > tmp loop
tmp := tmp * 10;
log := log + 1;
end loop;
return log;
end function;
function log10ceilnz(arg : positive) return positive is
begin
return imax(1, log10ceil(arg));
end function;
-- if-then-else (ite)
-- ==========================================================================
function ite(cond : BOOLEAN; value1 : BOOLEAN; value2 : BOOLEAN) return BOOLEAN is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : INTEGER; value2 : INTEGER) return INTEGER is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : REAL; value2 : REAL) return REAL is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : STD_LOGIC; value2 : STD_LOGIC) return STD_LOGIC is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : BIT_VECTOR; value2 : BIT_VECTOR) return BIT_VECTOR is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : CHARACTER; value2 : CHARACTER) return CHARACTER is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
-- *min / *max / *sum
-- ==========================================================================
function imin(arg1 : integer; arg2 : integer) return integer is
begin
if arg1 < arg2 then return arg1; end if;
return arg2;
end function;
-- function rmin(arg1 : real; arg2 : real) return real is
-- begin
-- if arg1 < arg2 then return arg1; end if;
-- return arg2;
-- end function;
function imin(vec : T_INTVEC) return INTEGER is
variable Result : INTEGER;
begin
Result := INTEGER'high;
for i in vec'range loop
if (vec(I) < Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function imin(vec : T_NATVEC) return NATURAL is
variable Result : NATURAL;
begin
Result := NATURAL'high;
for i in vec'range loop
if (vec(I) < Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function imin(vec : T_POSVEC) return POSITIVE is
variable Result : POSITIVE;
begin
Result := POSITIVE'high;
for i in vec'range loop
if (vec(I) < Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function rmin(vec : T_REALVEC) return REAL is
variable Result : REAL;
begin
Result := REAL'high;
for i in vec'range loop
if vec(i) < Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function imax(arg1 : integer; arg2 : integer) return integer is
begin
if arg1 > arg2 then return arg1; end if;
return arg2;
end function;
-- function rmax(arg1 : real; arg2 : real) return real is
-- begin
-- if arg1 > arg2 then return arg1; end if;
-- return arg2;
-- end function;
function imax(vec : T_INTVEC) return INTEGER is
variable Result : INTEGER;
begin
Result := INTEGER'low;
for i in vec'range loop
if (vec(I) > Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function imax(vec : T_NATVEC) return NATURAL is
variable Result : NATURAL;
begin
Result := NATURAL'low;
for i in vec'range loop
if (vec(I) > Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function imax(vec : T_POSVEC) return POSITIVE is
variable Result : POSITIVE;
begin
Result := POSITIVE'low;
for i in vec'range loop
if (vec(I) > Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function rmax(vec : T_REALVEC) return REAL is
variable Result : REAL;
begin
Result := REAL'low;
for i in vec'range loop
if vec(i) > Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function isum(vec : T_INTVEC) return INTEGER is
variable Result : INTEGER;
begin
Result := 0;
for i in vec'range loop
Result := Result + vec(i);
end loop;
return Result;
end function;
function isum(vec : T_NATVEC) return NATURAL is
variable Result : NATURAL;
begin
Result := 0;
for i in vec'range loop
Result := Result + vec(I);
end loop;
return Result;
end function;
function isum(vec : T_POSVEC) return natural is
variable Result : natural;
begin
Result := 0;
for i in vec'range loop
Result := Result + vec(I);
end loop;
return Result;
end function;
function rsum(vec : T_REALVEC) return REAL is
variable Result : REAL;
begin
Result := 0.0;
for i in vec'range loop
Result := Result + vec(i);
end loop;
return Result;
end function;
-- Vector aggregate functions: slv_*
-- ==========================================================================
function slv_or(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
variable Result : STD_LOGIC;
begin
Result := '0';
for i in vec'range loop
Result := Result or vec(i);
end loop;
return Result;
end function;
function slv_nor(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
begin
return not slv_or(vec);
end function;
function slv_and(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
variable Result : STD_LOGIC;
begin
Result := '1';
for i in vec'range loop
Result := Result and vec(i);
end loop;
return Result;
end function;
function slv_nand(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
begin
return not slv_and(vec);
end function;
function slv_xor(vec : std_logic_vector) return std_logic is
variable res : std_logic;
begin
res := '0';
for i in vec'range loop
res := res xor vec(i);
end loop;
return res;
end slv_xor;
-- Convert to integer: to_int
function to_int(bool : BOOLEAN; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER is
begin
return ite(bool, one, zero);
end function;
function to_int(sl : STD_LOGIC; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER is
begin
if (sl = '1') then
return one;
end if;
return zero;
end function;
-- Convert to bit: to_sl
-- ==========================================================================
function to_sl(Value : BOOLEAN) return STD_LOGIC is
begin
return ite(Value, '1', '0');
end function;
function to_sl(Value : CHARACTER) return STD_LOGIC is
begin
case Value is
when 'U' => return 'U';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when OTHERS => return 'X';
end case;
end function;
-- Convert to vector: to_slv
-- ==========================================================================
-- short for std_logic_vector(to_unsigned(Value, Size))
-- the return value is guaranteed to have the range (Size-1 downto 0)
function to_slv(Value : NATURAL; Size : POSITIVE) return STD_LOGIC_VECTOR is
constant res : std_logic_vector(Size-1 downto 0) := std_logic_vector(to_unsigned(Value, Size));
begin
return res;
end function;
function to_index(slv : UNSIGNED; max : NATURAL := 0) return INTEGER is
variable res : integer;
begin
if (slv'length = 0) then return 0; end if;
res := to_integer(slv);
if SIMULATION and max > 0 then
res := imin(res, max);
end if;
return res;
end function;
function to_index(slv : STD_LOGIC_VECTOR; max : NATURAL := 0) return INTEGER is
begin
return to_index(unsigned(slv), max);
end function;
-- is_*
-- ==========================================================================
function is_sl(c : CHARACTER) return BOOLEAN is
begin
case c is
when 'U'|'X'|'0'|'1'|'Z'|'W'|'L'|'H'|'-' => return true;
when OTHERS => return false;
end case;
end function;
-- Reverse vector elements
function reverse(vec : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(vec'range);
begin
for i in vec'low to vec'high loop
res(vec'low + (vec'high-i)) := vec(i);
end loop;
return res;
end function;
function reverse(vec : bit_vector) return bit_vector is
variable res : bit_vector(vec'range);
begin
res := to_bitvector(reverse(to_stdlogicvector(vec)));
return res;
end reverse;
function reverse(vec : unsigned) return unsigned is
begin
return unsigned(reverse(std_logic_vector(vec)));
end function;
-- Swap sub vectors in vector
-- ==========================================================================
function swap(slv : STD_LOGIC_VECTOR; Size : POSITIVE) return STD_LOGIC_VECTOR IS
CONSTANT SegmentCount : NATURAL := slv'length / Size;
variable FromH : NATURAL;
variable FromL : NATURAL;
variable ToH : NATURAL;
variable ToL : NATURAL;
variable Result : STD_LOGIC_VECTOR(slv'length - 1 DOWNTO 0);
begin
for i in 0 TO SegmentCount - 1 loop
FromH := ((I + 1) * Size) - 1;
FromL := I * Size;
ToH := ((SegmentCount - I) * Size) - 1;
ToL := (SegmentCount - I - 1) * Size;
Result(ToH DOWNTO ToL) := slv(FromH DOWNTO FromL);
end loop;
return Result;
end function;
-- generate bit masks
-- ==========================================================================
function genmask_high(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR IS
begin
if (Bits = 0) then
return (MaskLength - 1 DOWNTO 0 => '0');
else
return (MaskLength - 1 DOWNTO MaskLength - Bits + 1 => '1') & (MaskLength - Bits DOWNTO 0 => '0');
end if;
end function;
function genmask_low(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR is
begin
if (Bits = 0) then
return (MaskLength - 1 DOWNTO 0 => '0');
else
return (MaskLength - 1 DOWNTO Bits => '0') & (Bits - 1 DOWNTO 0 => '1');
end if;
end function;
-- binary encoding conversion functions
-- ==========================================================================
-- One-Hot-Code to Binary-Code
function onehot2bin(onehot : std_logic_vector) return unsigned is
variable res : unsigned(log2ceilnz(onehot'high+1)-1 downto 0);
variable chk : natural;
begin
res := (others => '0');
chk := 0;
for i in onehot'range loop
if onehot(i) = '1' then
res := res or to_unsigned(i, res'length);
chk := chk + 1;
end if;
end loop;
if SIMULATION and chk /= 1 then
report "Broken 1-Hot-Code with "&integer'image(chk)&" bits set."
severity error;
end if;
return res;
end onehot2bin;
-- Gray-Code to Binary-Code
function gray2bin(gray_val : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(gray_val'range);
begin -- gray2bin
res(res'left) := gray_val(gray_val'left);
for i in res'left-1 downto res'right loop
res(i) := res(i+1) xor gray_val(i);
end loop;
return res;
end gray2bin;
-- Binary-Code to One-Hot-Code
function bin2onehot(value : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(2**value'length - 1 downto 0);
begin
result := (others => '0');
result(to_index(value, 0)) := '1';
return result;
end function;
-- Binary-Code to Gray-Code
function bin2gray(value : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(value'range);
begin
result(result'left) := value(value'left);
for i in (result'left - 1) downto result'right loop
result(i) := value(i) xor value(i + 1);
end loop;
return result;
end function;
-- bit searching / bit indices
-- ==========================================================================
-- Least-Significant Set Bit (lssb): computes a vector of the same length with at most one bit set at the rightmost '1' found in arg.
function lssb(arg : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(arg'range);
begin
res := arg and std_logic_vector(unsigned(not arg)+1);
return res;
end function;
function lssb(arg : bit_vector) return bit_vector is
variable res : bit_vector(arg'range);
begin
res := to_bitvector(lssb(to_stdlogicvector(arg)));
return res;
end lssb;
-- Most-Significant Set Bit (mssb): computes a vector of the same length with at most one bit set at the leftmost '1' found in arg.
function mssb(arg : std_logic_vector) return std_logic_vector is
begin
return reverse(lssb(reverse(arg)));
end function;
function mssb(arg : bit_vector) return bit_vector is
begin
return reverse(lssb(reverse(arg)));
end mssb;
-- Index of lssb
function lssb_idx(arg : std_logic_vector) return integer is
begin
return to_integer(onehot2bin(lssb(arg)));
end function;
function lssb_idx(arg : bit_vector) return integer is
variable slv : std_logic_vector(arg'range);
begin
slv := to_stdlogicvector(arg);
return lssb_idx(slv);
end lssb_idx;
-- Index of mssb
function mssb_idx(arg : std_logic_vector) return integer is
begin
return to_integer(onehot2bin(mssb(arg)));
end function;
function mssb_idx(arg : bit_vector) return integer is
variable slv : std_logic_vector(arg'range);
begin
slv := to_stdlogicvector(arg);
return mssb_idx(slv);
end mssb_idx;
-- scale a value into a given range
function scale(Value : INTEGER; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
return scale(real(Value), Minimum, Maximum, RoundingStyle);
end function;
function scale(Value : REAL; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
variable Result : REAL;
begin
if (Maximum < Minimum) then
return INTEGER'low;
else
Result := real(Value) * ((real(Maximum) + 0.5) - (real(Minimum) - 0.5)) + (real(Minimum) - 0.5);
case RoundingStyle is
when ROUND_TO_NEAREST => return integer(round(Result));
when ROUND_TO_ZERO => report "scale: unsupported RoundingStyle." severity FAILURE;
when ROUND_TO_INF => report "scale: unsupported RoundingStyle." severity FAILURE;
when ROUND_UP => return integer(ceil(Result));
when ROUND_DOWN => return integer(floor(Result));
when others => report "scale: unsupported RoundingStyle." severity FAILURE;
end case;
end if;
end function;
function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL is
begin
if (Maximum < Minimum) then
return REAL'low;
else
return Value * (Maximum - Minimum) + Minimum;
end if;
end function;
function resize(vec : bit_vector; length : natural; fill : bit := '0') return bit_vector is
constant high2b : natural := vec'low+length-1;
constant highcp : natural := imin(vec'high, high2b);
variable res_up : bit_vector(vec'low to high2b);
variable res_dn : bit_vector(high2b downto vec'low);
begin
if vec'ascending then
res_up := (others => fill);
res_up(vec'low to highcp) := vec(vec'low to highcp);
return res_up;
else
res_dn := (others => fill);
res_dn(highcp downto vec'low) := vec(highcp downto vec'low);
return res_dn;
end if;
end resize;
function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector is
constant high2b : natural := vec'low+length-1;
constant highcp : natural := imin(vec'high, high2b);
variable res_up : std_logic_vector(vec'low to high2b);
variable res_dn : std_logic_vector(high2b downto vec'low);
begin
if vec'ascending then
res_up := (others => fill);
res_up(vec'low to highcp) := vec(vec'low to highcp);
return res_up;
else
res_dn := (others => fill);
res_dn(highcp downto vec'low) := vec(highcp downto vec'low);
return res_dn;
end if;
end resize;
-- Move vector boundaries
-- ==========================================================================
function move(vec : std_logic_vector; ofs : integer) return std_logic_vector is
variable res_up : std_logic_vector(vec'low +ofs to vec'high+ofs);
variable res_dn : std_logic_vector(vec'high+ofs downto vec'low +ofs);
begin
if vec'ascending then
res_up := vec;
return res_up;
else
res_dn := vec;
return res_dn;
end if;
end move;
function movez(vec : std_logic_vector) return std_logic_vector is
begin
return move(vec, -vec'low);
end movez;
function ascend(vec : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(vec'low to vec'high);
begin
res := vec;
return res;
end ascend;
function descend(vec : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(vec'high downto vec'low);
begin
res := vec;
return res;
end descend;
end package body;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_04.vhd | 4 | 2140 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
-- not in book
use work.serial_interface_defs.all;
entity microcontroller is
end entity microcontroller;
-- end not in book
library ieee; use ieee.std_logic_1164.all;
architecture structure of microcontroller is
use work.serial_interface_defs.serial_interface;
-- . . . -- declarations of other components, signals, etc
-- not in book
signal buffered_phi1, buffered_phi2, serial_a_select : std_logic;
signal internal_addr : std_logic_vector(1 downto 0);
signal internal_data_bus : data_vector;
signal serial_a_int_req, rx_data_a, tx_data_a : std_logic;
-- end not in book
begin
serial_a : component serial_interface
port map ( clock_phi1 => buffered_phi1,
clock_phi2 => buffered_phi2,
serial_select => serial_a_select,
reg_address => internal_addr(1 downto 0),
data => internal_data_bus,
interrupt_request => serial_a_int_req,
rx_serial_data => rx_data_a,
tx_serial_data => tx_data_a );
-- . . . -- other component instances
end architecture structure;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc240.vhd | 4 | 1699 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc240.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00240ent IS
END c03s01b02x00p04n01i00240ent;
ARCHITECTURE c03s01b02x00p04n01i00240arch OF c03s01b02x00p04n01i00240ent IS
type a is range (1+1) to 10;
type b is range (10+1) to 100;
type c is range a to b;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00240 - The bounds in the range constraint are not locally static expressions of type integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00240arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2194.vhd | 4 | 1836 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2194.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p01n02i02194ent IS
END c07s02b00x00p01n02i02194ent;
ARCHITECTURE c07s02b00x00p01n02i02194arch OF c07s02b00x00p01n02i02194ent IS
BEGIN
TESTING: PROCESS
type A_ARRAY is array (1 to 2) of CHARACTER;
variable I : INTEGER;
variable R : REAL;
variable B : BOOLEAN;
variable A : A_ARRAY;
BEGIN
I := I mod + I; -- Failure_here
-- SYNTAX ERROR: signed operator cannot follow multiplying operator.
assert FALSE
report "***FAILED TEST: c07s02b00x00p01n02i02194 - Signed operand cannot follow a mutiplying operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p01n02i02194arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/vector.d/add_134.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_134 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_134;
architecture augh of add_134 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug040/cmp_887.vhd | 2 | 378 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_887 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_887;
architecture augh of cmp_887 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2025.vhd | 4 | 1767 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2025.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02025ent IS
END c07s02b04x00p01n01i02025ent;
ARCHITECTURE c07s02b04x00p01n01i02025arch OF c07s02b04x00p01n01i02025ent IS
BEGIN
TESTING: PROCESS
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
variable LOGICV : LOGIC_SWITCH := '0';
BEGIN
LOGICV := LOGICV + '0';
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02025 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02025arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1423.vhd | 4 | 1963 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1423.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s06b00x00p05n01i01423ent IS
END c08s06b00x00p05n01i01423ent;
ARCHITECTURE c08s06b00x00p05n01i01423arch OF c08s06b00x00p05n01i01423ent IS
procedure check (signal x : in integer;
signal kkk : out integer ) is
begin
if (x = 0) then
kkk <= 5;
wait for 1 ns;
end if;
end check;
signal k : integer := 0;
signal kk : integer := 0;
BEGIN
TESTING : PROCESS
BEGIN
check (k,kk);
assert NOT(kk = 5)
report "***PASSED TEST: c08s06b00x00p05n01i01423"
severity NOTE;
assert (kk = 5)
report "***FAILED TEST: c08s06b00x00p05n01i01423 - No actual parmeter is required for a formal parmeter with a default expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s06b00x00p05n01i01423arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue263/mac.vhdl | 2 | 3289 | library ieee;
use ieee.std_logic_1164.all, ieee.fixed_pkg.all;
use ieee.math_complex.all;
entity mac is
port( clk, reset : in std_ulogic;
x_real : in u_sfixed(0 downto -15);-- real and imaginary part of the two input data sequences
x_imag : in u_sfixed(0 downto -15);
y_real : in u_sfixed(0 downto -15);
y_imag : in u_sfixed(0 downto -15);
s_real : out u_sfixed(0 downto -15); --real and imaginary parts of accumulated sum
s_imag : out u_sfixed(0 downto -15);
ovf : out std_ulogic); --overflow flag
end entity mac;
-- Behavioral model of MAC algorithm allows for focus on the algorithm without being distracted
-- by other details at this erly design stage.
architecture behavioral of mac is
signal x_complex, y_complex, s_complex : complex;
begin
x_complex <= ( to_real(x_real), to_real(x_imag) );
y_complex <= ( to_real(y_real), to_real(y_imag) );
behavior : process (clk) is
variable input_x, input_y : complex := (0.0, 0.0);
variable real_part_product_1, real_part_product_2,
imag_part_product_1, imag_part_product_2 : real := 0.0;
variable product, sum : complex := (0.0, 0.0);
variable real_accumulator_ovf,
imag_accumulator_ovf : boolean := false;
begin
if rising_edge(clk) then
-- Work from the end of the pipeline back to the start,
-- so as not to overwrite previosu results from the pipeline
-- registers before they are even used.
-- Update accumulator and generate outputs.
if reset then
sum := (0.0, 0.0);
real_accumulator_ovf := false;
imag_accumulator_ovf := false;
else
sum := product + sum;
real_accumulator_ovf := real_accumulator_ovf
or sum.re < -16.0
or sum.re >= +16.0;
imag_accumulator_ovf := imag_accumulator_ovf
or sum.im < -16.0
or sum.im >= +16.0;
end if;
s_complex <= sum;
ovf <= '1';
-- ovf <= '1' when (real_accumulator_ovf or imag_accumulator_ovf
-- or sum.re < -1.0 or sum.re >= +1.0
-- or sum.im < -1.0 or sum.im >= +1.0 ) else '0';
-- Update product registers
product.re := real_part_product_1 - real_part_product_2;
product.im := imag_part_product_1 + imag_part_product_2;
-- Update partial product registers
-- (actually with the full product).
real_part_product_1 := input_x.re * input_y.re;
real_part_product_2 := input_x.im * input_y.im;
imag_part_product_1 := input_x.re * input_y.re;
imag_part_product_2 := input_x.im * input_y.im;
-- Update input registers using MAC inputs
input_x := x_complex;
input_y := y_complex;
end if;
end process behavior;
s_real <= to_sfixed(s_complex.re, s_real);
s_imag <= to_sfixed(s_complex.im, s_imag);
end architecture behavioral;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/ticket43/file2.vhd | 3 | 266 | use work.pkg.all;
package body other_pkg is
procedure other_proc(variable rec : inout rec_t) is
begin
proc(default_prot, rec);
end;
procedure other_proc(variable rec : inout other_rec_t) is
begin
proc(default_prot, rec);
end;
end package body;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2317.vhd | 4 | 1684 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2317.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02317ent IS
END c07s02b07x00p01n01i02317ent;
ARCHITECTURE c07s02b07x00p01n01i02317arch OF c07s02b07x00p01n01i02317ent IS
BEGIN
TESTING: PROCESS
type BYTE is array(7 downto 0) of BIT;
variable BYTEV : BYTE;
BEGIN
BYTEV := ABS BYTEV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02317 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02317arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug040/cmp_880.vhd | 2 | 378 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_880 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_880;
architecture augh of cmp_880 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc976.vhd | 4 | 1780 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc976.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00976ent IS
END c06s03b00x00p05n01i00976ent;
ARCHITECTURE c06s03b00x00p05n01i00976arch OF c06s03b00x00p05n01i00976ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
variable V1: R1 ;
constant V3: BOOLEAN := TRUE;
variable V10: BOOLEAN;
BEGIN
V10 := V1.V3;
-- SEMANTIC ERROR: NO SUCH RECORD ELEMENT;
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00976 - Illegal record element name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00976arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-2.vhd | 4 | 1127 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity clock_gen is
end entity clock_gen;
architecture test of clock_gen is
constant T_pw : time := 10 ns;
signal clk : bit;
begin
-- code from book
clock_gen : process is
begin
clk <= '1' after T_pw, '0' after 2*T_pw;
wait for 2*T_pw;
end process clock_gen;
-- end code from book
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2761.vhd | 4 | 2093 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2761.vhd,v 1.1.1.1 2001-08-22 18:20:52 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p05n01i02761ent IS
END c13s07b00x00p05n01i02761ent;
-- Dale Martin modified this file to make the bit string literal comparisons
-- VHDL '93 compliant, by qualifying them with bit_string_literal'(
ARCHITECTURE c13s07b00x00p05n01i02761arch OF c13s07b00x00p05n01i02761ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( ( bit_vector'(B"01_111_101") = B"0111_1101" )
and ( bit_vector'(O"17_5") = O"1_75")
and ( bit_vector'(X"7D") = X"7_D"))
report "***PASSED TEST: c13s07b00x00p05n01i02761"
severity NOTE;
assert ( ( bit_vector'(B"01_111_101") = B"0111_1101" )
and ( bit_vector'(O"17_5")=O"1_75")
and ( bit_vector'(X"7D")=X"7_D"))
report "***FAILED TEST: c13s07b00x00p05n01i02761 - Underline character should not affect the value of the bit string literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p05n01i02761arch;
| gpl-2.0 |
mati75/ghdl | libraries/ieee2008/std_logic_textio.vhdl | 4 | 1988 | -- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard multivalue logic package
-- : (STD_LOGIC_TEXTIO package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages is provided as a replacement for non-standard
-- : implementations of the package provided by implementers of
-- : previous versions of this standard. The declarations that
-- : appeared in those non-standard implementations appear in the
-- : package STD_LOGIC_1164 in this standard.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
PACKAGE std_logic_textio IS
-- This package is empty - see notes above.
END PACKAGE std_logic_textio;
| gpl-2.0 |
mati75/ghdl | libraries/vital95/vital_timing.vhdl | 6 | 46973 | -------------------------------------------------------------------------------
-- Title : Standard VITAL TIMING Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, attributes, constants,
-- : functions and procedures for use in developing ASIC models.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0
-- #204 - Output mapping prior to glitch detection
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE VITAL_Timing IS
TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0X, trx1, tr1x, trx0, trxz, trzx);
SUBTYPE VitalDelayType IS TIME;
TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10)
OF TIME;
TYPE VitalDelayType01Z IS ARRAY (VitalTransitionType RANGE tr01 to trz0)
OF TIME;
TYPE VitalDelayType01ZX IS ARRAY (VitalTransitionType RANGE tr01 to trzx)
OF TIME;
TYPE VitalDelayArrayType IS ARRAY (NATURAL RANGE <>) OF VitalDelayType;
TYPE VitalDelayArrayType01 IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01;
TYPE VitalDelayArrayType01Z IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01Z;
TYPE VitalDelayArrayType01ZX IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01ZX;
-- ----------------------------------------------------------------------
-- **********************************************************************
-- ----------------------------------------------------------------------
CONSTANT VitalZeroDelay : VitalDelayType := 0 ns;
CONSTANT VitalZeroDelay01 : VitalDelayType01 := ( 0 ns, 0 ns );
CONSTANT VitalZeroDelay01Z : VitalDelayType01Z := ( OTHERS => 0 ns );
CONSTANT VitalZeroDelay01ZX : VitalDelayType01ZX := ( OTHERS => 0 ns );
---------------------------------------------------------------------------
-- examples of usage:
---------------------------------------------------------------------------
-- tpd_CLK_Q : VitalDelayType := 5 ns;
-- tpd_CLK_Q : VitalDelayType01 := (tr01 => 2 ns, tr10 => 3 ns);
-- tpd_CLK_Q : VitalDelayType01Z := ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns );
-- tpd_CLK_Q : VitalDelayArrayType(0 to 1)
-- := (0 => 5 ns, 1 => 6 ns);
-- tpd_CLK_Q : VitalDelayArrayType01(0 to 1)
-- := (0 => (tr01 => 2 ns, tr10 => 3 ns),
-- 1 => (tr01 => 2 ns, tr10 => 3 ns));
-- tpd_CLK_Q : VitalDelayArrayType01Z(0 to 1)
-- := (0 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ),
-- 1 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ));
---------------------------------------------------------------------------
-- TRUE if the model is LEVEL0 | LEVEL1 compliant
ATTRIBUTE VITAL_Level0 : BOOLEAN;
ATTRIBUTE VITAL_Level1 : BOOLEAN;
SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0);
SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0);
SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0);
-- Types for strength mapping of outputs
TYPE VitalOutputMapType IS ARRAY ( std_ulogic ) OF std_ulogic;
TYPE VitalResultMapType IS ARRAY ( UX01 ) OF std_ulogic;
TYPE VitalResultZMapType IS ARRAY ( UX01Z ) OF std_ulogic;
CONSTANT VitalDefaultOutputMap : VitalOutputMapType
:= "UX01ZWLH-";
CONSTANT VitalDefaultResultMap : VitalResultMapType
:= ( 'U', 'X', '0', '1' );
CONSTANT VitalDefaultResultZMap : VitalResultZMapType
:= ( 'U', 'X', '0', '1', 'Z' );
-- Types for fields of VitalTimingDataType
TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME;
TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT;
TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN;
TYPE VitalBoolArrayPT IS ACCESS VitalBoolArrayT;
TYPE VitalLogicArrayPT IS ACCESS std_logic_vector;
TYPE VitalTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
FUNCTION VitalTimingDataInit RETURN VitalTimingDataType;
-- type for internal data of VitalPeriodPulseCheck
TYPE VitalPeriodDataType IS RECORD
Last : X01;
Rise : TIME;
Fall : TIME;
NotFirstFlag : BOOLEAN;
END RECORD;
CONSTANT VitalPeriodDataInit : VitalPeriodDataType
:= ('X', 0 ns, 0 ns, FALSE );
-- Type for specifying the kind of Glitch handling to use
TYPE VitalGlitchKindType IS (OnEvent,
OnDetect,
VitalInertial,
VitalTransport);
TYPE VitalGlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
LastValue : std_ulogic;
END RECORD;
TYPE VitalGlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF VitalGlitchDataType;
-- PathTypes: for handling simple PathDelay info
TYPE VitalPathType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01Type IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01ZType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01Z;-- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
-- For representing multiple paths to an output
TYPE VitalPathArrayType IS ARRAY (NATURAL RANGE <> ) OF VitalPathType;
TYPE VitalPathArray01Type IS ARRAY (NATURAL RANGE <> ) OF VitalPath01Type;
TYPE VitalPathArray01ZType IS ARRAY (NATURAL RANGE <> ) OF VitalPath01ZType;
TYPE VitalTableSymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S' -- steady value
);
SUBTYPE VitalEdgeSymbolType IS VitalTableSymbolType RANGE '/' TO '*';
-- ------------------------------------------------------------------------
--
-- Function Name: VitalExtendToFillDelay
--
-- Description: A six element array of delay values of type
-- VitalDelayType01Z is returned when a 1, 2 or 6
-- element array is given. This function will convert
-- VitalDelayType and VitalDelayType01 delay values into
-- a VitalDelayType01Z type following these rules:
--
-- When a VitalDelayType is passed, all six transition
-- values are assigned the input value. When a
-- VitalDelayType01 is passed, the 01 transitions are
-- assigned to the 01, 0Z and Z1 transitions and the 10
-- transitions are assigned to 10, 1Z and Z0 transition
-- values. When a VitalDelayType01Z is passed, the values
-- are kept as is.
--
-- The function is overloaded based on input type.
--
-- There is no function to fill a 12 value delay
-- type.
--
-- Arguments:
--
-- IN Type Description
-- Delay A one, two or six delay value Vital-
-- DelayType is passed and a six delay,
-- VitalDelayType01Z, item is returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- VitalDelayType01Z
--
-- -------------------------------------------------------------------------
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalDelayType01Z;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalCalcDelay
--
-- Description: This function accepts a 1, 2 or 6 value delay and
-- chooses the correct delay time to delay the NewVal
-- signal. This function is overloaded based on the
-- delay type passed. The function returns a single value
-- of time.
--
-- This function is provided for Level 0 models in order
-- to calculate the delay which should be applied
-- for the passed signal. The delay selection is performed
-- using the OldVal and the NewVal to determine the
-- transition to select. The default value of OldVal is X.
--
-- This function cannot be used in a Level 1 model since
-- the VitalPathDelay routines perform the delay path
-- selection and output driving function.
--
-- Arguments:
--
-- IN Type Description
-- NewVal New value of the signal to be
-- assigned
-- OldVal Previous value of the signal.
-- Default value is 'X'
-- Delay The delay structure from which to
-- select the appropriate delay. The
-- function overload is based on the
-- type of delay passed. In the case of
-- the single delay, VitalDelayType, no
-- selection is performed, since there
-- is only one value to choose from.
-- For the other cases, the transition
-- from the old value to the new value
-- decide the value returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- Time The time value selected from the
-- Delay INPUT is returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN TIME;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPathDelay
--
-- Description: VitalPathDelay is the Level 1 routine used to select
-- the propagation delay path and schedule a new output
-- value.
--
-- For single and dual delay values, VitalDelayType and
-- VitalDelayType01 are used. The output value is
-- scheduled with a calculated delay without strength
-- modification.
--
-- For the six delay value, VitalDelayType01Z, the output
-- value is scheduled with a calculated delay. The drive
-- strength can be modified to handle weak signal strengths
-- to model tri-state devices, pull-ups and pull-downs as
-- an example.
--
-- The correspondence between the delay type and the
-- path delay function is as follows:
--
-- Delay Type Path Type
--
-- VitalDelayType VitalPathDelay
-- VitalDelayType01 VitalPathDelay01
-- VitalDelayType01Z VitalPathDelay01Z
--
-- For each of these routines, the following capabilities
-- is provided:
--
-- o Transition dependent path delay selection
-- o User controlled glitch detection with the ability
-- to generate "X" on output and report the violation
-- o Control of the severity level for message generation
-- o Scheduling of the computed values on the specified
-- signal.
--
-- Selection of the appropriate path delay begins with the
-- candidate paths. The candidate paths are selected by
-- identifying the paths for which the PathCondition is
-- true. If there is a single candidate path, then that
-- delay is selected. If there is more than one candidate
-- path, then the shortest delay is selected using
-- transition dependent delay selection. If there is no
-- candidate paths, then the delay specified by the
-- DefaultDelay parameter to the path delay is used.
--
-- Once the delay is known, the output signal is then
-- scheduled with that delay. In the case of
-- VitalPathDelay01Z, an additional result mapping of
-- the output value is performed before scheduling. The
-- result mapping is performed after transition dependent
-- delay selection but before scheduling the final output.
--
-- In order to perform glitch detection, the user is
-- obligated to provide a variable of VitalGlitchDataType
-- for the propagation delay functions to use. The user
-- cannot modify or use this information.
--
-- Arguments:
--
-- IN Type Description
-- OutSignalName string The name of the output signal
-- OutTemp std_logic The new output value to be driven
-- Paths VitalPathArrayType A list of paths of VitalPathArray
-- VitalPathArrayType01 type. The VitalPathDelay routine
-- VitalPathArrayType01Z is overloaded based on the type
-- of constant passed in. With
-- VitalPathArrayType01Z, the
-- resulting output strengths can be
-- mapped.
-- DefaultDelay VitalDelayType The default delay can be changed
-- VitalDelayType01 from zero-delay to another set of
-- VitalDelayType01Z values.
-- Mode VitalGlitchKindType The value of this constant
-- selects the type of glitch
-- detection.
-- OnEvent Glitch on transition event
-- | OnDetect Glitch immediate on detection
-- | VitalInertial No glitch, use INERTIAL
-- assignment
-- | VitalTransport No glitch, use TRANSPORT
-- assignment
-- XOn BOOLEAN Control for generation of 'X' on
-- glitch. When TRUE, 'X's are
-- scheduled for glitches, otherwise
-- no are generated.
-- MsgOn BOOLEAN Control for message generation on
-- glitch detect. When TRUE,
-- glitches are reported, otherwise
-- they are not reported.
-- MsgSeverity SEVERITY_LEVEL The level at which the message,
-- or assertion, will be reported.
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the output
-- can be mapped to alternate
-- strengths to model tri-state
-- devices, pull-ups and pull-downs.
--
-- INOUT
-- GlitchData VitalGlitchDataType The internal data storage
-- variable required to detect
-- glitches.
--
-- OUT
-- OutSignal std_logic The output signal to be driven
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalPathDelay (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01 (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01Z (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT OutputMap : IN VitalOutputMapType
:= VitalDefaultOutputMap
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalWireDelay
--
-- Description: VitalWireDelay is used to delay an input signal.
-- The delay is selected from the input parameter passed.
-- The function is useful for back annotation of actual
-- net delays.
--
-- The function is overloaded to permit passing a delay
-- value for twire for VitalDelayType, VitalDelayType01
-- and VitalDelayType01Z. twire is a generic which can
-- be back annotated and must be constructed to follow
-- the SDF to generic mapping rules.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The input signal (port) to be
-- delayed.
-- twire VitalDelayType The delay value for which the input
-- VitalDelayType01 signal should be delayed. For Vital-
-- VitalDelayType01Z DelayType, the value is single value
-- passed. For VitalDelayType01 and
-- VitalDelayType01Z, the appropriate
-- delay value is selected by VitalCalc-
-- Delay.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The internal delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01Z
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSignalDelay
--
-- Description: The VitalSignalDelay procedure is called in a signal
-- delay block in the architecture to delay the
-- appropriate test or reference signal in order to
-- accommodate negative constraint checks.
--
-- The amount of delay is of type TIME and is a constant.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The signal to be delayed.
-- dly TIME The amount of time the signal is
-- delayed.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSignalDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT dly : IN TIME
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSetupHoldCheck
--
-- Description: The VitalSetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal. A vector and scalar form are provided.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- std_logic_vector
-- TestSignalName STRING Name of test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- with RefSignal
-- SetupHigh TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a setup violation.
-- SetupLow TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a setup violation.
-- HoldHigh TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a hold violation.
-- HoldLow TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events on
-- the RefSignal which match the edge
-- spec. are used as reference edges.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalSetupHoldCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalRecoveryRemovalCheck
--
-- Description: The VitalRecoveryRemovalCheck detects the presence of
-- a recovery or removal violation on the input test
-- signal with respect to the corresponding input reference
-- signal. It assumes non-negative values of setup and
-- hold timing constraints. The timing constraint is
-- specified through parameters representing the recovery
-- and removal times associated with a reference edge of
-- the reference signal. A flag indicates whether a test
-- signal is asserted when it is high or when it is low.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative recovery times result in
-- a delayed reference signal. Negative removal times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of TestSignal. The routine is
-- TestSignalName STRING Name of TestSignal
-- TestDelay TIME Model internal delay associated with
-- the TestSignal
-- RefSignal std_ulogic Value of RefSignal
-- RefSignalName STRING Name of RefSignal
-- RefDelay TIME Model internal delay associated with
-- the RefSignal
-- Recovery TIME A change to an unasserted value on
-- the asynchronous TestSignal must
-- precede reference edge (on RefSignal)
-- by at least this time.
-- Removal TIME An asserted condition must be present
-- on the asynchronous TestSignal for at
-- least the removal time following a
-- reference edge on RefSignal.
-- ActiveLow BOOLEAN A flag which indicates if TestSignal
-- is asserted when it is low - "0."
-- FALSE indicate that TestSignal is
-- asserted when it has a value "1."
-- CheckEnabled BOOLEAN The check in enabled when the value
-- is TRUE, otherwise the constraints
-- are not checked.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specifier. Events on
-- RefSignal will match the edge
-- specified.
-- HeaderMsg STRING A header message that will accompany
-- any assertion message.
-- XOn BOOLEAN When TRUE, the output Violation is
-- set to "X." When FALSE, it is always
-- "0."
-- MsgOn BOOLEAN When TRUE, violation messages are
-- output. When FALSE, no messages are
-- generated.
-- MsgSeverity SEVERITY_LEVEL Severity level of the asserted
-- message.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalRecoveryRemovalCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalRecoveryRemovalCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT Recovery : IN TIME := 0 ns;
CONSTANT Removal : IN TIME := 0 ns;
CONSTANT ActiveLow : IN BOOLEAN := TRUE;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum and maximum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- Period TIME Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh TIME Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow TIME Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- PeriodData VitalPeriodDataType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- ------------------------------------------------------------------------
PROCEDURE VitalPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT Period : IN TIME := 0 ns;
CONSTANT PulseWidthHigh : IN TIME := 0 ns;
CONSTANT PulseWidthLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
END VITAL_Timing;
| gpl-2.0 |
freecores/raggedstone | source/generate_pci32tlite/new_pci32tlite.vhd | 1 | 19658 | --+-------------------------------------------------------------------------------------------------+
--| |
--| File: pci32tlite.vhd |
--| |
--| Components: pcidec_new.vhd |
--| pciwbsequ.vhd |
--| pcidmux.vhd |
--| pciregs.vhd |
--| pcipargen.vhd |
--| -- Libs -- |
--| ona.vhd |
--| |
--| Description: TARGET PCI : |
--| |
--| * PCI Target 32 Bits |
--| * BAR0 32MByte address space |
--| * Whisbone compatible: D16, 32MB address space |
--| |
--+-------------------------------------------------------------------------------------------------+
--| |
--| Revision history : |
--| Date Version Author Description |
--| 2005-05-13 R00A00 PAU First alfa revision (eng) |
--| 2006-01-05 R00B00 MS inverted reset nres |
--| and added debug signals debug_init and debug_access | |
--| |
--| To do: |
--| |
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------+
--| |
--| Copyright (C) 2005 Peio Azkarate, [email protected] |
--| |
--| This source file may be used and distributed without |
--| restriction provided that this copyright statement is not |
--| removed from the file and that any derivative work contains |
--| the original copyright notice and the associated disclaimer. |
--| |
--| This source file is free software; you can redistribute it |
--| and/or modify it under the terms of the GNU Lesser General |
--| Public License as published by the Free Software Foundation; |
--| either version 2.1 of the License, or (at your option) any |
--| later version. |
--| |
--| This source is distributed in the hope that it will be |
--| useful, but WITHOUT ANY WARRANTY; without even the implied |
--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
--| PURPOSE. See the GNU Lesser General Public License for more |
--| details. |
--| |
--| You should have received a copy of the GNU Lesser General |
--| Public License along with this source; if not, download it |
--| from http://www.opencores.org/lgpl.shtml |
--| |
--+-----------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| LIBRARIES |
--+-----------------------------------------------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
--+-----------------------------------------------------------------------------+
--| ENTITY |
--+-----------------------------------------------------------------------------+
entity pci32tlite is
generic (
vendorID : std_logic_vector(15 downto 0) := x"10EE";
deviceID : std_logic_vector(15 downto 0) := x"0100";
revisionID : std_logic_vector(7 downto 0) := x"37";
subsystemID : std_logic_vector(15 downto 0) := x"1558";
subsystemvID : std_logic_vector(15 downto 0) := x"0480";
jcarr1ID : std_logic_vector(31 downto 0) := x"12345671";
jcarr2ID : std_logic_vector(31 downto 0) := x"12345672";
jcarr3ID : std_logic_vector(31 downto 0) := x"12345673";
jcarr4ID : std_logic_vector(31 downto 0) := x"12345674";
jcarr5ID : std_logic_vector(31 downto 0) := x"12345675";
jcarr6ID : std_logic_vector(31 downto 0) := x"12345676";
jcarr7ID : std_logic_vector(31 downto 0) := x"12345677";
jcarr8ID : std_logic_vector(31 downto 0) := x"12345678";
jcarr9ID : std_logic_vector(31 downto 0) := x"12345679";
jcarr10ID : std_logic_vector(31 downto 0) := x"12345680";
jcarr11ID : std_logic_vector(31 downto 0) := x"12345681";
jcarr12ID : std_logic_vector(31 downto 0) := x"12345682";
jcarr13ID : std_logic_vector(31 downto 0) := x"12345683";
jcarr14ID : std_logic_vector(31 downto 0) := x"12345684";
jcarr15ID : std_logic_vector(31 downto 0) := x"12345685";
jcarr16ID : std_logic_vector(31 downto 0) := x"12345686";
jcarr17ID : std_logic_vector(31 downto 0) := x"12345687";
jcarr18ID : std_logic_vector(31 downto 0) := x"12345688";
jcarr19ID : std_logic_vector(31 downto 0) := x"12345689";
jcarr20ID : std_logic_vector(31 downto 0) := x"12345690";
jcarr21ID : std_logic_vector(31 downto 0) := x"12345691";
jcarr22ID : std_logic_vector(31 downto 0) := x"12345692";
jcarr23ID : std_logic_vector(31 downto 0) := x"12345693";
jcarr24ID : std_logic_vector(31 downto 0) := x"12345694";
jcarr25ID : std_logic_vector(31 downto 0) := x"12345695";
jcarr26ID : std_logic_vector(31 downto 0) := x"12345696";
jcarr27ID : std_logic_vector(31 downto 0) := x"12345697";
jcarr28ID : std_logic_vector(31 downto 0) := x"12345698";
jcarr29ID : std_logic_vector(31 downto 0) := x"12345699";
jcarr30ID : std_logic_vector(31 downto 0) := x"12345700";
jcarr31ID : std_logic_vector(31 downto 0) := x"12345701";
jcarr32ID : std_logic_vector(31 downto 0) := x"12345702";
jcarr33ID : std_logic_vector(31 downto 0) := x"12345703";
jcarr34ID : std_logic_vector(31 downto 0) := x"12345704";
jcarr35ID : std_logic_vector(31 downto 0) := x"12345705";
jcarr36ID : std_logic_vector(31 downto 0) := x"12345706";
jcarr37ID : std_logic_vector(31 downto 0) := x"12345707";
jcarr38ID : std_logic_vector(31 downto 0) := x"12345708";
jcarr39ID : std_logic_vector(31 downto 0) := x"12345709";
jcarr40ID : std_logic_vector(31 downto 0) := x"12345710";
jcarr41ID : std_logic_vector(31 downto 0) := x"12345711";
jcarr42ID : std_logic_vector(31 downto 0) := x"12345712"
);
port (
-- General
clk33 : in std_logic;
nrst : in std_logic;
-- PCI target 32bits
ad : inout std_logic_vector(31 downto 0);
cbe : in std_logic_vector(3 downto 0);
par : out std_logic;
frame : in std_logic;
irdy : in std_logic;
trdy : out std_logic;
devsel : out std_logic;
stop : out std_logic;
idsel : in std_logic;
perr : out std_logic;
serr : out std_logic;
intb : out std_logic;
-- Master whisbone
wb_adr_o : out std_logic_vector(24 downto 1);
wb_dat_i : in std_logic_vector(15 downto 0);
wb_dat_o : out std_logic_vector(15 downto 0);
wb_sel_o : out std_logic_vector(1 downto 0);
wb_we_o : out std_logic;
wb_stb_o : inout std_logic;
wb_cyc_o : out std_logic;
wb_ack_i : in std_logic;
wb_err_i : in std_logic;
wb_int_i : in std_logic;
-- debug signals
debug_init : out std_logic;
debug_access : out std_logic
);
end pci32tlite;
--+-----------------------------------------------------------------------------+
--| ARCHITECTURE |
--+-----------------------------------------------------------------------------+
architecture rtl of pci32tlite is
--+-----------------------------------------------------------------------------+
--| COMPONENTS |
--+-----------------------------------------------------------------------------+
component pcidec_new
port (
clk_i : in std_logic;
nrst_i : in std_logic;
--
ad_i : in std_logic_vector(31 downto 0);
cbe_i : in std_logic_vector(3 downto 0);
idsel_i : in std_logic;
bar0_i : in std_logic_vector(31 downto 25);
memEN_i : in std_logic;
pciadrLD_i : in std_logic;
adrcfg_o : out std_logic;
adrmem_o : out std_logic;
adr_o : out std_logic_vector(24 downto 1);
cmd_o : out std_logic_vector(3 downto 0)
);
end component;
component pciwbsequ
port (
-- General
clk_i : in std_logic;
nrst_i : in std_logic;
-- pci
cmd_i : in std_logic_vector(3 downto 0);
cbe_i : in std_logic_vector(3 downto 0);
frame_i : in std_logic;
irdy_i : in std_logic;
devsel_o : out std_logic;
trdy_o : out std_logic;
-- control
adrcfg_i : in std_logic;
adrmem_i : in std_logic;
pciadrLD_o : out std_logic;
pcidOE_o : out std_logic;
parOE_o : out std_logic;
wbdatLD_o : out std_logic;
wbrgdMX_o : out std_logic;
wbd16MX_o : out std_logic;
wrcfg_o : out std_logic;
rdcfg_o : out std_logic;
-- whisbone
wb_sel_o : out std_logic_vector(1 downto 0);
wb_we_o : out std_logic;
wb_stb_o : inout std_logic;
wb_cyc_o : out std_logic;
wb_ack_i : in std_logic;
wb_err_i : in std_logic;
-- debug signals
debug_init : out std_logic;
debug_access : out std_logic
);
end component;
component pcidmux
port (
clk_i : in std_logic;
nrst_i : in std_logic;
--
d_io : inout std_logic_vector(31 downto 0);
pcidatout_o : out std_logic_vector(31 downto 0);
pcidOE_i : in std_logic;
wbdatLD_i : in std_logic;
wbrgdMX_i : in std_logic;
wbd16MX_i : in std_logic;
wb_dat_i : in std_logic_vector(15 downto 0);
wb_dat_o : out std_logic_vector(15 downto 0);
rg_dat_i : in std_logic_vector(31 downto 0);
rg_dat_o : out std_logic_vector(31 downto 0)
);
end component;
component pciregs
generic (
vendorID : std_logic_vector(15 downto 0);
deviceID : std_logic_vector(15 downto 0);
revisionID : std_logic_vector(7 downto 0);
subsystemID : std_logic_vector(15 downto 0);
subsystemvID : std_logic_vector(15 downto 0);
jcarr1ID : std_logic_vector(31 downto 0);
jcarr2ID : std_logic_vector(31 downto 0);
jcarr3ID : std_logic_vector(31 downto 0);
jcarr4ID : std_logic_vector(31 downto 0);
jcarr5ID : std_logic_vector(31 downto 0);
jcarr6ID : std_logic_vector(31 downto 0);
jcarr7ID : std_logic_vector(31 downto 0);
jcarr8ID : std_logic_vector(31 downto 0);
jcarr9ID : std_logic_vector(31 downto 0);
jcarr10ID : std_logic_vector(31 downto 0);
jcarr11ID : std_logic_vector(31 downto 0);
jcarr12ID : std_logic_vector(31 downto 0);
jcarr13ID : std_logic_vector(31 downto 0);
jcarr14ID : std_logic_vector(31 downto 0);
jcarr15ID : std_logic_vector(31 downto 0);
jcarr16ID : std_logic_vector(31 downto 0);
jcarr17ID : std_logic_vector(31 downto 0);
jcarr18ID : std_logic_vector(31 downto 0);
jcarr19ID : std_logic_vector(31 downto 0);
jcarr20ID : std_logic_vector(31 downto 0);
jcarr21ID : std_logic_vector(31 downto 0);
jcarr22ID : std_logic_vector(31 downto 0);
jcarr23ID : std_logic_vector(31 downto 0);
jcarr24ID : std_logic_vector(31 downto 0);
jcarr25ID : std_logic_vector(31 downto 0);
jcarr26ID : std_logic_vector(31 downto 0);
jcarr27ID : std_logic_vector(31 downto 0);
jcarr28ID : std_logic_vector(31 downto 0);
jcarr29ID : std_logic_vector(31 downto 0);
jcarr30ID : std_logic_vector(31 downto 0);
jcarr31ID : std_logic_vector(31 downto 0);
jcarr32ID : std_logic_vector(31 downto 0);
jcarr33ID : std_logic_vector(31 downto 0);
jcarr34ID : std_logic_vector(31 downto 0);
jcarr35ID : std_logic_vector(31 downto 0);
jcarr36ID : std_logic_vector(31 downto 0);
jcarr37ID : std_logic_vector(31 downto 0);
jcarr38ID : std_logic_vector(31 downto 0);
jcarr39ID : std_logic_vector(31 downto 0);
jcarr40ID : std_logic_vector(31 downto 0);
jcarr41ID : std_logic_vector(31 downto 0);
jcarr42ID : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
nrst_i : in std_logic;
--
adr_i : in std_logic_vector(7 downto 2);
cbe_i : in std_logic_vector(3 downto 0);
dat_i : in std_logic_vector(31 downto 0);
dat_o : out std_logic_vector(31 downto 0);
wrcfg_i : in std_logic;
rdcfg_i : in std_logic;
perr_i : in std_logic;
serr_i : in std_logic;
tabort_i : in std_logic;
bar0_o : out std_logic_vector(31 downto 25);
perrEN_o : out std_logic;
serrEN_o : out std_logic;
memEN_o : out std_logic
);
end component;
component pcipargen
port (
clk_i : in std_logic;
pcidatout_i : in std_logic_vector(31 downto 0);
cbe_i : in std_logic_vector(3 downto 0);
parOE_i : in std_logic;
par_o : out std_logic
);
end component;
--+-----------------------------------------------------------------------------+
--| CONSTANTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| SIGNALS |
--+-----------------------------------------------------------------------------+
signal bar0 : std_logic_vector(31 downto 25);
signal memEN : std_logic;
signal pciadrLD : std_logic;
signal adrcfg : std_logic;
signal adrmem : std_logic;
signal adr : std_logic_vector(24 downto 1);
signal cmd : std_logic_vector(3 downto 0);
signal pcidOE : std_logic;
signal parOE : std_logic;
signal wbdatLD : std_logic;
signal wbrgdMX : std_logic;
signal wbd16MX : std_logic;
signal wrcfg : std_logic;
signal rdcfg : std_logic;
signal pcidatread : std_logic_vector(31 downto 0);
signal pcidatwrite : std_logic_vector(31 downto 0);
signal pcidatout : std_logic_vector(31 downto 0);
signal parerr : std_logic;
signal syserr : std_logic;
signal tabort : std_logic;
signal perrEN : std_logic;
signal serrEN : std_logic;
begin
--+-------------------------------------------------------------------------+
--| Component instances |
--+-------------------------------------------------------------------------+
--+-----------------------------------------+
--| PCI decoder |
--+-----------------------------------------+
u1: component pcidec_new
port map (
clk_i => clk33,
nrst_i => nrst,
--
ad_i => ad,
cbe_i => cbe,
idsel_i => idsel,
bar0_i => bar0,
memEN_i => memEN,
pciadrLD_i => pciadrLD,
adrcfg_o => adrcfg,
adrmem_o => adrmem,
adr_o => adr,
cmd_o => cmd
);
--+-----------------------------------------+
--| PCI-WB Sequencer |
--+-----------------------------------------+
u2: component pciwbsequ
port map (
-- General
clk_i => clk33,
nrst_i => nrst,
-- pci
cmd_i => cmd,
cbe_i => cbe,
frame_i => frame,
irdy_i => irdy,
devsel_o => devsel,
trdy_o => trdy,
-- control
adrcfg_i => adrcfg,
adrmem_i => adrmem,
pciadrLD_o => pciadrLD,
pcidOE_o => pcidOE,
parOE_o => parOE,
wbdatLD_o => wbdatLD,
wbrgdMX_o => wbrgdMX,
wbd16MX_o => wbd16MX,
wrcfg_o => wrcfg,
rdcfg_o => rdcfg,
-- whisbone
wb_sel_o => wb_sel_o,
wb_we_o => wb_we_o,
wb_stb_o => wb_stb_o,
wb_cyc_o => wb_cyc_o,
wb_ack_i => wb_ack_i,
wb_err_i => wb_err_i,
-- debug signals
debug_init => debug_init,
debug_access => debug_access
);
--+-----------------------------------------+
--| PCI-wb datamultiplexer |
--+-----------------------------------------+
u3: component pcidmux
port map (
clk_i => clk33,
nrst_i => nrst,
--
d_io => ad,
pcidatout_o => pcidatout,
pcidOE_i => pcidOE,
wbdatLD_i => wbdatLD,
wbrgdMX_i => wbrgdMX,
wbd16MX_i => wbd16MX,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
rg_dat_i => pcidatread,
rg_dat_o => pcidatwrite
);
--+-----------------------------------------+
--| PCI registers |
--+-----------------------------------------+
u4: component pciregs
generic map (
vendorID => vendorID,
deviceID => deviceID,
revisionID => revisionID,
subsystemID => subsystemID,
subsystemvID => subsystemvID,
jcarr1ID => jcarr1ID,
jcarr2ID => jcarr2ID,
jcarr3ID => jcarr3ID,
jcarr4ID => jcarr4ID,
jcarr5ID => jcarr5ID,
jcarr6ID => jcarr6ID,
jcarr7ID => jcarr7ID,
jcarr8ID => jcarr8ID,
jcarr9ID => jcarr9ID,
jcarr10ID => jcarr10ID,
jcarr11ID => jcarr11ID,
jcarr12ID => jcarr12ID,
jcarr13ID => jcarr13ID,
jcarr14ID => jcarr14ID,
jcarr15ID => jcarr15ID,
jcarr16ID => jcarr16ID,
jcarr17ID => jcarr17ID,
jcarr18ID => jcarr18ID,
jcarr19ID => jcarr19ID,
jcarr20ID => jcarr20ID,
jcarr21ID => jcarr21ID,
jcarr22ID => jcarr22ID,
jcarr23ID => jcarr23ID,
jcarr24ID => jcarr24ID,
jcarr25ID => jcarr25ID,
jcarr26ID => jcarr26ID,
jcarr27ID => jcarr27ID,
jcarr28ID => jcarr28ID,
jcarr29ID => jcarr29ID,
jcarr30ID => jcarr30ID,
jcarr31ID => jcarr31ID,
jcarr32ID => jcarr32ID,
jcarr33ID => jcarr33ID,
jcarr34ID => jcarr34ID,
jcarr35ID => jcarr35ID,
jcarr36ID => jcarr36ID,
jcarr37ID => jcarr37ID,
jcarr38ID => jcarr38ID,
jcarr39ID => jcarr39ID,
jcarr40ID => jcarr40ID,
jcarr41ID => jcarr41ID,
jcarr42ID => jcarr42ID
)
port map (
clk_i => clk33,
nrst_i => nrst,
--
adr_i => adr(7 downto 2),
cbe_i => cbe,
dat_i => pcidatwrite,
dat_o => pcidatread,
wrcfg_i => wrcfg,
rdcfg_i => rdcfg,
perr_i => parerr,
serr_i => syserr,
tabort_i => tabort,
bar0_o => bar0,
perrEN_o => perrEN,
serrEN_o => serrEN,
memEN_o => memEN
);
--+-----------------------------------------+
--| PCI Parity Gnerator |
--+-----------------------------------------+
u5: component pcipargen
port map (
clk_i => clk33,
pcidatout_i => pcidatout,
cbe_i => cbe,
parOE_i => parOE,
par_o => par
);
--+-----------------------------------------+
--| Whisbone Address bus |
--+-----------------------------------------+
wb_adr_o <= adr;
--+-----------------------------------------+
--| unimplemented |
--+-----------------------------------------+
parerr <= '0';
syserr <= '0';
tabort <= '0';
--+-----------------------------------------+
--| unused outputs |
--+-----------------------------------------+
-- #stop: Curret TARGET indicates to Master stop current transaction
-- #perr:
-- #serr:
perr <= 'Z';
serr <= 'Z';
stop <= 'Z';
intb <= '0' when ( wb_int_i = '1' ) else 'Z';
end rtl;
| gpl-2.0 |
mati75/ghdl | libraries/vital95/vital_timing_body.vhdl | 6 | 52671 | -------------------------------------------------------------------------------
-- Title : Standard VITAL TIMING Package
-- : $Revision$
-- Library : VITAL
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, attributes, constants,
-- : functions and procedures for use in developing ASIC models.
-- : This file contains the Package Body.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/08/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0
-- #204 - Output mapping prior to glitch detection
-- ----------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
PACKAGE BODY VITAL_Timing IS
-- --------------------------------------------------------------------
-- Package Local Declarations
-- --------------------------------------------------------------------
TYPE CheckType IS ( SetupCheck, HoldCheck, RecoveryCheck, RemovalCheck,
PulseWidCheck, PeriodCheck );
TYPE CheckInfoType IS RECORD
Violation : BOOLEAN;
CheckKind : CheckType;
ObsTime : TIME;
ExpTime : TIME;
DetTime : TIME;
State : X01;
END RECORD;
TYPE LogicCvtTableType IS ARRAY (std_ulogic) OF CHARACTER;
TYPE HiLoStrType IS ARRAY (std_ulogic RANGE 'X' TO '1') OF STRING(1 TO 4);
CONSTANT LogicCvtTable : LogicCvtTableType
:= ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
CONSTANT HiLoStr : HiLoStrType := (" X ", " Low", "High" );
TYPE EdgeSymbolMatchType IS ARRAY (X01,X01,VitalEdgeSymbolType) OF BOOLEAN;
-- last value, present value, edge symbol
CONSTANT EdgeSymbolMatch : EdgeSymbolMatchType := (
'X'=>('X'=>( OTHERS => FALSE),
'0'=>('N'|'F'|'v'|'E'|'D'|'*' => TRUE, OTHERS => FALSE ),
'1'=>('P'|'R'|'^'|'E'|'A'|'*' => TRUE, OTHERS => FALSE ) ),
'0'=>('X'=>( 'r'|'p'|'R'|'A'|'*' => TRUE, OTHERS => FALSE ),
'0'=>( OTHERS => FALSE ),
'1'=>( '/'|'P'|'p'|'R'|'*' => TRUE, OTHERS => FALSE ) ),
'1'=>('X'=>( 'f'|'n'|'F'|'D'|'*' => TRUE, OTHERS => FALSE ),
'0'=>( '\'|'N'|'n'|'F'|'*' => TRUE, OTHERS => FALSE ),
'1'=>( OTHERS => FALSE ) ) );
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Misc Utilities Local Utilities
---------------------------------------------------------------------------
-----------------------------------------------------------------------
FUNCTION Minimum ( CONSTANT t1,t2 : IN TIME ) RETURN TIME IS
BEGIN
IF ( t1 < t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF;
END Minimum;
-----------------------------------------------------------------------
FUNCTION Maximum ( CONSTANT t1,t2 : IN TIME ) RETURN TIME IS
BEGIN
IF ( t1 > t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF;
END Maximum;
--------------------------------------------------------------------
-- Error Message Types and Tables
--------------------------------------------------------------------
TYPE VitalErrorType IS (
ErrVctLng ,
ErrNoPath ,
ErrNegPath ,
ErrNegDel
);
TYPE VitalErrorSeverityType IS ARRAY (VitalErrorType) OF SEVERITY_LEVEL;
CONSTANT VitalErrorSeverity : VitalErrorSeverityType := (
ErrVctLng => ERROR,
ErrNoPath => WARNING,
ErrNegPath => WARNING,
ErrNegDel => WARNING
);
CONSTANT MsgNoPath : STRING :=
"No Delay Path Condition TRUE. 0-delay used. Output signal is: ";
CONSTANT MsgNegPath : STRING :=
"Path Delay less than time since input. 0 delay used. Output signal is: ";
CONSTANT MsgNegDel : STRING :=
"Negative delay. New output value not scheduled. Output signal is: ";
CONSTANT MsgVctLng : STRING :=
"Vector (array) lengths not equal. ";
CONSTANT MsgUnknown : STRING :=
"Unknown error message.";
FUNCTION VitalMessage (
CONSTANT ErrorId : IN VitalErrorType
) RETURN STRING IS
BEGIN
CASE ErrorId IS
WHEN ErrVctLng => RETURN MsgVctLng;
WHEN ErrNoPath => RETURN MsgNoPath;
WHEN ErrNegPath => RETURN MsgNegPath;
WHEN ErrNegDel => RETURN MsgNegDel;
WHEN OTHERS => RETURN MsgUnknown;
END CASE;
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId)
SEVERITY VitalErrorSeverity(ErrorId);
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType;
CONSTANT Info : IN STRING
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId) & Info
SEVERITY VitalErrorSeverity(ErrorId);
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType;
CONSTANT Info : IN CHARACTER
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId) & Info
SEVERITY VitalErrorSeverity(ErrorId);
END;
---------------------------------------------------------------------------
-- Time Delay Assignment Subprograms
---------------------------------------------------------------------------
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType
) RETURN VitalDelayType01Z IS
BEGIN
RETURN (OTHERS => Delay);
END VitalExtendToFillDelay;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01
) RETURN VitalDelayType01Z IS
VARIABLE Delay01Z : VitalDelayType01Z;
BEGIN
Delay01Z(tr01) := Delay(tr01);
Delay01Z(tr0z) := Delay(tr01);
Delay01Z(trz1) := Delay(tr01);
Delay01Z(tr10) := Delay(tr10);
Delay01Z(tr1z) := Delay(tr10);
Delay01Z(trz0) := Delay(tr10);
RETURN (Delay01Z);
END VitalExtendToFillDelay;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalDelayType01Z IS
BEGIN
RETURN Delay;
END VitalExtendToFillDelay;
---------------------------------------------------------------------------
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType
) RETURN TIME IS
BEGIN
RETURN delay;
END VitalCalcDelay;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01
) RETURN TIME IS
VARIABLE Result : TIME;
BEGIN
CASE Newval IS
WHEN '0' | 'L' => Result := Delay(tr10);
WHEN '1' | 'H' => Result := Delay(tr01);
WHEN 'Z' =>
CASE Oldval IS
WHEN '0' | 'L' => Result := Delay(tr01);
WHEN '1' | 'H' => Result := Delay(tr10);
WHEN OTHERS => Result := MAXIMUM(Delay(tr10), Delay(tr01));
END CASE;
WHEN OTHERS =>
CASE Oldval IS
WHEN '0' | 'L' => Result := Delay(tr01);
WHEN '1' | 'H' => Result := Delay(tr10);
WHEN 'Z' => Result := MINIMUM(Delay(tr10), Delay(tr01));
WHEN OTHERS => Result := MAXIMUM(Delay(tr10), Delay(tr01));
END CASE;
END CASE;
RETURN Result;
END VitalCalcDelay;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN TIME IS
VARIABLE Result : TIME;
BEGIN
CASE Oldval IS
WHEN '0' | 'L' =>
CASE Newval IS
WHEN '0' | 'L' => Result := Delay(tr10);
WHEN '1' | 'H' => Result := Delay(tr01);
WHEN 'Z' => Result := Delay(tr0z);
WHEN OTHERS => Result := MINIMUM(Delay(tr01), Delay(tr0z));
END CASE;
WHEN '1' | 'H' =>
CASE Newval IS
WHEN '0' | 'L' => Result := Delay(tr10);
WHEN '1' | 'H' => Result := Delay(tr01);
WHEN 'Z' => Result := Delay(tr1z);
WHEN OTHERS => Result := MINIMUM(Delay(tr10), Delay(tr1z));
END CASE;
WHEN 'Z' =>
CASE Newval IS
WHEN '0' | 'L' => Result := Delay(trz0);
WHEN '1' | 'H' => Result := Delay(trz1);
WHEN 'Z' => Result := MAXIMUM (Delay(tr0z), Delay(tr1z));
WHEN OTHERS => Result := MINIMUM (Delay(trz1), Delay(trz0));
END CASE;
WHEN 'U' | 'X' | 'W' | '-' =>
CASE Newval IS
WHEN '0' | 'L' => Result := MAXIMUM(Delay(tr10), Delay(trz0));
WHEN '1' | 'H' => Result := MAXIMUM(Delay(tr01), Delay(trz1));
WHEN 'Z' => Result := MAXIMUM(Delay(tr1z), Delay(tr0z));
WHEN OTHERS => Result := MAXIMUM(Delay(tr10), Delay(tr01));
END CASE;
END CASE;
RETURN Result;
END VitalCalcDelay;
---------------------------------------------------------------------------
FUNCTION VitalSelectPathDelay (
CONSTANT NewValue : IN std_logic;
CONSTANT OldValue : IN std_logic;
CONSTANT OutSignalName : IN string;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType
) RETURN TIME IS
VARIABLE TmpDelay : TIME;
VARIABLE InputAge : TIME := TIME'HIGH;
VARIABLE PropDelay : TIME := TIME'HIGH;
BEGIN
-- for each delay path
FOR i IN Paths'RANGE LOOP
-- ignore the delay path if it is not enabled
NEXT WHEN NOT Paths(i).PathCondition;
-- ignore the delay path if a more recent input event has been seen
NEXT WHEN Paths(i).InputChangeTime > InputAge;
-- This is the most recent input change (so far)
-- Get the transition dependent delay
TmpDelay := VitalCalcDelay(NewValue, OldValue, Paths(i).PathDelay);
-- If other inputs changed at the same time,
-- then use the minimum of their propagation delays,
-- else use the propagation delay from this input.
IF Paths(i).InputChangeTime < InputAge THEN
PropDelay := TmpDelay;
ELSE -- Simultaneous inputs change
IF TmpDelay < PropDelay THEN PropDelay := TmpDelay; END IF;
end if;
InputAge := Paths(i).InputChangeTime;
END LOOP;
-- If there were no paths (with an enabled condition),
-- use the default the delay
IF (PropDelay = TIME'HIGH ) THEN
PropDelay := VitalCalcDelay(NewValue, OldValue, DefaultDelay);
-- If the time since the most recent input event is greater than the
-- propagation delay from that input then
-- use the default the delay
ELSIF (InputAge > PropDelay) THEN
PropDelay := VitalCalcDelay(NewValue, OldValue, DefaultDelay);
-- Adjust the propagation delay by the time since the
-- the input event occurred (Usually 0 ns).
ELSE
PropDelay := PropDelay - InputAge;
END IF;
RETURN PropDelay;
END;
FUNCTION VitalSelectPathDelay (
CONSTANT NewValue : IN std_logic;
CONSTANT OldValue : IN std_logic;
CONSTANT OutSignalName : IN string;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01
) RETURN TIME IS
VARIABLE TmpDelay : TIME;
VARIABLE InputAge : TIME := TIME'HIGH;
VARIABLE PropDelay : TIME := TIME'HIGH;
BEGIN
-- for each delay path
FOR i IN Paths'RANGE LOOP
-- ignore the delay path if it is not enabled
NEXT WHEN NOT Paths(i).PathCondition;
-- ignore the delay path if a more recent input event has been seen
NEXT WHEN Paths(i).InputChangeTime > InputAge;
-- This is the most recent input change (so far)
-- Get the transition dependent delay
TmpDelay := VitalCalcDelay(NewValue, OldValue, Paths(i).PathDelay);
-- If other inputs changed at the same time,
-- then use the minimum of their propagation delays,
-- else use the propagation delay from this input.
IF Paths(i).InputChangeTime < InputAge THEN
PropDelay := TmpDelay;
ELSE -- Simultaneous inputs change
IF TmpDelay < PropDelay THEN PropDelay := TmpDelay; END IF;
end if;
InputAge := Paths(i).InputChangeTime;
END LOOP;
-- If there were no paths (with an enabled condition),
-- use the default the delay
IF (PropDelay = TIME'HIGH ) THEN
PropDelay := VitalCalcDelay(NewValue, OldValue, DefaultDelay);
-- If the time since the most recent input event is greater than the
-- propagation delay from that input then
-- use the default the delay
ELSIF (InputAge > PropDelay) THEN
PropDelay := VitalCalcDelay(NewValue, OldValue, DefaultDelay);
-- Adjust the propagation delay by the time since the
-- the input event occurred (Usually 0 ns).
ELSE
PropDelay := PropDelay - InputAge;
END IF;
RETURN PropDelay;
END;
FUNCTION VitalSelectPathDelay (
CONSTANT NewValue : IN std_logic;
CONSTANT OldValue : IN std_logic;
CONSTANT OutSignalName : IN string;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z
) RETURN TIME IS
VARIABLE TmpDelay : TIME;
VARIABLE InputAge : TIME := TIME'HIGH;
VARIABLE PropDelay : TIME := TIME'HIGH;
BEGIN
-- for each delay path
FOR i IN Paths'RANGE LOOP
-- ignore the delay path if it is not enabled
NEXT WHEN NOT Paths(i).PathCondition;
-- ignore the delay path if a more recent input event has been seen
NEXT WHEN Paths(i).InputChangeTime > InputAge;
-- This is the most recent input change (so far)
-- Get the transition dependent delay
TmpDelay := VitalCalcDelay(NewValue, OldValue, Paths(i).PathDelay);
-- If other inputs changed at the same time,
-- then use the minimum of their propagation delays,
-- else use the propagation delay from this input.
IF Paths(i).InputChangeTime < InputAge THEN
PropDelay := TmpDelay;
ELSE -- Simultaneous inputs change
IF TmpDelay < PropDelay THEN PropDelay := TmpDelay; END IF;
end if;
InputAge := Paths(i).InputChangeTime;
END LOOP;
-- If there were no paths (with an enabled condition),
-- use the default the delay
IF (PropDelay = TIME'HIGH ) THEN
PropDelay := VitalCalcDelay(NewValue, OldValue, DefaultDelay);
-- If the time since the most recent input event is greater than the
-- propagation delay from that input then
-- use the default the delay
ELSIF (InputAge > PropDelay) THEN
PropDelay := VitalCalcDelay(NewValue, OldValue, DefaultDelay);
-- Adjust the propagation delay by the time since the
-- the input event occurred (Usually 0 ns).
ELSE
PropDelay := PropDelay - InputAge;
END IF;
RETURN PropDelay;
END;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Glitch Handlers
---------------------------------------------------------------------------
---------------------------------------------------------------------------
PROCEDURE ReportGlitch (
CONSTANT GlitchRoutine : IN STRING;
CONSTANT OutSignalName : IN STRING;
CONSTANT PreemptedTime : IN TIME;
CONSTANT PreemptedValue : IN std_ulogic;
CONSTANT NewTime : IN TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT Index : IN INTEGER := 0;
CONSTANT IsArraySignal : IN BOOLEAN := FALSE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE StrPtr1, StrPtr2, StrPtr3, StrPtr4, StrPtr5 : LINE;
BEGIN
Write (StrPtr1, PreemptedTime );
Write (StrPtr2, NewTime);
Write (StrPtr3, LogicCvtTable(PreemptedValue));
Write (StrPtr4, LogicCvtTable(NewValue));
IF IsArraySignal THEN
Write (StrPtr5, STRING'( "(" ) );
Write (StrPtr5, Index);
Write (StrPtr5, STRING'( ")" ) );
ELSE
Write (StrPtr5, STRING'( " " ) );
END IF;
-- Issue Report only if Preempted value has not been
-- removed from event queue
ASSERT PreemptedTime > NewTime
REPORT GlitchRoutine & ": GLITCH Detected on port " &
OutSignalName & StrPtr5.ALL &
"; Preempted Future Value := " & StrPtr3.ALL &
" @ " & StrPtr1.ALL &
"; Newly Scheduled Value := " & StrPtr4.ALL &
" @ " & StrPtr2.ALL &
";"
SEVERITY MsgSeverity;
DEALLOCATE(StrPtr1);
DEALLOCATE(StrPtr2);
DEALLOCATE(StrPtr3);
DEALLOCATE(StrPtr4);
DEALLOCATE(StrPtr5);
RETURN;
END ReportGlitch;
---------------------------------------------------------------------------
PROCEDURE VitalGlitch (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT NewValue : IN std_logic;
CONSTANT NewDelay : IN TIME := 0 ns;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := FALSE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
---------------------------------------------------------------------------
VARIABLE NewGlitch : BOOLEAN := TRUE;
VARIABLE dly : TIME := NewDelay;
BEGIN
-- If nothing to schedule, just return
IF NewDelay < 0 ns THEN
IF (NewValue /= GlitchData.SchedValue) THEN
VitalError ( "VitalGlitch", ErrNegDel, OutSignalName );
END IF;
RETURN;
END IF;
-- If simple signal assignment
-- perform the signal assignment
IF ( Mode = VitalInertial) THEN
OutSignal <= NewValue AFTER dly;
ELSIF ( Mode = VitalTransport ) THEN
OutSignal <= TRANSPORT NewValue AFTER dly;
ELSE
-- Glitch Processing ---
-- If nothing currently scheduled
IF GlitchData.SchedTime <= NOW THEN
-- Note: NewValue is always /= OldValue when called from VPPD
IF (NewValue = GlitchData.SchedValue) THEN RETURN; END IF;
-- No new glitch, save time for possable future glitch
NewGlitch := FALSE;
GlitchData.GlitchTime := NOW+dly;
-- New value earlier than the earliest previous value scheduled
ELSIF (NOW+dly <= GlitchData.GlitchTime)
AND (NOW+dly <= GlitchData.SchedTime) THEN
-- No new glitch, save time for possible future glitch
NewGlitch := FALSE;
GlitchData.GlitchTime := NOW+dly;
-- Transaction currently scheduled - if glitch already happened
ELSIF GlitchData.GlitchTime <= NOW THEN
IF (GlitchData.SchedValue = NewValue) THEN
dly := Minimum( GlitchData.SchedTime-NOW, NewDelay );
END IF;
NewGlitch := FALSE;
-- Transaction currently scheduled (no glitch if same value)
ELSIF (GlitchData.SchedValue = NewValue)
AND (GlitchData.SchedTime = GlitchData.GlitchTime) THEN
-- revise scheduled output time if new delay is sooner
dly := Minimum( GlitchData.SchedTime-NOW, NewDelay );
-- No new glitch, save time for possable future glitch
NewGlitch := FALSE;
GlitchData.GlitchTime := NOW+dly;
-- Transaction currently scheduled represents a glitch
ELSE
-- A new glitch has been detected
NewGlitch := TRUE;
END IF;
IF NewGlitch THEN
-- If messages requested, report the glitch
IF MsgOn THEN
ReportGlitch ("VitalGlitch", OutSignalName,
GlitchData.GlitchTime, GlitchData.SchedValue,
(dly + NOW), NewValue,
MsgSeverity=>MsgSeverity );
END IF;
-- Force immediate glitch for "OnDetect" mode.
IF (Mode = OnDetect) THEN
GlitchData.GlitchTime := NOW;
END IF;
-- If 'X' generation is requested, schedule the new value
-- preceeded by a glitch pulse.
-- Otherwise just schedule the new value (inertial mode).
IF XOn THEN
OutSignal <= 'X' AFTER GlitchData.GlitchTime-NOW;
OutSignal <= TRANSPORT NewValue AFTER dly;
ELSE
OutSignal <= NewValue AFTER dly;
END IF;
-- If there no new glitch was detected, just schedule the new value.
ELSE
OutSignal <= NewValue AFTER dly;
END IF;
END IF;
-- Record the new value and time just scheduled.
GlitchData.SchedValue := NewValue;
GlitchData.SchedTime := NOW+dly;
RETURN;
END;
---------------------------------------------------------------------------
PROCEDURE VitalPathDelay (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE PropDelay : TIME;
BEGIN
-- Check if the new value to be scheduled is different than the
-- previously scheduled value
IF (GlitchData.SchedTime <= NOW) AND
(GlitchData.SchedValue = OutTemp)
THEN RETURN;
END IF;
-- Evaluate propagation delay paths
PropDelay := VitalSelectPathDelay (OutTemp, GlitchData.LastValue,
OutSignalName, Paths, DefaultDelay);
GlitchData.LastValue := OutTemp;
-- Schedule the output transactions - including glitch handling
VitalGlitch (OutSignal, GlitchData, OutSignalName, OutTemp,
PropDelay, Mode, XOn, MsgOn, MsgSeverity );
END VitalPathDelay;
PROCEDURE VitalPathDelay01 (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE PropDelay : TIME;
BEGIN
-- Check if the new value to be scheduled is different than the
-- previously scheduled value
IF (GlitchData.SchedTime <= NOW) AND
(GlitchData.SchedValue = OutTemp)
THEN RETURN;
END IF;
-- Evaluate propagation delay paths
PropDelay := VitalSelectPathDelay (OutTemp, GlitchData.LastValue,
OutSignalName, Paths, DefaultDelay);
GlitchData.LastValue := OutTemp;
-- Schedule the output transactions - including glitch handling
VitalGlitch (OutSignal, GlitchData, OutSignalName, OutTemp,
PropDelay, Mode, XOn, MsgOn, MsgSeverity );
END VitalPathDelay01;
PROCEDURE VitalPathDelay01Z (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT OutputMap : IN VitalOutputMapType
:= VitalDefaultOutputMap
) IS
VARIABLE PropDelay : TIME;
BEGIN
-- Check if the new value to be scheduled is different than the
-- previously scheduled value
IF (GlitchData.SchedTime <= NOW) AND
(GlitchData.SchedValue = OutputMap(OutTemp) )
THEN RETURN;
END IF;
-- Evaluate propagation delay paths
PropDelay := VitalSelectPathDelay (OutTemp, GlitchData.LastValue,
OutSignalName, Paths, DefaultDelay);
GlitchData.LastValue := OutTemp;
-- Schedule the output transactions - including glitch handling
VitalGlitch (OutSignal, GlitchData, OutSignalName, OutputMap(OutTemp),
PropDelay, Mode, XOn, MsgOn, MsgSeverity );
END VitalPathDelay01Z;
----------------------------------------------------------------------------
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType
) IS
BEGIN
OutSig <= TRANSPORT InSig AFTER twire;
END VitalWireDelay;
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01
) IS
VARIABLE Delay : TIME;
BEGIN
Delay := VitalCalcDelay( InSig, InSig'LAST_VALUE, twire );
OutSig <= TRANSPORT InSig AFTER Delay;
END VitalWireDelay;
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01Z
) IS
VARIABLE Delay : TIME;
BEGIN
Delay := VitalCalcDelay( InSig, InSig'LAST_VALUE, twire );
OutSig <= TRANSPORT InSig AFTER Delay;
END VitalWireDelay;
----------------------------------------------------------------------------
PROCEDURE VitalSignalDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT dly : IN TIME
) IS
BEGIN
OutSig <= TRANSPORT InSig AFTER dly;
END;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Setup and Hold Time Check Routine
---------------------------------------------------------------------------
---------------------------------------------------------------------------
PROCEDURE ReportViolation (
CONSTANT TestSignalName : IN STRING := "";
CONSTANT RefSignalName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT CheckInfo : IN CheckInfoType;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
IF NOT CheckInfo.Violation THEN RETURN; END IF;
Write ( Message, HeaderMsg );
Case CheckInfo.CheckKind IS
WHEN SetupCheck => Write ( Message, STRING'(" SETUP ") );
WHEN HoldCheck => Write ( Message, STRING'(" HOLD ") );
WHEN RecoveryCheck => Write ( Message, STRING'(" RECOVERY ") );
WHEN RemovalCheck => Write ( Message, STRING'(" REMOVAL ") );
WHEN PulseWidCheck => Write ( Message, STRING'(" PULSE WIDTH "));
WHEN PeriodCheck => Write ( Message, STRING'(" PERIOD ") );
END CASE;
Write ( Message, HiLoStr(CheckInfo.State) );
Write ( Message, STRING'(" VIOLATION ON ") );
Write ( Message, TestSignalName );
IF (RefSignalName'LENGTH > 0) THEN
Write ( Message, STRING'(" WITH RESPECT TO ") );
Write ( Message, RefSignalName );
END IF;
Write ( Message, ';' & LF );
Write ( Message, STRING'(" Expected := ") );
Write ( Message, CheckInfo.ExpTime);
Write ( Message, STRING'("; Observed := ") );
Write ( Message, CheckInfo.ObsTime);
Write ( Message, STRING'("; At : ") );
Write ( Message, CheckInfo.DetTime);
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END ReportViolation;
---------------------------------------------------------------------------
-- Procedure : InternalTimingCheck
---------------------------------------------------------------------------
PROCEDURE InternalTimingCheck (
CONSTANT TestSignal : IN std_ulogic;
CONSTANT RefSignal : IN std_ulogic;
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
VARIABLE RefTime : IN TIME;
VARIABLE RefEdge : IN BOOLEAN;
VARIABLE TestTime : IN TIME;
VARIABLE TestEvent : IN BOOLEAN;
VARIABLE SetupEn : INOUT BOOLEAN;
VARIABLE HoldEn : INOUT BOOLEAN;
VARIABLE CheckInfo : INOUT CheckInfoType;
CONSTANT MsgOn : IN BOOLEAN
) IS
VARIABLE bias, b2 : TIME;
BEGIN
-- Check SETUP constraint
IF RefEdge THEN
IF SetupEn THEN
CheckInfo.ObsTime := RefTime - TestTime;
CheckInfo.State := To_X01(TestSignal);
CASE CheckInfo.State IS
WHEN '0' => CheckInfo.ExpTime := SetupLow;
WHEN '1' => CheckInfo.ExpTime := SetupHigh;
WHEN 'X' => CheckInfo.ExpTime := Maximum(SetupHigh,SetupLow);
END CASE;
CheckInfo.Violation := CheckInfo.ObsTime < CheckInfo.ExpTime;
SetupEn := FALSE;
ELSE
CheckInfo.Violation := FALSE;
END IF;
-- Check HOLD constraint
ELSIF TestEvent THEN
IF HoldEn THEN
CheckInfo.ObsTime := TestTime - RefTime;
CheckInfo.State := To_X01(TestSignal);
CASE CheckInfo.State IS
WHEN '0' => CheckInfo.ExpTime := HoldHigh;
WHEN '1' => CheckInfo.ExpTime := HoldLow;
WHEN 'X' => CheckInfo.ExpTime := Maximum(HoldHigh,HoldLow);
END CASE;
CheckInfo.Violation := CheckInfo.ObsTime < CheckInfo.ExpTime;
HoldEn := NOT CheckInfo.Violation;
ELSE
CheckInfo.Violation := FALSE;
END IF;
ELSE
CheckInfo.Violation := FALSE;
END IF;
-- Adjust report values to account for internal model delays
-- Note: TestDelay, RefDelay, TestTime, RefTime and bias are non-negative
IF MsgOn AND CheckInfo.Violation THEN
bias := TestDelay - RefDelay;
IF TestTime - RefTime <= bias THEN
CheckInfo.CheckKind := SetupCheck;
b2 := TIME'HIGH - bias;
IF (CheckInfo.ObsTime <= b2)
THEN CheckInfo.ObsTime := CheckInfo.ObsTime + bias;
ELSE CheckInfo.ObsTime := Time'HIGH;
END IF;
IF (CheckInfo.ExpTime <= b2)
THEN CheckInfo.ExpTime := CheckInfo.ExpTime + bias;
ELSE CheckInfo.ExpTime := Time'HIGH;
END IF;
CheckInfo.DetTime := RefTime - RefDelay;
ELSE
CheckInfo.CheckKind := HoldCheck;
CheckInfo.ObsTime := CheckInfo.ObsTime - bias;
IF (CheckInfo.ExpTime >= 0 ns) THEN
CheckInfo.ExpTime := CheckInfo.ExpTime - bias;
END IF;
CheckInfo.DetTime := TestTime - TestDelay;
END IF;
END IF;
END InternalTimingCheck;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
FUNCTION VitalTimingDataInit
RETURN VitalTimingDataType IS
BEGIN
RETURN (FALSE,'X', 0 ns, FALSE, 'X', 0 ns, FALSE, NULL, NULL, NULL, NULL);
END;
---------------------------------------------------------------------------
-- Procedure : VitalSetupHoldCheck
---------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE RefEdge, TestEvent : BOOLEAN;
VARIABLE TestDly : TIME := Maximum(0 ns, TestDelay);
VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay);
VARIABLE bias : TIME;
BEGIN
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLast := To_X01(TestSignal);
TimingData.RefLast := To_X01(RefSignal);
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal),
RefTransition);
TimingData.RefLast := To_X01(RefSignal);
IF RefEdge THEN
TimingData.RefTime := NOW;
TimingData.HoldEn := TRUE;
END IF;
-- Detect test (data) changes and record the time of the last change
TestEvent := TimingData.TestLast /= To_X01Z(TestSignal);
TimingData.TestLast := To_X01Z(TestSignal);
IF TestEvent THEN
TimingData.TestTime := NOW;
TimingData.SetupEn := TRUE;
END IF;
-- Perform timing checks (if enabled)
Violation := '0';
IF (CheckEnabled) THEN
InternalTimingCheck (
TestSignal => TestSignal,
RefSignal => RefSignal,
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHigh,
SetupLow => SetupLow,
HoldHigh => HoldHigh,
HoldLow => HoldLow,
RefTime => TimingData.RefTime,
RefEdge => RefEdge,
TestTime => TimingData.TestTime,
TestEvent => TestEvent,
SetupEn => TimingData.SetupEn,
HoldEn => TimingData.HoldEn,
CheckInfo => CheckInfo,
MsgOn => MsgOn );
-- Report any detected violations and set return violation flag
IF CheckInfo.Violation THEN
IF (MsgOn) THEN
ReportViolation (TestSignalName, RefSignalName,
HeaderMsg, CheckInfo, MsgSeverity );
END IF;
IF (XOn) THEN Violation := 'X'; END IF;
END IF;
END IF;
END VitalSetupHoldCheck;
---------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE RefEdge : BOOLEAN;
VARIABLE TestEvent : VitalBoolArrayT(TestSignal'RANGE);
VARIABLE TestDly : TIME := Maximum(0 ns, TestDelay);
VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay);
VARIABLE bias : TIME;
VARIABLE ChangedAllAtOnce : BOOLEAN := TRUE;
VARIABLE StrPtr1 : LINE;
BEGIN
-- Initialization of working area.
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLastA := NEW std_logic_vector(TestSignal'RANGE);
TimingData.TestTimeA := NEW VitalTimeArrayT(TestSignal'RANGE);
TimingData.HoldEnA := NEW VitalBoolArrayT(TestSignal'RANGE);
TimingData.SetupEnA := NEW VitalBoolArrayT(TestSignal'RANGE);
FOR i IN TestSignal'RANGE LOOP
TimingData.TestLastA(i) := To_X01(TestSignal(i));
END LOOP;
TimingData.RefLast := To_X01(RefSignal);
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal),
RefTransition);
TimingData.RefLast := To_X01(RefSignal);
IF RefEdge THEN
TimingData.RefTime := NOW;
TimingData.HoldEnA.all := (TestSignal'RANGE=>TRUE);
END IF;
-- Detect test (data) changes and record the time of the last change
FOR i IN TestSignal'RANGE LOOP
TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignal(i));
TimingData.TestLastA(i) := To_X01Z(TestSignal(i));
IF TestEvent(i) THEN
TimingData.TestTimeA(i) := NOW;
TimingData.SetupEnA(i) := TRUE;
TimingData.TestTime := NOW;
END IF;
END LOOP;
-- Check to see if the Bus subelements changed all at the same time.
-- If so, then we can reduce the volume of error messages since we no
-- longer have to report every subelement individually
FOR i IN TestSignal'RANGE LOOP
IF TimingData.TestTimeA(i) /= TimingData.TestTime THEN
ChangedAllAtOnce := FALSE;
EXIT;
END IF;
END LOOP;
-- Perform timing checks (if enabled)
Violation := '0';
IF (CheckEnabled) THEN
FOR i IN TestSignal'RANGE LOOP
InternalTimingCheck (
TestSignal => TestSignal(i),
RefSignal => RefSignal,
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHigh,
SetupLow => SetupLow,
HoldHigh => HoldHigh,
HoldLow => HoldLow,
RefTime => TimingData.RefTime,
RefEdge => RefEdge,
TestTime => TimingData.TestTimeA(i),
TestEvent => TestEvent(i),
SetupEn => TimingData.SetupEnA(i),
HoldEn => TimingData.HoldEnA(i),
CheckInfo => CheckInfo,
MsgOn => MsgOn );
-- Report any detected violations and set return violation flag
IF CheckInfo.Violation THEN
IF (MsgOn) THEN
IF ( ChangedAllAtOnce AND (i = TestSignal'LEFT) ) THEN
ReportViolation (TestSignalName&"(...)", RefSignalName,
HeaderMsg, CheckInfo, MsgSeverity );
ELSIF (NOT ChangedAllAtOnce) THEN
Write (StrPtr1, i);
ReportViolation (TestSignalName & "(" & StrPtr1.ALL & ")",
RefSignalName,
HeaderMsg, CheckInfo, MsgSeverity );
DEALLOCATE (StrPtr1);
END IF;
END IF;
IF (XOn) THEN
Violation := 'X';
END IF;
END IF;
END LOOP;
END IF;
DEALLOCATE (StrPtr1);
END VitalSetupHoldCheck;
---------------------------------------------------------------------------
-- Function : VitalRecoveryRemovalCheck
---------------------------------------------------------------------------
PROCEDURE VitalRecoveryRemovalCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT Recovery : IN TIME := 0 ns;
CONSTANT Removal : IN TIME := 0 ns;
CONSTANT ActiveLow : IN BOOLEAN := TRUE;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE RefEdge, TestEvent : BOOLEAN;
VARIABLE TestDly : TIME := Maximum(0 ns, TestDelay);
VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay);
VARIABLE bias : TIME;
BEGIN
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLast := To_X01(TestSignal);
TimingData.RefLast := To_X01(RefSignal);
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal),
RefTransition);
TimingData.RefLast := To_X01(RefSignal);
IF RefEdge THEN
TimingData.RefTime := NOW;
TimingData.HoldEn := TRUE;
END IF;
-- Detect test (data) changes and record the time of the last change
TestEvent := TimingData.TestLast /= To_X01Z(TestSignal);
TimingData.TestLast := To_X01Z(TestSignal);
IF TestEvent THEN
TimingData.TestTime := NOW;
TimingData.SetupEn := TRUE;
END IF;
-- Perform timing checks (if enabled)
Violation := '0';
IF (CheckEnabled) THEN
IF ActiveLow THEN
InternalTimingCheck (
TestSignal, RefSignal, TestDly, RefDly,
Recovery, 0 ns, 0 ns, Removal,
TimingData.RefTime, RefEdge,
TimingData.TestTime, TestEvent,
TimingData.SetupEn, TimingData.HoldEn,
CheckInfo, MsgOn );
ELSE
InternalTimingCheck (
TestSignal, RefSignal, TestDly, RefDly,
0 ns, Recovery, Removal, 0 ns,
TimingData.RefTime, RefEdge,
TimingData.TestTime, TestEvent,
TimingData.SetupEn, TimingData.HoldEn,
CheckInfo, MsgOn );
END IF;
-- Report any detected violations and set return violation flag
IF CheckInfo.Violation THEN
IF CheckInfo.CheckKind = SetupCheck THEN
CheckInfo.CheckKind := RecoveryCheck;
ELSE
CheckInfo.CheckKind := RemovalCheck;
END IF;
IF (MsgOn) THEN
ReportViolation (TestSignalName, RefSignalName,
HeaderMsg, CheckInfo, MsgSeverity );
END IF;
IF (XOn) THEN Violation := 'X'; END IF;
END IF;
END IF;
END VitalRecoveryRemovalCheck;
---------------------------------------------------------------------------
PROCEDURE VitalPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT Period : IN TIME := 0 ns;
CONSTANT PulseWidthHigh : IN TIME := 0 ns;
CONSTANT PulseWidthLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE TestDly : TIME := Maximum(0 ns, TestDelay);
VARIABLE CheckInfo : CheckInfoType;
VARIABLE PeriodObs : TIME;
VARIABLE PulseTest, PeriodTest : BOOLEAN;
VARIABLE TestValue : X01 := To_X01(TestSignal);
BEGIN
IF (PeriodData.NotFirstFlag = FALSE) THEN
PeriodData.Rise :=
-maximum(Period, maximum(PulseWidthHigh, PulseWidthLow));
PeriodData.Fall :=
-maximum(Period, maximum(PulseWidthHigh, PulseWidthLow));
PeriodData.Last := To_X01(TestSignal);
PeriodData.NotFirstFlag := TRUE;
END IF;
-- Initialize for no violation
-- No violation possible if no test signal change
Violation := '0';
IF (PeriodData.Last = TestValue) THEN
RETURN;
END IF;
-- record starting pulse times
IF EdgeSymbolMatch(PeriodData.Last, TestValue, 'P') THEN
-- Compute period times, then record the High Rise Time
PeriodObs := NOW - PeriodData.Rise;
PeriodData.Rise := NOW;
PeriodTest := TRUE;
ELSIF EdgeSymbolMatch(PeriodData.Last, TestValue, 'N') THEN
-- Compute period times, then record the Low Fall Time
PeriodObs := NOW - PeriodData.Fall;
PeriodData.Fall := NOW;
PeriodTest := TRUE;
ELSE
PeriodTest := FALSE;
END IF;
-- do checks on pulse ends
IF EdgeSymbolMatch(PeriodData.Last, TestValue, 'p') THEN
-- Compute pulse times
CheckInfo.ObsTime := NOW - PeriodData.Fall;
CheckInfo.ExpTime := PulseWidthLow;
PulseTest := TRUE;
ELSIF EdgeSymbolMatch(PeriodData.Last, TestValue, 'n') THEN
-- Compute pulse times
CheckInfo.ObsTime := NOW - PeriodData.Rise;
CheckInfo.ExpTime := PulseWidthHigh;
PulseTest := TRUE;
ELSE
PulseTest := FALSE;
END IF;
IF PulseTest AND CheckEnabled THEN
-- Verify Pulse Width [ignore 1st edge]
IF ( CheckInfo.ObsTime < CheckInfo.ExpTime ) THEN
IF (XOn) THEN Violation := 'X'; END IF;
IF (MsgOn) THEN
CheckInfo.Violation := TRUE;
CheckInfo.CheckKind := PulseWidCheck;
CheckInfo.DetTime := NOW - TestDly;
CheckInfo.State := PeriodData.Last;
ReportViolation (TestSignalName, "",
HeaderMsg, CheckInfo, MsgSeverity );
END IF; -- MsgOn
END IF;
END IF;
IF PeriodTest AND CheckEnabled THEN
-- Verify the Period [ignore 1st edge]
CheckInfo.ObsTime := PeriodObs;
CheckInfo.ExpTime := Period;
IF ( CheckInfo.ObsTime < CheckInfo.ExpTime ) THEN
IF (XOn) THEN Violation := 'X'; END IF;
IF (MsgOn) THEN
CheckInfo.Violation := TRUE;
CheckInfo.CheckKind := PeriodCheck;
CheckInfo.DetTime := NOW - TestDly;
CheckInfo.State := TestValue;
ReportViolation (TestSignalName, "",
HeaderMsg, CheckInfo, MsgSeverity );
END IF; -- MsgOn
END IF;
END IF;
PeriodData.Last := TestValue;
END VitalPeriodPulseCheck;
END VITAL_Timing;
| gpl-2.0 |
mati75/ghdl | libraries/mentor/std_logic_arith.vhdl | 7 | 14183 | ----------------------------------------------------------------------------
-- --
-- Copyright (c) 1993 by Mentor Graphics --
-- --
-- This source file is proprietary information of Mentor Graphics,Inc. --
-- It may be distributed in whole without restriction provided that --
-- this copyright statement is not removed from the file and that --
-- any derivative work contains this copyright notice. --
-- --
-- Package Name : std_logic_arith --
-- --
-- Purpose : This package is to allow the synthesis of the 1164 package. --
-- This package add the capability of SIGNED/UNSIGNED math. --
-- --
----------------------------------------------------------------------------
LIBRARY ieee ;
PACKAGE std_logic_arith IS
USE ieee.std_logic_1164.ALL;
TYPE SIGNED IS ARRAY (Natural RANGE <>) OF STD_LOGIC ;
TYPE UNSIGNED IS ARRAY (Natural RANGE <>) OF STD_LOGIC ;
FUNCTION std_ulogic_wired_or ( input : std_ulogic_vector ) RETURN std_ulogic;
FUNCTION std_ulogic_wired_and ( input : std_ulogic_vector ) RETURN std_ulogic;
-------------------------------------------------------------------------------
-- Note that all functions that take two vector arguments will
-- handle unequal argument lengths
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Conversion Functions
-------------------------------------------------------------------
-- Except for the to_integer and conv_integer functions for the
-- signed argument all others assume the input vector to be of
-- magnitude representation. The signed functions assume
-- a 2's complement representation.
FUNCTION to_integer ( arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER;
FUNCTION to_integer ( arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER;
FUNCTION to_integer ( arg1 : STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL;
FUNCTION to_integer ( arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL;
FUNCTION to_integer ( arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER;
FUNCTION conv_integer ( arg1 : STD_ULOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER;
FUNCTION conv_integer ( arg1 : STD_LOGIC_VECTOR; x : INTEGER := 0 ) RETURN INTEGER;
FUNCTION conv_integer ( arg1 : STD_LOGIC; x : INTEGER := 0 ) RETURN NATURAL;
FUNCTION conv_integer ( arg1 : UNSIGNED; x : INTEGER := 0 ) RETURN NATURAL;
FUNCTION conv_integer ( arg1 : SIGNED; x : INTEGER := 0 ) RETURN INTEGER;
-- Following functions will return the natural argument in magnitude representation.
FUNCTION to_stdlogic ( arg1 : BOOLEAN ) RETURN STD_LOGIC;
FUNCTION to_stdlogicvector ( arg1 : INTEGER; size : NATURAL ) RETURN STD_LOGIC_VECTOR;
FUNCTION to_stdulogicvector ( arg1 : INTEGER; size : NATURAL ) RETURN STD_ULOGIC_VECTOR;
FUNCTION to_unsigned ( arg1 : NATURAL; size : NATURAL ) RETURN UNSIGNED;
FUNCTION conv_unsigned ( arg1 : NATURAL; size : NATURAL ) RETURN UNSIGNED;
-- The integer argument is returned in 2's complement representation.
FUNCTION to_signed ( arg1 : INTEGER; size : NATURAL ) RETURN SIGNED;
FUNCTION conv_signed ( arg1 : INTEGER; size : NATURAL ) RETURN SIGNED;
-------------------------------------------------------------------------------
-- sign/zero extend FUNCTIONs
-------------------------------------------------------------------------------
-- The zero_extend functions will perform zero padding to the input vector,
-- returning a vector of length equal to size (the second argument). Note that
-- if size is less than the length of the input argument an assertion will occur.
FUNCTION zero_extend ( arg1 : STD_ULOGIC_VECTOR; size : NATURAL ) RETURN STD_ULOGIC_VECTOR;
FUNCTION zero_extend ( arg1 : STD_LOGIC_VECTOR; size : NATURAL ) RETURN STD_LOGIC_VECTOR;
FUNCTION zero_extend ( arg1 : STD_LOGIC; size : NATURAL ) RETURN STD_LOGIC_VECTOR;
FUNCTION zero_extend ( arg1 : UNSIGNED; size : NATURAL ) RETURN UNSIGNED;
FUNCTION sign_extend ( arg1 : SIGNED; size : NATURAL ) RETURN SIGNED;
-------------------------------------------------------------------------------
-- Arithmetic functions
-------------------------------------------------------------------------------
-- All arithmetic functions except multiplication will return a vector
-- of size equal to the size of its largest argument. For multiplication,
-- the resulting vector has a size equal to the sum of the size of its inputs.
-- Note that arguments of unequal lengths are allowed.
FUNCTION "+" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC;
FUNCTION "+" ( arg1, arg2 : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "+" ( arg1, arg2 : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "+" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED ;
FUNCTION "+" ( arg1, arg2 : SIGNED ) RETURN SIGNED ;
FUNCTION "-" ( arg1, arg2 : STD_LOGIC ) RETURN STD_LOGIC;
FUNCTION "-" ( arg1, arg2 : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "-" ( arg1, arg2 : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "-" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED;
FUNCTION "-" ( arg1, arg2 : SIGNED ) RETURN SIGNED;
FUNCTION "+" ( arg1 : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "+" ( arg1 : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "+" ( arg1 : UNSIGNED ) RETURN UNSIGNED;
FUNCTION "+" ( arg1 : SIGNED ) RETURN SIGNED;
FUNCTION "-" ( arg1 : SIGNED ) RETURN SIGNED;
FUNCTION "*" ( arg1, arg2 : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "*" ( arg1, arg2 : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "*" ( arg1, arg2 : UNSIGNED ) RETURN UNSIGNED ;
FUNCTION "*" ( arg1, arg2 : SIGNED ) RETURN SIGNED ;
FUNCTION "abs" ( arg1 : SIGNED) RETURN SIGNED;
-- Vectorized Overloaded Arithmetic Operators, not supported for synthesis.
-- The following operators are not supported for synthesis.
FUNCTION "/" ( l, r : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "/" ( l, r : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "/" ( l, r : UNSIGNED ) RETURN UNSIGNED;
FUNCTION "/" ( l, r : SIGNED ) RETURN SIGNED;
FUNCTION "MOD" ( l, r : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "MOD" ( l, r : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "MOD" ( l, r : UNSIGNED ) RETURN UNSIGNED;
FUNCTION "REM" ( l, r : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "REM" ( l, r : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "REM" ( l, r : UNSIGNED ) RETURN UNSIGNED;
FUNCTION "**" ( l, r : STD_ULOGIC_VECTOR ) RETURN STD_ULOGIC_VECTOR;
FUNCTION "**" ( l, r : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR;
FUNCTION "**" ( l, r : UNSIGNED ) RETURN UNSIGNED;
-------------------------------------------------------------------------------
-- Shift and rotate functions.
-------------------------------------------------------------------------------
-- Note that all the shift and rotate functions below will change to overloaded
-- operators in the train1 release.
FUNCTION "sla" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "sla" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "sla" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ;
FUNCTION "sla" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ;
FUNCTION "sra" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "sra" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "sra" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ;
FUNCTION "sra" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ;
FUNCTION "sll" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "sll" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "sll" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ;
FUNCTION "sll" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ;
FUNCTION "srl" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "srl" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "srl" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ;
FUNCTION "srl" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ;
FUNCTION "rol" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "rol" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "rol" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ;
FUNCTION "rol" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ;
FUNCTION "ror" (arg1:UNSIGNED ; arg2:NATURAL) RETURN UNSIGNED ;
FUNCTION "ror" (arg1:SIGNED ; arg2:NATURAL) RETURN SIGNED ;
FUNCTION "ror" (arg1:STD_ULOGIC_VECTOR ; arg2:NATURAL) RETURN STD_ULOGIC_VECTOR ;
FUNCTION "ror" (arg1:STD_LOGIC_VECTOR ; arg2:NATURAL) RETURN STD_LOGIC_VECTOR ;
-------------------------------------------------------------------------------
-- Comparision functions and operators.
-------------------------------------------------------------------------------
-- For all comparision operators, the default operator for signed and unsigned
-- types has been overloaded to perform logical comparisions. Note that for
-- other types the default operator is not overloaded and the use will result
-- in literal comparisions which is not supported for synthesis.
--
-- Unequal operator widths are supported for all the comparision functions.
FUNCTION eq ( l, r : STD_LOGIC ) RETURN BOOLEAN;
FUNCTION eq ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION eq ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION eq ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION eq ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION "=" ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION "=" ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION ne ( l, r : STD_LOGIC ) RETURN BOOLEAN;
FUNCTION ne ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION ne ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION ne ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION ne ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION "/=" ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION "/=" ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION lt ( l, r : STD_LOGIC ) RETURN BOOLEAN;
FUNCTION lt ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION lt ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION lt ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION lt ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION "<" ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION "<" ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION gt ( l, r : STD_LOGIC ) RETURN BOOLEAN;
FUNCTION gt ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION gt ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION gt ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION gt ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION ">" ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION ">" ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION le ( l, r : STD_LOGIC ) RETURN BOOLEAN;
FUNCTION le ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION le ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION le ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION le ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION "<=" ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION "<=" ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION ge ( l, r : STD_LOGIC ) RETURN BOOLEAN;
FUNCTION ge ( l, r : STD_ULOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION ge ( l, r : STD_LOGIC_VECTOR ) RETURN BOOLEAN;
FUNCTION ge ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION ge ( l, r : SIGNED ) RETURN BOOLEAN ;
FUNCTION ">=" ( l, r : UNSIGNED ) RETURN BOOLEAN ;
FUNCTION ">=" ( l, r : SIGNED ) RETURN BOOLEAN ;
-------------------------------------------------------------------------------
-- Logical operators.
-------------------------------------------------------------------------------
-- allows operands of unequal lengths, return vector is
-- equal to the size of the largest argument.
FUNCTION "and" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "and" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION "nand" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "nand" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION "or" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "or" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION "nor" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "nor" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION "xor" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "xor" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
FUNCTION "not" (arg1:SIGNED) RETURN SIGNED;
FUNCTION "not" (arg1:UNSIGNED) RETURN UNSIGNED;
FUNCTION "xnor" (arg1, arg2:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR;
FUNCTION "xnor" (arg1, arg2:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
FUNCTION "xnor" (arg1, arg2:SIGNED) RETURN SIGNED;
FUNCTION "xnor" (arg1, arg2:UNSIGNED) RETURN UNSIGNED;
END std_logic_arith ;
| gpl-2.0 |
siavooshpayandehazad/TTU_CPU_Project | pico_CPU_pipelined/Adder.vhd | 2 | 1122 | library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.NUMERIC_STD.ALL;
use work.pico_cpu.all;
--Adder entity
entity Adder_Sub is
generic (BitWidth: integer);
port (
A: in std_logic_vector (BitWidth-1 downto 0);
B: in std_logic_vector (BitWidth-1 downto 0);
Add_Sub: in std_logic;
result: out std_logic_vector (BitWidth-1 downto 0);
Cout: out std_logic
);
end Adder_Sub;
--Architecture of the Adder
architecture RTL of Adder_Sub is
---------------------------------------------
-- Signals
---------------------------------------------
signal carry : std_logic_vector (bitwidth downto 0) := (others => '0');
---------------------------------------------
begin
carry(0) <= Add_Sub;
---------------------------------------------
-- component instantiation
---------------------------------------------
g_counter: for N in 0 to bitwidth-1 generate
ADDN : FullAdderSub port map (carry(N),A(N),B(N),Add_Sub,carry(N+1),result(N));
end generate;
---------------------------------------------
Cout <= carry(bitwidth);
end RTL;
| gpl-2.0 |
joaocarlos/ModelSIM-compile | counter.vhd | 2 | 790 | -- Up down counter
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_std.all;
entity Counter is
port (Clock, Reset, Enable, Load, UpDn: in Std_logic;
Data: in Std_logic_vector(7 downto 0);
Q: out Std_logic_vector(7 downto 0));
end;
architecture RTL of Counter is
signal Cnt: Unsigned(7 downto 0);
begin
process (Clock, Reset)
begin
if Reset = '1' then
Cnt <= "00000000";
elsif Rising_edge(Clock) then
if Enable = '0' then
null;
elsif Load = '1' then
Cnt <= Unsigned(Data);
else
if UpDn = '1' then
Cnt <= Cnt + 1;
else
Cnt <= Cnt - 1;
end if;
end if;
end if;
end process;
Q <= Std_logic_vector(Cnt);
end;
| gpl-2.0 |
siavooshpayandehazad/TTU_CPU_Project | pico_CPU_pipelined/ALU.vhd | 1 | 2509 | library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use work.pico_cpu.all;
--ALU entity
entity ALU is
generic (BitWidth: integer);
port ( A: in std_logic_vector (BitWidth-1 downto 0);
B: in std_logic_vector (BitWidth-1 downto 0);
Command: in std_logic_vector (3 downto 0);
Cflag_in: in std_logic;
Cflag_out: out std_logic;
Result: out std_logic_vector (BitWidth-1 downto 0)
);
end ALU;
--Architecture of the DPU
architecture RTL of ALU is
---------------------------------------------
-- Signals
---------------------------------------------
signal AddSub_result: std_logic_vector (BitWidth-1 downto 0) := (others => '0');
signal Cout,Add_Sub: std_logic := '0';
begin
---------------------------------------------
-- component instantiation
---------------------------------------------
Adder_comp: Adder_Sub generic map (BitWidth => BitWidth) port map (A,B,Add_Sub,AddSub_result,Cout);
---------------------------------------------
Cflag_out <= Cout;
PROC_ALU: process(Command,A,B,AddSub_result,Cflag_in)
begin
Add_Sub <= '0'; --adding by default
case Command is
WHEN ALU_ADD => Result<= AddSub_result; --add
WHEN ALU_SUB => Add_Sub <= '1';
Result<= AddSub_result; -- Subtract
WHEN ALU_PASS_A => Result <= A; --Bypass A
WHEN ALU_PASS_B => Result <= B; --Bypass B
WHEN ALU_AND => Result<= A and B; --And
WHEN ALU_OR => Result<= A or B; --or
WHEN ALU_XOR => Result<= A xor B; --xor
WHEN ALU_SLR => Result<= '0' & A(BitWidth-1 downto 1) ; --shift right
WHEN ALU_SLL => Result<= A(BitWidth-2 downto 0)& '0' ; --shift left
WHEN ALU_NEG_A => Result<= not A +1; --negation
WHEN ALU_SAR => Result<= A(BitWidth-1) & A(BitWidth-1 downto 1) ; --shift right Arith
WHEN ALU_SAL => Result<= A(BitWidth-1) & A(BitWidth-3 downto 0)& A(0) ; --shift left Arith
WHEN ALU_NOT_A => Result<= not(A); --Not of A
WHEN ALU_CLR_A => Result<= (others => '0'); --Clear ACC
WHEN ALU_RRC => Result<= Cflag_in & A(BitWidth-1 downto 1); -- RRC
WHEN ALU_RLC => Result<= A(BitWidth-2 downto 0)& Cflag_in ; -- RLC
WHEN OTHERS => Result<= (others => '0');
END CASE;
end process PROC_ALU;
end RTL;
| gpl-2.0 |
Logistic1994/CPU | module_CPU.vhd | 1 | 11422 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:35:09 06/03/2015
-- Design Name:
-- Module Name: module_CPU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity module_CPU is
port (
clk: in std_logic; -- ʱÖÓ
nreset: in std_logic;
io_input: in std_logic_vector(7 downto 0);
io_output: out std_logic_vector(7 downto 0);
data_test: out std_logic_vector(7 downto 0);
ar_test: out std_logic_vector(6 downto 0);
cm_test: out std_logic_vector(47 downto 0);
addr_test: out std_logic_vector(11 downto 0);
ir_test: out std_logic_vector(7 downto 0);
pc_test: out std_logic_vector(11 downto 0);
c1_test, c2_test, n1_test, n2_test, w0_test, w1_test, w2_test, w3_test: out std_logic;
ir_ctest: out std_logic;
rs_test, rd_test: out std_logic;
pc_ntest: out std_logic;
nload_test, x_test, z_test: out std_logic;
count_test: out integer);
end module_CPU;
architecture Behavioral of module_CPU is
-- ÉêÃ÷ËùÓеÄÄ£¿é
-- ¶þ·ÖƵÆ÷
component module_Divider
port(
clk: in std_logic;
nreset: in std_logic;
clk2: out std_logic);
end component;
-- MC
component module_MC
port(
clk_MC: in std_logic;
nreset: in std_logic;
IR: in std_logic_vector(7 downto 2);
M_uA: in std_logic; -- ΢µØÖ·¿ØÖÆÐźÅ
CMROM_CS: in std_logic; -- ¿ØÖÆ´æ´¢Æ÷ѡͨÐźÅ
CM: out std_logic_vector(47 downto 0)); -- ΢¿ØÖÆÊä³ö
end component;
-- ROM
component module_ROM
port (
clk_ROM: in std_logic;
M_ROM: in std_logic;
nROM_EN: in std_logic;
addr: in std_logic_vector(11 downto 0);
datao: out std_logic_vector(7 downto 0);
do: out std_logic);
end component;
-- IR
component module_IR
port (
clk_IR: in std_logic;
nreset: in std_logic;
LD_IR1, LD_IR2, LD_IR3: in std_logic; -- ¿ØÖÆÐźÅ
nARen: in std_logic; -- ramµØÖ·¿ØÖÆÐźÅ
datai: in std_logic_vector(7 downto 0);
IR: out std_logic_vector(7 downto 0); -- IRÖ¸Áî±àÂë
PC: out std_logic_vector(11 downto 0); -- PCеØÖ·
ARo: out std_logic_vector(6 downto 0); -- RAM¶ÁдµØÖ·
ao: out std_logic;
RS, RD: out std_logic); -- Ô´¼Ä´æÆ÷ºÍÄ¿µÄ¼Ä´æÆ÷
end component;
-- PC
component module_PC
port (
clk_PC: in std_logic; -- ʱÖÓ
nreset: in std_logic; -- È«¾Ö¸´Î»ÐźÅ
nLD_PC: in std_logic; -- µØÖ·¸üÐÂ
M_PC: in std_logic; -- PC¼ÓÒ»
nPCH: in std_logic; -- PCÊä³öµ½×ÜÏߵĿØÖÆÐźÅ
nPCL: in std_logic; -- PCÊä³öµ½×ÜÏߵĿØÖÆÐźÅ
PC: in std_logic_vector(11 downto 0); -- 12λµÄPC
ADDR: out std_logic_vector(11 downto 0); -- ROM¶ÁµØÖ·Êä³ö
datao: out std_logic_vector(7 downto 0);-- PCÊýÖµÊä³öµ½Êý¾Ý×ÜÏß
do: out std_logic);
end component;
-- P0
component module_P0
port(
clk_P0: in std_logic;
nreset: in std_logic;
P0_CS: in std_logic;
nP0_IEN: in std_logic; --ÊäÈëʹÄÜ
nP0_OEN: in std_logic; --Êä³öʹÄÜ
P0_IN: in std_logic_vector(7 downto 0);
P0_OUT: out std_logic_vector(7 downto 0);
datai: in std_logic_vector(7 downto 0);
datao: out std_logic_vector(7 downto 0);
do: out std_logic);
end component;
-- SP
component module_SP
port(
clk_SP: in std_logic;
nreset: in std_logic;
SP_CS: in std_logic; --Ƭѡ
SP_UP: in std_logic; -- +1£¬¼´³öÕ»
SP_DN: in std_logic; -- -1£¬¼´ÈëÕ»
nSP_EN: in std_logic; --µ±Õâ¸öΪ0ʱ£¬upÓëdownÓÐЧ£»µ±Õâ¸öΪ1ʱ±íʾÐèÒª¸üÐÂSPÁË
ARo: out std_logic_vector(6 downto 0);
ao: out std_logic;
datai: in std_logic_vector(7 downto 0));
end component;
-- RAM
component module_RAM
port(
clk_RAM: in std_logic;
nreset: in std_logic;
RAM_CS: in std_logic; -- RAMƬѡ
nRAM_EN: in std_logic; -- RAMÊä³öʹÄÜ
WR_nRD: in std_logic; -- 1Ϊд£¬0Ϊ¶Á
ARi: in std_logic_vector(6 downto 0); -- RAMµØÖ·ÐźÅ
datai: in std_logic_vector(7 downto 0);
datao: out std_logic_vector(7 downto 0); -- Êý¾Ý×ÜÏß
do: out std_logic);
end component;
-- RN
component module_Rn
port(
clk_RN: in std_logic;
nreset: in std_logic;
Rn_CS: in std_logic; -- µ±Rn_CS='0'²¢ÇÒ´¦ÓÚ¶ÁµÄʱºò£¬¶ÁÈ¡RDÀïÃæµÄÊý¾Ý
nRi_EN: in std_logic; -- µÍµçƽÓÐЧ
RDRi, WRRi: in std_logic; -- ¸ßµçƽÓÐЧ
RS: in std_logic;
RD: in std_logic;
datai: in std_logic_vector(7 downto 0);
datao: out std_logic_vector(7 downto 0);
do: out std_logic);
end component;
-- ALU
component module_ALU
port(
clk_ALU: in std_logic;
nreset: in std_logic;
M_A, M_B: in std_logic; -- ÔÝ´æÆ÷¿ØÖÆÐźÅ
M_F: in std_logic; -- ÒÆλµÄ¿ØÖÆÐźÅ
nALU_EN: in std_logic; -- ALU½á¹ûÊä³öʹÄÜ
nPSW_EN: in std_logic; -- PSWÊä³öʹÄÜ
C0: in std_logic; -- ½øλÊäÈë
S: in std_logic_vector(4 downto 0); -- ÔËËãÀàÐͺͲÙ×÷Ñ¡Ôñ
F_in: in std_logic_vector(1 downto 0); -- ÒÆλ¹¦ÄÜÑ¡Ôñ
datai: in std_logic_vector(7 downto 0); -- Êý¾Ý
datao: out std_logic_vector(7 downto 0);
do: out std_logic;
AC: out std_logic;
CY: out std_logic;
ZN: out std_logic;
OV: out std_logic);
end component;
-- CLK
component module_CLK
port (
clk: in std_logic;
nreset: in std_logic;
clk1, nclk1: out std_logic;
clk2, nclk2: out std_logic;
w0, w1, w2, w3: out std_logic);
end component;
-- signals
signal IR: std_logic_vector(7 downto 0);
signal CM: std_logic_vector(47 downto 0);
signal ADDR: std_logic_vector(11 downto 0);
signal DATA: std_logic_vector(7 downto 0); -- Õâ¸öÐźſÉÒÔÓÃÓÚËùÓеÄÊäÈë
signal PC: std_logic_vector(11 downto 0);
signal AR: std_logic_vector(6 downto 0);
signal RS, RD: std_logic;
signal AC, CY, ZN, OV: std_logic; -- AC°ë£¬CYÈ«£¬ZN0£¬OVÒç³ö
signal PC_nload: std_logic;
signal clk1, clk2, nclk1, nclk2, w0, w1, w2, w3: std_logic;
signal clk_double: std_logic;
signal clk_MC, clk_ROM, clk_IR, clk_PC, clk_P0, clk_SP, clk_RAM, clk_Rn, clk_ALU: std_logic;
signal d_ROM, d_PC, d_P0, d_RAM, d_Rn, d_ALU: std_logic_vector(7 downto 0); -- ÕâЩÐźÅÓÃÓÚÊä³ö
signal do_ROM, do_PC, do_P0, do_RAM, do_Rn, do_ALU: std_logic;
signal a_IR, a_SP: std_logic_vector(6 downto 0);
signal ao_IR, ao_SP: std_logic;
signal clk_count: std_logic;
signal count: integer;
begin
-- ʱÖÓ
clk_MC <= w0;
clk_ROM <= nclk1 and w0 and clk2;
clk_IR <= nclk2 and w0;
clk_PC <= nclk1 and w0 and nclk2;
clk_P0 <= w1;
clk_SP <= nclk1 and w1 and clk2;
clk_RAM <= nclk1 and w1 and nclk2;
clk_Rn <= nclk1 and w2 and clk2;
clk_ALU <= nclk1 and w2 and nclk2;
clk_count <= clk and (w0 or w1 or w2 or w3);
PC_nload <= (CM(22) or ((not CM(12)) and ZN));
-- for test
data_test <= DATA;
ar_test <= AR;
cm_test <= CM;
addr_test <= ADDR;
ir_test <= IR;
pc_test <= PC;
c1_test <= clk1;
c2_test <= clk2;
n1_test <= nclk1;
n2_test <= nclk2;
w0_test <= w0;w1_test <= w1;w2_test <= w2;w3_test <= w3;
count_test <= count;
ir_ctest <= clk_IR;
rs_test <= RS;
rd_test <= RD;
pc_ntest <= PC_nload;
nload_test <= CM(22);
x_test <= CM(12);
z_test <= ZN;
process(nreset, clk_count) -- ½øÐÐÊý¾ÝÑ¡Ôñ
begin
if nreset = '0' then
count <= 0;
elsif falling_edge(clk_count) then
if count = 1 then -- for update ROM
if do_ROM = '1' then
DATA <= d_ROM;
AR <= AR;
else
DATA <= DATA;
AR <= AR;
end if;
elsif count = 2 then -- for update IR
if ao_IR = '1' then
AR <= a_IR;
DATA <= DATA;
else
DATA <= DATA;
AR <= AR;
end if;
elsif count = 3 then -- for update PC
if do_PC = '1' then
DATA <= d_PC;
AR <= AR;
else
DATA <= DATA;
AR <= AR;
end if;
elsif count = 4 then -- for update P0
if do_P0 = '1' then
DATA <= d_P0;
AR <= AR;
else
DATA <= DATA;
AR <= AR;
end if;
elsif count = 5 then -- for update SP
if ao_SP = '1' then
AR <= a_SP;
DATA <= DATA;
else
DATA <= DATA;
AR <= AR;
end if;
elsif count = 7 then -- for update RAM
if do_RAM = '1' then
DATA <= d_RAM;
AR <= AR;
else
DATA <= DATA;
AR <= AR;
end if;
elsif count = 9 then -- for update Rn
if do_Rn = '1' then
DATA <= d_Rn;
AR <= AR;
else
DATA <= DATA;
AR <= AR;
end if;
elsif count = 11 then -- for update ALU
if do_ALU = '1' then
DATA <= d_ALU;
AR <= AR;
else
DATA <= DATA;
AR <= AR;
end if;
else
DATA <= DATA;
AR <= AR;
end if;
if count = 15 then
count <= 0;
else
count <= count + 1;
end if;
end if;
end process;
U_MC:
module_MC
port map(
clk_MC => clk_MC,
nreset => nreset,
IR => IR(7 downto 2),
M_uA => CM(9),
CMROM_CS => CM(8),
CM => CM);
U_ROM:
module_ROM
port map(
clk_ROM => clk_ROM,
M_ROM => CM(11),
nROM_EN => CM(10),
addr => ADDR,
datao => d_ROM,
do => do_ROM);
U_IR:
module_IR
port map(
clk_IR => clk_IR,
nreset => nreset,
LD_IR1 => CM(27),
LD_IR2 => CM(26),
LD_IR3 => CM(25),
nARen => CM(24),
datai => DATA,
IR => IR,
PC => PC,
ARo => a_IR,
ao => ao_IR,
RS => RS,
RD => RD);
U_PC:
module_PC
port map(
clk_PC => clk_PC,
nreset => nreset,
nLD_PC => PC_nload,
M_PC => CM(23),
nPCH => CM(21),
nPCL => CM(20),
PC => PC,
ADDR => ADDR,
datao => d_PC,
do => do_PC);
U_P0:
module_P0
port map(
clk_P0 => clk_P0,
nreset => nreset,
P0_CS => CM(15),
nP0_IEN => CM(14),
nP0_OEN => CM(13),
P0_IN => io_input,
P0_OUT => io_output,
datai => DATA,
datao => d_P0,
do => do_P0);
U_SP:
module_SP
port map(
clk_SP => clk_SP,
nreset => nreset,
SP_CS => CM(17),
SP_UP => CM(19),
SP_DN => CM(18),
nSP_EN => CM(16),
ARo => a_SP,
ao => ao_SP,
datai => DATA);
U_RAM:
module_RAM
port map(
clk_RAM => clk_RAM,
nreset => nreset,
RAM_CS => CM(34),
nRAM_EN => CM(32),
WR_nRD => CM(33),
ARi => AR,
datai => DATA,
datao => d_RAM,
do => do_RAM);
U_Rn:
module_Rn
port map(
clk_RN => clk_Rn,
nreset => nreset,
Rn_CS => CM(31),
nRi_EN => CM(28),
RDRi => CM(30),
WRRi => CM(29),
RS => RS,
RD => RD,
datai => DATA,
datao => d_Rn,
do => do_Rn);
U_ALU:
module_ALU
port map(
clk_ALU => clk_ALU,
nreset => nreset,
M_A => CM(47),
M_B => CM(46),
M_F => CM(45),
nALU_EN => CM(37),
nPSW_EN => CM(36),
C0 => CM(35),
S(4) => CM(44),
S(3) => CM(43),
S(2) => CM(42),
S(1) => CM(41),
S(0) => CM(40),
F_in(1) => CM(39),
F_in(0) => CM(38),
datai => DATA,
datao => d_ALU,
do => do_ALU,
AC => AC,
CY => CY,
ZN => ZN,
OV => OV);
U_CLK:
module_CLK
port map(
clk => clk_double,
nreset => nreset,
clk1 => clk1,
nclk1 => nclk1,
clk2 => clk2,
nclk2 => nclk2,
w0 => w0,
w1 => w1,
w2 => w2,
w3 => w3);
U_Divider:
module_Divider
port map(
clk => clk,
nreset => nreset,
clk2 => clk_double);
end Behavioral;
| gpl-2.0 |
Logistic1994/CPU | module_74181.vhd | 1 | 5810 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:40:00 05/25/2015
-- Design Name:
-- Module Name: module_74181 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity module_74181 is
port (
M: in std_logic; -- Ñ¡ÔñÂß¼»òÕßËãÊõ
A: in std_logic_vector(3 downto 0); -- ÊäÈëÊýA
B: in std_logic_vector(3 downto 0); -- ÊäÈëÊýB
S: in std_logic_vector(3 downto 0); -- op
C0: in std_logic; -- ½øλÊäÈë
result: out std_logic_vector(3 downto 0); -- ½á¹û
CN: out std_logic); -- ½øλÊä³ö
end module_74181;
architecture Behavioral of module_74181 is
signal lres: std_logic_vector(3 downto 0);
signal ares: std_logic_vector(4 downto 0);
signal aA, aB: std_logic_vector(4 downto 0);
begin
result <=
ares(3 downto 0) when M = '0' else
lres;
CN <=
'0' when M = '1' else
'1' when S = "0000" and ares(4) = '0' else
'0' when S = "0000" and ares(4) = '1' else
'1' when S = "1111" and ares(4) = '0' else
'0' when S = "1111" and ares(4) = '1' else
ares(4);
process(M, A, B, S, C0)
begin
if M = '1' then
-- Âß¼ÔËËã
ares <= (others => '0');
aA <= (others => '0');
aB <= (others => '0');
case S is
when "0000" =>
lres <= not A;
when "0001" =>
lres <= not (A or B);
when "0010" =>
lres <= (not A) and B;
when "0011" =>
lres <= (others => '0');
when "0100" =>
lres <= not (A and B);
when "0101" =>
lres <= not B;
when "0110" =>
lres <= A xor B;
when "0111" =>
lres <= A and (not B);
when "1000" =>
lres <= A or B;
when "1001" =>
lres <= not (A xor B);
when "1010" =>
lres <= B;
when "1011" =>
lres <= A and B;
when "1100" =>
lres <= (others => '1');
when "1101" =>
lres <= A or (not B);
when "1110" =>
lres <= A or B;
when others =>
lres <= A;
end case;
-- Êä³ö
--result <= lres;
--CN <= '0';
elsif M = '0' then
-- ËãÊõÔËËã
lres <= (others => '0');
aA <= '0' & A;
aB <= '0' & B;
case S is
when "0000" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA) + 1);
else
ares <= std_logic_vector(unsigned(aA));
end if;
when "0001" =>
if C0 = '0' then
ares <= aA or aB;
else
ares <= std_logic_vector(unsigned(aA or aB) + 1);
end if;
when "0010" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA or (not aB)));
else
ares <= std_logic_vector(unsigned(aA or (not aB)) + 1);
end if;
when "0011" =>
if C0 = '0' then
ares <= (others => '1');
else
ares <= (others => '0');
end if;
when "0100" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA) + unsigned(aA and (not aB)));
else
ares <= std_logic_vector(unsigned(aA) + unsigned(aA and (not aB)) + 1);
end if;
when "0101" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA or aB) + unsigned(aA and (not aB)));
else
ares <= std_logic_vector(unsigned(aA or aB) + unsigned(aA and (not aB)) + 1);
end if;
when "0110" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA) - unsigned(aB));
else
ares <= std_logic_vector(unsigned(aA) - unsigned(aB) - 1);
end if;
when "0111" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA and (not aB)) - 1);
else
ares <= std_logic_vector(unsigned(aA and (not aB)));
end if;
when "1000" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA) + unsigned(aA and aB));
else
ares <= std_logic_vector(unsigned(aA) + unsigned(aA and aB) + 1);
end if;
when "1001" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA) + unsigned(aB));
else
ares <= std_logic_vector(unsigned(aA) + unsigned(aB) + 1);
end if;
when "1010" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA or (not aB)) + unsigned(aA and aB));
else
ares <= std_logic_vector(unsigned(aA or (not aB)) + unsigned(aA and aB) + 1);
end if;
when "1011" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA and aB) - 1);
else
ares <= std_logic_vector(unsigned(aA and aB));
end if;
when "1100" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA) + unsigned(aA));
else
ares <= std_logic_vector(unsigned(aA) + unsigned(aA) + 1);
end if;
when "1101" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA or aB) + unsigned(aA));
else
ares <= std_logic_vector(unsigned(aA or aB) + unsigned(aA) + 1);
end if;
when "1110" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA or (not aB)) + unsigned(aA));
else
ares <= std_logic_vector(unsigned(aA or (not aB)) + unsigned(aA) + 1);
end if;
when "1111" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA) - 1);
else
ares <= aA;
end if;
when others =>
ares <= (others => '0');
end case;
-- Êä³ö
--result <= ares(3 downto 0);
--CN <= ares(4);
end if;
end process;
end Behavioral;
| gpl-2.0 |
siavooshpayandehazad/TTU_CPU_Project | pico_CPU_pipelined_MIPS32/DPU.vhd | 1 | 3292 | --Copyright (C) 2017 Siavoosh Payandeh Azad
-- DPU has one fixed input which is coming directly from Register-File
-- The other input is selectable between Rfile, Memory, Control
library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_misc.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
--DPU entity
entity DPU is
generic (BitWidth: integer);
port (
rst: in std_logic;
clk: in std_logic;
Data_in_mem: in std_logic_vector (BitWidth-1 downto 0);
Data_in_RegFile_1: in std_logic_vector (BitWidth-1 downto 0);
Data_in_RegFile_2: in std_logic_vector (BitWidth-1 downto 0);
Data_in_control_2: in std_logic_vector (BitWidth-1 downto 0);
ALUCommand: in ALU_COMMAND;
Mux_Cont_2: in DPU_IN_MUX;
DPU_OV : out std_logic;
Result : out std_logic_vector (2*BitWidth-1 downto 0);
Result_ACC : out std_logic_vector (2*BitWidth-1 downto 0)
);
end DPU;
--Architecture of the DPU
architecture RTL of DPU is
---------------------------------------------
-- Signals
---------------------------------------------
signal ACC_in, ACC_out: std_logic_vector (2*BitWidth-1 downto 0);
signal Mux_Out_1, Mux_Out_2: std_logic_vector (BitWidth-1 downto 0):= (others=>'0');
---------------------------------------------
-- Flags
---------------------------------------------
signal OV_Flag_Value, Cout :std_logic := '0';
begin
ALU_comp: ALU
generic map (BitWidth => BitWidth)
port map (Mux_Out_1, Mux_Out_2, ALUCommand, OV_Flag_Value, Cout, ACC_in);
---------------------------------------------
-- Registers and Flags
---------------------------------------------
CLOCK_PROCESS:process (clk,rst)
begin
if rst = '1' then
ACC_out<=(others =>'0');
elsif clk'event and clk= '1' then
if ALUCommand = ALU_MULT or ALUCommand = ALU_MULTU or ALUCommand = ALU_MTHI or
ALUCommand = ALU_MTLO or ALUCommand = ALU_DIV or ALUCommand = ALU_DIVU then
ACC_out <= ACC_in;
elsif ALUCommand = ALU_MADD then
ACC_out <= std_logic_vector(signed(ACC_in) + signed(ACC_out));
elsif ALUCommand = ALU_MADDU then
ACC_out <= std_logic_vector(unsigned(ACC_in) + unsigned(ACC_out));
elsif ALUCommand = ALU_MSUB then
ACC_out <= std_logic_vector(signed(ACC_in) - signed(ACC_out));
elsif ALUCommand = ALU_MSUBU then
ACC_out <= std_logic_vector(unsigned(ACC_in) - unsigned(ACC_out));
end if;
end if;
end process;
---------------------------------------------
-- ALU Input multiplexer
---------------------------------------------
Mux_Out_1 <= Data_in_RegFile_1;
INPUT_MUX_2:process (Data_in_mem, Data_in_control_2, Data_in_RegFile_2, Mux_Cont_2)
begin
case Mux_Cont_2 is
when MEM => Mux_Out_2 <= Data_in_mem;
when CONT => Mux_Out_2 <= Data_in_control_2;
when RFILE => Mux_Out_2 <= Data_in_RegFile_2;
when ONE => Mux_Out_2 <= std_logic_vector(to_unsigned(1, BitWidth));
when others => Mux_Out_2 <= std_logic_vector(to_unsigned(0, BitWidth));
end case;
end process;
Result <= ACC_in;
Result_ACC <= ACC_out;
DPU_OV <= OV_Flag_Value;
end RTL;
| gpl-2.0 |
Logistic1994/CPU | module_MC.vhd | 1 | 2488 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:29:59 05/29/2015
-- Design Name:
-- Module Name: micro_controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity module_MC is
port(
clk_MC: in std_logic;
nreset: in std_logic;
IR: in std_logic_vector(7 downto 2);
M_uA: in std_logic; -- ΢µØÖ·¿ØÖÆÐźÅ
CMROM_CS: in std_logic; -- ¿ØÖÆ´æ´¢Æ÷ѡͨÐźÅ
CM: out std_logic_vector(47 downto 0)); -- ΢¿ØÖÆÊä³ö
end module_MC;
architecture Behavioral of module_MC is
type matrix is array (integer range<>) of std_logic_vector(47 downto 0);
signal ir_table: matrix(0 to 255);
-- ´ÓÎļþÖжÁȡ΢²Ù×÷ÓëirÖ¸ÁîµÄ¶ÔÕÕ±í
procedure load_ir_table(signal data_word: out matrix) is
file tablefile: text open read_mode is "micro.txt";
variable lbuf: line; -- Ðлº´æ
variable i: integer := 0; -- ÐмÆÊýÆ÷
variable fdata: std_logic_vector(47 downto 0); -- ´ÓÿһÐÐÖжÁ³ö48λ
begin
for m in 0 to 9 loop
for n in 0 to 9 loop
for o in 0 to 1 loop
if not endfile(tablefile) then
readline(tablefile, lbuf);
hread(lbuf, fdata);
data_word(i) <= fdata;
i := i + 1;
end if;
end loop;
end loop;
end loop; -- 10 * 10 * 2 = 200;
end procedure;
signal u8: std_logic_vector(7 downto 0);
begin
load_ir_table(ir_table); -- Ò»´ÎÐÔ¶ÁÈ¡³öir_table
process(clk_MC, nreset)
begin
if nreset = '0' then
CM <= (others => 'Z');
u8 <= (others => '0');
elsif rising_edge(clk_MC) then
if M_uA = '1' and CMROM_CS = '1' then
CM <= ir_table(conv_integer(u8));
u8 <= ir_table(conv_integer(u8))(7 downto 0);
else
CM <= ir_table(conv_integer(IR & '0' & '0'));
u8 <= ir_table(conv_integer(IR & '0' & '0'))(7 downto 0);
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
siavooshpayandehazad/TTU_CPU_Project | pico_CPU/DPU.vhd | 1 | 5251 | library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_misc.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
--DPU entity
entity DPU is
generic (BitWidth: integer);
port ( Data_in_mem: in std_logic_vector (BitWidth-1 downto 0);
Data_in: in std_logic_vector (BitWidth-1 downto 0);
clk: in std_logic;
Command: in std_logic_vector (10 downto 0);
Reg_in_sel: in std_logic_vector (7 downto 0);
Reg_out_sel: in std_logic_vector (2 downto 0);
rst: in std_logic;
DPU_Flags: out std_logic_vector (3 downto 0);
Result: out std_logic_vector (BitWidth-1 downto 0)
);
end DPU;
--Architecture of the DPU
architecture RTL of DPU is
---------------------------------------------
-- Signals
---------------------------------------------
signal ACC_in,ACC_out: std_logic_vector (BitWidth-1 downto 0) := (others=>'0');
signal Reg_out: std_logic_vector (BitWidth-1 downto 0):= (others=>'0');
signal Mux_Out: std_logic_vector (BitWidth-1 downto 0):= (others=>'0');
---------------------------------------------
-- Flags
---------------------------------------------
signal EQ_Flag_out, EQ_Flag_in: std_logic := '0';
signal OV_Flag_out, OV_Flag_in: std_logic := '0';
signal Z_Flag_out, Z_Flag_in: std_logic := '0';
signal C_flag_in, C_flag_out, Cout:std_logic := '0';
signal OV_Flag_Value :std_logic := '0';
---------------------------------------------
-- Opcode Aliases
---------------------------------------------
alias Mux_Cont : std_logic_vector (1 downto 0) is Command (1 downto 0);
alias ALUCommand : std_logic_vector (3 downto 0) is Command (5 downto 2);
alias SetFlag : std_logic_vector (2 downto 0) is Command (8 downto 6);
alias B_Mux_Cont : std_logic_vector (1 downto 0) is Command (10 downto 9);
begin
ALU_comp: ALU generic map (BitWidth => BitWidth) port map (ACC_out, Mux_Out, ALUCommand,C_flag_out,Cout,ACC_in);
RegFile_comp: RegisterFile generic map (BitWidth => BitWidth) port map (clk, rst,Data_in_mem,Data_in,ACC_out,B_Mux_Cont,Reg_in_sel,Reg_out_sel,Reg_out);
---------------------------------------------
-- Registers and Flags
---------------------------------------------
process (clk,rst)
begin
if rst = '1' then
ACC_out<=(others =>'0');
OV_Flag_out <= '0';
Z_Flag_out <= '0';
EQ_Flag_out <= '0';
C_flag_out <= '0';
elsif clk'event and clk='1' then
ACC_out<=ACC_in;
OV_Flag_out <= OV_Flag_in;
Z_Flag_out <= Z_Flag_in;
EQ_Flag_out <= EQ_Flag_in;
C_flag_out <= C_flag_in;
end if;
end process;
---------------------------------------------
-- ALU 2nd Input multiplexer
---------------------------------------------
process (Data_in_mem,Data_in,Reg_out,Mux_Cont)
begin
case Mux_Cont is
when "00" => Mux_Out <= Data_in_mem;
when "01" => Mux_Out <= Data_in;
when "10" => Mux_Out <= Reg_out;
when "11" => Mux_Out <= std_logic_vector(to_unsigned(1, BitWidth ));
when others => Mux_Out <= std_logic_vector(to_unsigned(0, BitWidth ));
end case;
end process;
OV_Flag_Value <= (ACC_in(BitWidth-1 ) and Mux_Out(BitWidth-1 ) and (not ACC_out(BitWidth-1 ))) or ((not ACC_in(BitWidth-1 )) and (not Mux_Out(BitWidth-1)) and ACC_out(BitWidth-1));
---------------------------------------------
-- Flag controls
---------------------------------------------
process(SetFlag, ALUCommand, ACC_in, OV_Flag_Value, Data_in, Cout, ACC_out, EQ_Flag_out,
Z_Flag_out, C_flag_out, OV_Flag_out)
begin
----------------------------------
if SetFlag = "011" then
EQ_Flag_in <= '0';
else
if ALUCommand /= "0010" then
if (ACC_out = Data_in) then
EQ_Flag_in <= '1';
else
EQ_Flag_in <= '0';
end if;
else
EQ_Flag_in <= EQ_Flag_out;
end if;
end if;
----------------------------------
if SetFlag = "001" then
Z_Flag_in <= '0';
else
if ALUCommand /= "0010" then
Z_Flag_in <= not (or_reduce(ACC_in));
else
Z_Flag_in <= Z_Flag_out;
end if;
end if;
----------------------------------
if SetFlag = "100" then
C_flag_in <= '0';
else
if ALUCommand /= "0010" and ALUCommand /= "1110" and ALUCommand /= "1111" then
C_flag_in <= Cout;
elsif ALUCommand = "1110" then --RRC
C_flag_in <= ACC_out(0);
elsif ALUCommand = "1111" then --RLC
C_flag_in <= ACC_out(BitWidth-1);
else
C_flag_in <= C_flag_out;
END IF;
end if;
----------------------------------
if SetFlag = "010" then
OV_Flag_in <= '0';
else
if (ALUCommand = "0000" or ALUCommand = "0001") then
OV_Flag_in <= OV_Flag_Value;
else
OV_Flag_in <= OV_Flag_out;
end if;
end if;
----------------------------------
end process;
Result <= ACC_out;
DPU_Flags <= C_flag_out & EQ_Flag_out & Z_Flag_out & OV_Flag_out;
end RTL;
| gpl-2.0 |
wklimann/PCM3168 | I2S_OUT/I2S_OUT.vhd | 1 | 3432 | ---------------------------------------------------------------------------------
-- Engineer: Klimann Wendelin
--
-- Create Date: 08:36:20 11/Okt/2013
-- Design Name: i2s_out
--
-- Description:
--
-- This module provides a bridge between an I2S serial device (audio ADC, S/PDIF
-- Decoded data) and a parallel device (microcontroller, IP block).
--
-- It's coded as a generic VHDL entity, so developer can choose the proper signal
-- width (8/16/24/32 bit)
--
-- Input takes:
-- -I2S Bit Clock
-- -I2S LR Clock (Left/Right channel indication)
-- -DATA_L / DATA_R parallel inputs
--
-- Output provides:
-- -I2S Data
-- -DATA_RDY output ready signals.
--
--
-- The data from the parallel inputs is shifted to the I2S data output
--
--------------------------------------------------------------------------------
-- I2S Waveform summary
--
-- BIT_CK __ __ __ __ __ __ __ __ __
-- | 1|__| 2|_| 3|__| 4|__| 5|__... ... |32|__| 1|__| 2|__| 3| ...
--
-- LR_CK ... ... ___________________
-- ____________L_Channel_Data______________| R Channel Data ...
--
-- DATA x< 00 ><D24><D22><D21><D20> ... ... < 00 ><D24><D23> ...
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity i2s_out is
-- width: How many bits (from MSB) are gathered from the serial I2S input
generic(width : integer := 24);
port(
-- I2S ports
LR_CLK : in std_logic; --Left/Right indicator clock
BIT_CLK : in std_logic; --Bit clock
DOUT : out std_logic; --Data Output
-- Control ports
RESET : in std_logic; --Asynchronous Reset (Active Low)
-- Parallel ports
-- use (width-1 downto 0); for big endian fotmat
-- or (0 to width-1) for little endian
DATA_L : in std_logic_vector(0 to width-1);
DATA_R : in std_logic_vector(0 to width-1);
-- Output status ports
DATA_RDY_L : out std_logic; --Falling edge means data is ready
DATA_RDY_R : out std_logic --Falling edge means data is ready
);
end i2s_out;
architecture rtl of i2s_out is
--signals
signal counter : integer range 0 to width;
signal s_current_lr : std_logic;
begin
-- serial to parallel interface
i2s_out: process(RESET, BIT_CLK, LR_CLK, DATA_L, DATA_R)
begin
if(RESET = '0') then
counter <= 0;
s_current_lr <= '0';
DATA_RDY_L <= '0';
DATA_RDY_R <= '0';
DOUT <= '0';
elsif(BIT_CLK'event and BIT_CLK = '0') then
if(s_current_lr = LR_CLK) then
if(s_current_lr = '1') then
DOUT <= DATA_R(counter);
else
DOUT <= DATA_L(counter);
end if;
if(counter < width-1) then
counter <= counter + 1;
else
-- if there is a failure in the clk signals rate -> send 0 to DOUT
DOUT <= '0';
end if;
-- reset the DATA_RDY_x signals
DATA_RDY_L <= '0';
DATA_RDY_R <= '0';
-- if there is a change in the LR_CLK signal enter the else branch
else
if(s_current_lr = '1') then
DOUT <= DATA_R(counter);
DATA_RDY_R <= '1';
else
DOUT <= DATA_L(counter);
DATA_RDY_L <= '1';
end if;
counter <= 0;
s_current_lr <= LR_CLK;
end if; -- (s_current_lr = LR_CLK)
end if; -- reset / rising_edge
end process i2s_out;
end rtl;
| gpl-2.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ts_7300_usercore.vhd | 1 | 13033 | -------------------------------------------------------------------------------
--
-- Title : R4B user core
-- Design : r4b
-- Author : Bulent Selek
-- Company : Best Bilgisayar ve Elektronik Sanayi Ticaret
--
-------------------------------------------------------------------------------
--
-- File : ts7300_usercore.vhd
-- Generated : Fri Jan 8 13:22:36 2007
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Modified by Nigel Gunton
-- Company : Bristol Institute of Technology
-- version 1.0
-- full access to the DIO pins split into 3 registers plus output enable registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ts7300_usercore is
-- 75Mhz clock is fed to this module */
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_adr_i : in std_logic_vector ( 21 downto 0 );
wb_dat_i : in std_logic_vector ( 31 downto 0 );
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_dat_o : out std_logic_vector ( 31 downto 0 );
headerpin_i : in std_logic_vector( 40 downto 1 );
headerpin_o : out std_logic_vector( 40 downto 1 );
headerpin_oe_o : out std_logic_vector( 40 downto 1 );
irq_o : out std_logic;
-- SDRAM
sdram_ras_o : out std_logic; -- SDRAM row address strobe
sdram_cas_o : out std_logic; -- SDRAM column address strobe
sdram_we_n_o : out std_logic; -- SDRAM write enable
sdram_ba_o : out std_logic_vector( 1 downto 0 ); -- SDRAM bank address
sdram_saddr_o : out std_logic_vector( 11 downto 0 ); -- SDRAM row/column address
sdram_sdata_i : in std_logic_vector ( 15 downto 0 ); -- data from SDRAM
sdram_sdata_o : out std_logic_vector ( 15 downto 0 ); -- data to SDRAM
sdram_sdata_oe : out std_logic -- true if data is output to SDRAM on sDOut
);
end ts7300_usercore;
architecture ts7300_usercore of ts7300_usercore is
--- PWM Stuff ---
component pwm
port (
clk : in std_logic;
duty_cycle : in std_logic_vector(15 downto 0);
pwm_enable : in std_logic;
resetn : in std_logic;
pwm_out : out std_logic);
end component;
constant deadbeaf : std_logic_vector( 31 downto 0 ) := x"deadcafe";
signal vga_reg : std_logic_vector( 14 downto 0 ); -- only 14 downto 0 valid
signal dio2_reg : std_logic_vector( 15 downto 0 ); -- only 15 downto 0 valid
signal dummyreg : std_logic_vector( 31 downto 0 ); -- temporary reg
signal misc_reg : std_logic_vector( 3 downto 0 ); -- only 3 downto 0 valid
signal vga_enable : std_logic_vector( 14 downto 0 ); -- 1 = output enabled
signal dio2_enable : std_logic_vector( 15 downto 0 ); -- ditto
signal misc_enable : std_logic_vector( 3 downto 0 ); -- ditto
signal vga_read : std_logic_vector(14 downto 0); -- read from I/O pins
signal dio2_read : std_logic_vector(15 downto 0); -- ditto
signal misc_read : std_logic_vector(3 downto 0); -- ditto
signal DUTY_CYCLEA : std_logic_vector(15 downto 0) := X"006F";
signal DUTY_CYCLEB : std_logic_vector(15 downto 0) := X"006F";
signal DUTY_CYCLEC : std_logic_vector(15 downto 0) := X"006F";
signal DUTY_CYCLED : std_logic_vector(15 downto 0) := X"006F";
signal PWM_not_reset, PWM_enable_A, PWM_enable_B, PWM_enable_C, PWM_enable_D : std_logic := '1';
--- Read and write cycles of FPGA by and to the Processor
begin
process ( wb_clk_i )
variable addr : std_logic_vector ( 23 downto 0 );
begin
if ( wb_clk_i'event ) and ( wb_clk_i = '1' ) then
addr := "00" & wb_adr_i;
if (wb_cyc_i = '1' and wb_stb_i = '1' ) and ( wb_we_i = '1') then
-- WRITE CYCLE
case addr is
when x"280000" => vga_reg <= wb_dat_i(14 downto 0);
when x"280001" => vga_enable <= wb_dat_i(14 downto 0);
when x"280002" => dio2_reg <= wb_dat_i(15 downto 0);
when x"280003" => dio2_enable <= wb_dat_i(15 downto 0);
when x"280004" => misc_reg <= wb_dat_i(3 downto 0);
when x"280005" => misc_enable <= wb_dat_i(3 downto 0);
when x"280006" => DUTY_CYCLEA <= wb_dat_i(15 downto 0);
when x"280007" => DUTY_CYCLEB <= wb_dat_i(15 downto 0);
when x"280008" => DUTY_CYCLEC <= wb_dat_i(15 downto 0);
when x"280009" => DUTY_CYCLED <= wb_dat_i(15 downto 0);
when x"28000A" => PWM_enable_A <= wb_dat_i(0);
when x"28000B" => PWM_enable_B <= wb_dat_i(0);
when x"28000C" => PWM_enable_C <= wb_dat_i(0);
when x"28000D" => PWM_enable_D <= wb_dat_i(0);
when x"28000E" => PWM_not_reset <= wb_dat_i(0);
when others => null;
end case;
end if;
-- READ CYCLE
case addr is
when x"280000" => dummyreg <= "00000000000000000" & vga_read;
when x"280001" => dummyreg <= "00000000000000000" & vga_enable;
when x"280002" => dummyreg <= "0000000000000000" & dio2_read;
when x"280003" => dummyreg <= "0000000000000000" & dio2_enable;
when x"280004" => dummyreg <= "0000000000000000000000000000" & misc_read;
when x"280005" => dummyreg <= "0000000000000000000000000000" & misc_enable;
when x"280006" => dummyreg <= "0000000000000000" & DUTY_CYCLEA;
when x"280007" => dummyreg <= "0000000000000000" & DUTY_CYCLEB;
when x"280008" => dummyreg <= "0000000000000000" & DUTY_CYCLEC;
when x"280009" => dummyreg <= "0000000000000000" & DUTY_CYCLED;
when x"28000A" => dummyreg <= "0000000000000000000000000000000" & PWM_enable_A;
when x"28000B" => dummyreg <= "0000000000000000000000000000000" & PWM_enable_B;
when x"28000C" => dummyreg <= "0000000000000000000000000000000" & PWM_enable_C;
when x"28000D" => dummyreg <= "0000000000000000000000000000000" & PWM_enable_D;
when x"28000E" => dummyreg <= "0000000000000000000000000000000" & PWM_not_reset ;
when others => dummyreg <= x"deadbeef";
end case;
end if;
end process;
wb_ack_o <= wb_cyc_i and wb_stb_i; -- 0-wait state WISHBONE
wb_dat_o <= dummyreg;
irq_o <= '0';
-------------------------------------------------------------------------------
-- FPGA DIO output enable assignments: 40 downto 1
-- What follows is a pigs ear of assignments as the output enables are in pin
-- number order and the enable registers are in data name order
-------------------------------------------------------------------------------
headerpin_oe_o(1) <= vga_enable(0); -- blu0
headerpin_oe_o(3) <= vga_enable(1); -- blu1
headerpin_oe_o(5) <= vga_enable(2); -- blu2
headerpin_oe_o(7) <= vga_enable(3); -- blu3
headerpin_oe_o(9) <= vga_enable(4); -- blu4
headerpin_oe_o(11) <= vga_enable(5); -- grn0
headerpin_oe_o(13) <= vga_enable(6); -- grn1
headerpin_oe_o(15) <= vga_enable(7); -- grn2
headerpin_oe_o(17) <= vga_enable(8); -- grn3
headerpin_oe_o(4) <= vga_enable(10); -- red0
headerpin_oe_o(6) <= vga_enable(11); -- red1
headerpin_oe_o(8) <= vga_enable(12); -- red2
headerpin_oe_o(10) <= vga_enable(13); -- red3
headerpin_oe_o(12) <= vga_enable(14); -- red4
--headerpin_oe_o(19) <= '1';
headerpin_oe_o(21) <= '1';
headerpin_oe_o(23) <= '1';
headerpin_oe_o(25) <= '1';
headerpin_oe_o(29) <= '1';
-- headerpin_oe_o(29) <= dio2_enable(4); -- DIO2
headerpin_oe_o(31) <= dio2_enable(5); -- DIO2
headerpin_oe_o(33) <= dio2_enable(6); -- DIO2
headerpin_oe_o(35) <= dio2_enable(7); -- DIO2
headerpin_oe_o(37) <= dio2_enable(8); -- DIO2
-- THE FOLLOWING PIN IS DEDICATED CLK INPUT ONLY
-- headerpin_oe_o(39) <= dio2_enable(9); -- DIO2
headerpin_oe_o(24) <= dio2_enable(10); -- DIO2
headerpin_oe_o(26) <= dio2_enable(11); -- DIO2
headerpin_oe_o(28) <= dio2_enable(12); -- DIO2
headerpin_oe_o(30) <= dio2_enable(13); -- DIO2
headerpin_oe_o(32) <= dio2_enable(14); -- DIO2
headerpin_oe_o(34) <= dio2_enable(15); -- DIO2
headerpin_oe_o(14) <= misc_enable(0); -- HSYNC
headerpin_oe_o(16) <= misc_enable(1); -- VSYNC
headerpin_oe_o(36) <= misc_enable(2); -- RX_LD
headerpin_oe_o(38) <= misc_enable(3); -- TX_LD
-- the following MUST NOT be altered as they have dedicated use
headerpin_oe_o(2) <= '0'; -- GND
headerpin_oe_o(18) <= '0'; -- OEV
headerpin_oe_o(20) <= '0'; -- +5v fused
headerpin_oe_o(22) <= '0'; -- GND
headerpin_oe_o(39) <= '0'; -- external clk input only
headerpin_oe_o(40) <= '0'; -- +3.3v
-------------------------------------------------------------------------------
-- output assignments
-------------------------------------------------------------------------------
headerpin_o(1) <= vga_reg(0); --blu0
headerpin_o(3) <= vga_reg(1); --blu1
headerpin_o(5) <= vga_reg(2); --blu2
headerpin_o(6) <= vga_reg(3); --blu3
headerpin_o(7) <= vga_reg(4); --blu4
headerpin_o(11) <= vga_reg(5); --grn0
headerpin_o(13) <= vga_reg(6); --grn1
headerpin_o(15) <= vga_reg(7); --grn2
headerpin_o(17) <= vga_reg(8); --grn3
-- headerpin_o(29) <= dio2_reg(4); -- DIO2
headerpin_o(31) <= dio2_reg(5); -- DIO2
headerpin_o(33) <= dio2_reg(6); -- DIO2
headerpin_o(35) <= dio2_reg(7); -- DIO2
headerpin_o(37) <= dio2_reg(8); -- DIO2
-- THE FOLLOWING PIN IS INPUT ONLY
-- headerpin_o(39) <= dio2_reg(9); -- DIO2
headerpin_o(24) <= dio2_reg(10); -- DIO2
headerpin_o(26) <= dio2_reg(11); -- DIO2
headerpin_o(28) <= dio2_reg(12); -- DIO2
headerpin_o(30) <= dio2_reg(13); -- DIO2
headerpin_o(32) <= dio2_reg(14); -- DIO2
headerpin_o(34) <= dio2_reg(15); -- DIO2
headerpin_o(14) <= misc_reg(0); -- HSYNC
headerpin_o(16) <= misc_reg(1); -- VSYNC
headerpin_o(36) <= misc_reg(2); -- RX_LD
headerpin_o(38) <= misc_reg(3); -- TX_LD
-- just to keep synthesis warnings down ;)
headerpin_o(2) <= '0'; -- GND
headerpin_o(18) <= '0'; -- OEV
headerpin_o(20) <= '0'; -- +5v fused
headerpin_o(22) <= '0'; -- GND
headerpin_o(40) <= '0'; -- +3.3v
-----------------------------------------------------------------------------
-- read values on the IO pins; the special pins are handled in ts7300_top.v
-----------------------------------------------------------------------------
vga_read(0) <= headerpin_i(1); -- blu0
vga_read(1) <= headerpin_i(3); -- blu1
vga_read(2) <= headerpin_i(5); -- blu2
vga_read(3) <= headerpin_i(7); -- blu3
vga_read(4) <= headerpin_i(9); -- blu4
vga_read(5) <= headerpin_i(11); -- grn0
vga_read(6) <= headerpin_i(13); -- grn1
vga_read(7) <= headerpin_i(15); -- grn2
vga_read(8) <= headerpin_i(17); -- grn3
dio2_read(0) <= headerpin_i(21); -- DIO2
dio2_read(1) <= headerpin_i(23); -- DIO2
dio2_read(2) <= headerpin_i(25); -- DIO2
dio2_read(3) <= headerpin_i(27); -- DIO2
dio2_read(4) <= headerpin_i(29); -- DIO2
dio2_read(5) <= headerpin_i(31); -- DIO2
dio2_read(6) <= headerpin_i(33); -- DIO2
dio2_read(7) <= headerpin_i(35); -- DIO2
dio2_read(8) <= headerpin_i(37); -- DIO2
-- dio2_read(9) deliberately left out; see above
dio2_read(10) <= headerpin_i(24); -- DIO2
dio2_read(11) <= headerpin_i(26); -- DIO2
dio2_read(12) <= headerpin_i(28); -- DIO2
dio2_read(13) <= headerpin_i(30); -- DIO2
dio2_read(14) <= headerpin_i(32); -- DIO2
dio2_read(15) <= headerpin_i(34); -- DIO2
misc_read(0) <= headerpin_i(14); -- HSYNC
misc_read(1) <= headerpin_i(16); -- VSYNC
misc_read(2) <= headerpin_i(36); -- RX_LD but not a lot of point
misc_read(3) <= headerpin_i(38); -- TX_LD
PWM_1:pwm
port map (
clk => wb_clk_i,
duty_cycle => DUTY_CYCLEA,
pwm_enable => PWM_enable_A,--Enable_output_A,
resetn => PWM_not_reset,
pwm_out => headerpin_o(21));
PWM_2:pwm
port map (
clk => wb_clk_i,
duty_cycle => DUTY_CYCLEB,
pwm_enable => PWM_enable_B,--Enable_output_B,
resetn => PWM_not_reset,
pwm_out => headerpin_o(23));
PWM_3:pwm
port map (
clk => wb_clk_i,
duty_cycle => DUTY_CYCLEC,
pwm_enable => PWM_enable_C,--Enable_output_C,
resetn => PWM_not_reset,
pwm_out => headerpin_o(25));
PWM_4:pwm
port map (
clk => wb_clk_i,
duty_cycle => DUTY_CYCLED,
pwm_enable => PWM_enable_D,--Enable_output_D,
resetn => PWM_not_reset,
pwm_out => headerpin_o(29));
end ts7300_usercore;
| gpl-2.0 |
xylnao/w11a-extra | rtl/ibus/ibd_iist.vhd | 2 | 28981 | -- $Id: ibd_iist.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2009-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibd_iist - syn
-- Description: ibus dev(loc): IIST
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 112 510 0 291 s 15.8
-- 2010-10-17 314 12.1 M53d xc3s1000-4 111 504 0 290 s 15.6
-- 2009-06-01 223 10.1.03 K39 xc3s1000-4 111 439 0 256 s 9.8
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 111 449 0 258 s 13.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 0.8.1 now numeric_std clean
-- 2010-10-17 333 0.8 use ibus V2 interface
-- 2009-06-07 224 0.7 send inverted stc_stp; remove pgc_err; honor msk_im
-- also for dcf_dcf and exc_rte; add iist_mreq and
-- iist_sreq, boot and lock interfaces
-- 2009-06-05 223 0.6 level interrupt, parity logic, exc.ui logic
-- st logic modified (partially tested)
-- 2009-06-01 221 0.5 Initial version (untested, lock&boot missing)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.ibdlib.all;
-- ----------------------------------------------------------------------------
entity ibd_iist is -- ibus dev(loc): IIST
-- fixed address: 177500
generic (
SID : slv2 := "00"); -- self id
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit; -- interrupt acknowledge
IIST_BUS : in iist_bus_type; -- iist bus (input from all iist's)
IIST_OUT : out iist_line_type; -- iist output
IIST_MREQ : out iist_mreq_type; -- iist->cpu requests
IIST_SRES : in iist_sres_type -- cpu->iist responses
);
end ibd_iist;
architecture syn of ibd_iist is
constant ibaddr_iist : slv16 := slv(to_unsigned(8#177500#,16));
constant tdlysnd : natural := 150; -- send delay timer
constant ibaddr_acr : slv1 := "0"; -- acr address offset
constant ibaddr_adr : slv1 := "1"; -- adr address offset
constant acr_ibf_clr : integer := 15; -- clear flag
subtype acr_ibf_sid is integer range 9 downto 8; -- self id
subtype acr_ibf_ac is integer range 3 downto 0; -- ac code
constant ac_pge : slv4 := "0000"; -- 0 program generated enables
constant ac_pgc : slv4 := "0001"; -- 1 program generated control/status
constant ac_ste : slv4 := "0010"; -- 2 sanity timer enables
constant ac_stc : slv4 := "0011"; -- 3 sanity timer control/status
constant ac_msk : slv4 := "0100"; -- 4 input masks
constant ac_pgf : slv4 := "0101"; -- 5 program generated flags
constant ac_stf : slv4 := "0110"; -- 6 sanity timer flags
constant ac_dcf : slv4 := "0111"; -- 7 disconnect flags
constant ac_exc : slv4 := "1000"; -- 10 exceptions
constant ac_mtc : slv4 := "1101"; -- 15 maintenance control
subtype pge_ibf_pbe is integer range 11 downto 8; -- pg boot ena
subtype pge_ibf_pie is integer range 3 downto 0; -- pg int ena
constant pgc_ibf_err : integer := 15; -- error
constant pgc_ibf_grj : integer := 14; -- go reject
constant pgc_ibf_pgrmr : integer := 13; -- pg req refused
constant pgc_ibf_strmr : integer := 12; -- st req refused
constant pgc_ibf_rdy : integer := 11; -- ready flag
subtype pgc_ibf_sid is integer range 9 downto 8; -- self id
constant pgc_ibf_ip : integer := 3; -- int pending
constant pgc_ibf_ie : integer := 2; -- int enable
constant pgc_ibf_ptp : integer := 1; -- pg parity
constant pgc_ibf_go : integer := 0; -- go flag
subtype ste_ibf_sbe is integer range 11 downto 8; -- st boot enable
subtype ste_ibf_sie is integer range 3 downto 0; -- st int enable
subtype stc_ibf_count is integer range 15 downto 8; -- count
constant stc_ibf_tmo : integer := 3; -- timeout
constant stc_ibf_lke : integer := 2; -- lockup enable
constant stc_ibf_stp : integer := 1; -- st parity
constant stc_ibf_enb : integer := 0; -- enable
subtype msk_ibf_bm is integer range 11 downto 8; -- boot mask
subtype msk_ibf_im is integer range 3 downto 0; -- int mask
subtype pgf_ibf_pbf is integer range 11 downto 8; -- boot flags
subtype pgf_ibf_pif is integer range 3 downto 0; -- int flags
subtype stf_ibf_sbf is integer range 11 downto 8; -- boot flags
subtype stf_ibf_sif is integer range 3 downto 0; -- int flags
subtype dcf_ibf_brk is integer range 11 downto 8; -- break flags
subtype dcf_ibf_dcf is integer range 3 downto 0; -- disconnect flags
subtype exc_ibf_ui is integer range 11 downto 8; -- unexpected int
subtype exc_ibf_rte is integer range 3 downto 0; -- transm. error
constant mtc_ibf_mttp : integer := 11; -- maint. type
constant mtc_ibf_mfrm : integer := 10; -- maint. frame err
subtype mtc_ibf_mid is integer range 9 downto 8; -- maint. id
constant mtc_ibf_dsbt : integer := 3; -- disable boot
constant mtc_ibf_enmxd : integer := 2; -- enable maint mux
constant mtc_ibf_enmlp : integer := 1; -- enable maint loop
constant mtc_ibf_dsdrv : integer := 0; -- disable driver
type state_type is (
s_idle, -- idle state
s_clear, -- handle acr clr
s_stsnd, -- handle st transmit
s_pgsnd -- handle pg transmit
);
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
acr_ac : slv4; -- acr: ac
pge_pbe : slv4; -- pge: pg boot ena
pge_pie : slv4; -- pge: pg int ena
pgc_grj : slbit; -- pgc: go reject
pgc_pgrmr : slbit; -- pgc: pg req refused
pgc_strmr : slbit; -- pgc: st req refused
pgc_ie : slbit; -- pgc: int enable
pgc_ptp : slbit; -- pgc: pg parity
ste_sbe : slv4; -- ste: st boot enable
ste_sie : slv4; -- ste: st int enable
stc_count : slv8; -- stc: count
stc_tmo : slbit; -- stc: timeout
stc_lke : slbit; -- stc: lockup enable
stc_stp : slbit; -- stc: st parity
stc_enb : slbit; -- stc: enable
msk_bm : slv4; -- msk: boot mask
msk_im : slv4; -- msk: int mask
pgf_pbf : slv4; -- pgf: boot flags
pgf_pif : slv4; -- pgf: int flags
stf_sbf : slv4; -- stf: boot flags
stf_sif : slv4; -- stf: int flags
dcf_brk : slv4; -- dcf: break flags
dcf_dcf : slv4; -- dcf: disconnect flags
exc_ui : slv4; -- exc: unexpected int
exc_rte : slv4; -- exc: transm. error
mtc_mttp : slbit; -- mtc: maint. type
mtc_mfrm : slbit; -- mtc: maint. frame err
mtc_mid : slv2; -- mtc: maint. id
mtc_dsbt : slbit; -- mtc: disable boot
mtc_enmxd : slbit; -- mtc: enable maint mux
mtc_enmlp : slbit; -- mtc: enable maint loop
mtc_dsdrv : slbit; -- mtc: disable driver
state : state_type; -- state
req_clear : slbit; -- request clear
req_stsnd : slbit; -- request sanity timer transmit
req_pgsnd : slbit; -- request prog. gen. transmit
tcnt256 : slv8; -- usec clock divider for st clock
tcntsnd : slv8; -- timer for transmit delay
req_lock : slbit; -- cpu lock request
req_boot : slbit; -- cpu boot request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
"0000", -- acr_ac
"0000","0000", -- pge_pbe, pge_pie
'0', -- pgc_grj
'0','0', -- pgc_pgrmr, pgc_strmr
'0','0', -- pgc_ie, pgc_ptp
"0000","0000", -- ste_sbe, ste_sie
(others=>'0'), -- stc_count
'0','0', -- stc_tmo, stc_lke
'0','0', -- stc_stp, stc_enb
"0000","0000", -- msk_bm, msk_im
"0000","0000", -- pgf_pbf, pgf_pif
"0000","0000", -- stf_sbf, stf_sif
"0000","0000", -- dcf_brk, dcf_dcf
"0000","0000", -- exc_ui, exc_rte
'0','0', -- mtc_mttp, mtc_mfrm
"00", -- mtc_mid
'0','0', -- mtc_dsbt, mtc_enmxd
'0','0', -- mtc_enmlp, mtc_dsdrv
s_idle, -- state
'0', -- req_clear
'0','0', -- req_stsnd, req_pgsnd
(others=>'0'), -- tcnt256
(others=>'0'), -- tcntsnd
'0','0' -- req_lock, req_boot
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' or -- BRESET is 1 for system and ibus reset
R_REGS.req_clear='1' then
R_REGS <= regs_init; --
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.pgf_pbf <= N_REGS.pgf_pbf; -- don't reset pg boot flags
R_REGS.stf_sbf <= N_REGS.stf_sbf; -- don't reset st boot flags
R_REGS.tcnt256 <= N_REGS.tcnt256; -- don't reset st clock divider
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, CE_USEC, IB_MREQ, EI_ACK, EI_ACK,
IIST_BUS(0), IIST_BUS(1), IIST_BUS(2), IIST_BUS(3),
IIST_SRES)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibhold : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable int_or : slbit := '0';
variable tcnt256_end : slbit := '0';
variable tcntsnd_end : slbit := '0';
variable eff_id : slv2 := "00";
variable eff_bus : iist_bus_type := iist_bus_init;
variable par_err : slbit := '0';
variable act_ibit : slbit := '0';
variable act_bbit : slbit := '0';
variable iout : iist_line_type := iist_line_init;
begin
r := R_REGS;
n := R_REGS;
ibhold := '0';
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
int_or := r.pgc_grj or r.pgc_pgrmr or r.pgc_strmr;
for i in r.dcf_dcf'range loop
int_or := int_or or r.dcf_dcf(i) or
r.exc_rte(i) or
r.pgf_pif(i) or
r.stf_sif(i);
end loop; -- i
tcnt256_end := '0';
if CE_USEC='1' and r.stc_enb='1'then -- if st enabled on every usec
n.tcnt256 := slv(unsigned(r.tcnt256) + 1); -- advance 8 bit counter
if unsigned(r.tcnt256) = 255 then -- if wrap
tcnt256_end := '1'; -- signal 256 usec passed
end if;
end if;
tcntsnd_end := '0';
n.tcntsnd := slv(unsigned(r.tcntsnd) + 1); -- advance send timer counter
if unsigned(r.tcntsnd) = tdlysnd-1 then -- if delay time reached
tcntsnd_end := '1'; -- signal end
end if;
eff_id := SID; -- effective self-id, normally SID
if r.mtc_enmxd = '1' then -- if maint. mux enabled
eff_id := r.mtc_mid; -- use maint. id
end if;
eff_bus := IIST_BUS;
par_err := '0';
act_ibit := '0';
act_bbit := '0';
iout := iist_line_init; -- default state of out line
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 2)=ibaddr_iist(12 downto 2) then
n.ibsel := '1';
end if;
-- internal state machine
case r.state is
when s_idle => -- idle state
n.tcntsnd := (others=>'0'); -- keep send delay timer zero
if r.req_stsnd = '1' then -- sanity timer request pending
n.state := s_stsnd;
elsif r.req_pgsnd = '1' then -- prog. gen. request pending
n.state := s_pgsnd;
end if;
when s_clear => -- handle acr clr
ibhold := r.ibsel; -- keep req pending if selected
-- r.req_clear is set when in this state and cause a reset in prog_regs
-- --> n.req_clear := '0';
-- --> n.state := s_idle;
when s_stsnd => -- handle st transmit
if tcntsnd_end = '1' then -- send delay expired
n.req_stsnd := '0'; -- clear st transmit request
iout.req := '1'; -- do transmit
iout.stf := '1'; -- signal type = st
iout.imask := r.ste_sie; -- int enables
iout.bmask := r.ste_sbe; -- boot enables
iout.par := not r.stc_stp; -- send parity (odd incl. stf!)
iout.frm := '0'; -- frame always ok
n.state := s_idle;
end if;
when s_pgsnd => -- handle pg transmit
if tcntsnd_end = '1' then -- send delay expired
n.req_pgsnd := '0'; -- clear pg transmit request
iout.req := '1'; -- do transmit
iout.stf := '0'; -- signal type = pg
iout.imask := r.pge_pie; -- int enables
iout.bmask := r.pge_pbe; -- boot enables
iout.par := r.pgc_ptp; -- send parity
iout.frm := '0'; -- frame always ok
n.state := s_idle;
end if;
when others => null;
end case;
if r.mtc_enmxd = '1' then -- if maintenance mux enabled
iout.stf := r.mtc_mttp; -- force type from mtc_mttp
iout.frm := r.mtc_mfrm; -- force frame from mtc_mfrm
end if;
-- ibus transactions
if r.ibsel = '1' and ibhold='0' then
if IB_MREQ.addr(1 downto 1) = "0" then -- ACR -- access control reg -----
idout(acr_ibf_sid) := SID;
idout(acr_ibf_ac) := r.acr_ac;
if ibw1 = '1' then
if IB_MREQ.din(acr_ibf_clr) = '1' then
n.req_clear := '1';
n.state := s_clear;
end if;
end if;
if ibw0 = '1' then
n.acr_ac := IB_MREQ.din(acr_ibf_ac);
end if;
else -- ADR -- access data reg --------
case r.acr_ac is
when ac_pge => -- PGE -- program gen enables --------
idout(pge_ibf_pbe) := r.pge_pbe;
idout(pge_ibf_pie) := r.pge_pie;
if IB_MREQ.we = '1' then
if r.req_pgsnd = '0' then -- no pg transmit pending
if ibw1 = '1' then
n.pge_pbe := IB_MREQ.din(pge_ibf_pbe);
end if;
if ibw0 = '1' then
n.pge_pie := IB_MREQ.din(pge_ibf_pie);
end if;
else -- if collision with pg transmit
n.pgc_pgrmr := '1'; -- set pge refused flag
end if;
end if;
when ac_pgc => -- PGC -- program gen control/status -
idout(pgc_ibf_err) := r.pgc_grj or r.pgc_pgrmr or r.pgc_strmr;
idout(pgc_ibf_grj) := r.pgc_grj;
idout(pgc_ibf_pgrmr) := r.pgc_pgrmr;
idout(pgc_ibf_strmr) := r.pgc_strmr;
idout(pgc_ibf_rdy) := not r.req_pgsnd;
idout(pgc_ibf_sid) := eff_id;
idout(pgc_ibf_ip) := int_or;
idout(pgc_ibf_ie) := r.pgc_ie;
idout(pgc_ibf_ptp) := r.pgc_ptp;
if ibw1 = '1' then
if IB_MREQ.din(pgc_ibf_err) = '1' then -- '1' written into ERR
n.pgc_grj := '0'; -- clears GRJ
n.pgc_pgrmr := '0'; -- clears PGRMR
n.pgc_strmr := '0'; -- clears STRMR
end if;
end if;
if ibw0 = '1' then
n.pgc_ie := IB_MREQ.din(pgc_ibf_ie);
n.pgc_ptp := IB_MREQ.din(pgc_ibf_ptp);
if IB_MREQ.din(pgc_ibf_go) = '1' then -- GO bit set
if r.req_pgsnd = '0' then -- if ready (no pgsnd pend)
n.req_pgsnd := '1'; -- request pgsnd
else -- if not ready
n.pgc_grj := '1'; -- set go reject flag
end if;
end if;
end if;
when ac_ste => -- STE -- sanity timer enables -------
idout(ste_ibf_sbe) := r.ste_sbe;
idout(ste_ibf_sie) := r.ste_sie;
if IB_MREQ.we = '1' then
if r.req_stsnd = '0' then -- no st transmit pending
if ibw1 = '1' then
n.ste_sbe := IB_MREQ.din(ste_ibf_sbe);
end if;
if ibw0 = '1' then
n.ste_sie := IB_MREQ.din(ste_ibf_sie);
end if;
else -- if collision with st transmit
n.pgc_strmr := '1'; -- set ste refused flag
end if;
end if;
when ac_stc => -- STC -- sanity timer control/status
idout(stc_ibf_count) := r.stc_count;
idout(stc_ibf_tmo) := r.stc_tmo;
idout(stc_ibf_lke) := r.stc_lke;
idout(stc_ibf_stp) := r.stc_stp;
idout(stc_ibf_enb) := r.stc_enb;
if ibw1 = '1' then
n.stc_count := IB_MREQ.din(stc_ibf_count); -- reset st count
n.tcnt256 := (others=>'0'); -- reset usec count
end if;
if ibw0 = '1' then
if IB_MREQ.din(stc_ibf_tmo) = '1' then -- 1 written into TMO
n.stc_tmo := '0';
end if;
n.stc_lke := IB_MREQ.din(stc_ibf_lke);
n.stc_stp := IB_MREQ.din(stc_ibf_stp);
n.stc_enb := IB_MREQ.din(stc_ibf_enb);
end if;
when ac_msk => -- MSK -- input masks ----------------
idout(msk_ibf_bm) := r.msk_bm;
idout(msk_ibf_im) := r.msk_im;
if ibw1 = '1' then
n.msk_bm := IB_MREQ.din(msk_ibf_bm);
end if;
if ibw0 = '1' then
n.msk_im := IB_MREQ.din(msk_ibf_im);
end if;
when ac_pgf => -- PGF -- program generated flags ----
idout(pgf_ibf_pbf) := r.pgf_pbf;
idout(pgf_ibf_pif) := r.pgf_pif;
if ibw1 = '1' then
n.pgf_pbf := r.pgf_pbf and not IB_MREQ.din(pgf_ibf_pbf);
end if;
if ibw0 = '1' then
n.pgf_pif := r.pgf_pif and not IB_MREQ.din(pgf_ibf_pif);
end if;
when ac_stf => -- STF -- sanity timer flags ---------
idout(stf_ibf_sbf) := r.stf_sbf;
idout(stf_ibf_sif) := r.stf_sif;
if ibw1 = '1' then
n.stf_sbf := r.stf_sbf and not IB_MREQ.din(stf_ibf_sbf);
end if;
if ibw0 = '1' then
n.stf_sif := r.stf_sif and not IB_MREQ.din(stf_ibf_sif);
end if;
when ac_dcf => -- DCE -- disconnect flags -----------
idout(dcf_ibf_brk) := r.dcf_brk;
idout(dcf_ibf_dcf) := r.dcf_dcf;
if ibw0 = '1' then
n.dcf_dcf := r.dcf_dcf and not IB_MREQ.din(dcf_ibf_dcf);
end if;
when ac_exc => -- EXC -- exceptions -----------------
idout(exc_ibf_ui) := r.exc_ui;
idout(exc_ibf_rte) := r.exc_rte;
if ibw1 = '1' then
n.exc_ui := r.exc_ui and not IB_MREQ.din(exc_ibf_ui);
end if;
if ibw0 = '1' then
n.exc_rte := r.exc_rte and not IB_MREQ.din(exc_ibf_rte);
end if;
when ac_mtc => -- MTC -- maintenance control --------
idout(mtc_ibf_mttp) := r.mtc_mttp;
idout(mtc_ibf_mfrm) := r.mtc_mfrm;
idout(mtc_ibf_mid) := r.mtc_mid;
idout(mtc_ibf_dsbt) := r.mtc_dsbt;
idout(mtc_ibf_enmxd) := r.mtc_enmxd;
idout(mtc_ibf_enmlp) := r.mtc_enmlp;
idout(mtc_ibf_dsdrv) := r.mtc_dsdrv;
if ibw1 = '1' then
n.mtc_mttp := IB_MREQ.din(mtc_ibf_mttp);
n.mtc_mfrm := IB_MREQ.din(mtc_ibf_mfrm);
n.mtc_mid := IB_MREQ.din(mtc_ibf_mid);
end if;
if ibw0 = '1' then
n.mtc_dsbt := IB_MREQ.din(mtc_ibf_dsbt);
n.mtc_enmxd := IB_MREQ.din(mtc_ibf_enmxd);
n.mtc_enmlp := IB_MREQ.din(mtc_ibf_enmlp);
n.mtc_dsdrv := IB_MREQ.din(mtc_ibf_dsdrv);
end if;
when others => -- access to undefined AC code -------
null;
end case;
if unsigned(r.acr_ac) <= unsigned(ac_exc) then -- if ac 0,..,10
if IB_MREQ.rmw = '0' then -- if not 1st part of rmw
n.acr_ac := slv(unsigned(r.acr_ac) + 1); -- autoincrement
end if;
end if;
end if;
end if;
-- sanity timer
if tcnt256_end = '1' then -- if 256 usec expired (and enabled)
n.stc_count := slv(unsigned(r.stc_count) - 1);
if unsigned(r.stc_count) = 0 then -- if sanity timer expired
n.stc_tmo := '1'; -- set timeout flag
n.req_stsnd := '1'; -- request st transmit
if r.stc_lke = '1' then -- if lockup enabled
n.req_lock := '1'; -- request lockup
end if;
end if;
end if;
-- process iist bus inputs
if r.mtc_enmlp = '1' then -- if mainentance loop
for i in eff_bus'range loop
eff_bus(i) := iout; -- local signal on all input ports
eff_bus(i).dcf := '0'; -- all ports considered connected
end loop; -- i
end if;
for i in eff_bus'range loop
par_err := eff_bus(i).stf xor
eff_bus(i).imask(0) xor eff_bus(i).imask(1) xor
eff_bus(i).imask(2) xor eff_bus(i).imask(3) xor
eff_bus(i).bmask(0) xor eff_bus(i).bmask(1) xor
eff_bus(i).bmask(2) xor eff_bus(i).bmask(3) xor
not eff_bus(i).par;
act_ibit := eff_bus(i).imask(to_integer(unsigned(eff_id)));
act_bbit := eff_bus(i).bmask(to_integer(unsigned(eff_id)));
n.dcf_brk(i) := eff_bus(i).dcf; -- trace dcf state in brk
if eff_bus(i).dcf = '1' then -- if disconnected
if r.msk_im(i) = '0' then -- if not disabled
n.dcf_dcf(i) := '1'; -- set dcf flag
end if;
else -- if connected
if eff_bus(i).req = '1' then -- request received ?
if eff_bus(i).frm='1' or -- frame error seen ?
par_err='1' then -- parity error seen ?
if r.msk_im(i) = '0' then -- if not disabled
n.exc_rte(i) := '1'; -- set rte flag
end if;
else -- here if valid request seen
if act_ibit = '1' then -- interrupt request
if r.msk_im(i) = '1' then -- if disabled
n.exc_ui(i) := '1'; -- set ui flag
else -- if enabled
n.req_lock := '0'; -- release lock
if eff_bus(i).stf = '0' then -- and pg request
n.pgf_pif(i) := '1'; -- set pif flag
else -- and st request
n.stf_sif(i) := '1'; -- set sif flag
end if;
end if;
end if; -- act_ibit='1'
if act_bbit = '1' then -- boot request
if r.msk_bm(i) = '1' then -- if msk disabled
n.exc_ui(i) := '1'; -- set ui flag
else -- if msk enabled
if r.mtc_dsbt = '0' then -- if mtc enabled
n.req_lock := '0'; -- release lock
n.req_boot := '1'; -- request boot
end if;
if eff_bus(i).stf = '0' then -- and pg request
n.pgf_pbf(i) := '1'; -- set pbf flag
else -- and st request
n.stf_sbf(i) := '1'; -- set sbf flag
end if;
end if;
end if; -- act_bbit='1'
end if;
end if;
end if;
end loop;
-- process cpu->iist responses
if IIST_SRES.ack_lock = '1' then
n.req_lock := '0';
end if;
if IIST_SRES.ack_boot = '1' then
n.req_boot := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
EI_REQ <= r.pgc_ie and int_or;
if r.mtc_dsdrv = '1' then -- if driver disconnected
iout.dcf := '1'; -- set dcf flag
iout.req := '0'; -- suppress requests
end if;
IIST_OUT <= iout; -- and finally send it out...
IIST_MREQ.lock <= r.req_lock;
IIST_MREQ.boot <= r.req_boot;
end process proc_next;
end syn;
| gpl-2.0 |
xylnao/w11a-extra | rtl/vlib/comlib/cdata2byte.vhd | 2 | 4382 | -- $Id: cdata2byte.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: cdata2byte - syn
-- Description: 9 bit comma,data to Byte stream converter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity cdata2byte is -- 9bit comma,data -> byte stream
generic (
CPREF : slv4 := "1000"; -- comma prefix
NCOMM : positive := 4); -- number of comma chars
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv9; -- input data; bit 8 = comma flag
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data
VAL : out slbit; -- read valid
HOLD : in slbit -- read hold
);
end cdata2byte;
architecture syn of cdata2byte is
type state_type is (
s_idle,
s_data,
s_comma,
s_escape,
s_edata
);
type regs_type is record
data : slv8; -- current data
state : state_type; -- state
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'),
s_idle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert NCOMM <= 14
report "assert(NCOMM <= 14)"
severity FAILURE;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, DI, ENA, HOLD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ido : slv8 := (others=>'0');
variable ival : slbit := '0';
variable ibusy : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ido := r.data;
ival := '0';
ibusy := '1';
case r.state is
when s_idle =>
ibusy := '0';
if ENA = '1' then
n.data := DI(7 downto 0);
n.state := s_data;
if DI(8) = '1' then
n.state := s_comma;
else
if DI(7 downto 4)=CPREF and
(DI(3 downto 0)="1111" or
unsigned(DI(3 downto 0))<=NCOMM) then
n.state := s_escape;
end if;
end if;
end if;
when s_data =>
ival := '1';
if HOLD = '0' then
n.state := s_idle;
end if;
when s_comma =>
ido := CPREF & r.data(3 downto 0);
ival := '1';
if HOLD = '0' then
n.state := s_idle;
end if;
when s_escape =>
ido := CPREF & "1111";
ival := '1';
if HOLD = '0' then
n.state := s_edata;
end if;
when s_edata =>
ido := (not CPREF) & r.data(3 downto 0);
ival := '1';
if HOLD = '0' then
n.state := s_idle;
end if;
when others => null;
end case;
N_REGS <= n;
DO <= ido;
VAL <= ival;
BUSY <= ibusy;
end process proc_next;
end syn;
| gpl-2.0 |
xylnao/w11a-extra | rtl/vlib/comlib/comlib.vhd | 2 | 7831 | -- $Id: comlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: comlib
-- Description: communication components
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.4 now numeric_std clean; use for crc8 'A6' polynomial
-- of Koopman et al.; crc8_update(_tbl) now function
-- 2011-07-30 400 1.3 added byte2word, word2byte
-- 2007-10-12 88 1.2.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.2 added procedure crc8_update_tbl
-- 2007-06-29 61 1.1.1 rename for crc8 SALT->INIT
-- 2007-06-17 58 1.1 add crc8
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
package comlib is
component byte2word is -- 2 byte -> 1 word stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data (byte)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv16; -- output data (word)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end component;
component word2byte is -- 1 word -> 2 byte stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv16; -- input data (word)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data (byte)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end component;
component cdata2byte is -- 9bit comma,data -> byte stream
generic (
CPREF : slv4 := "1000"; -- comma prefix
NCOMM : positive := 4); -- number of comma chars
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv9; -- input data; bit 8 = komma flag
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data
VAL : out slbit; -- read valid
HOLD : in slbit -- read hold
);
end component;
component byte2cdata is -- byte stream -> 9bit comma,data
generic (
CPREF : slv4 := "1000"; -- comma prefix
NCOMM : positive := 4); -- number of comma chars
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv9; -- output data; bit 8 = komma flag
VAL : out slbit; -- read valid
HOLD : in slbit -- read hold
);
end component;
component crc8 is -- crc-8 generator, checker
generic (
INIT: slv8 := "00000000"); -- initial state of crc register
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENA : in slbit; -- update enable
DI : in slv8; -- input data
CRC : out slv8 -- crc code
);
end component;
function crc8_update (crc : in slv8; data : in slv8) return slv8;
function crc8_update_tbl (crc : in slv8; data : in slv8) return slv8;
end package comlib;
-- ----------------------------------------------------------------------------
package body comlib is
function crc8_update (crc: in slv8; data: in slv8) return slv8 is
variable t : slv8 := (others=>'0');
variable n : slv8 := (others=>'0');
begin
t := data xor crc;
n(0) := t(5) xor t(4) xor t(2) xor t(0);
n(1) := t(6) xor t(5) xor t(3) xor t(1);
n(2) := t(7) xor t(6) xor t(5) xor t(0);
n(3) := t(7) xor t(6) xor t(5) xor t(4) xor t(2) xor t(1) xor t(0);
n(4) := t(7) xor t(6) xor t(5) xor t(3) xor t(2) xor t(1);
n(5) := t(7) xor t(6) xor t(4) xor t(3) xor t(2);
n(6) := t(7) xor t(3) xor t(2) xor t(0);
n(7) := t(4) xor t(3) xor t(1);
return n;
end function crc8_update;
function crc8_update_tbl (crc: in slv8; data: in slv8) return slv8 is
type crc8_tbl_type is array (0 to 255) of integer;
variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
( 0, 77, 154, 215, 121, 52, 227, 174, -- 00-07
242, 191, 104, 37, 139, 198, 17, 92, -- 00-0f
169, 228, 51, 126, 208, 157, 74, 7, -- 10-17
91, 22, 193, 140, 34, 111, 184, 245, -- 10-1f
31, 82, 133, 200, 102, 43, 252, 177, -- 20-27
237, 160, 119, 58, 148, 217, 14, 67, -- 20-2f
182, 251, 44, 97, 207, 130, 85, 24, -- 30-37
68, 9, 222, 147, 61, 112, 167, 234, -- 30-3f
62, 115, 164, 233, 71, 10, 221, 144, -- 40-47
204, 129, 86, 27, 181, 248, 47, 98, -- 40-4f
151, 218, 13, 64, 238, 163, 116, 57, -- 50-57
101, 40, 255, 178, 28, 81, 134, 203, -- 50-5f
33, 108, 187, 246, 88, 21, 194, 143, -- 60-67
211, 158, 73, 4, 170, 231, 48, 125, -- 60-6f
136, 197, 18, 95, 241, 188, 107, 38, -- 70-70
122, 55, 224, 173, 3, 78, 153, 212, -- 70-7f
124, 49, 230, 171, 5, 72, 159, 210, -- 80-87
142, 195, 20, 89, 247, 186, 109, 32, -- 80-8f
213, 152, 79, 2, 172, 225, 54, 123, -- 90-97
39, 106, 189, 240, 94, 19, 196, 137, -- 90-9f
99, 46, 249, 180, 26, 87, 128, 205, -- a0-a7
145, 220, 11, 70, 232, 165, 114, 63, -- a0-af
202, 135, 80, 29, 179, 254, 41, 100, -- b0-b7
56, 117, 162, 239, 65, 12, 219, 150, -- b0-bf
66, 15, 216, 149, 59, 118, 161, 236, -- c0-c7
176, 253, 42, 103, 201, 132, 83, 30, -- c0-cf
235, 166, 113, 60, 146, 223, 8, 69, -- d0-d7
25, 84, 131, 206, 96, 45, 250, 183, -- d0-df
93, 16, 199, 138, 36, 105, 190, 243, -- e0-e7
175, 226, 53, 120, 214, 155, 76, 1, -- e0-ef
244, 185, 110, 35, 141, 192, 23, 90, -- f0-f7
6, 75, 156, 209, 127, 50, 229, 168 -- f0-ff
);
begin
return slv(to_unsigned(crc8_tbl(to_integer(unsigned(data xor crc))), 8));
end function crc8_update_tbl;
end package body comlib;
| gpl-2.0 |
vhavlena/appreal | netbench/pattern_match/algorithms/sourdis_bispo_nfa/vhdl/state_pcre_exact.vhd | 1 | 2970 | -- ----------------------------------------------------------------------------
-- Entity for implementation of exactly N
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity STATE_PCRE_EXACT is
generic(
M : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
INPUT : in std_logic;
SYMBOL : in std_logic;
WE : in std_logic;
-- output data interface
OUTPUT : out std_logic
);
end entity STATE_PCRE_EXACT;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of STATE_PCRE_EXACT is
signal local_reset : std_logic;
signal local_reset_out: std_logic;
signal cnt_reset: std_logic;
signal sh_out : std_logic;
signal sh_in : std_logic;
signal value : std_logic_vector(11 downto 0);
begin
local_reset <= RESET or not SYMBOL;
local_reset_out <= RESET or cnt_reset;
input_reg: process(CLK, RESET)
begin
if (clk'event and CLK='1') then
if (local_reset = '1') then
sh_in <= '0';
else
sh_in <= INPUT;
end if;
end if;
end process;
gen_shift: if M > 2 generate
shift_reg: entity work.sh_reg
generic map(
NUM_BITS => M - 2
)
port map(
CLK => CLK,
DIN => sh_in,
CE => WE,
DOUT => sh_out
);
end generate;
gen_2: if M = 2 generate
sh_out <= sh_in;
end generate;
gen_1: if M = 1 generate
sh_out <= INPUT;
end generate;
output_reg: process(CLK, RESET)
begin
if (clk'event and CLK='1') then
if (local_reset_out = '1') then
OUTPUT <= '0';
else
OUTPUT <= sh_out;
end if;
end if;
end process;
cnt_reset_u: process(CLK, RESET)
begin
if (CLK'event and CLK = '1') then
if (local_reset = '1') then
value <= (others => '0');
else
if (we = '1') then
if ((cnt_reset = '1')) then
value <= value + 1;
end if;
end if;
end if;
end if;
end process;
cnt_reset <= '1' when (value > 0 and value <= M) else '0';
end architecture full;
| gpl-2.0 |
vhavlena/appreal | netbench/pattern_match/algorithms/clark_nfa/vhdl/clark_nfa.vhd | 1 | 2919 | -- ----------------------------------------------------------------------------
-- Entity for implementation of Clark NFA
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity CLARK_NFA is
generic(
DATA_WIDTH : integer := %$%;
RULES : integer := %$%
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
DATA : in std_logic_vector(DATA_WIDTH - 1 downto 0);
SOF : in std_logic;
EOF : in std_logic;
SRC_RDY : in std_logic;
DST_RDY : out std_logic;
-- output data interface
BITMAP : out std_logic_vector(RULES - 1 downto 0);
VLD : out std_logic;
ACK : in std_logic
);
end entity CLARK_NFA;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of CLARK_NFA is
signal local_reset : std_logic;
signal local_reset_fsm : std_logic;
signal we : std_logic;
-- signal rdy : std_logic;
-- signal vld_internal : std_logic;
-- signal set : std_logic;
%$%
begin
local_reset <= RESET or local_reset_fsm;
ctrl_fsm: entity work.CONTROL_FSM
port map(
CLK => CLK,
RESET => RESET,
-- input interface
EOF => EOF,
SRC_RDY => SRC_RDY,
DST_RDY => DST_RDY,
-- output interface
WE => we,
LOCAL_RESET => local_reset_fsm,
-- inner interface
VLD => VLD,
ACK => ACK
);
-- we <= SRC_RDY and rdy;
-- DST_RDY <= rdy;
-- VLD <= vld_internal;
-- set <= SRC_RDY and EOF and rdy;
-- rdy <= not vld_internal;
--
-- end_reg: process(CLK)
-- begin
-- if (CLK'event and CLK = '1') then
-- if (local_reset = '1') then
-- vld_internal <= '0';
-- else
-- if set = '1' then
-- vld_internal <= '1';
-- end if;
-- end if;
-- end if;
-- end process end_reg;
%$%
final_bitmap_u: entity work.FINAL_BITMAP
generic map(
DATA_WIDTH => RULES
)
port map(
CLK => CLK,
RESET => local_reset,
-- input data interface
SET => bitmap_in,
-- output data interface
BITMAP => BITMAP
);
end architecture full;
| gpl-2.0 |
xylnao/w11a-extra | rtl/sys_gen/tst_rlink/avmb/tb/tb_tst_rlink_mb.vhd | 1 | 1269 | -- $Id$
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_mb
-- Description: Configuration for tb_tst_rlink_mb for tb_avmb_fusp
--
-- Dependencies: sys_tst_rlink_mb
--
-- To test: sys_tst_rlink_mb
--
-- Verified:
-- Date Rev Code ghdl ise Target Comment
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-02-24 ??? 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_rlink_mb of tb_avmb_fusp is
for sim
for all : avmb_fusp_aif
use entity work.sys_tst_rlink_mb;
end for;
end for;
end tb_tst_rlink_mb;
| gpl-2.0 |
wgml/sysrek | lut_test/ipcore_dir/LUT/example_design/LUT_exdes.vhd | 6 | 4054 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity LUT_exdes is
PORT (
CLK : IN STD_LOGIC := '0';
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
end LUT_exdes;
architecture xilinx of LUT_exdes is
SIGNAL CLK_i : std_logic;
component LUT is
PORT (
CLK : IN STD_LOGIC;
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : LUT
port map (
CLK => CLK_i,
QSPO => QSPO,
A => A
);
clk_buf: bufg
PORT MAP(
i => CLK,
o => CLK_i
);
end xilinx;
| gpl-2.0 |
xylnao/w11a-extra | rtl/vlib/rlink/tb/tbcore_rlink.vhd | 1 | 8507 | -- $Id: tbcore_rlink.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbcore_rlink - sim
-- Description: Core for a rlink_cext based test bench
--
-- Dependencies: simlib/simclk
--
-- To test: generic, any rlink_cext based target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 rename rritb_core->tbcore_rlink; use rbv3 naming
-- 2010-06-05 301 1.1.2 rename .rpmon -> .rbmon
-- 2010-05-02 287 1.1.1 rename config command .sdata -> .sinit;
-- use sbcntl_sbf_(cp|rp)mon defs, use rritblib;
-- 2010-04-25 283 1.1 new clk handling in proc_stim, wait period-setup
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rblib.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.rlink_cext_vhpi.all;
entity tbcore_rlink is -- core of rlink_cext based test bench
generic (
CLK_PERIOD : time := 20 ns; -- clock period
CLK_OFFSET : time := 200 ns; -- clock offset (time to start clock)
SETUP_TIME : time := 5 ns; -- setup time
C2OUT_TIME : time := 10 ns); -- clock to output time
port (
CLK : out slbit; -- main clock
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end tbcore_rlink;
architecture sim of tbcore_rlink is
signal CLK_L : slbit := '0';
signal CLK_STOP : slbit := '0';
begin
SYSCLK : simclk
generic map (
PERIOD => CLK_PERIOD,
OFFSET => CLK_OFFSET)
port map (
CLK => CLK_L,
CLK_CYCLE => SB_CLKCYCLE,
CLK_STOP => CLK_STOP
);
CLK <= CLK_L;
proc_conf: process
file fconf : text open read_mode is "rlink_cext_conf";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable ien : slbit := '0';
variable ibit : integer := 0;
variable iaddr : slv8 := (others=>'0');
variable idata : slv16 := (others=>'0');
begin
SB_CNTL <= (others=>'L');
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
file_loop: while not endfile(fconf) loop
readline (fconf, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".scntl" => -- .scntl
read_ea(iline, ibit);
read_ea(iline, ien);
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
report "assert bit number in range of SB_CNTL"
severity failure;
if ien = '1' then
SB_CNTL(ibit) <= 'H';
else
SB_CNTL(ibit) <= 'L';
end if;
when ".rlmon" => -- .rlmon
read_ea(iline, ien);
if ien = '1' then
SB_CNTL(sbcntl_sbf_rlmon) <= 'H';
else
SB_CNTL(sbcntl_sbf_rlmon) <= 'L';
end if;
when ".rbmon" => -- .rbmon
read_ea(iline, ien);
if ien = '1' then
SB_CNTL(sbcntl_sbf_rbmon) <= 'H';
else
SB_CNTL(sbcntl_sbf_rbmon) <= 'L';
end if;
when ".sinit" => -- .sinit
readgen_ea(iline, iaddr, 8);
readgen_ea(iline, idata, 8);
SB_ADDR <= iaddr;
SB_DATA <= idata;
SB_VAL <= 'H';
wait for 0 ns;
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
wait for 0 ns;
when others => -- bad command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
wait; -- halt process here
end process proc_conf;
proc_stim: process
variable icycle : integer := 0;
variable irxint : integer := 0;
variable irxslv : slv24 := (others=>'0');
variable ibit : integer := 0;
variable oline : line;
variable r_sb_cntl : slv16 := (others=>'Z');
variable iaddr : slv8 := (others=>'0');
variable idata : slv16 := (others=>'0');
begin
wait for CLK_OFFSET;
wait for 10*CLK_PERIOD;
stim_loop: loop
wait until rising_edge(CLK_L);
wait for CLK_PERIOD-SETUP_TIME;
SB_ADDR <= (others=>'Z');
SB_DATA <= (others=>'Z');
icycle := to_integer(unsigned(SB_CLKCYCLE));
RX_VAL <= '0';
if RX_HOLD = '0' then
irxint := rlink_cext_getbyte(icycle);
if irxint >= 0 then
if irxint <= 16#ff# then -- normal data byte
RX_DATA <= slv(to_unsigned(irxint, 8));
RX_VAL <= '1';
elsif irxint >= 16#1000000# then -- out-of-band message
irxslv := slv(to_unsigned(irxint mod 16#1000000#, 24));
iaddr := irxslv(23 downto 16);
idata := irxslv(15 downto 0);
writetimestamp(oline, SB_CLKCYCLE, ": OOB-MSG");
write(oline, irxslv(23 downto 16), right, 9);
write(oline, irxslv(15 downto 8), right, 9);
write(oline, irxslv( 7 downto 0), right, 9);
write(oline, string'(" : "));
writeoct(oline, iaddr, right, 3);
writeoct(oline, idata, right, 7);
writeline(output, oline);
if unsigned(iaddr) = 0 then
ibit := to_integer(unsigned(idata(15 downto 8)));
r_sb_cntl(ibit) := idata(0);
else
SB_ADDR <= iaddr;
SB_DATA <= idata;
SB_VAL <= '1';
wait for 0 ns;
SB_VAL <= 'Z';
wait for 0 ns;
end if;
end if;
elsif irxint = -1 then -- end-of-file seen
exit stim_loop;
else
report "rlink_cext_getbyte error: " & integer'image(-irxint)
severity failure;
end if;
end if;
SB_CNTL <= r_sb_cntl;
end loop;
wait for 50*CLK_PERIOD;
CLK_STOP <= '1';
writetimestamp(oline, SB_CLKCYCLE, ": DONE ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable itxdata : integer := 0;
variable itxrc : integer := 0;
variable oline : line;
begin
loop
wait until rising_edge(CLK_L);
wait for C2OUT_TIME;
if TX_ENA = '1' then
itxdata := to_integer(unsigned(TX_DATA));
itxrc := rlink_cext_putbyte(itxdata);
assert itxrc=0
report "rlink_cext_putbyte error: " & integer'image(itxrc)
severity failure;
end if;
end loop;
end process proc_moni;
end sim;
| gpl-2.0 |
xylnao/w11a-extra | rtl/w11a/pdp11_vmbox.vhd | 2 | 24725 | -- $Id: pdp11_vmbox.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_vmbox - syn
-- Description: pdp11: virtual memory
--
-- Dependencies: pdp11_mmu
-- pdp11_ubmap
-- ibus/ib_sres_or_4
-- ibus/ib_sres_or_2
-- ibus/ib_sel
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.6.3 now numeric_std clean
-- 2010-10-23 335 1.6.2 add r.paddr_iopage, use ib_sel
-- 2010-10-22 334 1.6.1 deassert ibus be's at end-cycle; fix rmw logic
-- 2010-10-17 333 1.6 implement ibus V2 interface
-- 2010-06-27 310 1.5 redo ibus driver logic, now ibus driven from flops
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
-- 2010-06-18 306 1.4.1 for cpacc: set cacc in ib_mreq, forward racc,be
-- from CP_ADDR; now all ibr handling via vmbox
-- 2010-06-13 305 1.4 rename CPADDR -> CP_ADDR
-- 2009-06-01 221 1.3.8 add dip signal in ib_mreq (set in s_ib)
-- 2009-05-30 220 1.3.7 final removal of snoopers (were already commented)
-- 2009-05-01 211 1.3.6 BUGFIX: add 177776 stack protect (SCCE)
-- 2008-08-22 161 1.3.5 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
-- 2008-04-25 138 1.3.4 add BRESET port, clear stklim with BRESET
-- 2008-04-20 137 1.3.3 add DM_STAT_VM port
-- 2008-03-19 127 1.3.2 ignore ack state when waiting on a busy IB in s_ib
-- 2008-03-02 121 1.3.1 remove snoopers
-- 2008-02-24 119 1.3 revamp paddr generation; add _ubmap
-- 2008-02-23 118 1.2.1 use sys_conf_mem_losize
-- 2008-02-17 117 1.2 use em_(mreq|sres) interface for external memory
-- 2008-01-26 114 1.1.4 rename 'ubus' to 'ib' (proper name of intbus now)
-- 2008-01-05 110 1.1.3 update snooper.
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2008-01-01 109 1.1.2 Use IB_SRES_(CPU|EXT); use r./n. coding style, move
-- all status into regs_type. add intbus HOLD support.
-- 2007-12-30 108 1.1.1 use ubf_byte[01]
-- 2007-12-30 107 1.1 Use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-09-16 83 1.0.2 Use ram_1swsr_wfirst_gen, not ram_2swsr_wfirst_gen
-- 2nd port was unused, connected ADDR caused slow net
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_vmbox is -- virtual memory
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CP_ADDR : in cp_addr_type; -- console port address
VM_CNTL : in vm_cntl_type; -- vm control port
VM_ADDR : in slv16; -- vm address
VM_DIN : in slv16; -- vm data in
VM_STAT : out vm_stat_type; -- vm status port
VM_DOUT : out slv16; -- vm data out
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
MMU_MONI : in mmu_moni_type; -- mmu monitor port
IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
);
end pdp11_vmbox;
architecture syn of pdp11_vmbox is
constant ibaddr_slim : slv16 := slv(to_unsigned(8#177774#,16));
constant atowidth : natural := 5; -- size of access timeout counter
type state_type is (
s_idle, -- s_idle: wait for vm_cntl request
s_mem_w, -- s_mem_w: check mmu, wait for memory
s_ib_w, -- s_ib_w: wait for ibus
s_ib_wend, -- s_ib_wend: ibus write completion
s_ib_rend, -- s_ib_rend: ibus read completion
s_idle_mw_ib, -- s_idle_mw_ib: wait macc write (ibus)
s_idle_mw_mem, -- s_idle_mw_mem: wait macc write (mem)
s_mem_mw_w, -- s_mem_mw_w: wait for memory (macc)
s_fail, -- s_fail: vmbox fatal error catcher
s_errrsv, -- s_errrsv: red stack violation
s_errib -- s_errib: ibus error handler
);
type regs_type is record -- state registers
state : state_type; -- state
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access
bytop : slbit; -- byte operation
kstack : slbit; -- access through kernel stack
ysv : slbit; -- yellow stack violation detected
vaok : slbit; -- virtual address valid (from MMU)
trap_mmu : slbit; -- mmu trace trap requested
mdin : slv16; -- data input (memory order)
paddr : slv22; -- physical address register
paddr_iopage : slv9; -- iopage base (upper 9 bits of paddr)
atocnt : slv(atowidth-1 downto 0); -- access timeout counter
ibre : slbit; -- ibus re signal
ibwe : slbit; -- ibus we signal
ibbe : slv2; -- ibus be0,be1 signals
ibrmw : slbit; -- ibus rmw signal
ibcacc : slbit; -- ibus cacc signal
ibracc : slbit; -- ibus racc signal
ibdout : slv16; -- ibus dout register
end record regs_type;
constant atocnt_init : slv(atowidth-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
s_idle, -- state
'0','0','0','0', -- wacc,macc,cacc,bytop
'0','0','0','0', -- kstack,ysv,vaok,trap_mmu
(others=>'0'), -- mdin
(others=>'0'), -- paddr
(others=>'0'), -- paddr_iopage
atocnt_init, -- atocnt
'0','0',"00", -- ibre,ibwe,ibbe
'0','0','0', -- ibrmw,ibcacc,ibracc
(others=>'0') -- ibdout
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal R_SLIM : slv8 := (others=>'0'); -- stack limit register
signal MMU_CNTL : mmu_cntl_type := mmu_cntl_init;
signal MMU_STAT : mmu_stat_type := mmu_stat_init;
signal PADDRH : slv16 := (others=>'0');
signal IBSEL_SLIM :slbit := '0'; -- select stack limit reg
signal IB_SRES_SLIM : ib_sres_type := ib_sres_init;
signal IB_SRES_MMU : ib_sres_type := ib_sres_init;
signal IB_SRES_UBMAP : ib_sres_type := ib_sres_init;
signal UBMAP_MREQ : slbit := '0';
signal UBMAP_ADDR_PM : slv22_1 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init; -- ibus request (local)
signal IB_SRES : ib_sres_type := ib_sres_init; -- ibus response (local)
signal IB_SRES_INT : ib_sres_type := ib_sres_init; -- ibus response (cpu)
begin
MMU : pdp11_mmu
port map (
CLK => CLK,
CRESET => CRESET,
BRESET => BRESET,
CNTL => MMU_CNTL,
VADDR => VM_ADDR,
MONI => MMU_MONI,
STAT => MMU_STAT,
PADDRH => PADDRH,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MMU
);
UBMAP : pdp11_ubmap
port map (
CLK => CLK,
MREQ => UBMAP_MREQ,
ADDR_UB => CP_ADDR.addr(17 downto 1),
ADDR_PM => UBMAP_ADDR_PM,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_UBMAP
);
SRES_OR_INT : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_CPU,
IB_SRES_2 => IB_SRES_SLIM,
IB_SRES_3 => IB_SRES_MMU,
IB_SRES_4 => IB_SRES_UBMAP,
IB_SRES_OR => IB_SRES_INT
);
SRES_OR_ALL : ib_sres_or_2
port map (
IB_SRES_1 => IB_SRES_INT,
IB_SRES_2 => IB_SRES_EXT,
IB_SRES_OR => IB_SRES
);
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_slim)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SLIM
);
proc_ibres : process (IBSEL_SLIM, IB_MREQ, R_SLIM)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_SLIM = '1' then
idout(ibf_byte1) := R_SLIM;
end if;
IB_SRES_SLIM.dout <= idout;
IB_SRES_SLIM.ack <= IBSEL_SLIM and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES_SLIM.busy <= '0';
end process proc_ibres;
proc_slim: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_SLIM <= (others=>'0');
elsif IBSEL_SLIM='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
R_SLIM <= IB_MREQ.din(ibf_byte1);
end if;
end if;
end if;
end process proc_slim;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, R_SLIM, CP_ADDR, VM_CNTL, VM_DIN, VM_ADDR,
IB_SRES, UBMAP_ADDR_PM,
EM_SRES, MMU_STAT, PADDRH)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ivm_stat : vm_stat_type := vm_stat_init;
variable ivm_dout : slv16 := (others=>'0');
variable iem_mreq : em_mreq_type := em_mreq_init;
variable immu_cntl : mmu_cntl_type := mmu_cntl_init;
variable ipaddr : slv22 := (others=>'0');
variable ipaddr_iopage : slv9 := (others=>'0');
variable iib_aval : slbit := '0';
variable ato_go : slbit := '0';
variable ato_end : slbit := '0';
variable is_stackyellow : slbit := '1'; -- VM_ADDR in yellow stack zone
variable is_stackred : slbit := '1'; -- VM_ADDR in red stack zone
variable iubmap_mreq : slbit := '0';
variable paddr_mmu : slbit := '0';
variable paddr_sel : slv2 := "00";
constant c_paddr_sel_vmaddr : slv2 := "00";
constant c_paddr_sel_rpaddr : slv2 := "01";
constant c_paddr_sel_cacc : slv2 := "10";
constant c_paddr_sel_ubmap : slv2 := "11";
begin
r := R_REGS;
n := R_REGS;
n.state := s_fail;
ivm_stat := vm_stat_init;
ivm_dout := EM_SRES.dout;
immu_cntl := mmu_cntl_init;
iib_aval := '0';
iem_mreq := em_mreq_init;
iem_mreq.din := VM_DIN;
if VM_CNTL.bytop = '0' then -- if word access
iem_mreq.be := "11"; -- both be's
else
if VM_ADDR(0) = '0' then -- if low byte
iem_mreq.be := "01";
else -- if high byte
iem_mreq.be := "10";
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
end if;
iubmap_mreq :='0';
paddr_mmu := '1'; -- ipaddr selector, used in s_idle
-- and overwritten in s_idle_mw_mem
paddr_sel := "00";
if MMU_STAT.ena_mmu='0' or VM_CNTL.cacc='1' then
paddr_mmu := '0';
paddr_sel := c_paddr_sel_vmaddr;
if VM_CNTL.cacc = '1' then
if CP_ADDR.ena_ubmap='1' and MMU_STAT.ena_ubmap='1' then
paddr_sel := c_paddr_sel_ubmap;
else
paddr_sel := c_paddr_sel_cacc;
end if;
end if;
end if;
-- the iopage base is determined based on mmu regs and request type
-- r.paddr_iopage is updated during s_idle. This way the iopage base
-- address is determined in parallel to paddr and latched at end of s_idle.
-- Note: is VM_CNTL.cacc here, the status in s_idle is relevant !
ipaddr_iopage := "111111111"; -- iopage match pattern (for 22 bit)
if VM_CNTL.cacc = '1' then
if CP_ADDR.ena_22bit = '0' then
ipaddr_iopage := "000000111"; -- 16 bit cacc
end if;
else
if MMU_STAT.ena_mmu = '0' then
ipaddr_iopage := "000000111"; -- 16 bit mode
else
if MMU_STAT.ena_22bit = '0' then
ipaddr_iopage := "000011111"; -- 18 bit mode
end if;
end if;
end if;
ato_go := '0'; -- default: keep access timeout in reset
ato_end := '0';
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
ato_end := '1'; -- signal expiration
end if;
is_stackyellow := '0';
is_stackred := '0';
if unsigned(VM_ADDR(15 downto 8)) <= unsigned(R_SLIM) then
is_stackyellow := '1';
if unsigned(VM_ADDR(7 downto 5)) /= 7 then -- below 340
is_stackred := '1';
end if;
end if;
if VM_ADDR(15 downto 1) = "111111111111111" then -- vaddr == 177776
is_stackred := '1';
end if;
immu_cntl.wacc := VM_CNTL.wacc;
immu_cntl.macc := VM_CNTL.macc;
immu_cntl.cacc := VM_CNTL.cacc;
immu_cntl.dspace := VM_CNTL.dspace;
immu_cntl.mode := VM_CNTL.mode;
immu_cntl.trap_done := VM_CNTL.trap_done;
case r.state is
when s_idle => -- s_idle: wait for vm_cntl request --
n.state := s_idle;
iubmap_mreq := '1'; -- activate ubmap always in s_idle
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.cacc := VM_CNTL.cacc;
n.bytop := VM_CNTL.bytop;
n.kstack := VM_CNTL.kstack;
n.ysv := '0';
n.vaok := MMU_STAT.vaok;
n.trap_mmu := MMU_STAT.trap;
n.mdin := iem_mreq.din;
-- n.paddr assignment handled separately in 'if state=s_idle' at the
-- end.
immu_cntl.req := '1';
if VM_CNTL.wacc='1' and VM_CNTL.macc='1' then
n.state := s_fail;
elsif VM_CNTL.kstack='1' and VM_CNTL.intrsv='0' and
is_stackred='1' then
n.state := s_errrsv;
else
iem_mreq.req := '1';
iem_mreq.we := VM_CNTL.wacc;
if VM_CNTL.kstack='1'and VM_CNTL.intrsv='0' then
n.ysv := is_stackyellow;
end if;
n.state := s_mem_w;
end if;
end if;
when s_mem_w => -- s_mem_w: check mmu, wait for memory
if r.bytop='0' and r.paddr(0)='1' then -- odd address ?
ivm_stat.err := '1';
ivm_stat.err_odd := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
elsif r.vaok = '0' then -- MMU abort ?
ivm_stat.err := '1';
ivm_stat.err_mmu := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
else
if r.paddr(21 downto 13) = r.paddr_iopage then
-- I/O page decoded
iem_mreq.cancel := '1'; -- cancel pending mem request
iib_aval := '1'; -- declare ibus addr valid
n.ibre := not r.wacc;
n.ibwe := r.wacc;
n.ibcacc := r.cacc;
n.ibracc := r.cacc and CP_ADDR.racc;
n.ibbe := "11";
if r.cacc = '1' then -- console access ?
n.ibbe := CP_ADDR.be;
else -- cpu access ?
if r.bytop = '1' then
if r.paddr(0) = '0' then
n.ibbe(1) := '0';
else
n.ibbe(0) := '0';
end if;
end if;
end if;
n.ibrmw := r.macc;
n.state := s_ib_w;
else
if unsigned(r.paddr(21 downto 6)) > sys_conf_mem_losize then
ivm_stat.err := '1';
ivm_stat.err_nxm := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
else
if EM_SRES.ack_r='1' or EM_SRES.ack_w='1' then
ivm_stat.ack := '1';
ivm_stat.trap_ysv := r.ysv;
ivm_stat.trap_mmu := r.trap_mmu;
if r.macc='1' and r.wacc='0' then
n.state := s_idle_mw_mem;
else
n.state := s_idle;
end if;
else
n.state := s_mem_w; -- keep waiting
end if;
end if;
end if;
end if;
when s_ib_w => -- s_ib_w: wait for ibus -------------
ato_go := '1'; -- activate timeout counter
iib_aval := '1'; -- declare ibus addr valid
n.ibre := '0'; -- end cycle, unless busy seen
n.ibwe := '0';
n.ibrmw := '0';
n.ibbe := "00";
n.ibcacc := '0';
n.ibracc := '0';
if IB_SRES.ack='1' and IB_SRES.busy='0' then -- ibus cycle finished
if r.wacc = '1' then
n.state := s_ib_wend;
else
if r.macc = '1' then -- if first part of rmw
n.ibrmw := r.macc; -- keep rmw
n.ibbe := r.ibbe; -- keep be's
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
end if;
n.ibdout := IB_SRES.dout;
n.state := s_ib_rend;
end if;
elsif IB_SRES.busy='1' and ato_end='0' then
n.ibre := r.ibre; -- continue ibus cycle
n.ibwe := r.ibwe;
n.ibrmw := r.ibrmw;
n.ibbe := r.ibbe;
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
n.state := s_ib_w;
else
n.state := s_errib;
end if;
when s_ib_wend => -- s_ib_wend: ibus write completion --
ivm_stat.ack := '1';
n.state := s_idle;
when s_ib_rend => -- s_ib_rend: ibus read completion ---
ivm_stat.ack := '1';
ivm_dout := r.ibdout;
if r.macc='1' then -- first part of read-mod-write
iib_aval := '1'; -- keep ibus addr valid
n.state := s_idle_mw_ib;
else
n.state := s_idle;
end if;
when s_idle_mw_ib => -- s_idle_mw_ib: wait macc write (ibus)
n.state := s_idle_mw_ib;
iib_aval := '1'; -- keep ibus addr valid
if r.ibbe = "10" then
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.mdin := iem_mreq.din;
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
n.state := s_fail;
else
n.ibwe := '1'; -- Note: all other ibus drivers
-- already set in 1st part
n.state := s_ib_w;
end if;
end if;
when s_idle_mw_mem => -- s_idle_mw_mem: wait macc write (mem)
n.state := s_idle_mw_mem;
paddr_mmu := '0';
paddr_sel := c_paddr_sel_rpaddr;
if VM_CNTL.bytop = '0' then -- if word access
iem_mreq.be := "11"; -- both be's
else
if r.paddr(0) = '0' then -- if low byte
iem_mreq.be := "01";
else -- if high byte
iem_mreq.be := "10";
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
end if;
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.bytop := VM_CNTL.bytop;
n.mdin := iem_mreq.din;
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
n.state := s_fail;
else
iem_mreq.req := '1';
iem_mreq.we := '1';
n.state := s_mem_mw_w;
end if;
end if;
when s_mem_mw_w => -- s_mem_mw_w: wait for memory (macc)
if EM_SRES.ack_w = '1' then
ivm_stat.ack := '1';
n.state := s_idle;
else
n.state := s_mem_mw_w; -- keep waiting
end if;
when s_fail => -- s_fail: vmbox fatal error catcher
ivm_stat.fail := '1';
n.state := s_idle;
when s_errrsv => -- s_errrsv: red stack violation -----
ivm_stat.err := '1';
ivm_stat.err_rsv := '1';
n.state := s_idle;
when s_errib => -- s_errib: ibus error handler -------
ivm_stat.err := '1';
ivm_stat.err_iobto := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
n.state := s_idle;
when others => null;
end case;
if r.bytop='1' and r.paddr(0)='1' then
ivm_dout(ibf_byte0) := ivm_dout(ibf_byte1);
end if;
if ato_go = '0' then -- handle access timeout counter
n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
else
n.atocnt := slv(unsigned(r.atocnt) - 1);-- otherwise count down
end if;
ipaddr := (others=>'0');
if paddr_mmu = '1' then
ipaddr( 5 downto 0) := VM_ADDR(5 downto 0);
ipaddr(21 downto 6) := PADDRH;
if MMU_STAT.ena_22bit = '0' then
ipaddr(21 downto 18) := (others=>'0');
end if;
else
case paddr_sel is
when c_paddr_sel_vmaddr =>
ipaddr(15 downto 0) := VM_ADDR(15 downto 0);
when c_paddr_sel_rpaddr =>
ipaddr := r.paddr;
when c_paddr_sel_cacc =>
ipaddr := CP_ADDR.addr & '0';
if CP_ADDR.ena_22bit = '0' then
ipaddr(21 downto 16) := (others=>'0');
end if;
when c_paddr_sel_ubmap =>
ipaddr := UBMAP_ADDR_PM & '0';
when others => null;
end case;
end if;
if r.state = s_idle then
n.paddr := ipaddr;
n.paddr_iopage := ipaddr_iopage;
end if;
iem_mreq.addr := ipaddr(21 downto 1);
N_REGS <= n;
UBMAP_MREQ <= iubmap_mreq;
IB_MREQ.aval <= iib_aval;
IB_MREQ.re <= r.ibre;
IB_MREQ.we <= r.ibwe;
IB_MREQ.be0 <= r.ibbe(0);
IB_MREQ.be1 <= r.ibbe(1);
IB_MREQ.rmw <= r.ibrmw;
IB_MREQ.cacc <= r.ibcacc;
IB_MREQ.racc <= r.ibracc;
IB_MREQ.addr <= r.paddr(12 downto 1);
IB_MREQ.din <= r.mdin;
VM_DOUT <= ivm_dout;
VM_STAT <= ivm_stat;
MMU_CNTL <= immu_cntl;
EM_MREQ <= iem_mreq;
end process proc_next;
IB_MREQ_M <= IB_MREQ; -- external drive master port
DM_STAT_VM.ibmreq <= IB_MREQ;
DM_STAT_VM.ibsres <= IB_SRES;
end syn;
| gpl-2.0 |
xylnao/w11a-extra | rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd | 1 | 7323 | -- $Id: tb_nexys3_fusp.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_fusp - sim
-- Description: Test bench for nexys3 (base+fusp)
--
-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
-- vlib/xlib/dcm_sfs
-- tb_nexys3_core
-- vlib/serport/serport_uart_rxtx
-- nexys3_fusp_aif [UUT]
--
-- To test: generic, any nexys3_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serport.all;
use work.xlib.all;
use work.nexys3lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys3_fusp is
end tb_nexys3_fusp;
architecture sim of tb_nexys3_fusp is
signal CLKOSC : slbit := '0';
signal CLKSYS : slbit := '0';
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_PPCM_CE_N : slbit := '0';
signal O_PPCM_RST_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL : slbit := '0';
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clockosc_period : time := 10 ns;
constant clockosc_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 9 ns;
begin
TBCORE : tbcore_rlink_dcm
generic map (
CLKOSC_PERIOD => clockosc_period,
CLKOSC_OFFSET => clockosc_offset,
SETUP_TIME => setup_time,
C2OUT_TIME => c2out_time)
port map (
CLKOSC => CLKOSC,
CLKSYS => CLKSYS,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
DCM_SYS : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKSYS,
LOCKED => open
);
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
N3CORE : entity work.tb_nexys3_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys3_fusp_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_PPCM_CE_N => O_PPCM_CE_N,
O_PPCM_RST_N => O_PPCM_RST_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKSYS,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKSYS);
wait for c2out_time;
if RXERR = '1' then
writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL <= to_x01(SB_DATA(0));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-2.0 |
xylnao/w11a-extra | rtl/vlib/serport/serport_1clock.vhd | 1 | 7756 | -- $Id: serport_1clock.vhd 438 2011-12-11 23:40:52Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_1clock - syn
-- Description: serial port: serial port module, 1 clock domain
--
-- Dependencies: serport_uart_rxtx_ab
-- serport_xonrx
-- serport_xontx
-- memlib/fifo_1c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-13 424 13.1 O40d xc3s1000-4 157 337 64 232 s 9.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 internal reset on abact
-- 2011-12-09 437 1.0.1 rename stat->moni port
-- 2011-11-13 424 1.0 Initial version
-- 2011-10-23 419 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serport.all;
use work.memlib.all;
entity serport_1clock is -- serial port module, 1 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXHOLD : in slbit; -- receiver data hold
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
MONI : out serport_moni_type; -- serport monitor port
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RXRTS_N : out slbit; -- receive rts (uart view, act.low)
TXCTS_N : in slbit -- transmit cts (uart view, act.low)
);
end serport_1clock;
architecture syn of serport_1clock is
signal R_RXOK : slbit := '1';
signal RESET_INT : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal XONTX_TXENA : slbit := '0';
signal XONTX_TXBUSY : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXFIFO_SIZE : slv(RXFAWIDTH downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal RXERR : slbit := '0';
signal RXOVR : slbit := '0';
signal RXACT : slbit := '0';
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0');
signal TXOK : slbit := '0';
signal RXOK : slbit := '0';
begin
assert CDWIDTH<=16
report "assert(CDWIDTH<=16): max width of UART clock divider"
severity failure;
UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
RXSD => RXSD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
ABACT => ABACT,
ABDONE => ABDONE,
ABCLKDIV => ABCLKDIV
);
RESET_INT <= RESET or ABACT;
XONRX : serport_xonrx -- xon/xoff logic rx path
port map (
CLK => CLK,
RESET => RESET_INT,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_RXDATA => UART_RXDATA,
UART_RXVAL => UART_RXVAL,
RXDATA => RXFIFO_DI,
RXVAL => RXFIFO_ENA,
RXHOLD => RXFIFO_BUSY,
RXOVR => RXOVR,
TXOK => TXOK
);
XONTX : serport_xontx -- xon/xoff logic tx path
port map (
CLK => CLK,
RESET => RESET_INT,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_TXDATA => UART_TXDATA,
UART_TXENA => XONTX_TXENA,
UART_TXBUSY => XONTX_TXBUSY,
TXDATA => TXFIFO_DO,
TXENA => TXFIFO_VAL,
TXBUSY => TXFIFO_HOLD,
RXOK => RXOK,
TXOK => TXOK
);
RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET_INT,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZE => RXFIFO_SIZE
);
TXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET_INT,
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZE => open
);
-- receive back preasure
-- on if fifo more than 3/4 full
-- off if fifo less than 1/2 full
proc_rxok: process (CLK)
constant rxsize_rxok_off : slv3 := "011";
constant rxsize_rxok_on : slv3 := "010";
variable rxsize_msb : slv3 := "000";
begin
if rising_edge(CLK) then
if RESET_INT = '1' then
R_RXOK <= '1';
else
rxsize_msb := RXFIFO_SIZE(RXFAWIDTH downto RXFAWIDTH-2);
if unsigned(rxsize_msb) >= unsigned(rxsize_rxok_off) then
R_RXOK <= '0';
elsif unsigned(rxsize_msb) <= unsigned(rxsize_rxok_on) then
R_RXOK <= '1';
end if;
end if;
end if;
end process proc_rxok;
RXOK <= R_RXOK;
RXRTS_N <= not R_RXOK;
proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
begin
if TXCTS_N = '0' then -- transmit cts asserted
UART_TXENA <= XONTX_TXENA;
XONTX_TXBUSY <= UART_TXBUSY;
else -- transmit cts not asserted
UART_TXENA <= '0';
XONTX_TXBUSY <= '1';
end if;
end process proc_cts;
MONI.rxerr <= RXERR;
MONI.rxovr <= RXOVR;
MONI.rxact <= RXACT;
MONI.txact <= UART_TXBUSY;
MONI.abact <= ABACT;
MONI.abdone <= ABDONE;
MONI.rxok <= RXOK;
MONI.txok <= TXOK;
proc_abclkdiv: process (ABCLKDIV)
begin
MONI.abclkdiv <= (others=>'0');
MONI.abclkdiv(ABCLKDIV'range) <= ABCLKDIV;
end process proc_abclkdiv;
end syn;
| gpl-2.0 |
wgml/sysrek | skin_color_segm/ipcore_dir/LUT/simulation/LUT_tb_pkg.vhd | 6 | 5828 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: LUT_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE LUT_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END LUT_TB_PKG;
PACKAGE BODY LUT_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END LUT_TB_PKG;
| gpl-2.0 |
xylnao/w11a-extra | rtl/vlib/rbus/rb_mon_sb.vhd | 1 | 2754 | -- $Id: rb_mon_sb.vhd 346 2010-12-22 22:59:26Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_mon_sb - sim
-- Description: simbus wrapper for rbus monitor (for tb's)
--
-- Dependencies: simbus
-- Test bench: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-22 346 3.0 renamed rritb_rbmon_sb -> rb_mon_sb
-- 2010-06-05 301 2.0.2 renamed _rpmon -> _rbmon
-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- use sbcntl_sbf_cpmon def
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2007-12-23 105 1.2 added AP_LAM display
-- 2007-11-24 98 1.1 added RP_IINT support
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rblib.all;
entity rb_mon_sb is -- simbus wrapper for rbus monitor
generic (
DBASE : positive := 2; -- base for writing data values
ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end rb_mon_sb;
architecture sim of rb_mon_sb is
signal ENA : slbit := '0';
begin
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
ENA <= to_x01(SB_CNTL(ENAPIN));
RBMON : rb_mon
generic map (
DBASE => DBASE)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
ENA => ENA,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
end sim;
| gpl-2.0 |
xylnao/w11a-extra | rtl/sys_gen/tst_serloop/nexys2/sys_conf1.vhd | 2 | 1446 | -- $Id: sys_conf1.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop1_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-16 439 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkdiv_usecdiv : integer := 50; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_uart_cdinit : integer := 434-1; -- 50000000/115200
end package sys_conf;
| gpl-2.0 |
vhavlena/appreal | netbench/pattern_match/vhdl/onehot2binary.vhd | 1 | 1847 | -- ----------------------------------------------------------------------------
-- Entity for conversion from one hot encoding to binary encoding
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity ONEHOT2BINARY is
generic(
INPUT_DATA_WIDTH : integer := 16;
OUTPUT_DATA_WIDTH : integer := 4
);
port(
-- input data interface
INPUT : in std_logic_vector(INPUT_DATA_WIDTH - 1 downto 0);
-- output data interface
OUTPUT : out std_logic_vector(OUTPUT_DATA_WIDTH - 1 downto 0);
VLD : out std_logic
);
end entity ONEHOT2BINARY;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of ONEHOT2BINARY is
begin
one_hot_2_binary: process(INPUT)
variable bin : std_logic_vector(OUTPUT_DATA_WIDTH - 1 downto 0);
begin
bin:= (others => '0');
for i in INPUT_DATA_WIDTH-1 downto 0 loop
if (INPUT(i) = '1') then
bin := conv_std_logic_vector(i, 32);
end if;
end loop;
OUTPUT <= bin;
end process one_hot_2_binary;
generic_or: process(INPUT)
begin
if (INPUT = conv_std_logic_vector(0, INPUT_DATA_WIDTH)) then
VLD <= '0';
else
VLD <= '1';
end if;
end process generic_or;
end architecture full; | gpl-2.0 |
xylnao/w11a-extra | rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vhd | 1 | 4000 | -- $Id: nexys2_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys2_dummy - syn
-- Description: nexys2 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys2
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.2 use nxcramlib
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0 Initial version (derived from s3board_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys2_fusp_dummy is -- NEXYS 2 dummy (base+fusp; loopback)
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end nexys2_fusp_dummy;
architecture syn of nexys2_fusp_dummy is
begin
O_CLKSYS <= I_CLK50; -- use 50 MHz clock
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
| gpl-2.0 |
xylnao/w11a-extra | rtl/sys_gen/tst_rlink/s3board/tb/tb_tst_rlink_s3.vhd | 2 | 1397 | -- $Id: tb_tst_rlink_s3.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_s3
-- Description: Configuration for tb_tst_rlink_s3 for tb_s3board_fusp
--
-- Dependencies: sys_tst_rlink_s3
--
-- To test: sys_tst_rlink_s3
--
-- Verified:
-- Date Rev Code ghdl ise Target Comment
-- 2011-12-22 442 - 0.29 13.1 O40d xc3s1000 u:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-22 442 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_rlink_s3 of tb_s3board_fusp is
for sim
for all : s3board_fusp_aif
use entity work.sys_tst_rlink_s3;
end for;
end for;
end tb_tst_rlink_s3;
| gpl-2.0 |
xylnao/w11a-extra | rtl/bplib/nexys3/tb/tb_nexys3_core.vhd | 1 | 3201 | -- $Id: tb_nexys3_core.vhd 432 2011-11-25 20:16:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_core - sim
-- Description: Test bench for nexys3 - core device handling
--
-- Dependencies: vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys3 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serport.all;
use work.simbus.all;
entity tb_nexys3_core is
port (
I_SWI : out slv8; -- n3 switches
I_BTN : out slv5; -- n3 buttons
O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
O_MEM_CLK : in slbit; -- cram: clock
O_MEM_CRE : in slbit; -- cram: command register enable
I_MEM_WAIT : out slbit; -- cram: mem wait
O_MEM_ADDR : in slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tb_nexys3_core;
architecture sim of tb_nexys3_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
| gpl-2.0 |
xylnao/w11a-extra | rtl/vlib/rlink/rlink_mon_sb.vhd | 1 | 2639 | -- $Id: rlink_mon_sb.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_mon_sb - sim
-- Description: simbus wrapper for rlink monitor
--
-- Dependencies: simbus
-- Test bench: -
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.0 renamed rritb_cpmon_sb -> rlink_mon_sb
-- 2010-05-02 287 1.0.1 use sbcntl_sbf_cpmon def
-- 2007-08-25 75 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rlinklib.all;
entity rlink_mon_sb is -- simbus wrap for rlink monitor
generic (
DWIDTH : positive := 9; -- data port width (8 or 9)
ENAPIN : integer := sbcntl_sbf_rlmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end rlink_mon_sb;
architecture sim of rlink_mon_sb is
signal ENA : slbit := '0';
begin
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
ENA <= to_x01(SB_CNTL(ENAPIN));
CPMON : rlink_mon
generic map (
DWIDTH => DWIDTH)
port map (
CLK => CLK,
CLK_CYCLE => SB_CLKCYCLE,
ENA => ENA,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD
);
end sim;
| gpl-2.0 |
wgml/sysrek | skin_color_segm/ipcore_dir/LUT/simulation/LUT_tb.vhd | 6 | 4189 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: LUT_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY LUT_tb IS
END ENTITY;
ARCHITECTURE LUT_tb_ARCH OF LUT_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
LUT_tb_synth_inst:ENTITY work.LUT_tb_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-2.0 |
wgml/sysrek | hdmi_example/ipcore_dir/LUT/simulation/LUT_tb.vhd | 6 | 4189 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: LUT_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY LUT_tb IS
END ENTITY;
ARCHITECTURE LUT_tb_ARCH OF LUT_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
LUT_tb_synth_inst:ENTITY work.LUT_tb_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-2.0 |
xylnao/w11a-extra | rtl/w11a/tb/tbd_pdp11core.vhd | 2 | 7932 | -- $Id: tbd_pdp11core.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_pdp11core - syn
-- Description: Wrapper for pdp11_core to avoid records. It has a port
-- interface which will not be modified by xst synthesis
-- (no records, no generic port).
--
-- Dependencies: genlib/clkdivce
-- pdp11_core
-- pdp11_bram
-- ibus/ibdr_minisys
-- pdp11_tmu_sb [sim only]
--
-- To test: pdp11_core
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-06-13 305 11.4 L68 xc3s1000-4 601 2504 206 1428 s 18.6
-- 2008-03-01 120 8.2.03 I34 xc3s1000-4 679 2562 206 1465 s 18.5
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 605 2324 164 1297 s 18.7
-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 536 2119 119 1184 s 19.3
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 INTERNAL_ERROR -> blog_webpack
-- 2007-10-27 92 9.1 J30 xc3s1000-4 503 2021 119 - t 18.7
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 534 2091 119 1170 s 19.3
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 557 2186 119 - s 18.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.5.1 now numeric_std clean
-- 2010-12-30 351 1.5 rename tbd_pdp11_core -> tbd_pdp11core
-- 2010-10-23 335 1.4.2 rename RRI_LAM->RB_LAM;
-- 2010-06-20 307 1.4.1 add CP_ADDR_racc, CP_ADDR_be port
-- 2010-06-13 305 1.4 add CP_ADDR_... in ports; add CP_CNTL_rnum in port
-- 2010-06-11 303 1.3.9 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.3.8 adapt to ibdr_minisys interface changes
-- 2009-05-10 214 1.3.7 use pdp11_tmu_sb instead of pdp11_tmu
-- 2008-08-22 161 1.3.6 use iblib, ibdlib
-- 2008-05-03 143 1.3.5 rename _cpursta->_cpurust
-- 2008-04-27 140 1.3.4 use cpursta interface, remove cpufail
-- 2008-04-19 137 1.3.3 add DM_STAT_(DP|VM|CO|SY) signals, add pdp11_tmu
-- 2008-04-18 136 1.3.2 add RESET for ibdr_minisys
-- 2008-02-23 118 1.3.1 use sys_conf for bram size
-- 2008-02-17 117 1.3 adapt to em_ core interface; use pdp11_bram
-- 2008-01-20 112 1.2.1 rename clkgen->clkdivce; use ibdr_minisys, BRESET;
-- 2008-01-06 111 1.2 add some external devices: KW11L, DL11, RK11
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-09-23 85 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
entity tbd_pdp11core is -- full core [no records]
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CP_CNTL_req : in slbit; -- console control port
CP_CNTL_func : in slv5; -- console control port
CP_CNTL_rnum : in slv3; -- console control port
CP_ADDR_addr : in slv22_1; -- console address port
CP_ADDR_racc : in slbit; -- console address port
CP_ADDR_be : in slv2; -- console address port
CP_ADDR_ena_22bit : in slbit; -- console address port
CP_ADDR_ena_ubmap : in slbit; -- console address port
CP_DIN : in slv16; -- console data in
CP_STAT_cmdbusy : out slbit; -- console status port
CP_STAT_cmdack : out slbit; -- console status port
CP_STAT_cmderr : out slbit; -- console status port
CP_STAT_cmdmerr : out slbit; -- console status port
CP_STAT_cpugo : out slbit; -- console status port
CP_STAT_cpuhalt : out slbit; -- console status port
CP_STAT_cpustep : out slbit; -- console status port
CP_STAT_cpurust : out slv4; -- console status port
CP_DOUT : out slv16 -- console data out
);
end tbd_pdp11core;
architecture syn of tbd_pdp11core is
signal CE_USEC : slbit := '0';
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_CNTL : cp_cntl_type := cp_cntl_init;
signal CP_ADDR : cp_addr_type := cp_addr_init;
signal CP_STAT : cp_stat_type := cp_stat_init;
signal EM_MREQ : em_mreq_type := em_mreq_init;
signal EM_SRES : em_sres_type := em_sres_init;
signal BRESET : slbit := '0';
signal IB_MREQ_M : ib_mreq_type := ib_mreq_init;
signal IB_SRES_M : ib_sres_type := ib_sres_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
begin
CP_CNTL.req <= CP_CNTL_req;
CP_CNTL.func <= CP_CNTL_func;
CP_CNTL.rnum <= CP_CNTL_rnum;
CP_ADDR.addr <= CP_ADDR_addr;
CP_ADDR.racc <= CP_ADDR_racc;
CP_ADDR.be <= CP_ADDR_be;
CP_ADDR.ena_22bit <= CP_ADDR_ena_22bit;
CP_ADDR.ena_ubmap <= CP_ADDR_ena_ubmap;
CP_STAT_cmdbusy <= CP_STAT.cmdbusy;
CP_STAT_cmdack <= CP_STAT.cmdack;
CP_STAT_cmderr <= CP_STAT.cmderr;
CP_STAT_cmdmerr <= CP_STAT.cmdmerr;
CP_STAT_cpugo <= CP_STAT.cpugo;
CP_STAT_cpuhalt <= CP_STAT.cpuhalt;
CP_STAT_cpustep <= CP_STAT.cpustep;
CP_STAT_cpurust <= CP_STAT.cpurust;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => open
);
PDP11 : pdp11_core
port map (
CLK => CLK,
RESET => RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
BRESET => BRESET,
IB_MREQ_M => IB_MREQ_M,
IB_SRES_M => IB_SRES_M,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
MEM : pdp11_bram
generic map (
AWIDTH => sys_conf_bram_awidth)
port map (
CLK => CLK,
GRESET => RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES
);
IBDR_SYS : ibdr_minisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_USEC, -- !! in test benches msec = usec !!
RESET => RESET,
BRESET => BRESET,
RB_LAM => open,
IB_MREQ => IB_MREQ_M,
IB_SRES => IB_SRES_M,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => open
);
-- synthesis translate_off
DM_STAT_SY.emmreq <= EM_MREQ;
DM_STAT_SY.emsres <= EM_SRES;
DM_STAT_SY.chit <= '0';
TMU : pdp11_tmu_sb
generic map (
ENAPIN => 13)
port map (
CLK => CLK,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_SY => DM_STAT_SY
);
-- synthesis translate_on
end syn;
| gpl-2.0 |
xylnao/w11a-extra | rtl/vlib/serport/tb/tbd_serport_autobaud.vhd | 1 | 4932 | -- $Id: tbd_serport_autobaud.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_serport_autobaud - syn
-- Description: Wrapper for serport_uart_autobaud and serport_uart_rxtx to
-- avoid records. It has a port interface which will not be
-- modified by xst synthesis (no records, no generic port).
--
-- Dependencies: clkdivce
-- serport_uart_autobaud
-- serport_uart_rxtx
-- serport_uart_rx
--
-- To test: serport_uart_autobaud
-- serport_uart_rxtx
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 151 291 0 - t 9.23
-- 2007-10-27 92 9.1 J30 xc3s1000-4 151 291 0 - t 9.23
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 153 338 0 178 s 9.45
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 152 293 0 - s 9.40
--
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2008-01-20 112 1.0.1 rename clkgen->clkdivce
-- 2007-06-24 60 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.serport.all;
entity tbd_serport_autobaud is -- serial port autobaud [tb design]
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
CE_USEC : out slbit; -- usec pulse (here every 4 clocks)
CE_MSEC : out slbit; -- msec pulse (here every 20 clocks)
CLKDIV : out slv13; -- clock divider setting
ABACT : out slbit; -- autobaud active
ABDONE : out slbit; -- autobaud done
RXDATA : out slv8; -- receiver data out (1st rx)
RXVAL : out slbit; -- receiver data valid (1st rx)
RXERR : out slbit; -- receiver data error (1st rx)
RXACT : out slbit; -- receiver active (1st rx)
TXSD2 : out slbit; -- transmit serial data (2nd tx)
RXDATA3 : out slv8; -- receiver data out (3rd rx)
RXVAL3 : out slbit; -- receiver data valid (3rd rx)
RXERR3 : out slbit; -- receiver data error (3rd rx)
RXACT3 : out slbit -- receiver active (3rd rx)
);
end tbd_serport_autobaud;
architecture syn of tbd_serport_autobaud is
constant cdwidth : positive := 13;
signal LCE_MSEC : slbit := '0';
signal LCLKDIV : slv13 := (others=>'0');
signal LRXDATA : slv8 := (others=>'0');
signal LRXVAL : slbit := '0';
signal LTXSD2 : slbit := '0';
signal LABACT : slbit := '0';
begin
CKLDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 4,
MSECDIV => 5)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => LCE_MSEC
);
AUTOBAUD : serport_uart_autobaud
generic map (
CDWIDTH => cdwidth,
CDINIT => 15)
port map (
CLK => CLK,
CE_MSEC => LCE_MSEC,
RESET => RESET,
RXSD => RXSD,
CLKDIV => LCLKDIV,
ACT => LABACT,
DONE => ABDONE
);
UART1 : serport_uart_rxtx
generic map (
CDWIDTH => cdwidth)
port map (
CLK => CLK,
RESET => LABACT,
CLKDIV => LCLKDIV,
RXSD => RXSD,
RXDATA => LRXDATA,
RXVAL => LRXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => LTXSD2,
TXDATA => LRXDATA,
TXENA => LRXVAL,
TXBUSY => open
);
UART2 : serport_uart_rx
generic map (
CDWIDTH => cdwidth)
port map (
CLK => CLK,
RESET => LABACT,
CLKDIV => LCLKDIV,
RXSD => LTXSD2,
RXDATA => RXDATA3,
RXVAL => RXVAL3,
RXERR => RXERR3,
RXACT => RXACT3
);
CE_MSEC <= LCE_MSEC;
CLKDIV <= LCLKDIV;
ABACT <= LABACT;
RXDATA <= LRXDATA;
RXVAL <= LRXVAL;
TXSD2 <= LTXSD2;
end syn;
| gpl-2.0 |
vhavlena/appreal | netbench/pattern_match/algorithms/sourdis_bispo_nfa/vhdl/state_pcre_at_least.vhd | 1 | 1814 | -- ----------------------------------------------------------------------------
-- Entity for implementation of exactly N
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity STATE_PCRE_AT_LEAST is
generic(
M : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- input data interface
INPUT : in std_logic;
SYMBOL : in std_logic;
WE : in std_logic;
-- output data interface
OUTPUT : out std_logic
);
end entity STATE_PCRE_AT_LEAST;
-- ----------------------------------------------------------------------------
-- Architecture: full
-- ----------------------------------------------------------------------------
architecture full of STATE_PCRE_AT_LEAST is
signal value : std_logic_vector(11 downto 0);
signal local_reset : std_logic;
begin
local_reset <= RESET or not SYMBOL;
cnt_symbols: process(RESET, CLK)
begin
if (CLK'event and CLK = '1') then
if (local_reset = '1') then
value <= (others => '0');
else
if (we = '1') then
if ((value > 0) or (INPUT = '1')) then
value <= value + 1;
end if;
end if;
end if;
end if;
end process;
OUTPUT <= '1' when (value >= M) else '0';
end architecture full;
| gpl-2.0 |
alex-gudilko/FPGA-DATA-CONVERTER | HDL source files/Input_filter_4channel.vhd | 1 | 3125 | ------------------------------------------------------------------------
-- Author: Aleksandr Gudilko
-- Email: [email protected]
--
-- File:Input_filter_4channel.vhd
--
-- Description:
--
-- General-purpose input filter for FPGA signals (Majority filter)
-- Eliminates line "ringing" and create stable output for high speed logic.
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity input_filter_4ch is
port(
reset :in std_logic; -- unfiltered input signal
INPUT_CLK :in std_logic; -- input clock signal
INPUT_SIGNAL_1 :in std_logic; -- unfiltered input signal
INPUT_SIGNAL_2 :in std_logic; -- unfiltered input signal
INPUT_SIGNAL_3 :in std_logic; -- unfiltered input signal
INPUT_SIGNAL_4 :in std_logic; -- unfiltered input signal
FILTERED_SIGNAL_1 :out std_logic; -- output filtered signal
FILTERED_SIGNAL_2 :out std_logic; -- output filtered signal
FILTERED_SIGNAL_3 :out std_logic; -- output filtered signal
FILTERED_SIGNAL_4 :out std_logic -- output filtered signal
);
end input_filter_4ch;
architecture arch of input_filter_4ch is
signal in1 :std_logic_vector (2 downto 0);
signal in2 :std_logic_vector (2 downto 0);
signal in3 :std_logic_vector (2 downto 0);
signal in4 :std_logic_vector (2 downto 0);
begin
FILTERED_SIGNAL_1 <= (in1(0) and in1(1)) or (in1(1) and in1(2)) or (in1(2) and in1(0));
FILTERED_SIGNAL_2 <= (in2(0) and in2(1)) or (in2(1) and in2(2)) or (in2(2) and in2(0));
FILTERED_SIGNAL_3 <= (in3(0) and in3(1)) or (in3(1) and in3(2)) or (in3(2) and in3(0));
FILTERED_SIGNAL_4 <= (in4(0) and in4(1)) or (in4(1) and in4(2)) or (in4(2) and in4(0));
proc1:
process(INPUT_CLK, reset)
begin
if reset = '0' then
in1 <= "000";
elsif rising_edge(input_clk) then
in1(2) <= in1(1);
in1(1) <= in1(0);
in1(0) <= input_signal_1;
end if;
end process proc1;
proc2:
process(INPUT_CLK, reset)
begin
if reset = '0' then
in2 <= "000";
elsif rising_edge(input_clk) then
in2(2) <= in2(1);
in2(1) <= in2(0);
in2(0) <= input_signal_2;
end if;
end process proc2;
proc3:
process(INPUT_CLK, reset)
begin
if reset = '0' then
in3 <= "000";
elsif rising_edge(input_clk) then
in3(2) <= in3(1);
in3(1) <= in3(0);
in3(0) <= input_signal_3;
end if;
end process proc3;
proc4:
process(INPUT_CLK, reset)
begin
if reset = '0' then
in4 <= "000";
elsif rising_edge(input_clk) then
in4(2) <= in4(1);
in4(1) <= in4(0);
in4(0) <= input_signal_4;
end if;
end process proc4;
end arch; | gpl-2.0 |
xylnao/w11a-extra | rtl/sys_gen/w11a/s3board/tb/tb_w11a_s3.vhd | 2 | 2088 | -- $Id: tb_w11a_s3.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_w11a_s3
-- Description: Configuration for tb_w11a_s3 for tb_s3board_fusp
--
-- Dependencies: sys_w11a_s3
--
-- To test: sys_w11a_s3
--
-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat
-- (#2) ../../tb/tb_pdp11_core_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2007-11-23 97 _tsim 0.26 9.1 J30 xc3s1000 d:ok (#2) 91497s; 632m
-- 2007-11-23 97 _tsim 0.26 9.1 J30 xc3s1000 d:ok (#1) 3356s; 632m
-- 2007-11-23 97 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (#2) 2227s
-- 2007-11-23 97 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (#1) 82s
-- 2007-10-21 91 - 0.26 - - d:ok (#2)
-- 2007-10-19 90 - 0.26 - - d:ok (#2)
-- 2007-10-19 90 - 0.26 - - d:ok (#1)
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-05-26 295 1.1.2 rename tb_s3board_pdp11core -> tb_w11a_s3
-- 2010-05-16 291 1.1.1 use now tb_s3board_fusp
-- 2010-05-02 287 1.1 use now tb_s3board_usp
-- 2007-09-23 84 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_w11a_s3 of tb_s3board_fusp is
for sim
for all : s3board_fusp_aif
use entity work.sys_w11a_s3;
end for;
end for;
end tb_w11a_s3;
| gpl-2.0 |
xylnao/w11a-extra | rtl/ibus/ibd_kw11l.vhd | 2 | 5638 | -- $Id: ibd_kw11l.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibd_kw11l - syn
-- Description: ibus dev(loc): KW11-L (line clock)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 9 23 0 14 s 5.3
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 8 25 0 15 s 5.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2009-06-01 221 1.0.5 BUGFIX: add RESET; don't clear tcnt on ibus reset
-- 2008-08-22 161 1.0.4 use iblib; add EI_ACK to proc_next sens. list
-- 2008-05-09 144 1.0.3 use intreq flop, use EI_ACK
-- 2008-01-20 112 1.0.2 fix proc_next sensitivity list; use BRESET
-- 2008-01-06 111 1.0.1 Renamed to ibd_kw11l (RRI_REQ not used)
-- 2008-01-05 110 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibd_kw11l is -- ibus dev(loc): KW11-L (line clock)
-- fixed address: 177546
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibd_kw11l;
architecture syn of ibd_kw11l is
constant ibaddr_kw11l : slv16 := slv(to_unsigned(8#177546#,16));
constant lks_ibf_ie : integer := 6;
constant lks_ibf_moni : integer := 7;
constant twidth : natural := 5;
constant tdivide : natural := 20;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
ie : slbit; -- interrupt enable
moni : slbit; -- monitor bit
intreq : slbit; -- interrupt request
tcnt : slv(twidth-1 downto 0); -- timer counter
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'0', -- ie
'1', -- moni (set on reset !!)
'0', -- intreq
(others=>'0') -- tcnt
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.tcnt <= N_REGS.tcnt; -- don't clear msec tick counter
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, CE_MSEC, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibw0 : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr=ibaddr_kw11l(12 downto 1) then
n.ibsel := '1';
end if;
-- ibus output driver
if r.ibsel = '1' then
idout(lks_ibf_ie) := R_REGS.ie;
idout(lks_ibf_moni) := R_REGS.moni;
end if;
-- ibus write transactions
if r.ibsel='1' and ibw0='1' then
n.ie := IB_MREQ.din(lks_ibf_ie);
n.moni := IB_MREQ.din(lks_ibf_moni);
if IB_MREQ.din(lks_ibf_ie)='0' or IB_MREQ.din(lks_ibf_moni)='0' then
n.intreq := '0';
end if;
end if;
-- other state changes
if CE_MSEC = '1' then
n.tcnt := slv(unsigned(r.tcnt) + 1);
if unsigned(r.tcnt) = tdivide-1 then
n.tcnt := (others=>'0');
n.moni := '1';
if r.ie = '1' then
n.intreq := '1';
end if;
end if;
end if;
if EI_ACK = '1' then
n.intreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
EI_REQ <= r.intreq;
end process proc_next;
end syn;
| gpl-2.0 |
xylnao/w11a-extra | rtl/vlib/rlink/tb/tb_rlink_sp1c.vhd | 2 | 1710 | -- $Id: tb_rlink_sp1c.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_rlink_sp1c
-- Description: Configuration for tb_rlink_sp1c for tb_rlink.
--
-- Dependencies: tbd_rlink_gen
--
-- To test: rlink_sp1c
--
-- Target Devices: generic
--
-- Verified (with tb_rlink_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (Test 15 fails)
-- 2007-10-12 88 - 0.26 - - c:ok (Test 15 fails)
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-22 442 3.2 renamed and retargeted to tbd_rlink_sp1c
-- 2010-12-05 343 3.0 rri->rlink renames
-- 2007-11-25 98 1.0.1 use entity rather arch name to switch core/serport
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_rlink_sp1c of tb_rlink is
for sim
for all : tbd_rlink_gen
use entity work.tbd_rlink_sp1c;
end for;
end for;
end tb_rlink_sp1c;
| gpl-2.0 |
xylnao/w11a-extra | rtl/ibus/ibdr_dl11.vhd | 2 | 13865 | -- $Id: ibdr_dl11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_dl11 - syn
-- Description: ibus dev(rem): DL11-A/B
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 39 126 0 72 s 7.6
-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 38 119 0 69 s 6.3
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 23 61 0 40 s 5.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.5 add RESET, CE_USEC port; implement input rate limit
-- 2008-08-22 161 1.0.6 use iblib; add EI_ACK_* to proc_next sens. list
-- 2008-05-09 144 1.0.5 use intreq flop, use EI_ACK
-- 2008-03-22 128 1.0.4 rename xdone -> xval (no functional change)
-- 2008-01-27 115 1.0.3 bugfix: set ilam when rbuf read by cpu;
-- add xdone and rrdy bits to rri xbuf read
-- 2008-01-20 113 1.0.2 fix maint mode logic (proper double buffer now)
-- 2008-01-20 112 1.0.1 use BRESET
-- 2008-01-05 108 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_dl11 is -- ibus dev(rem): DL11-A/B
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#177560#,16)));
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end ibdr_dl11;
architecture syn of ibdr_dl11 is
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
constant ibaddr_xcsr : slv2 := "10"; -- xcsr address offset
constant ibaddr_xbuf : slv2 := "11"; -- xbuf address offset
subtype rcsr_ibf_rrlim is integer range 14 downto 12;
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant xcsr_ibf_xrdy : integer := 7;
constant xcsr_ibf_xie : integer := 6;
constant xcsr_ibf_xmaint: integer := 2;
constant xbuf_ibf_xval : integer := 8;
constant xbuf_ibf_rrdy : integer := 9;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rrlim : slv3; -- rcsr: receiver rate limit
rdone : slbit; -- rcsr: receiver done
rie : slbit; -- rcsr: receiver interrupt enable
rbuf : slv8; -- rbuf:
rval : slbit; -- rx rbuf valid
rintreq : slbit; -- rx interrupt request
rdlybsy : slbit; -- rx delay busy
rdlycnt : slv10; -- rx delay counter
xrdy : slbit; -- xcsr: transmitter ready
xie : slbit; -- xcsr: transmitter interrupt enable
xmaint : slbit; -- xcsr: maintenance mode
xbuf : slv8; -- xbuf:
xintreq : slbit; -- tx interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
(others=>'0'), -- rrlim
'0','0', -- rdone, rie
(others=>'0'), -- rbuf
'0','0','0', -- rval,rintreq,rdlybsy
(others=>'0'), -- rdlycnt
'1', -- xrdy !! is set !!
'0','0', -- xie,xmaint
(others=>'0'), -- xbuf
'0' -- xintreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rrlim <= N_REGS.rrlim; -- don't reset rx rate limit
R_REGS.rdlybsy <= N_REGS.rdlybsy; -- don't reset rx delay busy
R_REGS.rdlycnt <= N_REGS.rdlycnt; -- don't reset rx delay counter
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (CE_USEC, R_REGS, IB_MREQ, EI_ACK_RX, EI_ACK_TX)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
variable rdlystart : slbit := '0';
variable rdlyinit : slv10 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
rdlystart := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rcsr => -- RCSR -- receive control status ----
idout(rcsr_ibf_rdone) := r.rdone;
idout(rcsr_ibf_rie) := r.rie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.rie := IB_MREQ.din(rcsr_ibf_rie);
if IB_MREQ.din(rcsr_ibf_rie) = '1' then
if r.rdone='1' and r.rie='0' then -- ie set while done=1
n.rintreq := '1'; -- request interrupt
end if;
else
n.rintreq := '0';
end if;
end if;
else -- rri ---------------------
idout(rcsr_ibf_rrlim) := r.rrlim;
if ibw1 = '1' then
n.rrlim := IB_MREQ.din(rcsr_ibf_rrlim);
end if;
end if;
when ibaddr_rbuf => -- RBUF -- receive data buffer -------
idout(r.rbuf'range) := r.rbuf;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibrd = '1' then
n.rdone := '0'; -- clear DONE
n.rval := '0'; -- clear rbuf valid
n.rintreq := '0'; -- clear pending interrupts
rdlystart := '1'; -- start rx delay counter
if r.xmaint = '0' then -- if not in loop-back
ilam := '1'; -- request rb attention
end if;
end if;
else -- rri ---------------------
if ibw0 = '1' then
n.rbuf := IB_MREQ.din(n.rbuf'range);
n.rval := '1'; -- set rbuf valid
if r.rdlybsy = '0' then -- if rdly timer not running
n.rdone := '1'; -- set DONE
if r.rie = '1' then -- if rx interrupt enabled
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
when ibaddr_xcsr => -- XCSR -- transmit control status ---
idout(xcsr_ibf_xrdy) := r.xrdy;
idout(xcsr_ibf_xie) := r.xie;
idout(xcsr_ibf_xmaint):= r.xmaint;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.xie := IB_MREQ.din(xcsr_ibf_xie);
if IB_MREQ.din(xcsr_ibf_xie) = '1' then
if r.xrdy='1' and r.xie='0' then -- ie set while ready=1
n.xintreq := '1'; -- request interrupt
end if;
else
n.xintreq := '0';
end if;
n.xmaint := IB_MREQ.din(xcsr_ibf_xmaint);
end if;
end if;
when ibaddr_xbuf => -- XBUF -- transmit data buffer ------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.xbuf := IB_MREQ.din(n.xbuf'range);
n.xrdy := '0';
n.xintreq := '0';
if r.xmaint = '0' then
ilam := '1';
end if;
end if;
else -- rri ---------------------
idout(r.xbuf'range) := r.xbuf;
if r.xmaint = '0' then -- if not in maintenace mode
idout(xbuf_ibf_xval) := not r.xrdy;
idout(xbuf_ibf_rrdy) := not r.rval;
end if;
if ibrd = '1' then
n.xrdy := '1';
if r.xie = '1' then
n.xintreq := '1';
end if;
end if;
end if;
when others => null;
end case;
else -- if unselected handle loop-back
if r.xmaint = '1' and -- if in maintenace mode
r.xrdy='0' and -- and transmit pending
r.rdone='0' and -- and receive buffer empty
r.rdlybsy='0' then -- and rdly timer not running
n.rbuf := r.xbuf; -- copy transmit to receive buffer
n.xrdy := '1'; -- mark transmit done
n.rdone := '1'; -- make receive done
if r.rie = '1' then -- if rx interrupt enabled
n.rintreq := '1'; -- request it
end if;
if r.xie = '1' then -- if tx interrupt enabled
n.xintreq := '1'; -- request it
end if;
end if;
end if;
-- other state changes
rdlyinit := (others=>'0');
case r.rrlim is
when "000" => rdlyinit := "0000000000"; -- rlim=0 -> disabled
when "001" => rdlyinit := "0000000011"; -- rlim=1 -> delay by 3+ usec
when "010" => rdlyinit := "0000001111"; -- rlim=2 -> delay by 15+ usec
when "011" => rdlyinit := "0000111111"; -- rlim=3 -> delay by 63+ usec
when "100" => rdlyinit := "0001111111"; -- rlim=4 -> delay by 127+ usec
when "101" => rdlyinit := "0011111111"; -- rlim=5 -> delay by 255+ usec
when "110" => rdlyinit := "0111111111"; -- rlim=6 -> delay by 511+ usec
when "111" => rdlyinit := "1111111111"; -- rlim=7 -> delay by 1023+ usec
when others => null;
end case;
if rdlystart = '1' then -- if rdly timer start requested
n.rdlycnt := rdlyinit; -- init counter
if r.rrlim /= "000" then -- rate limiter enabled ?
n.rdlybsy := '1'; -- set busy
end if;
elsif CE_USEC = '1' then -- if end-of-usec
n.rdlycnt := slv(unsigned(r.rdlycnt) - 1); -- decrement
if r.rdlybsy='1' and -- if delay busy
unsigned(r.rdlycnt) = 0 then -- and counter at zero
n.rdlybsy := '0'; -- clear busy
if n.rval = '1' then -- if rbuf is valid or is set
-- valid this cycle (use n.!!)
n.rdone := '1'; -- set DONE
if r.rie = '1' then -- if rx interrupt enabled
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
if EI_ACK_RX = '1' then
n.rintreq := '0';
end if;
if EI_ACK_TX = '1' then
n.xintreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_RX <= r.rintreq;
EI_REQ_TX <= r.xintreq;
end process proc_next;
end syn;
| gpl-2.0 |
wgml/sysrek | hdmi_example/ipcore_dir/LUT/simulation/LUT_tb_synth.vhd | 6 | 7026 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: LUT_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.LUT_TB_PKG.ALL;
ENTITY LUT_tb_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 0
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END LUT_tb_synth;
ARCHITECTURE LUT_synth_ARCH OF LUT_tb_synth IS
COMPONENT LUT_exdes
PORT (
CLK : IN STD_LOGIC := '0';
QSPO : OUT STD_LOGIC_VECTOR(8-1 downto 0);
A : IN STD_LOGIC_VECTOR(8-1-(4*0*boolean'pos(8>4)) downto 0)
:= (OTHERS => '0')
);
END COMPONENT;
CONSTANT STIM_CNT : INTEGER := if_then_else(C_ROM_SYNTH = 0, 8, 22);
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i : STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ADDR: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDR_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL QSPO: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL QSPO_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
LUT_TB_STIM_GEN_INST:ENTITY work.LUT_TB_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
A => ADDR,
DATA_IN => QSPO_R,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(STIM_CNT);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDR(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW + 1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
QSPO_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
QSPO_R <= QSPO AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDR_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDR_R <= ADDR AFTER 50 ns;
END IF;
END IF;
END PROCESS;
DMG_PORT: LUT_exdes PORT MAP (
CLK => CLKA,
QSPO => QSPO,
A => ADDR_R
);
END ARCHITECTURE;
| gpl-2.0 |
xylnao/w11a-extra | rtl/w11a/pdp11_dpath.vhd | 2 | 11075 | -- $Id: pdp11_dpath.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dpath - syn
-- Description: pdp11: CPU datapath
--
-- Dependencies: pdp11_gpr
-- pdp11_psr
-- pdp11_ounit
-- pdp11_aunit
-- pdp11_lunit
-- pdp11_munit
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-09-18 300 1.2.1 rename (adlm)box->(oalm)unit
-- 2010-06-13 305 1.2 rename CPDIN -> CP_DIN; add CP_DOUT out port;
-- remove CPADDR out port; drop R_CPADDR, proc_cpaddr;
-- added R_CPDOUT, proc_cpdout
-- 2009-05-30 220 1.1.6 final removal of snoopers (were already commented)
-- 2008-12-14 177 1.1.5 fill gpr_* fields in DM_STAT_DP
-- 2008-08-22 161 1.1.4 rename ubf_ -> ibf_; use iblib
-- 2008-04-19 137 1.1.3 add DM_STAT_DP port
-- 2008-03-02 121 1.1.2 remove snoopers
-- 2008-02-24 119 1.1.1 add CPADDR register, remove R_MDIN (not needed)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now (for psr access)
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_dpath is -- CPU datapath
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
CNTL : in dpath_cntl_type; -- control interface
STAT : out dpath_stat_type; -- status interface
CP_DIN : in slv16; -- console port data in
CP_DOUT : out slv16; -- console port data out
PSWOUT : out psw_type; -- current psw
PCOUT : out slv16; -- current pc
IREG : out slv16; -- ireg out
VM_ADDR : out slv16; -- virt. memory address
VM_DOUT : in slv16; -- virt. memory data out
VM_DIN : out slv16; -- virt. memory data in
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status
);
end pdp11_dpath;
architecture syn of pdp11_dpath is
signal R_DSRC : slv16 := (others=>'0'); -- SRC register
signal R_DDST : slv16 := (others=>'0'); -- DST register
signal R_DTMP : slv16 := (others=>'0'); -- TMP register
signal R_IREG : slv16 := (others=>'0'); -- IREG register
signal R_CPDOUT : slv16 := (others=>'0'); -- cp dout buffer
signal GPR_DSRC : slv16 := (others=>'0'); --
signal GPR_DDST : slv16 := (others=>'0'); --
signal GPR_PC : slv16 := (others=>'0'); --
signal PSW : psw_type := psw_init; --
signal CCIN : slv4 := (others=>'0'); -- cc input to xbox's
signal CCOUT : slv4 := (others=>'0'); -- cc output from xbox's
signal DRES : slv16 := (others=>'0'); -- result bus
signal DRESE : slv16 := (others=>'0'); -- result bus extra
signal OUNIT_DOUT : slv16 := (others=>'0'); -- result ounit
signal AUNIT_DOUT : slv16 := (others=>'0'); -- result aunit
signal LUNIT_DOUT : slv16 := (others=>'0'); -- result lunit
signal MUNIT_DOUT : slv16 := (others=>'0'); -- result munit
signal OUNIT_NZOUT : slv2 := (others=>'0'); -- nz flags ounit
signal OUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags ounit
signal AUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags aunit
signal LUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags lunit
signal MUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags munit
subtype lal_ibf_addr is integer range 15 downto 1;
subtype lah_ibf_addr is integer range 5 downto 0;
constant lah_ibf_ena_22bit: integer := 6;
constant lah_ibf_ena_ubmap: integer := 7;
begin
GPR : pdp11_gpr port map (
CLK => CLK,
DIN => DRES,
ASRC => CNTL.gpr_asrc,
ADST => CNTL.gpr_adst,
MODE => CNTL.gpr_mode,
RSET => CNTL.gpr_rset,
WE => CNTL.gpr_we,
BYTOP => CNTL.gpr_bytop,
PCINC => CNTL.gpr_pcinc,
DSRC => GPR_DSRC,
DDST => GPR_DDST,
PC => GPR_PC
);
PSR : pdp11_psr port map(
CLK => CLK,
CRESET => CRESET,
DIN => DRES,
CCIN => CCOUT,
CCWE => CNTL.psr_ccwe,
WE => CNTL.psr_we,
FUNC => CNTL.psr_func,
PSW => PSW,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES
);
OUNIT : pdp11_ounit port map (
DSRC => R_DSRC,
DDST => R_DDST,
DTMP => R_DTMP,
PC => GPR_PC,
ASEL => CNTL.ounit_asel,
AZERO => CNTL.ounit_azero,
IREG8 => R_IREG(7 downto 0),
VMDOUT => VM_DOUT,
CONST => CNTL.ounit_const,
BSEL => CNTL.ounit_bsel,
OPSUB => CNTL.ounit_opsub,
DOUT => OUNIT_DOUT,
NZOUT => OUNIT_NZOUT
);
AUNIT : pdp11_aunit port map (
DSRC => R_DSRC,
DDST => R_DDST,
CI => CCIN(0),
SRCMOD => CNTL.aunit_srcmod,
DSTMOD => CNTL.aunit_dstmod,
CIMOD => CNTL.aunit_cimod,
CC1OP => CNTL.aunit_cc1op,
CCMODE => CNTL.aunit_ccmode,
BYTOP => CNTL.aunit_bytop,
DOUT => AUNIT_DOUT,
CCOUT => AUNIT_CCOUT
);
LUNIT : pdp11_lunit port map (
DSRC => R_DSRC,
DDST => R_DDST,
CCIN => CCIN,
FUNC => CNTL.lunit_func,
BYTOP => CNTL.lunit_bytop,
DOUT => LUNIT_DOUT,
CCOUT => LUNIT_CCOUT
);
MUNIT : pdp11_munit port map (
CLK => CLK,
DSRC => R_DSRC,
DDST => R_DDST,
DTMP => R_DTMP,
GPR_DSRC => GPR_DSRC,
FUNC => CNTL.munit_func,
S_DIV => CNTL.munit_s_div,
S_DIV_CN => CNTL.munit_s_div_cn,
S_DIV_CR => CNTL.munit_s_div_cr,
S_ASH => CNTL.munit_s_ash,
S_ASH_CN => CNTL.munit_s_ash_cn,
S_ASHC => CNTL.munit_s_ashc,
S_ASHC_CN => CNTL.munit_s_ashc_cn,
SHC_TC => STAT.shc_tc,
DIV_CR => STAT.div_cr,
DIV_CQ => STAT.div_cq,
DIV_ZERO => STAT.div_zero,
DIV_OVFL => STAT.div_ovfl,
DOUT => MUNIT_DOUT,
DOUTE => DRESE,
CCOUT => MUNIT_CCOUT
);
CCIN <= PSW.cc;
OUNIT_CCOUT <= OUNIT_NZOUT & "0" & CCIN(0); -- clear v, keep c
proc_dres_sel: process (OUNIT_DOUT, AUNIT_DOUT, LUNIT_DOUT, MUNIT_DOUT,
VM_DOUT, R_IREG, CP_DIN, CNTL)
begin
case CNTL.dres_sel is
when c_dpath_res_ounit => DRES <= OUNIT_DOUT;
when c_dpath_res_aunit => DRES <= AUNIT_DOUT;
when c_dpath_res_lunit => DRES <= LUNIT_DOUT;
when c_dpath_res_munit => DRES <= MUNIT_DOUT;
when c_dpath_res_vmdout => DRES <= VM_DOUT;
when c_dpath_res_fpdout => DRES <= (others=>'0');
when c_dpath_res_ireg => DRES <= R_IREG;
when c_dpath_res_cpdin => DRES <= CP_DIN;
when others => null;
end case;
end process proc_dres_sel;
proc_cres_sel: process (OUNIT_CCOUT, AUNIT_CCOUT, LUNIT_CCOUT, MUNIT_CCOUT,
CCIN, CNTL)
begin
case CNTL.cres_sel is
when c_dpath_res_ounit => CCOUT <= OUNIT_CCOUT;
when c_dpath_res_aunit => CCOUT <= AUNIT_CCOUT;
when c_dpath_res_lunit => CCOUT <= LUNIT_CCOUT;
when c_dpath_res_munit => CCOUT <= MUNIT_CCOUT;
when c_dpath_res_vmdout => CCOUT <= CCIN;
when c_dpath_res_fpdout => CCOUT <= "0000";
when c_dpath_res_ireg => CCOUT <= CCIN;
when c_dpath_res_cpdin => CCOUT <= CCIN;
when others => null;
end case;
end process proc_cres_sel;
proc_dregs: process (CLK)
begin
if rising_edge(CLK) then
if CNTL.dsrc_we = '1' then
if CNTL.dsrc_sel = '0' then
R_DSRC <= GPR_DSRC;
else
R_DSRC <= DRES;
end if;
end if;
if CNTL.ddst_we = '1' then
if CNTL.ddst_sel = '0' then
R_DDST <= GPR_DDST;
else
R_DDST <= DRES;
end if;
end if;
if CNTL.dtmp_we = '1' then
case CNTL.dtmp_sel is
when c_dpath_dtmp_dsrc => R_DTMP <= GPR_DSRC;
when c_dpath_dtmp_psw =>
R_DTMP <= (others=>'0');
R_DTMP(psw_ibf_cmode) <= PSW.cmode;
R_DTMP(psw_ibf_pmode) <= PSW.pmode;
R_DTMP(psw_ibf_rset) <= PSW.rset;
R_DTMP(psw_ibf_pri) <= PSW.pri;
R_DTMP(psw_ibf_tflag) <= PSW.tflag;
R_DTMP(psw_ibf_cc) <= PSW.cc;
when c_dpath_dtmp_dres => R_DTMP <= DRES;
when c_dpath_dtmp_drese => R_DTMP <= DRESE;
when others => null;
end case;
end if;
end if;
end process proc_dregs;
proc_mregs: process (CLK)
begin
if rising_edge(CLK) then
if CNTL.ireg_we = '1' then
R_IREG <= VM_DOUT;
end if;
end if;
end process proc_mregs;
proc_cpdout: process (CLK)
begin
if rising_edge(CLK) then
if CRESET = '1' then
R_CPDOUT <= (others=>'0');
else
if CNTL.cpdout_we = '1' then
R_CPDOUT <= DRES;
end if;
end if;
end if;
end process proc_cpdout;
proc_vmaddr_sel: process (R_DSRC, R_DDST, R_DTMP, GPR_PC, CNTL)
begin
case CNTL.vmaddr_sel is
when c_dpath_vmaddr_dsrc => VM_ADDR <= R_DSRC;
when c_dpath_vmaddr_ddst => VM_ADDR <= R_DDST;
when c_dpath_vmaddr_dtmp => VM_ADDR <= R_DTMP;
when c_dpath_vmaddr_pc => VM_ADDR <= GPR_PC;
when others => null;
end case;
end process proc_vmaddr_sel;
STAT.ccout_z <= CCOUT(2); -- current Z cc flag
PSWOUT <= PSW;
PCOUT <= GPR_PC;
IREG <= R_IREG;
VM_DIN <= DRES;
CP_DOUT <= R_CPDOUT;
DM_STAT_DP.pc <= GPR_PC;
DM_STAT_DP.psw <= PSW;
DM_STAT_DP.ireg <= R_IREG;
DM_STAT_DP.ireg_we <= CNTL.ireg_we;
DM_STAT_DP.dsrc <= R_DSRC;
DM_STAT_DP.ddst <= R_DDST;
DM_STAT_DP.dtmp <= R_DTMP;
DM_STAT_DP.dres <= DRES;
DM_STAT_DP.gpr_adst <= CNTL.gpr_adst;
DM_STAT_DP.gpr_mode <= CNTL.gpr_mode;
DM_STAT_DP.gpr_bytop <= CNTL.gpr_bytop;
DM_STAT_DP.gpr_we <= CNTL.gpr_we;
end syn;
| gpl-2.0 |
xylnao/w11a-extra | rtl/vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd | 2 | 2401 | -- $Id: ram_1swsr_wfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_1swsr_wfirst_gen - syn
-- Description: Single-Port RAM with with one synchronous read/write port
-- and 'read-through' semantics (as block RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
use work.memlib.all;
entity ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w port, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end ram_1swsr_wfirst_gen;
architecture syn of ram_1swsr_wfirst_gen is
begin
UMEM: ram_1swsr_xfirst_gen_unisim
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH,
WRITE_MODE => "WRITE_FIRST")
port map (
CLK => CLK,
EN => EN,
WE => WE,
ADDR => ADDR,
DI => DI,
DO => DO
);
end syn;
| gpl-2.0 |
xylnao/w11a-extra | rtl/sys_gen/tst_serloop/nexys3/sys_conf1.vhd | 2 | 1449 | -- $Id: sys_conf1.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop1_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 438 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkdiv_usecdiv : integer := 100; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_uart_cdinit : integer := 868-1; -- 100000000/115200
end package sys_conf;
| gpl-2.0 |
xylnao/w11a-extra | rtl/w11a/pdp11.vhd | 2 | 54460 | -- $Id: pdp11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: pdp11
-- Description: Definitions for pdp11 components
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.4.8 now numeric_std clean
-- 2010-12-30 351 1.4.7 rename pdp11_core_rri->pdp11_core_rbus; use rblib
-- 2010-10-23 335 1.4.6 rename RRI_LAM->RB_LAM;
-- 2010-10-16 332 1.4.5 renames of pdp11_du_drv port names
-- 2010-09-18 330 1.4.4 rename (adlm)box->(oalm)unit
-- 2010-06-20 308 1.4.3 add c_ibrb_ibf_ def's
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
-- 2010-06-18 306 1.4.1 add racc, be to cp_addr_type; rm pdp11_ibdr_rri
-- 2010-06-13 305 1.4 add rnum to cp_cntl_type, cprnum to cpustat_type;
-- reassign cp command codes and rename: c_cp_func_...
-- -> c_cpfunc_...; remove cpaddr_(lal|lah|inc) from
-- dpath_cntl_type; add cpdout_we to dpath_cntl_type;
-- reassign rbus adresses and rename: c_rb_addr_...
-- -> c_rbaddr_...; rename rbus fields: c_rb_statf_...
-- -> c_stat_rbf_...
-- 2010-06-12 304 1.3.3 add cpuwait to cp_stat_type and cpustat_type
-- 2010-06-11 303 1.3.2 use IB_MREQ.racc instead of RRI_REQ
-- 2010-05-02 287 1.3.1 rename RP_STAT->RB_STAT
-- 2010-05-01 285 1.3 port to rri V2 interface; drop pdp11_rri_2rp;
-- rename c_rp_addr_* -> c_rb_addr_*
-- 2010-03-21 270 1.2.6 add pdp11_du_drv
-- 2009-05-30 220 1.2.5 final removal of snoopers (were already commented)
-- 2009-05-10 214 1.2.4 add ENA (trace enable) for _tmu; add _pdp11_tmu_sb
-- 2009-05-09 213 1.2.3 BUGFIX: default for inst_compl now '0'
-- 2008-12-14 177 1.2.2 add gpr_* fields to DM_STAT_DP
-- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc;
-- 2008-08-22 161 1.2 move slvnn_m subtypes to slvtypes;
-- move (and rename) intbus defs to iblib package;
-- move intbus devices to ibdlib package;
-- rename ubf_ --> ibf_;
-- 2008-05-09 144 1.1.17 use EI_ACK with _kw11l, _dl11
-- 2008-05-03 143 1.1.16 rename _cpursta->_cpurust
-- 2008-04-27 140 1.1.15 add c_cpursta_xxx defs; cpufail->cpursta in cp_stat
-- 2008-04-25 138 1.1.14 add BRESET port to _mmu, _vmbox, use in _irq
-- 2008-04-19 137 1.1.13 add _tmu,_sys70 entity, dm_stat_** types and ports
-- 2008-04-18 136 1.1.12 ibdr_sdreg: use RESET; ibdr_minisys: add RESET
-- 2008-03-02 121 1.1.11 remove snoopers; add waitsusp in cpustat_type
-- 2008-02-24 119 1.1.10 add lah,rps,wps commands, cp_addr_type.
-- _vmbox,_mmu interface changed
-- 2008-02-17 117 1.1.9 add em_(mreq|sres)_type, pdp11_cache, pdp11_bram
-- 2008-01-27 115 1.1.8 add pdp11_ubmap, pdp11_mem70
-- 2008-01-26 114 1.1.7 add c_rp_addr_ibr(b) defs (for ibr addresses)
-- 2008-01-20 113 1.1.6 _core_rri: use RRI_LAM; _minisys: RRI_LAM vector
-- 2008-01-20 112 1.1.5 added ibdr_minisys; _ibdr_rri
-- 2008-01-06 111 1.1.4 rename ibdr_kw11l->ibd_kw11l; add ibdr_(dl11|rk11)
-- mod pdp11_intmap;
-- 2008-01-05 110 1.1.3 delete _mmu_regfile; rename _mmu_regs->_mmu_sadr
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- add ibdr_kw11l.
-- 2008-01-01 109 1.1.2 _vmbox w/ IB_SRES_(CPU|EXT); remove vm_regs_type
-- 2007-12-30 108 1.1.1 add ibdr_sdreg, ubf_byte[01]
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-08-16 74 1.0.6 add AP_LAM interface to pdp11_core_rri
-- 2007-08-12 73 1.0.5 add c_rp_addr_xxx and c_rp_statf_xxx def's
-- 2007-08-10 72 1.0.4 added c_cp_func_xxx constant def's for commands
-- 2007-07-15 66 1.0.3 rename pdp11_top -> pdp11_core
-- 2007-07-02 63 1.0.2 reordered ports on pdp11_top (by function, not i/o)
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.rblib.all;
package pdp11 is
type psw_type is record -- processor status
cmode : slv2; -- current mode
pmode : slv2; -- previous mode
rset : slbit; -- register set
pri : slv3; -- processor priority
tflag : slbit; -- trace flag
cc : slv4; -- condition codes (NZVC).
end record psw_type;
constant psw_init : psw_type := (
"00","00", -- cmode, pmode (=kernel)
'0',"111",'0', -- rset, pri (=7), tflag
"0000" -- cc NZVC=0
);
constant c_psw_kmode : slv2 := "00"; -- processor mode: kernel
constant c_psw_smode : slv2 := "01"; -- processor mode: supervisor
constant c_psw_umode : slv2 := "11"; -- processor mode: user
subtype psw_ibf_cmode is integer range 15 downto 14;
subtype psw_ibf_pmode is integer range 13 downto 12;
constant psw_ibf_rset: integer := 11;
subtype psw_ibf_pri is integer range 7 downto 5;
constant psw_ibf_tflag: integer := 4;
subtype psw_ibf_cc is integer range 3 downto 0;
type sarsdr_type is record -- combined SAR/SDR MMU status
saf : slv16; -- segment address field
slf : slv7; -- segment length field
ed : slbit; -- expansion direction
acf : slv3; -- access control field
end record sarsdr_type;
constant sarsdr_init : sarsdr_type := (
(others=>'0'), -- saf
"0000000",'0',"000" -- slf, ed, acf
);
type dpath_cntl_type is record -- data path control
gpr_asrc : slv3; -- src register address
gpr_adst : slv3; -- dst register address
gpr_mode : slv2; -- psw mode for gpr access
gpr_rset : slbit; -- register set
gpr_we : slbit; -- gpr write enable
gpr_bytop : slbit; -- gpr high byte enable
gpr_pcinc : slbit; -- pc increment enable
psr_ccwe : slbit; -- enable update cc
psr_we: slbit; -- write enable psw (from DIN)
psr_func : slv3; -- write function psw (from DIN)
dsrc_sel : slbit; -- src data register source select
dsrc_we : slbit; -- src data register write enable
ddst_sel : slbit; -- dst data register source select
ddst_we : slbit; -- dst data register write enable
dtmp_sel : slv2; -- tmp data register source select
dtmp_we : slbit; -- tmp data register write enable
ounit_asel : slv2; -- ounit a port selector
ounit_azero : slbit; -- ounit a port force zero
ounit_const : slv9; -- ounit b port const
ounit_bsel : slv2; -- ounit b port selector
ounit_opsub : slbit; -- ounit operation
aunit_srcmod : slv2; -- aunit src port modifier
aunit_dstmod : slv2; -- aunit dst port modifier
aunit_cimod : slv2; -- aunit ci port modifier
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
aunit_ccmode : slv3; -- aunit cc port mode
aunit_bytop : slbit; -- aunit byte operation
lunit_func : slv4; -- lunit function
lunit_bytop : slbit; -- lunit byte operation
munit_func : slv2; -- munit function
munit_s_div : slbit; -- munit s_opg_div state
munit_s_div_cn : slbit; -- munit s_opg_div_cn state
munit_s_div_cr : slbit; -- munit s_opg_div_cr state
munit_s_ash : slbit; -- munit s_opg_ash state
munit_s_ash_cn : slbit; -- munit s_opg_ash_cn state
munit_s_ashc : slbit; -- munit s_opg_ashc state
munit_s_ashc_cn : slbit; -- munit s_opg_ashc_cn state
ireg_we : slbit; -- ireg register write enable
cres_sel : slv3; -- result bus (cres) select
dres_sel : slv3; -- result bus (dres) select
vmaddr_sel : slv2; -- virtual address select
cpdout_we : slbit; -- capture dres for cpdout
end record dpath_cntl_type;
constant dpath_cntl_init : dpath_cntl_type := (
"000","000","00",'0','0','0','0', -- gpr
'0','0',"000", -- psr
'0','0','0','0',"00",'0', -- dsrc,..,dtmp
"00",'0',"000000000","00",'0', -- ounit
"00","00","00",'0',"000",'0', -- aunit
"0000",'0', -- lunit
"00",'0','0','0','0','0','0','0', -- munit
'0',"000","000","00",'0' -- rest
);
constant c_dpath_dsrc_src : slbit := '0'; -- DSRC = R(SRC)
constant c_dpath_dsrc_res : slbit := '1'; -- DSRC = DRES
constant c_dpath_ddst_dst : slbit := '0'; -- DDST = R(DST)
constant c_dpath_ddst_res : slbit := '1'; -- DDST = DRES
constant c_dpath_dtmp_dsrc : slv2 := "00"; -- DTMP = DSRC
constant c_dpath_dtmp_psw : slv2 := "01"; -- DTMP = PSW
constant c_dpath_dtmp_dres : slv2 := "10"; -- DTMP = DRES
constant c_dpath_dtmp_drese : slv2 := "11"; -- DTMP = DRESE
constant c_dpath_res_ounit : slv3 := "000"; -- D/CRES = OUNIT
constant c_dpath_res_aunit : slv3 := "001"; -- D/CRES = AUNIT
constant c_dpath_res_lunit : slv3 := "010"; -- D/CRES = LUNIT
constant c_dpath_res_munit : slv3 := "011"; -- D/CRES = MUNIT
constant c_dpath_res_vmdout : slv3 := "100"; -- D/CRES = VMDOUT
constant c_dpath_res_fpdout : slv3 := "101"; -- D/CRES = FPDOUT
constant c_dpath_res_ireg : slv3 := "110"; -- D/CRES = IREG
constant c_dpath_res_cpdin : slv3 := "111"; -- D/CRES = CPDIN
constant c_dpath_vmaddr_dsrc : slv2 := "00"; -- VMADDR = DSRC
constant c_dpath_vmaddr_ddst : slv2 := "01"; -- VMADDR = DDST
constant c_dpath_vmaddr_pc : slv2 := "10"; -- VMADDR = PC
constant c_dpath_vmaddr_dtmp : slv2 := "11"; -- VMADDR = DTMP
type dpath_stat_type is record -- data path status
ccout_z : slbit; -- current effective Z cc flag
shc_tc : slbit; -- last shc cycle (shc==0)
div_cr : slbit; -- division: reminder correction needed
div_cq : slbit; -- division: quotient correction needed
div_zero : slbit; -- division: divident or divisor zero
div_ovfl : slbit; -- division: overflow
end record dpath_stat_type;
constant dpath_stat_init : dpath_stat_type := (others=>'0');
type decode_stat_type is record -- decode status
is_dstmode0 : slbit; -- dest. is register mode
is_srcpc : slbit; -- source is pc
is_srcpcmode1 : slbit; -- source is pc and mode=1
is_dstpc : slbit; -- dest. is pc
is_dstw_reg : slbit; -- dest. register to be written
is_dstw_pc : slbit; -- pc register to be written
is_rmwop : slbit; -- read-modify-write operation
is_bytop : slbit; -- byte operation
is_res : slbit; -- reserved operation code
op_rtt : slbit; -- RTT instruction
op_mov : slbit; -- MOV instruction
trap_vec : slv3; -- trap vector addr bits 4:2
force_srcsp : slbit; -- force src register to be sp
updt_dstadsrc : slbit; -- update dsrc in dsta flow
aunit_srcmod : slv2; -- aunit src port modifier
aunit_dstmod : slv2; -- aunit dst port modifier
aunit_cimod : slv2; -- aunit ci port modifier
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
aunit_ccmode : slv3; -- aunit cc port mode
lunit_func : slv4; -- lunit function
munit_func : slv2; -- munit function
res_sel : slv3; -- result bus (cres/dres) select
fork_op : slv4; -- op fork after idecode state
fork_srcr : slv2; -- src-read fork after idecode state
fork_dstr : slv2; -- dst-read fork after src read state
fork_dsta : slv2; -- dst-addr fork after idecode state
fork_opg : slv4; -- opg fork
fork_opa : slv3; -- opa fork
do_fork_op : slbit; -- execute fork_op
do_fork_srcr : slbit; -- execute fork_srcr
do_fork_dstr : slbit; -- execute fork_dstr
do_fork_dsta : slbit; -- execute fork_dsta
do_fork_opg : slbit; -- execute fork_opg
do_pref_dec : slbit; -- can do prefetch at decode phase
end record decode_stat_type;
constant decode_stat_init : decode_stat_type := (
'0','0','0','0','0','0','0','0','0', -- is_
'0','0',"000",'0','0', -- op_, trap_, force_, updt_
"00","00","00",'0',"000", -- aunit_
"0000","00","000", -- lunit_, munit_, res_
"0000","00","00","00","0000","000", -- fork_
'0','0','0','0','0', -- do_fork_
'0' -- do_pref_
);
constant c_fork_op_halt : slv4 := "0000";
constant c_fork_op_wait : slv4 := "0001";
constant c_fork_op_rtti : slv4 := "0010";
constant c_fork_op_trap : slv4 := "0011";
constant c_fork_op_reset: slv4 := "0100";
constant c_fork_op_rts : slv4 := "0101";
constant c_fork_op_spl : slv4 := "0110";
constant c_fork_op_mcc : slv4 := "0111";
constant c_fork_op_br : slv4 := "1000";
constant c_fork_op_mark : slv4 := "1001";
constant c_fork_op_sob : slv4 := "1010";
constant c_fork_op_mtp : slv4 := "1011";
constant c_fork_srcr_def : slv2:= "00";
constant c_fork_srcr_inc : slv2:= "01";
constant c_fork_srcr_dec : slv2:= "10";
constant c_fork_srcr_ind : slv2:= "11";
constant c_fork_dstr_def : slv2:= "00";
constant c_fork_dstr_inc : slv2:= "01";
constant c_fork_dstr_dec : slv2:= "10";
constant c_fork_dstr_ind : slv2:= "11";
constant c_fork_dsta_def : slv2:= "00";
constant c_fork_dsta_inc : slv2:= "01";
constant c_fork_dsta_dec : slv2:= "10";
constant c_fork_dsta_ind : slv2:= "11";
constant c_fork_opg_gen : slv4 := "0000";
constant c_fork_opg_wdef : slv4 := "0001";
constant c_fork_opg_winc : slv4 := "0010";
constant c_fork_opg_wdec : slv4 := "0011";
constant c_fork_opg_wind : slv4 := "0100";
constant c_fork_opg_mul : slv4 := "0101";
constant c_fork_opg_div : slv4 := "0110";
constant c_fork_opg_ash : slv4 := "0111";
constant c_fork_opg_ashc : slv4 := "1000";
constant c_fork_opa_jsr : slv3 := "000";
constant c_fork_opa_jmp : slv3 := "001";
constant c_fork_opa_mtp : slv3 := "010";
constant c_fork_opa_mfp_reg : slv3 := "011";
constant c_fork_opa_mfp_mem : slv3 := "100";
-- Note: MSB=0 are 'normal' states, MSB=1 are fatal errors
constant c_cpurust_init : slv4 := "0000"; -- cpu in init state
constant c_cpurust_halt : slv4 := "0001"; -- cpu executed HALT
constant c_cpurust_reset : slv4 := "0010"; -- cpu was reset
constant c_cpurust_stop : slv4 := "0011"; -- cpu was stopped
constant c_cpurust_step : slv4 := "0100"; -- cpu was stepped
constant c_cpurust_susp : slv4 := "0101"; -- cpu was suspended
constant c_cpurust_runs : slv4 := "0111"; -- cpu running
constant c_cpurust_vecfet : slv4 := "1000"; -- vector fetch error halt
constant c_cpurust_recrsv : slv4 := "1001"; -- recursive red-stack halt
constant c_cpurust_sfail : slv4 := "1100"; -- sequencer failure
constant c_cpurust_vfail : slv4 := "1101"; -- vmbox failure
type cpustat_type is record -- CPU status
cmdbusy : slbit; -- command busy
cmdack : slbit; -- command acknowledge
cmderr : slbit; -- command error
cmdmerr : slbit; -- command memory access error
cpugo : slbit; -- CPU go state
cpustep : slbit; -- CPU step flag
cpuhalt : slbit; -- CPU halt flag
cpuwait : slbit; -- CPU wait flag
cpurust : slv4; -- CPU run status
cpfunc : slv5; -- current control port function
cprnum : slv3; -- current control port register number
waitsusp : slbit; -- WAIT instruction suspended
intvect : slv9_2; -- current interrupt vector
trap_mmu : slbit; -- mmu trace trap pending
trap_ysv : slbit; -- ysv trap pending
prefdone : slbit; -- prefetch done
do_gprwe : slbit; -- pending gpr_we
do_intrsv : slbit; -- active rsv interrupt sequence
end record cpustat_type;
constant cpustat_init : cpustat_type := (
'0','0','0','0', -- cmd..
'0','0','0','0', -- cpu..
c_cpurust_init, -- cpurust
"00000","000", -- cpfunc, cprnum
'0', -- waitsusp
(others=>'0'), -- intvect
'0','0','0', -- trap_(mmu|ysv), prefdone
'0','0' -- do_gprwe, do_intrsv
);
type cpuerr_type is record -- CPU error register
illhlt : slbit; -- illegal halt (in non-kernel mode)
adderr : slbit; -- address error (odd, jmp/jsr reg)
nxm : slbit; -- non-existent memory
iobto : slbit; -- I/O bus timeout (non-exist UB)
ysv : slbit; -- yellow stack violation
rsv : slbit; -- red stack violation
end record cpuerr_type;
constant cpuerr_init : cpuerr_type := (others=>'0');
type vm_cntl_type is record -- virt memory control port
req : slbit; -- request
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access
bytop : slbit; -- byte operation
dspace : slbit; -- dspace operation
kstack : slbit; -- access through kernel stack
intrsv : slbit; -- active rsv interrupt sequence
mode : slv2; -- mode
trap_done : slbit; -- mmu trap taken (to set ssr0 bit)
end record vm_cntl_type;
constant vm_cntl_init : vm_cntl_type := (
'0','0','0','0', -- req, wacc, macc,cacc
'0','0','0', -- bytop, dspace, kstack
'0',"00",'0' -- intrsv, mode, trap_done
);
type vm_stat_type is record -- virt memory status port
ack : slbit; -- acknowledge
err : slbit; -- error (see err_xxx for reason)
fail : slbit; -- failure (machine check)
err_odd : slbit; -- abort: odd address error
err_mmu : slbit; -- abort: mmu reject
err_nxm : slbit; -- abort: non-existing memory
err_iobto : slbit; -- abort: non-existing I/O resource
err_rsv : slbit; -- abort: red stack violation
trap_ysv : slbit; -- trap: yellow stack violation
trap_mmu : slbit; -- trap: mmu trace trap
end record vm_stat_type;
constant vm_stat_init : vm_stat_type := (others=>'0');
type em_mreq_type is record -- external memory - master request
req : slbit; -- request
we : slbit; -- write enable
be : slv2; -- byte enables
cancel : slbit; -- cancel request
addr : slv22_1; -- address
din : slv16; -- data in (input to memory)
end record em_mreq_type;
constant em_mreq_init : em_mreq_type := (
'0','0',"00",'0', -- req, we, be, cancel
(others=>'0'),(others=>'0') -- addr, din
);
type em_sres_type is record -- external memory - slave response
ack_r : slbit; -- acknowledge read
ack_w : slbit; -- acknowledge write
dout : slv16; -- data out (output from memory)
end record em_sres_type;
constant em_sres_init : em_sres_type := (
'0','0', -- ack_r, ack_w
(others=>'0') -- dout
);
type mmu_cntl_type is record -- mmu control port
req : slbit; -- translate request
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access (bypass mmu)
dspace : slbit; -- dspace access
mode : slv2; -- processor mode
trap_done : slbit; -- mmu trap taken (set ssr0 bit)
end record mmu_cntl_type;
constant mmu_cntl_init : mmu_cntl_type := (
'0','0','0','0', -- req, wacc, macc, cacc
'0',"00",'0' -- dspace, mode, trap_done
);
type mmu_stat_type is record -- mmu status port
vaok : slbit; -- virtual address valid
trap : slbit; -- mmu trap request
ena_mmu : slbit; -- mmu enable (ssr0 bit 0)
ena_22bit : slbit; -- mmu in 22 bit mode (ssr3 bit 4)
ena_ubmap : slbit; -- ubmap enable (ssr3 bit 5)
end record mmu_stat_type;
constant mmu_stat_init : mmu_stat_type := (others=>'0');
type mmu_moni_type is record -- mmu monitor port
istart : slbit; -- instruction start
idone : slbit; -- instruction done
pc : slv16; -- PC of new instruction
regmod : slbit; -- register modified
regnum : slv3; -- register number
delta : slv4; -- register offset
isdec : slbit; -- offset to be subtracted
trace_prev : slbit; -- use ssr12 trace state of prev. state
end record mmu_moni_type;
constant mmu_moni_init : mmu_moni_type := (
'0','0',(others=>'0'), -- istart, idone, pc
'0',"000","0000", -- regmod, regnum, delta
'0','0' -- isdec, trace_prev
);
type mmu_ssr0_type is record -- MMU ssr0
abo_nonres : slbit; -- abort non resident
abo_length : slbit; -- abort segment length
abo_rdonly : slbit; -- abort read-only
trap_mmu : slbit; -- trap management
ena_trap : slbit; -- enable traps
inst_compl : slbit; -- instruction complete
seg_mode : slv2; -- segement mode
dspace : slbit; -- address space (D=1, I=0)
seg_num : slv3; -- segment number
ena_mmu : slbit; -- enable memory management
trace_prev : slbit; -- ssr12 trace status in prev. state
end record mmu_ssr0_type;
constant mmu_ssr0_init : mmu_ssr0_type := (
inst_compl=>'0', seg_mode=>"00", seg_num=>"000",
others=>'0'
);
type mmu_ssr1_type is record -- MMU ssr1
rb_delta : slv5; -- RB: amount change
rb_num : slv3; -- RB: register number
ra_delta : slv5; -- RA: amount change
ra_num : slv3; -- RA: register number
end record mmu_ssr1_type;
constant mmu_ssr1_init : mmu_ssr1_type := (
"00000","000", -- rb_...
"00000","000" -- ra_...
);
type mmu_ssr3_type is record -- MMU ssr3
ena_ubmap : slbit; -- enable unibus mapping
ena_22bit : slbit; -- enable 22 bit mapping
dspace_km : slbit; -- enable dspace kernel
dspace_sm : slbit; -- enable dspace supervisor
dspace_um : slbit; -- enable dspace user
end record mmu_ssr3_type;
constant mmu_ssr3_init : mmu_ssr3_type := (others=>'0');
-- control port definitions --------------------------------------------------
type cp_cntl_type is record -- control port control
req : slbit; -- request
func : slv5; -- function
rnum : slv3; -- register number
end record cp_cntl_type;
constant c_cpfunc_noop : slv5 := "00000"; -- noop : no operation
constant c_cpfunc_sta : slv5 := "00001"; -- sta : cpu start
constant c_cpfunc_sto : slv5 := "00010"; -- sto : cpu stop
constant c_cpfunc_cont : slv5 := "00011"; -- cont : cpu continue
constant c_cpfunc_step : slv5 := "00100"; -- step : cpu step
constant c_cpfunc_rst : slv5 := "01111"; -- rst : cpu reset (soft)
constant c_cpfunc_rreg : slv5 := "10000"; -- rreg : read register
constant c_cpfunc_wreg : slv5 := "10001"; -- wreg : write register
constant c_cpfunc_rpsw : slv5 := "10010"; -- rpsw : read psw
constant c_cpfunc_wpsw : slv5 := "10011"; -- wpsw : write psw
constant c_cpfunc_rmem : slv5 := "10100"; -- rmem : read memory
constant c_cpfunc_wmem : slv5 := "10101"; -- wmem : write memory
constant cp_cntl_init : cp_cntl_type := ('0',c_cpfunc_noop,"000");
type cp_stat_type is record -- control port status
cmdbusy : slbit; -- command busy
cmdack : slbit; -- command acknowledge
cmderr : slbit; -- command error
cmdmerr : slbit; -- command memory access error
cpugo : slbit; -- CPU go state
cpustep : slbit; -- CPU step flag
cpuhalt : slbit; -- CPU halt flag
cpuwait : slbit; -- CPU wait flag
cpurust : slv4; -- CPU run status
end record cp_stat_type;
constant cp_stat_init : cp_stat_type := (
'0','0','0','0', -- cmd...
'0','0','0','0', -- cpu...
(others=>'0') -- cpurust
);
type cp_addr_type is record -- control port address
addr : slv22_1; -- address
racc : slbit; -- ibr access
be : slv2; -- byte enables
ena_22bit : slbit; -- enable 22 bit mode
ena_ubmap : slbit; -- enable unibus mapper
end record cp_addr_type;
constant cp_addr_init : cp_addr_type := (
(others=>'0'), -- addr
'0',"00", -- racc, be
'0','0' -- ena_...
);
-- debug and monitoring port definitions -------------------------------------
type dm_cntl_type is record -- debug and monitor control
dum1 : slbit; -- dummy 1
dum2 : slbit; -- dummy 2
end record dm_cntl_type;
constant dm_cntl_init : dm_cntl_type := (others=>'0');
type dm_stat_dp_type is record -- debug and monitor status - dpath
pc : slv16; -- pc
psw : psw_type; -- psw
ireg : slv16; -- ireg
ireg_we : slbit; -- ireg we
dsrc : slv16; -- dsrc register
ddst : slv16; -- ddst register
dtmp : slv16; -- dtmp register
dres : slv16; -- dres bus
gpr_adst : slv3; -- gpr dst regsiter
gpr_mode : slv2; -- gpr mode
gpr_bytop : slbit; -- gpr bytop
gpr_we : slbit; -- gpr we
end record dm_stat_dp_type;
constant dm_stat_dp_init : dm_stat_dp_type := (
(others=>'0'), -- pc
psw_init, -- psw
(others=>'0'),'0', -- ireg, ireg_we
(others=>'0'),(others=>'0'), -- dsrc, ddst
(others=>'0'),(others=>'0'), -- dtmp, dres
(others=>'0'),(others=>'0'), -- gpr_adst, gpr_mode
'0','0' -- gpr_bytop, gpr_we
);
type dm_stat_vm_type is record -- debug and monitor status - vmbox
ibmreq : ib_mreq_type; -- ibus master request
ibsres : ib_sres_type; -- ibus slave response
end record dm_stat_vm_type;
constant dm_stat_vm_init : dm_stat_vm_type := (ib_mreq_init,ib_sres_init);
type dm_stat_co_type is record -- debug and monitor status - core
cpugo : slbit; -- cpugo state flag
cpuhalt : slbit; -- cpuhalt state flag
end record dm_stat_co_type;
constant dm_stat_co_init : dm_stat_co_type := ('0','0');
type dm_stat_sy_type is record -- debug and monitor status - system
emmreq : em_mreq_type; -- external memory: request
emsres : em_sres_type; -- external memory: response
chit : slbit; -- cache hit
end record dm_stat_sy_type;
constant dm_stat_sy_init : dm_stat_sy_type := (em_mreq_init,em_sres_init,'0');
-- rbus interface definitions ------------------------------------------------
constant c_rbaddr_conf : slv5 := "00000"; -- R/W configuration reg
constant c_rbaddr_cntl : slv5 := "00001"; -- -/F control reg
constant c_rbaddr_stat : slv5 := "00010"; -- R/- status reg
constant c_rbaddr_psw : slv5 := "00011"; -- R/W psw access
constant c_rbaddr_al : slv5 := "00100"; -- R/W address low reg
constant c_rbaddr_ah : slv5 := "00101"; -- R/W address high reg
constant c_rbaddr_mem : slv5 := "00110"; -- R/W memory access
constant c_rbaddr_memi : slv5 := "00111"; -- R/W memory access; inc addr
constant c_rbaddr_r0 : slv5 := "01000"; -- R/W gpr 0
constant c_rbaddr_r1 : slv5 := "01001"; -- R/W gpr 1
constant c_rbaddr_r2 : slv5 := "01010"; -- R/W gpr 2
constant c_rbaddr_r3 : slv5 := "01011"; -- R/W gpr 3
constant c_rbaddr_r4 : slv5 := "01100"; -- R/W gpr 4
constant c_rbaddr_r5 : slv5 := "01101"; -- R/W gpr 5
constant c_rbaddr_sp : slv5 := "01110"; -- R/W gpr 6 (sp)
constant c_rbaddr_pc : slv5 := "01111"; -- R/W gpr 7 (pc)
constant c_rbaddr_ibrb : slv5 := "10000"; -- R/W ibr base address
subtype c_al_rbf_addr is integer range 15 downto 1; -- al: address
constant c_ah_rbf_ena_ubmap: integer := 7; -- ah: ubmap
constant c_ah_rbf_ena_22bit: integer := 6; -- ah: 22bit
subtype c_ah_rbf_addr is integer range 5 downto 0; -- ah: address
constant c_stat_rbf_cmderr: integer := 0; -- stat field: cmderr
constant c_stat_rbf_cmdmerr: integer := 1; -- stat field: cmdmerr
constant c_stat_rbf_cpugo: integer := 2; -- stat field: cpugo
constant c_stat_rbf_cpuhalt: integer := 3; -- stat field: cpuhalt
subtype c_stat_rbf_cpurust is integer range 7 downto 4; -- cpurust
subtype c_ibrb_ibf_base is integer range 12 downto 6; -- ibrb: base addr
subtype c_ibrb_ibf_be is integer range 1 downto 0; -- ibrb: be's
-- -------------------------------------
component pdp11_gpr is -- general purpose registers
port (
CLK : in slbit; -- clock
DIN : in slv16; -- input data
ASRC : in slv3; -- source register number
ADST : in slv3; -- destination register number
MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
RSET : in slbit; -- register set
WE : in slbit; -- write enable
BYTOP : in slbit; -- byte operation (write low byte only)
PCINC : in slbit; -- increment PC
DSRC : out slv16; -- source register data
DDST : out slv16; -- destination register data
PC : out slv16 -- current PC value
);
end component;
constant c_gpr_r5 : slv3 := "101"; -- register number of r5
constant c_gpr_sp : slv3 := "110"; -- register number of SP
constant c_gpr_pc : slv3 := "111"; -- register number of PC
component pdp11_psr is -- processor status word register
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
DIN : in slv16; -- input data
CCIN : in slv4; -- cc input
CCWE : in slbit; -- enable update cc
WE : in slbit; -- write enable (from DIN)
FUNC : in slv3; -- write function (from DIN)
PSW : out psw_type; -- current psw
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
constant c_psr_func_wspl : slv3 := "000"; -- SPL mode: set pri
constant c_psr_func_wcc : slv3 := "001"; -- CC mode: set/clear cc
constant c_psr_func_wint : slv3 := "010"; -- interupt mode: pmode=cmode
constant c_psr_func_wrti : slv3 := "011"; -- rti mode: protect modes
constant c_psr_func_wall : slv3 := "100"; -- write all fields
component pdp11_ounit is -- offset adder for addresses (ounit)
port (
DSRC : in slv16; -- 'src' data for port A
DDST : in slv16; -- 'dst' data for port A
DTMP : in slv16; -- 'tmp' data for port A
PC : in slv16; -- PC data for port A
ASEL : in slv2; -- selector for port A
AZERO : in slbit; -- force zero for port A
IREG8 : in slv8; -- 'ireg' data for port B
VMDOUT : in slv16; -- virt. memory data for port B
CONST : in slv9; -- sequencer const data for port B
BSEL : in slv2; -- selector for port B
OPSUB : in slbit; -- operation: 0 add, 1 sub
DOUT : out slv16; -- data output
NZOUT : out slv2 -- NZ condition codes out
);
end component;
constant c_ounit_asel_ddst : slv2 := "00"; -- A = DDST
constant c_ounit_asel_dsrc : slv2 := "01"; -- A = DSRC
constant c_ounit_asel_pc : slv2 := "10"; -- A = PC
constant c_ounit_asel_dtmp : slv2 := "11"; -- A = DTMP
constant c_ounit_bsel_const : slv2 := "00"; -- B = CONST
constant c_ounit_bsel_vmdout : slv2 := "01"; -- B = VMDOUT
constant c_ounit_bsel_ireg6 : slv2 := "10"; -- B = 2*IREG(6bit)
constant c_ounit_bsel_ireg8 : slv2 := "11"; -- B = 2*IREG(8bit,sign-extend)
component pdp11_aunit is -- arithmetic unit for data (aunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CI : in slbit; -- carry flag in
SRCMOD : in slv2; -- src modifier mode
DSTMOD : in slv2; -- dst modifier mode
CIMOD : in slv2; -- ci modifier mode
CC1OP : in slbit; -- use cc modes (1 op instruction)
CCMODE : in slv3; -- cc mode
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_aunit_mod_pass : slv2 := "00"; -- pass data
constant c_aunit_mod_inv : slv2 := "01"; -- invert data
constant c_aunit_mod_zero : slv2 := "10"; -- set to 0
constant c_aunit_mod_one : slv2 := "11"; -- set to 1
-- the c_aunit_ccmode codes follow exactly the opcode format (bit 8:6)
constant c_aunit_ccmode_clr : slv3 := "000"; -- do clr instruction
constant c_aunit_ccmode_com : slv3 := "001"; -- do com instruction
constant c_aunit_ccmode_inc : slv3 := "010"; -- do inc instruction
constant c_aunit_ccmode_dec : slv3 := "011"; -- do dec instruction
constant c_aunit_ccmode_neg : slv3 := "100"; -- do neg instruction
constant c_aunit_ccmode_adc : slv3 := "101"; -- do adc instruction
constant c_aunit_ccmode_sbc : slv3 := "110"; -- do sbc instruction
constant c_aunit_ccmode_tst : slv3 := "111"; -- do tst instruction
component pdp11_lunit is -- logic unit for data (lunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CCIN : in slv4; -- condition codes in
FUNC : in slv4; -- function
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_lunit_func_asr : slv4 := "0000"; -- ASR/ASRB ??? recheck coding !!
constant c_lunit_func_asl : slv4 := "0001"; -- ASL/ASLB
constant c_lunit_func_ror : slv4 := "0010"; -- ROR/RORB
constant c_lunit_func_rol : slv4 := "0011"; -- ROL/ROLB
constant c_lunit_func_bis : slv4 := "0100"; -- BIS/BISB
constant c_lunit_func_bic : slv4 := "0101"; -- BIC/BICB
constant c_lunit_func_bit : slv4 := "0110"; -- BIT/BITB
constant c_lunit_func_mov : slv4 := "0111"; -- MOV/MOVB
constant c_lunit_func_sxt : slv4 := "1000"; -- SXT
constant c_lunit_func_swap : slv4 := "1001"; -- SWAB
constant c_lunit_func_xor : slv4 := "1010"; -- XOR
component pdp11_munit is -- mul/div unit for data (munit)
port (
CLK : in slbit; -- clock
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
DTMP : in slv16; -- 'tmp' data in
GPR_DSRC : in slv16; -- 'src' data from GPR
FUNC : in slv2; -- function
S_DIV : in slbit; -- s_opg_div state
S_DIV_CN : in slbit; -- s_opg_div_cn state
S_DIV_CR : in slbit; -- s_opg_div_cr state
S_ASH : in slbit; -- s_opg_ash state
S_ASH_CN : in slbit; -- s_opg_ash_cn state
S_ASHC : in slbit; -- s_opg_ashc state
S_ASHC_CN : in slbit; -- s_opg_ashc_cn state
SHC_TC : out slbit; -- last shc cycle (shc==0)
DIV_CR : out slbit; -- division: reminder correction needed
DIV_CQ : out slbit; -- division: quotient correction needed
DIV_ZERO : out slbit; -- division: divident or divisor zero
DIV_OVFL : out slbit; -- division: overflow
DOUT : out slv16; -- data output
DOUTE : out slv16; -- data output extra
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_munit_func_mul : slv2 := "00"; -- MUL
constant c_munit_func_div : slv2 := "01"; -- DIV
constant c_munit_func_ash : slv2 := "10"; -- ASH
constant c_munit_func_ashc : slv2 := "11"; -- ASHC
component pdp11_mmu_sadr is -- mmu SAR/SDR register set
port (
CLK : in slbit; -- clock
MODE : in slv2; -- mode
ASN : in slv4; -- augmented segment number (1+3 bit)
AIB_WE : in slbit; -- update AIB
AIB_SETA : in slbit; -- set access AIB
AIB_SETW : in slbit; -- set write AIB
SARSDR : out sarsdr_type; -- combined SAR/SDR
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
TRACE : in slbit; -- trace enable
MONI : in mmu_moni_type; -- MMU monitor port data
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mmu is -- mmu - memory management unit
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CNTL : in mmu_cntl_type; -- control port
VADDR : in slv16; -- virtual address
MONI : in mmu_moni_type; -- monitor port
STAT : out mmu_stat_type; -- status port
PADDRH : out slv16; -- physical address (upper 16 bit)
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_vmbox is -- virtual memory
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
CRESET : in slbit; -- console reset
BRESET : in slbit; -- ibus reset
CP_ADDR : in cp_addr_type; -- console port address
VM_CNTL : in vm_cntl_type; -- vm control port
VM_ADDR : in slv16; -- vm address
VM_DIN : in slv16; -- vm data in
VM_STAT : out vm_stat_type; -- vm status port
VM_DOUT : out slv16; -- vm data out
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
MMU_MONI : in mmu_moni_type; -- mmu monitor port
IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
);
end component;
component pdp11_dpath is -- CPU datapath
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
CNTL : in dpath_cntl_type; -- control interface
STAT : out dpath_stat_type; -- status interface
CP_DIN : in slv16; -- console port data in
CP_DOUT : out slv16; -- console port data out
PSWOUT : out psw_type; -- current psw
PCOUT : out slv16; -- current pc
IREG : out slv16; -- ireg out
VM_ADDR : out slv16; -- virt. memory address
VM_DOUT : in slv16; -- virt. memory data out
VM_DIN : out slv16; -- virt. memory data in
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status
);
end component;
component pdp11_decode is -- instruction decoder
port (
IREG : in slv16; -- input instruction word
STAT : out decode_stat_type -- status output
);
end component;
component pdp11_sequencer is -- cpu sequencer
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
PSW : in psw_type; -- processor status
PC : in slv16; -- program counter
IREG : in slv16; -- IREG
ID_STAT : in decode_stat_type; -- instr. decoder status
DP_STAT : in dpath_stat_type; -- data path status
CP_CNTL : in cp_cntl_type; -- console port control
VM_STAT : in vm_stat_type; -- virtual memory status port
INT_PRI : in slv3; -- interrupt priority
INT_VECT : in slv9_2; -- interrupt vector
CRESET : out slbit; -- console reset
BRESET : out slbit; -- ibus reset
MMU_MONI : out mmu_moni_type; -- mmu monitor port
DP_CNTL : out dpath_cntl_type; -- data path control
VM_CNTL : out vm_cntl_type; -- virtual memory control port
CP_STAT : out cp_stat_type; -- console port status
INT_ACK : out slbit; -- interrupt acknowledge
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_irq is -- interrupt requester
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- ibus reset
INT_ACK : in slbit; -- interrupt acknowledge from CPU
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
PRI : out slv3; -- interrupt priority
VECT : out slv9_2; -- interrupt vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_ubmap is -- 11/70 unibus mapper
port (
CLK : in slbit; -- clock
MREQ : in slbit; -- request mapping
ADDR_UB : in slv18_1; -- UNIBUS address (in)
ADDR_PM : out slv22_1; -- physical memory address (out)
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_sys70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mem70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
HM_ENA : in slbit; -- hit/miss enable
HM_VAL : in slbit; -- hit/miss value
CACHE_FMISS : out slbit; -- cache force miss
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_cache is -- cache
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type; -- em response
FMISS : in slbit; -- force miss
CHIT : out slbit; -- cache hit flag
MEM_REQ : out slbit; -- memory: request
MEM_WE : out slbit; -- memory: write enable
MEM_BUSY : in slbit; -- memory: controller busy
MEM_ACK_R : in slbit; -- memory: acknowledge read
MEM_ADDR : out slv20; -- memory: address
MEM_BE : out slv4; -- memory: byte enable
MEM_DI : out slv32; -- memory: data in (memory view)
MEM_DO : in slv32 -- memory: data out (memory view)
);
end component;
component pdp11_core is -- full processor core
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CP_CNTL : in cp_cntl_type; -- console control port
CP_ADDR : in cp_addr_type; -- console address port
CP_DIN : in slv16; -- console data in
CP_STAT : out cp_stat_type; -- console status port
CP_DOUT : out slv16; -- console data out
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
BRESET : out slbit; -- ibus reset
IB_MREQ_M : out ib_mreq_type; -- ibus master request (master)
IB_SRES_M : in ib_sres_type; -- ibus slave response (master)
DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core
);
end component;
component pdp11_tmu is -- trace and monitor unit
port (
CLK : in slbit; -- clock
ENA : in slbit := '0'; -- enable trace output
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
DM_STAT_CO : in dm_stat_co_type; -- DM core
DM_STAT_SY : in dm_stat_sy_type -- DM system
);
end component;
component pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper
generic (
ENAPIN : integer := 13); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
DM_STAT_CO : in dm_stat_co_type; -- DM core
DM_STAT_SY : in dm_stat_sy_type -- DM system
);
end component;
component pdp11_du_drv is -- display unit low level driver
generic (
CDWIDTH : positive := 3); -- clock divider width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
ROW0 : in slv22; -- led row 0 (22 leds, top)
ROW1 : in slv16; -- led row 1 (16 leds)
ROW2 : in slv16; -- led row 2 (16 leds)
ROW3 : in slv10; -- led row 3 (10 leds, bottom)
SWOPT : out slv8; -- option pattern from du
SWOPT_RDY : out slbit; -- marks update of swopt
DU_SCLK : out slbit; -- DU: sclk
DU_SS_N : out slbit; -- DU: ss_n
DU_MOSI : out slbit; -- DU: mosi (master out, slave in)
DU_MISO : in slbit -- DU: miso (master in, slave out)
);
end component;
component pdp11_bram is -- BRAM based ext. memory dummy
generic (
AWIDTH : positive := 14); -- address width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type -- em response
);
end component;
component pdp11_core_rbus is -- core to rbus interface
generic (
RB_ADDR_CORE : slv8 := slv(to_unsigned(2#00000000#,8));
RB_ADDR_IBUS : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_STAT : out slv3; -- rbus: status flags
RB_LAM : out slbit; -- remote attention
CPU_RESET : out slbit; -- cpu master reset
CP_CNTL : out cp_cntl_type; -- console control port
CP_ADDR : out cp_addr_type; -- console address port
CP_DIN : out slv16; -- console data in
CP_STAT : in cp_stat_type; -- console status port
CP_DOUT : in slv16 -- console data out
);
end component;
-- ----- move later to pdp11_conf --------------------------------------------
constant conf_vect_pirq : integer := 8#240#;
constant conf_pri_pirq_1 : integer := 1;
constant conf_pri_pirq_2 : integer := 2;
constant conf_pri_pirq_3 : integer := 3;
constant conf_pri_pirq_4 : integer := 4;
constant conf_pri_pirq_5 : integer := 5;
constant conf_pri_pirq_6 : integer := 6;
constant conf_pri_pirq_7 : integer := 7;
end package pdp11;
| gpl-2.0 |
xylnao/w11a-extra | rtl/bplib/bpgen/sn_humanio.vhd | 1 | 4353 | -- $Id: sn_humanio.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio - syn
-- Description: All BTN, SWI, LED and DSP handling for s3board, nexys2/3
--
-- Dependencies: xlib/iob_reg_o_gen
-- bpgen/bp_swibtnled
-- bpgen/sn_4x7segctl
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-17 409 13.1 O40d xc3s1000-4 49 86 0 53 s 5.3 ns
-- 2011-07-02 387 12.1 M53d xc3s1000-4 48 87 0 53 s 5.1 ns
-- 2010-04-10 275 11.4 L68 xc3s1000-4 48 87 0 53 s 5.2 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-30 400 1.2.1 use CDWIDTH=7 for sn_4x7segctl (for 100 MHz)
-- 2011-07-08 390 1.2 renamed from s3_humanio, add BWIDTH generic
-- 2011-07-02 387 1.1.2 use bp_swibtnled
-- 2010-04-17 278 1.1.1 rename dispdrv -> s3_dispdrv
-- 2010-04-11 276 1.1 instantiate BTN/SWI debouncers via DEBOUNCE generic
-- 2010-04-10 275 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio is -- human i/o handling: swi,btn,led,dsp
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end sn_humanio;
architecture syn of sn_humanio is
signal N_ANO_N : slv4 := (others=>'0');
signal N_SEG_N : slv8 := (others=>'0');
begin
IOB_ANO_N : iob_reg_o_gen
generic map (DWIDTH => 4)
port map (CLK => CLK, CE => '1', DO => N_ANO_N, PAD => O_ANO_N);
IOB_SEG_N : iob_reg_o_gen
generic map (DWIDTH => 8)
port map (CLK => CLK, CE => '1', DO => N_SEG_N, PAD => O_SEG_N);
HIO : bp_swibtnled
generic map (
SWIDTH => SWIDTH,
BWIDTH => BWIDTH,
LWIDTH => LWIDTH,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
DRV : sn_4x7segctl
generic map (
CDWIDTH => 7) -- 7 good for 100 MHz on nexys2
port map (
CLK => CLK,
DIN => DSP_DAT,
DP => DSP_DP,
ANO_N => N_ANO_N,
SEG_N => N_SEG_N
);
end syn;
| gpl-2.0 |
xylnao/w11a-extra | rtl/vlib/xlib/iob_reg_o.vhd | 2 | 1857 | -- $Id: iob_reg_o.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_i - syn
-- Description: Registered IOB, output only
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-16 101 1.0.1 add INIT generic port
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_o is -- registered IOB, output
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO : in slbit; -- output data
PAD : out slbit -- i/o pad
);
end iob_reg_o;
architecture syn of iob_reg_o is
begin
IOB : iob_reg_o_gen
generic map (
DWIDTH => 1,
INIT => INIT)
port map (
CLK => CLK,
CE => CE,
DO(0) => DO,
PAD(0) => PAD
);
end syn;
| gpl-2.0 |
a4a881d4/zcpsm | src/example/eth_hub/vhd/g_eth/g_ethtx_output.vhd | 1 | 19068 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity g_ethtx_output is
generic(
HEAD_AWIDTH : natural := 5;
BUFF_AWIDTH : natural := 16;
RAM_AWIDTH : natural := 32
);
port(
clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(7 downto 0);
txen : out std_logic;
tx_queue_empty : in std_logic;
tx_head_raddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0);
tx_head_rdata : in std_logic_vector(7 downto 0);
tx_head_rd_block : out std_logic;
db_queue_empty : in std_logic;
db_head_raddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0);
db_head_rdata : in std_logic_vector(7 downto 0);
db_head_rd_block : out std_logic;
buff_raddr : out std_logic_vector(BUFF_AWIDTH - 1 downto 0);
buff_rdata : in std_logic_vector(31 downto 0);
dma_start : out std_logic;
dma_start_addr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
dma_length : out std_logic_vector(15 downto 0);
dma_step : out std_logic_vector(7 downto 0);
localtime : in std_logic_vector(31 downto 0)
);
end g_ethtx_output;
architecture arch_ethtx_output of g_ethtx_output is
component crc8_blkrom
port(
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(31 downto 0));
end component;
component fifo_async_almost_full
generic(
DEPTH : NATURAL;
AWIDTH : NATURAL;
DWIDTH : NATURAL;
RAM_TYPE : STRING);
port(
reset : in std_logic;
clr : in std_logic;
clka : in std_logic;
wea : in std_logic;
dia : in std_logic_vector((DWIDTH-1) downto 0);
clkb : in std_logic;
rdb : in std_logic;
dob : out std_logic_vector((DWIDTH-1) downto 0);
empty : out std_logic;
almost_full : out std_logic;
full : out std_logic;
dn : out std_logic_vector((AWIDTH-1) downto 0));
end component;
for all: fifo_async_almost_full use entity WORK.fifo_async_almost_full(fast_write);
component shiftreg
generic(
width : INTEGER;
depth : INTEGER);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector((width-1) downto 0);
Q : out std_logic_vector((width-1) downto 0);
S : out std_logic_vector((width-1) downto 0));
end component;
component ASYNCWRITE
port(
reset: in std_logic;
async_clk: in std_logic;
sync_clk: in std_logic;
async_wren: in std_logic;
trigger: in std_logic;
sync_wren: out std_logic;
over: out std_logic;
flag: out std_logic
);
end component;
constant INFO_LENGTH : natural := 8;
signal ce : std_logic;
signal ce_d1 : std_logic;
signal ce_ext : std_logic;
signal ce_ext_d1 : std_logic;
signal ce_ext_d2 : std_logic;
signal txd_buf : std_logic_vector(7 downto 0);
signal txen_buf : std_logic;
signal txd_buf_d1 : std_logic_vector(7 downto 0);
signal txen_buf_d1 : std_logic;
signal TxFIFO_clr : std_logic;
signal TxFIFO_wea : std_logic;
signal TxFIFO_dia : std_logic_vector(31 downto 0);
signal TxFIFO_rdb : std_logic;
signal TxFIFO_rdb_d1 : std_logic;
signal TxFIFO_dob : std_logic_vector(31 downto 0);
signal TxFIFO_almost_full : std_logic;
signal TxFIFO_empty : std_logic;
signal TxFIFO_DN : std_logic_vector(3 downto 0);
signal busy : std_logic;
signal byte_cnt : std_logic_vector(11 downto 0);
signal byte_cnt_d1 : std_logic_vector(11 downto 0);
signal byte_cnt_ext : std_logic_vector(11 downto 0);
signal byte_cnt_ext_d1 : std_logic_vector(11 downto 0);
signal byte_cnt_ext_d2 : std_logic_vector(11 downto 0);
signal head_length : std_logic_vector(7 downto 0);
signal data_length : std_logic_vector(10 downto 0);
signal source_select : std_logic;
signal head_rd_block : std_logic;
signal info_ena : std_logic;
signal info_ena_d1 : std_logic;
signal info_cnt : integer range 0 to INFO_LENGTH;
signal info_cnt_d1 : integer range 0 to INFO_LENGTH;
signal data_ena : std_logic;
signal data_ena_d8 : std_logic;
signal data_ena_ext : std_logic;
signal data_ena_ext_d1 : std_logic;
signal data_ena_ext_d2 : std_logic;
signal data_ena_ext_d6 : std_logic;
signal data_ena_ext_d8 : std_logic;
signal data_ena_ext_d12 : std_logic;
signal data_ena_ext_d13 : std_logic;
signal head_ena : std_logic;
signal head_ena_d1 : std_logic;
signal buff_ena : std_logic;
signal buff_ena_d1 : std_logic;
signal info_start : std_logic;
signal data_start : std_logic;
signal data_start_ext : std_logic;
signal data_start_ext_wren : std_logic;
signal dword_data_int : std_logic_vector(31 downto 0);
signal dword_data_ext : std_logic_vector(31 downto 0);
signal byte_data : std_logic_vector(7 downto 0);
signal byte_data_buf : std_logic_vector(31 downto 0);
signal byte_data_dly : std_logic_vector(7 downto 0);
signal head_rden : std_logic;
signal head_rdata : std_logic_vector(7 downto 0);
signal head_rdata_buf : std_logic_vector(23 downto 0);
signal head_raddr_buf : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal buff_rden : std_logic;
signal buff_rden_d1 : std_logic;
signal buff_raddr_buf : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal buff_rdata_buf : std_logic_vector(31 downto 0);
signal crc_din : std_logic_vector(7 downto 0);
signal crc_reg : std_logic_vector(31 downto 0);
signal crc_reg_d1 : std_logic_vector(31 downto 0);
signal crcrom_addr : std_logic_vector(7 downto 0);
signal crcrom_dout : std_logic_vector(31 downto 0);
signal v0 : std_logic_vector(0 downto 0);
signal v1 : std_logic_vector(0 downto 0);
signal v2 : std_logic_vector(0 downto 0);
signal v3 : std_logic_vector(0 downto 0);
signal localtime_reg : std_logic_vector(31 downto 0);
signal crc_reg_dly : std_logic_vector(7 downto 0);
signal IFG_cnt : std_logic_vector(4 downto 0);
signal IFG_busy : std_logic;
signal m4_TxFIFO_DN : std_logic_vector( 3 downto 0 );
signal s_N_Empty : std_logic;
signal s_N_Empty_TxClk : std_logic;
signal s_N_Empty_TxClk_D1 : std_logic;
begin
p_info_start : process(clk, reset)
begin
if reset = '1' then
info_start <= '0';
source_select <= '0';
ce_d1 <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if busy = '0' then
if tx_queue_empty = '0' then
info_start <= '1';
source_select <= '0';
elsif db_queue_empty = '0' then
info_start <= '1';
source_select <= '1';
end if;
else
info_start <= '0';
end if;
end if;
ce_d1 <= ce;
end if;
end process;
busy <= info_start or info_ena or data_start or data_ena or data_ena_d8 or data_ena_ext or data_ena_ext_d13 or IFG_busy;
p_info_cnt : process(clk, reset)
begin
if reset = '1' then
info_ena <= '0';
info_cnt <= 0;
info_ena_d1 <= '0';
info_cnt_d1 <= 0;
elsif rising_edge(clk) then
if ce = '1' then
if info_start = '1' then
info_ena <= '1';
elsif info_cnt = INFO_LENGTH - 1 then
info_ena <= '0';
end if;
if info_ena = '0' then
info_cnt <= 0;
else
info_cnt <= info_cnt + 1;
end if;
end if;
info_ena_d1 <= info_ena;
info_cnt_d1 <= info_cnt;
end if;
end process;
------------------------------------------------------------------------------
data_start <= '1' when info_cnt = INFO_LENGTH else '0';
p_byte_cnt : process(clk, reset)
begin
if reset = '1' then
data_ena <= '0';
byte_cnt <= (others => '0');
byte_cnt_d1 <= (others=>'0');
head_ena_d1 <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if data_start = '1' then
data_ena <= '1';
elsif buff_ena = '0' and byte_cnt >= data_length-1 then
data_ena <= '0';
elsif buff_ena = '1' and byte_cnt >= data_length - 4 then
data_ena <= '0';
end if;
if data_start = '1' then
byte_cnt <= (others => '0');
elsif head_ena = '1' then
byte_cnt <= byte_cnt + 1;
elsif buff_ena = '1' then
byte_cnt <= byte_cnt + 4;
end if;
end if;
byte_cnt_d1 <= byte_cnt;
head_ena_d1 <= head_ena;
end if;
end process;
head_ena <= '1' when data_ena = '1' and byte_cnt < head_length else '0';
buff_ena <= '1' when data_ena = '1' and byte_cnt >= head_length else '0';
------------------------------------------------------------------------------
head_rden <= (info_ena or head_ena) and ce;
p_head_raddr : process(clk, reset)
begin
if reset = '1' then
head_raddr_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if info_start = '1' then
head_raddr_buf <= (others => '0');
elsif head_rden = '1' then
head_raddr_buf <= head_raddr_buf + 1;
end if;
end if;
end if;
end process;
tx_head_raddr <= head_raddr_buf;
db_head_raddr <= head_raddr_buf;
head_rdata <= tx_head_rdata when source_select = '0' else db_head_rdata;
head_rd_block <= '1' when byte_cnt = head_length else '0';
tx_head_rd_block <= head_rd_block and ce and (not source_select);
db_head_rd_block <= head_rd_block and ce and source_select;
p_get_info : process(clk, reset)
begin
if reset = '1' then
head_length <= (others => '0');
data_length <= (others => '0');
dma_start_addr <= (others => '0');
dma_step <= (others => '0');
elsif rising_edge(clk) then
if ce_d1 = '1' then
if info_ena_d1 = '1' then
case info_cnt_d1 is
when 0 =>
head_length(7 downto 0) <= head_rdata;
when 1 =>
data_length(7 downto 0) <= head_rdata;
when 2 =>
data_length(10 downto 8) <= head_rdata(2 downto 0);
when 3 =>
dma_start_addr(7 downto 0) <= head_rdata;
when 4 =>
dma_start_addr(15 downto 8) <= head_rdata;
when 5 =>
dma_start_addr(23 downto 16) <= head_rdata;
when 6 =>
dma_start_addr(31 downto 24) <= head_rdata;
when 7 =>
dma_step <= head_rdata;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
dma_start <= '1' when info_cnt_d1 = INFO_LENGTH and ce_d1 = '1' and data_length /= head_length else '0';
dma_length <= EXT(data_length, 16) - EXT(head_length, 16);
-----------------------------------------------------------------------------
p_get_head : process(clk, reset)
begin
if reset = '1' then
head_rdata_buf <= (others=>'0');
elsif rising_edge(clk) then
if ce_d1 = '1' then
if head_ena_d1 = '1' then
if byte_cnt_d1(1 downto 0) = "00" then
head_rdata_buf <= head_rdata & X"0000";
else
head_rdata_buf <= head_rdata & head_rdata_buf(23 downto 8);
end if;
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
buff_rden <= buff_ena and ce;
p_buff_raddr : process(clk, reset)
begin
if reset = '1' then
buff_raddr_buf <= (others => '0');
buff_rdata_buf <= (others=>'0');
buff_ena_d1 <= '0';
buff_rden_d1 <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if data_start = '1' then
buff_raddr_buf <= (others => '0');
elsif buff_rden = '1' then
buff_raddr_buf <= buff_raddr_buf + 1;
end if;
buff_rdata_buf <= buff_rdata;
end if;
buff_ena_d1 <= buff_ena;
buff_rden_d1 <= buff_rden;
end if;
end process;
buff_raddr <= buff_raddr_buf;
------------------------------------------------------------------------------
dword_data_int <= buff_rdata_buf when buff_ena_d1 = '1' else
head_rdata & head_rdata_buf when head_ena_d1 = '1' else
(others=>'0');
ce <= not TxFIFO_almost_full;
TxFIFO_clr <= '1' when data_start = '1' else '0';
TxFIFO_wea <= '1' when (head_ena_d1 = '1' and byte_cnt_d1(1 downto 0) = "11") or buff_rden_d1 = '1' else '0';
TxFIFO_dia <= dword_data_int;
u_txclk_sync : fifo_async_almost_full
generic map(
depth => 16,
awidth => 4,
dwidth => 32,
ram_type => "DIS_RAM"
)
port map(
reset => reset,
clr => TxFIFO_clr,
clka => clk,
wea => TxFIFO_wea,
dia => TxFIFO_dia,
clkb => txclk,
rdb => TxFIFO_rdb,
dob => TxFIFO_dob,
empty => TxFIFO_empty,
almost_full => TxFIFO_almost_full,
full => open,
dn => TxFIFO_DN
);
dword_data_ext <= TxFIFO_dob;
TxFIFO_rdb <= data_ena_ext and ce_ext when byte_cnt_ext(1 downto 0) = "00" else '0';
-------------------------------------------------------------------------------------------------------
data_start_ext_wren <= (not head_ena) and head_ena_d1;
ASYNCWRITE_data_start_ext : ASYNCWRITE
port map(
reset => reset,
async_clk => clk,
sync_clk => txclk,
async_wren => data_start_ext_wren,
trigger => '1',
sync_wren => data_start_ext,
over => open,
flag => open
);
ce_ext <= '1';
p_byte_cnt_ext : process(txclk, reset)
begin
if reset = '1' then
ce_ext_d1 <= '0';
ce_ext_d2 <= '0';
data_ena_ext <= '0';
data_ena_ext_d1 <= '0';
data_ena_ext_d2 <= '0';
byte_cnt_ext <= (others => '0');
byte_cnt_ext_d1 <= (others=>'0');
byte_cnt_ext_d2 <= (others=>'0');
TxFIFO_rdb_d1 <= '0';
elsif rising_edge(txclk) then
if ce_ext = '1' then
if data_start_ext = '1' then
data_ena_ext <= '1';
elsif byte_cnt_ext = data_length - 1 then
data_ena_ext <= '0';
end if;
if data_start_ext = '1' then
byte_cnt_ext <= (others => '0');
else
byte_cnt_ext <= byte_cnt_ext + 1;
end if;
end if;
ce_ext_d1 <= ce_ext;
ce_ext_d2 <= ce_ext_d1;
data_ena_ext_d1 <= data_ena_ext;
data_ena_ext_d2 <= data_ena_ext_d1;
byte_cnt_ext_d1 <= byte_cnt_ext;
byte_cnt_ext_d2 <= byte_cnt_ext_d1;
TxFIFO_rdb_d1 <= TxFIFO_rdb;
end if;
end process;
p_byte_data_buf : process(txclk, reset)
begin
if reset = '1' then
byte_data_buf <= (others => '0');
elsif rising_edge(txclk) then
if ce_ext_d1 = '1' then
if TxFIFO_rdb_d1 = '1' then
byte_data_buf <= TxFIFO_dob;
else
byte_data_buf <= X"00" & byte_data_buf(31 downto 8);
end if;
end if;
end if;
end process;
p_localtime : process(reset, txclk)
begin
if reset = '1' then
localtime_reg <= (others => '0');
elsif rising_edge(txclk) then
if byte_cnt_ext = 7 then
localtime_reg <= localtime;
end if;
end if;
end process;
byte_data <= localtime_reg(31 downto 24) when byte_cnt_ext_d1 = 14 and source_select = '0' else
localtime_reg(23 downto 16) when byte_cnt_ext_d1 = 15 and source_select = '0' else
localtime_reg(15 downto 8) when byte_cnt_ext_d1 = 16 and source_select = '0' else
localtime_reg(7 downto 0) when byte_cnt_ext_d1 = 17 and source_select = '0' else
TxFIFO_dob(7 downto 0) when byte_cnt_ext_d1(1 downto 0) = "00" else
byte_data_buf(15 downto 8);
u_crc_rom : CRC8_BlkRom
port map(
clk => txclk,
addr => crcrom_addr,
dout => crcrom_dout
);
crcrom_addr <= crc_reg(31 downto 24);
crc_din <= (others => '0') when data_ena_ext_d1 = '0' else
not (byte_data(0) & byte_data(1) & byte_data(2) & byte_data(3) & byte_data(4) & byte_data(5) & byte_data(6) & byte_data(7)) when byte_cnt_ext_d1 < 4 else
byte_data(0) & byte_data(1) & byte_data(2) & byte_data(3) & byte_data(4) & byte_data(5) & byte_data(6) & byte_data(7);
crc_reg <= (others=>'0') when data_start_ext = '1' and ce_ext = '1' else
crc_reg_d1 xor crcrom_dout when (data_ena_ext_d2 = '1' or data_ena_ext_d6 = '1') and ce_ext_d2 = '1' else
crc_reg_d1;
p_calc_crc : process(txclk, reset)
begin
if reset = '1' then
crc_reg_d1 <= (others => '0');
elsif rising_edge(txclk) then
if ce_ext_d1 = '1' then
if data_start_ext = '1' then
crc_reg_d1 <= (others => '0');
else
crc_reg_d1 <= (crc_reg(23 downto 0) & crc_din);
end if;
else
crc_reg_d1 <= crc_reg(23 downto 0) & crc_din;
end if;
end if;
end process;
------------------------------------------------------------------------------
u_nibble_data_dly : ShiftReg
generic map(
WIDTH => 8,
DEPTH => 7
)
port map(
clk => txclk,
ce => '1',
D => byte_data,
Q => byte_data_dly,
S => open
);
u_crc_reg_dly : ShiftReg
generic map(
WIDTH => 8,
DEPTH => 3
)
port map(
clk => txclk,
ce => '1',
D => crc_reg(31 downto 24),
Q => crc_reg_dly(7 downto 0),
S => open
);
u_data_ena_d0 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 8
)
port map(
clk => clk,
ce => '1',
D(0) => data_ena,
Q(0) => data_ena_d8,
S => open
);
u_data_ena_d1 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 4
)
port map(
clk => txclk,
ce => '1',
D => v0,
Q => v1,
S => open
);
u_data_ena_d2 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 2
)
port map(
clk => txclk,
ce => '1',
D => v1,
Q => v2,
S => open
);
u_data_ena_d3 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 4
)
port map(
clk => txclk,
ce => '1',
D => v2,
Q => v3,
S => open
);
v0(0) <= data_ena_ext_d2;
data_ena_ext_d6 <= v1(0);
data_ena_ext_d8 <= v2(0);
data_ena_ext_d12 <= v3(0);
txd_buf <= "01010101" when data_ena_ext = '1' and byte_cnt_ext < 7 else
"11010101" when data_ena_ext = '1' and byte_cnt_ext = 7 else
--
byte_data_dly when data_ena_ext_d8 = '1' else
not(crc_reg_dly(0) & crc_reg_dly(1) & crc_reg_dly(2) & crc_reg_dly(3) & crc_reg_dly(4) & crc_reg_dly(5) & crc_reg_dly(6) & crc_reg_dly(7));
txen_buf <= data_ena_ext or data_ena_ext_d12;
------------------------------------------------------------------------------
p_mii_dout : process(reset, txclk)
begin
if ( reset = '1' ) then
txen <= '0';
txd <= ( others => '0' );
elsif rising_edge(txclk) then
txen <= txen_buf;
txd <= txd_buf;
end if;
end process;
p_ifg_count : process(txclk, reset)
begin
if reset = '1' then
IFG_cnt <= "00000";
data_ena_ext_d13 <= '0';
elsif rising_edge(txclk) then
data_ena_ext_d13 <= data_ena_ext_d12;
if IFG_busy = '1' then
IFG_cnt <= IFG_cnt + '1';
else
IFG_cnt <= "00000";
end if;
end if;
end process;
p_ifg_busy_flag : process(txclk, reset)
begin
if reset = '1' then
IFG_busy <= '0';
elsif rising_edge(txclk) then
if data_ena_ext_d12 = '0' and data_ena_ext_d13 = '1' then
IFG_busy <= '1';
elsif IFG_cnt = "11111" then
IFG_busy <= '0';
end if;
end if;
end process;
end arch_ethtx_output;
| gpl-2.0 |
a4a881d4/zcpsm | src/example/eth_hub/vhd/ethrx_zcpsm/ethrx_zcpsm.vhd | 1 | 1950 | ---------------------------------------------------------------------------------------------------
--
-- Title : ethrx_zcpsm
-- Design : eth_new
-- Author : a4a881d4
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ethrx_zcpsm is
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end ethrx_zcpsm;
--}} End of automatically maintained section
architecture behavior of ethrx_zcpsm is
component zcpsm
Port (
address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component ethrxrom_romonly
port(
addrb : in std_logic_vector(11 downto 0);
clkb : in std_logic;
dob : out std_logic_vector(17 downto 0));
end component;
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
begin
u_rx_zcpsm : zcpsm
port map(
address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => '0',
reset => reset,
clk => clk
);
u_rx_rom : ethrxrom_romonly
port map(
addrb => address,
clkb => clk,
dob => instruction
);
end behavior;
| gpl-2.0 |
1995parham/Learning | vhdl/halfaddr/halfaddr.vhd | 1 | 539 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 08-02-2016
-- Module Name: halfaddr.vhd
--------------------------------------------------------------------------------
use IEEE;
library IEEE.std_logic_1164.all
entity halfaddr is
port(a b : in std_logic;
sum c_out : out std_logic);
end entity halfaddr;
architecture arch_halfaddr of halfaddr is
begin
sum <= a xor b;
c_out <= a and b;
end architecture arch_halfaddr;
| gpl-2.0 |
a4a881d4/zcpsm | src/example/eth_hub/vhd/m_eth/ethtx_output.vhd | 1 | 15834 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ethtx_output is
generic(
HEAD_AWIDTH : natural := 5;
BUFF_AWIDTH : natural := 16;
RAM_AWIDTH : natural := 32
);
port(
clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(3 downto 0);
txen : out std_logic;
tx_queue_empty : in std_logic;
tx_head_raddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0);
tx_head_rdata : in std_logic_vector(7 downto 0);
tx_head_rd_block : out std_logic;
db_queue_empty : in std_logic;
db_head_raddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0);
db_head_rdata : in std_logic_vector(7 downto 0);
db_head_rd_block : out std_logic;
buff_raddr : out std_logic_vector(BUFF_AWIDTH - 1 downto 0);
buff_rdata : in std_logic_vector(7 downto 0);
dma_start : out std_logic;
dma_start_addr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- dma_start_addr : out std_logic_vector(23 downto 0);
dma_length : out std_logic_vector(15 downto 0);
dma_step : out std_logic_vector(7 downto 0);
localtime : in std_logic_vector(31 downto 0)
);
end ethtx_output;
architecture arch_ethtx_output of ethtx_output is
component crcrom
port(
addr : in std_logic_vector(3 downto 0);
dout : out std_logic_vector(31 downto 0));
end component;
component fifo_async
generic(
DEPTH : NATURAL;
AWIDTH : NATURAL;
DWIDTH : NATURAL;
RAM_TYPE : STRING);
port(
reset : in std_logic;
clr : in std_logic;
clka : in std_logic;
wea : in std_logic;
dia : in std_logic_vector((DWIDTH-1) downto 0);
clkb : in std_logic;
rdb : in std_logic;
dob : out std_logic_vector((DWIDTH-1) downto 0);
empty : out std_logic;
full : out std_logic;
dn : out std_logic_vector((AWIDTH-1) downto 0));
end component;
for all: fifo_async use entity WORK.fifo_async(fast_write);
component shiftreg
generic(
width : INTEGER;
depth : INTEGER);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector((width-1) downto 0);
Q : out std_logic_vector((width-1) downto 0);
S : out std_logic_vector((width-1) downto 0));
end component;
-- constant INFO_LENGTH : natural := 7;
constant INFO_LENGTH : natural := 8;
signal full : std_logic;
signal ce : std_logic;
signal txd_int : std_logic_vector(3 downto 0);
signal txen_int : std_logic;
signal txd_buf : std_logic_vector(3 downto 0);
signal txen_buf : std_logic;
signal d_int : std_logic_vector(4 downto 0);
signal d_ext : std_logic_vector(4 downto 0);
signal busy : std_logic;
signal nibble_cnt : std_logic_vector(11 downto 0);
signal head_length : std_logic_vector(7 downto 0);
signal data_length : std_logic_vector(10 downto 0);
signal source_select : std_logic;
signal head_rd_block : std_logic;
signal info_ena : std_logic;
signal info_cnt : integer range 0 to INFO_LENGTH;
signal data_ena : std_logic;
signal data_ena_d1 : std_logic;
signal data_ena_d2 : std_logic;
signal data_ena_d3 : std_logic;
signal data_ena_d4 : std_logic;
signal data_ena_d5 : std_logic;
signal head_ena : std_logic;
signal buff_ena : std_logic;
signal info_start : std_logic;
signal data_start : std_logic;
signal byte_data : std_logic_vector(7 downto 0);
signal nibble_data : std_logic_vector(3 downto 0);
signal nibble_data_buf : std_logic_vector(3 downto 0);
signal nibble_data_dly : std_logic_vector(3 downto 0);
signal head_rden : std_logic;
signal head_rdata : std_logic_vector(7 downto 0);
signal head_raddr_buf : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal buff_rden : std_logic;
signal buff_raddr_buf : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal crc_din : std_logic_vector(3 downto 0);
signal crc_reg : std_logic_vector(31 downto 0);
signal crcrom_addr : std_logic_vector(3 downto 0);
signal crcrom_dout : std_logic_vector(31 downto 0);
signal v0 : std_logic_vector(0 downto 0);
signal v1 : std_logic_vector(0 downto 0);
signal v2 : std_logic_vector(0 downto 0);
signal v3 : std_logic_vector(0 downto 0);
signal localtime_reg : std_logic_vector(31 downto 0);
signal crc_reg_dly : std_logic_vector(3 downto 0);
signal IFG_cnt : std_logic_vector(4 downto 0);
signal IFG_busy : std_logic;
signal m4_TxFIFO_DN : std_logic_vector( 3 downto 0 );
signal s_N_Empty : std_logic;
signal s_N_Empty_TxClk : std_logic;
signal s_N_Empty_TxClk_D1 : std_logic;
begin
-- p_IFG_count : process(clk, reset)
p_info_start : process(clk, reset)
begin
if reset = '1' then
info_start <= '0';
source_select <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if busy = '0' then
if tx_queue_empty = '0' then
info_start <= '1';
source_select <= '0';
elsif db_queue_empty = '0' then
info_start <= '1';
source_select <= '1';
end if;
else
info_start <= '0';
end if;
end if;
end if;
end process;
-- busy <= info_start or info_ena or data_start or data_ena or data_ena_d3;
busy <= info_start or info_ena or data_start or data_ena or data_ena_d4 or IFG_busy;
p_info_cnt : process(clk, reset)
begin
if reset = '1' then
info_ena <= '0';
info_cnt <= 0;
elsif rising_edge(clk) then
if ce = '1' then
if info_start = '1' then
info_ena <= '1';
elsif info_cnt = INFO_LENGTH - 1 then
info_ena <= '0';
end if;
if info_ena = '0' then
info_cnt <= 0;
else
info_cnt <= info_cnt + 1;
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
data_start <= '1' when info_cnt = INFO_LENGTH else '0';
p_nibble_cnt : process(clk, reset)
begin
if reset = '1' then
data_ena <= '0';
nibble_cnt <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if data_start = '1' then
data_ena <= '1';
elsif nibble_cnt = (data_length & '0') - 1 then
data_ena <= '0';
end if;
if data_start = '1' then
nibble_cnt <= (others => '0');
else
nibble_cnt <= nibble_cnt + 1;
end if;
end if;
end if;
end process;
head_ena <= '1' when data_ena = '1' and nibble_cnt < head_length & '0' else '0';
buff_ena <= '1' when data_ena = '1' and nibble_cnt >= head_length & '0' else '0';
------------------------------------------------------------------------------
head_rden <= (info_ena or (head_ena and (not nibble_cnt(0)))) and ce;
p_head_raddr : process(clk, reset)
begin
if reset = '1' then
head_raddr_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if info_start = '1' then
head_raddr_buf <= (others => '0');
elsif head_rden = '1' then
head_raddr_buf <= head_raddr_buf + 1;
end if;
end if;
end if;
end process;
tx_head_raddr <= head_raddr_buf;
db_head_raddr <= head_raddr_buf;
head_rdata <= tx_head_rdata when source_select = '0' else db_head_rdata;
head_rd_block <= '1' when nibble_cnt = head_length & '0' else '0';
tx_head_rd_block <= head_rd_block and ce and (not source_select);
db_head_rd_block <= head_rd_block and ce and source_select;
p_get_info : process(clk, reset)
begin
if reset = '1' then
head_length <= (others => '0');
data_length <= (others => '0');
dma_start_addr <= (others => '0');
dma_step <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if info_ena = '1' then
case info_cnt is
when 0 =>
head_length(7 downto 0) <= head_rdata;
when 1 =>
data_length(7 downto 0) <= head_rdata;
when 2 =>
data_length(10 downto 8) <= head_rdata(2 downto 0);
when 3 =>
dma_start_addr(7 downto 0) <= head_rdata;
when 4 =>
dma_start_addr(15 downto 8) <= head_rdata;
when 5 =>
dma_start_addr(23 downto 16) <= head_rdata;
-- 4 bytes dma addr --
when 6 =>
dma_start_addr(31 downto 24) <= head_rdata;
when 7 =>
dma_step <= head_rdata;
--when 6 =>
--dma_step <= head_rdata;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
dma_start <= '1' when info_cnt = INFO_LENGTH and ce = '1' and data_length /= head_length else '0';
dma_length <= SXT(data_length, 16) - SXT(head_length, 16);
------------------------------------------------------------------------------
buff_rden <= buff_ena and (not nibble_cnt(0)) and ce;
p_buff_raddr : process(clk, reset)
begin
if reset = '1' then
buff_raddr_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if data_start = '1' then
buff_raddr_buf <= (others => '0');
elsif buff_rden = '1' then
buff_raddr_buf <= buff_raddr_buf + 1;
end if;
end if;
end if;
end process;
buff_raddr <= buff_raddr_buf;
------------------------------------------------------------------------------
byte_data <= head_rdata when head_ena = '1' else
buff_rdata when buff_ena = '1' else
(others => '0');
p_nibble_data_buf : process(clk, reset)
begin
if reset = '1' then
nibble_data_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
nibble_data_buf <= byte_data(7 downto 4);
end if;
end if;
end process;
--local time --
p_localtime : process(reset, clk)
begin
if reset = '1' then
localtime_reg <= (others => '0');
elsif rising_edge(clk) then
if nibble_cnt = 15 then
localtime_reg <= localtime;
end if;
end if;
end process;
nibble_data <= localtime_reg(31 downto 28) when nibble_cnt = 29 and source_select = '0' else
localtime_reg(27 downto 24) when nibble_cnt = 28 and source_select = '0' else
localtime_reg(23 downto 20) when nibble_cnt = 31 and source_select = '0' else
localtime_reg(19 downto 16) when nibble_cnt = 30 and source_select = '0' else
localtime_reg(15 downto 12) when nibble_cnt = 33 and source_select = '0' else
localtime_reg(11 downto 8) when nibble_cnt = 32 and source_select = '0' else
localtime_reg(7 downto 4) when nibble_cnt = 35 and source_select = '0' else
localtime_reg(3 downto 0) when nibble_cnt = 34 and source_select = '0' else
byte_data(3 downto 0) when nibble_cnt(0) = '0' else nibble_data_buf;
-- nibble_data <= byte_data(3 downto 0) when nibble_cnt(0) = '0' else nibble_data_buf;
------------------------------------------------------------------------------
u_crc_rom : CRCRom
port map(
addr => crcrom_addr,
dout => crcrom_dout
);
crcrom_addr <= crc_reg(31 downto 28);
crc_din <= (others => '0') when data_ena = '0' else
not (nibble_data(0) & nibble_data(1) & nibble_data(2) & nibble_data(3)) when nibble_cnt < 8 else
nibble_data(0) & nibble_data(1) & nibble_data(2) & nibble_data(3);
p_calc_crc : process(clk, reset)
begin
if reset = '1' then
crc_reg <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if data_start = '1' then
crc_reg <= (others => '0');
elsif data_ena_d1 = '1' then
crc_reg <= (crc_reg(27 downto 0) & crc_din) xor crcrom_dout;
else
crc_reg <= (crc_reg(27 downto 0) & crc_din);
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
u_nibble_data_dly : ShiftReg
generic map(
WIDTH => 4,
DEPTH => 16 -- 8
)
port map(
clk => clk,
ce => ce,
D => nibble_data,
Q => nibble_data_dly,
S => open
);
u_crc_reg_dly : ShiftReg
generic map(
WIDTH => 4,
DEPTH => 8 -- 8
)
port map(
clk => clk,
ce => ce,
D => crc_reg(31 downto 28),
Q => crc_reg_dly(3 downto 0),
S => open
);
u_data_ena_d1 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 8 -- 8
)
port map(
clk => clk,
ce => ce,
D => v0,
Q => v1,
S => open
);
u_data_ena_d2 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 8 --8
)
port map(
clk => clk,
ce => ce,
D => v1,
Q => v2,
S => open
);
u_data_ena_d3 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 8 --8
)
port map(
clk => clk,
ce => ce,
D => v2,
Q => v3,
S => open
);
v0(0) <= data_ena;
data_ena_d1 <= v1(0);
data_ena_d2 <= v2(0);
data_ena_d3 <= v3(0);
txd_int <= "0101" when data_ena = '1' and nibble_cnt < 15 else
"1101" when data_ena = '1' and nibble_cnt = 15 else
--
nibble_data_dly when data_ena_d2 = '1' else
not(crc_reg_dly(0) & crc_reg_dly(1) & crc_reg_dly(2) & crc_reg_dly(3));
txen_int <= data_ena or data_ena_d3;
------------------------------------------------------------------------------
-- u_dout_sync : fifo_async
-- generic map(
-- depth => 4,
-- awidth => 2,
-- dwidth => 5,
-- ram_type => "DIS_RAM"
-- )
-- port map(
-- reset => reset,
-- clr => '0',
-- clka => clk,
-- wea => ce,
-- dia => d_int,
-- clkb => txclk,
-- rdb => '1',
-- dob => d_ext,
-- empty => open,
-- full => full,
-- dn => open
-- );
u_dout_sync : fifo_async
generic map(
depth => 16,
awidth => 4,
dwidth => 5,
ram_type => "DIS_RAM"
)
port map(
reset => reset,
clr => '0',
clka => clk,
wea => ce,
dia => d_int,
clkb => txclk,
rdb => s_N_Empty_TxClk,
dob => d_ext,
empty => open,
full => full,
dn => m4_TxFIFO_DN
);
NEmpty : process( reset, clk )
begin
if ( reset = '1' ) then
s_N_Empty <= '0';
elsif ( rising_edge( clk ) ) then
if ( m4_TxFIFO_DN > "0111" ) then
s_N_Empty <= '1';
-- else
-- s_N_Empty <= '0';
end if;
end if;
end process;
NEmpty_TxClk : process( reset, txclk )
begin
if ( reset = '1' ) then
s_N_Empty_TxClk <= '0';
s_N_Empty_TxClk_D1 <= '0';
elsif ( rising_edge( txclk ) ) then
s_N_Empty_TxClk <= s_N_Empty;
s_N_Empty_TxClk_D1 <= s_N_Empty_TxClk;
end if;
end process;
d_int <= txen_int & txd_int;
txen_buf <= d_ext(4) and s_N_Empty_TxClk_D1;
txd_buf <= d_ext(3 downto 0) and ( s_N_Empty_TxClk_D1 & s_N_Empty_TxClk_D1 & s_N_Empty_TxClk_D1 & s_N_Empty_TxClk_D1 );
ce <= not full;
p_mii_dout : process(reset, txclk)
begin
if ( reset = '1' ) then
txen <= '0';
txd <= ( others => '0' );
elsif rising_edge(txclk) then
txen <= txen_buf;
txd <= txd_buf;
end if;
end process;
--------------------------------------------------------------
--- IFG - Inter Frame Gap generation
----------------------------------------------------------------
p_ifg_count : process(clk, reset)
begin
if reset = '1' then
IFG_cnt <= "00000";
elsif rising_edge(clk) then
data_ena_d4 <= data_ena_d3;
data_ena_d5 <= data_ena_d4;
if IFG_busy = '1' then
IFG_cnt <= IFG_cnt + '1';
else
IFG_cnt <= "00000";
end if;
end if;
end process;
p_ifg_busy_flag : process(clk, reset)
begin
if reset = '1' then
IFG_busy <= '0';
elsif rising_edge(clk) then
if data_ena_d3 = '0' and data_ena_d4 = '1' then
IFG_busy <= '1';
elsif IFG_cnt = "11111" then
IFG_busy <= '0';
end if;
end if;
end process;
end arch_ethtx_output;
| gpl-2.0 |
1995parham/Learning | vhdl/majority/majority.vhd | 1 | 674 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 08-02-2016
-- Module Name: majority.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1165.all;
entity majority is
port (i1, i2, i3 : in std_logic;
o1 : out std_logic);
end entity;
architecture arch_majority of majority is
signal tmp1 : std_logic;
signal tmp2 : std_logic;
signal tmp3 : std_logic;
begin
tmp1 <= i1 and i2;
tmp2 <= i2 and i3;
tmp3 <= i1 and i3;
o1 <= tmp1 or tmp2 or tmp3 after 2 ns;
end architecture arch_majority;
| gpl-2.0 |
a4a881d4/zcpsm | src/zcpsm/common/ShiftReg.vhd | 1 | 900 | library ieee;
use ieee.std_logic_1164.all;
--Library synplify;
--use synplify.attributes.all;
entity ShiftReg is
generic(
width : integer;
depth : integer
);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector(width-1 downto 0);
Q : out std_logic_vector(width-1 downto 0) := ( others => '0' );
S : out std_logic_vector(width-1 downto 0)
);
end ShiftReg;
architecture behave of ShiftReg is
type ram_memtype is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal mem : ram_memtype := (others => (others => '0'));
-- attribute syn_srlstyle of mem : signal is "select_srl";
begin
mem(0) <= D;
process(clk)
begin
if rising_edge(clk) then
if ce = '1' then
mem(depth downto 1) <= mem(depth-1 downto 0);
Q <= mem (depth-1);
end if;
end if;
end process;
S <= mem(depth);
end behave; | gpl-2.0 |
myriadrf/A2300 | hdl/wca/hal/FiFo512Core32W32R/example_design/FiFo512Core32W32R_exdes.vhd | 1 | 5592 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FiFo512Core32W32R_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity FiFo512Core32W32R_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end FiFo512Core32W32R_exdes;
architecture xilinx of FiFo512Core32W32R_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component FiFo512Core32W32R is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : FiFo512Core32W32R
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 |
a4a881d4/zcpsm | src/example/eth_hub/vhd/m_eth/ethtx.vhd | 1 | 11185 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ethtx is
generic(
HEAD_AWIDTH : natural := 5;
BUFF_AWIDTH : natural := 5;
FIFO_AWIDTH : natural := 2;
RD_CYCLE : natural := 1;
RD_DELAY : natural := 1;
RAM_AWIDTH : natural := 32
);
port (
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(3 downto 0);
txen : out std_logic;
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
-- ram_raddr : out std_logic_vector(23 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- ram_rdata : in std_logic_vector(7 downto 0);
ram_rdata : in std_logic_vector(15 downto 0);
-- local time --
localtime : in std_logic_vector(31 downto 0)
);
end entity;
architecture arch_ethtx of ethtx is
component ethtx_output
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 5;
RAM_AWIDTH : NATURAL := 32
);
port(
clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(3 downto 0);
txen : out std_logic;
tx_queue_empty : in std_logic;
tx_head_raddr : out std_logic_vector((HEAD_AWIDTH-1) downto 0);
tx_head_rdata : in std_logic_vector(7 downto 0);
tx_head_rd_block : out std_logic;
db_queue_empty : in std_logic;
db_head_raddr : out std_logic_vector((HEAD_AWIDTH-1) downto 0);
db_head_rdata : in std_logic_vector(7 downto 0);
db_head_rd_block : out std_logic;
buff_raddr : out std_logic_vector((BUFF_AWIDTH-1) downto 0);
buff_rdata : in std_logic_vector(7 downto 0);
dma_start : out std_logic;
-- dma_start_addr : out std_logic_vector(23 downto 0);
dma_start_addr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
dma_length : out std_logic_vector(15 downto 0);
dma_step : out std_logic_vector(7 downto 0);
-- local time --
localtime: in std_logic_vector(31 downto 0)
);
end component;
component Tx_queue
generic(
HEAD_AWIDTH : NATURAL := 5;
FIFO_AWIDTH : NATURAL := 2;
RAM_TYPE : STRING := "DIS_RAM");
port(
clk : in std_logic;
reset : in std_logic;
queue_empty : out std_logic;
head_raddr : in std_logic_vector((HEAD_AWIDTH-1) downto 0);
head_rdata : out std_logic_vector(7 downto 0);
head_rd_block : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0));
end component;
component disdram
generic(
depth : INTEGER;
Dwidth : INTEGER;
Awidth : INTEGER);
port(
A : in std_logic_vector((Awidth-1) downto 0);
CLK : in std_logic;
D : in std_logic_vector((Dwidth-1) downto 0);
WE : in std_logic;
DPRA : in std_logic_vector((Awidth-1) downto 0);
DPO : out std_logic_vector((Dwidth-1) downto 0);
QDPO : out std_logic_vector((Dwidth-1) downto 0));
end component;
component dma_ctrl
generic(
DWIDTH : NATURAL;
RD_CYCLE : NATURAL;
RD_DELAY : NATURAL;
RAM_AWIDTH : NATURAL
);
port(
clk : in std_logic;
reset : in std_logic;
ena : in std_logic;
start : in std_logic;
length : in std_logic_vector(15 downto 0);
start_waddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- start_raddr : in std_logic_vector(23 downto 0);
start_raddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
wstep : in std_logic_vector(7 downto 0);
rstep : in std_logic_vector(7 downto 0);
busy : out std_logic;
-- raddr : out std_logic_vector(23 downto 0);
raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
rdata : in std_logic_vector((DWIDTH-1) downto 0);
wren : out std_logic;
waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
wdata : out std_logic_vector((DWIDTH-1) downto 0));
end component;
signal tx_queue_empty : std_logic;
signal tx_head_raddr : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal tx_head_rdata : std_logic_vector(7 downto 0);
signal tx_head_rd_block : std_logic;
signal db_queue_empty : std_logic;
signal db_head_raddr : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal db_head_rdata : std_logic_vector(7 downto 0);
signal db_head_rd_block : std_logic;
signal buff_raddr : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal buff_rdata : std_logic_vector(7 downto 0);
signal buff_wren : std_logic;
signal buff_waddr : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal buff_wdata : std_logic_vector(7 downto 0);
signal dma_length : std_logic_vector(15 downto 0);
-- signal dma_start_raddr : std_logic_vector(23 downto 0);
signal dma_start_raddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_rstep : std_logic_vector(7 downto 0);
signal dma_start : std_logic;
signal dma_busy : std_logic;
-- signal dma_raddr : std_logic_vector(23 downto 0);
signal dma_raddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- signal dma_rdata : std_logic_vector(7 downto 0);
signal dma_rdata : std_logic_vector(15 downto 0);
signal dma_wdata_word : std_logic_vector(15 downto 0);
signal dma_length_word : std_logic_vector(15 downto 0);
signal dma_waddr_word : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_wren_word : std_logic;
signal flag : std_logic;
signal buff_waddr_reg : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal buff_wdata_reg : std_logic_vector(15 downto 0);
signal dma_wren_reg : std_logic;
-- signal dma_wren : std_logic;
-- signal dma_waddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- signal dma_wdata : std_logic_vector(7 downto 0);
signal dma_ena : std_logic;
signal buff_wr_diff : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
begin
u_output : ethtx_output
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
BUFF_AWIDTH => BUFF_AWIDTH,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
reset => reset,
txclk => txclk,
txd => txd,
txen => txen,
tx_queue_empty => tx_queue_empty,
tx_head_raddr => tx_head_raddr,
tx_head_rdata => tx_head_rdata,
tx_head_rd_block => tx_head_rd_block,
db_queue_empty => db_queue_empty,
db_head_raddr => db_head_raddr,
db_head_rdata => db_head_rdata,
db_head_rd_block => db_head_rd_block,
buff_raddr => buff_raddr,
buff_rdata => buff_rdata,
dma_start => dma_start,
dma_start_addr => dma_start_raddr,
dma_length => dma_length,
dma_step => dma_rstep,
-- local time
localtime => localtime
);
u_db_queue : Tx_queue
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
FIFO_AWIDTH => 0,
RAM_TYPE => "DIS_RAM"
)
port map(
clk => clk,
reset => reset,
queue_empty => db_queue_empty,
head_raddr => db_head_raddr,
head_rdata => db_head_rdata,
head_rd_block => db_head_rd_block,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => db_ce,
zcpsm_port_id => db_port_id,
zcpsm_write_strobe => db_write_strobe,
zcpsm_out_port => db_out_port,
zcpsm_read_strobe => db_read_strobe,
zcpsm_in_port => db_in_port
);
u_tx_queue : Tx_queue
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
FIFO_AWIDTH => FIFO_AWIDTH,
RAM_TYPE => "DIS_RAM"
)
port map(
clk => clk,
reset => reset,
queue_empty => tx_queue_empty,
head_raddr => tx_head_raddr,
head_rdata => tx_head_rdata,
head_rd_block => tx_head_rd_block,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => eth_ce,
zcpsm_port_id => eth_port_id,
zcpsm_write_strobe => eth_write_strobe,
zcpsm_out_port => eth_out_port,
zcpsm_read_strobe => eth_read_strobe,
zcpsm_in_port => eth_in_port
);
u_tx_buffer : disdram
generic map(
DEPTH => 2 ** BUFF_AWIDTH,
AWIDTH => BUFF_AWIDTH,
DWIDTH => 8
)
port map(
A => buff_waddr(BUFF_AWIDTH - 1 downto 0),
CLK => clk,
D => buff_wdata,
WE => buff_wren,
DPRA => buff_raddr(BUFF_AWIDTH - 1 downto 0),
DPO => buff_rdata,
QDPO => open
);
u_dma : dma_ctrl
generic map(
DWIDTH => 16,
RD_CYCLE => RD_CYCLE,
RD_DELAY => RD_DELAY,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
reset => reset,
ena => dma_ena,
start => dma_start,
length => dma_length_word,
start_waddr => (others => '0'),
start_raddr => dma_start_raddr,
wstep => X"01",
rstep => dma_rstep,
busy => dma_busy,
raddr => dma_raddr,
rdata => dma_rdata,
wren => dma_wren_word,
waddr => dma_waddr_word,
wdata => dma_wdata_word
);
----------
dma_length_word <= '0'&dma_length(15 downto 1);
--- process(reset, clk)
---- begin
-- if reset = '1' then
--- wren_byte <= '0';
-- elsif rising_edge(clk) then
-- if dma_wren_byte = '1' then
-- wren_byte <= dma_wren_byte;
-- buff_waddr <= dma_waddr_byte(BUFF_AWIDTH - 1 downto 1)&'0';
-- buff_wdata <= dma_wdata_byte(7 downto 0);
-- elsif flag = '1' then
-- buff_waddr <= dma_waddr_byte(BUFF_AWIDTH - 1 downto 1)&'1';
-- buff_wdata <= dma_wdata_byte(15 downto 8);
-- end if;
-- end if;
-- end process;
process(reset, clk)
begin
if reset = '1' then
buff_waddr_reg <= (others => '0');
buff_wdata_reg <= (others => '0');
dma_wren_reg <= '0';
elsif rising_edge(clk) then
if dma_wren_word = '1' then
buff_waddr_reg <= dma_waddr_word;
buff_wdata_reg <= dma_wdata_word;
end if;
dma_wren_reg <= dma_wren_word;
end if;
end process;
buff_waddr <= buff_waddr_reg(BUFF_AWIDTH - 2 downto 0)&'0' when dma_wren_reg = '1' else
buff_waddr_reg(BUFF_AWIDTH - 2 downto 0)&'1' ;
buff_wdata <= buff_wdata_reg(7 downto 0) when dma_wren_reg = '1' else
buff_wdata_reg(15 downto 8);
process(reset, clk)
begin
if reset = '1' then
flag <= '0';
elsif rising_edge(clk) then
-- if wren_byte = '1' then
flag <= dma_wren_reg;
-- end if;
end if;
end process;
buff_wren <= flag or dma_wren_reg;
ram_raddr <= dma_raddr;
dma_rdata <= ram_rdata;
-- buff_wren <= dma_wren;
-- buff_waddr <= dma_waddr(BUFF_AWIDTH - 1 downto 0);
-- buff_wdata <= dma_wdata;
buff_wr_diff <= buff_waddr - buff_raddr;
p_dma_ena : process(clk, reset)
begin
if reset = '1' then
dma_ena <= '1';
elsif rising_edge(clk) then
if buff_wr_diff >= 2 ** BUFF_AWIDTH - RD_CYCLE - RD_DELAY - 4 then
dma_ena <= '0';
elsif buff_wr_diff <= RD_CYCLE + RD_DELAY + 2 then
dma_ena <= '1';
end if;
end if;
end process;
end arch_ethtx;
| gpl-2.0 |
paulprozesky/shiny-octo-wookie | mkat/pfb_bb/pfb_core_snb.vhd | 1 | 600 | library IEEE;
use IEEE.std_logic_1164.all;
entity pfb_core_snb is
port (
ce_1: in std_logic;
clk_1: in std_logic;
en_in: in std_logic;
pol0_in: in std_logic_vector(35 downto 0);
pol1_in: in std_logic_vector(35 downto 0);
shift_in: in std_logic_vector(31 downto 0);
sync_in: in std_logic;
en_out: out std_logic;
of_out: out std_logic;
pol0_out: out std_logic_vector(35 downto 0);
pol1_out: out std_logic_vector(35 downto 0);
sync_out: out std_logic
);
end pfb_core_snb;
architecture structural of pfb_core_snb is
begin
end structural;
| gpl-2.0 |
EltonBroering/Estacionamento-Inteligente-com-portas-logicas | sensordeled.vhd | 1 | 17911 | -- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 32-bit"
-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
-- CREATED "Thu May 22 09:36:15 2014"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY sensordeled IS
PORT
(
Vaga1 : IN STD_LOGIC;
Vaga2 : IN STD_LOGIC;
Vaga3 : IN STD_LOGIC;
Vaga4 : IN STD_LOGIC;
Vaga5 : IN STD_LOGIC;
Vaga6 : IN STD_LOGIC;
Vaga7 : IN STD_LOGIC;
Vaga8 : IN STD_LOGIC;
Vaga9 : IN STD_LOGIC;
Vaga11 : IN STD_LOGIC;
Vaga10 : IN STD_LOGIC;
Vaga12 : IN STD_LOGIC;
Vaga13 : IN STD_LOGIC;
Vaga14 : IN STD_LOGIC;
Vaga15 : IN STD_LOGIC;
Vaga16 : IN STD_LOGIC;
Led_Vaga2 : OUT STD_LOGIC;
Led_Vaga3 : OUT STD_LOGIC;
Led_Vaga4 : OUT STD_LOGIC;
Led_Vaga5 : OUT STD_LOGIC;
Led_Vaga6 : OUT STD_LOGIC;
Led_Vaga7 : OUT STD_LOGIC;
Led_Vaga_Deficiente : OUT STD_LOGIC;
Led_Vaga8 : OUT STD_LOGIC;
Led_Vaga9 : OUT STD_LOGIC;
Led_Vaga10 : OUT STD_LOGIC;
Led_Vaga11 : OUT STD_LOGIC;
Led_Vaga12 : OUT STD_LOGIC;
Led_Vaga13 : OUT STD_LOGIC;
Led_Vaga14 : OUT STD_LOGIC;
Led_Vaga15 : OUT STD_LOGIC;
pin_name1 : OUT STD_LOGIC;
pin_name2 : OUT STD_LOGIC;
pin_name3 : OUT STD_LOGIC;
pin_name4 : OUT STD_LOGIC;
Led_Vaga1 : OUT STD_LOGIC
);
END sensordeled;
ARCHITECTURE bdf_type OF sensordeled IS
ATTRIBUTE black_box : BOOLEAN;
ATTRIBUTE noopt : BOOLEAN;
COMPONENT \74283_0\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_0\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_0\: COMPONENT IS true;
COMPONENT \74283_1\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_1\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_1\: COMPONENT IS true;
COMPONENT \74283_10\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_10\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_10\: COMPONENT IS true;
COMPONENT \74283_11\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_11\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_11\: COMPONENT IS true;
COMPONENT \74283_12\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_12\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_12\: COMPONENT IS true;
COMPONENT \74283_13\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_13\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_13\: COMPONENT IS true;
COMPONENT \74283_2\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_2\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_2\: COMPONENT IS true;
COMPONENT \74283_3\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_3\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_3\: COMPONENT IS true;
COMPONENT \74283_4\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_4\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_4\: COMPONENT IS true;
COMPONENT \74283_5\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_5\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_5\: COMPONENT IS true;
COMPONENT \74283_6\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_6\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_6\: COMPONENT IS true;
COMPONENT \74283_7\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_7\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_7\: COMPONENT IS true;
COMPONENT \74283_8\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_8\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_8\: COMPONENT IS true;
COMPONENT \74283_9\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_9\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_9\: COMPONENT IS true;
SIGNAL SYNTHESIZED_WIRE_118 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_10 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_119 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_17 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_18 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_21 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_25 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_26 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_28 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_29 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_120 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_33 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_34 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_36 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_37 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_41 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_42 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_44 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_45 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_121 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_49 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_50 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_52 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_53 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_56 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_58 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_59 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_61 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_62 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_122 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_66 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_67 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_69 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_70 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_74 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_75 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_77 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_78 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_123 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_82 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_83 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_85 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_86 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_90 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_91 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_93 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_94 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_124 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_98 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_99 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_101 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_102 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_106 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_107 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_109 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_110 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_113 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_114 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_115 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_116 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_117 : STD_LOGIC;
BEGIN
Led_Vaga2 <= Vaga2;
Led_Vaga3 <= Vaga3;
Led_Vaga4 <= Vaga4;
Led_Vaga5 <= Vaga5;
Led_Vaga6 <= Vaga6;
Led_Vaga7 <= Vaga7;
Led_Vaga_Deficiente <= Vaga16;
Led_Vaga8 <= Vaga8;
Led_Vaga9 <= Vaga9;
Led_Vaga10 <= Vaga10;
Led_Vaga11 <= Vaga11;
Led_Vaga12 <= Vaga12;
Led_Vaga13 <= Vaga13;
Led_Vaga14 <= Vaga14;
Led_Vaga15 <= Vaga15;
Led_Vaga1 <= Vaga1;
SYNTHESIZED_WIRE_7 <= '1';
SYNTHESIZED_WIRE_56 <= '1';
SYNTHESIZED_WIRE_113 <= '1';
SYNTHESIZED_WIRE_114 <= '1';
SYNTHESIZED_WIRE_115 <= '1';
SYNTHESIZED_WIRE_116 <= '1';
SYNTHESIZED_WIRE_117 <= '1';
b2v_inst : 74283_0
PORT MAP(CIN => SYNTHESIZED_WIRE_118,
A1 => Vaga1,
A2 => SYNTHESIZED_WIRE_118,
B2 => SYNTHESIZED_WIRE_118,
A3 => SYNTHESIZED_WIRE_118,
A4 => SYNTHESIZED_WIRE_118,
B4 => SYNTHESIZED_WIRE_118,
B1 => Vaga2,
B3 => SYNTHESIZED_WIRE_118,
SUM4 => SYNTHESIZED_WIRE_13,
SUM1 => SYNTHESIZED_WIRE_9,
SUM2 => SYNTHESIZED_WIRE_10,
SUM3 => SYNTHESIZED_WIRE_12);
SYNTHESIZED_WIRE_118 <= NOT(SYNTHESIZED_WIRE_7);
b2v_inst14 : 74283_1
PORT MAP(CIN => SYNTHESIZED_WIRE_118,
A1 => SYNTHESIZED_WIRE_9,
A2 => SYNTHESIZED_WIRE_10,
B2 => SYNTHESIZED_WIRE_118,
A3 => SYNTHESIZED_WIRE_12,
A4 => SYNTHESIZED_WIRE_13,
B4 => SYNTHESIZED_WIRE_118,
B1 => Vaga3,
B3 => SYNTHESIZED_WIRE_118,
SUM4 => SYNTHESIZED_WIRE_21,
SUM1 => SYNTHESIZED_WIRE_17,
SUM2 => SYNTHESIZED_WIRE_18,
SUM3 => SYNTHESIZED_WIRE_20);
b2v_inst15 : 74283_2
PORT MAP(CIN => SYNTHESIZED_WIRE_119,
A1 => SYNTHESIZED_WIRE_17,
A2 => SYNTHESIZED_WIRE_18,
B2 => SYNTHESIZED_WIRE_119,
A3 => SYNTHESIZED_WIRE_20,
A4 => SYNTHESIZED_WIRE_21,
B4 => SYNTHESIZED_WIRE_119,
B1 => Vaga4,
B3 => SYNTHESIZED_WIRE_119,
SUM4 => SYNTHESIZED_WIRE_29,
SUM1 => SYNTHESIZED_WIRE_25,
SUM2 => SYNTHESIZED_WIRE_26,
SUM3 => SYNTHESIZED_WIRE_28);
b2v_inst16 : 74283_3
PORT MAP(CIN => SYNTHESIZED_WIRE_119,
A1 => SYNTHESIZED_WIRE_25,
A2 => SYNTHESIZED_WIRE_26,
B2 => SYNTHESIZED_WIRE_119,
A3 => SYNTHESIZED_WIRE_28,
A4 => SYNTHESIZED_WIRE_29,
B4 => SYNTHESIZED_WIRE_119,
B1 => Vaga5,
B3 => SYNTHESIZED_WIRE_119,
SUM4 => SYNTHESIZED_WIRE_37,
SUM1 => SYNTHESIZED_WIRE_33,
SUM2 => SYNTHESIZED_WIRE_34,
SUM3 => SYNTHESIZED_WIRE_36);
b2v_inst17 : 74283_4
PORT MAP(CIN => SYNTHESIZED_WIRE_120,
A1 => SYNTHESIZED_WIRE_33,
A2 => SYNTHESIZED_WIRE_34,
B2 => SYNTHESIZED_WIRE_120,
A3 => SYNTHESIZED_WIRE_36,
A4 => SYNTHESIZED_WIRE_37,
B4 => SYNTHESIZED_WIRE_120,
B1 => Vaga6,
B3 => SYNTHESIZED_WIRE_120,
SUM4 => SYNTHESIZED_WIRE_45,
SUM1 => SYNTHESIZED_WIRE_41,
SUM2 => SYNTHESIZED_WIRE_42,
SUM3 => SYNTHESIZED_WIRE_44);
b2v_inst18 : 74283_5
PORT MAP(CIN => SYNTHESIZED_WIRE_120,
A1 => SYNTHESIZED_WIRE_41,
A2 => SYNTHESIZED_WIRE_42,
B2 => SYNTHESIZED_WIRE_120,
A3 => SYNTHESIZED_WIRE_44,
A4 => SYNTHESIZED_WIRE_45,
B4 => SYNTHESIZED_WIRE_120,
B1 => Vaga7,
B3 => SYNTHESIZED_WIRE_120,
SUM4 => SYNTHESIZED_WIRE_53,
SUM1 => SYNTHESIZED_WIRE_49,
SUM2 => SYNTHESIZED_WIRE_50,
SUM3 => SYNTHESIZED_WIRE_52);
b2v_inst19 : 74283_6
PORT MAP(CIN => SYNTHESIZED_WIRE_121,
A1 => SYNTHESIZED_WIRE_49,
A2 => SYNTHESIZED_WIRE_50,
B2 => SYNTHESIZED_WIRE_121,
A3 => SYNTHESIZED_WIRE_52,
A4 => SYNTHESIZED_WIRE_53,
B4 => SYNTHESIZED_WIRE_121,
B1 => Vaga8,
B3 => SYNTHESIZED_WIRE_121,
SUM4 => SYNTHESIZED_WIRE_62,
SUM1 => SYNTHESIZED_WIRE_58,
SUM2 => SYNTHESIZED_WIRE_59,
SUM3 => SYNTHESIZED_WIRE_61);
SYNTHESIZED_WIRE_119 <= NOT(SYNTHESIZED_WIRE_56);
b2v_inst20 : 74283_7
PORT MAP(CIN => SYNTHESIZED_WIRE_121,
A1 => SYNTHESIZED_WIRE_58,
A2 => SYNTHESIZED_WIRE_59,
B2 => SYNTHESIZED_WIRE_121,
A3 => SYNTHESIZED_WIRE_61,
A4 => SYNTHESIZED_WIRE_62,
B4 => SYNTHESIZED_WIRE_121,
B1 => Vaga9,
B3 => SYNTHESIZED_WIRE_121,
SUM4 => SYNTHESIZED_WIRE_70,
SUM1 => SYNTHESIZED_WIRE_66,
SUM2 => SYNTHESIZED_WIRE_67,
SUM3 => SYNTHESIZED_WIRE_69);
b2v_inst21 : 74283_8
PORT MAP(CIN => SYNTHESIZED_WIRE_122,
A1 => SYNTHESIZED_WIRE_66,
A2 => SYNTHESIZED_WIRE_67,
B2 => SYNTHESIZED_WIRE_122,
A3 => SYNTHESIZED_WIRE_69,
A4 => SYNTHESIZED_WIRE_70,
B4 => SYNTHESIZED_WIRE_122,
B1 => Vaga10,
B3 => SYNTHESIZED_WIRE_122,
SUM4 => SYNTHESIZED_WIRE_78,
SUM1 => SYNTHESIZED_WIRE_74,
SUM2 => SYNTHESIZED_WIRE_75,
SUM3 => SYNTHESIZED_WIRE_77);
b2v_inst22 : 74283_9
PORT MAP(CIN => SYNTHESIZED_WIRE_122,
A1 => SYNTHESIZED_WIRE_74,
A2 => SYNTHESIZED_WIRE_75,
B2 => SYNTHESIZED_WIRE_122,
A3 => SYNTHESIZED_WIRE_77,
A4 => SYNTHESIZED_WIRE_78,
B4 => SYNTHESIZED_WIRE_122,
B1 => Vaga11,
B3 => SYNTHESIZED_WIRE_122,
SUM4 => SYNTHESIZED_WIRE_86,
SUM1 => SYNTHESIZED_WIRE_82,
SUM2 => SYNTHESIZED_WIRE_83,
SUM3 => SYNTHESIZED_WIRE_85);
b2v_inst23 : 74283_10
PORT MAP(CIN => SYNTHESIZED_WIRE_123,
A1 => SYNTHESIZED_WIRE_82,
A2 => SYNTHESIZED_WIRE_83,
B2 => SYNTHESIZED_WIRE_123,
A3 => SYNTHESIZED_WIRE_85,
A4 => SYNTHESIZED_WIRE_86,
B4 => SYNTHESIZED_WIRE_123,
B1 => Vaga12,
B3 => SYNTHESIZED_WIRE_123,
SUM4 => SYNTHESIZED_WIRE_94,
SUM1 => SYNTHESIZED_WIRE_90,
SUM2 => SYNTHESIZED_WIRE_91,
SUM3 => SYNTHESIZED_WIRE_93);
b2v_inst24 : 74283_11
PORT MAP(CIN => SYNTHESIZED_WIRE_123,
A1 => SYNTHESIZED_WIRE_90,
A2 => SYNTHESIZED_WIRE_91,
B2 => SYNTHESIZED_WIRE_123,
A3 => SYNTHESIZED_WIRE_93,
A4 => SYNTHESIZED_WIRE_94,
B4 => SYNTHESIZED_WIRE_123,
B1 => Vaga13,
B3 => SYNTHESIZED_WIRE_123,
SUM4 => SYNTHESIZED_WIRE_102,
SUM1 => SYNTHESIZED_WIRE_98,
SUM2 => SYNTHESIZED_WIRE_99,
SUM3 => SYNTHESIZED_WIRE_101);
b2v_inst25 : 74283_12
PORT MAP(CIN => SYNTHESIZED_WIRE_124,
A1 => SYNTHESIZED_WIRE_98,
A2 => SYNTHESIZED_WIRE_99,
B2 => SYNTHESIZED_WIRE_124,
A3 => SYNTHESIZED_WIRE_101,
A4 => SYNTHESIZED_WIRE_102,
B4 => SYNTHESIZED_WIRE_124,
B1 => Vaga14,
B3 => SYNTHESIZED_WIRE_124,
SUM4 => SYNTHESIZED_WIRE_110,
SUM1 => SYNTHESIZED_WIRE_106,
SUM2 => SYNTHESIZED_WIRE_107,
SUM3 => SYNTHESIZED_WIRE_109);
b2v_inst26 : 74283_13
PORT MAP(CIN => SYNTHESIZED_WIRE_124,
A1 => SYNTHESIZED_WIRE_106,
A2 => SYNTHESIZED_WIRE_107,
B2 => SYNTHESIZED_WIRE_124,
A3 => SYNTHESIZED_WIRE_109,
A4 => SYNTHESIZED_WIRE_110,
B4 => SYNTHESIZED_WIRE_124,
B1 => Vaga15,
B3 => SYNTHESIZED_WIRE_124,
SUM4 => pin_name4,
SUM1 => pin_name1,
SUM2 => pin_name2,
SUM3 => pin_name3);
SYNTHESIZED_WIRE_120 <= NOT(SYNTHESIZED_WIRE_113);
SYNTHESIZED_WIRE_121 <= NOT(SYNTHESIZED_WIRE_114);
SYNTHESIZED_WIRE_122 <= NOT(SYNTHESIZED_WIRE_115);
SYNTHESIZED_WIRE_123 <= NOT(SYNTHESIZED_WIRE_116);
SYNTHESIZED_WIRE_124 <= NOT(SYNTHESIZED_WIRE_117);
END bdf_type; | gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_sa1_test2.vhd | 8 | 2573 | library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic);
end component fa1;
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic);
end component;
-- doing nothing at the moment
constant N: integer range 0 to 16 := 4;
end package work6;
-- a 1-bit Moore-type adder to be used in
-- a serial adder FSM-driven architecture
-- ________ _____
-- a_i -->| |------>|D Q|---> s_o
-- b_i -->| FA1 | | |
-- | |--- | |
-- ---> |_______| | |_____|
--rst __|_______________________|
-- | | |
-- | | |
-- | | | ______
-- | | ---->|D Q|---
-- | | | | |
-- | | | | |
-- | | |_____| |
-- | |____________| |
-- |________________________________|
--
library ieee;
use ieee.std_logic_1164.all;
use work.work6.all;
entity sa1 is
port (clk, reset: in std_logic;
a_i, b_i: in std_logic;
s_o: out std_logic
);
end entity sa1;
architecture sa1_rtl of sa1 is
signal sum, carry, carry_reg: std_logic;
begin
a1: fa1 port map (c_i => carry_reg,
a_i => a_i,
b_i => b_i,
s_o => sum,
c_o => carry
);
f1: fdc port map (clk => clk, reset => reset, d => sum, q => s_o);
f2: fdc port map (clk => clk, reset => reset, d => carry, q => carry_reg);
end architecture sa1_rtl;
-- a one bit full adder written according to
-- textbook's boolean equations
library ieee;
use ieee.std_logic_1164.all;
entity fa1 is
port (a_i, b_i, c_i: in std_logic;
s_o, c_o: out std_logic
);
end entity fa1;
architecture fa1_rtl of fa1 is
begin
s_o <= a_i xor b_i xor c_i;
c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
end architecture fa1_rtl;-- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end fdc_rtl;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_const_array.vhd | 3 | 1946 | -- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for constant arrays access
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constant_array_pkg.all;
entity constant_array is
port (index : in std_logic_vector(2 downto 0);
output : out std_logic_vector(7 downto 0));
end entity constant_array;
architecture test of constant_array is
type logic_array is array (integer range <>) of std_logic_vector(0 to 3);
constant test_array : logic_array(0 to 5) :=
(0 => "0010",
1 => "1000",
2 => "0100",
3 => "0110",
4 => "0101",
5 => "1100");
-- Check if constant vectors are not broken with the changes
constant vector : std_logic_vector(5 downto 0) := "110011";
signal test_a : unsigned(7 downto 0);
signal test_b : std_logic_vector(3 downto 0);
signal test_c : std_logic_vector(2 downto 0);
signal test_d : std_logic;
begin
test_a <= const_array(3);
test_b <= test_array(2);
test_c <= vector(4 downto 2);
test_d <= vector(5);
process (index)
begin
output <= const_array(to_integer(unsigned(index)));
end process;
end architecture test;
| gpl-2.0 |
bmazin/SDR | Firmware/dac_mkid_files/dac_mkid_interface_v1_01_a/hdl/vhdl/dac_mkid_interface.vhd | 1 | 10505 | ----------------------------------------------------------------------------------
-- dac_mkid_interface : DAC board with two DAC5681 for I and Q signals
----------------------------------------------------------------------------------
-- Authors: Sean McHugh, Bruno Serfass, Ran Duan
-- Create Date: 09/02/09
-- modification:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity section
--------------------------------------------------------------------------------
entity dac_mkid_interface is
Generic (
OUTPUT_CLK : INTEGER := 0;
CTRL_CLK_PHASE : INTEGER := 0
);
Port (
--------------------------------------
-- differential signals from/to DAC
--------------------------------------
-- clock from DAC
dac_clk_p : in STD_LOGIC;
dac_clk_n : in STD_LOGIC;
-- clock to DAC
dac_smpl_clk_i_p : out STD_LOGIC;
dac_smpl_clk_i_n : out STD_LOGIC;
dac_smpl_clk_q_p : out STD_LOGIC;
dac_smpl_clk_q_n : out STD_LOGIC;
-- enable analog output for DAC
dac_sync_i_p : out STD_LOGIC;
dac_sync_i_n : out STD_LOGIC;
dac_sync_q_p : out STD_LOGIC;
dac_sync_q_n : out STD_LOGIC;
-- data written to DAC
dac_data_i_p : out STD_LOGIC_VECTOR (15 downto 0);
dac_data_i_n : out STD_LOGIC_VECTOR (15 downto 0);
dac_data_q_p : out STD_LOGIC_VECTOR (15 downto 0);
dac_data_q_n : out STD_LOGIC_VECTOR (15 downto 0);
-- configuration ports of DAC
dac_not_sdenb_i : out STD_LOGIC;
dac_not_sdenb_q : out STD_LOGIC;
dac_sclk : out STD_LOGIC;
dac_sdi : out STD_LOGIC;
dac_not_reset : out STD_LOGIC;
-- dac_phase : in STD_LOGIC;
--------------------------------------
-- signals from/to design
--------------------------------------
-- defined in xps_dac_mkid.m
dac_smpl_clk : in STD_LOGIC;
-- defined in dac_mkid yellow block and dac_mkid_mask.m
dac_data_i0 : in STD_LOGIC_VECTOR (15 downto 0);
dac_data_i1 : in STD_LOGIC_VECTOR (15 downto 0);
dac_data_q0 : in STD_LOGIC_VECTOR (15 downto 0);
dac_data_q1 : in STD_LOGIC_VECTOR (15 downto 0);
dac_sync_i : in STD_LOGIC;
dac_sync_q : in STD_LOGIC;
-- serial ports
not_sdenb_i : in STD_LOGIC;
not_sdenb_q : in STD_LOGIC;
sclk : in STD_LOGIC;
sdi : in STD_LOGIC;
not_reset : in STD_LOGIC;
-- phase : out STD_LOGIC
-- clock to FPGA
dac_clk_out : out STD_LOGIC;
dac_clk90_out : out STD_LOGIC;
dac_clk180_out : out STD_LOGIC;
dac_clk270_out : out STD_LOGIC;
-- dcm lock
dac_dcm_locked : out STD_LOGIC
);
end dac_mkid_interface;
--------------------------------------------------------------------------------
-- Architecture section
--------------------------------------------------------------------------------
architecture Structural of dac_mkid_interface is
signal data_i : STD_LOGIC_VECTOR (15 downto 0);
signal data_q : STD_LOGIC_VECTOR (15 downto 0);
signal smpl_clk : STD_LOGIC;
signal dac_clk_in : STD_LOGIC;
signal dac_clk : STD_LOGIC;
signal dcm_clk : STD_LOGIC;
signal dcm_clk90 : STD_LOGIC;
signal dcm_clk180 : STD_LOGIC;
signal dcm_clk270 : STD_LOGIC;
signal clk : STD_LOGIC;
signal clk90 : STD_LOGIC;
signal clk180 : STD_LOGIC;
signal clk270 : STD_LOGIC;
begin
-----------------------------------------------------------------------
-- Serial input (DAC configuration)
-----------------------------------------------------------------------
OBUF_inst_not_sdenb_i : OBUF
generic map (
IOSTANDARD => "DEFAULT")
Port map (
O => dac_not_sdenb_i,
I => not_sdenb_i
);
OBUF_inst_not_sdenb_q : OBUF
generic map (
IOSTANDARD => "DEFAULT")
Port map (
O => dac_not_sdenb_q,
I => not_sdenb_q
);
OBUF_inst_sclk : OBUF
generic map (
IOSTANDARD => "DEFAULT")
Port map (
O => dac_sclk,
I => sclk
);
OBUF_inst_sdi : OBUF
generic map (
IOSTANDARD => "DEFAULT")
Port map (
O => dac_sdi,
I => sdi
);
OBUF_inst_not_reset : OBUF
generic map (
IOSTANDARD => "DEFAULT")
Port map (
O => dac_not_reset,
I => not_reset
);
-------------------------------------------------------------------
-- Sample clock in to DAC. "dac_smpl_clk_i_p/n" is a DDR clock. --
-------------------------------------------------------------------
BUFG_inst : BUFG
port map (O => smpl_clk,I => dac_smpl_clk);
OBUFDS_inst_smpl_clk_i : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_smpl_clk_i_p,
OB => dac_smpl_clk_i_n,
I => smpl_clk
);
OBUFDS_inst_smpl_clk_q : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_smpl_clk_q_p,
OB => dac_smpl_clk_q_n,
I => smpl_clk
);
----------------------------------
-- Enable analog output for DAC --
----------------------------------
OBUFDS_inst_dac_sync_i : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_sync_i_p,
OB => dac_sync_i_n,
I => dac_sync_i
);
OBUFDS_inst_dac_sync_q : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_sync_q_p,
OB => dac_sync_q_n,
I => dac_sync_q
);
-----------------------------------------------------------------------
-- DAC data outputs
-- Requires an ODDR to double the data rate, and an
-- OBUFDS to convert to differential signal.
-----------------------------------------------------------------------
-- DAC output I --
ODDR_inst_generate_data_i : for j in 0 to 15 generate
ODDR_inst_data_i : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map (
Q => data_i(j),
C => smpl_clk,
CE => '1',
D1 => dac_data_i0(j),
D2 => dac_data_i1(j),
R => '0',
S => '0'
);
end generate;
OBUFDS_inst_generate_data_i : for j in 0 to 15 generate
OBUFDS_inst_data1_i : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_data_i_p(j),
OB => dac_data_i_n(j),
I => data_i(j)
);
end generate;
-- DAC output Q --
ODDR_inst_generate_data_q : for j in 0 to 15 generate
ODDR_inst_data_q : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map (
Q => data_q(j),
C => smpl_clk,
CE => '1',
D1 => dac_data_q0(j),
D2 => dac_data_q1(j),
R => '0',
S => '0'
);
end generate;
OBUFDS_inst_generate_data1_q : for j in 0 to 15 generate
OBUFDS_inst_data1_q : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_data_q_p(j),
OB => dac_data_q_n(j),
I => data_q(j)
);
end generate;
-----------------------------------------------------------------------
-- Clock Management
-----------------------------------------------------------------------
GEN_DCM : if OUTPUT_CLK = 1 generate
IBUFDS_inst_dac_clk : IBUFGDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_clk_in,
I => dac_clk_p,
IB => dac_clk_n
);
BUFG_clk_dac : BUFG
port map (I => dac_clk_in, O => dac_clk);
BUFG_clk : BUFG
port map (I => dcm_clk, O => clk);
BUFG_clk90 : BUFG
port map (I => dcm_clk90, O => clk90);
BUFG_clk180 : BUFG
port map (I => dcm_clk180, O => clk180);
BUFG_clk270 : BUFG
port map (I => dcm_clk270, O => clk270);
-- out clock to fpga
dac_clk_out <= clk;
dac_clk90_out <= clk90;
dac_clk180_out <= clk180;
dac_clk270_out <= clk270;
-- DCM
CLK_DCM : DCM
generic map(
CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.000000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 0.000000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "HIGH",
DLL_FREQUENCY_MODE => "HIGH",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"F0F0",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (
CLKFB => clk,
CLKIN => dac_clk,
DSSEN => '0',
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
RST => '0',
CLKDV => open,
CLKFX => open,
CLKFX180 => open,
CLK0 => dcm_clk,
CLK2X => open,
CLK2X180 => open,
CLK90 => dcm_clk90,
CLK180 => dcm_clk180,
CLK270 => dcm_clk270,
LOCKED => dac_dcm_locked,
PSDONE => open,
STATUS => open
);
end generate;
end Structural;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/work7b/timebase.vhd | 8 | 1393 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- The operation is:
-- 1) An internal counter (of 25 bits) is initilaised to zero after a reset is received.
-- 2) An enable allows an internal running counter to count clock pulses
-- 3) A tick signal output is generated when a count of 20000000 pulses has been accumulated
entity TimeBase is
port(
CLOCK : in std_logic; -- input clock of 20MHz
TICK : out std_logic; -- out 1 sec timebase signal
RESET : in std_logic; -- master reset signal (active high)
ENABLE : in std_logic;
COUNT_VALUE: out std_logic_vector (24 downto 0)
);
end TimeBase;
architecture TimeBase_rtl of TimeBase is
constant DIVIDER_VALUE : std_logic_vector := x"7cf"; -- 20000000 count value, 1 second
signal RunningCounter : std_logic_vector(24 downto 0); -- this is the 25 bit free running counter to allow a big count
begin
RunningCounterProcess : process (CLOCK)
begin
if ( CLOCK'event and CLOCK = '1') then
if (RESET = '1') then
RunningCounter <= '0' & x"000000";
elsif ( ENABLE = '1') then
RunningCounter <= RunningCounter + 1;
end if;
else
RunningCounter <= RunningCounter;
end if;
end process;
TICK <= '1' when (RunningCounter = DIVIDER_VALUE) else '0';
COUNT_VALUE <= RunningCounter;
end TimeBase_rtl;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_unary_minus.vhd | 2 | 1254 | -- Copyright (c) 2016 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and-or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Unary minus operator test
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vhdl_unary_minus is
port(data_in : in signed(7 downto 0);
clk : in std_logic;
data_out : out signed(7 downto 0)
);
end vhdl_unary_minus;
architecture test of vhdl_unary_minus is
begin
process(clk)
begin
if rising_edge(clk) then
data_out <= -data_in;
end if;
end process;
end test;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_norg_stdlogic.vhd | 4 | 295 | library IEEE;
use IEEE.std_logic_1164.all;
entity nor_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity nor_gate;
architecture rtl of nor_gate is
begin
c_o <= a_i nor b_i;
end architecture rtl;
| gpl-2.0 |
shiqianmiao/mydoxygen_source | examples/mux.vhdl | 37 | 860 | -------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architecture definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_range_func.vhd | 3 | 1466 | -- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for 'range, 'left and 'right attributes in VHDL subprograms.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.range_func_pkg.all;
entity range_func is
end range_func;
architecture test of range_func is
signal neg_inp : std_logic_vector(3 downto 0);
signal neg_out : std_logic_vector(3 downto 0);
signal rev_inp : std_logic_vector(3 downto 0);
signal rev_out : std_logic_vector(3 downto 0);
begin
neg_inp <= "1100";
rev_inp <= "1000";
process(neg_inp)
begin
neg_out <= negator(neg_inp);
end process;
process(rev_inp)
begin
rev_out <= reverse(rev_inp);
end process;
end test;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/br986.vhd | 2 | 845 | -- Reduced test case, bug originally found in 4DSP's fmc110_ctrl.vhd
library ieee;
use ieee.std_logic_1164.all;
entity bug3 is
port (
clk1_i : in std_logic;
clk1_ib : in std_logic;
clk1_o : out std_logic
);
end bug3;
architecture bug3_syn of bug3 is
component IBUFDS generic (
DIFF_TERM : boolean := FALSE
); port(
O : out std_logic;
I : in std_logic;
IB : in std_logic
); end component;
begin
ibufds1 : ibufds
generic map (
DIFF_TERM => TRUE -- change to "1" and vhdlpp is happy
)
port map (
i => clk1_i,
ib => clk1_ib,
o => clk1_o
);
end bug3_syn;
entity ibufds is
generic (
DIFF_TERM : boolean := FALSE
);
port (
i : in std_logic;
ib : in std_logic;
o : out std_logic
);
end ibufds;
architecture ibufds_sim of ibufds is
begin
o <= i;
end ibufds_sim;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_time.vhd | 3 | 2038 | -- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for time related expressions.
library ieee;
use ieee.std_logic_1164.all;
use work.time_pkg.all;
entity vhdl_time is
port(a : out std_logic;
b : in std_logic;
tout : out time;
tin : in time);
end vhdl_time;
architecture test of vhdl_time is
signal time_sig : time_subtype := 100 ns;
begin
tout <= 140 ns;
process(b)
variable time_var : time;
begin
if(rising_edge(b)) then
time_var := 100 ns;
time_sig := 500 ns;
a := '0';
wait for 50 ns;
a := '1';
wait for time_sig; -- signal
a := '0';
wait for time_const; -- constant
a := '1';
wait for time_var; -- variable
a := '0';
wait for (time_sig + time_const + time_var);
a := '1';
-- Modify variable & signal values
time_var := 10 ns;
wait for time_var;
a := '0';
time_sig := 20 ns;
wait for time_sig;
a := '1';
-- Test time read from port
wait for tin;
a := '0';
end if;
end process;
end test;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_to_integer.vhd | 3 | 1282 | -- Copyright (c) 2014 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for to_integer() function.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity to_int is
port (
unsign : in unsigned(7 downto 0);
sign : in signed(7 downto 0)
);
end to_int;
architecture test of to_int is
signal s_natural : natural;
signal s_integer : integer;
begin
process (unsign)
begin
s_natural <= (unsign);
end process;
process (sign)
begin
s_integer <= (sign);
end process;
end test;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/work7/work7-pkg.vhd | 8 | 579 | library ieee;
use ieee.std_logic_1164.all;
package work7 is
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic);
end component;
component TimeBase is
port(
CLOCK : in std_logic; -- input clock of 20MHz
TICK : out std_logic; -- out 1 sec timebase signal
RESET : in std_logic; -- master reset signal (active high)
ENABLE : in std_logic;
COUNT_VALUE: out std_logic_vector (24 downto 0)
);
end component;
end package work7;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_uadd23_stdlogic.vhd | 4 | 310 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uadd23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity uadd23;
architecture rtl of uadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
| gpl-2.0 |
huxiaolei/xapp1078_2014.4_zybo | design/work/project_2/project_2.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/7820e39a/hdl/src/vhdl/upcnt_n.vhd | 44 | 7144 | -------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/work14_pkg.vhd | 4 | 667 |
library ieee;
use ieee.std_logic_1164.all;
package work14_pkg is
function f_log2_size (
A : natural)
return natural;
component work14_comp
generic (
max_out_val : natural;
sample_parm : string);
port (
clk_i : in std_logic;
val : out std_logic_vector(f_log2_size(max_out_val)-1 downto 0));
end component;
end work14_pkg;
package body work14_pkg is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
end work14_pkg;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_uadd23_bit.vhd | 4 | 281 | library ieee;
use ieee.numeric_bit.all;
entity uadd23 is
port (
a_i : in unsigned (22 downto 0);
b_i : in unsigned (22 downto 0);
c_o : out unsigned (22 downto 0)
);
end entity uadd23;
architecture rtl of uadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_unbounded_func.vhd | 3 | 1953 | -- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Basic test for functions that work with unbounded vectors as return
-- and param types.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vhdl_unbounded_func_pkg.all;
package included_pkg is
function negator(word_i : std_logic_vector) return std_logic_vector;
end included_pkg;
package body included_pkg is
function negator(word_i : std_logic_vector) return std_logic_vector is
variable word_o : std_logic_vector (word_i'left downto word_i'right);
begin
for I in word_i'range loop
word_o (I) := not word_i(I);
end loop;
return word_o;
end function;
end included_pkg;
entity vhdl_unbounded_func is
end vhdl_unbounded_func;
architecture test of vhdl_unbounded_func is
signal test_out1 : std_logic_vector(9 downto 0);
signal test_out2 : std_logic_vector(5 downto 0);
signal neg_test_out1 : std_logic_vector(9 downto 0);
signal neg_test_out2 : std_logic_vector(5 downto 0);
begin
test_out1 <= f_manch_encoder(B"11101");
test_out2 <= f_manch_encoder(B"001");
neg_test_out1 <= negator(test_out1);
neg_test_out2 <= negator(test_out2);
end test;
| gpl-2.0 |
steveicarus/iverilog | ivtest/ivltests/vhdl_signals.vhd | 4 | 988 | -- This VHDL was converted from Verilog using the
-- Icarus Verilog VHDL Code Generator 0.10.0 (devel) (s20090923-656-gce5c263)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Generated from Verilog module test (foo.v:3)
entity test is
port (
i : in unsigned(3 downto 0);
o : out std_logic
);
end entity;
-- Generated from Verilog module test (foo.v:3)
architecture from_verilog of test is
signal tmp_s1 : std_logic; -- Temporary created at foo.v:6
signal tmp_s11 : std_logic; -- Temporary created at foo.v:6
signal tmp_s3 : std_logic; -- Temporary created at foo.v:6
signal tmp_s4 : std_logic; -- Temporary created at foo.v:6
signal tmp_s7 : std_logic; -- Temporary created at foo.v:6
signal tmp_s8 : std_logic; -- Temporary created at foo.v:6
begin
tmp_s4 <= tmp_s1 and tmp_s3;
tmp_s8 <= tmp_s4 and tmp_s7;
o <= tmp_s8 and tmp_s11;
tmp_s1 <= i(3);
tmp_s3 <= i(2);
tmp_s7 <= i(1);
tmp_s11 <= i(0);
end architecture;
| gpl-2.0 |
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