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emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc408.vhd | 4 | 2987 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc408.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00408ent IS
END c03s02b01x01p19n01i00408ent;
ARCHITECTURE c03s02b01x01p19n01i00408arch OF c03s02b01x01p19n01i00408ent IS
constant C1 : character := 's';
function complex_scalar(s : character) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return character is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : character;
signal S2 : character;
signal S3 : character := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00408"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00408 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00408arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_pll.vhd | 4 | 2589 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
-- File : C:\VHDL-AMS\CaseStudies\CS4_CommSystem\Default\genhdl\vhdl\tb_pll.vhd
-- CDB : C:\VHDL-AMS\CaseStudies\CS4_CommSystem\default\default.cdb
-- By : CDB2VHDL Netlister version 16.1.0.2
-- Time : Fri Apr 05 12:08:46 2002
-- Entity/architecture declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.fluidic_systems.all;
use IEEE_proposed.thermal_systems.all;
use IEEE_proposed.radiant_systems.all;
entity tb_pll is
end tb_pll;
architecture tb_pll of tb_pll is
-- Component declarations
-- Signal declarations
signal f_ref : real;
terminal lf_out : electrical;
terminal v_ref : electrical;
signal vco_f : real;
terminal vco_out : electrical;
begin
-- Signal assignments
-- Component instances
PLL6 : entity work.PLL(behavioral)
generic map(
Fp => 20.0e3,
Fz => 1.0e6,
Kv => 100.0e3,
Fc => 1.0e6
)
port map(
input => v_ref,
lf_out => lf_out,
vco_out => vco_out
);
v1 : entity work.v_SweptSine(bhv)
generic map(
StartFreq => 900.0e3,
SweepRate => 2000.0e6,
FinishFreq => 1.1e6,
InitDelay => 80.0e-6,
PeakAmp => 5.0
)
port map(
pos => v_ref,
neg => ELECTRICAL_REF
);
MeasFreq9 : entity work.MeasFreq(ThresDetect)
port map(
input => v_ref,
f_out => f_ref
);
MeasFreq10 : entity work.MeasFreq(ThresDetect)
port map(
input => vco_out,
f_out => vco_f
);
end tb_pll;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_04.vhd | 4 | 1792 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_ch_18_04.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_18_04 is
end entity ch_18_04;
----------------------------------------------------------------
architecture test of ch_18_04 is
begin
process is
type data_file_type is file of character;
variable ch : character;
-- code from book:
procedure write_to_file is
file data_file : data_file_type open write_mode is "datafile";
begin
-- . . .
-- not in book
write(data_file, ch);
-- end not in book
end procedure write_to_file;
-- end of code from book
begin
ch := 'A';
write_to_file;
ch := 'B';
write_to_file;
ch := 'C';
write_to_file;
wait;
end process;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc150.vhd | 4 | 2196 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc150.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p14n01i00150ent IS
END c04s03b02x02p14n01i00150ent;
ARCHITECTURE c04s03b02x02p14n01i00150arch OF c04s03b02x02p14n01i00150ent IS
FUNCTION FLOAT ( ival : in integer) return real is
VARIABLE v1 : real := 543.0;
begin
RETURN v1;
end FLOAT;
FUNCTION ROUND ( rval : in real) return integer is
VARIABLE v1 : integer := 543;
begin
RETURN v1;
end ROUND;
PROCEDURE test_bed
( in1 : in integer;
out1 : out real )
is
begin
out1 := FLOAT (in1);
end test_bed;
BEGIN
TESTING: PROCESS
VARIABLE var1 : real;
VARIABLE var2 : real := 543.2;
BEGIN
test_bed ( ROUND (var2), var1 );
assert NOT( var1 = 543.0 )
report "***PASSED TEST:c04s03b02x02p14n01i00150"
severity NOTE;
assert ( var1 = 543.0 )
report "***FAILED TEST:c04s03b02x02p14n01i00150 - The actual part of a named element association may be in the form of a function call."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p14n01i00150arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc535.vhd | 4 | 1828 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc535.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p05n01i00535ent IS
END c03s03b00x00p05n01i00535ent;
ARCHITECTURE c03s03b00x00p05n01i00535arch OF c03s03b00x00p05n01i00535ent IS
type b is access BIT_VECTOR(0 to 10); -- Success_here
BEGIN
TESTING: PROCESS
variable k : b;
BEGIN
assert NOT(k=null)
report "***PASSED TEST: c03s03b00x00p05n01i00535"
severity NOTE;
assert ( k=null )
report "***FAILED TEST: c03s03b00x00p05n01i00535 - The only form of constraint that is allowed after the name of an access type in a subtype indication is an index constraint."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p05n01i00535arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2745.vhd | 4 | 1882 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2745.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s06b00x00p10n01i02745ent IS
END c13s06b00x00p10n01i02745ent;
ARCHITECTURE c13s06b00x00p10n01i02745arch OF c13s06b00x00p10n01i02745ent IS
constant mystring : string := "This string has too " &
"many characters.";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( mystring="This string has too many characters." )
report "***PASSED TEST: c13s06b00x00p10n01i02745"
severity NOTE;
assert ( mystring="This string has too many characters." )
report "***FAILED TEST: c13s06b00x00p10n01i02745 - Use of & as a continuation for a string test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s06b00x00p10n01i02745arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_27.vhd | 4 | 1329 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_27.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_27 is
end entity ch_05_27;
library wasp_lib;
-- code from book:
use wasp_lib.all;
-- end of code from book
architecture test of ch_05_27 is
signal clk, filter_clk : bit;
begin
clk_pad : entity wasp_lib.in_pad
port map ( i => clk, z => filter_clk );
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1793.vhd | 4 | 2043 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1793.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s07b00x00p06n02i01793ent IS
END c09s07b00x00p06n02i01793ent;
ARCHITECTURE c09s07b00x00p06n02i01793arch OF c09s07b00x00p06n02i01793ent IS
type Day is (Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday);
procedure i_proof_1 (x : integer) is
begin
end i_proof_1;
procedure i_proof_2 (x : character) is
begin
end i_proof_2;
procedure i_proof_3 (x : Day) is
begin
end i_proof_3;
BEGIN
glabel1 : FOR i in 0 to 8 generate
i_proof_1(i);
end generate glabel1;
glabel2 : FOR i in 'A' to 'Z' generate
i_proof_2(i);
end generate glabel2;
glabel3 : FOR i in Monday to Sunday generate
i_proof_3(i);
end generate glabel3;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s07b00x00p06n02i01793"
severity NOTE;
wait;
END PROCESS TESTING;
END c09s07b00x00p06n02i01793arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_piston.vhd | 4 | 2080 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tb_piston is
end tb_piston;
architecture TB_piston of tb_piston is
-- Component declarations
-- Signal declarations
terminal n1, n2 : translational;
begin
-- Signal assignments
-- Component instances
Force1 : entity work.ForcePulse_t(ideal)
generic map(
initial => 0.0,
pulse => 20.0e-3,
ti2p => 1 ms,
tp2i => 1 ms,
delay => 1 ms,
width => 1 sec,
period => 3 sec
)
port map(
trans_pos => n1,
trans_neg => TRANSLATIONAL_REF
);
mass1 : entity work.piston(simple)
port map(
motion => n1
);
Force2 : entity work.ForcePulse_t(ideal)
generic map(
initial => 0.0,
pulse => 20.0e-3,
ti2p => 1 ms,
tp2i => 1 ms,
delay => 1 ms,
width => 1 sec,
period => 3 sec
)
port map(
trans_pos => n2,
trans_neg => TRANSLATIONAL_REF
);
mass2 : entity work.mass_t(ideal)
generic map(
m => 10.0
)
port map(
trans1 => n2
);
end TB_piston;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_18.vhd | 4 | 2398 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_18 is
end entity inline_18;
----------------------------------------------------------------
architecture test of inline_18 is
begin
process_5_a : process is
constant initial_value : natural := 10;
constant max_value : natural := 8;
constant current_character : character := 'A';
constant input_string : string := "012ABC";
constant free_memory : natural := 0;
constant low_water_limit : natural := 1024;
constant packet_length : natural := 0;
constant clock_pulse_width : delay_length := 10 ns;
constant min_clock_width : delay_length := 20 ns;
constant last_position : natural := 10;
constant first_position : natural := 5;
constant number_of_entries : natural := 0;
begin
-- code from book:
assert initial_value <= max_value;
--
assert initial_value <= max_value
report "initial value too large";
--
assert current_character >= '0' and current_character <= '9'
report "Input number " & input_string & " contains a non-digit";
--
assert free_memory >= low_water_limit
report "low on memory, about to start garbage collect"
severity note;
--
assert packet_length /= 0
report "empty network packet received"
severity warning;
--
assert clock_pulse_width >= min_clock_width
severity error;
--
assert (last_position - first_position + 1) = number_of_entries
report "inconsistency in buffer model"
severity failure;
-- end of code from book
wait;
end process process_5_a;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1419.vhd | 4 | 1709 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1419.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s06b00x00p02n01i01419ent IS
END c08s06b00x00p02n01i01419ent;
ARCHITECTURE c08s06b00x00p02n01i01419arch OF c08s06b00x00p02n01i01419ent IS
BEGIN
TESTING: PROCESS
signal some : integer := 12;
signal p : integer := 3;
signal q : boolean := true;
BEGIN
some (p,q);
assert FALSE
report "***FAILED TEST: c08s06b00x00p02n01i01419 - A name that is not a procedure is used in a procedure call statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s06b00x00p02n01i01419arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_05.vhd | 4 | 1938 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_ch_08_05.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book:
library std, work; use std.standard.all;
-- end of code from book
entity ch_08_05 is
end entity ch_08_05;
----------------------------------------------------------------
architecture test of ch_08_05 is
begin
process_08_4_a : process is
constant a : integer := 10;
constant b : integer := 20;
variable result : boolean;
begin
-- code from book:
result := std.standard."<" ( a, b );
-- end of code from book
wait;
end process process_08_4_a;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1046.vhd | 4 | 1839 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1046.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01046ent IS
END c06s04b00x00p03n01i01046ent;
ARCHITECTURE c06s04b00x00p03n01i01046arch OF c06s04b00x00p03n01i01046ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type ONE is range 1 to 1;
type A2 is array (ONE) of BOOLEAN;
variable V1: BOOLEAN;
BEGIN
V1 := A1'(others=>TRUE)(2);
-- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n01i01046 - Prefix of an indexed name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01046arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2294.vhd | 4 | 2077 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2294.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p32n01i02294ent IS
END c07s02b06x00p32n01i02294ent;
ARCHITECTURE c07s02b06x00p32n01i02294arch OF c07s02b06x00p32n01i02294ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Test the predefined type TIME in this respect.
assert ((1 min * 60.0) > 1 min)
report "Assertion error.(34)";
assert ((60.0 * 1 min) > 1 min)
report "Assertion error.(41)";
wait for 5 ms;
assert NOT( ((1 min * 60.0) > 1 min) and
((60.0 * 1 min) > 1 min) )
report "***PASSED TEST: c07s02b06x00p32n01i02294"
severity NOTE;
assert ( ((1 min * 60.0) > 1 min) and
((60.0 * 1 min) > 1 min) )
report "***FAILED TEST: c07s02b06x00p32n01i02294 - Multiplication of a predefined physical type by an floating point test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p32n01i02294arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc180.vhd | 4 | 1870 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc180.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p03n01i00180ent IS
END c04s04b00x00p03n01i00180ent;
ARCHITECTURE c04s04b00x00p03n01i00180arch OF c04s04b00x00p03n01i00180ent IS
attribute p: POSITIVE;
signal s: integer;
attribute p of s: signal is 10; -- Success_here
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT( s'p=10 )
report "***PASSED TEST: c04s04b00x00p03n01i00180"
severity NOTE;
assert ( s'p=10 )
report "***FAILED TEST: c04s04b00x00p03n01i00180 - In attribute declaration, the reserved word attribute must be followed by an identifier, a colon, a type mark and a semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p03n01i00180arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2871.vhd | 4 | 1592 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2871.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p03n01i02871ent IS
END c02s01b00x00p03n01i02871ent;
ARCHITECTURE c02s01b00x00p03n01i02871arch OF c02s01b00x00p03n01i02871ent IS
function testp (I1:Bit) return; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b00x00p03n01i02871 - Missing type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p03n01i02871arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2326.vhd | 4 | 2329 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2326.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p07n01i02326ent IS
END c07s01b00x00p07n01i02326ent;
ARCHITECTURE c07s01b00x00p07n01i02326arch OF c07s01b00x00p07n01i02326ent IS
BEGIN
TESTING: PROCESS
variable r1, r2, r3, r4 : real;
BEGIN
r1 := 69.0;
r2 := 50.0;
r3 := (-69.0);
r4 := (-50.0);
wait for 5 ns;
assert NOT( ( r1 = abs(r3)) and
( r2 = abs(r4)) and
( 50.0 = abs(-50.0)) and
( (-25.0) = (-abs(-25.0))) and
( 3.14E-2 = abs(-3.14E-2)) and
( (-0.379) = (-abs(-0.379))) )
report "***PASSED TEST: c07s01b00x00p07n01i02326"
severity NOTE;
assert ( ( r1 = abs(r3)) and
( r2 = abs(r4)) and
( 50.0 = abs(-50.0)) and
( (-25.0) = (-abs(-25.0))) and
( 3.14E-2 = abs(-3.14E-2)) and
( (-0.379) = (-abs(-0.379))) )
report "***FAILED TEST: c07s01b00x00p07n01i02326 - The result of the 'abs' operation must be the absolute value of the operand."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p07n01i02326arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2439.vhd | 3 | 6443 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2439.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02439ent IS
END c07s03b02x02p01n01i02439ent;
ARCHITECTURE c07s03b02x02p01n01i02439arch OF c07s03b02x02p01n01i02439ent IS
BEGIN
TESTING: PROCESS
-- Range types are all predefined enumerated types.
type CHAR_ARR is ARRAY( CHARACTER ) of BIT;
type BIT_ARR is ARRAY( BIT ) of BIT;
type BOOL_ARR is ARRAY( BOOLEAN ) of BIT;
type SEV_ARR is ARRAY( SEVERITY_LEVEL ) of BIT;
-- Declare variables of these types.
variable CHARV : CHAR_ARR;
variable BITV : BIT_ARR;
variable BOOLV : BOOL_ARR;
variable SEVV : SEV_ARR;
variable OKtest: integer := 0;
BEGIN
-- Assign each of these arrays using aggregates.
-- 1. Individual aggregates.
CHARV := CHAR_ARR'( 'a' => '1', 'b' => '0', NUL to '`' => '1',
'c' to character'high => '1' );
for C in CHARACTER loop
if (C = 'a') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( '0' => '0', '1' => '1' );
assert( BITV( '0' ) = '0' );
if NOT( BITV( '0' ) = '0' ) then
OKtest := 1;
end if;
assert( BITV( '1' ) = '1' );
if NOT( BITV( '1' ) = '1' ) then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE => '0', TRUE => '1' );
assert( BOOLV( FALSE ) = '0' );
if NOT( BOOLV( FALSE ) = '0' ) then
OKtest := 1;
end if;
assert( BOOLV( TRUE ) = '1' );
if NOT( BOOLV( TRUE ) = '1' ) then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE => '0', WARNING => '1', ERROR => '0',
FAILURE => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
-- 2. Groups of aggregates.
CHARV := CHAR_ARR'( 'a' | 'b' => '1', NUL to '`' => '0',
'c' to character'high => '0' );
for C in CHARACTER loop
if (C = 'a') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( '0' | '1' => '0' );
assert( BITV( '0' ) = '0' );
assert( BITV( '1' ) = '0' );
if NOT((BITV('0')='0') and (BITV('1')='0')) then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE | TRUE => '1' );
assert( BOOLV( FALSE ) = '1' );
assert( BOOLV( TRUE ) = '1' );
if NOT((BOOLV(FALSE)='1') and (BOOLV(TRUE)='1')) then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE | ERROR => '0', WARNING | FAILURE => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
-- 3. Use of 'others' in these aggregates.
CHARV := CHAR_ARR'( 'a' | 'b' => '0', others => '1' );
for C in CHARACTER loop
if (C = 'a') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( others => '1' );
assert( BITV( '0' ) = '1' );
assert( BITV( '1' ) = '1' );
if NOT(( BITV( '0' ) = '1' )and( BITV( '1' ) = '1' ))then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE => '1', others => '0' );
assert( BOOLV( FALSE ) = '1' );
assert( BOOLV( TRUE ) = '0' );
if NOT(( BOOLV( FALSE ) = '1' )and( BOOLV( TRUE ) = '0' ))then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE | ERROR => '0', others => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
wait for 5 ns;
assert NOT(OKtest = 0)
report "***PASSED TEST: c07s03b02x02p01n01i02439"
severity NOTE;
assert (OKtest = 0)
report "***FAILED TEST: c07s03b02x02p01n01i02439 - Aggregates with different range types test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02439arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1558.vhd | 4 | 1793 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1558.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01558ent IS
END c08s10b00x00p03n01i01558ent;
ARCHITECTURE c08s10b00x00p03n01i01558arch OF c08s10b00x00p03n01i01558ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
next L;
k := 5;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s10b00x00p03n01i01558"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s10b00x00p03n01i01558 - a next statement with a loop label is allowed inside a labeled loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01558arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1259.vhd | 4 | 1667 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1259.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n02i01259ent IS
END c08s02b00x00p04n02i01259ent;
ARCHITECTURE c08s02b00x00p04n02i01259arch OF c08s02b00x00p04n02i01259ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "Report this Failure"
severity FAILURE;
assert FALSE
report "***PASSED TEST: c08s02b00x00p04n02i01259 - This test needed manual check to see FAILURE assertion note appear."
severity NOTE;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n02i01259arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc232.vhd | 4 | 1789 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc232.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p02n01i00232ent IS
END c03s01b02x00p02n01i00232ent;
ARCHITECTURE c03s01b02x00p02n01i00232arch OF c03s01b02x00p02n01i00232ent IS
type a is range (1+1) to (1 ms/1 ns);
BEGIN
TESTING: PROCESS
variable k : a := 3;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p02n01i00232"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p02n01i00232 - The right bound in the range constraint is not a locally static expression of type integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p02n01i00232arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2331.vhd | 4 | 1762 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2331.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02331ent IS
END c07s02b07x00p02n02i02331ent;
ARCHITECTURE c07s02b07x00p02n02i02331arch OF c07s02b07x00p02n02i02331ent IS
BEGIN
TESTING: PROCESS
type NEW_INT is range INTEGER'LOW to INTEGER'HIGH;
variable k : NEW_INT := 5;
BEGIN
k := 2 ** 2;
assert NOT(k=4)
report "***PASSED TEST: c07s02b07x00p02n02i02331"
severity NOTE;
assert (k=4)
report "***FAILED TEST: c07s02b07x00p02n02i02331 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02331arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/mul_579.vhd | 2 | 503 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_579 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_579;
architecture augh of mul_579 is
signal tmp_res : signed(47 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug06/repro.vhdl | 3 | 780 | library ieee;
use ieee.std_logic_1164.all;
entity foo is
end entity;
architecture fum of foo is
constant A: std_logic_vector (7 downto 0) := X"04";
function slv_image(inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end;
begin
SOME_LABEL:
process
begin
wait for 1 ns;
if A <= "00001011" then -- if A <= std_logic_vector'("00001011") then
report "A = " & slv_image(A) ;
end if;
wait;
end process;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2230.vhd | 4 | 1693 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2230.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02230ent IS
END c07s02b06x00p01n01i02230ent;
ARCHITECTURE c07s02b06x00p01n01i02230arch OF c07s02b06x00p01n01i02230ent IS
BEGIN
TESTING: PROCESS
variable SEVERV : SEVERITY_LEVEL := NOTE;
variable k : integer;
BEGIN
k := SEVERV rem WARNING;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02230 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02230arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_maxcode.vhd | 2 | 1460 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_dc_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_dc_dhuff_tbl_maxcode;
architecture augh of p_jinfo_dc_dhuff_tbl_maxcode is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc35.vhd | 4 | 1907 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc35.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p01n01i00035ent IS
END c04s03b01x01p01n01i00035ent;
ARCHITECTURE c04s03b01x01p01n01i00035arch OF c04s03b01x01p01n01i00035ent IS
type large is range 0 to 2_000_000_000 -- < 2**31-1
units
sbu;
lbu = 2000000000 sbu;
end units;
constant SC : large := sbu;
constant LC : large := lbu;
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( LC = 2000000000 * SC )
report "***PASSED TEST: c04s03b01x01p01n01i00035"
severity NOTE;
assert ( LC = 2000000000 * SC )
report "***FAILED TEST: c04s03b01x01p01n01i00035 - Large physical type declaration test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p01n01i00035arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug040/mul_214.vhd | 2 | 503 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_214 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end mul_214;
architecture augh of mul_214 is
signal tmp_res : signed(63 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
output <= std_logic_vector(tmp_res(40 downto 0));
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1001.vhd | 4 | 1792 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1001.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01001pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i01001pkg;
use work.c06s03b00x00p09n01i01001pkg.all;
ENTITY c06s03b00x00p09n01i01001ent IS
END c06s03b00x00p09n01i01001ent;
ARCHITECTURE c06s03b00x00p09n01i01001arch OF c06s03b00x00p09n01i01001ent IS
BEGIN
TESTING: PROCESS
subtype ST6 is c06s03b00x00p09n01i01001pkg.UNKNOWN;
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i01001 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01001arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc857.vhd | 4 | 10449 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc857.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00857pkg_2 is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00857pkg_2;
package body c01s03b01x00p12n01i00857pkg_2 is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00857pkg_2;
use work.c01s03b01x00p12n01i00857pkg_2.all;
package c01s03b01x00p12n01i00857pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant dumy : bit_vector(zero to three) := "1010" ;
signal Sin1 : bit_vector(zero to five) ;
signal Sin2 : boolean_vector(zero to five) ;
signal Sin4 : severity_level_vector(zero to five) ;
signal Sin5 : integer_vector(zero to five) ;
signal Sin6 : real_vector(zero to five) ;
signal Sin7 : time_vector(zero to five) ;
signal Sin8 : natural_vector(zero to five) ;
signal Sin9 : positive_vector(zero to five) ;
signal Sin10: array_rec_std(zero to five) ;
end c01s03b01x00p12n01i00857pkg;
use work.c01s03b01x00p12n01i00857pkg.all;
use work.c01s03b01x00p12n01i00857pkg_2.all;
entity c01s03b01x00p12n01i00857ent_a is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture c01s03b01x00p12n01i00857ent_a of c01s03b01x00p12n01i00857ent_a is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration c01s03b01x00p12n01i00857ent_abench of c01s03b01x00p12n01i00857ent_a is
for c01s03b01x00p12n01i00857ent_a
end for;
end;
use work.c01s03b01x00p12n01i00857pkg.all;
use work.c01s03b01x00p12n01i00857pkg_2.all;
ENTITY c01s03b01x00p12n01i00857ent IS
END c01s03b01x00p12n01i00857ent;
ARCHITECTURE c01s03b01x00p12n01i00857arch OF c01s03b01x00p12n01i00857ent IS
component c01s03b01x00p12n01i00857ent_a
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component c01s03b01x00p12n01i00857ent_a
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : c01s03b01x00p12n01i00857ent_a
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:c01s03b01x00p12n01i00857ent_a
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00857"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00857 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00857arch;
configuration c01s03b01x00p12n01i00857cfg of c01s03b01x00p12n01i00857ent is
for c01s03b01x00p12n01i00857arch
for K
for T5:c01s03b01x00p12n01i00857ent_a use configuration work.c01s03b01x00p12n01i00857ent_abench;
end for;
for G(dumy'low to 3)
for T1:c01s03b01x00p12n01i00857ent_a
use configuration work.c01s03b01x00p12n01i00857ent_abench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue238/cst.vhdl | 2 | 154 | package cst is
function four return natural;
end cst;
package body cst is
function four return natural is
begin
return 4;
end four;
end cst;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2178.vhd | 4 | 1784 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2178.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n02i02178ent IS
END c07s02b05x00p01n02i02178ent;
ARCHITECTURE c07s02b05x00p01n02i02178arch OF c07s02b05x00p01n02i02178ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 5;
BEGIN
k := + m;
assert NOT( k = 5 )
report "***PASSED TEST: c07s02b05x00p01n02i02178"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c07s02b05x00p01n02i02178 - For each of these unary operators, the operand and the result have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n02i02178arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc178.vhd | 4 | 1917 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc178.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p01n05i00178ent IS
END c04s04b00x00p01n05i00178ent;
ARCHITECTURE c04s04b00x00p01n05i00178arch OF c04s04b00x00p01n05i00178ent IS
signal S1 : INTEGER;
signal S2 : BOOLEAN;
BEGIN
TESTING: PROCESS
BEGIN
S1'DELAYED <= S2; -- Failure_here
-- ERROR - predefined signal attribute must not be driven
S1'STABLE <= S2; -- Failure_here
-- ERROR - predefined signal attribute must not be driven
S1'QUIET <= S2; -- Failure_here
-- ERROR - predefined signal attribute must not be driven
assert FALSE
report "***FAILED TEST: c04s04b00x00p01n05i00178 - Predefined atttribute DELAYED can not be driven."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p01n05i00178arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load.vhd | 4 | 1871 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity pwl_load is
generic ( load_enable : boolean := true;
res_init : resistance;
res1 : resistance;
t1 : time;
res2 : resistance;
t2 : time );
port ( terminal p1, p2 : electrical );
end entity pwl_load;
----------------------------------------------------------------
architecture ideal of pwl_load is
quantity v across i through p1 to p2;
signal res_signal : resistance := res_init;
begin
load_present : if load_enable generate
if domain = quiescent_domain or domain = frequency_domain use
v == i * res_init;
else
v == i * res_signal'ramp(1.0e-6, 1.0e-6);
end use;
create_event : process is
begin
wait for t1;
res_signal <= res1;
wait for t2 - t1;
res_signal <= res2;
wait;
end process create_event;
end generate load_present;
load_absent : if not load_enable generate
i == 0.0;
end generate load_absent;
end architecture ideal;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/sr2903/boundcheck.vhdl | 3 | 925 | library IEEE;
use IEEE.numeric_std.all;
entity tb is
end tb;
architecture behavioral of tb is
subtype int31 is integer range -2**(31-1) to 2**(31-1)-1;
type array_7_int31 is array(0 to 6) of int31;
function ASR(v : integer; n : natural ; nv : natural; nres : natural) return integer is
variable tmp : signed(nv downto 0);
variable res : signed(nv downto 0);
begin
tmp := resize(to_signed(v,nv),nv+1);
res := shift_right(tmp,n);
return to_integer(res(nres-1 downto 0));
end;
begin
software_emulation : process
variable test : int31;
variable tmp : int31;
begin
report "Start" severity note;
tmp := 5965232;
-- test := test + ASR(((tmp * 119304647) + 268435456),29,57,31);
-- test := test + ASR(((tmp * 178956971) + 268435456),29,57,31);
test := test + ASR(((tmp * 59652324) + 268435456),29,57,31);
end process;
end behavioral;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3201.vhd | 4 | 2086 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3201.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03201ent IS
END c14s03b00x00p42n01i03201ent;
ARCHITECTURE c14s03b00x00p42n01i03201arch OF c14s03b00x00p42n01i03201ent IS
BEGIN
TESTING: PROCESS
file F : TEXT open read_mode is "iofile.14";
variable L : LINE;
variable vstring : string(1 to 3);
variable fail : integer := 0;
BEGIN
for I in 1 to 100 loop
READLINE (F, L);
READ (L, vstring);
if (vstring /= "niu") then
fail := 1;
end if;
end loop;
assert NOT(fail = 0)
report "***PASSED TEST: c14s03b00x00p42n01i03201"
severity NOTE;
assert (fail = 0)
report "***FAILED TEST: c14s03b00x00p42n01i03201 - procedure READLINE for string TEXT file test failed, plese check s010116.vhd file also."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03201arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2768.vhd | 4 | 4882 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2768.vhd,v 1.1.1.1 2001-08-22 18:20:52 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
-- Dale Martin updated the bit_vectors in this file with bit_vector'()
-- qualification to make it VHDL '93 compliant. (It's still '87 compliant
-- as well.)
ENTITY c13s07b00x00p08n01i02768ent IS
END c13s07b00x00p08n01i02768ent;
ARCHITECTURE c13s07b00x00p08n01i02768arch OF c13s07b00x00p08n01i02768ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( bit_vector'(O"0") = "000" and
bit_vector'(O"1") = "001" and
bit_vector'(O"2") = "010" and
bit_vector'(O"3") = "011" and
bit_vector'(O"4") = "100" and
bit_vector'(O"5") = "101" and
bit_vector'(O"6") = "110" and
bit_vector'(O"7") = "111" and
bit_vector'(O"01") = "000001" and
bit_vector'(O"10") = "001000" and
bit_vector'(O"0_1") = "000001" and
bit_vector'(X"0") = "0000" and
bit_vector'(X"1") = "0001" and
bit_vector'(X"2") = "0010" and
bit_vector'(X"3") = "0011" and
bit_vector'(X"4") = "0100" and
bit_vector'(X"5") = "0101" and
bit_vector'(X"6") = "0110" and
bit_vector'(X"7") = "0111" and
bit_vector'(X"8") = "1000" and
bit_vector'(X"9") = "1001" and
bit_vector'(X"A") = "1010" and
bit_vector'(X"a") = "1010" and
bit_vector'(X"B") = "1011" and
bit_vector'(X"b") = "1011" and
bit_vector'(X"C") = "1100" and
bit_vector'(X"c") = "1100" and
bit_vector'(X"D") = "1101" and
bit_vector'(X"d") = "1101" and
bit_vector'(X"E") = "1110" and
bit_vector'(X"e") = "1110" and
bit_vector'(X"F") = "1111" and
bit_vector'(X"f") = "1111" and
bit_vector'(X"01") = "00000001" and
bit_vector'(X"10") = "00010000" and
bit_vector'(X"0_1") = "00000001" and
bit_vector'(X"E_7") = "11100111" and
bit_vector'(X"DEAD_BEEF") = B"1101_1110_1010_1101_1011_1110_1110_1111")
report "***PASSED TEST: c13s07b00x00p08n01i02768"
severity NOTE;
assert ( bit_vector'(O"0") = "000" and
bit_vector'(O"1") = "001" and
bit_vector'(O"2") = "010" and
bit_vector'(O"3") = "011" and
bit_vector'(O"4") = "100" and
bit_vector'(O"5") = "101" and
bit_vector'(O"6") = "110" and
bit_vector'(O"7") = "111" and
bit_vector'(O"01") = "000001" and
bit_vector'(O"10") = "001000" and
bit_vector'(O"0_1") = "000001" and
bit_vector'(X"0") = "0000" and
bit_vector'(X"1") = "0001" and
bit_vector'(X"2") = "0010" and
bit_vector'(X"3") = "0011" and
bit_vector'(X"4") = "0100" and
bit_vector'(X"5") = "0101" and
bit_vector'(X"6") = "0110" and
bit_vector'(X"7") = "0111" and
bit_vector'(X"8") = "1000" and
bit_vector'(X"9") = "1001" and
bit_vector'(X"A") = "1010" and
bit_vector'(X"a") = "1010" and
bit_vector'(X"B") = "1011" and
bit_vector'(X"b") = "1011" and
bit_vector'(X"C") = "1100" and
bit_vector'(X"c") = "1100" and
bit_vector'(X"D") = "1101" and
bit_vector'(X"d") = "1101" and
bit_vector'(X"E") = "1110" and
bit_vector'(X"e") = "1110" and
bit_vector'(X"F") = "1111" and
bit_vector'(X"f") = "1111" and
bit_vector'(X"01") = "00000001" and
bit_vector'(X"10") = "00010000" and
bit_vector'(X"0_1") = "00000001" and
bit_vector'(X"E_7") = "11100111" and
bit_vector'(X"DEAD_BEEF") = B"1101_1110_1010_1101_1011_1110_1110_1111")
report "***FAILED TEST: c13s07b00x00p08n01i02768 - Bit string literal and base specifier 'O' and 'X' value transfer test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p08n01i02768arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2418.vhd | 4 | 1837 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2418.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s03b02x00p10n01i02418pkg is
type byte is range 0 to 15;
type cmd_bus is array (0 to 3) of byte;
end c07s03b02x00p10n01i02418pkg;
use work.c07s03b02x00p10n01i02418pkg.all;
ENTITY c07s03b02x00p10n01i02418ent IS
port ( signal b_inp : in boolean := (0 to 3 => 0) = (0 to 3 => 1));
END c07s03b02x00p10n01i02418ent;
ARCHITECTURE c07s03b02x00p10n01i02418arch OF c07s03b02x00p10n01i02418ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x00p10n01i02418 - The type of the aggregate is not determinable from the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p10n01i02418
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug08/paren1.vhdl | 3 | 221 | entity paren1 is
end paren1;
architecture behav of paren1
is
signal a : bit_vector (1 to 4);
begin
process
begin
for b in a'range loop
assert a(b) = '0';
end loop;
wait;
end process;
end behav;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug040/outdata_comp_hpos.vhd | 2 | 1476 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity outdata_comp_hpos is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end outdata_comp_hpos;
architecture augh of outdata_comp_hpos is
-- Embedded RAM
type ram_type is array (0 to 2) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else (others => '-');
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1007.vhd | 4 | 1801 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1007.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01007pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i01007pkg;
use work.c06s03b00x00p09n01i01007pkg.all;
ENTITY c06s03b00x00p09n01i01007ent IS
END c06s03b00x00p09n01i01007ent;
ARCHITECTURE c06s03b00x00p09n01i01007arch OF c06s03b00x00p09n01i01007ent IS
BEGIN
TESTING: PROCESS
subtype ST13 is c06s03b00x00p09n01i01007ent.E.FOUR (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i01007 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01007arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc786.vhd | 4 | 1730 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc786.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b02x00p03n01i00786ent IS
--
-- Component declarations are not allowed here
--
component -- component illegal here
end component;
END c01s01b02x00p03n01i00786ent;
ARCHITECTURE c01s01b02x00p03n01i00786arch OF c01s01b02x00p03n01i00786ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b02x00p03n01i00786 - Component declarations are not permitted in an entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b02x00p03n01i00786arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_12.vhd | 4 | 1361 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
configuration controller_with_timing of controller is
for structural
for state_reg : reg
use entity work.reg(gate_level)
generic map ( t_setup => 200 ps, t_hold => 150 ps, t_pd => 150 ps,
width => width );
end for;
-- . . .
end for;
end configuration controller_with_timing;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc847.vhd | 4 | 2415 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc847.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity and2g is
end and2g;
architecture behavior of and2g is
begin
end behavior;
entity full_adder is
end full_adder;
architecture structural of full_adder is
component and2
end component;
begin
C1: and2;
end structural;
ENTITY c01s03b01x00p08n01i00847ent IS
END c01s03b01x00p08n01i00847ent;
ARCHITECTURE c01s03b01x00p08n01i00847arch OF c01s03b01x00p08n01i00847ent IS
component adder
end component;
BEGIN
A1 : adder;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s03b01x00p08n01i00847 - Architecture name in block configuration does not match block specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p08n01i00847arch;
configuration c01s03b01x00p08n01i00847cfg of c01s03b01x00p08n01i00847ent is
for c01s03b01x00p08n01i00847arch
for A1: adder use -- component configuration
entity work.full_adder(structural);
for bad_block_spec -- failure_here
for C1: and2 use
entity work.and2g(behavior);
end for;
end for;
end for;
end for;
end c01s03b01x00p08n01i00847cfg;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_read.vhd | 4 | 1916 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity mem_read is
end entity mem_read;
architecture test of mem_read is
attribute trace : string;
subtype byte is bit_vector(7 downto 0);
type byte_vector is array (natural range <>) of byte;
type ram_bus is record
d : byte;
cmd, status, clk : bit;
end record ram_bus;
-- code from book
procedure mem_read ( address : in natural;
result : out byte_vector;
signal memory_bus : inout ram_bus ) is
attribute trace of address : constant is "integer/hex";
attribute trace of result : variable is "byte/multiple/hex";
attribute trace of memory_bus : signal is
"custom/command=rambus.cmd";
-- . . .
begin
-- . . .
-- not in book
report address'trace;
report result'trace;
report memory_bus'trace;
-- end not in book
end procedure mem_read;
-- end code from book
signal memory_bus : ram_bus;
begin
process is
variable address : natural;
variable result : byte_vector(0 to 3);
begin
mem_read ( address, result, memory_bus );
wait;
end process;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_04.vhd | 4 | 1506 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_04.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_03_04 is
end entity test_bench_03_04;
architecture test_counter_behavior of test_bench_03_04 is
signal clk : bit := '0';
signal count : natural;
begin
dut : entity work.counter(behavior)
port map ( clk => clk, count => count );
stimulus : process is
begin
for cycle_count in 1 to 100 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
wait;
end process stimulus;
end architecture test_counter_behavior;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2515.vhd | 4 | 2069 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2515.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p03n02i02515ent IS
END c07s03b05x00p03n02i02515ent;
ARCHITECTURE c07s03b05x00p03n02i02515arch OF c07s03b05x00p03n02i02515ent IS
BEGIN
TESTING: PROCESS
type century is range 1 to 10;
function f(a:century) return century is
begin
return century'(1);
end;
type millenia is ('1', '2', '3', '4', '5');
function f (a:millenia) return millenia is
begin
return millenia'('2');
end;
variable hundreds : century ;
BEGIN
hundreds := century (f(hundreds));
assert NOT(hundreds = 1)
report "***PASSED TEST: c07s03b05x00p03n02i02515"
severity NOTE;
assert (hundreds = 1)
report "***FAILED TEST: c07s03b05x00p03n02i02515 - Type of operand must be determinable independent of the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p03n02i02515arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2336.vhd | 4 | 1665 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2336.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02336ent IS
END c07s02b07x00p02n02i02336ent;
ARCHITECTURE c07s02b07x00p02n02i02336arch OF c07s02b07x00p02n02i02336ent IS
BEGIN
TESTING: PROCESS
variable BITV : BIT := '0';
variable INTV : INTEGER;
BEGIN
INTV := BITV ** 2;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02336 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02336arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_lt.vhd | 4 | 1970 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity bv_lt is
end entity bv_lt;
architecture test of bv_lt is
-- code from book
procedure bv_lt ( bv1, bv2 : in bit_vector; result : out boolean ) is
variable tmp1 : bit_vector(bv1'range) := bv1;
variable tmp2 : bit_vector(bv2'range) := bv2;
begin
tmp1(tmp1'left) := not tmp1(tmp1'left);
tmp2(tmp2'left) := not tmp2(tmp2'left);
result := tmp1 < tmp2;
end procedure bv_lt;
-- end code from book
begin
stimulus : process is
subtype byte is bit_vector(0 to 7);
variable result : boolean;
begin
bv_lt( byte'(X"02"), byte'(X"04"), result );
assert result;
bv_lt( byte'(X"02"), byte'(X"02"), result );
assert not result;
bv_lt( byte'(X"02"), byte'(X"02"), result );
assert not result;
bv_lt( byte'(X"FC"), byte'(X"04"), result );
assert result;
bv_lt( byte'(X"04"), byte'(X"FC"), result );
assert not result;
bv_lt( byte'(X"FC"), byte'(X"FC"), result );
assert not result;
bv_lt( byte'(X"FC"), byte'(X"FE"), result );
assert result;
bv_lt( byte'(X"FE"), byte'(X"FC"), result );
assert not result;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3023.vhd | 4 | 1810 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3023.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library WORK, STD;
ENTITY c11s02b00x00p05n01i03023ent IS
END c11s02b00x00p05n01i03023ent;
ARCHITECTURE c11s02b00x00p05n01i03023arch OF c11s02b00x00p05n01i03023ent IS
signal S1 : STD.STANDARD.bit; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
S1 <= '1' after 20 ns;
wait for 30 ns;
assert NOT( S1 = '1' )
report "***PASSED TEST: c11s02b00x00p05n01i03023"
severity NOTE;
assert ( S1 = '1' )
report "***FAILED TEST: c11s02b00x00p05n01i03023 - Library logical name may be referenced in the design unit."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s02b00x00p05n01i03023arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_02.vhd | 4 | 1183 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_02.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
-- not in book
use work.tb_05_13.all;
-- end not in book
entity adder is
port ( a, b : in word;
sum : out word );
end entity adder;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc939.vhd | 4 | 1870 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc939.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s05b00x00p01n01i00939ent IS
port (PT:BOOLEAN) ;
type BITT is ('0','1');
type DBIT is ('0','1','x'); -- '0' and '1' are overloaded
attribute AT1 : BITT;
attribute AT1 : DBIT; -- Failure_here
-- ERROR : Attribute AT1 is overloaded.
attribute AT1 : INTEGER; -- Failure_here
-- ERROR : Attribute AT1 is overloaded.
END c10s05b00x00p01n01i00939ent;
ARCHITECTURE c10s05b00x00p01n01i00939arch OF c10s05b00x00p01n01i00939ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c10s05b00x00p01n01i00939 - Attributes cannot be overloaded."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s05b00x00p01n01i00939arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2960.vhd | 4 | 4579 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2960.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s03b00x00p02n01i02960pkg is
FUNCTION boo ( PARM_VAL : bit) RETURN integer;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer;
FUNCTION boo ( PARM_VAL : boolean) RETURN integer;
FUNCTION boo ( PARM_VAL : character) RETURN integer;
FUNCTION boo ( PARM_VAL : integer) RETURN integer;
FUNCTION boo ( PARM_VAL : real) RETURN integer;
FUNCTION boo ( PARM_VAL : string) RETURN integer;
FUNCTION boo ( PARM_VAL : time) RETURN integer;
end c02s03b00x00p02n01i02960pkg;
package body c02s03b00x00p02n01i02960pkg is
FUNCTION boo ( PARM_VAL : bit) RETURN integer IS
BEGIN
assert false report "boo with BIT param" severity note;
RETURN 1;
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer IS
BEGIN
assert false report "boo with BIT_VECTOR param" severity note;
RETURN 2;
END;
FUNCTION boo ( PARM_VAL : boolean) RETURN integer IS
BEGIN
assert false report "boo with BOOLEAN param" severity note;
RETURN 3;
END;
FUNCTION boo ( PARM_VAL : character) RETURN integer IS
BEGIN
assert false report "boo with CHARACTER param" severity note;
RETURN 4;
END;
FUNCTION boo ( PARM_VAL : integer) RETURN integer IS
BEGIN
assert false report "boo with INTEGER param" severity note;
RETURN 5;
END;
FUNCTION boo ( PARM_VAL : real) RETURN integer IS
BEGIN
assert false report "boo with REAL param" severity note;
RETURN 6;
END;
FUNCTION boo ( PARM_VAL : string) RETURN integer IS
BEGIN
assert false report "boo with STRING param" severity note;
RETURN 7;
END;
FUNCTION boo ( PARM_VAL : time) RETURN integer IS
BEGIN
assert false report "boo with TIME param" severity note;
RETURN 8;
END;
end c02s03b00x00p02n01i02960pkg;
ENTITY c02s03b00x00p02n01i02960ent IS
PORT (bb: INOUT bit;
bv: INOUT bit_vector(0 TO 3);
bo: INOUT boolean;
cc: INOUT character;
ii: INOUT integer;
rr: INOUT real;
ss: INOUT string(1 TO 6);
tt: INOUT time);
SUBTYPE bv_4 IS bit_vector(1 TO 4);
SUBTYPE bv_6 IS bit_vector(1 TO 6);
FUNCTION foo ( PARM_VAL : bv_4) RETURN bit_vector IS
BEGIN
assert false report "function foo in entity e" severity note;
RETURN PARM_VAL;
END;
END c02s03b00x00p02n01i02960ent;
use work.c02s03b00x00p02n01i02960pkg.all;
ARCHITECTURE c02s03b00x00p02n01i02960arch OF c02s03b00x00p02n01i02960ent IS
SIGNAL c1,c2,c3,c4,c5,c6,c7,c8 : INTEGER;
BEGIN
TESTING: PROCESS
BEGIN
WAIT FOR 1 ns;
c1 <= boo(bb);
c2 <= boo(bv);
c3 <= boo(bo);
c4 <= boo(cc);
c5 <= boo(ii);
c6 <= boo(rr);
c7 <= boo(ss);
c8 <= boo(tt);
WAIT FOR 1 ns;
assert NOT( (c1 = 1) AND
(c2 = 2) AND
(c3 = 3) AND
(c4 = 4) AND
(c5 = 5) AND
(c6 = 6) AND
(c7 = 7) AND
(c8 = 8))
report "***PASSED TEST: c02s03b00x00p02n01i02960"
severity NOTE;
assert ( (c1 = 1) AND
(c2 = 2) AND
(c3 = 3) AND
(c4 = 4) AND
(c5 = 5) AND
(c6 = 6) AND
(c7 = 7) AND
(c8 = 8))
report "***FAILED TEST: c02s03b00x00p02n01i02960 - Overloaded functions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p02n01i02960arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3079.vhd | 4 | 4169 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3079.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03079pkg is
type natural_cons_vector is array (15 downto 0) of natural;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
constant C19 : natural_cons_vectorofvector := (others => (others => 3));
end c12s06b02x00p06n01i03079pkg;
use work.c12s06b02x00p06n01i03079pkg.all;
ENTITY c12s06b02x00p06n01i03079ent_a IS
PORT
(
F1: OUT integer ;
F3: IN natural_cons_vectorofvector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03079ent_a;
ARCHITECTURE c12s06b02x00p06n01i03079arch_a OF c12s06b02x00p06n01i03079ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03079arch_a;
use work.c12s06b02x00p06n01i03079pkg.all;
ENTITY c12s06b02x00p06n01i03079ent IS
END c12s06b02x00p06n01i03079ent;
ARCHITECTURE c12s06b02x00p06n01i03079arch OF c12s06b02x00p06n01i03079ent IS
function scalar_complex(s : integer) return natural_cons_vectorofvector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN natural_cons_vectorofvector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03079ent_a(c12s06b02x00p06n01i03079arch_a);
signal S1 : natural_cons_vectorofvector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03079"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03079 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03079arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug035/physical.vhdl | 6 | 32559 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: This VHDL package declares new physical types and their
-- conversion functions.
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- NAMING CONVENTION:
-- t - time
-- p - period
-- d - delay
-- f - frequency
-- br - baud rate
-- vec - vector
--
-- ATTENTION:
-- This package is not supported by Xilinx Synthese Tools prior to 14.7!
--
-- It was successfully tested with:
-- - Xilinx Synthesis Tool (XST) 14.7 and Xilinx ISE Simulator (iSim) 14.7
-- - Quartus II 13.1
-- - QuestaSim 10.0d
-- - GHDL 0.31
--
-- Tool chains with known issues:
-- - Xilinx Vivado Synthesis 2014.4
--
-- Untested tool chains
-- - Xilinx Vivado Simulator (xSim) 2014.4
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
package physical is
type FREQ is range 0 to INTEGER'high units
Hz;
kHz = 1000 Hz;
MHz = 1000 kHz;
GHz = 1000 MHz;
-- THz = 1000 GHz;
end units;
type BAUD is range 0 to INTEGER'high units
Bd;
kBd = 1000 Bd;
MBd = 1000 kBd;
GBd = 1000 MBd;
end units;
type MEMORY is range 0 to INTEGER'high units
Byte;
KiB = 1024 Byte;
MiB = 1024 KiB;
GiB = 1024 MiB;
-- TiB = 1024 GiB;
end units;
--
type T_TIMEVEC is array(NATURAL range <>) of TIME;
type T_FREQVEC is array(NATURAL range <>) of FREQ;
type T_BAUDVEC is array(NATURAL range <>) of BAUD;
type T_MEMVEC is array(NATURAL range <>) of MEMORY;
-- TODO
constant C_PHYSICAL_REPORT_TIMING_DEVIATION : BOOLEAN := TRUE;
-- conversion functions
function to_time(f : FREQ) return TIME;
function to_freq(p : TIME) return FREQ;
function to_freq(br : BAUD) return FREQ;
function to_baud(str : STRING) return BAUD;
-- if-then-else
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY;
-- min/ max for 2 arguments
function min(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: min(arg1, arg2) for times
function min(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: min(arg1, arg2) for memory
function max(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: max(arg1, arg2) for times
function max(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: max(arg1, arg2) for memory
-- min/max/sum as vector aggregation
function min(vec : T_TIMEVEC) return TIME; -- Calculates: min(vec) for a time vector
function min(vec : T_FREQVEC) return FREQ; -- Calculates: min(vec) for a frequency vector
function min(vec : T_BAUDVEC) return BAUD; -- Calculates: min(vec) for a baud vector
function min(vec : T_MEMVEC) return MEMORY; -- Calculates: min(vec) for a memory vector
function max(vec : T_TIMEVEC) return TIME; -- Calculates: max(vec) for a time vector
function max(vec : T_FREQVEC) return FREQ; -- Calculates: max(vec) for a frequency vector
function max(vec : T_BAUDVEC) return BAUD; -- Calculates: max(vec) for a baud vector
function max(vec : T_MEMVEC) return MEMORY; -- Calculates: max(vec) for a memory vector
-- QUESTION: some sum functions are not meaningful -> orthogonal function/type system
function sum(vec : T_TIMEVEC) return TIME; -- Calculates: sum(vec) for a time vector
function sum(vec : T_FREQVEC) return FREQ; -- Calculates: sum(vec) for a frequency vector
function sum(vec : T_BAUDVEC) return BAUD; -- Calculates: sum(vec) for a baud vector
function sum(vec : T_MEMVEC) return MEMORY; -- Calculates: sum(vec) for a memory vector
-- convert standard types (NATURAL, REAL) to time (TIME)
function fs2Time(t_fs : NATURAL) return TIME;
function ps2Time(t_ps : NATURAL) return TIME;
function ns2Time(t_ns : NATURAL) return TIME;
function us2Time(t_us : NATURAL) return TIME;
function ms2Time(t_ms : NATURAL) return TIME;
function sec2Time(t_sec : NATURAL) return TIME;
function fs2Time(t_fs : REAL) return TIME;
function ps2Time(t_ps : REAL) return TIME;
function ns2Time(t_ns : REAL) return TIME;
function us2Time(t_us : REAL) return TIME;
function ms2Time(t_ms : REAL) return TIME;
function sec2Time(t_sec : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to period (TIME)
function Hz2Time(f_Hz : NATURAL) return TIME;
function kHz2Time(f_kHz : NATURAL) return TIME;
function MHz2Time(f_MHz : NATURAL) return TIME;
function GHz2Time(f_GHz : NATURAL) return TIME;
-- function THz2Time(f_THz : NATURAL) return TIME;
function Hz2Time(f_Hz : REAL) return TIME;
function kHz2Time(f_kHz : REAL) return TIME;
function MHz2Time(f_MHz : REAL) return TIME;
function GHz2Time(f_GHz : REAL) return TIME;
-- function THz2Time(f_THz : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
function Hz2Freq(f_Hz : NATURAL) return FREQ;
function kHz2Freq(f_kHz : NATURAL) return FREQ;
function MHz2Freq(f_MHz : NATURAL) return FREQ;
function GHz2Freq(f_GHz : NATURAL) return FREQ;
-- function THz2Freq(f_THz : NATURAL) return FREQ;
function Hz2Freq(f_Hz : REAL) return FREQ;
function kHz2Freq(f_kHz : REAL) return FREQ;
function MHz2Freq(f_MHz : REAL) return FREQ;
function GHz2Freq(f_GHz : REAL) return FREQ;
-- function THz2Freq(f_THz : REAL) return FREQ;
-- convert physical types to standard type (REAL)
function to_real(t : TIME; scale : TIME) return REAL;
function to_real(f : FREQ; scale : FREQ) return REAL;
function to_real(br : BAUD; scale : BAUD) return REAL;
function to_real(mem : MEMORY; scale : MEMORY) return REAL;
-- convert physical types to standard type (INTEGER)
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING;
function to_string(f : FREQ; precision : NATURAL) return STRING;
function to_string(br : BAUD; precision : NATURAL) return STRING;
function to_string(mem : MEMORY; precision : NATURAL) return STRING;
end physical;
package body physical is
-- iSim 14.7 does not support fs in simulation (fs values are converted to 0 ps)
function MinimalTimeResolutionInSimulation return TIME is
begin
if (1 fs > 0 sec) then return 1 fs;
elsif (1 ps > 0 sec) then return 1 ps;
elsif (1 ns > 0 sec) then return 1 ns;
elsif (1 us > 0 sec) then return 1 us;
elsif (1 ms > 0 sec) then return 1 ms;
else return 1 sec;
end if;
end function;
-- real division for physical types
-- ===========================================================================
function div(a : TIME; b : TIME) return REAL is
constant MTRIS : TIME := MinimalTimeResolutionInSimulation;
begin
if (a < 1 us) then
return real(a / MTRIS) / real(b / MTRIS);
elsif (a < 1 ms) then
return real(a / (1000 * MTRIS)) / real(b / MTRIS) * 1000.0;
elsif (a < 1 sec) then
return real(a / (1000000 * MTRIS)) / real(b / MTRIS) * 1000000.0;
else
return real(a / (1000000000 * MTRIS)) / real(b / MTRIS) * 1000000000.0;
end if;
end function;
function div(a : FREQ; b : FREQ) return REAL is
begin
return real(a / 1 Hz) / real(b / 1 Hz);
end function;
function div(a : BAUD; b : BAUD) return REAL is
begin
return real(a / 1 Bd) / real(b / 1 Bd);
end function;
function div(a : MEMORY; b : MEMORY) return REAL is
begin
return real(a / 1 Byte) / real(b / 1 Byte);
end function;
-- conversion functions
-- ===========================================================================
function to_time(f : FREQ) return TIME is
variable res : TIME;
begin
if (f < 1 kHz) then res := div(1 Hz, f) * 1 sec;
elsif (f < 1 MHz) then res := div(1 kHz, f) * 1 ms;
elsif (f < 1 GHz) then res := div(1 MHz, f) * 1 us;
-- elsif (f < 1 THz) then res := div(1 GHz, f) * 1 ns;
else res := div(1 GHz, f) * 1 ns;
-- else res := div(1 THz, f) * 1 ps;
end if;
if (POC_VERBOSE = TRUE) then
report "to_time: f= " & to_string(f, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(p : TIME) return FREQ is
variable res : FREQ;
begin
-- if (p < 1 ps) then res := div(1 fs, p) * 1 THz;
if (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
-- elsif (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
elsif (p < 1 us) then res := div(1 ns, p) * 1 MHz;
elsif (p < 1 ms) then res := div(1 us, p) * 1 kHz;
elsif (p < 1 sec) then res := div(1 ms, p) * 1 Hz;
else report "to_freq: input period exceeds output frequency scale." severity failure;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: p= " & to_string(p, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(br : BAUD) return FREQ is
variable res : FREQ;
begin
if (br < 1 kBd) then res := div(br, 1 Bd) * 1 Hz;
elsif (br < 1 MBd) then res := div(br, 1 kBd) * 1 kHz;
elsif (br < 1 GBd) then res := div(br, 1 MBd) * 1 MHz;
else res := div(br, 1 GBd) * 1 GHz;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: br= " & to_string(br, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_baud(str : STRING) return BAUD is
variable pos : INTEGER;
variable int : NATURAL;
variable base : POSITIVE;
variable frac : NATURAL;
variable digits : NATURAL;
begin
pos := str'low;
int := 0;
frac := 0;
digits := 0;
-- read integer part
for i in pos to str'high loop
if (chr_isDigit(str(i)) = TRUE) then int := int * 10 + to_digit_dec(str(i));
elsif (str(i) = '.') then pos := -i; exit;
elsif (str(i) = ' ') then pos := i; exit;
else pos := 0; exit;
end if;
end loop;
-- read fractional part
if ((pos < 0) and (-pos < str'high)) then
for i in -pos+1 to str'high loop
if ((frac = 0) and (str(i) = '0')) then next;
elsif (chr_isDigit(str(i)) = TRUE) then frac := frac * 10 + to_digit_dec(str(i));
elsif (str(i) = ' ') then digits := i + pos - 1; pos := i; exit;
else pos := 0; exit;
end if;
end loop;
end if;
-- abort if format is unknown
if (pos = 0) then report "to_baud: Unknown format" severity FAILURE; end if;
-- parse unit
pos := pos + 1;
if ((pos + 1 = str'high) and (str(pos to pos + 1) = "Bd")) then
return int * 1 Bd;
elsif (pos + 2 = str'high) then
if (str(pos to pos + 2) = "kBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 kBd) + (frac * 10**(3 - digits) * 1 Bd);
else return (int * 1 kBd) + (frac / 10**(digits - 3) * 100 Bd);
end if;
elsif (str(pos to pos + 2) = "MBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 MBd) + (frac * 10**(3 - digits) * 1 kBd);
elsif (digits <= 6) then return (int * 1 MBd) + (frac * 10**(6 - digits) * 1 Bd);
else return (int * 1 MBd) + (frac / 10**(digits - 6) * 100000 Bd);
end if;
elsif (str(pos to pos + 2) = "GBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 GBd) + (frac * 10**(3 - digits) * 1 MBd);
elsif (digits <= 6) then return (int * 1 GBd) + (frac * 10**(6 - digits) * 1 kBd);
elsif (digits <= 9) then return (int * 1 GBd) + (frac * 10**(9 - digits) * 1 Bd);
else return (int * 1 GBd) + (frac / 10**(digits - 9) * 100000000 Bd);
end if;
else
report "to_baud: Unknown unit." severity FAILURE;
end if;
else
report "to_baud: Unknown format" severity FAILURE;
end if;
end function;
-- if-then-else
-- ===========================================================================
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
-- min/ max for 2 arguments
-- ===========================================================================
-- Calculates: min(arg1, arg2) for times
function min(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for memory
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for times
function max(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for memory
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- min/max/sum as vector aggregation
-- ===========================================================================
-- Calculates: min(vec) for a time vector
function min(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a frequency vector
function min(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a baud vector
function min(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a memory vector
function min(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a time vector
function max(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a frequency vector
function max(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a baud vector
function max(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a memory vector
function max(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: sum(vec) for a time vector
function sum(vec : T_TIMEVEC) return TIME is
variable res : TIME := 0 fs;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a frequency vector
function sum(vec : T_FREQVEC) return FREQ is
variable res : FREQ := 0 Hz;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a baud vector
function sum(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := 0 Bd;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a memory vector
function sum(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := 0 Byte;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- convert standard types (NATURAL, REAL) to time (TIME)
-- ===========================================================================
function fs2Time(t_fs : NATURAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : NATURAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : NATURAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : NATURAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : NATURAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : NATURAL) return TIME is
begin
return t_sec * 1 sec;
end function;
function fs2Time(t_fs : REAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : REAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : REAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : REAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : REAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : REAL) return TIME is
begin
return t_sec * 1 sec;
end function;
-- convert standard types (NATURAL, REAL) to period (TIME)
-- ===========================================================================
function Hz2Time(f_Hz : NATURAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : NATURAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : NATURAL) return TIME
is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : NATURAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : NATURAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
function Hz2Time(f_Hz : REAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : REAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : REAL) return TIME is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : REAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : REAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
-- ===========================================================================
function Hz2Freq(f_Hz : NATURAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : NATURAL) return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : NATURAL) return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : NATURAL) return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : NATURAL) return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
function Hz2Freq(f_Hz : REAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : REAL )return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : REAL )return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : REAL )return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : REAL )return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
-- convert physical types to standard type (REAL)
-- ===========================================================================
function to_real(t : TIME; scale : TIME) return REAL is
begin
if (scale = 1 fs) then return div(t, 1 fs);
elsif (scale = 1 ps) then return div(t, 1 ps);
elsif (scale = 1 ns) then return div(t, 1 ns);
elsif (scale = 1 us) then return div(t, 1 us);
elsif (scale = 1 ms) then return div(t, 1 ms);
elsif (scale = 1 sec) then return div(t, 1 sec);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(f : FREQ; scale : FREQ) return REAL is
begin
if (scale = 1 Hz) then return div(f, 1 Hz);
elsif (scale = 1 kHz) then return div(f, 1 kHz);
elsif (scale = 1 MHz) then return div(f, 1 MHz);
elsif (scale = 1 GHz) then return div(f, 1 GHz);
-- elsif (scale = 1 THz) then return div(f, 1 THz);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(br : BAUD; scale : BAUD) return REAL is
begin
if (scale = 1 Bd) then return div(br, 1 Bd);
elsif (scale = 1 kBd) then return div(br, 1 kBd);
elsif (scale = 1 MBd) then return div(br, 1 MBd);
elsif (scale = 1 GBd) then return div(br, 1 GBd);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(mem : MEMORY; scale : MEMORY) return REAL is
begin
if (scale = 1 Byte) then return div(mem, 1 Byte);
elsif (scale = 1 KiB) then return div(mem, 1 KiB);
elsif (scale = 1 MiB) then return div(mem, 1 MiB);
elsif (scale = 1 GiB) then return div(mem, 1 GiB);
-- elsif (scale = 1 TiB) then return div(mem, 1 TiB);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
-- convert physical types to standard type (INTEGER)
-- ===========================================================================
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(t, scale)));
when ROUND_DOWN => return integer(floor(to_real(t, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(t, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(f, scale)));
when ROUND_DOWN => return integer(floor(to_real(f, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(f, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(br, scale)));
when ROUND_DOWN => return integer(floor(to_real(br, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(br, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(mem, scale)));
when ROUND_DOWN => return integer(floor(to_real(mem, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(mem, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
-- ===========================================================================
-- @param Timing A given timing or delay, which should be achived
-- @param Clock_Period The period of the circuits clock
-- @RoundingStyle Default = round to nearest; other choises: ROUND_UP, ROUND_DOWN
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
variable res_real : REAL;
variable res_nat : NATURAL;
variable res_time : TIME;
variable res_dev : REAL;
begin
res_real := div(Timing, Clock_Period);
case RoundingStyle is
when ROUND_TO_NEAREST => res_nat := natural(round(res_real));
when ROUND_UP => res_nat := natural(ceil(res_real));
when ROUND_DOWN => res_nat := natural(floor(res_real));
when others => report "RoundingStyle '" & T_ROUNDING_STYLE'image(RoundingStyle) & "' not supported." severity failure;
end case;
res_time := CyclesToDelay(res_nat, Clock_Period);
res_dev := (1.0 - div(res_time, Timing)) * 100.0;
if (POC_VERBOSE = TRUE) then
report "TimingToCycles: " & CR &
" Timing: " & to_string(Timing, 3) & CR &
" Clock_Period: " & to_string(Clock_Period, 3) & CR &
" RoundingStyle: " & str_substr(T_ROUNDING_STYLE'image(RoundingStyle), 7) & CR &
" res_real = " & str_format(res_real, 3) & CR &
" => " & INTEGER'image(res_nat)
severity note;
end if;
-- if (C_PHYSICAL_REPORT_TIMING_DEVIATION = TRUE) then
-- report "TimingToCycles (timing deviation report): " & CR &
-- " timing to achieve: " & to_string(Timing) & CR &
-- " calculated cycles: " & INTEGER'image(res_nat) & " cy" & CR &
-- " resulting timing: " & to_string(res_time) & CR &
-- " deviation: " & to_string(Timing - res_time) & " (" & str_format(res_dev, 2) & "%)"
-- severity note;
-- end if;
return res_nat;
end;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
begin
return TimingToCycles(Timing, to_time(Clock_Frequency), RoundingStyle);
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME is
begin
return Clock_Period * Cycles;
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME is
begin
return CyclesToDelay(Cycles, to_time(Clock_Frequency));
end function;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (t < 1 ps) then
unit(1 to 2) := "fs";
value := to_real(t, 1 fs);
elsif (t < 1 ns) then
unit(1 to 2) := "ps";
value := to_real(t, 1 ps);
elsif (t < 1 us) then
unit(1 to 2) := "ns";
value := to_real(t, 1 ns);
elsif (t < 1 ms) then
unit(1 to 2) := "us";
value := to_real(t, 1 us);
elsif (t < 1 sec) then
unit(1 to 2) := "ms";
value := to_real(t, 1 ms);
else
unit := "sec";
value := to_real(t, 1 sec);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(f : FREQ; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (f < 1 kHz) then
unit(1 to 2) := "Hz";
value := to_real(f, 1 Hz);
elsif (f < 1 MHz) then
unit := "kHz";
value := to_real(f, 1 kHz);
elsif (f < 1 GHz) then
unit := "MHz";
value := to_real(f, 1 MHz);
else --if (f < 1 THz) then
unit := "GHz";
value := to_real(f, 1 GHz);
-- else
-- unit := "THz";
-- value := to_real(f, 1 THz);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(br : BAUD; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (br < 1 kBd) then
unit(1 to 2) := "Bd";
value := to_real(br, 1 Bd);
elsif (br < 1 MBd) then
unit := "kBd";
value := to_real(br, 1 kBd);
elsif (br < 1 GBd) then
unit := "MBd";
value := to_real(br, 1 MBd);
else
unit := "GBd";
value := to_real(br, 1 GBd);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(mem : MEMORY; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (mem < 1 KiB) then
unit(1) := 'B';
value := to_real(mem, 1 Byte);
elsif (mem < 1 MiB) then
unit := "KiB";
value := to_real(mem, 1 KiB);
elsif (mem < 1 GiB) then
unit := "MiB";
value := to_real(mem, 1 MiB);
else --if (mem < 1 TiB) then
unit := "GiB";
value := to_real(mem, 1 GiB);
-- else
-- unit := "TiB";
-- value := to_real(mem, 1 TiB);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
end package body;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2184.vhd | 4 | 1915 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2184.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n02i02184ent IS
END c07s02b05x00p01n02i02184ent;
ARCHITECTURE c07s02b05x00p01n02i02184arch OF c07s02b05x00p01n02i02184ent IS
BEGIN
TESTING: PROCESS
type PHYS is range 0 to 1000
units
A;
B = 10 A;
C = 10 B;
D = 10 C;
end units;
variable k : PHYS := 1 A;
variable m : PHYS := 5 B;
BEGIN
k := + m;
assert NOT( k = 5 B )
report "***PASSED TEST: c07s02b05x00p01n02i02184"
severity NOTE;
assert ( k = 5 B )
report "***FAILED TEST: c07s02b05x00p01n02i02184 - For each of these unary operators, the operand and the result have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n02i02184arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3176.vhd | 4 | 1740 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3176.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p27n01i03176ent IS
END c14s01b00x00p27n01i03176ent;
ARCHITECTURE c14s01b00x00p27n01i03176arch OF c14s01b00x00p27n01i03176ent IS
type color is (red, green, blue);
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( color'low = red )
report "***PASSED TEST: c14s01b00x00p27n01i03176"
severity NOTE;
assert ( color'low = red )
report "***FAILED TEST: c14s01b00x00p27n01i03176 - Predefined attribute LOW for enumeration type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p27n01i03176arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc347.vhd | 4 | 1822 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc347.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p15n01i00347ent IS
END c03s02b01x00p15n01i00347ent;
ARCHITECTURE c03s02b01x00p15n01i00347arch OF c03s02b01x00p15n01i00347ent IS
type MEM is array(5 downto 0) of BIT; -- No_failure_here
signal S1 : MEM := "000000";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(S1(4 downto 3) = "00")
report "***PASSED TEST: c03s02b01x00p15n01i00347"
severity NOTE;
assert (S1(4 downto 3) = "00")
report "***FAILED TEST: c03s02b01x00p15n01i00347 - The direction of the discrete range is the same as the direction of the range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p15n01i00347arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1309.vhd | 4 | 4533 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1309.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s04b00x00p07n01i01309pkg is
-- Type declarations.
subtype BV2 is BIT_VECTOR( 0 to 1 );
subtype CH2 is STRING( 1 to 2 );
-- Constant declarations.
constant BVC : BV2 := B"00";
constant CHC : CH2 := "bb";
-- Function returns BV2.
function returnBV2 return BV2;
-- Function returns CH2.
function returnCH2 return CH2;
end c08s04b00x00p07n01i01309pkg;
package body c08s04b00x00p07n01i01309pkg is
-- Function returns BV2.
function returnBV2 return BV2 is
begin
return ( BVC );
end returnBV2;
-- Function returns CH2.
function returnCH2 return CH2 is
begin
return( CHC );
end returnCH2;
end c08s04b00x00p07n01i01309pkg;
use work.c08s04b00x00p07n01i01309pkg.all;
ENTITY c08s04b00x00p07n01i01309ent IS
END c08s04b00x00p07n01i01309ent;
ARCHITECTURE c08s04b00x00p07n01i01309arch OF c08s04b00x00p07n01i01309ent IS
-- Local signals.
signal S : BIT;
signal T : BIT;
signal C1, C2 : CHARACTER;
BEGIN
TESTING: PROCESS
-- local variables
variable BITV : BV2 := B"11";
variable STRV : CH2 := "ab";
variable ShouldBeTime : TIME;
variable k : integer := 0;
BEGIN
-- Assign with a variable as the expression.
( S, T ) <= BITV after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on S,T;
if (ShouldBeTime /= Now or S /= BITV(0) or T /= BITV(1)) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert ((S = BITV( 0 )) and (T = BITV( 1 )));
( C1,C2 ) <= STRV after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on C1,C2;
if (ShouldBeTime /= Now or C1 /= STRV(1) or C2 /= STRV(2)) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert ((C1 = STRV( 1 )) and (C2 = STRV( 2 )));
-- Assign with a function return value.
( S, T ) <= returnBV2 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on S,T;
if (ShouldBeTime /= Now or S /= BVC(0) or T /= BVC(1)) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert ((S = BVC( 0 )) and (T = BVC( 1 )));
( C1,C2 ) <= returnCH2 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on C1,C2;
if (ShouldBeTime /= Now or C1 /= CHC(1) or C2 /= CHC(2)) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert ((C1 = CHC( 1 )) and (C2 = CHC( 2 )));
-- Assign with a qualified expression.
( S, T ) <= BV2'( '0', '1' ) after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on S,T;
if (ShouldBeTime /= Now or S /= '0' or T /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert ((S = '0') and (T = '1'));
( C1,C2 ) <= CH2'( 'c', 'c' ) after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on C1,C2;
if (ShouldBeTime /= Now or C1 /= 'c' or C2 /= 'c') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert ((C1 = 'c') and (C2 = 'c'));
assert NOT( k = 0 )
report "***PASSED TEST: c08s04b00x00p07n01i01309"
severity NOTE;
assert ( k = 0 )
report "***FAILED TEST: c08s04b00x00p07n01i01309 - If the target of the signal assignment statement is in the form of an aggregate, then the type of the aggregate must be determinable from the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p07n01i01309arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1057.vhd | 4 | 1885 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1057.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01057ent IS
END c06s04b00x00p03n02i01057ent;
ARCHITECTURE c06s04b00x00p03n02i01057arch OF c06s04b00x00p03n02i01057ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type A21 is array (THREE, THREE) of BOOLEAN;
variable V1: BOOLEAN;
variable V21: A21 ;
BEGIN
V1 := V21(3, 2, 1); -- ONE MORE
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01057 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01057arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/bug069/bug8.vhdl | 2 | 156 | entity bug8 is
end entity bug8;
architecture x of bug8 is
type bit_position is (msb);
signal test : real;
begin
test <= msb;
end architecture x;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/vector.d/cmp_142.vhd | 2 | 376 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_142 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_142;
architecture augh of cmp_142 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc197.vhd | 4 | 1677 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc197.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p04n01i00197ent IS
END c03s01b00x00p04n01i00197ent;
ARCHITECTURE c03s01b00x00p04n01i00197arch OF c03s01b00x00p04n01i00197ent IS
type t1 is range 0 to 300;
type t2 is range -100 to 0;
type t3 is range t1 to t2;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b00x00p04n01i00197 - Illegal assignment in range constraint for type declaration of 't3'."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p04n01i00197arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc639.vhd | 4 | 3323 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc639.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:51 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:14 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:28 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00639ent IS
END c03s04b01x00p01n01i00639ent;
ARCHITECTURE c03s04b01x00p01n01i00639arch OF c03s04b01x00p01n01i00639ent IS
type four_value is ('Z','0','1','X');
subtype binary is four_value range '0' to '1';
subtype word is bit_vector(0 to 15);
constant size : integer := 7;
type primary_memory is array(0 to size) of word;
type primary_memory_module is
record
enable : binary;
memory_number : primary_memory;
end record;
type primary_memory_module_file is file of primary_memory_module;
constant C38 : word := (others => '1');
constant C44 : primary_memory := (others => C38);
constant C45 : primary_memory_module := ('1',C44);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : primary_memory_module_file open read_mode is "iofile.43";
variable v : primary_memory_module;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C45) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00639"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00639 - File reading operation (primary_memory_module file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00639arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2242.vhd | 4 | 1693 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2242.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02242ent IS
END c07s02b06x00p01n01i02242ent;
ARCHITECTURE c07s02b06x00p01n01i02242arch OF c07s02b06x00p01n01i02242ent IS
BEGIN
TESTING: PROCESS
variable BITSTRV : BIT_VECTOR( 0 to 31 );
variable k : integer;
BEGIN
k := BITSTRV mod X"7777";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02242 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02242arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1704.vhd | 4 | 2663 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1704.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p07n01i01704ent IS
END c09s02b00x00p07n01i01704ent;
ARCHITECTURE c09s02b00x00p07n01i01704arch OF c09s02b00x00p07n01i01704ent IS
signal S : Bit;
BEGIN
TESTING: PROCESS( S )
-- local variables.
variable INITED : BOOLEAN := FALSE;
variable CNT : INTEGER := 0;
variable NEWTIME: TIME;
variable k : integer := 1;
BEGIN
-- Take care of the first run.
if (not( INITED )) then
INITED := TRUE;
CNT := 0;
S <= (not S) after 1 ns;
NEWTIME := NOW + 1 ns;
-- Otherwise, take care of all subsequent runs.
-- NOTE: Take care of the last time we will get awakened.
elsif (NOW /= TIME'HIGH) then
-- Verify that we woke up when S was updated.
if NOT(( S'EVENT ) and ( NEWTIME = NOW )) then
k := 0;
end if;
-- See if we should continue. If so, do it.
CNT := CNT + 1;
if (CNT <= 50) then
S <= (not S) after 1 ns;
NEWTIME := NOW + 1 ns;
end if;
end if;
if (CNT = 50) then
assert NOT( k=1 )
report "***PASSED TEST: c09s02b00x00p07n01i01704"
severity NOTE;
assert ( k=1 )
report "***FAILED TEST: c09s02b00x00p07n01i01704 - The process statement is assumed to contain an implicit wait statement if a sensitivity list appears following the reserved word process."
severity ERROR;
end if;
END PROCESS TESTING;
END c09s02b00x00p07n01i01704arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc410.vhd | 4 | 2991 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc410.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00410ent IS
END c03s02b01x01p19n01i00410ent;
ARCHITECTURE c03s02b01x01p19n01i00410arch OF c03s02b01x01p19n01i00410ent IS
constant C1 : integer := 3;
function complex_scalar(s : integer) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return integer is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : integer;
signal S2 : integer;
signal S3 : integer := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00410"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00410 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00410arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/sensor.vhd | 4 | 2038 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity sensor is
generic ( threshold : real; -- voltage threshold
tipd_clk : delay_length; -- input prop delay on clk
tipd_input : real; -- input prop delay on sensor input
topd_q : delay_length ); -- output prop delay on q
port ( terminal input : electrical; -- sensor analog input
signal clk : in bit; -- edgetriggered clock input
signal q : out bit ); -- sensor digital output
end entity sensor;
architecture detailed_timing of sensor is
quantity vin across input; -- analog input values
quantity v_delayed : voltage; -- input voltage delayed
signal clk_delayed : bit; -- clk input port delayed
signal q_int : bit; -- q output with zero delay
begin
input_port_delay : block is
begin
v_delayed == vin'delayed(tipd_input);
clk_delayed <= clk'delayed(tipd_clk);
end block input_port_delay;
AD_conversion : block is
begin
q_int <= '1' when vin'above(threshold) else
'0';
end block AD_conversion;
output_port_delay : block is
begin
q <= q_int'delayed(topd_q);
end block output_port_delay;
end architecture detailed_timing;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1416.vhd | 4 | 1854 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1416.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b01x00p01n01i01416ent IS
END c08s05b01x00p01n01i01416ent;
ARCHITECTURE c08s05b01x00p01n01i01416arch OF c08s05b01x00p01n01i01416ent IS
BEGIN
TESTING: PROCESS
type ARAY_1 is array (INTEGER range <>) of BIT;
subtype SUB_ONE is ARAY_1 (1 to 10);
subtype SUB_TWO is ARAY_1 (1 to 100);
subtype SUB_THREE is ARAY_1 (41 to 60);
variable V1 : SUB_ONE;
variable V2 : SUB_TWO;
variable V3 : SUB_THREE;
BEGIN
V1 := V3;
assert FALSE
report "***FAILED TEST: c08s05b01x00p01n01i01416 - The number of components has to be the same."
severity NOTE;
wait;
END PROCESS TESTING;
END c08s05b01x00p01n01i01416arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1743.vhd | 4 | 1610 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1743.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p03n01i01743ent IS
END c09s05b00x00p03n01i01743ent;
ARCHITECTURE c09s05b00x00p03n01i01743arch OF c09s05b00x00p03n01i01743ent IS
signal err : bit;
BEGIN
B : block
begin
err <= transport guarded '1';
assert FALSE
report "***FAILED TEST: c09s05b00x00p03n01i01743 - Reserved word guarded must appear precede transport."
severity ERROR;
end block B;
END c09s05b00x00p03n01i01743arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc18.vhd | 4 | 2143 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc18.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p09n01i00018ent IS
END c04s02b00x00p09n01i00018ent;
ARCHITECTURE c04s02b00x00p09n01i00018arch OF c04s02b00x00p09n01i00018ent IS
BEGIN
TESTING: PROCESS
-- Define a subtype.
subtype DEC is INTEGER range 1 to 10;
-- Define a subtype based on DEC.
subtype DEC2 is DEC;
-- Define two variable counters.
variable CNT1, CNT2 : INTEGER := 0;
BEGIN
-- Verify that the range of DEC is the same as DEC2.
for I in DEC loop
CNT1 := CNT1 + 1;
end loop;
for I in DEC2 loop
CNT2 := CNT2 + 1;
end loop;
assert NOT( CNT1 = CNT2 )
report "***PASSED TEST: c04s02b00x00p09n01i00018"
severity NOTE;
assert ( CNT1 = CNT2 )
report "***FAILED TEST: c04s02b00x00p09n01i00018 - If the subtype indication does not indicate a type constraint, the subtype is the same as that denoted by the type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p09n01i00018arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2411.vhd | 4 | 1932 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2411.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p09n01i02411ent IS
END c07s03b02x00p09n01i02411ent;
ARCHITECTURE c07s03b02x00p09n01i02411arch OF c07s03b02x00p09n01i02411ent IS
type BIT_VECTOR is array
(natural range <>, natural range <>) of BIT;
BEGIN
TESTING: PROCESS
variable NUM1 : BIT_VECTOR(0 to 1, 0 to 7) := (
('0', '0'), ('1', '1'),
('0', '1'), ('1', '1'),
('0', '1'), ('0', '1'),
('0', '1'), ('1', '1'),
('1', '0'), ('1', '0')
); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x00p09n01i02411 - Each element of the value defined by an aggregate must be represented once and only once in the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p09n01i02411arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_11.vhd | 4 | 1721 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_11 is
end entity inline_11;
----------------------------------------------------------------
architecture test of inline_11 is
component comp is
end component comp;
signal clk_phase1, clk_phase2 : bit;
-- code from book:
group signal_pair is (signal, signal);
group clock_pair : signal_pair ( clk_phase1, clk_phase2 );
attribute max_skew : time;
attribute max_skew of clock_pair : group is 200 ps;
group component_instances is ( label <> );
group U1 : component_instances ( nand1, nand2, nand3 );
group U2 : component_instances ( inv1, inv2 );
attribute IC_allocation : string;
attribute IC_allocation of U1 : group is "74LS00";
attribute IC_allocation of U2 : group is "74LS04";
-- end of code from book
begin
nand1 : component comp;
nand2 : component comp;
nand3 : component comp;
inv1 : component comp;
inv2 : component comp;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_07.vhd | 4 | 1782 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_07.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity cpu is
end entity cpu;
-- end not in book
architecture behavioral of cpu is
begin
interpreter : process is
variable instr_reg : work.cpu_types.word;
variable instr_opcode : work.cpu_types.opcode;
begin
-- . . . -- initialize
loop
-- . . . -- fetch instruction
instr_opcode := work.cpu_types.extract_opcode ( instr_reg );
case instr_opcode is
when work.cpu_types.op_nop => null;
when work.cpu_types.op_breq => -- . . .
-- . . .
-- not in book
when others => null;
-- end not in book
end case;
end loop;
end process interpreter;
end architecture behavioral;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc831.vhd | 4 | 1699 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc831.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s03b00x00p02n01i00831ent IS
END c01s03b00x00p02n01i00831ent;
ARCHITECTURE c01s03b00x00p02n01i00831arch OF c01s03b00x00p02n01i00831ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s03b00x00p02n01i00831 - Missing entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b00x00p02n01i00831arch;
use work.all;
configuration C of c01s03b00x00p02n01i00831ent is
for c01s03b00x00p02n01i00831arch
use WORK.all ;
end for ;
C; -- Failure_here
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc110.vhd | 4 | 1965 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc110.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n06i00110ent IS
port (S1 : out BIT_VECTOR(0 to 3) := "1011");
END c04s03b02x00p29n06i00110ent;
ARCHITECTURE c04s03b02x00p29n06i00110arch OF c04s03b02x00p29n06i00110ent IS
signal S2,S3 : BIT;
BEGIN
TESTING: PROCESS
BEGIN
if (S1'LOW = 0) then
S2 <= '1' after 10 ns;
end if;
if (S1'HIGH = 3) then
S3 <= '1' after 10 ns;
end if;
wait for 20 ns;
assert NOT(S2='1' and S3='1')
report "***PASSED TEST: c04s03b02x00p29n06i00110"
severity NOTE;
assert (S2='1' and S3='1')
report "***FAILED TEST: c04s03b02x00p29n06i00110 - Reading of the attributes LOW and HIGH of the interface element of mode out is allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00110arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3148.vhd | 4 | 2516 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3148.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b02x00p08n01i03148ent_a IS
END c05s02b02x00p08n01i03148ent_a;
ARCHITECTURE c05s02b02x00p08n01i03148arch_a OF c05s02b02x00p08n01i03148ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s02b02x00p08n01i03148 - Architecture did not implicitly choose the most recently analyzed one for the entity."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03148arch_a;
--most recently analyzed ...
ARCHITECTURE c05s02b02x00p08n01i03148arch_b OF c05s02b02x00p08n01i03148ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c05s02b02x00p08n01i03148"
severity NOTE;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03148arch_b;
--
ENTITY c05s02b02x00p08n01i03148ent IS
END c05s02b02x00p08n01i03148ent;
ARCHITECTURE c05s02b02x00p08n01i03148arch OF c05s02b02x00p08n01i03148ent IS
begin
blk : block
component c05s02b02x00p08n01i03148ent_c
end component;
for comp1 : c05s02b02x00p08n01i03148ent_c use entity work.c05s02b02x00p08n01i03148ent_a;
BEGIN
comp1 : c05s02b02x00p08n01i03148ent_c;
end block;
END c05s02b02x00p08n01i03148arch;
configuration c05s02b02x00p08n01i03148_cfg of c05s02b02x00p08n01i03148ent is
for c05s02b02x00p08n01i03148arch
end for;
end c05s02b02x00p08n01i03148_cfg;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc981.vhd | 4 | 1828 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc981.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00981ent IS
END c06s03b00x00p05n01i00981ent;
ARCHITECTURE c06s03b00x00p05n01i00981arch OF c06s03b00x00p05n01i00981ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
type R2 is record
RE2: BOOLEAN;
end record;
variable V1: R1 ;
variable V10: BOOLEAN;
BEGIN
V10 := V1.TRUE;
-- SEMANTIC ERROR: NO SUCH RECORD ELEMENT;
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00981 - Illegal record element name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00981arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_02.vhd | 4 | 2513 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_12_fg_12_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book
entity D_flipflop is
generic ( Tpd_clk_q, Tsu_d_clk, Th_d_clk : delay_length );
port ( clk, d : in bit; q : out bit );
end entity D_flipflop;
--------------------------------------------------
architecture basic of D_flipflop is
begin
behavior : q <= d after Tpd_clk_q when clk = '1' and clk'event;
check_setup : process is
begin
wait until clk = '1';
assert d'last_event >= Tsu_d_clk
report "setup violation";
end process check_setup;
check_hold : process is
begin
wait until clk'delayed(Th_d_clk) = '1';
assert d'delayed'last_event >= Th_d_clk
report "hold violation";
end process check_hold;
end architecture basic;
-- end code from book
entity fg_12_02 is
end entity fg_12_02;
architecture test of fg_12_02 is
signal system_clock, request, request_pending : bit := '0';
begin
-- code from book (in text)
request_flipflop : entity work.D_flipflop(basic)
generic map ( Tpd_clk_q => 4 ns,
Tsu_d_clk => 3 ns, Th_d_clk => 1 ns )
port map ( clk => system_clock,
d => request, q => request_pending );
-- end code from book
clock_gen : system_clock <= '1' after 10 ns,
'0' after 20 ns when system_clock = '0';
stimulus : request <= '1' after 25 ns, '0' after 35 ns,
'1' after 67 ns, '0' after 71 ns,
'1' after 108 ns, '0' after 110.5 ns;
end architecture test;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue50/idct.d/muxb_322.vhd | 2 | 355 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity muxb_322 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end muxb_322;
architecture augh of muxb_322 is
begin
out_data <= in_data0 when in_sel = '0' else in_data1;
end architecture;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2123.vhd | 4 | 2240 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2123.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02123ent IS
END c07s02b04x00p20n01i02123ent;
ARCHITECTURE c07s02b04x00p20n01i02123arch OF c07s02b04x00p20n01i02123ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_4 is severity_level_v (1 to 4);
SUBTYPE severity_level_null is severity_level_v (1 to 0);
BEGIN
TESTING : PROCESS
variable result : severity_level_4;
variable l_operand : severity_level_4 := ( NOTE , FAILURE , NOTE , FAILURE );
variable r_operand : severity_level_null;
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT((result = (NOTE , FAILURE , NOTE , FAILURE)) and (result(1)=NOTE))
report "***PASSED TEST: c07s02b04x00p20n01i02123"
severity NOTE;
assert ((result = (NOTE , FAILURE , NOTE , FAILURE)) and (result(1)=NOTE))
report "***FAILED TEST: c07s02b04x00p20n01i02123 - Concatenation of null and SEVERITY_LEVEL arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02123arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2671.vhd | 4 | 1590 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2671.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02671ent IS
END c13s03b01x00p02n01i02671ent;
ARCHITECTURE c13s03b01x00p02n01i02671arch OF c13s03b01x00p02n01i02671ent IS
BEGIN
TESTING: PROCESS
variable `k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02671 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02671arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc655.vhd | 4 | 3143 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc655.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:55 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:21 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:33 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00655ent IS
END c03s04b01x00p01n01i00655ent;
ARCHITECTURE c03s04b01x00p01n01i00655arch OF c03s04b01x00p01n01i00655ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type integer_vector is array (natural range <>) of integer;
subtype integer_vector_range is integer_vector(hi_to_low_range);
constant C1 : integer_vector_range := (others => 3);
type integer_vector_range_file is file of integer_vector_range;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : integer_vector_range_file open read_mode is "iofile.03";
variable v : integer_vector_range := C1;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C1) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00655"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00655 - File reading of integer_vector_range_file operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00655arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc763.vhd | 4 | 8105 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc763.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00763pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level:= note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
end c01s01b01x01p05n02i00763pkg;
use work.c01s01b01x01p05n02i00763pkg.ALL;
ENTITY c01s01b01x01p05n02i00763ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen :integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen70 : boolean_vector_st :=(others => true);
Cgen71 : severity_level_vector_st :=(others => note);
Cgen72 : integer_vector_st :=(others => 3);
Cgen73 : real_vector_st :=(others => 3.0);
Cgen74 : time_vector_st :=(others => 3 ns);
Cgen75 : natural_vector_st :=(others => 1);
Cgen76 : positive_vector_st :=(others => 1)
);
END c01s01b01x01p05n02i00763ent;
ARCHITECTURE c01s01b01x01p05n02i00763arch OF c01s01b01x01p05n02i00763ent IS
signal Vgen1 : boolean := true;
signal Vgen2 : bit := '1';
signal Vgen3 : character := 's';
signal Vgen4 : severity_level:= note;
signal Vgen5 : integer := 3;
signal Vgen6 : real := 3.0;
signal Vgen7 : time := 3 ns;
signal Vgen8 : natural := 1;
signal Vgen9 : positive := 1;
signal Vgen70 : boolean_vector_st :=(others => Cgen1);
signal Vgen71 : severity_level_vector_st :=(others => Cgen4);
signal Vgen72 : integer_vector_st :=(others => Cgen5);
signal Vgen73 : real_vector_st :=(others => Cgen6);
signal Vgen74 : time_vector_st :=(others => Cgen7);
signal Vgen75 : natural_vector_st :=(others => Cgen8);
signal Vgen76 : positive_vector_st :=(others => Cgen9);
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***PASSED TEST: c01s01b01x01p05n02i00763"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***FAILED TEST: c01s01b01x01p05n02i00763 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00763arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1974.vhd | 4 | 4121 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1974.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01974ent IS
END c07s02b01x00p02n02i01974ent;
ARCHITECTURE c07s02b01x00p02n02i01974arch OF c07s02b01x00p02n02i01974ent IS
BEGIN
TESTING: PROCESS
constant L : BIT_VECTOR(1 to 4) := "0101";
constant R : BIT_VECTOR(1 to 4) := "0011";
constant N : BIT_VECTOR(1 TO 4) := not L;
constant A : BIT_VECTOR(1 TO 4) := L and R;
constant O : BIT_VECTOR(1 TO 4) := L or R;
constant NA : BIT_VECTOR(1 TO 4) := L nand R;
constant NO : BIT_VECTOR(1 TO 4) := L nor R;
constant X : BIT_VECTOR(1 TO 4) := L xor R;
BEGIN
assert N = "1010" report "FAIL: NOT";
assert A = "0001" report "FAIL: AND";
assert O = "0111" report "FAIL: OR";
assert NA = "1110" report "FAIL: NAND";
assert NO = "1000" report "FAIL: NOR";
assert X = "0110" report "FAIL: XOR";
assert N = not L report "FAIL: NOT (composite check)";
assert A = (L and R) report "FAIL: AND (composite check)";
assert O = (L or R) report "FAIL: OR (composite check)";
assert NA = (L nand R) report "FAIL: NAND (composite check)";
assert NO = (L nor R) report "FAIL: NOR (composite check)";
assert X = (L xor R) report "FAIL: XOR (composite check)";
for i in 1 to 4 loop
assert N(i) = not L(i) report "FAIL: NOT";
assert A(i) = (L(i) and R(i)) report "FAIL: AND";
assert O(i) = (L(i) or R(i)) report "FAIL: OR";
assert NA(i) = (L(i) nand R(i)) report "FAIL: NAND";
assert NO(i) = (L(i) nor R(i)) report "FAIL: NOR";
assert X(i) = (L(i) xor R(i)) report "FAIL: XOR";
end loop;
assert NOT( N = "1010" and
A = "0001" and
O = "0111" and
NA = "1110" and
NO = "1000" and
X = "0110" and
N = not L and
A = (L and R) and
O = (L or R) and
NA = (L nand R) and
NO = (L nor R) and
X = (L xor R) )
report "***PASSED TEST: c07s02b01x00p02n02i01974"
severity NOTE;
assert ( N = "1010" and
A = "0001" and
O = "0111" and
NA = "1110" and
NO = "1000" and
X = "0110" and
N = not L and
A = (L and R) and
O = (L or R) and
NA = (L nand R) and
NO = (L nor R) and
X = (L xor R) )
report "***FAILED TEST: c07s02b01x00p02n02i01974 - BIT_VECTOR type truth table test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01974arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/gna/issue123/adder.vhdl | 2 | 1858 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ADDER is
generic( WIDTH : positive := 8 );
port( CIN : in std_logic;
A : in std_logic_vector(WIDTH-1 downto 0);
B : in std_logic_vector(WIDTH-1 downto 0);
F : out std_logic_vector(WIDTH-1 downto 0);
COUT : out std_logic);
end entity ADDER;
-- Ripple Carry Adder
architecture RCA of ADDER is
signal CIN0 : unsigned(0 downto 0);
signal FIN : unsigned(WIDTH downto 0);
begin
CIN0(0) <= CIN;
FIN <= resize(unsigned(A), WIDTH+1) + resize(unsigned(B), WIDTH+1) + CIN0; -- yes, I know it's not a ripple carry adder
F <= std_logic_vector(FIN(WIDTH-1 downto 0));
COUT <= FIN(WIDTH);
end architecture RCA;
-- Carry Select Adder
architecture CSA of ADDER is
component ADDER is
generic( WIDTH : positive );
port( CIN : in std_logic;
A : in std_logic_vector(WIDTH-1 downto 0);
B : in std_logic_vector(WIDTH-1 downto 0);
F : out std_logic_vector(WIDTH-1 downto 0);
COUT : out std_logic);
end component ADDER;
signal F0, F1 : std_logic_vector(WIDTH-1 downto 0);
signal COUT0, COUT1 : std_logic;
begin
ADD0: ADDER generic map( WIDTH => WIDTH)
port map (
CIN => '0' ,
A => A ,
B => B ,
F => F0 ,
COUT => COUT0 );
ADD1: ADDER generic map( WIDTH => WIDTH)
port map (
CIN => '1' ,
A => A ,
B => B ,
F => F1 ,
COUT => COUT1 );
COUT <= COUT1 when CIN = '1' else COUT0;
F <= F1 when CIN = '1' else F0;
end architecture CSA;
-- here's the configuration
configuration CSAC of ADDER is
for CSA
for all: ADDER
use entity work.ADDER(RCA);
end for;
end for;
end configuration CSAC;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2286.vhd | 4 | 2016 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2286.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02286ent IS
END c07s02b06x00p14n01i02286ent;
ARCHITECTURE c07s02b06x00p14n01i02286arch OF c07s02b06x00p14n01i02286ent IS
BEGIN
TESTING: PROCESS
type PHYS is range 1 to 100000
units
A;
B = 100 A;
C = 100 B;
end units;
function F_PHYS ( A : PHYS ) return PHYS is
begin
return A;
end F_PHYS;
variable P : PHYS := 1 B;
variable Z : integer := time'(1 min) / time'(27 sec);
BEGIN
Z := P / F_PHYS(1 A);
assert NOT(Z = 100)
report "***PASSED TEST: c07s02b06x00p14n01i02286"
severity NOTE;
assert (Z = 100)
report "***FAILED TEST: c07s02b06x00p14n01i02286 - Incompatible operands: May not be multiplied or divided."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02286arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2683.vhd | 4 | 1661 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2683.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p02n01i02683ent IS
--ERROR: trailing decimal point not allowed
constant A1: REAL:=12.; -- failure_here
END c13s04b01x00p02n01i02683ent;
ARCHITECTURE c13s04b01x00p02n01i02683arch OF c13s04b01x00p02n01i02683ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s04b01x00p02n01i02683 - Integer should follow the dot in a real integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p02n01i02683arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_pkg.vhd | 4 | 2005 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package mem_pkg is
subtype word is bit_vector(0 to 31);
type word_array is array (natural range <>) of word;
procedure load_array ( words : out word_array; file_name : string );
end package mem_pkg;
--------------------------------------------------
package body mem_pkg is
procedure load_array ( words : out word_array; file_name : string ) is
-- words'path_name = ":project:mem_pkg:load_array:words"
use std.textio.all;
file load_file : text open read_mode is file_name;
-- load_file'path_name = ":project:mem_pkg:load_array:load_file"
procedure read_line is
-- read_line'path_name = ":project:mem_pkg:load_array:read_line:"
variable current_line : line;
-- current_line'path_name =
-- ":project:mem_pkg:load_array:read_line:current_line"
begin
-- . . .
-- not in book
report current_line'path_name;
-- end not in book
end procedure read_line;
begin -- load_array
-- . . .
-- not in book
report mem_pkg'path_name;
report words'path_name;
report load_file'path_name;
report read_line'path_name;
read_line;
-- end not in book
end procedure load_array;
end package body mem_pkg;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2676.vhd | 4 | 1900 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2676.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p05n01i02676ent IS
END c13s03b01x00p05n01i02676ent;
ARCHITECTURE c13s03b01x00p05n01i02676arch OF c13s03b01x00p05n01i02676ent IS
constant a234567_10_234567_20_234567a : integer := 2;
constant a234567_10_234567_20_234567b : integer := 7;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( a234567_10_234567_20_234567a /= a234567_10_234567_20_234567b )
report "***PASSED TEST: c13s03b01x00p05n01i02676"
severity NOTE;
assert ( a234567_10_234567_20_234567a /= a234567_10_234567_20_234567b )
report "***FAILED TEST: c13s03b01x00p05n01i02676 - All characters of an identifier are significant."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p05n01i02676arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc870.vhd | 4 | 12340 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc870.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00870pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
subtype dumy is integer range 0 to 3;
signal Sin1 : bit_vector(0 to 5) ;
signal Sin2 : boolean_vector(0 to 5) ;
signal Sin4 : severity_level_vector(0 to 5) ;
signal Sin5 : integer_vector(0 to 5) ;
signal Sin6 : real_vector(0 to 5) ;
signal Sin7 : time_vector(0 to 5) ;
signal Sin8 : natural_vector(0 to 5) ;
signal Sin9 : positive_vector(0 to 5) ;
signal Sin10: array_rec_std(0 to 5) ;
end c01s03b01x00p12n01i00870pkg;
use work.c01s03b01x00p12n01i00870pkg.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00870pkg.all;
entity test1 is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test1 of test1 is
begin
sigout1 <= false;
sigout2 <= '0';
sigout4 <= error;
sigout5 <= 6;
sigout6 <= 6.0;
sigout7 <= 6 ns;
sigout8 <= 6;
sigout9 <= 6;
sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
end;
configuration test1bench of test1 is
for test1
end for;
end;
use work.c01s03b01x00p12n01i00870pkg.all;
ENTITY c01s03b01x00p12n01i00870ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15);
port(
dumy : inout bit_vector(zero to three));
END c01s03b01x00p12n01i00870ent;
ARCHITECTURE c01s03b01x00p12n01i00870arch OF c01s03b01x00p12n01i00870ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test1
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test1
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
variable dumb : bit_vector(zero to three);
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(4) and
Sin2(0) = Sin2(4) and
Sin4(0) = Sin4(4) and
Sin5(0) = Sin5(4) and
Sin6(0) = Sin6(4) and
Sin7(0) = Sin7(4) and
Sin8(0) = Sin8(4) and
Sin9(0) = Sin9(4) and
Sin10(0)= Sin10(4) and
Sin1(5) = '0' and
Sin2(5) = FALSE and
Sin4(5) = error and
Sin5(5) = 6 and
Sin6(5) = 6.0 and
Sin7(5) = 6 ns and
Sin8(5) = 6 and
Sin9(5) = 6 and
Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
report "***PASSED TEST: c01s03b01x00p12n01i00870"
severity NOTE;
assert ( Sin1(0) = sin1(4) and
Sin2(0) = Sin2(4) and
Sin4(0) = Sin4(4) and
Sin5(0) = Sin5(4) and
Sin6(0) = Sin6(4) and
Sin7(0) = Sin7(4) and
Sin8(0) = Sin8(4) and
Sin9(0) = Sin9(4) and
Sin10(0)= Sin10(4) and
Sin1(5) = '0' and
Sin2(5) = FALSE and
Sin4(5) = error and
Sin5(5) = 6 and
Sin6(5) = 6.0 and
Sin7(5) = 6 ns and
Sin8(5) = 6 and
Sin9(5) = 6 and
Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
report "***FAILED TEST: c01s03b01x00p12n01i00870 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00870arch;
configuration c01s03b01x00p12n01i00870cfg of c01s03b01x00p12n01i00870ent is
for c01s03b01x00p12n01i00870arch
for K
for others:test1 use configuration work.test1bench;
end for;
for G(0 to 3)
for all :test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc911.vhd | 4 | 1921 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc911.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c10s03b00x00p07n01i00911ent_a is
end c10s03b00x00p07n01i00911ent_a;
architecture c10s03b00x00p07n01i00911arch_a of c10s03b00x00p07n01i00911ent_a is
begin
TESTING : PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c10s03b00x00p07n01i00911"
severity NOTE;
wait;
END PROCESS TESTING;
end c10s03b00x00p07n01i00911arch_a;
ENTITY c10s03b00x00p07n01i00911ent IS
END c10s03b00x00p07n01i00911ent;
ARCHITECTURE c10s03b00x00p07n01i00911arch OF c10s03b00x00p07n01i00911ent IS
component device
end component;
-- selected use of configuration primary unit
for all : device use entity work.c10s03b00x00p07n01i00911ent_a(c10s03b00x00p07n01i00911arch_a);
BEGIN
instance : device;
END c10s03b00x00p07n01i00911arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2772.vhd | 4 | 1599 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2772.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ABS is
end ABS;
ENTITY c13s09b00x00p99n01i02772ent IS
END c13s09b00x00p99n01i02772ent;
ARCHITECTURE c13s09b00x00p99n01i02772arch OF c13s09b00x00p99n01i02772ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02772 - Reserved word ABS can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02772arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1436.vhd | 4 | 1734 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1436.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01436ent IS
END c08s07b00x00p02n01i01436ent;
ARCHITECTURE c08s07b00x00p02n01i01436arch OF c08s07b00x00p02n01i01436ent IS
begin
TEST_PROCESS: process
variable I : INTEGER := 47;
begin
-- 'else' before 'elsif'.
if (I /= 47) then
NULL;
else
NULL;
elsif (I = 47) then
NULL;
end if;
assert FALSE
report "***FAILED TEST: c08s07b00x00p02n01i01436 - reserved word 'elsif' is misplaced"
severity ERROR;
wait;
end process TEST_PROCESS;
END c08s07b00x00p02n01i01436arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_latch.vhd | 4 | 1252 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_latch.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.dlx_types.all;
entity latch is
generic ( Tpd : delay_length );
port ( d : in dlx_word;
q : out dlx_word;
latch_en : in std_logic );
end entity latch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc832.vhd | 4 | 1698 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc832.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s03b00x00p02n01i00832ent IS
END c01s03b00x00p02n01i00832ent;
ARCHITECTURE c01s03b00x00p02n01i00832arch OF c01s03b00x00p02n01i00832ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s03b00x00p02n01i00832 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b00x00p02n01i00832arch;
use work.all;
configuration C of c01s03b00x00p02n01i00832ent is
for c01s03b00x00p02n01i00832arch
use WORK.all ;
end for ;
end C -- Failure_here
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1986.vhd | 4 | 5430 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1986.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01986ent IS
type omega is range (-100) to 100
units
o1;
o2 = 5 o1;
o3 = 10 o1;
end units;
END c07s02b02x00p02n01i01986ent;
ARCHITECTURE c07s02b02x00p02n01i01986arch OF c07s02b02x00p02n01i01986ent IS
BEGIN
TESTING: PROCESS
variable om1, om2, om3 : omega;
--alias in A of variable in A of E physical type
alias al1 : omega is om1;
alias al2 : omega is om2;
alias al3 : omega is om3;
BEGIN
om1 := 4 o1;
om2 := 5 o1;
om3 := 6 o1;
assert NOT( 5 o1 = 5 o1 and
5 o1 = abs(5 o1) and
5 o1 = abs(-5 o1) and
4 o1 /= 5 o1 and
4 o1 /= abs(5 o1) and
4 o1 /= abs(-5 o1) and
4 o1 <= 5 o1 and
4 o1 <= abs(5 o1) and
4 o1 <= abs(-5 o1) and
5 o1 <= abs(-5 o1) and
4 o1 < 5 o1 and
4 o1 < abs(5 o1) and
4 o1 < abs(-5 o1) and
6 o1 >= 5 o1 and
6 o1 >= abs(5 o1) and
6 o1 >= abs(-5 o1) and
5 o1 >= abs(-5 o1) and
6 o1 > 5 o1 and
6 o1 > abs(5 o1) and
6 o1 > abs(-5 o1) and
--relation operators with variables
om1 = om1 and
om2 = abs(om2) and
om2 = abs(-om2) and
om1 /= om2 and
om1 /= abs(om2) and
om1 /= abs(-om2) and
om1 <= om2 and
om1 <= abs(om2) and
om1 <= abs(-om2) and
om2 <= abs(-om2) and
om1 < om2 and
om1 < abs(om2) and
om1 < abs(-om2) and
om2 >= om1 and
om2 >= abs(om1) and
om2 >= abs(-om1) and
om2 >= abs(-om1) and
om2 > om1 and
om2 > abs(om1) and
om2 > abs(-om1) )
report "***PASSED TEST: c07s02b02x00p02n01i01986"
severity NOTE;
assert ( 5 o1 = 5 o1 and
5 o1 = abs(5 o1) and
5 o1 = abs(-5 o1) and
4 o1 /= 5 o1 and
4 o1 /= abs(5 o1) and
4 o1 /= abs(-5 o1) and
4 o1 <= 5 o1 and
4 o1 <= abs(5 o1) and
4 o1 <= abs(-5 o1) and
5 o1 <= abs(-5 o1) and
4 o1 < 5 o1 and
4 o1 < abs(5 o1) and
4 o1 < abs(-5 o1) and
6 o1 >= 5 o1 and
6 o1 >= abs(5 o1) and
6 o1 >= abs(-5 o1) and
5 o1 >= abs(-5 o1) and
6 o1 > 5 o1 and
6 o1 > abs(5 o1) and
6 o1 > abs(-5 o1) and
--relation operators with variables
om1 = om1 and
om2 = abs(om2) and
om2 = abs(-om2) and
om1 /= om2 and
om1 /= abs(om2) and
om1 /= abs(-om2) and
om1 <= om2 and
om1 <= abs(om2) and
om1 <= abs(-om2) and
om2 <= abs(-om2) and
om1 < om2 and
om1 < abs(om2) and
om1 < abs(-om2) and
om2 >= om1 and
om2 >= abs(om1) and
om2 >= abs(-om1) and
om2 >= abs(-om1) and
om2 > om1 and
om2 > abs(om1) and
om2 > abs(-om1) )
report "***FAILED TEST: c07s02b02x00p02n01i01986 - Relational operators truth table test for data type of Physical failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01986arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1527.vhd | 4 | 1670 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1527.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p08n01i01527ent IS
END c08s09b00x00p08n01i01527ent;
ARCHITECTURE c08s09b00x00p08n01i01527arch OF c08s09b00x00p08n01i01527ent IS
BEGIN
TESTING: PROCESS
variable NSS : integer := 5;
variable MIN : integer := 6;
BEGIN
while NSS * MIN loop
end loop;
assert FALSE
report "***FAILED TEST: c08s09b00x00p08n01i01527 - while condition is not boolean expression"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p08n01i01527arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2579.vhd | 4 | 1722 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2579.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s02b00x00p12n01i02579ent IS
port (PT:BOOLEAN) ;
ty
pe ONE is range 1 to 1;
--ERROR: RESERVED WORDS MUST FIT ON ONE LINE
END c13s02b00x00p12n01i02579ent;
ARCHITECTURE c13s02b00x00p12n01i02579arch OF c13s02b00x00p12n01i02579ent IS
b
egin
--ERROR: RESERVED WORDS MUST FIT ON ONE LINE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s02b00x00p12n01i02579 - Reserved words must fit on one line."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s02b00x00p12n01i02579arch;
| gpl-2.0 |
emogenet/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc358.vhd | 4 | 1687 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc358.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00358ent IS
END c03s02b01x01p02n01i00358ent;
ARCHITECTURE c03s02b01x01p02n01i00358arch OF c03s02b01x01p02n01i00358ent IS
type MVL1 is ('0', '1');
type MVL2 is ('X', 'Z');
type MVL3 is array(MVL1'LOW to MVL2'HIGH) of Integer; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00358 - Bounds are of different discrete types."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00358arch;
| gpl-2.0 |
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