repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc105.vhd | 4 | 1666 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc105.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n06i00105ent IS
port ( signal S : out bit) ;
END c04s03b02x00p29n06i00105ent;
ARCHITECTURE c04s03b02x00p29n06i00105arch OF c04s03b02x00p29n06i00105ent IS
BEGIN
TESTING: PROCESS
BEGIN
if (S'ACTIVE) then -- Failure_here
end if;
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n06i00105 - The attribute ACTIVE of a signal of mode out cannot be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00105arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1409.vhd | 4 | 1960 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1409.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b01x00p01n01i01409ent IS
END c08s05b01x00p01n01i01409ent;
ARCHITECTURE c08s05b01x00p01n01i01409arch OF c08s05b01x00p01n01i01409ent IS
BEGIN
TESTING: PROCESS
type A1 is array (positive range <>) of integer;
type A2 is array (0 to 10) of A1 (4 downto 1);
variable XC : A2;
BEGIN
XC (4) (1) := 1;
assert NOT(XC(4)(1) = 1)
report "***PASSED TEST: c08s05b01x00p01n01i01409"
severity NOTE;
assert (XC(4)(1) = 1)
report "***FAILED TEST: c08s05b01x00p01n01i01409 - The types of the right hand side and left hand side are the same and for each element of the array variable there is a matching element on the right hand side."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b01x00p01n01i01409arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2850.vhd | 4 | 1602 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2850.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity WITH is
end WITH;
ENTITY c13s09b00x00p99n01i02850ent IS
END c13s09b00x00p99n01i02850ent;
ARCHITECTURE c13s09b00x00p99n01i02850arch OF c13s09b00x00p99n01i02850ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02850 - Reserved word WITH can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02850arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1781.vhd | 4 | 4938 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1781.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
Package c09s06b00x00p04n05i01781pkg is
type info is record
field_1 : integer;
field_2 : real;
end record;
type stuff is array (Integer range 1 to 2) of info;
end c09s06b00x00p04n05i01781pkg;
use work.c09s06b00x00p04n05i01781pkg.all;
entity c09s06b00x00p04n05i01781ent_a is
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector ;
gB : stuff
);
end c09s06b00x00p04n05i01781ent_a;
use work.c09s06b00x00p04n05i01781pkg.all;
architecture c09s06b00x00p04n05i01781arch_a of c09s06b00x00p04n05i01781ent_a is
-- Check that the data was passed...
begin
TESTING: PROCESS
BEGIN
assert NOT( g0 = True and
g1 = '0' and
g2 = '@' and
g3 = NOTE and
g4 = 123456789 and
g5 = 987654321.5 and
g6 = 110 ns and
g7 = 12312 and
g8 = 3423 and
g9 = "16 characters OK" and
gA = B"01010010100101010010101001010100"and
gB = ((123, 456.7 ), (890, 135.7)))
report "***PASSED TEST: c09s06b00x00p04n05i01781"
severity NOTE;
assert ( g0 = True and
g1 = '0' and
g2 = '@' and
g3 = NOTE and
g4 = 123456789 and
g5 = 987654321.5 and
g6 = 110 ns and
g7 = 12312 and
g8 = 3423 and
g9 = "16 characters OK" and
gA = B"01010010100101010010101001010100"and
gB = ((123, 456.7 ), (890, 135.7)))
report "***FAILED TEST: c09s06b00x00p04n05i01781 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
end c09s06b00x00p04n05i01781arch_a;
-------------------------------------------------------------------------
ENTITY c09s06b00x00p04n05i01781ent IS
END c09s06b00x00p04n05i01781ent;
use work.c09s06b00x00p04n05i01781pkg.all;
ARCHITECTURE c09s06b00x00p04n05i01781arch OF c09s06b00x00p04n05i01781ent IS
subtype reg32 is Bit_vector ( 31 downto 0 );
subtype string16 is String ( 1 to 16 );
component MultiType
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector ;
gB : stuff
);
end component;
for u1 : MultiType use entity work.c09s06b00x00p04n05i01781ent_a(c09s06b00x00p04n05i01781arch_a);
BEGIN
u1 : MultiType
generic map (
True,
'0',
'@',
NOTE,
123456789,
987654321.5,
110 ns,
12312,
3423,
"16 characters OK",
B"0101_0010_1001_0101_0010_1010_0101_0100",
gB(2) => ( 890, 135.7 ),
gB(1) => ( 123, 456.7 )
);
END c09s06b00x00p04n05i01781arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket62/repro.vhdl | 3 | 310 | entity ent is
end;
architecture behav of ent is
shared variable v : integer;
begin
process
begin
v := 2;
wait for 2 ns;
assert v = 5 severity failure;
wait;
end process;
process
begin
wait for 1 ns;
assert v = 2 severity failure;
v := 5;
wait;
end process;
end;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc161.vhd | 4 | 2175 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc161.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p19n04i00161ent IS
PORT ( SIGNAL a : IN bit;
SIGNAL b : IN integer;
SIGNAL c : IN boolean;
SIGNAL d : IN time;
SIGNAL e,f : IN real;
SIGNAL oint : INOUT integer);
END c04s03b02x02p19n04i00161ent;
ARCHITECTURE c04s03b02x02p19n04i00161arch OF c04s03b02x02p19n04i00161ent IS
function funct1( fpar1 :bit :='1';
fpar2 :integer:=455;
fpar3 :boolean:=true;
fpar4 :time :=55.77 ns;
fpar5 :real :=34.558) return integer is
begin
return 1;
end funct1;
BEGIN
TESTING: PROCESS
BEGIN
wait for 1 ns;
oint <= funct1(fpar5=>f,fpar3=>c,fpar2=>b,fpar1=>a,fpar4=>d,fpar5=>e);
assert FALSE
report "***FAILED TEST: c04s03b02x02p19n04i00161 - Same formal parameter name can not be used more than once."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p19n04i00161arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2333.vhd | 4 | 1713 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2333.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02333ent IS
END c07s02b07x00p02n02i02333ent;
ARCHITECTURE c07s02b07x00p02n02i02333arch OF c07s02b07x00p02n02i02333ent IS
BEGIN
TESTING: PROCESS
type SWITCH_LEVEL is ('0', '1', 'X');
variable SWITCHV : SWITCH_LEVEL := '0';
variable INTV : INTEGER;
BEGIN
INTV := SWITCHV ** 2;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02333 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02333arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc625.vhd | 4 | 6627 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc625.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:46 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00625ent IS
END c03s04b01x00p01n01i00625ent;
ARCHITECTURE c03s04b01x00p01n01i00625arch OF c03s04b01x00p01n01i00625ent IS
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
i: record_array_st;
end record;
type record_of_records_file is file of record_of_records;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 3;
constant C9 : positive := 3;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C28 : boolean_vector_st :=(others => C1);
constant C29 : severity_level_vector_st:= (others => C4);
constant C30 : integer_vector_st:=(others => C5);
constant C31 : real_vector_st:=(others => C6);
constant C32 : time_vector_st:=(others => C7);
constant C33 : natural_vector_st:=(others => C8);
constant C34 : positive_vector_st:=(others => C9);
constant C35 : record_array_st := (C28,C29,C30,C31,C32,C33,C34);
constant C37 : record_of_records := (C26,C27,C35);
BEGIN
TESTING: PROCESS
file filein : record_of_records_file open write_mode is "iofile.35";
BEGIN
for i in 1 to 100 loop
write(filein, C37);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00625 - The output file will be verified by test s010272.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00625arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2495.vhd | 4 | 2070 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2495.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p04n02i02495ent IS
END c07s03b03x00p04n02i02495ent;
ARCHITECTURE c07s03b03x00p04n02i02495arch OF c07s03b03x00p04n02i02495ent IS
BEGIN
TESTING: PROCESS
function check (x:integer; y:boolean; z1:real; z2:real:= 1.3)
return boolean is
begin
if y then
return true;
end if;
return false;
end;
variable p: integer := 3;
variable q: boolean := true;
variable s: boolean;
variable r: real;
BEGIN
s := check (p, q, r); -- No_failure_here
assert NOT( s=true )
report "***PASSED TEST: c07s03b03x00p04n02i02495"
severity NOTE;
assert ( s=true )
report "***FAILED TEST: c07s03b03x00p04n02i02495 - The actual parameter can be specified explicitly by an association element in the association list."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p04n02i02495arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1358.vhd | 4 | 1645 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1358.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01358ent IS
END c08s05b00x00p03n01i01358ent;
ARCHITECTURE c08s05b00x00p03n01i01358arch OF c08s05b00x00p03n01i01358ent IS
signal s : integer := 0;
BEGIN
TESTING: PROCESS
variable i : integer := 12;
BEGIN
s := i;
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01358 - Target of a variable assignment is not a variable."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01358arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/integer-variable-persist-across-activations.vhdl | 4 | 468 | entity foo is
end foo;
use std.textio.all;
architecture only of foo is
signal clock : bit;
begin -- only
process (clock)
variable x : integer := 0;
variable l : line;
begin -- process
write( l, string'( "x = " ) );
write( l, x );
writeline( output, l );
x := x + 1;
end process;
process
begin -- process
clock <= '1' after 1 ns,
'0' after 2 ns,
'1' after 3 ns;
wait;
end process;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug14/bug.vhdl | 3 | 248 | package pkg is
function f (a : integer) return integer;
end pkg;
package body pkg is
function f (a : integer) return integer is
begin
return 1;
end f;
function f (a : integer) return integer is
begin
return 1;
end f;
end pkg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1138.vhd | 4 | 1888 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1138.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p05n02i01138ent IS
END c06s05b00x00p05n02i01138ent;
ARCHITECTURE c06s05b00x00p05n02i01138arch OF c06s05b00x00p05n02i01138ent IS
signal T1 : boolean;
BEGIN
TESTING: PROCESS
variable B : Bit_vector (1 to 10) := B"01010_10101";
BEGIN
if B(1 to 2) = B"01" then
T1 <= TRUE;
else
T1 <= FALSE;
end if;
wait for 1 ns;
assert NOT(T1=TRUE)
report "***PASSED TEST: c06s05b00x00p05n02i01138"
severity NOTE;
assert (T1=TRUE)
report "***FAILED TEST: c06s05b00x00p05n02i01138 - The prefix and the discrete range of the slice is not correctly evaluated."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p05n02i01138arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1693.vhd | 4 | 1882 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1693.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p03n01i01693ent IS
port (B:BIT; C:out BIT) ;
END c09s02b00x00p03n01i01693ent;
ARCHITECTURE c09s02b00x00p03n01i01693arch OF c09s02b00x00p03n01i01693ent IS
BEGIN
process
begin
architecture B6 of E1 is -- Failure_here
--SEMANTICS ERROR: body declarations may not be in a process statement.
begin
process
begin
null;
end process;
end B6;
null;
end process;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p03n01i01693 - Body declarations are not allowed in process statements."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p03n01i01693arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_05.vhd | 4 | 2216 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_ch_16_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_16_05 is
end entity ch_16_05;
----------------------------------------------------------------
architecture test of ch_16_05 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
-- code from book:
signal source_bus_1, source_bus_2 : resolved_word bus;
signal address_bus : resolved_word bus;
disconnect all : resolved_word after 2 ns;
-- end of code from book
signal s : word;
signal g : boolean;
begin
b : block (g) is
begin
source_bus_1 <= guarded s after 4 ns;
source_bus_2 <= guarded s after 4 ns;
address_bus <= guarded s after 4 ns;
end block b;
stimulus : process is
begin
s <= X"DDDDDDDD";
wait for 10 ns;
g <= true;
wait for 10 ns;
s <= X"AAAAAAAA";
wait for 10 ns;
g <= false;
wait for 10 ns;
s <= X"11111111";
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket77/bug2.vhdl | 3 | 206 | entity ent2 is
end entity;
architecture a of ent2 is
begin
main : process
begin
-- wait for 0 ns; -- Comment and it exits with code 1
std.env.stop(1);
wait;
end process;
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc524.vhd | 4 | 4694 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc524.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00524ent IS
END c03s03b00x00p03n04i00524ent;
ARCHITECTURE c03s03b00x00p03n04i00524arch OF c03s03b00x00p03n04i00524ent IS
BEGIN
TESTING: PROCESS
type integer_ptr is access integer;
variable v_integer_ptr1: integer_ptr := new integer'(365);
variable v_integer_ptr2: integer_ptr;
variable v_integer_ptr3: integer_ptr := v_integer_ptr1;
type int is range -500 to 500;
type int_ptr is access int;
variable v_int_ptr1: int_ptr := new int'(365);
variable v_int_ptr2: int_ptr;
variable v_int_ptr3: int_ptr := v_int_ptr1;
variable v_int_ptr4: int_ptr := new int'(-365);
variable OKtest : integer := 0;
BEGIN
assert v_integer_ptr1.all = 365;
if (v_integer_ptr1.all = 365) then
Oktest := OKtest + 1;
end if;
assert v_integer_ptr2 = null;
if (v_integer_ptr2 = null) then
Oktest := OKtest + 1;
end if;
assert v_integer_ptr3.all = 365;
if (v_integer_ptr3.all = 365) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr1.all + v_integer_ptr3.all) = 730;
if ((v_integer_ptr1.all + v_integer_ptr3.all) = 730) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr1.all - v_integer_ptr3.all) = 0;
if ((v_integer_ptr1.all - v_integer_ptr3.all) = 0) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr3.all * v_integer_ptr1.all) = 133225;
if ((v_integer_ptr3.all * v_integer_ptr1.all) = 133225) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr3.all / v_integer_ptr1.all) = 1;
if ((v_integer_ptr3.all / v_integer_ptr1.all) = 1) then
Oktest := OKtest + 1;
end if;
deallocate(v_integer_ptr2);
deallocate(v_integer_ptr1);
assert v_int_ptr1.all = 365;
if (v_int_ptr1.all = 365) then
Oktest := OKtest + 1;
end if;
assert v_int_ptr2 = null;
if (v_int_ptr2 = null) then
Oktest := OKtest + 1;
end if;
assert v_int_ptr3.all = 365;
if (v_int_ptr3.all = 365) then
Oktest := OKtest + 1;
end if;
assert v_int_ptr4.all = -365;
if (v_int_ptr4.all = -365) then
Oktest := OKtest + 1;
end if;
v_int_ptr2 := new int'(100);
assert v_int_ptr2.all = 100;
if (v_int_ptr2.all = 100) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr1.all + v_int_ptr3.all) = 730;
if ((v_int_ptr1.all + v_int_ptr3.all) = 730) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr2.all + v_int_ptr3.all) = 465;
if ((v_int_ptr2.all + v_int_ptr3.all) = 465) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr1.all + v_int_ptr4.all) = 0;
if ((v_int_ptr1.all + v_int_ptr4.all) = 0) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr1.all - v_int_ptr3.all) = 0;
if ((v_int_ptr1.all - v_int_ptr3.all) = 0) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr3.all * v_int_ptr1.all) = 133225;
if ((v_int_ptr3.all * v_int_ptr1.all) = 133225) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr3.all / v_int_ptr1.all) = 1;
if ((v_int_ptr3.all / v_int_ptr1.all) = 1) then
Oktest := OKtest + 1;
end if;
assert NOT(OKtest = 18)
report "***PASSED TEST: c03s03b00x00p03n04i00524"
severity NOTE;
assert (OKtest = 18)
report "***FAILED TEST: c03s03b00x00p03n04i00524 - Integer type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00524arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/perf02/mul_156.vhd | 3 | 503 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_156 is
port (
output : out std_logic_vector(63 downto 0);
in_a : in std_logic_vector(32 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end mul_156;
architecture augh of mul_156 is
signal tmp_res : signed(64 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
output <= std_logic_vector(tmp_res(63 downto 0));
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc652.vhd | 4 | 2017 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc652.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:54 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00652ent IS
END c03s04b01x00p01n01i00652ent;
ARCHITECTURE c03s04b01x00p01n01i00652arch OF c03s04b01x00p01n01i00652ent IS
subtype delay is integer range 1 to 10;
type delay_file is file of delay;
constant C47 : delay := 2;
BEGIN
TESTING: PROCESS
file filein : delay_file open write_mode is "iofile.45";
BEGIN
for i in 1 to 100 loop
write(filein, C47);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00652 - The output file will be verified by test s010296.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00652arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_06.vhd | 4 | 1593 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
architecture test of inline_06 is
signal y : bit := '0';
signal or_a_b : bit := '0';
signal clk : bit := '0';
begin
process_3_a : process is
begin
-- code from book:
y <= not or_a_b after 5 ns;
-- end of code from book
wait on or_a_b;
end process process_3_a;
stimulus_3_a : process is
begin
or_a_b <= '1' after 20 ns,
'0' after 40 ns;
wait;
end process stimulus_3_a;
process_3_b : process is
constant T_pw : delay_length := 10 ns;
begin
-- code from book:
clk <= '1' after T_pw, '0' after 2*T_pw;
-- end of code from book
wait for 2*T_pw;
end process process_3_b;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1639.vhd | 4 | 1951 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1639.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p06n01i01639ent IS
END c08s12b00x00p06n01i01639ent;
ARCHITECTURE c08s12b00x00p06n01i01639arch OF c08s12b00x00p06n01i01639ent IS
BEGIN
TESTING: PROCESS
variable correct : boolean := true;
procedure Proc1(constant p_boolean :boolean ) is
begin
if p_boolean = p_boolean then
return;
else
return;
end if;
correct := false;
end Proc1;
BEGIN
Proc1(false);
assert NOT( correct = true )
report "***PASSED TEST: c08s12b00x00p06n01i01639"
severity NOTE;
assert ( correct = true )
report "***FAILED TEST: c08s12b00x00p06n01i01639 - A return statement stops execution of a procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p06n01i01639arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc755.vhd | 4 | 57757 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc755.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x01p05n02i00755ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END c01s01b01x01p05n02i00755ent;
ARCHITECTURE c01s01b01x01p05n02i00755arch OF c01s01b01x01p05n02i00755ent IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector ;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b : record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78 : boolean_vector_range := (others => C1);
constant C79 : severity_level_vector_range := (others => C4) ;
constant C80 : integer_vector_range :=(others => C5) ;
constant C81 : real_vector_range :=(others => C6);
constant C82 : time_vector_range :=(others => C7);
constant C83 : natural_vector_range :=(others => C8);
constant C84 : positive_vector_range :=(others => C9);
constant C85 : array_rec_std(0 to 7) :=(others => C50) ;
constant C86 : array_rec_cons (0 to 7) :=(others => C51);
constant C88 : array_rec_rec(0 to 7) :=(others => C55);
constant C102 : record_of_arr_of_record:= (C85,C86,C88);
signal S1 : boolean_vector(zero to fifteen);
signal S2 : severity_level_vector(zero to fifteen);
signal S3 : integer_vector(zero to fifteen);
signal S4 : real_vector(zero to fifteen);
signal S5 : time_vector (zero to fifteen);
signal S6 : natural_vector(zero to fifteen);
signal S7 : positive_vector(zero to fifteen);
signal S8 : boolean_cons_vector;
signal S9 : severity_level_cons_vector ;
signal S10 : integer_cons_vector;
signal S11 : real_cons_vector;
signal S12 : time_cons_vector ;
signal S13 : natural_cons_vector ;
signal S14 : positive_cons_vector ;
signal S15 : boolean_cons_vectorofvector;
signal S16 : severity_level_cons_vectorofvector;
signal S17 : integer_cons_vectorofvector;
signal S18 : real_cons_vectorofvector;
signal S19 : time_cons_vectorofvector;
signal S20 : natural_cons_vectorofvector;
signal S21 : positive_cons_vectorofvector;
signal S22 : record_std_package;
signal S23 : record_cons_array;
signal S24 : record_cons_arrayofarray ;
signal S25 : boolean_vector_st;
signal S26 : severity_level_vector_st;
signal S27 : integer_vector_st;
signal S28 : real_vector_st;
signal S29 : time_vector_st;
signal S30 : natural_vector_st;
signal S31 : positive_vector_st;
signal S32 : record_array_st;
signal S33 : record_array_st;
signal S34 : record_array_new;
signal S35 : record_of_records;
signal S36 : byte;
signal S37 : word;
signal S38 : current_vector(zero to three);
signal S39 : resistance_vector(zero to three);
signal S40 : delay;
signal S41 : boolean_vector_range;
signal S42 : severity_level_vector_range ;
signal S43 : integer_vector_range ;
signal S44 : real_vector_range ;
signal S45 : time_vector_range ;
signal S46 : natural_vector_range ;
signal S47 : positive_vector_range ;
signal S48 : array_rec_std(zero to seven);
signal S49 : array_rec_cons(zero to seven);
signal S50 : array_rec_rec(zero to seven);
signal S51 : record_of_arr_of_record;
BEGIN
assert (S1'left = 0) report " boolean_vector(zero to fifteen) error in the left generic value" severity error;
assert (S2'left = 0) report " severity_level_vector(zero to fifteen) error in the left generic value" severity error;
assert (S3'left = 0) report " integer_vector(zero to fifteen) error in the left generic value" severity error;
assert (S4'left = 0) report " real_vector(zero to fifteen) error in the left generic value" severity error;
assert (S5'left = 0) report " time_vector (zero to fifteen) error in the left generic value" severity error;
assert (S6'left = 0) report " natural_vector(zero to fifteen) error in the left generic value" severity error;
assert (S7'left = 0) report " positive_vector(zero to fifteen) error in the left generic value" severity error;
assert (S8'left = 15) report " boolean_cons_vector error in the left generic value" severity error;
assert (S9'left = 15) report " severity_level_cons_vector error in the left generic value" severity error;
assert (S10'left = 15) report " integer_cons_vector error in the left generic value" severity error;
assert (S11'left = 15) report " real_cons_vector error in the left generic value" severity error;
assert (S12'left = 15) report " time_cons_vector error in the left generic value" severity error;
assert (S13'left = 15) report " natural_cons_vector error in the left generic value" severity error;
assert (S14'left = 15) report " positive_cons_vector error in the left generic value" severity error;
assert (S15'left = 0) report " boolean_cons_vectorofvector error in the left generic value" severity error;
assert (S16'left = 0) report " severity_level_cons_vectorofvector error in the left generic value" severity error;
assert (S17'left = 0) report " integer_cons_vectorofvector error in the left generic value" severity error;
assert (S18'left = 0) report " real_cons_vectorofvector error in the left generic value" severity error;
assert (S19'left = 0) report " time_cons_vectorofvector error in the left generic value" severity error;
assert (S20'left = 0) report " natural_cons_vectorofvector error in the left generic value" severity error;
assert (S21'left = 0) report " positive_cons_vectorofvector error in the left generic value" severity error;
assert (S22.j'left = 1) report " record_std_package error in the left generic value" severity error;
assert (S22.k'left = 0) report " record_std_package error in the left generic value" severity error;
assert (S23.a'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.b'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.c'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.d'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.e'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.f'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.g'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S24.a'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.b'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.c'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.d'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.e'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.f'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.g'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S25'left = 0) report " boolean_vector_st error in the left generic value" severity error;
assert (S26'left = 0) report " severity_level_vector_st error in the left generic value" severity error;
assert (S27'left = 0) report " integer_vector_st error in the left generic value" severity error;
assert (S28'left = 0) report " real_vector_st error in the left generic value" severity error;
assert (S29'left = 0) report " time_vector_st error in the left generic value" severity error;
assert (S30'left = 0) report " natural_vector_st error in the left generic value" severity error;
assert (S31'left = 0) report " positive_vector_st error in the left generic value" severity error;
assert (S32.a'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.b'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.c'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.d'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.e'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.f'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.g'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S34.a'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.b'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.c'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.d'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.e'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.f'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.g'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S36'left = 0) report " byte error in the left generic value" severity error;
assert (S37'left = 0) report " word error in the left generic value" severity error;
assert (S38'left = 0) report " current_vector(zero to three) error in the left generic value" severity error;
assert (S39'left = 0) report " resistance_vector(zero to three) error in the left generic value" severity error;
--assert (S40'left = 1) report " delay error in the left generic value" severity error;
assert (S41'left = 0) report " boolean_vector_range error in the left generic value" severity error;
assert (S42'left = 0) report " severity_level_vector_range error in the left generic value" severity error;
assert (S43'left = 0) report " integer_vector_range error in the left generic value" severity error;
assert (S44'left = 0) report " real_vector_range error in the left generic value" severity error;
assert (S45'left = 0) report " time_vector_range error in the left generic value" severity error;
assert (S46'left = 0) report " natural_vector_range error in the left generic value" severity error;
assert (S47'left = 0) report " positive_vector_range error in the left generic value" severity error;
assert (S48'left = 0) report " array_rec_std(zero to seven) error in the left generic value" severity error;
assert (S49'left = 0) report " array_rec_cons(zero to seven) error in the left generic value" severity error;
assert (S50'left = 0) report " array_rec_rec(zero to seven) error in the left generic value" severity error;
assert (S51.a'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (S51.b'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (S51.c'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (S1'right = 15) report " boolean_vector(zero to fifteen) error in the right generic value" severity error;
assert (S2'right = 15) report " severity_level_vector(zero to fifteen) error in the right generic value" severity error;
assert (S3'right = 15) report " integer_vector(zero to fifteen) error in the right generic value" severity error;
assert (S4'right = 15) report " real_vector(zero to fifteen) error in the right generic value" severity error;
assert (S5'right = 15) report " time_vector (zero to fifteen) error in the right generic value" severity error;
assert (S6'right = 15) report " natural_vector(zero to fifteen) error in the right generic value" severity error;
assert (S7'right = 15) report " positive_vector(zero to fifteen) error in the right generic value" severity error;
assert (S8'right = 0) report " boolean_cons_vector error in the right generic value" severity error;
assert (S9'right = 0) report " severity_level_cons_vector error in the right generic value" severity error;
assert (S10'right = 0) report " integer_cons_vector error in the right generic value" severity error;
assert (S11'right = 0) report " real_cons_vector error in the right generic value" severity error;
assert (S12'right = 0) report " time_cons_vector error in the right generic value" severity error;
assert (S13'right = 0) report " natural_cons_vector error in the right generic value" severity error;
assert (S14'right = 0) report " positive_cons_vector error in the right generic value" severity error;
assert (S15'right = 15) report " boolean_cons_vectorofvector error in the right generic value" severity error;
assert (S16'right = 15) report " severity_level_cons_vectorofvector error in the right generic value" severity error;
assert (S17'right = 15) report " integer_cons_vectorofvector error in the right generic value" severity error;
assert (S18'right = 15) report " real_cons_vectorofvector error in the right generic value" severity error;
assert (S19'right = 15) report " time_cons_vectorofvector error in the right generic value" severity error;
assert (S20'right = 15) report " natural_cons_vectorofvector error in the right generic value" severity error;
assert (S21'right = 15) report " positive_cons_vectorofvector error in the right generic value" severity error;
assert (S22.j'right = 7) report " record_std_package error in the right generic value" severity error;
assert (S22.k'right = 3) report " record_std_package error in the right generic value" severity error;
assert (S23.a'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.b'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.c'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.d'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.e'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.f'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.g'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S24.a'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.b'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.c'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.d'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.e'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.f'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.g'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S25'right = 15) report " boolean_vector_st error in the right generic value" severity error;
assert (S26'right = 15) report " severity_level_vector_st error in the right generic value" severity error;
assert (S27'right = 15) report " integer_vector_st error in the right generic value" severity error;
assert (S28'right = 15) report " real_vector_st error in the right generic value" severity error;
assert (S29'right = 15) report " time_vector_st error in the right generic value" severity error;
assert (S30'right = 15) report " natural_vector_st error in the right generic value" severity error;
assert (S31'right = 15) report " positive_vector_st error in the right generic value" severity error;
assert (S32.a'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.b'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.c'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.d'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.e'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.f'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.g'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S34.a'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.b'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.c'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.d'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.e'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.f'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.g'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S36'right = 7) report " byte error in the right generic value" severity error;
assert (S37'right = 15) report " word error in the right generic value" severity error;
assert (S38'right = 3) report " current_vector(zero to three) error in the right generic value" severity error;
assert (S39'right = 3) report " resistance_vector(zero to three) error in the right generic value" severity error;
--assert (S40'right = 1) report " delay error in the right generic value" severity error;
assert (S41'right = 7) report " boolean_vector_range error in the right generic value" severity error;
assert (S42'right = 7) report " severity_level_vector_range error in the right generic value" severity error;
assert (S43'right = 7) report " integer_vector_range error in the right generic value" severity error;
assert (S44'right = 7) report " real_vector_range error in the right generic value" severity error;
assert (S45'right = 7) report " time_vector_range error in the right generic value" severity error;
assert (S46'right = 7) report " natural_vector_range error in the right generic value" severity error;
assert (S47'right = 7) report " positive_vector_range error in the right generic value" severity error;
assert (S48'right = 7) report " array_rec_std(zero to seven) error in the right generic value" severity error;
assert (S49'right = 7) report " array_rec_cons(zero to seven) error in the right generic value" severity error;
assert (S50'right = 7) report " array_rec_rec(zero to seven) error in the right generic value" severity error;
assert (S51.a'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (S51.b'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (S51.c'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (S1'length = 16) report " boolean_vector(zero to fifteen) error in the length generic value" severity error;
assert (S2'length = 16) report " severity_level_vector(zero to fifteen) error in the length generic value" severity error;
assert (S3'length = 16) report " integer_vector(zero to fifteen) error in the length generic value" severity error;
assert (S4'length = 16) report " real_vector(zero to fifteen) error in the length generic value" severity error;
assert (S5'length = 16) report " time_vector (zero to fifteen) error in the length generic value" severity error;
assert (S6'length = 16) report " natural_vector(zero to fifteen) error in the length generic value" severity error;
assert (S7'length = 16) report " positive_vector(zero to fifteen) error in the length generic value" severity error;
assert (S8'length = 16) report " boolean_cons_vector error in the length generic value" severity error;
assert (S9'length = 16) report " severity_level_cons_vector error in the length generic value" severity error;
assert (S10'length = 16) report " integer_cons_vector error in the length generic value" severity error;
assert (S11'length = 16) report " real_cons_vector error in the length generic value" severity error;
assert (S12'length = 16) report " time_cons_vector error in the length generic value" severity error;
assert (S13'length = 16) report " natural_cons_vector error in the length generic value" severity error;
assert (S14'length = 16) report " positive_cons_vector error in the length generic value" severity error;
assert (S15'length = 16) report " boolean_cons_vectorofvector error in the length generic value" severity error;
assert (S16'length = 16) report " severity_level_cons_vectorofvector error in the length generic value" severity error;
assert (S17'length = 16) report " integer_cons_vectorofvector error in the length generic value" severity error;
assert (S18'length = 16) report " real_cons_vectorofvector error in the length generic value" severity error;
assert (S19'length = 16) report " time_cons_vectorofvector error in the length generic value" severity error;
assert (S20'length = 16) report " natural_cons_vectorofvector error in the length generic value" severity error;
assert (S21'length = 16) report " positive_cons_vectorofvector error in the length generic value" severity error;
assert (S22.j'length = 7) report " record_std_package error in the length generic value" severity error;
assert (S22.k'length = 4) report " record_std_package error in the length generic value" severity error;
assert (S23.a'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.b'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.c'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.d'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.e'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.f'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.g'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S24.a'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.b'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.c'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.d'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.e'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.f'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.g'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S25'length = 16) report " boolean_vector_st error in the length generic value" severity error;
assert (S26'length = 16) report " severity_level_vector_st error in the length generic value" severity error;
assert (S27'length = 16) report " integer_vector_st error in the length generic value" severity error;
assert (S28'length = 16) report " real_vector_st error in the length generic value" severity error;
assert (S29'length = 16) report " time_vector_st error in the length generic value" severity error;
assert (S30'length = 16) report " natural_vector_st error in the length generic value" severity error;
assert (S31'length = 16) report " positive_vector_st error in the length generic value" severity error;
assert (S32.a'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.b'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.c'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.d'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.e'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.f'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.g'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S34.a'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.b'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.c'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.d'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.e'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.f'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.g'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S36'length = 8) report " byte error in the length generic value" severity error;
assert (S37'length = 16) report " word error in the length generic value" severity error;
assert (S38'length = 4) report " current_vector(zero to three) error in the length generic value" severity error;
assert (S39'length = 4) report " resistance_vector(zero to three) error in the length generic value" severity error;
--assert (S40'length = 1) report " delay error in the length generic value" severity error;
assert (S41'length = 8) report " boolean_vector_range error in the length generic value" severity error;
assert (S42'length = 8) report " severity_level_vector_range error in the length generic value" severity error;
assert (S43'length = 8) report " integer_vector_range error in the length generic value" severity error;
assert (S44'length = 8) report " real_vector_range error in the length generic value" severity error;
assert (S45'length = 8) report " time_vector_range error in the length generic value" severity error;
assert (S46'length = 8) report " natural_vector_range error in the length generic value" severity error;
assert (S48'length = 8) report " positive_vector_range error in the length generic value" severity error;
assert (S48'length = 8) report " array_rec_std(zero to seven) error in the length generic value" severity error;
assert (S49'length = 8) report " array_rec_cons(zero to seven) error in the length generic value" severity error;
assert (S50'length = 8) report " array_rec_rec(zero to seven) error in the length generic value" severity error;
assert (S51.a'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
assert (S51.b'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
assert (S51.c'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
TESTING: PROCESS
BEGIN
assert NOT( (S1'left = 0) and
(S2'left = 0) and
(S3'left = 0) and
(S4'left = 0) and
(S5'left = 0) and
(S6'left = 0) and
(S7'left = 0) and
(S8'left = 15) and
(S9'left = 15) and
(S10'left = 15) and
(S11'left = 15) and
(S12'left = 15) and
(S13'left = 15) and
(S14'left = 15) and
(S15'left = 0) and
(S16'left = 0) and
(S17'left = 0) and
(S18'left = 0) and
(S19'left = 0) and
(S20'left = 0) and
(S21'left = 0) and
(S22.j'left = 1) and
(S22.k'left = 0) and
(S23.a'left = 15) and
(S23.b'left = 15) and
(S23.c'left = 15) and
(S23.d'left = 15) and
(S23.e'left = 15) and
(S23.f'left = 15) and
(S23.g'left = 15) and
(S24.a'left = 0) and
(S24.b'left = 0) and
(S24.c'left = 0) and
(S24.d'left = 0) and
(S24.e'left = 0) and
(S24.f'left = 0) and
(S24.g'left = 0) and
(S25'left = 0) and
(S26'left = 0) and
(S27'left = 0) and
(S28'left = 0) and
(S29'left = 0) and
(S30'left = 0) and
(S31'left = 0) and
(S32.a'left = 0) and
(S32.b'left = 0) and
(S32.c'left = 0) and
(S32.d'left = 0) and
(S32.e'left = 0) and
(S32.f'left = 0) and
(S32.g'left = 0) and
(S34.a'left = 0) and
(S34.b'left = 0) and
(S34.c'left = 0) and
(S34.d'left = 0) and
(S34.e'left = 0) and
(S34.f'left = 0) and
(S34.g'left = 0) and
(S36'left = 0) and
(S37'left = 0) and
(S38'left = 0) and
(S39'left = 0) and
-- (S40'left = 1) and
(S42'left = 0) and
(S43'left = 0) and
(S44'left = 0) and
(S45'left = 0) and
(S46'left = 0) and
(S47'left = 0) and
(S48'left = 0) and
(S49'left = 0) and
(S50'left = 0) and
(S51.a'left = 0) and
(S51.b'left = 0) and
(S51.c'left = 0) and
(S1'right = 15) and
(S2'right = 15) and
(S3'right = 15) and
(S4'right = 15) and
(S5'right = 15) and
(S6'right = 15) and
(S7'right = 15) and
(S8'right = 0) and
(S9'right = 0) and
(S10'right = 0)and
(S11'right = 0) and
(S12'right = 0) and
(S13'right = 0) and
(S14'right = 0) and
(S15'right = 15) and
(S16'right = 15) and
(S17'right = 15) and
(S18'right = 15) and
(S19'right = 15) and
(S20'right = 15) and
(S21'right = 15) and
(S22.j'right = 7) and
(S22.k'right = 3) and
(S23.a'right = 0) and
(S23.b'right = 0) and
(S23.c'right = 0) and
(S23.d'right = 0) and
(S23.e'right = 0) and
(S23.f'right = 0) and
(S23.g'right = 0) and
(S24.a'right = 15) and
(S24.b'right = 15) and
(S24.c'right = 15) and
(S24.d'right = 15) and
(S24.e'right = 15) and
(S24.f'right = 15) and
(S24.g'right = 15) and
(S25'right = 15) and
(S26'right = 15) and
(S27'right = 15) and
(S28'right = 15) and
(S29'right = 15) and
(S30'right = 15) and
(S31'right = 15) and
(S32.a'right = 15) and
(S32.b'right = 15) and
(S32.c'right = 15) and
(S32.d'right = 15) and
(S32.e'right = 15) and
(S32.f'right = 15) and
(S32.g'right = 15) and
(S34.a'right = 15) and
(S34.b'right = 15) and
(S34.c'right = 15) and
(S34.d'right = 15) and
(S34.e'right = 15) and
(S34.f'right = 15) and
(S34.g'right = 15) and
(S36'right = 7) and
(S37'right = 15) and
(S38'right = 3) and
(S39'right = 3) and
-- (S40'right = 1) and
(S41'right = 7) and
(S42'right = 7) and
(S43'right = 7) and
(S44'right = 7) and
(S45'right = 7) and
(S46'right = 7) and
(S47'right = 7) and
(S48'right = 7) and
(S49'right = 7) and
(S50'right = 7) and
(S51.a'right = 7) and
(S51.b'right = 7) and
(S51.c'right = 7) and
(S1'length = 16) and
(S2'length = 16) and
(S3'length = 16) and
(S4'length = 16) and
(S5'length = 16) and
(S6'length = 16) and
(S7'length = 16) and
(S8'length = 16) and
(S9'length = 16) and
(S10'length = 16) and
(S11'length = 16) and
(S12'length = 16) and
(S13'length = 16) and
(S14'length = 16) and
(S15'length = 16) and
(S16'length = 16) and
(S17'length = 16) and
(S18'length = 16) and
(S19'length = 16) and
(S20'length = 16) and
(S21'length = 16) and
(S22.j'length = 7)and
(S22.k'length = 4) and
(S23.a'length = 16) and
(S23.b'length = 16) and
(S23.c'length = 16) and
(S23.d'length = 16) and
(S23.e'length = 16) and
(S23.f'length = 16) and
(S23.g'length = 16) and
(S24.a'length = 16) and
(S24.b'length = 16) and
(S24.c'length = 16) and
(S24.d'length = 16) and
(S24.e'length = 16) and
(S24.f'length = 16) and
(S24.g'length = 16) and
(S25'length = 16) and
(S26'length = 16) and
(S27'length = 16) and
(S28'length = 16) and
(S29'length = 16) and
(S30'length = 16) and
(S31'length = 16) and
(S32.a'length = 16) and
(S32.b'length = 16) and
(S32.c'length = 16) and
(S32.d'length = 16) and
(S32.e'length = 16) and
(S32.f'length = 16) and
(S32.g'length = 16) and
(S34.a'length = 16) and
(S34.b'length = 16) and
(S34.c'length = 16) and
(S34.d'length = 16) and
(S34.e'length = 16) and
(S34.f'length = 16) and
(S34.g'length = 16) and
(S36'length = 8) and
(S37'length = 16) and
(S38'length = 4) and
(S39'length = 4) and
-- (S40'length = 1) and
(S41'length = 8) and
(S42'length = 8) and
(S43'length = 8) and
(S44'length = 8) and
(S45'length = 8) and
(S46'length = 8) and
(S48'length = 8) and
(S48'length = 8) and
(S49'length = 8) and
(S50'length = 8) and
(S51.a'length = 8) and
(S51.b'length = 8) and
(S51.c'length = 8) )
report "***PASSED TEST: c01s01b01x01p05n02i00755"
severity NOTE;
assert ((S1'left = 0) and
(S2'left = 0) and
(S3'left = 0) and
(S4'left = 0) and
(S5'left = 0) and
(S6'left = 0) and
(S7'left = 0) and
(S8'left = 15) and
(S9'left = 15) and
(S10'left = 15) and
(S11'left = 15) and
(S12'left = 15) and
(S13'left = 15) and
(S14'left = 15) and
(S15'left = 0) and
(S16'left = 0) and
(S17'left = 0) and
(S18'left = 0) and
(S19'left = 0) and
(S20'left = 0) and
(S21'left = 0) and
(S22.j'left = 1) and
(S22.k'left = 0) and
(S23.a'left = 15) and
(S23.b'left = 15) and
(S23.c'left = 15) and
(S23.d'left = 15) and
(S23.e'left = 15) and
(S23.f'left = 15) and
(S23.g'left = 15) and
(S24.a'left = 0) and
(S24.b'left = 0) and
(S24.c'left = 0) and
(S24.d'left = 0) and
(S24.e'left = 0) and
(S24.f'left = 0) and
(S24.g'left = 0) and
(S25'left = 0) and
(S26'left = 0) and
(S27'left = 0) and
(S28'left = 0) and
(S29'left = 0) and
(S30'left = 0) and
(S31'left = 0) and
(S32.a'left = 0) and
(S32.b'left = 0) and
(S32.c'left = 0) and
(S32.d'left = 0) and
(S32.e'left = 0) and
(S32.f'left = 0) and
(S32.g'left = 0) and
(S34.a'left = 0) and
(S34.b'left = 0) and
(S34.c'left = 0) and
(S34.d'left = 0) and
(S34.e'left = 0) and
(S34.f'left = 0) and
(S34.g'left = 0) and
(S36'left = 0) and
(S37'left = 0) and
(S38'left = 0) and
(S39'left = 0) and
-- (S40'left = 1) and
(S42'left = 0) and
(S43'left = 0) and
(S44'left = 0) and
(S45'left = 0) and
(S46'left = 0) and
(S47'left = 0) and
(S48'left = 0) and
(S49'left = 0) and
(S50'left = 0) and
(S51.a'left = 0) and
(S51.b'left = 0) and
(S51.c'left = 0) and
(S1'right = 15) and
(S2'right = 15) and
(S3'right = 15) and
(S4'right = 15) and
(S5'right = 15) and
(S6'right = 15) and
(S7'right = 15) and
(S8'right = 0) and
(S9'right = 0) and
(S10'right = 0)and
(S11'right = 0) and
(S12'right = 0) and
(S13'right = 0) and
(S14'right = 0) and
(S15'right = 15) and
(S16'right = 15) and
(S17'right = 15) and
(S18'right = 15) and
(S19'right = 15) and
(S20'right = 15) and
(S21'right = 15) and
(S22.j'right = 7) and
(S22.k'right = 3) and
(S23.a'right = 0) and
(S23.b'right = 0) and
(S23.c'right = 0) and
(S23.d'right = 0) and
(S23.e'right = 0) and
(S23.f'right = 0) and
(S23.g'right = 0) and
(S24.a'right = 15) and
(S24.b'right = 15) and
(S24.c'right = 15) and
(S24.d'right = 15) and
(S24.e'right = 15) and
(S24.f'right = 15) and
(S24.g'right = 15) and
(S25'right = 15) and
(S26'right = 15) and
(S27'right = 15) and
(S28'right = 15) and
(S29'right = 15) and
(S30'right = 15) and
(S31'right = 15) and
(S32.a'right = 15) and
(S32.b'right = 15) and
(S32.c'right = 15) and
(S32.d'right = 15) and
(S32.e'right = 15) and
(S32.f'right = 15) and
(S32.g'right = 15) and
(S34.a'right = 15) and
(S34.b'right = 15) and
(S34.c'right = 15) and
(S34.d'right = 15) and
(S34.e'right = 15) and
(S34.f'right = 15) and
(S34.g'right = 15) and
(S36'right = 7) and
(S37'right = 15) and
(S38'right = 3) and
(S39'right = 3) and
-- (S40'right = 1) and
(S41'right = 7) and
(S42'right = 7) and
(S43'right = 7) and
(S44'right = 7) and
(S45'right = 7) and
(S46'right = 7) and
(S47'right = 7) and
(S48'right = 7) and
(S49'right = 7) and
(S50'right = 7) and
(S51.a'right = 7) and
(S51.b'right = 7) and
(S51.c'right = 7) and
(S1'length = 16) and
(S2'length = 16) and
(S3'length = 16) and
(S4'length = 16) and
(S5'length = 16) and
(S6'length = 16) and
(S7'length = 16) and
(S8'length = 16) and
(S9'length = 16) and
(S10'length = 16) and
(S11'length = 16) and
(S12'length = 16) and
(S13'length = 16) and
(S14'length = 16) and
(S15'length = 16) and
(S16'length = 16) and
(S17'length = 16) and
(S18'length = 16) and
(S19'length = 16) and
(S20'length = 16) and
(S21'length = 16) and
(S22.j'length = 7)and
(S22.k'length = 4) and
(S23.a'length = 16) and
(S23.b'length = 16) and
(S23.c'length = 16) and
(S23.d'length = 16) and
(S23.e'length = 16) and
(S23.f'length = 16) and
(S23.g'length = 16) and
(S24.a'length = 16) and
(S24.b'length = 16) and
(S24.c'length = 16) and
(S24.d'length = 16) and
(S24.e'length = 16) and
(S24.f'length = 16) and
(S24.g'length = 16) and
(S25'length = 16) and
(S26'length = 16) and
(S27'length = 16) and
(S28'length = 16) and
(S29'length = 16) and
(S30'length = 16) and
(S31'length = 16) and
(S32.a'length = 16) and
(S32.b'length = 16) and
(S32.c'length = 16) and
(S32.d'length = 16) and
(S32.e'length = 16) and
(S32.f'length = 16) and
(S32.g'length = 16) and
(S34.a'length = 16) and
(S34.b'length = 16) and
(S34.c'length = 16) and
(S34.d'length = 16) and
(S34.e'length = 16) and
(S34.f'length = 16) and
(S34.g'length = 16) and
(S36'length = 8) and
(S37'length = 16) and
(S38'length = 4) and
(S39'length = 4) and
-- (S40'length = 1) and
(S41'length = 8) and
(S42'length = 8) and
(S43'length = 8) and
(S44'length = 8) and
(S45'length = 8) and
(S46'length = 8) and
(S48'length = 8) and
(S48'length = 8) and
(S49'length = 8) and
(S50'length = 8) and
(S51.a'length = 8) and
(S51.b'length = 8) and
(S51.c'length = 8) )
report "***FAILED TEST: c01s01b01x01p05n02i00755 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00755arch;
| gpl-2.0 |
thx0701/hackrf-UART-1602LCD | firmware/cpld/sgpio_if/top.vhd | 12 | 5535 | --
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_DECIM_SEL : in std_logic_vector(2 downto 0);
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal decimate_count : std_logic_vector(2 downto 0) := "111";
signal decimate_sel_i : std_logic_vector(2 downto 0);
signal decimate_en : std_logic;
signal q_invert : std_logic;
signal rx_q_invert_mask : std_logic_vector(7 downto 0);
signal tx_q_invert_mask : std_logic_vector(7 downto 0);
begin
------------------------------------------------
-- Codec interface
adc_data_i <= DA(7 downto 0);
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
codec_clk_i <= CODEC_CLK;
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
data_from_host_i <= HOST_DATA;
HOST_CAPTURE <= host_data_capture_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
decimate_sel_i <= HOST_DECIM_SEL;
------------------------------------------------
decimate_en <= '1' when decimate_count = "111" else '0';
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
if decimate_count = "111" or host_data_enable_i = '0' then
decimate_count <= decimate_sel_i;
else
decimate_count <= decimate_count + 1;
end if;
end if;
end if;
end process;
q_invert <= HOST_Q_INVERT;
rx_q_invert_mask <= X"80" when q_invert = '1' else X"7f";
tx_q_invert_mask <= X"7F" when q_invert = '1' else X"80";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor rx_q_invert_mask;
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
dac_data_o <= (data_from_host_i xor tx_q_invert_mask) & tx_q_invert_mask(0) & tx_q_invert_mask(0);
else
dac_data_o <= (data_from_host_i xor X"80") & "00";
end if;
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
host_data_capture_o <= host_data_enable_i;
end if;
else
if codec_clk_i = '0' then
host_data_capture_o <= host_data_enable_i and decimate_en;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1399.vhd | 4 | 1763 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1399.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p06n01i01399ent IS
END c08s05b00x00p06n01i01399ent;
ARCHITECTURE c08s05b00x00p06n01i01399arch OF c08s05b00x00p06n01i01399ent IS
BEGIN
TESTING: PROCESS
subtype ST is INTEGER range 1 to 10;
variable ILL : INTEGER := 11;
variable V : ST;
BEGIN
V := ILL; -- should catch error here
assert FALSE
report "***FAILED TEST: c08s05b00x00p06n01i01399 - Variable assignment scalar subtype (integer type) check test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p06n01i01399arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket77/bug3.vhdl | 3 | 206 | entity ent3 is
end entity;
architecture a of ent3 is
begin
main : process
begin
-- wait for 0 ns; -- Comment and it exits with code 1
std.env.stop(7);
wait;
end process;
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2244.vhd | 4 | 1693 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2244.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02244ent IS
END c07s02b06x00p01n01i02244ent;
ARCHITECTURE c07s02b06x00p01n01i02244arch OF c07s02b06x00p01n01i02244ent IS
BEGIN
TESTING: PROCESS
variable BITSTRV : BIT_VECTOR( 0 to 31 );
variable k : integer;
BEGIN
k := BITSTRV rem X"7777";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02244 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02244arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd | 4 | 2447 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_16 is
end entity inline_16;
----------------------------------------------------------------
architecture test of inline_16 is
-- code from book:
type time_stamp is record
seconds : integer range 0 to 59;
minutes : integer range 0 to 59;
hours : integer range 0 to 23;
end record time_stamp;
-- end of code from book
begin
process_4_a : process is
-- code from book:
variable sample_time, current_time : time_stamp;
--
constant midday : time_stamp := (0, 0, 12);
-- end of code from book
constant clock : integer := 79;
variable sample_hour : integer;
begin
current_time := (30, 15, 2);
-- code from book:
sample_time := current_time;
sample_hour := sample_time.hours;
current_time.seconds := clock mod 60;
-- end of code from book
wait;
end process process_4_a;
process_4_b : process is
type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, nop);
type reg_number is range 0 to 31;
type instruction is record
opcode : opcodes;
source_reg1, source_reg2, dest_reg : reg_number;
displacement : integer;
end record instruction;
-- code from book:
constant midday : time_stamp := (hours => 12, minutes => 0, seconds => 0);
--
constant nop_instr : instruction :=
( opcode => addu,
source_reg1 | source_reg2 | dest_reg => 0,
displacement => 0 );
variable latest_event : time_stamp := (others => 0); -- initially midnight
-- end of code from book
begin
wait;
end process process_4_b;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2039.vhd | 4 | 1661 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2039.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02039ent IS
END c07s02b04x00p01n01i02039ent;
ARCHITECTURE c07s02b04x00p01n01i02039arch OF c07s02b04x00p01n01i02039ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
BEGIN
BOOLV := BOOLV - FALSE;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02039 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02039arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rf.vhd | 4 | 1589 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_rf.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use work.dlx_types.all,
work.reg_file_types.all;
entity reg_file is
generic ( Tac : delay_length );
port ( a1 : in reg_file_addr;
q1 : out dlx_word;
a2 : in reg_file_addr;
q2 : out dlx_word;
a3 : in reg_file_addr;
d3 : in dlx_word;
write_en : in std_logic );
end entity reg_file;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc932.vhd | 4 | 2512 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc932.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s04b00x00p03n03i00932pkg is
subtype register16 is bit_vector(15 downto 0);
function "+" (l,r : bit_vector) return bit_vector;
function "-" (l,r : bit_vector) return bit_vector;
end c10s04b00x00p03n03i00932pkg;
package body c10s04b00x00p03n03i00932pkg is
function "+" (l,r : bit_vector) return bit_vector is
begin
return (B"1111010100101010");
end;
function "-" (l,r : bit_vector) return bit_vector is
begin
return (B"1111010100101010");
end;
end c10s04b00x00p03n03i00932pkg;
use work.c10s04b00x00p03n03i00932pkg.all;
ENTITY c10s04b00x00p03n03i00932ent IS
END c10s04b00x00p03n03i00932ent;
ARCHITECTURE c10s04b00x00p03n03i00932arch OF c10s04b00x00p03n03i00932ent IS
signal i_sig : register16 := B"1010_1110_1010_0011";
BEGIN
TESTING: PROCESS
BEGIN
i_sig <= i_sig - i_sig + B"1111111100000000" after 10 ns;
wait for 20 ns;
assert NOT( i_sig = (B"1111010100101010") )
report "***PASSED TEST: c10s04b00x00p03n03i00932"
severity NOTE;
assert ( i_sig = (B"1111010100101010") )
report "***FAILED TEST: c10s04b00x00p03n03i00932 - All of the declarations of a package are visible within the declarative region if the suffix of a selected name in a use clause is the word 'all'."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s04b00x00p03n03i00932arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2335.vhd | 4 | 1683 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2335.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02335ent IS
END c07s02b07x00p02n02i02335ent;
ARCHITECTURE c07s02b07x00p02n02i02335arch OF c07s02b07x00p02n02i02335ent IS
BEGIN
TESTING: PROCESS
variable CHARV : CHARACTER := '0';
variable INTV : CHARACTER := '0';
BEGIN
INTV := CHARV ** 2;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02335 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02335arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1376.vhd | 4 | 1896 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1376.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01376ent IS
END c08s05b00x00p03n01i01376ent;
ARCHITECTURE c08s05b00x00p03n01i01376arch OF c08s05b00x00p03n01i01376ent IS
BEGIN
TESTING: PROCESS
type type1 is range 1 to 10;
type type2 is range 1 to 10;
variable v1 : type1 := 1;
variable v2 : type2 := 1;
BEGIN
--
-- The following variable assignment is illegal and
-- should generate a type mis-match error.
--
v1 := v2; -- mismatched types
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01376 - Named variable and right-hand side expression type mismatched."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01376arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc683.vhd | 4 | 3191 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc683.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:01 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:33 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:40 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00683ent IS
END c03s04b01x00p23n01i00683ent;
ARCHITECTURE c03s04b01x00p23n01i00683arch OF c03s04b01x00p23n01i00683ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type POSITIVE_R is range 0.0 to REAL'HIGH;
type FT is file of POSITIVE_R;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.54";
-- Declare a variable into which we will read.
constant CON : POSITIVE_R := 1.0;
variable VAR : POSITIVE_R;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00683"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00683 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00683arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc672.vhd | 4 | 3202 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc672.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:58 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:29 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:38 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00672ent IS
END c03s04b01x00p23n01i00672ent;
ARCHITECTURE c03s04b01x00p23n01i00672arch OF c03s04b01x00p23n01i00672ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type SWITCH_LEVEL is ('0', '1', 'X');
type FT is file of SWITCH_LEVEL;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.48";
-- Declare a variable into which we will read.
constant CON : SWITCH_LEVEL := '1';
variable VAR : SWITCH_LEVEL ;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00672"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00672 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00672arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1327.vhd | 4 | 6674 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1327.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p03n02i01327ent IS
END c08s04b01x00p03n02i01327ent;
ARCHITECTURE c08s04b01x00p03n02i01327arch OF c08s04b01x00p03n02i01327ent IS
-- enumerated types.
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
-- floating point types.
type POSITIVE_R is range 0.0 to REAL'HIGH;
-- array types.
type MEMORY is array(INTEGER range <>) of BIT;
type WORD is array(0 to 31) of BIT;
type BYTE is array(7 downto 0) of BIT;
-- record types.
type DATE is
record
DAY : INTEGER range 1 to 31;
MONTH : INTEGER range 1 to 12;
YEAR : INTEGER range -10000 to 1988;
end record;
-- Signals with no resolution function.
signal SWITCHSIG : SWITCH_LEVEL;
signal LOGICSIG : LOGIC_SWITCH;
signal CHARSIG : CHARACTER;
signal BOOLSIG : BOOLEAN;
signal SEVERSIG : SEVERITY_LEVEL;
signal INTSIG : INTEGER;
signal POSSIG : POSITIVE;
signal DISTSIG : DISTANCE;
signal TIMESIG : TIME;
signal REALSIG : REAL;
signal POSRSIG : POSITIVE_R;
signal BYTESIG : BYTE;
signal RECSIG : DATE;
-- Composite signals with resolution functions on the scalar subelements.
BEGIN
TESTING: PROCESS
-- local variables
variable ShouldBeTime : TIME := 0 ns;
variable k : integer := 0;
BEGIN
-- Test each signal assignment.
SWITCHSIG <= '1' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on SWITCHSIG;
if (ShouldBeTime /= now or switchsig /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (SWITCHSIG = '1');
LOGICSIG <= '1' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on LOGICSIG;
if (ShouldBeTime /= now or logicsig /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (LOGICSIG = '1');
CHARSIG <= '1' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on CHARSIG;
if (ShouldBeTime /= now or charsig /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (CHARSIG = '1');
BOOLSIG <= TRUE after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on BOOLSIG;
if (ShouldBeTime /= now or boolsig /= true) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (BOOLSIG = TRUE);
SEVERSIG <= ERROR after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on SEVERSIG;
if (ShouldBeTime /= now or seversig /= error) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (SEVERSIG = ERROR);
INTSIG <= 47 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on INTSIG;
if (ShouldBeTime /= now or intsig /= 47) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (INTSIG = 47);
POSSIG <= 47 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on POSSIG;
if (ShouldBeTime /= now or possig /= 47) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (POSSIG = 47);
DISTSIG <= 1 A after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on DISTSIG;
if (ShouldBeTime /= now or distsig /= 1 A) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (DISTSIG = 1 A);
TIMESIG <= 10 ns after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on TIMESIG;
if (ShouldBeTime /= now or timesig /= 10 ns) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (TIMESIG = 10 ns);
REALSIG <= 47.0 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on REALSIG;
if (ShouldBeTime /= now or realsig /= 47.0) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (REALSIG = 47.0);
POSRSIG <= 47.0 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on POSRSIG;
if (ShouldBeTime /= now or posrsig /= 47.0) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (POSRSIG = 47.0);
BYTESIG <= B"10101010" after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on BYTESIG;
if (ShouldBeTime /= now or bytesig /= B"10101010") then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (BYTESIG = B"10101010");
RECSIG <= ( DAY => 14, MONTH => 2, YEAR => 1988 ) after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on RECSIG;
if (ShouldBeTime /= now or recsig.day /= 14 or recsig.month /= 2 or recsig.year /= 1988) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (RECSIG.DAY = 14);
assert (RECSIG.MONTH = 2);
assert (RECSIG.YEAR = 1988);
assert NOT( k=0 )
report "***PASSED TEST: c08s04b01x00p03n02i01327"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s04b01x00p03n02i01327 - Evaluation of waveform elements is used to specify that driver is to assign a particular value to a target at the specified time."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p03n02i01327arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2427.vhd | 4 | 1842 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2427.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n03i02427ent IS
END c07s03b02x01p01n03i02427ent;
ARCHITECTURE c07s03b02x01p01n03i02427arch OF c07s03b02x01p01n03i02427ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_1 : integer;
ele_2 : real;
ele_3 : boolean;
end record;
constant p :rec := (ele_1 | ele_2 | ele_3 => 4.5); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x01p01n03i02427 - Element association with others choice should be used to represent elements of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n03i02427arch;
| gpl-2.0 |
peteut/ghdl | libraries/vital2000/timing_p.vhdl | 7 | 65467 | -------------------------------------------------------------------------------
-- Title : Standard VITAL TIMING Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, attributes, constants,
-- : functions and procedures for use in developing ASIC models.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0
-- #204 - Output mapping prior to glitch detection
-- v98.0 |TAG | 03/27/98 | Initial ballot draft 1998
-- | #IR225 - Negative Premptive Glitch
-- **Pkg_effected=VitalPathDelay,
-- VitalPathDelay01,VitalPathDelay01z.
-- #IR105 - Skew timing check needed
-- **Pkg_effected=NONE, New code added!!
-- #IR248 - Allows VPD to use a default timing
-- delay
-- **Pkg_effected=VitalPathDelay,
-- VitalPathDelay01,VitalPathDelay01z,
-- #IR250 - Corrects fastpath condition in VPD
-- **Pkg_effected=VitalPathDelay01,
-- VitalPathDelay01z,
-- #IR252 - Corrects cancelled timing check call if
-- condition expires.
-- **Pkg_effected=VitalSetupHoldCheck,
-- VitalRecoveryRemovalCheck.
-- #IR105 - Skew timing check
-- **Pkg_effected=NONE, New code added
-- v98.1 | jdc | 03/25/99 | Changed UseDefaultDelay to IgnoreDefaultDelay
-- and set default to FALSE in VitalPathDelay()
-- v00.7 | dbb | 07/18/00 | Removed "maximum" from VitalPeriodPulse()
-- comments
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE VITAL_Timing IS
TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0X, trx1, tr1x, trx0, trxz, trzx);
SUBTYPE VitalDelayType IS TIME;
TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10)
OF TIME;
TYPE VitalDelayType01Z IS ARRAY (VitalTransitionType RANGE tr01 to trz0)
OF TIME;
TYPE VitalDelayType01ZX IS ARRAY (VitalTransitionType RANGE tr01 to trzx)
OF TIME;
TYPE VitalDelayArrayType IS ARRAY (NATURAL RANGE <>) OF VitalDelayType;
TYPE VitalDelayArrayType01 IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01;
TYPE VitalDelayArrayType01Z IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01Z;
TYPE VitalDelayArrayType01ZX IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01ZX;
-- ----------------------------------------------------------------------
-- **********************************************************************
-- ----------------------------------------------------------------------
CONSTANT VitalZeroDelay : VitalDelayType := 0 ns;
CONSTANT VitalZeroDelay01 : VitalDelayType01 := ( 0 ns, 0 ns );
CONSTANT VitalZeroDelay01Z : VitalDelayType01Z := ( OTHERS => 0 ns );
CONSTANT VitalZeroDelay01ZX : VitalDelayType01ZX := ( OTHERS => 0 ns );
---------------------------------------------------------------------------
-- examples of usage:
---------------------------------------------------------------------------
-- tpd_CLK_Q : VitalDelayType := 5 ns;
-- tpd_CLK_Q : VitalDelayType01 := (tr01 => 2 ns, tr10 => 3 ns);
-- tpd_CLK_Q : VitalDelayType01Z := ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns );
-- tpd_CLK_Q : VitalDelayArrayType(0 to 1)
-- := (0 => 5 ns, 1 => 6 ns);
-- tpd_CLK_Q : VitalDelayArrayType01(0 to 1)
-- := (0 => (tr01 => 2 ns, tr10 => 3 ns),
-- 1 => (tr01 => 2 ns, tr10 => 3 ns));
-- tpd_CLK_Q : VitalDelayArrayType01Z(0 to 1)
-- := (0 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ),
-- 1 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ));
---------------------------------------------------------------------------
-- TRUE if the model is LEVEL0 | LEVEL1 compliant
ATTRIBUTE VITAL_Level0 : BOOLEAN;
ATTRIBUTE VITAL_Level1 : BOOLEAN;
SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0);
SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0);
SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0);
-- Types for strength mapping of outputs
TYPE VitalOutputMapType IS ARRAY ( std_ulogic ) OF std_ulogic;
TYPE VitalResultMapType IS ARRAY ( UX01 ) OF std_ulogic;
TYPE VitalResultZMapType IS ARRAY ( UX01Z ) OF std_ulogic;
CONSTANT VitalDefaultOutputMap : VitalOutputMapType
:= "UX01ZWLH-";
CONSTANT VitalDefaultResultMap : VitalResultMapType
:= ( 'U', 'X', '0', '1' );
CONSTANT VitalDefaultResultZMap : VitalResultZMapType
:= ( 'U', 'X', '0', '1', 'Z' );
-- Types for fields of VitalTimingDataType
TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME;
TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT;
TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN;
TYPE VitalBoolArrayPT IS ACCESS VitalBoolArrayT;
TYPE VitalLogicArrayPT IS ACCESS std_logic_vector;
TYPE VitalTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
FUNCTION VitalTimingDataInit RETURN VitalTimingDataType;
-- type for internal data of VitalPeriodPulseCheck
TYPE VitalPeriodDataType IS RECORD
Last : X01;
Rise : TIME;
Fall : TIME;
NotFirstFlag : BOOLEAN;
END RECORD;
CONSTANT VitalPeriodDataInit : VitalPeriodDataType
:= ('X', 0 ns, 0 ns, FALSE );
-- Type for specifying the kind of Glitch handling to use
TYPE VitalGlitchKindType IS (OnEvent,
OnDetect,
VitalInertial,
VitalTransport);
TYPE VitalGlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
LastValue : std_ulogic;
END RECORD;
TYPE VitalGlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF VitalGlitchDataType;
-- PathTypes: for handling simple PathDelay info
TYPE VitalPathType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01Type IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01ZType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01Z;-- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
-- For representing multiple paths to an output
TYPE VitalPathArrayType IS ARRAY (NATURAL RANGE <> ) OF VitalPathType;
TYPE VitalPathArray01Type IS ARRAY (NATURAL RANGE <> ) OF VitalPath01Type;
TYPE VitalPathArray01ZType IS ARRAY (NATURAL RANGE <> ) OF VitalPath01ZType;
TYPE VitalTableSymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S' -- steady value
);
SUBTYPE VitalEdgeSymbolType IS VitalTableSymbolType RANGE '/' TO '*';
-- Addition of Vital Skew Type Information
-- March 14, 1998
---------------------------------------------------------------------------
-- Procedures and Type Definitions for Defining Skews
---------------------------------------------------------------------------
TYPE VitalSkewExpectedType IS (none, s1r, s1f, s2r, s2f);
TYPE VitalSkewDataType IS RECORD
ExpectedType : VitalSkewExpectedType;
Signal1Old1 : TIME;
Signal2Old1 : TIME;
Signal1Old2 : TIME;
Signal2Old2 : TIME;
END RECORD;
CONSTANT VitalSkewDataInit : VitalSkewDataType := ( none, 0 ns, 0 ns, 0 ns, 0 ns );
-- ------------------------------------------------------------------------
--
-- Function Name: VitalExtendToFillDelay
--
-- Description: A six element array of delay values of type
-- VitalDelayType01Z is returned when a 1, 2 or 6
-- element array is given. This function will convert
-- VitalDelayType and VitalDelayType01 delay values into
-- a VitalDelayType01Z type following these rules:
--
-- When a VitalDelayType is passed, all six transition
-- values are assigned the input value. When a
-- VitalDelayType01 is passed, the 01 transitions are
-- assigned to the 01, 0Z and Z1 transitions and the 10
-- transitions are assigned to 10, 1Z and Z0 transition
-- values. When a VitalDelayType01Z is passed, the values
-- are kept as is.
--
-- The function is overloaded based on input type.
--
-- There is no function to fill a 12 value delay
-- type.
--
-- Arguments:
--
-- IN Type Description
-- Delay A one, two or six delay value Vital-
-- DelayType is passed and a six delay,
-- VitalDelayType01Z, item is returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- VitalDelayType01Z
--
-- -------------------------------------------------------------------------
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalDelayType01Z;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalCalcDelay
--
-- Description: This function accepts a 1, 2 or 6 value delay and
-- chooses the correct delay time to delay the NewVal
-- signal. This function is overloaded based on the
-- delay type passed. The function returns a single value
-- of time.
--
-- This function is provided for Level 0 models in order
-- to calculate the delay which should be applied
-- for the passed signal. The delay selection is performed
-- using the OldVal and the NewVal to determine the
-- transition to select. The default value of OldVal is X.
--
-- This function cannot be used in a Level 1 model since
-- the VitalPathDelay routines perform the delay path
-- selection and output driving function.
--
-- Arguments:
--
-- IN Type Description
-- NewVal New value of the signal to be
-- assigned
-- OldVal Previous value of the signal.
-- Default value is 'X'
-- Delay The delay structure from which to
-- select the appropriate delay. The
-- function overload is based on the
-- type of delay passed. In the case of
-- the single delay, VitalDelayType, no
-- selection is performed, since there
-- is only one value to choose from.
-- For the other cases, the transition
-- from the old value to the new value
-- decide the value returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- Time The time value selected from the
-- Delay INPUT is returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN TIME;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPathDelay
--
-- Description: VitalPathDelay is the Level 1 routine used to select
-- the propagation delay path and schedule a new output
-- value.
--
-- For single and dual delay values, VitalDelayType and
-- VitalDelayType01 are used. The output value is
-- scheduled with a calculated delay without strength
-- modification.
--
-- For the six delay value, VitalDelayType01Z, the output
-- value is scheduled with a calculated delay. The drive
-- strength can be modified to handle weak signal strengths
-- to model tri-state devices, pull-ups and pull-downs as
-- an example.
--
-- The correspondence between the delay type and the
-- path delay function is as follows:
--
-- Delay Type Path Type
--
-- VitalDelayType VitalPathDelay
-- VitalDelayType01 VitalPathDelay01
-- VitalDelayType01Z VitalPathDelay01Z
--
-- For each of these routines, the following capabilities
-- is provided:
--
-- o Transition dependent path delay selection
-- o User controlled glitch detection with the ability
-- to generate "X" on output and report the violation
-- o Control of the severity level for message generation
-- o Scheduling of the computed values on the specified
-- signal.
--
-- Selection of the appropriate path delay begins with the
-- candidate paths. The candidate paths are selected by
-- identifying the paths for which the PathCondition is
-- true. If there is a single candidate path, then that
-- delay is selected. If there is more than one candidate
-- path, then the shortest delay is selected using
-- transition dependent delay selection. If there is no
-- candidate paths, then the delay specified by the
-- DefaultDelay parameter to the path delay is used.
--
-- Once the delay is known, the output signal is then
-- scheduled with that delay. In the case of
-- VitalPathDelay01Z, an additional result mapping of
-- the output value is performed before scheduling. The
-- result mapping is performed after transition dependent
-- delay selection but before scheduling the final output.
--
-- In order to perform glitch detection, the user is
-- obligated to provide a variable of VitalGlitchDataType
-- for the propagation delay functions to use. The user
-- cannot modify or use this information.
--
-- Arguments:
--
-- IN Type Description
-- OutSignalName string The name of the output signal
-- OutTemp std_logic The new output value to be driven
-- Paths VitalPathArrayType A list of paths of VitalPathArray
-- VitalPathArrayType01 type. The VitalPathDelay routine
-- VitalPathArrayType01Z is overloaded based on the type
-- of constant passed in. With
-- VitalPathArrayType01Z, the
-- resulting output strengths can be
-- mapped.
-- DefaultDelay VitalDelayType The default delay can be changed
-- VitalDelayType01 from zero-delay to another set
-- VitalDelayType01Z of values.
--
-- IgnoreDefaultDelay BOOLEAN If TRUE, the default delay will
-- be used when no paths are
-- selected. If false, no event
-- will be scheduled if no paths are
-- selected.
--
-- Mode VitalGlitchKindType The value of this constant
-- selects the type of glitch
-- detection.
-- OnEvent Glitch on transition event
-- | OnDetect Glitch immediate on detection
-- | VitalInertial No glitch, use INERTIAL
-- assignment
-- | VitalTransport No glitch, use TRANSPORT
-- assignment
-- XOn BOOLEAN Control for generation of 'X' on
-- glitch. When TRUE, 'X's are
-- scheduled for glitches, otherwise
-- no are generated.
-- MsgOn BOOLEAN Control for message generation on
-- glitch detect. When TRUE,
-- glitches are reported, otherwise
-- they are not reported.
-- MsgSeverity SEVERITY_LEVEL The level at which the message,
-- or assertion, will be reported.
-- IgnoreDefaultDelay BOOLEAN Tells the VPD whether to use the
-- default delay value in the absense
-- of a valid delay for input conditions 3/14/98 MG
--
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the output
-- can be mapped to alternate
-- strengths to model tri-state
-- devices, pull-ups and pull-downs.
--
-- INOUT
-- GlitchData VitalGlitchDataType The internal data storage
-- variable required to detect
-- glitches.
--
-- OUT
-- OutSignal std_logic The output signal to be driven
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalPathDelay (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 3/14/98
CONSTANT IgnoreDefaultDelay : IN BOOLEAN := FALSE --IR248 3/14/98
);
PROCEDURE VitalPathDelay01 (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 3/14/98
CONSTANT IgnoreDefaultDelay : IN BOOLEAN := FALSE; --IR248 3/14/98
CONSTANT RejectFastPath : IN BOOLEAN := FALSE --IR250
);
PROCEDURE VitalPathDelay01Z (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap;
CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 3/14/98
CONSTANT IgnoreDefaultDelay : IN BOOLEAN := FALSE; --IR248 3/14/98
CONSTANT RejectFastPath : IN BOOLEAN := FALSE --IR250
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalWireDelay
--
-- Description: VitalWireDelay is used to delay an input signal.
-- The delay is selected from the input parameter passed.
-- The function is useful for back annotation of actual
-- net delays.
--
-- The function is overloaded to permit passing a delay
-- value for twire for VitalDelayType, VitalDelayType01
-- and VitalDelayType01Z. twire is a generic which can
-- be back annotated and must be constructed to follow
-- the SDF to generic mapping rules.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The input signal (port) to be
-- delayed.
-- twire VitalDelayType The delay value for which the input
-- VitalDelayType01 signal should be delayed. For Vital-
-- VitalDelayType01Z DelayType, the value is single value
-- passed. For VitalDelayType01 and
-- VitalDelayType01Z, the appropriate
-- delay value is selected by VitalCalc-
-- Delay.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The internal delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01Z
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSignalDelay
--
-- Description: The VitalSignalDelay procedure is called in a signal
-- delay block in the architecture to delay the
-- appropriate test or reference signal in order to
-- accommodate negative constraint checks.
--
-- The amount of delay is of type TIME and is a constant.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The signal to be delayed.
-- dly TIME The amount of time the signal is
-- delayed.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSignalDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT dly : IN TIME
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSetupHoldCheck
--
-- Description: The VitalSetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal. A vector and scalar form are provided.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- std_logic_vector
-- TestSignalName STRING Name of test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- with RefSignal
-- SetupHigh TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a setup violation.
-- SetupLow TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a setup violation.
-- HoldHigh TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a hold violation.
-- HoldLow TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events on
-- the RefSignal which match the edge
-- spec. are used as reference edges.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0".
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
-- EnableSetupOnTest BOOLEAN If FALSE at the time that the
-- TestSignal signal changes,
-- no setup check will be performed.
-- EnableSetupOnRef BOOLEAN If FALSE at the time that the
-- RefSignal signal changes,
-- no setup check will be performed.
-- EnableHoldOnRef BOOLEAN If FALSE at the time that the
-- RefSignal signal changes,
-- no hold check will be performed.
-- EnableHoldOnTest BOOLEAN If FALSE at the time that the
-- TestSignal signal changes,
-- no hold check will be performed.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalSetupHoldCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE --IR252 3/23/98
);
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE --IR252 3/23/98
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalRecoveryRemovalCheck
--
-- Description: The VitalRecoveryRemovalCheck detects the presence of
-- a recovery or removal violation on the input test
-- signal with respect to the corresponding input reference
-- signal. It assumes non-negative values of setup and
-- hold timing constraints. The timing constraint is
-- specified through parameters representing the recovery
-- and removal times associated with a reference edge of
-- the reference signal. A flag indicates whether a test
-- signal is asserted when it is high or when it is low.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative recovery times result in
-- a delayed reference signal. Negative removal times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of TestSignal. The routine is
-- TestSignalName STRING Name of TestSignal
-- TestDelay TIME Model internal delay associated with
-- the TestSignal
-- RefSignal std_ulogic Value of RefSignal
-- RefSignalName STRING Name of RefSignal
-- RefDelay TIME Model internal delay associated with
-- the RefSignal
-- Recovery TIME A change to an unasserted value on
-- the asynchronous TestSignal must
-- precede reference edge (on RefSignal)
-- by at least this time.
-- Removal TIME An asserted condition must be present
-- on the asynchronous TestSignal for at
-- least the removal time following a
-- reference edge on RefSignal.
-- ActiveLow BOOLEAN A flag which indicates if TestSignal
-- is asserted when it is low - "0."
-- FALSE indicate that TestSignal is
-- asserted when it has a value "1."
-- CheckEnabled BOOLEAN The check in enabled when the value
-- is TRUE, otherwise the constraints
-- are not checked.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specifier. Events on
-- RefSignal will match the edge
-- specified.
-- HeaderMsg STRING A header message that will accompany
-- any assertion message.
-- XOn BOOLEAN When TRUE, the output Violation is
-- set to "X." When FALSE, it is always
-- "0."
-- MsgOn BOOLEAN When TRUE, violation messages are
-- output. When FALSE, no messages are
-- generated.
-- MsgSeverity SEVERITY_LEVEL Severity level of the asserted
-- message.
-- EnableRecOnTest BOOLEAN If FALSE at the time that the
-- TestSignal signal changes,
-- no recovery check will be performed.
-- EnableRecOnRef BOOLEAN If FALSE at the time that the
-- RefSignal signal changes,
-- no recovery check will be performed.
-- EnableRemOnRef BOOLEAN If FALSE at the time that the
-- RefSignal signal changes,
-- no removal check will be performed.
-- EnableRemOnTest BOOLEAN If FALSE at the time that the
-- TestSignal signal changes,
-- no removal check will be performed.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalRecoveryRemovalCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalRecoveryRemovalCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT Recovery : IN TIME := 0 ns;
CONSTANT Removal : IN TIME := 0 ns;
CONSTANT ActiveLow : IN BOOLEAN := TRUE;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT EnableRecOnTest : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableRecOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableRemOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableRemOnTest : IN BOOLEAN := TRUE --IR252 3/23/98
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- Period TIME Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh TIME Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow TIME Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0".
-- XOnChecks is a global that allows for
-- only timing checks to be turned on.
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgOnChecks allows for only timing
-- check messages to be turned on.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- PeriodData VitalPeriodDataType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- ------------------------------------------------------------------------
PROCEDURE VitalPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT Period : IN TIME := 0 ns;
CONSTANT PulseWidthHigh : IN TIME := 0 ns;
CONSTANT PulseWidthLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalInPhaseSkewCheck
--
-- Description: The VitalInPhaseSkewCheck procedure detects an in-phase
-- skew violation between input signals Signal1 and Signal2.
-- This is a timer based skew check in which a
-- violation is detected if Signal1 and Signal2 are in
-- different logic states longer than the specified skew
-- interval.
--
-- The timing constraints are specified through parameters
-- representing the skew values for the different states
-- of Signal1 and Signal2.
--
--
-- Signal2 XXXXXXXXXXXX___________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| |<--
-- : Signal2 should go low in this region
-- :
--
-- ____________
-- Signal1 \_________________________________________________
-- : | |
-- : |<-------- tskew -------->|
--
-- Arguments:
--
-- IN Type Description
-- Signal1 std_ulogic Value of first signal
-- Signal1Name STRING Name of first signal
-- Signal1Delay TIME Model's internal delay associated
-- with Signal1
-- Signal2 std_ulogic Value of second signal
-- Signal2Name STRING Name of second signal
-- Signal2Delay TIME Model's internal delay associated
-- with Signal2
-- SkewS1S2RiseRise TIME Absolute maximum time duration for
-- which Signal2 can remain at "0"
-- after Signal1 goes to the "1" state,
-- without causing a skew violation.
-- SkewS2S1RiseRise TIME Absolute maximum time duration for
-- which Signal1 can remain at "0"
-- after Signal2 goes to the "1" state,
-- without causing a skew violation.
-- SkewS1S2FallFall TIME Absolute maximum time duration for
-- which Signal2 can remain at "1"
-- after Signal1 goes to the "0" state,
-- without causing a skew violation.
-- SkewS2S1FallFall TIME Absolute maximum time duration for
-- which Signal1 can remain at "1"
-- after Signal2 goes to the "0" state,
-- without causing a skew violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, skew timing violation
-- messages will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- SkewData VitalSkewDataType
-- VitalInPhaseSkewCheck information
-- storage area. This is used
-- internally to detect signal edges
-- and record the time of the last edge.
--
--
-- Trigger std_ulogic This signal is used to trigger the
-- process in which the timing check
-- occurs upon expiry of the skew
-- interval.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalInPhaseSkewCheck (
VARIABLE Violation : OUT X01;
VARIABLE SkewData : INOUT VitalSkewDataType;
SIGNAL Signal1 : IN std_ulogic;
CONSTANT Signal1Name : IN STRING := "";
CONSTANT Signal1Delay : IN TIME := 0 ns;
SIGNAL Signal2 : IN std_ulogic;
CONSTANT Signal2Name : IN STRING := "";
CONSTANT Signal2Delay : IN TIME := 0 ns;
CONSTANT SkewS1S2RiseRise : IN TIME := TIME'HIGH;
CONSTANT SkewS2S1RiseRise : IN TIME := TIME'HIGH;
CONSTANT SkewS1S2FallFall : IN TIME := TIME'HIGH;
CONSTANT SkewS2S1FallFall : IN TIME := TIME'HIGH;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT HeaderMsg : IN STRING := "";
SIGNAL Trigger : INOUT std_ulogic
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalOutPhaseSkewCheck
--
-- Description: The VitalOutPhaseSkewCheck procedure detects an
-- out-of-phase skew violation between input signals Signal1
-- and Signal2. This is a timer based skew check in
-- which a violation is detected if Signal1 and Signal2 are
-- in the same logic state longer than the specified skew
-- interval.
--
-- The timing constraints are specified through parameters
-- representing the skew values for the different states
-- of Signal1 and Signal2.
--
--
-- Signal2 XXXXXXXXXXXX___________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| |<--
-- : Signal2 should go high in this region
-- :
--
-- ____________
-- Signal1 \_________________________________________________
-- : | |
-- : |<-------- tskew -------->|
--
-- Arguments:
--
-- IN Type Description
-- Signal1 std_ulogic Value of first signal
-- Signal1Name STRING Name of first signal
-- Signal1Delay TIME Model's internal delay associated
-- with Signal1
-- Signal2 std_ulogic Value of second signal
-- Signal2Name STRING Name of second signal
-- Signal2Delay TIME Model's internal delay associated
-- with Signal2
-- SkewS1S2RiseFall TIME Absolute maximum time duration for
-- which Signal2 can remain at "1"
-- after Signal1 goes to the "1" state,
-- without causing a skew violation.
-- SkewS2S1RiseFall TIME Absolute maximum time duration for
-- which Signal1 can remain at "1"
-- after Signal2 goes to the "1" state,
-- without causing a skew violation.
-- SkewS1S2FallRise TIME Absolute maximum time duration for
-- which Signal2 can remain at "0"
-- after Signal1 goes to the "0" state,
-- without causing a skew violation.
-- SkewS2S1FallRise TIME Absolute maximum time duration for
-- which Signal1 can remain at "0"
-- after Signal2 goes to the "0" state,
-- without causing a skew violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, skew timing violation
-- messages will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- SkewData VitalSkewDataType
-- VitalInPhaseSkewCheck information
-- storage area. This is used
-- internally to detect signal edges
-- and record the time of the last edge.
--
-- Trigger std_ulogic This signal is used to trigger the
-- process in which the timing check
-- occurs upon expiry of the skew
-- interval.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalOutPhaseSkewCheck (
VARIABLE Violation : OUT X01;
VARIABLE SkewData : INOUT VitalSkewDataType;
SIGNAL Signal1 : IN std_ulogic;
CONSTANT Signal1Name : IN STRING := "";
CONSTANT Signal1Delay : IN TIME := 0 ns;
SIGNAL Signal2 : IN std_ulogic;
CONSTANT Signal2Name : IN STRING := "";
CONSTANT Signal2Delay : IN TIME := 0 ns;
CONSTANT SkewS1S2RiseFall : IN TIME := TIME'HIGH;
CONSTANT SkewS2S1RiseFall : IN TIME := TIME'HIGH;
CONSTANT SkewS1S2FallRise : IN TIME := TIME'HIGH;
CONSTANT SkewS2S1FallRise : IN TIME := TIME'HIGH;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT HeaderMsg : IN STRING := "";
SIGNAL Trigger : INOUT std_ulogic
);
END VITAL_Timing;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/variable_comparator.vhd | 4 | 1513 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity variable_comparator is
port ( terminal a : electrical;
terminal ref : electrical;
signal d : out std_ulogic );
end entity variable_comparator;
----------------------------------------------------------------
architecture ideal of variable_comparator is
quantity v_ref across ref;
quantity vin across a;
begin
comparator_behavior : process is
begin
if vin > v_ref then
d <= '1' after 5 ns;
else
d <= '0' after 5 ns;
end if;
wait on vin'above(v_ref / 2.0);
end process comparator_behavior;
end architecture ideal;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1373.vhd | 4 | 6563 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1373.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01373ent IS
END c08s05b00x00p03n01i01373ent;
ARCHITECTURE c08s05b00x00p03n01i01373arch OF c08s05b00x00p03n01i01373ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr2 : st_arr2 := c_st_arr2_1 ;
--
BEGIN
v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01373"
severity NOTE;
assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01373 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01373arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1622.vhd | 4 | 1664 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1622.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01622ent IS
END c08s12b00x00p03n01i01622ent;
ARCHITECTURE c08s12b00x00p03n01i01622arch OF c08s12b00x00p03n01i01622ent IS
return true; -- illegal in architecture declaration region.
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01622 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01622arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/latch.vhd | 4 | 1207 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity latch is
generic ( width : positive );
port ( enable : in bit;
d : in bit_vector(0 to width - 1);
q : out bit_vector(0 to width - 1) );
end entity latch;
--------------------------------------------------
architecture behavioral of latch is
begin
transfer_control : block ( enable = '1' ) is
begin
q <= guarded d;
end block transfer_control;
end architecture behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2084.vhd | 4 | 1936 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2084.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02084ent IS
END c07s02b04x00p20n01i02084ent;
ARCHITECTURE c07s02b04x00p20n01i02084arch OF c07s02b04x00p20n01i02084ent IS
BEGIN
TESTING: PROCESS
VARIABLE target : string (1 to 7) ;
VARIABLE slice_1 : string (1 to 10) := "0123456789";
VARIABLE slice_2 : string (1 to 10) := "abcdefghji";
BEGIN
target := slice_1 ( 1 to 3 ) & slice_2 ( 4 to 7 );
assert NOT(target="012defg")
report "***PASSED TEST: c07s02b04x00p20n01i02084"
severity NOTE;
assert (target="012defg")
report "***FAILED TEST: c07s02b04x00p20n01i02084 - One dimensional array of STRING type concatenation into a larger ARRAY failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02084arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1897.vhd | 4 | 1965 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1897.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01897ent IS
END c07s01b00x00p08n01i01897ent;
ARCHITECTURE c07s01b00x00p08n01i01897arch OF c07s01b00x00p08n01i01897ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal ibus : cmd_bus(small_int);
signal s_int : small_int;
signal bool : boolean;
BEGIN
sig : bool <= true;
TESTING : PROCESS
BEGIN
s_int <= ibus'right(small_int(sig)) after 5 ns;
-- signal assignment labels illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01897 - Signal assignment labels are not permitted as primaries in a type conversion expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01897arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1921.vhd | 4 | 1760 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1921.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01921ent IS
END c07s02b01x00p01n01i01921ent;
ARCHITECTURE c07s02b01x00p01n01i01921arch OF c07s02b01x00p01n01i01921ent IS
BEGIN
TESTING: PROCESS
variable b1 : Boolean := TRUE;
BEGIN
b1 := b1 and b1;
assert NOT(b1 = TRUE)
report "***PASSED TEST: c07s02b01x00p01n01i01921"
severity NOTE;
assert (b1 = TRUE)
report "***FAILED TEST: c07s02b01x00p01n01i01921 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01921arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_07.vhd | 4 | 1816 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
configuration counter_down_to_gate_level of counter is
for registered
for all : digit_register
use configuration work.reg4_gate_level;
end for;
-- . . . -- bindings for other component instances
end for; -- end of architecture registered
end configuration counter_down_to_gate_level;
-- not in book
entity fg_13_07 is
end entity fg_13_07;
use work.counter_types.all;
architecture test of fg_13_07 is
signal clk, clr : bit := '0';
signal q0, q1 : digit;
begin
dut : configuration work.counter_down_to_gate_level
port map ( clk => clk, clr => clr,
q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 20 ns;
clr_gen : clr <= '1' after 95 ns,
'0' after 135 ns;
end architecture test;
-- end not in book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc525.vhd | 4 | 3348 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc525.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00525ent IS
END c03s03b00x00p03n04i00525ent;
ARCHITECTURE c03s03b00x00p03n04i00525arch OF c03s03b00x00p03n04i00525ent IS
BEGIN
TESTING : PROCESS
type bit_ptr is access bit;
variable v_bit_ptr1: bit_ptr := new bit'('1');
variable v_bit_ptr2: bit_ptr;
variable v_bit_ptr3: bit_ptr := v_bit_ptr1;
variable v_bit_ptr4: bit_ptr := new bit'('0');
variable v_bit_ptr5: bit_ptr := v_bit_ptr4;
variable OKtest : integer := 0;
BEGIN
assert v_bit_ptr1.all = '1';
if (v_bit_ptr1.all = '1') then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr2 = null;
if (v_bit_ptr2 = null) then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr3.all = '1';
if (v_bit_ptr3.all = '1') then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr4.all = '0';
if (v_bit_ptr4.all = '0') then
OKtest := OKtest + 1;
end if;
assert v_bit_ptr5.all = '0';
if (v_bit_ptr5.all = '0') then
OKtest := OKtest + 1;
end if;
v_bit_ptr2 := new bit'('0');
assert v_bit_ptr2.all = '0';
if (v_bit_ptr2.all = '0') then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr1.all & v_bit_ptr3.all) = "11";
if ((v_bit_ptr1.all & v_bit_ptr3.all) = "11") then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr3.all & v_bit_ptr5.all) = "10";
if ((v_bit_ptr3.all & v_bit_ptr5.all) = "10") then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr3.all & v_bit_ptr2.all) = "10";
if ((v_bit_ptr3.all & v_bit_ptr2.all) = "10") then
OKtest := OKtest + 1;
end if;
assert (v_bit_ptr3.all > v_bit_ptr5.all) = true;
if ((v_bit_ptr3.all > v_bit_ptr5.all) = true) then
OKtest := OKtest + 1;
end if;
deallocate(v_bit_ptr1);
deallocate(v_bit_ptr2);
deallocate(v_bit_ptr4);
assert NOT(OKtest = 10)
report "***PASSED TEST: c03s03b00x00p03n04i00525"
severity NOTE;
assert (OKtest = 10)
report "***FAILED TEST: c03s03b00x00p03n04i00525 - Bit type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00525arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc235.vhd | 4 | 1686 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc235.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00235ent IS
port ( p1 : inout integer;
p2 : inout integer);
END c03s01b02x00p04n01i00235ent;
ARCHITECTURE c03s01b02x00p04n01i00235arch OF c03s01b02x00p04n01i00235ent IS
type t3 is range p1 to p2;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00235 -The range constraints in the type definition of 't3' must be locally static."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00235arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1181.vhd | 4 | 1697 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1181.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s00b00x00p02n01i01181ent IS
END c08s00b00x00p02n01i01181ent;
ARCHITECTURE c08s00b00x00p02n01i01181arch OF c08s00b00x00p02n01i01181ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 5;
variable p : integer := 3;
BEGIN
if (k > p) generate
end generate;
end if;
assert FALSE
report "***FAILED TEST: c08s00b00x00p02n01i01181 - Concurrent statement are not permitted within sequence of statements."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s00b00x00p02n01i01181arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2173.vhd | 4 | 1706 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2173.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02173ent IS
END c07s02b05x00p01n01i02173ent;
ARCHITECTURE c07s02b05x00p01n01i02173arch OF c07s02b05x00p01n01i02173ent IS
BEGIN
TESTING: PROCESS
constant x1: integer := - 10;
BEGIN
assert NOT(x1=-10)
report "***PASSED TEST: c07s02b05x00p01n01i02173"
severity NOTE;
assert (x1=-10)
report "***FAILED TEST: c07s02b05x00p01n01i02173 - Signs - can be used with only numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02173arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_array.vhd | 4 | 2633 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity read_array_write_data is
end entity read_array_write_data;
architecture writer of read_array_write_data is
begin
process is
type integer_file is file of integer;
file data_file : integer_file open write_mode is "coeff-data";
begin
write(data_file, 0);
write(data_file, 1);
write(data_file, 2);
write(data_file, 3);
write(data_file, 4);
write(data_file, 5);
write(data_file, 6);
write(data_file, 7);
write(data_file, 8);
write(data_file, 9);
write(data_file, 10);
write(data_file, 11);
write(data_file, 12);
write(data_file, 13);
write(data_file, 14);
write(data_file, 15);
write(data_file, 16);
write(data_file, 17);
write(data_file, 18);
wait;
end process;
end architecture writer;
entity read_array is
end entity read_array;
architecture test of read_array is
begin
process is
-- code from book (in text)
type integer_vector is array (integer range <>) of integer;
-- end code from book
-- code from book (in Figure)
impure function read_array ( file_name : string; array_length : natural )
return integer_vector is
type integer_file is file of integer;
file data_file : integer_file open read_mode is file_name;
variable result : integer_vector(1 to array_length) := (others => 0);
variable index : integer := 1;
begin
while not endfile(data_file) and index <= array_length loop
read(data_file, result(index));
index := index + 1;
end loop;
return result;
end function read_array;
-- end code from book
-- code from book (in text)
constant coeffs : integer_vector := read_array("coeff-data", 16);
-- end code from book
begin
wait;
end process;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2584.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2584.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02584ent IS
END c13s03b01x00p02n01i02584ent;
ARCHITECTURE c13s03b01x00p02n01i02584arch OF c13s03b01x00p02n01i02584ent IS
BEGIN
TESTING: PROCESS
variable k^ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02584 - Identifier can not end with '^'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02584arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc39.vhd | 4 | 1748 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc39.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p02n01i00039ent IS
END c04s03b01x01p02n01i00039ent;
ARCHITECTURE c04s03b01x01p02n01i00039arch OF c04s03b01x01p02n01i00039ent IS
constant C1 : Boolean := 10 = 10; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( C1 = true )
report "***PASSED TEST: c04s03b01x01p02n01i00039"
severity NOTE;
assert ( C1 = true )
report "***FAILED TEST: c04s03b01x01p02n01i00039 - A boolean expression assigned to the constant test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p02n01i00039arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket30/lib_numeric_tb.vhd | 3 | 564 | use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_primitives.all;
use ieee.vital_timing.all;
entity numeric_tb is
generic (
tperiod_CLK_posedge : VitalDelayType := 0.000 ns);
port (
CLK : in std_ulogic);
attribute VITAL_LEVEL0 of numeric_tb : entity is true;
end numeric_tb;
architecture test of numeric_tb is
begin
process
variable l : line;
begin
write(l, string'("tperiod_CLK_posedge = "));
write(l, tperiod_CLK_posedge);
writeline(output, l);
wait;
end process;
end;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/constants/simple-string-constant.vhdl | 8 | 614 | entity test is
end test;
architecture only of test is
begin -- only
doit: process
constant string_constant : string := "init";
begin -- process
assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
assert string_constant(2) = 'n' REPORT "string_constant(2) not properly intialized" SEVERITY FAILURE;
assert string_constant(3) = 'i' REPORT "string_constant(3) not properly intialized" SEVERITY FAILURE;
assert string_constant(4) = 't' REPORT "string_constant(4) not properly intialized" SEVERITY FAILURE;
wait;
end process;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2224.vhd | 4 | 1688 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2224.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02224ent IS
END c07s02b06x00p01n01i02224ent;
ARCHITECTURE c07s02b06x00p01n01i02224arch OF c07s02b06x00p01n01i02224ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
variable k : integer;
BEGIN
k := BOOLV mod TRUE;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02224 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02224arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2973.vhd | 4 | 2290 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2973.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p03n01i02973ent IS
END c02s03b01x00p03n01i02973ent;
ARCHITECTURE c02s03b01x00p03n01i02973arch OF c02s03b01x00p03n01i02973ent IS
type newt is (one,two,three,four);
function "+" (constant c1,c2 : in integer) return newt is
begin
assert (c1=10)
report "Error in association of left binary + operator"
severity failure;
assert (c2=20)
report "Error in association of right binary + operator"
severity failure;
assert NOT( c1=10 and c2=20 )
report "***PASSED TEST: c02s03b01x00p03n01i02973"
severity NOTE;
assert ( c1=10 and c2=20 )
report "***FAILED TEST: c02s03b01x00p03n01i02973 - Error in + overloading as binary operator."
severity ERROR;
return three;
end;
BEGIN
TESTING: PROCESS
variable n1 : newt;
BEGIN
n1 := two;
assert (n1=two)
report "Error in initial conditions detected"
severity failure;
n1:= 10 + 20;
assert (n1=three)
report "Error in call to overloaded binary + operator"
severity failure;
wait;
END PROCESS TESTING;
END c02s03b01x00p03n01i02973arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/display_interface.vhd | 4 | 1427 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package display_interface is
-- . . .
-- not in book
type status_type is (t1, t2, t3);
-- end not in book
procedure create_window ( size_x, size_y : natural;
status : out status_type );
attribute foreign of create_window : procedure is
"language Ada; with window_operations;" &
"bind to window_operations.create_window;" &
"parameter size_x maps to size_x : in natural;" &
"parameter size_y maps to size_y : in natural;" &
"parameter status maps to status : out window_operations.status_type;" &
"others map to default";
-- . . .
end package display_interface;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_07.vhd | 4 | 1385 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_07.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity SR_flipflop is
port ( S, R : in bit; Q : out bit );
end entity SR_flipflop;
architecture checking of SR_flipflop is
begin
set_reset : process (S, R) is
begin
assert S = '1' nand R = '1';
if S = '1' then
Q <= '1';
end if;
if R = '1' then
Q <= '0';
end if;
end process set_reset;
end architecture checking;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/perf02/shr_141.vhd | 3 | 1108 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity shr_141 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end shr_141;
architecture augh of shr_141 is
signal tmp_padding : std_logic;
signal tmp_result : std_logic_vector(32 downto 0);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Temporary signals
tmp_padding <= padding;
tmp_result <= std_logic_vector(shift_right( unsigned(padding & input), to_integer(shift) ));
-- The output
output <= tmp_result(31 downto 0);
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1804.vhd | 4 | 1846 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1804.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p06n01i01804ent IS
END c07s01b00x00p06n01i01804ent;
ARCHITECTURE c07s01b00x00p06n01i01804arch OF c07s01b00x00p06n01i01804ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 0;
variable y : integer := 2;
variable z : integer := 5;
BEGIN
x := y * 10 * z; -- No_failure_here
assert NOT( x=100 )
report "***PASSED TEST: c07s01b00x00p06n01i01804"
severity NOTE;
assert ( x=100 )
report "***FAILED TEST: c07s01b00x00p06n01i01804 - The term must be factor or a sequence of factors combined with multiplying operators."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p06n01i01804arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc929.vhd | 4 | 1802 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc929.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s04b00x00p01n01i00929pkg is
type p2 is (a, b);
end c10s04b00x00p01n01i00929pkg;
use work.all;
ENTITY c10s04b00x00p01n01i00929ent IS
END c10s04b00x00p01n01i00929ent;
ARCHITECTURE c10s04b00x00p01n01i00929arch OF c10s04b00x00p01n01i00929ent IS
signal s: p2; -- Failure_here
-- should report an error as the type p2 is not visible.
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c10s04b00x00p01n01i00929 - Type definition does not exist in scope of declaration region for architecture."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s04b00x00p01n01i00929arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2325.vhd | 4 | 1761 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2325.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p07n01i02325ent IS
END c07s01b00x00p07n01i02325ent;
ARCHITECTURE c07s01b00x00p07n01i02325arch OF c07s01b00x00p07n01i02325ent IS
BEGIN
TESTING: PROCESS
variable k : real := 0.0;
BEGIN
k := abs (-10.3);
assert NOT( k = 10.3 )
report "***PASSED TEST: c07s01b00x00p07n01i02325"
severity NOTE;
assert ( k = 10.3 )
report "***FAILED TEST: c07s01b00x00p07n01i02325 - The result of the 'abs' operation must be the absolute value of the operand."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p07n01i02325arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2890.vhd | 4 | 1981 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2890.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x00p05n03i02890ent IS
END c02s01b01x00p05n03i02890ent;
ARCHITECTURE c02s01b01x00p05n03i02890arch OF c02s01b01x00p05n03i02890ent IS
function F1 ( A,B : integer) return integer;
function F1 ( A,B : integer ) return integer is
begin
A := 2 ; -- Failure_here
--ERROR: formal paramters not explicitly given are constant and therfore
-- this assignment is illegal.
B := B * A; -- Failure_here
--ERROR: formal paramters not explicitly given are constant and therfore
-- this assignment is illegal.
return 3;
end F1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x00p05n03i02890 - Cannot assign a value to a 'constant'."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x00p05n03i02890arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3050.vhd | 4 | 2283 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3050.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b04x00p03n01i03050ent IS
END c12s02b04x00p03n01i03050ent;
ARCHITECTURE c12s02b04x00p03n01i03050arch OF c12s02b04x00p03n01i03050ent IS
signal si:integer;
signal sr:real;
signal sb:bit;
BEGIN
-- test for no associated ports
bl1: block
port (i:integer:=4;r:real:=6.4;b:bit:='1');
begin
assert (i=4)
report "Default expression for unassociated integer port I incorrect"
severity failure;
assert (r=6.4)
report "Default expression for unassociated real port R incorrect"
severity failure;
assert (b='1')
report "Default expression for unassociated bit port B incorrect"
severity failure;
TESTING: PROCESS
BEGIN
assert NOT( i=4 and r=6.4 and b='1' )
report "***PASSED TEST: c12s02b04x00p03n01i03050"
severity NOTE;
assert ( i=4 and r=6.4 and b='1' )
report "***FAILED TEST: c12s02b04x00p03n01i03050 - Unassociated ports are not correctly evaluated for the ports of a block."
severity ERROR;
wait;
END PROCESS TESTING;
end block;
END c12s02b04x00p03n01i03050arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc309.vhd | 4 | 1893 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc309.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p06n01i00309ent IS
END c03s01b04x00p06n01i00309ent;
ARCHITECTURE c03s01b04x00p06n01i00309arch OF c03s01b04x00p06n01i00309ent IS
type R1 is range -10.0 to 10.0;
constant C1 : R1 := 2.0 ;
type R2 is range REAL'LOW to REAL'HIGH;
signal S1 : R1;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= C1 * 2.0 after 5 ns;
wait for 10 ns;
assert NOT(S1 = 4.0)
report "***PASSED TEST: c03s01b04x00p06n01i00309"
severity NOTE;
assert ( S1=4.0)
report "***FAILED TEST: c03s01b04x00p06n01i00309 - The result of an arithmetic operation results in a value belonging to the floating point type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p06n01i00309arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1211.vhd | 4 | 2059 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1211.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p25n01i01211ent IS
END c08s01b00x00p25n01i01211ent;
ARCHITECTURE c08s01b00x00p25n01i01211arch OF c08s01b00x00p25n01i01211ent IS
-- Local signals.
signal A : BIT;
BEGIN
TESTING: PROCESS
-- Local variables.
variable ShouldBeTime : TIME;
BEGIN
-- Check a condition clause that is NEVER true.
-- Should suspend until the timeout_clause is reached.
A <= '1' after 1 ns;
ShouldBeTime := NOW + 20 ns;
wait on A until (FALSE) for 20 ns;
assert NOT(ShouldBeTime = NOW)
report "***PASSED TEST: c08s01b00x00p25n01i01211"
severity NOTE;
assert (ShouldBeTime = NOW)
report "***FAILED TEST: c08s01b00x00p25n01i01211 - If the condition specified by the condition clause is FALSE, the wait statement will suspend itself again."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p25n01i01211arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc792.vhd | 4 | 2520 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc792.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b02x00p03n01i00792pkg is
constant k : integer := 5;
function wired_and (sig : bit_vector) return bit;
end c01s01b02x00p03n01i00792pkg;
package body c01s01b02x00p03n01i00792pkg is
function wired_and (sig : bit_vector) return bit is
begin
return '0';
end wired_and;
end c01s01b02x00p03n01i00792pkg;
ENTITY c01s01b02x00p03n01i00792ent_1 IS
GENERIC (CONSTANT a : bit);
ALIAS alias_identifier : bit IS a ;
END c01s01b02x00p03n01i00792ent_1 ;
ENTITY c01s01b02x00p03n01i00792ent_2 IS
GENERIC (CONSTANT a : bit);
ATTRIBUTE my_name : integer;
END c01s01b02x00p03n01i00792ent_2 ;
ENTITY c01s01b02x00p03n01i00792ent_4 IS
GENERIC (CONSTANT a : bit);
USE work.c01s01b02x00p03n01i00792pkg.ALL;
END c01s01b02x00p03n01i00792ent_4 ;
use work.c01s01b02x00p03n01i00792pkg.all;
ENTITY c01s01b02x00p03n01i00792ent_5 IS
port (signal a : in wired_and bit bus);
DISCONNECT a:bit AFTER 100 ns;
END c01s01b02x00p03n01i00792ent_5 ;
--------------------------------
ENTITY c01s01b02x00p03n01i00792ent IS
END c01s01b02x00p03n01i00792ent;
ARCHITECTURE c01s01b02x00p03n01i00792arch OF c01s01b02x00p03n01i00792ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b02x00p03n01i00792"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b02x00p03n01i00792arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug23482/test2.vhdl | 3 | 169 | entity test2 is end entity;
architecture arch of test2 is
signal b:bit;
-- alias bit_base is bit'base;
alias b_stable is b'stable;
begin
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc164.vhd | 4 | 2394 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc164.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p23n01i00164ent IS
END c04s03b02x02p23n01i00164ent;
ARCHITECTURE c04s03b02x02p23n01i00164arch OF c04s03b02x02p23n01i00164ent IS
signal p1 : bit; --added to make it compile
BEGIN
TESTING: PROCESS(p1)
VARIABLE v1,v2,v3,v4 : integer;
PROCEDURE default_test
(
param_1 : in integer;
default : in integer := 22;
param_3 : out integer;
param_4 : out integer
)
is
begin
param_3 := param_1;
param_4 := default;
end default_test;
BEGIN
v1 := 1919;
default_test (v1,
-- missing association
param_3 => v3,
param_4 => v4
);
assert NOT( v3=1919 and v4=22 )
report "***PASSED TEST: c04s03b02x02p23n01i00164"
severity NOTE;
assert ( v3=1919 and v4=22 )
report "***FAILED TEST: c04s03b02x02p23n01i00164 - If an association element is omitted from an association list in order to make use of the default expression on the corresponding interface element, all subsequent association elements in that association list must be named associations."
severity ERROR;
END PROCESS TESTING;
END c04s03b02x02p23n01i00164arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_04.vhd | 4 | 4384 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_04.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity cache is
generic ( cache_size, block_size, associativity : positive;
benchmark_name : string(1 to 10) );
port ( halt : in bit );
end entity cache;
architecture instrumented of cache is
begin
-- code from book
cache_monitor : process is
type measurement_record is
record
cache_size, block_size, associativity : positive;
benchmark_name : string(1 to 10);
miss_rate : real;
ave_access_time : delay_length;
end record;
type measurement_file is file of measurement_record;
file measurements : measurement_file
open append_mode is "cache-measurements";
-- . . .
-- not in book
constant miss_count : natural := 100;
constant total_accesses : natural := 1000;
constant total_delay : delay_length := 2400 ns;
-- end not in book
begin
-- . . .
loop
-- . . .
-- not in book
wait on halt;
-- end not in book
exit when halt = '1';
-- . . .
end loop;
write ( measurements,
measurement_record'(
-- write values of generics for this run
cache_size, block_size, associativity, benchmark_name,
-- calculate performance metrics
miss_rate => real(miss_count) / real(total_accesses),
ave_access_time => total_delay / total_accesses ) );
wait;
end process cache_monitor;
-- end code from book
end architecture instrumented;
entity fg_18_04 is
end entity fg_18_04;
architecture test of fg_18_04 is
signal halt : bit := '0';
begin
dut : entity work.cache(instrumented)
generic map ( cache_size => 128*1024, block_size => 16,
associativity => 2, benchmark_name => "dhrystone " )
port map ( halt => halt );
halt <= '1' after 10 ns;
end architecture test;
entity fg_18_04_a is
end entity fg_18_04_a;
architecture reader of fg_18_04_a is
begin
process is
type measurement_record is
record
cache_size, block_size, associativity : positive;
benchmark_name : string(1 to 10);
miss_rate : real;
ave_access_time : delay_length;
end record;
type measurement_file is file of measurement_record;
file measurements : measurement_file open read_mode is "cache-measurements";
variable measurement : measurement_record;
use std.textio.all;
variable L : line;
begin
while not endfile(measurements) loop
read(measurements, measurement);
write(L, measurement.cache_size);
write(L, ' ');
write(L, measurement.block_size);
write(L, ' ');
write(L, measurement.associativity);
write(L, ' ');
write(L, measurement.benchmark_name);
write(L, ' ');
write(L, measurement.miss_rate);
write(L, ' ');
write(L, measurement.ave_access_time);
writeline(output, L);
end loop;
wait;
end process;
end architecture reader;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc807.vhd | 4 | 1581 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc807.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b00x00p02n01i00807ent IS
END c01s02b00x00p02n01i00807ent;
ARCHITECTURE c01s02b00x00p02n01i00807arch OF c01s02b00x00p02n01i00807ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b00x00p02n01i00807 - The name after the reserved word of is not an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b00x00p02n01i00807arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket66/bug.vhdl | 3 | 366 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity;
architecture a of ent is
procedure proc(constant value : std_logic_vector) is
begin
end procedure;
begin
main : process is
constant const : unsigned(1 downto 0) := "00";
begin
proc(std_logic_vector(const));
wait;
end process;
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_25.vhd | 4 | 2096 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_25.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity nand3 is
generic ( Tpd : delay_length );
port ( a, b, c : in bit; y : out bit );
end entity nand3;
architecture basic of nand3 is
begin
y <= not (a and b and c) after Tpd;
end architecture basic;
library project_lib;
library stimulus;
use stimulus.stimulus_generators.all;
entity misc_logic is
end entity misc_logic;
-- code from book
architecture gate_level of misc_logic is
component nand3 is
generic ( Tpd : delay_length );
port ( a, b, c : in bit; y : out bit );
end component nand3;
for all : nand3
use entity project_lib.nand3(basic);
-- . . .
-- not in book
signal sig1, sig2, sig3, out_sig : bit;
signal test_vector : bit_vector(1 to 3);
-- end not in book
begin
gate1 : component nand3
generic map ( Tpd => 2 ns )
port map ( a => sig1, b => sig2, c => sig3, y => out_sig );
-- . . .
-- not in book
all_possible_values(test_vector, 10 ns);
(sig1, sig2, sig3) <= test_vector;
-- end not in book
end architecture gate_level;
-- end code from book
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug02/repro.vhdl | 3 | 462 | entity repro is
end repro;
architecture behav of repro is
function inc (a : integer) return integer is
begin
return a + 1;
end inc;
function inc (a : time) return time is
begin
return a + 1 ns;
end inc;
procedure inc (a : inout integer) is
begin
a := inc (a);
end inc;
begin -- behav
process
variable a : integer := 2;
begin
inc (a);
assert a = 3 report "bad value of a";
wait;
end process;
end behav;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1613.vhd | 4 | 1890 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1613.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p01n01i01613ent IS
END c08s12b00x00p01n01i01613ent;
ARCHITECTURE c08s12b00x00p01n01i01613arch OF c08s12b00x00p01n01i01613ent IS
--
-- Nested functions to test return statement.
--
function two return integer is
function one return integer is
begin
return 1;
end one;
begin
return one + one;
end two;
BEGIN
TESTING : PROCESS
BEGIN
assert NOT( two=2 )
report "***PASSED TEST: c08s12b00x00p01n01i01613"
severity NOTE;
assert ( two=2 )
report "***FAILED TEST: c08s12b00x00p01n01i01613 - Return statement applies to the innermost enclosing function."
severity ERROR;
wait;
END PROCESS;
END c08s12b00x00p01n01i01613arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc266.vhd | 4 | 1916 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc266.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p02n01i00266ent IS
END c03s01b03x00p02n01i00266ent;
ARCHITECTURE c03s01b03x00p02n01i00266arch OF c03s01b03x00p02n01i00266ent IS
type UPLE is
units -- Failure_here
-- ERROR - SYNTAX ERROR: PHYSICAL TYPE DEFINITION MUST HAVE RANGE CONSTRAINT
single;
double = 2 single;
triple = 3 single;
quadruple = 2 double;
pentuple = 5 single;
sextuple = 2 triple;
septuple = 7 single;
octuple = 2 quadruple;
end units;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p02n01i00266 - Physical type definition must have range constraint."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p02n01i00266arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3150.vhd | 4 | 2882 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3150.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b02x00p08n01i03150ent_a IS
END c05s02b02x00p08n01i03150ent_a;
ARCHITECTURE c05s02b02x00p08n01i03150arch_a OF c05s02b02x00p08n01i03150ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s02b02x00p08n01i03150 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03150arch_a;
ARCHITECTURE c05s02b02x00p08n01i03150arch_c OF c05s02b02x00p08n01i03150ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s02b02x00p08n01i03150 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03150arch_c;
ARCHITECTURE c05s02b02x00p08n01i03150arch_b OF c05s02b02x00p08n01i03150ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c05s02b02x00p08n01i03150"
severity NOTE;
wait;
END PROCESS TESTING;
END c05s02b02x00p08n01i03150arch_b;
--
ENTITY c05s02b02x00p08n01i03150ent IS
END c05s02b02x00p08n01i03150ent;
ARCHITECTURE c05s02b02x00p08n01i03150arch OF c05s02b02x00p08n01i03150ent IS
component c05s02b02x00p08n01i03150ent_a
end component;
BEGIN
comp1 : c05s02b02x00p08n01i03150ent_a;
END c05s02b02x00p08n01i03150arch;
configuration c05s02b02x00p08n01i03150cfg of c05s02b02x00p08n01i03150ent is
for c05s02b02x00p08n01i03150arch
for comp1 : c05s02b02x00p08n01i03150ent_a use entity work.c05s02b02x00p08n01i03150ent_a;
end for;
end for;
end c05s02b02x00p08n01i03150cfg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2918.vhd | 4 | 3311 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2918.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p06n01i02918ent IS
END c02s01b01x02p06n01i02918ent;
ARCHITECTURE c02s01b01x02p06n01i02918arch OF c02s01b01x02p06n01i02918ent IS
function bit_func ( x : bit) return bit is
begin
return x;
end bit_func ;
function bit_vector_func ( x : bit_vector) return bit_vector is
begin
return x;
end bit_vector_func ;
function boolean_func ( x : boolean) return boolean is
begin
return x;
end boolean_func ;
function character_func ( x : character) return character is
begin
return x;
end character_func ;
function integer_func ( x : integer) return integer is
begin
return x;
end integer_func ;
function real_func ( x : real) return real is
begin
return x;
end real_func ;
function string_func ( x : string) return string is
begin
return x;
end string_func ;
function time_func ( x : time) return time is
begin
return x;
end time_func ;
BEGIN
TESTING: PROCESS
variable v : bit_vector (1 to 3) ;
BEGIN
v(1) := '0';
v(2) := '1';
v(3) := '0';
assert NOT( (bit_func('1') = '1') and
(bit_vector_func(v) = v) and
(boolean_func(true) = true) and
(character_func('X') = 'X') and
(integer_func(6) = 6) and
(real_func(3.14159) = 3.14159) and
(string_func("qwertyuiop") = "qwertyuiop") and
(time_func(2 ns) = 2 ns))
report "***PASSED TEST: c02s01b01x02p06n01i02918"
severity NOTE;
assert ( (bit_func('1') = '1') and
(bit_vector_func(v) = v) and
(boolean_func(true) = true) and
(character_func('X') = 'X') and
(integer_func(6) = 6) and
(real_func(3.14159) = 3.14159) and
(string_func("qwertyuiop") = "qwertyuiop") and
(time_func(2 ns) = 2 ns))
report "***FAILED TEST: c02s01b01x02p06n01i02918 - Static signal as actual test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p06n01i02918arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_v_source.vhd | 4 | 1436 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_v_source is
end tb_v_source ;
architecture TB_v_source of tb_v_source is
terminal in_src, out_flt : electrical;
-- Component declarations
-- Signal declarations
begin
-- Signal assignments
-- Component instances
vio : entity work.v_source(source_sine)
port map(
p => in_src,
m => ELECTRICAL_REF
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => in_src,
p2 => electrical_ref
);
end TB_v_source ;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2930.vhd | 4 | 1681 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2930.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p07n03i02930ent IS
END c02s02b00x00p07n03i02930ent;
ARCHITECTURE c02s02b00x00p07n03i02930arch OF c02s02b00x00p07n03i02930ent IS
function func1 (i,l:integer) return boolean;
-- ERROR: non-existent body for function func1
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02930 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02930_arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2592.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2592.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02592ent IS
END c13s03b01x00p02n01i02592ent;
ARCHITECTURE c13s03b01x00p02n01i02592arch OF c13s03b01x00p02n01i02592ent IS
BEGIN
TESTING: PROCESS
variable k= : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02592 - Identifier can not end with '='."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02592arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2187.vhd | 4 | 3954 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2187.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02187ent IS
END c07s02b05x00p01n01i02187ent;
ARCHITECTURE c07s02b05x00p01n01i02187arch OF c07s02b05x00p01n01i02187ent IS
BEGIN
TESTING: PROCESS
-- Local declarations.
variable INTV1 : INTEGER := 0;
variable INTV2 : INTEGER := 0;
variable TIMEV1 : TIME := 1 ns;
variable TIMEV2 : TIME := 1 ns;
variable REALV1 : REAL := 0.0;
variable REALV2 : REAL := 0.0;
BEGIN
-- Test negation of simple integers.
INTV1 := 14;
assert (-INTV1 = -14)
report "Negation of simple integers does not work.";
INTV2 := INTEGER'HIGH;
assert (-INTV2 = -INTEGER'HIGH)
report "Negation of simple integers does not work.";
-- Test identity of simple integers.
assert (+14 = 14)
report "Identity of simple integers does not work.";
-- Test negation of "TIME".
TIMEV1 := 1 ns;
assert (-TIMEV1 = -1 ns)
report "Negation of TIME values does not work.";
TIMEV2 := TIME'HIGH;
assert (-TIMEV2 = -TIME'HIGH)
report "Negation of TIME values does not work.";
-- Test identify of "TIME".
assert (+14 ps = 14 ps)
report "Identity of TIME values does not work.";
-- Test negation of simple floating point numbers.
REALV1 := 14.0;
assert (-REALV1 = -14.0)
report "Negation of simple integers does not work.";
REALV2 := REAL'HIGH;
assert (-REALV2 = -REAL'HIGH)
report "Negation of simple integers does not work.";
-- Test identity of simple floating point numbers.
assert (+14.0 = 14.0)
report "Identity of simple integers does not work.";
wait for 5 fs;
assert NOT( (-INTV1 = -14) and
(-INTV2 = -INTEGER'HIGH) and
(+14 = 14) and
(-TIMEV1 = -1 ns) and
(-TIMEV2 = -TIME'HIGH) and
(+14 ps = 14 ps) and
(-REALV1 = -14.0) and
(-REALV2 = -REAL'HIGH) and
(+14.0 = 14.0) )
report "***PASSED TEST: c07s02b05x00p01n01i02187"
severity NOTE;
assert ( (-INTV1 = -14) and
(-INTV2 = -INTEGER'HIGH) and
(+14 = 14) and
(-TIMEV1 = -1 ns) and
(-TIMEV2 = -TIME'HIGH) and
(+14 ps = 14 ps) and
(-REALV1 = -14.0) and
(-REALV2 = -REAL'HIGH) and
(+14.0 = 14.0) )
report "***FAILED TEST: c07s02b05x00p01n01i02187 - Identity and nefation function did not work correctly for all numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02187arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1719.vhd | 4 | 2045 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1719.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p16n02i01719ent IS
END c09s02b00x00p16n02i01719ent;
ARCHITECTURE c09s02b00x00p16n02i01719arch OF c09s02b00x00p16n02i01719ent IS
SUBTYPE bit_4 is bit_vector ( 0 to 3);
SUBTYPE bit_8 is bit_vector ( 0 to 7);
SIGNAL s : bit_8 := B"0000_0000";
SIGNAL s4 : bit_4;
SIGNAL s5 : bit_4;
BEGIN
-- trigger only one element.
s (6) <= '1' after 10 ns;
TESTING: PROCESS(s(0 to 3))
BEGIN
assert (NOW <= 0 fs )
report "***FAILED TEST: c09s02b00x00p16n02i01719 - This process should be inactive."
severity ERROR;
END PROCESS TESTING;
p2 : PROCESS (s(3 to 6))
begin
assert NOT((s(3 to 6) = B"0001") and (NOW = 10 ns))
report "***PASSED TEST: c09s02b00x00p16n02i01719 - This test is passed only is the FAILED assertion did not appear."
severity NOTE;
end process p2;
END c09s02b00x00p16n02i01719arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_a2d_d2a.vhd | 4 | 3540 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_a2d_d2a is
end tb_a2d_d2a;
architecture TB_a2d_d2a of tb_a2d_d2a is
-- Component declarations
-- Signal declarations
terminal ana_out : electrical;
terminal analog_in : electrical;
signal clock : std_ulogic;
signal start : std_ulogic;
signal eoc : std_ulogic;
signal eoc_logic: std_logic;
signal oe : std_logic;
signal data_bus : std_ulogic_vector(0 to 9);
signal latch : std_ulogic;
signal latch_logic : std_logic;
signal nn_eoc : std_logic;
signal or_out : std_logic;
signal n_eoc : std_logic;
begin
-- Signal assignments
eoc_logic <= To_X01Z(eoc); -- convert std_ulogic to std_logic
latch <= To_X01(latch_logic); -- convert std_logic to std_ulogic
-- Component instances
ad1 : entity work.a2d_nbit(sar)
port map(
dout => data_bus,
ain => analog_in,
clk => clock,
start => start,
eoc => eoc
);
v1 : entity work.v_sine(ideal)
generic map(
freq => 2.5,
amplitude => 2.5,
offset => 2.5,
phase => 0.0
)
port map(
pos => analog_in,
neg => ELECTRICAL_REF
);
inv1 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => or_out,
output => oe
);
inv2 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => n_eoc,
output => nn_eoc
);
or1 : entity work.or2(ideal)
port map(
in1 => n_eoc,
in2 => nn_eoc,
output => or_out
);
inv3 : entity work.inverter(ideal)
generic map(
delay => 0us
)
port map(
input => eoc_logic,
output => n_eoc
);
U2 : entity work.buff(ideal)
generic map(
delay => 250ns
)
port map(
input => oe,
output => latch_logic
);
da1 : entity work.dac_10_bit(behavioral)
port map(
bus_in => data_bus,
analog_out => ana_out,
clk => latch
);
-- clock
P_clock :
process
begin
clock <= '1';
wait for 50.0 us;
clock <= '0';
wait for 50.0 us;
end process P_clock;
-- start
P_start :
process
begin
start <= '0';
wait for 2.0 ms;
start <= '1';
wait for 0.2 ms;
start <= '0';
wait for 2.0 ms;
end process P_start;
end TB_a2d_d2a;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1933.vhd | 4 | 1943 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1933.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01933ent IS
END c07s02b01x00p01n04i01933ent;
ARCHITECTURE c07s02b01x00p01n04i01933arch OF c07s02b01x00p01n04i01933ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
z := (x and y); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01933 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01933arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1147.vhd | 5 | 2139 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1147.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p05n03i01147ent IS
END c06s05b00x00p05n03i01147ent;
ARCHITECTURE c06s05b00x00p05n03i01147arch OF c06s05b00x00p05n03i01147ent IS
SUBTYPE thirteen is INTEGER range 0 to 12;
BEGIN
TESTING: PROCESS
VARIABLE null_array : bit_vector ( 1 to 0 ); -- OK, a nice clean null array
VARIABLE slice : bit_vector ( thirteen );
BEGIN
assert NOT( null_array = slice (11 to 10) and
null_array = slice (-1 to -5) and
null_array = slice (15 to 14) )
report "***PASSED TEST: c06s05b00x00p05n03i01147"
severity NOTE;
assert ( null_array = slice (11 to 10) and
null_array = slice (-1 to -5) and
null_array = slice (15 to 14) )
report "***FAILED TEST: c06s05b00x00p05n03i01147 - The bounds of a null slice need not belong to the subtype of the index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p05n03i01147arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/switch_dig_2in.vhd | 4 | 2582 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity switch_dig_2in is
port ( sw_state : in std_ulogic; -- Digital control input
terminal p_in1, p_in2, p_out : electrical ); -- Analog output
end entity switch_dig_2in;
----------------------------------------------------------------
architecture ideal of switch_dig_2in is
constant r_open : resistance := 1.0e6; -- Open switch resistance
constant r_closed : resistance := 0.001; -- Closed switch resistance
constant trans_time : real := 0.00001; -- Transition time to each position
signal r_sig1 : resistance := r_closed; -- Closed switch resistance variable
signal r_sig2 : resistance := r_open; -- Open switch resistance variable
quantity v1 across i1 through p_in1 to p_out; -- V & I for in1 to out
quantity v2 across i2 through p_in2 to p_out; -- V & I for in2 to out
quantity r1 : resistance; -- Time-varying resistance for in1 to out
quantity r2 : resistance; -- Time-varying resistance for in2 to out
begin
process (sw_state) is -- Sensitivity to digital control input
begin
if sw_state = '0' or sw_state = 'L' then -- Close sig1, open sig2
r_sig1 <= r_closed;
r_sig2 <= r_open;
elsif sw_state = '1' or sw_state = 'H' then -- Open sig1, close sig2
r_sig1 <= r_open;
r_sig2 <= r_closed;
end if;
end process;
r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity
r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity
v1 == r1 * i1; -- Apply Ohm's law to in1
v2 == r2 * i2; -- Apply Ohm's law to in2
end architecture ideal;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/non_compliant/ch_04_ch_04_09.vhd | 4 | 2329 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_ch_04_09.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_04_09 is
end entity ch_04_09;
----------------------------------------------------------------
architecture test of ch_04_09 is
begin
process_04_3_c : process is
-- code from book:
subtype name is string(1 to 20);
type display_string is array (integer range 0 to 19) of character;
variable item_name : name;
variable display : display_string;
--
subtype big_endian_upper_halfword is bit_vector(0 to 15);
subtype little_endian_upper_halfword is bit_vector(31 downto 16);
variable big : big_endian_upper_halfword;
variable little : little_endian_upper_halfword;
-- end of code from book
begin
-- error: Incompatible types for assignment
-- display := item_name; -- ilegal
item_name := (others => 'A');
little := x"AAAA";
-- code from book:
display := display_string(item_name);
--
big := little;
little := big;
-- end of code from book
wait;
end process process_04_3_c;
----------------
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi-b.vhd | 4 | 13461 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxi-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
package body dlx_instr is
use bv_utilities.bv_arithmetic.all;
constant opcode_names : opcode_name_array
:= ( "SPECIAL ", "FPARITH ", "J ", "JAL ",
"BEQZ ", "BNEZ ", "BFPT ", "BFPF ",
"ADDI ", "ADDUI ", "SUBI ", "SUBUI ",
"ANDI ", "ORI ", "XORI ", "LHI ",
"RFE ", "TRAP ", "JR ", "JALR ",
"SLLI ", "UNDEF_15", "SRLI ", "SRAI ",
"SEQI ", "SNEI ", "SLTI ", "SGTI ",
"SLEI ", "SGEI ", "UNDEF_1E", "UNDEF_1F",
"LB ", "LH ", "UNDEF_22", "LW ",
"LBU ", "LHU ", "LF ", "LD ",
"SB ", "SH ", "UNDEF_2A", "SW ",
"UNDEF_2C", "UNDEF_2D", "SF ", "SD ",
"SEQUI ", "SNEUI ", "SLTUI ", "SGTUI ",
"SLEUI ", "SGEUI ", "UNDEF_36", "UNDEF_37",
"UNDEF_38", "UNDEF_39", "UNDEF_3A", "UNDEF_3B",
"UNDEF_3C", "UNDEF_3D", "UNDEF_3E", "UNDEF_3F" );
constant sp_func_names : sp_func_name_array
:= ( "NOP ", "UNDEF_01", "UNDEF_02", "UNDEF_03",
"SLL ", "UNDEF_05", "SRL ", "SRA ",
"UNDEF_08", "UNDEF_09", "UNDEF_0A", "UNDEF_0B",
"UNDEF_0C", "UNDEF_0D", "UNDEF_0E", "UNDEF_0F",
"SEQU ", "SNEU ", "SLTU ", "SGTU ",
"SLEU ", "SGEU ", "UNDEF_16", "UNDEF_17",
"UNDEF_18", "UNDEF_19", "UNDEF_1A", "UNDEF_1B",
"UNDEF_1C", "UNDEF_1D", "UNDEF_1E", "UNDEF_1F",
"ADD ", "ADDU ", "SUB ", "SUBU ",
"AND ", "OR ", "XOR ", "UNDEF_27",
"SEQ ", "SNE ", "SLT ", "SGT ",
"SLE ", "SGE ", "UNDEF_2E", "UNDEF_2F",
"MOVI2S ", "MOVS2I ", "MOVF ", "MOVD ",
"MOVFP2I ", "MOVI2FP ", "UNDEF_36", "UNDEF_37",
"UNDEF_38", "UNDEF_39", "UNDEF_3A", "UNDEF_3B",
"UNDEF_3C", "UNDEF_3D", "UNDEF_3E", "UNDEF_3F" );
constant fp_func_names : fp_func_name_array
:= ( "ADDF ", "SUBF ", "MULTF ", "DIVF ",
"ADDD ", "SUBD ", "MULTD ", "DIVD ",
"CVTF2D ", "CVTF2I ", "CVTD2F ", "CVTD2I ",
"CVTI2F ", "CVTI2D ", "MULT ", "DIV ",
"EQF ", "NEF ", "LTF ", "GTF ",
"LEF ", "GEF ", "MULTU ", "DIVU ",
"EQD ", "NED ", "LTD ", "GTD ",
"LED ", "GED ", "UNDEF_1E", "UNDEF_1F" );
procedure disassemble ( instr : dlx_bv_word;
disassembled_instr : out string; len : out positive ) is
alias norm_disassembled_instr : string(1 to disassembled_instr'length)
is disassembled_instr;
alias instr_opcode : dlx_opcode is instr(0 to 5);
alias instr_sp_func : dlx_sp_func is instr(26 to 31);
alias instr_fp_func : dlx_fp_func is instr(27 to 31);
alias instr_rs1 : dlx_reg_addr is instr(6 to 10);
alias instr_rs2 : dlx_reg_addr is instr(11 to 15);
alias instr_Itype_rd : dlx_reg_addr is instr(11 to 15);
alias instr_Rtype_rd : dlx_reg_addr is instr(16 to 20);
alias instr_immed16 : dlx_immed16 is instr(16 to 31);
alias instr_immed26 : dlx_immed26 is instr(6 to 31);
variable instr_opcode_num : dlx_opcode_num;
variable instr_sp_func_num : dlx_sp_func_num;
variable instr_fp_func_num : dlx_fp_func_num;
variable rs1 : reg_index;
variable rs2 : reg_index;
variable Itype_rd : reg_index;
variable Rtype_rd : reg_index;
variable result : string(1 to 40) -- long enough for longest instruction
:= (others => ' ');
variable index : positive range 1 to 41 := 1; -- position for next char in result
procedure disassemble_reg ( reg : reg_index; reg_prefix : character ) is
begin
result(index) := reg_prefix;
index := index + 1;
if reg < 10 then
result(index to index) := integer'image(reg);
index := index + 1;
else
result(index to index + 1) := integer'image(reg);
index := index + 2;
end if;
end procedure disassemble_reg;
procedure disassemble_special_reg ( reg : reg_index ) is
begin
case reg is
when 0 =>
result(index to index + 2) := "IAR";
index := index + 3;
when 1 =>
result(index to index + 2) := "FSR";
index := index + 3;
when others =>
disassemble_reg(reg, 'S');
end case;
end procedure disassemble_special_reg;
procedure disassemble_integer ( int : integer ) is
constant int_image_length : natural := integer'image(int)'length;
begin
result(index to index + int_image_length - 1) := integer'image(int);
index := index + int_image_length;
end procedure disassemble_integer;
begin
instr_opcode_num := bv_to_natural(instr_opcode);
instr_sp_func_num := bv_to_natural(instr_sp_func);
instr_fp_func_num := bv_to_natural(instr_fp_func);
rs1 := bv_to_natural(instr_rs1);
rs2 := bv_to_natural(instr_rs2);
Itype_rd := bv_to_natural(instr_Itype_rd);
Rtype_rd := bv_to_natural(instr_Rtype_rd);
if (instr_opcode /= op_special) and (instr_opcode /= op_fparith) then
result(index to index + instr_name'length - 1) := opcode_names(instr_opcode_num);
index := index + instr_name'length + 1; -- include space after opcode name
end if;
case instr_opcode is
when op_special =>
result(index to index + instr_name'length - 1) := sp_func_names(instr_sp_func_num);
index := index + instr_name'length + 1; -- include space after function name
case instr_sp_func is
when sp_func_nop =>
null;
when sp_func_sll | sp_func_srl | sp_func_sra
| sp_func_sequ | sp_func_sneu | sp_func_sltu
| sp_func_sgtu | sp_func_sleu | sp_func_sgeu
| sp_func_add | sp_func_addu | sp_func_sub | sp_func_subu
| sp_func_and | sp_func_or | sp_func_xor
| sp_func_seq | sp_func_sne | sp_func_slt
| sp_func_sgt | sp_func_sle | sp_func_sge =>
disassemble_reg(Rtype_rd, 'R');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(rs1, 'R');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(rs2, 'R');
when sp_func_movi2s =>
disassemble_special_reg(Rtype_rd);
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(rs1, 'R');
when sp_func_movs2i =>
disassemble_reg(Rtype_rd, 'R');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_special_reg(rs1);
when sp_func_movf | sp_func_movd =>
disassemble_reg(Rtype_rd, 'F');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(rs1, 'F');
when sp_func_movfp2i =>
disassemble_reg(Rtype_rd, 'R');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(rs1, 'F');
when sp_func_movi2fp =>
disassemble_reg(Rtype_rd, 'F');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(rs1, 'R');
when others =>
null;
end case;
when op_fparith =>
result(index to index + instr_name'length - 1) := fp_func_names(instr_fp_func_num);
index := index + instr_name'length + 1; -- include space after function name
case instr_fp_func is
when fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf
| fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd
| fp_func_mult | fp_func_div | fp_func_multu | fp_func_divu =>
disassemble_reg(Rtype_rd, 'F');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(rs1, 'F');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(rs2, 'F');
when fp_func_cvtf2d | fp_func_cvtd2f =>
disassemble_reg(Rtype_rd, 'F');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(rs1, 'F');
when fp_func_cvtf2i | fp_func_cvtd2i =>
disassemble_reg(Rtype_rd, 'R');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(rs1, 'F');
when fp_func_cvti2f | fp_func_cvti2d =>
disassemble_reg(Rtype_rd, 'F');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(rs1, 'R');
when fp_func_eqf | fp_func_nef | fp_func_ltf
| fp_func_gtf | fp_func_lef | fp_func_gef
| fp_func_eqd | fp_func_ned | fp_func_ltd
| fp_func_gtd | fp_func_led | fp_func_ged =>
disassemble_reg(rs1, 'F');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(rs2, 'F');
when others =>
null;
end case;
when op_j | op_jal =>
disassemble_integer(bv_to_integer(instr_immed26));
when op_beqz | op_bnez =>
disassemble_reg(rs1, 'R');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_integer(bv_to_integer(instr_immed16));
when op_bfpt | op_bfpf =>
disassemble_integer(bv_to_integer(instr_immed16));
when op_slli | op_srli | op_srai =>
disassemble_reg(Itype_rd, 'R');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(rs1, 'R');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_integer(bv_to_natural(instr_immed16(11 to 15)));
when op_addi | op_subi
| op_seqi | op_snei | op_slti | op_sgti | op_slei | op_sgei =>
disassemble_reg(Itype_rd, 'R');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(rs1, 'R');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_integer(bv_to_integer(instr_immed16));
when op_addui | op_subui | op_andi | op_ori | op_xori
| op_sequi | op_sneui | op_sltui | op_sgtui | op_sleui | op_sgeui =>
disassemble_reg(Itype_rd, 'R');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(rs1, 'R');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_integer(bv_to_natural(instr_immed16));
when op_lhi =>
disassemble_reg(Itype_rd, 'R');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_integer(bv_to_natural(instr_immed16));
when op_rfe =>
null;
when op_trap =>
disassemble_integer(bv_to_natural(instr_immed26));
when op_jr | op_jalr =>
disassemble_reg(rs1, 'R');
when op_lb | op_lh | op_lw | op_lbu | op_lhu | op_lf | op_ld =>
disassemble_reg(Itype_rd, 'R');
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_integer(bv_to_integer(instr_immed16));
result(index) := '(';
index := index + 1;
disassemble_reg(rs1, 'R');
result(index) := ')';
index := index + 1;
when op_sb | op_sh | op_sw | op_sf | op_sd =>
disassemble_integer(bv_to_integer(instr_immed16));
result(index) := '(';
index := index + 1;
disassemble_reg(rs1, 'R');
result(index) := ')';
index := index + 1;
result(index) := ',';
index := index + 2; -- include space after comma
disassemble_reg(Itype_rd, 'R');
when others =>
null; -- remaining opcodes have no operands to disassemble
end case;
if index > norm_disassembled_instr'length then
index := norm_disassembled_instr'length; -- limit to out parameter length
else
index := index - 1; -- index points to last result character
end if;
norm_disassembled_instr(1 to index) := result(1 to index);
len := index;
end procedure disassemble;
end package body dlx_instr;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2783.vhd | 4 | 1774 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2783.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity BLOCK is
end BLOCK;
ENTITY c13s09b00x00p99n01i02783ent IS
END c13s09b00x00p99n01i02783ent;
ARCHITECTURE c13s09b00x00p99n01i02783arch OF c13s09b00x00p99n01i02783ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02783 - Reserved word BLOCK can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02783arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd | 4 | 2771 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
-- code from book
entity bottom is
port ( terminal Tb : electrical; -- ... );
-- not in book
terminal Tz : electrical );
-- end not in book
end entity bottom;
-- end code from book
architecture bottom_arch of bottom is
-- code from book
quantity -- ...
i_b1 through Tb to Tz; -- ...;
quantity -- ...
i_b2 through Tb to Tz; -- ...;
quantity -- ...
i_b3 through Tz to Tb; -- ... to Tb;
quantity -- ...
i_b4 through Tz to Tb; -- ... to Tb;
-- end code from book
begin
assert
-- code from book
Tb'contribution = ( i_b1 + i_b2 ) - ( i_b3 + i_b4 )
-- end code from book
;
end architecture bottom_arch;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity other_ent is
port ( terminal Tx, Tz : electrical );
end entity other_ent;
architecture other_arch of other_ent is
begin
end architecture other_arch;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_03a is
end entity inline_03a;
architecture test of inline_03a is
terminal Ty, Tb, Tx : electrical;
-- code from book
terminal T : electrical;
quantity -- ...
i_t1, i_t2 through T to Ty; -- ...;
quantity -- ...
i_t3 through Ty to T; -- ... to T;
-- ...
-- end code from book
begin
-- code from book
comp1 : entity work.bottom(bottom_arch)
port map ( Tb => T, -- ... );
-- not in book
Tz => Ty );
-- end not in book
comp2 : entity work.other_ent(other_arch)
port map ( Tx => T, -- ... );
-- not in book
Tz => Ty );
-- end not in book
-- end code from book
assert
-- code from book
T'contribution = ( i_t1 + i_t2 ) - ( i_t3 ) + ( Tb'contribution + Tx'contribution )
-- end code from book
;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1003.vhd | 4 | 1771 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1003.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01003pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i01003pkg;
use work.c06s03b00x00p09n01i01003pkg.all;
ENTITY c06s03b00x00p09n01i01003ent IS
END c06s03b00x00p09n01i01003ent;
ARCHITECTURE c06s03b00x00p09n01i01003arch OF c06s03b00x00p09n01i01003ent IS
BEGIN
TESTING: PROCESS
subtype ST8 is E.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i01003 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01003arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc601.vhd | 4 | 2826 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc601.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:41 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:58 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:19 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00601ent IS
END c03s04b01x00p01n01i00601ent;
ARCHITECTURE c03s04b01x00p01n01i00601arch OF c03s04b01x00p01n01i00601ent IS
type time_cons_vector is array (15 downto 0) of time;
type time_cons_vector_file is file of time_cons_vector;
constant C19 : time_cons_vector := (others => 3 ns);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : time_cons_vector_file open read_mode is "iofile.32";
variable v : time_cons_vector;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C19) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00601"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00601 - File reading operation (time_cons_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00601arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1280.vhd | 4 | 1684 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1280.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01280ent IS
END c08s04b00x00p04n01i01280ent;
ARCHITECTURE c08s04b00x00p04n01i01280arch OF c08s04b00x00p04n01i01280ent IS
type ENUM_1 is (ONE,TWO,THREE);
signal S1 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
TWO - ONE <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01280 - Literal expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01280arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc944.vhd | 4 | 1600 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc944.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p09n01i00944ent IS
END c06s01b00x00p09n01i00944ent;
ARCHITECTURE c06s01b00x00p09n01i00944arch OF c06s01b00x00p09n01i00944ent IS
BEGIN
TESTING: PROCESS
constant T: time := 'a'.foo;
BEGIN
assert FALSE
report "***FAILED TEST: c06s01b00x00p09n01i00944 - Prefix can only be a name or a function_call."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p09n01i00944arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/deb573721/573721_deb.vhd | 3 | 1935 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is end entity;
architecture a_test of test is
signal a, b : std_logic;
signal i1 : integer := 1;
constant i2 : integer := 1;
signal t1 : time := 1 ns;
constant t2 : time := 1 ns;
begin
process
variable m : boolean;
variable ip1 : integer := 1;
constant ip2 : integer := 1;
variable tp1 : time := 1 ns;
constant tp2 : time := 1 ns;
begin
m := a'stable(1 ns); --works ... literal
m := a'stable(i1 * ns); --works ... signal * unit
m := a'stable(i2 * ns); --works ... constant * unit
m := a'stable(t1); --works ... signal (time)
m := a'stable(t2); --works ... constant (time)
m := a'stable(ip1 * ns); --crashs ... LOCAL variable * unit
m := a'stable(ip2 * ns); --works ... LOCAL constant * unit
m := a'stable(tp1); --crashs ... LOCAL variable (time)
m := a'stable(tp2); --crashs ... LOCAL constant (time)
--
m := a'quiet(1 ns); --works
m := a'quiet(i1 * ns); --works
m := a'quiet(i2 * ns); --works
m := a'quiet(t1); --works
m := a'quiet(t2); --works
m := a'quiet(ip1 * ns); --crashs
m := a'quiet(ip2 * ns); --works
m := a'quiet(tp1); --crashs
m := a'quiet(tp2); --crashs
--
b <= a'delayed(1 ns); --works
b <= a'delayed(i1 * ns); --works
b <= a'delayed(i2 * ns); --works
b <= a'delayed(t1); --works
b <= a'delayed(t2); --works
b <= a'delayed(ip1 * ns); --crashs
b <= a'delayed(ip2 * ns); --works
b <= a'delayed(tp1); --crashs
b <= a'delayed(tp2); --crashs
end process;
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1193.vhd | 4 | 1618 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1193.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p05n01i01193ent IS
END c08s01b00x00p05n01i01193ent;
ARCHITECTURE c08s01b00x00p05n01i01193arch OF c08s01b00x00p05n01i01193ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
k <= 5 after 5 ns;
wait no k;
assert FALSE
report "***FAILED TEST: c08s01b00x00p05n01i01193 - Reserved word 'on' is misspelled"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p05n01i01193arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_count2.vhd | 4 | 1067 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_count2 is
end entity tb_count2;
architecture test of tb_count2 is
signal clk, q0, q1 : bit;
begin
dut : entity work.count2(buffered_outputs)
port map ( clk => clk, q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 10 ns;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_03.vhd | 4 | 3280 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_03.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
package CPU_types is
subtype word is bit_vector(0 to 31);
subtype byte is bit_vector(0 to 7);
alias convert_to_natural is
bv_utilities.bv_arithmetic.bv_to_natural [ bit_vector return natural ];
constant halt_opcode : byte := "00000000";
type code_array is array (natural range <>) of word;
constant code : code_array := ( X"01000000", X"01000000", X"02000000",
X"01000000", X"01000000", X"02000000",
X"00000000" );
end package CPU_types;
use work.CPU_types.all;
entity CPU is
end entity CPU;
-- code from book
architecture instrumented of CPU is
type count_file is file of natural;
file instruction_counts : count_file open write_mode is "instructions";
begin
interpreter : process is
variable IR : word;
alias opcode : byte is IR(0 to 7);
variable opcode_number : natural;
type counter_array is array (0 to 2**opcode'length - 1) of natural;
variable counters : counter_array := (others => 0);
-- . . .
-- not in book
variable code_index : natural := 0;
-- end not in book
begin
-- . . . -- initialize the instruction set interpreter
instruction_loop : loop
-- . . . -- fetch the next instruction into IR
-- not in book
IR := code(code_index);
code_index := code_index + 1;
-- end not in book
-- decode the instruction
opcode_number := convert_to_natural(opcode);
counters(opcode_number) := counters(opcode_number) + 1;
-- . . .
-- execute the decoded instruction
case opcode is
-- . . .
when halt_opcode => exit instruction_loop;
-- . . .
-- not in book
when others => null;
-- end not in book
end case;
end loop instruction_loop;
for index in counters'range loop
write(instruction_counts, counters(index));
end loop;
wait; -- program finished, wait forever
end process interpreter;
end architecture instrumented;
-- code from book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc531.vhd | 4 | 3585 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc531.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00531ent IS
END c03s03b00x00p03n04i00531ent;
ARCHITECTURE c03s03b00x00p03n04i00531arch OF c03s03b00x00p03n04i00531ent IS
BEGIN
TESTING : PROCESS
type bool_ptr is access boolean;
variable v_bool_ptr1: bool_ptr := new boolean'(true);
variable v_bool_ptr2: bool_ptr;
variable v_bool_ptr3: bool_ptr := v_bool_ptr1;
variable v_bool_ptr4: bool_ptr := new boolean'(false);
variable v_bool_ptr5: bool_ptr := v_bool_ptr4;
variable OKtest : integer := 0;
BEGIN
assert v_bool_ptr1.all = true;
if (v_bool_ptr1.all = true) then
OKtest := Oktest + 1;
end if;
assert v_bool_ptr2 = null;
if (v_bool_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_bool_ptr3.all = true;
if (v_bool_ptr3.all = true) then
OKtest := Oktest + 1;
end if;
assert v_bool_ptr4.all = false;
if (v_bool_ptr4.all = false) then
OKtest := Oktest + 1;
end if;
assert v_bool_ptr5.all = false;
if (v_bool_ptr5.all = false) then
OKtest := Oktest + 1;
end if;
v_bool_ptr2 := new boolean'(true);
assert v_bool_ptr2.all = true;
if (v_bool_ptr2.all = true) then
OKtest := Oktest + 1;
end if;
assert (v_bool_ptr1.all and v_bool_ptr5.all) = false;
if ((v_bool_ptr1.all and v_bool_ptr5.all) = false) then
OKtest := Oktest + 1;
end if;
assert (v_bool_ptr1.all and v_bool_ptr2.all) = true;
if ((v_bool_ptr1.all and v_bool_ptr2.all) = true) then
OKtest := Oktest + 1;
end if;
assert (v_bool_ptr3.all or v_bool_ptr5.all) = true;
if ((v_bool_ptr3.all or v_bool_ptr5.all) = true) then
OKtest := Oktest + 1;
end if;
assert (v_bool_ptr3.all > v_bool_ptr5.all) = true;
if ((v_bool_ptr3.all > v_bool_ptr5.all) = true) then
OKtest := Oktest + 1;
end if;
assert (not v_bool_ptr3.all) = false;
if ((not v_bool_ptr3.all) = false) then
OKtest := Oktest + 1;
end if;
deallocate(v_bool_ptr1);
deallocate(v_bool_ptr2);
deallocate(v_bool_ptr4);
assert NOT(OKtest = 11)
report "***PASSED TEST: c03s03b00x00p03n04i00531"
severity NOTE;
assert (OKtest = 11)
report "***FAILED TEST: c03s03b00x00p03n04i00531 - Boolean type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00531arch;
| gpl-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.