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peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3002.vhd | 4 | 1774 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3002.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p05n02i03002pkg is
end c02s06b00x00p05n02i03002pkg;
package body c02s06b00x00p05n02i03002pkg is
end c02s06b00x00p05n02i03002; --Failure here
ENTITY c02s06b00x00p05n02i03002ent IS
END c02s06b00x00p05n02i03002ent;
ARCHITECTURE c02s06b00x00p05n02i03002arch OF c02s06b00x00p05n02i03002ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p05n02i03002- The simple name at the end of a package body must be the same as the package identifier."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p05n02i03002arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1242.vhd | 4 | 1672 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1242.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n01i01242ent IS
END c08s02b00x00p04n01i01242ent;
ARCHITECTURE c08s02b00x00p04n01i01242arch OF c08s02b00x00p04n01i01242ent IS
BEGIN
TESTING: PROCESS
constant N2 : Character := 'R';
BEGIN
assert FALSE
report N2
severity NOTE;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n01i01242 - Expression type used in a report clause should be STRING"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n01i01242arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket77/bug1.vhdl | 3 | 204 | entity ent1 is
end entity;
architecture a of ent1 is
begin
main : process
begin
wait for 0 ns; -- Comment and it exits with code 1
std.env.stop(1);
wait;
end process;
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2015.vhd | 4 | 2011 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2015.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p11n02i02015ent IS
END c07s02b02x00p11n02i02015ent;
ARCHITECTURE c07s02b02x00p11n02i02015arch OF c07s02b02x00p11n02i02015ent IS
BEGIN
TESTING: PROCESS
type array_three is array (1 to 6) of integer;
variable array_1 : array_three := (6,5,4,3,2,1);
variable array_2 : array_three := (6,5,4,4,3,2);
variable k : integer;
BEGIN
if array_1 < array_2 then -- No_failure_here
k := 5;
end if;
wait for 5 ns;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p11n02i02015"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c07s02b02x00p11n02i02015 - The relation < returns TRUE if the left operand is a null array and the right operand is a non-null array."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p11n02i02015arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1701.vhd | 4 | 1824 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1701.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p05n01i01701ent IS
END c09s02b00x00p05n01i01701ent;
ARCHITECTURE c09s02b00x00p05n01i01701arch OF c09s02b00x00p05n01i01701ent IS
signal b_sig : boolean := true;
BEGIN
TESTING: PROCESS
variable trigger : integer := 0;
BEGIN
--
-- Test concurrent conditional signal assignment
--
b_sig <= false when trigger = 0 else -- illegal loc for conc statement
true;
assert FALSE
report "***FAILED TEST: c09s02b00x00p05n01i01701 - Process statement can only have sequential statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p05n01i01701arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_04a.vhd | 4 | 1769 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
-- code from book
entity battery is
port ( terminal plus, minus : electrical );
end entity battery;
architecture wrong of battery is
constant v_nominal : real := 9.0;
quantity v across plus to minus;
begin
v == v_nominal;
end architecture wrong;
--
architecture correct of battery is
constant v_nominal : real := 9.0;
quantity v across i through plus to minus;
begin
v == v_nominal;
end architecture correct;
-- end code from book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_04a is
end entity inline_04a;
architecture test of inline_04a is
signal clamp : bit;
quantity v1, v2 : real;
begin
-- code from book
if clamp = '1' use
v1 == 5.0;
v2 == 0.0;
else
v1 == v2;
end use;
-- end code from book
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_01.vhd | 4 | 1540 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
begin
process is
-- code from book:
type natural_ptr is access natural;
variable count : natural_ptr;
-- end of code from book
begin
-- code from book:
count := new natural;
count.all := 10;
if count.all = 0 then
-- . . .
-- not in book
report "count.all = 0";
-- end not in book
end if;
-- end of code from book
if count.all /= 0 then
report "count.all /= 0";
end if;
-- code from book:
count := new natural'(10);
-- end of code from book
wait;
end process;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd | 4 | 1997 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity decoder_3_to_8 is
generic ( Tpd_01, Tpd_10 : delay_length );
port ( s0, s1, s2 : in bit;
enable : in bit;
y0, y1, y2, y3, y4, y5, y6, y7 : out bit );
end entity decoder_3_to_8;
-- not in book
architecture basic of decoder_3_to_8 is
begin
process (enable, s2, s1, s0) is
begin
if enable = '0' then
(y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000000");
else
case bit_vector'(s2, s1, s0) is
when "000" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000001");
when "001" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000010");
when "010" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000100");
when "011" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00001000");
when "100" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00010000");
when "101" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00100000");
when "110" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("01000000");
when "111" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("10000000");
end case;
end if;
end process;
end architecture basic;
-- end not in book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/access-types/tb_bounded_buffer_adt.vhd | 4 | 2225 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_bounded_buffer_adt is
end entity tb_bounded_buffer_adt;
architecture test of tb_bounded_buffer_adt is
begin
process is
use work.bounded_buffer_adt.all;
variable buf : bounded_buffer := new_bounded_buffer(4);
variable empty, full : boolean;
variable d : byte;
begin
test_empty(buf, empty);
assert empty;
test_full(buf, full);
assert not full;
write(buf, X"01");
write(buf, X"02");
test_empty(buf, empty);
assert not empty;
test_full(buf, full);
assert not full;
write(buf, X"03");
write(buf, X"04");
test_empty(buf, empty);
assert not empty;
test_full(buf, full);
assert full;
write(buf, X"05");
read(buf, d);
read(buf, d);
test_empty(buf, empty);
assert not empty;
test_full(buf, full);
assert not full;
read(buf, d);
read(buf, d);
test_empty(buf, empty);
assert empty;
test_full(buf, full);
assert not full;
read(buf, d);
write(buf, X"06");
write(buf, X"07");
write(buf, X"08");
read(buf, d);
read(buf, d);
write(buf, X"09");
read(buf, d);
write(buf, X"0A");
read(buf, d);
write(buf, X"0B");
read(buf, d);
write(buf, X"0C");
read(buf, d);
write(buf, X"0D");
read(buf, d);
write(buf, X"0E");
read(buf, d);
write(buf, X"0F");
read(buf, d);
wait;
end process;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2208.vhd | 4 | 1813 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2208.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02208ent IS
END c07s02b06x00p01n01i02208ent;
ARCHITECTURE c07s02b06x00p01n01i02208arch OF c07s02b06x00p01n01i02208ent IS
BEGIN
TESTING: PROCESS
constant x : integer := 15;
constant y : integer := 9;
variable z : integer;
BEGIN
z := x mod y; -- No_failure_here
assert NOT(z=6)
report "***PASSED TEST: c07s02b06x00p01n01i02208"
severity NOTE;
assert (z=6)
report "***FAILED TEST: c07s02b06x00p01n01i02208 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02208arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc187.vhd | 4 | 1895 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc187.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p12n01i00187ent IS
attribute ATE : INTEGER;
attribute ATE of c04s04b00x00p12n01i00187ent : entity is 2;
--Correct placement in interface declaration
END c04s04b00x00p12n01i00187ent;
ARCHITECTURE c04s04b00x00p12n01i00187arch OF c04s04b00x00p12n01i00187ent IS
BEGIN
TESTING: PROCESS
variable S : integer;
BEGIN
S := c04s04b00x00p12n01i00187ent'ATE;
assert NOT( S = 2 )
report "***PASSED TEST: c04s04b00x00p12n01i00187"
severity NOTE;
assert ( S = 2 )
report "***FAILED TEST: c04s04b00x00p12n01i00187 - Attribute specification of the entity test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p12n01i00187arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_transmission_line.vhd | 4 | 1587 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_transmission_line is
end tb_transmission_line;
architecture TB_transmission_line of tb_transmission_line is
quantity in_src, line_out : voltage;
-- Component declarations
-- Signal declarations
begin
-- Signal assignments
-- Component instances
q1 : entity work.src_pulse(ideal)
generic map(
initial => 0.0,
pulse => 1.0e1,
ti2p => 1.0e-12,
tp2i => 1.0e-12,
delay => 1 ps,
width => 20 ns,
period => 50 ns
)
port map(
output => in_src
);
T1 : entity work.transmission_line_wa(abstract)
port map(
vin => in_src,
vout => line_out
);
end TB_transmission_line;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc16.vhd | 4 | 2000 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc16.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p06n03i00016ent IS
END c04s02b00x00p06n03i00016ent;
ARCHITECTURE c04s02b00x00p06n03i00016arch OF c04s02b00x00p06n03i00016ent IS
BEGIN
TESTING: PROCESS
-- Define a subtype of a subtype.
subtype ZERO is NATURAL;
-- Define variables of these subtypes.
variable ZEROV : ZERO := 0;
variable NATURALV : NATURAL := 0;
BEGIN
-- Verify that these two variables have the same base type.
assert NOT( Naturalv = zerov and zerov = zero'low )
report "***PASSED TEST: c04s02b00x00p06n03i00016"
severity NOTE;
assert ( Naturalv = zerov and zerov = zero'low )
report "***FAILED TEST: c04s02b00x00p06n03i00016 - The base type of a subtype is the base type of the type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p06n03i00016arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug18810/DMEM.vhd | 3 | 6721 | -- NOTE: http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
library ieee;
use ieee.std_logic_1164.all;
package DMEM_PRIM_PKG is
component DMEM_PRIM is
generic (
log2A : integer range 0 to integer'high := 4;
DW : integer range 1 to integer'high := 8;
ZERO : boolean := false
);
port (
iWCLK : in std_logic;
iWE : in std_logic;
iWA : in integer range 0 to 2**log2A-1;
iWD : in std_logic_vector(DW-1 downto 0);
iRA0 : in integer range 0 to 2**log2A-1;
iRA1 : in integer range 0 to 2**log2A-1;
iRA2 : in integer range 0 to 2**log2A-1;
oRD0 : out std_logic_vector(DW-1 downto 0);
oRD1 : out std_logic_vector(DW-1 downto 0);
oRD2 : out std_logic_vector(DW-1 downto 0)
);
end component DMEM_PRIM;
constant cDMEM_PRIM_W_LATENCY : integer := 1;
constant cDMEM_PRIM_R0_LATENCY : integer := 0;
constant cDMEM_PRIM_R1_LATENCY : integer := 0;
constant cDMEM_PRIM_R2_LATENCY : integer := 0;
end package DMEM_PRIM_PKG;
package body DMEM_PRIM_PKG is
-- NOTE: This body should keep to be empty to stub.
end package body DMEM_PRIM_PKG;
library ieee;
use ieee.std_logic_1164.all;
entity DMEM_PRIM is
generic (
log2A : integer range 0 to integer'high := 4;
DW : integer range 1 to integer'high := 8;
ZERO : boolean := false
);
port (
iWCLK : in std_logic;
iWE : in std_logic;
iWA : in integer range 0 to 2**log2A-1;
iWD : in std_logic_vector(DW-1 downto 0);
iRA0 : in integer range 0 to 2**log2A-1;
iRA1 : in integer range 0 to 2**log2A-1;
iRA2 : in integer range 0 to 2**log2A-1;
oRD0 : out std_logic_vector(DW-1 downto 0);
oRD1 : out std_logic_vector(DW-1 downto 0);
oRD2 : out std_logic_vector(DW-1 downto 0)
);
begin
end entity DMEM_PRIM;
architecture RTL of DMEM_PRIM is
type tDMEM_PRIM is array (0 to 2**log2A-1) of std_logic_vector(DW-1 downto 0);
signal aDMEM_PRIM0 : tDMEM_PRIM := (0 to 2**log2A-1 => (DW-1 downto 0 => '0'));
signal aDMEM_PRIM1 : tDMEM_PRIM := (0 to 2**log2A-1 => (DW-1 downto 0 => '0'));
signal aDMEM_PRIM2 : tDMEM_PRIM := (0 to 2**log2A-1 => (DW-1 downto 0 => '0'));
begin
P_DMEM_PRIM : process (iWCLK)
begin
if (rising_edge(iWCLK)) then
if (iWE = '1') then
aDMEM_PRIM0(iWA) <= iWD;
aDMEM_PRIM1(iWA) <= iWD;
aDMEM_PRIM2(iWA) <= iWD;
end if;
end if;
end process P_DMEM_PRIM;
oRD0 <= (DW-1 downto 0 => '0') when (ZERO = true and iRA0 = 0) else aDMEM_PRIM0(iRA0);
oRD1 <= (DW-1 downto 0 => '0') when (ZERO = true and iRA1 = 0) else aDMEM_PRIM1(iRA1);
oRD2 <= (DW-1 downto 0 => '0') when (ZERO = true and iRA2 = 0) else aDMEM_PRIM2(iRA2);
end architecture RTL;
library ieee;
use ieee.std_logic_1164.all;
use work.DMEM_PRIM_PKG.all;
package DMEM_PKG is
component DMEM is
generic (
log2DADDR : integer range 0 to integer'high := 4;
DW : integer range 1 to integer'high := 8;
ZERO : boolean := false
);
port (
iDCLK : in std_logic;
iDWE : in std_logic;
iDADDR : in integer range 0 to 2**log2DADDR-1;
iDDATA : in std_logic_vector(DW-1 downto 0);
oDDATA : out std_logic_vector(DW-1 downto 0);
iCLK : in std_logic;
iAADDR : in integer range 0 to 2**log2DADDR-1;
oADATA : out std_logic_vector(DW-1 downto 0);
iBWE : in std_logic;
iBADDR : in integer range 0 to 2**log2DADDR-1;
iBDATA : in std_logic_vector(DW-1 downto 0);
oBDATA : out std_logic_vector(DW-1 downto 0)
);
end component DMEM;
constant cDMEM_DW_LATENCY : integer := cDMEM_PRIM_W_LATENCY;
constant cDMEM_DR_LATENCY : integer := cDMEM_PRIM_R0_LATENCY;
constant cDMEM_AR_LATENCY : integer := cDMEM_PRIM_R1_LATENCY;
constant cDMEM_BW_LATENCY : integer := cDMEM_PRIM_W_LATENCY;
constant cDMEM_BR_LATENCY : integer := cDMEM_PRIM_R2_LATENCY;
end package DMEM_PKG;
package body DMEM_PKG is
-- NOTE: This body should keep to be empty to stub.
end package body DMEM_PKG;
library ieee;
use ieee.std_logic_1164.all;
use work.DMEM_PRIM_PKG.all;
entity DMEM is
generic (
log2DADDR : integer range 0 to integer'high := 4;
DW : integer range 1 to integer'high := 8;
ZERO : boolean := false
);
port (
iDCLK : in std_logic;
iDWE : in std_logic;
iDADDR : in integer range 0 to 2**log2DADDR-1;
iDDATA : in std_logic_vector(DW-1 downto 0);
oDDATA : out std_logic_vector(DW-1 downto 0);
iCLK : in std_logic;
iAADDR : in integer range 0 to 2**log2DADDR-1;
oADATA : out std_logic_vector(DW-1 downto 0);
iBWE : in std_logic;
iBADDR : in integer range 0 to 2**log2DADDR-1;
iBDATA : in std_logic_vector(DW-1 downto 0);
oBDATA : out std_logic_vector(DW-1 downto 0)
);
begin
end entity DMEM;
architecture RTL of DMEM is
-- FIXME: ISE 13.2 does not support "protected"... :(
type tBANK is (BANK_D, BANK_B);
type tLVT is array (0 to 2**log2DADDR-1) of tBANK;
shared variable aLVT : tLVT := (0 to 2**log2DADDR-1 => BANK_D);
signal sDMEM_PRIM_D_oDDATA : std_logic_vector(DW-1 downto 0);
signal sDMEM_PRIM_D_oADATA : std_logic_vector(DW-1 downto 0);
signal sDMEM_PRIM_D_oBDATA : std_logic_vector(DW-1 downto 0);
signal sDMEM_PRIM_B_oDDATA : std_logic_vector(DW-1 downto 0);
signal sDMEM_PRIM_B_oADATA : std_logic_vector(DW-1 downto 0);
signal sDMEM_PRIM_B_oBDATA : std_logic_vector(DW-1 downto 0);
begin
P_LVT_D : process (iDCLK)
begin
if (rising_edge(iDCLK)) then
if (iDWE = '1') then
aLVT(iDADDR) := BANK_D;
end if;
end if;
end process P_LVT_D;
P_LVT_B : process (iCLK)
begin
if (rising_edge(iCLK)) then
if (iBWE = '1') then
aLVT(iBADDR) := BANK_B;
end if;
end if;
end process P_LVT_B;
U_DMEM_PRIM_D : DMEM_PRIM
generic map (
log2A => log2DADDR,
DW => DW,
ZERO => ZERO
)
port map (
iWCLK => iDCLK,
iWE => iDWE,
iWA => iDADDR,
iWD => iDDATA,
iRA0 => iDADDR,
iRA1 => iAADDR,
iRA2 => iBADDR,
oRD0 => sDMEM_PRIM_D_oDDATA,
oRD1 => sDMEM_PRIM_D_oADATA,
oRD2 => sDMEM_PRIM_D_oBDATA
);
U_DMEM_PRIM_B : DMEM_PRIM
generic map (
log2A => log2DADDR,
DW => DW,
ZERO => ZERO
)
port map (
iWCLK => iCLK,
iWE => iBWE,
iWA => iBADDR,
iWD => iBDATA,
iRA0 => iDADDR,
iRA1 => iAADDR,
iRA2 => iBADDR,
oRD0 => sDMEM_PRIM_B_oDDATA,
oRD1 => sDMEM_PRIM_B_oADATA,
oRD2 => sDMEM_PRIM_B_oBDATA
);
oDDATA <= sDMEM_PRIM_D_oDDATA when (aLVT(iDADDR) = BANK_D) else sDMEM_PRIM_B_oDDATA;
oADATA <= sDMEM_PRIM_D_oADATA when (aLVT(iAADDR) = BANK_D) else sDMEM_PRIM_B_oADATA;
oBDATA <= sDMEM_PRIM_D_oBDATA when (aLVT(iBADDR) = BANK_D) else sDMEM_PRIM_B_oBDATA;
end architecture RTL;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc762.vhd | 4 | 8163 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc762.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00762pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
end c01s01b01x01p05n02i00762pkg;
use work.c01s01b01x01p05n02i00762pkg.ALL;
ENTITY c01s01b01x01p05n02i00762ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen :integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen70 : boolean_vector_st :=(others => true);
Cgen71 : severity_level_vector_st :=(others => note);
Cgen72 : integer_vector_st :=(others => 3);
Cgen73 : real_vector_st :=(others => 3.0);
Cgen74 : time_vector_st :=(others => 3 ns);
Cgen75 : natural_vector_st :=(others => 1);
Cgen76 : positive_vector_st :=(others => 1)
);
END c01s01b01x01p05n02i00762ent;
ARCHITECTURE c01s01b01x01p05n02i00762arch OF c01s01b01x01p05n02i00762ent IS
constant Vgen1 : boolean := true;
constant Vgen2 : bit := '1';
constant Vgen3 : character := 's';
constant Vgen4 : severity_level := note;
constant Vgen5 : integer := 3;
constant Vgen6 : real := 3.0;
constant Vgen7 : time := 3 ns;
constant Vgen8 : natural := 1;
constant Vgen9 : positive := 1;
constant Vgen70 : boolean_vector_st :=(others => Cgen1);
constant Vgen71 : severity_level_vector_st :=(others => Cgen4);
constant Vgen72 : integer_vector_st :=(others => Cgen5);
constant Vgen73 : real_vector_st :=(others => Cgen6);
constant Vgen74 : time_vector_st :=(others => Cgen7);
constant Vgen75 : natural_vector_st :=(others => Cgen8);
constant Vgen76 : positive_vector_st :=(others => Cgen9);
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***PASSED TEST: c01s01b01x01p05n02i00762"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***FAILED TEST: c01s01b01x01p05n02i00762 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00762arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc367.vhd | 4 | 2020 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc367.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n01i00367ent IS
END c03s02b01x01p03n01i00367ent;
ARCHITECTURE c03s02b01x01p03n01i00367arch OF c03s02b01x01p03n01i00367ent IS
type MVL is ('0', '1', 'Z') ;
type MVL_vector is array (positive range <>) of MVL;
function tristate (X:MVL_vector) return MVL;
subtype tribit is tristate MVL;
type tribit_vector is array (positive range <>) of tribit;
subtype byte is tribit_vector (0 to 7);
subtype half_byte is byte (0 to 3); -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p03n01i00367 - If an index constraint appears after a type mark in a subtype indication, then the type or subtype denoted by the type mark must not already impose an index constraint."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n01i00367arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_coeff_ram.vhd | 4 | 1652 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_coeff_ram is
end entity tb_coeff_ram;
----------------------------------------------------------------
architecture test_abstract of tb_coeff_ram is
use work.coeff_ram_types.all;
signal rd, wr : bit := '0';
signal addr : coeff_ram_address := 0;
signal d_in, d_out : real := 0.0;
begin
dut : entity work.coeff_ram(abstract)
port map ( rd => rd, wr => wr,
addr => addr,
d_in => d_in, d_out => d_out );
stumulus : process is
begin
wait for 100 ns;
addr <= 10; d_in <= 10.0; wait for 10 ns;
wr <= '1'; wait for 10 ns;
d_in <= 20.0; wait for 10 ns;
wr <= '0'; wait for 70 ns;
addr <= 20; wait for 10 ns;
rd <= '1'; wait for 10 ns;
addr <= 10; wait for 10 ns;
rd <= '0'; wait for 10 ns;
wait;
end process stumulus;
end architecture test_abstract;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_07.vhd | 4 | 2458 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_fg_17_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_17_07 is
end entity fg_17_07;
----------------------------------------------------------------
architecture test of fg_17_07 is
signal s : bit_vector(0 to 3);
begin
process is
type value_cell;
type value_ptr is access value_cell;
type value_cell is record
value : bit_vector(0 to 3);
next_cell : value_ptr;
end record value_cell;
variable value_list, current_cell : value_ptr;
variable search_value : bit_vector(0 to 3);
begin
value_list := new value_cell'( B"1000", value_list );
value_list := new value_cell'( B"0010", value_list );
value_list := new value_cell'( B"0000", value_list );
search_value := B"0010";
-- code from book:
current_cell := value_list;
while current_cell /= null
and current_cell.value /= search_value loop
current_cell := current_cell.next_cell;
end loop;
assert current_cell /= null
report "search for value failed";
-- end of code from book
search_value := B"1111";
current_cell := value_list;
while current_cell /= null
and current_cell.value /= search_value loop
current_cell := current_cell.next_cell;
end loop;
assert current_cell /= null
report "search for value failed";
wait;
end process;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1621.vhd | 4 | 1663 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1621.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01621ent IS
begin
return true; -- illegal in entity statement region.
END c08s12b00x00p03n01i01621ent;
ARCHITECTURE c08s12b00x00p03n01i01621arch OF c08s12b00x00p03n01i01621ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01621 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01621arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2232.vhd | 4 | 1757 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2232.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02232ent IS
END c07s02b06x00p01n01i02232ent;
ARCHITECTURE c07s02b06x00p01n01i02232arch OF c07s02b06x00p01n01i02232ent IS
BEGIN
TESTING: PROCESS
type POSITIVE_R is range 0.0 to REAL'HIGH;
variable REALV : REAL;
variable POSRV : POSITIVE_R;
variable k : integer;
BEGIN
k := POSRV mod REALV;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02232 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02232arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3141.vhd | 4 | 2301 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3141.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b02x00p10n01i03141ent_a IS
generic ( g1 : real := 22.0 );
END c05s02b02x00p10n01i03141ent_a;
ARCHITECTURE c05s02b02x00p10n01i03141arch_a OF c05s02b02x00p10n01i03141ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( g1 = 22.0 )
report "***PASSED TEST: c05s02b02x00p10n01i03141"
severity NOTE;
assert ( g1 = 22.0 )
report "***FAILED TEST: c05s02b02x00p10n01i03141 - The formal generics take on implicit OPENs."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b02x00p10n01i03141arch_a;
--
ENTITY c05s02b02x00p10n01i03141ent IS
END c05s02b02x00p10n01i03141ent;
ARCHITECTURE c05s02b02x00p10n01i03141arch OF c05s02b02x00p10n01i03141ent IS
component c05s02b02x00p10n01i03141ent_a
end component;
for comp1 : c05s02b02x00p10n01i03141ent_a use entity work.c05s02b02x00p10n01i03141ent_a(c05s02b02x00p10n01i03141arch_a);
BEGIN
comp1 : c05s02b02x00p10n01i03141ent_a;
END c05s02b02x00p10n01i03141arch;
configuration c05s02b02x00p10n01i03141_cfg of c05s02b02x00p10n01i03141ent is
for c05s02b02x00p10n01i03141arch
end for;
end c05s02b02x00p10n01i03141_cfg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1976.vhd | 4 | 2060 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1976.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p03n01i01976ent IS
END c07s02b01x00p03n01i01976ent;
ARCHITECTURE c07s02b01x00p03n01i01976arch OF c07s02b01x00p03n01i01976ent IS
signal s : integer := 0;
function temp(s:integer) return boolean is
begin
assert FALSE
report "***FAILED TEST: c07s02b01x00p03n01i01976 - The right operand is evaluated only if the value of the left operand is not sufficient to determine the result of the operation."
severity ERROR;
return true;
end;
BEGIN
TESTING: PROCESS
variable x : boolean := false;
BEGIN
if x and (temp(s)) then
NULL;
end if;
wait for 1 ns;
assert FALSE
report "***PASSED TEST: c07s02b01x00p03n01i01976 - This test needs manual check, only when the FAILED TEST assertion do not appear then the test is passed."
severity NOTE;
wait;
END PROCESS TESTING;
END c07s02b01x00p03n01i01976arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd | 4 | 1841 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_08 is
end entity inline_08;
----------------------------------------------------------------
library util; use util.stimulus_generators.all;
architecture test of inline_08 is
constant T_pd : delay_length := 5 ns;
signal a, b : bit := '0';
signal test_inputs : bit_vector(1 to 2);
begin
block_3_f : block is
signal sum, carry : bit;
begin
-- code from book:
half_add : process is
begin
sum <= a xor b after T_pd;
carry <= a and b after T_pd;
wait on a, b;
end process half_add;
-- end of code from book
end block block_3_f;
----------------
block_3_g : block is
signal sum, carry : bit;
begin
-- code from book:
half_add : process (a, b) is
begin
sum <= a xor b after T_pd;
carry <= a and b after T_pd;
end process half_add;
-- end of code from book
end block block_3_g;
----------------
stimulus_3_f_g :
all_possible_values(test_inputs, 20 ns);
(a, b) <= test_inputs;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1455.vhd | 4 | 1703 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1455.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p01n01i01455ent IS
END c08s07b00x00p01n01i01455ent;
ARCHITECTURE c08s07b00x00p01n01i01455arch OF c08s07b00x00p01n01i01455ent IS
begin
TESTING: process
variable i1, i2 : integer := 0;
begin
if 1 then -- failure_here condition not boolean.
i1 := 1;
end if;
assert FALSE
report "***FAILED TEST: c08s07b00x00p01n01i01455 - Expression of IF statement is not of type BOOLEAN"
severity ERROR;
wait;
end process TESTING;
END c08s07b00x00p01n01i01455arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket65/bug2.vhdl | 3 | 433 | entity ent2 is
end entity;
architecture a of ent2 is
begin
main : process is
type enum_t is (value1, value2);
variable var : enum_t;
begin
var := enum_t'rightof(value1); -- Works
var := enum_t'leftof(value2); -- Works
var := enum_t'rightof(var); -- cannot handle IIR_KIND_RIGHTOF_ATTRIBUTE
var := enum_t'leftof(var); -- cannot handle IIR_KIND_LEFTOF_ATTRIBUTE
wait;
end process;
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_structure.vhd | 4 | 1310 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
configuration computer_structure of computer_system is
for structure
for interface_decoder : decoder_2_to_4
use entity work.decoder_3_to_8(basic)
generic map ( Tpd_01 => prop_delay, Tpd_10 => prop_delay )
port map ( s0 => in0, s1 => in1, s2 => '0',
enable => '1',
y0 => out0, y1 => out1, y2 => out2, y3 => out3,
y4 => open, y5 => open, y6 => open, y7 => open );
end for;
-- . . .
end for;
end configuration computer_structure;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1762.vhd | 4 | 3979 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1762.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b02x00p01n01i01762ent IS
END c09s05b02x00p01n01i01762ent;
ARCHITECTURE c09s05b02x00p01n01i01762arch OF c09s05b02x00p01n01i01762ent IS
type t_wlogic is (U, D, Z0, Z1, ZDX, DZX, ZX);
signal count : integer ;
signal ECLK : t_wlogic;
signal ECLK2 : t_wlogic;
signal ECL : integer := 1;
BEGIN
count <= 0 after 0 ns,
1 after 10 ns,
2 after 20 ns,
3 after 30 ns,
4 after 40 ns,
5 after 50 ns,
6 after 60 ns;
----------------------------------------------------------------------
WITH count SELECT
ECLK <= U after 1 ns WHEN 0,
D after 1 ns WHEN 1,
Z0 after 1 ns WHEN 2,
Z1 after 1 ns WHEN 3,
ZDX after 1 ns WHEN 4,
DZX after 1 ns WHEN 5,
ZX after 1 ns WHEN OTHERS;
TESTING: PROCESS(count)
BEGIN
case count is
WHEN 0 => ECLK2 <= U after 1 ns;
WHEN 1 => ECLK2 <= D after 1 ns;
WHEN 2 => ECLK2 <= Z0 after 1 ns;
WHEN 3 => ECLK2 <= Z1 after 1 ns;
WHEN 4 => ECLK2 <= ZDX after 1 ns;
WHEN 5 => ECLK2 <= DZX after 1 ns;
WHEN OTHERS => ECLK2 <= ZX after 1 ns;
end case;
END PROCESS TESTING;
PROCESS(ECLK,ECLK2)
BEGIN
if now = 0 ns then
NULL;
elsif (now = 1 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 11 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 21 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 31 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 41 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 51 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
elsif (now = 61 ns) and (ECLK /= ECLK2) then
assert FALSE
report "FAILED TEST"
severity ERROR;
ECL <= 0;
end if;
END PROCESS;
PROCESS(ECLK,ECLK2)
BEGIN
if (now > 60 ns) and (ECL = 1) then
assert FALSE
report "***PASSED TEST: c09s05b02x00p01n01i01762"
severity NOTE;
elsif (now > 60 ns) and (ECL = 0) then
assert FALSE
report "***FAILED TEST: c09s05b02x00p01n01i01762 - The selected signal assignment represents a process statement in which the signal transform is a case statement."
severity ERROR;
end if;
END PROCESS;
END c09s05b02x00p01n01i01762arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1475.vhd | 4 | 1822 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1475.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p04n01i01475ent IS
END c08s08b00x00p04n01i01475ent;
ARCHITECTURE c08s08b00x00p04n01i01475arch OF c08s08b00x00p04n01i01475ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable i : BIT := '0';
BEGIN
case i is
when '0' => k := 5;
when '1' => NULL;
when others => NULL;
end case;
assert NOT( k = 5 )
report "***PASSED TEST: c08s08b00x00p04n01i01475"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c08s08b00x00p04n01i01475 - expression of integer type"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p04n01i01475arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc679.vhd | 4 | 2126 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc679.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:00 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00679ent IS
END c03s04b01x00p23n01i00679ent;
ARCHITECTURE c03s04b01x00p23n01i00679arch OF c03s04b01x00p23n01i00679ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of INTEGER;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.08";
-- Declare a variable.
constant CON : INTEGER := 1;
variable VAR : INTEGER := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00679 - The output file will tested by test file s010412.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00679arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_03.vhd | 4 | 902 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity and_or_inv is
port ( a1, a2, b1, b2 : in bit := '1';
y : out bit );
end entity and_or_inv;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1514.vhd | 4 | 1772 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1514.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p02n01i01514ent IS
END c08s09b00x00p02n01i01514ent;
ARCHITECTURE c08s09b00x00p02n01i01514arch OF c08s09b00x00p02n01i01514ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for i in 1 to 5 loop
k := k + 1;
end loop;
assert NOT( k = 5 )
report "***PASSED TEST: c08s09b00x00p02n01i01514"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c08s09b00x00p02n01i01514 - Missing reserved word 'end loop' in a loop statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p02n01i01514arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc415.vhd | 4 | 3149 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc415.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00415ent IS
END c03s02b01x01p19n01i00415ent;
ARCHITECTURE c03s02b01x01p19n01i00415arch OF c03s02b01x01p19n01i00415ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
constant C1 : boolean_cons_vector := (others => true);
function complex_scalar(s : boolean_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return boolean_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : boolean_cons_vector;
signal S2 : boolean_cons_vector;
signal S3 : boolean_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00415"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00415 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00415arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug17202/test.vhdl | 3 | 128 | entity test_val is end test_val;
architecture test of test_val is
signal t : time := time'value("123 fs");
begin
end test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1855.vhd | 4 | 1736 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1855.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01855ent IS
END c07s01b00x00p08n01i01855ent;
ARCHITECTURE c07s01b00x00p08n01i01855arch OF c07s01b00x00p08n01i01855ent IS
signal sma_int : integer;
BEGIN
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01855 - Process labels are not permitted as primaries in a block guard expression."
severity ERROR;
wait;
END PROCESS TESTING;
b: block ( sma_int = TESTING ) -- process label illegal here
begin
end block b;
END c07s01b00x00p08n01i01855arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc919.vhd | 4 | 2367 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc919.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c10s03b00x00p14n01i00919ent_a is
generic ( x : integer; y : real );
end c10s03b00x00p14n01i00919ent_a;
architecture c10s03b00x00p14n01i00919arch_a of c10s03b00x00p14n01i00919ent_a is
begin
TESTING:PROCESS
BEGIN
assert NOT( real(x) = y )
report "***PASSED TEST: c10s03b00x00p14n01i00919"
severity NOTE;
assert ( real(x) = y )
report "***FAILED TEST: c10s03b00x00p14n01i00919 - The named associated local generics can be made visible by selection."
severity ERROR;
wait;
END PROCESS TESTING;
end c10s03b00x00p14n01i00919arch_a;
ENTITY c10s03b00x00p14n01i00919ent IS
END c10s03b00x00p14n01i00919ent;
ARCHITECTURE c10s03b00x00p14n01i00919arch OF c10s03b00x00p14n01i00919ent IS
component d
generic ( a : integer; b : real );
end component;
BEGIN
instance : d generic map (a => 10, b => 10.0);
END c10s03b00x00p14n01i00919arch;
configuration c10s03b00x00p14n01i00919cfg of c10s03b00x00p14n01i00919ent is
for c10s03b00x00p14n01i00919arch
for instance : d
use entity work.c10s03b00x00p14n01i00919ent_a(c10s03b00x00p14n01i00919arch_a) generic map ( x => a, y => b);
end for;
end for;
end c10s03b00x00p14n01i00919cfg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc511.vhd | 4 | 1833 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc511.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p06n03i00511ent IS
END c03s02b02x00p06n03i00511ent;
ARCHITECTURE c03s02b02x00p06n03i00511arch OF c03s02b02x00p06n03i00511ent IS
type R1 is record
RE1: I1;
RE2: RE1; -- Failure_here
-- ERROR - SEMANTIC ERROR: NAME OF RECORD ELEMENT CANNOT BE USED
-- WITHIN THE RECORD TYPE DEFINITION
end record;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b02x00p06n03i00511 - Name of record element cannot be used in the record type definition."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p06n03i00511arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_11.vhd | 4 | 1962 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_ch_20_11.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_20_11 is
end entity ch_20_11;
----------------------------------------------------------------
architecture test of ch_20_11 is
component comp is
end component comp;
signal clk_phase1, clk_phase2 : bit;
-- code from book:
group signal_pair is (signal, signal);
group clock_pair : signal_pair ( clk_phase1, clk_phase2 );
attribute max_skew : time;
attribute max_skew of clock_pair : group is 200 ps;
group component_instances is ( label <> );
group U1 : component_instances ( nand1, nand2, nand3 );
group U2 : component_instances ( inv1, inv2 );
attribute IC_allocation : string;
attribute IC_allocation of U1 : group is "74LS00";
attribute IC_allocation of U2 : group is "74LS04";
-- end of code from book
begin
nand1 : component comp;
nand2 : component comp;
nand3 : component comp;
inv1 : component comp;
inv2 : component comp;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2769.vhd | 4 | 1926 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2769.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p09n01i02769ent IS
END c13s07b00x00p09n01i02769ent;
ARCHITECTURE c13s07b00x00p09n01i02769arch OF c13s07b00x00p09n01i02769ent IS
constant aaa : bit_vector := B"101101";
constant bbb : bit_vector := O"777";
constant ccc : bit_vector := X"FFFF";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( aaa'length = 6 and bbb'length = 9 and ccc'length = 16 )
report "***PASSED TEST: c13s07b00x00p09n01i02769"
severity NOTE;
assert ( aaa'length = 6 and bbb'length = 9 and ccc'length = 16 )
report "***FAILED TEST: c13s07b00x00p09n01i02769 - The length of a bit string literal is the length of its string literal value."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p09n01i02769arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket35/utf8.vhdl | 3 | 66 | -- This is utf-8 encoding, with a BOM.
package p1 is
end p1;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1739.vhd | 4 | 1959 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1739.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s04b00x00p10n01i01739ent IS
begin
assert false
report "Success:entity assertion with static expression"
severity NOTE;
END c09s04b00x00p10n01i01739ent;
ARCHITECTURE c09s04b00x00p10n01i01739arch OF c09s04b00x00p10n01i01739ent IS
BEGIN
assert false
report "Success:architecture assertion with static expression"
severity NOTE;
b: block
begin
assert false
report "Success:architecture in block: assertion with static expression"
severity NOTE;
end block b;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c09s04b00x00p10n01i01739 - This test need manual check, three assertion notes of Success should appear."
severity NOTE;
wait;
END PROCESS TESTING;
END c09s04b00x00p10n01i01739arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc45.vhd | 4 | 3398 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc45.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p02n01i00045ent IS
END c04s03b01x01p02n01i00045ent;
ARCHITECTURE c04s03b01x01p02n01i00045arch OF c04s03b01x01p02n01i00045ent IS
type T1_0 is array (integer range <>) of integer;
subtype T1_1 is T1_0 (1 to 2);
subtype T1_2 is T1_0 (1 to 4);
type T2_0 is array (integer range <>) of T1_2;
subtype T2_1 is T2_0 (1 to 2);
subtype T2_2 is T2_0 (1 to 4);
-- Create some constants for constructing the real tests...
constant C1 : T1_1 := (1, 2);
constant C2 : T1_1 := C1;
constant C3 : T1_2 := (1, 2, 3, 4);
constant C4 : T1_2 := C3;
-- Success_here : on all constant declarations below
constant C5 : T2_1 := ((1, 2, 3, 4), (5, 6, 7, 8));
constant C6 : T2_1 := (C3, C4);
constant C7 : T2_1 := (C1 & C2, C2 & C1);
constant C8 : T2_1 := (1 & 2 & C2, C3);
constant C10: T2_2 := ((1, 2, 3, 4), (5, 6, 7, 8),
(9, 0, 1, 2), (3, 4, 5, 6));
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( C1 = (1,2) and
C2 = (1,2) and
C3 = (1,2,3,4) and
C4 = (1,2,3,4) and
C5 = ((1, 2, 3, 4), (5, 6, 7, 8)) and
C6 = ((1, 2, 3, 4), (1, 2, 3, 4)) and
C7 = ((1, 2, 1, 2), (1, 2, 1, 2)) and
C8 = ((1, 2, 1, 2), (1, 2, 3, 4)) and
C10= ( (1, 2, 3, 4), (5, 6, 7, 8),
(9, 0, 1, 2), (3, 4, 5, 6)) )
report "***PASSED TEST: c04s03b01x01p02n01i00045"
severity NOTE;
assert ( C1 = (1,2) and
C2 = (1,2) and
C3 = (1,2,3,4) and
C4 = (1,2,3,4) and
C5 = ((1, 2, 3, 4), (5, 6, 7, 8)) and
C6 = ((1, 2, 3, 4), (1, 2, 3, 4)) and
C7 = ((1, 2, 1, 2), (1, 2, 1, 2)) and
C8 = ((1, 2, 1, 2), (1, 2, 3, 4)) and
C10= ( (1, 2, 3, 4), (5, 6, 7, 8),
(9, 0, 1, 2), (3, 4, 5, 6)) )
report "***FAILED TEST: c04s03b01x01p02n01i00045 - Syntactic error in constant declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p02n01i00045arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug16/repro.vhdl | 3 | 416 | entity repro is
end repro;
architecture behav of repro is
component comp is
port (s : bit);
end component;
signal s : bit;
begin
c : comp port map (s);
end behav;
entity comp is
port (s : bit);
end comp;
configuration conf of repro is
for behav
for c : comp
use entity work.compx (behav);
end for;
end for;
end conf;
architecture behav of comp is
begin
assert s = '1';
end behav;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/string_array_write.vhd | 4 | 1777 |
-- Copyright (C) Clifton Labs. All rights reserved.
-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. CLIFTON LABS SHALL NOT BE
-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the GNU General Public License as published
-- by the Free Software Foundation; version 2 of the License.
-- You should have received a copy of the GNU General Public License along
-- with this software; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity string_array_write is
end string_array_write;
architecture test0 of string_array_write is
subtype str16 is string (1 to 16);
type string_table is array (natural range <>) of str16;
constant string_array : string_table :=
( "This is string 1"
,"__Hello World__"
,"This is string 3"
,"_Bird is a word_"
,"_Goodbye (ciao)_"
);
type string_array_file is file of string_table;
begin
doit: process
file fileout : string_array_file open write_mode is "string_array_write.out";
begin
write(fileout,string_array);
assert false
report "PASSED TEST: string_array_write."
severity note;
wait;
end process;
end test0;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bv.vhd | 4 | 4306 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mact-bv.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture bench_verify of mac_test is
signal clk, clr, behavioral_ovf, rtl_ovf : std_ulogic := '0';
signal x_real, x_imag,
y_real, y_imag,
behavioral_s_real, behavioral_s_imag,
rtl_s_real, rtl_s_imag : std_ulogic_vector(15 downto 0);
type complex is record
re, im : real;
end record;
signal x, y, behavioral_s, rtl_s : complex := (0.0, 0.0);
constant Tpw_clk : time := 50 ns;
begin
x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
dut_behavioral : entity work.mac(behavioral)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag,
behavioral_s_real, behavioral_s_imag, behavioral_ovf );
dut_rtl : entity work.mac(rtl)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag,
rtl_s_real, rtl_s_imag, rtl_ovf );
behavioral_s_real_converter :
entity work.to_fp(behavioral) port map (behavioral_s_real, behavioral_s.re);
behavioral_s_imag_converter :
entity work.to_fp(behavioral) port map (behavioral_s_imag, behavioral_s.im);
rtl_s_real_converter :
entity work.to_fp(behavioral) port map (rtl_s_real, rtl_s.re);
rtl_s_imag_converter :
entity work.to_fp(behavioral) port map (rtl_s_imag, rtl_s.im);
clock_gen : process is
begin
clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
wait for 2 * Tpw_clk;
end process clock_gen;
stimulus : process is
begin
-- first sequence
clr <= '1'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (+0.2, +0.2); y <= (+0.2, +0.2); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
-- should be (0.4, 0.58) when it falls out the other end
clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (-0.5, +0.5); y <= (-0.5, +0.5); clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '1'; wait until clk = '0';
wait;
end process stimulus;
verifier : process
constant epsilon : real := 4.0E-5; -- 1-bit error in 15-bit mantissa
begin
wait until clk = '0';
assert behavioral_ovf = rtl_ovf
report "Overflow flags differ" severity error;
if behavioral_ovf = '0' and rtl_ovf = '0' then
assert abs (behavioral_s.re - rtl_s.re) < epsilon
report "Real sums differ" severity error;
assert abs (behavioral_s.im - rtl_s.im) < epsilon
report "Imag sums differ" severity error;
end if;
end process verifier;
end architecture bench_verify;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1594.vhd | 4 | 1779 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1594.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01594ent IS
END c08s11b00x00p03n01i01594ent;
ARCHITECTURE c08s11b00x00p03n01i01594arch OF c08s11b00x00p03n01i01594ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for i in 1 to 10 loop
k := i;
exit;
end loop;
assert NOT(k = 1)
report "***PASSED TEST: c08s11b00x00p03n01i01594"
severity NOTE;
assert (k = 1)
report "***FAILED TEST: c08s11b00x00p03n01i01594 - A exit statement inside a FOR loop without a loop label"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01594arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2507.vhd | 4 | 1798 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2507.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b04x00p03n01i02507ent IS
END c07s03b04x00p03n01i02507ent;
ARCHITECTURE c07s03b04x00p03n01i02507arch OF c07s03b04x00p03n01i02507ent IS
BEGIN
TESTING: PROCESS
function F1 ( PARAM : bit ) return boolean is
begin
return boolean'(PARAM); -- Failure_here
-- SEMANTIC ERROR: type of expression does not match type mark.
end F1;
variable k : boolean;
BEGIN
k := F1('1');
assert FALSE
report "***FAILED TEST: c07s03b04x00p03n01i02507 - Expression type does not match type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b04x00p03n01i02507arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2061.vhd | 4 | 1869 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2061.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02061ent IS
END c07s02b04x00p01n02i02061ent;
ARCHITECTURE c07s02b04x00p01n02i02061arch OF c07s02b04x00p01n02i02061ent IS
signal S1 : Integer;
signal S2 : Integer;
signal S3 : BIT_VECTOR(0 to 7);
BEGIN
TESTING: PROCESS
variable V1,V2 : Integer := 10;
variable V3,V4 : BIT_VECTOR(0 to 3) := "0101" ;
BEGIN
S1 <= V1 + V2;
wait for 1 ns;
assert NOT(S1 = 20)
report "***PASSED TEST: c07s02b04x00p01n02i02061"
severity NOTE;
assert (S1 = 20)
report "***FAILED TEST: c07s02b04x00p01n02i02061 - Operands must be of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02061arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2399.vhd | 4 | 1975 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2399.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n01i02399ent IS
END c07s03b02x00p08n01i02399ent;
ARCHITECTURE c07s03b02x00p08n01i02399arch OF c07s03b02x00p08n01i02399ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_2 : real;
ele_3 : boolean;
end record;
variable v23 : rec;
BEGIN
v23 := (ele_2 => 2.3, ele_3 => True); -- No_failure_here
assert NOT((v23.ele_2=2.3) and (v23.ele_3=TRUE))
report "***PASSED TEST: c07s03b02x00p08n01i02399"
severity NOTE;
assert ((v23.ele_2=2.3) and (v23.ele_3=TRUE))
report "***FAILED TEST: c07s03b02x00p08n01i02399 - Element associations by an element simple name is allowed only in record aggregates."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n01i02399arch;
| gpl-2.0 |
123gmax/Digital-Lab | AES128/building_blocks/invShiftRows.vhd | 2 | 2424 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/15/2015 03:27:35 PM
-- Design Name:
-- Module Name: invShiftRows - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity invShiftRows is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
blockIn : in STD_LOGIC_VECTOR (127 downto 0);
blockOut : out STD_LOGIC_VECTOR (127 downto 0));
end invShiftRows;
architecture Behavioral of invShiftRows is
begin
process(CLK, RESET, blockIn)
begin
if RESET = '1' then
blockOut <= (others => '0');
elsif rising_edge(CLK) then
blockOut(127 downto 120) <= blockIn(127 downto 120); --Block[0] = Block[0]
blockOut(119 downto 112) <= blockIn(23 downto 16); --Block[1] = Block[13]
blockOut(111 downto 104) <= blockIn(47 downto 40); --Block[2] = Block[10]
blockOut(103 downto 96) <= blockIn(71 downto 64); --Block[3] = Block[7]
blockOut(95 downto 88) <= blockIn(95 downto 88); --Block[4] = Block[4]
blockOut(87 downto 80) <= blockIn(119 downto 112); --Block[5] = Block[1]
blockOut(79 downto 72) <= blockIn(15 downto 8); --Block[6] = Block[14]
blockOut(71 downto 64) <= blockIn(39 downto 32); --Block[7] = Block[11]
blockOut(63 downto 56) <= blockIn(63 downto 56); --Block[8] = Block[8]
blockOut(55 downto 48) <= blockIn(87 downto 80); --Block[9] = Block[5]
blockOut(47 downto 40) <= blockIn(111 downto 104); --Block[10] = Block[2]
blockOut(39 downto 32) <= blockIn(7 downto 0); --Block[11] = Block[15]
blockOut(31 downto 24) <= blockIn(31 downto 24); --Block[12] = Block[12]
blockOut(23 downto 16) <= blockIn(55 downto 48); --Block[13] = Block[9]
blockOut(15 downto 8) <= blockIn(79 downto 72); --Block[14] = Block[6]
blockOut(7 downto 0) <= blockIn(103 downto 96); --Block[15] = Block[3]
end if;
end process;
end Behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc869.vhd | 4 | 12336 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc869.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00869pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
subtype dumy is integer range 0 to 3;
signal Sin1 : bit_vector(0 to 5) ;
signal Sin2 : boolean_vector(0 to 5) ;
signal Sin4 : severity_level_vector(0 to 5) ;
signal Sin5 : integer_vector(0 to 5) ;
signal Sin6 : real_vector(0 to 5) ;
signal Sin7 : time_vector(0 to 5) ;
signal Sin8 : natural_vector(0 to 5) ;
signal Sin9 : positive_vector(0 to 5) ;
signal Sin10: array_rec_std(0 to 5) ;
end c01s03b01x00p12n01i00869pkg;
use work.c01s03b01x00p12n01i00869pkg.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00869pkg.all;
entity test1 is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test1 of test1 is
begin
sigout1 <= false;
sigout2 <= '0';
sigout4 <= error;
sigout5 <= 6;
sigout6 <= 6.0;
sigout7 <= 6 ns;
sigout8 <= 6;
sigout9 <= 6;
sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
end;
configuration test1bench of test1 is
for test1
end for;
end;
use work.c01s03b01x00p12n01i00869pkg.all;
ENTITY c01s03b01x00p12n01i00869ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15);
port(
dumy : inout bit_vector(zero to three));
END c01s03b01x00p12n01i00869ent;
ARCHITECTURE c01s03b01x00p12n01i00869arch OF c01s03b01x00p12n01i00869ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test1
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test1
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
variable dumb : bit_vector(zero to three);
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(4) and
Sin2(0) = Sin2(4) and
Sin4(0) = Sin4(4) and
Sin5(0) = Sin5(4) and
Sin6(0) = Sin6(4) and
Sin7(0) = Sin7(4) and
Sin8(0) = Sin8(4) and
Sin9(0) = Sin9(4) and
Sin10(0)= Sin10(4) and
Sin1(5) = '0' and
Sin2(5) = FALSE and
Sin4(5) = error and
Sin5(5) = 6 and
Sin6(5) = 6.0 and
Sin7(5) = 6 ns and
Sin8(5) = 6 and
Sin9(5) = 6 and
Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
report "***PASSED TEST: c01s03b01x00p12n01i00869"
severity NOTE;
assert ( Sin1(0) = sin1(4) and
Sin2(0) = Sin2(4) and
Sin4(0) = Sin4(4) and
Sin5(0) = Sin5(4) and
Sin6(0) = Sin6(4) and
Sin7(0) = Sin7(4) and
Sin8(0) = Sin8(4) and
Sin9(0) = Sin9(4) and
Sin10(0)= Sin10(4) and
Sin1(5) = '0' and
Sin2(5) = FALSE and
Sin4(5) = error and
Sin5(5) = 6 and
Sin6(5) = 6.0 and
Sin7(5) = 6 ns and
Sin8(5) = 6 and
Sin9(5) = 6 and
Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
report "***FAILED TEST: c01s03b01x00p12n01i00869 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00869arch;
configuration c01s03b01x00p12n01i00869cfg of c01s03b01x00p12n01i00869ent is
for c01s03b01x00p12n01i00869arch
for K
for all:test1 use configuration work.test1bench;
end for;
for G(0 to 3)
for T1 :test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_04.vhd | 4 | 835 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity top_level is
end entity top_level;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_08a.vhd | 4 | 1680 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_08a is
end entity inline_08a;
architecture test of inline_08a is
-- code from book
terminal bias_node : electrical;
--
subnature accurate_electrical is electrical
tolerance "accurate_voltage" across "accurate_current" through;
--
terminal n1, n2 : accurate_electrical;
--
quantity n1_n2_voltage across n1_n2_current through n1 to n2;
--
quantity internal_voltage : voltage tolerance n1_n2_voltage'tolerance;
quantity internal_current : current tolerance n1_n2_current'tolerance;
--
terminal bus_a_end, bus_b_end : electrical_vector(15 downto 0);
quantity bus_currents through bus_a_end to bus_b_end;
-- end code from book
begin
-- code from book
bias_node'reference == 0.5;
-- end code from book
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alu-b.vhd | 4 | 2669 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_10_alu-b.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture behavior of alu is
begin
alu_op: process (s1, s2, func) is
constant Tpd : delay_length := 10 ns;
variable bv_s1 : bit_vector(s1'range) := To_bitvector(s1);
variable bv_s2 : bit_vector(s2'range) := To_bitvector(s2);
variable temp_result : bit_vector(result'range);
constant zero_result : bit_vector(result'range) := (others => '0');
variable temp_overflow : boolean;
type boolean_to_X01_table is array (boolean) of X01;
constant boolean_to_X01 : boolean_to_X01_table
:= ( false => '0', true => '1' );
begin
case func is
when alu_add =>
bv_add(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_addu =>
bv_addu(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_sub =>
bv_sub(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_subu =>
bv_subu(bv_s1, bv_s2, temp_result, temp_overflow);
when others =>
report "alu: illegal function code" severity error;
temp_result := X"0000_0000";
end case;
result <= To_X01(temp_result) after Tpd;
zero <= boolean_to_X01(temp_result = zero_result) after Tpd;
negative <= To_X01(temp_result(temp_result'left)) after Tpd;
overflow <= boolean_to_X01(temp_overflow) after Tpd;
end process alu_op;
end architecture behavior;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3068.vhd | 4 | 4087 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3068.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03068pkg is
type severity_level_cons_vector is array (15 downto 0) of severity_level;
constant C19 : severity_level_cons_vector := (others => note);
end c12s06b02x00p06n01i03068pkg;
use work.c12s06b02x00p06n01i03068pkg.all;
ENTITY c12s06b02x00p06n01i03068ent_a IS
PORT
(
F1: OUT integer ;
F3: IN severity_level_cons_vector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03068ent_a;
ARCHITECTURE c12s06b02x00p06n01i03068arch_a OF c12s06b02x00p06n01i03068ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03068arch_a;
use work.c12s06b02x00p06n01i03068pkg.all;
ENTITY c12s06b02x00p06n01i03068ent IS
END c12s06b02x00p06n01i03068ent;
ARCHITECTURE c12s06b02x00p06n01i03068arch OF c12s06b02x00p06n01i03068ent IS
function scalar_complex(s : integer) return severity_level_cons_vector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN severity_level_cons_vector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03068ent_a(c12s06b02x00p06n01i03068arch_a);
signal S1 : severity_level_cons_vector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03068"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03068 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03068arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc405.vhd | 4 | 2229 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc405.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p19n01i00405ent IS
END c03s02b01x01p19n01i00405ent;
ARCHITECTURE c03s02b01x01p19n01i00405arch OF c03s02b01x01p19n01i00405ent IS
type MEM is array (positive range <>) of BIT;
type ME1 is array (positive range <>) of Integer;
subtype ME2 is ME1(1 to 3);
subtype M1 is MEM (1 to 5);
function WR_OR(Input : ME1) return M1 is
begin
for I in Input'Range loop
if Input(I) = 2 then
return "11111" ;
end if;
end loop;
end WR_OR;
procedure F2 (X1 : in MEM; WR_OR: out M1) is
begin
end F2;
BEGIN
TESTING: PROCESS
variable V1 :ME2 := (20, 30, 40, 50);
BEGIN
F2(WR_OR(V1),WR_OR(V1)) ; -- failure_here
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c03s02b01x01p19n01i00405 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00405arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/slices/slice-lvalue.vhdl | 4 | 353 | entity test is
end test;
architecture only of test is
begin -- only
doit: process
variable string_var : string( 1 to 6 );
begin -- process
string_var( 1 to 3 ) := "foo";
string_var( 4 to 6 ) := "bar";
assert string_var = "foobar" report "TEST FAILED" severity FAILURE;
report "TEST PASSED";
wait;
end process;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket89/project/src93/bfm_common_pkg.vhd | 3 | 18983 | --========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : bfm_common_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.methods_pkg.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.std_logic_1164_additions.all;
use ieee_proposed.standard_textio_additions.all;
package bfm_common_pkg is
-- General declarations related to BFMs
type t_normalization_mode is (ALLOW_WIDER, ALLOW_NARROWER, ALLOW_WIDER_NARROWER, ALLOW_EXACT_ONLY);
-- Functions/procedures
impure function normalise(
constant value : in std_logic_vector;
constant target : in std_logic_vector;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "slv"
) return std_logic_vector;
impure function normalise(
constant value : in unsigned;
constant target : in unsigned;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "unsigned"
) return unsigned;
impure function normalise(
constant value : in signed;
constant target : in signed;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "signed"
) return signed;
-- Functions/procedures
impure function normalize_and_check(
constant value : in std_logic_vector;
constant target : in std_logic_vector;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "slv"
) return std_logic_vector;
impure function normalize_and_check(
constant value : in unsigned;
constant target : in unsigned;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "unsigned"
) return unsigned;
impure function normalize_and_check(
constant value : in signed;
constant target : in signed;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "signed"
) return signed;
procedure wait_until_given_time_after_rising_edge (
signal clk : in std_logic;
constant wait_time : in time
);
end package bfm_common_pkg;
--=================================================================================================
package body bfm_common_pkg is
constant C_SCOPE : string := "bfm_common";
-- Normalize 'value' to the width given by 'target' and perform sanity check.
impure function normalize_and_check(
constant value : in std_logic_vector;
constant target : in std_logic_vector;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "slv"
) return std_logic_vector is
constant name : string := "normalize_and_check(" & val_type & ": " &
value_name & "=" & to_string(value, HEX, AS_IS) & ", " &
target_name & "=" & to_string(target, HEX, AS_IS) & ")";
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_target : std_logic_vector(target'length - 1 downto 0) is target;
variable v_normalized_value : std_logic_vector(target'length - 1 downto 0);
begin
-- Verify that value and target are not zero-length vectors
if value'length = 0 then
tb_error(name & " => Value length is zero! " & msg, C_SCOPE);
return v_normalized_value;
elsif target'length = 0 then
tb_error(name & " => Target length is zero! " & msg, C_SCOPE);
return v_normalized_value;
end if;
-- If value'length > target'length, remove leading zeros from value
if (a_value'length > a_target'length) then
v_normalized_value := a_value(a_target'length - 1 downto 0);
-- Sanity checks
if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE);
end if;
if not matching_widths(a_value, a_target) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE);
end if;
-- If value'length = target'length
elsif (a_value'length = a_target'length) then
v_normalized_value := a_value;
-- If value'length < target'length, add padding (leading zeros) to value
elsif (a_value'length < a_target'length) then
v_normalized_value := (others => '0');
v_normalized_value(a_value'length - 1 downto 0) := a_value;
-- Sanity check
if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE);
end if;
end if;
return v_normalized_value;
end;
impure function normalize_and_check(
constant value : in unsigned;
constant target : in unsigned;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "unsigned"
) return unsigned is
begin
return unsigned( normalize_and_check(std_logic_vector(value), std_logic_vector(target), mode, value_name, target_name, msg, val_type) );
end;
impure function normalize_and_check(
constant value : in signed;
constant target : in signed;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "signed"
) return signed is
constant name : string := "normalize_and_check(" & val_type & ": " &
value_name & "=" & to_string(std_logic_vector(value)) & ", " &
target_name & "=" & to_string(std_logic_vector(target)) & ")";
alias a_value : signed(value'length - 1 downto 0) is value;
alias a_target : signed(target'length - 1 downto 0) is target;
variable v_normalized_value : signed(target'length - 1 downto 0);
begin
-- Verify that value and target are not zero-length vectors
if value'length = 0 then
tb_error(name & " => Value length is zero! " & msg, C_SCOPE);
return v_normalized_value;
elsif target'length = 0 then
tb_error(name & " => Target length is zero! " & msg, C_SCOPE);
return v_normalized_value;
end if;
-- If value'length > target'length, remove leading zeros/ones from value
if a_value'length > a_target'length then
v_normalized_value := a_value(a_target'length - 1 downto 0);
-- Sanity checks
if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE);
end if;
if a_value(a_value'high) = '0' then -- positive value
if not matching_widths(a_value, a_target) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE);
end if;
elsif a_value(a_value'high) = '1' then -- negative value
for i in a_value'high downto a_target'length loop
if a_value(i) = '0' then
tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-sign bits in the extended MSB. " & msg, C_SCOPE);
end if;
end loop;
end if;
-- If value'length = target'length
elsif a_value'length = a_target'length then
v_normalized_value := a_value;
-- If value'length < target'length, add padding (leading zeros/ones) to value
elsif a_value'length < a_target'length then
if a_value(a_value'high) = '0' then -- positive value
v_normalized_value := (others => '0');
elsif a_value(a_value'high) = '1' then -- negative value
v_normalized_value := (others => '1');
end if;
v_normalized_value(a_value'length - 1 downto 0) := a_value;
-- Sanity check
if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE);
end if;
end if;
return v_normalized_value;
end;
-- Normalise 'value' to the width given by 'target'.
impure function normalise(
constant value : in std_logic_vector;
constant target : in std_logic_vector;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "slv"
) return std_logic_vector is
constant name : string := "normalise(" & val_type & ": " &
value_name & "=" & to_string(value, HEX, AS_IS) & ", " &
target_name & "=" & to_string(target, HEX, AS_IS) & ")";
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_target : std_logic_vector(target'length - 1 downto 0) is target;
variable v_normalised_value : std_logic_vector(target'length - 1 downto 0);
begin
deprecate(get_procedure_name_from_instance_name(value'instance_name), "Use normalize_and_check().");
-- Verify that value and target are not zero-length vectors
if value'length = 0 then
tb_error(name & " => Value length is zero! " & msg, C_SCOPE);
return v_normalised_value;
elsif target'length = 0 then
tb_error(name & " => Target length is zero! " & msg, C_SCOPE);
return v_normalised_value;
end if;
-- If value'length > target'length, remove leading zeros from value
if (a_value'length > a_target'length) then
v_normalised_value := a_value(a_target'length - 1 downto 0);
-- Sanity checks
if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE);
end if;
if not matching_widths(a_value, a_target) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE);
end if;
-- If value'length = target'length
elsif (a_value'length = a_target'length) then
v_normalised_value := a_value;
-- If value'length < target'length, add padding (leading zeros) to value
elsif (a_value'length < a_target'length) then
v_normalised_value := (others => '0');
v_normalised_value(a_value'length - 1 downto 0) := a_value;
-- Sanity check
if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE);
end if;
end if;
return v_normalised_value;
end;
impure function normalise(
constant value : in unsigned;
constant target : in unsigned;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "unsigned"
) return unsigned is
begin
return unsigned( normalise(std_logic_vector(value), std_logic_vector(target), mode, value_name, target_name, msg, val_type) );
end;
impure function normalise(
constant value : in signed;
constant target : in signed;
constant mode : in t_normalization_mode;
constant value_name : string;
constant target_name : string;
constant msg : string;
constant val_type : string := "signed"
) return signed is
constant name : string := "normalise(" & val_type & ": " &
value_name & "=" & to_string(std_logic_vector(value)) & ", " &
target_name & "=" & to_string(std_logic_vector(target)) & ")";
alias a_value : signed(value'length - 1 downto 0) is value;
alias a_target : signed(target'length - 1 downto 0) is target;
variable v_normalised_value : signed(target'length - 1 downto 0);
begin
deprecate(get_procedure_name_from_instance_name(value'instance_name), "Use normalize_and_check().");
-- Verify that value and target are not zero-length vectors
if value'length = 0 then
tb_error(name & " => Value length is zero! " & msg, C_SCOPE);
return v_normalised_value;
elsif target'length = 0 then
tb_error(name & " => Target length is zero! " & msg, C_SCOPE);
return v_normalised_value;
end if;
-- If value'length > target'length, remove leading zeros/ones from value
if a_value'length > a_target'length then
v_normalised_value := a_value(a_target'length - 1 downto 0);
-- Sanity checks
if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE);
end if;
if a_value(a_value'high) = '0' then -- positive value
if not matching_widths(a_value, a_target) then
tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE);
end if;
elsif a_value(a_value'high) = '1' then -- negative value
for i in a_value'high downto a_target'length loop
if a_value(i) = '0' then
tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-sign bits in the extended MSB. " & msg, C_SCOPE);
end if;
end loop;
end if;
-- If value'length = target'length
elsif a_value'length = a_target'length then
v_normalised_value := a_value;
-- If value'length < target'length, add padding (leading zeros/ones) to value
elsif a_value'length < a_target'length then
if a_value(a_value'high) = '0' then -- positive value
v_normalised_value := (others => '0');
elsif a_value(a_value'high) = '1' then -- negative value
v_normalised_value := (others => '1');
end if;
v_normalised_value(a_value'length - 1 downto 0) := a_value;
-- Sanity check
if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then
tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE);
end if;
end if;
return v_normalised_value;
end;
-- Wait until wait_time after rising_edge(clk)
procedure wait_until_given_time_after_rising_edge (
signal clk : in std_logic;
constant wait_time : in time
) is
variable v_remaining_wait_time : time;
begin
-- If the time since the previous rising_edge is less than wait_time,
-- we don't have to wait until the next rising_edge,
-- only wait_time minus the time already passed since rising_edge
if (clk'last_event <= wait_time and -- less than wait_time has passed since last event
clk'last_value = '0' and clk = '1' -- last event was a rising_edge
) then
v_remaining_wait_time := wait_time - clk'last_event; -- Wait until wait_time after rising_edge
else
wait until rising_edge(clk);
v_remaining_wait_time := wait_time; -- Wait until wait_time after rising_edge
end if;
wait for v_remaining_wait_time;
end;
end package body bfm_common_pkg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/simple-procedure-call.vhdl | 4 | 257 | entity test is
end test;
architecture only of test is
procedure doit is
begin
report "PROCEDURE CALLED!";
end procedure;
begin -- only
process
begin -- process doit
doit;
report "TEST PASSED";
wait;
end process;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_18.vhd | 4 | 2398 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_18 is
end entity inline_18;
----------------------------------------------------------------
architecture test of inline_18 is
begin
process_5_a : process is
constant initial_value : natural := 10;
constant max_value : natural := 8;
constant current_character : character := 'A';
constant input_string : string := "012ABC";
constant free_memory : natural := 0;
constant low_water_limit : natural := 1024;
constant packet_length : natural := 0;
constant clock_pulse_width : delay_length := 10 ns;
constant min_clock_width : delay_length := 20 ns;
constant last_position : natural := 10;
constant first_position : natural := 5;
constant number_of_entries : natural := 0;
begin
-- code from book:
assert initial_value <= max_value;
--
assert initial_value <= max_value
report "initial value too large";
--
assert current_character >= '0' and current_character <= '9'
report "Input number " & input_string & " contains a non-digit";
--
assert free_memory >= low_water_limit
report "low on memory, about to start garbage collect"
severity note;
--
assert packet_length /= 0
report "empty network packet received"
severity warning;
--
assert clock_pulse_width >= min_clock_width
severity error;
--
assert (last_position - first_position + 1) = number_of_entries
report "inconsistency in buffer model"
severity failure;
-- end of code from book
wait;
end process process_5_a;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2871.vhd | 4 | 1592 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2871.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p03n01i02871ent IS
END c02s01b00x00p03n01i02871ent;
ARCHITECTURE c02s01b00x00p03n01i02871arch OF c02s01b00x00p03n01i02871ent IS
function testp (I1:Bit) return; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b00x00p03n01i02871 - Missing type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p03n01i02871arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1075.vhd | 4 | 2265 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1075.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01075ent IS
END c06s04b00x00p03n02i01075ent;
ARCHITECTURE c06s04b00x00p03n02i01075arch OF c06s04b00x00p03n02i01075ent IS
BEGIN
TESTING: PROCESS
type CSTRING is array (CHARACTER range <>) of CHARACTER;
constant C1 : CSTRING('A' to 'H') := "BCDEFGHA";
constant C2 : CSTRING('A' to 'H') := "CDEFGHAB";
constant C3 : CSTRING('A' to 'H') := "DEFGHABC";
variable V1 : CHARACTER;
variable V2 : CHARACTER;
variable V3 : CHARACTER;
BEGIN
V1 := C1('A'); -- A -> B
assert V1 = 'B';
V2 := C2(C1('A')); -- A -> B -> D
assert V2 = 'D';
V3 := C3(C2(C1('A'))); -- A -> B -> H
assert V3 = 'G';
wait for 5 ns;
assert NOT( V1 = 'B' and V2 = 'D' and V3 = 'G' )
report "***PASSED TEST: c06s04b00x00p03n02i01075"
severity NOTE;
assert ( V1 = 'B' and V2 = 'D' and V3 = 'G' )
report "***FAILED TEST: c06s04b00x00p03n02i01075 - The expresion for index name check test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01075arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/sr2676/reset_types.vhdl | 3 | 394 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package reset_types is
type reset_state is (
RST,
ENABLE_CORE_POWER,
SAMPLE_HW_CONFIG,
SELECT_PROCESSOR_POR_CONFIG,
SELECT_PERSONALITY_ID,
SAMPLE_PERSONALITY_ID,
DESELECT_PERSONALITY_ID,
DEASSERT_HRESET,
DESELECT_PROCESSOR_POR_CONFIG,
WAIT_FOR_PROCESSOR,
ENABLE_ALL_DEVICES,
MONITOR_RESET
);
end reset_types;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc232.vhd | 4 | 1789 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc232.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p02n01i00232ent IS
END c03s01b02x00p02n01i00232ent;
ARCHITECTURE c03s01b02x00p02n01i00232arch OF c03s01b02x00p02n01i00232ent IS
type a is range (1+1) to (1 ms/1 ns);
BEGIN
TESTING: PROCESS
variable k : a := 3;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p02n01i00232"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p02n01i00232 - The right bound in the range constraint is not a locally static expression of type integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p02n01i00232arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_05.vhd | 4 | 956 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.std_ulogic;
entity logic_block is
port ( a, b : in std_ulogic;
y, z : out std_ulogic );
end entity logic_block;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug06/repro.vhdl | 3 | 780 | library ieee;
use ieee.std_logic_1164.all;
entity foo is
end entity;
architecture fum of foo is
constant A: std_logic_vector (7 downto 0) := X"04";
function slv_image(inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end;
begin
SOME_LABEL:
process
begin
wait for 1 ns;
if A <= "00001011" then -- if A <= std_logic_vector'("00001011") then
report "A = " & slv_image(A) ;
end if;
wait;
end process;
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc686.vhd | 4 | 2129 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc686.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:02 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00686ent IS
END c03s04b01x00p23n01i00686ent;
ARCHITECTURE c03s04b01x00p23n01i00686arch OF c03s04b01x00p23n01i00686ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of BOOLEAN;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.10";
-- Declare a variable.
constant CON : BOOLEAN := TRUE;
variable VAR : BOOLEAN := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00686 - The output file will tested by test file s010428.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00686arch;
| gpl-2.0 |
123gmax/Digital-Lab | AES128/building_blocks/invSubByte_tb.vhd | 1 | 1692 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/26/2015 10:49:35 PM
-- Design Name:
-- Module Name: invSubByte_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity invSubByte_tb is
end invSubByte_tb;
architecture Behavioral of invSubByte_tb is
component invSubByte is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end component;
constant clk_period : time := 2ns;
signal CLK, RESET : STD_LOGIC := '0';
signal byteIn, byteOut : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
uut: invSubByte port map( CLK => CLK,
RESET => RESET,
byteIn => byteIn,
byteOut => byteOut);
clk_process: process
begin
CLK <= '0';
wait for clk_period/2;
CLK <= '1';
wait for clk_period/2;
end process;
stim_process: process
begin
byteIn <= x"05";
wait for clk_period;
byteIn <= x"70";
wait for clk_period;
RESET <= '1';
byteIn <= x"80";
wait for clk_period;
RESET <= '0';
wait for clk_period;
end process;
end Behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/sr2903/boundcheck.vhdl | 3 | 925 | library IEEE;
use IEEE.numeric_std.all;
entity tb is
end tb;
architecture behavioral of tb is
subtype int31 is integer range -2**(31-1) to 2**(31-1)-1;
type array_7_int31 is array(0 to 6) of int31;
function ASR(v : integer; n : natural ; nv : natural; nres : natural) return integer is
variable tmp : signed(nv downto 0);
variable res : signed(nv downto 0);
begin
tmp := resize(to_signed(v,nv),nv+1);
res := shift_right(tmp,n);
return to_integer(res(nres-1 downto 0));
end;
begin
software_emulation : process
variable test : int31;
variable tmp : int31;
begin
report "Start" severity note;
tmp := 5965232;
-- test := test + ASR(((tmp * 119304647) + 268435456),29,57,31);
-- test := test + ASR(((tmp * 178956971) + 268435456),29,57,31);
test := test + ASR(((tmp * 59652324) + 268435456),29,57,31);
end process;
end behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3201.vhd | 4 | 2086 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3201.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03201ent IS
END c14s03b00x00p42n01i03201ent;
ARCHITECTURE c14s03b00x00p42n01i03201arch OF c14s03b00x00p42n01i03201ent IS
BEGIN
TESTING: PROCESS
file F : TEXT open read_mode is "iofile.14";
variable L : LINE;
variable vstring : string(1 to 3);
variable fail : integer := 0;
BEGIN
for I in 1 to 100 loop
READLINE (F, L);
READ (L, vstring);
if (vstring /= "niu") then
fail := 1;
end if;
end loop;
assert NOT(fail = 0)
report "***PASSED TEST: c14s03b00x00p42n01i03201"
severity NOTE;
assert (fail = 0)
report "***FAILED TEST: c14s03b00x00p42n01i03201 - procedure READLINE for string TEXT file test failed, plese check s010116.vhd file also."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03201arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2085.vhd | 4 | 2659 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2085.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02085ent IS
END c07s02b04x00p20n01i02085ent;
ARCHITECTURE c07s02b04x00p20n01i02085arch OF c07s02b04x00p20n01i02085ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4_up is boolean_v (1 to 4);
SUBTYPE boolean_4_dwn is boolean_v (4 downto 1);
SUBTYPE boolean_8_dwn is boolean_v (4 downto -3);
BEGIN
TESTING: PROCESS
variable r_operand : boolean_4_up := (true, true, false, false);
variable l_operand : boolean_4_dwn:= (false, false, true, true);
variable result : boolean_8_dwn;
BEGIN
result := l_operand & r_operand;
assert ( result (4) = false )
report "result (4) /= false" severity FAILURE;
assert ( result (1) = true )
report "result (1) /= true" severity FAILURE;
assert ( result (0) = true )
report "result (0) /= true" severity FAILURE;
assert ( result (-3) = false )
report "result (-3) /= false" severity FAILURE;
assert NOT((result(4)=false) and (result=(false,false,true,true,true,true,false,false)))
report "***PASSED TEST: c07s02b04x00p20n01i02085"
severity NOTE;
assert ((result(4)=false) and (result=(false,false,true,true,true,true,false,false)))
report "***FAILED TEST: c07s02b04x00p20n01i02085 - Concatenated array is descending and that the left bound is that of the first operand."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02085arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/non_compliant/ch_17_fg_17_14.vhd | 4 | 2970 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_fg_17_14.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity test_bench is
end entity test_bench;
-- end not in book
library ieee; use ieee.std_logic_1164.all;
architecture initial_test of test_bench is
use work.stimulus_types.all;
-- . . . -- component and signal declarations
-- not in book
signal dut_signals : std_logic_vector(0 to stimulus_vector_length - 1);
-- end not in book
begin
-- . . . -- instantiate design under test
stimulus_generation : process is
use work.stimulus_element_ordered_collection_adt.all;
variable stimulus_list : ordered_collection := new_ordered_collection;
variable next_stimulus_position : position;
variable next_stimulus : stimulus_element;
variable position_is_null : boolean;
begin
insert(stimulus_list, stimulus_element'(0 ns, "0XXXXXXXXX"));
insert(stimulus_list, stimulus_element'(200 ns, "0000110110"));
insert(stimulus_list, stimulus_element'(300 ns, "10001ZZZZZ"));
insert(stimulus_list, stimulus_element'(50 ns, "1XXXXXXXXX"));
insert(stimulus_list, stimulus_element'(60 ns, "1ZZZZZZZZZ"));
-- . . .
-- not in book
insert(stimulus_list, stimulus_element'(100 ns, "----------"));
search(stimulus_list, 100 ns, next_stimulus_position);
delete(next_stimulus_position);
get_element(next_stimulus_position, next_stimulus);
-- end not in book
find_first(stimulus_list, next_stimulus_position);
loop
test_null_position(next_stimulus_position, position_is_null);
exit when position_is_null;
get_element(next_stimulus_position, next_stimulus);
wait for next_stimulus.application_time - now;
dut_signals <= next_stimulus.pattern;
advance(next_stimulus_position);
end loop;
wait;
end process stimulus_generation;
end architecture initial_test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_10.vhd | 4 | 1591 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_10.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity reg is
generic ( t_setup, t_hold, t_pd : delay_length;
width : positive );
port ( clock : in std_logic;
data_in : in std_logic_vector(0 to width - 1);
data_out : out std_logic_vector(0 to width - 1) );
end entity reg;
-- not in book
architecture gate_level of reg is
begin
end architecture gate_level;
-- end not in book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2877.vhd | 4 | 1606 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2877.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p06n05i02877ent IS
-- Failure_here
function "an" & "d" return BOOLEAN;
END c02s01b00x00p06n05i02877ent;
ARCHITECTURE c02s01b00x00p06n05i02877arch OF c02s01b00x00p06n05i02877ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b00x00p06n05i02877 - Illegal function designator."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p06n05i02877arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2552.vhd | 4 | 1774 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2552.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b06x00p02n01i02552ent IS
END c07s03b06x00p02n01i02552ent;
ARCHITECTURE c07s03b06x00p02n01i02552arch OF c07s03b06x00p02n01i02552ent IS
BEGIN
TESTING: PROCESS
type CELL;
type LINK is access CELL;
type CELL is
record
VALUE : Integer;
SUCC : LINK;
PRED : LINK;
end record;
variable HEAD : LINK := CELL'(0,null,null); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b06x00p02n01i02552 - Missing keyword 'new'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b06x00p02n01i02552arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_09.vhd | 4 | 1399 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_09_defs is
attribute attr : integer;
end package inline_09_defs;
use work.inline_09_defs.all;
entity e is
port ( p : in bit );
attribute attr of p : signal is 1;
end entity e;
architecture arch of e is
begin
assert false report integer'image(p'attr);
end architecture arch;
use work.inline_09_defs.all;
entity inline_09 is
end entity inline_09;
architecture test of inline_09 is
signal s : bit;
attribute attr of s : signal is 2;
begin
-- code from book
c1 : entity work.e(arch)
port map ( p => s );
-- end code from book
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc456.vhd | 4 | 3398 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc456.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00456ent IS
END c03s02b01x01p19n01i00456ent;
ARCHITECTURE c03s02b01x01p19n01i00456arch OF c03s02b01x01p19n01i00456ent IS
type four_value is ('Z','0','1','X');
type four_value_vector is array (natural range <>) of four_value;
function resolution14(i:in four_value_vector) return four_value is
variable temp : four_value := 'Z';
begin
return temp;
end resolution14;
subtype four_value_state is resolution14 four_value;
constant C56 : four_value_state := 'Z';
function complex_scalar(s : four_value_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return four_value_state is
begin
return C56;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : four_value_state;
signal S2 : four_value_state;
signal S3 : four_value_state := C56;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C56) and (S2 = C56))
report "***PASSED TEST: c03s02b01x01p19n01i00456"
severity NOTE;
assert ((S1 = C56) and (S2 = C56))
report "***FAILED TEST: c03s02b01x01p19n01i00456 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00456arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_ch_13_01.vhd | 4 | 1801 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_ch_13_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_13_01 is
end entity ch_13_01;
architecture test of ch_13_01 is
-- code from book
component nand3 is
port ( a, b, c : in bit := '1'; y : out bit );
end component nand3;
-- end code from book
signal s1, s2, s3 : bit;
begin
-- code from book
gate1 : component nand3
port map ( a => s1, b => s2, c => open, y => s3 );
-- end code from book
end architecture test;
-- code from book
entity nand2 is
port ( a, b : in bit := '1'; y : out bit );
end entity nand2;
-- end code from book
configuration ch_13_01_test of ch_13_01 is
for test
-- code from book
for gate1 : nand3
use entity work.nand2(basic);
end for;
-- end code from book
end for;
end configuration ch_13_01_test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_reg-b.vhd | 4 | 1222 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_reg-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture behavioral of reg is
begin
behavior : process (clk) is
begin
if rising_edge(clk) then
q <= d;
end if;
end process behavior;
end architecture behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2051.vhd | 4 | 1673 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2051.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02051ent IS
END c07s02b04x00p01n01i02051ent;
ARCHITECTURE c07s02b04x00p01n01i02051arch OF c07s02b04x00p01n01i02051ent IS
BEGIN
TESTING: PROCESS
variable BITSTRV : BIT_VECTOR( 0 to 7 );
BEGIN
BITSTRV := BITSTRV + "01010101";
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02051 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02051arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2688.vhd | 4 | 1604 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2688.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p02n01i02688ent IS
constant n: real := 45.3 E+11; -- failure_here
END c13s04b01x00p02n01i02688ent;
ARCHITECTURE c13s04b01x00p02n01i02688arch OF c13s04b01x00p02n01i02688ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s04b01x00p02n01i02688 - No space is allowed in literals."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p02n01i02688arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3023.vhd | 4 | 1810 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3023.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library WORK, STD;
ENTITY c11s02b00x00p05n01i03023ent IS
END c11s02b00x00p05n01i03023ent;
ARCHITECTURE c11s02b00x00p05n01i03023arch OF c11s02b00x00p05n01i03023ent IS
signal S1 : STD.STANDARD.bit; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
S1 <= '1' after 20 ns;
wait for 30 ns;
assert NOT( S1 = '1' )
report "***PASSED TEST: c11s02b00x00p05n01i03023"
severity NOTE;
assert ( S1 = '1' )
report "***FAILED TEST: c11s02b00x00p05n01i03023 - Library logical name may be referenced in the design unit."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s02b00x00p05n01i03023arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1654.vhd | 4 | 2146 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1654.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s00b00x00p04n01i01654ent IS
END c09s00b00x00p04n01i01654ent;
ARCHITECTURE c09s00b00x00p04n01i01654arch OF c09s00b00x00p04n01i01654ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE -- force assertion violation
report "PASS: process TESTING executes."
severity NOTE;
assert FALSE
report "***PASSED TEST: c09s00b00x00p04n01i01654 - it is really uncertain that which assertion note appear first for different simulator."
severity NOTE;
wait;
END PROCESS TESTING;
TEST: PROCESS
begin
assert FALSE
report "PASS: process TEST executes."
severity NOTE;
-- Note: It does not matter which process executes first. (The order
-- of process execution is not defined by the LRM, and dependence
-- on the execution order is not allowed.)
wait; -- wait forever
END PROCESS TEST;
END c09s00b00x00p04n01i01654arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1175.vhd | 4 | 1948 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1175.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s00b00x00p01n02i01175ent IS
END c08s00b00x00p01n02i01175ent;
ARCHITECTURE c08s00b00x00p01n02i01175arch OF c08s00b00x00p01n02i01175ent IS
BEGIN
TESTING: PROCESS
variable a : integer := 0;
variable b : integer := 1;
BEGIN
LP1 : for i in 1 to 10 loop
a := a + 1;
end loop;
if a = 10 then
b := 10;
elsif a = 0 then
b := 0;
else
b := 5;
end if;
assert NOT( (a=10) and (b=10) )
report "***PASSED TEST: c08s00b00x00p01n02i01175"
severity NOTE;
assert ( (a=10) and (b=10) )
report "***FAILED TEST: c08s00b00x00p01n02i01175 - Sequential statements are permitted in a sequence of statements."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s00b00x00p01n02i01175arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1688.vhd | 4 | 1659 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1688.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p03n01i01688ent IS
port (B:Bit);
END c09s02b00x00p03n01i01688ent;
ARCHITECTURE c09s02b00x00p03n01i01688arch OF c09s02b00x00p03n01i01688ent IS
BEGIN
TESTING: PROCESS(B)
signal S : Bit; --illegal: no signal declaration here
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p03n01i01688 - Signal declarations are not permitted in process statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p03n01i01688arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_search.vhd | 4 | 2134 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity list_search is
end entity list_search;
----------------------------------------------------------------
architecture test of list_search is
signal s : bit_vector(0 to 3);
begin
process is
type value_cell;
type value_ptr is access value_cell;
type value_cell is record
value : bit_vector(0 to 3);
next_cell : value_ptr;
end record value_cell;
variable value_list, current_cell : value_ptr;
variable search_value : bit_vector(0 to 3);
begin
value_list := new value_cell'( B"1000", value_list );
value_list := new value_cell'( B"0010", value_list );
value_list := new value_cell'( B"0000", value_list );
search_value := B"0010";
-- code from book:
current_cell := value_list;
while current_cell /= null
and current_cell.value /= search_value loop
current_cell := current_cell.next_cell;
end loop;
assert current_cell /= null
report "search for value failed";
-- end of code from book
search_value := B"1111";
current_cell := value_list;
while current_cell /= null
and current_cell.value /= search_value loop
current_cell := current_cell.next_cell;
end loop;
assert current_cell /= null
report "search for value failed";
wait;
end process;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3079.vhd | 4 | 4169 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3079.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03079pkg is
type natural_cons_vector is array (15 downto 0) of natural;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
constant C19 : natural_cons_vectorofvector := (others => (others => 3));
end c12s06b02x00p06n01i03079pkg;
use work.c12s06b02x00p06n01i03079pkg.all;
ENTITY c12s06b02x00p06n01i03079ent_a IS
PORT
(
F1: OUT integer ;
F3: IN natural_cons_vectorofvector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03079ent_a;
ARCHITECTURE c12s06b02x00p06n01i03079arch_a OF c12s06b02x00p06n01i03079ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03079arch_a;
use work.c12s06b02x00p06n01i03079pkg.all;
ENTITY c12s06b02x00p06n01i03079ent IS
END c12s06b02x00p06n01i03079ent;
ARCHITECTURE c12s06b02x00p06n01i03079arch OF c12s06b02x00p06n01i03079ent IS
function scalar_complex(s : integer) return natural_cons_vectorofvector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN natural_cons_vectorofvector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03079ent_a(c12s06b02x00p06n01i03079arch_a);
signal S1 : natural_cons_vectorofvector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03079"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03079 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03079arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1707.vhd | 4 | 2080 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1707.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p07n01i01707ent IS
END c09s02b00x00p07n01i01707ent;
ARCHITECTURE c09s02b00x00p07n01i01707arch OF c09s02b00x00p07n01i01707ent IS
procedure call_wait (variable dly : in time;
variable bool : out boolean) is
--
-- This procedure simply waits for the time specified in its argument.
--
begin
wait for dly;
bool := false;
end call_wait;
signal trigger : bit;
BEGIN
trigger <= '1' after 5 ns;
TESTING: PROCESS( trigger )
variable delay : time := 2 ns;
variable bool : boolean := true;
BEGIN
call_wait(delay, bool); -- use wait indirectly
assert FALSE
report "***FAILED TEST: c09s02b00x00p07n01i01707 - Procedure with an indirect wait was illegal to be placed in a process with an explicit sensitivity list."
severity ERROR;
END PROCESS TESTING;
END c09s02b00x00p07n01i01707arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1848.vhd | 4 | 1807 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1848.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01848ent IS
type small_int is range 0 to 7;
END c07s01b00x00p08n01i01848ent;
ARCHITECTURE c07s01b00x00p08n01i01848arch OF c07s01b00x00p08n01i01848ent IS
signal s_int : small_int;
BEGIN
sig : s_int <= 5 after 5 ns;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01848 - Signal assignment labels are not permitted as primaries in an initialization expression."
severity ERROR;
wait;
END PROCESS TESTING;
b : block (s_int = 0)
signal tmp : small_int := sig;
begin
end block b;
END c07s01b00x00p08n01i01848arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug18361/cnt.vhdl | 3 | 1771 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CNT_V is
Generic(clk_divisor: natural);
Port(clk : in std_logic;
reset : in std_logic;
q_o : out std_logic);
end CNT_V;
architecture behv of CNT_V is
--components
--constants
--signals
signal q: std_logic;
begin
q_o <= q;
count: process(clk, reset) is
--variable
variable idx: natural range 0 to clk_divisor-1;
begin
if reset = '1' then
idx:= 0;
q <= '0';
elsif rising_edge(clk) then
if idx = clk_divisor - 1 then
q <= '1';
idx := 0;
else
q <= '0';
idx := idx + 1;
end if;
end if;
end process;
end behv;
-- Testbench:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cnt_v_tb is
end cnt_v_tb;
architecture TB of cnt_v_tb is
component CNT_V is
Generic(clk_divisor: natural);
Port(clk : in std_logic;
reset : in std_logic;
q_o : out std_logic);
end component;
--components
--constants
--signals
signal clk : std_logic;
signal reset : std_logic;
signal q_o : std_logic;
begin
DUV: cnt_v
--generic map(clk_divisor => 10) -- here ist the error
port map( clk, reset, q_o);
--stimuli here
--Stimuli for Signal "clk" 40 mhz
process
begin
clk <= '1';
wait for 12.5 ns;
clk <= '0';
wait for 12.5 ns;
end process;
process
begin
--initialisation
reset <= '1';
wait for 20 ns;
--stimuli
reset <= '0';
wait for 22 ns;
-- do some stuff
wait;
end process;
end TB;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1381.vhd | 4 | 1854 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1381.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s05b00x00p03n01i01381pkg is
type base_type is ( 'B', 'O', 'X', 'b', 'o', 'x' );
end ch0805_p00301_27_pkg;
use work.c08s05b00x00p03n01i01381pkg.all;
ENTITY c08s05b00x00p03n01i01381ent IS
END c08s05b00x00p03n01i01381ent;
ARCHITECTURE c08s05b00x00p03n01i01381arch OF c08s05b00x00p03n01i01381ent IS
BEGIN
TESTING: PROCESS
variable v1 : integer := 0;
BEGIN
pack := v1; -- illegal package name target
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01381 - Target of a variable assignment can not be the name of a package."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01381arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2037.vhd | 4 | 1660 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2037.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02037ent IS
END c07s02b04x00p01n01i02037ent;
ARCHITECTURE c07s02b04x00p01n01i02037arch OF c07s02b04x00p01n01i02037ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
BEGIN
BOOLV := BOOLV + TRUE;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02037 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02037arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc730.vhd | 4 | 1657 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc730.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x00p04n01i00730ent IS
port ( signal s : bit
);
port ( signal t : bit -- illegal second port clause
);
END c01s01b01x00p04n01i00730ent;
ARCHITECTURE c01s01b01x00p04n01i00730arch OF c01s01b01x00p04n01i00730ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p04n01i00730 - Extra port clause."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p04n01i00730arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_12.vhd | 4 | 1628 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_12.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity counter is
generic ( tipd_reset, -- input prop delay on reset
tipd_clk, -- input prop delay on clk
topd_q : delay_length; -- output prop delay on q
tsetup_reset, -- setup: reset before clk
thold_reset : delay_length ); -- hold time: reset after clk
port ( reset, -- synchronous reset input
clk : in bit; -- edge triggered clock input
q : out bit_vector ); -- counter output
end entity counter;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc639.vhd | 4 | 3323 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc639.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:51 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:14 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:28 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00639ent IS
END c03s04b01x00p01n01i00639ent;
ARCHITECTURE c03s04b01x00p01n01i00639arch OF c03s04b01x00p01n01i00639ent IS
type four_value is ('Z','0','1','X');
subtype binary is four_value range '0' to '1';
subtype word is bit_vector(0 to 15);
constant size : integer := 7;
type primary_memory is array(0 to size) of word;
type primary_memory_module is
record
enable : binary;
memory_number : primary_memory;
end record;
type primary_memory_module_file is file of primary_memory_module;
constant C38 : word := (others => '1');
constant C44 : primary_memory := (others => C38);
constant C45 : primary_memory_module := ('1',C44);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : primary_memory_module_file open read_mode is "iofile.43";
variable v : primary_memory_module;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C45) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00639"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00639 - File reading operation (primary_memory_module file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00639arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2463.vhd | 4 | 1826 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2463.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02463ent IS
END c07s03b02x02p03n02i02463ent;
ARCHITECTURE c07s03b02x02p03n02i02463arch OF c07s03b02x02p03n02i02463ent IS
subtype BV1 is BIT_VECTOR (2 downto 1);
constant c : BV1 := ('1', others => '0');
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( c="10" )
report "***PASSED TEST: c07s03b02x02p03n02i02463"
severity NOTE;
assert ( c="10" )
report "***FAILED TEST: c07s03b02x02p03n02i02463 - An aggregate with an others choice can appear as an expression defining the initial value of a constant."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02463arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1703.vhd | 4 | 4277 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1703.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p05n01i01703ent IS
END c09s02b00x00p05n01i01703ent;
ARCHITECTURE c09s02b00x00p05n01i01703arch OF c09s02b00x00p05n01i01703ent IS
signal s : boolean := false;
BEGIN
TESTING: PROCESS
type result_type is (fail, pass);
variable result : result_type := fail;
variable i, j : integer;
variable k : integer := 0;
BEGIN
--
-- Test all sequential statements in this process
--
s <= true; -- signal assignment
j := 1; -- variable assignment
i := 0;
L1: while ( i < 10 ) loop -- conditional loop
if i > 2 then
exit;
end if;
case i is
when 0 =>
L2: for j in 1 to 3 loop
case j is
when 3 => -- should never execute because of
i := i + 1; -- alternative 2
k := 1;
exit;
assert false
report "exit in loop 2 case failed."
severity note;
when 2 =>
i := i + 1;
next L1;
k := 1;
assert false -- should never execute
report "next in loop 2 case failed."
severity note;
when 1 =>
assert false
report "first iteration of loop 2."
severity note ;
next; -- applies to loop L2
when others =>
--
-- This should never be executed but is
-- required by the 1076-1987 spec. which
-- says the subtype of 'j' is the same as
-- the base type (integer) and not constrained
-- to the range "1 to 3".
--
k := 1;
assert false
report "Should never get here."
severity note ;
end case;
k := 1;
assert false -- should never execute
report "next in loop 2 failed."
severity note;
end loop L2;
when 2 =>
s <= false after 5 ns;
wait for 6 ns;
assert not s
report "wait statement in loop L1 failed."
severity note ;
i := i +1;
when 1 =>
null;
assert false
report "null statement and next statement worked."
severity note ;
i := i +1;
when others =>
k := 1;
assert false
report "exit in if statement in loop L1 failed."
severity note ;
exit;
end case;
end loop L1;
wait for 50 ns;
assert NOT(s=false and k = 0 and j=1)
report "***PASSED TEST: c09s02b00x00p05n01i01703"
severity NOTE;
assert (s=false and k = 0 and j=1)
report "***FAILED TEST: c09s02b00x00p05n01i01703 - Process statement execution failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p05n01i01703arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc797.vhd | 4 | 1688 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc797.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b03x00p03n01i00797ent IS
signal err : boolean := false;
begin
err <= true; -- illegal location for signal assignment
END c01s01b03x00p03n01i00797ent;
ARCHITECTURE c01s01b03x00p03n01i00797arch OF c01s01b03x00p03n01i00797ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b03x00p03n01i00797 - Signal assignment statement can not appear in entity statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b03x00p03n01i00797arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_crtl.vhd | 4 | 2719 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_crtl.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.dlx_types.all,
work.alu_types.all,
work.reg_file_types.all;
entity controller is
generic ( Tpd_clk_ctrl, Tpd_clk_const : delay_length;
debug : dlx_debug_control := none );
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
width : out dlx_mem_width;
write_enable : out std_logic;
mem_enable : out std_logic;
ifetch : out std_logic;
ready : in std_logic;
alu_in_latch_en : out std_logic;
alu_function : out alu_func;
alu_zero, alu_negative, alu_overflow : in std_logic;
reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr;
reg_write : out std_logic;
c_latch_en : out std_logic;
a_latch_en, a_out_en : out std_logic;
b_latch_en, b_out_en : out std_logic;
temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic;
iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic;
pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic;
mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic;
mem_addr_mux_sel : out std_logic;
mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic;
mdr_mux_sel : out std_logic;
ir_latch_en : out std_logic;
ir_immed1_size_26, ir_immed2_size_26 : out std_logic;
ir_immed1_unsigned, ir_immed2_unsigned : out std_logic;
ir_immed1_en, ir_immed2_en : out std_logic;
current_instruction : in dlx_word;
mem_addr : std_logic_vector(1 downto 0);
const1, const2 : out dlx_word );
end entity controller;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-fl.vhd | 4 | 8659 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_mem-fl.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all,
std.textio.all;
architecture file_loaded of memory is
begin
mem_behavior : process is
constant high_address : natural := mem_size - 1;
type memory_array is
array (natural range 0 to high_address / 4) of dlx_bv_word;
variable mem : memory_array;
variable byte_address, word_address : natural;
variable write_access : boolean;
procedure load is
file binary_file : text open read_mode is load_file_name;
variable L : line;
variable ch : character;
variable line_number : natural := 0;
variable addr : natural;
variable word : dlx_bv_word;
procedure read_hex_natural ( L : inout line; n : out natural ) is
variable result : natural := 0;
begin
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
result := result*16 + character'pos(ch) - character'pos('0');
elsif 'A' <= ch and ch <= 'F' then
result := result*16 + character'pos(ch) - character'pos('A') + 10;
elsif 'a' <= ch and ch <= 'f' then
result := result*16 + character'pos(ch) - character'pos('a') + 10;
else
report "Format error in file " & load_file_name
& " on line " & integer'image(line_number) severity error;
end if;
end loop;
n := result;
end read_hex_natural;
procedure read_hex_word ( L : inout line; word : out dlx_bv_word ) is
variable digit : natural;
variable r : natural := 0;
begin
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
digit := character'pos(ch) - character'pos('0');
elsif 'A' <= ch and ch <= 'F' then
digit := character'pos(ch) - character'pos('A') + 10;
elsif 'a' <= ch and ch <= 'f' then
digit := character'pos(ch) - character'pos('a') + 10;
else
report "Format error in file " & load_file_name
& " on line " & integer'image(line_number)
severity error;
end if;
word(r to r+3) := natural_to_bv(digit, 4);
r := r + 4;
end loop;
end read_hex_word;
begin
while not endfile(binary_file) loop
readline(binary_file, L);
line_number := line_number + 1;
read_hex_natural(L, addr);
read(L, ch); -- the space between addr and data
read_hex_word(L, word);
mem(addr / 4) := word;
end loop;
end load;
procedure do_write is
subtype ls_2_bits is bit_vector(1 downto 0);
begin
case width is
when dlx_mem_width_word =>
mem(word_address) := to_bitvector(d);
when dlx_mem_width_halfword =>
if To_bit(a(1)) = '0' then -- ms half word
mem(word_address)(0 to 15) := to_bitvector( d(0 to 15) );
else -- ls half word
mem(word_address)(16 to 31) := to_bitvector( d(16 to 31) );
end if;
when dlx_mem_width_byte =>
case ls_2_bits'(To_bitvector(a(1 downto 0))) is
when b"00" =>
mem(word_address)(0 to 7) := to_bitvector( d(0 to 7) );
when b"01" =>
mem(word_address)(8 to 15) := to_bitvector( d(8 to 15) );
when b"10" =>
mem(word_address)(16 to 23) := to_bitvector( d(16 to 23) );
when b"11" =>
mem(word_address)(24 to 31) := to_bitvector( d(24 to 31) );
end case;
when others =>
report "illegal width indicator in write" severity error;
end case;
end do_write;
procedure do_read is
begin
d <= To_X01( mem(word_address) );
end do_read;
begin
load; -- read binary memory image into memory array
-- initialize outputs
d <= disabled_dlx_word;
ready <= '0';
-- process memory cycles
loop
-- wait for a command, valid on leading edge of phi2
wait on phi2 until rising_edge(phi2) and To_bit(mem_enable) = '1';
-- decode address and perform command if selected
byte_address := bv_to_natural(To_bitvector(a));
write_access := To_bit(write_enable) = '1';
if byte_address <= high_address then
word_address := byte_address / 4;
if write_access then -- write cycle
do_write;
wait for Tac_first; -- write access time, 1st cycle
else -- read cycle
wait for Tac_first; -- read access time, 1st cycle
do_read;
end if;
-- ready synchronous with phi2
wait until rising_edge(phi2);
ready <= '1' after Tpd_clk_out;
wait until falling_edge(phi2);
ready <= '0' after Tpd_clk_out;
-- do subsequent cycles in burst
while To_bit(burst) = '1' loop
word_address := (word_address + 1) mod (mem_size / 4);
wait until rising_edge(phi2);
if write_access then -- write cycle
do_write;
wait for Tac_burst; -- write access time, burst cycle
else -- read cycle
wait for Tac_burst; -- read access time, burst cycle
do_read;
end if;
-- ready synchronous with phi2
wait until rising_edge(phi2);
ready <= '1' after Tpd_clk_out;
wait until falling_edge(phi2);
ready <= '0' after Tpd_clk_out;
end loop;
if not write_access then -- was read
d <= disabled_dlx_word after Tpd_clk_out;
end if;
end if;
end loop;
end process mem_behavior;
end architecture file_loaded;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket31/top_phystest_simple.vhdl | 3 | 647 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.MATH_REAL.all;
entity Top_PhysicalTest_Simple is
port (
Clock : in STD_LOGIC;
Input : in STD_LOGIC;
Output : out STD_LOGIC
);
end;
architecture top of Top_PhysicalTest_Simple is
constant int_1 : INTEGER := natural(1.5);
-- constant int_2 : INTEGER := integer(-1.5);
constant int_2 : INTEGER := natural(-1.5);
begin
assert FALSE report "16 - int_1 (natural(1.5)): " & INTEGER'image(int_1) severity note;
assert FALSE report "17 - int_2 (natural(-1.5)): " & INTEGER'image(int_2) severity note;
Output <= Input when rising_edge(Clock);
end;
| gpl-2.0 |
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