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peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc107.vhd | 4 | 1712 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc107.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n06i00107ent IS
port ( signal S : out bit) ;
END c04s03b02x00p29n06i00107ent;
ARCHITECTURE c04s03b02x00p29n06i00107arch OF c04s03b02x00p29n06i00107ent IS
BEGIN
TESTING: PROCESS
variable T : TIME := 10 ns;
BEGIN
if (S'LAST_ACTIVE = T) then -- Failure_here
end if;
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n06i00107 - The attribute LAST_ACTIVE of a signal of mode out cannot be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00107arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc985.vhd | 4 | 1861 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc985.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p06n01i00985ent IS
END c06s03b00x00p06n01i00985ent;
ARCHITECTURE c06s03b00x00p06n01i00985arch OF c06s03b00x00p06n01i00985ent IS
BEGIN
TESTING: PROCESS
type T is
record
a:integer;
b:integer;
end record;
type A is access T;
variable B1, B2: A := new T'(0, 0);
variable C : T;
BEGIN
C := B1.all;
B1.all := C.all; -- C.all is illegal
assert FALSE
report "***FAILED TEST: c06s03b00x00p06n01i00985 - Prefix of a selected name used to denote an object designated by an access value should be an access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p06n01i00985arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1830.vhd | 4 | 1843 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1830.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01830ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int) of bit;
END c07s01b00x00p08n01i01830ent;
ARCHITECTURE c07s01b00x00p08n01i01830arch OF c07s01b00x00p08n01i01830ent IS
signal s_int : small_int := 0;
signal s_bus : cmd_bus;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= s_bus'right(c07s01b00x00p08n01i01830ent); -- entity name illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01830 - Entity name are not permitted as primaries in an attribute argument."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01830arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc956.vhd | 4 | 2115 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc956.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n02i00956ent IS
END c06s01b00x00p10n02i00956ent;
ARCHITECTURE c06s01b00x00p10n02i00956arch OF c06s01b00x00p10n02i00956ent IS
signal PT : boolean;
subtype ONE is integer range 1 to 1;
type R1 is record
X1: ONE;
RE1: BOOLEAN;
end record;
function rr1(i : integer) return R1 is
variable vr : r1;
begin
return vr;
end rr1;
attribute AT1 : R1;
attribute AT1 of PT : signal is rr1(3);
type A1 is array (BOOLEAN) of BOOLEAN;
BEGIN
TESTING: PROCESS
variable V1 : BOOLEAN;
variable V2 : A1;
BEGIN
V1 := V2(PT'AT1.RE1);
assert NOT( V1=FALSE )
report "***PASSED TEST: c06s01b00x00p10n02i00956"
severity NOTE;
assert ( V1=FALSE )
report "***FAILED TEST: c06s01b00x00p10n02i00956 - The prefix of a name is a function call."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n02i00956arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2853.vhd | 4 | 1833 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2853.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s10b00x00p02n01i02853ent IS
END c13s10b00x00p02n01i02853ent;
ARCHITECTURE c13s10b00x00p02n01i02853arch OF c13s10b00x00p02n01i02853ent IS
BEGIN
TESTING: PROCESS
subtype BYTE is BIT_VECTOR (0 to 7);
variable b1 : BYTE;
variable b2 : BYTE;
BEGIN
b1 := BYTE'(0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 => '1');
b2 := BYTE'(0 ! 1 ! 2 ! 3 ! 4 ! 5 ! 6 ! 7 => '1');
assert NOT( b1=b2 )
report "***PASSED TEST: c13s10b00x00p02n01i02853"
severity NOTE;
assert ( b1=b2 )
report "***FAILED TEST: c13s10b00x00p02n01i02853 - "
severity ERROR;
wait;
END PROCESS TESTING;
END c13s10b00x00p02n01i02853arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1011.vhd | 4 | 2100 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1011.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n01i01011ent IS
END c06s03b00x00p10n01i01011ent;
ARCHITECTURE c06s03b00x00p10n01i01011arch OF c06s03b00x00p10n01i01011ent IS
procedure check (x: in integer; y: in boolean; signal z :out integer) is
begin
z <= 5;
end;
signal p: integer ;
signal q: boolean ;
signal k: integer ;
BEGIN
TESTING: PROCESS
BEGIN
check(c06s03b00x00p10n01i01011arch.p, c06s03b00x00p10n01i01011arch.q, k);
wait for 10 ns;
assert NOT(k=5)
report "***PASSED TEST: c06s03b00x00p10n01i01011"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s03b00x00p10n01i01011 - An expanded name with the prefix of an architecture name and the suffix of signal names declared in the architecture can be used in a statement (in this test, procedure call statement) within the architecture body."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p10n01i01011arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/computer.vhd | 4 | 2943 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book:
entity computer is
end entity computer;
-- end not in book
architecture system_level of computer is
type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, -- . . .);
-- not in book:
nop);
-- end not in book
type reg_number is range 0 to 31;
constant r0 : reg_number := 0; constant r1 : reg_number := 1; -- . . .
-- not in book:
constant r2 : reg_number := 2;
-- end not in book
type instruction is record
opcode : opcodes;
source_reg1, source_reg2, dest_reg : reg_number;
displacement : integer;
end record instruction;
type word is record
instr : instruction;
data : bit_vector(31 downto 0);
end record word;
signal address : natural;
signal read_word, write_word : word;
signal mem_read, mem_write : bit := '0';
signal mem_ready : bit := '0';
begin
cpu : process is
variable instr_reg : instruction;
variable PC : natural;
-- . . . -- other declarations for register file, etc.
begin
address <= PC;
mem_read <= '1';
wait until mem_ready = '1';
instr_reg := read_word.instr;
mem_read <= '0';
-- not in book:
wait until mem_ready = '0';
-- end not in book
PC := PC + 4;
case instr_reg.opcode is -- execute the instruction
-- . . .
-- not in book:
when others => null;
-- end not in book
end case;
end process cpu;
memory : process is
subtype address_range is natural range 0 to 2**14 - 1;
type memory_array is array (address_range) of word;
variable store : memory_array :=
( 0 => ( ( ld, r0, r0, r2, 40 ), X"00000000" ),
1 => ( ( breq, r2, r0, r0, 5 ), X"00000000" ),
-- . . .
40 => ( ( nop, r0, r0, r0, 0 ), X"FFFFFFFE"),
others => ( ( nop, r0, r0, r0, 0 ), X"00000000") );
begin
-- . . .
-- not in book:
wait until mem_read = '1';
read_word <= store(address);
mem_ready <= '1';
wait until mem_read = '0';
mem_ready <= '0';
-- end not in book
end process memory;
end architecture system_level;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1164.vhd | 4 | 2035 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1164.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s06b00x00p02n01i01164pkg is
type A1 is array (1 to 2) of BOOLEAN;
type A2 is array (1 to 2) of A1;
end c06s06b00x00p02n01i01164pkg;
use work.c06s06b00x00p02n01i01164pkg.all;
ENTITY c06s06b00x00p02n01i01164ent IS
port (PT: A2);
attribute AT1 : BOOLEAN;
attribute AT1 of PT : signal is TRUE;
END c06s06b00x00p02n01i01164ent;
ARCHITECTURE c06s06b00x00p02n01i01164arch OF c06s06b00x00p02n01i01164ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if PT'AT1 then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c06s06b00x00p02n01i01164"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s06b00x00p02n01i01164 - The prefix of an attribute name may be an indexed name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01164arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/test_bench.vhd | 4 | 2225 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book (in text)
entity random_source is
generic ( min, max : natural;
seed : natural;
interval : delay_length );
port ( number : out natural );
end entity random_source;
-- end code from book
architecture fudged of random_source is
begin
process is
variable next_number : natural := seed;
begin
if next_number > max then
next_number := min;
end if;
number <= next_number;
next_number := next_number + 1;
wait for interval;
end process;
end architecture fudged;
entity test_bench is
end entity test_bench;
-- code from book
architecture random_test of test_bench is
subtype bv11 is bit_vector(10 downto 0);
function natural_to_bv11 ( n : natural ) return bv11 is
variable result : bv11 := (others => '0');
variable remaining_digits : natural := n;
begin
for index in result'reverse_range loop
result(index) := bit'val(remaining_digits mod 2);
remaining_digits := remaining_digits / 2;
exit when remaining_digits = 0;
end loop;
return result;
end function natural_to_bv11;
signal stimulus_vector : bv11;
-- . . .
begin
stimulus_generator : entity work.random_source
generic map ( min => 0, max => 2**10 - 1, seed => 0,
interval => 100 ns )
port map ( natural_to_bv11(number) => stimulus_vector );
-- . . .
end architecture random_test;
-- end code from book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2450.vhd | 4 | 2588 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2450.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02450ent IS
END c07s03b02x02p03n02i02450ent;
ARCHITECTURE c07s03b02x02p03n02i02450arch OF c07s03b02x02p03n02i02450ent IS
BEGIN
TESTING: PROCESS
type ENUM is ( ONE );
type A_ARRAY is array ( integer range <> ) of integer;
type B_ARRAY is array ( boolean range <> ) of real;
type C_ARRAY is array ( ENUM range <>, ENUM range <>) of bit;
subtype A_CON is A_ARRAY ( 1 to 4 );
subtype B_CON is B_ARRAY ( FALSE to TRUE );
subtype C_CON is C_ARRAY ( ONE to ONE, ONE to ONE );
function F_A ( PAR : A_ARRAY ) return A_CON is
begin return (1,2,3,4);
end F_A;
function F_B ( PAR : B_ARRAY ) return B_CON is
begin return (1.0, 2.0);
end F_B;
function F_C ( PAR : C_ARRAY ) return C_CON is
begin return (ONE=>(ONE=>'0'));
end F_C;
variable V_A : A_CON ;
variable V_B : B_CON ;
variable V_C : C_CON ;
BEGIN
V_A := F_A( F_A( (1,2,others=>3) ) ); -- Failure_here
-- SEMANTIC ERROR: "others" used in aggregate which corresponds to
-- an unconstrained formal parameter
assert FALSE
report "***FAILED TEST: c07s03b02x02p03n02i02450 - Others is used in an aggregate which corresponds to an unconstrained formal parameter."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02450arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc844.vhd | 4 | 2204 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc844.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s03b01x00p05n01i00844ent_a is
end c01s03b01x00p05n01i00844ent_a ;
architecture c01s03b01x00p05n01i00844arch_a of c01s03b01x00p05n01i00844ent_a is
begin
A1_BLK : block
signal S : INTEGER;
begin
S <= 1;
end block;
end c01s03b01x00p05n01i00844arch_a;
ENTITY c01s03b01x00p05n01i00844ent IS
END c01s03b01x00p05n01i00844ent;
architecture c01s03b01x00p05n01i00844arch of c01s03b01x00p05n01i00844ent is
BEGIN
AA_BLK : block
component FOUR
end component;
begin
LH : FOUR;
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s03b01x00p05n01i00844"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s03b01x00p05n01i00844arch;
configuration c01s03b01x00p05n01i00844cfg of c01s03b01x00p05n01i00844ent is
for c01s03b01x00p05n01i00844arch
for AA_BLK
for LH : FOUR
use
entity work.c01s03b01x00p05n01i00844ent_a(c01s03b01x00p05n01i00844arch_a);
end for;
end for;
end for ;
end c01s03b01x00p05n01i00844cfg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc418.vhd | 4 | 3146 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc418.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00418ent IS
END c03s02b01x01p19n01i00418ent;
ARCHITECTURE c03s02b01x01p19n01i00418arch OF c03s02b01x01p19n01i00418ent IS
type integer_cons_vector is array (15 downto 0) of integer;
constant C1 : integer_cons_vector := (others => 3);
function complex_scalar(s : integer_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return integer_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : integer_cons_vector;
signal S2 : integer_cons_vector;
signal S3 : integer_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00418"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00418 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00418arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2079.vhd | 4 | 2186 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2079.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02079ent IS
END c07s02b04x00p20n01i02079ent;
ARCHITECTURE c07s02b04x00p20n01i02079arch OF c07s02b04x00p20n01i02079ent IS
BEGIN
TESTING: PROCESS
type array_type is array (positive range <>) of integer;
-- No_failure_here
constant a : array_type (1 to 3) := (1, 2, 3);
constant b : array_type (1 to 5) := (1, 2, 3, 4, 5);
constant x : array_type := a & b;
BEGIN
assert NOT(x=(1,2,3,1,2,3,4,5))
report "***PASSED TEST: c07s02b04x00p20n01i02079"
severity NOTE;
assert (x=(1,2,3,1,2,3,4,5))
report "***FAILED TEST: c07s02b04x00p20n01i02079 - The result of the concatenation of two one-dimensional arrays is a one-dimensional array whose length is the sum of the lengths of its operands, and whose elements consist of the elements of the left operand (in left to right order) followed by the elements of the right operand (in left to right order)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02079arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc795.vhd | 4 | 1623 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc795.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b03x00p03n01i00795ent IS
begin
generic ( constant const : boolean );
END c01s01b03x00p03n01i00795ent;
ARCHITECTURE c01s01b03x00p03n01i00795arch OF c01s01b03x00p03n01i00795ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b03x00p03n01i00795 - Generic clause is not permitted as an entity statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b03x00p03n01i00795arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug18360/testcase.vhdl | 3 | 212 | entity TESTCASE is
end entity TESTCASE;
architecture PROBLEM of TESTCASE is
type ENUMERATION_TYPE is (VALUE1, VALUE2);
constant SOME_VAR : integer := ENUMERATION_TYPE'length;
begin
end architecture PROBLEM;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2845.vhd | 4 | 1599 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2845.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity USE is
end USE;
ENTITY c13s09b00x00p99n01i02845ent IS
END c13s09b00x00p99n01i02845ent;
ARCHITECTURE c13s09b00x00p99n01i02845arch OF c13s09b00x00p99n01i02845ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02845 - Reserved word USE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02845arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1605.vhd | 4 | 1696 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1605.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p04n01i01605ent IS
END c08s11b00x00p04n01i01605ent;
ARCHITECTURE c08s11b00x00p04n01i01605arch OF c08s11b00x00p04n01i01605ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
L : for i in 1 to 10 loop
exit L when k + 3;
k := i;
end loop;
assert FALSE
report "***FAILED TEST: c08s11b00x00p04n01i01605 - The condition in an exit statement must be of boolean type"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p04n01i01605arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2189.vhd | 4 | 1828 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2189.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p01n02i02189ent IS
END c07s02b00x00p01n02i02189ent;
ARCHITECTURE c07s02b00x00p01n02i02189arch OF c07s02b00x00p01n02i02189ent IS
BEGIN
TESTING: PROCESS
type A_ARRAY is array (1 to 2) of CHARACTER;
variable I : INTEGER;
variable R : REAL;
variable B : BOOLEAN;
variable A : A_ARRAY;
BEGIN
R := R + - R; -- Failure_here
-- SYNTAX ERROR: signed operator cannot follow adding operator.
assert FALSE
report "***FAILED TEST: c07s02b00x00p01n02i02189 - Signed operand cannot follow a mutiplying operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p01n02i02189arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_02.vhd | 4 | 2494 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity graphics_engine is
end entity graphics_engine;
-- end not in book
architecture behavioral of graphics_engine is
type point is array (1 to 3) of real;
type transformation_matrix is array (1 to 3, 1 to 3) of real;
signal p, transformed_p : point;
signal a : transformation_matrix;
signal clock : bit;
-- . . .
begin
transform_stage : for i in 1 to 3 generate
begin
cross_product_transform : process is
variable result1, result2, result3 : real := 0.0;
begin
wait until clock = '1';
transformed_p(i) <= result3;
result3 := result2;
result2 := result1;
result1 := a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
end process cross_product_transform;
end generate transform_stage;
-- . . . -- other stages in the pipeline, etc
-- not in book
clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
stimulus : process is
begin
a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
p <= ( 10.0, 10.0, 10.0 );
wait until clock = '0';
p <= ( 20.0, 20.0, 20.0 );
wait until clock = '0';
p <= ( 30.0, 30.0, 30.0 );
wait until clock = '0';
p <= ( 40.0, 40.0, 40.0 );
wait until clock = '0';
p <= ( 50.0, 50.0, 50.0 );
wait until clock = '0';
p <= ( 60.0, 60.0, 60.0 );
wait;
end process stimulus;
-- end not in book
end architecture behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac-r.vhd | 4 | 6274 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mac-r.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture rtl of mac is
signal pipelined_x_real,
pipelined_x_imag,
pipelined_y_real,
pipelined_y_imag : std_ulogic_vector(15 downto 0);
signal real_part_product_1,
real_part_product_2,
imag_part_product_1,
imag_part_product_2 : std_ulogic_vector(31 downto 0);
signal pipelined_real_part_product_1,
pipelined_real_part_product_2,
pipelined_imag_part_product_1,
pipelined_imag_part_product_2 : std_ulogic_vector(31 downto 0);
signal real_product,
imag_product : std_ulogic_vector(32 downto 0);
signal pipelined_real_product,
pipelined_imag_product : std_ulogic_vector(19 downto 0);
signal real_sum,
imag_sum : std_ulogic_vector(21 downto 0);
signal real_accumulator_ovf,
imag_accumulator_ovf : std_ulogic;
signal pipelined_real_sum,
pipelined_imag_sum : std_ulogic_vector(21 downto 0);
signal pipelined_real_accumulator_ovf,
pipelined_imag_accumulator_ovf : std_ulogic;
begin
x_real_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => x_real, q => pipelined_x_real );
x_imag_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => x_imag, q => pipelined_x_imag );
y_real_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => y_real, q => pipelined_y_real );
y_imag_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => y_imag, q => pipelined_y_imag );
real_mult_1 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_real, b => pipelined_y_real,
p => real_part_product_1 );
real_mult_2 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_imag, b => pipelined_y_imag,
p => real_part_product_2 );
imag_mult_1 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_real, b => pipelined_y_imag,
p => imag_part_product_1 );
imag_mult_2 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_imag, b => pipelined_y_real,
p => imag_part_product_2 );
real_part_product_reg_1 : entity work.reg(behavioral)
port map ( clk => clk, d => real_part_product_1,
q => pipelined_real_part_product_1 );
real_part_product_reg_2 : entity work.reg(behavioral)
port map ( clk => clk, d => real_part_product_2,
q => pipelined_real_part_product_2 );
imag_part_product_reg_1 : entity work.reg(behavioral)
port map ( clk => clk, d => imag_part_product_1,
q => pipelined_imag_part_product_1 );
imag_part_product_reg_2 : entity work.reg(behavioral)
port map ( clk => clk, d => imag_part_product_2,
q => pipelined_imag_part_product_2 );
real_product_subtracter : entity work.product_adder_subtracter(behavioral)
port map ( mode => '1',
a => pipelined_real_part_product_1,
b => pipelined_real_part_product_2,
s => real_product );
imag_product_adder : entity work.product_adder_subtracter(behavioral)
port map ( mode => '0',
a => pipelined_imag_part_product_1,
b => pipelined_imag_part_product_2,
s => imag_product );
real_product_reg : entity work.reg(behavioral)
port map ( clk => clk,
d => real_product(32 downto 13),
q => pipelined_real_product );
imag_product_reg : entity work.reg(behavioral)
port map ( clk => clk,
d => imag_product(32 downto 13),
q => pipelined_imag_product );
real_accumulator : entity work.accumulator_adder(behavioral)
port map ( a(19 downto 0) => pipelined_real_product(19 downto 0),
a(20) => pipelined_real_product(19),
a(21) => pipelined_real_product(19),
b => pipelined_real_sum,
s => real_sum,
ovf => real_accumulator_ovf );
imag_accumulator : entity work.accumulator_adder(behavioral)
port map ( a(19 downto 0) => pipelined_imag_product(19 downto 0),
a(20) => pipelined_imag_product(19),
a(21) => pipelined_imag_product(19),
b => pipelined_imag_sum,
s => imag_sum,
ovf => imag_accumulator_ovf );
real_accumulator_reg : entity work.accumulator_reg(behavioral)
port map ( clk => clk, clr => clr,
d => real_sum, q => pipelined_real_sum );
imag_accumulator_reg : entity work.accumulator_reg(behavioral)
port map ( clk => clk, clr => clr,
d => imag_sum, q => pipelined_imag_sum );
real_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
port map ( clk => clk,
set => real_accumulator_ovf, clr => clr,
q => pipelined_real_accumulator_ovf );
imag_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
port map ( clk => clk,
set => imag_accumulator_ovf, clr => clr,
q => pipelined_imag_accumulator_ovf );
s_real <= pipelined_real_sum(21) & pipelined_real_sum(16 downto 2);
s_imag <= pipelined_imag_sum(21) & pipelined_imag_sum(16 downto 2);
result_overflow_logic : entity work.overflow_logic(behavioral)
port map ( real_accumulator_ovf => pipelined_real_accumulator_ovf,
imag_accumulator_ovf => pipelined_imag_accumulator_ovf,
real_sum => pipelined_real_sum(21 downto 17),
imag_sum => pipelined_imag_sum(21 downto 17),
ovf => ovf );
end architecture rtl;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/generics/entity-generic-defines-port-type.vhdl | 3 | 1012 | entity test_bench is
end test_bench;
entity generic_defines_port_type is
generic( width : natural );
port( input : in bit_vector( width - 1 downto 0 );
finished : in boolean );
end entity;
architecture only of generic_defines_port_type is
begin -- only
p: process( finished )
begin -- process p
if finished = true then
for i in input'range loop
assert input(i) = '1' report "TEST FAILED" severity FAILURE;
end loop; -- i
end if;
end process p;
end only;
architecture only of test_bench is
signal gdpt1_input : bit_vector( 3 downto 0 ) := "0000";
signal gdpt1_finished : boolean := false;
begin -- only
gdpt1: entity work.generic_defines_port_type
generic map ( width => 4 )
port map ( input => gdpt1_input, finished => gdpt1_finished );
doit: process
begin -- process doit
gdpt1_input <= "1111";
wait for 1 fs;
gdpt1_finished <= true;
wait for 1 fs;
report "TEST PASSED";
wait;
end process doit;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/non_compliant/ch_17_fg_17_12.vhd | 4 | 3354 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_fg_17_12.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package «element_type_simple_name»_ordered_collection_adt is
-- template: fill in the placeholders to specialize for a particular type
alias element_type is «element_type»;
alias key_type is «key_type»;
alias key_of is «key_function» [ element_type return key_type ];
alias "<" is «less_than_function» [ key_type, key_type return boolean ];
-- types provided by the package
type ordered_collection_object; -- private
type position_object; -- private
type ordered_collection is access ordered_collection_object;
type position is access position_object;
-- operations on ordered collections
function new_ordered_collection return ordered_collection;
-- returns an empty ordered collection of element_type values
procedure insert ( c : inout ordered_collection; e : in element_type );
-- inserts e into c in position determined by key_of(e)
procedure get_element ( variable p : in position; e : out element_type );
-- returns the element value at position p in its collection
procedure test_null_position ( variable p : in position; is_null : out boolean );
-- test whether p refers to no position in its collection
procedure search ( variable c : in ordered_collection; k : in key_type;
p : out position );
-- searches for an element with key k in c, and returns the position of
-- that element, or, if not found, a position for which test_null_position
-- returns true
procedure find_first ( variable c : in ordered_collection; p : out position );
-- returns the position of the first element of c
procedure advance ( p : inout position );
-- advances p to the next element in its collection,
-- or if there are no more, sets p so that test_null_position returns true
procedure delete ( p : inout position );
-- deletes the element at position p from its collection, and advances p
-- private types: pretend these are not visible
type ordered_collection_object is
record
element : element_type;
next_element, prev_element : ordered_collection;
end record ordered_collection_object;
type position_object is
record
the_collection : ordered_collection;
current_element : ordered_collection;
end record position_object;
end package «element_type_simple_name»_ordered_collection_adt;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_04.vhd | 4 | 1892 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_04.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_04 is
end entity ch_03_04;
architecture test of ch_03_04 is
type opcode_type is (opcode_1, opcode_2, halt_opcode);
signal opcode : opcode_type := opcode_1;
signal halt_indicator : boolean := false;
begin
process_3_1_d : process (opcode) is
variable PC : integer := 0;
constant effective_address : integer := 1;
variable executing : boolean := true;
begin
-- code from book:
if opcode = halt_opcode then
PC := effective_address;
executing := false;
halt_indicator <= true;
end if;
-- end of code from book
end process process_3_1_d;
stimulus : process is
begin
opcode <= opcode_2 after 100 ns, halt_opcode after 200 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/integer-types/subprogram-dynamic-type.vhdl | 4 | 546 | entity test is
end test;
architecture only of test is
procedure proc ( constant l : in integer;
constant r : in integer ) is
type dyn is range l to r;
constant x : dyn;
begin
if r = 3 then
assert x = 1 report "TEST FAILED" severity FAILURE;
elsif r = 42 then
assert x = 0 report "TEST FAILED" severity FAILURE;
end if;
end proc;
begin -- only
doit: process
begin -- process doit
proc( 1, 3 );
proc( 0, 42 );
report "TEST PASSED";
wait;
end process doit;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1117.vhd | 4 | 2027 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1117.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01117ent IS
END c06s05b00x00p03n01i01117ent;
ARCHITECTURE c06s05b00x00p03n01i01117arch OF c06s05b00x00p03n01i01117ent IS
subtype FIVE is INTEGER range 1 to 5;
type ABASE is array (FIVE range <>) of BOOLEAN;
subtype A1 is ABASE (FIVE);
function F (i: integer) return A1 is
variable ARR : A1;
begin
return ARR;
end F;
BEGIN
TESTING: PROCESS
variable V1 : A1;
BEGIN
V1(2 to 4) := F(5)(2 to 4);
assert NOT(V1(2 to 4) = (false,false,false))
report "***PASSED TEST: c06s05b00x00p03n01i01117"
severity NOTE;
assert (V1(2 to 4) = (false,false,false))
report "***FAILED TEST: c06s05b00x00p03n01i01117 - Prefix of a slice number must be a one-dimensional array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01117arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2019.vhd | 4 | 1806 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2019.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02019ent IS
END c07s02b04x00p01n01i02019ent;
ARCHITECTURE c07s02b04x00p01n01i02019arch OF c07s02b04x00p01n01i02019ent IS
BEGIN
TESTING: PROCESS
type array_type is array (1 to 10) of integer;
variable x : array_type := (1,2,3,4,5,6,7,8,9,10);
variable y : array_type := (1,2,3,4,5,6,7,8,9,0);
variable z : array_type;
BEGIN
z := (x + y); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02019 - The adding operators are predefined only for numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02019arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1411.vhd | 4 | 1618 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1411.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b01x00p01n01i01411ent IS
END c08s05b01x00p01n01i01411ent;
ARCHITECTURE c08s05b01x00p01n01i01411arch OF c08s05b01x00p01n01i01411ent IS
BEGIN
TESTING: PROCESS
type A1 is array (1 to 15) of integer;
variable XC : A1;
BEGIN
XC (4 to 1) := 4321;
assert FALSE
report "***PASSED TEST: c08s05b01x00p01n01i01411"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s05b01x00p01n01i01411arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/piston.vhd | 4 | 1253 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.mechanical_systems.all;
entity piston is
port ( terminal motion : translational );
end entity piston;
--------------------------------------------------------------
architecture simple of piston is
constant mass : real := 10.0;
quantity resultant_displacement across applied_force through motion;
begin
applied_force == mass * resultant_displacement'dot'dot;
end architecture simple;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug18810/OISC_SUBLEQ.vhd | 3 | 9815 | library ieee;
use ieee.std_logic_1164.all;
use work.DMEM_PKG.all;
package OISC_SUBLEQ_PKG is
component OISC_SUBLEQ is
generic (
log2PADDR : integer range 0 to integer'high := 8;
log2DADDR : integer range 0 to integer'high := 4;
DW : integer range 1 to integer'high := 8;
ZERO : boolean := false;
LVT_DMEM : boolean := true;
ASYNC : boolean := false
);
port (
iPCLK : in std_logic;
iPWE : in std_logic;
iPADDR : in integer range 0 to 2**log2PADDR-1;
iPINST : in std_logic_vector(log2DADDR+log2DADDR+log2PADDR-1 downto 0);
oPINST : out std_logic_vector(log2DADDR+log2DADDR+log2PADDR-1 downto 0);
iDCLK : in std_logic;
iDWE : in std_logic;
iDADDR : in integer range 0 to 2**log2DADDR-1;
iDDATA : in std_logic_vector(DW-1 downto 0);
oDDATA : out std_logic_vector(DW-1 downto 0);
iCLR : in std_logic;
iCLK : in std_logic;
iACT : in std_logic;
oACT : out std_logic;
oPC : out integer range 0 to 2**log2PADDR-1;
oLEQ : out std_logic
);
end component OISC_SUBLEQ;
constant cOISC_SUBLEQ_PW_LATENCY : integer := 1;
constant cOISC_SUBLEQ_PR_LATENCY : integer := 0;
constant cOISC_SUBLEQ_LATENCY : integer := 1;
pure function fOISC_SUBLEQ_DW_LATENCY (
iLVT_DMEM : boolean
) return integer;
pure function fOISC_SUBLEQ_DR_LATENCY (
iLVT_DMEM : boolean
) return integer;
end package OISC_SUBLEQ_PKG;
package body OISC_SUBLEQ_PKG is
pure function fOISC_SUBLEQ_DW_LATENCY (
iLVT_DMEM : boolean
) return integer is
begin
if (iLVT_DMEM = true) then
return cDMEM_DW_LATENCY;
else
return 1;
end if;
end function fOISC_SUBLEQ_DW_LATENCY;
pure function fOISC_SUBLEQ_DR_LATENCY (
iLVT_DMEM : boolean
) return integer is
begin
if (iLVT_DMEM = true) then
return cDMEM_DR_LATENCY;
else
return 0;
end if;
end function fOISC_SUBLEQ_DR_LATENCY;
end package body OISC_SUBLEQ_PKG;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.DMEM_PKG.all;
entity OISC_SUBLEQ is
generic (
log2PADDR : integer range 0 to integer'high := 8;
log2DADDR : integer range 0 to integer'high := 4;
DW : integer range 1 to integer'high := 8;
ZERO : boolean := true;
LVT_DMEM : boolean := true;
ASYNC : boolean := false
);
port (
iPCLK : in std_logic;
iPWE : in std_logic;
iPADDR : in integer range 0 to 2**log2PADDR-1;
iPINST : in std_logic_vector(log2DADDR+log2DADDR+log2PADDR-1 downto 0);
oPINST : out std_logic_vector(log2DADDR+log2DADDR+log2PADDR-1 downto 0);
iDCLK : in std_logic;
iDWE : in std_logic;
iDADDR : in integer range 0 to 2**log2DADDR-1;
iDDATA : in std_logic_vector(DW-1 downto 0);
oDDATA : out std_logic_vector(DW-1 downto 0);
iCLR : in std_logic;
iCLK : in std_logic;
iACT : in std_logic;
oACT : out std_logic;
oPC : out integer range 0 to 2**log2PADDR-1;
oLEQ : out std_logic
);
begin
-- RTL_SYNTHESIS OFF
A_DMEM_AR_LATENCY : assert (not (LVT_DMEM = true and cDMEM_AR_LATENCY /= 0))
report OISC_SUBLEQ'instance_name &
"cDMEM_AR_LATENCY =" & integer'image(cDMEM_AR_LATENCY)
severity warning;
A_DMEM_BW_LATENCY : assert (not (LVT_DMEM = true and cDMEM_BW_LATENCY /= 1))
report OISC_SUBLEQ'instance_name &
"cDMEM_BW_LATENCY =" & integer'image(cDMEM_BW_LATENCY)
severity warning;
A_DMEM_BR_LATENCY : assert (not (LVT_DMEM = true and cDMEM_BR_LATENCY /= 0))
report OISC_SUBLEQ'instance_name &
"cDMEM_BR_LATENCY =" & integer'image(cDMEM_BR_LATENCY)
severity warning;
-- RTL_SYNTHESIS ON
end entity OISC_SUBLEQ;
architecture TP of OISC_SUBLEQ is
type tIF is record
PMEM_oA : integer range 0 to 2**log2DADDR-1;
PMEM_oB : integer range 0 to 2**log2DADDR-1;
PMEM_oC : integer range 0 to 2**log2PADDR-1;
DMEM_oA : std_logic_vector(DW-1 downto 0);
DMEM_oB : std_logic_vector(DW-1 downto 0);
end record tIF;
signal s : tIF;
type t is record
ACT : std_logic;
SUB : std_logic_vector(DW-1 downto 0);
PC : integer range 0 to 2**log2PADDR-1;
LEQ : std_logic;
end record t;
constant c : t := (
ACT => '0',
SUB => (DW-1 downto 0 => '0'),
PC => 0,
LEQ => '0'
);
signal g : t;
signal r : t := c;
begin
B_BLOB : block is
type tPMEM is array (0 to 2**log2PADDR-1) of std_logic_vector(log2DADDR+log2DADDR+log2PADDR-1 downto 0);
signal aPMEM : tPMEM := (0 to 2**log2PADDR-1 => (log2DADDR+log2DADDR+log2PADDR-1 downto 0 => '0'));
signal gPMEM_oINST : std_logic_vector(log2DADDR+log2DADDR+log2PADDR-1 downto 0);
signal gPMEM_oA : std_logic_vector(log2DADDR-1 downto 0);
signal gPMEM_oB : std_logic_vector(log2DADDR-1 downto 0);
signal gPMEM_oC : std_logic_vector(log2PADDR-1 downto 0);
begin
P_PMEM_P : process (iPCLK)
begin
if (rising_edge(iPCLK)) then
if (iPWE = '1') then
aPMEM(iPADDR) <= iPINST;
end if;
end if;
end process P_PMEM_P;
oPINST <= aPMEM(iPADDR);
gPMEM_oINST <= aPMEM(r.PC);
gPMEM_oA <= gPMEM_oINST(log2DADDR+log2DADDR+log2PADDR-1 downto log2DADDR+log2PADDR);
gPMEM_oB <= gPMEM_oINST( log2DADDR+log2PADDR-1 downto log2PADDR);
gPMEM_oC <= gPMEM_oINST( log2PADDR-1 downto 0);
s.PMEM_oA <= to_integer(unsigned(gPMEM_oA));
s.PMEM_oB <= to_integer(unsigned(gPMEM_oB));
s.PMEM_oC <= to_integer(unsigned(gPMEM_oC));
G_LVT_DMEM : if (LVT_DMEM = true) generate
begin
U_DMEM : DMEM
generic map (
log2DADDR => log2DADDR,
DW => DW,
ZERO => ZERO
)
port map (
iDCLK => iDCLK,
iDWE => iDWE,
iDADDR => iDADDR,
iDDATA => iDDATA,
oDDATA => oDDATA,
iCLK => iCLK,
iAADDR => s.PMEM_oA,
oADATA => s.DMEM_oA,
iBWE => iACT,
iBADDR => s.PMEM_oB,
iBDATA => g.SUB,
oBDATA => s.DMEM_oB
);
end generate G_LVT_DMEM;
G_2W3R_DMEM : if (LVT_DMEM = false) generate
-- FIXME: ISE 13.2 does not support "protected"... :(
--type tDMEM is protected
-- procedure pWRITE(
-- iADDR : in integer range 0 to 2**log2DADDR-1;
-- iDATA : in std_logic_vector(DW-1 downto 0)
-- );
-- impure function fREAD(
-- iADDR : integer range 0 to 2**log2DADDR-1
-- ) return std_logic_vector;
--end protected tDMEM;
--type tDMEM is protected body
-- type tDMEM_PRIM is array (0 to 2**log2DADDR-1) of std_logic_vector(DW-1 downto 0);
-- variable aDMEM_PRIM : tDMEM_PRIM := (0 to 2**log2DADDR-1 => (DW-1 downto 0 => '0'));
-- procedure pWRITE(
-- iADDR : in integer range 0 to 2**log2DADDR-1;
-- iDATA : in std_logic_vector(DW-1 downto 0)
-- ) is
-- begin
-- aDMEM_PRIM(iADDR) := iDATA;
-- end procedure pWRITE;
-- impure function fREAD(
-- iADDR : integer range 0 to 2**log2DADDR-1
-- ) return std_logic_vector is
-- begin
-- return aDMEM_PRIM(iADDR);
-- end function fREAD;
--end protected body tDMEM;
--shared variable aDMEM : tDMEM;
-- FIXME: VHDL-93 shared variable does not provide mutex... :(
type tDMEM is array (0 to 2**log2DADDR-1) of std_logic_vector(DW-1 downto 0);
shared variable aDMEM : tDMEM := (0 to 2**log2DADDR-1 => (DW-1 downto 0 => '0'));
begin
P_DMEM_D : process (iDCLK)
begin
if (rising_edge(iDCLK)) then
if (iDWE = '1') then
--aDMEM.pWRITE(iDADDR, iDDATA);
aDMEM(iDADDR) := iDDATA;
end if;
end if;
end process P_DMEM_D;
--oDDATA <= (DW-1 downto 0 => '0') when (ZERO = true and iDADDR = 0) else aDMEM.fREAD(iDADDR);
--s.DMEM_oA <= (DW-1 downto 0 => '0') when (ZERO = true and s.PMEM_oA = 0) else aDMEM.fREAD(s.PMEM_oA);
--s.DMEM_oB <= (DW-1 downto 0 => '0') when (ZERO = true and s.PMEM_oB = 0) else aDMEM.fREAD(s.PMEM_oB);
oDDATA <= (DW-1 downto 0 => '0') when (ZERO = true and iDADDR = 0) else aDMEM(iDADDR);
s.DMEM_oA <= (DW-1 downto 0 => '0') when (ZERO = true and s.PMEM_oA = 0) else aDMEM(s.PMEM_oA);
s.DMEM_oB <= (DW-1 downto 0 => '0') when (ZERO = true and s.PMEM_oB = 0) else aDMEM(s.PMEM_oB);
-- FIXME: This DMEM write back is kludge... :(
P_DMEM_WRITE_BACK : process (iCLK)
begin
if (rising_edge(iCLK)) then
if (iACT = '1') then
--aDMEM.pWRITE(s.PMEM_oB, g.SUB);
aDMEM(s.PMEM_oB) := g.SUB;
end if;
end if;
end process P_DMEM_WRITE_BACK;
end generate G_2W3R_DMEM;
end block B_BLOB;
P_COMB : process (iACT, r, s)
variable v : t := c;
pure function fSUB (
iA : std_logic_vector(DW-1 downto 0);
iB : std_logic_vector(DW-1 downto 0)
) return std_logic_vector is
variable vSUB : signed(DW-1 downto 0);
begin
-- FIXME: Consider th3 borrow?
vSUB := signed(iB) - signed(iA);
return std_logic_vector(vSUB);
end function fSUB;
begin
if (iACT = '1') then
v.ACT := '1';
v.SUB := fSUB(s.DMEM_oA, s.DMEM_oB);
if (signed(v.SUB) <= 0) then
v.PC := s.PMEM_oC;
v.LEQ := '1';
else
if (r.PC >= 2**log2PADDR-1) then
v.PC := 0;
else
v.PC := r.PC + 1;
end if;
v.LEQ := '0';
end if;
else
v.ACT := '0';
v.SUB := r.SUB;
v.PC := r.PC;
v.LEQ := r.LEQ;
end if;
g <= v;
oACT <= r.ACT;
oPC <= r.PC;
oLEQ <= r.LEQ;
end process P_COMB;
G_ASYNC : if (ASYNC = true) generate
begin
P_SEQ : process (iCLR, iCLK)
begin
if (iCLR = '1') then
r <= c;
elsif (rising_edge(iCLK)) then
r <= g;
end if;
end process P_SEQ;
end generate G_ASYNC;
G_SYNC : if (ASYNC = false) generate
begin
P_SEQ : process (iCLK)
begin
if (rising_edge(iCLK)) then
if (iCLR = '1') then
r <= c;
else
r <= g;
end if;
end if;
end process P_SEQ;
end generate G_SYNC;
end architecture TP;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2134.vhd | 4 | 2282 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2134.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02134ent IS
END c07s02b04x00p21n01i02134ent;
ARCHITECTURE c07s02b04x00p21n01i02134arch OF c07s02b04x00p21n01i02134ent IS
TYPE simple_record is record
data_1 : integer;
data_2 : integer;
end record;
TYPE record_v is array (integer range <>) of simple_record;
SUBTYPE record_null is record_v (1 to 0);
SUBTYPE record_1 is record_v (1 to 1);
BEGIN
TESTING: PROCESS
variable result : record_1;
variable l_operand : simple_record := (12,34) ;
variable r_operand : record_null;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result(1) = (12,34) )
report "***PASSED TEST: c07s02b04x00p21n01i02134"
severity NOTE;
assert ( result(1) = (12,34) )
report "***FAILED TEST: c07s02b04x00p21n01i02134 - Concatenation of null and RECORD element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02134arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2092.vhd | 4 | 2650 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2092.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02092ent IS
END c07s02b04x00p20n01i02092ent;
ARCHITECTURE c07s02b04x00p20n01i02092arch OF c07s02b04x00p20n01i02092ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4_up is boolean_v (1 to 4);
SUBTYPE boolean_8_up is boolean_v (1 to 8);
SUBTYPE boolean_4_dwn is boolean_v (4 downto 1);
BEGIN
TESTING: PROCESS
variable l_operand : boolean_4_up := (true, true, false, false);
variable r_operand : boolean_4_dwn:= (false, false, true, true);
variable result : boolean_8_up;
BEGIN
result := l_operand & r_operand;
assert ( result (1) = true )
report "result (1) /= true" severity FAILURE;
assert ( result (4) = false )
report "result (4) /= false" severity FAILURE;
assert ( result (5) = false )
report "result (5) /= false" severity FAILURE;
assert ( result (8) = true )
report "result (8) /= true" severity FAILURE;
assert NOT((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
report "***PASSED TEST: c07s02b04x00p20n01i02092"
severity NOTE;
assert ((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
report "***FAILED TEST: c07s02b04x00p20n01i02092 - Concatenated array should be ascending and the left bound is that of the first operand."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02092arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2082.vhd | 4 | 2074 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2082.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02082ent IS
END c07s02b04x00p20n01i02082ent;
ARCHITECTURE c07s02b04x00p20n01i02082arch OF c07s02b04x00p20n01i02082ent IS
TYPE real_vector is array (INTEGER range <>) of REAL;
BEGIN
TESTING: PROCESS
VARIABLE target : real_vector (1 to 7) ;
VARIABLE slice_1 : real_vector (1 to 4) := (1.0,2.0,3.0,4.0);
VARIABLE slice_2 : real_vector (-2 to 4) :=
(5.0,6.0,7.0,8.0,9.0,10.0,11.0);
BEGIN
target := slice_1 ( 1 to 3 ) & slice_2 ( -1 to 2 );
assert NOT(target=(1.0,2.0,3.0,6.0,7.0,8.0,9.0))
report "***PASSED TEST: c07s02b04x00p20n01i02082"
severity NOTE;
assert (target=(1.0,2.0,3.0,6.0,7.0,8.0,9.0))
report "***FAILED TEST: c07s02b04x00p20n01i02082 - One dimensional array of REAL type concatenation into a larger ARRAY failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02082arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_13.vhd | 4 | 1502 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_13 is
end entity inline_13;
----------------------------------------------------------------
architecture test of inline_13 is
begin
process_3_b : process is
-- code from book:
type array1 is array (1 to 100) of integer;
type array2 is array (100 downto 1) of integer;
variable a1 : array1;
variable a2 : array2;
-- end of code from book
begin
a1(11 to 20) := a1(11 to 20);
a2(50 downto 41) := a2(50 downto 41);
a1(10 to 1) := a1(10 to 1);
a2(1 downto 10) := a2(1 downto 10);
a1(10 downto 1) := a1(10 downto 1); -- illegal
a2(1 to 10) := a2(1 to 10); -- illegal;
wait;
end process process_3_b;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc987.vhd | 4 | 46990 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc987.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p06n01i00987pkg is
------------------------------------USING ONLY WHITE MATTER---------------------------------
--------------------------------------------------------------------------------------------
---ACCESS TYPE FROM STANDARD PACKAGE
type boolean_ptr is access boolean ; --simple boolean type
type bit_ptr is access bit ; --simple bit type
type char_ptr is access character; --simple character type
type severity_level_ptr is access severity_level; --simple severity type
type integer_ptr is access integer; --simple integer type
type real_ptr is access real; --simple real type
type time_ptr is access time; --simple time type
type natural_ptr is access natural; --simple natural type
type positive_ptr is access positive; --simple positive type
type string_ptr is access string; --simple string type
type bit_vector_ptr is access bit_vector; --simple bit_vector type
--------------------------------------------------------------------------------------------
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
---------------------------------------------------------------------------------------------
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
---------------------------------------------------------------------------------------------
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
---------------------------------------------------------------------------------------------
--CONSTRAINED ARRAY OF ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
---------------------------------------------------------------------------------------------
--UNCONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type s2boolean_vector is array (natural range <>,natural range <>) of boolean;
type s2bit_vector is array (natural range<>,natural range <>) of bit;
type s2char_vector is array (natural range<>,natural range <>) of character;
type s2severity_level_vector is array (natural range <>,natural range <>) of severity_level;
type s2integer_vector is array (natural range <>,natural range <>) of integer;
type s2real_vector is array (natural range <>,natural range <>) of real;
type s2time_vector is array (natural range <>,natural range <>) of time;
type s2natural_vector is array (natural range <>,natural range <>) of natural;
type s2positive_vector is array (natural range <>,natural range <>) of positive;
----------------------------------------------------------------------------------------------
--CONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type column is range 1 to 64;
type row is range 1 to 1024;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
-----------------------------------------------------------------------------------------------
--RECORD WITH FIELDS FROM STANDARD PACKAGE
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
-----------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS UNCONSTRAINT ARRAYS
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
-----------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS CONSTRAINT ARRAYS
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
-----------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
-----------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS OF ARRAY
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
-----------------------------------------------------------------------------------------------
type record_of_ptr is record
a:boolean_ptr ; --simple boolean type
b:bit_ptr; --simple bit type
c:char_ptr; --simple character type
e:severity_level_ptr; --simple severity type
f:integer_ptr; --simple integer type
g: real_ptr ; --simple real type
h:time_ptr; --simple time type
i: natural_ptr; --simple natural type
j:positive_ptr; --simple positive type
k: string_ptr; --simple string type
l: bit_vector_ptr; --simple bit_vector type
end record;
-----------------------------------------------------------------------------------------------
type record_of_records is record
a: record_std_package;
c: record_cons_array;
e: record_2cons_array;
g: record_cons_arrayofarray;
h: record_of_ptr;
i: record_array_st;
end record;
-----------------------------------------------------------------------------------------------
--ACCESS TYPES FOR ABOVE
-----------------------------------------------------------------------------------------------
type boolean_vector_ptr is access boolean_vector;
type severity_level_vector_ptr is access severity_level_vector;
type integer_vector_ptr is access integer_vector;
type real_vector_ptr is access real_vector;
type time_vector_ptr is access time_vector;
type natural_vector_ptr is access natural_vector;
type positive_vector_ptr is access positive_vector;
-----------------------------------------------------------------------------------------------
type boolean_vector_st_ptr is access boolean_vector_st;--(0 to 15);
type severity_level_vector_st_ptr is access severity_level_vector_st;--(0 to 15);
type integer_vector_st_ptr is access integer_vector_st;--(0 to 15);
type real_vector_st_ptr is access real_vector_st;--(0 to 15);
type time_vector_st_ptr is access time_vector_st;--(0 to 15);
type natural_vector_st_ptr is access natural_vector_st;--(0 to 15);
type positive_vector_st_ptr is access positive_vector_st;--(0 to 15);
-----------------------------------------------------------------------------------------------
type boolean_cons_vector_ptr is access boolean_cons_vector;
type severity_level_cons_vector_ptr is access severity_level_cons_vector;
type integer_cons_vector_ptr is access integer_cons_vector;
type real_cons_vector_ptr is access real_cons_vector;
type time_cons_vector_ptr is access time_cons_vector;
type natural_cons_vector_ptr is access natural_cons_vector;
type positive_cons_vector_ptr is access positive_cons_vector;
-----------------------------------------------------------------------------------------------
type boolean_cons_vectorofvector_ptr is access boolean_cons_vectorofvector;
type sev_lvl_cons_vecofvec_ptr is access severity_level_cons_vectorofvector;
type integer_cons_vectorofvector_ptr is access integer_cons_vectorofvector;
type real_cons_vectorofvector_ptr is access real_cons_vectorofvector;
type time_cons_vectorofvector_ptr is access time_cons_vectorofvector;
type natural_cons_vectorofvector_ptr is access natural_cons_vectorofvector;
type posi_cons_vecofvec_ptr is access positive_cons_vectorofvector;
-----------------------------------------------------------------------------------------------
type s2boolean_vector_ptr is access s2boolean_vector;
type s2bit_vector_ptr is access s2bit_vector;
type s2char_vector_ptr is access s2char_vector;
type s2severity_level_vector_ptr is access s2severity_level_vector;
type s2integer_vector_ptr is access s2integer_vector;
type s2real_vector_ptr is access s2real_vector;
type s2time_vector_ptr is access s2time_vector;
type s2positive_vector_ptr is access s2positive_vector;
-----------------------------------------------------------------------------------------------
type s2boolean_cons_vector_ptr is access s2boolean_cons_vector;
type s2bit_cons_vector_ptr is access s2bit_cons_vector;
type s2char_cons_vector_ptr is access s2char_cons_vector;
type s2sev_lvl_cons_vec_ptr is access s2severity_level_cons_vector;
type s2integer_cons_vector_ptr is access s2integer_cons_vector;
type s2real_cons_vector_ptr is access s2real_cons_vector;
type s2time_cons_vector_ptr is access s2time_cons_vector;
type s2natural_cons_vector_ptr is access s2natural_cons_vector;
type s2positive_cons_vector_ptr is access s2positive_cons_vector;
----------------------------------------------------------------------------------------------
type record_std_package_ptr is access record_std_package;
type record_cons_array_ptr is access record_cons_array;
type record_2cons_array_ptr is access record_2cons_array;
type record_cons_arrayofarray_ptr is access record_cons_arrayofarray;
type record_of_ptr_ptr is access record_of_ptr;
type record_of_records_ptr is access record_of_records;
type record_array_st_ptr is access record_array_st;
-----------------------------------------------------------------------------------------------
-------------------------USING PARTIAL GRAY & PARTIAL WHITE MATTER-----------------------------
type four_value is ('Z','0','1','X'); --enumerated type
type four_value_map is array(four_value) of boolean;
subtype binary is four_value range '0' to '1';
type four_value_vector is array (natural range <>) of four_value; --unconstraint array of
type byte is array(0 to 7) of bit;
subtype word is bit_vector(0 to 15); --constrained array
function resolution(i:in four_value_vector) return four_value; --bus resolution
subtype four_value_state is resolution four_value; --function type
type state_vector is array (natural range <>) of four_value_state; --unconstraint array of
constant size :integer := 63;
type primary_memory is array(0 to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:binary;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
subtype delay is integer range 1 to 10;
type four_value_ptr is access four_value;
type four_value_map_ptr is access four_value_map;
type binary_ptr is access binary;
type four_value_vector_ptr is access four_value_vector; --ennumerated type
type byte_ptr is access byte;
type word_ptr is access word;
type four_value_state_ptr is access four_value_state;
type state_vector_ptr is access state_vector; --type returned by resolu.
type primary_memory_ptr is access primary_memory;
type primary_memory_module_ptr is access primary_memory_module;
type whole_memory_ptr is access whole_memory;
type current_ptr is access current;
type resistance_ptr is access resistance;
type delay_ptr is access delay;
-------------------------------------------------------------------------------------------
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
--constant C33 : s2boolean_vector := ((true,true),(false,false));
--constant C34 : s2bit_vector := ((B"0011"),(B"1100"));
--constant C35 : s2char_vector := (('s','h'),('i','s'));
--constant C36 : s2severity_level_vector := ((note,error),(error,note));
--constant C37 : s2integer_vector := ((1,2,3,4),(4,3,2,1));
--constant C38 : s2real_vector := ((1.0,2.0,3.0,4.0),(4.0,3.0,2.0,1.0));
--constant C39 : s2time_vector := ((1 ns, 2 ns, 3 ns, 4 ns),(1 ns, 2 ns, 3 ns, 4 ns));
--constant C40 : s2positive_vector := ((1,2,3,4),(4,3,2,1));
constant C41 : s2boolean_cons_vector := (others =>(others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others =>(others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others =>(others => C6));
constant C47 : s2time_cons_vector := (others =>(others => C7));
constant C48 : s2natural_cons_vector := (others =>(others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
--constant C54 : record_of_ptr := (NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL);
--constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
--constant C55 : record_of_records := (C50,C51,C52,C53,C54,C54a);
constant C56 : four_value := 'Z';
constant C57 : four_value_map := (true,true,true,true);
constant C58 : binary := '0';
constant C59 : four_value_vector := ('1','0','1','0');
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C62 : four_value_state := 'Z';
constant C63 : state_vector := ('Z','Z','Z','Z');
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
end c06s03b00x00p06n01i00987pkg;
package body c06s03b00x00p06n01i00987pkg is
function resolution(i:in four_value_vector) return four_value is
variable temp :four_value := 'Z';
begin
return temp;
end;
end c06s03b00x00p06n01i00987pkg;
use work.c06s03b00x00p06n01i00987pkg.all;
ENTITY c06s03b00x00p06n01i00987ent IS
END c06s03b00x00p06n01i00987ent;
ARCHITECTURE c06s03b00x00p06n01i00987arch OF c06s03b00x00p06n01i00987ent IS
BEGIN
TESTING: PROCESS
variable var1 : boolean_ptr ;
variable var2 : bit_ptr ;
variable var3 : char_ptr ;
variable var4 : severity_level_ptr ;
variable var5 : integer_ptr ;
variable var6 : real_ptr ;
variable var7 : time_ptr ;
variable var8 : natural_ptr ;
variable var9 : positive_ptr ;
variable var10 : string_ptr ;
variable var11 : bit_vector_ptr ;
variable var12 : boolean_vector_ptr ;
variable var13 : severity_level_vector_ptr ;
variable var14 : integer_vector_ptr ;
variable var15 : real_vector_ptr ;
variable var16 : time_vector_ptr ;
variable var17 : natural_vector_ptr ;
variable var18 : positive_vector_ptr ;
variable var19 : boolean_cons_vector_ptr ;
variable var20 : severity_level_cons_vector_ptr ;
variable var21 : integer_cons_vector_ptr ;
variable var22 : real_cons_vector_ptr ;
variable var23 : time_cons_vector_ptr ;
variable var24 : natural_cons_vector_ptr ;
variable var25 : positive_cons_vector_ptr ;
variable var26 : boolean_cons_vectorofvector_ptr ;
variable var27 : sev_lvl_cons_vecofvec_ptr ;
variable var28 : integer_cons_vectorofvector_ptr ;
variable var29 : real_cons_vectorofvector_ptr ;
variable var30 : time_cons_vectorofvector_ptr ;
variable var31 : natural_cons_vectorofvector_ptr ;
variable var32 : posi_cons_vecofvec_ptr ;
-- variable var33 : s2boolean_vector_ptr ;
-- variable var34 : s2bit_vector_ptr ;
-- variable var35 : s2char_vector_ptr ;
-- variable var36 : s2severity_level_vector_ptr ;
-- variable var37 : s2integer_vector_ptr ;
-- variable var38 : s2real_vector_ptr ;
-- variable var39 : s2time_vector_ptr ;
-- variable var40 : s2positive_vector_ptr ;
variable var41 : s2boolean_cons_vector_ptr ;
variable var42 : s2bit_cons_vector_ptr ;
variable var43 : s2char_cons_vector_ptr ;
variable var44 : s2sev_lvl_cons_vec_ptr ;
variable var45 : s2integer_cons_vector_ptr ;
variable var46 : s2real_cons_vector_ptr ;
variable var47 : s2time_cons_vector_ptr ;
variable var48 : s2natural_cons_vector_ptr ;
variable var49 : s2positive_cons_vector_ptr ;
variable var50 : record_std_package_ptr ;
variable var51 : record_cons_array_ptr ;
variable var52 : record_2cons_array_ptr ;
variable var53 : record_cons_arrayofarray_ptr ;
variable var54 : record_of_ptr_ptr ;
variable var54a : record_array_st_ptr;
variable var55 : record_of_records_ptr ;
variable var56 : four_value_ptr ;
variable var57 : four_value_map_ptr ;
variable var58 : binary_ptr ;
variable var59 : four_value_vector_ptr ;
variable var60 : byte_ptr ;
variable var61 : word_ptr ;
variable var62 : four_value_state_ptr ;
variable var63 : state_vector_ptr ;
variable var64 : primary_memory_ptr ;
variable var65 : primary_memory_module_ptr;
variable var66 : whole_memory_ptr ;
variable var67 : current_ptr ;
variable var68 : resistance_ptr ;
variable var69 : delay_ptr ;
variable var70 : boolean_vector_st_ptr;
variable var71 : severity_level_vector_st_ptr;
variable var72 : integer_vector_st_ptr;
variable var73 : real_vector_st_ptr;
variable var74 : time_vector_st_ptr;
variable var75 : natural_vector_st_ptr;
variable var76 : positive_vector_st_ptr;
variable vari1 : boolean;
variable vari2 : bit;
variable vari3 : character;
variable vari4 : severity_level;
variable vari5 : integer;
variable vari6 : real;
variable vari7 : time;
variable vari8 : natural;
variable vari9 : positive;
variable vari10 : string(1 to 7);
variable vari11 : bit_vector(0 to 3);
variable vari12 : boolean_vector(0 to 1);
variable vari13 : severity_level_vector(0 to 1);
variable vari14 : integer_vector(0 to 3);
variable vari15 : real_vector(0 to 3);
variable vari16 : time_vector(0 to 3);
variable vari17 : natural_vector(0 to 3);
variable vari18 : positive_vector(0 to 3);
variable vari19 : boolean_cons_vector;
variable vari20 : severity_level_cons_vector;
variable vari21 : integer_cons_vector;
variable vari22 : real_cons_vector;
variable vari23 : time_cons_vector;
variable vari24 : natural_cons_vector;
variable vari25 : positive_cons_vector;
variable vari26 : boolean_cons_vectorofvector;
variable vari27 : severity_level_cons_vectorofvector;
variable vari28 : integer_cons_vectorofvector;
variable vari29 : real_cons_vectorofvector;
variable vari30 : time_cons_vectorofvector;
variable vari31 : natural_cons_vectorofvector;
variable vari32 : positive_cons_vectorofvector;
--variable vari33 : s2boolean_vector;
--variable vari34 : s2bit_vector;
--variable vari35 : s2char_vector;
--variable vari36 : s2severity_level_vector;
--variable vari37 : s2integer_vector;
--variable vari38 : s2real_vector;
--variable vari39 : s2time_vector;
--variable vari40 : s2positive_vector;
variable vari41 : s2boolean_cons_vector;
variable vari42 : s2bit_cons_vector;
variable vari43 : s2char_cons_vector;
variable vari44 : s2severity_level_cons_vector;
variable vari45 : s2integer_cons_vector;
variable vari46 : s2real_cons_vector;
variable vari47 : s2time_cons_vector;
variable vari48 : s2natural_cons_vector;
variable vari49 : s2positive_cons_vector;
variable vari50 : record_std_package;
variable vari51 : record_cons_array;
variable vari52 : record_2cons_array;
variable vari53 : record_cons_arrayofarray;
variable vari54 : record_of_ptr;
variable vari55 : record_of_records;
variable vari56 : four_value;
variable vari57 : four_value_map;
variable vari58 : binary;
variable vari59 : four_value_vector(0 to 3);
variable vari60 : byte;
variable vari61 : word;
variable vari62 : four_value_state;
variable vari63 : state_vector(0 to 3);
variable vari64 : primary_memory;
variable vari65 : primary_memory_module;
variable vari66 : whole_memory;
variable vari67 : current;
variable vari68 : resistance;
variable vari69 : delay;
variable vari70 : boolean_vector_st;
variable vari71 : severity_level_vector_st;
variable vari72 : integer_vector_st;
variable vari73 : real_vector_st;
variable vari74 : time_vector_st;
variable vari75 : natural_vector_st;
variable vari76 : positive_vector_st;
variable vari54a : record_array_st;
BEGIN
var1 := NEW boolean '(C1);
var2 := NEW bit '(C2);
var3 := NEW character '(C3);
var4 := NEW severity_level '(C4);
var5 := NEW integer '(C5);
var6 := NEW real '(C6);
var7 := NEW time '(C7);
var8 := NEW natural '(C8);
var9 := NEW positive '(C9);
var10 := NEW string '(C10);
var11 := NEW bit_vector '(C11);
var12 := NEW boolean_vector '(C12);
var13 := NEW severity_level_vector '(C13);
var14 := NEW integer_vector '(C14);
var15 := NEW real_vector '(C15);
var16 := NEW time_vector '(C16);
var17 := NEW natural_vector '(C17);
var18 := NEW positive_vector '(C18);
var19 := NEW boolean_cons_vector '(C19);
var20 := NEW severity_level_cons_vector '(C20);
var21 := NEW integer_cons_vector '(C21);
var22 := NEW real_cons_vector '(C22);
var23 := NEW time_cons_vector '(C23);
var24 := NEW natural_cons_vector '(C24);
var25 := NEW positive_cons_vector '(C25);
var26 := NEW boolean_cons_vectorofvector '(C26);
var27 := NEW severity_level_cons_vectorofvector '(C27);
var28 := NEW integer_cons_vectorofvector '(C28);
var29 := NEW real_cons_vectorofvector '(C29);
var30 := NEW time_cons_vectorofvector '(C30);
var31 := NEW natural_cons_vectorofvector '(C31);
var32 := NEW positive_cons_vectorofvector '(C32);
--var33 := NEW s2boolean_vector '(C33);
--var34 := NEW s2bit_vector '(C34);
--var35 := NEW s2char_vector '(C35);
--var36 := NEW s2severity_level_vector '(C36);
--var37 := NEW s2integer_vector '(C37);
--var38 := NEW s2real_vector '(C38);
--var39 := NEW s2time_vector '(C39);
--var40 := NEW s2positive_vector '(C40);
var41 := NEW s2boolean_cons_vector '(C41);
var42 := NEW s2bit_cons_vector '(C42);
var43 := NEW s2char_cons_vector '(C43);
var44 := NEW s2severity_level_cons_vector '(C44);
var45 := NEW s2integer_cons_vector '(C45);
var46 := NEW s2real_cons_vector '(C46);
var47 := NEW s2time_cons_vector '(C47);
var48 := NEW s2natural_cons_vector '(C48);
var49 := NEW s2positive_cons_vector '(C49);
var50 := NEW record_std_package '(C50);
var51 := NEW record_cons_array '(C51);
var52 := NEW record_2cons_array '(C52);
var53 := NEW record_cons_arrayofarray '(C53);
--var54 := NEW record_of_ptr '(C54);
--var54a := NEW record_array_st '(C54a);
--var55 := NEW record_of_records '(C55);
var56 := NEW four_value '(C56);
var57 := NEW four_value_map '(C57);
var58 := NEW binary '(C58);
var59 := NEW four_value_vector '(C59);
var60 := NEW byte '(C60);
var61 := NEW word '(C61);
var62 := NEW four_value_state '(C62);
var63 := NEW state_vector '(C63);
var64 := NEW primary_memory '(C64);
var65 := NEW primary_memory_module '(C65);
var66 := NEW whole_memory '(C66);
var67 := NEW current '(C67);
var68 := NEW resistance '(C68);
var69 := NEW delay '(C69);
var70 := NEW boolean_vector_st '(C70);
var71 := NEW severity_level_vector_st '(C71);
var72 := NEW integer_vector_st '(C72);
var73 := NEW real_vector_st '(C73);
var74 := NEW time_vector_st '(C74);
var75 := NEW natural_vector_st '(C75);
var76 := NEW positive_vector_st '(C76);
vari1 := var1.all;
vari2 := var2.all;
vari3 := var3.all;
vari4 := var4.all;
vari5 := var5.all;
vari6 := var6.all;
vari7 := var7.all;
vari8 := var8.all;
vari9 := var9.all;
vari10 := var10.all;
vari11 := var11.all;
vari12 := var12.all;
vari13 := var13.all;
vari14 := var14.all;
vari15 := var15.all;
vari16 := var16.all;
vari17 := var17.all;
vari18 := var18.all;
vari19 := var19.all;
vari20 := var20.all;
vari21 := var21.all;
vari22 := var22.all;
vari23 := var23.all;
vari24 := var24.all;
vari25 := var25.all;
vari26 := var26.all;
vari27 := var27.all;
vari28 := var28.all;
vari29 := var29.all;
vari30 := var30.all;
vari31 := var31.all;
vari32 := var32.all;
--vari33 := var33.all;
--vari34 := var34.all;
--vari35 := var35.all;
--vari36 := var36.all;
--vari37 := var37.all;
--vari38 := var38.all;
--vari39 := var39.all;
--vari40 := var40.all;
vari41 := var41.all;
vari42 := var42.all;
vari43 := var43.all;
vari44 := var44.all;
vari45 := var45.all;
vari46 := var46.all;
vari47 := var47.all;
vari48 := var48.all;
vari49 := var49.all;
vari50 := var50.all;
vari51 := var51.all;
vari52 := var52.all;
vari53 := var53.all;
--vari54 := var54.all;
--vari55 := var55.all;
vari56 := var56.all;
vari57 := var57.all;
vari58 := var58.all;
vari59 := var59.all;
vari60 := var60.all;
vari61 := var61.all;
vari62 := var62.all;
vari63 := var63.all;
vari64 := var64.all;
vari65 := var65.all;
vari66 := var66.all;
vari67 := var67.all;
vari68 := var68.all;
vari69 := var69.all;
vari70 := var70.all;
vari71 := var71.all;
vari72 := var72.all;
vari73 := var73.all;
vari74 := var74.all;
vari75 := var75.all;
vari76 := var76.all;
--vari54a := var54a.all;
ASSERT vari1= C1 report "Improper Assignment of vari1" SEVERITY FAILURE;
ASSERT vari2 = C2 report "Improper Assignment of vari2" SEVERITY FAILURE;
ASSERT vari3 = C3 report "Improper Assignment of vari3" SEVERITY FAILURE;
ASSERT vari4 = C4 report "Improper Assignment of vari4" SEVERITY FAILURE;
ASSERT vari5 = C5 report "Improper Assignment of vari5" SEVERITY FAILURE;
ASSERT vari6 = C6 report "Improper Assignment of vari6" SEVERITY FAILURE;
ASSERT vari7 = C7 report "Improper Assignment of vari7" SEVERITY FAILURE;
ASSERT vari8 = C8 report "Improper Assignment of vari8" SEVERITY FAILURE;
ASSERT vari9 = C9 report "Improper Assignment of vari9" SEVERITY FAILURE;
ASSERT vari10 = C10 report "Improper Assignment of vari10" SEVERITY FAILURE;
ASSERT vari11 = C11 report "Improper Assignment of vari11" SEVERITY FAILURE;
ASSERT vari12 = C12 report "Improper Assignment of vari12" SEVERITY FAILURE;
ASSERT vari13 = C13 report "Improper Assignment of vari13" SEVERITY FAILURE;
ASSERT vari14 = C14 report "Improper Assignment of vari14" SEVERITY FAILURE;
ASSERT vari15 = C15 report "Improper Assignment of vari15" SEVERITY FAILURE;
ASSERT vari16 = C16 report "Improper Assignment of vari16" SEVERITY FAILURE;
ASSERT vari17 = C17 report "Improper Assignment of vari17" SEVERITY FAILURE;
ASSERT vari18 = C18 report "Improper Assignment of vari18" SEVERITY FAILURE;
ASSERT vari19 = C19 report "Improper Assignment of vari19" SEVERITY FAILURE;
ASSERT vari20 = C20 report "Improper Assignment of vari20" SEVERITY FAILURE;
ASSERT vari21 = C21 report "Improper Assignment of vari21" SEVERITY FAILURE;
ASSERT vari22 = C22 report "Improper Assignment of vari22" SEVERITY FAILURE;
ASSERT vari23 = C23 report "Improper Assignment of vari23" SEVERITY FAILURE;
ASSERT vari24 = C24 report "Improper Assignment of vari24" SEVERITY FAILURE;
ASSERT vari25 = C25 report "Improper Assignment of vari25" SEVERITY FAILURE;
ASSERT vari26 = C26 report "Improper Assignment of vari26" SEVERITY FAILURE;
ASSERT vari27 = C27 report "Improper Assignment of vari27" SEVERITY FAILURE;
ASSERT vari28 = C28 report "Improper Assignment of vari28" SEVERITY FAILURE;
ASSERT vari29 = C29 report "Improper Assignment of vari29" SEVERITY FAILURE;
ASSERT vari30 = C30 report "Improper Assignment of vari30" SEVERITY FAILURE;
ASSERT vari31 = C31 report "Improper Assignment of vari31" SEVERITY FAILURE;
ASSERT vari32 = C32 report "Improper Assignment of vari32" SEVERITY FAILURE;
--ASSERT vari33 = C33 report "Improper Assignment of vari33" SEVERITY FAILURE;
--ASSERT vari34 = C34 report "Improper Assignment of vari34" SEVERITY FAILURE;
--ASSERT vari35 = C35 report "Improper Assignment of vari35" SEVERITY FAILURE;
--ASSERT vari36 = C36 report "Improper Assignment of vari36" SEVERITY FAILURE;
--ASSERT vari37 = C37 report "Improper Assignment of vari37" SEVERITY FAILURE;
--ASSERT vari38 = C38 report "Improper Assignment of vari38" SEVERITY FAILURE;
--ASSERT vari39 = C39 report "Improper Assignment of vari39" SEVERITY FAILURE;
--ASSERT vari40 = C40 report "Improper Assignment of vari40" SEVERITY FAILURE;
ASSERT vari41 = C41 report "Improper Assignment of vari41" SEVERITY FAILURE;
ASSERT vari42 = C42 report "Improper Assignment of vari42" SEVERITY FAILURE;
ASSERT vari43 = C43 report "Improper Assignment of vari43" SEVERITY FAILURE;
ASSERT vari44 = C44 report "Improper Assignment of vari44" SEVERITY FAILURE;
ASSERT vari45 = C45 report "Improper Assignment of vari45" SEVERITY FAILURE;
ASSERT vari46 = C46 report "Improper Assignment of vari46" SEVERITY FAILURE;
ASSERT vari47 = C47 report "Improper Assignment of vari47" SEVERITY FAILURE;
ASSERT vari48 = C48 report "Improper Assignment of vari48" SEVERITY FAILURE;
ASSERT vari49 = C49 report "Improper Assignment of vari49" SEVERITY FAILURE;
ASSERT vari50 = C50 report "Improper Assignment of vari50" SEVERITY FAILURE;
ASSERT vari51 = C51 report "Improper Assignment of vari51" SEVERITY FAILURE;
ASSERT vari52 = C52 report "Improper Assignment of vari52" SEVERITY FAILURE;
ASSERT vari53 = C53 report "Improper Assignment of vari53" SEVERITY FAILURE;
--ASSERT vari54 = C54 report "Improper Assignment of vari54" SEVERITY FAILURE;
--ASSERT vari54a = C54a report "Improper Assignment of vari54a" SEVERITY FAILURE;
--ASSERT vari55 = C55 report "Improper Assignment of vari55" SEVERITY FAILURE;
ASSERT vari56 = C56 report "Improper Assignment of vari56" SEVERITY FAILURE;
ASSERT vari57 = C57 report "Improper Assignment of vari57" SEVERITY FAILURE;
ASSERT vari58 = C58 report "Improper Assignment of vari58" SEVERITY FAILURE;
ASSERT vari59 = C59 report "Improper Assignment of vari59" SEVERITY FAILURE;
ASSERT vari60 = C60 report "Improper Assignment of vari60" SEVERITY FAILURE;
ASSERT vari61 = C61 report "Improper Assignment of vari61" SEVERITY FAILURE;
ASSERT vari62 = C62 report "Improper Assignment of vari62" SEVERITY FAILURE;
ASSERT vari63 = C63 report "Improper Assignment of vari63" SEVERITY FAILURE;
ASSERT vari64 = C64 report "Improper Assignment of vari64" SEVERITY FAILURE;
ASSERT vari65 = C65 report "Improper Assignment of vari65" SEVERITY FAILURE;
ASSERT vari66 = C66 report "Improper Assignment of vari66" SEVERITY FAILURE;
ASSERT vari67 = C67 report "Improper Assignment of vari67" SEVERITY FAILURE;
ASSERT vari68 = C68 report "Improper Assignment of vari68" SEVERITY FAILURE;
ASSERT vari69 = C69 report "Improper Assignment of vari69" SEVERITY FAILURE;
ASSERT vari70 = C70 report "Improper Assignment of vari70" SEVERITY FAILURE;
ASSERT vari71 = C71 report "Improper Assignment of vari71" SEVERITY FAILURE;
ASSERT vari72 = C72 report "Improper Assignment of vari72" SEVERITY FAILURE;
ASSERT vari73 = C73 report "Improper Assignment of vari73" SEVERITY FAILURE;
ASSERT vari74 = C74 report "Improper Assignment of vari74" SEVERITY FAILURE;
ASSERT vari74 = C74 report "Improper Assignment of vari74" SEVERITY FAILURE;
ASSERT vari75 = C75 report "Improper Assignment of vari75" SEVERITY FAILURE;
ASSERT vari76 = C76 report "Improper Assignment of vari76" SEVERITY FAILURE;
assert NOT( vari1 = C1 and
vari2 = C2 and
vari3 = C3 and
vari4 = C4 and
vari5 = C5 and
vari6 = C6 and
vari7 = C7 and
vari8 = C8 and
vari9 = C9 and
vari10 = C10 and
vari11 = C11 and
vari12 = C12 and
vari13 = C13 and
vari14 = C14 and
vari15 = C15 and
vari16 = C16 and
vari17 = C17 and
vari18 = C18 and
vari19 = C19 and
vari20 = C20 and
vari21 = C21 and
vari22 = C22 and
vari23 = C23 and
vari24 = C24 and
vari25 = C25 and
vari26 = C26 and
vari27 = C27 and
vari28 = C28 and
vari29 = C29 and
vari30 = C30 and
vari31 = C31 and
vari32 = C32 and
-- vari33 = C33 and
-- vari34 = C34 and
-- vari35 = C35 and
-- vari36 = C36 and
-- vari37 = C37 and
-- vari38 = C38 and
-- vari39 = C39 and
-- vari40 = C40 and
vari41 = C41 and
vari42 = C42 and
vari43 = C43 and
vari44 = C44 and
vari45 = C45 and
vari46 = C46 and
vari47 = C47 and
vari48 = C48 and
vari49 = C49 and
vari50 = C50 and
vari51 = C51 and
vari52 = C52 and
vari53 = C53 and
-- vari54 = C54 and
-- vari54a = C54a and
-- vari55 = C55 and
vari56 = C56 and
vari57 = C57 and
vari58 = C58 and
vari59 = C59 and
vari60 = C60 and
vari61 = C61 and
vari62 = C62 and
vari63 = C63 and
vari64 = C64 and
vari65 = C65 and
vari66 = C66 and
vari67 = C67 and
vari68 = C68 and
vari69 = C69 and
vari70 = C70 and
vari71 = C71 and
vari72 = C72 and
vari73 = C73 and
vari74 = C74 and
vari75 = C75 and
vari76 = C76 )
report "***PASSED TEST: c06s03b00x00p06n01i00987"
severity NOTE;
assert ( vari1 = C1 and
vari2 = C2 and
vari3 = C3 and
vari4 = C4 and
vari5 = C5 and
vari6 = C6 and
vari7 = C7 and
vari8 = C8 and
vari9 = C9 and
vari10 = C10 and
vari11 = C11 and
vari12 = C12 and
vari13 = C13 and
vari14 = C14 and
vari15 = C15 and
vari16 = C16 and
vari17 = C17 and
vari18 = C18 and
vari19 = C19 and
vari20 = C20 and
vari21 = C21 and
vari22 = C22 and
vari23 = C23 and
vari24 = C24 and
vari25 = C25 and
vari26 = C26 and
vari27 = C27 and
vari28 = C28 and
vari29 = C29 and
vari30 = C30 and
vari31 = C31 and
vari32 = C32 and
-- vari33 = C33 and
-- vari34 = C34 and
-- vari35 = C35 and
-- vari36 = C36 and
-- vari37 = C37 and
-- vari38 = C38 and
-- vari39 = C39 and
-- vari40 = C40 and
vari41 = C41 and
vari42 = C42 and
vari43 = C43 and
vari44 = C44 and
vari45 = C45 and
vari46 = C46 and
vari47 = C47 and
vari48 = C48 and
vari49 = C49 and
vari50 = C50 and
vari51 = C51 and
vari52 = C52 and
vari53 = C53 and
-- vari54 = C54 and
-- vari54a = C54a and
-- vari55 = C55 and
vari56 = C56 and
vari57 = C57 and
vari58 = C58 and
vari59 = C59 and
vari60 = C60 and
vari61 = C61 and
vari62 = C62 and
vari63 = C63 and
vari64 = C64 and
vari65 = C65 and
vari66 = C66 and
vari67 = C67 and
vari68 = C68 and
vari69 = C69 and
vari70 = C70 and
vari71 = C71 and
vari72 = C72 and
vari73 = C73 and
vari74 = C74 and
vari75 = C75 and
vari76 = C76 )
report "***FAILED TEST: c06s03b00x00p06n01i00987 - Prefix of a selected name used to denote an object designated by an access value should be an access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p06n01i00987arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc163.vhd | 4 | 2107 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc163.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p20n01i00163pkg is
procedure P1 (p : in integer := 0; r: inout integer);
end c04s03b02x02p20n01i00163pkg;
package body c04s03b02x02p20n01i00163pkg is
procedure P1 (p : in integer := 0; r: inout integer) is
begin
r := p / 3 ;
end;
end c04s03b02x02p20n01i00163pkg;
use work.c04s03b02x02p20n01i00163pkg.all;
ENTITY c04s03b02x02p20n01i00163ent IS
END c04s03b02x02p20n01i00163ent;
ARCHITECTURE c04s03b02x02p20n01i00163arch OF c04s03b02x02p20n01i00163ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 1;
BEGIN
P1 (r => x); -- No_failure_here
-- no association for p
assert NOT( x=0 )
report "***PASSED TEST: c04s03b02x02p20n01i00163"
severity NOTE;
assert ( x=0 )
report "***FAILED TEST: c04s03b02x02p20n01i00163 - Defualt value in an association list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p20n01i00163arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc8.vhd | 4 | 1829 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc8.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p08n01i00008ent IS
END c04s01b00x00p08n01i00008ent;
ARCHITECTURE c04s01b00x00p08n01i00008arch OF c04s01b00x00p08n01i00008ent IS
BEGIN
TESTING: PROCESS
type A1 is array (1 to 1) of BOOLEAN;
type A2 is array (1 to 1) of BOOLEAN;
variable V7: A1;
variable V8: A2;
BEGIN
if V7 = V8 then -- Failure_here
-- ERROR - SEMANTIC ERROR: OPERANDS OF = INCOMPATIBLE IN TYPE
null ;
end if;
assert FALSE
report "***FAILED TEST: c04s01b00x00p08n01i00008 - Types are different and hence incompatible."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p08n01i00008arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd | 4 | 5210 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package bus_monitor_pkg is
type stats_type is record
ifetch_freq, write_freq, read_freq : real;
end record stats_type;
component bus_monitor is
generic ( verbose, dump_stats : boolean := false );
port ( mem_req, ifetch, write : in bit;
bus_stats : out stats_type );
end component bus_monitor;
end package bus_monitor_pkg;
use work.bus_monitor_pkg.all;
entity bus_monitor is
generic ( verbose, dump_stats : boolean := false );
port ( mem_req, ifetch, write : in bit;
bus_stats : out stats_type );
end entity bus_monitor;
architecture general_purpose of bus_monitor is
begin
access_monitor : process is
variable access_count, ifetch_count,
write_count, read_count : natural := 0;
use std.textio;
variable L : textio.line;
begin
wait until mem_req = '1';
if ifetch = '1' then
ifetch_count := ifetch_count + 1;
if verbose then
textio.write(L, string'("Ifetch"));
textio.writeline(textio.output, L);
end if;
elsif write = '1' then
write_count := write_count + 1;
if verbose then
textio.write(L, string'("Write"));
textio.writeline(textio.output, L);
end if;
else
read_count := read_count + 1;
if verbose then
textio.write(L, string'("Read"));
textio.writeline(textio.output, L);
end if;
end if;
access_count := access_count + 1;
bus_stats.ifetch_freq <= real(ifetch_count) / real(access_count);
bus_stats.write_freq <= real(write_count) / real(access_count);
bus_stats.read_freq <= real(read_count) / real(access_count);
if dump_stats and access_count mod 5 = 0 then
textio.write(L, string'("Ifetch frequency = "));
textio.write(L, real(ifetch_count) / real(access_count));
textio.writeline(textio.output, L);
textio.write(L, string'("Write frequency = "));
textio.write(L, real(write_count) / real(access_count));
textio.writeline(textio.output, L);
textio.write(L, string'("Read frequency = "));
textio.write(L, real(read_count) / real(access_count));
textio.writeline(textio.output, L);
end if;
end process access_monitor;
end architecture general_purpose;
-- code from book (in text)
entity computer_system is
generic ( instrumented : boolean := false );
port ( -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end entity computer_system;
-- end code from book
-- code from book
architecture block_level of computer_system is
-- . . . -- type and component declarations for cpu and memory, etc.
signal clock : bit; -- the system clock
signal mem_req : bit; -- cpu access request to memory
signal ifetch : bit; -- indicates access is to fetch an instruction
signal write : bit; -- indicates access is a write
-- . . . -- other signal declarations
begin
-- . . . -- component instances for cpu and memory, etc.
instrumentation : if instrumented generate
use work.bus_monitor_pkg;
signal bus_stats : bus_monitor_pkg.stats_type;
begin
cpu_bus_monitor : component bus_monitor_pkg.bus_monitor
port map ( mem_req, ifetch, write, bus_stats );
end generate instrumentation;
-- not in book
stimulus : process is
begin
ifetch <= '1'; write <= '0';
mem_req <= '1', '0' after 10 ns;
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '1';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
wait;
end process stimulus;
-- end not in book
end architecture block_level;
-- end code from book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2444.vhd | 4 | 1778 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2444.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02444ent IS
type idx is range 0 to 15;
type aray is array (idx) of positive;
END c07s03b02x02p01n01i02444ent;
ARCHITECTURE c07s03b02x02p01n01i02444arch OF c07s03b02x02p01n01i02444ent IS
signal sig : aray;
BEGIN
TESTING: PROCESS
BEGIN
sig <= (others => 0);
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s03b02x02p01n01i02444 - An aggregate of a one-dimensional array type the expression of each element association must be of the element type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02444arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1173.vhd | 4 | 1734 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1173.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p06n01i01173ent IS
END c06s06b00x00p06n01i01173ent;
ARCHITECTURE c06s06b00x00p06n01i01173arch OF c06s06b00x00p06n01i01173ent IS
signal POS : Integer;
attribute PIO : positive;
attribute PIO of POS : signal is 10; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
if (POS'PIO(1) = 10) then -- Failure_here
end if;
assert FALSE
report "***FAILED TEST: c06s06b00x00p06n01i01173 - Static expression must not be present."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p06n01i01173arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3165.vhd | 4 | 2123 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3165.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p12n01i03165ent IS
END c14s01b00x00p12n01i03165ent;
ARCHITECTURE c14s01b00x00p12n01i03165arch OF c14s01b00x00p12n01i03165ent IS
subtype abc is real range 0.0 to 20.0;
subtype cba is real range 20.0 downto 0.0;
subtype xyz is real range 20.0 to 0.0;
subtype zyx is real range 0.0 downto 20.0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( abc'left = 0.0 and
cba'left = 20.0 and
xyz'left = 20.0 and
zyx'left = 0.0 )
report "***PASSED TEST: c14s01b00x00p12n01i03165"
severity NOTE;
assert ( abc'left = 0.0 and
cba'left = 20.0 and
xyz'left = 20.0 and
zyx'left = 0.0 )
report "***FAILED TEST: c14s01b00x00p12n01i03165 - Predefined attribute LEFT for floating point type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p12n01i03165arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1228.vhd | 4 | 1625 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1228.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p29n02i01228ent IS
port(s1, s2 : bit);
END c08s01b00x00p29n02i01228ent;
ARCHITECTURE c08s01b00x00p29n02i01228arch OF c08s01b00x00p29n02i01228ent IS
BEGIN
TESTING: PROCESS(s1,s2)
BEGIN
wait on s1, s2;
assert FALSE
report "***FAILED TEST: c08s01b00x00p29n02i01228 - Wait not allowed in a process with a sensitivity list"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p29n02i01228arch;
| gpl-2.0 |
peteut/ghdl | libraries/ieee2008/numeric_bit.vhdl | 4 | 63654 | -- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC Synthesis Working Group,
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
package NUMERIC_BIT is
constant CopyRightNotice : STRING
:= "Copyright © 2008 IEEE. All rights reserved.";
--============================================================================
-- Numeric Array Type Definitions
--============================================================================
type UNSIGNED is array (NATURAL range <>) of BIT;
type SIGNED is array (NATURAL range <>) of BIT;
--============================================================================
-- Arithmetic Operators:
--============================================================================
-- Id: A.1
function "abs" (ARG : SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG : SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit UNSIGNED
-- Id: A.3L
function "+"(L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.4
function "+" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.4R
function "+"(L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.4 where R is bit 0 of a non-negative.
-- Id: A.4L
function "+"(L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.4 where L is bit 0 of a non-negative.
-- Id: A.5
function "+" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Adds an UNSIGNED vector, L, with a nonnegative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Adds a nonnegative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.10
function "-" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0)
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.10R
function "-"(L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Similar to A.10 where R is bit 0 of a non-negative.
-- Id: A.10L
function "-"(L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Similar to A.10 where R is bit 0 of a non-negative.
-- Id: A.11
function "-" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Subtracts a nonnegative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Subtracts an UNSIGNED vector, R, from a nonnegative INTEGER, L.
-- Id: A.13
function "-" (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies an UNSIGNED vector, L, with a nonnegative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- size L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies an UNSIGNED vector, R, with a nonnegative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- size R'LENGTH before multiplication.
-- Id: A.19
function "*" (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of size L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of size R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a nonnegative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a nonnegative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- nonnegative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- nonnegative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a nonnegative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a nonnegative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Id: A.39
function find_leftmost (ARG : UNSIGNED; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.40
function find_leftmost (ARG : SIGNED; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : UNSIGNED; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.42
function find_rightmost (ARG : SIGNED; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.6
function ">" (L : SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.12
function "<" (L : SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.18
function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.24
function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.30
function "=" (L : SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.36
function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.38
function MINIMUM (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED
-- Result: Returns the lesser of two SIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.40
function MINIMUM (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED
-- Result: Returns the lesser of an INTEGER, L, and a SIGNED
-- vector, R.
-- Id: C.41
function MINIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
-- Id: C.42
function MINIMUM (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED
-- Result: Returns the lesser of a SIGNED vector, L, and
-- an INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.44
function MAXIMUM (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED
-- Result: Returns the greater of two SIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.46
function MAXIMUM (L : INTEGER; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED
-- Result: Returns the greater of an INTEGER, L, and a SIGNED
-- vector, R.
-- Id: C.47
function MAXIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
-- Id: C.48
function MAXIMUM (L : SIGNED; R : INTEGER) return SIGNED;
-- Result subtype: SIGNED
-- Result: Returns the greater of a SIGNED vector, L, and
-- an INTEGER, R.
--============================================================================
-- Id: C.49
function "?>" (L, R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.50
function "?>" (L, R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function "?>" (L : NATURAL; R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.52
function "?>" (L : INTEGER; R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.53
function "?>" (L : UNSIGNED; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.54
function "?>" (L : SIGNED; R : INTEGER) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.55
function "?<" (L, R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.56
function "?<" (L, R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function "?<" (L : NATURAL; R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.58
function "?<" (L : INTEGER; R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.59
function "?<" (L : UNSIGNED; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.60
function "?<" (L : SIGNED; R : INTEGER) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.61
function "?<=" (L, R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.62
function "?<=" (L, R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function "?<=" (L : NATURAL; R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.64
function "?<=" (L : INTEGER; R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.65
function "?<=" (L : UNSIGNED; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.66
function "?<=" (L : SIGNED; R : INTEGER) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.67
function "?>=" (L, R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.68
function "?>=" (L, R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function "?>=" (L : NATURAL; R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.70
function "?>=" (L : INTEGER; R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.71
function "?>=" (L : UNSIGNED; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.72
function "?>=" (L : SIGNED; R : INTEGER) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.73
function "?=" (L, R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.74
function "?=" (L, R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function "?=" (L : NATURAL; R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.76
function "?=" (L : INTEGER; R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is an INTEGER and
-- R is an SIGNED vector.
-- Id: C.77
function "?=" (L : UNSIGNED; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.78
function "?=" (L : SIGNED; R : INTEGER) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is an SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.79
function "?/=" (L, R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.80
function "?/=" (L, R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function "?/=" (L : NATURAL; R : UNSIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.82
function "?/=" (L : INTEGER; R : SIGNED) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is an SIGNED vector.
-- Id: C.83
function "?/=" (L : UNSIGNED; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
-- Id: C.84
function "?/=" (L : SIGNED; R : INTEGER) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is an SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT rightmost bits are lost.
-- Id: S.3
function SHIFT_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost bit, ARG'LEFT.
-- The COUNT rightmost bits are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG : SIGNED; NEW_SIZE : NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG : UNSIGNED; NEW_SIZE : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
function RESIZE (ARG, SIZE_RES : UNSIGNED) return UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED (SIZE_RES'length-1 downto 0)
function RESIZE (ARG, SIZE_RES : SIGNED) return SIGNED;
-- Result subtype: UNRESOLVED_SIGNED (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG : SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a nonnegative INTEGER to an UNSIGNED vector with
-- the specified size.
-- Id: D.4
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified size.
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED) return UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE_RES'length-1 downto 0)
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED) return SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE_RES'length-1 downto 0)
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.15
function "and" (L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector AND operation
-- Id: L.16
function "and" (L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar AND operation
-- Id: L.17
function "or" (L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector OR operation
-- Id: L.18
function "or" (L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar OR operation
-- Id: L.19
function "nand" (L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NAND operation
-- Id: L.20
function "nand" (L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NAND operation
-- Id: L.21
function "nor" (L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NOR operation
-- Id: L.22
function "nor" (L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NOR operation
-- Id: L.23
function "xor" (L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XOR operation
-- Id: L.24
function "xor" (L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XOR operation
------------------------------------------------------------------------------
-- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.25
function "xnor" (L : BIT; R : UNSIGNED) return UNSIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XNOR operation
------------------------------------------------------------------------------
-- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.26
function "xnor" (L : UNSIGNED; R : BIT) return UNSIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XNOR operation
-- Id: L.27
function "and" (L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector AND operation
-- Id: L.28
function "and" (L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar AND operation
-- Id: L.29
function "or" (L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector OR operation
-- Id: L.30
function "or" (L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar OR operation
-- Id: L.31
function "nand" (L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NAND operation
-- Id: L.32
function "nand" (L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NAND operation
-- Id: L.33
function "nor" (L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector NOR operation
-- Id: L.34
function "nor" (L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar NOR operation
-- Id: L.35
function "xor" (L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XOR operation
-- Id: L.36
function "xor" (L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XOR operation
------------------------------------------------------------------------------
-- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.37
function "xnor" (L : BIT; R : SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Scalar/Vector XNOR operation
------------------------------------------------------------------------------
-- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.38
function "xnor" (L : SIGNED; R : BIT) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector/Scalar XNOR operation
------------------------------------------------------------------------------
-- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.39
function "and" (L : SIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of and'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.40
function "nand" (L : SIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of nand'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.41
function "or" (L : SIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of or'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.42
function "nor" (L : SIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of nor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.43
function "xor" (L : SIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of xor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.44
function "xnor" (L : SIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of xnor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.45
function "and" (L : UNSIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of and'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.46
function "nand" (L : UNSIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of nand'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.47
function "or" (L : UNSIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of or'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.48
function "nor" (L : UNSIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of nor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.49
function "xor" (L : UNSIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of xor'ing all of the bits of the vector.
------------------------------------------------------------------------------
-- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.50
function "xnor" (L : UNSIGNED) return BIT;
-- Result subtype: BIT.
-- Result: Result of xnor'ing all of the bits of the vector.
--============================================================================
-- Edge Detection Functions
--============================================================================
-- Id: E.1
alias RISING_EDGE is STD.STANDARD.RISING_EDGE
[STD.STANDARD.BIT return STD.STANDARD.BOOLEAN];
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '0' to a '1'.
-- Id: E.2
alias FALLING_EDGE is STD.STANDARD.FALLING_EDGE
[STD.STANDARD.BIT return STD.STANDARD.BOOLEAN];
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '1' to a '0'.
--============================================================================
-- string conversion and write operations
--============================================================================
-- the following operations are predefined
-- FUNCTION to_string ( value : UNSIGNED ) RETURN string;
-- FUNCTION to_string ( value : SIGNED ) RETURN string;
-- explicitly defined operations
alias to_bstring is to_string [UNSIGNED return STRING];
alias to_bstring is to_string [SIGNED return STRING];
alias to_binary_string is to_string [UNSIGNED return STRING];
alias to_binary_string is to_string [SIGNED return STRING];
function to_ostring (value : UNSIGNED) return STRING;
function to_ostring (value : SIGNED) return STRING;
alias to_octal_string is to_ostring [UNSIGNED return STRING];
alias to_octal_string is to_ostring [SIGNED return STRING];
function to_hstring (value : UNSIGNED) return STRING;
function to_hstring (value : SIGNED) return STRING;
alias to_hex_string is to_hstring [UNSIGNED return STRING];
alias to_hex_string is to_hstring [SIGNED return STRING];
procedure READ(L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out UNSIGNED);
procedure READ(L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out SIGNED);
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, UNSIGNED, BOOLEAN];
alias BREAD is READ [LINE, SIGNED, BOOLEAN];
alias BREAD is READ [LINE, UNSIGNED];
alias BREAD is READ [LINE, SIGNED];
alias BINARY_READ is READ [LINE, UNSIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, SIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, UNSIGNED];
alias BINARY_READ is READ [LINE, SIGNED];
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED);
procedure OREAD (L : inout LINE; VALUE : out SIGNED);
alias OCTAL_READ is OREAD [LINE, UNSIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, SIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNSIGNED];
alias OCTAL_READ is OREAD [LINE, SIGNED];
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED);
procedure HREAD (L : inout LINE; VALUE : out SIGNED);
alias HEX_READ is HREAD [LINE, UNSIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, SIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNSIGNED];
alias HEX_READ is HREAD [LINE, SIGNED];
alias BWRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, SIGNED, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, SIGNED, SIDE, WIDTH];
end package NUMERIC_BIT;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc23.vhd | 4 | 1906 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc23.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p09n03i00023ent IS
END c04s02b00x00p09n03i00023ent;
ARCHITECTURE c04s02b00x00p09n03i00023arch OF c04s02b00x00p09n03i00023ent IS
type T1 is range 0 to 100;
subtype T2 is T1 range 20 to 80 ;
subtype T3 is T2 range 40 to 60 ; -- No_failure_here
subtype T4 is T3 range 50 to 50 ;
BEGIN
TESTING: PROCESS
variable k : T4 := 50;
BEGIN
assert NOT(k=50)
report "***PASSED TEST: c04s02b00x00p09n03i00023"
severity NOTE;
assert (k=50)
report "***FAILED TEST: c04s02b00x00p09n03i00023 - Range constraints for the subtype declarations contradict the range of the subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p09n03i00023arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2763.vhd | 4 | 1655 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2763.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p06n02i02763ent IS
END c13s07b00x00p06n02i02763ent;
ARCHITECTURE c13s07b00x00p06n02i02763arch OF c13s07b00x00p06n02i02763ent IS
BEGIN
TESTING: PROCESS
constant empty ; bit_vector := O"058";
BEGIN
assert FALSE
report "***FAILED TEST: c13s07b00x00p06n02i02763 - For the base specifier `O', the extended digits are restricted to the digits 0 through 7."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p06n02i02763arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1323.vhd | 4 | 1813 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1323.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p02n01i01323ent IS
END c08s04b01x00p02n01i01323ent;
ARCHITECTURE c08s04b01x00p02n01i01323arch OF c08s04b01x00p02n01i01323ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
k <= transport 5;
wait for 1 ns;
assert NOT( k=5 )
report "***PASSED TEST: c08s04b01x00p02n01i01323"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s04b01x00p02n01i01323 - waveform element in a signal assignment statement may either consist of a value expression and an after clause (optional)"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p02n01i01323arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2493.vhd | 4 | 2048 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2493.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p04n01i02493ent IS
END c07s03b03x00p04n01i02493ent;
ARCHITECTURE c07s03b03x00p04n01i02493arch OF c07s03b03x00p04n01i02493ent IS
BEGIN
TESTING: PROCESS
type index_values is (one, two, three);
type ucarr is array (index_values range <>) of Boolean;
subtype carr is ucarr (index_values'low to index_values'high);
function f1 (i : integer) return carr is
begin
return (index_values'LOW => TRUE, others => False);
end f1;
variable V1 : CARR;
variable I1 : Integer := 10;
BEGIN
V1 := f1(I1,10) ; -- Failure_here
assert FALSE
report "***FAILED TEST: c07s03b03x00p04n01i02493 - Each formal parameter of a function should have exactly one actual parameter associated with it in a function call."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p04n01i02493arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc736.vhd | 4 | 3277 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc736.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:41:06 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:27:25 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:35:44 1996 --
-- **************************** --
library STD;
use STD.textio.all;
entity c01s01b01x00p05n01i00736ent_a is
generic (
constant gc1 : text;
constant gc2 : natural;
constant gc3 : positive
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x00p05n01i00736ent_a;
architecture arch of c01s01b01x00p05n01i00736ent_a is
begin
assert false
report "FAIL: should not compile";
end arch;
ENTITY c01s01b01x00p05n01i00736ent IS
generic ( constant gen_con : natural := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x00p05n01i00736ent;
ARCHITECTURE c01s01b01x00p05n01i00736arch OF c01s01b01x00p05n01i00736ent IS
signal s1 : integer;
signal s2 : natural;
signal s3 : positive;
file f1 : text open read_mode is "e.in";
component comp1
generic (
constant dgc1 : text;
constant dgc2 : natural;
constant dgc3 : positive
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x00p05n01i00736ent_a
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
BEGIN
u1 : comp1
generic map (f1,3,3)
port map (ee1,ee2);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x00p05n01i00736 - Formal generic can not be of type FILE."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x00p05n01i00736arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc876.vhd | 4 | 2272 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc876.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s03b02x00p02n01i00876ent_a is
port ( ia, ib : bit;
oc, od : out bit) ;
end c01s03b02x00p02n01i00876ent_a;
architecture c01s03b02x00p02n01i00876arch_a of c01s03b02x00p02n01i00876ent_a is
begin
A1_BLK : block
signal S : INTEGER;
begin
S <= 1;
end block;
end c01s03b02x00p02n01i00876arch_a;
ENTITY c01s03b02x00p02n01i00876ent IS
port ( P3 : out bit;
P4 : out bit) ;
END c01s03b02x00p02n01i00876ent;
ARCHITECTURE c01s03b02x00p02n01i00876arch OF c01s03b02x00p02n01i00876ent IS
BEGIN
BB : block
signal S1 : bit;
signal S2 : bit;
component LOCAL port( CI, I2 : in BIT;
CO, RES :out BIT);
end component ;
for all : LOCAL
use entity work.c01s03b02x00p02n01i00876ent_a (c01s03b02x00p02n01i00876arch_a)
port map (ia => CI, ib => I2, oc => CO, od => RES);
begin
L : LOCAL
port map (CI =>S1 , I2 =>S2 , CO=>P3 , RES =>P4 );
assert FALSE
report "***PASSED TEST: c01s03b02x00p02n01i00876"
severity NOTE;
end block BB;
END c01s03b02x00p02n01i00876arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_01.vhd | 4 | 1615 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_ap_a_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ap_a_01 is
end entity ap_a_01;
library ieee; use ieee.std_logic_1164.all;
architecture test of ap_a_01 is
signal clk : std_ulogic;
begin
process (clk) is
-- code from book
-- end code from book
begin
if
-- code from book
clk'event and (To_X01(clk) = '1') and (To_X01(clk'last_value) = '0')
-- end code from book
then
report "rising edge on clk";
end if;
end process;
clk <= '0', '1' after 10 ns, '0' after 20 ns,
'1' after 30 ns, '0' after 40 ns;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1225.vhd | 4 | 3436 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1225.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p28n01i01225ent IS
END c08s01b00x00p28n01i01225ent;
ARCHITECTURE c08s01b00x00p28n01i01225arch OF c08s01b00x00p28n01i01225ent IS
-- Local signals.
signal A : BIT;
BEGIN
TESTING: PROCESS
-- Local variables.
variable ShouldBeTime : TIME;
variable I : INTEGER;
variable k : integer := 0;
BEGIN
-- Make sure it takes an EVENT to trigger the WAIT statement.
A <= A after 2 ns, -- NOT an event.
(not A) after 4 ns; -- an event.
ShouldBeTime := NOW + 4 ns; -- Should wait for event.
wait on A;
if (ShouldBeTime /= Now) then
k := 1;
end if;
assert (ShouldBeTime = NOW)
report "Did not wait for 4ns";
-- If the value of the condition is FALSE, resuspend.
-- If the value is TRUE, the process will resume.
A <= '1' after 2 ns,
'0' after 4 ns;
-- Make sure that we wait until the second one for
-- the following wait statement to resume.
ShouldBeTime := NOW + 4 ns;
wait until (A = '0');
if (ShouldBeTime /= Now and A /= '0') then
k := 1;
end if;
assert (ShouldBeTime = NOW)
report "Did not wait for 4ns";
assert (A = '0')
report "Did not assign the correct value.";
-- Such resuspension does not involve the recalculation of the timeout interval.
-- If the value of the condition is FALSE, resuspend.
-- IF the value is TRUE, the process will resume.
A <= '1' after 2 ns,
'0' after 4 ns;
-- Make sure that we wait until the second one for
-- the following wait statement to resume.
ShouldBeTime := NOW + 3 ns;
wait until (A = '0') for 3 ns;
if (ShouldBeTime /= Now and A /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW)
report "Did not wait for 3ns";
assert (A = '1')
report "Did not assign the correct value to A.";
assert NOT( k=0 )
report "***PASSED TEST: c08s01b00x00p28n01i01225"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s01b00x00p28n01i01225 - The process will resume if the result of an event occuring on sentivity set is TRUE."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p28n01i01225arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_01.vhd | 4 | 5648 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity D_flipflop is
port ( clk : in std_logic; d : in std_logic;
q : out std_logic );
end entity D_flipflop;
architecture synthesized of D_flipflop is
begin
q <= d when not clk'stable and (To_X01(clk) = '1') and
(To_X01(clk'last_value) = '0');
end architecture synthesized;
library ieee; use ieee.std_logic_1164.all;
entity tristate_buffer is
port ( a : in std_logic;
en : in std_logic;
y : out std_logic );
end entity tristate_buffer;
architecture synthesized of tristate_buffer is
begin
y <= 'X' when is_X(en) else
a when To_X01(en) = '1' else
'Z';
end architecture synthesized;
-- code from book (in Figure 14-1)
library ieee; use ieee.std_logic_1164.all;
entity register_tristate is
generic ( width : positive );
port ( clock : in std_logic;
out_enable : in std_logic;
data_in : in std_logic_vector(0 to width - 1);
data_out : out std_logic_vector(0 to width - 1) );
end entity register_tristate;
--------------------------------------------------
architecture cell_level of register_tristate is
component D_flipflop is
port ( clk : in std_logic; d : in std_logic;
q : out std_logic );
end component D_flipflop;
component tristate_buffer is
port ( a : in std_logic;
en : in std_logic;
y : out std_logic );
end component tristate_buffer;
begin
cell_array : for bit_index in 0 to width - 1 generate
signal data_unbuffered : std_logic;
begin
cell_storage : component D_flipflop
port map ( clk => clock, d => data_in(bit_index),
q => data_unbuffered );
cell_buffer : component tristate_buffer
port map ( a => data_unbuffered, en => out_enable,
y => data_out(bit_index) );
end generate cell_array;
end architecture cell_level;
-- end code from book (in Figure 14-1)
-- code from book (in Figure 14-11)
library cell_lib;
configuration identical_cells of register_tristate is
for cell_level
for cell_array
for cell_storage : D_flipflop
use entity cell_lib.D_flipflop(synthesized);
end for;
for cell_buffer : tristate_buffer
use entity cell_lib.tristate_buffer(synthesized);
end for;
end for;
end for;
end configuration identical_cells;
-- code from book (in Figure 14-11)
library ieee; use ieee.std_logic_1164.all;
entity fg_14_01 is
end entity fg_14_01;
architecture test of fg_14_01 is
signal clk, en : std_logic;
signal d_in, d_out : std_logic_vector(0 to 3);
begin
dut : configuration work.identical_cells
generic map ( width => d_in'length )
port map ( clock => clk, out_enable => en,
data_in => d_in, data_out => d_out );
stimulus : process is
begin
wait for 10 ns;
d_in <= "0000"; en <= '0'; clk <= '0'; wait for 10 ns;
clk <= '1', '0' after 5 ns; wait for 10 ns;
en <= '1', '0' after 5 ns; wait for 10 ns;
d_in <= "0101"; wait for 10 ns;
clk <= '1', '0' after 5 ns; wait for 10 ns;
en <= 'H', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
-- end not in book
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3115.vhd | 4 | 3232 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3115.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x01p03n01i03115ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b01x01p03n01i03115ent_a;
ARCHITECTURE c05s02b01x01p03n01i03115arch_a OF c05s02b01x01p03n01i03115ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b01x01p03n01i03115arch_a;
ARCHITECTURE c05s02b01x01p03n01i03115arch_b OF c05s02b01x01p03n01i03115ent_a IS
BEGIN
p2 <= p1 after 15 ns;
END c05s02b01x01p03n01i03115arch_b;
configuration c05s02b01x01p03n01i03115cfg_a of c05s02b01x01p03n01i03115ent_a is
for c05s02b01x01p03n01i03115arch_a
end for;
end c05s02b01x01p03n01i03115cfg_a;
configuration c05s02b01x01p03n01i03115cfg_b of c05s02b01x01p03n01i03115ent_a is
for c05s02b01x01p03n01i03115arch_b
end for;
end c05s02b01x01p03n01i03115cfg_b;
--
ENTITY c05s02b01x01p03n01i03115ent IS
END c05s02b01x01p03n01i03115ent;
ARCHITECTURE c05s02b01x01p03n01i03115arch OF c05s02b01x01p03n01i03115ent IS
component ic_socket
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
signal s1,s2,s3,s4 : Bit;
BEGIN
u1 : ic_socket
generic map ( true )
port map (s1, s2);
u2 : ic_socket
generic map ( true )
port map (s2, s3);
u3 : ic_socket
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 60 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b01x01p03n01i03115"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b01x01p03n01i03115 - Absense of an explicit architecture test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x01p03n01i03115arch;
configuration c05s02b01x01p03n01i03115cfg of c05s02b01x01p03n01i03115ent is
for c05s02b01x01p03n01i03115arch
for all : ic_socket use entity work.c05s02b01x01p03n01i03115ent_a;
end for;
end for;
end c05s02b01x01p03n01i03115cfg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2479.vhd | 4 | 1817 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2479.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p13n04i02479ent IS
END c07s03b02x02p13n04i02479ent;
ARCHITECTURE c07s03b02x02p13n04i02479arch OF c07s03b02x02p13n04i02479ent IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(CA_DOWN'LEFT = 10)
report "***PASSED TEST: c07s03b02x02p13n04i02479"
severity NOTE;
assert (CA_DOWN'LEFT = 10)
report "***FAILED TEST: c07s03b02x02p13n04i02479 - S'LEFT did not return the correct value."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p13n04i02479arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1499.vhd | 4 | 2937 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1499.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n01i01499ent IS
END c08s08b00x00p14n01i01499ent;
ARCHITECTURE c08s08b00x00p14n01i01499arch OF c08s08b00x00p14n01i01499ent IS
BEGIN
TESTING: PROCESS
subtype sub_int is integer range 1 to 2;
variable V1 : integer;
variable k1 : integer := 0;
variable k2 : integer := 0;
variable k3 : integer := 0;
variable k4 : integer := 0;
BEGIN
V1 := 0;
case V1 is
when sub_int'low
to sub_int'high => assert (false)
report "V1 in specified range"
severity failure;
when others => k1 := 1;
end case;
V1 := 1;
case V1 is
when sub_int'low
to sub_int'high => k2 := 1;
when others => assert (false)
report "V1 NOT in specified range"
severity failure;
end case;
V1 := 2;
case V1 is
when sub_int'low
to sub_int'high => k3 := 1;
when others => assert (false)
report "V1 NOT in specified range"
severity failure;
end case;
V1 := 3;
case V1 is
when sub_int'low
to sub_int'high => assert (false)
report "V1 in specified range"
severity failure;
when others => k4 := 1;
end case;
assert NOT(k1=1 and k2=1 and k3=1 and k4=1)
report "***PASSED TEST: c08s08b00x00p14n01i01499"
severity NOTE;
assert (k1=1 and k2=1 and k3=1 and k4=1)
report "***FAILED TEST: c08s08b00x00p14n01i01499 - A choice can be a discrete range using attributes."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n01i01499arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2888.vhd | 4 | 2045 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2888.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x00p04n01i02888ent IS
END c02s01b01x00p04n01i02888ent;
ARCHITECTURE c02s01b01x00p04n01i02888arch OF c02s01b01x00p04n01i02888ent IS
procedure exp_type_check (c1: out integer;
c2: in integer;
c3: inout integer;
c5: linkage integer); -- Failure_here
procedure exp_type_check (c1: out integer;
c2: in integer;
c3: inout integer;
c5: linkage integer) is
begin
null;
end exp_type_check;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x00p04n01i02888 - Linkage is not an allowed mode for formal parameter of a procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x00p04n01i02888arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3112.vhd | 4 | 2525 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3112.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b00x00p06n01i03112ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b00x00p06n01i03112ent_a;
ARCHITECTURE c05s02b00x00p06n01i03112arch_a OF c05s02b00x00p06n01i03112ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b00x00p06n01i03112arch_a;
ENTITY c05s02b00x00p06n01i03112ent IS
END c05s02b00x00p06n01i03112ent;
ARCHITECTURE c05s02b00x00p06n01i03112arch OF c05s02b00x00p06n01i03112ent IS
signal s1 : Bit := '0';
signal s2 : Bit := '1';
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
BEGIN
u1 : virtual generic map ( true ) port map (s1, s2);
TESTING: PROCESS
BEGIN
wait for 50 ns;
assert NOT( s2 = s1 )
report "***PASSED TEST: c05s02b00x00p06n01i03112"
severity NOTE;
assert ( s2 = s1 )
report "***FAILED TEST: c05s02b00x00p06n01i03112 - Component instance configuration test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b00x00p06n01i03112arch;
configuration c05s02b00x00p06n01i03112cfg of c05s02b00x00p06n01i03112ent is
for c05s02b00x00p06n01i03112arch
for u1 : virtual use entity work.c05s02b00x00p06n01i03112ent_a (c05s02b00x00p06n01i03112arch_a);
end for;
end for;
end c05s02b00x00p06n01i03112cfg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_motor_system.vhd | 4 | 1489 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_motor_system is
end tb_motor_system ;
architecture TB_motor_system of tb_motor_system is
-- Component declarations
-- Signal declarations
terminal in_src, x1_out, x2_out, x3_out : electrical;
begin
v7 : entity work.v_sine(ideal)
generic map(
freq => 10.0,
amplitude => 1.0
)
port map(
pos => in_src,
neg => electrical_ref
);
state_var1: entity work.motor_system_wa(simple)
port map(
vp => in_src,
vm => ELECTRICAL_REF,
px1 => x1_out,
px2 => x2_out,
px3 => x3_out
);
end TB_motor_system ;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug21332/twoscomplement.vhdl | 3 | 1169 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity twoscompliment is
generic
(
Nbits : positive := 8
);
port
(
--Inputs
A : in std_logic_vector (Nbits-1 downto 0);
--Outputs
Y : out std_logic_vector (Nbits downto 0)
);
end twoscompliment;
architecture twoscompliment_v1 of twoscompliment is
constant ONE: UNSIGNED(Y'RANGE) := (0 => '1', others => '0');
begin
Y <= std_logic_vector(unsigned (not A) + ONE);
end twoscompliment_v1;
architecture twoscompliment_v2 of twoscompliment is
signal temp : std_logic_vector(Nbits-1 downto 0);
begin
temp <= not A;
Y <= std_logic_vector(unsigned(temp) + 1);
end twoscompliment_v2;
library ieee;
use ieee.std_logic_1164.all;
entity test is
end entity;
architecture foo of test is
-- counts on default value for Nbits in DUT = 8)
signal A: std_logic_vector (7 downto 0) := (0=>'1', others => '0'); -- ONE
signal Y: std_logic_vector ( 8 downto 0);
begin
DUT: entity work.twoscompliment(twoscompliment_v2)
port map (
A => A,
Y => Y
);
end architecture; | gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_02.vhd | 4 | 1222 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_02.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package test_bench_03_02 is
-- following type used in Figure 3-02
-- code from book:
type sel_range is range 0 to 3;
-- end of code from book
end package test_bench_03_02;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_06a.vhd | 4 | 2107 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_06a is
end entity inline_06a;
architecture test of inline_06a is
-- code from book
terminal a_bus : electrical_vector(1 to 8);
terminal b_bus : electrical_vector(8 downto 1);
--
quantity a_to_b_drops across a_to_b_currents through a_bus to b_bus;
--
nature electrical_bus is
record
strobe: electrical;
databus : electrical_vector(0 to 7);
end record;
terminal t1, t2 : electrical_bus;
--
quantity bus_voltages across t1 to t2;
--
terminal p1, p2 : electrical_vector(0 to 3);
quantity v across i through p1 to p2;
-- end code from book
begin
block_1 : block is
terminal anode, cathode : electrical;
-- code from book
quantity battery_voltage tolerance "battery_tolerance" across
battery_current tolerance "battery_tolerance" through anode to cathode;
-- end code from book
begin
end block block_1;
block_2 : block is
terminal anode, cathode : electrical;
-- code from book
quantity battery_volts := 5.0 across
battery_amps := 0.0 through
anode to cathode;
-- end code from book
begin
end block block_2;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2156.vhd | 4 | 2186 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2156.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02156ent IS
END c07s02b04x00p21n01i02156ent;
ARCHITECTURE c07s02b04x00p21n01i02156arch OF c07s02b04x00p21n01i02156ent IS
TYPE character_v is array (integer range <>) of character;
SUBTYPE character_5 is character_v (1 to 5);
SUBTYPE character_4 is character_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : character_5;
variable l_operand : character_4 := ('A', 'z', 'A', 'z' );
variable r_operand : character := 'A';
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result=('A', 'z', 'A', 'z', 'A'))
report "***PASSED TEST: c07s02b04x00p21n01i02156"
severity NOTE;
assert (result=('A', 'z', 'A', 'z', 'A'))
report "***FAILED TEST: c07s02b04x00p21n01i02156 - Concatenation of CHARACTER element and CHARACTER array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02156arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_srff-b.vhd | 4 | 1430 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_srff-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of synch_sr_ff is
begin
behavior : process (clk) is
constant Tpd_clk_out : time := 3 ns;
begin
if rising_edge(clk) then
if To_X01(clr) = '1' then
q <= '0' after Tpd_clk_out;
elsif To_X01(set) = '1' then
q <= '1' after Tpd_clk_out;
end if;
end if;
end process behavior;
end architecture behavioral;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_25.vhd | 4 | 1549 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_25.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity reg4 is
port ( clk, clr, d0, d1, d2, d3 : in bit;
q0, q1, q2, q3 : out bit );
end entity reg4;
architecture struct of reg4 is
begin
bit0 : entity work.edge_triggered_Dff(behavioral)
port map (d0, clk, clr, q0);
bit1 : entity work.edge_triggered_Dff(behavioral)
port map (d1, clk, clr, q1);
bit2 : entity work.edge_triggered_Dff(behavioral)
port map (d2, clk, clr, q2);
bit3 : entity work.edge_triggered_Dff(behavioral)
port map (d3, clk, clr, q3);
end architecture struct;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc134.vhd | 4 | 2244 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc134.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p08n01i00134ent IS
END c04s03b02x02p08n01i00134ent;
ARCHITECTURE c04s03b02x02p08n01i00134arch OF c04s03b02x02p08n01i00134ent IS
type AT1 is array (INTEGER range <>) of INTEGER;
subtype ST1 is AT1(1 to 2);
BEGIN
TESTING: PROCESS
procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is
begin
if ( P = ref ) then
P := set;
end if;
end;
variable V1, V2 : INTEGER;
BEGIN
V1 := 1;
V2 := 2;
Proc1(P(1) => V2, P(2) => V1, ref => (2, 1), set => (2, 3));
-- test here
assert V1 = 3 report "FAIL: actual V1 didn't get set right";
assert V2 = 2 report "FAIL: actual V2 didn't get set right";
assert NOT( V1 = 3 and V2 = 2 )
report "***PASSED TEST: c04s03b02x02p08n01i00134"
severity NOTE;
assert ( V1 = 3 and V2 = 2 )
report "***FAILED TEST: c04s03b02x02p08n01i00134 - Association element in an association list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p08n01i00134arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2243.vhd | 4 | 1653 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2243.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02243ent IS
END c07s02b06x00p01n01i02243ent;
ARCHITECTURE c07s02b06x00p01n01i02243arch OF c07s02b06x00p01n01i02243ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
k := B"1010101010" mod X"FFFF";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02243 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02243arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1599.vhd | 4 | 2098 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1599.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01599ent IS
END c08s11b00x00p03n01i01599ent;
ARCHITECTURE c08s11b00x00p03n01i01599arch OF c08s11b00x00p03n01i01599ent IS
BEGIN
TESTING: PROCESS
variable p : integer := 0;
variable done : boolean := false;
variable v_boolean : boolean := false;
BEGIN
L1 : while v_boolean /= boolean'High loop
while not done loop
done := true ;
exit ;
p := 0;
end loop ;
p := p + 1;
v_boolean := boolean'Succ(v_boolean);
end loop L1;
assert NOT( p=1 )
report "***PASSED TEST: c08s11b00x00p03n01i01599"
severity NOTE;
assert ( p=1 )
report "***FAILED TEST: c08s11b00x00p03n01i01599 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01599arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_std_logic_type.vhdl | 4 | 1776 | entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
architecture only of test is
begin -- only
process
variable x : std_logic;
begin -- process
assert std_logic'pos('U') = 0 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('X') = 1 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('0') = 2 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('1') = 3 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('Z') = 4 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('W') = 5 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('L') = 6 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('H') = 7 report "TEST FAILED" severity FAILURE;
assert std_logic'pos('-') = 8 report "TEST FAILED" severity FAILURE;
assert x'left = 'U' report "TEST FAILED" severity FAILURE;
assert x'right = '-' report "TEST FAILED" severity FAILURE;
assert x'high = '-' report "TEST FAILED" severity FAILURE;
assert x'low = 'U' report "TEST FAILED" severity FAILURE;
assert x'ascending = true report "TEST FAILED" severity FAILURE;
assert std_logic'image('U') = "'U'" report "TEST FAILED" severity FAILURE;
assert std_logic'value("'U'") = 'U' report "TEST FAILED" severity FAILURE;
assert std_logic'val(0) = 'U' report "TEST FAILED" severity FAILURE;
assert std_logic'succ('U') = 'X' report "TEST FAILED" severity FAILURE;
assert std_logic'pred('-') = 'H' report "TEST FAILED" severity FAILURE;
assert std_logic'leftof('-') = 'H' report "TEST FAILED" severity FAILURE;
assert std_logic'rightof('U') = 'X' report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity note;
wait;
end process;
end only;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket55/bug2.vhdl | 3 | 198 | package pkg is
function identifier return integer;
-- procedure identifier;
-- alias identifier_alias_fun is identifier[return integer];
alias identifier_alias_proc is identifier[];
end package;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1438.vhd | 4 | 1622 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1438.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01438ent IS
END c08s07b00x00p02n01i01438ent;
ARCHITECTURE c08s07b00x00p02n01i01438arch OF c08s07b00x00p02n01i01438ent IS
begin
process
variable VAR_1: INTEGER := 3;
begin
if VAR_1 > 2 then
NULL;
assert FALSE
report "***FAILED TEST: c08s07b00x00p02n01i01438 - reserved word 'end if;' is missing"
severity ERROR;
wait;
end process;
END c08s07b00x00p02n01i01438arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3110.vhd | 4 | 2662 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3110.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p34n01i03110ent_a IS
PORT ( Y : IN BIT ;
Z : OUT INTEGER );
ATTRIBUTE A : INTEGER;
ATTRIBUTE A OF Y : SIGNAL IS 1;
END c05s01b00x00p34n01i03110ent_a;
ARCHITECTURE c05s01b00x00p34n01i03110arch_a OF c05s01b00x00p34n01i03110ent_a IS
BEGIN
PROCESS
BEGIN
ASSERT Y'A = 1
REPORT "ERROR: Bad value for Y'A" SEVERITY FAILURE;
if (Y'A = 1) then
Z <= 100;
end if;
WAIT;
END PROCESS;
END c05s01b00x00p34n01i03110arch_a;
ENTITY c05s01b00x00p34n01i03110ent IS
ATTRIBUTE A : INTEGER;
END c05s01b00x00p34n01i03110ent;
ARCHITECTURE c05s01b00x00p34n01i03110arch OF c05s01b00x00p34n01i03110ent IS
COMPONENT c05s01b00x00p34n01i03110ent_a
PORT ( Y : IN BIT ;
Z : OUT INTEGER );
END COMPONENT;
for all : c05s01b00x00p34n01i03110ent_a use entity work.c05s01b00x00p34n01i03110ent_a(c05s01b00x00p34n01i03110arch_a);
SIGNAL X : BIT;
SIGNAL XX: INTEGER;
ATTRIBUTE A OF X : SIGNAL IS 2;
BEGIN
inst1 : c05s01b00x00p34n01i03110ent_a PORT MAP ( Y => X , Z => XX );
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( X'A = 2 and XX = 100 )
report "***PASSED TEST: c05s01b00x00p34n01i03110"
severity NOTE;
assert ( X'A = 2 and XX = 100 )
report "***FAILED TEST: c05s01b00x00p34n01i03110 - User defined attribute represent local information only."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p34n01i03110arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1912.vhd | 4 | 3729 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1912.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p09n03i01912ent IS
END c07s02b00x00p09n03i01912ent;
ARCHITECTURE c07s02b00x00p09n03i01912arch OF c07s02b00x00p09n03i01912ent IS
BEGIN
TESTING: PROCESS
variable b1a,b2a,b3a : BOOLEAN;
variable b1b,b2b,b3b : BOOLEAN;
variable b1c,b2c,b3c : BOOLEAN;
variable i1a,i2a,i3a : INTEGER;
variable i1b,i2b,i3b : INTEGER;
BEGIN
-- I. logical operator and relational operator.
b1a := FALSE;
b2a := FALSE;
b3a := TRUE;
assert ((b1a and b2a) /= b3a)
report "1:Parentheses do NOT change the precedence of operation.";
-- V. logical operator and miscellaneous operator.
b1b := FALSE;
b2b := TRUE;
assert (not (b1b and b2b))
report "2:Parentheses do NOT change the precedence of operation.";
-- VI. relational operators cannot be thus compared to ANY other operators
-- but the NOT operator, because they return boolean values and no other
-- higher precedence operators work on this type.
b1c := FALSE;
b2c := TRUE;
assert (not (b1c >= b2c))
report "3:Parentheses do NOT change the precedence of operation.";
-- VIII. adding operator and multiplying operator.
i1a := 3;
i2a := 4;
i3a := 5;
assert (((i1a + i2a) * i3a) = 35)
report "4:Parentheses do NOT change the precedence of operation.";
-- XII. multiplying operator and miscellaneous operator.
i1b := 2;
i2b := 3;
i3b := 2;
assert (((i1b + i2b) ** i3b) = 25)
report "5:Parentheses do NOT change the precedence of operation.";
wait for 5 ns;
assert NOT( ((b1a and b2a) /= b3a) and
(not (b1b and b2b)) and
(not (b1c >= b2c)) and
(((i1a + i2a) * i3a) = 35) and
(((i1b + i2b) ** i3b) = 25) )
report "***PASSED TEST: c07s02b00x00p09n03i01912"
severity NOTE;
assert ( ((b1a and b2a) /= b3a) and
(not (b1b and b2b)) and
(not (b1c >= b2c)) and
(((i1a + i2a) * i3a) = 35) and
(((i1b + i2b) ** i3b) = 25) )
report "***FAILED TEST: c07s02b00x00p09n03i01912 - The parentheses should be able to control the association of operators and operands."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p09n03i01912arch;
| gpl-2.0 |
peteut/ghdl | libraries/vital95/vital_timing.vhdl | 6 | 46973 | -------------------------------------------------------------------------------
-- Title : Standard VITAL TIMING Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, attributes, constants,
-- : functions and procedures for use in developing ASIC models.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0
-- #204 - Output mapping prior to glitch detection
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE VITAL_Timing IS
TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0X, trx1, tr1x, trx0, trxz, trzx);
SUBTYPE VitalDelayType IS TIME;
TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10)
OF TIME;
TYPE VitalDelayType01Z IS ARRAY (VitalTransitionType RANGE tr01 to trz0)
OF TIME;
TYPE VitalDelayType01ZX IS ARRAY (VitalTransitionType RANGE tr01 to trzx)
OF TIME;
TYPE VitalDelayArrayType IS ARRAY (NATURAL RANGE <>) OF VitalDelayType;
TYPE VitalDelayArrayType01 IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01;
TYPE VitalDelayArrayType01Z IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01Z;
TYPE VitalDelayArrayType01ZX IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01ZX;
-- ----------------------------------------------------------------------
-- **********************************************************************
-- ----------------------------------------------------------------------
CONSTANT VitalZeroDelay : VitalDelayType := 0 ns;
CONSTANT VitalZeroDelay01 : VitalDelayType01 := ( 0 ns, 0 ns );
CONSTANT VitalZeroDelay01Z : VitalDelayType01Z := ( OTHERS => 0 ns );
CONSTANT VitalZeroDelay01ZX : VitalDelayType01ZX := ( OTHERS => 0 ns );
---------------------------------------------------------------------------
-- examples of usage:
---------------------------------------------------------------------------
-- tpd_CLK_Q : VitalDelayType := 5 ns;
-- tpd_CLK_Q : VitalDelayType01 := (tr01 => 2 ns, tr10 => 3 ns);
-- tpd_CLK_Q : VitalDelayType01Z := ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns );
-- tpd_CLK_Q : VitalDelayArrayType(0 to 1)
-- := (0 => 5 ns, 1 => 6 ns);
-- tpd_CLK_Q : VitalDelayArrayType01(0 to 1)
-- := (0 => (tr01 => 2 ns, tr10 => 3 ns),
-- 1 => (tr01 => 2 ns, tr10 => 3 ns));
-- tpd_CLK_Q : VitalDelayArrayType01Z(0 to 1)
-- := (0 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ),
-- 1 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ));
---------------------------------------------------------------------------
-- TRUE if the model is LEVEL0 | LEVEL1 compliant
ATTRIBUTE VITAL_Level0 : BOOLEAN;
ATTRIBUTE VITAL_Level1 : BOOLEAN;
SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0);
SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0);
SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0);
-- Types for strength mapping of outputs
TYPE VitalOutputMapType IS ARRAY ( std_ulogic ) OF std_ulogic;
TYPE VitalResultMapType IS ARRAY ( UX01 ) OF std_ulogic;
TYPE VitalResultZMapType IS ARRAY ( UX01Z ) OF std_ulogic;
CONSTANT VitalDefaultOutputMap : VitalOutputMapType
:= "UX01ZWLH-";
CONSTANT VitalDefaultResultMap : VitalResultMapType
:= ( 'U', 'X', '0', '1' );
CONSTANT VitalDefaultResultZMap : VitalResultZMapType
:= ( 'U', 'X', '0', '1', 'Z' );
-- Types for fields of VitalTimingDataType
TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME;
TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT;
TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN;
TYPE VitalBoolArrayPT IS ACCESS VitalBoolArrayT;
TYPE VitalLogicArrayPT IS ACCESS std_logic_vector;
TYPE VitalTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
FUNCTION VitalTimingDataInit RETURN VitalTimingDataType;
-- type for internal data of VitalPeriodPulseCheck
TYPE VitalPeriodDataType IS RECORD
Last : X01;
Rise : TIME;
Fall : TIME;
NotFirstFlag : BOOLEAN;
END RECORD;
CONSTANT VitalPeriodDataInit : VitalPeriodDataType
:= ('X', 0 ns, 0 ns, FALSE );
-- Type for specifying the kind of Glitch handling to use
TYPE VitalGlitchKindType IS (OnEvent,
OnDetect,
VitalInertial,
VitalTransport);
TYPE VitalGlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
LastValue : std_ulogic;
END RECORD;
TYPE VitalGlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF VitalGlitchDataType;
-- PathTypes: for handling simple PathDelay info
TYPE VitalPathType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01Type IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01ZType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01Z;-- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
-- For representing multiple paths to an output
TYPE VitalPathArrayType IS ARRAY (NATURAL RANGE <> ) OF VitalPathType;
TYPE VitalPathArray01Type IS ARRAY (NATURAL RANGE <> ) OF VitalPath01Type;
TYPE VitalPathArray01ZType IS ARRAY (NATURAL RANGE <> ) OF VitalPath01ZType;
TYPE VitalTableSymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S' -- steady value
);
SUBTYPE VitalEdgeSymbolType IS VitalTableSymbolType RANGE '/' TO '*';
-- ------------------------------------------------------------------------
--
-- Function Name: VitalExtendToFillDelay
--
-- Description: A six element array of delay values of type
-- VitalDelayType01Z is returned when a 1, 2 or 6
-- element array is given. This function will convert
-- VitalDelayType and VitalDelayType01 delay values into
-- a VitalDelayType01Z type following these rules:
--
-- When a VitalDelayType is passed, all six transition
-- values are assigned the input value. When a
-- VitalDelayType01 is passed, the 01 transitions are
-- assigned to the 01, 0Z and Z1 transitions and the 10
-- transitions are assigned to 10, 1Z and Z0 transition
-- values. When a VitalDelayType01Z is passed, the values
-- are kept as is.
--
-- The function is overloaded based on input type.
--
-- There is no function to fill a 12 value delay
-- type.
--
-- Arguments:
--
-- IN Type Description
-- Delay A one, two or six delay value Vital-
-- DelayType is passed and a six delay,
-- VitalDelayType01Z, item is returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- VitalDelayType01Z
--
-- -------------------------------------------------------------------------
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalDelayType01Z;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalCalcDelay
--
-- Description: This function accepts a 1, 2 or 6 value delay and
-- chooses the correct delay time to delay the NewVal
-- signal. This function is overloaded based on the
-- delay type passed. The function returns a single value
-- of time.
--
-- This function is provided for Level 0 models in order
-- to calculate the delay which should be applied
-- for the passed signal. The delay selection is performed
-- using the OldVal and the NewVal to determine the
-- transition to select. The default value of OldVal is X.
--
-- This function cannot be used in a Level 1 model since
-- the VitalPathDelay routines perform the delay path
-- selection and output driving function.
--
-- Arguments:
--
-- IN Type Description
-- NewVal New value of the signal to be
-- assigned
-- OldVal Previous value of the signal.
-- Default value is 'X'
-- Delay The delay structure from which to
-- select the appropriate delay. The
-- function overload is based on the
-- type of delay passed. In the case of
-- the single delay, VitalDelayType, no
-- selection is performed, since there
-- is only one value to choose from.
-- For the other cases, the transition
-- from the old value to the new value
-- decide the value returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- Time The time value selected from the
-- Delay INPUT is returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN TIME;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPathDelay
--
-- Description: VitalPathDelay is the Level 1 routine used to select
-- the propagation delay path and schedule a new output
-- value.
--
-- For single and dual delay values, VitalDelayType and
-- VitalDelayType01 are used. The output value is
-- scheduled with a calculated delay without strength
-- modification.
--
-- For the six delay value, VitalDelayType01Z, the output
-- value is scheduled with a calculated delay. The drive
-- strength can be modified to handle weak signal strengths
-- to model tri-state devices, pull-ups and pull-downs as
-- an example.
--
-- The correspondence between the delay type and the
-- path delay function is as follows:
--
-- Delay Type Path Type
--
-- VitalDelayType VitalPathDelay
-- VitalDelayType01 VitalPathDelay01
-- VitalDelayType01Z VitalPathDelay01Z
--
-- For each of these routines, the following capabilities
-- is provided:
--
-- o Transition dependent path delay selection
-- o User controlled glitch detection with the ability
-- to generate "X" on output and report the violation
-- o Control of the severity level for message generation
-- o Scheduling of the computed values on the specified
-- signal.
--
-- Selection of the appropriate path delay begins with the
-- candidate paths. The candidate paths are selected by
-- identifying the paths for which the PathCondition is
-- true. If there is a single candidate path, then that
-- delay is selected. If there is more than one candidate
-- path, then the shortest delay is selected using
-- transition dependent delay selection. If there is no
-- candidate paths, then the delay specified by the
-- DefaultDelay parameter to the path delay is used.
--
-- Once the delay is known, the output signal is then
-- scheduled with that delay. In the case of
-- VitalPathDelay01Z, an additional result mapping of
-- the output value is performed before scheduling. The
-- result mapping is performed after transition dependent
-- delay selection but before scheduling the final output.
--
-- In order to perform glitch detection, the user is
-- obligated to provide a variable of VitalGlitchDataType
-- for the propagation delay functions to use. The user
-- cannot modify or use this information.
--
-- Arguments:
--
-- IN Type Description
-- OutSignalName string The name of the output signal
-- OutTemp std_logic The new output value to be driven
-- Paths VitalPathArrayType A list of paths of VitalPathArray
-- VitalPathArrayType01 type. The VitalPathDelay routine
-- VitalPathArrayType01Z is overloaded based on the type
-- of constant passed in. With
-- VitalPathArrayType01Z, the
-- resulting output strengths can be
-- mapped.
-- DefaultDelay VitalDelayType The default delay can be changed
-- VitalDelayType01 from zero-delay to another set of
-- VitalDelayType01Z values.
-- Mode VitalGlitchKindType The value of this constant
-- selects the type of glitch
-- detection.
-- OnEvent Glitch on transition event
-- | OnDetect Glitch immediate on detection
-- | VitalInertial No glitch, use INERTIAL
-- assignment
-- | VitalTransport No glitch, use TRANSPORT
-- assignment
-- XOn BOOLEAN Control for generation of 'X' on
-- glitch. When TRUE, 'X's are
-- scheduled for glitches, otherwise
-- no are generated.
-- MsgOn BOOLEAN Control for message generation on
-- glitch detect. When TRUE,
-- glitches are reported, otherwise
-- they are not reported.
-- MsgSeverity SEVERITY_LEVEL The level at which the message,
-- or assertion, will be reported.
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the output
-- can be mapped to alternate
-- strengths to model tri-state
-- devices, pull-ups and pull-downs.
--
-- INOUT
-- GlitchData VitalGlitchDataType The internal data storage
-- variable required to detect
-- glitches.
--
-- OUT
-- OutSignal std_logic The output signal to be driven
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalPathDelay (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01 (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01Z (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT OutputMap : IN VitalOutputMapType
:= VitalDefaultOutputMap
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalWireDelay
--
-- Description: VitalWireDelay is used to delay an input signal.
-- The delay is selected from the input parameter passed.
-- The function is useful for back annotation of actual
-- net delays.
--
-- The function is overloaded to permit passing a delay
-- value for twire for VitalDelayType, VitalDelayType01
-- and VitalDelayType01Z. twire is a generic which can
-- be back annotated and must be constructed to follow
-- the SDF to generic mapping rules.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The input signal (port) to be
-- delayed.
-- twire VitalDelayType The delay value for which the input
-- VitalDelayType01 signal should be delayed. For Vital-
-- VitalDelayType01Z DelayType, the value is single value
-- passed. For VitalDelayType01 and
-- VitalDelayType01Z, the appropriate
-- delay value is selected by VitalCalc-
-- Delay.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The internal delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01Z
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSignalDelay
--
-- Description: The VitalSignalDelay procedure is called in a signal
-- delay block in the architecture to delay the
-- appropriate test or reference signal in order to
-- accommodate negative constraint checks.
--
-- The amount of delay is of type TIME and is a constant.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The signal to be delayed.
-- dly TIME The amount of time the signal is
-- delayed.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSignalDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT dly : IN TIME
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSetupHoldCheck
--
-- Description: The VitalSetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal. A vector and scalar form are provided.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- std_logic_vector
-- TestSignalName STRING Name of test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- with RefSignal
-- SetupHigh TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a setup violation.
-- SetupLow TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a setup violation.
-- HoldHigh TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a hold violation.
-- HoldLow TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events on
-- the RefSignal which match the edge
-- spec. are used as reference edges.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalSetupHoldCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalRecoveryRemovalCheck
--
-- Description: The VitalRecoveryRemovalCheck detects the presence of
-- a recovery or removal violation on the input test
-- signal with respect to the corresponding input reference
-- signal. It assumes non-negative values of setup and
-- hold timing constraints. The timing constraint is
-- specified through parameters representing the recovery
-- and removal times associated with a reference edge of
-- the reference signal. A flag indicates whether a test
-- signal is asserted when it is high or when it is low.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative recovery times result in
-- a delayed reference signal. Negative removal times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of TestSignal. The routine is
-- TestSignalName STRING Name of TestSignal
-- TestDelay TIME Model internal delay associated with
-- the TestSignal
-- RefSignal std_ulogic Value of RefSignal
-- RefSignalName STRING Name of RefSignal
-- RefDelay TIME Model internal delay associated with
-- the RefSignal
-- Recovery TIME A change to an unasserted value on
-- the asynchronous TestSignal must
-- precede reference edge (on RefSignal)
-- by at least this time.
-- Removal TIME An asserted condition must be present
-- on the asynchronous TestSignal for at
-- least the removal time following a
-- reference edge on RefSignal.
-- ActiveLow BOOLEAN A flag which indicates if TestSignal
-- is asserted when it is low - "0."
-- FALSE indicate that TestSignal is
-- asserted when it has a value "1."
-- CheckEnabled BOOLEAN The check in enabled when the value
-- is TRUE, otherwise the constraints
-- are not checked.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specifier. Events on
-- RefSignal will match the edge
-- specified.
-- HeaderMsg STRING A header message that will accompany
-- any assertion message.
-- XOn BOOLEAN When TRUE, the output Violation is
-- set to "X." When FALSE, it is always
-- "0."
-- MsgOn BOOLEAN When TRUE, violation messages are
-- output. When FALSE, no messages are
-- generated.
-- MsgSeverity SEVERITY_LEVEL Severity level of the asserted
-- message.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalRecoveryRemovalCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalRecoveryRemovalCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT Recovery : IN TIME := 0 ns;
CONSTANT Removal : IN TIME := 0 ns;
CONSTANT ActiveLow : IN BOOLEAN := TRUE;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum and maximum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- Period TIME Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh TIME Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow TIME Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- PeriodData VitalPeriodDataType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- ------------------------------------------------------------------------
PROCEDURE VitalPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT Period : IN TIME := 0 ns;
CONSTANT PulseWidthHigh : IN TIME := 0 ns;
CONSTANT PulseWidthLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
END VITAL_Timing;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc437.vhd | 4 | 3256 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc437.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00437ent IS
END c03s02b01x01p19n01i00437ent;
ARCHITECTURE c03s02b01x01p19n01i00437arch OF c03s02b01x01p19n01i00437ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2positive_cons_vector is array (row,column) of positive;
constant C1 : s2positive_cons_vector := (others => (others => 1));
function complex_scalar(s : s2positive_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return s2positive_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : s2positive_cons_vector;
signal S2 : s2positive_cons_vector;
signal S3 : s2positive_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00437"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00437 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00437arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1867.vhd | 4 | 1992 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1867.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01867ent IS
END c07s01b00x00p08n01i01867ent;
ARCHITECTURE c07s01b00x00p08n01i01867arch OF c07s01b00x00p08n01i01867ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
signal s_int : small_int;
signal bool : boolean;
BEGIN
with c07s01b00x00p08n01i01867arch select --body name illegal here
obus <= (0 => 1, others => 0) after 5 ns when true;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01867 - Architecture body names are not permitted as primaries in a selected signal expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01867arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1581.vhd | 4 | 1846 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1581.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p02n01i01581ent IS
END c08s11b00x00p02n01i01581ent;
ARCHITECTURE c08s11b00x00p02n01i01581arch OF c08s11b00x00p02n01i01581ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for i in 1 to 10 loop
exit when i = 6;
k := i;
end loop;
assert NOT( k=5 )
report "***PASSED TEST: c08s11b00x00p02n01i01581"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s11b00x00p02n01i01581 - Exit statement consists of the reserved word 'exit' and optionally the reserved word 'when' followed by a condition "
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p02n01i01581arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1735.vhd | 4 | 3686 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1735.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s04b00x00p06n01i01735ent IS
END c09s04b00x00p06n01i01735ent;
ARCHITECTURE c09s04b00x00p06n01i01735arch OF c09s04b00x00p06n01i01735ent IS
signal arch_s1 : bit;
signal arch_s2 : boolean;
signal arch_s3 : character;
signal arch_s4 : severity_level;
signal arch_s5 : integer;
signal arch_s6 : real;
signal arch_s7 : time;
signal arch_s8 : positive;
signal arch_s9 : natural;
BEGIN
ASSERT arch_s1 /= bit'left
REPORT "bit concurrent assertion"
severity NOTE;
ASSERT arch_s2 /= boolean'left
REPORT "boolean concurrent assertion"
severity NOTE;
ASSERT arch_s3 /= character'left
REPORT "character concurrent assertion"
severity NOTE;
ASSERT arch_s4 /= severity_level'left
REPORT "severity_level concurrent assertion"
severity NOTE;
ASSERT arch_s5 /= integer'left
REPORT "integer concurrent assertion"
severity NOTE;
ASSERT arch_s6 /= real'left
REPORT "real concurrent assertion"
severity NOTE;
ASSERT arch_s7 /= time'left
REPORT "time concurrent assertion"
severity NOTE;
ASSERT arch_s8 /= positive'left
REPORT "positive concurrent assertion"
severity NOTE;
ASSERT arch_s9 /= natural'left
REPORT "natural concurrent assertion"
severity NOTE;
TESTING: PROCESS
BEGIN
ASSERT arch_s1 /= bit'left
REPORT "bit concurrent assertion"
severity NOTE;
ASSERT arch_s2 /= boolean'left
REPORT "boolean concurrent assertion"
severity NOTE;
ASSERT arch_s3 /= character'left
REPORT "character concurrent assertion"
severity NOTE;
ASSERT arch_s4 /= severity_level'left
REPORT "severity_level concurrent assertion"
severity NOTE;
ASSERT arch_s5 /= integer'left
REPORT "integer concurrent assertion"
severity NOTE;
ASSERT arch_s6 /= real'left
REPORT "real concurrent assertion"
severity NOTE;
ASSERT arch_s7 /= time'left
REPORT "time concurrent assertion"
severity NOTE;
ASSERT arch_s8 /= positive'left
REPORT "positive concurrent assertion"
severity NOTE;
ASSERT arch_s9 /= natural'left
REPORT "natural concurrent assertion"
severity NOTE;
assert FALSE
report "***PASSED TEST: c09s04b00x00p06n01i01735 - This need manual check - The concurrent assertion statement and the sequential assertion should print out the same ASSERTION NOTES."
severity NOTE;
wait;
END PROCESS TESTING;
END c09s04b00x00p06n01i01735arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd | 4 | 1752 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity synchronized_module is
end entity synchronized_module;
architecture test of synchronized_module is
use work.synchronize.all;
signal barrier : std_logic;
begin
pullup : barrier <= 'H';
-- code from book
synchronized_module : process is
-- . . .
begin
init_synchronize(barrier);
-- . . .
loop
-- . . .
begin_synchronize(barrier);
-- . . . -- perform operation, synchronized with other processes
end_synchronize(barrier);
-- . . .
end loop;
end process synchronized_module;
-- end code from book
another_synchronized_module : process is
begin
init_synchronize(barrier);
loop
wait for 10 ns;
begin_synchronize(barrier);
-- . . . -- perform operation, synchronized with other processes
end_synchronize(barrier);
end loop;
end process another_synchronized_module;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1403.vhd | 4 | 1917 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1403.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p06n01i01403ent IS
END c08s05b00x00p06n01i01403ent;
ARCHITECTURE c08s05b00x00p06n01i01403arch OF c08s05b00x00p06n01i01403ent IS
BEGIN
TESTING: PROCESS
variable T : INTEGER := 1;
subtype ST is BIT_VECTOR(T to 10);
variable OK : BIT_VECTOR(T+1 to 11);
variable ILL : BIT_VECTOR(T to 11);
variable V : ST;
BEGIN
V := OK;
assert NOT(V = "0000000000")
report "***PASSED TEST: c08s05b00x00p06n01i01403"
severity NOTE;
assert (V = "0000000000")
report "***FAILED TEST: c08s05b00x00p06n01i01403 - Variable assignment scalar subtype check test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p06n01i01403arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc117.vhd | 4 | 3174 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc117.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
Package c04s03b02x00p29n10i00117pkg is
type Apollo_string is array (INTEGER range 1 to 8) of CHARACTER;
type V_REGISTER is array (INTEGER range 0 to 7) of BIT;
end c04s03b02x00p29n10i00117pkg;
use work.c04s03b02x00p29n10i00117pkg.all;
ENTITY c04s03b02x00p29n10i00117ent IS
port (
p23 : buffer Boolean := FALSE;
p24 : buffer Bit := '0' ;
p25 : buffer Character := NUL ;
p26 : buffer SEVERITY_LEVEL := NOTE ;
p27 : buffer Integer := -1 ;
p28 : buffer Real := -1.0 ;
p29 : buffer TIME := 1 fs ;
p30 : buffer Natural := 0 ;
p31 : buffer Positive := 1 ;
p32 : buffer Apollo_string := "abcdefgh";
p33 : buffer V_register := B"10010110"
);
END c04s03b02x00p29n10i00117ent;
ARCHITECTURE c04s03b02x00p29n10i00117arch OF c04s03b02x00p29n10i00117ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( p23 = FALSE and
p24 = '0' and
p25 = NUL and
p26 = NOTE and
p27 = -1 and
p28 = -1.0 and
p29 = 1 fs and
p30 = 0 and
p31 = 1 and
p32 = "abcdefgh"and
p33 = B"10010110" )
report "***PASSED TEST: c04s03b02x00p29n10i00117"
severity NOTE;
assert ( p23 = FALSE and
p24 = '0' and
p25 = NUL and
p26 = NOTE and
p27 = -1 and
p28 = -1.0 and
p29 = 1 fs and
p30 = 0 and
p31 = 1 and
p32 = "abcdefgh"and
p33 = B"10010110" )
report "***FAILED TEST: c04s03b02x00p29n10i00117 - The buffer ports on entities should be able to read."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n10i00117arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2377.vhd | 4 | 1868 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2377.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p02n01i02377ent IS
END c07s03b02x00p02n01i02377ent;
ARCHITECTURE c07s03b02x00p02n01i02377arch OF c07s03b02x00p02n01i02377ent IS
BEGIN
TESTING: PROCESS
type ENUM is ( ONE, TWO, THREE, FOUR );
function F_ENUM ( A : ENUM := ONE;
B : ENUM := TWO ) return ENUM is
begin
return A;
end F_ENUM;
variable V : ENUM := F_ENUM(,); -- Failure_here
-- SYNTAX ERROR: null parameter association not legal.
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x00p02n01i02377 - Null association element is not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p02n01i02377arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc473.vhd | 4 | 5454 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc473.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00473ent IS
END c03s02b01x01p19n01i00473ent;
ARCHITECTURE c03s02b01x01p19n01i00473arch OF c03s02b01x01p19n01i00473ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
type array_rec_2cons is array (integer range <>) of record_2cons_array;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C41 : s2boolean_cons_vector := (others => (others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others => (others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others => (others => C6));
constant C47 : s2time_cons_vector := (others => (others => C7));
constant C48 : s2natural_cons_vector := (others => (others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
constant C66 : array_rec_2cons(0 to 7) := (others => C52) ;
function complex_scalar(s : array_rec_2cons(0 to 7)) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_2cons is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_2cons(0 to 7);
signal S2 : array_rec_2cons(0 to 7);
signal S3 : array_rec_2cons(0 to 7):= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00473"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00473 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00473arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc839.vhd | 4 | 2435 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc839.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s03b01x00p03n01i00839ent_a is
end c01s03b01x00p03n01i00839ent_a;
architecture c01s03b01x00p03n01i00839arch_a of c01s03b01x00p03n01i00839ent_a is
begin
AC_BLK : block
signal B : BIT;
begin
B <= '1';
end block;
end c01s03b01x00p03n01i00839arch_a;
ENTITY c01s03b01x00p03n01i00839ent IS
END c01s03b01x00p03n01i00839ent;
ARCHITECTURE c01s03b01x00p03n01i00839arch OF c01s03b01x00p03n01i00839ent IS
BEGIN
A_BLK : block
component C
end component;
begin
L1 : C;
L2 : C;
L3 : C;
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s03b01x00p03n01i00839"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s03b01x00p03n01i00839arch;
configuration c01s03b01x00p03n01i00839cfg of c01s03b01x00p03n01i00839ent is
--- Failure_here; Missing architecture name
for A_BLK
for L1 : C
use entity work.c01s03b01x00p03n01i00839ent_a (c01s03b01x00p03n01i00839arch_a) ;
end for;
for L2 : C
use entity work.c01s03b01x00p03n01i00839ent_a (c01s03b01x00p03n01i00839arch_a) ;
end for;
for L3 : C
use entity work.c01s03b01x00p03n01i00839ent_a (c01s03b01x00p03n01i00839arch_a) ;
end for;
end for;
end c01s03b01x00p03n01i00839cfg;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2322.vhd | 4 | 1721 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2322.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02322ent IS
END c07s02b07x00p01n01i02322ent;
ARCHITECTURE c07s02b07x00p01n01i02322arch OF c07s02b07x00p01n01i02322ent IS
BEGIN
TESTING: PROCESS
type WORD is array(0 to 31) of BIT;
type WORDPTR is access WORD;
variable WORDPTRV : WORDPTR;
BEGIN
WORDPTRV := ABS WORDPTRV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02322 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02322arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofpt-b.vhd | 4 | 1763 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tofpt-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture bench of to_fp_test is
signal vec : std_ulogic_vector(15 downto 0);
signal r : real;
begin
dut : entity work.to_fp(behavioral)
port map (vec, r);
stimulus : process is
begin
vec <= X"0000"; wait for 10 ns;
vec <= X"8000"; wait for 10 ns;
vec <= X"7FFF"; wait for 10 ns;
vec <= X"4000"; wait for 10 ns;
vec <= X"C000"; wait for 10 ns;
wait;
end process stimulus;
end architecture bench;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2190.vhd | 4 | 1828 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2190.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p01n02i02190ent IS
END c07s02b00x00p01n02i02190ent;
ARCHITECTURE c07s02b00x00p01n02i02190arch OF c07s02b00x00p01n02i02190ent IS
BEGIN
TESTING: PROCESS
type A_ARRAY is array (1 to 2) of CHARACTER;
variable I : INTEGER;
variable R : REAL;
variable B : BOOLEAN;
variable A : A_ARRAY;
BEGIN
R := R - - R; -- Failure_here
-- SYNTAX ERROR: signed operator cannot follow adding operator.
assert FALSE
report "***FAILED TEST: c07s02b00x00p01n02i02190 - Signed operand cannot follow a mutiplying operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p01n02i02190arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc643.vhd | 4 | 2393 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc643.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:52 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00643ent IS
END c03s04b01x00p01n01i00643ent;
ARCHITECTURE c03s04b01x00p01n01i00643arch OF c03s04b01x00p01n01i00643ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
constant C1 : boolean := true;
constant C2 : boolean_vector_range := (others => C1);
type boolean_vector_range_file is file of boolean_vector_range;
BEGIN
TESTING: PROCESS
file filein : boolean_vector_range_file open write_mode is "iofile.46";
BEGIN
for i in 1 to 100 loop
write(filein, C2);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00643 - The output file will be verified by test s010298.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00643arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2136.vhd | 4 | 2169 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2136.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02136ent IS
END c07s02b04x00p21n01i02136ent;
ARCHITECTURE c07s02b04x00p21n01i02136arch OF c07s02b04x00p21n01i02136ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_5 is positive_v (1 to 5);
SUBTYPE positive_4 is positive_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : positive_5;
variable l_operand : positive := 1 ;
variable r_operand : positive_4 := ( 1 , 89 , 1 , 89 );
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result = ( 1 , 1 , 89 , 1 , 89 ))
report "***PASSED TEST: c07s02b04x00p21n01i02136"
severity NOTE;
assert ( result = ( 1 , 1 , 89 , 1 , 89 ))
report "***FAILED TEST: c07s02b04x00p21n01i02136 - Concatenation of element and POSITIVE array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02136arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2812.vhd | 4 | 1602 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2812.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity NAND is
end NAND;
ENTITY c13s09b00x00p99n01i02812ent IS
END c13s09b00x00p99n01i02812ent;
ARCHITECTURE c13s09b00x00p99n01i02812arch OF c13s09b00x00p99n01i02812ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02812 - Reserved word NAND can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02812arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc862.vhd | 4 | 10419 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc862.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00862pkg_b is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00862pkg_b;
package body c01s03b01x00p12n01i00862pkg_b is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00862pkg_b;
use work.c01s03b01x00p12n01i00862pkg_b.all;
package c01s03b01x00p12n01i00862pkg_a is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant dumy : bit_vector(zero to three) := "1010" ;
signal Sin1 : bit_vector(zero to six) ;
signal Sin2 : boolean_vector(zero to six) ;
signal Sin4 : severity_level_vector(zero to six) ;
signal Sin5 : integer_vector(zero to six) ;
signal Sin6 : real_vector(zero to six) ;
signal Sin7 : time_vector(zero to six) ;
signal Sin8 : natural_vector(zero to six) ;
signal Sin9 : positive_vector(zero to six) ;
signal Sin10: array_rec_std(zero to six) ;
end c01s03b01x00p12n01i00862pkg_a;
use work.c01s03b01x00p12n01i00862pkg_a.all;
use work.c01s03b01x00p12n01i00862pkg_b.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00862pkg_a.all;
use work.c01s03b01x00p12n01i00862pkg_b.all;
ENTITY c01s03b01x00p12n01i00862ent IS
END c01s03b01x00p12n01i00862ent;
ARCHITECTURE c01s03b01x00p12n01i00862arch OF c01s03b01x00p12n01i00862ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
Gif : if fifteen = 15 generate
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
end generate;
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00862"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00862 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00862arch;
configuration c01s03b01x00p12n01i00862cfg of c01s03b01x00p12n01i00862ent is
for c01s03b01x00p12n01i00862arch
for K
for GIF
for T5:test use configuration work.testbench;
end for;
end for;
for G(dumy'low to 1)
for T1:test
use configuration work.testbench;
end for;
end for;
for G(2 to dumy'high)
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1029.vhd | 4 | 2272 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1029.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p02n01i01029ent IS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type A2 is array (THREE, THREE) of BOOLEAN;
type A3 is array (THREE) of A1;
type R1 is record
RE1: A1;
end record;
type R2 is record
RE2: A2;
end record;
type R3 is record
RE3: A3;
end record;
END c06s04b00x00p02n01i01029ent;
ARCHITECTURE c06s04b00x00p02n01i01029arch OF c06s04b00x00p02n01i01029ent IS
BEGIN
TESTING: PROCESS
variable V: BOOLEAN;
variable V1: R1 ; -- := (RE1=>(others=>TRUE));
variable V2: R2 ; -- := (RE2=>(others=>(others=>TRUE)));
variable V3: R3 ; -- := (RE3=>(others=>(others=>TRUE)));
BEGIN
V := V2.RE2(2, 3);
assert NOT( V=false )
report "***PASSED TEST: c06s04b00x00p02n01i01029"
severity NOTE;
assert ( V=false )
report "***FAILED TEST: c06s04b00x00p02n01i01029 - The prefix of an indexed name can be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01029arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inverting_integrator.vhd | 4 | 1532 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inverting_integrator is
port ( terminal input, output : electrical );
end entity inverting_integrator;
----------------------------------------------------------------
architecture structural of inverting_integrator is
terminal internal : electrical;
begin
r1 : entity work.resistor(ideal)
port map ( node1 => input, node2 => internal ) ;
c1 : entity work.capacitor(leakage)
port map ( node1 => internal, node2 => output );
amp : entity work.opamp(slew_limited)
port map ( plus_in => electrical_ref, minus_in => internal,
output => output );
end architecture structural;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2663.vhd | 4 | 1589 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2663.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02663ent IS
END c13s03b01x00p02n01i02663ent;
ARCHITECTURE c13s03b01x00p02n01i02663arch OF c13s03b01x00p02n01i02663ent IS
BEGIN
TESTING: PROCESS
variable $k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02663 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02663arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc330.vhd | 4 | 1772 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc330.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p05n01i00330ent IS
END c03s02b01x00p05n01i00330ent;
ARCHITECTURE c03s02b01x00p05n01i00330arch OF c03s02b01x00p05n01i00330ent IS
type bit_vctor is array (natural range <>) of bit;
type str_vctor is array (natural <>) of character; -- Failure_here
type matrix is array (integer range <>) of real;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x00p05n01i00330 - The reserved word range in the unconstrained array definition is missing."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p05n01i00330arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1545.vhd | 4 | 1968 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1545.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01545ent IS
END c08s09b00x00p10n01i01545ent;
ARCHITECTURE c08s09b00x00p10n01i01545arch OF c08s09b00x00p10n01i01545ent IS
BEGIN
TESTING: PROCESS
variable counter : integer := 0;
BEGIN
for i in severity_level loop
counter := counter + 1;
end loop;
assert NOT(counter=severity_level'Pos(severity_level'High)-severity_level'Pos(severity_level'Low)+1)
report "***PASSED TEST: c08s09b00x00p10n01i01545"
severity NOTE;
assert (counter=severity_level'Pos(severity_level'High)-severity_level'Pos(severity_level'Low)+1)
report "***FAILED TEST: c08s09b00x00p10n01i01545 - The loop is executed once for each of the values in the range."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01545arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug09/univ1.vhdl | 3 | 807 | entity univ1 is
end entity;
architecture foo of univ1 is
signal i: integer := Time'POS(Time'High); -- should produce error
-- 6.4.2.3 Signal declarations, para 5, first sentence:
-- If the signal declaration includes the assignment symbol followed by an
-- expression, it shall be of the same type as the signal. Such an
-- expression is said to be a default expression.
--
-- -1993 4.3.1.2 Signal declarations, para 6, first sentence:
-- If the signal declaration includes the assignment symbol followed by
-- an expression, it must be of the same type as the signal.
-- 'POS returns universal integer
--
begin
assert False
report "i = " & integer'IMAGE(i) -- shows left clipping instead of error
severity ERROR;
end architecture; | gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc400.vhd | 4 | 1850 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc400.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p08n01i00400ent IS
END c03s02b01x01p08n01i00400ent;
ARCHITECTURE c03s02b01x01p08n01i00400arch OF c03s02b01x01p08n01i00400ent IS
type MEM is array (positive range <>) of BIT;
attribute X : MEM;
attribute X of MEM: type is ('1','0','1') ; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(MEM'X(1)='1' and MEM'X(2)='0' and MEM'X(3)='1')
report "***PASSED TEST: c03s02b01x01p08n01i00400"
severity NOTE;
assert (MEM'X(1)='1' and MEM'X(2)='0' and MEM'X(3)='1')
report "***FAILED TEST: c03s02b01x01p08n01i00400 - "
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p08n01i00400arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2446.vhd | 4 | 1961 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2446.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p02n01i02446ent IS
END c07s03b02x02p02n01i02446ent;
ARCHITECTURE c07s03b02x02p02n01i02446arch OF c07s03b02x02p02n01i02446ent IS
BEGIN
TESTING: PROCESS
type T1 is array (1 to 10) of Integer;
constant C : T1 := (1 => 2, 2=>4, 3 =>6, 4 =>5, others =>10) ; -- No_failure_here
BEGIN
assert NOT(C(1)=2 and C(2)=4 and C(3)=6 and C(4)=5 and C(5)=10 and C(6)=10)
report "***PASSED TEST: c07s03b02x02p02n01i02446"
severity NOTE;
assert (C(1)=2 and C(2)=4 and C(3)=6 and C(4)=5 and C(5)=10 and C(6)=10)
report "***FAILED TEST: c07s03b02x02p02n01i02446 - All element associations of an array aggregate must be either all positional or all named."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p02n01i02446arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1539.vhd | 4 | 1791 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1539.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01539ent IS
END c08s09b00x00p10n01i01539ent;
ARCHITECTURE c08s09b00x00p10n01i01539arch OF c08s09b00x00p10n01i01539ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for i in 1 to 5 loop
k := k + 1;
end loop;
assert NOT( k=5 )
report "***PASSED TEST: c08s09b00x00p10n01i01539"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s09b00x00p10n01i01539 - The sequence of statements is executed once for each value of the discrete range"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01539arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovec.vhd | 4 | 1248 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tovec.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity to_vector is
port ( r : in real;
vec : out std_ulogic_vector(15 downto 0) );
end entity to_vector;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc646.vhd | 4 | 1698 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ENTITY c03s04b01x00p01n01i00646ent IS
END c03s04b01x00p01n01i00646ent;
ARCHITECTURE c03s04b01x00p01n01i00646arch OF c03s04b01x00p01n01i00646ent IS
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_file is file of current;
constant C47 : current := 1 A;
BEGIN
TESTING: PROCESS
file filein : current_file open write_mode is "iofile.62";
BEGIN
for i in 1 to 100 loop
write(filein, C47);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00646 - The output file will be verified by test s010292.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00646arch;
| gpl-2.0 |
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