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545/Atari7800 | core/cpu6502_true_cycle/tags/arelease/rtl/vhdl/fsm_execution_unit.vhd | 2 | 189939 | -- VHDL Entity R6502_TC.FSM_Execution_Unit.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:42:53 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity FSM_Execution_Unit is
port(
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic;
nmi_i : in std_logic;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic;
reg_0flag_i : in std_logic;
reg_1flag_i : in std_logic;
reg_7flag_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
fetch_o : out std_logic;
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic;
ld_sp_o : out std_logic;
load_regs_o : out std_logic;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic;
sel_pc_as_o : out std_logic;
sel_pc_in_o : out std_logic;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic;
sel_sp_in_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
);
-- Declarations
end FSM_Execution_Unit ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- [email protected]
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
-- <<-- more -->>
-- Title: FSM Execution Unit for all op codes
-- Path: R6502_TC/FSM_Execution_Unit/fsm
-- Edited: by eda on 04 Jan 2009
--
-- VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:42:55 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture fsm of FSM_Execution_Unit is
-- Architecture Declarations
signal reg_F : std_logic_vector( 7 DOWNTO 0 );
signal reg_PC : std_logic_vector(15 DOWNTO 0);
signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 );
signal reg_sel_pc_as : std_logic;
signal reg_sel_pc_in : std_logic;
signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_sp_as : std_logic;
signal reg_sel_sp_in : std_logic;
signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
signal sig_PC : std_logic_vector(15 DOWNTO 0);
signal sig_RD : std_logic;
signal sig_RWn : std_logic;
signal sig_SYNC : std_logic;
signal sig_WR : std_logic;
signal zw_ALU : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU1 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU2 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU3 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU4 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU5 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU6 : std_logic_vector( 8 DOWNTO 0 );
signal zw_PC : std_logic_vector( 15 DOWNTO 0 );
signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 );
signal zw_REG_NMI : std_logic;
signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0);
signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );
signal zw_so : std_logic;
signal zw_w1 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w2 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w3 : std_logic_vector( 15 DOWNTO 0 );
subtype state_type is
std_logic_vector(7 downto 0);
-- State vector declaration
attribute state_vector : string;
attribute state_vector of fsm : architecture is "current_state";
-- Hard encoding
constant FETCH : state_type := "00000000";
constant s1 : state_type := "00000001";
constant s2 : state_type := "00000011";
constant s5 : state_type := "00000010";
constant s3 : state_type := "00000110";
constant s4 : state_type := "00000111";
constant s12 : state_type := "00000101";
constant s16 : state_type := "00000100";
constant s17 : state_type := "00001100";
constant s24 : state_type := "00001101";
constant s25 : state_type := "00001111";
constant s271 : state_type := "00001110";
constant s273 : state_type := "00001010";
constant s304 : state_type := "00001011";
constant s307 : state_type := "00001001";
constant s177 : state_type := "00001000";
constant s180 : state_type := "00011000";
constant s181 : state_type := "00011001";
constant s182 : state_type := "00011011";
constant s183 : state_type := "00011010";
constant s184 : state_type := "00011110";
constant s185 : state_type := "00011111";
constant s186 : state_type := "00011101";
constant s187 : state_type := "00011100";
constant s188 : state_type := "00010100";
constant s189 : state_type := "00010101";
constant s190 : state_type := "00010111";
constant s191 : state_type := "00010110";
constant s192 : state_type := "00010010";
constant s193 : state_type := "00010011";
constant s377 : state_type := "00010001";
constant s381 : state_type := "00010000";
constant s378 : state_type := "00110000";
constant s382 : state_type := "00110001";
constant s379 : state_type := "00110011";
constant s383 : state_type := "00110010";
constant s384 : state_type := "00110110";
constant s380 : state_type := "00110111";
constant s385 : state_type := "00110101";
constant s386 : state_type := "00110100";
constant s387 : state_type := "00111100";
constant s388 : state_type := "00111101";
constant s389 : state_type := "00111111";
constant s391 : state_type := "00111110";
constant s392 : state_type := "00111010";
constant s390 : state_type := "00111011";
constant s393 : state_type := "00111001";
constant s394 : state_type := "00111000";
constant s395 : state_type := "00101000";
constant s396 : state_type := "00101001";
constant s397 : state_type := "00101011";
constant s398 : state_type := "00101010";
constant s399 : state_type := "00101110";
constant s400 : state_type := "00101111";
constant s401 : state_type := "00101101";
constant s526 : state_type := "00101100";
constant s527 : state_type := "00100100";
constant s528 : state_type := "00100101";
constant s529 : state_type := "00100111";
constant s530 : state_type := "00100110";
constant s531 : state_type := "00100010";
constant s544 : state_type := "00100011";
constant s545 : state_type := "00100001";
constant s546 : state_type := "00100000";
constant s547 : state_type := "01100000";
constant s549 : state_type := "01100001";
constant s550 : state_type := "01100011";
constant s404 : state_type := "01100010";
constant s556 : state_type := "01100110";
constant s557 : state_type := "01100111";
constant s579 : state_type := "01100101";
constant s201 : state_type := "01100100";
constant s202 : state_type := "01101100";
constant s210 : state_type := "01101101";
constant s211 : state_type := "01101111";
constant s215 : state_type := "01101110";
constant s217 : state_type := "01101010";
constant s218 : state_type := "01101011";
constant s222 : state_type := "01101001";
constant s223 : state_type := "01101000";
constant s224 : state_type := "01111000";
constant s225 : state_type := "01111001";
constant s226 : state_type := "01111011";
constant s243 : state_type := "01111010";
constant s244 : state_type := "01111110";
constant s247 : state_type := "01111111";
constant s344 : state_type := "01111101";
constant s343 : state_type := "01111100";
constant s250 : state_type := "01110100";
constant s251 : state_type := "01110101";
constant s351 : state_type := "01110111";
constant s361 : state_type := "01110110";
constant s360 : state_type := "01110010";
constant s403 : state_type := "01110011";
constant s406 : state_type := "01110001";
constant s407 : state_type := "01110000";
constant s409 : state_type := "01010000";
constant s412 : state_type := "01010001";
constant s413 : state_type := "01010011";
constant s416 : state_type := "01010010";
constant s418 : state_type := "01010110";
constant s510 : state_type := "01010111";
constant s553 : state_type := "01010101";
constant s555 : state_type := "01010100";
constant s558 : state_type := "01011100";
constant s560 : state_type := "01011101";
constant s561 : state_type := "01011111";
constant s563 : state_type := "01011110";
constant s564 : state_type := "01011010";
constant s565 : state_type := "01011011";
constant s566 : state_type := "01011001";
constant s266 : state_type := "01011000";
constant s301 : state_type := "01001000";
constant s302 : state_type := "01001001";
constant RES : state_type := "01001011";
constant s511 : state_type := "01001010";
constant s559 : state_type := "01001110";
constant s562 : state_type := "01001111";
constant s567 : state_type := "01001101";
constant s568 : state_type := "01001100";
constant s569 : state_type := "01000100";
constant s570 : state_type := "01000101";
constant s571 : state_type := "01000111";
constant s572 : state_type := "01000110";
constant s573 : state_type := "01000010";
constant s574 : state_type := "01000011";
constant s548 : state_type := "01000001";
constant s551 : state_type := "01000000";
constant s552 : state_type := "11000000";
constant s575 : state_type := "11000001";
constant s576 : state_type := "11000011";
constant s577 : state_type := "11000010";
constant s532 : state_type := "11000110";
constant s533 : state_type := "11000111";
constant s534 : state_type := "11000101";
constant s535 : state_type := "11000100";
constant s536 : state_type := "11001100";
constant s537 : state_type := "11001101";
-- Declare current and next state signals
signal current_state : state_type;
signal next_state : state_type;
-- Declare any pre-registered internal signals
signal d_o_cld : std_logic_vector ( 7 downto 0 );
signal rd_o_cld : std_logic ;
signal sync_o_cld : std_logic ;
signal wr_n_o_cld : std_logic ;
signal wr_o_cld : std_logic ;
begin
-----------------------------------------------------------------
clocked_proc : process (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
begin
if (rst_rst_n_i = '0') then
current_state <= RES;
-- Default Reset Values
d_o_cld <= X"00";
rd_o_cld <= '0';
sync_o_cld <= '0';
wr_n_o_cld <= '1';
wr_o_cld <= '0';
reg_F <= "00000100";
reg_PC <= X"0000";
reg_PC1 <= X"0000";
reg_sel_pc_as <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_rb_in <= "00";
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_sp_as <= '0';
reg_sel_sp_in <= '0';
sig_PC <= X"0000";
zw_PC <= X"0000";
zw_REG_ALU <= '0' & X"00";
zw_REG_NMI <= '0';
zw_REG_OP <= X"00";
zw_REG_sig_PC <= X"0000";
zw_b1 <= X"00";
zw_b2 <= X"00";
zw_b3 <= X"00";
zw_b4 <= X"00";
zw_so <= '0';
zw_w1 <= X"0000";
zw_w2 <= X"0000";
zw_w3 <= X"0000";
elsif (clk_clk_i'event and clk_clk_i = '1') then
current_state <= next_state;
-- Default Assignment To Internals
reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);
reg_PC <= reg_PC;
reg_PC1 <= reg_PC1;
reg_sel_pc_as <= reg_sel_pc_as;
reg_sel_pc_in <= reg_sel_pc_in;
reg_sel_pc_val <= reg_sel_pc_val;
reg_sel_rb_in <= reg_sel_rb_in;
reg_sel_rb_out <= reg_sel_rb_out;
reg_sel_reg <= reg_sel_reg;
reg_sel_sp_as <= reg_sel_sp_as;
reg_sel_sp_in <= reg_sel_sp_in;
sig_PC <= sig_PC;
zw_PC <= zw_PC;
zw_REG_ALU <= zw_REG_ALU;
zw_REG_NMI <= zw_REG_NMI or nmi_i;
zw_REG_OP <= zw_REG_OP;
zw_REG_sig_PC <= zw_REG_sig_PC;
zw_b1 <= zw_b1;
zw_b2 <= zw_b2;
zw_b3 <= zw_b3;
zw_b4 <= zw_b4;
zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));
zw_w1 <= zw_w1;
zw_w2 <= zw_w2;
zw_w3 <= zw_w3;
d_o_cld <= sig_D_OUT;
rd_o_cld <= sig_RD;
sync_o_cld <= sig_SYNC;
wr_n_o_cld <= sig_RWn;
wr_o_cld <= sig_WR;
-- Combined Actions
case current_state is
when FETCH =>
zw_REG_OP <= d_i;
if ((nmi_i = '1') and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
zw_REG_NMI <= '0';
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b1(0) <= reg_F(7);
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
zw_b3 <= adr_nxt_pc_i (15 downto 8);
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"00") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"18") and (rdy_i = '1')) then
elsif ((d_i = X"D8") and (rdy_i = '1')) then
elsif ((d_i = X"58") and (rdy_i = '1')) then
elsif ((d_i = X"B8") and (rdy_i = '1')) then
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
zw_b4 <= X"FF";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"CA") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
elsif ((d_i = X"88") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
zw_b4 <= X"01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"E8") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
elsif ((d_i = X"C8") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"20") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
elsif ((d_i = X"48") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"08") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"68") and (rdy_i = '1')) then
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"28") and (rdy_i = '1')) then
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"40") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"60") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b1(0) <= reg_F(7);
elsif ((d_i = X"38") and (rdy_i = '1')) then
elsif ((d_i = X"F8") and (rdy_i = '1')) then
elsif ((d_i = X"78") and (rdy_i = '1')) then
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"AA") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "01";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"0A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"4A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"2A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"6A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"A8") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "10";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"98") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "00";
reg_sel_rb_in <= "01";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"BA") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"8A") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "00";
reg_sel_rb_in <= "10";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"9A") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "11";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
end if;
when s1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s2 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s5 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s3 =>
sig_PC <= adr_pc_i;
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s12 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s16 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s17 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s24 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(6) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s25 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s271 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
zw_b1 <= d_i;
end if;
when s273 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
zw_b2 <= d_i;
end if;
when s304 =>
if (rdy_i = '1') then
sig_PC <= zw_b2 & adr_pc_i(7 downto 0);
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
end if;
when s307 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s177 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s180 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s181 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s182 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s183 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s184 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s185 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s186 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s187 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s188 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s189 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s190 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s191 =>
sig_PC <= zw_b3 & zw_b1;
when s192 =>
sig_PC <= d_i & zw_b1;
when s193 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s377 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s381 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s378 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s382 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s383 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s384 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s385 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s386 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F <= d_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s387 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s388 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s389 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
reg_F <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
end if;
when s391 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end if;
when s392 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s390 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s393 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s394 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
end if;
when s395 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s396 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s397 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end if;
when s399 =>
sig_PC <= adr_sp_i;
when s400 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
when s401 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1 (7 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s526 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s527 =>
sig_PC <= adr_sp_i;
when s528 =>
sig_PC <= adr_sp_i;
when s529 =>
sig_PC <= X"FFFE";
when s530 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s531 =>
if (rdy_i = '1') then
sig_PC <= X"FFFF";
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
end if;
when s544 =>
sig_PC <= adr_sp_i;
when s545 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
when s546 =>
sig_PC <= adr_pc_i;
when s547 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
zw_w1 (7 downto 0) <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
end if;
when s549 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_w1 (7 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s550 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
when s404 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s556 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s557 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s579 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s201 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
sig_PC <= X"00" & d_i;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s202 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s210 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s211 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s215 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s217 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s218 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s222 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s223 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s226 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s243 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s244 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s247 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s344 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s343 =>
if (rdy_i = '1') then
zw_b1 <= d_alu_i;
end if;
when s251 =>
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end if;
when s361 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= d_i(7);
reg_F(6) <= d_i(6);
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s360 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s403 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end if;
when s406 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s407 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s409 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s412 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s416 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
zw_b1 <= d_i(6 downto 0) & '0';
zw_b2(0) <= d_i(7);
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
zw_b1 <= '0' & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
zw_b1 <= d_i(6 downto 0) & reg_F(0);
zw_b2(0) <= d_i(7);
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
zw_b1 <= reg_F(0) & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
end if;
when s418 =>
sig_PC <= adr_pc_i;
reg_F(0) <= zw_b2(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s553 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s555 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s558 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s560 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s561 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s563 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s564 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s566 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s266 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "10";
zw_b2 <= d_i;
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
end if;
when s302 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when RES =>
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_pc_as <= '0';
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s559 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s562 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s567 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s568 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s569 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s570 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s571 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s572 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s573 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s548 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s551 =>
sig_PC <= adr_sp_i;
when s552 =>
sig_PC <= adr_sp_i;
when s575 =>
if (rdy_i = '1') then
sig_PC <= X"FFFF";
zw_b1 <= d_i;
end if;
when s576 =>
sig_PC <= X"FFFE";
when s577 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s532 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s533 =>
sig_PC <= adr_sp_i;
when s534 =>
sig_PC <= adr_sp_i;
when s535 =>
if (rdy_i = '1') then
sig_PC <= X"FFFB";
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
end if;
when s536 =>
sig_PC <= X"FFFA";
when s537 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when others =>
null;
end case;
end if;
end process clocked_proc;
-----------------------------------------------------------------
nextstate_proc : process (
adr_nxt_pc_i,
current_state,
d_i,
irq_n_i,
nmi_i,
rdy_i,
reg_F,
zw_REG_OP,
zw_b2,
zw_b3
)
-----------------------------------------------------------------
begin
case current_state is
when FETCH =>
if ((nmi_i = '1') and (rdy_i = '1')) then
next_state <= s532;
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
next_state <= s548;
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
next_state <= s510;
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
next_state <= s266;
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
next_state <= s351;
elsif ((d_i = X"00") and (rdy_i = '1')) then
next_state <= s526;
elsif ((d_i = X"18") and (rdy_i = '1')) then
next_state <= s12;
elsif ((d_i = X"D8") and (rdy_i = '1')) then
next_state <= s16;
elsif ((d_i = X"58") and (rdy_i = '1')) then
next_state <= s17;
elsif ((d_i = X"B8") and (rdy_i = '1')) then
next_state <= s24;
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
next_state <= s226;
elsif ((d_i = X"CA") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"88") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
next_state <= s226;
elsif ((d_i = X"E8") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"C8") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
next_state <= s271;
elsif ((d_i = X"20") and (rdy_i = '1')) then
next_state <= s397;
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
next_state <= s1;
elsif ((d_i = X"48") and (rdy_i = '1')) then
next_state <= s377;
elsif ((d_i = X"08") and (rdy_i = '1')) then
next_state <= s378;
elsif ((d_i = X"68") and (rdy_i = '1')) then
next_state <= s379;
elsif ((d_i = X"28") and (rdy_i = '1')) then
next_state <= s380;
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"40") and (rdy_i = '1')) then
next_state <= s387;
elsif ((d_i = X"60") and (rdy_i = '1')) then
next_state <= s390;
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
next_state <= s511;
elsif ((d_i = X"38") and (rdy_i = '1')) then
next_state <= s2;
elsif ((d_i = X"F8") and (rdy_i = '1')) then
next_state <= s5;
elsif ((d_i = X"78") and (rdy_i = '1')) then
next_state <= s3;
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") and (rdy_i = '1')) then
next_state <= s177;
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
next_state <= s177;
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
next_state <= s177;
elsif ((d_i = X"AA") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"0A") and (rdy_i = '1')) then
next_state <= s404;
elsif ((d_i = X"4A") and (rdy_i = '1')) then
next_state <= s556;
elsif ((d_i = X"2A") and (rdy_i = '1')) then
next_state <= s557;
elsif ((d_i = X"6A") and (rdy_i = '1')) then
next_state <= s579;
elsif ((d_i = X"A8") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"98") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"BA") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"8A") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"9A") and (rdy_i = '1')) then
next_state <= s4;
elsif (rdy_i = '1') then
next_state <= s1;
else
next_state <= FETCH;
end if;
when s1 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s1;
end if;
when s2 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s2;
end if;
when s5 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s5;
end if;
when s3 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s3;
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s4;
end if;
when s12 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s12;
end if;
when s16 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s16;
end if;
when s17 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s17;
end if;
when s24 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s24;
end if;
when s25 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s25;
end if;
when s271 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
next_state <= s307;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
next_state <= s273;
else
next_state <= s271;
end if;
when s273 =>
if (rdy_i = '1') then
next_state <= s304;
else
next_state <= s273;
end if;
when s304 =>
if (rdy_i = '1') then
next_state <= s307;
else
next_state <= s304;
end if;
when s307 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s307;
end if;
when s177 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
next_state <= s184;
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
next_state <= s185;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
next_state <= s183;
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
next_state <= s182;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
next_state <= s180;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
next_state <= s181;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
next_state <= s186;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
next_state <= s185;
else
next_state <= s177;
end if;
when s180 =>
if (rdy_i = '1') then
next_state <= s191;
else
next_state <= s180;
end if;
when s181 =>
if (rdy_i = '1') then
next_state <= s189;
else
next_state <= s181;
end if;
when s182 =>
if (rdy_i = '1') then
next_state <= s191;
else
next_state <= s182;
end if;
when s183 =>
if (rdy_i = '1') then
next_state <= s187;
else
next_state <= s183;
end if;
when s184 =>
next_state <= FETCH;
when s185 =>
if (rdy_i = '1') then
next_state <= s190;
else
next_state <= s185;
end if;
when s186 =>
if (rdy_i = '1') then
next_state <= s188;
else
next_state <= s186;
end if;
when s187 =>
next_state <= FETCH;
when s188 =>
if (rdy_i = '1') then
next_state <= s192;
else
next_state <= s188;
end if;
when s189 =>
if (rdy_i = '1') then
next_state <= s191;
else
next_state <= s189;
end if;
when s190 =>
next_state <= FETCH;
when s191 =>
next_state <= s193;
when s192 =>
next_state <= s193;
when s193 =>
next_state <= FETCH;
when s377 =>
if (rdy_i = '1') then
next_state <= s381;
else
next_state <= s377;
end if;
when s381 =>
next_state <= FETCH;
when s378 =>
if (rdy_i = '1') then
next_state <= s382;
else
next_state <= s378;
end if;
when s382 =>
next_state <= FETCH;
when s379 =>
if (rdy_i = '1') then
next_state <= s383;
else
next_state <= s379;
end if;
when s383 =>
if (rdy_i = '1') then
next_state <= s384;
else
next_state <= s383;
end if;
when s384 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s384;
end if;
when s380 =>
if (rdy_i = '1') then
next_state <= s385;
else
next_state <= s380;
end if;
when s385 =>
if (rdy_i = '1') then
next_state <= s386;
else
next_state <= s385;
end if;
when s386 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s386;
end if;
when s387 =>
if (rdy_i = '1') then
next_state <= s388;
else
next_state <= s387;
end if;
when s388 =>
if (rdy_i = '1') then
next_state <= s389;
else
next_state <= s388;
end if;
when s389 =>
if (rdy_i = '1') then
next_state <= s391;
else
next_state <= s389;
end if;
when s391 =>
if (rdy_i = '1') then
next_state <= s392;
else
next_state <= s391;
end if;
when s392 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s392;
end if;
when s390 =>
if (rdy_i = '1') then
next_state <= s393;
else
next_state <= s390;
end if;
when s393 =>
if (rdy_i = '1') then
next_state <= s394;
else
next_state <= s393;
end if;
when s394 =>
if (rdy_i = '1') then
next_state <= s395;
else
next_state <= s394;
end if;
when s395 =>
if (rdy_i = '1') then
next_state <= s396;
else
next_state <= s395;
end if;
when s396 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s396;
end if;
when s397 =>
if (rdy_i = '1') then
next_state <= s398;
else
next_state <= s397;
end if;
when s398 =>
if (rdy_i = '1') then
next_state <= s399;
else
next_state <= s398;
end if;
when s399 =>
next_state <= s400;
when s400 =>
next_state <= s401;
when s401 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s401;
end if;
when s526 =>
if (rdy_i = '1') then
next_state <= s527;
else
next_state <= s526;
end if;
when s527 =>
next_state <= s528;
when s528 =>
next_state <= s529;
when s529 =>
next_state <= s531;
when s530 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s530;
end if;
when s531 =>
if (rdy_i = '1') then
next_state <= s530;
else
next_state <= s531;
end if;
when s544 =>
next_state <= s550;
when s545 =>
next_state <= s546;
when s546 =>
next_state <= s547;
when s547 =>
if (rdy_i = '1') then
next_state <= s549;
else
next_state <= s547;
end if;
when s549 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s549;
end if;
when s550 =>
next_state <= s545;
when s404 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s404;
end if;
when s556 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s556;
end if;
when s557 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s557;
end if;
when s579 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s579;
end if;
when s201 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
next_state <= s224;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
next_state <= FETCH;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
next_state <= s217;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
next_state <= s202;
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
next_state <= s210;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
next_state <= s211;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
next_state <= s215;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
next_state <= s218;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
next_state <= s217;
else
next_state <= s201;
end if;
when s202 =>
if (rdy_i = '1') then
next_state <= s224;
else
next_state <= s202;
end if;
when s210 =>
if (rdy_i = '1') then
next_state <= s225;
else
next_state <= s210;
end if;
when s211 =>
if (rdy_i = '1') then
next_state <= s225;
else
next_state <= s211;
end if;
when s215 =>
if (rdy_i = '1') then
next_state <= s223;
else
next_state <= s215;
end if;
when s217 =>
if (rdy_i = '1') then
next_state <= s224;
else
next_state <= s217;
end if;
when s218 =>
if (rdy_i = '1') then
next_state <= s222;
else
next_state <= s218;
end if;
when s222 =>
if (rdy_i = '1') then
next_state <= s202;
else
next_state <= s222;
end if;
when s223 =>
if (rdy_i = '1') then
next_state <= s225;
else
next_state <= s223;
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s224;
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s224;
else
next_state <= s225;
end if;
when s226 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
next_state <= s343;
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
next_state <= s247;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
next_state <= s243;
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
next_state <= s244;
else
next_state <= s226;
end if;
when s243 =>
if (rdy_i = '1') then
next_state <= s343;
else
next_state <= s243;
end if;
when s244 =>
if (rdy_i = '1') then
next_state <= s344;
else
next_state <= s244;
end if;
when s247 =>
if (rdy_i = '1') then
next_state <= s343;
else
next_state <= s247;
end if;
when s344 =>
if (rdy_i = '1') then
next_state <= s343;
else
next_state <= s344;
end if;
when s343 =>
if (rdy_i = '1') then
next_state <= s250;
else
next_state <= s343;
end if;
when s250 =>
if (rdy_i = '1') then
next_state <= s251;
else
next_state <= s250;
end if;
when s251 =>
next_state <= FETCH;
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
next_state <= s361;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
next_state <= s360;
else
next_state <= s351;
end if;
when s361 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s361;
end if;
when s360 =>
if (rdy_i = '1') then
next_state <= s361;
else
next_state <= s360;
end if;
when s403 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
next_state <= s407;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
next_state <= s413;
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
next_state <= s409;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
next_state <= s406;
else
next_state <= s403;
end if;
when s406 =>
if (rdy_i = '1') then
next_state <= s413;
else
next_state <= s406;
end if;
when s407 =>
if (rdy_i = '1') then
next_state <= s412;
else
next_state <= s407;
end if;
when s409 =>
if (rdy_i = '1') then
next_state <= s413;
else
next_state <= s409;
end if;
when s412 =>
if (rdy_i = '1') then
next_state <= s413;
else
next_state <= s412;
end if;
when s413 =>
if (rdy_i = '1') then
next_state <= s416;
else
next_state <= s413;
end if;
when s416 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
next_state <= s418;
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
next_state <= s418;
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
next_state <= s418;
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
next_state <= s418;
else
next_state <= s416;
end if;
when s418 =>
next_state <= FETCH;
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
next_state <= s565;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
next_state <= s560;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
next_state <= s553;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
next_state <= s555;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
next_state <= s555;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
next_state <= s558;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
next_state <= s561;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s510;
end if;
when s553 =>
if (rdy_i = '1') then
next_state <= s565;
else
next_state <= s553;
end if;
when s555 =>
if (rdy_i = '1') then
next_state <= s564;
else
next_state <= s555;
end if;
when s558 =>
if (rdy_i = '1') then
next_state <= s566;
else
next_state <= s558;
end if;
when s560 =>
if (rdy_i = '1') then
next_state <= s565;
else
next_state <= s560;
end if;
when s561 =>
if (rdy_i = '1') then
next_state <= s563;
else
next_state <= s561;
end if;
when s563 =>
if (rdy_i = '1') then
next_state <= s553;
else
next_state <= s563;
end if;
when s564 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s565;
else
next_state <= s564;
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s565;
end if;
when s566 =>
if (rdy_i = '1') then
next_state <= s564;
else
next_state <= s566;
end if;
when s266 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s301;
else
next_state <= s266;
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s302;
else
next_state <= s301;
end if;
when s302 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s302;
end if;
when RES =>
next_state <= s544;
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
next_state <= s574;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
next_state <= s569;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
next_state <= s559;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
next_state <= s562;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
next_state <= s567;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
next_state <= s568;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
next_state <= s570;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s511;
end if;
when s559 =>
if (rdy_i = '1') then
next_state <= s574;
else
next_state <= s559;
end if;
when s562 =>
if (rdy_i = '1') then
next_state <= s573;
else
next_state <= s562;
end if;
when s567 =>
if (rdy_i = '1') then
next_state <= s573;
else
next_state <= s567;
end if;
when s568 =>
if (rdy_i = '1') then
next_state <= s571;
else
next_state <= s568;
end if;
when s569 =>
if (rdy_i = '1') then
next_state <= s574;
else
next_state <= s569;
end if;
when s570 =>
if (rdy_i = '1') then
next_state <= s572;
else
next_state <= s570;
end if;
when s571 =>
if (rdy_i = '1') then
next_state <= s573;
else
next_state <= s571;
end if;
when s572 =>
if (rdy_i = '1') then
next_state <= s559;
else
next_state <= s572;
end if;
when s573 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s574;
else
next_state <= s573;
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s574;
end if;
when s548 =>
if (rdy_i = '1') then
next_state <= s551;
else
next_state <= s548;
end if;
when s551 =>
next_state <= s552;
when s552 =>
next_state <= s576;
when s575 =>
if (rdy_i = '1') then
next_state <= s577;
else
next_state <= s575;
end if;
when s576 =>
next_state <= s575;
when s577 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s577;
end if;
when s532 =>
if (rdy_i = '1') then
next_state <= s533;
else
next_state <= s532;
end if;
when s533 =>
next_state <= s534;
when s534 =>
next_state <= s536;
when s535 =>
if (rdy_i = '1') then
next_state <= s537;
else
next_state <= s535;
end if;
when s536 =>
next_state <= s535;
when s537 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s537;
end if;
when others =>
next_state <= RES;
end case;
end process nextstate_proc;
-----------------------------------------------------------------
output_proc : process (
adr_nxt_pc_i,
adr_pc_i,
adr_sp_i,
current_state,
d_alu_i,
d_i,
d_regs_out_i,
irq_n_i,
nmi_i,
q_a_i,
q_x_i,
q_y_i,
rdy_i,
reg_F,
reg_sel_pc_as,
reg_sel_pc_in,
reg_sel_pc_val,
reg_sel_rb_in,
reg_sel_rb_out,
reg_sel_reg,
reg_sel_sp_as,
reg_sel_sp_in,
sig_PC,
zw_ALU,
zw_ALU1,
zw_ALU2,
zw_ALU3,
zw_ALU4,
zw_ALU5,
zw_ALU6,
zw_REG_OP,
zw_b1,
zw_b2,
zw_b3,
zw_b4,
zw_w1
)
-----------------------------------------------------------------
begin
-- Default Assignment
a_o <= sig_PC;
adr_o <= X"0000";
ch_a_o <= X"00";
ch_b_o <= X"00";
d_regs_in_o <= X"00";
fetch_o <= '0';
ld_o <= "00";
ld_pc_o <= '0';
ld_sp_o <= '0';
load_regs_o <= '0';
offset_o <= X"0000";
sel_pc_as_o <= reg_sel_pc_as;
sel_pc_in_o <= reg_sel_pc_in;
sel_pc_val_o <= reg_sel_pc_val;
sel_rb_in_o <= reg_sel_rb_in;
sel_rb_out_o <= reg_sel_rb_out;
sel_reg_o <= reg_sel_reg;
sel_sp_as_o <= reg_sel_sp_as;
sel_sp_in_o <= reg_sel_sp_in;
-- Default Assignment To Internals
sig_D_OUT <= X"00";
sig_RD <= '1';
sig_RWn <= '1';
sig_SYNC <= '0';
sig_WR <= '0';
zw_ALU <= '0' & X"00";
zw_ALU1 <= '0' & X"00";
zw_ALU2 <= '0' & X"00";
zw_ALU3 <= '0' & X"00";
zw_ALU4 <= '0' & X"00";
zw_ALU5 <= '0' & X"00";
zw_ALU6 <= '0' & X"00";
-- Combined Actions
case current_state is
when FETCH =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= NOT (rdy_i);
if ((nmi_i = '1') and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"00") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"18") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"D8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"58") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"B8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"CA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"88") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"20") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"EA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"48") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"08") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"68") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"28") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"40") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"60") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"38") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"F8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"78") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"AA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"0A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"4A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"2A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"6A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"98") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"BA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"8A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"9A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s1 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s2 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s5 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s3 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
adr_o <= X"01" & d_regs_out_i;
ld_o <= "11";
ld_sp_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
d_regs_in_o <= adr_sp_i (7 downto 0);
ch_a_o <= adr_sp_i (7 downto 0);
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1') then
ch_a_o <= d_regs_out_i;
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s12 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s16 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s17 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s24 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s25 =>
if (rdy_i = '1') then
d_regs_in_o <= d_alu_i;
ch_a_o <= d_regs_out_i;
ch_b_o <= zw_b4;
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s273 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s307 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s177 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s180 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s181 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s182 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s183 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s184 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s185 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s187 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s188 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s189 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s190 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s191 =>
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
when s192 =>
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
when s193 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s377 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= q_a_i;
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s381 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s378 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s382 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s379 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s384 =>
if (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s380 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s386 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s387 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s388 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s389 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s392 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s390 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s393 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s395 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s396 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s397 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
end if;
when s398 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s399 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s401 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s526 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s527 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s528 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F OR X"10";
when s530 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s544 =>
ld_o <= "11";
ld_sp_o <= '1';
when s545 =>
adr_o <= X"FFFB";
ld_o <= "11";
ld_pc_o <= '1';
when s546 =>
ld_o <= "11";
ld_pc_o <= '1';
when s549 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_w1 (7 downto 0);
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s550 =>
ld_o <= "11";
ld_sp_o <= '1';
when s404 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & '0';
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & '0';
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s556 =>
if (rdy_i = '1') then
ch_a_o <= '0' & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= '0' & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s557 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s579 =>
if (rdy_i = '1') then
ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s201 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
ld_o <= "11";
ld_pc_o <= '1';
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s202 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s210 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s211 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s215 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s217 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s222 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s223 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s226 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end if;
when s243 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s244 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s247 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s343 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= zw_b4;
end if;
when s250 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= zw_b1;
end if;
when s251 =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s361 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s360 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s403 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s406 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s407 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s409 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s416 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
sig_D_OUT <= d_i(6 downto 0) & '0';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
sig_D_OUT <= '0' & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
end if;
when s418 =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5));
zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0';
zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0';
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s553 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s555 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s558 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s560 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s563 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s564 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5));
zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0';
zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0';
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5));
zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0';
zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0';
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s566 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s266 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1') then
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s302 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when RES =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_pc_o <= '1';
ld_sp_o <= '1';
sig_RWn <= '1';
sig_RD <= '1';
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
unsigned ((zw_ALU6(8 downto 5)));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
unsigned ((zw_ALU5(8 downto 5)));
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s559 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s562 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s567 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s568 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s569 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s571 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s572 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s573 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
unsigned ((zw_ALU6(8 downto 5)));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
unsigned ((zw_ALU5(8 downto 5)));
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
unsigned ((zw_ALU6(8 downto 5)));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
unsigned ((zw_ALU5(8 downto 5)));
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s548 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s551 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s552 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
when s577 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s532 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s533 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s534 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
when s537 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when others =>
null;
end case;
end process output_proc;
-- Concurrent Statements
-- Clocked output assignments
d_o <= d_o_cld;
rd_o <= rd_o_cld;
sync_o <= sync_o_cld;
wr_n_o <= wr_n_o_cld;
wr_o <= wr_o_cld;
end fsm;
| gpl-2.0 |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/FOODFIGHT_ROM/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd | 41 | 20439 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13392)
`protect data_block
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`protect end_protected
| gpl-2.0 |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/CHOPLIFTER/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd | 41 | 20439 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13392)
`protect data_block
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`protect end_protected
| gpl-2.0 |
545/Atari7800 | tia/sound_interface/adau1761_configuraiton_data.vhd | 3 | 7458 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Module Name: adau1761_configuraiton_data - Behavioral
-- Description: A script for the I3C2, which sends out I2c transactions to configure
-- the ADAU1761 codec.
--
-- See i3c2program for original source for script
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adau1761_configuraiton_data is
Port ( clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (9 downto 0);
data : out STD_LOGIC_VECTOR (8 downto 0));
end adau1761_configuraiton_data;
architecture Behavioral of adau1761_configuraiton_data is
begin
process(clk)
begin
if rising_edge(clk) then
case address is
when "0000000000" => data <= "011101111";
when "0000000001" => data <= "101110110";
when "0000000010" => data <= "101000000";
when "0000000011" => data <= "100000000";
when "0000000100" => data <= "100001110";
when "0000000101" => data <= "011111111";
when "0000000110" => data <= "101110110";
when "0000000111" => data <= "101000000";
when "0000001000" => data <= "100000010";
when "0000001001" => data <= "100000000";
when "0000001010" => data <= "101111101";
when "0000001011" => data <= "100000000";
when "0000001100" => data <= "100001100";
when "0000001101" => data <= "100100011";
when "0000001110" => data <= "100000001";
when "0000001111" => data <= "011111111";
when "0000010000" => data <= "011101111";
when "0000010001" => data <= "101110110";
when "0000010010" => data <= "101000000";
when "0000010011" => data <= "100000000";
when "0000010100" => data <= "100001111";
when "0000010101" => data <= "011111111";
when "0000010110" => data <= "011101111";
when "0000010111" => data <= "101110110";
when "0000011000" => data <= "101000000";
when "0000011001" => data <= "100010101";
when "0000011010" => data <= "100000001";
when "0000011011" => data <= "011111111";
when "0000011100" => data <= "101110110";
when "0000011101" => data <= "101000000";
when "0000011110" => data <= "100001010";
when "0000011111" => data <= "100000001";
when "0000100000" => data <= "011111111";
when "0000100001" => data <= "101110110";
when "0000100010" => data <= "101000000";
when "0000100011" => data <= "100001011";
when "0000100100" => data <= "100000101";
when "0000100101" => data <= "011111111";
when "0000100110" => data <= "101110110";
when "0000100111" => data <= "101000000";
when "0000101000" => data <= "100001100";
when "0000101001" => data <= "100000001";
when "0000101010" => data <= "011111111";
when "0000101011" => data <= "101110110";
when "0000101100" => data <= "101000000";
when "0000101101" => data <= "100001101";
when "0000101110" => data <= "100000101";
when "0000101111" => data <= "011111111";
when "0000110000" => data <= "101110110";
when "0000110001" => data <= "101000000";
when "0000110010" => data <= "100011100";
when "0000110011" => data <= "100100001";
when "0000110100" => data <= "011111111";
when "0000110101" => data <= "101110110";
when "0000110110" => data <= "101000000";
when "0000110111" => data <= "100011110";
when "0000111000" => data <= "101000001";
when "0000111001" => data <= "011111111";
when "0000111010" => data <= "101110110";
when "0000111011" => data <= "101000000";
when "0000111100" => data <= "100100011";
when "0000111101" => data <= "111100111";
when "0000111110" => data <= "011111111";
when "0000111111" => data <= "101110110";
when "0001000000" => data <= "101000000";
when "0001000001" => data <= "100100100";
when "0001000010" => data <= "111100111";
when "0001000011" => data <= "011111111";
when "0001000100" => data <= "101110110";
when "0001000101" => data <= "101000000";
when "0001000110" => data <= "100100101";
when "0001000111" => data <= "111100111";
when "0001001000" => data <= "011111111";
when "0001001001" => data <= "101110110";
when "0001001010" => data <= "101000000";
when "0001001011" => data <= "100100110";
when "0001001100" => data <= "111100111";
when "0001001101" => data <= "011111111";
when "0001001110" => data <= "101110110";
when "0001001111" => data <= "101000000";
when "0001010000" => data <= "100011001";
when "0001010001" => data <= "100000011";
when "0001010010" => data <= "011111111";
when "0001010011" => data <= "101110110";
when "0001010100" => data <= "101000000";
when "0001010101" => data <= "100101001";
when "0001010110" => data <= "100000011";
when "0001010111" => data <= "011111111";
when "0001011000" => data <= "101110110";
when "0001011001" => data <= "101000000";
when "0001011010" => data <= "100101010";
when "0001011011" => data <= "100000011";
when "0001011100" => data <= "011111111";
when "0001011101" => data <= "101110110";
when "0001011110" => data <= "101000000";
when "0001011111" => data <= "111110010";
when "0001100000" => data <= "100000001";
when "0001100001" => data <= "011111111";
when "0001100010" => data <= "101110110";
when "0001100011" => data <= "101000000";
when "0001100100" => data <= "111110011";
when "0001100101" => data <= "100000001";
when "0001100110" => data <= "011111111";
when "0001100111" => data <= "101110110";
when "0001101000" => data <= "101000000";
when "0001101001" => data <= "111111001";
when "0001101010" => data <= "101111111";
when "0001101011" => data <= "011111111";
when "0001101100" => data <= "101110110";
when "0001101101" => data <= "101000000";
when "0001101110" => data <= "111111010";
when "0001101111" => data <= "100000011";
when "0001110000" => data <= "011111111";
when "0001110001" => data <= "011111110";
when "0001110010" => data <= "011111110";
when "0001110011" => data <= "011111110";
when "0001110100" => data <= "011111110";
when "0001110101" => data <= "011111110";
when "0001110110" => data <= "011111110";
when "0001110111" => data <= "011111110";
when "0001111000" => data <= "011101111";
when "0001111001" => data <= "000001111";
when others => data <= (others =>'0');
end case;
end if;
end process;
end Behavioral;
| gpl-2.0 |
545/Atari7800 | core/cpu6502_true_cycle/branches/avendor/rtl/vhdl/core.vhd | 2 | 14532 | -- VHDL Entity R6502_TC.Core.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:43:05 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity Core is
port(
clk_clk_i : in std_logic;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic;
nmi_n_i : in std_logic;
rdy_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
);
-- Declarations
end Core ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- [email protected]
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version
-- 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
-- <<-- more -->>
-- Title: Core
-- Path: R6502_TC/Core/struct
-- Edited: by eda on 04 Jan 2009
--
-- VHDL Architecture R6502_TC.Core.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:43:06 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
library R6502_TC;
architecture struct of Core is
-- Architecture declarations
-- Internal signal declarations
signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
signal adr_o_i : std_logic_vector(15 downto 0);
signal adr_pc_o_i : std_logic_vector(15 downto 0);
signal adr_sp_o_i : std_logic_vector(15 downto 0);
signal ch_a_o_i : std_logic_vector(7 downto 0);
signal ch_b_o_i : std_logic_vector(7 downto 0);
signal d_alu_n_o_i : std_logic;
signal d_alu_o_i : std_logic_vector(7 downto 0);
signal d_alu_or_o_i : std_logic;
signal d_regs_in_o_i : std_logic_vector(7 downto 0);
signal d_regs_out_o_i : std_logic_vector(7 downto 0);
signal fetch_o_i : std_logic;
signal ld_o_i : std_logic_vector(1 downto 0);
signal ld_pc_o_i : std_logic;
signal ld_sp_o_i : std_logic;
signal load_regs_o_i : std_logic;
signal nmi_o_i : std_logic;
signal offset_o_i : std_logic_vector(15 downto 0);
signal q_a_o_i : std_logic_vector(7 downto 0);
signal q_x_o_i : std_logic_vector(7 downto 0);
signal q_y_o_i : std_logic_vector(7 downto 0);
signal reg_0flag_o_i : std_logic;
signal reg_1flag_o_i : std_logic;
signal reg_7flag_o_i : std_logic;
signal sel_pc_as_o_i : std_logic;
signal sel_pc_in_o_i : std_logic;
signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
signal sel_rb_in_o_i : std_logic_vector(1 downto 0);
signal sel_rb_out_o_i : std_logic_vector(1 downto 0);
signal sel_reg_o_i : std_logic_vector(1 downto 0);
signal sel_sp_as_o_i : std_logic;
signal sel_sp_in_o_i : std_logic;
-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'add'
signal mw_U_11temp_din0 : std_logic_vector(8 downto 0);
signal mw_U_11temp_din1 : std_logic_vector(8 downto 0);
signal mw_U_11sum : unsigned(8 downto 0);
-- Component Declarations
component FSM_Execution_Unit
port (
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic ;
nmi_i : in std_logic ;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic ;
reg_0flag_i : in std_logic ;
reg_1flag_i : in std_logic ;
reg_7flag_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
fetch_o : out std_logic ;
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic ;
ld_sp_o : out std_logic ;
load_regs_o : out std_logic ;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic ;
sel_pc_as_o : out std_logic ;
sel_pc_in_o : out std_logic ;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic ;
sel_sp_in_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic
);
end component;
component FSM_NMI
port (
clk_clk_i : in std_logic ;
fetch_i : in std_logic ;
nmi_n_i : in std_logic ;
rst_rst_n_i : in std_logic ;
nmi_o : out std_logic
);
end component;
component RegBank_AXY
port (
clk_clk_i : in std_logic ;
d_regs_in_i : in std_logic_vector (7 downto 0);
load_regs_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_rb_in_i : in std_logic_vector (1 downto 0);
sel_rb_out_i : in std_logic_vector (1 downto 0);
sel_reg_i : in std_logic_vector (1 downto 0);
d_regs_out_o : out std_logic_vector (7 downto 0);
q_a_o : out std_logic_vector (7 downto 0);
q_x_o : out std_logic_vector (7 downto 0);
q_y_o : out std_logic_vector (7 downto 0)
);
end component;
component Reg_PC
port (
adr_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
ld_i : in std_logic_vector (1 downto 0);
ld_pc_i : in std_logic ;
offset_i : in std_logic_vector (15 downto 0);
rst_rst_n_i : in std_logic ;
sel_pc_as_i : in std_logic ;
sel_pc_in_i : in std_logic ;
sel_pc_val_i : in std_logic_vector (1 downto 0);
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
adr_pc_o : out std_logic_vector (15 downto 0)
);
end component;
component Reg_SP
port (
adr_low_i : in std_logic_vector (7 downto 0);
clk_clk_i : in std_logic ;
ld_low_i : in std_logic ;
ld_sp_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_sp_as_i : in std_logic ;
sel_sp_in_i : in std_logic ;
adr_sp_o : out std_logic_vector (15 downto 0)
);
end component;
-- Optional embedded configurations
-- pragma synthesis_off
for all : FSM_Execution_Unit use entity R6502_TC.FSM_Execution_Unit;
for all : FSM_NMI use entity R6502_TC.FSM_NMI;
for all : RegBank_AXY use entity R6502_TC.RegBank_AXY;
for all : Reg_PC use entity R6502_TC.Reg_PC;
for all : Reg_SP use entity R6502_TC.Reg_SP;
-- pragma synthesis_on
begin
-- ModuleWare code(v1.9) for instance 'U_11' of 'add'
mw_U_11temp_din0 <= '0' & ch_a_o_i;
mw_U_11temp_din1 <= '0' & ch_b_o_i;
u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1)
variable temp_carry : std_logic;
begin
temp_carry := '0';
mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry;
end process u_11combo_proc;
d_alu_o_i <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8);
reg_0flag_o_i <= mw_U_11sum(8) ;
-- ModuleWare code(v1.9) for instance 'U_8' of 'inv'
reg_1flag_o_i <= not(d_alu_or_o_i);
-- ModuleWare code(v1.9) for instance 'U_9' of 'inv'
reg_7flag_o_i <= not(d_alu_n_o_i);
-- ModuleWare code(v1.9) for instance 'U_10' of 'inv'
d_alu_n_o_i <= not(d_alu_o_i(7));
-- ModuleWare code(v1.9) for instance 'U_7' of 'por'
d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7);
-- Instance port mappings.
U_4 : FSM_Execution_Unit
port map (
adr_nxt_pc_i => adr_nxt_pc_o_i,
adr_pc_i => adr_pc_o_i,
adr_sp_i => adr_sp_o_i,
clk_clk_i => clk_clk_i,
d_alu_i => d_alu_o_i,
d_i => d_i,
d_regs_out_i => d_regs_out_o_i,
irq_n_i => irq_n_i,
nmi_i => nmi_o_i,
q_a_i => q_a_o_i,
q_x_i => q_x_o_i,
q_y_i => q_y_o_i,
rdy_i => rdy_i,
reg_0flag_i => reg_0flag_o_i,
reg_1flag_i => reg_1flag_o_i,
reg_7flag_i => reg_7flag_o_i,
rst_rst_n_i => rst_rst_n_i,
so_n_i => so_n_i,
a_o => a_o,
adr_o => adr_o_i,
ch_a_o => ch_a_o_i,
ch_b_o => ch_b_o_i,
d_o => d_o,
d_regs_in_o => d_regs_in_o_i,
fetch_o => fetch_o_i,
ld_o => ld_o_i,
ld_pc_o => ld_pc_o_i,
ld_sp_o => ld_sp_o_i,
load_regs_o => load_regs_o_i,
offset_o => offset_o_i,
rd_o => rd_o,
sel_pc_as_o => sel_pc_as_o_i,
sel_pc_in_o => sel_pc_in_o_i,
sel_pc_val_o => sel_pc_val_o_i,
sel_rb_in_o => sel_rb_in_o_i,
sel_rb_out_o => sel_rb_out_o_i,
sel_reg_o => sel_reg_o_i,
sel_sp_as_o => sel_sp_as_o_i,
sel_sp_in_o => sel_sp_in_o_i,
sync_o => sync_o,
wr_n_o => wr_n_o,
wr_o => wr_o
);
U_6 : FSM_NMI
port map (
clk_clk_i => clk_clk_i,
fetch_i => fetch_o_i,
nmi_n_i => nmi_n_i,
rst_rst_n_i => rst_rst_n_i,
nmi_o => nmi_o_i
);
U_2 : RegBank_AXY
port map (
clk_clk_i => clk_clk_i,
d_regs_in_i => d_regs_in_o_i,
load_regs_i => load_regs_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_rb_in_i => sel_rb_in_o_i,
sel_rb_out_i => sel_rb_out_o_i,
sel_reg_i => sel_reg_o_i,
d_regs_out_o => d_regs_out_o_i,
q_a_o => q_a_o_i,
q_x_o => q_x_o_i,
q_y_o => q_y_o_i
);
U_0 : Reg_PC
port map (
adr_i => adr_o_i,
clk_clk_i => clk_clk_i,
ld_i => ld_o_i,
ld_pc_i => ld_pc_o_i,
offset_i => offset_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_pc_as_i => sel_pc_as_o_i,
sel_pc_in_i => sel_pc_in_o_i,
sel_pc_val_i => sel_pc_val_o_i,
adr_nxt_pc_o => adr_nxt_pc_o_i,
adr_pc_o => adr_pc_o_i
);
U_1 : Reg_SP
port map (
adr_low_i => adr_o_i(7 DOWNTO 0),
clk_clk_i => clk_clk_i,
ld_low_i => ld_o_i(0),
ld_sp_i => ld_sp_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_sp_as_i => sel_sp_as_o_i,
sel_sp_in_i => sel_sp_in_o_i,
adr_sp_o => adr_sp_o_i
);
end struct;
| gpl-2.0 |
545/Atari7800 | core/cpu6502_true_cycle/tags/arelease/rtl/vhdl/core.vhd | 2 | 14532 | -- VHDL Entity R6502_TC.Core.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:43:05 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity Core is
port(
clk_clk_i : in std_logic;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic;
nmi_n_i : in std_logic;
rdy_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
);
-- Declarations
end Core ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- [email protected]
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version
-- 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
-- <<-- more -->>
-- Title: Core
-- Path: R6502_TC/Core/struct
-- Edited: by eda on 04 Jan 2009
--
-- VHDL Architecture R6502_TC.Core.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:43:06 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
library R6502_TC;
architecture struct of Core is
-- Architecture declarations
-- Internal signal declarations
signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
signal adr_o_i : std_logic_vector(15 downto 0);
signal adr_pc_o_i : std_logic_vector(15 downto 0);
signal adr_sp_o_i : std_logic_vector(15 downto 0);
signal ch_a_o_i : std_logic_vector(7 downto 0);
signal ch_b_o_i : std_logic_vector(7 downto 0);
signal d_alu_n_o_i : std_logic;
signal d_alu_o_i : std_logic_vector(7 downto 0);
signal d_alu_or_o_i : std_logic;
signal d_regs_in_o_i : std_logic_vector(7 downto 0);
signal d_regs_out_o_i : std_logic_vector(7 downto 0);
signal fetch_o_i : std_logic;
signal ld_o_i : std_logic_vector(1 downto 0);
signal ld_pc_o_i : std_logic;
signal ld_sp_o_i : std_logic;
signal load_regs_o_i : std_logic;
signal nmi_o_i : std_logic;
signal offset_o_i : std_logic_vector(15 downto 0);
signal q_a_o_i : std_logic_vector(7 downto 0);
signal q_x_o_i : std_logic_vector(7 downto 0);
signal q_y_o_i : std_logic_vector(7 downto 0);
signal reg_0flag_o_i : std_logic;
signal reg_1flag_o_i : std_logic;
signal reg_7flag_o_i : std_logic;
signal sel_pc_as_o_i : std_logic;
signal sel_pc_in_o_i : std_logic;
signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
signal sel_rb_in_o_i : std_logic_vector(1 downto 0);
signal sel_rb_out_o_i : std_logic_vector(1 downto 0);
signal sel_reg_o_i : std_logic_vector(1 downto 0);
signal sel_sp_as_o_i : std_logic;
signal sel_sp_in_o_i : std_logic;
-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'add'
signal mw_U_11temp_din0 : std_logic_vector(8 downto 0);
signal mw_U_11temp_din1 : std_logic_vector(8 downto 0);
signal mw_U_11sum : unsigned(8 downto 0);
-- Component Declarations
component FSM_Execution_Unit
port (
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic ;
nmi_i : in std_logic ;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic ;
reg_0flag_i : in std_logic ;
reg_1flag_i : in std_logic ;
reg_7flag_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
fetch_o : out std_logic ;
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic ;
ld_sp_o : out std_logic ;
load_regs_o : out std_logic ;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic ;
sel_pc_as_o : out std_logic ;
sel_pc_in_o : out std_logic ;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic ;
sel_sp_in_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic
);
end component;
component FSM_NMI
port (
clk_clk_i : in std_logic ;
fetch_i : in std_logic ;
nmi_n_i : in std_logic ;
rst_rst_n_i : in std_logic ;
nmi_o : out std_logic
);
end component;
component RegBank_AXY
port (
clk_clk_i : in std_logic ;
d_regs_in_i : in std_logic_vector (7 downto 0);
load_regs_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_rb_in_i : in std_logic_vector (1 downto 0);
sel_rb_out_i : in std_logic_vector (1 downto 0);
sel_reg_i : in std_logic_vector (1 downto 0);
d_regs_out_o : out std_logic_vector (7 downto 0);
q_a_o : out std_logic_vector (7 downto 0);
q_x_o : out std_logic_vector (7 downto 0);
q_y_o : out std_logic_vector (7 downto 0)
);
end component;
component Reg_PC
port (
adr_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
ld_i : in std_logic_vector (1 downto 0);
ld_pc_i : in std_logic ;
offset_i : in std_logic_vector (15 downto 0);
rst_rst_n_i : in std_logic ;
sel_pc_as_i : in std_logic ;
sel_pc_in_i : in std_logic ;
sel_pc_val_i : in std_logic_vector (1 downto 0);
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
adr_pc_o : out std_logic_vector (15 downto 0)
);
end component;
component Reg_SP
port (
adr_low_i : in std_logic_vector (7 downto 0);
clk_clk_i : in std_logic ;
ld_low_i : in std_logic ;
ld_sp_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_sp_as_i : in std_logic ;
sel_sp_in_i : in std_logic ;
adr_sp_o : out std_logic_vector (15 downto 0)
);
end component;
-- Optional embedded configurations
-- pragma synthesis_off
for all : FSM_Execution_Unit use entity R6502_TC.FSM_Execution_Unit;
for all : FSM_NMI use entity R6502_TC.FSM_NMI;
for all : RegBank_AXY use entity R6502_TC.RegBank_AXY;
for all : Reg_PC use entity R6502_TC.Reg_PC;
for all : Reg_SP use entity R6502_TC.Reg_SP;
-- pragma synthesis_on
begin
-- ModuleWare code(v1.9) for instance 'U_11' of 'add'
mw_U_11temp_din0 <= '0' & ch_a_o_i;
mw_U_11temp_din1 <= '0' & ch_b_o_i;
u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1)
variable temp_carry : std_logic;
begin
temp_carry := '0';
mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry;
end process u_11combo_proc;
d_alu_o_i <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8);
reg_0flag_o_i <= mw_U_11sum(8) ;
-- ModuleWare code(v1.9) for instance 'U_8' of 'inv'
reg_1flag_o_i <= not(d_alu_or_o_i);
-- ModuleWare code(v1.9) for instance 'U_9' of 'inv'
reg_7flag_o_i <= not(d_alu_n_o_i);
-- ModuleWare code(v1.9) for instance 'U_10' of 'inv'
d_alu_n_o_i <= not(d_alu_o_i(7));
-- ModuleWare code(v1.9) for instance 'U_7' of 'por'
d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7);
-- Instance port mappings.
U_4 : FSM_Execution_Unit
port map (
adr_nxt_pc_i => adr_nxt_pc_o_i,
adr_pc_i => adr_pc_o_i,
adr_sp_i => adr_sp_o_i,
clk_clk_i => clk_clk_i,
d_alu_i => d_alu_o_i,
d_i => d_i,
d_regs_out_i => d_regs_out_o_i,
irq_n_i => irq_n_i,
nmi_i => nmi_o_i,
q_a_i => q_a_o_i,
q_x_i => q_x_o_i,
q_y_i => q_y_o_i,
rdy_i => rdy_i,
reg_0flag_i => reg_0flag_o_i,
reg_1flag_i => reg_1flag_o_i,
reg_7flag_i => reg_7flag_o_i,
rst_rst_n_i => rst_rst_n_i,
so_n_i => so_n_i,
a_o => a_o,
adr_o => adr_o_i,
ch_a_o => ch_a_o_i,
ch_b_o => ch_b_o_i,
d_o => d_o,
d_regs_in_o => d_regs_in_o_i,
fetch_o => fetch_o_i,
ld_o => ld_o_i,
ld_pc_o => ld_pc_o_i,
ld_sp_o => ld_sp_o_i,
load_regs_o => load_regs_o_i,
offset_o => offset_o_i,
rd_o => rd_o,
sel_pc_as_o => sel_pc_as_o_i,
sel_pc_in_o => sel_pc_in_o_i,
sel_pc_val_o => sel_pc_val_o_i,
sel_rb_in_o => sel_rb_in_o_i,
sel_rb_out_o => sel_rb_out_o_i,
sel_reg_o => sel_reg_o_i,
sel_sp_as_o => sel_sp_as_o_i,
sel_sp_in_o => sel_sp_in_o_i,
sync_o => sync_o,
wr_n_o => wr_n_o,
wr_o => wr_o
);
U_6 : FSM_NMI
port map (
clk_clk_i => clk_clk_i,
fetch_i => fetch_o_i,
nmi_n_i => nmi_n_i,
rst_rst_n_i => rst_rst_n_i,
nmi_o => nmi_o_i
);
U_2 : RegBank_AXY
port map (
clk_clk_i => clk_clk_i,
d_regs_in_i => d_regs_in_o_i,
load_regs_i => load_regs_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_rb_in_i => sel_rb_in_o_i,
sel_rb_out_i => sel_rb_out_o_i,
sel_reg_i => sel_reg_o_i,
d_regs_out_o => d_regs_out_o_i,
q_a_o => q_a_o_i,
q_x_o => q_x_o_i,
q_y_o => q_y_o_i
);
U_0 : Reg_PC
port map (
adr_i => adr_o_i,
clk_clk_i => clk_clk_i,
ld_i => ld_o_i,
ld_pc_i => ld_pc_o_i,
offset_i => offset_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_pc_as_i => sel_pc_as_o_i,
sel_pc_in_i => sel_pc_in_o_i,
sel_pc_val_i => sel_pc_val_o_i,
adr_nxt_pc_o => adr_nxt_pc_o_i,
adr_pc_o => adr_pc_o_i
);
U_1 : Reg_SP
port map (
adr_low_i => adr_o_i(7 DOWNTO 0),
clk_clk_i => clk_clk_i,
ld_low_i => ld_o_i(0),
ld_sp_i => ld_sp_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_sp_as_i => sel_sp_as_o_i,
sel_sp_in_i => sel_sp_in_o_i,
adr_sp_o => adr_sp_o_i
);
end struct;
| gpl-2.0 |
545/Atari7800 | core/cpu6502_true_cycle/trunk/rtl/vhdl/reg_pc.vhd | 1 | 9349 | -- VHDL Entity R6502_TC.Reg_PC.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW1)
-- at - 18:39:48 08.02.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Reg_PC IS
PORT(
adr_i : IN std_logic_vector (15 DOWNTO 0);
clk_clk_i : IN std_logic;
ld_i : IN std_logic_vector (1 DOWNTO 0);
ld_pc_i : IN std_logic;
offset_i : IN std_logic_vector (15 DOWNTO 0);
rst_rst_n_i : IN std_logic;
sel_pc_in_i : IN std_logic;
sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0);
adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0);
adr_pc_o : OUT std_logic_vector (15 DOWNTO 0)
);
-- Declarations
END Reg_PC ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- [email protected]
-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: struct.bd,v $
-- <<-- more -->>
-- Title: Program Counter Logic
-- Path: R6502_TC/Reg_PC/struct
-- Edited: by eda on 08 Feb 2010
--
-- VHDL Architecture R6502_TC.Reg_PC.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW1)
-- at - 18:39:49 08.02.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE struct OF Reg_PC IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL adr_pc_high_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL adr_pc_low_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0);
SIGNAL ci_o_i : std_logic;
SIGNAL cout_pc_o_i : std_logic;
SIGNAL load3_o_i : std_logic;
SIGNAL load_o_i : std_logic;
SIGNAL offset_high_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL offset_low_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL val_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL val_one : std_logic_vector(7 DOWNTO 0);
SIGNAL val_zero : std_logic_vector(7 DOWNTO 0);
-- Implicit buffer signal declarations
SIGNAL adr_nxt_pc_o_internal : std_logic_vector (15 DOWNTO 0);
SIGNAL adr_pc_o_internal : std_logic_vector (15 DOWNTO 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
SIGNAL mw_U_4reg_cval : std_logic_vector(7 DOWNTO 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_3' of 'split'
SIGNAL mw_U_3temp_din : std_logic_vector(15 DOWNTO 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'split'
SIGNAL mw_U_5temp_din : std_logic_vector(15 DOWNTO 0);
BEGIN
-- ModuleWare code(v1.9) for instance 'U_2' of 'add'
u_2combo_proc: PROCESS (adr_pc_low_o_i, val_o_i)
VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
VARIABLE temp_carry : std_logic;
BEGIN
temp_din0 := '0' & adr_pc_low_o_i;
temp_din1 := '0' & val_o_i;
temp_carry := '0';
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
cout_pc_o_i <= temp_sum(8) ;
END PROCESS u_2combo_proc;
-- ModuleWare code(v1.9) for instance 'U_11' of 'add'
u_11combo_proc: PROCESS (adr_pc_high_o_i, offset_high_o_i, ci_o_i)
VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
VARIABLE temp_sum : unsigned(8 DOWNTO 0);
VARIABLE temp_carry : std_logic;
BEGIN
temp_din0 := '0' & adr_pc_high_o_i;
temp_din1 := '0' & offset_high_o_i;
temp_carry := ci_o_i;
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
END PROCESS u_11combo_proc;
-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
BEGIN
IF (rst_rst_n_i = '0') THEN
mw_U_0reg_cval <= "00000000";
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
IF (load_o_i = '1') THEN
mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);
END IF;
END IF;
END PROCESS u_0seq_proc;
-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
u_4seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
BEGIN
IF (rst_rst_n_i = '0') THEN
mw_U_4reg_cval <= "00000000";
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
IF (load3_o_i = '1') THEN
mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);
END IF;
END IF;
END PROCESS u_4seq_proc;
-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
load_o_i <= ld_pc_i AND ld_i(0);
-- ModuleWare code(v1.9) for instance 'U_7' of 'and'
load3_o_i <= ld_pc_i AND ld_i(1);
-- ModuleWare code(v1.9) for instance 'U_10' of 'and'
ci_o_i <= cout_pc_o_i AND ld_pc_i;
-- ModuleWare code(v1.9) for instance 'U_1' of 'constval'
val_zero <= "00000000";
-- ModuleWare code(v1.9) for instance 'U_9' of 'constval'
val_one <= "00000001";
-- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
u_8combo_proc: PROCESS(adr_pc_o_internal, adr_i, sel_pc_in_i)
BEGIN
CASE sel_pc_in_i IS
WHEN '0' => adr_pc_o_i <= adr_pc_o_internal;
WHEN '1' => adr_pc_o_i <= adr_i;
WHEN OTHERS => adr_pc_o_i <= (OTHERS => 'X');
END CASE;
END PROCESS u_8combo_proc;
-- ModuleWare code(v1.9) for instance 'U_13' of 'mux'
u_13combo_proc: PROCESS(val_one, val_zero, offset_low_o_i,
sel_pc_val_i)
BEGIN
CASE sel_pc_val_i IS
WHEN "00" => val_o_i <= val_one;
WHEN "01" => val_o_i <= val_zero;
WHEN "10" => val_o_i <= offset_low_o_i;
WHEN "11" => val_o_i <= val_zero;
WHEN OTHERS => val_o_i <= (OTHERS => 'X');
END CASE;
END PROCESS u_13combo_proc;
-- ModuleWare code(v1.9) for instance 'U_3' of 'split'
mw_U_3temp_din <= adr_pc_o_i;
u_3combo_proc: PROCESS (mw_U_3temp_din)
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
BEGIN
temp_din := mw_U_3temp_din(15 DOWNTO 0);
adr_pc_low_o_i <= temp_din(7 DOWNTO 0);
adr_pc_high_o_i <= temp_din(15 DOWNTO 8);
END PROCESS u_3combo_proc;
-- ModuleWare code(v1.9) for instance 'U_5' of 'split'
mw_U_5temp_din <= offset_i;
u_5combo_proc: PROCESS (mw_U_5temp_din)
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
BEGIN
temp_din := mw_U_5temp_din(15 DOWNTO 0);
offset_low_o_i <= temp_din(7 DOWNTO 0);
offset_high_o_i <= temp_din(15 DOWNTO 8);
END PROCESS u_5combo_proc;
-- Instance port mappings.
-- Implicit buffered output assignments
adr_nxt_pc_o <= adr_nxt_pc_o_internal;
adr_pc_o <= adr_pc_o_internal;
END struct;
| gpl-2.0 |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/AST_ROM/synth/AST_ROM.vhd | 1 | 6750 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0;
USE dist_mem_gen_v8_0.dist_mem_gen_v8_0;
ENTITY AST_ROM IS
PORT (
a : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END AST_ROM;
ARCHITECTURE AST_ROM_arch OF AST_ROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF AST_ROM_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF AST_ROM_arch: ARCHITECTURE IS "dist_mem_gen_v8_0,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF AST_ROM_arch : ARCHITECTURE IS "AST_ROM,dist_mem_gen_v8_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF AST_ROM_arch: ARCHITECTURE IS "AST_ROM,dist_mem_gen_v8_0,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_ADDR_WIDTH=14,C_DEFAULT_DATA=0,C_DEPTH=16384,C_HAS_CLK=0,C_HAS_D=0,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=0,C_MEM_INIT_FILE=AST_ROM.mif,C_ELABORATION_DIR=./,C_MEM_TYPE=0,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=1,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=8,C_PARSER_TYPE=1}";
BEGIN
U0 : dist_mem_gen_v8_0
GENERIC MAP (
C_FAMILY => "zynq",
C_ADDR_WIDTH => 14,
C_DEFAULT_DATA => "0",
C_DEPTH => 16384,
C_HAS_CLK => 0,
C_HAS_D => 0,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 0,
C_MEM_INIT_FILE => "AST_ROM.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 0,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 8,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
clk => '0',
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END AST_ROM_arch;
| gpl-2.0 |
545/Atari7800 | lab3sound/lab3sound.srcs/sources_1/imports/dsp_base_project/adau1761_izedboard.vhd | 3 | 4578 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:47:06 01/18/2014
-- Design Name:
-- Module Name: adau1761_izedboard - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library unisim;
use unisim.vcomponents.all;
entity adau1761_izedboard is
Port ( clk_48 : in STD_LOGIC;
AC_ADR0 : out STD_LOGIC;
AC_ADR1 : out STD_LOGIC;
AC_GPIO0 : out STD_LOGIC; -- I2S MISO
AC_GPIO1 : in STD_LOGIC; -- I2S MOSI
AC_GPIO2 : in STD_LOGIC; -- I2S_bclk
AC_GPIO3 : in STD_LOGIC; -- I2S_LR
AC_MCLK : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
AC_SDA : inout STD_LOGIC;
hphone_l : in std_logic_vector(15 downto 0);
hphone_r : in std_logic_vector(15 downto 0);
line_in_l : out std_logic_vector(15 downto 0);
line_in_r : out std_logic_vector(15 downto 0);
new_sample: out std_logic
);
end adau1761_izedboard;
architecture Behavioral of adau1761_izedboard is
COMPONENT i2c
PORT(
clk : IN std_logic;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : OUT std_logic);
END COMPONENT;
COMPONENT ADAU1761_interface
PORT(
clk_48 : IN std_logic;
codec_master_clk : OUT std_logic
);
END COMPONENT;
COMPONENT i2s_bit_clock
PORT(
clk_48 : IN std_logic;
pulse_per_bit : OUT std_logic;
i2s_clk : OUT std_logic
);
END COMPONENT;
component clocking
port(
CLK_100 : in std_logic;
CLK_48 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
COMPONENT audio_signal
PORT(
clk : IN std_logic;
sample_taken : IN std_logic;
audio_l : OUT std_logic_vector(15 downto 0);
audio_r : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT i2s_data_interface
PORT(
clk : IN std_logic;
audio_l_in : IN std_logic_vector(15 downto 0);
audio_r_in : IN std_logic_vector(15 downto 0);
i2s_bclk : IN std_logic;
i2s_lr : IN std_logic;
audio_l_out : OUT std_logic_vector(15 downto 0);
audio_r_out : OUT std_logic_vector(15 downto 0);
new_sample : OUT std_logic;
i2s_d_out : OUT std_logic;
i2s_d_in : IN std_logic
);
END COMPONENT;
signal audio_l : std_logic_vector(15 downto 0);
signal audio_r : std_logic_vector(15 downto 0);
signal codec_master_clk : std_logic;
signal i2c_scl : std_logic;
signal i2c_sda_i : std_logic;
signal i2c_sda_o : std_logic;
signal i2c_sda_t : std_logic;
signal i2s_mosi : std_logic;
signal i2s_miso : std_logic;
signal i2s_bclk : std_logic;
signal i2s_lr : std_logic;
begin
AC_ADR0 <= '1';
AC_ADR1 <= '1';
AC_GPIO0 <= i2s_MISO;
i2s_MOSI <= AC_GPIO1;
i2s_bclk <= AC_GPIO2;
i2s_lr <= AC_GPIO3;
AC_MCLK <= codec_master_clk;
AC_SCK <= i2c_scl;
i_i2s_sda_obuf : IOBUF
port map (
IO => AC_SDA, -- Buffer inout port (connect directly to top-level port)
O => i2c_sda_i, -- Buffer output (to fabric)
I => i2c_sda_o, -- Buffer input (from fabric)
T => i2c_sda_t -- 3-state enable input, high=input, low=output
);
Inst_i2c: i2c PORT MAP(
clk => CLK_48,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
i2c_sda_t => i2c_sda_t,
i2c_scl => i2c_scl
);
i_ADAU1761_interface: ADAU1761_interface PORT MAP(
clk_48 => clk_48 ,
codec_master_clk => codec_master_clk
);
Inst_i2s_data_interface: i2s_data_interface PORT MAP(
clk => clk_48,
audio_l_out => line_in_l,
audio_r_out => line_in_r,
audio_l_in => hphone_l,
audio_r_in => hphone_r,
new_sample => new_sample,
i2s_bclk => i2s_bclk,
i2s_d_out => i2s_MISO,
i2s_d_in => i2s_MOSI,
i2s_lr => i2s_lr
);
end Behavioral; | gpl-2.0 |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/MSPAC_DROM/dist_mem_gen_v8_0/hdl/dist_mem_gen_v8_0_vhsyn_rfs.vhd | 6 | 172455 | `protect begin_protected
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`protect end_protected
| gpl-2.0 |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/XEVIOUS_BROM/synth/XEVIOUS_BROM.vhd | 1 | 13960 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY XEVIOUS_BROM IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END XEVIOUS_BROM;
ARCHITECTURE XEVIOUS_BROM_arch OF XEVIOUS_BROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF XEVIOUS_BROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF XEVIOUS_BROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF XEVIOUS_BROM_arch : ARCHITECTURE IS "XEVIOUS_BROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF XEVIOUS_BROM_arch: ARCHITECTURE IS "XEVIOUS_BROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=XEVIOUS_BROM.mif,C_INIT_FILE=XEVIOUS_BROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=32768,C_READ_DEPTH_A=32768,C_ADDRA_WIDTH=15,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=32768,C_READ_DEPTH_B=32768,C_ADDRB_WIDTH=15,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "XEVIOUS_BROM.mif",
C_INIT_FILE => "XEVIOUS_BROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 32768,
C_READ_DEPTH_A => 32768,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 32768,
C_READ_DEPTH_B => 32768,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 15)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END XEVIOUS_BROM_arch;
| gpl-2.0 |
cafe-alpha/wasca | v12/fpga_firmware/wasca/synthesis/submodules/Altera_UP_SD_Signal_Trigger.vhd | 7 | 1749 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
---------------------------------------------------------------------------------------
-- This module generates a trigger pulse every time it sees a transition
-- from 0 to 1 on signal i_signal.
--
-- NOTES/REVISIONS:
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_Signal_Trigger is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_signal : in std_logic;
o_trigger : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Signal_Trigger is
-- Local wires
-- REGISTERED
signal local_reg : std_logic;
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
local_reg <= '0';
else
if (rising_edge(i_clock)) then
local_reg <= i_signal;
end if;
end if;
end process;
o_trigger <= '1' when ((local_reg = '0') and (i_signal = '1'))
else '0';
end rtl; | gpl-2.0 |
summershrimp/VHDLClock | Counter24.vhd | 1 | 1018 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity Counter24 is
Port(
h:out std_logic_vector(2 downto 0);
l:out std_logic_vector(3 downto 0);
co:out std_logic;
en:in std_logic;
clk:in std_logic;
rst:in std_logic
);
End Entity Counter24;
Architecture ArchCounter24 of Counter24 is
Begin
Process(clk, rst)
Variable tlow:std_logic_vector(3 downto 0);
Variable thigh:std_logic_vector(2 downto 0);
Begin
If rst = '1' then
tlow := (Others => '0' );
thigh := (Others => '0' );
Elsif clk'event and clk='1' Then
co<='0';
If en = '1' Then
If tlow < 10 Then
tlow := tlow + 1;
End If;
If tlow = 10 Then
thigh := thigh + 1;
tlow := (Others => '0' );
End If;
If thigh = 2 Then
if tlow = 4 Then
thigh := (Others => '0');
tlow := (Others => '0');
co<='1';
End If;
End If;
h<=thigh;
l<=tlow;
End If;
End If;
End Process;
End Architecture;
| gpl-2.0 |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/wasca_rst_controller_001.vhd | 6 | 9079 | -- wasca_rst_controller_001.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_rst_controller_001;
architecture rtl of wasca_rst_controller_001 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller_001 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_rst_controller_001
| gpl-2.0 |
upci/upci | Projeto/pc.vhd | 1 | 2554 | ---- Program Counter ---------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE work.processor_functions.all;
------------------------------------------------------------------------------------------------------------------
ENTITY pc IS
PORT (clk, nrst: IN STD_LOGIC; -- reset ativo em zero
PC_inc: IN STD_LOGIC; -- sinal que indica que o PC deve ser incrementado
PC_load: IN STD_LOGIC; -- sinal que indica que PC deve ser substituido pelo valor em PC_bus
PC_valid: IN STD_LOGIC; -- sinal que indica que o valor de PC deve ser colocado em PC_bus (ou Z se 0)
PC_bus: INOUT STD_LOGIC_VECTOR(n-1 DOWNTO 0);
PC_7seg: OUT STD_LOGIC_VECTOR(0 TO 15)); -- barramento de entrada/saida
END ENTITY pc;
------------------------------------------------------------------------------------------------------------------
ARCHITECTURE rtl OF pc IS
SIGNAL counter: INTEGER RANGE 0 to 2**n -1; -- contador em si
SIGNAL counter_vector: STD_LOGIC_VECTOR(n-1 DOWNTO 0);
COMPONENT bcd_to_7seg IS
PORT (bcd: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
en: IN STD_LOGIC;
output: OUT STD_LOGIC_VECTOR (0 TO 7));
END COMPONENT;
BEGIN
-- Se o PC_valid = '1', manda o valor do PC pro barramento. Caso contrario, manda Z.
PC_bus <= counter_vector
WHEN PC_valid = '1'
ELSE (OTHERS => 'Z');
counter_vector <= STD_LOGIC_VECTOR(to_unsigned(counter, PC_bus'length));
-- Gera a visualizacao 7seg
counter7seg_0: bcd_to_7seg PORT MAP(counter_vector(3 DOWNTO 0), seg_en, PC_7seg(0 TO 7));
counter7seg_1: bcd_to_7seg PORT MAP(counter_vector(7 DOWNTO 4), seg_en, PC_7seg(8 TO 15));
PROCESS (clk, nrst) IS
BEGIN
-- De forma assincrona, se o reset ficar em nivel 0, volta o contador pra 0
IF nrst = '0' THEN
counter <= 0;
-- Se teve uma borda de subida no clock, faz as outras coisas
ELSIF rising_edge(clk) THEN
-- A maior prioridade eh do incremento. Se esta em 1, incrementa o PC
IF PC_inc = '1' THEN
counter <= counter + 1;
-- Caso contrario, verifica se eh pra carregar o valor do bus.
ELSIF PC_load = '1' THEN
-- O PC_load deve carregar apenas o endereco, desconsiderando o OPCODE
counter <= TO_INTEGER(UNSIGNED(PC_bus(n-oplen-1 DOWNTO 0))); -- Cast de STD_LOGIC_VECTOR pra INTEGER
END IF;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
------------------------------------------------------------------------------------------------------------------ | gpl-2.0 |
summershrimp/VHDLClock | Timer.vhd | 1 | 1185 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity Timer is
Port(
clk, seth, setm: in std_logic;
ssig: out std_logic;
hsigh, msigh: out std_logic_vector(2 downto 0);
hsigl, msigl: out std_logic_vector(3 downto 0)
);
End Entity;
Architecture ArchTimer of Timer is
Component Counter60
Port(
h:out std_logic_vector(2 downto 0);
l:out std_logic_vector(3 downto 0);
co:out std_logic;
en:in std_logic;
clk:in std_logic;
rst:in std_logic
);
End Component Counter60;
Component Counter24
Port(
h:out std_logic_vector(2 downto 0);
l:out std_logic_vector(3 downto 0);
co:out std_logic;
en:in std_logic;
clk:in std_logic;
rst:in std_logic
);
End Component Counter24;
Signal hclk, mclk, hco, mco, srst, en, gnd: std_logic;
Begin
en <= '1';
gnd <= '0';
Sec:Counter60
Port Map(co=> mco, en=>en, clk=>clk, rst=>srst );
Min:Counter60
Port Map(msigh, msigl, hco, en, mclk , gnd);
Hor:Counter24
Port Map(h=>hsigh, l=>hsigl, en=>en, clk=>hclk, rst=>gnd );
ssig <= clk;
hclk<= seth or hco;
mclk<= setm or mco;
srst<= seth or setm;
End Architecture;
| gpl-2.0 |
cafe-alpha/wasca | obsolete/fpga_firmware_V2/ip_repo/ABus2AXI4Lite/hdl/ABus2AXI4Lite_Slave_AXI.vhd | 2 | 18750 | -- This one is a slave interface, it provides Zynq PS with access to system registers
-- and filesystem buffers. Since PS have its own memory interface, no need to provide
-- access for DDR here.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ABus2AXI4Lite_Slave_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_SLAVE_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_SLAVE_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
-- registers
PCNTR : out std_logic_vector(15 downto 0);
STATUS : out std_logic_vector(15 downto 0);
MODE : in std_logic_vector(15 downto 0);
HWVER : in std_logic_vector(15 downto 0);
SWVER : out std_logic_vector(15 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
SLAVE_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
SLAVE_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
SLAVE_AXI_AWADDR : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
SLAVE_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
SLAVE_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
SLAVE_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
SLAVE_AXI_WDATA : in std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
SLAVE_AXI_WSTRB : in std_logic_vector((C_SLAVE_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
SLAVE_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
SLAVE_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
SLAVE_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
SLAVE_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
SLAVE_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
SLAVE_AXI_ARADDR : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
SLAVE_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
SLAVE_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
SLAVE_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
SLAVE_AXI_RDATA : out std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
SLAVE_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
SLAVE_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
SLAVE_AXI_RREADY : in std_logic
);
end ABus2AXI4Lite_Slave_AXI;
architecture arch_imp of ABus2AXI4Lite_Slave_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_SLAVE_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_SLAVE_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 8
signal slv_reg0 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
SLAVE_AXI_AWREADY <= axi_awready;
SLAVE_AXI_WREADY <= axi_wready;
SLAVE_AXI_BRESP <= axi_bresp;
SLAVE_AXI_BVALID <= axi_bvalid;
SLAVE_AXI_ARREADY <= axi_arready;
SLAVE_AXI_RDATA <= axi_rdata;
SLAVE_AXI_RRESP <= axi_rresp;
SLAVE_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and SLAVE_AXI_AWVALID = '1' and SLAVE_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and SLAVE_AXI_AWVALID = '1' and SLAVE_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= SLAVE_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and SLAVE_AXI_WVALID = '1' and SLAVE_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and SLAVE_AXI_WVALID and axi_awready and SLAVE_AXI_AWVALID ;
process (SLAVE_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and SLAVE_AXI_AWVALID = '1' and axi_wready = '1' and SLAVE_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (SLAVE_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and SLAVE_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= SLAVE_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and SLAVE_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and SLAVE_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and SLAVE_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, axi_araddr, SLAVE_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000" =>
reg_data_out <= slv_reg0;
when b"001" =>
reg_data_out <= HWVER & MODE;--slv_reg1;
when b"010" =>
reg_data_out <= slv_reg2;
-- when b"011" =>
-- reg_data_out <= slv_reg3;
-- when b"100" =>
-- reg_data_out <= slv_reg4;
-- when b"101" =>
-- reg_data_out <= slv_reg5;
-- when b"110" =>
-- reg_data_out <= slv_reg6;
-- when b"111" =>
-- reg_data_out <= slv_reg7;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( SLAVE_AXI_ACLK ) is
begin
if (rising_edge (SLAVE_AXI_ACLK)) then
if ( SLAVE_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
PCNTR <= slv_reg0(15 downto 0);
STATUS <= slv_reg0(31 downto 16);
--MODE : in std_logic_vector(15 downto 0);
--HWVER : in std_logic_vector(15 downto 0);
SWVER <= slv_reg2(15 downto 0);
-- User logic ends
end arch_imp;
| gpl-2.0 |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/wasca_rst_controller.vhd | 6 | 9018 | -- wasca_rst_controller.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_rst_controller;
architecture rtl of wasca_rst_controller is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_rst_controller
| gpl-2.0 |
summershrimp/VHDLClock | Alarm.vhd | 1 | 915 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Library work;
use work.all;
Entity Alarm is
Port(
hlow, mlow: out std_logic_vector(3 downto 0);
hhigh,mhigh: out std_logic_vector(2 downto 0);
en, hadd, madd: in std_logic
);
End Entity Alarm;
Architecture ArchAlarm of Alarm is
Component Counter60
Port(
h:out std_logic_vector(2 downto 0);
l:out std_logic_vector(3 downto 0);
en:in std_logic;
clk:in std_logic;
rst:in std_logic
);
End Component Counter60;
Component Counter24
Port(
h:out std_logic_vector(2 downto 0);
l:out std_logic_vector(3 downto 0);
en:in std_logic;
clk:in std_logic;
rst:in std_logic
);
End Component Counter24;
Signal rst :std_logic;
Begin
rst<='0';
CM: Counter60
Port Map (mhigh, mlow, en, madd, rst);
CH: Counter24
Port Map (hhigh, hlow, en, hadd, rst);
End Architecture;
| gpl-2.0 |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/wasca_rst_controller_002.vhd | 6 | 9079 | -- wasca_rst_controller_002.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_rst_controller_002 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_rst_controller_002;
architecture rtl of wasca_rst_controller_002 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller_002 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_rst_controller_002
| gpl-2.0 |
peter-b/geda-gaf | netlist/examples/vams/vhdl/basic-vhdl/transitest.vhdl | 15 | 192 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY top_entity IS
END ENTITY top_entity;
| gpl-2.0 |
peter-b/geda-gaf | netlist/docs/README.vhdl | 7 | 598 |
The VHDL backend
Written by Magnus Danielson and improved by Thomas Heidel
A few things you have to care about:
1. In order to generate valid component declarations, you
have to add an additional attribute to each pin.
"type=IN" or "type=OUT" or "type=INOUT"
2. The "device" attribute must be unique to a symbol!
The verilog symbols of the same type for example, have all
the same device attribute and will therefore not work.
3. Make sure your component-library picks up the vhdl symbols instead
of the verilog symbols Library paths that show up last are searched
first!
| gpl-2.0 |
hpcn-uam/hardware_packet_train | ZedBoard/VHDL/precise_timestamp/precise_timestamp.vhd | 1 | 5316 | --/*******************************************************************************
-- *
-- *
-- * File:
-- * precise_timestamp.vhd
-- *
-- *
-- * Module:
-- * precise_timestamp
-- *
-- * Author:
-- * Mario Ruiz
-- *
-- *
-- * Copyright (C) 2015 - Mario Ruiz and HPCN-UAM High Performance Computing and Networking
-- *
-- * Licence:
-- * This file is part of the HPCN-NetFPGA 10G development base package.
-- *
-- * This file is free code: you can redistribute it and/or modify it under
-- * the terms of the GNU Lesser General Public License version 2.0 as
-- * published by the Free Software Foundation.
-- *
-- * This package is distributed in the hope that it will be useful, but
-- * WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- * Lesser General Public License for more details.
-- *
-- * You should have received a copy of the GNU Lesser General Public
-- * License along with the NetFPGA source package. If not, see
-- * http://www.gnu.org/licenses/.
-- *
-- */
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity precise_timestamp is
generic (
constant width_counter : integer := 32;
constant max_count : std_logic_vector := x"3B9ACA00"; -- 1.000.000.000 ns
constant high_time_pps : std_logic_vector := x"05F5E100"; -- 100.000.000 ns
constant counter_increment : integer :=10; -- 10ns
constant max_count_2 : std_logic_vector := x"1DCD6500"; -- 500.000.000 ns
constant fix_point_width : integer := 3
);
port (
aclk : in std_logic;
aresetn : in std_logic;
nanosecond : out std_logic_vector(width_counter-1 downto 0);
second : out std_logic_vector(width_counter-1 downto 0);
correction : in std_logic_vector(width_counter-1 downto 0);
updatesec : in std_logic_vector(width_counter-1 downto 0);
mode : in std_logic;
correction_enable : in std_logic;
pps : in std_logic;
pps_sync : out std_logic;
pps_internal : out std_logic
);
end precise_timestamp;
architecture Behavioral of precise_timestamp is
component counter is
generic (
constant width_counter : integer := 32;
constant max_count : std_logic_vector := x"3B9ACA00"; -- 1.000.000.000 ns
constant high_time_pps : std_logic_vector := x"05F5E100"; -- 100.000.000 ns
constant counter_increment : integer :=10 -- 10ns
);
port(
aclk : in std_logic;
aresetn : in std_logic;
timedrift : in std_logic_vector (1 downto 0);
pps : in std_logic;
pps_internal : out std_logic;
second : out std_logic_vector (width_counter-1 downto 0);
nanosecond : out std_logic_vector (width_counter-1 downto 0);
mode : in std_logic;
updatesec : in std_logic_vector (width_counter-1 downto 0)
);
end component;
component tuning is
generic (
constant width_counter : integer := 32;
constant counter_increment : integer :=10 -- 10ns
);
port (
aclk : in std_logic;
aresetn : in std_logic;
pps : in std_logic;
correction : in std_logic_vector(width_counter-1 downto 0);
timedrift : out std_logic_vector(1 downto 0);
correction_enable : in std_logic
);
end component;
signal nsec_counter,sec_counter : std_logic_vector(width_counter-1 downto 0);
signal time_corr : std_logic_vector(width_counter-1 downto 0 );
signal time_drift : std_logic_vector (1 downto 0);
signal pps_out : std_logic;
signal error_calc : std_logic_vector(width_counter-1 downto 0);
signal correction_calc : std_logic_vector(width_counter-1 downto 0);
signal pps_ant_ant : std_logic:='0';
signal pps_ant : std_logic:='0';
begin
CONT : counter
generic map (
width_counter => width_counter,
max_count => max_count,
high_time_pps => high_time_pps,
counter_increment => counter_increment
)
port map(
aclk => aclk,
aresetn => aresetn,
timedrift => time_drift,
pps => pps_ant_ant,
pps_internal => pps_out,
second => sec_counter,
nanosecond => nsec_counter,
mode => mode,
updatesec => updatesec
);
TUN : tuning
generic map (
width_counter => width_counter,
counter_increment => counter_increment
)
port map (
aclk => aclk,
aresetn => aresetn,
pps => pps_ant_ant,
correction => correction,
timedrift => time_drift,
correction_enable => correction_enable
);
process (aclk) -- synchroniser pps
begin
if rising_edge(aclk) then
pps_ant_ant <= pps_ant;
pps_ant <= pps;
end if;
end process;
pps_sync <= pps_ant_ant;
pps_internal <= pps_out;
second <= sec_counter;
nanosecond <= nsec_counter;
-- time_corr <= correction;
-- error_out <= error_calc;
end Behavioral;
| gpl-2.0 |
systec-dk/openPOWERLINK_systec | Examples/altera_nios2/SYSTEC_ECUcore-EP3C/design_nios2_directIO/niosII_openMac_clock_2.vhd | 8 | 29264 | --Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_2_edge_to_pulse is
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end entity niosII_openMac_clock_2_edge_to_pulse;
architecture europa of niosII_openMac_clock_2_edge_to_pulse is
signal data_in_d1 : STD_LOGIC;
begin
process (clock, reset_n)
begin
if reset_n = '0' then
data_in_d1 <= std_logic'('0');
elsif clock'event and clock = '1' then
data_in_d1 <= data_in;
end if;
end process;
data_out <= data_in XOR data_in_d1;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_2_slave_FSM is
port (
-- inputs:
signal master_read_done_token : IN STD_LOGIC;
signal master_write_done_token : IN STD_LOGIC;
signal slave_clk : IN STD_LOGIC;
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
-- outputs:
signal slave_read_request : OUT STD_LOGIC;
signal slave_waitrequest : OUT STD_LOGIC;
signal slave_write_request : OUT STD_LOGIC
);
end entity niosII_openMac_clock_2_slave_FSM;
architecture europa of niosII_openMac_clock_2_slave_FSM is
signal internal_slave_read_request : STD_LOGIC;
signal internal_slave_write_request : STD_LOGIC;
signal next_slave_read_request : STD_LOGIC;
signal next_slave_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_slave_write_request : STD_LOGIC;
signal slave_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
begin
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
internal_slave_read_request <= std_logic'('0');
elsif slave_clk'event and slave_clk = '1' then
if true then
internal_slave_read_request <= next_slave_read_request;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
internal_slave_write_request <= std_logic'('0');
elsif slave_clk'event and slave_clk = '1' then
if true then
internal_slave_write_request <= next_slave_write_request;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_state <= std_logic_vector'("001");
elsif slave_clk'event and slave_clk = '1' then
if true then
slave_state <= next_slave_state;
end if;
end if;
end process;
process (internal_slave_read_request, internal_slave_write_request, master_read_done_token, master_write_done_token, slave_read, slave_state, slave_write)
begin
case slave_state is -- synthesis parallel_case
when std_logic_vector'("001") =>
--read request: go from IDLE state to READ_WAIT state
if std_logic'(slave_read) = '1' then
next_slave_state <= std_logic_vector'("010");
slave_waitrequest <= std_logic'('1');
next_slave_read_request <= NOT(internal_slave_read_request);
next_slave_write_request <= internal_slave_write_request;
elsif std_logic'(slave_write) = '1' then
next_slave_state <= std_logic_vector'("100");
slave_waitrequest <= std_logic'('1');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= NOT(internal_slave_write_request);
else
next_slave_state <= slave_state;
slave_waitrequest <= std_logic'('0');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
end if;
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
--stay in READ_WAIT state until master passes read done token
if std_logic'(master_read_done_token) = '1' then
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
else
next_slave_state <= std_logic_vector'("010");
slave_waitrequest <= std_logic'('1');
end if;
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when std_logic_vector'("010")
when std_logic_vector'("100") =>
--stay in WRITE_WAIT state until master passes write done token
if std_logic'(master_write_done_token) = '1' then
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
else
next_slave_state <= std_logic_vector'("100");
slave_waitrequest <= std_logic'('1');
end if;
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when std_logic_vector'("100")
when others =>
next_slave_state <= std_logic_vector'("001");
slave_waitrequest <= std_logic'('0');
next_slave_read_request <= internal_slave_read_request;
next_slave_write_request <= internal_slave_write_request;
-- when others
end case; -- slave_state
end process;
--vhdl renameroo for output signals
slave_read_request <= internal_slave_read_request;
--vhdl renameroo for output signals
slave_write_request <= internal_slave_write_request;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_2_master_FSM is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_read_request_token : IN STD_LOGIC;
signal slave_write_request_token : IN STD_LOGIC;
-- outputs:
signal master_read : OUT STD_LOGIC;
signal master_read_done : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_write_done : OUT STD_LOGIC
);
end entity niosII_openMac_clock_2_master_FSM;
architecture europa of niosII_openMac_clock_2_master_FSM is
signal internal_master_read1 : STD_LOGIC;
signal internal_master_read_done : STD_LOGIC;
signal internal_master_write1 : STD_LOGIC;
signal internal_master_write_done : STD_LOGIC;
signal master_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_master_read : STD_LOGIC;
signal next_master_read_done : STD_LOGIC;
signal next_master_state : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal next_master_write : STD_LOGIC;
signal next_master_write_done : STD_LOGIC;
begin
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_read_done <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_read_done <= next_master_read_done;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_write_done <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_write_done <= next_master_write_done;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_read1 <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_read1 <= next_master_read;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
internal_master_write1 <= std_logic'('0');
elsif master_clk'event and master_clk = '1' then
if true then
internal_master_write1 <= next_master_write;
end if;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_state <= std_logic_vector'("001");
elsif master_clk'event and master_clk = '1' then
if true then
master_state <= next_master_state;
end if;
end if;
end process;
process (internal_master_read1, internal_master_read_done, internal_master_write1, internal_master_write_done, master_state, master_waitrequest, slave_read_request_token, slave_write_request_token)
begin
case master_state is -- synthesis parallel_case
when std_logic_vector'("001") =>
--if read request token from slave then goto READ_WAIT state
if std_logic'(slave_read_request_token) = '1' then
next_master_state <= std_logic_vector'("010");
next_master_read <= std_logic'('1');
next_master_write <= std_logic'('0');
elsif std_logic'(slave_write_request_token) = '1' then
next_master_state <= std_logic_vector'("100");
next_master_read <= std_logic'('0');
next_master_write <= std_logic'('1');
else
next_master_state <= master_state;
next_master_read <= std_logic'('0');
next_master_write <= std_logic'('0');
end if;
next_master_read_done <= internal_master_read_done;
next_master_write_done <= internal_master_write_done;
-- when std_logic_vector'("001")
when std_logic_vector'("010") =>
--stay in READ_WAIT state until master wait is deasserted
if std_logic'(NOT(master_waitrequest)) = '1' then
next_master_state <= std_logic_vector'("001");
next_master_read_done <= NOT(internal_master_read_done);
next_master_read <= std_logic'('0');
else
next_master_state <= std_logic_vector'("010");
next_master_read_done <= internal_master_read_done;
next_master_read <= internal_master_read1;
end if;
next_master_write_done <= internal_master_write_done;
next_master_write <= std_logic'('0');
-- when std_logic_vector'("010")
when std_logic_vector'("100") =>
--stay in WRITE_WAIT state until slave wait is deasserted
if std_logic'(NOT(master_waitrequest)) = '1' then
next_master_state <= std_logic_vector'("001");
next_master_write <= std_logic'('0');
next_master_write_done <= NOT(internal_master_write_done);
else
next_master_state <= std_logic_vector'("100");
next_master_write <= internal_master_write1;
next_master_write_done <= internal_master_write_done;
end if;
next_master_read_done <= internal_master_read_done;
next_master_read <= std_logic'('0');
-- when std_logic_vector'("100")
when others =>
next_master_state <= std_logic_vector'("001");
next_master_write <= std_logic'('0');
next_master_write_done <= internal_master_write_done;
next_master_read <= std_logic'('0');
next_master_read_done <= internal_master_read_done;
-- when others
end case; -- master_state
end process;
--vhdl renameroo for output signals
master_read <= internal_master_read1;
--vhdl renameroo for output signals
master_read_done <= internal_master_read_done;
--vhdl renameroo for output signals
master_write <= internal_master_write1;
--vhdl renameroo for output signals
master_write_done <= internal_master_write_done;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity niosII_openMac_clock_2_bit_pipe is
port (
-- inputs:
signal clk1 : IN STD_LOGIC;
signal clk2 : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_clk1_n : IN STD_LOGIC;
signal reset_clk2_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end entity niosII_openMac_clock_2_bit_pipe;
architecture europa of niosII_openMac_clock_2_bit_pipe is
signal data_in_d1 : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of data_in_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of data_out : signal is "PRESERVE_REGISTER=ON";
begin
process (clk1, reset_clk1_n)
begin
if reset_clk1_n = '0' then
data_in_d1 <= std_logic'('0');
elsif clk1'event and clk1 = '1' then
data_in_d1 <= data_in;
end if;
end process;
process (clk2, reset_clk2_n)
begin
if reset_clk2_n = '0' then
data_out <= std_logic'('0');
elsif clk2'event and clk2 = '1' then
data_out <= data_in_d1;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--Clock Domain Crossing AdapterniosII_openMac_clock_2
entity niosII_openMac_clock_2 is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_endofpacket : IN STD_LOGIC;
signal master_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_address : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal slave_byteenable : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal slave_clk : IN STD_LOGIC;
signal slave_nativeaddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
signal slave_writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal master_address : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal master_byteenable : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal master_nativeaddress : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
signal master_read : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal slave_endofpacket : OUT STD_LOGIC;
signal slave_readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal slave_waitrequest : OUT STD_LOGIC
);
end entity niosII_openMac_clock_2;
architecture europa of niosII_openMac_clock_2 is
component altera_std_synchronizer is
GENERIC (
depth : NATURAL
);
PORT (
signal dout : OUT STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal din : IN STD_LOGIC
);
end component altera_std_synchronizer;
component niosII_openMac_clock_2_edge_to_pulse is
port (
-- inputs:
signal clock : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end component niosII_openMac_clock_2_edge_to_pulse;
component niosII_openMac_clock_2_slave_FSM is
port (
-- inputs:
signal master_read_done_token : IN STD_LOGIC;
signal master_write_done_token : IN STD_LOGIC;
signal slave_clk : IN STD_LOGIC;
signal slave_read : IN STD_LOGIC;
signal slave_reset_n : IN STD_LOGIC;
signal slave_write : IN STD_LOGIC;
-- outputs:
signal slave_read_request : OUT STD_LOGIC;
signal slave_waitrequest : OUT STD_LOGIC;
signal slave_write_request : OUT STD_LOGIC
);
end component niosII_openMac_clock_2_slave_FSM;
component niosII_openMac_clock_2_master_FSM is
port (
-- inputs:
signal master_clk : IN STD_LOGIC;
signal master_reset_n : IN STD_LOGIC;
signal master_waitrequest : IN STD_LOGIC;
signal slave_read_request_token : IN STD_LOGIC;
signal slave_write_request_token : IN STD_LOGIC;
-- outputs:
signal master_read : OUT STD_LOGIC;
signal master_read_done : OUT STD_LOGIC;
signal master_write : OUT STD_LOGIC;
signal master_write_done : OUT STD_LOGIC
);
end component niosII_openMac_clock_2_master_FSM;
component niosII_openMac_clock_2_bit_pipe is
port (
-- inputs:
signal clk1 : IN STD_LOGIC;
signal clk2 : IN STD_LOGIC;
signal data_in : IN STD_LOGIC;
signal reset_clk1_n : IN STD_LOGIC;
signal reset_clk2_n : IN STD_LOGIC;
-- outputs:
signal data_out : OUT STD_LOGIC
);
end component niosII_openMac_clock_2_bit_pipe;
signal internal_master_read : STD_LOGIC;
signal internal_master_write : STD_LOGIC;
signal internal_slave_endofpacket : STD_LOGIC;
signal internal_slave_waitrequest : STD_LOGIC;
signal master_read_done : STD_LOGIC;
signal master_read_done_sync : STD_LOGIC;
signal master_read_done_token : STD_LOGIC;
signal master_write_done : STD_LOGIC;
signal master_write_done_sync : STD_LOGIC;
signal master_write_done_token : STD_LOGIC;
signal slave_address_d1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal slave_byteenable_d1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal slave_nativeaddress_d1 : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal slave_read_request : STD_LOGIC;
signal slave_read_request_sync : STD_LOGIC;
signal slave_read_request_token : STD_LOGIC;
signal slave_readdata_p1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal slave_write_request : STD_LOGIC;
signal slave_write_request_sync : STD_LOGIC;
signal slave_write_request_token : STD_LOGIC;
signal slave_writedata_d1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of master_address : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_byteenable : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_nativeaddress : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of master_writedata : signal is "PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_address_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_byteenable_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_nativeaddress_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of slave_readdata : signal is "{-from ""*""} CUT=ON";
attribute ALTERA_ATTRIBUTE of slave_writedata_d1 : signal is "{-to ""*""} CUT=ON ; PRESERVE_REGISTER=ON";
begin
--in, which is an e_avalon_slave
--out, which is an e_avalon_master
the_altera_std_synchronizer : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => slave_clk,
din => master_read_done,
dout => master_read_done_sync,
reset_n => slave_reset_n
);
the_altera_std_synchronizer1 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => slave_clk,
din => master_write_done,
dout => master_write_done_sync,
reset_n => slave_reset_n
);
--read_done_edge_to_pulse, which is an e_instance
read_done_edge_to_pulse : niosII_openMac_clock_2_edge_to_pulse
port map(
data_out => master_read_done_token,
clock => slave_clk,
data_in => master_read_done_sync,
reset_n => slave_reset_n
);
--write_done_edge_to_pulse, which is an e_instance
write_done_edge_to_pulse : niosII_openMac_clock_2_edge_to_pulse
port map(
data_out => master_write_done_token,
clock => slave_clk,
data_in => master_write_done_sync,
reset_n => slave_reset_n
);
--slave_FSM, which is an e_instance
slave_FSM : niosII_openMac_clock_2_slave_FSM
port map(
slave_read_request => slave_read_request,
slave_waitrequest => internal_slave_waitrequest,
slave_write_request => slave_write_request,
master_read_done_token => master_read_done_token,
master_write_done_token => master_write_done_token,
slave_clk => slave_clk,
slave_read => slave_read,
slave_reset_n => slave_reset_n,
slave_write => slave_write
);
the_altera_std_synchronizer2 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => master_clk,
din => slave_read_request,
dout => slave_read_request_sync,
reset_n => master_reset_n
);
the_altera_std_synchronizer3 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => master_clk,
din => slave_write_request,
dout => slave_write_request_sync,
reset_n => master_reset_n
);
--read_request_edge_to_pulse, which is an e_instance
read_request_edge_to_pulse : niosII_openMac_clock_2_edge_to_pulse
port map(
data_out => slave_read_request_token,
clock => master_clk,
data_in => slave_read_request_sync,
reset_n => master_reset_n
);
--write_request_edge_to_pulse, which is an e_instance
write_request_edge_to_pulse : niosII_openMac_clock_2_edge_to_pulse
port map(
data_out => slave_write_request_token,
clock => master_clk,
data_in => slave_write_request_sync,
reset_n => master_reset_n
);
--master_FSM, which is an e_instance
master_FSM : niosII_openMac_clock_2_master_FSM
port map(
master_read => internal_master_read,
master_read_done => master_read_done,
master_write => internal_master_write,
master_write_done => master_write_done,
master_clk => master_clk,
master_reset_n => master_reset_n,
master_waitrequest => master_waitrequest,
slave_read_request_token => slave_read_request_token,
slave_write_request_token => slave_write_request_token
);
--endofpacket_bit_pipe, which is an e_instance
endofpacket_bit_pipe : niosII_openMac_clock_2_bit_pipe
port map(
data_out => internal_slave_endofpacket,
clk1 => slave_clk,
clk2 => master_clk,
data_in => master_endofpacket,
reset_clk1_n => slave_reset_n,
reset_clk2_n => master_reset_n
);
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
slave_readdata_p1 <= std_logic_vector'("0000000000000000");
elsif master_clk'event and master_clk = '1' then
if std_logic'((internal_master_read AND NOT master_waitrequest)) = '1' then
slave_readdata_p1 <= master_readdata;
end if;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_readdata <= std_logic_vector'("0000000000000000");
elsif slave_clk'event and slave_clk = '1' then
slave_readdata <= slave_readdata_p1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_writedata_d1 <= std_logic_vector'("0000000000000000");
elsif slave_clk'event and slave_clk = '1' then
slave_writedata_d1 <= slave_writedata;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_writedata <= std_logic_vector'("0000000000000000");
elsif master_clk'event and master_clk = '1' then
master_writedata <= slave_writedata_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_address_d1 <= std_logic_vector'("0000");
elsif slave_clk'event and slave_clk = '1' then
slave_address_d1 <= slave_address;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_address <= std_logic_vector'("0000");
elsif master_clk'event and master_clk = '1' then
master_address <= slave_address_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_nativeaddress_d1 <= std_logic_vector'("000");
elsif slave_clk'event and slave_clk = '1' then
slave_nativeaddress_d1 <= slave_nativeaddress;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_nativeaddress <= std_logic_vector'("000");
elsif master_clk'event and master_clk = '1' then
master_nativeaddress <= slave_nativeaddress_d1;
end if;
end process;
process (slave_clk, slave_reset_n)
begin
if slave_reset_n = '0' then
slave_byteenable_d1 <= std_logic_vector'("00");
elsif slave_clk'event and slave_clk = '1' then
slave_byteenable_d1 <= slave_byteenable;
end if;
end process;
process (master_clk, master_reset_n)
begin
if master_reset_n = '0' then
master_byteenable <= std_logic_vector'("00");
elsif master_clk'event and master_clk = '1' then
master_byteenable <= slave_byteenable_d1;
end if;
end process;
--vhdl renameroo for output signals
master_read <= internal_master_read;
--vhdl renameroo for output signals
master_write <= internal_master_write;
--vhdl renameroo for output signals
slave_endofpacket <= internal_slave_endofpacket;
--vhdl renameroo for output signals
slave_waitrequest <= internal_slave_waitrequest;
end europa;
| gpl-2.0 |
systec-dk/openPOWERLINK_systec | Examples/ipcore/xilinx/library/pcores/axi_powerlink_v0_30_a/hdl/vhdl/axi_powerlink.vhd | 3 | 86416 | -------------------------------------------------------------------------------
--! @file axi_powerlink.vhd
--
--! @brief
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This is the toplevel file for using the POWERLINK IP-Core
-- with Xilinx AXI.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use work.global.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_master_burst_v1_00_a;
use axi_master_burst_v1_00_a.axi_master_burst;
-- standard libraries declarations
library UNISIM;
use UNISIM.vcomponents.all;
-- pragma synthesis_off
library IEEE;
use IEEE.vital_timing.all;
-- pragma synthesis_on
-- other libraries declarations
library AXI_LITE_IPIF_V1_01_A;
library AXI_MASTER_BURST_V1_00_A;
entity axi_powerlink is
generic(
C_FAMILY : string := "spartan6";
-- general
C_GEN_PDI : boolean := false;
C_GEN_PAR_IF : boolean := false;
C_GEN_SPI_IF : boolean := false;
C_GEN_AXI_BUS_IF : boolean := false;
C_GEN_SIMPLE_IO : boolean := false;
-- openMAC
C_MAC_PKT_SIZE : integer := 1024;
C_MAC_PKT_SIZE_LOG2 : integer := 10;
C_MAC_RX_BUFFERS : integer := 16;
C_USE_RMII : boolean := false;
C_TX_INT_PKT : boolean := false;
C_RX_INT_PKT : boolean := false;
C_USE_2ND_PHY : boolean := true;
C_NUM_SMI : integer range 1 to 2 := 2;
C_MAC_GEN_SECOND_TIMER : boolean := false;
--pdi
C_PDI_REV : integer := 0;
C_PCP_SYS_ID : integer := 0;
C_PDI_GEN_ASYNC_BUF_0 : boolean := true;
C_PDI_ASYNC_BUF_0 : integer := 50;
C_PDI_GEN_ASYNC_BUF_1 : boolean := true;
C_PDI_ASYNC_BUF_1 : integer := 50;
C_PDI_GEN_LED : boolean := false;
C_PDI_GEN_TIME_SYNC : boolean := true;
C_PDI_GEN_EVENT : boolean := true;
--global pdi and mac
C_NUM_RPDO : integer := 3;
C_RPDO_0_BUF_SIZE : integer := 100;
C_RPDO_1_BUF_SIZE : integer := 100;
C_RPDO_2_BUF_SIZE : integer := 100;
C_NUM_TPDO : integer := 1;
C_TPDO_BUF_SIZE : integer := 100;
-- pap
C_PAP_DATA_WIDTH : integer := 16;
--C_PAP_BIG_END : boolean := false;
C_PAP_LOW_ACT : boolean := false;
-- spi
C_SPI_CPOL : boolean := false;
C_SPI_CPHA : boolean := false;
--C_SPI_BIG_END : boolean := false;
-- simpleIO
C_PIO_VAL_LENGTH : integer := 50;
-- debug
C_OBSERVER_ENABLE : boolean := false;
-- clock stabiliser
C_INSTANCE_ODDR2 : boolean := false;
-- sync IRQ pulse width
C_USE_PULSE_2nd_CMP_TIMER : boolean := true;
C_PULSE_WIDTH_2nd_CMP_TIMER : integer := 9;
-- PDI AP AXI Slave
C_S_AXI_PDI_AP_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_PDI_AP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_S_AXI_PDI_AP_DATA_WIDTH : integer := 32;
C_S_AXI_PDI_AP_ADDR_WIDTH : integer := 32;
C_S_AXI_PDI_AP_USE_WSTRB : integer := 1;
C_S_AXI_PDI_AP_DPHASE_TIMEOUT : integer := 8;
-- PDI AP AXI Slave
C_S_AXI_SMP_PCP_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_SMP_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_S_AXI_SMP_PCP_DATA_WIDTH : integer := 32;
C_S_AXI_SMP_PCP_ADDR_WIDTH : integer := 32;
C_S_AXI_SMP_PCP_USE_WSTRB : integer := 1;
C_S_AXI_SMP_PCP_DPHASE_TIMEOUT : integer := 8;
-- PDI PCP AXI Slave
C_S_AXI_PDI_PCP_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_PDI_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_S_AXI_PDI_PCP_DATA_WIDTH : integer := 32;
C_S_AXI_PDI_PCP_ADDR_WIDTH : integer := 32;
C_S_AXI_PDI_PCP_USE_WSTRB : integer := 1;
C_S_AXI_PDI_PCP_DPHASE_TIMEOUT : integer := 8;
-- openMAC DMA AXI Master
C_M_AXI_MAC_DMA_ADDR_WIDTH : INTEGER := 32;
C_M_AXI_MAC_DMA_DATA_WIDTH : INTEGER := 32;
C_M_AXI_MAC_DMA_NATIVE_DWIDTH : INTEGER := 32;
C_M_AXI_MAC_DMA_LENGTH_WIDTH : INTEGER := 12;
C_M_AXI_MAC_DMA_MAX_BURST_LEN : INTEGER := 16;
C_MAC_DMA_BURST_SIZE_RX : INTEGER := 8; --in bytes
C_MAC_DMA_BURST_SIZE_TX : INTEGER := 8; --in bytes
C_MAC_DMA_FIFO_SIZE_RX : INTEGER := 32; --in bytes
C_MAC_DMA_FIFO_SIZE_TX : INTEGER := 32; --in bytes
-- openMAC PKT AXI Slave
C_S_AXI_MAC_PKT_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_MAC_PKT_HIGHADDR : std_logic_vector := X"000FFFFF";
C_S_AXI_MAC_PKT_DATA_WIDTH : integer := 32;
C_S_AXI_MAC_PKT_ADDR_WIDTH : integer := 32;
C_S_AXI_MAC_PKT_USE_WSTRB : integer := 1;
C_S_AXI_MAC_PKT_DPHASE_TIMEOUT : integer := 8;
-- openMAC REG AXI Slave
--- MAC_REG
C_S_AXI_MAC_REG_RNG0_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_MAC_REG_RNG0_HIGHADDR : std_logic_vector := X"0000FFFF";
--- MAC_CMP
C_S_AXI_MAC_REG_RNG1_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_MAC_REG_RNG1_HIGHADDR : std_logic_vector := X"0000FFFF";
C_S_AXI_MAC_REG_DATA_WIDTH : integer := 32;
C_S_AXI_MAC_REG_ADDR_WIDTH : integer := 32;
C_S_AXI_MAC_REG_USE_WSTRB : integer := 1;
C_S_AXI_MAC_REG_DPHASE_TIMEOUT : integer := 8;
C_S_AXI_MAC_REG_ACLK_FREQ_HZ : integer := 20 --clock frequency in Hz
);
port(
M_AXI_MAC_DMA_aclk : in std_logic;
M_AXI_MAC_DMA_aresetn : in std_logic;
M_AXI_MAC_DMA_arready : in std_logic;
M_AXI_MAC_DMA_awready : in std_logic;
M_AXI_MAC_DMA_bvalid : in std_logic;
M_AXI_MAC_DMA_rlast : in std_logic;
M_AXI_MAC_DMA_rvalid : in std_logic;
M_AXI_MAC_DMA_wready : in std_logic;
S_AXI_MAC_PKT_ACLK : in std_logic;
S_AXI_MAC_PKT_ARESETN : in std_logic;
S_AXI_MAC_PKT_ARVALID : in std_logic;
S_AXI_MAC_PKT_AWVALID : in std_logic;
S_AXI_MAC_PKT_BREADY : in std_logic;
S_AXI_MAC_PKT_RREADY : in std_logic;
S_AXI_MAC_PKT_WVALID : in std_logic;
S_AXI_MAC_REG_ACLK : in std_logic;
S_AXI_MAC_REG_ARESETN : in std_logic;
S_AXI_MAC_REG_ARVALID : in std_logic;
S_AXI_MAC_REG_AWVALID : in std_logic;
S_AXI_MAC_REG_BREADY : in std_logic;
S_AXI_MAC_REG_RREADY : in std_logic;
S_AXI_MAC_REG_WVALID : in std_logic;
S_AXI_PDI_AP_ACLK : in std_logic;
S_AXI_PDI_AP_ARESETN : in std_logic;
S_AXI_PDI_AP_ARVALID : in std_logic;
S_AXI_PDI_AP_AWVALID : in std_logic;
S_AXI_PDI_AP_BREADY : in std_logic;
S_AXI_PDI_AP_RREADY : in std_logic;
S_AXI_PDI_AP_WVALID : in std_logic;
S_AXI_PDI_PCP_ACLK : in std_logic;
S_AXI_PDI_PCP_ARESETN : in std_logic;
S_AXI_PDI_PCP_ARVALID : in std_logic;
S_AXI_PDI_PCP_AWVALID : in std_logic;
S_AXI_PDI_PCP_BREADY : in std_logic;
S_AXI_PDI_PCP_RREADY : in std_logic;
S_AXI_PDI_PCP_WVALID : in std_logic;
S_AXI_SMP_PCP_ACLK : in std_logic;
S_AXI_SMP_PCP_ARESETN : in std_logic;
S_AXI_SMP_PCP_ARVALID : in std_logic;
S_AXI_SMP_PCP_AWVALID : in std_logic;
S_AXI_SMP_PCP_BREADY : in std_logic;
S_AXI_SMP_PCP_RREADY : in std_logic;
S_AXI_SMP_PCP_WVALID : in std_logic;
clk100 : in std_logic;
clk50 : in std_logic;
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic;
phy0_link : in std_logic;
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic;
phy1_link : in std_logic;
phyMii0_RxClk : in std_logic;
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic;
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
M_AXI_MAC_DMA_bresp : in std_logic_vector(1 downto 0);
M_AXI_MAC_DMA_rdata : in std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
M_AXI_MAC_DMA_rresp : in std_logic_vector(1 downto 0);
S_AXI_MAC_PKT_ARADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
S_AXI_MAC_PKT_AWADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
S_AXI_MAC_PKT_WDATA : in std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
S_AXI_MAC_PKT_WSTRB : in std_logic_vector((C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0);
S_AXI_MAC_REG_ARADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
S_AXI_MAC_REG_AWADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
S_AXI_MAC_REG_WDATA : in std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
S_AXI_MAC_REG_WSTRB : in std_logic_vector((C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0);
S_AXI_PDI_AP_ARADDR : in std_logic_vector(C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0);
S_AXI_PDI_AP_AWADDR : in std_logic_vector(C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0);
S_AXI_PDI_AP_WDATA : in std_logic_vector(C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0);
S_AXI_PDI_AP_WSTRB : in std_logic_vector((C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0);
S_AXI_PDI_PCP_ARADDR : in std_logic_vector(C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0);
S_AXI_PDI_PCP_AWADDR : in std_logic_vector(C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0);
S_AXI_PDI_PCP_WDATA : in std_logic_vector(C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0);
S_AXI_PDI_PCP_WSTRB : in std_logic_vector((C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0);
S_AXI_SMP_PCP_ARADDR : in std_logic_vector(C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0);
S_AXI_SMP_PCP_AWADDR : in std_logic_vector(C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0);
S_AXI_SMP_PCP_WDATA : in std_logic_vector(C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0);
S_AXI_SMP_PCP_WSTRB : in std_logic_vector((C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_be_n : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_data_I : in std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy1_RxDat : in std_logic_vector(1 downto 0);
phyMii0_RxDat : in std_logic_vector(3 downto 0);
phyMii1_RxDat : in std_logic_vector(3 downto 0);
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0);
M_AXI_MAC_DMA_arvalid : out std_logic;
M_AXI_MAC_DMA_awvalid : out std_logic;
M_AXI_MAC_DMA_bready : out std_logic;
M_AXI_MAC_DMA_md_error : out std_logic;
M_AXI_MAC_DMA_rready : out std_logic;
M_AXI_MAC_DMA_wlast : out std_logic;
M_AXI_MAC_DMA_wvalid : out std_logic;
S_AXI_MAC_PKT_ARREADY : out std_logic;
S_AXI_MAC_PKT_AWREADY : out std_logic;
S_AXI_MAC_PKT_BVALID : out std_logic;
S_AXI_MAC_PKT_RVALID : out std_logic;
S_AXI_MAC_PKT_WREADY : out std_logic;
S_AXI_MAC_REG_ARREADY : out std_logic;
S_AXI_MAC_REG_AWREADY : out std_logic;
S_AXI_MAC_REG_BVALID : out std_logic;
S_AXI_MAC_REG_RVALID : out std_logic;
S_AXI_MAC_REG_WREADY : out std_logic;
S_AXI_PDI_AP_ARREADY : out std_logic;
S_AXI_PDI_AP_AWREADY : out std_logic;
S_AXI_PDI_AP_BVALID : out std_logic;
S_AXI_PDI_AP_RVALID : out std_logic;
S_AXI_PDI_AP_WREADY : out std_logic;
S_AXI_PDI_PCP_ARREADY : out std_logic;
S_AXI_PDI_PCP_AWREADY : out std_logic;
S_AXI_PDI_PCP_BVALID : out std_logic;
S_AXI_PDI_PCP_RVALID : out std_logic;
S_AXI_PDI_PCP_WREADY : out std_logic;
S_AXI_SMP_PCP_ARREADY : out std_logic;
S_AXI_SMP_PCP_AWREADY : out std_logic;
S_AXI_SMP_PCP_BVALID : out std_logic;
S_AXI_SMP_PCP_RVALID : out std_logic;
S_AXI_SMP_PCP_WREADY : out std_logic;
ap_asyncIrq : out std_logic;
ap_asyncIrq_n : out std_logic;
ap_syncIrq : out std_logic;
ap_syncIrq_n : out std_logic;
led_error : out std_logic;
led_status : out std_logic;
mac_irq : out std_logic;
pap_ack : out std_logic;
pap_ack_n : out std_logic;
pap_data_T : out std_logic;
phy0_Rst_n : out std_logic;
phy0_SMIClk : out std_logic;
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxEn : out std_logic;
phy0_clk : out std_logic;
phy1_Rst_n : out std_logic;
phy1_SMIClk : out std_logic;
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxEn : out std_logic;
phy1_clk : out std_logic;
phyMii0_TxEn : out std_logic;
phyMii0_TxEr : out std_logic;
phyMii1_TxEn : out std_logic;
phyMii1_TxEr : out std_logic;
phy_Rst_n : out std_logic;
phy_SMIClk : out std_logic;
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic;
spi_miso : out std_logic;
tcp_irq : out std_logic;
M_AXI_MAC_DMA_araddr : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
M_AXI_MAC_DMA_arburst : out std_logic_vector(1 downto 0);
M_AXI_MAC_DMA_arcache : out std_logic_vector(3 downto 0);
M_AXI_MAC_DMA_arlen : out std_logic_vector(7 downto 0);
M_AXI_MAC_DMA_arprot : out std_logic_vector(2 downto 0);
M_AXI_MAC_DMA_arsize : out std_logic_vector(2 downto 0);
M_AXI_MAC_DMA_awaddr : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
M_AXI_MAC_DMA_awburst : out std_logic_vector(1 downto 0);
M_AXI_MAC_DMA_awcache : out std_logic_vector(3 downto 0);
M_AXI_MAC_DMA_awlen : out std_logic_vector(7 downto 0);
M_AXI_MAC_DMA_awprot : out std_logic_vector(2 downto 0);
M_AXI_MAC_DMA_awsize : out std_logic_vector(2 downto 0);
M_AXI_MAC_DMA_wdata : out std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
M_AXI_MAC_DMA_wstrb : out std_logic_vector((C_M_AXI_MAC_DMA_DATA_WIDTH/8)-1 downto 0);
S_AXI_MAC_PKT_BRESP : out std_logic_vector(1 downto 0);
S_AXI_MAC_PKT_RDATA : out std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
S_AXI_MAC_PKT_RRESP : out std_logic_vector(1 downto 0);
S_AXI_MAC_REG_BRESP : out std_logic_vector(1 downto 0);
S_AXI_MAC_REG_RDATA : out std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
S_AXI_MAC_REG_RRESP : out std_logic_vector(1 downto 0);
S_AXI_PDI_AP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_PDI_AP_RDATA : out std_logic_vector(C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0);
S_AXI_PDI_AP_RRESP : out std_logic_vector(1 downto 0);
S_AXI_PDI_PCP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_PDI_PCP_RDATA : out std_logic_vector(C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0);
S_AXI_PDI_PCP_RRESP : out std_logic_vector(1 downto 0);
S_AXI_SMP_PCP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_SMP_PCP_RDATA : out std_logic_vector(C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0);
S_AXI_SMP_PCP_RRESP : out std_logic_vector(1 downto 0);
led_gpo : out std_logic_vector(7 downto 0);
led_opt : out std_logic_vector(1 downto 0);
led_phyAct : out std_logic_vector(1 downto 0);
led_phyLink : out std_logic_vector(1 downto 0);
pap_data_O : out std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
phy0_TxDat : out std_logic_vector(1 downto 0);
phy1_TxDat : out std_logic_vector(1 downto 0);
phyMii0_TxDat : out std_logic_vector(3 downto 0);
phyMii1_TxDat : out std_logic_vector(3 downto 0);
pio_portOutValid : out std_logic_vector(3 downto 0);
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
test_port : out std_logic_vector(255 downto 0) := (others => '0')
);
-- Entity declarations --
-- Click here to add additional declarations --
attribute SIGIS : string;
-- Entity attributes --
attribute SIGIS of M_AXI_MAC_DMA_aclk : signal is "Clk";
attribute SIGIS of M_AXI_MAC_DMA_aresetn : signal is "Rst";
attribute SIGIS of S_AXI_MAC_PKT_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_MAC_PKT_ARESETN : signal is "Rst";
attribute SIGIS of S_AXI_MAC_REG_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_MAC_REG_ARESETN : signal is "Rst";
attribute SIGIS of S_AXI_PDI_AP_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_PDI_AP_ARESETN : signal is "Rst";
attribute SIGIS of S_AXI_PDI_PCP_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_PDI_PCP_ARESETN : signal is "Rst";
attribute SIGIS of S_AXI_SMP_PCP_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_SMP_PCP_ARESETN : signal is "Rst";
attribute SIGIS of clk100 : signal is "Clk";
attribute SIGIS of phy0_clk : signal is "Clk";
attribute SIGIS of phy1_clk : signal is "Clk";
end axi_powerlink;
architecture struct of axi_powerlink is
---- Architecture declarations -----
function get_max( a, b : integer) return integer is
begin
if a < b then
return b;
else
return a;
end if;
end get_max;
---- Component declarations -----
component clkXing
generic(
gCsNum : natural := 2;
gDataWidth : natural := 32
);
port (
iArst : in std_logic;
iFastClk : in std_logic;
iFastCs : in std_logic_vector(gCsNum-1 downto 0);
iFastRNW : in std_logic;
iSlowClk : in std_logic;
iSlowRdAck : in std_logic;
iSlowReaddata : in std_logic_vector(gDataWidth-1 downto 0);
iSlowWrAck : in std_logic;
oFastRdAck : out std_logic;
oFastReaddata : out std_logic_vector(gDataWidth-1 downto 0);
oFastWrAck : out std_logic;
oSlowCs : out std_logic_vector(gCsNum-1 downto 0);
oSlowRNW : out std_logic
);
end component;
component ipif_master_handler
generic(
C_MAC_DMA_IPIF_AWIDTH : integer := 32;
C_MAC_DMA_IPIF_NATIVE_DWIDTH : integer := 32;
dma_highadr_g : integer := 31;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4
);
port (
Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1';
Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0';
Bus2MAC_DMA_Mst_Error : in std_logic := '0';
Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0';
MAC_DMA_CLK : in std_logic;
MAC_DMA_Rst : in std_logic;
m_address : in std_logic_vector(dma_highadr_g downto 0);
m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : in std_logic_vector(3 downto 0);
m_read : in std_logic := '0';
m_write : in std_logic := '0';
m_writedata : in std_logic_vector(31 downto 0);
MAC_DMA2Bus_MstRd_Req : out std_logic := '0';
MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_Req : out std_logic := '0';
MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1';
MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_IPIF_AWIDTH-1 downto 0);
MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0);
MAC_DMA2Bus_Mst_Lock : out std_logic := '0';
MAC_DMA2Bus_Mst_Reset : out std_logic := '0';
MAC_DMA2Bus_Mst_Type : out std_logic := '0';
m_clk : out std_logic;
m_readdata : out std_logic_vector(31 downto 0);
m_readdatavalid : out std_logic := '0';
m_waitrequest : out std_logic := '1'
);
end component;
component openMAC_16to32conv
generic(
bus_address_width : integer := 10;
gEndian : string := "little"
);
port (
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_byteenable : in std_logic_vector(3 downto 0);
bus_read : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_writedata : in std_logic_vector(31 downto 0);
clk : in std_logic;
rst : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_waitrequest : in std_logic;
bus_ack_rd : out std_logic;
bus_ack_wr : out std_logic;
bus_readdata : out std_logic_vector(31 downto 0);
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_chipselect : out std_logic;
s_read : out std_logic;
s_write : out std_logic;
s_writedata : out std_logic_vector(15 downto 0)
);
end component;
component powerlink
generic(
Simulate : integer := 0;
endian_g : string := "little";
gNumSmi : integer range 1 to 2 := 2;
genABuf1_g : integer := 1;
genABuf2_g : integer := 1;
genEvent_g : integer := 0;
genInternalAp_g : integer := 1;
genIoBuf_g : integer := 1;
genLedGadget_g : integer := 0;
genOnePdiClkDomain_g : integer := 0;
genPdi_g : integer := 1;
genSimpleIO_g : integer := 0;
genSmiIO : integer := 1;
genSpiAp_g : integer := 0;
genTimeSync_g : integer := 0;
gen_dma_observer_g : integer := 1;
iAsyBuf1Size_g : integer := 100;
iAsyBuf2Size_g : integer := 100;
iBufSizeLOG2_g : integer := 10;
iBufSize_g : integer := 1024;
iPdiRev_g : integer := 21930;
iRpdo0BufSize_g : integer := 100;
iRpdo1BufSize_g : integer := 100;
iRpdo2BufSize_g : integer := 100;
iRpdos_g : integer := 3;
iTpdoBufSize_g : integer := 100;
iTpdos_g : integer := 1;
m_burstcount_const_g : integer := 1;
m_burstcount_width_g : integer := 4;
m_data_width_g : integer := 16;
m_rx_burst_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_tx_fifo_size_g : integer := 16;
papBigEnd_g : integer := 0;
papDataWidth_g : integer := 8;
papLowAct_g : integer := 0;
pcpSysId : integer := 1;
pioValLen_g : integer := 50;
spiBigEnd_g : integer := 0;
spiCPHA_g : integer := 0;
spiCPOL_g : integer := 0;
use2ndCmpTimer_g : integer := 1;
usePulse2ndCmpTimer_g : integer := 1;
pulseWidth2ndCmpTimer_g : integer := 9;
use2ndPhy_g : integer := 1;
useIntPacketBuf_g : integer := 1;
useRmii_g : integer := 1;
useRxIntPacketBuf_g : integer := 1
);
port (
ap_address : in std_logic_vector(12 downto 0);
ap_byteenable : in std_logic_vector(3 downto 0);
ap_chipselect : in std_logic;
ap_read : in std_logic;
ap_write : in std_logic;
ap_writedata : in std_logic_vector(31 downto 0);
clk50 : in std_logic;
clkAp : in std_logic;
clkEth : in std_logic;
clkPcp : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
m_readdatavalid : in std_logic := '0';
m_waitrequest : in std_logic;
mac_address : in std_logic_vector(11 downto 0);
mac_byteenable : in std_logic_vector(1 downto 0);
mac_chipselect : in std_logic;
mac_read : in std_logic;
mac_write : in std_logic;
mac_writedata : in std_logic_vector(15 downto 0);
mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0);
mbf_byteenable : in std_logic_vector(3 downto 0);
mbf_chipselect : in std_logic;
mbf_read : in std_logic;
mbf_write : in std_logic;
mbf_writedata : in std_logic_vector(31 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
pcp_address : in std_logic_vector(12 downto 0);
pcp_byteenable : in std_logic_vector(3 downto 0);
pcp_chipselect : in std_logic;
pcp_read : in std_logic;
pcp_write : in std_logic;
pcp_writedata : in std_logic_vector(31 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic := '1';
phy0_link : in std_logic := '0';
phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0');
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic := '1';
phy1_link : in std_logic := '0';
phyMii0_RxClk : in std_logic;
phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic := '1';
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0');
pkt_clk : in std_logic;
rst : in std_logic;
rstAp : in std_logic;
rstPcp : in std_logic;
smp_address : in std_logic;
smp_byteenable : in std_logic_vector(3 downto 0);
smp_read : in std_logic;
smp_write : in std_logic;
smp_writedata : in std_logic_vector(31 downto 0);
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
tcp_address : in std_logic_vector(1 downto 0);
tcp_byteenable : in std_logic_vector(3 downto 0);
tcp_chipselect : in std_logic;
tcp_read : in std_logic;
tcp_write : in std_logic;
tcp_writedata : in std_logic_vector(31 downto 0);
ap_asyncIrq : out std_logic := '0';
ap_asyncIrq_n : out std_logic := '1';
ap_irq : out std_logic := '0';
ap_irq_n : out std_logic := '1';
ap_readdata : out std_logic_vector(31 downto 0) := (others => '0');
ap_syncIrq : out std_logic := '0';
ap_syncIrq_n : out std_logic := '1';
ap_waitrequest : out std_logic;
led_error : out std_logic := '0';
led_gpo : out std_logic_vector(7 downto 0) := (others => '0');
led_opt : out std_logic_vector(1 downto 0) := (others => '0');
led_phyAct : out std_logic_vector(1 downto 0) := (others => '0');
led_phyLink : out std_logic_vector(1 downto 0) := (others => '0');
led_status : out std_logic := '0';
m_address : out std_logic_vector(31 downto 0) := (others => '0');
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0) := (others => '0');
m_read : out std_logic := '0';
m_write : out std_logic := '0';
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
mac_irq : out std_logic := '0';
mac_readdata : out std_logic_vector(15 downto 0) := (others => '0');
mac_waitrequest : out std_logic;
mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0');
mbf_waitrequest : out std_logic;
pap_ack : out std_logic := '0';
pap_ack_n : out std_logic := '1';
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
pcp_waitrequest : out std_logic;
phy0_Rst_n : out std_logic := '1';
phy0_SMIClk : out std_logic := '0';
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy0_TxEn : out std_logic := '0';
phy1_Rst_n : out std_logic := '1';
phy1_SMIClk : out std_logic := '0';
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy1_TxEn : out std_logic := '0';
phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii0_TxEn : out std_logic := '0';
phyMii0_TxEr : out std_logic := '0';
phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii1_TxEn : out std_logic := '0';
phyMii1_TxEr : out std_logic := '0';
phy_Rst_n : out std_logic := '1';
phy_SMIClk : out std_logic := '0';
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic := '0';
pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0');
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
smp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
smp_waitrequest : out std_logic;
spi_miso : out std_logic := '0';
tcp_irq : out std_logic := '0';
tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
tcp_waitrequest : out std_logic;
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0');
phy0_SMIDat : inout std_logic := '1';
phy1_SMIDat : inout std_logic := '1';
phy_SMIDat : inout std_logic := '1';
pio_portio : inout std_logic_vector(31 downto 0) := (others => '0')
);
end component;
component axi_lite_ipif
generic(
C_ARD_ADDR_RANGE_ARRAY : slv64_array_type := (X"0000_0000_7000_0000",X"0000_0000_7000_00FF",X"0000_0000_7000_0100",X"0000_0000_7000_01FF");
C_ARD_NUM_CE_ARRAY : integer_array_type := (4,12);
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_FAMILY : string := "virtex6";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) := X"000001FF";
C_USE_WSTRB : integer := 0
);
port (
IP2Bus_Data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
IP2Bus_Error : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_WrAck : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARESETN : in std_logic;
S_AXI_ARVALID : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
Bus2IP_Addr : out std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
Bus2IP_BE : out std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
Bus2IP_CS : out std_logic_vector((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
Bus2IP_Clk : out std_logic;
Bus2IP_Data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_RdCE : out std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
Bus2IP_Resetn : out std_logic;
Bus2IP_WrCE : out std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
S_AXI_ARREADY : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic
);
end component;
component axi_master_burst
generic(
C_ADDR_PIPE_DEPTH : integer range 1 to 14 := 1;
C_FAMILY : string := "virtex6";
C_LENGTH_WIDTH : integer range 12 to 20 := 12;
C_MAX_BURST_LEN : integer range 16 to 256 := 16;
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_DATA_WIDTH : integer range 32 to 256 := 32;
C_NATIVE_DATA_WIDTH : integer range 32 to 128 := 32
);
port (
ip2bus_mst_addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
ip2bus_mst_be : in std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);
ip2bus_mst_length : in std_logic_vector(C_LENGTH_WIDTH-1 downto 0);
ip2bus_mst_lock : in std_logic;
ip2bus_mst_reset : in std_logic;
ip2bus_mst_type : in std_logic;
ip2bus_mstrd_dst_dsc_n : in std_logic;
ip2bus_mstrd_dst_rdy_n : in std_logic;
ip2bus_mstrd_req : in std_logic;
ip2bus_mstwr_d : in std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
ip2bus_mstwr_eof_n : in std_logic;
ip2bus_mstwr_rem : in std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);
ip2bus_mstwr_req : in std_logic;
ip2bus_mstwr_sof_n : in std_logic;
ip2bus_mstwr_src_dsc_n : in std_logic;
ip2bus_mstwr_src_rdy_n : in std_logic;
m_axi_aclk : in std_logic;
m_axi_aresetn : in std_logic;
m_axi_arready : in std_logic;
m_axi_awready : in std_logic;
m_axi_bresp : in std_logic_vector(1 downto 0);
m_axi_bvalid : in std_logic;
m_axi_rdata : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
m_axi_rlast : in std_logic;
m_axi_rresp : in std_logic_vector(1 downto 0);
m_axi_rvalid : in std_logic;
m_axi_wready : in std_logic;
bus2ip_mst_cmd_timeout : out std_logic;
bus2ip_mst_cmdack : out std_logic;
bus2ip_mst_cmplt : out std_logic;
bus2ip_mst_error : out std_logic;
bus2ip_mst_rearbitrate : out std_logic;
bus2ip_mstrd_d : out std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
bus2ip_mstrd_eof_n : out std_logic;
bus2ip_mstrd_rem : out std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);
bus2ip_mstrd_sof_n : out std_logic;
bus2ip_mstrd_src_dsc_n : out std_logic;
bus2ip_mstrd_src_rdy_n : out std_logic;
bus2ip_mstwr_dst_dsc_n : out std_logic;
bus2ip_mstwr_dst_rdy_n : out std_logic;
m_axi_araddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
m_axi_arburst : out std_logic_vector(1 downto 0);
m_axi_arcache : out std_logic_vector(3 downto 0);
m_axi_arlen : out std_logic_vector(7 downto 0);
m_axi_arprot : out std_logic_vector(2 downto 0);
m_axi_arsize : out std_logic_vector(2 downto 0);
m_axi_arvalid : out std_logic;
m_axi_awaddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
m_axi_awburst : out std_logic_vector(1 downto 0);
m_axi_awcache : out std_logic_vector(3 downto 0);
m_axi_awlen : out std_logic_vector(7 downto 0);
m_axi_awprot : out std_logic_vector(2 downto 0);
m_axi_awsize : out std_logic_vector(2 downto 0);
m_axi_awvalid : out std_logic;
m_axi_bready : out std_logic;
m_axi_rready : out std_logic;
m_axi_wdata : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
m_axi_wlast : out std_logic;
m_axi_wstrb : out std_logic_vector((C_M_AXI_DATA_WIDTH/8)-1 downto 0);
m_axi_wvalid : out std_logic;
md_error : out std_logic
);
end component;
---- Architecture declarations -----
constant C_ADDR_PAD_ZERO : std_logic_vector(31 downto 0) := (others => '0');
-- openMAC REG PLB Slave
constant C_MAC_REG_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG0_BASEADDR;
constant C_MAC_REG_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG0_HIGHADDR;
constant C_MAC_REG_MINSIZE : std_logic_vector(31 downto 0) := conv_std_logic_vector(get_max(conv_integer(C_S_AXI_MAC_REG_RNG0_HIGHADDR), conv_integer(C_S_AXI_MAC_REG_RNG1_HIGHADDR)), 32);
-- openMAC CMP PLB Slave
constant C_MAC_CMP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG1_BASEADDR;
constant C_MAC_CMP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG1_HIGHADDR;
-- openMAC PKT PLB Slave
constant C_MAC_PKT_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_PKT_BASEADDR;
constant C_MAC_PKT_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_PKT_HIGHADDR;
constant C_MAC_PKT_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_MAC_PKT_HIGHADDR;
-- SimpleIO Slave
constant C_SMP_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_SMP_PCP_BASEADDR;
constant C_SMP_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_SMP_PCP_HIGHADDR;
constant C_SMP_PCP_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_SMP_PCP_HIGHADDR;
-- PDI PCP Slave
constant C_PDI_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_PCP_BASEADDR;
constant C_PDI_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_PCP_HIGHADDR;
constant C_PDI_PCP_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_PDI_PCP_HIGHADDR;
-- AP PCP Slave
constant C_PDI_AP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_AP_BASEADDR;
constant C_PDI_AP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_AP_HIGHADDR;
constant C_PDI_AP_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_PDI_AP_HIGHADDR;
-- POWERLINK IP-core
constant C_MAC_PKT_EN : boolean := C_TX_INT_PKT or C_RX_INT_PKT;
constant C_MAC_PKT_RX_EN : boolean := C_RX_INT_PKT;
constant C_DMA_EN : boolean := not C_TX_INT_PKT or not C_RX_INT_PKT;
constant C_PKT_BUF_EN : boolean := C_MAC_PKT_EN;
constant C_M_BURSTCOUNT_WIDTH : integer := integer(ceil(log2(real(get_max(C_MAC_DMA_BURST_SIZE_RX,C_MAC_DMA_BURST_SIZE_TX)/4)))) + 1; --in dwords
constant C_M_FIFO_SIZE_RX : integer := C_MAC_DMA_FIFO_SIZE_RX/4; --in dwords
constant C_M_FIFO_SIZE_TX : integer := C_MAC_DMA_FIFO_SIZE_TX/4; --in dwords
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
constant GND_CONSTANT : std_logic := '0';
---- Signal declarations used on the diagram ----
signal ap_chipselect : std_logic;
signal ap_read : std_logic;
signal ap_waitrequest : std_logic;
signal ap_write : std_logic;
signal bus2MAC_DMA_mstrd_eof_n : std_logic;
signal bus2MAC_DMA_mstrd_sof_n : std_logic;
signal bus2MAC_DMA_mstrd_src_dsc_n : std_logic;
signal bus2MAC_DMA_mstrd_src_rdy_n : std_logic;
signal bus2MAC_DMA_mstwr_dst_dsc_n : std_logic;
signal bus2MAC_DMA_mstwr_dst_rdy_n : std_logic;
signal bus2MAC_DMA_mst_cmdack : std_logic;
signal bus2MAC_DMA_mst_cmd_timeout : std_logic;
signal bus2MAC_DMA_mst_cmplt : std_logic;
signal bus2MAC_DMA_mst_error : std_logic;
signal bus2MAC_DMA_mst_rearbitrate : std_logic;
signal Bus2MAC_PKT_Clk : std_logic;
signal Bus2MAC_PKT_Reset : std_logic := '0';
signal Bus2MAC_PKT_Resetn : std_logic;
signal Bus2MAC_PKT_RNW : std_logic;
signal Bus2MAC_REG_Clk : std_logic;
signal Bus2MAC_REG_Reset : std_logic := '0';
signal Bus2MAC_REG_Resetn : std_logic;
signal Bus2MAC_REG_RNW : std_logic;
signal Bus2MAC_REG_RNW_fast : std_logic;
signal Bus2MAC_REG_RNW_n : std_logic;
signal Bus2PDI_AP_Clk : std_logic;
signal Bus2PDI_AP_Reset : std_logic := '0';
signal Bus2PDI_AP_Resetn : std_logic;
signal Bus2PDI_AP_RNW : std_logic;
signal Bus2PDI_PCP_Clk : std_logic;
signal Bus2PDI_PCP_Reset : std_logic := '0';
signal Bus2PDI_PCP_Resetn : std_logic;
signal Bus2PDI_PCP_RNW : std_logic;
signal Bus2SMP_PCP_Clk : std_logic;
signal Bus2SMP_PCP_Reset : std_logic := '0';
signal Bus2SMP_PCP_Resetn : std_logic;
signal Bus2SMP_PCP_RNW : std_logic;
signal clkAp : std_logic;
signal clkPcp : std_logic;
signal GND : std_logic;
signal IP2Bus_Error_s : std_logic;
signal IP2Bus_RdAck_fast : std_logic;
signal IP2Bus_RdAck_s : std_logic;
signal IP2Bus_WrAck_fast : std_logic;
signal IP2Bus_WrAck_s : std_logic;
signal mac_chipselect : std_logic;
signal MAC_CMP2Bus_Error : std_logic;
signal MAC_CMP2Bus_RdAck : std_logic;
signal MAC_CMP2Bus_WrAck : std_logic;
signal MAC_DMA2bus_mstrd_dst_dsc_n : std_logic;
signal MAC_DMA2bus_mstrd_dst_rdy_n : std_logic;
signal MAC_DMA2bus_mstrd_req : std_logic;
signal MAC_DMA2bus_mstwr_eof_n : std_logic;
signal MAC_DMA2bus_mstwr_req : std_logic;
signal MAC_DMA2bus_mstwr_sof_n : std_logic;
signal MAC_DMA2bus_mstwr_src_dsc_n : std_logic;
signal MAC_DMA2bus_mstwr_src_rdy_n : std_logic;
signal MAC_DMA2bus_mst_lock : std_logic;
signal MAC_DMA2bus_mst_reset : std_logic;
signal MAC_DMA2bus_mst_type : std_logic;
signal MAC_DMA_areset : std_logic;
signal mac_irq_s : std_logic;
signal MAC_PKT2Bus_Error : std_logic;
signal MAC_PKT2Bus_RdAck : std_logic;
signal MAC_PKT2Bus_WrAck : std_logic;
signal mac_read : std_logic;
signal MAC_REG2Bus_Error : std_logic;
signal MAC_REG2Bus_RdAck : std_logic;
signal MAC_REG2Bus_WrAck : std_logic;
signal mac_waitrequest : std_logic;
signal mac_write : std_logic;
signal mbf_chipselect : std_logic;
signal mbf_read : std_logic;
signal mbf_waitrequest : std_logic;
signal mbf_write : std_logic;
signal m_clk : std_logic;
signal m_read : std_logic;
signal m_readdatavalid : std_logic;
signal m_waitrequest : std_logic;
signal m_write : std_logic;
signal NET38418 : std_ulogic;
signal NET38470 : std_ulogic;
signal pcp_chipselect : std_logic;
signal pcp_read : std_logic;
signal pcp_waitrequest : std_logic;
signal pcp_write : std_logic;
signal PDI_AP2Bus_Error : std_logic;
signal PDI_AP2Bus_RdAck : std_logic;
signal PDI_AP2Bus_WrAck : std_logic;
signal PDI_PCP2Bus_Error : std_logic;
signal PDI_PCP2Bus_RdAck : std_logic;
signal PDI_PCP2Bus_WrAck : std_logic;
signal pkt_clk : std_logic;
signal rst : std_logic := '0';
signal rstAp : std_logic := '0';
signal rstPcp : std_logic := '0';
signal smp_address : std_logic;
signal smp_chipselect : std_logic;
signal SMP_PCP2Bus_Error : std_logic;
signal SMP_PCP2Bus_RdAck : std_logic;
signal SMP_PCP2Bus_WrAck : std_logic;
signal smp_read : std_logic;
signal smp_waitrequest : std_logic;
signal smp_write : std_logic;
signal tcp_chipselect : std_logic;
signal tcp_irq_s : std_logic;
signal tcp_read : std_logic;
signal tcp_waitrequest : std_logic;
signal tcp_write : std_logic;
signal VCC : std_logic;
signal ap_address : std_logic_vector (12 downto 0);
signal ap_byteenable : std_logic_vector (3 downto 0);
signal ap_readdata : std_logic_vector (31 downto 0);
signal ap_writedata : std_logic_vector (31 downto 0);
signal bus2MAC_DMA_mstrd_d : std_logic_vector (C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0);
signal bus2MAC_DMA_mstrd_rem : std_logic_vector ((C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0);
signal Bus2MAC_PKT_Addr : std_logic_vector (C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
signal Bus2MAC_PKT_BE : std_logic_vector ((C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0);
signal Bus2MAC_PKT_CS : std_logic_vector (0 downto 0);
signal Bus2MAC_PKT_Data : std_logic_vector (C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
signal Bus2MAC_REG_Addr : std_logic_vector (C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
signal Bus2MAC_REG_BE : std_logic_vector ((C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0);
signal Bus2MAC_REG_CS : std_logic_vector (1 downto 0);
signal Bus2MAC_REG_CS_fast : std_logic_vector (1 downto 0);
signal Bus2MAC_REG_Data : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
signal Bus2PDI_AP_Addr : std_logic_vector (C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0);
signal Bus2PDI_AP_BE : std_logic_vector ((C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0);
signal Bus2PDI_AP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_AP_Data : std_logic_vector (C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0);
signal Bus2PDI_PCP_Addr : std_logic_vector (C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0);
signal Bus2PDI_PCP_BE : std_logic_vector ((C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0);
signal Bus2PDI_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_PCP_Data : std_logic_vector (C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0);
signal Bus2SMP_PCP_Addr : std_logic_vector (C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0);
signal Bus2SMP_PCP_BE : std_logic_vector ((C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0);
signal Bus2SMP_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2SMP_PCP_Data : std_logic_vector (C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0);
signal IP2Bus_Data_fast : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
signal IP2Bus_Data_s : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
signal mac_address : std_logic_vector (11 downto 0);
signal mac_address_full : std_logic_vector (C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
signal mac_byteenable : std_logic_vector (1 downto 0);
signal MAC_CMP2Bus_Data : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_d : std_logic_vector (C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0);
signal MAC_DMA2bus_mstwr_rem : std_logic_vector ((C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0);
signal MAC_DMA2bus_mst_addr : std_logic_vector (C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
signal MAC_DMA2bus_mst_be : std_logic_vector ((C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0);
signal MAC_DMA2bus_mst_length : std_logic_vector (C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0);
signal MAC_PKT2Bus_Data : std_logic_vector (C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
signal mac_readdata : std_logic_vector (15 downto 0);
signal MAC_REG2Bus_Data : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
signal mac_writedata : std_logic_vector (15 downto 0);
signal mbf_address : std_logic_vector (C_MAC_PKT_SIZE_LOG2-3 downto 0);
signal mbf_byteenable : std_logic_vector (3 downto 0);
signal mbf_readdata : std_logic_vector (31 downto 0);
signal mbf_writedata : std_logic_vector (31 downto 0);
signal m_address : std_logic_vector (31 downto 0);
signal m_burstcount : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_burstcounter : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_byteenable : std_logic_vector (3 downto 0);
signal m_readdata : std_logic_vector (31 downto 0);
signal m_writedata : std_logic_vector (31 downto 0);
signal pcp_address : std_logic_vector (12 downto 0);
signal pcp_byteenable : std_logic_vector (3 downto 0);
signal pcp_readdata : std_logic_vector (31 downto 0);
signal pcp_writedata : std_logic_vector (31 downto 0);
signal PDI_AP2Bus_Data : std_logic_vector (C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0);
signal PDI_PCP2Bus_Data : std_logic_vector (C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0);
signal smp_byteenable : std_logic_vector (3 downto 0);
signal SMP_PCP2Bus_Data : std_logic_vector (C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0);
signal smp_readdata : std_logic_vector (31 downto 0);
signal smp_writedata : std_logic_vector (31 downto 0);
signal tcp_address : std_logic_vector (1 downto 0);
signal tcp_byteenable : std_logic_vector (3 downto 0);
signal tcp_readdata : std_logic_vector (31 downto 0);
signal tcp_writedata : std_logic_vector (31 downto 0);
begin
---- User Signal Assignments ----
-- connect mac reg with mac cmp or reg output signals
with Bus2MAC_REG_CS select
IP2Bus_Data_s <= MAC_CMP2Bus_Data when "01",
MAC_REG2Bus_Data when others; --"10" and others are decoded to MAC_REG
IP2Bus_WrAck_s <= MAC_REG2Bus_WrAck or MAC_CMP2Bus_WrAck;
IP2Bus_RdAck_s <= MAC_REG2Bus_RdAck or MAC_CMP2Bus_RdAck;
IP2Bus_Error_s <= MAC_REG2Bus_Error or MAC_CMP2Bus_Error;
mac_address <= mac_address_full(mac_address'range);
--mac_cmp assignments
---cmp_clk <= Bus2MAC_CMP_Clk;
tcp_writedata <= Bus2MAC_REG_Data;
tcp_read <= Bus2MAC_REG_RNW;
tcp_write <= not Bus2MAC_REG_RNW;
tcp_chipselect <= Bus2MAC_REG_CS(0);
tcp_byteenable <= Bus2MAC_REG_BE;
tcp_address <= Bus2MAC_REG_Addr(3 downto 2);
MAC_CMP2Bus_Data <= tcp_readdata;
MAC_CMP2Bus_RdAck <= tcp_chipselect and tcp_read and not tcp_waitrequest;
MAC_CMP2Bus_WrAck <= tcp_chipselect and tcp_write and not tcp_waitrequest;
MAC_CMP2Bus_Error <= '0';
--mac_pkt assignments
pkt_clk <= Bus2MAC_PKT_Clk;
Bus2MAC_PKT_Reset <= not Bus2MAC_PKT_Resetn;
mbf_writedata <= Bus2MAC_PKT_Data;
-- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
-- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
mbf_read <= Bus2MAC_PKT_RNW;
mbf_write <= not Bus2MAC_PKT_RNW;
mbf_chipselect <= Bus2MAC_PKT_CS(0);
mbf_byteenable <= Bus2MAC_PKT_BE;
mbf_address <= Bus2MAC_PKT_Addr(C_MAC_PKT_SIZE_LOG2-1 downto 2);
MAC_PKT2Bus_Data <= mbf_readdata;
MAC_PKT2Bus_RdAck <= mbf_chipselect and mbf_read and not mbf_waitrequest;
MAC_PKT2Bus_WrAck <= mbf_chipselect and mbf_write and not mbf_waitrequest;
MAC_PKT2Bus_Error <= '0';
--test_port
--test_port(181 downto 179) <= mac_chipselect & mac_write & mac_read;
--test_port(178) <= mac_waitrequest;
--test_port(177 downto 176) <= mac_byteenable;
--
--test_port(171 downto 160) <= mac_address;
--test_port(159 downto 144) <= mac_writedata;
--test_port(143 downto 128) <= mac_readdata;
--
--test_port(104 downto 102) <= Bus2MAC_REG_CS & Bus2MAC_REG_RNW;
--test_port(101 downto 100) <= IP2Bus_WrAck_s & IP2Bus_RdAck_s;
--test_port(99 downto 96) <= Bus2MAC_REG_BE;
--
--test_port(95 downto 64) <= Bus2MAC_REG_Addr;
--test_port(63 downto 32) <= Bus2MAC_REG_Data;
--test_port(31 downto 0) <= IP2Bus_Data_s;
test_port(255 downto 251) <= m_read & m_write & m_waitrequest & m_readdatavalid & MAC_DMA2Bus_Mst_Type;
test_port(244 downto 240) <= MAC_DMA2Bus_MstWr_Req & MAC_DMA2Bus_MstWr_sof_n & MAC_DMA2Bus_MstWr_eof_n & MAC_DMA2Bus_MstWr_src_rdy_n & Bus2MAC_DMA_MstWr_dst_rdy_n;
test_port(234 downto 230) <= MAC_DMA2Bus_MstRd_Req & Bus2MAC_DMA_MstRd_sof_n & Bus2MAC_DMA_MstRd_eof_n & Bus2MAC_DMA_MstRd_src_rdy_n & MAC_DMA2Bus_MstRd_dst_rdy_n;
test_port(142 downto 140) <= Bus2MAC_DMA_Mst_Cmplt & Bus2MAC_DMA_Mst_Error & Bus2MAC_DMA_Mst_Cmd_Timeout;
test_port(MAC_DMA2Bus_Mst_Length'length+120-1 downto 120) <= MAC_DMA2Bus_Mst_Length;
test_port(m_burstcount'length+110-1 downto 110) <= m_burstcount;
test_port(m_burstcounter'length+96-1 downto 96) <= m_burstcounter;
test_port(95 downto 64) <= m_address;
test_port(63 downto 32) <= m_writedata;
test_port(31 downto 0) <= m_readdata;
---- Component instantiations ----
MAC_REG_16to32 : openMAC_16to32conv
generic map (
bus_address_width => C_S_AXI_MAC_REG_ADDR_WIDTH,
gEndian => "little"
)
port map(
bus_ack_rd => MAC_REG2Bus_RdAck,
bus_ack_wr => MAC_REG2Bus_WrAck,
bus_address => Bus2MAC_REG_Addr( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ),
bus_byteenable => Bus2MAC_REG_BE( (C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0 ),
bus_read => Bus2MAC_REG_RNW,
bus_readdata => MAC_REG2Bus_Data( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
bus_select => Bus2MAC_REG_CS(1),
bus_write => Bus2MAC_REG_RNW_n,
bus_writedata => Bus2MAC_REG_Data( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
clk => clk50,
rst => Bus2MAC_REG_Reset,
s_address => mac_address_full( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ),
s_byteenable => mac_byteenable,
s_chipselect => mac_chipselect,
s_read => mac_read,
s_readdata => mac_readdata,
s_waitrequest => mac_waitrequest,
s_write => mac_write,
s_writedata => mac_writedata
);
MAC_REG_AXI_SINGLE_SLAVE : axi_lite_ipif
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_REG_BASE,C_MAC_REG_HIGH,C_MAC_CMP_BASE,C_MAC_CMP_HIGH),
C_ARD_NUM_CE_ARRAY => (1,1),
C_DPHASE_TIMEOUT => C_S_AXI_MAC_REG_DPHASE_TIMEOUT,
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_REG_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_REG_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_MAC_REG_MINSIZE,
C_USE_WSTRB => C_S_AXI_MAC_REG_USE_WSTRB
)
port map(
Bus2IP_Addr => Bus2MAC_REG_Addr( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_REG_BE( (C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_REG_CS_fast( 1 downto 0 ),
Bus2IP_Clk => Bus2MAC_REG_Clk,
Bus2IP_Data => Bus2MAC_REG_Data( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_REG_RNW_fast,
Bus2IP_RdCE => open,
Bus2IP_Resetn => Bus2MAC_REG_Resetn,
Bus2IP_WrCE => open,
IP2Bus_Data => IP2Bus_Data_fast( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
IP2Bus_Error => IP2Bus_Error_s,
IP2Bus_RdAck => IP2Bus_RdAck_fast,
IP2Bus_WrAck => IP2Bus_WrAck_fast,
S_AXI_ACLK => S_AXI_MAC_REG_ACLK,
S_AXI_ARADDR => S_AXI_MAC_REG_ARADDR( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ),
S_AXI_ARESETN => S_AXI_MAC_REG_ARESETN,
S_AXI_ARREADY => S_AXI_MAC_REG_ARREADY,
S_AXI_ARVALID => S_AXI_MAC_REG_ARVALID,
S_AXI_AWADDR => S_AXI_MAC_REG_AWADDR( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ),
S_AXI_AWREADY => S_AXI_MAC_REG_AWREADY,
S_AXI_AWVALID => S_AXI_MAC_REG_AWVALID,
S_AXI_BREADY => S_AXI_MAC_REG_BREADY,
S_AXI_BRESP => S_AXI_MAC_REG_BRESP,
S_AXI_BVALID => S_AXI_MAC_REG_BVALID,
S_AXI_RDATA => S_AXI_MAC_REG_RDATA( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
S_AXI_RREADY => S_AXI_MAC_REG_RREADY,
S_AXI_RRESP => S_AXI_MAC_REG_RRESP,
S_AXI_RVALID => S_AXI_MAC_REG_RVALID,
S_AXI_WDATA => S_AXI_MAC_REG_WDATA( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
S_AXI_WREADY => S_AXI_MAC_REG_WREADY,
S_AXI_WSTRB => S_AXI_MAC_REG_WSTRB( (C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0 ),
S_AXI_WVALID => S_AXI_MAC_REG_WVALID
);
THE_POWERLINK_IP_CORE : powerlink
generic map (
Simulate => booleanToInteger(false),
endian_g => "little",
gNumSmi => C_NUM_SMI,
genABuf1_g => booleanToInteger(C_PDI_GEN_ASYNC_BUF_0),
genABuf2_g => booleanToInteger(C_PDI_GEN_ASYNC_BUF_1),
genEvent_g => booleanToInteger(C_PDI_GEN_EVENT),
genInternalAp_g => booleanToInteger(C_GEN_AXI_BUS_IF),
genIoBuf_g => booleanToInteger(false),
genLedGadget_g => booleanToInteger(C_PDI_GEN_LED),
genOnePdiClkDomain_g => booleanToInteger(false),
genPdi_g => booleanToInteger(C_GEN_PDI),
genSimpleIO_g => booleanToInteger(C_GEN_SIMPLE_IO),
genSmiIO => booleanToInteger(false),
genSpiAp_g => booleanToInteger(C_GEN_SPI_IF),
genTimeSync_g => booleanToInteger(C_PDI_GEN_TIME_SYNC),
gen_dma_observer_g => booleanToInteger(C_OBSERVER_ENABLE),
iAsyBuf1Size_g => C_PDI_ASYNC_BUF_0,
iAsyBuf2Size_g => C_PDI_ASYNC_BUF_1,
iBufSizeLOG2_g => C_MAC_PKT_SIZE_LOG2,
iBufSize_g => C_MAC_PKT_SIZE,
iPdiRev_g => C_PDI_REV,
iRpdo0BufSize_g => C_RPDO_0_BUF_SIZE,
iRpdo1BufSize_g => C_RPDO_1_BUF_SIZE,
iRpdo2BufSize_g => C_RPDO_2_BUF_SIZE,
iRpdos_g => C_NUM_RPDO,
iTpdoBufSize_g => C_TPDO_BUF_SIZE,
iTpdos_g => C_NUM_TPDO,
m_burstcount_const_g => booleanToInteger(true),
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH,
m_data_width_g => 32,
m_rx_burst_size_g => C_MAC_DMA_BURST_SIZE_RX/4,
m_rx_fifo_size_g => C_M_FIFO_SIZE_RX,
m_tx_burst_size_g => C_MAC_DMA_BURST_SIZE_TX/4,
m_tx_fifo_size_g => C_M_FIFO_SIZE_TX,
papBigEnd_g => booleanToInteger(false),
papDataWidth_g => C_PAP_DATA_WIDTH,
papLowAct_g => booleanToInteger(C_PAP_LOW_ACT),
pcpSysId => C_PCP_SYS_ID,
pioValLen_g => C_PIO_VAL_LENGTH,
pulseWidth2ndCmpTimer_g => C_PULSE_WIDTH_2nd_CMP_TIMER,
spiBigEnd_g => booleanToInteger(false),
spiCPHA_g => booleanToInteger(C_SPI_CPHA),
spiCPOL_g => booleanToInteger(C_SPI_CPOL),
use2ndCmpTimer_g => booleanToInteger(C_MAC_GEN_SECOND_TIMER),
use2ndPhy_g => booleanToInteger(C_USE_2ND_PHY),
useIntPacketBuf_g => booleanToInteger(C_MAC_PKT_EN),
usePulse2ndCmpTimer_g => booleanToInteger(C_USE_PULSE_2nd_CMP_TIMER),
useRmii_g => booleanToInteger(C_USE_RMII),
useRxIntPacketBuf_g => booleanToInteger(C_MAC_PKT_RX_EN)
)
port map(
ap_address => ap_address,
ap_asyncIrq => ap_asyncIrq,
ap_asyncIrq_n => ap_asyncIrq_n,
ap_byteenable => ap_byteenable,
ap_chipselect => ap_chipselect,
ap_irq => open,
ap_irq_n => open,
ap_read => ap_read,
ap_readdata => ap_readdata,
ap_syncIrq => ap_syncIrq,
ap_syncIrq_n => ap_syncIrq_n,
ap_waitrequest => ap_waitrequest,
ap_write => ap_write,
ap_writedata => ap_writedata,
clk50 => clk50,
clkAp => clkAp,
clkEth => clk100,
clkPcp => clkPcp,
led_error => led_error,
led_gpo => led_gpo,
led_opt => led_opt,
led_phyAct => led_phyAct,
led_phyLink => led_phyLink,
led_status => led_status,
m_address => m_address,
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable( 3 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( 31 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( 31 downto 0 ),
mac_address => mac_address,
mac_byteenable => mac_byteenable,
mac_chipselect => mac_chipselect,
mac_irq => mac_irq_s,
mac_read => mac_read,
mac_readdata => mac_readdata,
mac_waitrequest => mac_waitrequest,
mac_write => mac_write,
mac_writedata => mac_writedata,
mbf_address => mbf_address( C_MAC_PKT_SIZE_LOG2-3 downto 0 ),
mbf_byteenable => mbf_byteenable,
mbf_chipselect => mbf_chipselect,
mbf_read => mbf_read,
mbf_readdata => mbf_readdata,
mbf_waitrequest => mbf_waitrequest,
mbf_write => mbf_write,
mbf_writedata => mbf_writedata,
pap_ack => pap_ack,
pap_ack_n => pap_ack_n,
pap_addr => pap_addr,
pap_be => pap_be( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_be_n => pap_be_n( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_cs => pap_cs,
pap_cs_n => pap_cs_n,
pap_data => open,
pap_data_I => pap_data_I( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_O => pap_data_O( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_T => pap_data_T,
pap_gpio => open,
pap_gpio_I => pap_gpio_I,
pap_gpio_O => pap_gpio_O,
pap_gpio_T => pap_gpio_T,
pap_rd => pap_rd,
pap_rd_n => pap_rd_n,
pap_wr => pap_wr,
pap_wr_n => pap_wr_n,
pcp_address => pcp_address,
pcp_byteenable => pcp_byteenable,
pcp_chipselect => pcp_chipselect,
pcp_read => pcp_read,
pcp_readdata => pcp_readdata,
pcp_waitrequest => pcp_waitrequest,
pcp_write => pcp_write,
pcp_writedata => pcp_writedata,
phy0_Rst_n => phy0_Rst_n,
phy0_RxDat => phy0_RxDat,
phy0_RxDv => phy0_RxDv,
phy0_RxErr => phy0_RxErr,
phy0_SMIClk => phy0_SMIClk,
phy0_SMIDat => open,
phy0_SMIDat_I => phy0_SMIDat_I,
phy0_SMIDat_O => phy0_SMIDat_O,
phy0_SMIDat_T => phy0_SMIDat_T,
phy0_TxDat => phy0_TxDat,
phy0_TxEn => phy0_TxEn,
phy0_link => phy0_link,
phy1_Rst_n => phy1_Rst_n,
phy1_RxDat => phy1_RxDat,
phy1_RxDv => phy1_RxDv,
phy1_RxErr => phy1_RxErr,
phy1_SMIClk => phy1_SMIClk,
phy1_SMIDat => open,
phy1_SMIDat_I => phy1_SMIDat_I,
phy1_SMIDat_O => phy1_SMIDat_O,
phy1_SMIDat_T => phy1_SMIDat_T,
phy1_TxDat => phy1_TxDat,
phy1_TxEn => phy1_TxEn,
phy1_link => phy1_link,
phyMii0_RxClk => phyMii0_RxClk,
phyMii0_RxDat => phyMii0_RxDat,
phyMii0_RxDv => phyMii0_RxDv,
phyMii0_RxEr => phyMii0_RxEr,
phyMii0_TxClk => phyMii0_TxClk,
phyMii0_TxDat => phyMii0_TxDat,
phyMii0_TxEn => phyMii0_TxEn,
phyMii0_TxEr => phyMii0_TxEr,
phyMii1_RxClk => phyMii1_RxClk,
phyMii1_RxDat => phyMii1_RxDat,
phyMii1_RxDv => phyMii1_RxDv,
phyMii1_RxEr => phyMii1_RxEr,
phyMii1_TxClk => phyMii1_TxClk,
phyMii1_TxDat => phyMii1_TxDat,
phyMii1_TxEn => phyMii1_TxEn,
phyMii1_TxEr => phyMii1_TxEr,
phy_Rst_n => phy_Rst_n,
phy_SMIClk => phy_SMIClk,
phy_SMIDat => open,
phy_SMIDat_I => phy_SMIDat_I,
phy_SMIDat_O => phy_SMIDat_O,
phy_SMIDat_T => phy_SMIDat_T,
pio_operational => pio_operational,
pio_pconfig => pio_pconfig,
pio_portInLatch => pio_portInLatch,
pio_portOutValid => pio_portOutValid,
pio_portio => open,
pio_portio_I => pio_portio_I,
pio_portio_O => pio_portio_O,
pio_portio_T => pio_portio_T,
pkt_clk => pkt_clk,
rst => rst,
rstAp => rstAp,
rstPcp => rstPcp,
smp_address => smp_address,
smp_byteenable => smp_byteenable,
smp_read => smp_read,
smp_readdata => smp_readdata,
smp_waitrequest => smp_waitrequest,
smp_write => smp_write,
smp_writedata => smp_writedata,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
spi_sel_n => spi_sel_n,
tcp_address => tcp_address,
tcp_byteenable => tcp_byteenable,
tcp_chipselect => tcp_chipselect,
tcp_irq => tcp_irq_s,
tcp_read => tcp_read,
tcp_readdata => tcp_readdata,
tcp_waitrequest => tcp_waitrequest,
tcp_write => tcp_write,
tcp_writedata => tcp_writedata
);
MAC_DMA_areset <= not(M_AXI_MAC_DMA_aresetn);
Bus2MAC_REG_RNW_n <= not(Bus2MAC_REG_RNW);
Bus2MAC_REG_Reset <= not(Bus2MAC_REG_Resetn);
rstPcp <= Bus2SMP_PCP_Reset or Bus2PDI_PCP_Reset or Bus2MAC_PKT_Reset;
rstAp <= Bus2PDI_AP_Reset;
rst <= Bus2MAC_REG_Reset;
macRegClkXing : clkXing
generic map (
gCsNum => 2,
gDataWidth => C_S_AXI_MAC_REG_DATA_WIDTH
)
port map(
iArst => Bus2MAC_REG_Reset,
iFastClk => Bus2MAC_REG_Clk,
iFastCs => Bus2MAC_REG_CS_fast( 1 downto 0 ),
iFastRNW => Bus2MAC_REG_RNW_fast,
iSlowClk => clk50,
iSlowRdAck => IP2Bus_RdAck_s,
iSlowReaddata => IP2Bus_Data_s( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
iSlowWrAck => IP2Bus_WrAck_s,
oFastRdAck => IP2Bus_RdAck_fast,
oFastReaddata => IP2Bus_Data_fast( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
oFastWrAck => IP2Bus_WrAck_fast,
oSlowCs => Bus2MAC_REG_CS( 1 downto 0 ),
oSlowRNW => Bus2MAC_REG_RNW
);
---- Power , ground assignment ----
GND <= GND_CONSTANT;
VCC <= VCC_CONSTANT;
MAC_REG2Bus_Error <= GND;
---- Terminal assignment ----
-- Output\buffer terminals
mac_irq <= mac_irq_s;
tcp_irq <= tcp_irq_s;
---- Generate statements ----
genMacDmaPlbBurst : if C_DMA_EN = TRUE generate
begin
MAC_DMA_AXI_BURST_MASTER : axi_master_burst
generic map (
C_ADDR_PIPE_DEPTH => 1,
C_FAMILY => C_FAMILY,
C_LENGTH_WIDTH => C_M_AXI_MAC_DMA_LENGTH_WIDTH,
C_MAX_BURST_LEN => C_M_AXI_MAC_DMA_MAX_BURST_LEN,
C_M_AXI_ADDR_WIDTH => C_M_AXI_MAC_DMA_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_MAC_DMA_DATA_WIDTH,
C_NATIVE_DATA_WIDTH => C_M_AXI_MAC_DMA_NATIVE_DWIDTH
)
port map(
bus2ip_mst_cmd_timeout => bus2MAC_DMA_mst_cmd_timeout,
bus2ip_mst_cmdack => bus2MAC_DMA_mst_cmdack,
bus2ip_mst_cmplt => bus2MAC_DMA_mst_cmplt,
bus2ip_mst_error => bus2MAC_DMA_mst_error,
bus2ip_mst_rearbitrate => bus2MAC_DMA_mst_rearbitrate,
bus2ip_mstrd_d => bus2MAC_DMA_mstrd_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ),
bus2ip_mstrd_eof_n => bus2MAC_DMA_mstrd_eof_n,
bus2ip_mstrd_rem => bus2MAC_DMA_mstrd_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
bus2ip_mstrd_sof_n => bus2MAC_DMA_mstrd_sof_n,
bus2ip_mstrd_src_dsc_n => bus2MAC_DMA_mstrd_src_dsc_n,
bus2ip_mstrd_src_rdy_n => bus2MAC_DMA_mstrd_src_rdy_n,
bus2ip_mstwr_dst_dsc_n => bus2MAC_DMA_mstwr_dst_dsc_n,
bus2ip_mstwr_dst_rdy_n => bus2MAC_DMA_mstwr_dst_rdy_n,
ip2bus_mst_addr => MAC_DMA2bus_mst_addr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ),
ip2bus_mst_be => MAC_DMA2bus_mst_be( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
ip2bus_mst_length => MAC_DMA2bus_mst_length( C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0 ),
ip2bus_mst_lock => MAC_DMA2bus_mst_lock,
ip2bus_mst_reset => MAC_DMA2bus_mst_reset,
ip2bus_mst_type => MAC_DMA2bus_mst_type,
ip2bus_mstrd_dst_dsc_n => MAC_DMA2bus_mstrd_dst_dsc_n,
ip2bus_mstrd_dst_rdy_n => MAC_DMA2bus_mstrd_dst_rdy_n,
ip2bus_mstrd_req => MAC_DMA2bus_mstrd_req,
ip2bus_mstwr_d => MAC_DMA2bus_mstwr_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ),
ip2bus_mstwr_eof_n => MAC_DMA2bus_mstwr_eof_n,
ip2bus_mstwr_rem => MAC_DMA2bus_mstwr_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
ip2bus_mstwr_req => MAC_DMA2bus_mstwr_req,
ip2bus_mstwr_sof_n => MAC_DMA2bus_mstwr_sof_n,
ip2bus_mstwr_src_dsc_n => MAC_DMA2bus_mstwr_src_dsc_n,
ip2bus_mstwr_src_rdy_n => MAC_DMA2bus_mstwr_src_rdy_n,
m_axi_aclk => M_AXI_MAC_DMA_aclk,
m_axi_araddr => M_AXI_MAC_DMA_araddr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ),
m_axi_arburst => M_AXI_MAC_DMA_arburst,
m_axi_arcache => M_AXI_MAC_DMA_arcache,
m_axi_aresetn => M_AXI_MAC_DMA_aresetn,
m_axi_arlen => M_AXI_MAC_DMA_arlen,
m_axi_arprot => M_AXI_MAC_DMA_arprot,
m_axi_arready => M_AXI_MAC_DMA_arready,
m_axi_arsize => M_AXI_MAC_DMA_arsize,
m_axi_arvalid => M_AXI_MAC_DMA_arvalid,
m_axi_awaddr => M_AXI_MAC_DMA_awaddr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ),
m_axi_awburst => M_AXI_MAC_DMA_awburst,
m_axi_awcache => M_AXI_MAC_DMA_awcache,
m_axi_awlen => M_AXI_MAC_DMA_awlen,
m_axi_awprot => M_AXI_MAC_DMA_awprot,
m_axi_awready => M_AXI_MAC_DMA_awready,
m_axi_awsize => M_AXI_MAC_DMA_awsize,
m_axi_awvalid => M_AXI_MAC_DMA_awvalid,
m_axi_bready => M_AXI_MAC_DMA_bready,
m_axi_bresp => M_AXI_MAC_DMA_bresp,
m_axi_bvalid => M_AXI_MAC_DMA_bvalid,
m_axi_rdata => M_AXI_MAC_DMA_rdata( C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0 ),
m_axi_rlast => M_AXI_MAC_DMA_rlast,
m_axi_rready => M_AXI_MAC_DMA_rready,
m_axi_rresp => M_AXI_MAC_DMA_rresp,
m_axi_rvalid => M_AXI_MAC_DMA_rvalid,
m_axi_wdata => M_AXI_MAC_DMA_wdata( C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0 ),
m_axi_wlast => M_AXI_MAC_DMA_wlast,
m_axi_wready => M_AXI_MAC_DMA_wready,
m_axi_wstrb => M_AXI_MAC_DMA_wstrb( (C_M_AXI_MAC_DMA_DATA_WIDTH/8)-1 downto 0 ),
m_axi_wvalid => M_AXI_MAC_DMA_wvalid,
md_error => M_AXI_MAC_DMA_md_error
);
end generate genMacDmaPlbBurst;
genThePlbMaster : if C_DMA_EN = TRUE generate
begin
THE_IPIF_MASTER_HANDLER : ipif_master_handler
generic map (
C_MAC_DMA_IPIF_AWIDTH => C_M_AXI_MAC_DMA_ADDR_WIDTH,
C_MAC_DMA_IPIF_NATIVE_DWIDTH => C_M_AXI_MAC_DMA_NATIVE_DWIDTH,
dma_highadr_g => m_address'high,
gen_rx_fifo_g => not C_RX_INT_PKT,
gen_tx_fifo_g => not C_TX_INT_PKT,
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH
)
port map(
Bus2MAC_DMA_MstRd_d => bus2MAC_DMA_mstrd_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ),
Bus2MAC_DMA_MstRd_eof_n => bus2MAC_DMA_mstrd_eof_n,
Bus2MAC_DMA_MstRd_rem => bus2MAC_DMA_mstrd_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
Bus2MAC_DMA_MstRd_sof_n => bus2MAC_DMA_mstrd_sof_n,
Bus2MAC_DMA_MstRd_src_dsc_n => bus2MAC_DMA_mstrd_src_dsc_n,
Bus2MAC_DMA_MstRd_src_rdy_n => bus2MAC_DMA_mstrd_src_rdy_n,
Bus2MAC_DMA_MstWr_dst_dsc_n => bus2MAC_DMA_mstwr_dst_dsc_n,
Bus2MAC_DMA_MstWr_dst_rdy_n => bus2MAC_DMA_mstwr_dst_rdy_n,
Bus2MAC_DMA_Mst_CmdAck => bus2MAC_DMA_mst_cmdack,
Bus2MAC_DMA_Mst_Cmd_Timeout => bus2MAC_DMA_mst_cmd_timeout,
Bus2MAC_DMA_Mst_Cmplt => bus2MAC_DMA_mst_cmplt,
Bus2MAC_DMA_Mst_Error => bus2MAC_DMA_mst_error,
Bus2MAC_DMA_Mst_Rearbitrate => bus2MAC_DMA_mst_rearbitrate,
MAC_DMA2Bus_MstRd_Req => MAC_DMA2bus_mstrd_req,
MAC_DMA2Bus_MstRd_dst_dsc_n => MAC_DMA2bus_mstrd_dst_dsc_n,
MAC_DMA2Bus_MstRd_dst_rdy_n => MAC_DMA2bus_mstrd_dst_rdy_n,
MAC_DMA2Bus_MstWr_Req => MAC_DMA2bus_mstwr_req,
MAC_DMA2Bus_MstWr_d => MAC_DMA2Bus_MstWr_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ),
MAC_DMA2Bus_MstWr_eof_n => MAC_DMA2bus_mstwr_eof_n,
MAC_DMA2Bus_MstWr_rem => MAC_DMA2bus_mstwr_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
MAC_DMA2Bus_MstWr_sof_n => MAC_DMA2bus_mstwr_sof_n,
MAC_DMA2Bus_MstWr_src_dsc_n => MAC_DMA2bus_mstwr_src_dsc_n,
MAC_DMA2Bus_MstWr_src_rdy_n => MAC_DMA2bus_mstwr_src_rdy_n,
MAC_DMA2Bus_Mst_Addr => MAC_DMA2bus_mst_addr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ),
MAC_DMA2Bus_Mst_BE => MAC_DMA2bus_mst_be( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
MAC_DMA2Bus_Mst_Length => MAC_DMA2bus_mst_length( C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0 ),
MAC_DMA2Bus_Mst_Lock => MAC_DMA2bus_mst_lock,
MAC_DMA2Bus_Mst_Reset => MAC_DMA2bus_mst_reset,
MAC_DMA2Bus_Mst_Type => MAC_DMA2bus_mst_type,
MAC_DMA_CLK => M_AXI_MAC_DMA_aclk,
MAC_DMA_Rst => MAC_DMA_areset,
m_address => m_address( 31 downto 0 ),
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable,
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata
);
end generate genThePlbMaster;
genMacPktPLbSingleSlave : if C_PKT_BUF_EN generate
begin
MAC_PKT_AXI_SINGLE_SLAVE : axi_lite_ipif
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_PKT_BASE,C_MAC_PKT_HIGH),
C_ARD_NUM_CE_ARRAY => (0=>1),
C_DPHASE_TIMEOUT => C_S_AXI_MAC_PKT_DPHASE_TIMEOUT,
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_PKT_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_PKT_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_MAC_PKT_MINSIZE,
C_USE_WSTRB => C_S_AXI_MAC_PKT_USE_WSTRB
)
port map(
Bus2IP_Addr => Bus2MAC_PKT_Addr( C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_PKT_BE( (C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_PKT_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2MAC_PKT_Clk,
Bus2IP_Data => Bus2MAC_PKT_Data( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_PKT_RNW,
Bus2IP_RdCE => open,
Bus2IP_Resetn => Bus2MAC_PKT_Resetn,
Bus2IP_WrCE => open,
IP2Bus_Data => MAC_PKT2Bus_Data( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ),
IP2Bus_Error => MAC_PKT2Bus_Error,
IP2Bus_RdAck => MAC_PKT2Bus_RdAck,
IP2Bus_WrAck => MAC_PKT2Bus_WrAck,
S_AXI_ACLK => S_AXI_MAC_PKT_ACLK,
S_AXI_ARADDR => S_AXI_MAC_PKT_ARADDR( C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0 ),
S_AXI_ARESETN => S_AXI_MAC_PKT_ARESETN,
S_AXI_ARREADY => S_AXI_MAC_PKT_ARREADY,
S_AXI_ARVALID => S_AXI_MAC_PKT_ARVALID,
S_AXI_AWADDR => S_AXI_MAC_PKT_AWADDR( C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0 ),
S_AXI_AWREADY => S_AXI_MAC_PKT_AWREADY,
S_AXI_AWVALID => S_AXI_MAC_PKT_AWVALID,
S_AXI_BREADY => S_AXI_MAC_PKT_BREADY,
S_AXI_BRESP => S_AXI_MAC_PKT_BRESP,
S_AXI_BVALID => S_AXI_MAC_PKT_BVALID,
S_AXI_RDATA => S_AXI_MAC_PKT_RDATA( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ),
S_AXI_RREADY => S_AXI_MAC_PKT_RREADY,
S_AXI_RRESP => S_AXI_MAC_PKT_RRESP,
S_AXI_RVALID => S_AXI_MAC_PKT_RVALID,
S_AXI_WDATA => S_AXI_MAC_PKT_WDATA( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ),
S_AXI_WREADY => S_AXI_MAC_PKT_WREADY,
S_AXI_WSTRB => S_AXI_MAC_PKT_WSTRB( (C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0 ),
S_AXI_WVALID => S_AXI_MAC_PKT_WVALID
);
end generate genMacPktPLbSingleSlave;
genPdiPcp : if (C_GEN_PDI) generate
begin
PDI_PCP_AXI_SINGLE_SLAVE : axi_lite_ipif
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_PCP_BASE,C_PDI_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0=>1),
C_DPHASE_TIMEOUT => C_S_AXI_PDI_PCP_DPHASE_TIMEOUT,
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_PDI_PCP_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_PDI_PCP_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_PDI_PCP_MINSIZE,
C_USE_WSTRB => C_S_AXI_PDI_PCP_USE_WSTRB
)
port map(
Bus2IP_Addr => Bus2PDI_PCP_Addr( C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_PCP_BE( (C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_PCP_Clk,
Bus2IP_Data => Bus2PDI_PCP_Data( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_PCP_RNW,
Bus2IP_RdCE => open,
Bus2IP_Resetn => Bus2PDI_PCP_Resetn,
Bus2IP_WrCE => open,
IP2Bus_Data => PDI_PCP2Bus_Data( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ),
IP2Bus_Error => PDI_PCP2Bus_Error,
IP2Bus_RdAck => PDI_PCP2Bus_RdAck,
IP2Bus_WrAck => PDI_PCP2Bus_WrAck,
S_AXI_ACLK => S_AXI_PDI_PCP_ACLK,
S_AXI_ARADDR => S_AXI_PDI_PCP_ARADDR( C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0 ),
S_AXI_ARESETN => S_AXI_PDI_PCP_ARESETN,
S_AXI_ARREADY => S_AXI_PDI_PCP_ARREADY,
S_AXI_ARVALID => S_AXI_PDI_PCP_ARVALID,
S_AXI_AWADDR => S_AXI_PDI_PCP_AWADDR( C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0 ),
S_AXI_AWREADY => S_AXI_PDI_PCP_AWREADY,
S_AXI_AWVALID => S_AXI_PDI_PCP_AWVALID,
S_AXI_BREADY => S_AXI_PDI_PCP_BREADY,
S_AXI_BRESP => S_AXI_PDI_PCP_BRESP,
S_AXI_BVALID => S_AXI_PDI_PCP_BVALID,
S_AXI_RDATA => S_AXI_PDI_PCP_RDATA( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ),
S_AXI_RREADY => S_AXI_PDI_PCP_RREADY,
S_AXI_RRESP => S_AXI_PDI_PCP_RRESP,
S_AXI_RVALID => S_AXI_PDI_PCP_RVALID,
S_AXI_WDATA => S_AXI_PDI_PCP_WDATA( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ),
S_AXI_WREADY => S_AXI_PDI_PCP_WREADY,
S_AXI_WSTRB => S_AXI_PDI_PCP_WSTRB( (C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0 ),
S_AXI_WVALID => S_AXI_PDI_PCP_WVALID
);
end generate genPdiPcp;
genPcpPdiLink : if C_GEN_PDI generate
begin
--pdi_pcp assignments
clkPcp <= Bus2PDI_PCP_Clk;
Bus2PDI_PCP_Reset <= not Bus2PDI_PCP_Resetn;
pcp_writedata <= Bus2PDI_PCP_Data;
-- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
-- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
pcp_read <= Bus2PDI_PCP_RNW;
pcp_write <= not Bus2PDI_PCP_RNW;
pcp_chipselect <= Bus2PDI_PCP_CS(0);
pcp_byteenable <= Bus2PDI_PCP_BE;
pcp_address <= Bus2PDI_PCP_Addr(14 downto 2);
PDI_PCP2Bus_Data <= pcp_readdata;
PDI_PCP2Bus_RdAck <= pcp_chipselect and pcp_read and not pcp_waitrequest;
PDI_PCP2Bus_WrAck <= pcp_chipselect and pcp_write and not pcp_waitrequest;
PDI_PCP2Bus_Error <= '0';
end generate genPcpPdiLink;
genPdiAp : if (C_GEN_AXI_BUS_IF) generate
begin
PDI_AP_AXI_SINGLE_SLAVE : axi_lite_ipif
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_AP_BASE,C_PDI_AP_HIGH),
C_ARD_NUM_CE_ARRAY => (0=>1),
C_DPHASE_TIMEOUT => C_S_AXI_PDI_AP_DPHASE_TIMEOUT,
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_PDI_AP_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_PDI_AP_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_PDI_AP_MINSIZE,
C_USE_WSTRB => C_S_AXI_PDI_AP_USE_WSTRB
)
port map(
Bus2IP_Addr => Bus2PDI_AP_Addr( C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_AP_BE( (C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_AP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_AP_Clk,
Bus2IP_Data => Bus2PDI_AP_Data( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_AP_RNW,
Bus2IP_RdCE => open,
Bus2IP_Resetn => Bus2PDI_AP_Resetn,
Bus2IP_WrCE => open,
IP2Bus_Data => PDI_AP2Bus_Data( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ),
IP2Bus_Error => PDI_AP2Bus_Error,
IP2Bus_RdAck => PDI_AP2Bus_RdAck,
IP2Bus_WrAck => PDI_AP2Bus_WrAck,
S_AXI_ACLK => S_AXI_PDI_AP_ACLK,
S_AXI_ARADDR => S_AXI_PDI_AP_ARADDR( C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0 ),
S_AXI_ARESETN => S_AXI_PDI_AP_ARESETN,
S_AXI_ARREADY => S_AXI_PDI_AP_ARREADY,
S_AXI_ARVALID => S_AXI_PDI_AP_ARVALID,
S_AXI_AWADDR => S_AXI_PDI_AP_AWADDR( C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0 ),
S_AXI_AWREADY => S_AXI_PDI_AP_AWREADY,
S_AXI_AWVALID => S_AXI_PDI_AP_AWVALID,
S_AXI_BREADY => S_AXI_PDI_AP_BREADY,
S_AXI_BRESP => S_AXI_PDI_AP_BRESP,
S_AXI_BVALID => S_AXI_PDI_AP_BVALID,
S_AXI_RDATA => S_AXI_PDI_AP_RDATA( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ),
S_AXI_RREADY => S_AXI_PDI_AP_RREADY,
S_AXI_RRESP => S_AXI_PDI_AP_RRESP,
S_AXI_RVALID => S_AXI_PDI_AP_RVALID,
S_AXI_WDATA => S_AXI_PDI_AP_WDATA( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ),
S_AXI_WREADY => S_AXI_PDI_AP_WREADY,
S_AXI_WSTRB => S_AXI_PDI_AP_WSTRB( (C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0 ),
S_AXI_WVALID => S_AXI_PDI_AP_WVALID
);
end generate genPdiAp;
genApPdiLink : if C_GEN_PDI generate
begin
--ap_pcp assignments
clkAp <= Bus2PDI_AP_Clk;
Bus2PDI_AP_Reset <= not Bus2PDI_AP_Resetn;
ap_writedata <= Bus2PDI_AP_Data;
-- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
-- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
ap_read <= Bus2PDI_AP_RNW;
ap_write <= not Bus2PDI_AP_RNW;
ap_chipselect <= Bus2PDI_AP_CS(0);
ap_byteenable <= Bus2PDI_AP_BE;
ap_address <= Bus2PDI_AP_Addr(14 downto 2);
PDI_AP2Bus_Data <= ap_readdata;
PDI_AP2Bus_RdAck <= ap_chipselect and ap_read and not ap_waitrequest;
PDI_AP2Bus_WrAck <= ap_chipselect and ap_write and not ap_waitrequest;
PDI_AP2Bus_Error <= '0';
end generate genApPdiLink;
genSmpIo : if (C_GEN_SIMPLE_IO) generate
begin
SMP_IO_AXI_SINGLE_SLAVE : axi_lite_ipif
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_SMP_PCP_BASE,C_SMP_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0=>1),
C_DPHASE_TIMEOUT => C_S_AXI_SMP_PCP_DPHASE_TIMEOUT,
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_SMP_PCP_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_SMP_PCP_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_SMP_PCP_MINSIZE,
C_USE_WSTRB => C_S_AXI_SMP_PCP_USE_WSTRB
)
port map(
Bus2IP_Addr => Bus2SMP_PCP_Addr( C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0 ),
Bus2IP_BE => Bus2SMP_PCP_BE( (C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2SMP_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2SMP_PCP_Clk,
Bus2IP_Data => Bus2SMP_PCP_Data( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2SMP_PCP_RNW,
Bus2IP_RdCE => open,
Bus2IP_Resetn => Bus2SMP_PCP_Resetn,
Bus2IP_WrCE => open,
IP2Bus_Data => SMP_PCP2Bus_Data( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ),
IP2Bus_Error => SMP_PCP2Bus_Error,
IP2Bus_RdAck => SMP_PCP2Bus_RdAck,
IP2Bus_WrAck => SMP_PCP2Bus_WrAck,
S_AXI_ACLK => S_AXI_SMP_PCP_ACLK,
S_AXI_ARADDR => S_AXI_SMP_PCP_ARADDR( C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0 ),
S_AXI_ARESETN => S_AXI_SMP_PCP_ARESETN,
S_AXI_ARREADY => S_AXI_SMP_PCP_ARREADY,
S_AXI_ARVALID => S_AXI_SMP_PCP_ARVALID,
S_AXI_AWADDR => S_AXI_SMP_PCP_AWADDR( C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0 ),
S_AXI_AWREADY => S_AXI_SMP_PCP_AWREADY,
S_AXI_AWVALID => S_AXI_SMP_PCP_AWVALID,
S_AXI_BREADY => S_AXI_SMP_PCP_BREADY,
S_AXI_BRESP => S_AXI_SMP_PCP_BRESP,
S_AXI_BVALID => S_AXI_SMP_PCP_BVALID,
S_AXI_RDATA => S_AXI_SMP_PCP_RDATA( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ),
S_AXI_RREADY => S_AXI_SMP_PCP_RREADY,
S_AXI_RRESP => S_AXI_SMP_PCP_RRESP,
S_AXI_RVALID => S_AXI_SMP_PCP_RVALID,
S_AXI_WDATA => S_AXI_SMP_PCP_WDATA( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ),
S_AXI_WREADY => S_AXI_SMP_PCP_WREADY,
S_AXI_WSTRB => S_AXI_SMP_PCP_WSTRB( (C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0 ),
S_AXI_WVALID => S_AXI_SMP_PCP_WVALID
);
end generate genSmpIo;
genSimpleIoSignals : if C_GEN_SIMPLE_IO generate
begin
--SMP_PCP assignments
clkPcp <= Bus2SMP_PCP_Clk;
Bus2SMP_PCP_Reset <= not Bus2SMP_PCP_Resetn;
smp_writedata <= Bus2SMP_PCP_Data;
smp_read <= Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_write <= not Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_chipselect <= Bus2SMP_PCP_CS(0);
smp_byteenable <= Bus2SMP_PCP_BE;
smp_address <= Bus2SMP_PCP_Addr(2);
SMP_PCP2Bus_Data <= smp_readdata;
SMP_PCP2Bus_RdAck <= smp_chipselect and smp_read and not smp_waitrequest;
SMP_PCP2Bus_WrAck <= smp_chipselect and smp_write and not smp_waitrequest;
SMP_PCP2Bus_Error <= '0';
end generate genSimpleIoSignals;
oddr2_0 : if not C_INSTANCE_ODDR2 generate
begin
phy0_clk <= clk50;
phy1_clk <= clk50;
end generate oddr2_0;
oddr2_1 : if C_INSTANCE_ODDR2 generate
begin
U10 : ODDR2
port map(
C0 => clk50,
C1 => NET38418,
CE => VCC,
D0 => VCC,
D1 => GND,
Q => phy0_clk,
R => GND,
S => GND
);
U11 : ODDR2
port map(
C0 => clk50,
C1 => NET38470,
CE => VCC,
D0 => VCC,
D1 => GND,
Q => phy1_clk,
R => GND,
S => GND
);
NET38470 <= not(clk50);
NET38418 <= not(clk50);
end generate oddr2_1;
end struct;
| gpl-2.0 |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/pdi/src/pdi_spi.vhd | 3 | 13652 | -------------------------------------------------------------------------------
-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_spi is
generic (
spiSize_g : integer := 8;
cpol_g : boolean := false;
cpha_g : boolean := false;
spiBigEnd_g : boolean := false
);
port (
-- SPI
spi_clk : in std_logic;
spi_sel : in std_logic;
spi_miso : out std_logic;
spi_mosi : in std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0)
);
end entity pdi_spi;
architecture rtl of pdi_spi is
--wake up command
constant cmdWakeUp : std_logic_vector(7 downto 0) := x"03"; --0b00000011
constant cmdWakeUp1 : std_logic_vector(7 downto 0) := x"0A"; --0b00001010
constant cmdWakeUp2 : std_logic_vector(7 downto 0) := x"0C"; --0b00001100
constant cmdWakeUp3 : std_logic_vector(7 downto 0) := x"0F"; --0b00001111
--spi frame constants
constant cmdHighaddr_c : std_logic_vector(2 downto 0) := "100";
constant cmdMidaddr_c : std_logic_vector(2 downto 0) := "101";
constant cmdWr_c : std_logic_vector(2 downto 0) := "110";
constant cmdRd_c : std_logic_vector(2 downto 0) := "111";
constant cmdWRSQ_c : std_logic_vector(2 downto 0) := "001";
constant cmdRDSQ_c : std_logic_vector(2 downto 0) := "010";
constant cmdLowaddr_c : std_logic_vector(2 downto 0) := "011";
constant cmdIdle_c : std_logic_vector(2 downto 0) := "000";
--pdi_spi control signals
type fsm_t is (reset, reset1, reset2, reset3, idle, decode, waitwr, waitrd, wr, rd);
signal fsm : fsm_t;
signal addrReg : std_logic_vector(ap_address'left+2 downto 0);
signal cmd : std_logic_vector(2 downto 0);
signal highPriorLoad : std_logic;
signal highPriorLoadVal : std_logic_vector(spiSize_g-1 downto 0);
--spi core signals
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic_vector(spiSize_g-1 downto 0);
signal load : std_logic;
signal dout : std_logic_vector(spiSize_g-1 downto 0);
signal valid : std_logic;
--
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
begin
clk <= ap_clk;
rst <= ap_reset;
ap_chipselect <= '1' when fsm = wr or fsm = rd or fsm = waitrd else '0';
ap_write <= '1' when fsm = wr else '0';
ap_read <= '1' when fsm = waitrd or fsm = rd else '0';
ap_address <= addrReg(addrReg'left downto 2);
ap_byteenable <= ap_byteenable_s;
ap_byteenable_s <= --little endian
"0001" when addrReg(1 downto 0) = "00" and spiBigEnd_g = false else
"0010" when addrReg(1 downto 0) = "01" and spiBigEnd_g = false else
"0100" when addrReg(1 downto 0) = "10" and spiBigEnd_g = false else
"1000" when addrReg(1 downto 0) = "11" and spiBigEnd_g = false else
--big endian
--"0001" when addrReg(1 downto 0) = "11" and spiBigEnd_g = true else
--"0010" when addrReg(1 downto 0) = "10" and spiBigEnd_g = true else
--"0100" when addrReg(1 downto 0) = "01" and spiBigEnd_g = true else
--"1000" when addrReg(1 downto 0) = "00" and spiBigEnd_g = true else
"0000";
ap_writedata <= (dout & dout & dout & dout);
din <= highPriorLoadVal when highPriorLoad = '1' else --load value that was just received
ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
load <= '1' when highPriorLoad = '1' else --load value that was just received
'1' when fsm = rd else --load data from pdi to spi shift register
'0';
cmd <= dout(dout'left downto dout'left-2); --get cmd pattern
highPriorLoadVal <= not dout; --create inverse of received pattern
thePdiSpiFsm : process(clk, rst)
variable timeout : integer range 0 to 3;
variable writes : integer range 0 to 32;
variable reads : integer range 0 to 32;
begin
if rst = '1' then
fsm <= reset;
timeout := 0;
writes := 0; reads := 0;
addrReg <= (others => '0');
highPriorLoad <= '0';
elsif clk = '1' and clk'event then
--default assignment
highPriorLoad <= '0';
case fsm is
when reset =>
fsm <= reset;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp then
--wake up command (1/4) received
fsm <= reset1;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset1 =>
fsm <= reset1;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp1 then
--wake up command (2/4) sequence was correctly decoded!
fsm <= reset2;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset2 =>
fsm <= reset2;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp2 then
--wake up command (3/4) sequence was correctly decoded!
fsm <= reset3;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset3 =>
fsm <= reset3;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp3 then
--wake up command (4/4) sequence was correctly decoded!
fsm <= idle;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when idle =>
if writes /= 0 then
fsm <= waitwr;
elsif reads /= 0 and valid = '1' then
fsm <= waitrd;
elsif valid = '1' then
fsm <= decode;
else
fsm <= idle;
end if;
when decode =>
fsm <= idle; --default
case cmd is
when cmdHighaddr_c =>
addrReg(addrReg'left downto addrReg'left-4) <= dout(spiSize_g-4 downto 0);
when cmdMidaddr_c =>
addrReg(addrReg'left-5 downto addrReg'left-9) <= dout(spiSize_g-4 downto 0);
when cmdLowaddr_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
when cmdWr_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
fsm <= waitwr;
writes := 1;
when cmdRd_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
fsm <= waitrd;
reads := 1;
when cmdWRSQ_c =>
fsm <= waitwr;
writes := conv_integer(dout(spiSize_g-4 downto 0)) + 1; --BYTES byte are written
when cmdRDSQ_c =>
fsm <= waitrd;
reads := conv_integer(dout(spiSize_g-4 downto 0)) + 1; --BYTES byte are read
when cmdIdle_c =>
--don't interpret the command, inverse pattern and goto idle
when others =>
--error, goto idle
end case;
when waitwr =>
--wait for data from spi master
if valid = '1' then
fsm <= wr;
else
fsm <= waitwr;
end if;
when waitrd =>
--spi master wants to read
--wait for dpr to read
if timeout = 3 then
fsm <= rd;
timeout := 0;
else
timeout := timeout + 1;
fsm <= waitrd;
end if;
when wr =>
fsm <= idle;
writes := writes - 1;
addrReg <= addrReg + 1;
when rd =>
fsm <= idle;
reads := reads - 1;
addrReg <= addrReg + 1;
end case;
end if;
end process;
theSpiCore : entity work.spi
generic map (
frameSize_g => spiSize_g,
cpol_g => cpol_g,
cpha_g => cpha_g
)
port map (
-- Control Interface
clk => clk,
rst => rst,
din => din,
load => load,
dout => dout,
valid => valid,
-- SPI
sck => spi_clk,
ss => spi_sel,
miso => spi_miso,
mosi => spi_mosi
);
end architecture rtl;
| gpl-2.0 |
systec-dk/openPOWERLINK_systec | Examples/altera_nios2/TERASIC_DE2-115/design_nios2_directIO/sevsegEncode.vhd | 10 | 902 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sevsegdec IS
PORT
(
d : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
seg_n : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
seg : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END sevsegdec;
ARCHITECTURE rtl of sevsegdec is
SIGNAL seg_s : STD_LOGIC_VECTOR(6 DOWNTO 0);
begin
seg_n <= seg_s;
seg <= not seg_s;
with d select
seg_s <= "1000000" when "0000", -- 0
"1111001" when "0001", -- 1
"0100100" when "0010", -- 2
"0110000" when "0011", -- 3
"0011001" when "0100", -- 4
"0010010" when "0101", -- 5
"0000010" when "0110", -- 6
"1111000" when "0111", -- 7
"0000000" when "1000", -- 8
"0010000" when "1001", -- 9
"0001000" when "1010", -- A
"0000011" when "1011", -- b
"1000110" when "1100", -- C
"0100001" when "1101", -- d
"0000110" when "1110", -- E
"0001110" when "1111"; -- F
END rtl;
| gpl-2.0 |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/openmac/src/openMAC_Ethernet.vhd | 3 | 38357 | -------------------------------------------------------------------------------
-- Entity : openMAC_Ethernet
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity openmac_ethernet is
generic(
genSmiIO : boolean := true;
gNumSmi : integer := 2;
gen2ndCmpTimer_g : boolean := false;
genPulse2ndCmpTimer_g : boolean := true;
pulseWidth2ndCmpTimer_g : integer := 9;
simulate : boolean := false;
dma_highadr_g : integer := 31;
m_data_width_g : integer := 16;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_fifo_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
endian_g : string := "little";
genPhyActLed_g : boolean := false;
gen_dma_observer_g : boolean := true;
useIntPktBuf_g : boolean := false;
useRxIntPktBuf_g : boolean := false;
iPktBufSize_g : integer := 1024;
iPktBufSizeLog2_g : integer := 10;
genHub_g : boolean := false;
useRmii_g : boolean := true
);
port(
clk : in std_logic;
clkx2 : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
phy0_rx_dv : in std_logic;
phy0_rx_err : in std_logic;
phy0_smi_dio_I : in std_logic;
phy1_rx_dv : in std_logic;
phy1_rx_err : in std_logic;
phy1_smi_dio_I : in std_logic;
phyMii0_rx_clk : in std_logic;
phyMii0_rx_dv : in std_logic;
phyMii0_rx_err : in std_logic;
phyMii0_tx_clk : in std_logic;
phyMii1_rx_clk : in std_logic;
phyMii1_rx_dv : in std_logic;
phyMii1_rx_err : in std_logic;
phyMii1_tx_clk : in std_logic;
phy_smi_dio_I : in std_logic;
pkt_chipselect : in std_logic;
pkt_clk : in std_logic;
pkt_read : in std_logic;
pkt_write : in std_logic;
rst : in std_logic;
s_chipselect : in std_logic;
s_read : in std_logic;
s_write : in std_logic;
t_chipselect : in std_logic;
t_read : in std_logic;
t_write : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
phy0_rx_dat : in std_logic_vector(1 downto 0);
phy1_rx_dat : in std_logic_vector(1 downto 0);
phyMii0_rx_dat : in std_logic_vector(3 downto 0);
phyMii1_rx_dat : in std_logic_vector(3 downto 0);
pkt_address : in std_logic_vector(iPktBufSizeLog2_g-3 downto 0) := (others => '0');
pkt_byteenable : in std_logic_vector(3 downto 0);
pkt_writedata : in std_logic_vector(31 downto 0);
s_address : in std_logic_vector(11 downto 0);
s_byteenable : in std_logic_vector(1 downto 0);
s_writedata : in std_logic_vector(15 downto 0);
t_address : in std_logic_vector(1 downto 0);
t_byteenable : in std_logic_vector(3 downto 0);
t_writedata : in std_logic_vector(31 downto 0);
act_led : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
mac_rx_irq : out std_logic;
mac_tx_irq : out std_logic;
phy0_rst_n : out std_logic;
phy0_smi_clk : out std_logic;
phy0_smi_dio_O : out std_logic;
phy0_smi_dio_T : out std_logic;
phy0_tx_en : out std_logic;
phy1_rst_n : out std_logic;
phy1_smi_clk : out std_logic;
phy1_smi_dio_O : out std_logic;
phy1_smi_dio_T : out std_logic;
phy1_tx_en : out std_logic;
phyMii0_tx_en : out std_logic;
phyMii1_tx_en : out std_logic;
phy_rst_n : out std_logic;
phy_smi_clk : out std_logic;
phy_smi_dio_O : out std_logic;
phy_smi_dio_T : out std_logic;
pkt_waitrequest : out std_logic;
s_irq : out std_logic;
s_waitrequest : out std_logic;
t_irq : out std_logic;
t_tog : out std_logic;
t_waitrequest : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0);
phy0_tx_dat : out std_logic_vector(1 downto 0);
phy1_tx_dat : out std_logic_vector(1 downto 0);
phyMii0_tx_dat : out std_logic_vector(3 downto 0);
phyMii1_tx_dat : out std_logic_vector(3 downto 0);
pkt_readdata : out std_logic_vector(31 downto 0);
s_readdata : out std_logic_vector(15 downto 0);
t_readdata : out std_logic_vector(31 downto 0);
phy0_smi_dio : inout std_logic := '1';
phy1_smi_dio : inout std_logic := '1';
phy_smi_dio : inout std_logic := '1'
);
end openmac_ethernet;
architecture rtl of openmac_ethernet is
---- Component declarations -----
component addr_decoder
generic(
addrWidth_g : integer := 32;
baseaddr_g : integer := 4096;
highaddr_g : integer := 8191
);
port (
addr : in std_logic_vector(addrWidth_g-1 downto 0);
selin : in std_logic;
selout : out std_logic
);
end component;
component openFILTER
generic(
bypassFilter : boolean := false
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDatIn : in std_logic_vector(1 downto 0);
RxDvIn : in std_logic;
RxErr : in std_logic := '0';
TxDatIn : in std_logic_vector(1 downto 0);
TxEnIn : in std_logic;
nCheckShortFrames : in std_logic := '0';
RxDatOut : out std_logic_vector(1 downto 0);
RxDvOut : out std_logic;
TxDatOut : out std_logic_vector(1 downto 0);
TxEnOut : out std_logic
);
end component;
component OpenHUB
generic(
Ports : integer := 3
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDat0 : in std_logic_vector(Ports downto 1);
RxDat1 : in std_logic_vector(Ports downto 1);
RxDv : in std_logic_vector(Ports downto 1);
TransmitMask : in std_logic_vector(Ports downto 1) := (others => '1');
internPort : in integer range 1 to ports := 1;
ReceivePort : out integer range 0 to ports;
TxDat0 : out std_logic_vector(Ports downto 1);
TxDat1 : out std_logic_vector(Ports downto 1);
TxEn : out std_logic_vector(Ports downto 1)
);
end component;
component OpenMAC
generic(
HighAdr : integer := 16;
Simulate : boolean := false;
Timer : boolean := false;
TxDel : boolean := false;
TxSyncOn : boolean := false
);
port (
Clk : in std_logic;
Dma_Ack : in std_logic;
Dma_Din : in std_logic_vector(15 downto 0);
Hub_Rx : in std_logic_vector(1 downto 0) := "00";
Rst : in std_logic;
S_Adr : in std_logic_vector(10 downto 1);
S_Din : in std_logic_vector(15 downto 0);
S_nBe : in std_logic_vector(1 downto 0);
Sel_Cont : in std_logic := '0';
Sel_Ram : in std_logic := '0';
rCrs_Dv : in std_logic;
rRx_Dat : in std_logic_vector(1 downto 0);
s_nWr : in std_logic := '0';
Dma_Addr : out std_logic_vector(HighAdr downto 1);
Dma_Dout : out std_logic_vector(15 downto 0);
Dma_Rd_Done : out std_logic;
Dma_Rd_Len : out std_logic_vector(11 downto 0);
Dma_Req : out std_logic;
Dma_Req_Overflow : out std_logic;
Dma_Rw : out std_logic;
Dma_Wr_Done : out std_logic;
Mac_Zeit : out std_logic_vector(31 downto 0);
S_Dout : out std_logic_vector(15 downto 0);
nRx_Int : out std_logic;
nTx_BegInt : out std_logic;
nTx_Int : out std_logic;
rTx_Dat : out std_logic_vector(1 downto 0);
rTx_En : out std_logic
);
end component;
component openMAC_cmp
generic(
gen2ndCmpTimer_g : BOOLEAN := false;
genPulse2ndCmpTimer_g : BOOLEAN := false;
mac_time_width_g : INTEGER := 32;
pulseWidth2ndCmpTimer_g : INTEGER := 9
);
port (
addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
din : in std_logic_vector(31 downto 0);
mac_time : in std_logic_vector(mac_time_width_g-1 downto 0);
rst : in std_logic;
wr : in std_logic;
dout : out std_logic_vector(31 downto 0);
irq : out std_logic;
toggle : out std_logic
);
end component;
component openMAC_DMAmaster
generic(
dma_highadr_g : integer := 31;
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_g : integer := 32;
simulate : boolean := false;
tx_fifo_word_size_g : integer := 32
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_dout : in std_logic_vector(15 downto 0);
dma_rd_len : in std_logic_vector(11 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end component;
component OpenMAC_DPRpackets
generic(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
port (
address_a : in std_logic_vector(memSizeLOG2_g-2 downto 0);
address_b : in std_logic_vector(memSizeLOG2_g-3 downto 0);
byteena_a : in std_logic_vector(1 downto 0) := (others => '1');
byteena_b : in std_logic_vector(3 downto 0) := (others => '1');
clock_a : in std_logic := '1';
clock_b : in std_logic;
data_a : in std_logic_vector(15 downto 0);
data_b : in std_logic_vector(31 downto 0);
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
q_a : out std_logic_vector(15 downto 0);
q_b : out std_logic_vector(31 downto 0)
);
end component;
component OpenMAC_MII
port (
Addr : in std_logic_vector(2 downto 0);
Clk : in std_logic;
Data_In : in std_logic_vector(15 downto 0);
Mii_Di : in std_logic;
Rst : in std_logic;
Sel : in std_logic;
nBe : in std_logic_vector(1 downto 0);
nWr : in std_logic;
Data_Out : out std_logic_vector(15 downto 0);
Mii_Clk : out std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic;
nResetOut : out std_logic
);
end component;
component OpenMAC_phyAct
generic(
iBlinkFreq_g : integer := 6
);
port (
clk : in std_logic;
rst : in std_logic;
rx_dv : in std_logic;
tx_en : in std_logic;
act_led : out std_logic
);
end component;
component req_ack
generic(
ack_delay_g : integer := 1;
zero_delay_g : boolean := false
);
port (
clk : in std_logic;
enable : in std_logic;
rst : in std_logic;
ack : out std_logic
);
end component;
component rmii2mii
port (
clk50 : in std_logic;
mRxClk : in std_logic;
mRxDat : in std_logic_vector(3 downto 0);
mRxDv : in std_logic;
mRxEr : in std_logic;
mTxClk : in std_logic;
rTxDat : in std_logic_vector(1 downto 0);
rTxEn : in std_logic;
rst : in std_logic;
mTxDat : out std_logic_vector(3 downto 0);
mTxEn : out std_logic;
rRxDat : out std_logic_vector(1 downto 0);
rRxDv : out std_logic;
rRxEr : out std_logic
);
end component;
---- Architecture declarations -----
--constants for packet dma master
constant gen_tx_fifo_c : boolean := not useIntPktBuf_g;
constant gen_rx_fifo_c : boolean := not(useIntPktBuf_g and useRxIntPktBuf_g);
constant fifo_data_width_c : integer := m_data_width_g;
constant rx_fifo_word_size_c : integer := m_rx_fifo_size_g; --set value power of 2
constant tx_fifo_word_size_c : integer := m_tx_fifo_size_g; --set value power of 2
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
---- Signal declarations used on the diagram ----
signal cmp_rd : std_logic;
signal cmp_rd_ack : std_logic;
signal cmp_wr : std_logic;
signal cmp_wr_ack : std_logic;
signal dmaErr_sel : std_logic;
signal dma_ack : std_logic;
signal dma_ack_rd_mst : std_logic;
signal dma_ack_read : std_logic;
signal dma_ack_rw : std_logic;
signal dma_ack_write : std_logic;
signal dma_rd_err : std_logic;
signal dma_req : std_logic;
signal dma_req_overflow : std_logic;
signal dma_req_read : std_logic;
signal dma_req_write : std_logic;
signal dma_rw : std_logic;
signal dma_wr_err : std_logic;
signal flt0_rx_dv : std_logic;
signal flt0_tx_en : std_logic;
signal flt1_rx_dv : std_logic;
signal flt1_tx_en : std_logic;
signal hub_intern_port : integer;
signal hub_rx_port : integer;
signal irqTable_sel : std_logic;
signal mac_rx_dv : std_logic;
signal mac_rx_irq_s : std_logic;
signal mac_rx_irq_s_n : std_logic;
signal mac_rx_off : std_logic;
signal mac_selcont : std_logic;
signal mac_selfilter : std_logic;
signal mac_selram : std_logic;
signal mac_tx_en : std_logic;
signal mac_tx_irq_s : std_logic;
signal mac_tx_irq_s_n : std_logic;
signal mac_tx_off : std_logic;
signal mac_write : std_logic;
signal mac_write_n : std_logic;
signal phy0_rx_dv_s : std_logic;
signal phy0_rx_err_s : std_logic;
signal phy0_tx_en_s : std_logic;
signal phy1_rx_dv_s : std_logic;
signal phy1_rx_err_s : std_logic;
signal phy1_tx_en_s : std_logic;
signal pkt_read_ack : std_logic;
signal pkt_write_ack : std_logic;
signal read_a : std_logic;
signal read_b : std_logic;
signal smi_clk : std_logic;
signal smi_di_s : std_logic;
signal smi_doe_s : std_logic;
signal smi_doe_s_n : std_logic;
signal smi_do_s : std_logic;
signal smi_rst_n : std_logic;
signal smi_sel : std_logic;
signal smi_write : std_logic;
signal smi_write_n : std_logic;
signal s_rd : std_logic;
signal s_rd_ack : std_logic;
signal s_wr : std_logic;
signal s_wr_ack : std_logic;
signal toggle : std_logic;
signal VCC : std_logic;
signal write_a : std_logic;
signal write_b : std_logic;
signal dma_addr : std_logic_vector (dma_highadr_g downto 1);
signal dma_addr_s : std_logic_vector (iPktBufSizeLog2_g-1 downto 1);
signal dma_be : std_logic_vector (1 downto 0);
signal dma_din : std_logic_vector (15 downto 0);
signal dma_din_mst : std_logic_vector (15 downto 0);
signal dma_din_s : std_logic_vector (15 downto 0);
signal dma_dout : std_logic_vector (15 downto 0);
signal dma_dout_s : std_logic_vector (15 downto 0);
signal dma_rd_len : std_logic_vector (11 downto 0);
signal flt0_rx_dat : std_logic_vector (1 downto 0);
signal flt0_tx_dat : std_logic_vector (1 downto 0);
signal flt1_rx_dat : std_logic_vector (1 downto 0);
signal flt1_tx_dat : std_logic_vector (1 downto 0);
signal hub_rx : std_logic_vector (1 downto 0);
signal hub_rx_dat0 : std_logic_vector (3 downto 1);
signal hub_rx_dat1 : std_logic_vector (3 downto 1);
signal hub_rx_dv : std_logic_vector (3 downto 1);
signal hub_tx_dat0 : std_logic_vector (3 downto 1);
signal hub_tx_dat1 : std_logic_vector (3 downto 1);
signal hub_tx_en : std_logic_vector (3 downto 1);
signal hub_tx_msk : std_logic_vector (3 downto 1);
signal irqTable : std_logic_vector (15 downto 0);
signal mac_addr : std_logic_vector (10 downto 1);
signal mac_be : std_logic_vector (1 downto 0);
signal mac_be_n : std_logic_vector (1 downto 0);
signal mac_din : std_logic_vector (15 downto 0);
signal mac_dout : std_logic_vector (15 downto 0);
signal mac_rx_dat : std_logic_vector (1 downto 0);
signal mac_time : std_logic_vector (31 downto 0);
signal mac_tx_dat : std_logic_vector (1 downto 0);
signal phy0_rx_dat_s : std_logic_vector (1 downto 0);
signal phy0_tx_dat_s : std_logic_vector (1 downto 0);
signal phy1_rx_dat_s : std_logic_vector (1 downto 0);
signal phy1_tx_dat_s : std_logic_vector (1 downto 0);
signal smi_addr : std_logic_vector (2 downto 0);
signal smi_be : std_logic_vector (1 downto 0);
signal smi_be_n : std_logic_vector (1 downto 0);
signal smi_din : std_logic_vector (15 downto 0);
signal smi_dout : std_logic_vector (15 downto 0);
signal s_address_s : std_logic_vector (s_address'length downto 0);
signal t_readdata_s : std_logic_vector (31 downto 0);
signal t_writedata_s : std_logic_vector (31 downto 0);
begin
---- User Signal Assignments ----
--endian conversion
t_writedata_s <= t_writedata(7 downto 0) & t_writedata(15 downto 8) &
t_writedata(23 downto 16) & t_writedata(31 downto 24) when endian_g = "big" else
t_writedata;
t_readdata <= t_readdata_s(7 downto 0) & t_readdata_s(15 downto 8) &
t_readdata_s(23 downto 16) & t_readdata_s(31 downto 24) when endian_g = "big" else
t_readdata_s;
--assign address bus and be to openMA
mac_addr <= s_address(9 downto 0);
mac_be <= s_byteenable;
--convert word into byte addresses
s_address_s <= s_address & '0';
smi_addr <= s_address(2 downto 0);
smi_be <= s_byteenable;
--assign output data to readdata
s_readdata <=
mac_dout when (mac_selram = '1' or mac_selcont = '1') and endian_g = "little" else
mac_dout when (mac_selram = '1' or mac_selcont = '1') and endian_g = "big" and s_byteenable /= "11" else
mac_dout(7 downto 0) & mac_dout(15 downto 8) when (mac_selram = '1' or mac_selcont = '1') and endian_g = "big" else --and s_byteenable = "11"
smi_dout when smi_sel = '1' and endian_g = "little" else
smi_dout when smi_sel = '1' and endian_g = "big" and s_byteenable /= "11" else
smi_dout(7 downto 0) & smi_dout(15 downto 8) when smi_sel = '1' and endian_g = "big" else --and s_byteenable = "11"
irqTable when irqTable_sel = '1' and endian_g = "little" else
irqTable(7 downto 0) & irqTable(15 downto 8) when irqTable_sel = '1' and endian_g = "big" else
(8 => dma_rd_err, 0 => dma_wr_err, others => '0') when dmaErr_sel = '1' and endian_g = "little" else
(8 => dma_rd_err, 0 => dma_wr_err, others => '0') when dmaErr_sel = '1' and endian_g = "big" else
(others => '0');
--assign writedata to input data
mac_din <= s_writedata when endian_g = "little" or (endian_g = "big" and s_byteenable /= "11") else
s_writedata(7 downto 0) & s_writedata(15 downto 8); --when endian_g = "big" and s_byteenable = "11"
smi_din <= s_writedata when endian_g = "little" or (endian_g = "big" and s_byteenable /= "11") else
s_writedata(7 downto 0) & s_writedata(15 downto 8); --when endian_g = "big" and s_byteenable = "11"
---- Component instantiations ----
THE_MAC_TIME_CMP : openMAC_cmp
generic map (
gen2ndCmpTimer_g => gen2ndCmpTimer_g,
genPulse2ndCmpTimer_g => genPulse2ndCmpTimer_g,
mac_time_width_g => 32,
pulseWidth2ndCmpTimer_g => pulseWidth2ndCmpTimer_g
)
port map(
addr => t_address,
clk => clk,
din => t_writedata_s,
dout => t_readdata_s,
irq => t_irq,
mac_time => mac_time( 31 downto 0 ),
rst => rst,
toggle => toggle,
wr => cmp_wr
);
THE_OPENMAC : OpenMAC
generic map (
HighAdr => dma_highadr_g,
Simulate => simulate,
Timer => true,
TxDel => true,
TxSyncOn => true
)
port map(
Clk => clk,
Dma_Ack => dma_ack,
Dma_Addr => dma_addr( dma_highadr_g downto 1 ),
Dma_Din => dma_din,
Dma_Dout => dma_dout,
Dma_Rd_Done => mac_tx_off,
Dma_Rd_Len => dma_rd_len,
Dma_Req => dma_req,
Dma_Req_Overflow => dma_req_overflow,
Dma_Rw => dma_rw,
Dma_Wr_Done => mac_rx_off,
Hub_Rx => hub_rx,
Mac_Zeit => mac_time,
Rst => rst,
S_Adr => mac_addr,
S_Din => mac_din,
S_Dout => mac_dout,
S_nBe => mac_be_n,
Sel_Cont => mac_selcont,
Sel_Ram => mac_selram,
nRx_Int => mac_rx_irq_s_n,
nTx_Int => mac_tx_irq_s_n,
rCrs_Dv => mac_rx_dv,
rRx_Dat => mac_rx_dat,
rTx_Dat => mac_tx_dat,
rTx_En => mac_tx_en,
s_nWr => mac_write_n
);
THE_PHY_MGMT : OpenMAC_MII
port map(
Addr => smi_addr,
Clk => clk,
Data_In => smi_din,
Data_Out => smi_dout,
Mii_Clk => smi_clk,
Mii_Di => smi_di_s,
Mii_Do => smi_do_s,
Mii_Doe => smi_doe_s_n,
Rst => rst,
Sel => smi_sel,
nBe => smi_be_n,
nResetOut => smi_rst_n,
nWr => smi_write_n
);
mac_rx_irq_s <= not(mac_rx_irq_s_n);
s_irq <= mac_tx_irq_s or mac_rx_irq_s;
mac_write_n <= not(mac_write);
mac_be_n(1) <= not(mac_be(1));
mac_be_n(0) <= not(mac_be(0));
smi_doe_s <= not(smi_doe_s_n);
smi_write_n <= not(smi_write);
smi_be_n(1) <= not(smi_be(1));
smi_be_n(0) <= not(smi_be(0));
s_wr <= s_write and s_chipselect;
irqTable(0) <= mac_tx_irq_s;
irqTable(1) <= mac_rx_irq_s;
mac_write <= s_write;
smi_write <= s_write;
cmp_wr <= t_write and t_chipselect;
dma_req_write <= not(dma_rw) and dma_req;
dma_ack <= dma_ack_write or dma_ack_read;
s_rd <= s_read and s_chipselect;
dma_req_read <= dma_rw and dma_req;
t_waitrequest <= not(cmp_wr_ack or cmp_rd_ack);
cmp_rd <= t_read and t_chipselect;
s_waitrequest <= not(s_rd_ack or s_wr_ack);
mac_tx_irq_s <= not(mac_tx_irq_s_n);
addrdec0 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0000#,
highaddr_g => 16#03FF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selcont
);
addrdec1 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0FFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selram
);
addrdec2 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0BFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selfilter
);
addrdec3 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1000#,
highaddr_g => 16#100F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => smi_sel
);
addrdec4 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1010#,
highaddr_g => 16#101F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => irqTable_sel
);
addrdec5 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1020#,
highaddr_g => 16#102F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => dmaErr_sel
);
regack0 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => s_wr_ack,
clk => clk,
enable => s_wr,
rst => rst
);
regack1 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => s_rd_ack,
clk => clk,
enable => s_rd,
rst => rst
);
regack2 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => cmp_rd_ack,
clk => clk,
enable => cmp_rd,
rst => rst
);
regack3 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => cmp_wr_ack,
clk => clk,
enable => cmp_wr,
rst => rst
);
---- Power , ground assignment ----
VCC <= VCC_CONSTANT;
dma_be(1) <= VCC;
dma_be(0) <= VCC;
---- Terminal assignment ----
-- Output\buffer terminals
mac_rx_irq <= mac_rx_irq_s;
mac_tx_irq <= mac_tx_irq_s;
t_tog <= toggle;
---- Generate statements ----
genPhyActLed : if genPhyActLed_g generate
begin
THE_PHY_ACT : OpenMAC_phyAct
generic map (
iBlinkFreq_g => 6
)
port map(
act_led => act_led,
clk => clk,
rst => rst,
rx_dv => mac_rx_dv,
tx_en => mac_tx_en
);
end generate genPhyActLed;
genHub : if genHub_g generate
begin
THE_OPENFILTER0 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => flt0_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => flt0_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => flt0_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => flt0_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENFILTER1 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy1_rx_dat_s,
RxDatOut => flt1_rx_dat,
RxDvIn => phy1_rx_dv_s,
RxDvOut => flt1_rx_dv,
RxErr => phy1_rx_err_s,
TxDatIn => flt1_tx_dat,
TxDatOut => phy1_tx_dat_s,
TxEnIn => flt1_tx_en,
TxEnOut => phy1_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENHUB : OpenHUB
generic map (
Ports => 3
)
port map(
Clk => clk,
ReceivePort => hub_rx_port,
Rst => rst,
RxDat0 => hub_rx_dat0( 3 downto 1 ),
RxDat1 => hub_rx_dat1( 3 downto 1 ),
RxDv => hub_rx_dv( 3 downto 1 ),
TransmitMask => hub_tx_msk( 3 downto 1 ),
TxDat0 => hub_tx_dat0( 3 downto 1 ),
TxDat1 => hub_tx_dat1( 3 downto 1 ),
TxEn => hub_tx_en( 3 downto 1 ),
internPort => hub_intern_port
);
--mac tx to hub rx
hub_rx_dv(1) <= mac_tx_en;
hub_rx_dat0(1) <= mac_tx_dat(0);
hub_rx_dat1(1) <= mac_tx_dat(1);
--hub tx to mac rx
mac_rx_dv <= hub_tx_en(1);
mac_rx_dat(0) <= hub_tx_dat0(1);
mac_rx_dat(1) <= hub_tx_dat1(1);
--filter 0 to hub rx
hub_rx_dv(2) <= flt0_rx_dv;
hub_rx_dat0(2) <= flt0_rx_dat(0);
hub_rx_dat1(2) <= flt0_rx_dat(1);
--hub tx to filter 0
flt0_tx_en <= hub_tx_en(2);
flt0_tx_dat(0) <= hub_tx_dat0(2);
flt0_tx_dat(1) <= hub_tx_dat1(2);
--filter 1 to hub rx
hub_rx_dv(3) <= flt1_rx_dv;
hub_rx_dat0(3) <= flt1_rx_dat(0);
hub_rx_dat1(3) <= flt1_rx_dat(1);
--hub tx to filter 1
flt1_tx_en <= hub_tx_en(3);
flt1_tx_dat(0) <= hub_tx_dat0(3);
flt1_tx_dat(1) <= hub_tx_dat1(3);
--convert to std_logic_vector
hub_rx <= conv_std_logic_vector(hub_rx_port,hub_rx'length);
--set intern port
hub_intern_port <= 1;
--set tx mask
hub_tx_msk <= (others => '1');
end generate genHub;
genRmii2Mii0 : if not useRmii_g generate
begin
THE_MII2RMII0 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii0_rx_clk,
mRxDat => phyMii0_rx_dat,
mRxDv => phyMii0_rx_dv,
mRxEr => phyMii0_rx_err,
mTxClk => phyMii0_tx_clk,
mTxDat => phyMii0_tx_dat,
mTxEn => phyMii0_tx_en,
rRxDat => phy0_rx_dat_s,
rRxDv => phy0_rx_dv_s,
rRxEr => phy0_rx_err_s,
rTxDat => phy0_tx_dat_s,
rTxEn => phy0_tx_en_s,
rst => rst
);
end generate genRmii2Mii0;
genRmii2Mii1 : if not useRmii_g and genHub_g generate
begin
THE_MII2RMII1 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii1_rx_clk,
mRxDat => phyMii1_rx_dat,
mRxDv => phyMii1_rx_dv,
mRxEr => phyMii1_rx_err,
mTxClk => phyMii1_tx_clk,
mTxDat => phyMii1_tx_dat,
mTxEn => phyMii1_tx_en,
rRxDat => phy1_rx_dat_s,
rRxDv => phy1_rx_dv_s,
rRxEr => phy1_rx_err_s,
rTxDat => phy1_tx_dat_s,
rTxEn => phy1_tx_en_s,
rst => rst
);
end generate genRmii2Mii1;
genRmii100MegFFs : if useRmii_g generate
begin
latchRxSignals :
process (clk, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_rx_dv_s <= '0';
phy0_rx_err_s <= '0';
phy0_rx_dat_s <= (others => '0');
phy1_rx_dv_s <= '0';
phy1_rx_err_s <= '0';
phy1_rx_dat_s <= (others => '0');
elsif clk = '1' and clk'event then
phy0_rx_dv_s <= phy0_rx_dv;
phy0_rx_err_s <= phy0_rx_err;
phy0_rx_dat_s <= phy0_rx_dat;
phy1_rx_dv_s <= phy1_rx_dv;
phy1_rx_err_s <= phy1_rx_err;
phy1_rx_dat_s <= phy1_rx_dat;
end if;
end process;
latchTxSignals :
process (clkx2, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_tx_en <= '0';
phy0_tx_dat <= (others => '0');
phy1_tx_en <= '0';
phy1_tx_dat <= (others => '0');
elsif clkx2 = '0' and clkx2'event then
phy0_tx_en <= phy0_tx_en_s;
phy0_tx_dat <= phy0_tx_dat_s;
phy1_tx_en <= phy1_tx_en_s;
phy1_tx_dat <= phy1_tx_dat_s;
end if;
end process;
end generate genRmii100MegFFs;
genOneFilter : if genHub_g = false generate
begin
THE_OPENFILTER : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => mac_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => mac_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => mac_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => mac_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
end generate genOneFilter;
genPktBuf : if useIntPktBuf_g = TRUE generate
begin
g5 : if useRxIntPktBuf_g = TRUE generate
begin
dma_ack_write <= dma_ack_rw;
end generate g5;
THE_MAC_PKT_BUF : OpenMAC_DPRpackets
generic map (
memSizeLOG2_g => iPktBufSizeLog2_g,
memSize_g => iPktBufSize_g
)
port map(
address_a => dma_addr_s( iPktBufSizeLog2_g-1 downto 1 ),
address_b => pkt_address( iPktBufSizeLog2_g-3 downto 0 ),
byteena_a => dma_be,
byteena_b => pkt_byteenable,
clock_a => clk,
clock_b => pkt_clk,
data_a => dma_dout_s,
data_b => pkt_writedata,
q_a => dma_din_s,
q_b => pkt_readdata,
rden_a => read_a,
rden_b => read_b,
wren_a => write_a,
wren_b => write_b
);
read_b <= pkt_read and pkt_chipselect;
write_b <= pkt_write and pkt_chipselect;
read_a <= dma_req_read;
dma_ack_read <= dma_ack_rw;
pkt_waitrequest <= not(pkt_write_ack or pkt_read_ack);
regack4 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => pkt_write_ack,
clk => pkt_clk,
enable => write_b,
rst => rst
);
regack5 : req_ack
generic map (
ack_delay_g => 2,
zero_delay_g => false
)
port map(
ack => pkt_read_ack,
clk => pkt_clk,
enable => read_b,
rst => rst
);
--endian conversion
dma_dout_s <= dma_dout;
dma_din <= dma_din_s;
dma_addr_s(iPktBufSizeLog2_g-1 downto 1) <= dma_addr(iPktBufSizeLog2_g-1 downto 1);
--write DPR from port A only if RX data is written to DPR
write_a <= dma_req_write when useRxIntPktBuf_g = TRUE else '0';
genAck :
process (clk, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
-- declarations
begin
if rst = '1' then
dma_ack_rw <= '0';
elsif clk = '1' and clk'event then
if dma_req = '1' and dma_ack_rw = '0' then
dma_ack_rw <= '1';
else
dma_ack_rw <= '0';
end if;
end if;
end process;
end generate genPktBuf;
genDmaMaster : if not useIntPktBuf_g or (useIntPktBuf_g and not useRxIntPktBuf_g) generate
begin
genReadDmaMaster : if not useIntPktBuf_g generate
begin
dma_ack_read <= dma_ack_rd_mst;
U69_array: for U69_array_index in 0 to (dma_din'length - 1) generate
U69_array :
dma_din(U69_array_index+dma_din'Low) <= dma_din_mst(U69_array_index+dma_din_mst'Low);
end generate;
end generate genReadDmaMaster;
THE_MAC_DMA_MASTER : openMAC_DMAmaster
generic map (
dma_highadr_g => dma_highadr_g,
fifo_data_width_g => fifo_data_width_c,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_c,
gen_tx_fifo_g => gen_tx_fifo_c,
m_burstcount_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount'length,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_g => rx_fifo_word_size_c,
simulate => simulate,
tx_fifo_word_size_g => tx_fifo_word_size_c
)
port map(
dma_ack_rd => dma_ack_rd_mst,
dma_ack_wr => dma_ack_write,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_clk => clk,
dma_din => dma_din_mst,
dma_dout => dma_dout,
dma_rd_err => dma_rd_err,
dma_rd_len => dma_rd_len,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_read,
dma_req_wr => dma_req_write,
dma_wr_err => dma_wr_err,
m_address => m_address( dma_highadr_g downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( m_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( m_data_width_g-1 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( m_data_width_g-1 downto 0 ),
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst
);
end generate genDmaMaster;
genOneSmi : if gNumSmi = 1 or not genHub_g generate
begin
genOneTriStateBuf : if genSmiIO generate
begin
smi_di_s <= phy_smi_dio;
phy_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
end generate genOneTriStateBuf;
dontGenOneTriStateBuf : if not genSmiIO generate
begin
smi_di_s <= phy_smi_dio_I;
phy_smi_dio_O <= smi_do_s;
phy_smi_dio_T <= smi_doe_s_n;
end generate dontGenOneTriStateBuf;
phy_rst_n <= smi_rst_n;
phy_smi_clk <= smi_clk;
end generate genOneSmi;
genTwoSmi : if gNumSmi = 2 and genHub_g generate
begin
genTwoTriStateBuf : if genSmiIO generate
begin
phy0_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
phy1_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
smi_di_s <= phy0_smi_dio and phy1_smi_dio;
end generate genTwoTriStateBuf;
dontGenTwoTriStateBuf : if not genSmiIO generate
begin
phy1_smi_dio_T <= smi_doe_s_n;
smi_di_s <= phy0_smi_dio_I and phy1_smi_dio_I;
phy0_smi_dio_T <= smi_doe_s_n;
phy1_smi_dio_O <= smi_do_s;
phy0_smi_dio_O <= smi_do_s;
end generate dontGenTwoTriStateBuf;
phy0_smi_clk <= smi_clk;
phy0_rst_n <= smi_rst_n;
phy1_smi_clk <= smi_clk;
phy1_rst_n <= smi_rst_n;
end generate genTwoSmi;
end rtl;
| gpl-2.0 |
dphase/ctags | Test/bug2374109.vhd | 98 | 196 | function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
| gpl-2.0 |
systec-dk/openPOWERLINK_systec | Examples/ipcore/xilinx/openmac/src/ipif_master_handler.vhd | 3 | 11156 | -------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ipif_master_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
C_MAC_DMA_IPIF_NATIVE_DWIDTH : integer := 32;
C_MAC_DMA_IPIF_AWIDTH : integer := 32;
m_burstcount_width_g : integer := 4
);
port(
MAC_DMA_CLK : in std_logic;
MAC_DMA_Rst : in std_logic;
Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0';
Bus2MAC_DMA_Mst_Error : in std_logic := '0';
Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0';
Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1';
MAC_DMA2Bus_MstRd_Req : out std_logic := '0';
MAC_DMA2Bus_MstWr_Req : out std_logic := '0';
MAC_DMA2Bus_Mst_Type : out std_logic := '0';
MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_IPIF_AWIDTH-1 downto 0);
MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0);
MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_Mst_Lock : out std_logic := '0';
MAC_DMA2Bus_Mst_Reset : out std_logic := '0';
MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1';
m_read : in std_logic := '0';
m_write : in std_logic := '0';
m_byteenable : in std_logic_vector(3 downto 0);
m_address : in std_logic_vector(dma_highadr_g downto 0);
m_writedata : in std_logic_vector(31 downto 0);
m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_readdata : out std_logic_vector(31 downto 0);
m_waitrequest : out std_logic := '1';
m_readdatavalid : out std_logic := '0';
m_clk : out std_logic
);
end ipif_master_handler;
architecture rtl of ipif_master_handler is
signal clk, rst : std_logic;
--signals for requesting transfers
signal m_write_s, m_read_s, m_wrd_en_n : std_logic;
signal m_write_l, m_read_l : std_logic;
signal m_write_rise, m_read_rise : std_logic;
signal m_write_fall, m_read_fall : std_logic;
signal mst_write_req, mst_write_req_next : std_logic;
signal mst_read_req, mst_read_req_next : std_logic;
--what if master wants to req new transfer, but previous is not yet completed (= no Mst_Cmplt pulse!!!)
signal mst_done : std_logic;
--signals for the transfer
type tran_t is (idle, sof, tran, eof, seof, wait4cmplt); --seof = start/end of frame (single beat)
signal wr_tran, wr_tran_next : tran_t;
signal rd_tran : tran_t;
--avoid preset of FFs
signal MAC_DMA2Bus_MstRd_dst_rdy : std_logic;
begin
--some assignments..
m_clk <= MAC_DMA_CLK;
clk <= MAC_DMA_CLK;
rst <= MAC_DMA_Rst;
mst_done <= Bus2MAC_DMA_Mst_Cmplt;
m_write_s <= m_write and not m_wrd_en_n; --NOTE: write/read enable is low-active!
m_read_s <= m_read and not m_wrd_en_n; --NOTE: write/read enable is low-active!
--reserved
MAC_DMA2Bus_Mst_Lock <= '0';
MAC_DMA2Bus_Mst_Reset <= '0';
--delay some signals..
del_proc : process(clk, rst)
begin
if rst = '1' then
m_write_l <= '0'; m_read_l <= '0';
m_wrd_en_n <= '0'; --is low-active to avoid preset of FF
elsif rising_edge(clk) then
m_write_l <= m_write_s; m_read_l <= m_read_s;
if mst_done = '1' then
m_wrd_en_n <= '0';
elsif m_write_fall = '1' or m_read_fall = '1' then
m_wrd_en_n <= '1'; --write/read done, wait for Mst_Cmplt
end if;
end if;
end process;
--generate pulse if write/read is asserted
m_write_rise <= '1' when m_write_l = '0' and m_write_s = '1' else '0';
m_read_rise <= '1' when m_read_l = '0' and m_read_s = '1' else '0';
m_write_fall <= '1' when m_write_l = '1' and m_write_s = '0' else '0';
m_read_fall <= '1' when m_read_l = '1' and m_read_s = '0' else '0';
--generate req qualifiers
req_proc : process(clk, rst)
begin
if rst = '1' then
mst_write_req <= '0'; mst_read_req <= '0';
MAC_DMA2Bus_MstRd_dst_rdy <= '0';
elsif rising_edge(clk) then
mst_write_req <= mst_write_req_next; mst_read_req <= mst_read_req_next;
if m_read_s = '1' then
MAC_DMA2Bus_MstRd_dst_rdy <= '1';
elsif rd_tran = eof and Bus2MAC_DMA_MstRd_src_rdy_n = '0' then
MAC_DMA2Bus_MstRd_dst_rdy <= '0';
end if;
end if;
end process;
MAC_DMA2Bus_MstRd_dst_rdy_n <= not MAC_DMA2Bus_MstRd_dst_rdy;
mst_write_req_next <= '0' when mst_write_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else
'1' when mst_write_req = '0' and m_write_rise = '1' else
mst_write_req;
mst_read_req_next <= '0' when mst_read_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else
'1' when mst_read_req = '0' and m_read_rise = '1' else
mst_read_req;
MAC_DMA2Bus_MstRd_Req <= mst_read_req;
MAC_DMA2Bus_MstWr_Req <= mst_write_req;
MAC_DMA2Bus_Mst_Type <= '0' when m_burstcount < 2 else --single beat
mst_read_req or mst_write_req; --we are talking about bursts..
--assign address, byteenable and burst size
comb_addrZeroPad : process(m_address)
begin
for i in MAC_DMA2Bus_Mst_Addr'range loop
if i <= m_address'high then
MAC_DMA2Bus_Mst_Addr(i) <= m_address(i);
else
MAC_DMA2Bus_Mst_Addr(i) <= '0'; --zero padding
end if;
end loop;
end process;
--MAC_DMA2Bus_Mst_Addr <= m_address;
MAC_DMA2Bus_Mst_BE <= "1111";
MAC_DMA2Bus_Mst_Length <= conv_std_logic_vector(conv_integer(m_burstcount),
MAC_DMA2Bus_Mst_Length'length - 2) & "00"; -- dword x 4 = byte
--write/read link
wrd_proc : process(clk, rst)
begin
if rst = '1' then
wr_tran <= idle;
elsif rising_edge(clk) then
wr_tran <= wr_tran_next;
end if;
end process;
--generate fsm for write and read transfers
wr_tran_next <=
seof when wr_tran = idle and mst_write_req_next = '1' and (m_burstcount <= 1 or m_burstcount'length = 1) else
sof when wr_tran = idle and mst_write_req_next = '1' and m_burstcount'length > 1 else
eof when wr_tran = sof and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount = 2 and m_burstcount'length > 1 else
tran when wr_tran = sof and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount'length > 1 else
eof when wr_tran = tran and m_burstcounter <= 2 and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount'length > 1 else
wait4cmplt when (wr_tran = eof or wr_tran = seof) and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' else
idle when wr_tran = wait4cmplt and mst_done = '1' else
wr_tran;
rd_tran <=
seof when Bus2MAC_DMA_MstRd_sof_n = '0' and Bus2MAC_DMA_MstRd_eof_n = '0' else
sof when Bus2MAC_DMA_MstRd_sof_n = '0' else
eof when Bus2MAC_DMA_MstRd_eof_n = '0' else
tran when Bus2MAC_DMA_MstRd_src_rdy_n = '0' else
idle;
--set write qualifiers
MAC_DMA2Bus_MstWr_sof_n <= '0' when wr_tran = sof or wr_tran = seof else '1';
MAC_DMA2Bus_MstWr_eof_n <= '0' when wr_tran = eof or wr_tran = seof else '1';
MAC_DMA2Bus_MstWr_src_rdy_n <= '0' when wr_tran /= idle and wr_tran /= wait4cmplt else '1';
MAC_DMA2Bus_MstWr_src_dsc_n <= '1'; --no support
MAC_DMA2Bus_MstWr_rem <= (others => '0'); --no support
--set read qualifiers
MAC_DMA2Bus_MstRd_dst_dsc_n <= '1'; --no support
--connect ipif with avalon
m_waitrequest <= --waitrequest if not ready or no write active
not m_write when Bus2MAC_DMA_MstWr_dst_rdy_n = '0' else
not m_read when mst_read_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else '1';
m_readdatavalid <= not Bus2MAC_DMA_MstRd_src_rdy_n;
MAC_DMA2Bus_MstWr_d <= m_writedata;
m_readdata <= Bus2MAC_DMA_MstRd_d;
end rtl;
| gpl-2.0 |
systec-dk/openPOWERLINK_systec | Examples/ipcore/altera/openmac/src/openMAC_DPR.vhd | 3 | 10368 | -------------------------------------------------------------------------------
-- OpenMAC - DPR for Altera FPGA
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- 16 / 16 DPR
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity Dpr_16_16 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA, WeB : in std_logic := '0';
EnA, EnB : in std_logic := '1';
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
DoA : out std_logic_vector(15 downto 0);
BeB : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 7 downto 0);
DiB : in std_logic_vector (15 downto 0) := (others => '0');
DoB : out std_logic_vector(15 downto 0)
);
end Dpr_16_16;
architecture struct of Dpr_16_16 is
begin
Ram: COMPONENT altsyncram
GENERIC MAP ( OPERATION_MODE => "BIDIR_DUAL_PORT", INIT_FILE => "dpr_16_16.mif",
WIDTH_A => 16, WIDTHAD_A => 8, NUMWORDS_A => 256, WIDTH_BYTEENA_A => 2,
WIDTH_B => 16, WIDTHAD_B => 8, NUMWORDS_B => 256, WIDTH_BYTEENA_B => 2
)
PORT MAP(
clock0 => ClkA, clock1 => ClkB,
wren_a => WeA, wren_b => WeB,
clocken0 => EnA, clocken1 => EnB,
byteena_a => BeA, byteena_b => BeB,
address_a => AddrA, address_b => AddrB,
data_a => DiA, data_b => DiB,
q_a => DoA, q_b => DoB
);
end struct;
-------------------------------------------------------------------------------
-- 16 / 32 DPR
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity Dpr_16_32 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA : in std_logic := '0';
EnA, EnB : in std_logic := '1';
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 6 downto 0);
DoB : out std_logic_vector(31 downto 0)
);
end Dpr_16_32;
architecture struct of Dpr_16_32 is
begin
Ram: COMPONENT altsyncram
GENERIC MAP ( OPERATION_MODE => "DUAL_PORT", INIT_FILE => "dpr_16_32.mif",
WIDTH_A => 16, WIDTHAD_A => 8, NUMWORDS_A => 256, WIDTH_BYTEENA_A => 2,
WIDTH_B => 32, WIDTHAD_B => 7, NUMWORDS_B => 128
)
PORT MAP(
clock0 => ClkA, clock1 => ClkB,
wren_a => WeA,
clocken0 => EnA, clocken1 => EnB,
byteena_a => BeA,
address_a => AddrA, address_b => AddrB,
data_a => DiA,
q_b => DoB
);
end struct;
-------------------------------------------------------------------------------
-- Packet buffer
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.math_real.log2;
USE ieee.math_real.ceil;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY OpenMAC_DPRpackets IS
GENERIC
(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END OpenMAC_DPRpackets;
ARCHITECTURE SYN OF openmac_dprpackets IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
byteena_reg_b : STRING;
byte_size : NATURAL;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
rden_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rden_b : IN STD_LOGIC ;
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(15 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
byteena_reg_b => "CLOCK1",
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => memSize_g/2,
numwords_b => memSize_g/4,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => memSizeLOG2_g-1,
widthad_b => memSizeLOG2_g-2,
width_a => 16,
width_b => 32,
width_byteena_a => 2,
width_byteena_b => 4,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
byteena_a => byteena_a,
byteena_b => byteena_b,
address_a => address_a,
address_b => address_b,
rden_a => rden_a,
rden_b => rden_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
| gpl-2.0 |
sjohann81/hf-risc | mips/core_mips/alu.vhd | 1 | 1875 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port ( op1: in std_logic_vector(31 downto 0);
op2: in std_logic_vector(31 downto 0);
alu_op: in std_logic_vector(3 downto 0);
result: out std_logic_vector(31 downto 0);
zero: out std_logic;
less_than: out std_logic
);
end alu;
architecture arch_alu of alu is
signal r, shift: std_logic_vector(31 downto 0);
signal shift_op2: std_logic_vector(4 downto 0);
signal addsub: std_logic_vector(32 downto 0);
signal less, left, logical: std_logic;
begin
process(op1, op2, alu_op, addsub, less, shift_op2, shift)
begin
case alu_op is
when "0000" => r <= op1 and op2;
when "0001" => r <= op1 or op2;
when "0010" => r <= op1 xor op2;
when "0011" => r <= op1 nor op2;
when "0100" | "0101" => r <= addsub(31 downto 0);
when "0110" => r <= op2(15 downto 0) & x"0000";
when "0111" | "1000" => r <= x"0000000" & "000" & less;
when others => r <= shift;
end case;
end process;
addsub <= ('0' & op1) - ('0' & op2) when alu_op > "0100" else ('0' & op1) + ('0' & op2);
less <= addsub(32) when op1(31) = op2(31) or alu_op = "1000" else op1(31);
less_than <= less;
zero <= not (r(31) or r(30) or r(29) or r(28) or r(27) or r(26) or r(25) or r(24) or
r(23) or r(22) or r(21) or r(20) or r(19) or r(18) or r(17) or r(16) or
r(15) or r(14) or r(13) or r(12) or r(11) or r(10) or r(9) or r(8) or
r(7) or r(6) or r(5) or r(4) or r(3) or r(2) or r(1) or r(0));
shift_op2 <= op2(10 downto 6) when alu_op < "1100" else op2(4 downto 0);
left <= '1' when alu_op = "1001" or alu_op = "1100" else '0';
logical <= '0' when alu_op = "1011" or alu_op = "1110" else '1';
barrel_shifter: entity work.bshift
port map( left => left,
logical => logical,
shift => shift_op2,
input => op1,
output => shift
);
result <= r;
end arch_alu;
| gpl-2.0 |
sjohann81/hf-risc | mips/sim/ram.vhd | 2 | 1715 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
entity bram is
generic(memory_file : string := "code.txt";
data_width: integer := 8; -- data width (fixed)
address_width: integer := 16; -- address width
bank: integer := 0); -- memory bank (0,1,2,3)
port(
clk : in std_logic; --clock
addr : in std_logic_vector(address_width - 1 downto 2); --address bus
cs_n : in std_logic; --chip select
we_n : in std_logic; --write enable
data_i: in std_logic_vector(data_width - 1 downto 0); --write data bus
data_o: out std_logic_vector(data_width - 1 downto 0) --read data bus
);
end bram;
architecture memory of bram is
type ram is array(2 ** address_width -1 downto 0) of std_logic_vector(data_width - 1 downto 0);
signal ram1 : ram := (others => (others => '0'));
begin
process(clk)
variable data : std_logic_vector(data_width*4 -1 downto 0);
variable index : natural := 0;
file load_file : text open read_mode is "code.txt";
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
readline(load_file, hex_file_line);
hread(hex_file_line, data);
ram1(conv_integer(index)) <= data(((bank+1)*data_width)-1 downto bank*data_width);
index := index + 1;
end loop;
end if;
if (clk'event and clk = '1') then
if(cs_n = '0') then
if(we_n = '0') then
ram1(conv_integer(addr(address_width -1 downto 2))) <= data_i;
else
data_o <= ram1(conv_integer(addr(address_width -1 downto 2)));
end if;
end if;
end if;
end process;
end memory;
| gpl-2.0 |
jasonpeng/cg3207-proj | MEM_WB_BUFF.vhd | 1 | 2186 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:30:58 10/31/2013
-- Design Name:
-- Module Name: MEM_WB_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MEM_WB_BUFF is
Port (
IN_MemToReg : in STD_LOGIC;
IN_DataMemory_Result : in STD_LOGIC_VECTOR(31 downto 0);
IN_ALU_Result : in STD_LOGIC_VECTOR(31 downto 0);
IN_ALU_Result_2 : in STD_LOGIC_VECTOR(31 downto 0);
IN_MUL_DIV : in STD_LOGIC;
IN_REG_WriteAddr : in STD_LOGIC_VECTOR(4 downto 0);
IN_RegWrite : in STD_LOGIC;
OUT_MemToReg : out STD_LOGIC;
OUT_DataMemory_Result : out STD_LOGIC_VECTOR(31 downto 0);
OUT_ALU_Result : out STD_LOGIC_VECTOR(31 downto 0);
OUT_ALU_Result_2 : out STD_LOGIC_VECTOR(31 downto 0);
OUT_MUL_DIV : out STD_LOGIC;
OUT_REG_WriteAddr : out STD_LOGIC_VECTOR(4 downto 0);
OUT_RegWrite : out STD_LOGIC;
Clk, Reset : in std_logic
);
end MEM_WB_BUFF;
architecture Behavioral of MEM_WB_BUFF is
begin
process (Clk, Reset)
begin
if (Reset = '1') then
OUT_MemToReg <= '0';
OUT_DataMemory_Result <= (others => '0');
OUT_ALU_Result <= (others => '0');
OUT_ALU_Result_2 <= (others => '0');
OUT_MUL_DIV <= '0';
OUT_REG_WriteAddr <= (others => '0');
OUT_RegWrite <= '0';
elsif rising_edge(CLK) then
OUT_MemToReg <= IN_MemToReg;
OUT_DataMemory_Result <= IN_DataMemory_Result;
OUT_ALU_Result <= IN_ALU_Result;
OUT_ALU_Result_2 <= IN_ALU_Result_2;
OUT_MUL_DIV <= IN_MUL_DIV;
OUT_REG_WriteAddr <= IN_REG_WriteAddr;
OUT_RegWrite <= IN_RegWrite;
end if;
end process;
end Behavioral;
| gpl-2.0 |
sjohann81/hf-risc | mips/core_mips/datapath.vhd | 1 | 10898 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity datapath is
port ( clock: in std_logic;
reset: in std_logic;
stall: in std_logic;
mwait: in std_logic;
irq_vector: in std_logic_vector(31 downto 0);
irq: in std_logic;
irq_ack: out std_logic;
exception: out std_logic;
inst_addr: out std_logic_vector(31 downto 0);
inst_in: in std_logic_vector(31 downto 0);
data_addr: out std_logic_vector(31 downto 0);
data_in: in std_logic_vector(31 downto 0);
data_out: out std_logic_vector(31 downto 0);
data_w: out std_logic_vector(3 downto 0);
data_b: out std_logic;
data_h: out std_logic;
data_access: out std_logic
);
end datapath;
architecture arch_datapath of datapath is
-- datapath signals
signal inst_in_s, data_in_s, pc, pc_last, pc_plus4, pc_next, result, branch, jump, ext32, ext32b, ext32h, alu_src: std_logic_vector(31 downto 0);
signal opcode, funct: std_logic_vector(5 downto 0);
signal read_reg1, read_reg2, write_reg: std_logic_vector(4 downto 0);
signal rs, rt, rd, target: std_logic_vector(4 downto 0);
signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
signal imm: std_logic_vector(15 downto 0);
signal wreg, zero, less_than, br_link_ctl, branch_taken, jump_taken, stall_reg: std_logic;
signal irq_ack_s, irq_ack_s_dly, bds, data_access_s, data_access_s_dly: std_logic;
-- control signals
signal reg_dst_ctl, reg_write_ctl, alu_src_ctl, reg_to_mem_ctl, mem_to_reg_ctl, signed_imm_ctl, signed_rd_ctl, shift_ctl: std_logic;
signal jump_ctl, mem_read_ctl, mem_write_ctl: std_logic_vector(1 downto 0);
signal branch_ctl: std_logic_vector(2 downto 0);
signal alu_op_ctl: std_logic_vector(3 downto 0);
signal reg_dst_ctl_r, reg_write_ctl_r, alu_src_ctl_r, reg_to_mem_ctl_r, mem_to_reg_ctl_r, signed_imm_ctl_r, signed_rd_ctl_r, shift_ctl_r, br_link_ctl_r: std_logic;
signal jump_ctl_r, mem_read_ctl_r, mem_write_ctl_r: std_logic_vector(1 downto 0);
signal branch_ctl_r: std_logic_vector(2 downto 0);
signal alu_op_ctl_r: std_logic_vector(3 downto 0);
signal rs_r, rt_r, rd_r: std_logic_vector(4 downto 0);
signal imm_r: std_logic_vector(15 downto 0);
begin
--
-- FETCH STAGE
--
-- 1st stage, instruction memory access, PC update, interrupt acknowledge logic
-- program counter logic
process(clock, reset, stall_reg)
begin
if reset = '1' then
pc <= (others => '0');
pc_last <= (others => '0');
elsif clock'event and clock = '1' then
if stall = '0' then
pc <= pc_next;
pc_last <= pc;
end if;
end if;
end process;
pc_plus4 <= pc + 4;
pc_next <= irq_vector when (irq = '1' and irq_ack_s = '1') else
branch when branch_taken = '1' else
jump when jump_taken = '1' else
pc_last when data_access_s = '1' else
pc_plus4;
-- interrupt acknowledge logic
irq_ack_s <= '1' when irq = '1' and
bds = '0' and branch_taken = '0' and jump_taken = '0' and
reg_to_mem_ctl_r = '0' and mem_to_reg_ctl_r = '0' else '0';
irq_ack <= irq_ack_s_dly;
exception <= '0';
process(clock, reset, irq, irq_ack_s, mem_to_reg_ctl_r, stall, mwait)
begin
if reset = '1' then
irq_ack_s_dly <= '0';
bds <= '0';
data_access_s_dly <= '0';
stall_reg <= '0';
elsif clock'event and clock = '1' then
stall_reg <= stall;
if stall = '0' then
data_access_s_dly <= data_access_s;
if mwait = '0' then
irq_ack_s_dly <= irq_ack_s;
if branch_taken = '1' or jump_taken = '1' then
bds <= '1';
else
bds <= '0';
end if;
end if;
end if;
end if;
end process;
--
-- DECODE STAGE
--
-- 2nd stage, instruction decode, control unit operation, pipeline bubble insertion logic on load/store and 2nd branch delay slot
-- pipeline bubble insertion on loads/stores, branches and interrupts
inst_in_s <= x"00000000" when data_access_s = '1' or bds = '1' or irq_ack_s = '1' else inst_in;
-- instruction decode
opcode <= inst_in_s(31 downto 26);
rs <= inst_in_s(25 downto 21);
rt <= inst_in_s(20 downto 16);
rd <= "11111" when br_link_ctl = '1' else inst_in_s(15 downto 11); -- FIXME: this will not work for the 'jalr rd, rs' format
funct <= inst_in_s(5 downto 0);
imm <= inst_in_s(15 downto 0);
-- control unit
control_unit: entity work.control
port map( opcode => opcode,
funct => funct,
rtx => rt,
reg_dst => reg_dst_ctl,
reg_write => reg_write_ctl,
alu_src => alu_src_ctl,
alu_op => alu_op_ctl,
jump => jump_ctl,
branch => branch_ctl,
br_link => br_link_ctl,
reg_to_mem => reg_to_mem_ctl,
mem_to_reg => mem_to_reg_ctl,
signed_imm => signed_imm_ctl,
mem_write => mem_write_ctl,
mem_read => mem_read_ctl,
signed_rd => signed_rd_ctl,
shift => shift_ctl
);
process(clock, reset, stall, mwait)
begin
if reset = '1' then
rs_r <= (others => '0');
rt_r <= (others => '0');
rd_r <= (others => '0');
imm_r <= (others => '0');
reg_dst_ctl_r <= '0';
reg_write_ctl_r <= '0';
alu_src_ctl_r <= '0';
alu_op_ctl_r <= (others => '0');
jump_ctl_r <= (others => '0');
branch_ctl_r <= (others => '0');
br_link_ctl_r <= '0';
reg_to_mem_ctl_r <= '0';
mem_to_reg_ctl_r <= '0';
signed_imm_ctl_r <= '0';
mem_write_ctl_r <= "00";
mem_read_ctl_r <= "00";
signed_rd_ctl_r <= '0';
shift_ctl_r <= '0';
elsif clock'event and clock = '1' then
if stall = '0' and mwait = '0' then
rs_r <= rs;
rt_r <= rt;
rd_r <= rd;
imm_r <= imm;
reg_dst_ctl_r <= reg_dst_ctl;
reg_write_ctl_r <= reg_write_ctl;
alu_src_ctl_r <= alu_src_ctl;
alu_op_ctl_r <= alu_op_ctl;
jump_ctl_r <= jump_ctl;
branch_ctl_r <= branch_ctl;
br_link_ctl_r <= br_link_ctl;
reg_to_mem_ctl_r <= reg_to_mem_ctl;
mem_to_reg_ctl_r <= mem_to_reg_ctl;
signed_imm_ctl_r <= signed_imm_ctl;
mem_write_ctl_r <= mem_write_ctl;
mem_read_ctl_r <= mem_read_ctl;
signed_rd_ctl_r <= signed_rd_ctl;
shift_ctl_r <= shift_ctl;
end if;
end if;
end process;
--
-- EXECUTE STAGE
--
-- 3rd stage (a) register file access (read)
-- the register file
register_bank: entity work.reg_bank
port map( clock => clock,
read_reg1 => read_reg1,
read_reg2 => read_reg2,
write_reg => write_reg,
wreg => wreg,
write_data => write_data,
read_data1 => read_data1,
read_data2 => read_data2
);
-- register file read/write selection and write enable
read_reg1 <= rs_r when shift_ctl_r = '0' else rt_r; -- source for shifts or normal operations
read_reg2 <= "00000" when branch_ctl_r > "010" else -- source for branch and link (for zero operations)
rs_r when shift_ctl_r = '1' else rt_r; -- source for register based shifts or normal operations
write_reg <= target when mem_to_reg_ctl_r = '0' else rt_r;
ext32 <= x"0000" & imm_r when (imm_r(15) = '0' or signed_imm_ctl_r = '0') else x"ffff" & imm_r;
target <= rt_r when reg_dst_ctl_r = '0' else rd_r; -- target register selection
wreg <= (reg_write_ctl_r or mem_to_reg_ctl_r) and not mwait and not stall_reg; -- enable the register bank for write back also
-- 3rd stage (b) ALU operation
alu: entity work.alu
port map( op1 => read_data1,
op2 => alu_src,
alu_op => alu_op_ctl_r,
result => result,
zero => zero,
less_than => less_than
);
alu_src <= read_data2 when alu_src_ctl_r = '0' else ext32;
branch <= (ext32(29 downto 0) & "00") + pc_last;
jump <= read_data1 when jump_ctl_r = "10" else pc_last(31 downto 28) & rs_r & rt_r & imm_r & "00";
branch_taken <= '1' when (zero = '1' and branch_ctl_r = "001") or -- BEQ
(zero = '0' and branch_ctl_r = "010") or -- BNE
((zero = '1' or less_than = '1') and branch_ctl_r = "011") or -- BLEZ
((zero = '0' and less_than = '0') and branch_ctl_r = "100") or -- BGTZ
((zero = '0' and less_than = '1') and branch_ctl_r = "101") or -- BLTZ, BLTZAL
((zero = '1' or less_than = '0') and branch_ctl_r = "110") -- BGEZ, BGEZAL
else '0';
jump_taken <= '1' when jump_ctl_r /= "00" else '0'; -- J, JAL, JR, JALR
inst_addr <= pc;
data_addr <= result;
data_b <= '1' when mem_read_ctl_r = "01" or mem_write_ctl_r = "01" else '0';
data_h <= '1' when mem_read_ctl_r = "10" or mem_write_ctl_r = "10" else '0';
data_access_s <= '1' when reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' else '0';
data_access <= '1' when data_access_s = '1' and data_access_s_dly = '0' else '0';
-- 3rd stage (c) data memory / write back operation, register file access (write)
-- memory access, store operations
process(mem_write_ctl_r, result, read_data2)
begin
case mem_write_ctl_r is
when "11" => -- store word
data_out <= read_data2;
data_w <= "1111";
when "01" => -- store byte
data_out <= read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0);
case result(1 downto 0) is
when "11" => data_w <= "0001";
when "10" => data_w <= "0010";
when "01" => data_w <= "0100";
when others => data_w <= "1000";
end case;
when "10" => -- store half word
data_out <= read_data2(15 downto 0) & read_data2(15 downto 0);
case result(1) is
when '1' => data_w <= "0011";
when others => data_w <= "1100";
end case;
when others => -- WTF??
data_out <= read_data2;
data_w <= "0000";
end case;
end process;
-- memory access, load operations
process(mem_read_ctl_r, result, data_in)
begin
case mem_read_ctl_r is
when "01" => -- load byte
case result(1 downto 0) is
when "11" => data_in_s <= x"000000" & data_in(7 downto 0);
when "10" => data_in_s <= x"000000" & data_in(15 downto 8);
when "01" => data_in_s <= x"000000" & data_in(23 downto 16);
when others => data_in_s <= x"000000" & data_in(31 downto 24);
end case;
when "10" => -- load half word
case result(1) is
when '1' => data_in_s <= x"0000" & data_in(15 downto 0);
when others => data_in_s <= x"0000" & data_in(31 downto 16);
end case;
when others => -- load word
data_in_s <= data_in;
end case;
end process;
-- write back
ext32b <= x"000000" & data_in_s(7 downto 0) when (data_in_s(7) = '0' or signed_rd_ctl_r = '0') else x"ffffff" & data_in_s(7 downto 0);
ext32h <= x"0000" & data_in_s(15 downto 0) when (data_in_s(15) = '0' or signed_rd_ctl_r = '0') else x"ffff" & data_in_s(15 downto 0);
write_data <= data_in_s when mem_read_ctl_r = "11" else
ext32b when mem_read_ctl_r = "01" else
ext32h when mem_read_ctl_r = "10" else
pc when br_link_ctl_r = '1' else result;
end arch_datapath;
| gpl-2.0 |
sjohann81/hf-risc | riscv/core_rv32e/alu.vhd | 2 | 1735 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port ( op1: in std_logic_vector(31 downto 0);
op2: in std_logic_vector(31 downto 0);
alu_op: in std_logic_vector(3 downto 0);
result: out std_logic_vector(31 downto 0);
zero: out std_logic;
less_than: out std_logic
);
end alu;
architecture arch_alu of alu is
signal r, shift: std_logic_vector(31 downto 0);
signal shift_op2: std_logic_vector(4 downto 0);
signal addsub: std_logic_vector(32 downto 0);
signal less, left, logical: std_logic;
begin
process(op1, op2, alu_op, addsub, less, shift_op2, shift)
begin
case alu_op is
when "0000" => r <= op1 and op2;
when "0001" => r <= op1 or op2;
when "0010" => r <= op1 xor op2;
when "0100" | "0101" => r <= addsub(31 downto 0);
when "0110" => r <= op2;
when "0111" | "1000" => r <= x"0000000" & "000" & less;
when others => r <= shift;
end case;
end process;
addsub <= ('0' & op1) - ('0' & op2) when alu_op > "0100" else ('0' & op1) + ('0' & op2);
less <= addsub(32) when op1(31) = op2(31) or alu_op = "1000" else op1(31);
less_than <= less;
zero <= not (r(31) or r(30) or r(29) or r(28) or r(27) or r(26) or r(25) or r(24) or
r(23) or r(22) or r(21) or r(20) or r(19) or r(18) or r(17) or r(16) or
r(15) or r(14) or r(13) or r(12) or r(11) or r(10) or r(9) or r(8) or
r(7) or r(6) or r(5) or r(4) or r(3) or r(2) or r(1) or r(0));
shift_op2 <= op2(4 downto 0);
left <= '1' when alu_op(0) = '1' else '0';
logical <= '1' when alu_op(2) = '0' else '0';
barrel_shifter: entity work.bshift
port map( left => left,
logical => logical,
shift => shift_op2,
input => op1,
output => shift
);
result <= r;
end arch_alu;
| gpl-2.0 |
sjohann81/hf-risc | devices/peripherals/minimal_soc.vhd | 1 | 8804 | -- file: minimal_soc.vhd
-- description: basic SoC with peripherals
-- date: 01/2019
-- author: Sergio Johann Filho <[email protected]>
--
-- Very simple configuration for a minimal SoC. Only a single GPIO port
-- a counter and timer are included in this version.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity peripherals is
port (
clk_i: in std_logic;
rst_i: in std_logic;
addr_i: in std_logic_vector(31 downto 0);
data_i: in std_logic_vector(31 downto 0);
data_o: out std_logic_vector(31 downto 0);
sel_i: in std_logic;
wr_i: in std_logic;
irq_o: out std_logic;
gpioa_in: in std_logic_vector(7 downto 0);
gpioa_out: out std_logic_vector(7 downto 0);
gpioa_ddr: out std_logic_vector(7 downto 0)
);
end peripherals;
architecture peripherals_arch of peripherals is
signal segment: std_logic_vector(3 downto 0);
signal class: std_logic_vector(3 downto 0);
signal device: std_logic_vector(5 downto 0);
signal funct: std_logic_vector(3 downto 0);
signal paaltcfg0, s0cause, gpiocause, gpiocause_inv, gpiomask, timercause, timercause_inv, timermask: std_logic_vector(3 downto 0);
signal paddr, paout, pain, pain_inv, pain_mask: std_logic_vector(7 downto 0);
signal timer0: std_logic_vector(31 downto 0);
signal timer1, timer1_ctc, timer1_ocr: std_logic_vector(15 downto 0);
signal timer1_pre: std_logic_vector(2 downto 0);
signal timer1_set: std_logic;
signal int_gpio, int_timer: std_logic;
signal int_gpioa, int_timer1_ocr, int_timer1_ctc, tmr1_pulse, tmr1_dly, tmr1_dly2: std_logic;
signal paalt0: std_logic;
begin
segment <= addr_i(27 downto 24);
class <= addr_i(19 downto 16);
device <= addr_i(15 downto 10);
funct <= addr_i(7 downto 4);
irq_o <= '1' when s0cause /= "0000" else '0';
s0cause <= '0' & int_timer & int_gpio & '0';
int_gpio <= '1' when ((gpiocause xor gpiocause_inv) and gpiomask) /= "0000" else '0';
gpiocause <= "000" & int_gpioa;
int_gpioa <= '1' when ((pain xor pain_inv) and pain_mask) /= "0000" else '0';
int_timer <= '1' when ((timercause xor timercause_inv) and timermask) /= "0000" else '0';
timercause <= int_timer1_ocr & int_timer1_ctc & timer0(18) & timer0(16);
pain <= gpioa_in;
gpioa_out <= paout(7 downto 1) & paalt0;
gpioa_ddr <= paddr;
paalt0 <= int_timer1_ctc when paaltcfg0(1 downto 0) = "01" else int_timer1_ocr when paaltcfg0(1 downto 0) = "10" else paout(0);
-- address decoder, read from peripheral registers
process(clk_i, rst_i, segment, class, device, funct)
begin
if rst_i = '1' then
data_o <= (others => '0');
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' then
case segment is
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "000001" => -- S0CAUSE (RO)
data_o <= x"0000000" & s0cause;
when "010000" => -- PAALTCFG0 (RW)
data_o <= x"0000000" & paaltcfg0;
when others =>
data_o <= (others => '0');
end case;
when "0001" => -- GPIO
case device is
when "000001" => -- GPIOCAUSE (RO)
data_o <= x"0000000" & gpiocause;
when "000010" => -- GPIOCAUSE_INV (RW)
data_o <= x"0000000" & gpiocause_inv;
when "000011" => -- GPIOMASK (RW)
data_o <= x"0000000" & gpiomask;
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
data_o <= x"000000" & paddr;
when "0001" => -- PAOUT (RW)
data_o <= x"000000" & paout;
when "0010" => -- PAIN (RO)
data_o <= x"000000" & pain;
when "0011" => -- PAIN_INV (RW)
data_o <= x"000000" & pain_inv;
when "0100" => -- PAIN_MASK (RW)
data_o <= x"000000" & pain_mask;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when "0010" => -- timers
case device is
when "000001" => -- TIMERCAUSE (RO)
data_o <= x"0000000" & timercause;
when "000010" => -- TIMERCAUSE_INV (RW)
data_o <= x"0000000" & timercause_inv;
when "000011" => -- TIMERMASK (RW)
data_o <= x"0000000" & timermask;
when "010000" => -- TIMER0 (RO)
data_o <= timer0;
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
data_o <= x"0000" & timer1;
when "0001" => -- TIMER1_PRE (RW)
data_o <= x"0000000" & '0' & timer1_pre;
when "0010" => -- TIMER1_CTC (RW)
data_o <= x"0000" & timer1_ctc;
when "0011" => -- TIMER1_OCR (RW)
data_o <= x"0000" & timer1_ocr;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
end if;
end if;
end process;
-- peripheral register logic, write to peripheral registers
process(clk_i, rst_i, segment, class, device, funct, tmr1_pulse)
begin
if rst_i = '1' then
paaltcfg0 <= (others => '0');
gpiocause_inv <= (others => '0');
gpiomask <= (others => '0');
paout <= (others => '0');
pain_inv <= (others => '0');
pain_mask <= (others => '0');
paddr <= (others => '0');
timercause_inv <= (others => '0');
timermask <= (others => '0');
timer0 <= (others => '0');
timer1 <= (others => '0');
timer1_set <= '0';
timer1_pre <= (others => '0');
timer1_ctc <= (others => '1');
timer1_ocr <= (others => '0');
int_timer1_ctc <= '0';
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' and wr_i = '1' then
case segment is
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "010000" => -- PAALTCFG0 (RW)
paaltcfg0 <= data_i(3 downto 0);
when others =>
end case;
when "0001" => -- GPIO
case device is
when "000010" => -- GPIOCAUSE_INV (RW)
gpiocause_inv <= data_i(3 downto 0);
when "000011" => -- GPIOMASK (RW)
gpiomask <= data_i(3 downto 0);
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
paddr <= data_i(7 downto 0);
when "0001" => -- PAOUT (RW)
paout <= data_i(7 downto 0);
when "0011" => -- PAIN_INV (RW)
pain_inv <= data_i(7 downto 0);
when "0100" => -- PAIN_MASK (RW)
pain_mask <= data_i(7 downto 0);
when others =>
end case;
when others =>
end case;
when "0010" => -- timers
case device is
when "000010" => -- TIMERCAUSE_INV (RW)
timercause_inv <= data_i(3 downto 0);
when "000011" => -- TIMERMASK (RW)
timermask <= data_i(3 downto 0);
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
if data_i(31) = '1' then
timer1_set <= '1';
end if;
if timer1_set = '1' then
timer1 <= data_i(15 downto 0);
timer1_set <= '0';
end if;
when "0001" => -- TIMER1_PRE (RW)
timer1_pre <= data_i(2 downto 0);
when "0010" => -- TIMER1_CTC (RW)
timer1_ctc <= data_i(15 downto 0);
when "0011" => -- TIMER1_OCR (RW)
timer1_ocr <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when others =>
end case;
when others =>
end case;
end if;
timer0 <= timer0 + 1;
if tmr1_pulse = '1' then
if (timer1 /= timer1_ctc) then
if timer1_set = '0' then
timer1 <= timer1 + 1;
end if;
else
int_timer1_ctc <= not int_timer1_ctc;
timer1 <= (others => '0');
end if;
end if;
end if;
end process;
process(clk_i, rst_i) -- TIMER1 prescaler
begin
if rst_i = '1' then
tmr1_dly <= '0';
tmr1_dly2 <= '0';
elsif clk_i'event and clk_i = '1' then
case timer1_pre is
when "001" =>
tmr1_dly <= timer0(2); -- /4
when "010" =>
tmr1_dly <= timer0(4); -- /16
when "011" =>
tmr1_dly <= timer0(6); -- /64
when "100" =>
tmr1_dly <= timer0(8); -- /256
when "101" =>
tmr1_dly <= timer0(10); -- /1024
when "110" =>
tmr1_dly <= timer0(12); -- /4096
when "111" =>
tmr1_dly <= timer0(14); -- /16384
when others =>
tmr1_dly <= timer0(0); -- /1
end case;
tmr1_dly2 <= tmr1_dly;
end if;
end process;
tmr1_pulse <= '1' when tmr1_dly /= tmr1_dly2 else '0';
int_timer1_ocr <= '1' when timer1 < timer1_ocr else '0';
end peripherals_arch;
| gpl-2.0 |
sjohann81/hf-risc | riscv/platform/virtex4_ml403/virtex4ml403.vhd | 1 | 4854 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
begin
-- clock divider (50MHz clock from 100MHz main clock for ML403 kit)
process (reset_in, clk_in, clock)
begin
if reset_in = '1' then
clock <= '0';
else
if clk_in'event and clk_in='1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, reset_in)
begin
if (reset_in = '0') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
gpioa_in(3) <= uart_read;
uart_write <= gpioa_out(2);
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
| gpl-2.0 |
sjohann81/hf-risc | riscv/platform/spartan3_starterkit/spartan3_SRAM.vhd | 1 | 5234 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt";
uart_support : string := "yes"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
int_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic;
extio_in: in std_logic_vector(7 downto 0);
extio_out: out std_logic_vector(7 downto 0);
ram_address: out std_logic_vector(31 downto 2);
ram_data: inout std_logic_vector(31 downto 0);
ram_ce1_n: out std_logic;
ram_ub1_n: out std_logic;
ram_lb1_n: out std_logic;
ram_ce2_n: out std_logic;
ram_ub2_n: out std_logic;
ram_lb2_n: out std_logic;
ram_we_n: out std_logic;
ram_oe_n: out std_logic
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, stall_cpu, irq_cpu, irq_ack_cpu, exception_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal data_we, data_w_cpu: std_logic_vector(3 downto 0);
signal we_n_next : std_logic;
signal we_n_reg : std_logic;
signal data_reg : std_logic_vector(31 downto 0);
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (reset_in, clk_in, clock, we_n_next)
begin
if reset_in = '1' then
clock <= '0';
else
if clk_in'event and clk_in='1' then
clock <= not clock;
end if;
end if;
if reset_in = '1' then
we_n_reg <= '1';
elsif rising_edge(clk_in) then
we_n_reg <= we_n_next or not clock;
end if;
if reset_in = '1' then
data_read_ram <= (others => '0');
elsif rising_edge(clock) then
data_read_ram <= ram_data;
end if;
end process;
-- reset synchronizer
process (clock, reset_in)
begin
if (reset_in = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
data_read <= data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
-- HF-RISC core
core: entity work.datapath
port map( clock => clock,
reset => reset,
stall => stall_cpu,
irq_vector => irq_vector_cpu,
irq => irq_cpu,
irq_ack => irq_ack_cpu,
exception => exception_cpu,
address => address_cpu,
data_in => data_in_cpu,
data_out => data_out_cpu,
data_w => data_w_cpu,
data_access => data_access_cpu
);
-- peripherals / busmux logic
peripherals_busmux: entity work.busmux
generic map(
uart_support => uart_support
)
port map(
clock => clock,
reset => reset,
stall => stall,
stall_cpu => stall_cpu,
irq_vector_cpu => irq_vector_cpu,
irq_cpu => irq_cpu,
irq_ack_cpu => irq_ack_cpu,
exception_cpu => exception_cpu,
address_cpu => address_cpu,
data_in_cpu => data_in_cpu,
data_out_cpu => data_out_cpu,
data_w_cpu => data_w_cpu,
data_access_cpu => data_access_cpu,
addr_mem => address,
data_read_mem => data_read,
data_write_mem => data_write,
data_we_mem => data_we,
extio_in => extio_in,
extio_out => extio_out,
uart_read => uart_read,
uart_write => uart_write
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external SRAM)
-- very simple SRAM memory controller using both IS61LV25616AL chips.
-- these SRAMs have 16-bit words, so we use both chips and access each using low and
-- high banks. using this arrangement, we have byte addressable 32-bit words.
-- the address bus is controlled directly by the CPU.
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
ram_address <= address(31 downto 2);
ram_we_n <= we_n_reg;
ram_control:
process(clock, ram_enable_n, data_we, data_write)
begin
if ram_enable_n = '0' then --SRAM
ram_ce1_n <= '0';
ram_ce2_n <= '0';
if data_we = "0000" then -- read
ram_data <= (others => 'Z');
ram_ub1_n <= '0';
ram_lb1_n <= '0';
ram_ub2_n <= '0';
ram_lb2_n <= '0';
we_n_next <= '1';
ram_oe_n <= '0';
else -- write
if clock = '1' then
ram_data <= (others => 'Z');
else
ram_data <= data_write;
end if;
ram_ub1_n <= not data_we(3);
ram_lb1_n <= not data_we(2);
ram_ub2_n <= not data_we(1);
ram_lb2_n <= not data_we(0);
we_n_next <= '0';
ram_oe_n <= '1';
end if;
else
ram_data <= (others => 'Z');
ram_ce1_n <= '1';
ram_ub1_n <= '1';
ram_lb1_n <= '1';
ram_ce2_n <= '1';
ram_ub2_n <= '1';
ram_lb2_n <= '1';
we_n_next <= '1';
ram_oe_n <= '1';
end if;
end process;
end top_level;
| gpl-2.0 |
sjohann81/hf-risc | riscv/core_rv32i/bshifter.vhd | 4 | 1568 | library ieee;
use ieee.std_logic_1164.all;
entity bshift is
port ( left: in std_logic; -- '1' for left, '0' for right
logical: in std_logic; -- '1' for logical, '0' for arithmetic
shift: in std_logic_vector(4 downto 0); -- shift count
input: in std_logic_vector (31 downto 0);
output: out std_logic_vector (31 downto 0)
);
end entity bshift;
architecture logic of bshift is
signal shift1l, shift2l, shift4l, shift8l, shift16l : std_logic_vector(31 downto 0);
signal shift1r, shift2r, shift4r, shift8r, shift16r : std_logic_vector(31 downto 0);
signal fill : std_logic_vector(31 downto 16);
begin
fill <= (others => input(31)) when logical = '0' else x"0000";
shift1l <= input(30 downto 0) & '0' when shift(0) = '1' else input;
shift2l <= shift1l(29 downto 0) & "00" when shift(1) = '1' else shift1l;
shift4l <= shift2l(27 downto 0) & x"0" when shift(2) = '1' else shift2l;
shift8l <= shift4l(23 downto 0) & x"00" when shift(3) = '1' else shift4l;
shift16l <= shift8l(15 downto 0) & x"0000" when shift(4) = '1' else shift8l;
shift1r <= fill(31) & input(31 downto 1) when shift(0) = '1' else input;
shift2r <= fill(31 downto 30) & shift1r(31 downto 2) when shift(1) = '1' else shift1r;
shift4r <= fill(31 downto 28) & shift2r(31 downto 4) when shift(2) = '1' else shift2r;
shift8r <= fill(31 downto 24) & shift4r(31 downto 8) when shift(3) = '1' else shift4r;
shift16r <= fill(31 downto 16) & shift8r(31 downto 16) when shift(4) = '1' else shift8r;
output <= shift16r when left = '0' else shift16l;
end;
| gpl-2.0 |
sjohann81/hf-risc | mips/core_mips/bshifter.vhd | 4 | 1568 | library ieee;
use ieee.std_logic_1164.all;
entity bshift is
port ( left: in std_logic; -- '1' for left, '0' for right
logical: in std_logic; -- '1' for logical, '0' for arithmetic
shift: in std_logic_vector(4 downto 0); -- shift count
input: in std_logic_vector (31 downto 0);
output: out std_logic_vector (31 downto 0)
);
end entity bshift;
architecture logic of bshift is
signal shift1l, shift2l, shift4l, shift8l, shift16l : std_logic_vector(31 downto 0);
signal shift1r, shift2r, shift4r, shift8r, shift16r : std_logic_vector(31 downto 0);
signal fill : std_logic_vector(31 downto 16);
begin
fill <= (others => input(31)) when logical = '0' else x"0000";
shift1l <= input(30 downto 0) & '0' when shift(0) = '1' else input;
shift2l <= shift1l(29 downto 0) & "00" when shift(1) = '1' else shift1l;
shift4l <= shift2l(27 downto 0) & x"0" when shift(2) = '1' else shift2l;
shift8l <= shift4l(23 downto 0) & x"00" when shift(3) = '1' else shift4l;
shift16l <= shift8l(15 downto 0) & x"0000" when shift(4) = '1' else shift8l;
shift1r <= fill(31) & input(31 downto 1) when shift(0) = '1' else input;
shift2r <= fill(31 downto 30) & shift1r(31 downto 2) when shift(1) = '1' else shift1r;
shift4r <= fill(31 downto 28) & shift2r(31 downto 4) when shift(2) = '1' else shift2r;
shift8r <= fill(31 downto 24) & shift4r(31 downto 8) when shift(3) = '1' else shift4r;
shift16r <= fill(31 downto 16) & shift8r(31 downto 16) when shift(4) = '1' else shift8r;
output <= shift16r when left = '0' else shift16l;
end;
| gpl-2.0 |
sjohann81/hf-risc | mips/core_mips/control.vhd | 1 | 17876 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port ( opcode: in std_logic_vector(5 downto 0);
rtx: in std_logic_vector(4 downto 0);
funct: in std_logic_vector(5 downto 0);
reg_dst: out std_logic;
reg_write: out std_logic;
alu_src: out std_logic;
alu_op: out std_logic_vector(3 downto 0);
jump: out std_logic_vector(1 downto 0);
branch: out std_logic_vector(2 downto 0);
br_link: out std_logic;
reg_to_mem: out std_logic;
mem_to_reg: out std_logic;
signed_imm: out std_logic;
mem_write: out std_logic_vector(1 downto 0);
mem_read: out std_logic_vector(1 downto 0);
signed_rd: out std_logic;
shift: out std_logic
);
end control;
architecture arch_control of control is
begin
process(opcode, funct, rtx)
begin
case opcode is
when "000000" => -- R type
case funct is
when "000000" => -- SLL
reg_dst <= '1';
reg_write <= '1';
alu_src <= '1';
alu_op <= "1001";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "000010" => -- SRL
reg_dst <= '1';
reg_write <= '1';
alu_src <= '1';
alu_op <= "1010";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "000011" => -- SRA
reg_dst <= '1';
reg_write <= '1';
alu_src <= '1';
alu_op <= "1011";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "000100" => -- SLLV
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "1100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "000110" => -- SRLV
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "1101";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "000111" => -- SRAV
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "1110";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "001000" => -- JR
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0100";
jump <= "10";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001001" => -- JALR
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0100";
jump <= "10";
branch <= "000";
br_link <= '1';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "001100" => -- SYSCALL
-- when "001101" => -- BREAK
-- when "010000" => -- MFHI
-- when "010001" => -- MTHI
-- when "010010" => -- MFLO
-- when "010011" => -- MTLO
-- when "011000" => -- MULT
-- when "011001" => -- MULTU
-- when "011010" => -- DIV
-- when "011011" => -- DIVU
-- when "100000" => -- ADD
when "100001" => -- ADDU
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "100010" => -- SUB
when "100011" => -- SUBU
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "100100" => -- AND
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0000";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "100101" => -- OR
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0001";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "100110" => -- XOR
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0010";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "100111" => -- NOR
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0011";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "101010" => -- SLT
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0111";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "101011" => -- SLTU
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "1000";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when others => -- all other R type instructions, generate a NOP
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0000";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
end case;
when "000001" =>
case rtx is
when "00000" => -- BLTZ
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "101";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "00001" => -- BGEZ
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "110";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "10000" => -- BLTZAL
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "101";
br_link <= '1';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "10001" => -- BGEZAL
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "110";
br_link <= '1';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when others => -- invalid instruction, generate a NOP
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
end case;
when "000010" => -- J
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0100";
jump <= "01";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "000011" => -- JAL
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0100";
jump <= "01";
branch <= "000";
br_link <= '1';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "000100" => -- BEQ
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "001";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "000101" => -- BNE
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "010";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "000110" => -- BLEZ
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "011";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "000111" => -- BGTZ
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "100";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "001000" => -- ADDI
when "001001" => -- ADDIU
reg_dst <= '0';
reg_write <= '1';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001010" => -- SLTI
reg_dst <= '0';
reg_write <= '1';
alu_src <= '1';
alu_op <= "0111";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001011" => -- SLTIU
reg_dst <= '0';
reg_write <= '1';
alu_src <= '1';
alu_op <= "1000";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001100" => -- ANDI
reg_dst <= '0';
reg_write <= '1';
alu_src <= '1';
alu_op <= "0000";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001101" => -- ORI
reg_dst <= '0';
reg_write <= '1';
alu_src <= '1';
alu_op <= "0001";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001110" => -- XORI
reg_dst <= '0';
reg_write <= '1';
alu_src <= '1';
alu_op <= "0010";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001111" => -- LUI
reg_dst <= '0';
reg_write <= '1';
alu_src <= '1';
alu_op <= "0110";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "010000" => -- COP0
-- when "010001" => -- COP1
-- when "010010" => -- COP2
-- when "010011" => -- COP3
when "100000" => -- LB
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '1';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "01";
signed_rd <= '1';
shift <= '0';
when "100001" => -- LH
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '1';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "10";
signed_rd <= '1';
shift <= '0';
-- when "100010" => -- LWL
when "100011" => -- LW
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '1';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "11";
signed_rd <= '0';
shift <= '0';
when "100100" => -- LBU
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '1';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "01";
signed_rd <= '0';
shift <= '0';
when "100101" => -- LHU
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '1';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "10";
signed_rd <= '0';
shift <= '0';
-- when "100110" => -- LWR
when "101000" => -- SB
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '1';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "01";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "101001" => -- SH
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '1';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "10";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "101010" => -- SWL
when "101011" => -- SW
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '1';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "11";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "101110" => -- SWR
-- when "110000" => -- LWC0
-- when "110001" => -- LWC1
-- when "110010" => -- LWC2
-- when "110011" => -- LWC3
-- when "111000" => -- SWC0
-- when "111001" => -- SWC1
-- when "111010" => -- SWC2
-- when "111011" => -- SWC3
when others => -- invalid instruction, generate a NOP
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
end case;
end process;
end arch_control;
| gpl-2.0 |
sjohann81/hf-risc | riscv/core_rv32e/cpu.vhd | 3 | 2184 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity processor is
port ( clk_i: in std_logic;
rst_i: in std_logic;
stall_i: in std_logic;
addr_o: out std_logic_vector(31 downto 0);
data_i: in std_logic_vector(31 downto 0);
data_o: out std_logic_vector(31 downto 0);
data_w_o: out std_logic_vector(3 downto 0);
data_mode_o: out std_logic_vector(2 downto 0);
extio_in: in std_logic_vector(7 downto 0);
extio_out: out std_logic_vector(7 downto 0)
);
end processor;
architecture arch_processor of processor is
signal stall_cpu, mwait_cpu, irq_cpu, irq_ack_cpu, exception_cpu, data_b_cpu, data_h_cpu, data_access_cpu: std_logic;
signal irq_vector_cpu, inst_addr_cpu, inst_in_cpu, data_addr_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal data_w_cpu: std_logic_vector(3 downto 0);
begin
data_mode_o <= data_b_cpu & data_h_cpu & data_access_cpu;
-- HF-RISC core
core: entity work.datapath
port map( clock => clk_i,
reset => rst_i,
stall => stall_cpu,
mwait => mwait_cpu,
irq_vector => irq_vector_cpu,
irq => irq_cpu,
irq_ack => irq_ack_cpu,
exception => exception_cpu,
inst_addr => inst_addr_cpu,
inst_in => inst_in_cpu,
data_addr => data_addr_cpu,
data_in => data_in_cpu,
data_out => data_out_cpu,
data_w => data_w_cpu,
data_b => data_b_cpu,
data_h => data_h_cpu,
data_access => data_access_cpu
);
-- interrupt controller
int_control: entity work.interrupt_controller
port map(
clock => clk_i,
reset => rst_i,
stall => stall_i,
stall_cpu => stall_cpu,
mwait_cpu => mwait_cpu,
irq_vector_cpu => irq_vector_cpu,
irq_cpu => irq_cpu,
irq_ack_cpu => irq_ack_cpu,
exception_cpu => exception_cpu,
inst_addr_cpu => inst_addr_cpu,
inst_in_cpu => inst_in_cpu,
data_addr_cpu => data_addr_cpu,
data_in_cpu => data_in_cpu,
data_out_cpu => data_out_cpu,
data_w_cpu => data_w_cpu,
data_access_cpu => data_access_cpu,
addr_mem => addr_o,
data_read_mem => data_i,
data_write_mem => data_o,
data_we_mem => data_w_o,
extio_in => extio_in,
extio_out => extio_out
);
end arch_processor;
| gpl-2.0 |
jasonpeng/cg3207-proj | Mem_test.vhd | 1 | 4559 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:19:59 10/31/2013
-- Design Name:
-- Module Name: D:/AY1314/CG3207/Lab3/MEM_TEST.vhd
-- Project Name: Lab3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DataMemory
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MEM_TEST IS
END MEM_TEST;
ARCHITECTURE behavior OF MEM_TEST IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DataMemory
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
MEM_MemWrite : IN std_logic;
MEM_MemToReg : IN std_logic;
MEM_MemRead : IN std_logic;
MEM_Branch : IN std_logic;
MEM_OVF : IN std_logic;
MEM_Zero : IN std_logic;
MEM_ALU_Result : IN std_logic_vector(31 downto 0);
MEM_BEQ_Addr : IN std_logic_vector(31 downto 0);
MEM_Data2 : IN std_logic_vector(31 downto 0);
MEM_REG_WriteAddr : IN std_logic_vector(4 downto 0);
WB_PCSrc : OUT std_logic;
WB_Data : OUT std_logic_vector(31 downto 0);
WB_ALU_Result : OUT std_logic_vector(31 downto 0);
WB_BEQ_Addr : OUT std_logic_vector(31 downto 0);
WB_REG_WriteAddr : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
signal MEM_MemWrite : std_logic := '0';
signal MEM_MemToReg : std_logic := '0';
signal MEM_MemRead : std_logic := '0';
signal MEM_Branch : std_logic := '0';
signal MEM_OVF : std_logic := '0';
signal MEM_Zero : std_logic := '0';
signal MEM_ALU_Result : std_logic_vector(31 downto 0) := (others => '0');
signal MEM_BEQ_Addr : std_logic_vector(31 downto 0) := (others => '0');
signal MEM_Data2 : std_logic_vector(31 downto 0) := (others => '0');
signal MEM_REG_WriteAddr : std_logic_vector(4 downto 0) := (others => '0');
--Outputs
signal WB_PCSrc : std_logic;
signal WB_Data : std_logic_vector(31 downto 0);
signal WB_ALU_Result : std_logic_vector(31 downto 0);
signal WB_BEQ_Addr : std_logic_vector(31 downto 0);
signal WB_REG_WriteAddr : std_logic_vector(4 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DataMemory PORT MAP (
CLK => CLK,
RESET => RESET,
MEM_MemWrite => MEM_MemWrite,
MEM_MemToReg => MEM_MemToReg,
MEM_MemRead => MEM_MemRead,
MEM_Branch => MEM_Branch,
MEM_OVF => MEM_OVF,
MEM_Zero => MEM_Zero,
MEM_ALU_Result => MEM_ALU_Result,
MEM_BEQ_Addr => MEM_BEQ_Addr,
MEM_Data2 => MEM_Data2,
MEM_REG_WriteAddr => MEM_REG_WriteAddr,
WB_PCSrc => WB_PCSrc,
WB_Data => WB_Data,
WB_ALU_Result => WB_ALU_Result,
WB_BEQ_Addr => WB_BEQ_Addr,
WB_REG_WriteAddr => WB_REG_WriteAddr
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period;
-- insert stimulus here
-- read from address 0x4
MEM_MemRead <= '1';
MEM_MemWrite <= '0';
MEM_ALU_Result <= X"00000004";
wait until rising_edge(CLK);
-- write 0xe to address 0x4
MEM_MemRead <= '0';
MEM_MemWrite <= '1';
MEM_ALU_Result <= X"00000004";
MEM_Data2 <= X"0000000E";
wait until rising_edge(CLK);
-- read again from address 0x4
MEM_MemRead <= '1';
MEM_MemWrite <= '0';
MEM_ALU_Result <= X"00000004";
wait;
end process;
END;
| gpl-2.0 |
jasonpeng/cg3207-proj | ALU/AddSub.vhd | 1 | 3556 | library ieee;
use ieee.std_logic_1164.all;
entity addsub_lookahead is
Port ( Control : in STD_LOGIC_VECTOR ( 2 downto 0);
Operand1 : in STD_LOGIC_VECTOR (31 downto 0);
Operand2 : in STD_LOGIC_VECTOR (31 downto 0);
Result1 : out STD_LOGIC_VECTOR (31 downto 0);
Result2 : out STD_LOGIC_VECTOR (31 downto 0);
Debug : out STD_LOGIC_VECTOR (27 downto 0));
end addsub_lookahead;
architecture beh_addsub_lookahead of addsub_lookahead is
component adder_lookahead_4
Port (
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
SUM : out STD_LOGIC_VECTOR (3 downto 0);
Cout: out STD_LOGIC
);
end component;
signal Cin: STD_LOGIC;
signal C: STD_LOGIC_VECTOR(7 downto 0);
signal OP2: STD_LOGIC_VECTOR(31 downto 0);
signal buffer1: STD_LOGIC_VECTOR(31 downto 0);
begin
L0: adder_lookahead_4 port map(Operand1(3 downto 0), OP2(3 downto 0), Cin, buffer1(3 downto 0), C(0));
L1: adder_lookahead_4 port map(Operand1(7 downto 4), OP2(7 downto 4), C(0), buffer1(7 downto 4), C(1));
L2: adder_lookahead_4 port map(Operand1(11 downto 8), OP2(11 downto 8), C(1), buffer1(11 downto 8), C(2));
L3: adder_lookahead_4 port map(Operand1(15 downto 12), OP2(15 downto 12), C(2), buffer1(15 downto 12), C(3));
L4: adder_lookahead_4 port map(Operand1(19 downto 16), OP2(19 downto 16), C(3), buffer1(19 downto 16), C(4));
L5: adder_lookahead_4 port map(Operand1(23 downto 20), OP2(23 downto 20), C(4), buffer1(23 downto 20), C(5));
L6: adder_lookahead_4 port map(Operand1(27 downto 24), OP2(27 downto 24), C(5), buffer1(27 downto 24), C(6));
L7: adder_lookahead_4 port map(Operand1(31 downto 28), OP2(31 downto 28), C(6), buffer1(31 downto 28), C(7));
Result1 <= buffer1;
Result2 <= (others => '0');
process (Control, Operand1, Operand2, C, buffer1)
variable O : STD_LOGIC := '0';
variable operand_same_sign : STD_LOGIC := '0';
variable result_diff_sign : STD_LOGIC := '0';
begin
if (Control(1) = '1') then
Cin <= '1';
OP2 <= NOT Operand2;
else
Cin <= '0';
OP2 <= Operand2;
end if;
if (Control(0) = '0') then
operand_same_sign := NOT (Operand1(31) XOR Operand2(31));
result_diff_sign := Operand1(31) XOR buffer1(31);
O := operand_same_sign and result_diff_sign;
Debug <= X"0000" & "000" & O & C; -- add, sub with overflow trap/flag
else
Debug <= X"00000" & C; --addu, subu
end if;
end process;
end beh_addsub_lookahead;
--- lookahead entity
library ieee;
use ieee.std_logic_1164.all;
entity adder_lookahead_4 is
Port (
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin: in STD_LOGIC;
SUM : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC
);
end adder_lookahead_4;
architecture beh_adder_lookahead_4 of adder_lookahead_4 is
begin
process (A, B, Cin)
variable G : STD_LOGIC_VECTOR (3 downto 0);
variable P : STD_LOGIC_VECTOR (3 downto 0);
variable C: STD_LOGIC_VECTOR (4 downto 0);
begin
G := A AND B;
P := A OR B;
C(0) := Cin;
C(1) := G(0) OR (P(0) AND C(0));
C(2) := G(1) OR (G(0) AND P(1)) OR (C(0) AND P(0) AND P(1));
C(3) := G(2) OR (G(1) AND P(2)) OR (G(0) AND P(1) AND P(2)) OR (C(0) AND P(0) AND P(1) AND P(2));
C(4) := G(3) OR (G(2) AND P(3)) OR (G(1) AND P(2) AND P(3)) OR (G(0) AND P(1) AND P(2) AND P(3)) OR (C(0) AND P(0) AND P(1) AND P(2) AND P(3));
Sum <= (A(3) xor B(3) xor C(3)) & (A(2) xor B(2) xor C(2)) & (A(1) xor B(1) xor C(1)) & (A(0) xor B(0) xor C(0));
Cout <= C(4);
end process;
end beh_adder_lookahead_4; | gpl-2.0 |
sjohann81/hf-risc | devices/peripherals/basic_soc.vhd | 1 | 13162 | -- file: basic_soc.vhd
-- description: basic SoC with peripherals
-- date: 07/2019
-- author: Sergio Johann Filho <[email protected]>
--
-- Basic SoC configuration template for prototyping. Dual GPIO ports,
-- a counter, a timer and a UART are included in this version.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity peripherals is
port (
clk_i: in std_logic;
rst_i: in std_logic;
addr_i: in std_logic_vector(31 downto 0);
data_i: in std_logic_vector(31 downto 0);
data_o: out std_logic_vector(31 downto 0);
sel_i: in std_logic;
wr_i: in std_logic;
irq_o: out std_logic;
gpioa_in: in std_logic_vector(15 downto 0);
gpioa_out: out std_logic_vector(15 downto 0);
gpioa_ddr: out std_logic_vector(15 downto 0);
gpiob_in: in std_logic_vector(15 downto 0);
gpiob_out: out std_logic_vector(15 downto 0);
gpiob_ddr: out std_logic_vector(15 downto 0)
);
end peripherals;
architecture peripherals_arch of peripherals is
signal segment: std_logic_vector(3 downto 0);
signal class: std_logic_vector(3 downto 0);
signal device: std_logic_vector(5 downto 0);
signal funct: std_logic_vector(3 downto 0);
signal paaltcfg0: std_logic_vector(23 downto 0);
signal s0cause, gpiocause, gpiocause_inv, gpiomask, timercause, timercause_inv, timermask: std_logic_vector(3 downto 0);
signal paddr, paout, pain, pain_inv, pain_mask: std_logic_vector(15 downto 0);
signal pbddr, pbout, pbin, pbin_inv, pbin_mask: std_logic_vector(15 downto 0);
signal timer0: std_logic_vector(31 downto 0);
signal timer1, timer1_ctc, timer1_ocr: std_logic_vector(15 downto 0);
signal timer1_pre: std_logic_vector(2 downto 0);
signal timer1_set: std_logic;
signal int_gpio, int_timer: std_logic;
signal int_gpioa, int_gpiob, int_timer1_ocr, int_timer1_ctc, tmr1_pulse, tmr1_dly, tmr1_dly2: std_logic;
signal paalt0, paalt2, paalt8, paalt10: std_logic;
signal int_uart, uart0_tx, uart0_rx, uart0_enable_w, uart0_enable_r, uart0_write_busy, uart0_data_avail: std_logic;
signal uartcause, uartcause_inv, uartmask: std_logic_vector(3 downto 0);
signal uart0_data_read, uart0_data_write: std_logic_vector(7 downto 0);
signal uart0_divisor: std_logic_vector(15 downto 0);
begin
segment <= addr_i(27 downto 24);
class <= addr_i(19 downto 16);
device <= addr_i(15 downto 10);
funct <= addr_i(7 downto 4);
irq_o <= '1' when s0cause /= "0000" else '0';
s0cause <= int_uart & int_timer & int_gpio & '0';
int_gpio <= '1' when ((gpiocause xor gpiocause_inv) and gpiomask) /= "0000" else '0';
gpiocause <= "00" & int_gpiob & int_gpioa;
int_gpioa <= '1' when ((pain xor pain_inv) and pain_mask) /= "0000" else '0';
int_gpiob <= '1' when ((pbin xor pbin_inv) and pbin_mask) /= "0000" else '0';
int_timer <= '1' when ((timercause xor timercause_inv) and timermask) /= "0000" else '0';
timercause <= int_timer1_ocr & int_timer1_ctc & timer0(18) & timer0(16);
pain <= gpioa_in(15 downto 0);
gpioa_out <= paout(15 downto 11) & paalt10 & paout(9) & paalt8 & paout(7 downto 3) & paalt2 & paout(1) & paalt0;
gpioa_ddr <= paddr;
pbin <= gpiob_in(15 downto 0);
gpiob_out <= pbout;
gpiob_ddr <= pbddr;
int_uart <= '1' when ((uartcause xor uartcause_inv) and uartmask) /= "0000" else '0';
uartcause <= "00" & uart0_write_busy & uart0_data_avail;
paalt0 <= int_timer1_ctc when paaltcfg0(1 downto 0) = "01" else int_timer1_ocr when paaltcfg0(1 downto 0) = "10" else paout(0);
paalt2 <= uart0_tx when paaltcfg0(5 downto 4) = "01" else paout(2);
paalt8 <= int_timer1_ctc when paaltcfg0(17 downto 16) = "01" else int_timer1_ocr when paaltcfg0(17 downto 16) = "10" else paout(8);
paalt10 <= uart0_tx when paaltcfg0(21 downto 20) = "01" else paout(10);
uart0_rx <= gpioa_in(3) when paaltcfg0(7 downto 6) = "01" else gpioa_in(11) when paaltcfg0(23 downto 22) = "01" else '1';
-- address decoder, read from peripheral registers
process(clk_i, rst_i, segment, class, device, funct)
begin
if rst_i = '1' then
data_o <= (others => '0');
uart0_enable_r <= '0';
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' then
case segment is
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "000001" => -- S0CAUSE (RO)
data_o <= x"0000000" & s0cause;
when "010000" => -- PAALTCFG0 (RW)
data_o <= x"00" & paaltcfg0;
when others =>
data_o <= (others => '0');
end case;
when "0001" => -- GPIO
case device is
when "000001" => -- GPIOCAUSE (RO)
data_o <= x"0000000" & gpiocause;
when "000010" => -- GPIOCAUSE_INV (RW)
data_o <= x"0000000" & gpiocause_inv;
when "000011" => -- GPIOMASK (RW)
data_o <= x"0000000" & gpiomask;
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
data_o <= x"0000" & paddr;
when "0001" => -- PAOUT (RW)
data_o <= x"0000" & paout;
when "0010" => -- PAIN (RO)
data_o <= x"0000" & pain;
when "0011" => -- PAIN_INV (RW)
data_o <= x"0000" & pain_inv;
when "0100" => -- PAIN_MASK (RW)
data_o <= x"0000" & pain_mask;
when others =>
data_o <= (others => '0');
end case;
when "010001" => -- PORTB
case funct is
when "0000" => -- PBDDR (RW)
data_o <= x"0000" & pbddr;
when "0001" => -- PBOUT (RW)
data_o <= x"0000" & pbout;
when "0010" => -- PBIN (RO)
data_o <= x"0000" & pbin;
when "0011" => -- PBIN_INV (RW)
data_o <= x"0000" & pbin_inv;
when "0100" => -- PBIN_MASK (RW)
data_o <= x"0000" & pbin_mask;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when "0010" => -- timers
case device is
when "000001" => -- TIMERCAUSE (RO)
data_o <= x"0000000" & timercause;
when "000010" => -- TIMERCAUSE_INV (RW)
data_o <= x"0000000" & timercause_inv;
when "000011" => -- TIMERMASK (RW)
data_o <= x"0000000" & timermask;
when "010000" => -- TIMER0 (RO)
data_o <= timer0;
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
data_o <= x"0000" & timer1;
when "0001" => -- TIMER1_PRE (RW)
data_o <= x"0000000" & '0' & timer1_pre;
when "0010" => -- TIMER1_CTC (RW)
data_o <= x"0000" & timer1_ctc;
when "0011" => -- TIMER1_OCR (RW)
data_o <= x"0000" & timer1_ocr;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when "0011" => -- UARTs
case device is
when "000001" => -- TIMERCAUSE (RO)
data_o <= x"0000000" & uartcause;
when "000010" => -- UARTCAUSE_INV (RW)
data_o <= x"0000000" & uartcause_inv;
when "000011" => -- UARTMASK (RW)
data_o <= x"0000000" & uartmask;
when "010000" => -- UART0
case funct is
when "0000" => -- UART0 (RW)
data_o <= x"000000" & uart0_data_read;
uart0_enable_r <= '1';
when "0001" => -- UART0DIV (RW)
data_o <= x"0000" & uart0_divisor;
when others =>
end case;
when others =>
end case;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
else
uart0_enable_r <= '0';
end if;
end if;
end process;
-- peripheral register logic, write to peripheral registers
process(clk_i, rst_i, segment, class, device, funct, tmr1_pulse)
begin
if rst_i = '1' then
paaltcfg0 <= (others => '0');
gpiocause_inv <= (others => '0');
gpiomask <= (others => '0');
paout <= (others => '0');
pain_inv <= (others => '0');
pain_mask <= (others => '0');
paddr <= (others => '0');
pbout <= (others => '0');
pbin_inv <= (others => '0');
pbin_mask <= (others => '0');
pbddr <= (others => '0');
timercause_inv <= (others => '0');
timermask <= (others => '0');
timer0 <= (others => '0');
timer1 <= (others => '0');
timer1_set <= '0';
timer1_pre <= (others => '0');
timer1_ctc <= (others => '1');
timer1_ocr <= (others => '0');
int_timer1_ctc <= '0';
uartcause_inv <= (others => '0');
uartmask <= (others => '0');
uart0_enable_w <= '0';
uart0_data_write <= (others => '0');
uart0_divisor <= (others => '0');
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' and wr_i = '1' then
case segment is
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "010000" => -- PAALTCFG0 (RW)
paaltcfg0 <= data_i(23 downto 0);
when others =>
end case;
when "0001" => -- GPIO
case device is
when "000010" => -- GPIOCAUSE_INV (RW)
gpiocause_inv <= data_i(3 downto 0);
when "000011" => -- GPIOMASK (RW)
gpiomask <= data_i(3 downto 0);
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
paddr <= data_i(15 downto 0);
when "0001" => -- PAOUT (RW)
paout <= data_i(15 downto 0);
when "0011" => -- PAIN_INV (RW)
pain_inv <= data_i(15 downto 0);
when "0100" => -- PAIN_MASK (RW)
pain_mask <= data_i(15 downto 0);
when others =>
end case;
when "010001" => -- PORTB
case funct is
when "0000" => -- PBDDR (RW)
pbddr <= data_i(15 downto 0);
when "0001" => -- PBOUT (RW)
pbout <= data_i(15 downto 0);
when "0011" => -- PBIN_INV (RW)
pbin_inv <= data_i(15 downto 0);
when "0100" => -- PBIN_MASK (RW)
pbin_mask <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when "0010" => -- timers
case device is
when "000010" => -- TIMERCAUSE_INV (RW)
timercause_inv <= data_i(3 downto 0);
when "000011" => -- TIMERMASK (RW)
timermask <= data_i(3 downto 0);
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
if data_i(31) = '1' then
timer1_set <= '1';
end if;
if timer1_set = '1' then
timer1 <= data_i(15 downto 0);
timer1_set <= '0';
end if;
when "0001" => -- TIMER1_PRE (RW)
timer1_pre <= data_i(2 downto 0);
when "0010" => -- TIMER1_CTC (RW)
timer1_ctc <= data_i(15 downto 0);
when "0011" => -- TIMER1_OCR (RW)
timer1_ocr <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when "0011" => -- UARTs
case device is
when "000010" => -- UARTCAUSE_INV (RW)
uartcause_inv <= data_i(3 downto 0);
when "000011" => -- UARTMASK (RW)
uartmask <= data_i(3 downto 0);
when "010000" => -- UART0
case funct is
when "0000" => -- UART0 (RW)
uart0_data_write <= data_i(7 downto 0);
uart0_enable_w <= '1';
when "0001" => -- UART0DIV (RW)
uart0_divisor <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when others =>
end case;
when others =>
end case;
else
uart0_enable_w <= '0';
end if;
timer0 <= timer0 + 1;
if tmr1_pulse = '1' then
if (timer1 /= timer1_ctc) then
if timer1_set = '0' then
timer1 <= timer1 + 1;
end if;
else
int_timer1_ctc <= not int_timer1_ctc;
timer1 <= (others => '0');
end if;
end if;
end if;
end process;
process(clk_i, rst_i) -- TIMER1 prescaler
begin
if rst_i = '1' then
tmr1_dly <= '0';
tmr1_dly2 <= '0';
elsif clk_i'event and clk_i = '1' then
case timer1_pre is
when "001" =>
tmr1_dly <= timer0(2); -- /4
when "010" =>
tmr1_dly <= timer0(4); -- /16
when "011" =>
tmr1_dly <= timer0(6); -- /64
when "100" =>
tmr1_dly <= timer0(8); -- /256
when "101" =>
tmr1_dly <= timer0(10); -- /1024
when "110" =>
tmr1_dly <= timer0(12); -- /4096
when "111" =>
tmr1_dly <= timer0(14); -- /16384
when others =>
tmr1_dly <= timer0(0); -- /1
end case;
tmr1_dly2 <= tmr1_dly;
end if;
end process;
tmr1_pulse <= '1' when tmr1_dly /= tmr1_dly2 else '0';
int_timer1_ocr <= '1' when timer1 < timer1_ocr else '0';
uart0: entity work.uart
port map(
clk => clk_i,
reset => rst_i,
divisor => uart0_divisor(11 downto 0),
enable_read => uart0_enable_r,
enable_write => uart0_enable_w,
data_in => uart0_data_write,
data_out => uart0_data_read,
uart_read => uart0_rx,
uart_write => uart0_tx,
busy_write => uart0_write_busy,
data_avail => uart0_data_avail
);
end peripherals_arch;
| gpl-2.0 |
trcwm/fptool | ghdl/csd_test_prolog.vhdl | 1 | 616 | --
--
--
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.MATH_REAL.ALL;
entity tb is
end entity;
architecture behavior of tb is
signal a : SIGNED(15 downto 0); -- Q(1,15)
signal result : SIGNED(21 downto 0); -- Q(4,18)
signal result_real : REAL;
begin
proc_sim: process
variable result_real : real;
begin
a <= "0111111111111111";
wait for 10 ns;
result_real := real(TO_INTEGER(result));
result_real := result_real*2.0**(-18.0);
report "The value of 'result' is " & real'image(result_real);
wait;
end process proc_sim;
| gpl-2.0 |
dl3yc/sdr-fm | dev/div/div.vhd | 1 | 1866 | -- DIV module for Betty SDR
-- implements an iterative restoring divider
-- heavily based on 8-bit Restoring Divider(p.94 U. Meyer-Baese "DSP with FPGA")
-- file: div.vhd
-- author: Sebastian Weiss DL3YC <[email protected]>
-- version: 1.0
--
-- change log:
-- - release implementation 1.0
-- - tested with use cases
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity div is
generic (
WN : natural;
WD : natural
);
port (
clk : in std_logic;
stb : in std_logic;
num : in signed(WN-1 downto 0);
denom : in signed(WD-1 downto 0);
quot : out signed(WN-1 downto 0);
remaind : out signed(WD-1 downto 0);
rdy : out std_logic
);
end entity div;
architecture rtl of div is
type state_t is (init, processing, restoring, establish);
signal state : state_t;
signal r, d : signed(WN+WD-1 downto 0) := (others => '0');
signal q : signed(WN-1 downto 0);
signal count : integer range 0 to WN;
begin
process
begin
wait until rising_edge(clk);
case state is
when init =>
rdy <= '0';
if stb = '1' then
state <= processing;
count <= 0;
q <= (others => '0');
if denom = 0 then
state <= establish;
d <= to_signed(1,d'length);
r <= (others => '0');
else
d <= shift_left(resize(denom,d'length),WN-1);
r <= resize(num,r'length);
end if;
end if;
when processing =>
r <= r - d;
state <= restoring;
when restoring =>
if r < 0 then
r <= r + d;
q <= shift_left(q,1);
else
q <= shift_left(q,1) + 1;
end if;
count <= count + 1;
d <= d / 2;
if count = WN-1 then
state <= establish;
else
state <= processing;
end if;
when establish =>
quot <= q;
remaind <= resize(r,remaind'length);
rdy <= '1';
state <= init;
end case;
end process;
end architecture rtl;
| gpl-2.0 |
dl3yc/sdr-fm | testing/fir-1.0/inc/fir_coeff.vhd | 2 | 1826 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fir_types.all;
package fir_coeff_lib is
constant fir_order : natural := 128;
type integer_vector is array(fir_order downto 0) of integer;
constant fir_coeff_content : integer_vector := (
30251, 25860, 4784, -21256, -36393, -29458, -1554, 32410,
50644, 37512, -4503, -52413, -74050, -48513, 16566, 84046,
107070, 60122, -38397, -130080, -149580, -69234, 74231, 193160,
200780, 71802, -129020, -276090, -259370, -62958, 208440, 381780,
323340, 36338, -319910, -514420, -390640, 16054, 473460, 680160,
458700, -106210, -685690, -891130, -526160, 252490, 985540, 1170900,
592070, -491400, -1436600, -1577800, -662630, 904470, 2199700, 2274900,
763940, -1750000, -3862800, -3974600, -1129700, 4365600, 10902000, 16178000,
18199000, 16178000, 10902000, 4365600, -1129700, -3974600, -3862800, -1750000,
763940, 2274900, 2199700, 904470, -662630, -1577800, -1436600, -491400,
592070, 1170900, 985540, 252490, -526160, -891130, -685690, -106210,
458700, 680160, 473460, 16054, -390640, -514420, -319910, 36338,
323340, 381780, 208440, -62958, -259370, -276090, -129020, 71802,
200780, 193160, 74231, -69234, -149580, -130080, -38397, 60122,
107070, 84046, 16566, -48513, -74050, -52413, -4503, 37512,
50644, 32410, -1554, -29458, -36393, -21256, 4784, 25860, 30251
);
function to_fir_coeff_t(iv: integer_vector) return fir_coeff_t;
end package fir_coeff_lib;
package body fir_coeff_lib is
function to_fir_coeff_t(iv: integer_vector) return fir_coeff_t is
variable ret : fir_coeff_t(fir_order downto 0);
begin
for i in 0 to fir_order loop
ret(i) := to_signed(iv(i) ,27);
end loop;
return ret;
end function;
end package body fir_coeff_lib;
| gpl-2.0 |
dl3yc/sdr-fm | testing/euler-1.0/sim/euler_tb.vhd | 1 | 5201 | -- title: Testbench for VCORDIC
-- author: Sebastian Weiss
-- last change: 03.12.14
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity euler_tb is
end entity;
architecture behavioral of euler_tb is
constant A : natural := 16;
constant P : natural := 24;
constant N : natural := 15;
signal clk : std_logic := '0';
signal i : signed(A-1 downto 0) := (others => '0');
signal q : signed(A-1 downto 0) := (others => '0');
signal amp : unsigned(A-1 downto 0);
signal phi : signed(P-1 downto 0) := (others => '0');
begin
dut : entity work.euler
generic map(
A => A,
P => P,
N => N
)
port map(
clk => clk,
i => i,
q => q,
amp => amp,
phi => phi
);
process
begin
wait until rising_edge(clk);
i <= to_signed(integer(1.0 * 2.0**(A-1)-1.0),A);
q <= to_signed(integer(1.0 * 2.0**(A-1)-1.0),A);
wait until rising_edge(clk);
i <= to_signed(integer(0.7071 * 2.0**(A-1)),A);
q <= to_signed(integer(0.7071 * 2.0**(A-1)),A);
wait until rising_edge(clk);
i <= to_signed(integer(0.5 * 2.0**(A-1)),A);
q <= to_signed(integer(0.2 * 2.0**(A-1)),A);
wait until rising_edge(clk);
i <= to_signed(integer(-0.1 * 2.0**(A-1)),A);
q <= to_signed(integer(0.9 * 2.0**(A-1)),A);
wait until rising_edge(clk);
i <= to_signed(integer(-1.0 * 2.0**(A-1)+1.0),A);
q <= to_signed(integer(-1.0 * 2.0**(A-1)+1.0),A);
wait until rising_edge(clk);
i <= to_signed(integer(-0.7071 * 2.0**(A-1)),A);
q <= to_signed(integer(0.7071 * 2.0**(A-1)),A);
wait until rising_edge(clk);
i <= to_signed(integer(0.5 * 2.0**(A-1)),A);
q <= to_signed(integer(-0.2 * 2.0**(A-1)),A);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
i <= to_signed(integer(0.0 * (2.0**(A-1)-1.0)),A);
q <= to_signed(integer(0.0 * (2.0**(A-1)-1.0)),A);
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 1.4142 * 2.0**(A-1)),A)) and (amp >= to_unsigned(integer(0.99 * 1.4142 * 2.0**(A-1)),A))
report "case 1 failed!" severity error;
assert (phi < to_signed(integer(1.01 * atan(1.0/1.0)/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * atan(1.0/1.0)/(MATH_PI) * 2.0**(P-1)),P))
report "case 2 failed!" severity error;
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 1.0 * 2.0**(A-1)),A)) and (amp >=to_unsigned(integer(0.99 * 1.0 * 2.0**(A-1)),A))
report "case 3 failed!" severity error;
assert (phi < to_signed(integer(1.01 * atan(0.7071/0.7071)/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * atan(0.7071/0.7071)/(MATH_PI) * 2.0**(P-1)),P))
report "case 4 failed!" severity error;
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 0.5385 * 2.0**(A-1)),A)) and (amp >=to_unsigned(integer(0.99 * 0.5385 * 2.0**(A-1)),A))
report "case 5 failed!" severity error;
assert (phi < to_signed(integer(1.01 * atan(0.5/0.2)/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * atan(0.5/0.2)/(MATH_PI) * 2.0**(P-1)),P))
report "case 6 failed!" severity error;
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 0.9055 * 2.0**(A-1)),A)) and (amp >=to_unsigned(integer(0.99 * 0.9055 * 2.0**(A-1)),A))
report "case 7 failed!" severity error;
assert (phi < to_signed(integer(1.01 * 1.6815/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * 1.6815/(MATH_PI) * 2.0**(P-1)),P))
report "case 8 failed!" severity error;
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 1.4142 * 2.0**(A-1)),A)) and (amp >= to_unsigned(integer(0.99 * 1.4142 * 2.0**(A-1)),A))
report "case 9 failed!" severity error;
assert (phi < to_signed(integer(1.01 * atan(1.0/1.0)/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * atan(1.0/1.0)/(MATH_PI) * 2.0**(P-1)),P))
report "case 10 failed!" severity error;
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 1.0 * 2.0**(A-1)),A)) and (amp >=to_unsigned(integer(0.99 * 1.0 * 2.0**(A-1)),A))
report "case 11 failed!" severity error;
assert (phi < to_signed(integer(1.01 * atan(0.7071/0.7071)/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * atan(0.7071/0.7071)/(MATH_PI) * 2.0**(P-1)),P))
report "case 12 failed!" severity error;
wait until rising_edge(clk);
assert (amp < to_unsigned(integer(1.01 * 0.5385 * 2.0**(A-1)),A)) and (amp >=to_unsigned(integer(0.99 * 0.5385 * 2.0**(A-1)),A))
report "case 13 failed!" severity error;
assert (phi < to_signed(integer(1.01 * atan(0.5/0.2)/(MATH_PI) * 2.0**(P-1)),P)) and (phi >= to_signed(integer(0.99 * atan(0.5/0.2)/(MATH_PI) * 2.0**(P-1)),P))
report "case 14 failed!" severity error;
report "all tests finished!";
wait;
end process;
clk <= not clk after 11363 ps;
end behavioral;
| gpl-2.0 |
vargax/ejemplos | vhd/fundSistDigitales/practica4/sumador.vhd | 1 | 1293 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:36:09 09/10/2011
-- Design Name:
-- Module Name: sumador - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sumador is
Port ( num : in STD_LOGIC_VECTOR (2 downto 0);
suma : out STD_LOGIC_VECTOR (2 downto 0));
end sumador;
architecture Behavioral of sumador is
begin
with num select
suma <= "001" when "000",
"010" when "001",
"011" when "010",
"100" when "011",
"101" when "100",
"110" when "101",
"111" when "110",
"000" when "111",
"---" when others;
end Behavioral;
| gpl-2.0 |
zhanglongqi/LED_Blinking_on_ZedBoard | zynq_Gpio.srcs/sources_1/ipshared/xilinx.com/interrupt_control_v3_1/dd9a9dbd/hdl/src/vhdl/interrupt_control.vhd | 8 | 57387 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers. This module has been optimized
-- for the 64 bit wide PLB bus.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP2
--
-- Initial Release
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_K_SP3
--
-- Updated to use proc_common_v4_0 library
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- DET 11/5/2003 v1_00_e
-- ~~~~~~
-- - Revamped register topology to take advantage of 64 bit wide data bus
-- interface. This required adding the Bus2IP_BE_sa input port to
-- provide byte lane qualifiers for write operations.
-- ^^^^^^
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed proc_common library reference to v2_00_a
-- - Removed ipif_common library reference
-- ^^^^^^
-- GAB 06/29/2005 v2_00_a
-- ~~~~~~
-- - Modified plb_interrupt_control of plb_ipif_v1_00_f to make
-- a common version that supports 32,64, and 128-Bit Data Bus Widths.
-- - Changed to use ieee.numeric_std library and removed
-- ieee.std_logic_arith.all
-- ^^^^^^
-- GAB 09/01/2006 v2_00_a
-- ~~~~~~
-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs
-- - Removed strobe from interrupt enable registers where it was not needed
-- ^^^^^^
-- GAB 07/02/2008 v3_1
-- ~~~~~~
-- - Modified to used proc_common_v4_0 library
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of Interrupt Control to v3.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_NUM_CE : integer range 4 to 16 := 4;
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2 -- pass through (inverting)
);
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER : boolean := false;
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : boolean := false;
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH : integer range 32 to 128 := 128
);
port(
-- Inputs From the IPIF Bus
bus2ip_clk : In std_logic;
bus2ip_reset : In std_logic;
bus2ip_data : In std_logic_vector(0 to C_IPIF_DWIDTH-1);
bus2ip_be : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
interrupt_rdce : In std_logic_vector(0 to C_NUM_CE-1);
interrupt_wrce : In std_logic_vector(0 to C_NUM_CE-1);
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
ipif_reg_interrupts : In std_logic_vector(0 to 1);
-- Level Interrupt inputs from the IPIF sources
ipif_lvl_interrupts : In std_logic_vector
(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Inputs from the IP Interface
ip2bus_intrevent : In std_logic_vector
(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Final Device Interrupt Output
intr2bus_devintr : Out std_logic;
-- Status Reply Outputs to the Bus
intr2bus_dbus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
intr2bus_wrack : Out std_logic;
intr2bus_rdack : Out std_logic;
intr2bus_error : Out std_logic;
intr2bus_retry : Out std_logic;
intr2bus_toutsup : Out std_logic
);
end interrupt_control;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_max_allowed_irpt_width
--
-- Function Description:
-- This function determines the maximum number of interrupts that
-- can be processed from the User IP based on the IPIF data bus width
-- and the number of interrupt entries desired.
--
-------------------------------------------------------------------
function get_max_allowed_irpt_width(data_bus_width : integer;
num_intrpts_entered : integer)
return integer is
Variable temp_max : Integer;
begin
If (data_bus_width >= num_intrpts_entered) Then
temp_max := num_intrpts_entered;
else
temp_max := data_bus_width;
End if;
return(temp_max);
end function get_max_allowed_irpt_width;
-------------------------------------------------------------------------------
-- Function data_port_map
-- This function will return an index within a 'reg_width' divided port
-- having a width of 'port_width' based on an address 'offset'.
-- For instance if the port_width is 128-bits and the register width
-- reg_width = 32 bits and the register address offset=16 (0x10), this
-- function will return a index of 0.
--
-- Address Offset Returned Index Return Index Returned Index
-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus)
-- 0x00 0 0 0
-- 0x04 1 1 0
-- 0x08 2 0 0
-- 0x0C 3 1 0
-- 0x10 0 0 0
-- 0x14 1 1 0
-- 0x18 2 0 0
-- 0x1C 3 1 0
-------------------------------------------------------------------------------
function data_port_map(offset : integer;
reg_width : integer;
port_width : integer)
return integer is
variable upper_index : integer;
variable vector_range : integer;
variable reg_offset : std_logic_vector(0 to 7);
variable word_offset_i : integer;
begin
-- Calculate index position to start decoding the address offset
upper_index := log2(port_width/8);
-- Calculate the number of bits to look at in decoding
-- the address offset
vector_range := max2(1,log2(port_width/reg_width));
-- Convert address offset into a std_logic_vector in order to
-- strip out a set of bits for decoding
reg_offset := std_logic_vector(to_unsigned(offset,8));
-- Calculate an index representing the word position of
-- a register with respect to the port width.
word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length
- upper_index to (reg_offset'length
- upper_index) + vector_range - 1)));
return word_offset_i;
end data_port_map;
-------------------------------------------------------------------------------
-- Type declarations
-------------------------------------------------------------------------------
-- no Types
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- figure out if 32 bits wide or 64 bits wide
Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1;
Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32);
constant BITS_PER_REG : integer := 32;
constant BYTES_PER_REG : integer := BITS_PER_REG/8;
-- Register Index
Constant DEVICE_ISR_INDEX : integer := 0;
Constant DEVICE_IPR_INDEX : integer := 1;
Constant DEVICE_IER_INDEX : integer := 2;
Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD
Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD
Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD
Constant DEVICE_IIR_INDEX : integer := 6;
Constant DEVICE_GIE_INDEX : integer := 7;
Constant IP_ISR_INDEX : integer := 8;
Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD
Constant IP_IER_INDEX : integer := 10;
Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD
Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD
Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD
Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD
Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
-- Register Address Offset
Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG;
Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG;
Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG;
Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG;
Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG;
Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG;
Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG;
Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG;
Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG;
Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG;
Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG;
Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG;
Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG;
Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG;
Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG;
Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG;
-- Column Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
-- Generic to constant mapping
Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1;
Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length;
-- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IP_IRPT_HIGH_INDEX : Integer :=
get_max_allowed_irpt_width(C_IPIF_DWIDTH,
NUM_USER_DESIRED_IRPTS)
-1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector
(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector
(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector
(DBUS_WIDTH_MINUS1 downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector
(PRIORITY_ENC_WIDTH-1 downto 0);
Signal column_sel : std_logic_vector
(0 to LSB_BYTLE_LANE_COL_OFFSET);
signal interrupt_wrce_strb : std_logic;
signal irpt_wrack_d1 : std_logic;
signal irpt_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
REG_WRACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_wrack_d1 <= '0';
Intr2Bus_WrAck <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
Intr2Bus_WrAck <= interrupt_wrce_strb;
end if;
end if;
end process REG_WRACK_PROCESS;
interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1;
REG_RDACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_rdack_d1 <= '0';
Intr2Bus_RdAck <= '0';
else
irpt_rdack_d1 <= irpt_rdack;
Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1;
end if;
end if;
end process REG_RDACK_PROCESS;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_COL
--
-- Process Description:
--
--
-------------------------------------------------------------
ASSIGN_COL : process (Bus2IP_BE)
begin
-- Assign the 32-bit column selects from BE inputs
for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop
column_sel(i) <= Bus2IP_BE(i*4);
end loop;
end process ASSIGN_COL;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to DBUS_WIDTH_MINUS1 loop
Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1' and
column_sel(IP_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs
-- (GAB)
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data((BITS_PER_REG * IP_ISR_COL)
+(BITS_PER_REG - 1)
- irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1' and
column_sel(IP_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ip_irpt_enable_reg <= Bus2IP_Data
( (BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
- IP_IRPT_HIGH_INDEX to
(BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and
column_sel(DEVICE_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then
for i in 0 to 1 loop
-- (GAB)
ipif_irpt_status_reg(i) <= (Bus2IP_Data
( (BITS_PER_REG * DEVICE_ISR_COL)
+(BITS_PER_REG - 1)
- i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1' and
column_sel(DEVICE_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ipif_irpt_enable_reg <= Bus2IP_Data
(
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
- IPIF_IRPT_HIGH_INDEX to
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and
column_sel(DEVICE_GIE_COL) = '1' )then
--interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs
-- (GAB)
ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <= (
Interrupt_WrCE(DEVICE_ISR) and
column_sel(DEVICE_ISR_COL)
)
or
(
Interrupt_WrCE(DEVICE_IER) and
column_sel(DEVICE_IER_COL)
)
or
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <=
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, column_sel,
ip_irpt_status_reg,
ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1'
and column_sel(DEVICE_ISR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_ISR_COL)
- BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1'
and column_sel(DEVICE_IPR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IPR_COL)
- BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1'
and column_sel(DEVICE_IER_COL) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IER_COL)
- BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1'
and column_sel(DEVICE_IIR_COL) = '1') Then
-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_read_data( (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG) + PRIORITY_ENC_WIDTH-1
downto (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG)) <= ipif_priority_encode_value;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg,column_sel)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
| gpl-2.0 |
zhanglongqi/LED_Blinking_on_ZedBoard | zynq_Gpio.srcs/sources_1/ipshared/xilinx.com/axi_gpio_v2_0/e416c384/hdl/src/vhdl/axi_gpio.vhd | 5 | 33293 | -------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_gpio.vhd
-- Version: v2.0
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
-------------------------------------------------------------------------------
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 07/28/09
-- ^^^^^^^^^^^^^^
-- First version of axi_gpio. Based on xps_gpio 2.00a
--
-- KSB 05/20/10
-- ^^^^^^^^^^^^^^
-- Updated for holes in address range
-- ~~~~~~~~~~~~~~
-- VB 09/23/10
-- ^^^^^^^^^^^^^^
-- Updated for axi_lite_ipfi_v1_01_a
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use std.textio.all;
-------------------------------------------------------------------------------
-- AXI common package of the proc common library is used for different
-- function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_gpio_v2_0 library is used for axi4 component declarations
-------------------------------------------------------------------------------
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
use axi_lite_ipif_v3_0.ipif_pkg.SLV64_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0 library is used for interrupt controller component
-- declarations
-------------------------------------------------------------------------------
library interrupt_control_v3_1;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0 library is used for axi_gpio component declarations
-------------------------------------------------------------------------------
library axi_gpio_v2_0;
-------------------------------------------------------------------------------
-- Defination of Generics : --
-------------------------------------------------------------------------------
-- AXI generics
-- C_BASEADDR -- Base address of the core
-- C_HIGHADDR -- Permits alias of address space
-- by making greater than xFFF
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits)
-- C_FAMILY -- XILINX FPGA family
-- C_INSTANCE -- Instance name ot the core in the EDK system
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_ALL_INPUTS -- Inputs Only.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_IS_BIDIR -- Selects gpio_io_i as input.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_ALL_INPUTS_2 -- Channel2 Inputs only.
-- C_IS_BIDIR_2 -- Selects gpio2_io_i as input.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Defination of Ports --
-------------------------------------------------------------------------------
-- AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- GPIO Signals
-- gpio_io_i -- Channel 1 General purpose I/O in port
-- gpio_io_o -- Channel 1 General purpose I/O out port
-- gpio_io_t -- Channel 1 General purpose I/O
-- TRI-STATE control port
-- gpio2_io_i -- Channel 2 General purpose I/O in port
-- gpio2_io_o -- Channel 2 General purpose I/O out port
-- gpio2_io_t -- Channel 2 General purpose I/O
-- TRI-STATE control port
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- ip2intc_irpt -- AXI GPIO Interrupt
-------------------------------------------------------------------------------
entity axi_gpio is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- GPIO Parameter
C_GPIO_WIDTH : integer range 1 to 32 := 32;
C_GPIO2_WIDTH : integer range 1 to 32 := 32;
C_ALL_INPUTS : integer range 0 to 1 := 0;
C_ALL_INPUTS_2 : integer range 0 to 1 := 0;
C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013
C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013
C_INTERRUPT_PRESENT : integer range 0 to 1 := 0;
C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF";
C_IS_DUAL : integer range 0 to 1 := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF"
);
port
(
-- AXI interface Signals --------------------------------------------------
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1
downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Interrupt---------------------------------------------------------------
ip2intc_irpt : out std_logic;
-- GPIO Signals------------------------------------------------------------
gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0)
);
-------------------------------------------------------------------------------
-- fan-out attributes for XST
-------------------------------------------------------------------------------
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
-------------------------------------------------------------------------------
-- Attributes for MPD file
-------------------------------------------------------------------------------
attribute IP_GROUP : string ;
attribute IP_GROUP of axi_gpio : entity is "LOGICORE";
attribute SIGIS : string ;
attribute SIGIS of s_axi_aclk : signal is "Clk";
attribute SIGIS of s_axi_aresetn : signal is "Rst";
attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
end entity axi_gpio;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of axi_gpio is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- constant added for webtalk information
-------------------------------------------------------------------------------
--function chr(sl: std_logic) return character is
-- variable c: character;
-- begin
-- case sl is
-- when '0' => c:= '0';
-- when '1' => c:= '1';
-- when 'Z' => c:= 'Z';
-- when 'U' => c:= 'U';
-- when 'X' => c:= 'X';
-- when 'W' => c:= 'W';
-- when 'L' => c:= 'L';
-- when 'H' => c:= 'H';
-- when '-' => c:= '-';
-- end case;
-- return c;
-- end chr;
--
--function str(slv: std_logic_vector) return string is
-- variable result : string (1 to slv'length);
-- variable r : integer;
-- begin
-- r := 1;
-- for i in slv'range loop
-- result(r) := chr(slv(i));
-- r := r + 1;
-- end loop;
-- return result;
-- end str;
type bo2na_type is array (boolean) of natural; -- boolean to
--natural conversion
constant bo2na : bo2na_type := (false => 0, true => 1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean;
----------------------------------------------------------------------------
-- This function returns the number of elements that are true in
-- a boolean array.
----------------------------------------------------------------------------
function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is
variable n : natural := 0;
begin
for i in ba'range loop
n := n + bo2na(ba(i));
end loop;
return n;
end;
----------------------------------------------------------------------------
-- This function returns a num_ce integer array that is constructed by
-- taking only those elements of superset num_ce integer array
-- that will be defined by the current case.
-- The superset num_ce array is given by parameter num_ce_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE;
num_ce_by_ard : INTEGER_ARRAY_TYPE
) return INTEGER_ARRAY_TYPE is
variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := num_ce_by_ard(j);
i := i+1;
j := j+1;
end loop;
return res;
end;
----------------------------------------------------------------------------
-- This function returns a addr_range array that is constructed by
-- taking only those elements of superset addr_range array
-- that will be defined by the current case.
-- The superset addr_range array is given by parameter addr_range_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE;
addr_range_by_ard : SLV64_ARRAY_TYPE
) return SLV64_ARRAY_TYPE is
variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := addr_range_by_ard(2*j);
res(i+1) := addr_range_by_ard((2*j)+1);
i := i+2;
j := j+1;
end loop;
return res;
end;
function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE
) return std_logic_vector is
variable res : std_logic_vector(0 to 31);
begin
res := (others => '0');
if defined_ards(defined_ards'right) then
res(0 to 3) := "1111";
res(12) := '1';
res(13) := '1';
res(15) := '1';
else
res(0 to 3) := "1111";
end if;
return res;
end;
----------------------------------------------------------------------------
-- This function returns the maximum width amongst the two GPIO Channels
-- and if there is only one channel, it returns just the width of that
-- channel.
----------------------------------------------------------------------------
function max_width( dual_channel : INTEGER;
channel1_width : INTEGER;
channel2_width : INTEGER
) return INTEGER is
begin
if (dual_channel = 0) then
return channel1_width;
else
if (channel1_width > channel2_width) then
return channel1_width;
else
return channel2_width;
end if;
end if;
end;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) :=
(others => '0');
constant INTR_TYPE : integer := 5;
constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100";
constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF";
constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F";
constant MAX_GPIO_WIDTH : integer := max_width
(C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
qual_ard_addr_range_array(
(true,C_INTERRUPT_PRESENT=1),
(ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & GPIO_HIGHADDR,
ZERO_ADDR_PAD & INTR_BASEADDR,
ZERO_ADDR_PAD & INTR_HIGHADDR
)
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
qual_ard_num_ce_array(
(true,C_INTERRUPT_PRESENT=1),
(4,16)
);
constant ARD_CE_VALID : std_logic_vector(0 to 31) :=
qual_ard_ce_valid(
(true,C_INTERRUPT_PRESENT=1)
);
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1))
:= (others => 5);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal ip2bus_intrevent : std_logic_vector(0 to 1);
signal GPIO_xferAck_i : std_logic;
signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-- IPIC Used Signals
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na
(C_INTERRUPT_PRESENT=1));
signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15);
signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15);
signal intr_wr_ce_or_reduce : std_logic;
signal intr_rd_ce_or_reduce : std_logic;
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1);
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal intr2bus_wrack : std_logic;
signal intr2bus_rdack : std_logic;
signal intr2bus_error : std_logic;
signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_wrack_i : std_logic;
signal ip2bus_wrack_i_D1 : std_logic;
signal ip2bus_rdack_i : std_logic;
signal ip2bus_rdack_i_D1 : std_logic;
signal ip2bus_error_i : std_logic;
signal IP2INTC_Irpt_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data_i_D1,
IP2Bus_WrAck => ip2bus_wrack_i_D1,
IP2Bus_RdAck => ip2bus_rdack_i_D1,
--IP2Bus_WrAck => ip2bus_wrack_i,
--IP2Bus_RdAck => ip2bus_rdack_i,
IP2Bus_Error => ip2bus_error_i,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
ip2bus_data_i <= intr2bus_data or ip2bus_data;
ip2bus_wrack_i <= intr2bus_wrack or
(GPIO_xferAck_i and not(bus2ip_rnw)) or
ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range
ip2bus_rdack_i <= intr2bus_rdack or
(GPIO_xferAck_i and bus2ip_rnw) or
ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range
I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2bus_wrack_i_D1 <= '0';
ip2bus_rdack_i_D1 <= '0';
ip2bus_data_i_D1 <= (others => '0');
else
ip2bus_wrack_i_D1 <= ip2bus_wrack_i;
ip2bus_rdack_i_D1 <= ip2bus_rdack_i;
ip2bus_data_i_D1 <= ip2bus_data_i;
end if;
end if;
end process I_WRACK_RDACK_DELAYS;
ip2bus_error_i <= intr2bus_error;
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset <= not(bus2ip_resetn);
end if;
end process REG_RESET_FROM_IPIF;
---------------------------------------------------------------------------
-- Interrupts
---------------------------------------------------------------------------
INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate
constant NUM_IPIF_IRPT_SRC : natural := 1;
constant NUM_CE : integer := 16;
signal errack_reserved : std_logic_vector(0 to 1);
signal ipif_lvl_interrupts : std_logic_vector(0 to
NUM_IPIF_IRPT_SRC-1);
begin
ipif_lvl_interrupts <= (others => '0');
errack_reserved <= (others => '0');
--- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes
Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0'
& bus2ip_rdce(14) & "00000";
Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0'
& bus2ip_wrce(14) & "00000";
intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or
Bus2IP_RdCE(13) or
or_reduce(Bus2IP_RdCE(15 to 19));
intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or
bus2ip_wrce(13) or
or_reduce(bus2ip_wrce(15 to 19));
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
INTERRUPT_CONTROL_I : entity interrupt_control_v3_1.interrupt_control
generic map
(
C_NUM_CE => NUM_CE,
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => false,
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
-- Inputs From the IPIF Bus
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => bus2ip_reset,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Interrupt_RdCE => Intrpt_bus2ip_rdce,
Interrupt_WrCE => Intrpt_bus2ip_wrce,
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => errack_reserved,
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => ipif_lvl_interrupts,
-- Inputs from the IP Interface
IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range),
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IP2INTC_Irpt_i,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-- registering interrupt
I_INTR_DELAY: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2intc_irpt <= '0';
else
ip2intc_irpt <= IP2INTC_Irpt_i;
end if;
end if;
end process I_INTR_DELAY;
end generate INTR_CTRLR_GEN;
-----------------------------------------------------------------------
-- Assigning the intr2bus signal to zero's when interrupt is not
-- present
-----------------------------------------------------------------------
REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
intr2bus_data <= (others => '0');
ip2intc_irpt <= '0';
intr2bus_error <= '0';
intr2bus_rdack <= '0';
intr2bus_wrack <= '0';
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole <= '0';
end generate REMOVE_INTERRUPT;
gpio_core_1 : entity axi_gpio_v2_0.gpio_core
generic map
(
C_DW => C_S_AXI_DATA_WIDTH,
C_AW => C_S_AXI_ADDR_WIDTH,
C_GPIO_WIDTH => C_GPIO_WIDTH,
C_GPIO2_WIDTH => C_GPIO2_WIDTH,
C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH,
C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT,
C_DOUT_DEFAULT => C_DOUT_DEFAULT,
C_TRI_DEFAULT => C_TRI_DEFAULT,
C_IS_DUAL => C_IS_DUAL,
C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2,
C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Bus2IP_Clk,
Rst => bus2ip_reset,
ABus_Reg => Bus2IP_Addr,
BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1),
DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1),
RNW_Reg => Bus2IP_RNW,
GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1),
GPIO_xferAck => GPIO_xferAck_i,
GPIO_Select => bus2ip_cs(0),
GPIO_intr => ip2bus_intrevent(0),
GPIO2_intr => ip2bus_intrevent(1),
GPIO_IO_I => gpio_io_i,
GPIO_IO_O => gpio_io_o,
GPIO_IO_T => gpio_io_t,
GPIO2_IO_I => gpio2_io_i,
GPIO2_IO_O => gpio2_io_o,
GPIO2_IO_T => gpio2_io_t
);
Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1'
and bus2ip_addr (5) = '0'else
Bus2IP2_Data_i;
BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate
Bus2IP1_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH);
end generate BUS_CONV_ch1;
BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate
Bus2IP2_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH);
end generate BUS_CONV_ch2;
end architecture imp;
| gpl-2.0 |
nsauzede/cpu86 | p2_lcd_spi/drigmorn1_top.vhd | 1 | 11654 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Toplevel : CPU86, 256Byte ROM, 16550 UART, 40K8 SRAM (all blockrams used)--
-------------------------------------------------------------------------------
-- Revision History: --
-- --
-- Date: Revision Author --
-- --
-- 30 Dec 2007 0.1 H. Tiggeler First version --
-- 17 May 2008 0.75 H. Tiggeler Updated for CPU86 ver0.75 --
-- 27 Jun 2008 0.79 H. Tiggeler Changed UART to Opencores 16750 --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY drigmorn1_top IS
PORT(
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
vramaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
spi_cs : out std_logic;
spi_clk : out std_logic;
spi_mosi : out std_logic;
spi_miso : in std_logic;
buttons : in STD_LOGIC_VECTOR (3 downto 0);
leds : out STD_LOGIC_VECTOR (3 downto 0);
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END drigmorn1_top ;
ARCHITECTURE struct OF drigmorn1_top IS
-- Architecture declarations
signal csromn : std_logic;
signal csesramn : std_logic;
signal csisramn : std_logic;
signal csspin : std_logic;
signal csspi : std_logic;
signal csbutled : std_logic := '1';
-- Internal signal declarations
signal leds_b : STD_LOGIC_VECTOR (3 downto 0);
signal vramaddr2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
-- signal vrambase : STD_LOGIC_VECTOR(15 DOWNTO 0):=x"4000";
signal vrambase : STD_LOGIC_VECTOR(15 DOWNTO 0):=x"0000";
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL clk : std_logic;
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_esram : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_spi : std_logic_vector(7 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL sel_s : std_logic_vector(5 DOWNTO 0);
-- SIGNAL sel_s : std_logic_vector(4 DOWNTO 0);
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL wran : std_logic;
SIGNAL wrcom : std_logic;
SIGNAL wspi : std_logic;
SIGNAL wrn : std_logic;
signal rxclk_s : std_logic;
BEGIN
sram_addr <= '0' & abus;
---- sram_data <= dbus_.
-- dbus_esram <= sram_data;
-- sram_data <= (others => 'Z') when rdn='0' else sram_data;
-- sram_ce <= csesramn;
-- sram_we <= wrn;
-- sram_oe <= rdn;
process(csesramn,wrn,rdn,dbus_out,sram_data)
begin
sram_ce <= '1';
sram_we <= '1';
sram_oe <= '1';
sram_data <= (others => 'Z');
if csesramn='0' then
sram_ce <= '0';
if wrn='0' then
sram_data <= dbus_out;
sram_we <= '0';
else
if rdn='0' then
dbus_esram <= sram_data;
sram_oe <= '0';
end if;
end if;
end if;
end process;
leds <= leds_b;
leds_b <= dbus_out(3 downto 0) when (csbutled='0') and (wrn='0') else leds_b;
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 mux
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom,dbus_esram,dbus_spi,buttons)
-- process(sel_s,dbus_com1,dbus_in,dbus_rom,dbus_esram,dbus_spi)
begin
case sel_s is
when "011111" => dbus_in_cpu <= dbus_com1; -- UART
when "101111" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when "110111" => dbus_in_cpu <= dbus_in; -- Embedded SRAM
when "111011" => dbus_in_cpu <= dbus_spi; -- SPI
-- when "111101" => dbus_in_cpu <= dbus_esram; -- External SRAM
when "111101" => dbus_in_cpu <= sram_data; -- External SRAM
when "111110" => dbus_in_cpu <= x"0" & buttons; -- butled
when others => dbus_in_cpu <= dbus_in_cpu; -- Embedded SRAM
end case;
end process;
-- HDL Embedded Text Block 7 clogic
clk <= CLOCK_40MHZ;
wrcom <= not wrn;
wea(0)<= not wrn and not csisramn;
wspi<= not wrn;
PIN4 <= resoutn; -- For debug only
-- dbus_in_cpu multiplexer
sel_s <= cscom1 & csromn & csisramn & csspin & csesramn & csbutled;
-- sel_s <= cscom1 & csromn & csisramn & csspin & csesramn;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
-- cscom1 <= '0' when (abus(15 downto 3)="0000001111111" AND iom='1') else '1';
cscom1 <= '0' when ((abus(15 downto 4)=X"03F") AND iom='1') else '1';
-- SPI, 0x400-0x407
-- csspin <= '0' when (abus(15 downto 3)="0000010000000" AND iom='1') else '1';
csspin <= '0' when ((abus(15 downto 4)=X"040") AND iom='1') else '1';
csspi <= not csspin;
-- BUTLED, 0x500-0x507
csbutled <= '0' when ((abus(15 downto 4)=X"050") AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
-- external SRAM
-- 0xE0000
-- csesramn <= '0' when ((abus(19 downto 16)=X"1") AND iom='0') else '1'; -- 0x10000
csesramn <= '0' when ((abus(19 downto 16)=X"E") AND iom='0') else '1'; -- 0xE0000
-- csesramn <= '0' when (csromn='1' and csisramn='1' AND iom='0') else '1';
-- csesramn <= not (cscom1 and csromnn and csiramn);
-- internal SRAM
-- below 0x10000
csisramn <= '0' when ((abus(19 downto 16)=X"0") AND iom='0') else '1';
spim0: entity work.spi_master
port map ( clk => clk,
reset => por,
cpu_address => abus(2 downto 0),
cpu_wait => open,
data_in => dbus_out,
data_out => dbus_spi,
enable => csspi,
req_read => '0',
req_write => wspi,
slave_cs => spi_cs,
slave_clk => spi_clk,
slave_mosi => spi_mosi,
slave_miso => spi_miso
);
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
por <= NOT(PIN3);
-- Instance port mappings.
U_1 : entity work.cpu86
PORT MAP (
clk => clk,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => LED1,
dbus_out => dbus_out,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
-- U_3 : blk_mem_40K
-- PORT MAP (
-- clka => clk,
-- dina => dbus_out,
-- addra => abus(15 DOWNTO 0),
-- wea => wea,
-- douta => dbus_in
-- );
vramaddr2 <= vramaddr + vrambase;
U_3 : entity work.blk_mem_40K
PORT MAP (
clka => clk,
dina => dbus_out,
addra => abus(15 DOWNTO 0),
wea => wea,
douta => dbus_in,
clkb => clk,
dinb => (others => '0'),
addrb => vramaddr2,
web => (others => '0'),
doutb => vramdata
);
U_2 : entity work.bootstrap
PORT MAP (
abus => abus(7 DOWNTO 0),
dbus => dbus_rom
);
U_0 : entity work.uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => clk,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RXD,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
END struct;
| gpl-2.0 |
nsauzede/cpu86 | p2_lcd_spi/cpu86pack.vhd | 3 | 17116 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
PACKAGE cpu86pack IS
constant RESET_CS_C : std_logic_vector(15 downto 0) := (others => '1'); -- FFFF:0000
constant RESET_IP_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_ES_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_SS_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_DS_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_VECTOR_C : std_logic_vector(19 downto 0) := (RESET_CS_C & X"0") + (X"0" & RESET_IP_C);
constant MUL_MCD_C : std_logic_vector(4 downto 0) := "00010"; -- mul MCP
-- Serial Divider delay
-- changed later to done signal
-- You can gain 1 clk cycle, done can be asserted 1 cycle earlier
constant DIV_MCD_C : std_logic_vector(4 downto 0) := "10011"; -- div waitstates 19!
constant ONE : std_logic := '1';
constant ZERO : std_logic := '0';
constant ZEROVECTOR_C : std_logic_vector(31 downto 0) := X"00000000";
-- Minimum value for MAX_WS="000", this result in a 2 cycle rd/wr strobe
-- Total Read cycle is 1 cycle for address setup + 2 cycles for rd/wr strobe, thus
-- minimum bus cycle is 3 clk cycles.
constant WS_WIDTH : integer := 3; -- 2^WS_WIDTH=MAX Waitstates
constant MAX_WS : std_logic_vector(WS_WIDTH-1 downto 0) := "000"; -- 3 clk bus cycles
constant DONTCARE : std_logic_vector(31 downto 0):=X"FFFFFFFF";
-- Status record containing some data and flag register
type instruction_type is record
ireg : std_logic_vector(7 downto 0); -- Instruction register
xmod : std_logic_vector(1 downto 0); -- mod is a reserved word
reg : std_logic_vector(2 downto 0); -- between mode and rm
rm : std_logic_vector(2 downto 0);
data : std_logic_vector(15 downto 0);
disp : std_logic_vector(15 downto 0);
nb : std_logic_vector(2 downto 0); -- Number of bytes
end record;
-- Status record containing some data and flag register
type status_out_type is record
ax : std_logic_vector(15 downto 0);
cx_one : std_logic; -- '1' if CX=0001
cx_zero : std_logic; -- '1' if CX=0000
cl : std_logic_vector(7 downto 0); -- 5 bits shift/rotate counter
flag : std_logic_vector(15 downto 0);
div_err : std_logic; -- Divider overflow
end record;
--------------------------------------------------------------------------------------
-- Data Path Records
--------------------------------------------------------------------------------------
type path_in_type is record
datareg_input : std_logic_vector(6 downto 0); -- dimux(3) & w & seldreg(3)
alu_operation : std_logic_vector(14 downto 0);-- selalua(4) & selalub(4) & aluopr(7)
dbus_output : std_logic_vector(1 downto 0); -- (Odd/Even) domux setting
segreg_input : std_logic_vector(3 downto 0); -- simux & selsreg
ea_output : std_logic_vector(9 downto 0); -- dispmux(3) & eamux(4) & [flag]&segop(2)
end record;
-- Write Strobe Record for Data Path
type write_in_type is record
wrd : std_logic; -- Write datareg
wralu : std_logic; -- Write ALU result
wrcc : std_logic; -- Write Flag register
wrs : std_logic; -- Write Segment register
wrip : std_logic; -- Write Instruction Pointer
wrop : std_logic; -- Write Segment Prefix register, Set Prefix Flag
wrtemp: std_logic; -- Write to ALU_TEMP register
end record;
constant SET_OPFLAG : std_logic:='1'; -- Override Prefix Flag
-- DIMUX
constant DATAIN_IN : std_logic_vector(2 downto 0) := "000";
constant EABUS_IN : std_logic_vector(2 downto 0) := "001";
constant ALUBUS_IN : std_logic_vector(2 downto 0) := "010";
constant MDBUS_IN : std_logic_vector(2 downto 0) := "011";
constant ES_IN : std_logic_vector(2 downto 0) := "100";
constant CS_IN : std_logic_vector(2 downto 0) := "101";
constant SS_IN : std_logic_vector(2 downto 0) := "110";
constant DS_IN : std_logic_vector(2 downto 0) := "111";
-- SIMUX Segment Register input Mux
constant SDATAIN_IN : std_logic_vector(1 downto 0) := "00";
constant SEABUS_IN : std_logic_vector(1 downto 0) := "01"; -- Effective Address
constant SALUBUS_IN : std_logic_vector(1 downto 0) := "10";
constant SMDBUS_IN : std_logic_vector(1 downto 0) := "11";
-- DOMUX (Note bit 2=odd/even)
constant ALUBUS_OUT : std_logic_vector(1 downto 0) := "00";
constant CCBUS_OUT : std_logic_vector(1 downto 0) := "01";
constant DIBUS_OUT : std_logic_vector(1 downto 0) := "10";
constant IPBUS_OUT : std_logic_vector(1 downto 0) := "11";
-- dispmux(3) & eamux(4) & poflag & segop[1:0]
-- note some bits may be dontcare!
constant NB_ES_IP : std_logic_vector(9 downto 0) := "0000000000"; -- IPREG+NB ADDR=ES:IP
constant NB_CS_IP : std_logic_vector(9 downto 0) := "0000000001";
constant NB_SS_IP : std_logic_vector(9 downto 0) := "0000000010";
constant NB_DS_IP : std_logic_vector(9 downto 0) := "0000000011";
constant NB_ES_EA : std_logic_vector(9 downto 0) := "0000001000"; -- IPREG+NB ADDR=EA
constant NB_CS_EA : std_logic_vector(9 downto 0) := "0000001001";
constant NB_SS_EA : std_logic_vector(9 downto 0) := "0000001010";
constant NB_DS_EA : std_logic_vector(9 downto 0) := "0000001011";
constant DISP_ES_EA : std_logic_vector(9 downto 0) := "0010001000"; -- IPREG+DISP ADDR=EA
constant DISP_CS_EA : std_logic_vector(9 downto 0) := "0010001001";
constant DISP_SS_EA : std_logic_vector(9 downto 0) := "0010001010";
constant DISP_DS_EA : std_logic_vector(9 downto 0) := "0010001011";
constant DISP_CS_IP : std_logic_vector(9 downto 0) := "0010000001"; -- Used for Jx instructions
constant PORT_00_DX : std_logic_vector(6 downto 0) := "0000010"; -- EAMUX IN/OUT instruction
constant PORT_00_EA : std_logic_vector(6 downto 0) := "0000001"; -- EAMUX Segm=00 00:IP or 00:DISP
constant NB_SS_SP : std_logic_vector(6 downto 0) := "0000100"; -- IP=IP+NBREQ, EAMUX=SS:SP , 100, 101, 110 unused
constant LD_SS_SP : std_logic_vector(6 downto 0) := "0100100"; -- Load new IP from MDBUS & out=SS:SP
constant LD_MD_IP : std_logic_vector(9 downto 0) := "0100000001"; -- Load new IP from MDBUS (e.g. RET instruction)
constant LD_CS_IP : std_logic_vector(9 downto 0) := "0110000001"; -- Load new IP (e.g. RET instruction)
constant EA_CS_IP : std_logic_vector(9 downto 0) := "1000001001"; -- Load new IP (e.g. RET instruction)
constant IPB_CS_IP : std_logic_vector(9 downto 0) := "1110000001"; -- Select IPBUS=IPREG
constant MD_EA2_DS : std_logic_vector(9 downto 0) := "0100011011"; -- IP<-MD, addr=DS:EA2
-- SELALUA/B or SELDREG(2 downto 0)
constant REG_AX : std_logic_vector(3 downto 0) := "0000"; -- W=1 Into ALUBUS A or B
constant REG_CX : std_logic_vector(3 downto 0) := "0001";
constant REG_DX : std_logic_vector(3 downto 0) := "0010";
constant REG_BX : std_logic_vector(3 downto 0) := "0011";
constant REG_SP : std_logic_vector(3 downto 0) := "0100";
constant REG_BP : std_logic_vector(3 downto 0) := "0101";
constant REG_SI : std_logic_vector(3 downto 0) := "0110";
constant REG_DI : std_logic_vector(3 downto 0) := "0111";
constant REG_DATAIN : std_logic_vector(3 downto 0) := "1000"; -- Pass data_in to ALU
constant REG_MDBUS : std_logic_vector(3 downto 0) := "1111"; -- Pass memory bus (mdbus) to ALU
-- Only for SELALUB
constant REG_CONST1 : std_logic_vector(3 downto 0) := "1001"; -- Used for INC/DEC function, W=0/1
constant REG_CONST2 : std_logic_vector(3 downto 0) := "1010"; -- Used for POP/PUSH function W=1
-- W+SELDREG
constant REG_AH : std_logic_vector(3 downto 0) := "0100"; -- W=1 SELDREG=AH
---------------------------------------------------------------
-- ALU Operations
-- Use ireg(5 downto 3) / modrm(5 downto 3) / ireg(3 downto 0)
-- Constants for
---------------------------------------------------------------
constant ALU_ADD : std_logic_vector(6 downto 0) := "0000000";
constant ALU_OR : std_logic_vector(6 downto 0) := "0000001";
constant ALU_ADC : std_logic_vector(6 downto 0) := "0000010";
constant ALU_SBB : std_logic_vector(6 downto 0) := "0000011";
constant ALU_AND : std_logic_vector(6 downto 0) := "0000100";
constant ALU_SUB : std_logic_vector(6 downto 0) := "0000101";
constant ALU_XOR : std_logic_vector(6 downto 0) := "0000110";
constant ALU_CMP : std_logic_vector(6 downto 0) := "0000111"; -- See also ALU_CMPS
constant ALU_TEST0 : std_logic_vector(6 downto 0) := "0001000";
constant ALU_TEST1 : std_logic_vector(6 downto 0) := "0001101";
-- Random assignment, these can be changed.
constant ALU_PUSH : std_logic_vector(6 downto 0) := "0001001"; -- Used for PUSH (SUB)
constant ALU_POP : std_logic_vector(6 downto 0) := "0001010"; -- Used for POP (ADD)
constant ALU_REGL : std_logic_vector(6 downto 0) := "0001011"; -- alureg(15..0) (latched alu_busb)
constant ALU_REGH : std_logic_vector(6 downto 0) := "0111011"; -- alureg(31..16) (latched alu_busa)
constant ALU_PASSA : std_logic_vector(6 downto 0) := "0001100"; -- abus_s only
constant ALU_TEMP : std_logic_vector(6 downto 0) := "1111001"; -- Used to select temp/scratchpad register (80186 only)
-- CONST & instr.irg(3 downto 0)
constant ALU_SAHF : std_logic_vector(6 downto 0) := "0001110"; -- AH -> Flags
-- CONST & instr.irg(3 downto 0)
constant ALU_LAHF : std_logic_vector(6 downto 0) := "0001111"; -- Flags->ALUBUS (->AH)
-- CONSTANT & instr.ireg(1) & modrm.reg(5 downto 3)
-- CONSTANT=001
constant ALU_ROL1 : std_logic_vector(6 downto 0) := "0010000"; -- count=1
constant ALU_ROR1 : std_logic_vector(6 downto 0) := "0010001";
constant ALU_RCL1 : std_logic_vector(6 downto 0) := "0010010";
constant ALU_RCR1 : std_logic_vector(6 downto 0) := "0010011";
constant ALU_SHL1 : std_logic_vector(6 downto 0) := "0010100";
constant ALU_SHR1 : std_logic_vector(6 downto 0) := "0010101";
constant ALU_SAR1 : std_logic_vector(6 downto 0) := "0010111";
constant ALU_ROL : std_logic_vector(6 downto 0) := "0011000"; -- Count in CL
constant ALU_ROR : std_logic_vector(6 downto 0) := "0011001";
constant ALU_RCL : std_logic_vector(6 downto 0) := "0011010";
constant ALU_RCR : std_logic_vector(6 downto 0) := "0011011";
constant ALU_SHL : std_logic_vector(6 downto 0) := "0011100";
constant ALU_SHR : std_logic_vector(6 downto 0) := "0011101";
constant ALU_SAR : std_logic_vector(6 downto 0) := "0011111";
-- CONST & modrm.reg(5 downto 3)/instr.ireg(5 downto 3)
constant ALU_INC : std_logic_vector(6 downto 0) := "0100000"; -- Increment
constant ALU_DEC : std_logic_vector(6 downto 0) := "0100001"; -- Decrement also used for LOOP/JCXZ
constant ALU_CLRTIF : std_logic_vector(6 downto 0) := "0100010"; -- Clear TF/IF flag, used for INT
constant ALU_CMPS : std_logic_vector(6 downto 0) := "0100111"; -- Compare String ALUREG-MDBUS
constant ALU_SCAS : std_logic_vector(6 downto 0) := "0101111"; -- AX/AL-MDBUS, no SEXT
-- CONST & instr.irg(3 downto 0)
constant ALU_CMC : std_logic_vector(6 downto 0) := "0100101"; -- Complement Carry
constant ALU_CLC : std_logic_vector(6 downto 0) := "0101000"; -- Clear Carry
constant ALU_STC : std_logic_vector(6 downto 0) := "0101001"; -- Set Carry
constant ALU_CLI : std_logic_vector(6 downto 0) := "0101010"; -- Clear interrupt
constant ALU_STI : std_logic_vector(6 downto 0) := "0101011"; -- Set Interrupt
constant ALU_CLD : std_logic_vector(6 downto 0) := "0101100"; -- Clear Direction
constant ALU_STD : std_logic_vector(6 downto 0) := "0101101"; -- Set Direction
-- CONST & modrm.reg(5 downto 3)
constant ALU_TEST2 : std_logic_vector(6 downto 0) := "0110000"; -- F6/F7
constant ALU_NOT : std_logic_vector(6 downto 0) := "0110010"; -- F6/F7
constant ALU_NEG : std_logic_vector(6 downto 0) := "0110011"; -- F6/F7
constant ALU_MUL : std_logic_vector(6 downto 0) := "0110100"; -- F6/F7
constant ALU_IMUL : std_logic_vector(6 downto 0) := "0110101"; -- F6/F7
constant ALU_DIV : std_logic_vector(6 downto 0) := "0110110"; -- F6/F7
constant ALU_IDIV : std_logic_vector(6 downto 0) := "0110111"; -- F6/F7
-- Second cycle write DX
constant ALU_MUL2 : std_logic_vector(6 downto 0) := "0111100"; -- F6/F7
constant ALU_IMUL2 : std_logic_vector(6 downto 0) := "0111101"; -- F6/F7
constant ALU_DIV2 : std_logic_vector(6 downto 0) := "0111110"; -- F6/F7
constant ALU_IDIV2 : std_logic_vector(6 downto 0) := "0111111"; -- F6/F7
-- CONST & instr.ireg(3 downto 0)
constant ALU_SEXT : std_logic_vector(6 downto 0) := "0111000"; -- Used for CBW
constant ALU_SEXTW : std_logic_vector(6 downto 0) := "0111001"; -- Used for CWD
-- CONSTANT & & instr.ireg(1) & instr.ireg(5 downto 3)
constant ALU_AAM : std_logic_vector(6 downto 0) := "1000010";
constant ALU_AAD : std_logic_vector(6 downto 0) := "1001010";
constant ALU_DAA : std_logic_vector(6 downto 0) := "1001100";
constant ALU_DAS : std_logic_vector(6 downto 0) := "1001101";
constant ALU_AAA : std_logic_vector(6 downto 0) := "1001110";
constant ALU_AAS : std_logic_vector(6 downto 0) := "1001111";
constant ALU_ADD_SE : std_logic_vector(6 downto 0) := "1100000";
constant ALU_OR_SE : std_logic_vector(6 downto 0) := "1100001";
constant ALU_ADC_SE : std_logic_vector(6 downto 0) := "1100010";
constant ALU_SBB_SE : std_logic_vector(6 downto 0) := "1100011";
constant ALU_AND_SE : std_logic_vector(6 downto 0) := "1100100";
constant ALU_SUB_SE : std_logic_vector(6 downto 0) := "1100101";
constant ALU_XOR_SE : std_logic_vector(6 downto 0) := "1100110";
constant ALU_CMP_SE : std_logic_vector(6 downto 0) := "1100111";
END cpu86pack;
| gpl-2.0 |
nsauzede/cpu86 | p2_lcd_spi/spi_master.vhd | 2 | 7000 | --+-----------------------------------+-------------------------------------+--
--| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
--| ___ ___ ___ ___( _ ) / _ \ | [email protected] |--
--| / __|/ _ \ / __|_ / _ \| | | | | |--
--| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
--| |___/\___/ \___/___\___/ \___/ | |--
--| | http://sowerbutts.com/ |--
--+-----------------------------------+-------------------------------------+--
--| A rudimentary SPI master peripheral |--
--+-------------------------------------------------------------------------+--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spi_master is
port ( clk : in std_logic;
reset : in std_logic;
cpu_address : in std_logic_vector(2 downto 0);
cpu_wait : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
enable : in std_logic;
req_read : in std_logic;
req_write : in std_logic;
slave_cs : out std_logic;
slave_clk : out std_logic;
slave_mosi : out std_logic;
slave_miso : in std_logic
);
end spi_master;
-- registers:
-- base+0 -- chip select control; bit 0 is slave_cs
-- base+1 -- status register; bit 0 indicates "transmitter busy"
-- base+2 -- transmitter: write a byte here, starts SPI bus transaction
-- base+3 -- receiver: last byte received (updated on each transation)
-- base+4 -- clock divider: clk counts from 0 to whatever is in this register before proceeding
--
-- Note that if an SPI transfer is underway already the CPU will be
-- forced to wait until it completes before any register can be
-- read or written. This is very convenient as it means you can
-- just read or write bytes without checking the status register.
architecture Behavioral of spi_master is
-- start up in idle state
signal slave_cs_register : std_logic := '1';
signal slave_clk_register : std_logic := '1'; --MODE3
-- signal slave_clk_register : std_logic := '0'; --MODE0
signal slave_mosi_register: std_logic := '0';
signal data_out_sr : std_logic_vector(7 downto 0) := (others => '0'); -- shifted left ie MSB <- LSB
-- signal data_out_sr : std_logic_vector(7 downto 0) := x"55"; -- shifted left ie MSB <- LSB
signal data_in_sr : std_logic_vector(7 downto 0) := (others => '0'); -- shifted left ie MSB <- LSB
signal busy_sr : std_logic_vector(7 downto 0) := (others => '0'); -- shifted left ie MSB <- LSB
signal clk_divide_target : unsigned(7 downto 0) := (others => '0');
-- signal clk_divide_target : unsigned(7 downto 0) := x"aa";
signal clk_divide_value : unsigned(7 downto 0) := (others => '0');
signal cpu_was_idle : std_logic := '1';
-- cpu visible registers
signal chip_select_out : std_logic_vector(7 downto 0);
signal status_data_out : std_logic_vector(7 downto 0);
begin
chip_select_out <= "0000000" & slave_cs_register;
status_data_out <= "0000000" & busy_sr(7);
cpu_wait <= busy_sr(7);
with cpu_address select
data_out <=
chip_select_out when "000",
status_data_out when "001",
data_out_sr when "010",
data_in_sr when "011",
std_logic_vector(clk_divide_target) when "100",
status_data_out when others;
-- data_out <= data_out_sr;
slave_cs <= slave_cs_register;
slave_clk <= slave_clk_register;
slave_mosi <= slave_mosi_register;
spimaster_proc: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
slave_cs_register <= '1';
slave_clk_register <= '1'; --MODE3
-- slave_clk_register <= '0'; --MODE0
slave_mosi_register <= '0';
data_out_sr <= (others => '0');
-- data_out_sr <= x"aa";
data_in_sr <= (others => '0');
busy_sr <= (others => '0');
clk_divide_target <= (others => '0');
clk_divide_value <= (others => '0');
cpu_was_idle <= '1';
else
-- divide down input clk to get 2 * spi clk
clk_divide_value <= clk_divide_value + 1;
if clk_divide_value = clk_divide_target then
clk_divide_value <= to_unsigned(0, 8);
end if;
if busy_sr(7) = '1' then
if clk_divide_value = clk_divide_target then
-- we're in the midst of a transaction! whoo!
if slave_clk_register = '1' then
-- clk is high; next cycle will be falling edge of clk
slave_clk_register <= '0';
slave_mosi_register <= data_out_sr(7);
-- shift data out
data_out_sr <= data_out_sr(6 downto 0) & '0';
else
-- clk is low; next cycle will be rising edge of clk
slave_clk_register <= '1';
-- shift busy
busy_sr <= busy_sr(6 downto 0) & '0';
-- latch data in
data_in_sr <= data_in_sr(6 downto 0) & slave_miso;
end if;
end if;
end if;
if enable = '1' and req_write = '1' then
if busy_sr(7) = '0' and cpu_was_idle = '1' then
cpu_was_idle <= '0';
case cpu_address is
when "000" =>
slave_cs_register <= data_in(0);
when "010" =>
-- only allow writes when transmitter is idle
data_out_sr <= data_in;
busy_sr <= (others => '1');
when "100" =>
clk_divide_target <= unsigned(data_in);
when others => -- no change
end case;
else
cpu_was_idle <= cpu_was_idle;
end if;
else
cpu_was_idle <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
nsauzede/cpu86 | papilio2_drigmorn1/ipcore_dir/clk32to40/simulation/timing/clk32to40_tb.vhd | 2 | 6460 | -- file: clk32to40_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clk32to40_tb is
end clk32to40_tb;
architecture test of clk32to40_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.25 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clk32to40_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clk32to40_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
| gpl-2.0 |
nsauzede/cpu86 | p2_lcd_spi/slib_edge_detect.vhd | 3 | 1756 | --
-- Signal edge detect
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end slib_edge_detect;
architecture rtl of slib_edge_detect is
signal iDd : std_logic; -- D register
begin
-- Store D
ED_D: process (RST, CLK)
begin
if (RST = '1') then
iDd <= '0';
elsif (CLK'event and CLK='1') then
iDd <= D;
end if;
end process;
-- Output ports
RE <= '1' when iDd = '0' and D = '1' else '0';
FE <= '1' when iDd = '1' and D = '0' else '0';
end rtl;
| gpl-2.0 |
nsauzede/cpu86 | papilio1/uart_tx.vhd | 1 | 5192 | -- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for UART_TX
--
entity uart_tx is
Port ( data_in : in std_logic_vector(7 downto 0);
write_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end uart_tx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for UART_TX
--
architecture macro_level_definition of uart_tx is
--
------------------------------------------------------------------------------------
--
-- Components used in UART_TX and defined in subsequent entities.
--
------------------------------------------------------------------------------------
--
-- Constant (K) Compact UART Transmitter
--
component kcuart_tx
Port ( data_in : in std_logic_vector(7 downto 0);
send_character : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
Tx_complete : out std_logic;
clk : in std_logic);
end component;
--
-- 'Bucket Brigade' FIFO
--
component bbfifo_16x8
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used in UART_TX
--
------------------------------------------------------------------------------------
--
signal fifo_data_out : std_logic_vector(7 downto 0);
signal fifo_data_present : std_logic;
signal fifo_read : std_logic;
--
------------------------------------------------------------------------------------
--
-- Start of UART_TX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- 8 to 1 multiplexer to convert parallel data to serial
kcuart: kcuart_tx
port map ( data_in => fifo_data_out,
send_character => fifo_data_present,
en_16_x_baud => en_16_x_baud,
serial_out => serial_out,
Tx_complete => fifo_read,
clk => clk);
buf: bbfifo_16x8
port map ( data_in => data_in,
data_out => fifo_data_out,
reset => reset_buffer,
write => write_buffer,
read => fifo_read,
full => buffer_full,
half_full => buffer_half_full,
data_present => fifo_data_present,
clk => clk);
end macro_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_TX.VHD
--
------------------------------------------------------------------------------------
| gpl-2.0 |
nsauzede/cpu86 | papilio2_lcd/uart_16750.vhd | 3 | 53058 | --
-- UART 16750
--
-- Author: Sebastian Witt
-- Date: 29.01.2008
-- Version: 1.4
--
-- History: 1.0 - Initial version
-- 1.1 - THR empty interrupt register connected to RST
-- 1.2 - Registered outputs
-- 1.3 - Automatic flow control
-- 1.4 - De-assert IIR FIFO64 when FIFO is disabled
--
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART
entity uart_16750 is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
BAUDCE : in std_logic; -- Baudrate generator clock enable
CS : in std_logic; -- Chip select
WR : in std_logic; -- Write to UART
RD : in std_logic; -- Read from UART
A : in std_logic_vector(2 downto 0); -- Register select
DIN : in std_logic_vector(7 downto 0); -- Data bus input
DOUT : out std_logic_vector(7 downto 0); -- Data bus output
DDIS : out std_logic; -- Driver disable
INT : out std_logic; -- Interrupt output
OUT1N : out std_logic; -- Output 1
OUT2N : out std_logic; -- Output 2
RCLK : in std_logic; -- Receiver clock (16x baudrate)
BAUDOUTN : out std_logic; -- Baudrate generator output (16x baudrate)
RTSN : out std_logic; -- RTS output
DTRN : out std_logic; -- DTR output
CTSN : in std_logic; -- CTS input
DSRN : in std_logic; -- DSR input
DCDN : in std_logic; -- DCD input
RIN : in std_logic; -- RI input
SIN : in std_logic; -- Receiver input
SOUT : out std_logic -- Transmitter output
);
end uart_16750;
architecture rtl of uart_16750 is
-- UART transmitter
component uart_transmitter is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
TXCLK : in std_logic; -- Transmitter clock (2x baudrate)
TXSTART : in std_logic; -- Start transmitter
CLEAR : in std_logic; -- Clear transmitter state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
BC : in std_logic; -- Break control
DIN : in std_logic_vector(7 downto 0); -- Input data
TXFINISHED : out std_logic; -- Transmitter operation finished
SOUT : out std_logic -- Transmitter output
);
end component;
-- UART receiver
component uart_receiver is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
RXCLK : in std_logic; -- Receiver clock (16x baudrate)
RXCLEAR : in std_logic; -- Reset receiver state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
SIN : in std_logic; -- Receiver input
PE : out std_logic; -- Parity error
FE : out std_logic; -- Framing error
BI : out std_logic; -- Break interrupt
DOUT : out std_logic_vector(7 downto 0); -- Output data
RXFINISHED : out std_logic -- Receiver operation finished
);
end component;
-- UART interrupt control
component uart_interrupt is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
IER : in std_logic_vector(3 downto 0); -- IER 3:0
LSR : in std_logic_vector(4 downto 0); -- LSR 4:0
THI : in std_logic; -- Transmitter holding register empty interrupt
RDA : in std_logic; -- Receiver data available
CTI : in std_logic; -- Character timeout indication
AFE : in std_logic; -- Automatic flow control enable
MSR : in std_logic_vector(3 downto 0); -- MSR 3:0
IIR : out std_logic_vector(3 downto 0); -- IIR 3:0
INT : out std_logic -- Interrupt
);
end component;
-- UART baudrate generator
component uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end component;
-- UART FIFO
component slib_fifo is
generic (
WIDTH : integer := 8; -- FIFO width
SIZE_E : integer := 6 -- FIFO size (2^SIZE_E)
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear FIFO
WRITE : in std_logic; -- Write to FIFO
READ : in std_logic; -- Read from FIFO
D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input
Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output
EMPTY : out std_logic; -- FIFO is empty
FULL : out std_logic; -- FIFO is full
USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage
);
end component;
-- Edge detect
component slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end component;
-- Input synchronization
component slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end component;
-- Input filter
component slib_input_filter is
generic (
SIZE : natural := 4 -- Filter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end component;
-- Clock enable generation
component slib_clock_div is
generic (
RATIO : integer := 8 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end component;
-- Global device signals
signal iCSWR : std_logic; -- Chipselect and write
signal iCSRD : std_logic; -- Chipselect and read
signal iWriteFE : std_logic; -- Write falling edge
signal iReadFE : std_logic; -- Read falling edge
signal iWrite : std_logic; -- Write to UART
signal iRead : std_logic; -- Read from UART
signal iA : std_logic_vector(2 downto 0); -- UART register address
signal iDIN : std_logic_vector(7 downto 0); -- UART data input
-- UART registers read/write signals
signal iRBRRead : std_logic; -- Read from RBR
signal iTHRWrite : std_logic; -- Write to THR
signal iDLLWrite : std_logic; -- Write to DLL
signal iDLMWrite : std_logic; -- Write to DLM
signal iIERWrite : std_logic; -- Write to IER
signal iIIRRead : std_logic; -- Read from IIR
signal iFCRWrite : std_logic; -- Write to FCR
signal iLCRWrite : std_logic; -- Write to LCR
signal iMCRWrite : std_logic; -- Write to MCR
signal iLSRRead : std_logic; -- Read from LSR
signal iMSRRead : std_logic; -- Read from MSR
signal iSCRWrite : std_logic; -- Write to SCR
-- UART registers
signal iTSR : std_logic_vector(7 downto 0); -- Transmitter holding register
signal iRBR : std_logic_vector(7 downto 0); -- Receiver buffer register
signal iDLL : std_logic_vector(7 downto 0); -- Divisor latch LSB
signal iDLM : std_logic_vector(7 downto 0); -- Divisor latch MSB
signal iIER : std_logic_vector(7 downto 0); -- Interrupt enable register
signal iIIR : std_logic_vector(7 downto 0); -- Interrupt identification register
signal iFCR : std_logic_vector(7 downto 0); -- FIFO control register
signal iLCR : std_logic_vector(7 downto 0); -- Line control register
signal iMCR : std_logic_vector(7 downto 0); -- Modem control register
signal iLSR : std_logic_vector(7 downto 0); -- Line status register
signal iMSR : std_logic_vector(7 downto 0); -- Modem status register
signal iSCR : std_logic_vector(7 downto 0); -- Scratch register
-- IER register signals
signal iIER_ERBI : std_logic; -- IER: Enable received data available interrupt
signal iIER_ETBEI : std_logic; -- IER: Enable transmitter holding register empty interrupt
signal iIER_ELSI : std_logic; -- IER: Enable receiver line status interrupt
signal iIER_EDSSI : std_logic; -- IER: Enable modem status interrupt
-- IIR register signals
signal iIIR_PI : std_logic; -- IIR: Pending interrupt
signal iIIR_ID0 : std_logic; -- IIR: Interrupt ID0
signal iIIR_ID1 : std_logic; -- IIR: Interrupt ID1
signal iIIR_ID2 : std_logic; -- IIR: Interrupt ID2
signal iIIR_FIFO64 : std_logic; -- IIR: 64 byte FIFO enabled
-- FCR register signals
signal iFCR_FIFOEnable : std_logic; -- FCR: FIFO enable
signal iFCR_RXFIFOReset : std_logic; -- FCR: Receiver FIFO reset
signal iFCR_TXFIFOReset : std_logic; -- FCR: Transmitter FIFO reset
signal iFCR_DMAMode : std_logic; -- FCR: DMA mode select
signal iFCR_FIFO64E : std_logic; -- FCR: 64 byte FIFO enable
signal iFCR_RXTrigger : std_logic_vector(1 downto 0); -- FCR: Receiver trigger
-- LCR register signals
signal iLCR_WLS : std_logic_vector(1 downto 0); -- LCR: Word length select
signal iLCR_STB : std_logic; -- LCR: Number of stop bits
signal iLCR_PEN : std_logic; -- LCR: Parity enable
signal iLCR_EPS : std_logic; -- LCR: Even parity select
signal iLCR_SP : std_logic; -- LCR: Sticky parity
signal iLCR_BC : std_logic; -- LCR: Break control
signal iLCR_DLAB : std_logic; -- LCR: Divisor latch access bit
-- MCR register signals
signal iMCR_DTR : std_logic; -- MCR: Data terminal ready
signal iMCR_RTS : std_logic; -- MCR: Request to send
signal iMCR_OUT1 : std_logic; -- MCR: OUT1
signal iMCR_OUT2 : std_logic; -- MCR: OUT2
signal iMCR_LOOP : std_logic; -- MCR: Loop
signal iMCR_AFE : std_logic; -- MCR: Auto flow control enable
-- LSR register signals
signal iLSR_DR : std_logic; -- LSR: Data ready
signal iLSR_OE : std_logic; -- LSR: Overrun error
signal iLSR_PE : std_logic; -- LSR: Parity error
signal iLSR_FE : std_logic; -- LSR: Framing error
signal iLSR_BI : std_logic; -- LSR: Break Interrupt
signal iLSR_THRE : std_logic; -- LSR: Transmitter holding register empty
signal iLSR_TEMT : std_logic; -- LSR: Transmitter empty
signal iLSR_FIFOERR : std_logic; -- LSR: Error in receiver FIFO
-- MSR register signals
signal iMSR_dCTS : std_logic; -- MSR: Delta CTS
signal iMSR_dDSR : std_logic; -- MSR: Delta DSR
signal iMSR_TERI : std_logic; -- MSR: Trailing edge ring indicator
signal iMSR_dDCD : std_logic; -- MSR: Delta DCD
signal iMSR_CTS : std_logic; -- MSR: CTS
signal iMSR_DSR : std_logic; -- MSR: DSR
signal iMSR_RI : std_logic; -- MSR: RI
signal iMSR_DCD : std_logic; -- MSR: DCD
-- UART MSR signals
signal iCTSNs : std_logic; -- Synchronized CTSN input
signal iDSRNs : std_logic; -- Synchronized DSRN input
signal iDCDNs : std_logic; -- Synchronized DCDN input
signal iRINs : std_logic; -- Synchronized RIN input
signal iCTSn : std_logic; -- Filtered CTSN input
signal iDSRn : std_logic; -- Filtered DSRN input
signal iDCDn : std_logic; -- Filtered DCDN input
signal iRIn : std_logic; -- Filtered RIN input
signal iCTSnRE : std_logic; -- CTSn rising edge
signal iCTSnFE : std_logic; -- CTSn falling edge
signal iDSRnRE : std_logic; -- DSRn rising edge
signal iDSRnFE : std_logic; -- DSRn falling edge
signal iDCDnRE : std_logic; -- DCDn rising edge
signal iDCDnFE : std_logic; -- DCDn falling edge
signal iRInRE : std_logic; -- RIn rising edge
signal iRInFE : std_logic; -- RIn falling edge
-- UART baudrate generation signals
signal iBaudgenDiv : std_logic_vector(15 downto 0); -- Baudrate divider
signal iBaudtick16x : std_logic; -- 16x Baudrate output from baudrate generator
signal iBaudtick2x : std_logic; -- 2x Baudrate for transmitter
signal iRCLK : std_logic; -- 16x Baudrate for receiver
-- UART FIFO signals
signal iTXFIFOClear : std_logic; -- Clear TX FIFO
signal iTXFIFOWrite : std_logic; -- Write to TX FIFO
signal iTXFIFORead : std_logic; -- Read from TX FIFO
signal iTXFIFOEmpty : std_logic; -- TX FIFO is empty
signal iTXFIFOFull : std_logic; -- TX FIFO is full
signal iTXFIFO16Full : std_logic; -- TX FIFO 16 byte mode is full
signal iTXFIFO64Full : std_logic; -- TX FIFO 64 byte mode is full
signal iTXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage
signal iTXFIFOQ : std_logic_vector(7 downto 0); -- TX FIFO output
signal iRXFIFOClear : std_logic; -- Clear RX FIFO
signal iRXFIFOWrite : std_logic; -- Write to RX FIFO
signal iRXFIFORead : std_logic; -- Read from RX FIFO
signal iRXFIFOEmpty : std_logic; -- RX FIFO is empty
signal iRXFIFOFull : std_logic; -- RX FIFO is full
signal iRXFIFO16Full : std_logic; -- RX FIFO 16 byte mode is full
signal iRXFIFO64Full : std_logic; -- RX FIFO 64 byte mode is full
signal iRXFIFOD : std_logic_vector(10 downto 0); -- RX FIFO input
signal iRXFIFOQ : std_logic_vector(10 downto 0); -- RX FIFO output
signal iRXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage
signal iRXFIFOTrigger : std_logic; -- FIFO trigger level reached
signal iRXFIFO16Trigger : std_logic; -- FIFO 16 byte mode trigger level reached
signal iRXFIFO64Trigger : std_logic; -- FIFO 64 byte mode trigger level reached
signal iRXFIFOPE : std_logic; -- Parity error from FIFO
signal iRXFIFOFE : std_logic; -- Frame error from FIFO
signal iRXFIFOBI : std_logic; -- Break interrupt from FIFO
-- UART transmitter signals
signal iSOUT : std_logic; -- Transmitter output
signal iTXStart : std_logic; -- Start transmitter
signal iTXClear : std_logic; -- Clear transmitter status
signal iTXFinished : std_logic; -- TX finished, character transmitted
signal iTXRunning : std_logic; -- TX in progress
-- UART receiver signals
signal iSINr : std_logic; -- Synchronized SIN input
signal iSIN : std_logic; -- Receiver input
signal iRXFinished : std_logic; -- RX finished, character received
signal iRXClear : std_logic; -- Clear receiver status
signal iRXData : std_logic_vector(7 downto 0); -- RX data
signal iRXPE : std_logic; -- RX parity error
signal iRXFE : std_logic; -- RX frame error
signal iRXBI : std_logic; -- RX break interrupt
-- UART control signals
signal iFERE : std_logic; -- Frame error detected
signal iPERE : std_logic; -- Parity error detected
signal iBIRE : std_logic; -- Break interrupt detected
signal iFECounter : integer range 0 to 64; -- FIFO error counter
signal iFEIncrement : std_logic; -- FIFO error counter increment
signal iFEDecrement : std_logic; -- FIFO error counter decrement
signal iRDAInterrupt : std_logic; -- Receiver data available interrupt (DA or FIFO trigger level)
signal iTimeoutCount : unsigned(5 downto 0); -- Character timeout counter (FIFO mode)
signal iCharTimeout : std_logic; -- Character timeout indication (FIFO mode)
signal iLSR_THRERE : std_logic; -- LSR THRE rising edge for interrupt generation
signal iTHRInterrupt : std_logic; -- Transmitter holding register empty interrupt
signal iTXEnable : std_logic; -- Transmitter enable signal
signal iRTS : std_logic; -- Internal RTS signal with/without automatic flow control
begin
-- Global device signals
iCSWR <= '1' when CS = '1' and WR = '1' else '0';
iCSRD <= '1' when CS = '1' and RD = '1' else '0';
UART_ED_WRITE: slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSWR, FE => iWriteFE);
UART_ED_READ: slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSRD, FE => iReadFE);
iWrite <= '1' when iWriteFE = '1' else '0';
iRead <= '1' when iReadFE = '1' else '0';
-- UART registers read/write signals
iRBRRead <= '1' when iRead = '1' and iA = "000" and iLCR_DLAB = '0' else '0';
iTHRWrite <= '1' when iWrite = '1' and iA = "000" and iLCR_DLAB = '0' else '0';
iDLLWrite <= '1' when iWrite = '1' and iA = "000" and iLCR_DLAB = '1' else '0';
iDLMWrite <= '1' when iWrite = '1' and iA = "001" and iLCR_DLAB = '1' else '0';
iIERWrite <= '1' when iWrite = '1' and iA = "001" and iLCR_DLAB = '0' else '0';
iIIRRead <= '1' when iRead = '1' and iA = "010" else '0';
iFCRWrite <= '1' when iWrite = '1' and iA = "010" else '0';
iLCRWrite <= '1' when iWrite = '1' and iA = "011" else '0';
iMCRWrite <= '1' when iWrite = '1' and iA = "100" else '0';
iLSRRead <= '1' when iRead = '1' and iA = "101" else '0';
iMSRRead <= '1' when iRead = '1' and iA = "110" else '0';
iSCRWrite <= '1' when iWrite = '1' and iA = "111" else '0';
-- Async. input synchronization
UART_IS_SIN: slib_input_sync port map (CLK, RST, SIN, iSINr);
UART_IS_CTS: slib_input_sync port map (CLK, RST, CTSN, iCTSNs);
UART_IS_DSR: slib_input_sync port map (CLK, RST, DSRN, iDSRNs);
UART_IS_DCD: slib_input_sync port map (CLK, RST, DCDN, iDCDNs);
UART_IS_RI: slib_input_sync port map (CLK, RST, RIN, iRINs);
-- Input filter for UART control signals
UART_IF_CTS: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iCTSNs, iCTSn);
UART_IF_DSR: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iDSRNs, iDSRn);
UART_IF_DCD: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iDCDNs, iDCDn);
UART_IF_RI: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iRINs, iRIn);
-- Sync. input synchronization
UART_SIS: process (CLK, RST)
begin
if (RST = '1') then
iA <= (others => '0');
iDIN <= (others => '0');
elsif (CLK'event and CLK = '1') then
iA <= A;
iDIN <= DIN;
end if;
end process;
-- Divisor latch register
UART_DLR: process (CLK, RST)
begin
if (RST = '1') then
iDLL <= (others => '0');
iDLM <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iDLLWrite = '1') then
iDLL <= iDIN;
end if;
if (iDLMWrite = '1') then
iDLM <= iDIN;
end if;
end if;
end process;
-- Interrupt enable register
UART_IER: process (CLK, RST)
begin
if (RST = '1') then
iIER(3 downto 0) <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iIERWrite = '1') then
iIER(3 downto 0) <= iDIN(3 downto 0);
end if;
end if;
end process;
iIER_ERBI <= iIER(0);
iIER_ETBEI <= iIER(1);
iIER_ELSI <= iIER(2);
iIER_EDSSI <= iIER(3);
iIER(7 downto 4) <= (others => '0');
-- Interrupt control and IIR
UART_IIC: uart_interrupt port map (CLK => CLK,
RST => RST,
IER => iIER(3 downto 0),
LSR => iLSR(4 downto 0),
THI => iTHRInterrupt,
RDA => iRDAInterrupt,
CTI => iCharTimeout,
AFE => iMCR_AFE,
MSR => iMSR(3 downto 0),
IIR => iIIR(3 downto 0),
INT => INT
);
-- THR empty interrupt
UART_IIC_THRE_ED: slib_edge_detect port map (CLK => CLK, RST => RST, D => iLSR_THRE, RE => iLSR_THRERE);
UART_IIC_THREI: process (CLK, RST)
begin
if (RST = '1') then
iTHRInterrupt <= '0';
elsif (CLK'event and CLK = '1') then
if (iLSR_THRERE = '1' or iFCR_TXFIFOReset = '1' or (iIERWrite = '1' and iDIN(1) = '1' and iLSR_THRE = '1')) then
iTHRInterrupt <= '1'; -- Set on THRE, TX FIFO reset (FIFO enable) or ETBEI enable
elsif ((iIIRRead = '1' and iIIR(3 downto 1) = "001") or iTHRWrite = '1') then
iTHRInterrupt <= '0'; -- Clear on IIR read (if source of interrupt) or THR write
end if;
end if;
end process;
iRDAInterrupt <= '1' when (iFCR_FIFOEnable = '0' and iLSR_DR = '1') or
(iFCR_FIFOEnable = '1' and iRXFIFOTrigger = '1') else '0';
iIIR_PI <= iIIR(0);
iIIR_ID0 <= iIIR(1);
iIIR_ID1 <= iIIR(2);
iIIR_ID2 <= iIIR(3);
iIIR_FIFO64 <= iIIR(5);
iIIR(4) <= '0';
iIIR(5) <= iFCR_FIFO64E when iFCR_FIFOEnable = '1' else '0';
iIIR(6) <= iFCR_FIFOEnable;
iIIR(7) <= iFCR_FIFOEnable;
-- Character timeout indication
UART_CTI: process (CLK, RST)
begin
if (RST = '1') then
iTimeoutCount <= (others => '0');
iCharTimeout <= '0';
elsif (CLK'event and CLK = '1') then
if (iRXFIFOEmpty = '1' or iRBRRead = '1' or iRXFIFOWrite = '1') then
iTimeoutCount <= (others => '0');
elsif (iRXFIFOEmpty = '0' and iBaudtick2x = '1' and iTimeoutCount(5) = '0') then
iTimeoutCount <= iTimeoutCount + 1;
end if;
-- Timeout indication
if (iFCR_FIFOEnable = '1') then
if (iRBRRead = '1') then
iCharTimeout <= '0';
elsif (iTimeoutCount(5) = '1') then
iCharTimeout <= '1';
end if;
else
iCharTimeout <= '0';
end if;
end if;
end process;
-- FIFO control register
UART_FCR: process (CLK, RST)
begin
if (RST = '1') then
iFCR_FIFOEnable <= '0';
iFCR_RXFIFOReset <= '0';
iFCR_TXFIFOReset <= '0';
iFCR_DMAMode <= '0';
iFCR_FIFO64E <= '0';
iFCR_RXTrigger <= (others => '0');
elsif (CLK'event and CLK = '1') then
-- FIFO reset pulse only
iFCR_RXFIFOReset <= '0';
iFCR_TXFIFOReset <= '0';
if (iFCRWrite = '1') then
iFCR_FIFOEnable <= iDIN(0);
iFCR_DMAMode <= iDIN(3);
iFCR_RXTrigger <= iDIN(7 downto 6);
if (iLCR_DLAB = '1') then
iFCR_FIFO64E <= iDIN(5);
end if;
-- RX FIFO reset control, reset on FIFO enable/disable
if (iDIN(1) = '1' or (iFCR_FIFOEnable = '0' and iDIN(0) = '1') or (iFCR_FIFOEnable = '1' and iDIN(0) = '0')) then
iFCR_RXFIFOReset <= '1';
end if;
-- TX FIFO reset control, reset on FIFO enable/disable
if (iDIN(2) = '1' or (iFCR_FIFOEnable = '0' and iDIN(0) = '1') or (iFCR_FIFOEnable = '1' and iDIN(0) = '0')) then
iFCR_TXFIFOReset <= '1';
end if;
end if;
end if;
end process;
iFCR(0) <= iFCR_FIFOEnable;
iFCR(1) <= iFCR_RXFIFOReset;
iFCR(2) <= iFCR_TXFIFOReset;
iFCR(3) <= iFCR_DMAMode;
iFCR(4) <= '0';
iFCR(5) <= iFCR_FIFO64E;
iFCR(7 downto 6) <= iFCR_RXTrigger;
-- Line control register
UART_LCR: process (CLK, RST)
begin
if (RST = '1') then
iLCR <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iLCRWrite = '1') then
iLCR <= iDIN;
end if;
end if;
end process;
iLCR_WLS <= iLCR(1 downto 0);
iLCR_STB <= iLCR(2);
iLCR_PEN <= iLCR(3);
iLCR_EPS <= iLCR(4);
iLCR_SP <= iLCR(5);
iLCR_BC <= iLCR(6);
iLCR_DLAB <= iLCR(7);
-- Modem control register
UART_MCR: process (CLK, RST)
begin
if (RST = '1') then
iMCR(5 downto 0) <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iMCRWrite = '1') then
iMCR(5 downto 0) <= iDIN(5 downto 0);
end if;
end if;
end process;
iMCR_DTR <= iMCR(0);
iMCR_RTS <= iMCR(1);
iMCR_OUT1 <= iMCR(2);
iMCR_OUT2 <= iMCR(3);
iMCR_LOOP <= iMCR(4);
iMCR_AFE <= iMCR(5);
iMCR(6) <= '0';
iMCR(7) <= '0';
-- Line status register
UART_LSR: process (CLK, RST)
begin
if (RST = '1') then
iLSR_OE <= '0';
iLSR_PE <= '0';
iLSR_FE <= '0';
iLSR_BI <= '0';
iFECounter <= 0;
elsif (CLK'event and CLK = '1') then
-- Overrun error
if ((iFCR_FIFOEnable = '0' and iLSR_DR = '1' and iRXFinished = '1') or
(iFCR_FIFOEnable = '1' and iRXFIFOFull = '1' and iRXFinished = '1')) then
iLSR_OE <= '1';
elsif (iLSRRead = '1') then
iLSR_OE <= '0';
end if;
-- Parity error
if (iPERE = '1') then
iLSR_PE <= '1';
elsif (iLSRRead = '1') then
iLSR_PE <= '0';
end if;
-- Frame error
if (iFERE = '1') then
iLSR_FE <= '1';
elsif (iLSRRead = '1') then
iLSR_FE <= '0';
end if;
-- Break interrupt
if (iBIRE = '1') then
iLSR_BI <= '1';
elsif (iLSRRead = '1') then
iLSR_BI <= '0';
end if;
-- FIFO error
-- Datasheet: Cleared by LSR read when no subsequent errors in FIFO
-- Observed: Cleared when no subsequent errors in FIFO
if (iFECounter /= 0) then
iLSR_FIFOERR <= '1';
--elsif (iLSRRead = '1' and iFECounter = 0 and not (iRXFIFOEmpty = '0' and iRXFIFOQ(10 downto 8) /= "000")) then
elsif (iRXFIFOEmpty = '1' or iRXFIFOQ(10 downto 8) = "000") then
iLSR_FIFOERR <= '0';
end if;
-- FIFO error counter
if (iRXFIFOClear = '1') then
iFECounter <= 0;
else
if (iFEIncrement = '1' and iFEDecrement = '0') then
iFECounter <= iFECounter + 1;
elsif (iFEIncrement = '0' and iFEDecrement = '1') then
iFECounter <= iFECounter - 1;
end if;
end if;
end if;
end process;
iRXFIFOPE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(8) = '1' else '0';
iRXFIFOFE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(9) = '1' else '0';
iRXFIFOBI <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(10) = '1' else '0';
UART_PEDET: slib_edge_detect port map (CLK, RST, iRXFIFOPE, iPERE);
UART_FEDET: slib_edge_detect port map (CLK, RST, iRXFIFOFE, iFERE);
UART_BIDET: slib_edge_detect port map (CLK, RST, iRXFIFOBI, iBIRE);
iFEIncrement <= '1' when iRXFIFOWrite = '1' and iRXFIFOD(10 downto 8) /= "000" else '0';
iFEDecrement <= '1' when iFECounter /= 0 and iRXFIFOEmpty = '0' and (iPERE = '1' or iFERE = '1' or iBIRE = '1') else '0';
iLSR(0) <= iLSR_DR;
iLSR(1) <= iLSR_OE;
iLSR(2) <= iLSR_PE;
iLSR(3) <= iLSR_FE;
iLSR(4) <= iLSR_BI;
iLSR(5) <= iLSR_THRE;
iLSR(6) <= iLSR_TEMT;
iLSR(7) <= '1' when iFCR_FIFOEnable = '1' and iLSR_FIFOERR = '1' else '0';
iLSR_DR <= '1' when iRXFIFOEmpty = '0' or iRXFIFOWrite = '1' else '0';
iLSR_THRE <= '1' when iTXFIFOEmpty = '1' else '0';
iLSR_TEMT <= '1' when iTXRunning = '0' and iLSR_THRE = '1' else '0';
-- Modem status register
iMSR_CTS <= '1' when (iMCR_LOOP = '1' and iRTS = '1') or (iMCR_LOOP = '0' and iCTSn = '0') else '0';
iMSR_DSR <= '1' when (iMCR_LOOP = '1' and iMCR_DTR = '1') or (iMCR_LOOP = '0' and iDSRn = '0') else '0';
iMSR_RI <= '1' when (iMCR_LOOP = '1' and iMCR_OUT1 = '1') or (iMCR_LOOP = '0' and iRIn = '0') else '0';
iMSR_DCD <= '1' when (iMCR_LOOP = '1' and iMCR_OUT2 = '1') or (iMCR_LOOP = '0' and iDCDn = '0') else '0';
-- Edge detection for CTS, DSR, DCD and RI
UART_ED_CTS: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_CTS, RE => iCTSnRE, FE => iCTSnFE);
UART_ED_DSR: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_DSR, RE => iDSRnRE, FE => iDSRnFE);
UART_ED_RI: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_RI, RE => iRInRE, FE => iRInFE);
UART_ED_DCD: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_DCD, RE => iDCDnRE, FE => iDCDnFE);
UART_MSR: process (CLK, RST)
begin
if (RST = '1') then
iMSR_dCTS <= '0';
iMSR_dDSR <= '0';
iMSR_TERI <= '0';
iMSR_dDCD <= '0';
elsif (CLK'event and CLK = '1') then
-- Delta CTS
if (iCTSnRE = '1' or iCTSnFE = '1') then
iMSR_dCTS <= '1';
elsif (iMSRRead = '1') then
iMSR_dCTS <= '0';
end if;
-- Delta DSR
if (iDSRnRE = '1' or iDSRnFE = '1') then
iMSR_dDSR <= '1';
elsif (iMSRRead = '1') then
iMSR_dDSR <= '0';
end if;
-- Trailing edge RI
if (iRInFE = '1') then
iMSR_TERI <= '1';
elsif (iMSRRead = '1') then
iMSR_TERI <= '0';
end if;
-- Delta DCD
if (iDCDnRE = '1' or iDCDnFE = '1') then
iMSR_dDCD <= '1';
elsif (iMSRRead = '1') then
iMSR_dDCD <= '0';
end if;
end if;
end process;
iMSR(0) <= iMSR_dCTS;
iMSR(1) <= iMSR_dDSR;
iMSR(2) <= iMSR_TERI;
iMSR(3) <= iMSR_dDCD;
iMSR(4) <= iMSR_CTS;
iMSR(5) <= iMSR_DSR;
iMSR(6) <= iMSR_RI;
iMSR(7) <= iMSR_DCD;
-- Scratch register
UART_SCR: process (CLK, RST)
begin
if (RST = '1') then
iSCR <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iSCRWrite = '1') then
iSCR <= iDIN;
end if;
end if;
end process;
-- Baudrate generator
iBaudgenDiv <= iDLM & iDLL;
UART_BG16: uart_baudgen port map (CLK => CLK,
RST => RST,
CE => BAUDCE,
CLEAR => '0',
DIVIDER => iBaudgenDiv,
BAUDTICK => iBaudtick16x
);
UART_BG2: slib_clock_div generic map (RATIO => 8)
port map (CLK => CLK,
RST => RST,
CE => iBaudtick16x,
Q => iBaudtick2x
);
UART_RCLK: slib_edge_detect port map (CLK => CLK,
RST => RST,
D => RCLK,
RE => iRCLK
);
-- Transmitter FIFO
UART_TXFF: slib_fifo generic map (WIDTH => 8, SIZE_E => 6)
port map (CLK => CLK,
RST => RST,
CLEAR => iTXFIFOClear,
WRITE => iTXFIFOWrite,
READ => iTXFIFORead,
D => iDIN,
Q => iTXFIFOQ,
EMPTY => iTXFIFOEmpty,
FULL => iTXFIFO64Full,
USAGE => iTXFIFOUsage
);
-- Transmitter FIFO inputs
iTXFIFO16Full <= iTXFIFOUsage(4);
iTXFIFOFull <= iTXFIFO16Full when iFCR_FIFO64E = '0' else iTXFIFO64Full;
iTXFIFOWrite <= '1' when ((iFCR_FIFOEnable = '0' and iTXFIFOEmpty = '1') or (iFCR_FIFOEnable = '1' and iTXFIFOFull = '0')) and iTHRWrite = '1' else '0';
iTXFIFOClear <= '1' when iFCR_TXFIFOReset = '1' else '0';
-- Receiver FIFO
UART_RXFF: slib_fifo generic map (WIDTH => 11, SIZE_E => 6)
port map (CLK => CLK,
RST => RST,
CLEAR => iRXFIFOClear,
WRITE => iRXFIFOWrite,
READ => iRXFIFORead,
D => iRXFIFOD,
Q => iRXFIFOQ,
EMPTY => iRXFIFOEmpty,
FULL => iRXFIFO64Full,
USAGE => iRXFIFOUsage
);
-- Receiver FIFO inputs
iRXFIFORead <= '1' when iRBRRead = '1' else '0';
iRXFIFO16Full <= iRXFIFOUsage(4);
iRXFIFOFull <= iRXFIFO16Full when iFCR_FIFO64E = '0' else iRXFIFO64Full;
-- Receiver FIFO outputs
iRBR <= iRXFIFOQ(7 downto 0);
-- FIFO trigger level: 1, 4, 8, 14
iRXFIFO16Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or
(iFCR_RXTrigger = "01" and (iRXFIFOUsage(2) = '1' or iRXFIFOUsage(3) = '1')) or
(iFCR_RXTrigger = "10" and iRXFIFOUsage(3) = '1') or
(iFCR_RXTrigger = "11" and iRXFIFOUsage(3) = '1' and iRXFIFOUsage(2) = '1' and iRXFIFOUsage(1) = '1') or
iRXFIFO16Full = '1' else '0';
-- FIFO 64 trigger level: 1, 16, 32, 56
iRXFIFO64Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or
(iFCR_RXTrigger = "01" and (iRXFIFOUsage(4) = '1' or iRXFIFOUsage(5) = '1')) or
(iFCR_RXTrigger = "10" and iRXFIFOUsage(5) = '1') or
(iFCR_RXTrigger = "11" and iRXFIFOUsage(5) = '1' and iRXFIFOUsage(4) = '1' and iRXFIFOUsage(3) = '1') or
iRXFIFO64Full = '1' else '0';
iRXFIFOTrigger <= iRXFIFO16Trigger when iFCR_FIFO64E = '0' else iRXFIFO64Trigger;
-- Transmitter
UART_TX: uart_transmitter port map (CLK => CLK,
RST => RST,
TXCLK => iBaudtick2x,
TXSTART => iTXStart,
CLEAR => iTXClear,
WLS => iLCR_WLS,
STB => iLCR_STB,
PEN => iLCR_PEN,
EPS => iLCR_EPS,
SP => iLCR_SP,
BC => iLCR_BC,
DIN => iTSR,
TXFINISHED => iTXFinished,
SOUT => iSOUT
);
iTXClear <= '0';
-- Receiver
UART_RX: uart_receiver port map (CLK => CLK,
RST => RST,
RXCLK => iRCLK,
RXCLEAR => iRXClear,
WLS => iLCR_WLS,
STB => iLCR_STB,
PEN => iLCR_PEN,
EPS => iLCR_EPS,
SP => iLCR_SP,
SIN => iSIN,
PE => iRXPE,
FE => iRXFE,
BI => iRXBI,
DOUT => iRXData,
RXFINISHED => iRXFinished
);
iRXClear <= '0';
iSIN <= iSINr when iMCR_LOOP = '0' else iSOUT;
-- Transmitter enable signal
-- TODO: Use iCTSNs instead of iMSR_CTS? Input filter increases delay for Auto-CTS recognition.
iTXEnable <= '1' when iTXFIFOEmpty = '0' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iMSR_CTS = '1')) else '0';
-- Transmitter process
UART_TXPROC: process (CLK, RST)
type state_type is (IDLE, TXSTART, TXRUN, TXEND);
variable State : state_type;
begin
if (RST = '1') then
State := IDLE;
iTSR <= (others => '0');
iTXStart <= '0';
iTXFIFORead <= '0';
iTXRunning <= '0';
elsif (CLK'event and CLK = '1') then
-- Defaults
iTXStart <= '0';
iTXFIFORead <= '0';
iTXRunning <= '0';
case State is
when IDLE => if (iTXEnable = '1') then
iTXStart <= '1'; -- Start transmitter
State := TXSTART;
else
State := IDLE;
end if;
when TXSTART => iTSR <= iTXFIFOQ;
iTXStart <= '1'; -- Start transmitter
iTXFIFORead <= '1'; -- Increment TX FIFO read counter
State := TXRUN;
when TXRUN => if (iTXFinished = '1') then -- TX finished
State := TXEND;
else
State := TXRUN;
end if;
iTXRunning <= '1';
iTXStart <= '1';
when TXEND => State := IDLE;
when others => State := IDLE;
end case;
end if;
end process;
-- Receiver process
UART_RXPROC: process (CLK, RST)
type state_type is (IDLE, RXSAVE);
variable State : state_type;
begin
if (RST = '1') then
State := IDLE;
iRXFIFOWrite <= '0';
iRXFIFOClear <= '0';
iRXFIFOD <= (others => '0');
elsif (CLK'event and CLK = '1') then
-- Defaults
iRXFIFOWrite <= '0';
iRXFIFOClear <= iFCR_RXFIFOReset;
case State is
when IDLE => if (iRXFinished = '1') then -- Receive finished
iRXFIFOD <= iRXBI & iRXFE & iRXPE & iRXData;
if (iFCR_FIFOEnable = '0') then
iRXFIFOClear <= '1'; -- Non-FIFO mode
end if;
State := RXSAVE;
else
State := IDLE;
end if;
when RXSAVE => if (iFCR_FIFOEnable = '0') then
iRXFIFOWrite <= '1'; -- Non-FIFO mode: Overwrite
elsif (iRXFIFOFull = '0') then
iRXFIFOWrite <= '1'; -- FIFO mode
end if;
State := IDLE;
when others => State := IDLE;
end case;
end if;
end process;
-- Automatic flow control
UART_AFC: process (CLK, RST)
begin
if (RST = '1') then
iRTS <= '0';
elsif (CLK'event and CLK = '1') then
if (iMCR_RTS = '0' or (iMCR_AFE = '1' and iRXFIFOTrigger = '1')) then
-- Deassert when MCR_RTS is not set or AFC is enabled and the RX FIFO trigger level is reached
iRTS <= '0';
elsif (iMCR_RTS = '1' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iRXFIFOEmpty = '1'))) then
-- Assert when MCR_RTS is set and AFC is disabled or when AFC is enabled and the RX FIFO is empty
iRTS <= '1';
end if;
end if;
end process;
-- Output registers
UART_OUTREGS: process (CLK, RST)
begin
if (RST = '1') then
DDIS <= '0';
BAUDOUTN <= '0';
OUT1N <= '0';
OUT2N <= '0';
RTSN <= '0';
DTRN <= '0';
SOUT <= '0';
elsif (CLK'event and CLK = '1') then
-- Default values
DDIS <= '0';
BAUDOUTN <= '0';
OUT1N <= '0';
OUT2N <= '0';
RTSN <= '0';
DTRN <= '0';
SOUT <= '0';
-- DDIS
if (CS = '0' or RD = '0') then
DDIS <= '1';
end if;
-- BAUDOUTN
if (iBaudtick16x = '0') then
BAUDOUTN <= '1';
end if;
-- OUT1N
if (iMCR_LOOP = '1' or iMCR_OUT1 = '0') then
OUT1N <= '1';
end if;
-- OUT2N
if (iMCR_LOOP = '1' or iMCR_OUT2 = '0') then
OUT2N <= '1';
end if;
-- RTS
if (iMCR_LOOP = '1' or iRTS = '0') then
RTSN <= '1';
end if;
-- DTR
if (iMCR_LOOP = '1' or iMCR_DTR = '0') then
DTRN <= '1';
end if;
-- SOUT
if (iMCR_LOOP = '1' or iSOUT = '1') then
SOUT <= '1';
end if;
end if;
end process;
-- UART data output
UART_DOUT: process (A, iLCR_DLAB, iRBR, iDLL, iDLM, iIER, iIIR, iLCR, iMCR, iLSR, iMSR, iSCR)
begin
case A is
when "000" => if (iLCR_DLAB = '0') then
DOUT <= iRBR;
else
DOUT <= iDLL;
end if;
when "001" => if (iLCR_DLAB = '0') then
DOUT <= iIER;
else
DOUT <= iDLM;
end if;
when "010" => DOUT <= iIIR;
when "011" => DOUT <= iLCR;
when "100" => DOUT <= iMCR;
when "101" => DOUT <= iLSR;
when "110" => DOUT <= iMSR;
when "111" => DOUT <= iSCR;
when others => DOUT <= iRBR;
end case;
end process;
end rtl;
| gpl-2.0 |
nsauzede/cpu86 | papilio1_0/coregen/blk_mem_40K.vhd | 4 | 5211 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_40K.vhd when simulating
-- the core, blk_mem_40K. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_40K IS
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(15 downto 0);
dina: IN std_logic_VECTOR(7 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
END blk_mem_40K;
ARCHITECTURE blk_mem_40K_a OF blk_mem_40K IS
-- synthesis translate_off
component wrapped_blk_mem_40K
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(15 downto 0);
dina: IN std_logic_VECTOR(7 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
-- Configuration specification
for all : wrapped_blk_mem_40K use entity XilinxCoreLib.blk_mem_gen_v3_2(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 8,
c_initb_val => "0",
c_family => "spartan3",
c_read_width_a => 8,
c_disable_warn_bhv_coll => 1,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "blk_mem_40K.mif",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 1,
c_xdevicefamily => "spartan3e",
c_write_depth_b => 40960,
c_write_depth_a => 40960,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 16,
c_addrb_width => 16,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 1,
c_write_width_b => 8,
c_write_width_a => 8,
c_read_depth_b => 40960,
c_read_depth_a => 40960,
c_byte_size => 9,
c_sim_collision_check => "NONE",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_40K
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- synthesis translate_on
END blk_mem_40K_a;
| gpl-2.0 |
nsauzede/cpu86 | papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/data_gen.vhd | 26 | 5164 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
| gpl-2.0 |
nsauzede/cpu86 | papilio2/ipcore_dir/blk_mem_40K/simulation/data_gen.vhd | 26 | 5164 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
| gpl-2.0 |
nsauzede/cpu86 | papilio2/ipcore_dir/blk_mem_40K/simulation/blk_mem_40K_synth.vhd | 2 | 8184 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_40K_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_40K_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_40K_synth_ARCH OF blk_mem_40K_synth IS
COMPONENT blk_mem_40K_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_40K_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| gpl-2.0 |
nsauzede/cpu86 | papilio2_lcd/multiplier_rtl.vhd | 3 | 4121 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY multiplier IS
GENERIC(
WIDTH : integer := 16
);
PORT(
multiplicant : IN std_logic_vector (WIDTH-1 DOWNTO 0);
multiplier : IN std_logic_vector (WIDTH-1 DOWNTO 0);
product : OUT std_logic_vector (WIDTH+WIDTH-1 DOWNTO 0); -- result
twocomp : IN std_logic
);
END multiplier ;
architecture rtl of multiplier is
function rectify (r : in std_logic_vector (WIDTH-1 downto 0); -- Rectifier for signed multiplication
twoc : in std_logic) -- Signed/Unsigned
return std_logic_vector is
variable rec_v : std_logic_vector (WIDTH-1 downto 0);
begin
if ((r(WIDTH-1) and twoc)='1') then
rec_v := not(r);
else
rec_v := r;
end if;
return (rec_v + (r(WIDTH-1) and twoc));
end;
signal multiplicant_s : std_logic_vector (WIDTH-1 downto 0);
signal multiplier_s : std_logic_vector (WIDTH-1 downto 0);
signal product_s : std_logic_vector (WIDTH+WIDTH-1 downto 0); -- Result
signal sign_s : std_logic;
begin
multiplicant_s <= rectify(multiplicant,twocomp);
multiplier_s <= rectify(multiplier,twocomp);
sign_s <= multiplicant(WIDTH-1) xor multiplier(WIDTH-1); -- sign product
product_s <= multiplicant_s * multiplier_s;
product <= ((not(product_s)) + '1') when (sign_s and twocomp)='1' else product_s;
end rtl;
| gpl-2.0 |
nsauzede/cpu86 | cpu86_rtl/multiplier_rtl.vhd | 3 | 4121 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY multiplier IS
GENERIC(
WIDTH : integer := 16
);
PORT(
multiplicant : IN std_logic_vector (WIDTH-1 DOWNTO 0);
multiplier : IN std_logic_vector (WIDTH-1 DOWNTO 0);
product : OUT std_logic_vector (WIDTH+WIDTH-1 DOWNTO 0); -- result
twocomp : IN std_logic
);
END multiplier ;
architecture rtl of multiplier is
function rectify (r : in std_logic_vector (WIDTH-1 downto 0); -- Rectifier for signed multiplication
twoc : in std_logic) -- Signed/Unsigned
return std_logic_vector is
variable rec_v : std_logic_vector (WIDTH-1 downto 0);
begin
if ((r(WIDTH-1) and twoc)='1') then
rec_v := not(r);
else
rec_v := r;
end if;
return (rec_v + (r(WIDTH-1) and twoc));
end;
signal multiplicant_s : std_logic_vector (WIDTH-1 downto 0);
signal multiplier_s : std_logic_vector (WIDTH-1 downto 0);
signal product_s : std_logic_vector (WIDTH+WIDTH-1 downto 0); -- Result
signal sign_s : std_logic;
begin
multiplicant_s <= rectify(multiplicant,twocomp);
multiplier_s <= rectify(multiplier,twocomp);
sign_s <= multiplicant(WIDTH-1) xor multiplier(WIDTH-1); -- sign product
product_s <= multiplicant_s * multiplier_s;
product <= ((not(product_s)) + '1') when (sign_s and twocomp)='1' else product_s;
end rtl;
| gpl-2.0 |
nsauzede/cpu86 | p2_lcd_spi/vga_sync.vhd | 2 | 2106 | --
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
-- Based on code from P. P. Chu, "FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version", 2008
-- Chapters 12-13
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity vga_sync is
port(
clock: in std_logic;
reset: in std_logic;
hsync, vsync: out std_logic;
video_on: out std_logic;
pixel_tick: out std_logic;
pixel_x, pixel_y: out std_logic_vector(9 downto 0)
);
end vga_sync;
architecture arch of vga_sync is
signal h_sync_reg, v_sync_reg, video_on_reg: std_logic := '0';
signal v_count_reg: std_logic_vector(9 downto 0);
signal h_count_reg: std_logic_vector(9 downto 0);
-- VGA 640x480
constant thp : integer := 6; -- hsync 156
constant htotal : integer := 850; -- screen size, with back porch 900
constant tvp : integer := 34; -- vsync 1
constant vtotal : integer := 560; -- screen size, with back porch 560
begin
-- registers
process(clock)
begin
if rising_edge(clock) then
video_on_reg <= '1';
if h_count_reg < (thp) then
h_sync_reg <= '0';
video_on_reg <= '0';
else
h_sync_reg <= '1';
end if;
if v_count_reg < tvp then
v_sync_reg <= '0';
video_on_reg <= '0';
else
v_sync_reg <= '1';
end if;
if h_count_reg = htotal then
h_count_reg <= (others => '0');
if v_count_reg = vtotal then
v_count_reg <= (others => '0');
else
v_count_reg <= v_count_reg + 1;
end if;
else
h_count_reg <= h_count_reg + 1;
end if;
end if;
end process;
-- video on/off
-- video_on <= h_sync_reg and v_sync_reg;
video_on <= video_on_reg;
-- output signals
hsync <= h_sync_reg;
vsync <= v_sync_reg;
pixel_x <= std_logic_vector(h_count_reg)-thp-104;
pixel_y <= std_logic_vector(v_count_reg)-tvp;
-- pixel_tick <= p_tick;
end arch;
| gpl-2.0 |
nsauzede/cpu86 | papilio2_lcd/slib_fifo.vhd | 3 | 5060 | --
-- FIFO
--
-- Author: Sebastian Witt
-- Date: 29.01.2008
-- Version: 1.3
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_fifo is
generic (
WIDTH : integer := 8; -- FIFO width
SIZE_E : integer := 6 -- FIFO size (2^SIZE_E)
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear FIFO
WRITE : in std_logic; -- Write to FIFO
READ : in std_logic; -- Read from FIFO
D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input
Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output
EMPTY : out std_logic; -- FIFO is empty
FULL : out std_logic; -- FIFO is full
USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage
);
end slib_fifo;
architecture rtl of slib_fifo is
-- Signals
signal iEMPTY : std_logic; -- Internal EMPTY
signal iFULL : std_logic; -- Internal FULL
signal iWRAddr : unsigned(SIZE_E downto 0); -- FIFO write address
signal iRDAddr : unsigned(SIZE_E downto 0); -- FIFO read address
signal iUSAGE : unsigned(SIZE_E-1 downto 0); -- FIFO usage
-- FIFO memory
type FIFO_Mem_Type is array (2**SIZE_E-1 downto 0) of std_logic_vector(WIDTH-1 downto 0);
signal iFIFOMem : FIFO_Mem_Type := (others => (others => '0'));
begin
-- Full signal (biggest difference of read and write address)
iFULL <= '1' when (iRDAddr(SIZE_E-1 downto 0) = iWRAddr(SIZE_E-1 downto 0)) and
(iRDAddr(SIZE_E) /= iWRAddr(SIZE_E)) else '0';
-- Write/read address counter and empty signal
FF_ADDR: process (RST, CLK)
begin
if (RST = '1') then
iWRAddr <= (others => '0');
iRDAddr <= (others => '0');
iEMPTY <= '1';
elsif (CLK'event and CLK='1') then
if (WRITE = '1' and iFULL = '0') then -- Write to FIFO
iWRAddr <= iWRAddr + 1;
end if;
if (READ = '1' and iEMPTY = '0') then -- Read from FIFO
iRDAddr <= iRDAddr + 1;
end if;
if (CLEAR = '1') then -- Reset FIFO
iWRAddr <= (others => '0');
iRDAddr <= (others => '0');
end if;
if (iRDAddr = iWRAddr) then -- Empty signal (read address same as write address)
iEMPTY <= '1';
else
iEMPTY <= '0';
end if;
end if;
end process;
-- FIFO memory process
FF_MEM: process (RST, CLK)
begin
if (RST = '1') then
--iFIFOMem(2**SIZE_E-1 downto 0) <= (others => (others => '0'));
elsif (CLK'event and CLK = '1') then
if (WRITE = '1' and iFULL = '0') then
iFIFOMem(to_integer(iWRAddr(SIZE_E-1 downto 0))) <= D;
end if;
Q <= iFIFOMem(to_integer(iRDAddr(SIZE_E-1 downto 0)));
end if;
end process;
-- Usage counter
FF_USAGE: process (RST, CLK)
begin
if (RST = '1') then
iUSAGE <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (CLEAR = '1') then
iUSAGE <= (others => '0');
else
if (READ = '0' and WRITE = '1' and iFULL = '0') then
iUSAGE <= iUSAGE + 1;
end if;
if (WRITE = '0' and READ = '1' and iEMPTY = '0') then
iUSAGE <= iUSAGE - 1;
end if;
end if;
end if;
end process;
-- Output signals
EMPTY <= iEMPTY;
FULL <= iFULL;
USAGE <= std_logic_vector(iUSAGE);
end rtl;
| gpl-2.0 |
nsauzede/cpu86 | p2_lcd_spi/segregfile_rtl.vhd | 3 | 5118 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY segregfile IS
PORT(
selsreg : IN std_logic_vector (1 DOWNTO 0);
sibus : IN std_logic_vector (15 DOWNTO 0);
wrs : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
sdbus : OUT std_logic_vector (15 DOWNTO 0);
dimux : IN std_logic_vector (2 DOWNTO 0);
es_s : OUT std_logic_vector (15 DOWNTO 0);
cs_s : OUT std_logic_vector (15 DOWNTO 0);
ss_s : OUT std_logic_vector (15 DOWNTO 0);
ds_s : OUT std_logic_vector (15 DOWNTO 0)
);
END segregfile ;
architecture rtl of segregfile is
signal esreg_s : std_logic_vector(15 downto 0);
signal csreg_s : std_logic_vector(15 downto 0);
signal ssreg_s : std_logic_vector(15 downto 0);
signal dsreg_s : std_logic_vector(15 downto 0);
signal sdbus_s : std_logic_vector (15 downto 0); -- internal sdbus
signal dimux_s : std_logic_vector (2 downto 0); -- replaced dimux
begin
----------------------------------------------------------------------------
-- 4 registers of 16 bits each
----------------------------------------------------------------------------
process (clk,reset)
begin
if reset='1' then
esreg_s <= RESET_ES_C;
csreg_s <= RESET_CS_C; -- Only CS set after reset
ssreg_s <= RESET_SS_C;
dsreg_s <= RESET_DS_C;
elsif rising_edge(clk) then
if (wrs='1') then
case selsreg is
when "00" => esreg_s <= sibus;
when "01" => csreg_s <= sibus;
when "10" => ssreg_s <= sibus;
when others => dsreg_s <= sibus;
end case;
end if;
end if;
end process;
dimux_s <= dimux;
process (dimux_s,esreg_s,csreg_s,ssreg_s,dsreg_s)
begin
case dimux_s is -- Only 2 bits required
when "100" => sdbus_s <= esreg_s;
when "101" => sdbus_s <= csreg_s;
when "110" => sdbus_s <= ssreg_s;
when others => sdbus_s <= dsreg_s;
end case;
end process;
sdbus <= sdbus_s; -- Connect to entity
es_s <= esreg_s;
cs_s <= csreg_s;
ss_s <= ssreg_s;
ds_s <= dsreg_s;
end rtl;
| gpl-2.0 |
davewebb8211/ghdl | libraries/vital95/vital_timing.vhdl | 6 | 46973 | -------------------------------------------------------------------------------
-- Title : Standard VITAL TIMING Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, attributes, constants,
-- : functions and procedures for use in developing ASIC models.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0
-- #204 - Output mapping prior to glitch detection
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE VITAL_Timing IS
TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0X, trx1, tr1x, trx0, trxz, trzx);
SUBTYPE VitalDelayType IS TIME;
TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10)
OF TIME;
TYPE VitalDelayType01Z IS ARRAY (VitalTransitionType RANGE tr01 to trz0)
OF TIME;
TYPE VitalDelayType01ZX IS ARRAY (VitalTransitionType RANGE tr01 to trzx)
OF TIME;
TYPE VitalDelayArrayType IS ARRAY (NATURAL RANGE <>) OF VitalDelayType;
TYPE VitalDelayArrayType01 IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01;
TYPE VitalDelayArrayType01Z IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01Z;
TYPE VitalDelayArrayType01ZX IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01ZX;
-- ----------------------------------------------------------------------
-- **********************************************************************
-- ----------------------------------------------------------------------
CONSTANT VitalZeroDelay : VitalDelayType := 0 ns;
CONSTANT VitalZeroDelay01 : VitalDelayType01 := ( 0 ns, 0 ns );
CONSTANT VitalZeroDelay01Z : VitalDelayType01Z := ( OTHERS => 0 ns );
CONSTANT VitalZeroDelay01ZX : VitalDelayType01ZX := ( OTHERS => 0 ns );
---------------------------------------------------------------------------
-- examples of usage:
---------------------------------------------------------------------------
-- tpd_CLK_Q : VitalDelayType := 5 ns;
-- tpd_CLK_Q : VitalDelayType01 := (tr01 => 2 ns, tr10 => 3 ns);
-- tpd_CLK_Q : VitalDelayType01Z := ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns );
-- tpd_CLK_Q : VitalDelayArrayType(0 to 1)
-- := (0 => 5 ns, 1 => 6 ns);
-- tpd_CLK_Q : VitalDelayArrayType01(0 to 1)
-- := (0 => (tr01 => 2 ns, tr10 => 3 ns),
-- 1 => (tr01 => 2 ns, tr10 => 3 ns));
-- tpd_CLK_Q : VitalDelayArrayType01Z(0 to 1)
-- := (0 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ),
-- 1 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ));
---------------------------------------------------------------------------
-- TRUE if the model is LEVEL0 | LEVEL1 compliant
ATTRIBUTE VITAL_Level0 : BOOLEAN;
ATTRIBUTE VITAL_Level1 : BOOLEAN;
SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0);
SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0);
SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0);
-- Types for strength mapping of outputs
TYPE VitalOutputMapType IS ARRAY ( std_ulogic ) OF std_ulogic;
TYPE VitalResultMapType IS ARRAY ( UX01 ) OF std_ulogic;
TYPE VitalResultZMapType IS ARRAY ( UX01Z ) OF std_ulogic;
CONSTANT VitalDefaultOutputMap : VitalOutputMapType
:= "UX01ZWLH-";
CONSTANT VitalDefaultResultMap : VitalResultMapType
:= ( 'U', 'X', '0', '1' );
CONSTANT VitalDefaultResultZMap : VitalResultZMapType
:= ( 'U', 'X', '0', '1', 'Z' );
-- Types for fields of VitalTimingDataType
TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME;
TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT;
TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN;
TYPE VitalBoolArrayPT IS ACCESS VitalBoolArrayT;
TYPE VitalLogicArrayPT IS ACCESS std_logic_vector;
TYPE VitalTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
FUNCTION VitalTimingDataInit RETURN VitalTimingDataType;
-- type for internal data of VitalPeriodPulseCheck
TYPE VitalPeriodDataType IS RECORD
Last : X01;
Rise : TIME;
Fall : TIME;
NotFirstFlag : BOOLEAN;
END RECORD;
CONSTANT VitalPeriodDataInit : VitalPeriodDataType
:= ('X', 0 ns, 0 ns, FALSE );
-- Type for specifying the kind of Glitch handling to use
TYPE VitalGlitchKindType IS (OnEvent,
OnDetect,
VitalInertial,
VitalTransport);
TYPE VitalGlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
LastValue : std_ulogic;
END RECORD;
TYPE VitalGlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF VitalGlitchDataType;
-- PathTypes: for handling simple PathDelay info
TYPE VitalPathType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01Type IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01ZType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01Z;-- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
-- For representing multiple paths to an output
TYPE VitalPathArrayType IS ARRAY (NATURAL RANGE <> ) OF VitalPathType;
TYPE VitalPathArray01Type IS ARRAY (NATURAL RANGE <> ) OF VitalPath01Type;
TYPE VitalPathArray01ZType IS ARRAY (NATURAL RANGE <> ) OF VitalPath01ZType;
TYPE VitalTableSymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S' -- steady value
);
SUBTYPE VitalEdgeSymbolType IS VitalTableSymbolType RANGE '/' TO '*';
-- ------------------------------------------------------------------------
--
-- Function Name: VitalExtendToFillDelay
--
-- Description: A six element array of delay values of type
-- VitalDelayType01Z is returned when a 1, 2 or 6
-- element array is given. This function will convert
-- VitalDelayType and VitalDelayType01 delay values into
-- a VitalDelayType01Z type following these rules:
--
-- When a VitalDelayType is passed, all six transition
-- values are assigned the input value. When a
-- VitalDelayType01 is passed, the 01 transitions are
-- assigned to the 01, 0Z and Z1 transitions and the 10
-- transitions are assigned to 10, 1Z and Z0 transition
-- values. When a VitalDelayType01Z is passed, the values
-- are kept as is.
--
-- The function is overloaded based on input type.
--
-- There is no function to fill a 12 value delay
-- type.
--
-- Arguments:
--
-- IN Type Description
-- Delay A one, two or six delay value Vital-
-- DelayType is passed and a six delay,
-- VitalDelayType01Z, item is returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- VitalDelayType01Z
--
-- -------------------------------------------------------------------------
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalDelayType01Z;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalCalcDelay
--
-- Description: This function accepts a 1, 2 or 6 value delay and
-- chooses the correct delay time to delay the NewVal
-- signal. This function is overloaded based on the
-- delay type passed. The function returns a single value
-- of time.
--
-- This function is provided for Level 0 models in order
-- to calculate the delay which should be applied
-- for the passed signal. The delay selection is performed
-- using the OldVal and the NewVal to determine the
-- transition to select. The default value of OldVal is X.
--
-- This function cannot be used in a Level 1 model since
-- the VitalPathDelay routines perform the delay path
-- selection and output driving function.
--
-- Arguments:
--
-- IN Type Description
-- NewVal New value of the signal to be
-- assigned
-- OldVal Previous value of the signal.
-- Default value is 'X'
-- Delay The delay structure from which to
-- select the appropriate delay. The
-- function overload is based on the
-- type of delay passed. In the case of
-- the single delay, VitalDelayType, no
-- selection is performed, since there
-- is only one value to choose from.
-- For the other cases, the transition
-- from the old value to the new value
-- decide the value returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- Time The time value selected from the
-- Delay INPUT is returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN TIME;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPathDelay
--
-- Description: VitalPathDelay is the Level 1 routine used to select
-- the propagation delay path and schedule a new output
-- value.
--
-- For single and dual delay values, VitalDelayType and
-- VitalDelayType01 are used. The output value is
-- scheduled with a calculated delay without strength
-- modification.
--
-- For the six delay value, VitalDelayType01Z, the output
-- value is scheduled with a calculated delay. The drive
-- strength can be modified to handle weak signal strengths
-- to model tri-state devices, pull-ups and pull-downs as
-- an example.
--
-- The correspondence between the delay type and the
-- path delay function is as follows:
--
-- Delay Type Path Type
--
-- VitalDelayType VitalPathDelay
-- VitalDelayType01 VitalPathDelay01
-- VitalDelayType01Z VitalPathDelay01Z
--
-- For each of these routines, the following capabilities
-- is provided:
--
-- o Transition dependent path delay selection
-- o User controlled glitch detection with the ability
-- to generate "X" on output and report the violation
-- o Control of the severity level for message generation
-- o Scheduling of the computed values on the specified
-- signal.
--
-- Selection of the appropriate path delay begins with the
-- candidate paths. The candidate paths are selected by
-- identifying the paths for which the PathCondition is
-- true. If there is a single candidate path, then that
-- delay is selected. If there is more than one candidate
-- path, then the shortest delay is selected using
-- transition dependent delay selection. If there is no
-- candidate paths, then the delay specified by the
-- DefaultDelay parameter to the path delay is used.
--
-- Once the delay is known, the output signal is then
-- scheduled with that delay. In the case of
-- VitalPathDelay01Z, an additional result mapping of
-- the output value is performed before scheduling. The
-- result mapping is performed after transition dependent
-- delay selection but before scheduling the final output.
--
-- In order to perform glitch detection, the user is
-- obligated to provide a variable of VitalGlitchDataType
-- for the propagation delay functions to use. The user
-- cannot modify or use this information.
--
-- Arguments:
--
-- IN Type Description
-- OutSignalName string The name of the output signal
-- OutTemp std_logic The new output value to be driven
-- Paths VitalPathArrayType A list of paths of VitalPathArray
-- VitalPathArrayType01 type. The VitalPathDelay routine
-- VitalPathArrayType01Z is overloaded based on the type
-- of constant passed in. With
-- VitalPathArrayType01Z, the
-- resulting output strengths can be
-- mapped.
-- DefaultDelay VitalDelayType The default delay can be changed
-- VitalDelayType01 from zero-delay to another set of
-- VitalDelayType01Z values.
-- Mode VitalGlitchKindType The value of this constant
-- selects the type of glitch
-- detection.
-- OnEvent Glitch on transition event
-- | OnDetect Glitch immediate on detection
-- | VitalInertial No glitch, use INERTIAL
-- assignment
-- | VitalTransport No glitch, use TRANSPORT
-- assignment
-- XOn BOOLEAN Control for generation of 'X' on
-- glitch. When TRUE, 'X's are
-- scheduled for glitches, otherwise
-- no are generated.
-- MsgOn BOOLEAN Control for message generation on
-- glitch detect. When TRUE,
-- glitches are reported, otherwise
-- they are not reported.
-- MsgSeverity SEVERITY_LEVEL The level at which the message,
-- or assertion, will be reported.
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the output
-- can be mapped to alternate
-- strengths to model tri-state
-- devices, pull-ups and pull-downs.
--
-- INOUT
-- GlitchData VitalGlitchDataType The internal data storage
-- variable required to detect
-- glitches.
--
-- OUT
-- OutSignal std_logic The output signal to be driven
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalPathDelay (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01 (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01Z (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT OutputMap : IN VitalOutputMapType
:= VitalDefaultOutputMap
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalWireDelay
--
-- Description: VitalWireDelay is used to delay an input signal.
-- The delay is selected from the input parameter passed.
-- The function is useful for back annotation of actual
-- net delays.
--
-- The function is overloaded to permit passing a delay
-- value for twire for VitalDelayType, VitalDelayType01
-- and VitalDelayType01Z. twire is a generic which can
-- be back annotated and must be constructed to follow
-- the SDF to generic mapping rules.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The input signal (port) to be
-- delayed.
-- twire VitalDelayType The delay value for which the input
-- VitalDelayType01 signal should be delayed. For Vital-
-- VitalDelayType01Z DelayType, the value is single value
-- passed. For VitalDelayType01 and
-- VitalDelayType01Z, the appropriate
-- delay value is selected by VitalCalc-
-- Delay.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The internal delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01Z
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSignalDelay
--
-- Description: The VitalSignalDelay procedure is called in a signal
-- delay block in the architecture to delay the
-- appropriate test or reference signal in order to
-- accommodate negative constraint checks.
--
-- The amount of delay is of type TIME and is a constant.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The signal to be delayed.
-- dly TIME The amount of time the signal is
-- delayed.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSignalDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT dly : IN TIME
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSetupHoldCheck
--
-- Description: The VitalSetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal. A vector and scalar form are provided.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- std_logic_vector
-- TestSignalName STRING Name of test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- with RefSignal
-- SetupHigh TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a setup violation.
-- SetupLow TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a setup violation.
-- HoldHigh TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a hold violation.
-- HoldLow TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events on
-- the RefSignal which match the edge
-- spec. are used as reference edges.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalSetupHoldCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalRecoveryRemovalCheck
--
-- Description: The VitalRecoveryRemovalCheck detects the presence of
-- a recovery or removal violation on the input test
-- signal with respect to the corresponding input reference
-- signal. It assumes non-negative values of setup and
-- hold timing constraints. The timing constraint is
-- specified through parameters representing the recovery
-- and removal times associated with a reference edge of
-- the reference signal. A flag indicates whether a test
-- signal is asserted when it is high or when it is low.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative recovery times result in
-- a delayed reference signal. Negative removal times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of TestSignal. The routine is
-- TestSignalName STRING Name of TestSignal
-- TestDelay TIME Model internal delay associated with
-- the TestSignal
-- RefSignal std_ulogic Value of RefSignal
-- RefSignalName STRING Name of RefSignal
-- RefDelay TIME Model internal delay associated with
-- the RefSignal
-- Recovery TIME A change to an unasserted value on
-- the asynchronous TestSignal must
-- precede reference edge (on RefSignal)
-- by at least this time.
-- Removal TIME An asserted condition must be present
-- on the asynchronous TestSignal for at
-- least the removal time following a
-- reference edge on RefSignal.
-- ActiveLow BOOLEAN A flag which indicates if TestSignal
-- is asserted when it is low - "0."
-- FALSE indicate that TestSignal is
-- asserted when it has a value "1."
-- CheckEnabled BOOLEAN The check in enabled when the value
-- is TRUE, otherwise the constraints
-- are not checked.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specifier. Events on
-- RefSignal will match the edge
-- specified.
-- HeaderMsg STRING A header message that will accompany
-- any assertion message.
-- XOn BOOLEAN When TRUE, the output Violation is
-- set to "X." When FALSE, it is always
-- "0."
-- MsgOn BOOLEAN When TRUE, violation messages are
-- output. When FALSE, no messages are
-- generated.
-- MsgSeverity SEVERITY_LEVEL Severity level of the asserted
-- message.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalRecoveryRemovalCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalRecoveryRemovalCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT Recovery : IN TIME := 0 ns;
CONSTANT Removal : IN TIME := 0 ns;
CONSTANT ActiveLow : IN BOOLEAN := TRUE;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum and maximum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- Period TIME Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh TIME Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow TIME Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- PeriodData VitalPeriodDataType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- ------------------------------------------------------------------------
PROCEDURE VitalPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT Period : IN TIME := 0 ns;
CONSTANT PulseWidthHigh : IN TIME := 0 ns;
CONSTANT PulseWidthLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
END VITAL_Timing;
| gpl-2.0 |
davewebb8211/ghdl | libraries/ieee/numeric_bit-body.vhdl | 7 | 57051 | -- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
--==============================================================================
--======================= Package Body =========================================
--==============================================================================
package body NUMERIC_BIT is
-- null range array constants
constant NAU: UNSIGNED(0 downto 1) := (others => '0');
constant NAS: SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING: BOOLEAN := FALSE; -- default to emit warnings
--=========================Local Subprograms =================================
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
function SIGNED_NUM_BITS (ARG: INTEGER) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG: NATURAL) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end UNSIGNED_NUM_BITS;
------------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R: UNSIGNED; C: BIT) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(L_LEFT downto 0) is R;
variable RESULT: UNSIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_SIGNED (L, R: SIGNED; C: BIT) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(L_LEFT downto 0) is R;
variable RESULT: SIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_SIGNED;
------------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM: UNSIGNED; XQUOT, XREMAIN: out UNSIGNED) is
variable TEMP: UNSIGNED(NUM'LENGTH downto 0);
variable QUOT: UNSIGNED(MAX(NUM'LENGTH, XDENOM'LENGTH)-1 downto 0);
alias DENOM: UNSIGNED(XDENOM'LENGTH-1 downto 0) is XDENOM;
variable TOPBIT: INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'RANGE loop
if DENOM(J)='1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "DIV, MOD, or REM by zero" severity ERROR;
for J in NUM'LENGTH-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1)='0'
report "internal error in the division algorithm"
severity ERROR;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'LENGTH);
XREMAIN := RESIZE(TEMP, XREMAIN'LENGTH);
end DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end XSLL;
function XSRL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end XSRL;
function XSRA (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0);
variable XCOUNT: NATURAL := COUNT;
begin
if ((ARG'LENGTH <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end XSRA;
function XROL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end XROL;
function XROR (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end XROR;
---------------- Local Subprograms - Relational Operators --------------------
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R: SIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) < BIT_VECTOR(R);
end UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) < BIT_VECTOR(INTERN_R);
end SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) <= BIT_VECTOR(R);
end UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) <= BIT_VECTOR(INTERN_R);
end SIGNED_LESS_OR_EQUAL;
--====================== Exported Functions ==================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
variable RESULT: SIGNED(ARG_LEFT downto 0);
begin
if ARG'LENGTH < 1 then return NAS;
end if;
RESULT := ARG;
if RESULT(RESULT'LEFT) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end "abs";
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: SIGNED(ARG_LEFT downto 0);
variable CBIT: BIT := '1';
begin
if ARG'LENGTH < 1 then return NAS;
end if;
for I in 0 to RESULT'LEFT loop
RESULT(I) := not(XARG(I)) xor CBIT;
CBIT := CBIT and not(XARG(I));
end loop;
return RESULT;
end "-";
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'LENGTH);
end "+";
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) + R;
end "+";
-- Id: A.7
function "+" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'LENGTH);
end "+";
-- Id: A.8
function "+" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) + R;
end "+";
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'LENGTH);
end "-";
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) - R;
end "-";
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'LENGTH);
end "-";
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) - R;
end "-";
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable RESULT: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) := (others => '0');
variable ADVAL: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end "*";
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable RESULT: SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL: SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := L;
XR := R;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT-1 loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT)='1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end "*";
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'LENGTH);
end "*";
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) * R;
end "*";
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'LENGTH);
end "*";
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) * R;
end "*";
--============================================================================
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FQUOT;
end "/";
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable QNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
QNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end "/";
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, QUOT: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH
and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, QUOT: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => QUOT(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
--============================================================================
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "rem";
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
RNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "rem";
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "mod";
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
RNEG := TRUE;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'LEFT)='1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN/="0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'LEFT)='1' and FREMAIN/="0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "mod";
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end ">";
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end ">";
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end "<";
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end "<";
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "<=";
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end ">=";
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end ">=";
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "=";
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "=";
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH)));
end "/=";
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH)));
end "/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSRL(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSRA(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
--============================================================================
--START-V93
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
--END-V93
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: NATURAL := 0;
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
for I in XARG'RANGE loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER is
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
if ARG(ARG'LEFT) = '0' then
return TO_INTEGER(UNSIGNED(ARG));
else
return (- (TO_INTEGER(UNSIGNED(- (ARG + 1)))) -1);
end if;
end TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL =0) then
assert NO_WARNING
report "NUMERIC_BIT.TO_UNSIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG: INTEGER;
SIZE: NATURAL) return SIGNED is
variable RESULT: SIGNED(SIZE-1 downto 0);
variable B_VAL: BIT := '0';
variable I_VAL: INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL/=0) or (B_VAL/=RESULT(RESULT'LEFT))) then
assert NO_WARNING
report "NUMERIC_BIT.TO_SIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_SIGNED;
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG;
variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'LENGTH = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'LEFT));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end RESIZE;
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'LENGTH =0 then return RESULT;
end if;
if (RESULT'LENGTH < ARG'LENGTH) then
RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
else
RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0');
RESULT(XARG'LEFT downto 0) := XARG;
end if;
return RESULT;
end RESIZE;
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-V93
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-V93
-- Id: L.8
function "not" (L: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-V93
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-V93
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '1';
end RISING_EDGE;
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '0';
end FALLING_EDGE;
--============================================================================
end NUMERIC_BIT;
| gpl-2.0 |
davewebb8211/ghdl | libraries/ieee/numeric_std.vhdl | 6 | 34284 | -- --------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_STD)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_STD. The NUMERIC_STD package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
--
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- Version: 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD is
constant CopyRightNotice: STRING
:= "Copyright 1995 IEEE. All rights reserved.";
--============================================================================
-- Numeric array type definitions
--============================================================================
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
--============================================================================
-- Arithmetic Operators:
--===========================================================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" (L: UNSIGNED;R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of SIZE L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of SIZE R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost
-- element, ARG'LEFT. The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED
-- vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED
-- vector COUNT times.
--============================================================================
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified SIZE.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED; --V93
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
--============================================================================
-- Match Functions
--============================================================================
-- Id: M.1
function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.2
function STD_MATCH (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.3
function STD_MATCH (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.4
function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.5
function STD_MATCH (L, R: STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S: UNSIGNED; XMAP: STD_LOGIC := '0') return UNSIGNED;
-- Result subtype: UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- Id: T.2
function TO_01 (S: SIGNED; XMAP: STD_LOGIC := '0') return SIGNED;
-- Result subtype: SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
end NUMERIC_STD;
| gpl-2.0 |
louis-bonicel/VHDL | Porte_AND/addN.vhd | 2 | 1166 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:22:12 02/06/2015
-- Design Name:
-- Module Name: addN - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addN is
generic(N: integer := 5);
port ( a,b: in std_logic_vector ( N-1 downto 0);
s: out std_logic_vector (N-1 downto 0));
end addN;
architecture archi of addN is
begin
process(a,b)
begin
s <= a + b ;
end process ;
end archi; | gpl-2.0 |
davewebb8211/ghdl | libraries/ieee/math_complex-body.vhdl | 2 | 12489 | ---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE BODY MATH_COMPLEX
--
-- Purpose: VHDL declarations for mathematical package MATH_COMPLEX
-- which contains common complex constants and basic complex
-- functions and operations.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body uses package IEEE.MATH_REAL
--
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- Source code for this package body comes from the following
-- following sources:
-- IEEE VHDL Math Package Study Group participants,
-- U. of Mississippi, Mentor Graphics, Synopsys,
-- Viewlogic/Vantage, Communications of the ACM (June 1988, Vol
-- 31, Number 6, pp. 747, Pierre L'Ecuyer, Efficient and Portable
-- Random Number Generators, Handbook of Mathematical Functions
-- by Milton Abramowitz and Irene A. Stegun (Dover).
--
-- History:
-- Version 0.1 Jose A. Torres 4/23/93 First draft
-- Version 0.2 Jose A. Torres 5/28/93 Fixed potentially illegal code
--
-------------------------------------------------------------
Library IEEE;
Use IEEE.MATH_REAL.all; -- real trascendental operations
Package body MATH_COMPLEX is
function CABS(Z: in complex ) return real is
-- returns absolute value (magnitude) of Z
variable ztemp : complex_polar;
begin
ztemp := COMPLEX_TO_POLAR(Z);
return ztemp.mag;
end CABS;
function CARG(Z: in complex ) return real is
-- returns argument (angle) in radians of a complex number
variable ztemp : complex_polar;
begin
ztemp := COMPLEX_TO_POLAR(Z);
return ztemp.arg;
end CARG;
function CMPLX(X: in real; Y: in real := 0.0 ) return complex is
-- returns complex number X + iY
begin
return COMPLEX'(X, Y);
end CMPLX;
function "-" (Z: in complex ) return complex is
-- unary minus; returns -x -jy for z= x + jy
begin
return COMPLEX'(-z.Re, -z.Im);
end "-";
function "-" (Z: in complex_polar ) return complex_polar is
-- unary minus; returns (z.mag, z.arg + MATH_PI)
begin
return COMPLEX_POLAR'(z.mag, z.arg + MATH_PI);
end "-";
function CONJ (Z: in complex) return complex is
-- returns complex conjugate (x-jy for z = x+ jy)
begin
return COMPLEX'(z.Re, -z.Im);
end CONJ;
function CONJ (Z: in complex_polar) return complex_polar is
-- returns complex conjugate (z.mag, -z.arg)
begin
return COMPLEX_POLAR'(z.mag, -z.arg);
end CONJ;
function CSQRT(Z: in complex ) return complex_vector is
-- returns square root of Z; 2 values
variable ztemp : complex_polar;
variable zout : complex_vector (0 to 1);
variable temp : real;
begin
ztemp := COMPLEX_TO_POLAR(Z);
temp := SQRT(ztemp.mag);
zout(0).re := temp*COS(ztemp.arg/2.0);
zout(0).im := temp*SIN(ztemp.arg/2.0);
zout(1).re := temp*COS(ztemp.arg/2.0 + MATH_PI);
zout(1).im := temp*SIN(ztemp.arg/2.0 + MATH_PI);
return zout;
end CSQRT;
function CEXP(Z: in complex ) return complex is
-- returns e**Z
begin
return COMPLEX'(EXP(Z.re)*COS(Z.im), EXP(Z.re)*SIN(Z.im));
end CEXP;
function COMPLEX_TO_POLAR(Z: in complex ) return complex_polar is
-- converts complex to complex_polar
begin
return COMPLEX_POLAR'(sqrt(z.re**2 + z.im**2),atan2(z.re,z.im));
end COMPLEX_TO_POLAR;
function POLAR_TO_COMPLEX(Z: in complex_polar ) return complex is
-- converts complex_polar to complex
begin
return COMPLEX'( z.mag*cos(z.arg), z.mag*sin(z.arg) );
end POLAR_TO_COMPLEX;
--
-- arithmetic operators
--
function "+" ( L: in complex; R: in complex ) return complex is
begin
return COMPLEX'(L.Re + R.Re, L.Im + R.Im);
end "+";
function "+" (L: in complex_polar; R: in complex_polar) return complex is
variable zL, zR : complex;
begin
zL := POLAR_TO_COMPLEX( L );
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(zL.Re + zR.Re, zL.Im + zR.Im);
end "+";
function "+" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re + R.Re, zL.Im + R.Im);
end "+";
function "+" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L.Re + zR.Re, L.Im + zR.Im);
end "+";
function "+" ( L: in real; R: in complex ) return complex is
begin
return COMPLEX'(L + R.Re, R.Im);
end "+";
function "+" ( L: in complex; R: in real ) return complex is
begin
return COMPLEX'(L.Re + R, L.Im);
end "+";
function "+" ( L: in real; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L + zR.Re, zR.Im);
end "+";
function "+" ( L: in complex_polar; R: in real) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re + R, zL.Im);
end "+";
function "-" ( L: in complex; R: in complex ) return complex is
begin
return COMPLEX'(L.Re - R.Re, L.Im - R.Im);
end "-";
function "-" ( L: in complex_polar; R: in complex_polar) return complex is
variable zL, zR : complex;
begin
zL := POLAR_TO_COMPLEX( L );
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(zL.Re - zR.Re, zL.Im - zR.Im);
end "-";
function "-" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re - R.Re, zL.Im - R.Im);
end "-";
function "-" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L.Re - zR.Re, L.Im - zR.Im);
end "-";
function "-" ( L: in real; R: in complex ) return complex is
begin
return COMPLEX'(L - R.Re, -1.0 * R.Im);
end "-";
function "-" ( L: in complex; R: in real ) return complex is
begin
return COMPLEX'(L.Re - R, L.Im);
end "-";
function "-" ( L: in real; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L - zR.Re, -1.0*zR.Im);
end "-";
function "-" ( L: in complex_polar; R: in real) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re - R, zL.Im);
end "-";
function "*" ( L: in complex; R: in complex ) return complex is
begin
return COMPLEX'(L.Re * R.Re - L.Im * R.Im, L.Re * R.Im + L.Im * R.Re);
end "*";
function "*" ( L: in complex_polar; R: in complex_polar) return complex is
variable zout : complex_polar;
begin
zout.mag := L.mag * R.mag;
zout.arg := L.arg + R.arg;
return POLAR_TO_COMPLEX(zout);
end "*";
function "*" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re*R.Re - zL.Im * R.Im, zL.Re * R.Im + zL.Im*R.Re);
end "*";
function "*" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L.Re*zR.Re - L.Im * zR.Im, L.Re * zR.Im + L.Im*zR.Re);
end "*";
function "*" ( L: in real; R: in complex ) return complex is
begin
return COMPLEX'(L * R.Re, L * R.Im);
end "*";
function "*" ( L: in complex; R: in real ) return complex is
begin
return COMPLEX'(L.Re * R, L.Im * R);
end "*";
function "*" ( L: in real; R: in complex_polar) return complex is
variable zR : complex;
begin
zR := POLAR_TO_COMPLEX( R );
return COMPLEX'(L * zR.Re, L * zR.Im);
end "*";
function "*" ( L: in complex_polar; R: in real) return complex is
variable zL : complex;
begin
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'(zL.Re * R, zL.Im * R);
end "*";
function "/" ( L: in complex; R: in complex ) return complex is
variable magrsq : REAL := R.Re ** 2 + R.Im ** 2;
begin
if (magrsq = 0.0) then
assert FALSE report "Attempt to divide by (0,0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'( (L.Re * R.Re + L.Im * R.Im) / magrsq,
(L.Im * R.Re - L.Re * R.Im) / magrsq);
end if;
end "/";
function "/" ( L: in complex_polar; R: in complex_polar) return complex is
variable zout : complex_polar;
begin
if (R.mag = 0.0) then
assert FALSE report "Attempt to divide by (0,0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
zout.mag := L.mag/R.mag;
zout.arg := L.arg - R.arg;
return POLAR_TO_COMPLEX(zout);
end if;
end "/";
function "/" ( L: in complex_polar; R: in complex ) return complex is
variable zL : complex;
variable temp : REAL := R.Re ** 2 + R.Im ** 2;
begin
if (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
zL := POLAR_TO_COMPLEX( L );
return COMPLEX'( (zL.Re * R.Re + zL.Im * R.Im) / temp,
(zL.Im * R.Re - zL.Re * R.Im) / temp);
end if;
end "/";
function "/" ( L: in complex; R: in complex_polar) return complex is
variable zR : complex := POLAR_TO_COMPLEX( R );
variable temp : REAL := zR.Re ** 2 + zR.Im ** 2;
begin
if (R.mag = 0.0) or (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'( (L.Re * zR.Re + L.Im * zR.Im) / temp,
(L.Im * zR.Re - L.Re * zR.Im) / temp);
end if;
end "/";
function "/" ( L: in real; R: in complex ) return complex is
variable temp : REAL := R.Re ** 2 + R.Im ** 2;
begin
if (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
temp := L / temp;
return COMPLEX'( temp * R.Re, -temp * R.Im );
end if;
end "/";
function "/" ( L: in complex; R: in real ) return complex is
begin
if (R = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'(L.Re / R, L.Im / R);
end if;
end "/";
function "/" ( L: in real; R: in complex_polar) return complex is
variable zR : complex := POLAR_TO_COMPLEX( R );
variable temp : REAL := zR.Re ** 2 + zR.Im ** 2;
begin
if (R.mag = 0.0) or (temp = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
temp := L / temp;
return COMPLEX'( temp * zR.Re, -temp * zR.Im );
end if;
end "/";
function "/" ( L: in complex_polar; R: in real) return complex is
variable zL : complex := POLAR_TO_COMPLEX( L );
begin
if (R = 0.0) then
assert FALSE report "Attempt to divide by (0.0,0.0)"
severity ERROR;
return COMPLEX'(REAL'RIGHT, REAL'RIGHT);
else
return COMPLEX'(zL.Re / R, zL.Im / R);
end if;
end "/";
end MATH_COMPLEX;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/switch_dig.vhd | 4 | 1752 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity switch_dig is
generic ( r_open : resistance := 1.0e6;
r_closed : resistance := 1.0e-3;
trans_time : real := 1.0e-9 );
port ( sw_state : in std_logic;
terminal p1, p2 : electrical );
end entity switch_dig;
----------------------------------------------------------------
architecture linear of switch_dig is
signal r_sig : resistance := r_open;
quantity v across i through p1 to p2;
quantity r : resistance;
begin
-- detect switch state and assign resistance value to r_sig
DetectState: process (sw_state)
begin
if (sw_state'event and sw_state = '0') then
r_sig <= r_open;
elsif (sw_state'event and sw_state = '1') then
r_sig <= r_closed;
end if;
end process DetectState;
r == r_sig'ramp(trans_time, trans_time);
v == r * i;
end architecture linear;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_13.vhd | 4 | 1108 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_13.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package tb_05_13 is
subtype word is integer;
end package tb_05_13;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1526.vhd | 4 | 1608 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1526.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p08n01i01526ent IS
END c08s09b00x00p08n01i01526ent;
ARCHITECTURE c08s09b00x00p08n01i01526arch OF c08s09b00x00p08n01i01526ent IS
BEGIN
TESTING: PROCESS
BEGIN
while "HELLO" & "O" loop
end loop;
assert FALSE
report "***FAILED TEST: c08s09b00x00p08n01i01526 - while condition is not boolean expression"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p08n01i01526arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_08.vhd | 4 | 1782 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_08.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture do_nothing of ROM is
begin
end architecture do_nothing;
entity tb_05_08 is
end entity tb_05_08;
architecture test of tb_05_08 is
signal address : natural := 0;
signal data : bit_vector(0 to 7);
signal enable : bit := '0';
begin
dut : entity work.ROM(do_nothing)
port map ( address => address, data => data, enable => enable );
stimulus : process is
begin
wait for 100 ns;
address <= 1000; wait for 10 ns;
enable <= '1', '0' after 10 ns; wait for 90 ns;
address <= 1004; wait for 10 ns;
enable <= '1', '0' after 10 ns; wait for 90 ns;
address <= 1008; wait for 10 ns;
enable <= '1', '0' after 10 ns; wait for 90 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc910.vhd | 4 | 1944 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc910.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00910ent IS
END c10s03b00x00p05n01i00910ent;
ARCHITECTURE c10s03b00x00p05n01i00910arch OF c10s03b00x00p05n01i00910ent IS
BEGIN
B2:block
type A is (A1, A2, A3);
signal S : A;
begin
S <= A1;
end block B2;
B3:block
signal S1 : A; -- Failure_here
-- error: entity not within the region it is immediately declared
begin
S1 <= A1; -- Failure_here
-- error: entity nor within the region it is immediately declated
end block B3;
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: /c10s03b00x00p05n01i00910 - Entity is not within the region it is immediately declared in."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00910arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_06.vhd | 4 | 2378 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
use std.textio.all;
architecture test of inline_06 is
subtype encoding_type is bit_vector(1 downto 0);
attribute encoding : encoding_type;
begin
process1 : process is
-- code from book:
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle [ return controller_state ] : literal is b"00";
attribute encoding of active [ return controller_state ] : literal is b"01";
attribute encoding of fail_safe [ return controller_state ] : literal is b"10";
-- end of code from book
variable L : line;
begin
write(L, string'("process1"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, active [ return controller_state ] ' encoding);
writeline(output, L);
write(L, fail_safe [ return controller_state ] ' encoding);
writeline(output, L);
wait;
end process process1;
process2 : process is
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle : literal is b"11";
variable L : line;
begin
write(L, string'("process2"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, idle [ return load_level ] ' encoding);
writeline(output, L);
wait;
end process process2;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1020.vhd | 4 | 1985 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1020.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n01i01020ent IS
port (p : in bit);
END c06s03b00x00p10n01i01020ent;
ARCHITECTURE c06s03b00x00p10n01i01020arch OF c06s03b00x00p10n01i01020ent IS
BEGIN
B1:Block
type chars is ('a', 'b', 'c', 'd', 'e');
begin
TESTING: PROCESS
variable c : chars;
variable All_done : boolean;
BEGIN
L1 : for LL1 in 0 to 5 loop
TESTING.c := 'a';
end loop L1;
assert NOT(TESTING.c='a')
report "***PASSED TEST: c06s03b00x00p10n01i01020"
severity NOTE;
assert (TESTING.c='a')
report "***FAILED TEST: c06s03b00x00p10n01i01020 - Entity declaration does not occur in construct specifed by the prefix."
severity ERROR;
wait;
END PROCESS TESTING;
end block B1;
END c06s03b00x00p10n01i01020arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_04.vhd | 4 | 2115 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_ch_04_04.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_04_04 is
end entity ch_04_04;
----------------------------------------------------------------
architecture test of ch_04_04 is
begin
process_04_1_i : process is
-- code from book:
type A is array (1 to 4, 31 downto 0) of boolean;
-- end of code from book
variable free_map : bit_vector(1 to 10) := "0011010110";
variable count : natural;
begin
-- code from book (just the conditions):
assert A'left(1) = 1; assert A'low(1) = 1;
assert A'right(2) = 0 ; assert A'high(2) = 31;
assert A'length(1) = 4; assert A'length(2) = 32;
assert A'ascending(1) = true; assert A'ascending(2) = false;
assert A'low = 1; assert A'length = 4;
--
count := 0;
for index in free_map'range loop
if free_map(index) = '1' then
count := count + 1;
end if;
end loop;
-- end of code from book
wait;
end process process_04_1_i;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket26/psl_test_named_statement.vhd | 3 | 1191 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity psl_test_named_statement is
end entity psl_test_named_statement;
architecture test of psl_test_named_statement is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 100 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING psl_test_named_statement test case";
report "==========================================";
s_write <= '0'; -- named assertion should hit
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1';
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait;
end process TestP;
-- -psl statements
-- psl default clock is rising_edge(s_clk);
-- named statements seems to be not supported (ignored by GHDL)
-- psl RESET_CHECK : assert always not(s_rst_n) -> s_write;
-- statements without name work
-- - psl assert always s_write -> not(s_read);
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_22.vhd | 4 | 1476 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_22.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity S_R_flipflop is
port ( s, r : in bit; q, q_n : out bit );
end entity S_R_flipflop;
--------------------------------------------------
architecture functional of S_R_flipflop is
begin
q <= '1' when s = '1' else
'0' when r = '1';
q_n <= '0' when s = '1' else
'1' when r = '1';
check : assert not (s = '1' and r = '1')
report "Incorrect use of S_R_flip_flop: s and r both '1'";
end architecture functional;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc513.vhd | 4 | 1812 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc513.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p02n01i00513ent IS
END c03s03b00x00p02n01i00513ent;
ARCHITECTURE c03s03b00x00p02n01i00513arch OF c03s03b00x00p02n01i00513ent IS
type a is range 1 to 10;
type b is access a; -- Success_here
BEGIN
TESTING: PROCESS
variable k :b;
BEGIN
assert NOT(k = null)
report "***PASSED TEST: c03s03b00x00p02n01i00513"
severity NOTE;
assert ( k = null )
report "***FAILED TEST: c03s03b00x00p02n01i00513 - In the access type definition, the reserved word access must be followed by a subtype definition."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p02n01i00513arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc444.vhd | 4 | 3232 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc444.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00444ent IS
END c03s02b01x01p19n01i00444ent;
ARCHITECTURE c03s02b01x01p19n01i00444arch OF c03s02b01x01p19n01i00444ent IS
type integer_vector is array (natural range <>) of integer;
subtype integer_vector_st is integer_vector(0 to 15);
constant C1 : integer := 4;
constant C70 : integer_vector_st :=(others => C1);
function complex_scalar(s : integer_vector_st) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return integer_vector_st is
begin
return C70;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : integer_vector_st;
signal S2 : integer_vector_st;
signal S3 : integer_vector_st := C70;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C70) and (S2 = C70))
report "***PASSED TEST: c03s02b01x01p19n01i00444"
severity NOTE;
assert ((S1 = C70) and (S2 = C70))
report "***FAILED TEST: c03s02b01x01p19n01i00444 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00444arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink-b.vhd | 4 | 4519 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_sink-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library math;
architecture behavior of sink is
begin
token_consumer : process is
variable number_of_tokens_consumed : natural := 0;
variable life_time : real; -- in time_unit
variable sum_of_life_times : real := 0.0; -- in time_unit
variable sum_of_squares_of_life_times : real := 0.0; --in time_unit**2
use std.textio.all;
file info_file : text;
variable L : line;
use math.math_real.sqrt;
procedure write_summary is
variable mean_life_time : real
:= sum_of_life_times / real(number_of_tokens_consumed);
variable std_dev_of_life_times : real
:= sqrt ( ( sum_of_squares_of_life_times
- sum_of_life_times**2 / real(number_of_tokens_consumed) )
/ real( number_of_tokens_consumed - 1 ) );
begin
write(L, string'("Summary information for sink "));
write(L, name);
write(L, string'(" up to time "));
write(L, now, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Number of tokens consumed = "));
write(L, natural(number_of_tokens_consumed));
writeline(info_file, L);
write(L, string'(" Mean life_time = "));
write(L, mean_life_time * time_unit, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Standard deviation of life_times = "));
write(L, std_dev_of_life_times * time_unit, unit => time_unit);
writeline(info_file, L);
writeline(info_file, L);
end procedure write_summary;
procedure write_trace is
begin
write(L, string'("Sink "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" consumed "));
write(L, in_arc.token, time_unit);
writeline(info_file, L);
end procedure write_trace;
begin
file_open(info_file, info_file_name, write_mode);
loop
wait on info_detail'transaction, in_arc;
if info_detail'active and info_detail = summary then
write_summary;
end if;
if in_arc'event then
number_of_tokens_consumed := number_of_tokens_consumed + 1;
life_time := real( (now - in_arc.token.creation_time) / time_unit );
sum_of_life_times := sum_of_life_times + life_time;
sum_of_squares_of_life_times := sum_of_squares_of_life_times + life_time ** 2;
if info_detail = trace then
write_trace;
end if;
end if;
end loop;
end process token_consumer;
end architecture behavior;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1209.vhd | 4 | 4688 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1209.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s01b00x00p24n01i01209pkg is
-- Type declarations.
type SWITCH_LEVEL is ( '0', '1', 'X' );
type S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
-- Define the bus resolution function.
function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
-- Further type declarations.
subtype SWITCH_T is switchF SWITCH_LEVEL;
type WORD is array(0 to 31) of SWITCH_T;
end c08s01b00x00p24n01i01209pkg;
package body c08s01b00x00p24n01i01209pkg is
-- A dumb resolution function.
function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
begin
return( S(1) );
end switchf;
end c08s01b00x00p24n01i01209pkg;
use work.c08s01b00x00p24n01i01209pkg.all;
ENTITY c08s01b00x00p24n01i01209ent IS
END c08s01b00x00p24n01i01209ent;
ARCHITECTURE c08s01b00x00p24n01i01209arch OF c08s01b00x00p24n01i01209ent IS
-- Local types
type WORD2 is array(0 to 31) of SWITCH_LEVEL;
type REC is RECORD
R1 : SWITCH_T;
R2 : SWITCH_T;
end RECORD;
-- Local signals.
signal A : WORD;
signal UnResolved : WORD2;
signal RecSig : REC;
BEGIN
TESTING: PROCESS
-- Constant declarations.
constant One : INTEGER := 1;
constant Two : INTEGER := 2;
-- Local variables.
variable ShouldBeTime : TIME;
variable I : INTEGER;
variable k : integer := 0;
BEGIN
--1. Test waiting on an array of scalar resolved elements.
for I in 0 to 31 loop
ShouldBeTime := NOW + 1 ns;
A( I ) <= 'X' after 1 ns;
wait on A;
if (A(I) /= 'X' and ShouldBeTime /= Now) then
k := 1;
end if;
-- Verify that we waited the right amount of time.
assert (ShouldBeTime = NOW);
assert (A( I ) = 'X');
end loop;
-- 2. Test waiting on an array of scalar unresolved elements.
ShouldBeTime := NOW + 1 ns;
UnResolved <= ( '1','1','1','1','1','1','1','1','1','1',
'1','1','1','1','1','1','1','1','1','1',
'1','1','1','1','1','1','1','1','1','1',
'1','1' ) after 1 ns;
wait on UnResolved;
if (UnResolved /= ( '1','1','1','1','1','1','1','1','1','1',
'1','1','1','1','1','1','1','1','1','1',
'1','1','1','1','1','1','1','1','1','1',
'1','1' ) and ShouldBeTime /= Now) then
k := 1;
end if;
-- Verify that we waited allright.
assert (ShouldBeTime = NOW);
for I in 0 to 31 loop
assert ( UnResolved( I ) = '1');
end loop;
-- 3. Test waiting on a record.
RECSIG.R1 <= 'X' after 1 ns;
RECSIG.R2 <= 'X' after 2 ns;
ShouldBeTime := NOW + 1 ns;
wait on RECSIG;
if (RECSIG.R1 /= 'X' and ShouldBeTime /= Now) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (RECSIG.R1 = 'X');
ShouldBeTime := NOW + 1 ns;
wait on RECSIG;
if (RECSIG.R2 /= 'X' and ShouldBeTime /= Now) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (RECSIG.R2 = 'X');
assert NOT( k=0 )
report "***PASSED TEST: c08s01b00x00p24n01i01209"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s01b00x00p24n01i01209 - The effect of a signal name denotes a signal of a composite type is as if name of each scalar subelement of that signal appears in the list."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p24n01i01209arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket78/bug.vhdl | 3 | 273 | entity ent is
end entity;
architecture a of ent is
procedure proc(bv : bit_vector) is
begin
report to_string(bv'length);
end procedure;
begin
main : process
variable bv : bit_vector(0 to 1);
begin
proc(bv);
wait;
end process;
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc188.vhd | 4 | 2091 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc188.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p13n01i00188ent IS
port ( S2 : in integer;
V2 : inout Real ) ;
attribute V1 : REAL;
attribute V1 of V2 : signal is 1.0;
alias A2 : real is V2;
attribute S1 : INTEGER;
attribute S1 of S2 : signal is 1;
alias A1 : integer is S2;
END c04s04b00x00p13n01i00188ent;
ARCHITECTURE c04s04b00x00p13n01i00188arch OF c04s04b00x00p13n01i00188ent IS
BEGIN
TESTING: PROCESS
subtype BTRUE is BOOLEAN range TRUE to TRUE;
variable B1 : BTRUE;
BEGIN
assert NOT( (A1'S1 = S2'S1) and (A2'V1 = V2'V1) )
report "***PASSED TEST: c04s04b00x00p13n01i00188"
severity NOTE;
assert ( (A1'S1 = S2'S1) and (A2'V1 = V2'V1) )
report "***FAILED TEST: c04s04b00x00p13n01i00188 - Attribute of an object applies to any alias of the object."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p13n01i00188arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1127.vhd | 4 | 1770 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1127.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p04n01i01127ent IS
END c06s05b00x00p04n01i01127ent;
ARCHITECTURE c06s05b00x00p04n01i01127arch OF c06s05b00x00p04n01i01127ent IS
type idx is range 1 to 10;
type aray1 is array (idx) of bit;
type aray2 is array (idx range <>) of aray1;
BEGIN
TESTING: PROCESS
variable v2 : aray1;
variable v3 : aray2(1 to 2);
BEGIN
v2 := v3(2 to 2)(1); -- wrong index
assert FALSE
report "***FAILED TEST: c06s05b00x00p04n01i01127 - Invalid index for slice."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p04n01i01127arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/bug16695/lfsr_updown.vhd | 3 | 2090 | -------------------------------------------------------
-- Design Name : lfsr
-- File Name : lfsr_updown.vhd
-- Function : Linear feedback shift register
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lfsr_updown is
generic (
WIDTH :integer := 8
);
port (
clk :in std_logic; -- Clock input
reset :in std_logic; -- Reset input
enable :in std_logic; -- Enable input
up_down :in std_logic; -- Up Down input
count :out std_logic_vector (WIDTH-1 downto 0); -- Count output
overflow :out std_logic -- Overflow output
);
end entity;
architecture rtl of lfsr_updown is
signal cnt :std_logic_vector (WIDTH-1 downto 0);
begin
process (up_down, cnt) begin
if (((up_down = '1') and (cnt(WIDTH-1) = '1')) or
((up_down = '0') and ((cnt(WIDTH-1) = '1') and
(cnt(WIDTH-2 downto 0) = "0")))) then
overflow <= '1';
else
overflow <= '0';
end if;
end process;
process (clk, reset, cnt, enable, up_down)
variable temp_a :std_logic_vector (WIDTH-1 downto 0);
variable temp_b :std_logic :='1';
begin
temp_a := cnt and "01100011";
temp_b :='1';
for i in 0 to WIDTH-1 loop
temp_b := temp_a(i) xnor temp_b;
end loop;
if (rising_edge(clk)) then
if (reset = '1') then
cnt <= (others=>'0');
elsif (enable = '1') then
if (up_down = '1') then
cnt <= (temp_b & cnt(WIDTH-1 downto 1));
else
cnt <= (cnt(WIDTH-2 downto 0) & temp_b);
end if;
end if;
end if;
end process;
count <= cnt;
end architecture;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_03.vhd | 4 | 1500 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
library ieee;
architecture test of inline_03 is
begin
process_3_a : process is
-- code from book:
use work.cpu_types;
variable data_word : cpu_types.word;
variable next_address : cpu_types.address;
-- end of code from book
begin
wait;
end process process_3_a;
----------------
process_3_b : process is
-- code from book:
use work.cpu_types.word, work.cpu_types.address;
variable data_word : word;
variable next_address : address;
-- end of code from book
begin
wait;
end process process_3_b;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_02.vhd | 4 | 1896 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_02.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- test code:
use work.test_bench_03_02.all;
-- end test code
library ieee; use ieee.std_logic_1164.all;
entity mux4 is
port ( sel : in sel_range;
d0, d1, d2, d3 : in std_ulogic;
z : out std_ulogic );
end entity mux4;
architecture demo of mux4 is
begin
out_select : process (sel, d0, d1, d2, d3) is
begin
case sel is
when 0 =>
z <= d0;
when 1 =>
z <= d1;
when 2 =>
z <= d2;
when 3 =>
z <= d3;
end case;
end process out_select;
end architecture demo;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc356.vhd | 4 | 1768 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc356.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00356ent IS
END c03s02b01x01p02n01i00356ent;
ARCHITECTURE c03s02b01x01p02n01i00356arch OF c03s02b01x01p02n01i00356ent IS
type days is (mon, tue, wed, thu, fri, sat, sun);
type weekdays is (mon, tue, wed, thu, fri);
type startdays is array (mon to wed) of integer; --Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00356 - Both bounds in the constrained array definition must have the same discrete type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00356arch;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2406.vhd | 4 | 1776 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2406.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n05i02406ent IS
END c07s03b02x00p08n05i02406ent;
ARCHITECTURE c07s03b02x00p08n05i02406arch OF c07s03b02x00p08n05i02406ent IS
type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
signal S1 : ARRAY_TYPE(1 to 2) ;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= (others=>TRUE,TRUE); -- Failure_here
-- SEMANTIC ERROR: association cannot follow "others" association.
assert FALSE
report "***FAILED TEST: c07s03b02x00p08n05i02406 - Nothing may follow an others association."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n05i02406arch;
| gpl-2.0 |
peteut/ghdl | testsuite/gna/ticket89/x_ieee_proposed/src/env_c.vhdl | 3 | 1300 | package ENV is
procedure STOP (STATUS : INTEGER);
procedure FINISH (STATUS : INTEGER);
function RESOLUTION_LIMIT return DELAY_LENGTH;
end package ENV;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
package body ENV is
procedure STOP (STATUS : INTEGER) is
begin
report "Procedure STOP called with status: " & INTEGER'image(STATUS)
severity failure;
end procedure STOP;
procedure FINISH (STATUS : INTEGER) is
begin
report "Procedure FINISH called with status: " & INTEGER'image(STATUS)
severity failure;
end procedure FINISH;
constant BASE_TIME_ARRAY : time_vector :=
(
1 fs, 10 fs, 100 fs,
1 ps, 10 ps, 100 ps,
1 ns, 10 ns, 100 ns,
1 us, 10 us, 100 us,
1 ms, 10 ms, 100 ms,
1 sec, 10 sec, 100 sec,
1 min, 10 min, 100 min,
1 hr, 10 hr, 100 hr
) ;
function RESOLUTION_LIMIT return DELAY_LENGTH is
begin
for i in BASE_TIME_ARRAY'range loop
if BASE_TIME_ARRAY(i) > 0 hr then
return BASE_TIME_ARRAY(i);
end if;
end loop;
report "STANDATD.RESOLUTION_LIMIT: Simulator resolution not less than 100 hr"
severity failure;
return 1 ns;
end function RESOLUTION_LIMIT;
end package body ENV;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_05a.vhd | 4 | 2480 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_05a is
end entity inline_05a;
architecture test of inline_05a is
begin
block_1 : block is
constant cap : real := 1.0e-9;
constant rleak : real := 1.0E6;
-- code from book
terminal p1, p2 : electrical;
quantity vcap across icap, ileak through p1 to p2;
-- end code from book
begin
-- code from book
icap == cap * vcap'dot;
ileak == vcap / rleak;
-- end code from book
end block block_1;
block_2 : block is
-- code from book
nature electrical_vector is array (natural range <>) of electrical;
terminal a_bus : electrical_vector(1 to 8);
terminal signal_ground : electrical;
--
quantity bus_drops across bus_currents through a_bus to signal_ground;
--
terminal p1 : electrical_vector(0 to 3);
terminal p2 : electrical;
quantity v across i through p1 to p2;
--
constant tc1 : real := 1.0e-3; -- Linear temperature coefficient
constant tc2 : real := 1.0e-6; -- Second-order temperature coefficient
constant temp : real := 27.0; -- Ambient temperature
constant tnom : real := 50.0; -- Nominal temperature
constant res : real_vector := (1.0e3, 2.0e3, 4.0e3, 8.0e3); -- Nominal resistances
--
constant res_factor : real := (1.0 + tc1*(temp-tnom) + tc2*(temp-tnom)**2);
-- end code from book
begin
-- code from book
v(0) == i(0) * res(0) * res_factor;
v(1) == i(1) * res(1) * res_factor;
v(2) == i(2) * res(2) * res_factor;
v(3) == i(3) * res(3) * res_factor;
-- end code from book
end block block_2;
end architecture test;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb.vhd | 4 | 1076 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tb.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity test_bench is
end entity test_bench;
| gpl-2.0 |
peteut/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_10a.vhd | 4 | 1691 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_10a is
end entity inline_10a;
----------------------------------------------------------------
architecture test of inline_10a is
-- code from book:
type stick_position is (down, center, up);
-- end of code from book
signal throttle : stick_position;
begin
process_3_a : process (throttle) is
variable speed : integer := 0;
constant decrement : integer := 1;
constant increment : integer := 1;
begin
-- code from book:
case throttle is
when down =>
speed := speed - decrement;
when up =>
speed := speed + increment;
when center =>
null; -- no change to speed
end case;
-- end of code from book
end process process_3_a;
stimulus : process is
begin
throttle <= down after 10 ns, center after 20 ns, up after 30 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
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