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pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SW_standalone/hdl/design_SW_standalone_wrapper.vhd | 1 | 6,330 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
--Date : Wed Aug 31 22:23:41 2016
--Host : DESKTOP-I329812 running 64-bit major release (build 9200)
--Command : generate_target design_SW_standalone_wrapper.bd
--Design : design_SW_standalone_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SW_standalone_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
leds_4bits_tri_io : inout STD_LOGIC_VECTOR ( 3 downto 0 )
);
end design_SW_standalone_wrapper;
architecture STRUCTURE of design_SW_standalone_wrapper is
component design_SW_standalone is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
leds_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component design_SW_standalone;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal leds_4bits_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal leds_4bits_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal leds_4bits_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal leds_4bits_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal leds_4bits_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal leds_4bits_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal leds_4bits_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
design_SW_standalone_i: component design_SW_standalone
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
leds_4bits_tri_i(3) => leds_4bits_tri_i_3(3),
leds_4bits_tri_i(2) => leds_4bits_tri_i_2(2),
leds_4bits_tri_i(1) => leds_4bits_tri_i_1(1),
leds_4bits_tri_i(0) => leds_4bits_tri_i_0(0),
leds_4bits_tri_o(3) => leds_4bits_tri_o_3(3),
leds_4bits_tri_o(2) => leds_4bits_tri_o_2(2),
leds_4bits_tri_o(1) => leds_4bits_tri_o_1(1),
leds_4bits_tri_o(0) => leds_4bits_tri_o_0(0),
leds_4bits_tri_t(3) => leds_4bits_tri_t_3(3),
leds_4bits_tri_t(2) => leds_4bits_tri_t_2(2),
leds_4bits_tri_t(1) => leds_4bits_tri_t_1(1),
leds_4bits_tri_t(0) => leds_4bits_tri_t_0(0)
);
leds_4bits_tri_iobuf_0: component IOBUF
port map (
I => leds_4bits_tri_o_0(0),
IO => leds_4bits_tri_io(0),
O => leds_4bits_tri_i_0(0),
T => leds_4bits_tri_t_0(0)
);
leds_4bits_tri_iobuf_1: component IOBUF
port map (
I => leds_4bits_tri_o_1(1),
IO => leds_4bits_tri_io(1),
O => leds_4bits_tri_i_1(1),
T => leds_4bits_tri_t_1(1)
);
leds_4bits_tri_iobuf_2: component IOBUF
port map (
I => leds_4bits_tri_o_2(2),
IO => leds_4bits_tri_io(2),
O => leds_4bits_tri_i_2(2),
T => leds_4bits_tri_t_2(2)
);
leds_4bits_tri_iobuf_3: component IOBUF
port map (
I => leds_4bits_tri_o_3(3),
IO => leds_4bits_tri_io(3),
O => leds_4bits_tri_i_3(3),
T => leds_4bits_tri_t_3(3)
);
end STRUCTURE;
| gpl-3.0 | b41b7937f43da918b5f0e2fde90a2351 | 0.593523 | 2.769029 | false | false | false | false |
bonfireprocessor/bonfire-soc | uart/tb_soc_uart.vhd | 1 | 5,811 | -- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2016 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
-- TH: Enhanced UART Testbench to test UART receiver more deeply
library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
library STD;
use STD.textio.all;
use work.txt_util.all;
entity tb_soc_uart is
end entity tb_soc_uart;
architecture testbench of tb_soc_uart is
-- Clock signal:
signal clk : std_logic := '0';
constant clk_period : time := 10.41 ns; --Clock 96Mhz
-- Reset signal:
signal reset : std_logic := '1';
-- UART ports:
signal txd : std_logic;
signal rxd : std_logic := '1';
-- interrupt signals:
signal irq : std_logic;
-- Wishbone ports:
signal wb_adr_in : std_logic_vector(7 downto 0) := (others => '0');
signal wb_dat_in : std_logic_vector( 7 downto 0) := (others => '0');
signal wb_dat_out : std_logic_vector( 7 downto 0);
signal wb_we_in : std_logic := '0';
signal wb_cyc_in : std_logic := '0';
signal wb_stb_in : std_logic := '0';
signal wb_ack_out : std_logic;
constant Teststr : string :="The quick brown fox";
constant baudrate : natural := 115200;
constant bit_time : time := 8.68 us;
signal cbyte : std_logic_vector(7 downto 0);
signal bitref : integer :=0;
signal finish : boolean := false;
constant log_file : string := "receive.log";
begin
uut: entity work.wb_uart_interface
generic map(
FIFO_DEPTH => 32 )
port map(
clk => clk,
reset => reset,
txd => txd,
rxd => rxd,
irq => irq,
wb_adr_in => wb_adr_in,
wb_dat_in => wb_dat_in,
wb_dat_out => wb_dat_out,
wb_we_in => wb_we_in,
wb_cyc_in => wb_cyc_in,
wb_stb_in => wb_stb_in,
wb_ack_out => wb_ack_out
);
clock: process
begin
clk <= '1';
wait for clk_period / 2;
clk <= '0';
wait for clk_period / 2;
end process clock;
send: process
procedure send_byte(v: std_logic_vector(7 downto 0)) is
variable bi : natural;
variable t : std_logic_vector(7 downto 0);
begin
bi:=7;
for i in 0 to 7 loop
t(bi) := v(i); -- for debugging purposes
bi:=bi-1;
end loop;
cbyte <= t;
bitref<= 0;
rxd <= '0'; -- start bit
for i in 0 to 7 loop
wait for bit_time;
rxd<=v(i);
bitref<=bitref+1;
end loop;
wait for bit_time;
rxd <= '1'; -- stop bit
bitref<=bitref+1;
wait for bit_time;
end;
procedure sendstring(s:string) is
begin
for i in 1 to s'length loop
send_byte(std_logic_vector(to_unsigned(character'pos(s(i)),8)));
end loop;
end;
begin
wait for bit_time*10;
-- Send range of bytes
-- for i in 0 to 255 loop
-- send_byte(std_logic_vector(to_unsigned(i,8)));
-- end loop;
--
-- -- send difficult values
-- for i in 0 to 16 loop
-- send_byte("10000000");
-- end loop;
--
-- for i in 0 to 16 loop
-- send_byte("00000001");
-- end loop;
-- Send a string to the UART receiver pin
for i in 0 to 128 / Teststr'length loop
sendstring(Teststr);
end loop;
wait for bit_time*10;
finish<=true; -- signal end of send simulation
wait;
end process;
stimulus: process
procedure uart_write(address : in std_logic_vector(7 downto 0); data : in std_logic_vector(7 downto 0)) is
begin
wb_adr_in <= address;
wait until rising_edge(clk);
wb_dat_in <= data;
wb_we_in <= '1';
wb_cyc_in <= '1';
wb_stb_in <= '1';
wait until wb_ack_out = '1';
wait until rising_edge(clk);
wb_stb_in <= '0';
wb_cyc_in <= '0';
end procedure;
procedure uart_read(address : in std_logic_vector(7 downto 0);
data: out std_logic_vector(7 downto 0) ) is
begin
wb_adr_in <= address;
wait until rising_edge(clk);
wb_we_in <= '1';
wb_cyc_in <= '1';
wb_stb_in <= '1';
wb_we_in <= '0';
wait until wb_ack_out = '1';
data:= wb_dat_out;
wait until rising_edge(clk);
wb_stb_in <= '0';
wb_cyc_in <= '0';
--wait for clk_period;
end procedure;
variable status,rx_byte : std_logic_vector(7 downto 0);
variable s: string(1 to 1);
file l_file: TEXT open write_mode is log_file;
begin
wait for clk_period * 2;
reset <= '0';
uart_write(x"0C",std_logic_vector(to_unsigned(51,8))); -- Divisor 51 for 115200 Baud
-- Enable the data received interrupt:
--uart_write(x"10", x"01");
--receive loop
while not finish loop
-- Check Status Register
status := X"01";
while (status and X"01") = X"01" and not finish loop
uart_read(X"08",status);
end loop;
-- Get byte
if (status and X"01") = X"00" then
uart_read(X"04",rx_byte);
s(1):=character'val(to_integer(unsigned(rx_byte)));
write(l_file,s);
--print(l_file,hstr(rx_byte));
end if;
end loop;
print("Receive Simulation finished");
-- UART Send Simulation
for i in 1 to TestStr'length loop
-- Check Status Register
status := X"08";
while (status and X"82") /= X"02" loop
uart_read(X"08",status);
end loop;
uart_write(X"00",char_to_ascii_byte(TestStr(i)));
end loop;
print("Send Simulation finished");
wait;
end process stimulus;
end architecture testbench;
| gpl-3.0 | ac6afa7776db9ed93b6f17a271283c5e | 0.549475 | 3.262774 | false | false | false | false |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fcmp_0_no_dsp_32/synth/ANN_ap_fcmp_0_no_dsp_32.vhd | 1 | 12,772 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fcmp_0_no_dsp_32 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ANN_ap_fcmp_0_no_dsp_32;
ARCHITECTURE ANN_ap_fcmp_0_no_dsp_32_arch OF ANN_ap_fcmp_0_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fcmp_0_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fcmp_0_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fcmp_0_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=1,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=1,C_RESULT_FRACTION_WIDTH=0,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=1,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=8,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 1,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 1,
C_RESULT_FRACTION_WIDTH => 0,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 1,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 8,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => s_axis_operation_tvalid,
s_axis_operation_tdata => s_axis_operation_tdata,
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fcmp_0_no_dsp_32_arch;
| gpl-3.0 | ba96c2c9b7f847b66d2ce31846e306ca | 0.650329 | 2.996715 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/ip/ANN_ap_fptrunc_0_no_dsp_64.vhd | 6 | 12,165 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fptrunc_0_no_dsp_64 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fptrunc_0_no_dsp_64;
ARCHITECTURE ANN_ap_fptrunc_0_no_dsp_64_arch OF ANN_ap_fptrunc_0_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fptrunc_0_no_dsp_64_arch : ARCHITECTURE IS "ANN_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "ANN_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fptrunc_0_no_dsp_64_arch;
| gpl-3.0 | 00f6eac198209392032faa5f7e0d6b70 | 0.646363 | 3.003704 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/interrupt_control_v3_1/hdl/src/vhdl/interrupt_control.vhd | 4 | 57,397 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers. This module has been optimized
-- for the 64 bit wide PLB bus.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP2
--
-- Initial Release
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_K_SP3
--
-- Updated to use proc_common_v4_0_2 library
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- DET 11/5/2003 v1_00_e
-- ~~~~~~
-- - Revamped register topology to take advantage of 64 bit wide data bus
-- interface. This required adding the Bus2IP_BE_sa input port to
-- provide byte lane qualifiers for write operations.
-- ^^^^^^
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed proc_common library reference to v2_00_a
-- - Removed ipif_common library reference
-- ^^^^^^
-- GAB 06/29/2005 v2_00_a
-- ~~~~~~
-- - Modified plb_interrupt_control of plb_ipif_v1_00_f to make
-- a common version that supports 32,64, and 128-Bit Data Bus Widths.
-- - Changed to use ieee.numeric_std library and removed
-- ieee.std_logic_arith.all
-- ^^^^^^
-- GAB 09/01/2006 v2_00_a
-- ~~~~~~
-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs
-- - Removed strobe from interrupt enable registers where it was not needed
-- ^^^^^^
-- GAB 07/02/2008 v3_1
-- ~~~~~~
-- - Modified to used proc_common_v4_0_2 library
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of Interrupt Control to v3.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0_2
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_NUM_CE : integer range 4 to 16 := 4;
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2 -- pass through (inverting)
);
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER : boolean := false;
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : boolean := false;
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH : integer range 32 to 128 := 128
);
port(
-- Inputs From the IPIF Bus
bus2ip_clk : In std_logic;
bus2ip_reset : In std_logic;
bus2ip_data : In std_logic_vector(0 to C_IPIF_DWIDTH-1);
bus2ip_be : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
interrupt_rdce : In std_logic_vector(0 to C_NUM_CE-1);
interrupt_wrce : In std_logic_vector(0 to C_NUM_CE-1);
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
ipif_reg_interrupts : In std_logic_vector(0 to 1);
-- Level Interrupt inputs from the IPIF sources
ipif_lvl_interrupts : In std_logic_vector
(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Inputs from the IP Interface
ip2bus_intrevent : In std_logic_vector
(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Final Device Interrupt Output
intr2bus_devintr : Out std_logic;
-- Status Reply Outputs to the Bus
intr2bus_dbus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
intr2bus_wrack : Out std_logic;
intr2bus_rdack : Out std_logic;
intr2bus_error : Out std_logic;
intr2bus_retry : Out std_logic;
intr2bus_toutsup : Out std_logic
);
end interrupt_control;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_max_allowed_irpt_width
--
-- Function Description:
-- This function determines the maximum number of interrupts that
-- can be processed from the User IP based on the IPIF data bus width
-- and the number of interrupt entries desired.
--
-------------------------------------------------------------------
function get_max_allowed_irpt_width(data_bus_width : integer;
num_intrpts_entered : integer)
return integer is
Variable temp_max : Integer;
begin
If (data_bus_width >= num_intrpts_entered) Then
temp_max := num_intrpts_entered;
else
temp_max := data_bus_width;
End if;
return(temp_max);
end function get_max_allowed_irpt_width;
-------------------------------------------------------------------------------
-- Function data_port_map
-- This function will return an index within a 'reg_width' divided port
-- having a width of 'port_width' based on an address 'offset'.
-- For instance if the port_width is 128-bits and the register width
-- reg_width = 32 bits and the register address offset=16 (0x10), this
-- function will return a index of 0.
--
-- Address Offset Returned Index Return Index Returned Index
-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus)
-- 0x00 0 0 0
-- 0x04 1 1 0
-- 0x08 2 0 0
-- 0x0C 3 1 0
-- 0x10 0 0 0
-- 0x14 1 1 0
-- 0x18 2 0 0
-- 0x1C 3 1 0
-------------------------------------------------------------------------------
function data_port_map(offset : integer;
reg_width : integer;
port_width : integer)
return integer is
variable upper_index : integer;
variable vector_range : integer;
variable reg_offset : std_logic_vector(0 to 7);
variable word_offset_i : integer;
begin
-- Calculate index position to start decoding the address offset
upper_index := log2(port_width/8);
-- Calculate the number of bits to look at in decoding
-- the address offset
vector_range := max2(1,log2(port_width/reg_width));
-- Convert address offset into a std_logic_vector in order to
-- strip out a set of bits for decoding
reg_offset := std_logic_vector(to_unsigned(offset,8));
-- Calculate an index representing the word position of
-- a register with respect to the port width.
word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length
- upper_index to (reg_offset'length
- upper_index) + vector_range - 1)));
return word_offset_i;
end data_port_map;
-------------------------------------------------------------------------------
-- Type declarations
-------------------------------------------------------------------------------
-- no Types
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- figure out if 32 bits wide or 64 bits wide
Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1;
Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32);
constant BITS_PER_REG : integer := 32;
constant BYTES_PER_REG : integer := BITS_PER_REG/8;
-- Register Index
Constant DEVICE_ISR_INDEX : integer := 0;
Constant DEVICE_IPR_INDEX : integer := 1;
Constant DEVICE_IER_INDEX : integer := 2;
Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD
Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD
Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD
Constant DEVICE_IIR_INDEX : integer := 6;
Constant DEVICE_GIE_INDEX : integer := 7;
Constant IP_ISR_INDEX : integer := 8;
Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD
Constant IP_IER_INDEX : integer := 10;
Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD
Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD
Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD
Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD
Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
-- Register Address Offset
Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG;
Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG;
Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG;
Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG;
Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG;
Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG;
Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG;
Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG;
Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG;
Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG;
Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG;
Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG;
Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG;
Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG;
Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG;
Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG;
-- Column Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
-- Generic to constant mapping
Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1;
Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length;
-- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IP_IRPT_HIGH_INDEX : Integer :=
get_max_allowed_irpt_width(C_IPIF_DWIDTH,
NUM_USER_DESIRED_IRPTS)
-1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector
(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector
(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector
(DBUS_WIDTH_MINUS1 downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector
(PRIORITY_ENC_WIDTH-1 downto 0);
Signal column_sel : std_logic_vector
(0 to LSB_BYTLE_LANE_COL_OFFSET);
signal interrupt_wrce_strb : std_logic;
signal irpt_wrack_d1 : std_logic;
signal irpt_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
REG_WRACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_wrack_d1 <= '0';
Intr2Bus_WrAck <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
Intr2Bus_WrAck <= interrupt_wrce_strb;
end if;
end if;
end process REG_WRACK_PROCESS;
interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1;
REG_RDACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_rdack_d1 <= '0';
Intr2Bus_RdAck <= '0';
else
irpt_rdack_d1 <= irpt_rdack;
Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1;
end if;
end if;
end process REG_RDACK_PROCESS;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_COL
--
-- Process Description:
--
--
-------------------------------------------------------------
ASSIGN_COL : process (Bus2IP_BE)
begin
-- Assign the 32-bit column selects from BE inputs
for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop
column_sel(i) <= Bus2IP_BE(i*4);
end loop;
end process ASSIGN_COL;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to DBUS_WIDTH_MINUS1 loop
Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1' and
column_sel(IP_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs
-- (GAB)
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data((BITS_PER_REG * IP_ISR_COL)
+(BITS_PER_REG - 1)
- irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1' and
column_sel(IP_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ip_irpt_enable_reg <= Bus2IP_Data
( (BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
- IP_IRPT_HIGH_INDEX to
(BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and
column_sel(DEVICE_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then
for i in 0 to 1 loop
-- (GAB)
ipif_irpt_status_reg(i) <= (Bus2IP_Data
( (BITS_PER_REG * DEVICE_ISR_COL)
+(BITS_PER_REG - 1)
- i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1' and
column_sel(DEVICE_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ipif_irpt_enable_reg <= Bus2IP_Data
(
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
- IPIF_IRPT_HIGH_INDEX to
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and
column_sel(DEVICE_GIE_COL) = '1' )then
--interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs
-- (GAB)
ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <= (
Interrupt_WrCE(DEVICE_ISR) and
column_sel(DEVICE_ISR_COL)
)
or
(
Interrupt_WrCE(DEVICE_IER) and
column_sel(DEVICE_IER_COL)
)
or
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <=
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, column_sel,
ip_irpt_status_reg,
ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1'
and column_sel(DEVICE_ISR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_ISR_COL)
- BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1'
and column_sel(DEVICE_IPR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IPR_COL)
- BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1'
and column_sel(DEVICE_IER_COL) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IER_COL)
- BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1'
and column_sel(DEVICE_IIR_COL) = '1') Then
-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_read_data( (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG) + PRIORITY_ENC_WIDTH-1
downto (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG)) <= ipif_priority_encode_value;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg,column_sel)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
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`protect end_protected
| gpl-3.0 | 177baee5c0d6fffed58727152f16484e | 0.95323 | 1.830061 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/vhdl/feedforward.vhd | 1 | 184,791 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity feedforward is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
P_config_V_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
P_config_V_TVALID : IN STD_LOGIC;
P_config_V_TREADY : OUT STD_LOGIC;
P_WandB_TDATA : IN STD_LOGIC_VECTOR (63 downto 0);
P_WandB_TVALID : IN STD_LOGIC;
P_WandB_TREADY : OUT STD_LOGIC;
P_uOut_TDATA : OUT STD_LOGIC_VECTOR (63 downto 0);
P_uOut_TVALID : OUT STD_LOGIC;
P_uOut_TREADY : IN STD_LOGIC;
P_netIn_TDATA : IN STD_LOGIC_VECTOR (63 downto 0);
P_netIn_TVALID : IN STD_LOGIC;
P_netIn_TREADY : OUT STD_LOGIC;
P_netOut_V_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0);
P_netOut_V_TVALID : OUT STD_LOGIC;
P_netOut_V_TREADY : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of feedforward is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"feedforward,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=9.395400,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=36,HLS_SYN_DSP=45,HLS_SYN_FF=7119,HLS_SYN_LUT=10499}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st79_fsm_78 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st80_fsm_79 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st81_fsm_80 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st82_fsm_81 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st83_fsm_82 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st84_fsm_83 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st85_fsm_84 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st86_fsm_85 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st87_fsm_86 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st88_fsm_87 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st89_fsm_88 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st90_fsm_89 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st91_fsm_90 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st92_fsm_91 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st93_fsm_92 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st94_fsm_93 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st95_fsm_94 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st96_fsm_95 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st97_fsm_96 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st98_fsm_97 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st99_fsm_98 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st100_fsm_99 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st101_fsm_100 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st102_fsm_101 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st103_fsm_102 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st104_fsm_103 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st105_fsm_104 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st106_fsm_105 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st107_fsm_106 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st108_fsm_107 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st109_fsm_108 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st110_fsm_109 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st111_fsm_110 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st112_fsm_111 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st113_fsm_112 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st114_fsm_113 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st115_fsm_114 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st116_fsm_115 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st117_fsm_116 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st118_fsm_117 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st119_fsm_118 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st120_fsm_119 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st121_fsm_120 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st122_fsm_121 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st123_fsm_122 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st124_fsm_123 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st125_fsm_124 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st126_fsm_125 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st127_fsm_126 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st128_fsm_127 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st129_fsm_128 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st130_fsm_129 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st131_fsm_130 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st132_fsm_131 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st133_fsm_132 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st134_fsm_133 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st135_fsm_134 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st136_fsm_135 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st137_fsm_136 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st138_fsm_137 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st139_fsm_138 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st140_fsm_139 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st141_fsm_140 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st142_fsm_141 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st143_fsm_142 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st144_fsm_143 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st145_fsm_144 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st146_fsm_145 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st147_fsm_146 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st148_fsm_147 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st149_fsm_148 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st150_fsm_149 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st151_fsm_150 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st152_fsm_151 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st153_fsm_152 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st154_fsm_153 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st155_fsm_154 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st156_fsm_155 : STD_LOGIC_VECTOR (166 downto 0) := "00000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st157_fsm_156 : STD_LOGIC_VECTOR (166 downto 0) := "00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st158_fsm_157 : STD_LOGIC_VECTOR (166 downto 0) := "00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st159_fsm_158 : STD_LOGIC_VECTOR (166 downto 0) := "00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st160_fsm_159 : STD_LOGIC_VECTOR (166 downto 0) := "00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st161_fsm_160 : STD_LOGIC_VECTOR (166 downto 0) := "00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st162_fsm_161 : STD_LOGIC_VECTOR (166 downto 0) := "00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st163_fsm_162 : STD_LOGIC_VECTOR (166 downto 0) := "00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st164_fsm_163 : STD_LOGIC_VECTOR (166 downto 0) := "00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st165_fsm_164 : STD_LOGIC_VECTOR (166 downto 0) := "00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st166_fsm_165 : STD_LOGIC_VECTOR (166 downto 0) := "01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st167_fsm_166 : STD_LOGIC_VECTOR (166 downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
constant ap_const_lv32_7A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111010";
constant ap_const_lv32_9C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011100";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_5C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011100";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_56 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010110";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_5B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011011";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_61 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100001";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv32_73 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110011";
constant ap_const_lv32_4C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001100";
constant ap_const_lv32_99 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_4E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001110";
constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
constant ap_const_lv32_78 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111000";
constant ap_const_lv32_79 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111001";
constant ap_const_lv32_9B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011011";
constant ap_const_lv32_9D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011101";
constant ap_const_lv32_9E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011110";
constant ap_const_lv32_9F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011111";
constant ap_const_lv32_A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100000";
constant ap_const_lv32_A2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100010";
constant ap_const_lv32_A3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100011";
constant ap_const_lv32_A4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100100";
constant ap_const_lv32_A5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100101";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv32_4D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001101";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_9A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011010";
constant ap_const_lv14_0 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000000";
constant ap_const_lv32_A1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100001";
constant ap_const_lv9_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_lv3_4 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_const_lv3_3 : STD_LOGIC_VECTOR (2 downto 0) := "011";
constant ap_const_lv3_2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_74 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110100";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001";
constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
constant ap_const_lv32_5D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011101";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv32_7B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111011";
constant ap_const_lv32_62 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100010";
constant ap_const_lv8_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_const_lv8_3 : STD_LOGIC_VECTOR (7 downto 0) := "00000011";
constant ap_const_lv15_23 : STD_LOGIC_VECTOR (14 downto 0) := "000000000100011";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv9_23 : STD_LOGIC_VECTOR (8 downto 0) := "000100011";
constant ap_const_lv9_1FF : STD_LOGIC_VECTOR (8 downto 0) := "111111111";
constant ap_const_lv16_23 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000100011";
constant ap_const_lv9_1FE : STD_LOGIC_VECTOR (8 downto 0) := "111111110";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv64_8000000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv8_4 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
constant ap_const_lv32_3E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111110";
constant ap_const_lv11_7FF : STD_LOGIC_VECTOR (10 downto 0) := "11111111111";
constant ap_const_lv52_0 : STD_LOGIC_VECTOR (51 downto 0) := "0000000000000000000000000000000000000000000000000000";
constant ap_const_lv14_23 : STD_LOGIC_VECTOR (13 downto 0) := "00000000100011";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv9_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
constant ap_const_lv14_5 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000101";
constant ap_const_lv14_2 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000010";
constant ap_const_lv32_A6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100110";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (166 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_185 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal P_mode_V : STD_LOGIC_VECTOR (7 downto 0);
signal ST_numLayer_V : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_3 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_layerSize_V_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ST_WandB_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal ST_WandB_ce0 : STD_LOGIC;
signal ST_WandB_we0 : STD_LOGIC;
signal ST_WandB_d0 : STD_LOGIC_VECTOR (63 downto 0);
signal ST_WandB_q0 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_return : STD_LOGIC_VECTOR (7 downto 0);
signal feedforward_AXILiteS_s_axi_U_ap_dummy_ce : STD_LOGIC;
signal p_uOut_q0 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_578 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_268 : BOOLEAN;
signal ap_sig_cseq_ST_st81_fsm_80 : STD_LOGIC;
signal ap_sig_bdd_275 : BOOLEAN;
signal ap_sig_cseq_ST_st123_fsm_122 : STD_LOGIC;
signal ap_sig_bdd_283 : BOOLEAN;
signal ap_sig_cseq_ST_st157_fsm_156 : STD_LOGIC;
signal ap_sig_bdd_291 : BOOLEAN;
signal reg_585 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_300 : BOOLEAN;
signal ap_sig_cseq_ST_st93_fsm_92 : STD_LOGIC;
signal ap_sig_bdd_309 : BOOLEAN;
signal grp_fu_543_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_591 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_319 : BOOLEAN;
signal ap_sig_cseq_ST_st87_fsm_86 : STD_LOGIC;
signal ap_sig_bdd_326 : BOOLEAN;
signal grp_fu_535_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_336 : BOOLEAN;
signal ap_sig_cseq_ST_st92_fsm_91 : STD_LOGIC;
signal ap_sig_bdd_343 : BOOLEAN;
signal reg_602 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_352 : BOOLEAN;
signal ap_sig_cseq_ST_st46_fsm_45 : STD_LOGIC;
signal ap_sig_bdd_359 : BOOLEAN;
signal ap_sig_cseq_ST_st98_fsm_97 : STD_LOGIC;
signal ap_sig_bdd_367 : BOOLEAN;
signal grp_fu_557_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_608 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st41_fsm_40 : STD_LOGIC;
signal ap_sig_bdd_377 : BOOLEAN;
signal ap_sig_cseq_ST_st116_fsm_115 : STD_LOGIC;
signal ap_sig_bdd_384 : BOOLEAN;
signal grp_fu_547_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_615 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st77_fsm_76 : STD_LOGIC;
signal ap_sig_bdd_394 : BOOLEAN;
signal ap_sig_cseq_ST_st154_fsm_153 : STD_LOGIC;
signal ap_sig_bdd_401 : BOOLEAN;
signal P_mode_V_read_reg_1453 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_fu_620_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_414 : BOOLEAN;
signal ST_numLayer_V_load_reg_1461 : STD_LOGIC_VECTOR (7 downto 0);
signal ST_layerSize_V_0_load_reg_1472 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_1_fu_630_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal P_config_V_read_reg_1477 : STD_LOGIC_VECTOR (7 downto 0);
signal i_8_fu_647_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_435 : BOOLEAN;
signal exitcond1_fu_642_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_441 : BOOLEAN;
signal tmp_59_cast_fu_673_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_59_cast_reg_1493 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_451 : BOOLEAN;
signal tmp_7_fu_658_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_24_fu_677_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_24_reg_1498 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_29_fu_691_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_29_reg_1503 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_fu_697_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_31_reg_1508 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_36_fu_720_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_36_reg_1513 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_61_cast_fu_724_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_61_cast_reg_1520 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_39_fu_728_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_39_reg_1525 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_41_fu_738_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_41_reg_1530 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_42_fu_744_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_42_reg_1535 : STD_LOGIC_VECTOR (1 downto 0);
signal j_5_fu_771_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_5_reg_1543 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_481 : BOOLEAN;
signal tmp_20_fu_777_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_20_reg_1548 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_16_fu_765_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_54_fu_824_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_54_reg_1554 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_1_reg_1560 : STD_LOGIC_VECTOR (7 downto 0);
signal i_10_fu_830_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal k_3_fu_841_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal k_3_reg_1573 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_503 : BOOLEAN;
signal exitcond3_fu_836_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_fu_898_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st24_fsm_23 : STD_LOGIC;
signal ap_sig_bdd_523 : BOOLEAN;
signal tmp_17_fu_903_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_17_reg_1598 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st79_fsm_78 : STD_LOGIC;
signal ap_sig_bdd_532 : BOOLEAN;
signal i_12_fu_926_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_12_reg_1607 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_fu_932_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_22_reg_1612 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_19_fu_920_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_58_fu_983_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_58_reg_1618 : STD_LOGIC_VECTOR (13 downto 0);
signal p_uOut_addr_3_reg_1624 : STD_LOGIC_VECTOR (7 downto 0);
signal j_6_fu_994_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal j_6_reg_1632 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st80_fsm_79 : STD_LOGIC;
signal ap_sig_bdd_553 : BOOLEAN;
signal exitcond4_fu_989_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st121_fsm_120 : STD_LOGIC;
signal ap_sig_bdd_572 : BOOLEAN;
signal i_11_fu_1046_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_11_reg_1660 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st122_fsm_121 : STD_LOGIC;
signal ap_sig_bdd_581 : BOOLEAN;
signal p_uOut_addr_5_reg_1665 : STD_LOGIC_VECTOR (7 downto 0);
signal exitcond5_fu_1041_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st156_fsm_155 : STD_LOGIC;
signal ap_sig_bdd_595 : BOOLEAN;
signal tmp_38_fu_1071_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_ioackin_P_netOut_V_TREADY : STD_LOGIC;
signal p_uOut_q1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_uOut_load_4_reg_1686 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_51_fu_1181_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_51_reg_1692 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st158_fsm_157 : STD_LOGIC;
signal ap_sig_bdd_617 : BOOLEAN;
signal p_netOut_V_1_fu_1187_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st159_fsm_158 : STD_LOGIC;
signal ap_sig_bdd_626 : BOOLEAN;
signal i_15_fu_1194_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_fu_1200_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_66_reg_1707 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st160_fsm_159 : STD_LOGIC;
signal ap_sig_bdd_637 : BOOLEAN;
signal next_mul_fu_1204_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal next_mul_reg_1712 : STD_LOGIC_VECTOR (13 downto 0);
signal i_14_fu_1215_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_14_reg_1720 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_40_fu_1225_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_40_reg_1725 : STD_LOGIC_VECTOR (7 downto 0);
signal exitcond6_fu_1210_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal j_7_fu_1244_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal j_7_reg_1733 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st161_fsm_160 : STD_LOGIC;
signal ap_sig_bdd_655 : BOOLEAN;
signal exitcond_fu_1239_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_fu_1273_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_s_reg_1746 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_cseq_ST_st163_fsm_162 : STD_LOGIC;
signal ap_sig_bdd_669 : BOOLEAN;
signal tmp_8_fu_1264_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_layerSize_V_load_1_phi_fu_1303_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal ST_layerSize_V_load_1_phi_reg_1751 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_fu_1335_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_10_reg_1756 : STD_LOGIC_VECTOR (8 downto 0);
signal j_4_fu_1346_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal j_4_reg_1764 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st164_fsm_163 : STD_LOGIC;
signal ap_sig_bdd_686 : BOOLEAN;
signal tmp_21_fu_1373_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_21_reg_1769 : STD_LOGIC_VECTOR (13 downto 0);
signal exitcond2_fu_1341_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_9_fu_1379_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal k_2_fu_1404_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st165_fsm_164 : STD_LOGIC;
signal ap_sig_bdd_704 : BOOLEAN;
signal exitcond8_fu_1399_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_710 : BOOLEAN;
signal i_7_fu_1415_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st166_fsm_165 : STD_LOGIC;
signal ap_sig_bdd_720 : BOOLEAN;
signal exitcond7_fu_1410_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_725 : BOOLEAN;
signal p_uOut_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce0 : STD_LOGIC;
signal p_uOut_we0 : STD_LOGIC;
signal p_uOut_d0 : STD_LOGIC_VECTOR (63 downto 0);
signal p_uOut_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_uOut_ce1 : STD_LOGIC;
signal i_2_reg_297 : STD_LOGIC_VECTOR (7 downto 0);
signal i_3_reg_308 : STD_LOGIC_VECTOR (7 downto 0);
signal j_1_reg_320 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st78_fsm_77 : STD_LOGIC;
signal ap_sig_bdd_754 : BOOLEAN;
signal sum_reg_331 : STD_LOGIC_VECTOR (63 downto 0);
signal k_1_reg_343 : STD_LOGIC_VECTOR (7 downto 0);
signal sumsoft_reg_354 : STD_LOGIC_VECTOR (63 downto 0);
signal i_4_reg_366 : STD_LOGIC_VECTOR (31 downto 0);
signal sum_1_reg_377 : STD_LOGIC_VECTOR (63 downto 0);
signal j_2_reg_389 : STD_LOGIC_VECTOR (7 downto 0);
signal i_5_reg_400 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st155_fsm_154 : STD_LOGIC;
signal ap_sig_bdd_776 : BOOLEAN;
signal p_s_reg_411 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_35_fu_1066_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_netOut_V_reg_424 : STD_LOGIC_VECTOR (7 downto 0);
signal i_6_reg_436 : STD_LOGIC_VECTOR (7 downto 0);
signal phi_mul_reg_447 : STD_LOGIC_VECTOR (13 downto 0);
signal j_3_reg_458 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st162_fsm_161 : STD_LOGIC;
signal ap_sig_bdd_805 : BOOLEAN;
signal ap_sig_ioackin_P_uOut_TREADY : STD_LOGIC;
signal i_1_reg_469 : STD_LOGIC_VECTOR (7 downto 0);
signal j_reg_481 : STD_LOGIC_VECTOR (7 downto 0);
signal k_reg_492 : STD_LOGIC_VECTOR (8 downto 0);
signal i_reg_503 : STD_LOGIC_VECTOR (7 downto 0);
signal agg_result_V_reg_514 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_6_fu_653_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_64_cast_fu_795_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_73_cast_fu_860_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_74_cast_fu_870_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_72_cast_fu_883_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_68_cast_fu_954_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_76_cast_fu_1013_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_77_cast_fu_1023_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_75_cast_fu_1036_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_78_cast_fu_1061_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_80_cast_fu_1085_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_81_cast_fu_1099_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_82_cast_fu_1259_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_63_cast_fu_1394_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_3_fu_1421_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ioackin_P_netOut_V_TREADY : STD_LOGIC := '0';
signal ap_reg_ioackin_P_uOut_TREADY : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st117_fsm_116 : STD_LOGIC;
signal ap_sig_bdd_929 : BOOLEAN;
signal grp_fu_535_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_535_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_954 : BOOLEAN;
signal ap_sig_cseq_ST_st19_fsm_18 : STD_LOGIC;
signal ap_sig_bdd_961 : BOOLEAN;
signal ap_sig_cseq_ST_st42_fsm_41 : STD_LOGIC;
signal ap_sig_bdd_969 : BOOLEAN;
signal ap_sig_cseq_ST_st88_fsm_87 : STD_LOGIC;
signal ap_sig_bdd_976 : BOOLEAN;
signal ap_sig_cseq_ST_st94_fsm_93 : STD_LOGIC;
signal ap_sig_bdd_983 : BOOLEAN;
signal grp_fu_547_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_547_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st47_fsm_46 : STD_LOGIC;
signal ap_sig_bdd_1012 : BOOLEAN;
signal ap_sig_cseq_ST_st124_fsm_123 : STD_LOGIC;
signal ap_sig_bdd_1019 : BOOLEAN;
signal grp_fu_557_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st99_fsm_98 : STD_LOGIC;
signal ap_sig_bdd_1029 : BOOLEAN;
signal tmp_23_fu_667_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_23_fu_667_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_4_fu_681_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_29_fu_691_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal lhs_V_1_cast_fu_701_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_fu_704_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_fu_714_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_fu_714_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal r_V_1_fu_732_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_14_fu_748_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_15_fu_761_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_46_fu_790_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_52_fu_800_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_53_fu_812_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl2_cast_fu_804_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl3_cast_fu_816_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_29_cast_fu_851_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_61_fu_855_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_29_cast1_fu_847_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_62_fu_865_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_24_cast_fu_875_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_60_fu_878_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_38_to_int_fu_888_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_38_neg_fu_892_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_18_fu_916_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_23_cast_fu_945_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_55_fu_949_p2 : STD_LOGIC_VECTOR (32 downto 0);
signal tmp_56_fu_959_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_57_fu_971_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_shl4_cast_fu_963_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl5_cast_fu_975_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_33_cast_fu_1004_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_64_fu_1008_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_33_cast1_fu_1000_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_65_fu_1018_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_cast_fu_1028_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_63_fu_1031_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_36_cast_fu_1052_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_59_fu_1056_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_41_cast_fu_1076_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_68_fu_1080_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_42_cast_fu_1090_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_69_fu_1094_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal p_uOut_load_3_to_int_fu_1104_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_uOut_load_4_to_int_fu_1122_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_43_fu_1108_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_70_fu_1118_p1 : STD_LOGIC_VECTOR (51 downto 0);
signal notrhs_fu_1145_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs_fu_1139_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_45_fu_1125_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_71_fu_1135_p1 : STD_LOGIC_VECTOR (51 downto 0);
signal notrhs1_fu_1163_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs1_fu_1157_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_47_fu_1151_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_48_fu_1169_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_49_fu_1175_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_fu_553_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_40_fu_1225_p5 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_52_cast_fu_1250_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_72_fu_1254_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_s_fu_1273_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_5_fu_1279_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal sel_tmp_fu_1283_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_fu_1297_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp1_fu_1289_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_2_fu_1317_p5 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_2_fu_1317_p6 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_9_fu_1331_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_cast_fu_1352_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_11_fu_1356_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_12_fu_1361_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_13_fu_1367_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_12_cast_fu_1385_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_44_fu_1389_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_cseq_ST_st167_fsm_166 : STD_LOGIC;
signal ap_sig_bdd_1384 : BOOLEAN;
signal grp_fu_535_ce : STD_LOGIC;
signal grp_fu_543_ce : STD_LOGIC;
signal grp_fu_547_ce : STD_LOGIC;
signal tmp_50_fu_553_opcode : STD_LOGIC_VECTOR (4 downto 0);
signal grp_fu_557_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (166 downto 0);
signal tmp_23_fu_667_p10 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_29_fu_691_p10 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_s_fu_1273_p10 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_bdd_909 : BOOLEAN;
component feedforward_dadd_64ns_64ns_64_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_dmul_64ns_64ns_64_6_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_ddiv_64ns_64ns_64_31 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_dcmp_64ns_64ns_1_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
opcode : IN STD_LOGIC_VECTOR (4 downto 0);
dout : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component feedforward_dexp_64ns_64ns_64_18_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_mux_4to1_sel2_8_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
din3_WIDTH : INTEGER;
din4_WIDTH : INTEGER;
din5_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
din2 : IN STD_LOGIC_VECTOR (7 downto 0);
din3 : IN STD_LOGIC_VECTOR (7 downto 0);
din4 : IN STD_LOGIC_VECTOR (7 downto 0);
din5 : IN STD_LOGIC_VECTOR (1 downto 0);
dout : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component feedforward_ST_WandB IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (63 downto 0);
q0 : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_p_uOut IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (63 downto 0);
q0 : OUT STD_LOGIC_VECTOR (63 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component feedforward_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_return : IN STD_LOGIC_VECTOR (7 downto 0);
P_mode_V : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
ST_WandB_U : component feedforward_ST_WandB
generic map (
DataWidth => 64,
AddressRange => 5040,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_WandB_address0,
ce0 => ST_WandB_ce0,
we0 => ST_WandB_we0,
d0 => ST_WandB_d0,
q0 => ST_WandB_q0);
feedforward_AXILiteS_s_axi_U : component feedforward_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => feedforward_AXILiteS_s_axi_U_ap_dummy_ce,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
ap_return => ap_return,
P_mode_V => P_mode_V);
p_uOut_U : component feedforward_p_uOut
generic map (
DataWidth => 64,
AddressRange => 140,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => p_uOut_address0,
ce0 => p_uOut_ce0,
we0 => p_uOut_we0,
d0 => p_uOut_d0,
q0 => p_uOut_q0,
address1 => p_uOut_address1,
ce1 => p_uOut_ce1,
q1 => p_uOut_q1);
feedforward_dadd_64ns_64ns_64_5_full_dsp_U0 : component feedforward_dadd_64ns_64ns_64_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_535_p0,
din1 => grp_fu_535_p1,
ce => grp_fu_535_ce,
dout => grp_fu_535_p2);
feedforward_dmul_64ns_64ns_64_6_max_dsp_U1 : component feedforward_dmul_64ns_64ns_64_6_max_dsp
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_578,
din1 => reg_585,
ce => grp_fu_543_ce,
dout => grp_fu_543_p2);
feedforward_ddiv_64ns_64ns_64_31_U2 : component feedforward_ddiv_64ns_64ns_64_31
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_547_p0,
din1 => grp_fu_547_p1,
ce => grp_fu_547_ce,
dout => grp_fu_547_p2);
feedforward_dcmp_64ns_64ns_1_1_U3 : component feedforward_dcmp_64ns_64ns_1_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 1)
port map (
din0 => reg_578,
din1 => p_uOut_load_4_reg_1686,
opcode => tmp_50_fu_553_opcode,
dout => tmp_50_fu_553_p2);
feedforward_dexp_64ns_64ns_64_18_full_dsp_U4 : component feedforward_dexp_64ns_64ns_64_18_full_dsp
generic map (
ID => 1,
NUM_STAGE => 18,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_0,
din1 => grp_fu_557_p1,
ce => grp_fu_557_ce,
dout => grp_fu_557_p2);
feedforward_mux_4to1_sel2_8_1_U5 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_24_reg_1498,
dout => tmp_14_fu_748_p6);
feedforward_mux_4to1_sel2_8_1_U6 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_31_reg_1508,
dout => tmp_20_fu_777_p6);
feedforward_mux_4to1_sel2_8_1_U7 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_39_reg_1525,
dout => tmp_17_fu_903_p6);
feedforward_mux_4to1_sel2_8_1_U8 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_42_reg_1535,
dout => tmp_22_fu_932_p6);
feedforward_mux_4to1_sel2_8_1_U9 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_40_fu_1225_p5,
dout => tmp_40_fu_1225_p6);
feedforward_mux_4to1_sel2_8_1_U10 : component feedforward_mux_4to1_sel2_8_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 8,
din2_WIDTH => 8,
din3_WIDTH => 8,
din4_WIDTH => 8,
din5_WIDTH => 2,
dout_WIDTH => 8)
port map (
din1 => ST_layerSize_V_0,
din2 => ST_layerSize_V_1,
din3 => ST_layerSize_V_2,
din4 => ST_layerSize_V_3,
din5 => tmp_2_fu_1317_p5,
dout => tmp_2_fu_1317_p6);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_P_netOut_V_TREADY assign process. --
ap_reg_ioackin_P_netOut_V_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_0;
else
if (ap_sig_bdd_909) then
if (not(((ap_const_lv1_0 = tmp_38_fu_1071_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY)))) then
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_netOut_V_TREADY)) then
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- ap_reg_ioackin_P_uOut_TREADY assign process. --
ap_reg_ioackin_P_uOut_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st162_fsm_161)) then
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = P_uOut_TREADY)) then
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- agg_result_V_reg_514 assign process. --
agg_result_V_reg_514_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st166_fsm_165) and not(ap_sig_bdd_725) and not((ap_const_lv1_0 = exitcond7_fu_1410_p2)))) then
agg_result_V_reg_514 <= ap_const_lv3_2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st163_fsm_162) and (ap_const_lv1_0 = tmp_8_fu_1264_p2))) then
agg_result_V_reg_514 <= ap_const_lv3_3;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st160_fsm_159) and not((ap_const_lv1_0 = exitcond6_fu_1210_p2)))) then
agg_result_V_reg_514 <= ap_const_lv3_4;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155) and (ap_const_lv1_0 = tmp_38_fu_1071_p2) and not(((ap_const_lv1_0 = tmp_38_fu_1071_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))))) then
agg_result_V_reg_514 <= ap_const_lv3_1;
end if;
end if;
end process;
-- i_1_reg_469 assign process. --
i_1_reg_469_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_620_p2 = ap_const_lv1_0) and not(ap_sig_bdd_414) and not((ap_const_lv1_0 = tmp_1_fu_630_p2)))) then
i_1_reg_469 <= ap_const_lv8_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st164_fsm_163) and not((ap_const_lv1_0 = exitcond2_fu_1341_p2)))) then
i_1_reg_469 <= i_9_fu_1379_p2;
end if;
end if;
end process;
-- i_2_reg_297 assign process. --
i_2_reg_297_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_620_p2 = ap_const_lv1_0) and not(ap_sig_bdd_414) and (ap_const_lv1_0 = tmp_1_fu_630_p2))) then
i_2_reg_297 <= ap_const_lv8_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_642_p2) and not(ap_sig_bdd_441))) then
i_2_reg_297 <= i_8_fu_647_p2;
end if;
end if;
end process;
-- i_3_reg_308 assign process. --
i_3_reg_308_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not(ap_sig_bdd_441) and not((ap_const_lv1_0 = exitcond1_fu_642_p2)))) then
i_3_reg_308 <= ap_const_lv8_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (ap_const_lv1_0 = tmp_16_fu_765_p2))) then
i_3_reg_308 <= i_10_fu_830_p2;
end if;
end if;
end process;
-- i_4_reg_366 assign process. --
i_4_reg_366_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_7_fu_658_p2))) then
i_4_reg_366 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_120)) then
i_4_reg_366 <= i_12_reg_1607;
end if;
end if;
end process;
-- i_5_reg_400 assign process. --
i_5_reg_400_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and (ap_const_lv1_0 = tmp_19_fu_920_p2))) then
i_5_reg_400 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st155_fsm_154)) then
i_5_reg_400 <= i_11_reg_1660;
end if;
end if;
end process;
-- i_6_reg_436 assign process. --
i_6_reg_436_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st161_fsm_160) and not((ap_const_lv1_0 = exitcond_fu_1239_p2)))) then
i_6_reg_436 <= i_14_reg_1720;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121) and not((ap_const_lv1_0 = exitcond5_fu_1041_p2)) and not((ap_const_lv1_0 = tmp_35_fu_1066_p2)))) then
i_6_reg_436 <= ap_const_lv8_0;
end if;
end if;
end process;
-- i_reg_503 assign process. --
i_reg_503_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st166_fsm_165) and (ap_const_lv1_0 = exitcond7_fu_1410_p2) and not(ap_sig_bdd_725))) then
i_reg_503 <= i_7_fu_1415_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_620_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_414))) then
i_reg_503 <= ap_const_lv8_0;
end if;
end if;
end process;
-- j_1_reg_320 assign process. --
j_1_reg_320_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not((ap_const_lv1_0 = tmp_7_fu_658_p2)))) then
j_1_reg_320 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) then
j_1_reg_320 <= j_5_reg_1543;
end if;
end if;
end process;
-- j_2_reg_389 assign process. --
j_2_reg_389_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and not((ap_const_lv1_0 = tmp_19_fu_920_p2)))) then
j_2_reg_389 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) then
j_2_reg_389 <= j_6_reg_1632;
end if;
end if;
end process;
-- j_3_reg_458 assign process. --
j_3_reg_458_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st160_fsm_159) and (ap_const_lv1_0 = exitcond6_fu_1210_p2))) then
j_3_reg_458 <= ap_const_lv8_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st162_fsm_161) and not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY)))) then
j_3_reg_458 <= j_7_reg_1733;
end if;
end if;
end process;
-- j_reg_481 assign process. --
j_reg_481_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164) and not(ap_sig_bdd_710) and not((ap_const_lv1_0 = exitcond8_fu_1399_p2)))) then
j_reg_481 <= j_4_reg_1764;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st163_fsm_162) and not((ap_const_lv1_0 = tmp_8_fu_1264_p2)))) then
j_reg_481 <= ap_const_lv8_0;
end if;
end if;
end process;
-- k_1_reg_343 assign process. --
k_1_reg_343_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((ap_const_lv1_0 = tmp_16_fu_765_p2)))) then
k_1_reg_343 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
k_1_reg_343 <= k_3_reg_1573;
end if;
end if;
end process;
-- k_reg_492 assign process. --
k_reg_492_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st164_fsm_163) and (ap_const_lv1_0 = exitcond2_fu_1341_p2))) then
k_reg_492 <= ap_const_lv9_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164) and (ap_const_lv1_0 = exitcond8_fu_1399_p2) and not(ap_sig_bdd_710))) then
k_reg_492 <= k_2_fu_1404_p2;
end if;
end if;
end process;
-- p_netOut_V_reg_424 assign process. --
p_netOut_V_reg_424_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121) and (ap_const_lv1_0 = tmp_35_fu_1066_p2) and not((ap_const_lv1_0 = exitcond5_fu_1041_p2)))) then
p_netOut_V_reg_424 <= ap_const_lv8_1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st159_fsm_158)) then
p_netOut_V_reg_424 <= i_15_fu_1194_p2;
end if;
end if;
end process;
-- p_s_reg_411 assign process. --
p_s_reg_411_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121) and (ap_const_lv1_0 = tmp_35_fu_1066_p2) and not((ap_const_lv1_0 = exitcond5_fu_1041_p2)))) then
p_s_reg_411 <= ap_const_lv8_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st159_fsm_158)) then
p_s_reg_411 <= p_netOut_V_1_fu_1187_p3;
end if;
end if;
end process;
-- phi_mul_reg_447 assign process. --
phi_mul_reg_447_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st161_fsm_160) and not((ap_const_lv1_0 = exitcond_fu_1239_p2)))) then
phi_mul_reg_447 <= next_mul_reg_1712;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121) and not((ap_const_lv1_0 = exitcond5_fu_1041_p2)) and not((ap_const_lv1_0 = tmp_35_fu_1066_p2)))) then
phi_mul_reg_447 <= ap_const_lv14_0;
end if;
end if;
end process;
-- sum_1_reg_377 assign process. --
sum_1_reg_377_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and not((ap_const_lv1_0 = tmp_19_fu_920_p2)))) then
sum_1_reg_377 <= ap_const_lv64_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) then
sum_1_reg_377 <= grp_fu_535_p2;
end if;
end if;
end process;
-- sum_reg_331 assign process. --
sum_reg_331_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((ap_const_lv1_0 = tmp_16_fu_765_p2)))) then
sum_reg_331 <= ap_const_lv64_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
sum_reg_331 <= grp_fu_535_p2;
end if;
end if;
end process;
-- sumsoft_reg_354 assign process. --
sumsoft_reg_354_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_7_fu_658_p2))) then
sumsoft_reg_354 <= ap_const_lv64_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_120)) then
sumsoft_reg_354 <= grp_fu_535_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_620_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_414))) then
P_config_V_read_reg_1477 <= P_config_V_TDATA;
ST_numLayer_V <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_414))) then
P_mode_V_read_reg_1453 <= P_mode_V;
ST_numLayer_V_load_reg_1461 <= ST_numLayer_V;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st166_fsm_165) and (ap_const_lv1_0 = exitcond7_fu_1410_p2) and not(ap_sig_bdd_725) and (tmp_3_fu_1421_p1 = ap_const_lv2_0))) then
ST_layerSize_V_0 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_fu_620_p2 = ap_const_lv1_0) and not(ap_sig_bdd_414) and (ap_const_lv1_0 = tmp_1_fu_630_p2))) then
ST_layerSize_V_0_load_reg_1472 <= ST_layerSize_V_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st166_fsm_165) and (ap_const_lv1_0 = exitcond7_fu_1410_p2) and not(ap_sig_bdd_725) and (tmp_3_fu_1421_p1 = ap_const_lv2_1))) then
ST_layerSize_V_1 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st166_fsm_165) and (ap_const_lv1_0 = exitcond7_fu_1410_p2) and not(ap_sig_bdd_725) and (tmp_3_fu_1421_p1 = ap_const_lv2_2))) then
ST_layerSize_V_2 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st166_fsm_165) and (ap_const_lv1_0 = exitcond7_fu_1410_p2) and not(ap_sig_bdd_725) and not((tmp_3_fu_1421_p1 = ap_const_lv2_2)) and not((tmp_3_fu_1421_p1 = ap_const_lv2_1)) and not((tmp_3_fu_1421_p1 = ap_const_lv2_0)))) then
ST_layerSize_V_3 <= P_config_V_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st163_fsm_162) and not((ap_const_lv1_0 = tmp_8_fu_1264_p2)))) then
ST_layerSize_V_load_1_phi_reg_1751 <= ST_layerSize_V_load_1_phi_fu_1303_p3;
tmp_10_reg_1756 <= tmp_10_fu_1335_p2;
tmp_s_reg_1746 <= tmp_s_fu_1273_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121)) then
i_11_reg_1660 <= i_11_fu_1046_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
i_12_reg_1607 <= i_12_fu_926_p2;
tmp_17_reg_1598 <= tmp_17_fu_903_p6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st160_fsm_159)) then
i_14_reg_1720 <= i_14_fu_1215_p2;
next_mul_reg_1712 <= next_mul_fu_1204_p2;
tmp_66_reg_1707 <= tmp_66_fu_1200_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st164_fsm_163)) then
j_4_reg_1764 <= j_4_fu_1346_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
j_5_reg_1543 <= j_5_fu_771_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) then
j_6_reg_1632 <= j_6_fu_994_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st161_fsm_160)) then
j_7_reg_1733 <= j_7_fu_1244_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
k_3_reg_1573 <= k_3_fu_841_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((ap_const_lv1_0 = tmp_16_fu_765_p2)))) then
p_uOut_addr_1_reg_1560 <= tmp_64_cast_fu_795_p1(8 - 1 downto 0);
tmp_20_reg_1548 <= tmp_20_fu_777_p6;
tmp_54_reg_1554(13 downto 2) <= tmp_54_fu_824_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) and not((ap_const_lv1_0 = tmp_19_fu_920_p2)))) then
p_uOut_addr_3_reg_1624 <= tmp_68_cast_fu_954_p1(8 - 1 downto 0);
tmp_22_reg_1612 <= tmp_22_fu_932_p6;
tmp_58_reg_1618(13 downto 2) <= tmp_58_fu_983_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121) and (ap_const_lv1_0 = exitcond5_fu_1041_p2))) then
p_uOut_addr_5_reg_1665 <= tmp_78_cast_fu_1061_p1(8 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st157_fsm_156)) then
p_uOut_load_4_reg_1686 <= p_uOut_q1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80) or (ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122) or (ap_const_logic_1 = ap_sig_cseq_ST_st157_fsm_156))) then
reg_578 <= p_uOut_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92))) then
reg_585 <= ST_WandB_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86))) then
reg_591 <= grp_fu_543_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22) or (ap_const_logic_1 = ap_sig_cseq_ST_st46_fsm_45) or (ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97))) then
reg_602 <= grp_fu_535_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st41_fsm_40) or (ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_115))) then
reg_608 <= grp_fu_557_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76) or (ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153))) then
reg_615 <= grp_fu_547_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st164_fsm_163) and (ap_const_lv1_0 = exitcond2_fu_1341_p2))) then
tmp_21_reg_1769(13 downto 2) <= tmp_21_fu_1373_p2(13 downto 2);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not((ap_const_lv1_0 = tmp_7_fu_658_p2)))) then
tmp_24_reg_1498 <= tmp_24_fu_677_p1;
tmp_29_reg_1503 <= tmp_29_fu_691_p2;
tmp_31_reg_1508 <= tmp_31_fu_697_p1;
tmp_59_cast_reg_1493(14 downto 0) <= tmp_59_cast_fu_673_p1(14 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_lv1_0 = tmp_7_fu_658_p2))) then
tmp_36_reg_1513 <= tmp_36_fu_720_p1;
tmp_39_reg_1525 <= tmp_39_fu_728_p1;
tmp_41_reg_1530 <= tmp_41_fu_738_p2;
tmp_42_reg_1535 <= tmp_42_fu_744_p1;
tmp_61_cast_reg_1520 <= tmp_61_cast_fu_724_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st160_fsm_159) and (ap_const_lv1_0 = exitcond6_fu_1210_p2))) then
tmp_40_reg_1725 <= tmp_40_fu_1225_p6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st158_fsm_157)) then
tmp_51_reg_1692 <= tmp_51_fu_1181_p2;
end if;
end if;
end process;
tmp_59_cast_reg_1493(31 downto 15) <= "00000000000000000";
tmp_54_reg_1554(1 downto 0) <= "00";
tmp_58_reg_1618(1 downto 0) <= "00";
tmp_21_reg_1769(1 downto 0) <= "00";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, tmp_fu_620_p2, ap_sig_bdd_414, tmp_1_fu_630_p2, exitcond1_fu_642_p2, ap_sig_bdd_441, tmp_7_fu_658_p2, tmp_16_fu_765_p2, exitcond3_fu_836_p2, tmp_19_fu_920_p2, exitcond4_fu_989_p2, exitcond5_fu_1041_p2, tmp_38_fu_1071_p2, ap_sig_ioackin_P_netOut_V_TREADY, exitcond6_fu_1210_p2, exitcond_fu_1239_p2, tmp_8_fu_1264_p2, exitcond2_fu_1341_p2, exitcond8_fu_1399_p2, ap_sig_bdd_710, exitcond7_fu_1410_p2, ap_sig_bdd_725, tmp_35_fu_1066_p2, ap_sig_ioackin_P_uOut_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if ((not((tmp_fu_620_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_414))) then
ap_NS_fsm <= ap_ST_st166_fsm_165;
elsif (((tmp_fu_620_p2 = ap_const_lv1_0) and not(ap_sig_bdd_414) and (ap_const_lv1_0 = tmp_1_fu_630_p2))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif (((tmp_fu_620_p2 = ap_const_lv1_0) and not(ap_sig_bdd_414) and not((ap_const_lv1_0 = tmp_1_fu_630_p2)))) then
ap_NS_fsm <= ap_ST_st163_fsm_162;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (((ap_const_lv1_0 = exitcond1_fu_642_p2) and not(ap_sig_bdd_441))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif ((not(ap_sig_bdd_441) and not((ap_const_lv1_0 = exitcond1_fu_642_p2)))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if ((ap_const_lv1_0 = tmp_7_fu_658_p2)) then
ap_NS_fsm <= ap_ST_st79_fsm_78;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st4_fsm_3 =>
if ((ap_const_lv1_0 = tmp_16_fu_765_p2)) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st5_fsm_4 =>
if (not((ap_const_lv1_0 = exitcond3_fu_836_p2))) then
ap_NS_fsm <= ap_ST_st18_fsm_17;
else
ap_NS_fsm <= ap_ST_st6_fsm_5;
end if;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
ap_NS_fsm <= ap_ST_st46_fsm_45;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
ap_NS_fsm <= ap_ST_st50_fsm_49;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st52_fsm_51;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st54_fsm_53;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st55_fsm_54;
when ap_ST_st55_fsm_54 =>
ap_NS_fsm <= ap_ST_st56_fsm_55;
when ap_ST_st56_fsm_55 =>
ap_NS_fsm <= ap_ST_st57_fsm_56;
when ap_ST_st57_fsm_56 =>
ap_NS_fsm <= ap_ST_st58_fsm_57;
when ap_ST_st58_fsm_57 =>
ap_NS_fsm <= ap_ST_st59_fsm_58;
when ap_ST_st59_fsm_58 =>
ap_NS_fsm <= ap_ST_st60_fsm_59;
when ap_ST_st60_fsm_59 =>
ap_NS_fsm <= ap_ST_st61_fsm_60;
when ap_ST_st61_fsm_60 =>
ap_NS_fsm <= ap_ST_st62_fsm_61;
when ap_ST_st62_fsm_61 =>
ap_NS_fsm <= ap_ST_st63_fsm_62;
when ap_ST_st63_fsm_62 =>
ap_NS_fsm <= ap_ST_st64_fsm_63;
when ap_ST_st64_fsm_63 =>
ap_NS_fsm <= ap_ST_st65_fsm_64;
when ap_ST_st65_fsm_64 =>
ap_NS_fsm <= ap_ST_st66_fsm_65;
when ap_ST_st66_fsm_65 =>
ap_NS_fsm <= ap_ST_st67_fsm_66;
when ap_ST_st67_fsm_66 =>
ap_NS_fsm <= ap_ST_st68_fsm_67;
when ap_ST_st68_fsm_67 =>
ap_NS_fsm <= ap_ST_st69_fsm_68;
when ap_ST_st69_fsm_68 =>
ap_NS_fsm <= ap_ST_st70_fsm_69;
when ap_ST_st70_fsm_69 =>
ap_NS_fsm <= ap_ST_st71_fsm_70;
when ap_ST_st71_fsm_70 =>
ap_NS_fsm <= ap_ST_st72_fsm_71;
when ap_ST_st72_fsm_71 =>
ap_NS_fsm <= ap_ST_st73_fsm_72;
when ap_ST_st73_fsm_72 =>
ap_NS_fsm <= ap_ST_st74_fsm_73;
when ap_ST_st74_fsm_73 =>
ap_NS_fsm <= ap_ST_st75_fsm_74;
when ap_ST_st75_fsm_74 =>
ap_NS_fsm <= ap_ST_st76_fsm_75;
when ap_ST_st76_fsm_75 =>
ap_NS_fsm <= ap_ST_st77_fsm_76;
when ap_ST_st77_fsm_76 =>
ap_NS_fsm <= ap_ST_st78_fsm_77;
when ap_ST_st78_fsm_77 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st79_fsm_78 =>
if (not((ap_const_lv1_0 = tmp_19_fu_920_p2))) then
ap_NS_fsm <= ap_ST_st80_fsm_79;
else
ap_NS_fsm <= ap_ST_st122_fsm_121;
end if;
when ap_ST_st80_fsm_79 =>
if (not((ap_const_lv1_0 = exitcond4_fu_989_p2))) then
ap_NS_fsm <= ap_ST_st93_fsm_92;
else
ap_NS_fsm <= ap_ST_st81_fsm_80;
end if;
when ap_ST_st81_fsm_80 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st82_fsm_81 =>
ap_NS_fsm <= ap_ST_st83_fsm_82;
when ap_ST_st83_fsm_82 =>
ap_NS_fsm <= ap_ST_st84_fsm_83;
when ap_ST_st84_fsm_83 =>
ap_NS_fsm <= ap_ST_st85_fsm_84;
when ap_ST_st85_fsm_84 =>
ap_NS_fsm <= ap_ST_st86_fsm_85;
when ap_ST_st86_fsm_85 =>
ap_NS_fsm <= ap_ST_st87_fsm_86;
when ap_ST_st87_fsm_86 =>
ap_NS_fsm <= ap_ST_st88_fsm_87;
when ap_ST_st88_fsm_87 =>
ap_NS_fsm <= ap_ST_st89_fsm_88;
when ap_ST_st89_fsm_88 =>
ap_NS_fsm <= ap_ST_st90_fsm_89;
when ap_ST_st90_fsm_89 =>
ap_NS_fsm <= ap_ST_st91_fsm_90;
when ap_ST_st91_fsm_90 =>
ap_NS_fsm <= ap_ST_st92_fsm_91;
when ap_ST_st92_fsm_91 =>
ap_NS_fsm <= ap_ST_st80_fsm_79;
when ap_ST_st93_fsm_92 =>
ap_NS_fsm <= ap_ST_st94_fsm_93;
when ap_ST_st94_fsm_93 =>
ap_NS_fsm <= ap_ST_st95_fsm_94;
when ap_ST_st95_fsm_94 =>
ap_NS_fsm <= ap_ST_st96_fsm_95;
when ap_ST_st96_fsm_95 =>
ap_NS_fsm <= ap_ST_st97_fsm_96;
when ap_ST_st97_fsm_96 =>
ap_NS_fsm <= ap_ST_st98_fsm_97;
when ap_ST_st98_fsm_97 =>
ap_NS_fsm <= ap_ST_st99_fsm_98;
when ap_ST_st99_fsm_98 =>
ap_NS_fsm <= ap_ST_st100_fsm_99;
when ap_ST_st100_fsm_99 =>
ap_NS_fsm <= ap_ST_st101_fsm_100;
when ap_ST_st101_fsm_100 =>
ap_NS_fsm <= ap_ST_st102_fsm_101;
when ap_ST_st102_fsm_101 =>
ap_NS_fsm <= ap_ST_st103_fsm_102;
when ap_ST_st103_fsm_102 =>
ap_NS_fsm <= ap_ST_st104_fsm_103;
when ap_ST_st104_fsm_103 =>
ap_NS_fsm <= ap_ST_st105_fsm_104;
when ap_ST_st105_fsm_104 =>
ap_NS_fsm <= ap_ST_st106_fsm_105;
when ap_ST_st106_fsm_105 =>
ap_NS_fsm <= ap_ST_st107_fsm_106;
when ap_ST_st107_fsm_106 =>
ap_NS_fsm <= ap_ST_st108_fsm_107;
when ap_ST_st108_fsm_107 =>
ap_NS_fsm <= ap_ST_st109_fsm_108;
when ap_ST_st109_fsm_108 =>
ap_NS_fsm <= ap_ST_st110_fsm_109;
when ap_ST_st110_fsm_109 =>
ap_NS_fsm <= ap_ST_st111_fsm_110;
when ap_ST_st111_fsm_110 =>
ap_NS_fsm <= ap_ST_st112_fsm_111;
when ap_ST_st112_fsm_111 =>
ap_NS_fsm <= ap_ST_st113_fsm_112;
when ap_ST_st113_fsm_112 =>
ap_NS_fsm <= ap_ST_st114_fsm_113;
when ap_ST_st114_fsm_113 =>
ap_NS_fsm <= ap_ST_st115_fsm_114;
when ap_ST_st115_fsm_114 =>
ap_NS_fsm <= ap_ST_st116_fsm_115;
when ap_ST_st116_fsm_115 =>
ap_NS_fsm <= ap_ST_st117_fsm_116;
when ap_ST_st117_fsm_116 =>
ap_NS_fsm <= ap_ST_st118_fsm_117;
when ap_ST_st118_fsm_117 =>
ap_NS_fsm <= ap_ST_st119_fsm_118;
when ap_ST_st119_fsm_118 =>
ap_NS_fsm <= ap_ST_st120_fsm_119;
when ap_ST_st120_fsm_119 =>
ap_NS_fsm <= ap_ST_st121_fsm_120;
when ap_ST_st121_fsm_120 =>
ap_NS_fsm <= ap_ST_st79_fsm_78;
when ap_ST_st122_fsm_121 =>
if ((not((ap_const_lv1_0 = exitcond5_fu_1041_p2)) and not((ap_const_lv1_0 = tmp_35_fu_1066_p2)))) then
ap_NS_fsm <= ap_ST_st160_fsm_159;
elsif (((ap_const_lv1_0 = tmp_35_fu_1066_p2) and not((ap_const_lv1_0 = exitcond5_fu_1041_p2)))) then
ap_NS_fsm <= ap_ST_st156_fsm_155;
else
ap_NS_fsm <= ap_ST_st123_fsm_122;
end if;
when ap_ST_st123_fsm_122 =>
ap_NS_fsm <= ap_ST_st124_fsm_123;
when ap_ST_st124_fsm_123 =>
ap_NS_fsm <= ap_ST_st125_fsm_124;
when ap_ST_st125_fsm_124 =>
ap_NS_fsm <= ap_ST_st126_fsm_125;
when ap_ST_st126_fsm_125 =>
ap_NS_fsm <= ap_ST_st127_fsm_126;
when ap_ST_st127_fsm_126 =>
ap_NS_fsm <= ap_ST_st128_fsm_127;
when ap_ST_st128_fsm_127 =>
ap_NS_fsm <= ap_ST_st129_fsm_128;
when ap_ST_st129_fsm_128 =>
ap_NS_fsm <= ap_ST_st130_fsm_129;
when ap_ST_st130_fsm_129 =>
ap_NS_fsm <= ap_ST_st131_fsm_130;
when ap_ST_st131_fsm_130 =>
ap_NS_fsm <= ap_ST_st132_fsm_131;
when ap_ST_st132_fsm_131 =>
ap_NS_fsm <= ap_ST_st133_fsm_132;
when ap_ST_st133_fsm_132 =>
ap_NS_fsm <= ap_ST_st134_fsm_133;
when ap_ST_st134_fsm_133 =>
ap_NS_fsm <= ap_ST_st135_fsm_134;
when ap_ST_st135_fsm_134 =>
ap_NS_fsm <= ap_ST_st136_fsm_135;
when ap_ST_st136_fsm_135 =>
ap_NS_fsm <= ap_ST_st137_fsm_136;
when ap_ST_st137_fsm_136 =>
ap_NS_fsm <= ap_ST_st138_fsm_137;
when ap_ST_st138_fsm_137 =>
ap_NS_fsm <= ap_ST_st139_fsm_138;
when ap_ST_st139_fsm_138 =>
ap_NS_fsm <= ap_ST_st140_fsm_139;
when ap_ST_st140_fsm_139 =>
ap_NS_fsm <= ap_ST_st141_fsm_140;
when ap_ST_st141_fsm_140 =>
ap_NS_fsm <= ap_ST_st142_fsm_141;
when ap_ST_st142_fsm_141 =>
ap_NS_fsm <= ap_ST_st143_fsm_142;
when ap_ST_st143_fsm_142 =>
ap_NS_fsm <= ap_ST_st144_fsm_143;
when ap_ST_st144_fsm_143 =>
ap_NS_fsm <= ap_ST_st145_fsm_144;
when ap_ST_st145_fsm_144 =>
ap_NS_fsm <= ap_ST_st146_fsm_145;
when ap_ST_st146_fsm_145 =>
ap_NS_fsm <= ap_ST_st147_fsm_146;
when ap_ST_st147_fsm_146 =>
ap_NS_fsm <= ap_ST_st148_fsm_147;
when ap_ST_st148_fsm_147 =>
ap_NS_fsm <= ap_ST_st149_fsm_148;
when ap_ST_st149_fsm_148 =>
ap_NS_fsm <= ap_ST_st150_fsm_149;
when ap_ST_st150_fsm_149 =>
ap_NS_fsm <= ap_ST_st151_fsm_150;
when ap_ST_st151_fsm_150 =>
ap_NS_fsm <= ap_ST_st152_fsm_151;
when ap_ST_st152_fsm_151 =>
ap_NS_fsm <= ap_ST_st153_fsm_152;
when ap_ST_st153_fsm_152 =>
ap_NS_fsm <= ap_ST_st154_fsm_153;
when ap_ST_st154_fsm_153 =>
ap_NS_fsm <= ap_ST_st155_fsm_154;
when ap_ST_st155_fsm_154 =>
ap_NS_fsm <= ap_ST_st122_fsm_121;
when ap_ST_st156_fsm_155 =>
if (((ap_const_lv1_0 = tmp_38_fu_1071_p2) and not(((ap_const_lv1_0 = tmp_38_fu_1071_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))))) then
ap_NS_fsm <= ap_ST_st167_fsm_166;
elsif ((not(((ap_const_lv1_0 = tmp_38_fu_1071_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY))) and not((ap_const_lv1_0 = tmp_38_fu_1071_p2)))) then
ap_NS_fsm <= ap_ST_st157_fsm_156;
else
ap_NS_fsm <= ap_ST_st156_fsm_155;
end if;
when ap_ST_st157_fsm_156 =>
ap_NS_fsm <= ap_ST_st158_fsm_157;
when ap_ST_st158_fsm_157 =>
ap_NS_fsm <= ap_ST_st159_fsm_158;
when ap_ST_st159_fsm_158 =>
ap_NS_fsm <= ap_ST_st156_fsm_155;
when ap_ST_st160_fsm_159 =>
if ((ap_const_lv1_0 = exitcond6_fu_1210_p2)) then
ap_NS_fsm <= ap_ST_st161_fsm_160;
else
ap_NS_fsm <= ap_ST_st167_fsm_166;
end if;
when ap_ST_st161_fsm_160 =>
if ((ap_const_lv1_0 = exitcond_fu_1239_p2)) then
ap_NS_fsm <= ap_ST_st162_fsm_161;
else
ap_NS_fsm <= ap_ST_st160_fsm_159;
end if;
when ap_ST_st162_fsm_161 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_P_uOut_TREADY))) then
ap_NS_fsm <= ap_ST_st161_fsm_160;
else
ap_NS_fsm <= ap_ST_st162_fsm_161;
end if;
when ap_ST_st163_fsm_162 =>
if (not((ap_const_lv1_0 = tmp_8_fu_1264_p2))) then
ap_NS_fsm <= ap_ST_st164_fsm_163;
else
ap_NS_fsm <= ap_ST_st167_fsm_166;
end if;
when ap_ST_st164_fsm_163 =>
if (not((ap_const_lv1_0 = exitcond2_fu_1341_p2))) then
ap_NS_fsm <= ap_ST_st163_fsm_162;
else
ap_NS_fsm <= ap_ST_st165_fsm_164;
end if;
when ap_ST_st165_fsm_164 =>
if (((ap_const_lv1_0 = exitcond8_fu_1399_p2) and not(ap_sig_bdd_710))) then
ap_NS_fsm <= ap_ST_st165_fsm_164;
elsif ((not(ap_sig_bdd_710) and not((ap_const_lv1_0 = exitcond8_fu_1399_p2)))) then
ap_NS_fsm <= ap_ST_st164_fsm_163;
else
ap_NS_fsm <= ap_ST_st165_fsm_164;
end if;
when ap_ST_st166_fsm_165 =>
if (((ap_const_lv1_0 = exitcond7_fu_1410_p2) and not(ap_sig_bdd_725))) then
ap_NS_fsm <= ap_ST_st166_fsm_165;
elsif ((not(ap_sig_bdd_725) and not((ap_const_lv1_0 = exitcond7_fu_1410_p2)))) then
ap_NS_fsm <= ap_ST_st167_fsm_166;
else
ap_NS_fsm <= ap_ST_st166_fsm_165;
end if;
when ap_ST_st167_fsm_166 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- P_WandB_TREADY assign process. --
P_WandB_TREADY_assign_proc : process(ap_sig_cseq_ST_st165_fsm_164, exitcond8_fu_1399_p2, ap_sig_bdd_710)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164) and (ap_const_lv1_0 = exitcond8_fu_1399_p2) and not(ap_sig_bdd_710))) then
P_WandB_TREADY <= ap_const_logic_1;
else
P_WandB_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_config_V_TREADY assign process. --
P_config_V_TREADY_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, tmp_fu_620_p2, ap_sig_bdd_414, ap_sig_cseq_ST_st166_fsm_165, exitcond7_fu_1410_p2, ap_sig_bdd_725)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((tmp_fu_620_p2 = ap_const_lv1_0)) and not(ap_sig_bdd_414)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st166_fsm_165) and (ap_const_lv1_0 = exitcond7_fu_1410_p2) and not(ap_sig_bdd_725)))) then
P_config_V_TREADY <= ap_const_logic_1;
else
P_config_V_TREADY <= ap_const_logic_0;
end if;
end process;
-- P_netIn_TREADY assign process. --
P_netIn_TREADY_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_642_p2, ap_sig_bdd_441)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_642_p2) and not(ap_sig_bdd_441))) then
P_netIn_TREADY <= ap_const_logic_1;
else
P_netIn_TREADY <= ap_const_logic_0;
end if;
end process;
P_netOut_V_TDATA <= p_s_reg_411;
-- P_netOut_V_TVALID assign process. --
P_netOut_V_TVALID_assign_proc : process(ap_sig_cseq_ST_st156_fsm_155, tmp_38_fu_1071_p2, ap_reg_ioackin_P_netOut_V_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155) and (ap_const_lv1_0 = tmp_38_fu_1071_p2) and (ap_const_logic_0 = ap_reg_ioackin_P_netOut_V_TREADY))) then
P_netOut_V_TVALID <= ap_const_logic_1;
else
P_netOut_V_TVALID <= ap_const_logic_0;
end if;
end process;
P_uOut_TDATA <= p_uOut_q1;
-- P_uOut_TVALID assign process. --
P_uOut_TVALID_assign_proc : process(ap_sig_cseq_ST_st162_fsm_161, ap_reg_ioackin_P_uOut_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st162_fsm_161) and (ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY))) then
P_uOut_TVALID <= ap_const_logic_1;
else
P_uOut_TVALID <= ap_const_logic_0;
end if;
end process;
-- ST_WandB_address0 assign process. --
ST_WandB_address0_assign_proc : process(ap_sig_cseq_ST_st5_fsm_4, exitcond3_fu_836_p2, ap_sig_cseq_ST_st80_fsm_79, exitcond4_fu_989_p2, ap_sig_cseq_ST_st165_fsm_164, tmp_73_cast_fu_860_p1, tmp_72_cast_fu_883_p1, tmp_76_cast_fu_1013_p1, tmp_75_cast_fu_1036_p1, tmp_63_cast_fu_1394_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164)) then
ST_WandB_address0 <= tmp_63_cast_fu_1394_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) and not((ap_const_lv1_0 = exitcond4_fu_989_p2)))) then
ST_WandB_address0 <= tmp_75_cast_fu_1036_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) and (ap_const_lv1_0 = exitcond4_fu_989_p2))) then
ST_WandB_address0 <= tmp_76_cast_fu_1013_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and not((ap_const_lv1_0 = exitcond3_fu_836_p2)))) then
ST_WandB_address0 <= tmp_72_cast_fu_883_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (ap_const_lv1_0 = exitcond3_fu_836_p2))) then
ST_WandB_address0 <= tmp_73_cast_fu_860_p1(13 - 1 downto 0);
else
ST_WandB_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
-- ST_WandB_ce0 assign process. --
ST_WandB_ce0_assign_proc : process(ap_sig_cseq_ST_st5_fsm_4, exitcond3_fu_836_p2, ap_sig_cseq_ST_st80_fsm_79, exitcond4_fu_989_p2, ap_sig_cseq_ST_st165_fsm_164, ap_sig_bdd_710)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (ap_const_lv1_0 = exitcond3_fu_836_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and not((ap_const_lv1_0 = exitcond3_fu_836_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) and (ap_const_lv1_0 = exitcond4_fu_989_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) and not((ap_const_lv1_0 = exitcond4_fu_989_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164) and not(ap_sig_bdd_710)))) then
ST_WandB_ce0 <= ap_const_logic_1;
else
ST_WandB_ce0 <= ap_const_logic_0;
end if;
end process;
ST_WandB_d0 <= P_WandB_TDATA;
-- ST_WandB_we0 assign process. --
ST_WandB_we0_assign_proc : process(ap_sig_cseq_ST_st165_fsm_164, exitcond8_fu_1399_p2, ap_sig_bdd_710)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164) and (ap_const_lv1_0 = exitcond8_fu_1399_p2) and not(ap_sig_bdd_710)))) then
ST_WandB_we0 <= ap_const_logic_1;
else
ST_WandB_we0 <= ap_const_logic_0;
end if;
end process;
ST_layerSize_V_load_1_phi_fu_1303_p3 <=
ST_layerSize_V_2 when (sel_tmp2_fu_1297_p2(0) = '1') else
sel_tmp1_fu_1289_p3;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_sig_cseq_ST_st167_fsm_166)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st167_fsm_166)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st167_fsm_166)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st167_fsm_166)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= std_logic_vector(resize(unsigned(agg_result_V_reg_514),8));
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_1012 assign process. --
ap_sig_bdd_1012_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1012 <= (ap_const_lv1_1 = ap_CS_fsm(46 downto 46));
end process;
-- ap_sig_bdd_1019 assign process. --
ap_sig_bdd_1019_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1019 <= (ap_const_lv1_1 = ap_CS_fsm(123 downto 123));
end process;
-- ap_sig_bdd_1029 assign process. --
ap_sig_bdd_1029_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1029 <= (ap_const_lv1_1 = ap_CS_fsm(98 downto 98));
end process;
-- ap_sig_bdd_1384 assign process. --
ap_sig_bdd_1384_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1384 <= (ap_const_lv1_1 = ap_CS_fsm(166 downto 166));
end process;
-- ap_sig_bdd_185 assign process. --
ap_sig_bdd_185_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_185 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_268 assign process. --
ap_sig_bdd_268_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_268 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_275 assign process. --
ap_sig_bdd_275_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_275 <= (ap_const_lv1_1 = ap_CS_fsm(80 downto 80));
end process;
-- ap_sig_bdd_283 assign process. --
ap_sig_bdd_283_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_283 <= (ap_const_lv1_1 = ap_CS_fsm(122 downto 122));
end process;
-- ap_sig_bdd_291 assign process. --
ap_sig_bdd_291_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_291 <= (ap_const_lv1_1 = ap_CS_fsm(156 downto 156));
end process;
-- ap_sig_bdd_300 assign process. --
ap_sig_bdd_300_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_300 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_309 assign process. --
ap_sig_bdd_309_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_309 <= (ap_const_lv1_1 = ap_CS_fsm(92 downto 92));
end process;
-- ap_sig_bdd_319 assign process. --
ap_sig_bdd_319_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_319 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_326 assign process. --
ap_sig_bdd_326_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_326 <= (ap_const_lv1_1 = ap_CS_fsm(86 downto 86));
end process;
-- ap_sig_bdd_336 assign process. --
ap_sig_bdd_336_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_336 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_343 assign process. --
ap_sig_bdd_343_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_343 <= (ap_const_lv1_1 = ap_CS_fsm(91 downto 91));
end process;
-- ap_sig_bdd_352 assign process. --
ap_sig_bdd_352_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_352 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_359 assign process. --
ap_sig_bdd_359_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_359 <= (ap_const_lv1_1 = ap_CS_fsm(45 downto 45));
end process;
-- ap_sig_bdd_367 assign process. --
ap_sig_bdd_367_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_367 <= (ap_const_lv1_1 = ap_CS_fsm(97 downto 97));
end process;
-- ap_sig_bdd_377 assign process. --
ap_sig_bdd_377_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_377 <= (ap_const_lv1_1 = ap_CS_fsm(40 downto 40));
end process;
-- ap_sig_bdd_384 assign process. --
ap_sig_bdd_384_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_384 <= (ap_const_lv1_1 = ap_CS_fsm(115 downto 115));
end process;
-- ap_sig_bdd_394 assign process. --
ap_sig_bdd_394_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_394 <= (ap_const_lv1_1 = ap_CS_fsm(76 downto 76));
end process;
-- ap_sig_bdd_401 assign process. --
ap_sig_bdd_401_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_401 <= (ap_const_lv1_1 = ap_CS_fsm(153 downto 153));
end process;
-- ap_sig_bdd_414 assign process. --
ap_sig_bdd_414_assign_proc : process(ap_start, P_config_V_TVALID, tmp_fu_620_p2)
begin
ap_sig_bdd_414 <= (((P_config_V_TVALID = ap_const_logic_0) and not((tmp_fu_620_p2 = ap_const_lv1_0))) or (ap_start = ap_const_logic_0));
end process;
-- ap_sig_bdd_435 assign process. --
ap_sig_bdd_435_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_435 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_441 assign process. --
ap_sig_bdd_441_assign_proc : process(P_netIn_TVALID, exitcond1_fu_642_p2)
begin
ap_sig_bdd_441 <= ((P_netIn_TVALID = ap_const_logic_0) and (ap_const_lv1_0 = exitcond1_fu_642_p2));
end process;
-- ap_sig_bdd_451 assign process. --
ap_sig_bdd_451_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_451 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_481 assign process. --
ap_sig_bdd_481_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_481 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_503 assign process. --
ap_sig_bdd_503_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_503 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_523 assign process. --
ap_sig_bdd_523_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_523 <= (ap_const_lv1_1 = ap_CS_fsm(23 downto 23));
end process;
-- ap_sig_bdd_532 assign process. --
ap_sig_bdd_532_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_532 <= (ap_const_lv1_1 = ap_CS_fsm(78 downto 78));
end process;
-- ap_sig_bdd_553 assign process. --
ap_sig_bdd_553_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_553 <= (ap_const_lv1_1 = ap_CS_fsm(79 downto 79));
end process;
-- ap_sig_bdd_572 assign process. --
ap_sig_bdd_572_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_572 <= (ap_const_lv1_1 = ap_CS_fsm(120 downto 120));
end process;
-- ap_sig_bdd_581 assign process. --
ap_sig_bdd_581_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_581 <= (ap_const_lv1_1 = ap_CS_fsm(121 downto 121));
end process;
-- ap_sig_bdd_595 assign process. --
ap_sig_bdd_595_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_595 <= (ap_const_lv1_1 = ap_CS_fsm(155 downto 155));
end process;
-- ap_sig_bdd_617 assign process. --
ap_sig_bdd_617_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_617 <= (ap_const_lv1_1 = ap_CS_fsm(157 downto 157));
end process;
-- ap_sig_bdd_626 assign process. --
ap_sig_bdd_626_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_626 <= (ap_const_lv1_1 = ap_CS_fsm(158 downto 158));
end process;
-- ap_sig_bdd_637 assign process. --
ap_sig_bdd_637_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_637 <= (ap_const_lv1_1 = ap_CS_fsm(159 downto 159));
end process;
-- ap_sig_bdd_655 assign process. --
ap_sig_bdd_655_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_655 <= (ap_const_lv1_1 = ap_CS_fsm(160 downto 160));
end process;
-- ap_sig_bdd_669 assign process. --
ap_sig_bdd_669_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_669 <= (ap_const_lv1_1 = ap_CS_fsm(162 downto 162));
end process;
-- ap_sig_bdd_686 assign process. --
ap_sig_bdd_686_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_686 <= (ap_const_lv1_1 = ap_CS_fsm(163 downto 163));
end process;
-- ap_sig_bdd_704 assign process. --
ap_sig_bdd_704_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_704 <= (ap_const_lv1_1 = ap_CS_fsm(164 downto 164));
end process;
-- ap_sig_bdd_710 assign process. --
ap_sig_bdd_710_assign_proc : process(P_WandB_TVALID, exitcond8_fu_1399_p2)
begin
ap_sig_bdd_710 <= ((P_WandB_TVALID = ap_const_logic_0) and (ap_const_lv1_0 = exitcond8_fu_1399_p2));
end process;
-- ap_sig_bdd_720 assign process. --
ap_sig_bdd_720_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_720 <= (ap_const_lv1_1 = ap_CS_fsm(165 downto 165));
end process;
-- ap_sig_bdd_725 assign process. --
ap_sig_bdd_725_assign_proc : process(P_config_V_TVALID, exitcond7_fu_1410_p2)
begin
ap_sig_bdd_725 <= ((P_config_V_TVALID = ap_const_logic_0) and (ap_const_lv1_0 = exitcond7_fu_1410_p2));
end process;
-- ap_sig_bdd_754 assign process. --
ap_sig_bdd_754_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_754 <= (ap_const_lv1_1 = ap_CS_fsm(77 downto 77));
end process;
-- ap_sig_bdd_776 assign process. --
ap_sig_bdd_776_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_776 <= (ap_const_lv1_1 = ap_CS_fsm(154 downto 154));
end process;
-- ap_sig_bdd_805 assign process. --
ap_sig_bdd_805_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_805 <= (ap_const_lv1_1 = ap_CS_fsm(161 downto 161));
end process;
-- ap_sig_bdd_909 assign process. --
ap_sig_bdd_909_assign_proc : process(ap_sig_cseq_ST_st156_fsm_155, tmp_38_fu_1071_p2)
begin
ap_sig_bdd_909 <= ((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155) and (ap_const_lv1_0 = tmp_38_fu_1071_p2));
end process;
-- ap_sig_bdd_929 assign process. --
ap_sig_bdd_929_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_929 <= (ap_const_lv1_1 = ap_CS_fsm(116 downto 116));
end process;
-- ap_sig_bdd_954 assign process. --
ap_sig_bdd_954_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_954 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_961 assign process. --
ap_sig_bdd_961_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_961 <= (ap_const_lv1_1 = ap_CS_fsm(18 downto 18));
end process;
-- ap_sig_bdd_969 assign process. --
ap_sig_bdd_969_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_969 <= (ap_const_lv1_1 = ap_CS_fsm(41 downto 41));
end process;
-- ap_sig_bdd_976 assign process. --
ap_sig_bdd_976_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_976 <= (ap_const_lv1_1 = ap_CS_fsm(87 downto 87));
end process;
-- ap_sig_bdd_983 assign process. --
ap_sig_bdd_983_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_983 <= (ap_const_lv1_1 = ap_CS_fsm(93 downto 93));
end process;
-- ap_sig_cseq_ST_st116_fsm_115 assign process. --
ap_sig_cseq_ST_st116_fsm_115_assign_proc : process(ap_sig_bdd_384)
begin
if (ap_sig_bdd_384) then
ap_sig_cseq_ST_st116_fsm_115 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st116_fsm_115 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st117_fsm_116 assign process. --
ap_sig_cseq_ST_st117_fsm_116_assign_proc : process(ap_sig_bdd_929)
begin
if (ap_sig_bdd_929) then
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st121_fsm_120 assign process. --
ap_sig_cseq_ST_st121_fsm_120_assign_proc : process(ap_sig_bdd_572)
begin
if (ap_sig_bdd_572) then
ap_sig_cseq_ST_st121_fsm_120 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st121_fsm_120 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st122_fsm_121 assign process. --
ap_sig_cseq_ST_st122_fsm_121_assign_proc : process(ap_sig_bdd_581)
begin
if (ap_sig_bdd_581) then
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st123_fsm_122 assign process. --
ap_sig_cseq_ST_st123_fsm_122_assign_proc : process(ap_sig_bdd_283)
begin
if (ap_sig_bdd_283) then
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st124_fsm_123 assign process. --
ap_sig_cseq_ST_st124_fsm_123_assign_proc : process(ap_sig_bdd_1019)
begin
if (ap_sig_bdd_1019) then
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_319)
begin
if (ap_sig_bdd_319) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_954)
begin
if (ap_sig_bdd_954) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st154_fsm_153 assign process. --
ap_sig_cseq_ST_st154_fsm_153_assign_proc : process(ap_sig_bdd_401)
begin
if (ap_sig_bdd_401) then
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st155_fsm_154 assign process. --
ap_sig_cseq_ST_st155_fsm_154_assign_proc : process(ap_sig_bdd_776)
begin
if (ap_sig_bdd_776) then
ap_sig_cseq_ST_st155_fsm_154 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st155_fsm_154 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st156_fsm_155 assign process. --
ap_sig_cseq_ST_st156_fsm_155_assign_proc : process(ap_sig_bdd_595)
begin
if (ap_sig_bdd_595) then
ap_sig_cseq_ST_st156_fsm_155 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st156_fsm_155 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st157_fsm_156 assign process. --
ap_sig_cseq_ST_st157_fsm_156_assign_proc : process(ap_sig_bdd_291)
begin
if (ap_sig_bdd_291) then
ap_sig_cseq_ST_st157_fsm_156 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st157_fsm_156 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st158_fsm_157 assign process. --
ap_sig_cseq_ST_st158_fsm_157_assign_proc : process(ap_sig_bdd_617)
begin
if (ap_sig_bdd_617) then
ap_sig_cseq_ST_st158_fsm_157 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st158_fsm_157 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st159_fsm_158 assign process. --
ap_sig_cseq_ST_st159_fsm_158_assign_proc : process(ap_sig_bdd_626)
begin
if (ap_sig_bdd_626) then
ap_sig_cseq_ST_st159_fsm_158 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st159_fsm_158 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st160_fsm_159 assign process. --
ap_sig_cseq_ST_st160_fsm_159_assign_proc : process(ap_sig_bdd_637)
begin
if (ap_sig_bdd_637) then
ap_sig_cseq_ST_st160_fsm_159 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st160_fsm_159 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st161_fsm_160 assign process. --
ap_sig_cseq_ST_st161_fsm_160_assign_proc : process(ap_sig_bdd_655)
begin
if (ap_sig_bdd_655) then
ap_sig_cseq_ST_st161_fsm_160 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st161_fsm_160 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st162_fsm_161 assign process. --
ap_sig_cseq_ST_st162_fsm_161_assign_proc : process(ap_sig_bdd_805)
begin
if (ap_sig_bdd_805) then
ap_sig_cseq_ST_st162_fsm_161 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st162_fsm_161 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st163_fsm_162 assign process. --
ap_sig_cseq_ST_st163_fsm_162_assign_proc : process(ap_sig_bdd_669)
begin
if (ap_sig_bdd_669) then
ap_sig_cseq_ST_st163_fsm_162 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st163_fsm_162 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st164_fsm_163 assign process. --
ap_sig_cseq_ST_st164_fsm_163_assign_proc : process(ap_sig_bdd_686)
begin
if (ap_sig_bdd_686) then
ap_sig_cseq_ST_st164_fsm_163 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st164_fsm_163 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st165_fsm_164 assign process. --
ap_sig_cseq_ST_st165_fsm_164_assign_proc : process(ap_sig_bdd_704)
begin
if (ap_sig_bdd_704) then
ap_sig_cseq_ST_st165_fsm_164 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st165_fsm_164 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st166_fsm_165 assign process. --
ap_sig_cseq_ST_st166_fsm_165_assign_proc : process(ap_sig_bdd_720)
begin
if (ap_sig_bdd_720) then
ap_sig_cseq_ST_st166_fsm_165 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st166_fsm_165 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st167_fsm_166 assign process. --
ap_sig_cseq_ST_st167_fsm_166_assign_proc : process(ap_sig_bdd_1384)
begin
if (ap_sig_bdd_1384) then
ap_sig_cseq_ST_st167_fsm_166 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st167_fsm_166 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_336)
begin
if (ap_sig_bdd_336) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_300)
begin
if (ap_sig_bdd_300) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st19_fsm_18 assign process. --
ap_sig_cseq_ST_st19_fsm_18_assign_proc : process(ap_sig_bdd_961)
begin
if (ap_sig_bdd_961) then
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_185)
begin
if (ap_sig_bdd_185) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_352)
begin
if (ap_sig_bdd_352) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st24_fsm_23 assign process. --
ap_sig_cseq_ST_st24_fsm_23_assign_proc : process(ap_sig_bdd_523)
begin
if (ap_sig_bdd_523) then
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_435)
begin
if (ap_sig_bdd_435) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_451)
begin
if (ap_sig_bdd_451) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st41_fsm_40 assign process. --
ap_sig_cseq_ST_st41_fsm_40_assign_proc : process(ap_sig_bdd_377)
begin
if (ap_sig_bdd_377) then
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st42_fsm_41 assign process. --
ap_sig_cseq_ST_st42_fsm_41_assign_proc : process(ap_sig_bdd_969)
begin
if (ap_sig_bdd_969) then
ap_sig_cseq_ST_st42_fsm_41 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st42_fsm_41 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st46_fsm_45 assign process. --
ap_sig_cseq_ST_st46_fsm_45_assign_proc : process(ap_sig_bdd_359)
begin
if (ap_sig_bdd_359) then
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st47_fsm_46 assign process. --
ap_sig_cseq_ST_st47_fsm_46_assign_proc : process(ap_sig_bdd_1012)
begin
if (ap_sig_bdd_1012) then
ap_sig_cseq_ST_st47_fsm_46 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st47_fsm_46 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_481)
begin
if (ap_sig_bdd_481) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_503)
begin
if (ap_sig_bdd_503) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_268)
begin
if (ap_sig_bdd_268) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st77_fsm_76 assign process. --
ap_sig_cseq_ST_st77_fsm_76_assign_proc : process(ap_sig_bdd_394)
begin
if (ap_sig_bdd_394) then
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st78_fsm_77 assign process. --
ap_sig_cseq_ST_st78_fsm_77_assign_proc : process(ap_sig_bdd_754)
begin
if (ap_sig_bdd_754) then
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st79_fsm_78 assign process. --
ap_sig_cseq_ST_st79_fsm_78_assign_proc : process(ap_sig_bdd_532)
begin
if (ap_sig_bdd_532) then
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st80_fsm_79 assign process. --
ap_sig_cseq_ST_st80_fsm_79_assign_proc : process(ap_sig_bdd_553)
begin
if (ap_sig_bdd_553) then
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st81_fsm_80 assign process. --
ap_sig_cseq_ST_st81_fsm_80_assign_proc : process(ap_sig_bdd_275)
begin
if (ap_sig_bdd_275) then
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st87_fsm_86 assign process. --
ap_sig_cseq_ST_st87_fsm_86_assign_proc : process(ap_sig_bdd_326)
begin
if (ap_sig_bdd_326) then
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st88_fsm_87 assign process. --
ap_sig_cseq_ST_st88_fsm_87_assign_proc : process(ap_sig_bdd_976)
begin
if (ap_sig_bdd_976) then
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st92_fsm_91 assign process. --
ap_sig_cseq_ST_st92_fsm_91_assign_proc : process(ap_sig_bdd_343)
begin
if (ap_sig_bdd_343) then
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st93_fsm_92 assign process. --
ap_sig_cseq_ST_st93_fsm_92_assign_proc : process(ap_sig_bdd_309)
begin
if (ap_sig_bdd_309) then
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st94_fsm_93 assign process. --
ap_sig_cseq_ST_st94_fsm_93_assign_proc : process(ap_sig_bdd_983)
begin
if (ap_sig_bdd_983) then
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st98_fsm_97 assign process. --
ap_sig_cseq_ST_st98_fsm_97_assign_proc : process(ap_sig_bdd_367)
begin
if (ap_sig_bdd_367) then
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st99_fsm_98 assign process. --
ap_sig_cseq_ST_st99_fsm_98_assign_proc : process(ap_sig_bdd_1029)
begin
if (ap_sig_bdd_1029) then
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_P_netOut_V_TREADY assign process. --
ap_sig_ioackin_P_netOut_V_TREADY_assign_proc : process(P_netOut_V_TREADY, ap_reg_ioackin_P_netOut_V_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_netOut_V_TREADY)) then
ap_sig_ioackin_P_netOut_V_TREADY <= P_netOut_V_TREADY;
else
ap_sig_ioackin_P_netOut_V_TREADY <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ioackin_P_uOut_TREADY assign process. --
ap_sig_ioackin_P_uOut_TREADY_assign_proc : process(P_uOut_TREADY, ap_reg_ioackin_P_uOut_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_P_uOut_TREADY)) then
ap_sig_ioackin_P_uOut_TREADY <= P_uOut_TREADY;
else
ap_sig_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end if;
end process;
exitcond1_fu_642_p2 <= "1" when (i_2_reg_297 = ST_layerSize_V_0_load_reg_1472) else "0";
exitcond2_fu_1341_p2 <= "1" when (j_reg_481 = ST_layerSize_V_load_1_phi_reg_1751) else "0";
exitcond3_fu_836_p2 <= "1" when (k_1_reg_343 = tmp_20_reg_1548) else "0";
exitcond4_fu_989_p2 <= "1" when (j_2_reg_389 = tmp_22_reg_1612) else "0";
exitcond5_fu_1041_p2 <= "1" when (i_5_reg_400 = tmp_17_reg_1598) else "0";
exitcond6_fu_1210_p2 <= "1" when (i_6_reg_436 = ST_numLayer_V_load_reg_1461) else "0";
exitcond7_fu_1410_p2 <= "1" when (i_reg_503 = P_config_V_read_reg_1477) else "0";
exitcond8_fu_1399_p2 <= "1" when (k_reg_492 = tmp_10_reg_1756) else "0";
exitcond_fu_1239_p2 <= "1" when (j_3_reg_458 = tmp_40_reg_1725) else "0";
feedforward_AXILiteS_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
grp_fu_535_ce <= ap_const_logic_1;
-- grp_fu_535_p0 assign process. --
grp_fu_535_p0_assign_proc : process(reg_608, sum_reg_331, sumsoft_reg_354, sum_1_reg_377, ap_sig_cseq_ST_st117_fsm_116, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st42_fsm_41, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st94_fsm_93)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116)) then
grp_fu_535_p0 <= sumsoft_reg_354;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) or (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93))) then
grp_fu_535_p0 <= sum_1_reg_377;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41)) then
grp_fu_535_p0 <= reg_608;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) or (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18))) then
grp_fu_535_p0 <= sum_reg_331;
else
grp_fu_535_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_535_p1 assign process. --
grp_fu_535_p1_assign_proc : process(reg_585, reg_591, reg_608, ap_sig_cseq_ST_st117_fsm_116, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st42_fsm_41, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st94_fsm_93)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116)) then
grp_fu_535_p1 <= reg_608;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41)) then
grp_fu_535_p1 <= ap_const_lv64_3FF0000000000000;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93))) then
grp_fu_535_p1 <= reg_585;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) or (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87))) then
grp_fu_535_p1 <= reg_591;
else
grp_fu_535_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_543_ce <= ap_const_logic_1;
grp_fu_547_ce <= ap_const_logic_1;
-- grp_fu_547_p0 assign process. --
grp_fu_547_p0_assign_proc : process(reg_578, ap_sig_cseq_ST_st47_fsm_46, ap_sig_cseq_ST_st124_fsm_123)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
grp_fu_547_p0 <= reg_578;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st47_fsm_46)) then
grp_fu_547_p0 <= ap_const_lv64_3FF0000000000000;
else
grp_fu_547_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_547_p1 assign process. --
grp_fu_547_p1_assign_proc : process(reg_602, sumsoft_reg_354, ap_sig_cseq_ST_st47_fsm_46, ap_sig_cseq_ST_st124_fsm_123)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
grp_fu_547_p1 <= sumsoft_reg_354;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st47_fsm_46)) then
grp_fu_547_p1 <= reg_602;
else
grp_fu_547_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_557_ce <= ap_const_logic_1;
-- grp_fu_557_p1 assign process. --
grp_fu_557_p1_assign_proc : process(reg_602, tmp_25_fu_898_p1, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st99_fsm_98)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98)) then
grp_fu_557_p1 <= reg_602;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23)) then
grp_fu_557_p1 <= tmp_25_fu_898_p1;
else
grp_fu_557_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
i_10_fu_830_p2 <= std_logic_vector(unsigned(i_3_reg_308) + unsigned(ap_const_lv8_1));
i_11_fu_1046_p2 <= std_logic_vector(unsigned(i_5_reg_400) + unsigned(ap_const_lv8_1));
i_12_fu_926_p2 <= std_logic_vector(unsigned(i_4_reg_366) + unsigned(ap_const_lv32_1));
i_14_fu_1215_p2 <= std_logic_vector(unsigned(ap_const_lv8_1) + unsigned(i_6_reg_436));
i_15_fu_1194_p2 <= std_logic_vector(unsigned(ap_const_lv8_1) + unsigned(p_netOut_V_reg_424));
i_7_fu_1415_p2 <= std_logic_vector(unsigned(i_reg_503) + unsigned(ap_const_lv8_1));
i_8_fu_647_p2 <= std_logic_vector(unsigned(i_2_reg_297) + unsigned(ap_const_lv8_1));
i_9_fu_1379_p2 <= std_logic_vector(unsigned(i_1_reg_469) + unsigned(ap_const_lv8_1));
j_4_fu_1346_p2 <= std_logic_vector(unsigned(j_reg_481) + unsigned(ap_const_lv8_1));
j_5_fu_771_p2 <= std_logic_vector(unsigned(j_1_reg_320) + unsigned(ap_const_lv32_1));
j_6_fu_994_p2 <= std_logic_vector(unsigned(j_2_reg_389) + unsigned(ap_const_lv8_1));
j_7_fu_1244_p2 <= std_logic_vector(unsigned(j_3_reg_458) + unsigned(ap_const_lv8_1));
k_2_fu_1404_p2 <= std_logic_vector(unsigned(k_reg_492) + unsigned(ap_const_lv9_1));
k_3_fu_841_p2 <= std_logic_vector(unsigned(k_1_reg_343) + unsigned(ap_const_lv8_1));
lhs_V_1_cast_fu_701_p1 <= std_logic_vector(resize(unsigned(ST_numLayer_V_load_reg_1461),9));
next_mul_fu_1204_p2 <= std_logic_vector(unsigned(ap_const_lv14_23) + unsigned(phi_mul_reg_447));
notlhs1_fu_1157_p2 <= "0" when (tmp_45_fu_1125_p4 = ap_const_lv11_7FF) else "1";
notlhs_fu_1139_p2 <= "0" when (tmp_43_fu_1108_p4 = ap_const_lv11_7FF) else "1";
notrhs1_fu_1163_p2 <= "1" when (tmp_71_fu_1135_p1 = ap_const_lv52_0) else "0";
notrhs_fu_1145_p2 <= "1" when (tmp_70_fu_1118_p1 = ap_const_lv52_0) else "0";
p_netOut_V_1_fu_1187_p3 <=
p_netOut_V_reg_424 when (tmp_51_reg_1692(0) = '1') else
p_s_reg_411;
p_shl2_cast_fu_804_p3 <= (tmp_52_fu_800_p1 & ap_const_lv5_0);
p_shl3_cast_fu_816_p3 <= (tmp_53_fu_812_p1 & ap_const_lv2_0);
p_shl4_cast_fu_963_p3 <= (tmp_56_fu_959_p1 & ap_const_lv5_0);
p_shl5_cast_fu_975_p3 <= (tmp_57_fu_971_p1 & ap_const_lv2_0);
-- p_uOut_address0 assign process. --
p_uOut_address0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, p_uOut_addr_1_reg_1560, ap_sig_cseq_ST_st5_fsm_4, p_uOut_addr_3_reg_1624, ap_sig_cseq_ST_st80_fsm_79, ap_sig_cseq_ST_st122_fsm_121, p_uOut_addr_5_reg_1665, ap_sig_cseq_ST_st156_fsm_155, ap_sig_cseq_ST_st78_fsm_77, ap_sig_cseq_ST_st155_fsm_154, tmp_6_fu_653_p1, tmp_74_cast_fu_870_p1, tmp_77_cast_fu_1023_p1, tmp_78_cast_fu_1061_p1, tmp_80_cast_fu_1085_p1, ap_sig_cseq_ST_st117_fsm_116)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st155_fsm_154)) then
p_uOut_address0 <= p_uOut_addr_5_reg_1665;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116)) then
p_uOut_address0 <= p_uOut_addr_3_reg_1624;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) then
p_uOut_address0 <= p_uOut_addr_1_reg_1560;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_address0 <= tmp_6_fu_653_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155)) then
p_uOut_address0 <= tmp_80_cast_fu_1085_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121)) then
p_uOut_address0 <= tmp_78_cast_fu_1061_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) then
p_uOut_address0 <= tmp_77_cast_fu_1023_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
p_uOut_address0 <= tmp_74_cast_fu_870_p1(8 - 1 downto 0);
else
p_uOut_address0 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_address1 assign process. --
p_uOut_address1_assign_proc : process(ap_sig_cseq_ST_st156_fsm_155, ap_sig_cseq_ST_st161_fsm_160, tmp_81_cast_fu_1099_p1, tmp_82_cast_fu_1259_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st161_fsm_160)) then
p_uOut_address1 <= tmp_82_cast_fu_1259_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155)) then
p_uOut_address1 <= tmp_81_cast_fu_1099_p1(8 - 1 downto 0);
else
p_uOut_address1 <= "XXXXXXXX";
end if;
end process;
-- p_uOut_ce0 assign process. --
p_uOut_ce0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ap_sig_bdd_441, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st80_fsm_79, ap_sig_cseq_ST_st122_fsm_121, ap_sig_cseq_ST_st156_fsm_155, tmp_38_fu_1071_p2, ap_sig_ioackin_P_netOut_V_TREADY, ap_sig_cseq_ST_st78_fsm_77, ap_sig_cseq_ST_st155_fsm_154, ap_sig_cseq_ST_st117_fsm_116)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not(ap_sig_bdd_441)) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) or (ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121) or ((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155) and not(((ap_const_lv1_0 = tmp_38_fu_1071_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) or (ap_const_logic_1 = ap_sig_cseq_ST_st155_fsm_154) or (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116))) then
p_uOut_ce0 <= ap_const_logic_1;
else
p_uOut_ce0 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_ce1 assign process. --
p_uOut_ce1_assign_proc : process(ap_sig_cseq_ST_st156_fsm_155, tmp_38_fu_1071_p2, ap_sig_ioackin_P_netOut_V_TREADY, ap_sig_cseq_ST_st161_fsm_160)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155) and not(((ap_const_lv1_0 = tmp_38_fu_1071_p2) and (ap_const_logic_0 = ap_sig_ioackin_P_netOut_V_TREADY)))) or (ap_const_logic_1 = ap_sig_cseq_ST_st161_fsm_160))) then
p_uOut_ce1 <= ap_const_logic_1;
else
p_uOut_ce1 <= ap_const_logic_0;
end if;
end process;
-- p_uOut_d0 assign process. --
p_uOut_d0_assign_proc : process(P_netIn_TDATA, reg_608, reg_615, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st78_fsm_77, ap_sig_cseq_ST_st155_fsm_154, ap_sig_cseq_ST_st117_fsm_116)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116)) then
p_uOut_d0 <= reg_608;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) or (ap_const_logic_1 = ap_sig_cseq_ST_st155_fsm_154))) then
p_uOut_d0 <= reg_615;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
p_uOut_d0 <= P_netIn_TDATA;
else
p_uOut_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
p_uOut_load_3_to_int_fu_1104_p1 <= reg_578;
p_uOut_load_4_to_int_fu_1122_p1 <= p_uOut_load_4_reg_1686;
-- p_uOut_we0 assign process. --
p_uOut_we0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_642_p2, ap_sig_bdd_441, ap_sig_cseq_ST_st78_fsm_77, ap_sig_cseq_ST_st155_fsm_154, ap_sig_cseq_ST_st117_fsm_116)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_642_p2) and not(ap_sig_bdd_441)) or (ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77) or (ap_const_logic_1 = ap_sig_cseq_ST_st155_fsm_154) or (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116))) then
p_uOut_we0 <= ap_const_logic_1;
else
p_uOut_we0 <= ap_const_logic_0;
end if;
end process;
r_V_1_fu_732_p2 <= std_logic_vector(signed(ap_const_lv9_1FE) + signed(lhs_V_1_cast_fu_701_p1));
r_V_fu_704_p2 <= std_logic_vector(signed(ap_const_lv9_1FF) + signed(lhs_V_1_cast_fu_701_p1));
sel_tmp1_fu_1289_p3 <=
ST_layerSize_V_1 when (sel_tmp_fu_1283_p2(0) = '1') else
ST_layerSize_V_3;
sel_tmp2_fu_1297_p2 <= "1" when (tmp_5_fu_1279_p1 = ap_const_lv2_2) else "0";
sel_tmp_fu_1283_p2 <= "1" when (tmp_5_fu_1279_p1 = ap_const_lv2_1) else "0";
tmp_10_fu_1335_p2 <= std_logic_vector(unsigned(ap_const_lv9_1) + unsigned(tmp_9_fu_1331_p1));
tmp_11_fu_1356_p2 <= std_logic_vector(unsigned(tmp_cast_fu_1352_p1) + unsigned(tmp_s_reg_1746));
tmp_12_cast_fu_1385_p1 <= std_logic_vector(resize(unsigned(k_reg_492),14));
tmp_12_fu_1361_p2 <= std_logic_vector(shift_left(unsigned(tmp_11_fu_1356_p2),to_integer(unsigned('0' & ap_const_lv14_5(14-1 downto 0)))));
tmp_13_fu_1367_p2 <= std_logic_vector(shift_left(unsigned(tmp_11_fu_1356_p2),to_integer(unsigned('0' & ap_const_lv14_2(14-1 downto 0)))));
tmp_15_fu_761_p1 <= std_logic_vector(resize(unsigned(tmp_14_fu_748_p6),32));
tmp_16_fu_765_p2 <= "1" when (signed(j_1_reg_320) < signed(tmp_15_fu_761_p1)) else "0";
tmp_18_fu_916_p1 <= std_logic_vector(resize(unsigned(tmp_17_fu_903_p6),32));
tmp_19_fu_920_p2 <= "1" when (signed(i_4_reg_366) < signed(tmp_18_fu_916_p1)) else "0";
tmp_1_fu_630_p2 <= "1" when (P_mode_V = ap_const_lv8_3) else "0";
tmp_21_fu_1373_p2 <= std_logic_vector(unsigned(tmp_12_fu_1361_p2) + unsigned(tmp_13_fu_1367_p2));
tmp_23_cast_fu_945_p1 <= std_logic_vector(resize(signed(i_4_reg_366),33));
tmp_23_fu_667_p1 <= tmp_23_fu_667_p10(8 - 1 downto 0);
tmp_23_fu_667_p10 <= std_logic_vector(resize(unsigned(i_3_reg_308),15));
tmp_23_fu_667_p2 <= std_logic_vector(resize(unsigned(ap_const_lv15_23) * unsigned(tmp_23_fu_667_p1), 15));
tmp_24_cast_fu_875_p1 <= std_logic_vector(resize(unsigned(tmp_20_reg_1548),14));
tmp_24_fu_677_p1 <= i_3_reg_308(2 - 1 downto 0);
tmp_25_fu_898_p1 <= tmp_38_neg_fu_892_p2;
tmp_29_cast1_fu_847_p1 <= std_logic_vector(resize(unsigned(k_1_reg_343),9));
tmp_29_cast_fu_851_p1 <= std_logic_vector(resize(unsigned(k_1_reg_343),14));
tmp_29_fu_691_p1 <= tmp_29_fu_691_p10(8 - 1 downto 0);
tmp_29_fu_691_p10 <= std_logic_vector(resize(unsigned(tmp_4_fu_681_p2),9));
tmp_29_fu_691_p2 <= std_logic_vector(resize(unsigned(ap_const_lv9_23) * unsigned(tmp_29_fu_691_p1), 9));
tmp_2_fu_1317_p5 <= std_logic_vector(signed(ap_const_lv2_3) + signed(tmp_5_fu_1279_p1));
tmp_31_cast_fu_1028_p1 <= std_logic_vector(resize(unsigned(tmp_22_reg_1612),14));
tmp_31_fu_697_p1 <= tmp_4_fu_681_p2(2 - 1 downto 0);
tmp_33_cast1_fu_1000_p1 <= std_logic_vector(resize(unsigned(j_2_reg_389),9));
tmp_33_cast_fu_1004_p1 <= std_logic_vector(resize(unsigned(j_2_reg_389),14));
tmp_33_fu_714_p1 <= r_V_fu_704_p2;
tmp_33_fu_714_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv16_23) * signed(tmp_33_fu_714_p1))), 16));
tmp_35_fu_1066_p2 <= "1" when (P_mode_V_read_reg_1453 = ap_const_lv8_4) else "0";
tmp_36_cast_fu_1052_p1 <= std_logic_vector(resize(unsigned(i_5_reg_400),9));
tmp_36_fu_720_p1 <= tmp_33_fu_714_p2(9 - 1 downto 0);
tmp_38_fu_1071_p2 <= "1" when (unsigned(p_netOut_V_reg_424) < unsigned(tmp_17_reg_1598)) else "0";
tmp_38_neg_fu_892_p2 <= (tmp_38_to_int_fu_888_p1 xor ap_const_lv64_8000000000000000);
tmp_38_to_int_fu_888_p1 <= reg_602;
tmp_39_fu_728_p1 <= r_V_fu_704_p2(2 - 1 downto 0);
tmp_3_fu_1421_p1 <= i_reg_503(2 - 1 downto 0);
tmp_40_fu_1225_p5 <= i_6_reg_436(2 - 1 downto 0);
tmp_41_cast_fu_1076_p1 <= std_logic_vector(resize(unsigned(p_netOut_V_reg_424),9));
tmp_41_fu_738_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv9_23) * signed(r_V_1_fu_732_p2))), 9));
tmp_42_cast_fu_1090_p1 <= std_logic_vector(resize(unsigned(p_s_reg_411),9));
tmp_42_fu_744_p1 <= r_V_1_fu_732_p2(2 - 1 downto 0);
tmp_43_fu_1108_p4 <= p_uOut_load_3_to_int_fu_1104_p1(62 downto 52);
tmp_44_fu_1389_p2 <= std_logic_vector(unsigned(tmp_21_reg_1769) + unsigned(tmp_12_cast_fu_1385_p1));
tmp_45_fu_1125_p4 <= p_uOut_load_4_to_int_fu_1122_p1(62 downto 52);
tmp_46_fu_790_p2 <= std_logic_vector(unsigned(j_1_reg_320) + unsigned(tmp_59_cast_reg_1493));
tmp_47_fu_1151_p2 <= (notrhs_fu_1145_p2 or notlhs_fu_1139_p2);
tmp_48_fu_1169_p2 <= (notrhs1_fu_1163_p2 or notlhs1_fu_1157_p2);
tmp_49_fu_1175_p2 <= (tmp_47_fu_1151_p2 and tmp_48_fu_1169_p2);
tmp_4_fu_681_p2 <= std_logic_vector(signed(ap_const_lv8_FF) + signed(i_3_reg_308));
tmp_50_fu_553_opcode <= ap_const_lv5_2;
tmp_51_fu_1181_p2 <= (tmp_49_fu_1175_p2 and tmp_50_fu_553_p2);
tmp_52_cast_fu_1250_p1 <= std_logic_vector(resize(unsigned(j_3_reg_458),9));
tmp_52_fu_800_p1 <= tmp_46_fu_790_p2(9 - 1 downto 0);
tmp_53_fu_812_p1 <= tmp_46_fu_790_p2(12 - 1 downto 0);
tmp_54_fu_824_p2 <= std_logic_vector(unsigned(p_shl2_cast_fu_804_p3) + unsigned(p_shl3_cast_fu_816_p3));
tmp_55_fu_949_p2 <= std_logic_vector(signed(tmp_23_cast_fu_945_p1) + signed(tmp_61_cast_reg_1520));
tmp_56_fu_959_p1 <= tmp_55_fu_949_p2(9 - 1 downto 0);
tmp_57_fu_971_p1 <= tmp_55_fu_949_p2(12 - 1 downto 0);
tmp_58_fu_983_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_963_p3) + unsigned(p_shl5_cast_fu_975_p3));
tmp_59_cast_fu_673_p1 <= std_logic_vector(resize(unsigned(tmp_23_fu_667_p2),32));
tmp_59_fu_1056_p2 <= std_logic_vector(unsigned(tmp_36_reg_1513) + unsigned(tmp_36_cast_fu_1052_p1));
tmp_5_fu_1279_p1 <= i_1_reg_469(2 - 1 downto 0);
tmp_60_fu_878_p2 <= std_logic_vector(unsigned(tmp_54_reg_1554) + unsigned(tmp_24_cast_fu_875_p1));
tmp_61_cast_fu_724_p1 <= std_logic_vector(resize(signed(tmp_33_fu_714_p2),33));
tmp_61_fu_855_p2 <= std_logic_vector(unsigned(tmp_54_reg_1554) + unsigned(tmp_29_cast_fu_851_p1));
tmp_62_fu_865_p2 <= std_logic_vector(unsigned(tmp_29_reg_1503) + unsigned(tmp_29_cast1_fu_847_p1));
tmp_63_cast_fu_1394_p1 <= std_logic_vector(resize(unsigned(tmp_44_fu_1389_p2),64));
tmp_63_fu_1031_p2 <= std_logic_vector(unsigned(tmp_58_reg_1618) + unsigned(tmp_31_cast_fu_1028_p1));
tmp_64_cast_fu_795_p1 <= std_logic_vector(resize(signed(tmp_46_fu_790_p2),64));
tmp_64_fu_1008_p2 <= std_logic_vector(unsigned(tmp_58_reg_1618) + unsigned(tmp_33_cast_fu_1004_p1));
tmp_65_fu_1018_p2 <= std_logic_vector(unsigned(tmp_41_reg_1530) + unsigned(tmp_33_cast1_fu_1000_p1));
tmp_66_fu_1200_p1 <= phi_mul_reg_447(9 - 1 downto 0);
tmp_68_cast_fu_954_p1 <= std_logic_vector(resize(signed(tmp_55_fu_949_p2),64));
tmp_68_fu_1080_p2 <= std_logic_vector(unsigned(tmp_36_reg_1513) + unsigned(tmp_41_cast_fu_1076_p1));
tmp_69_fu_1094_p2 <= std_logic_vector(unsigned(tmp_36_reg_1513) + unsigned(tmp_42_cast_fu_1090_p1));
tmp_6_fu_653_p1 <= std_logic_vector(resize(unsigned(i_2_reg_297),64));
tmp_70_fu_1118_p1 <= p_uOut_load_3_to_int_fu_1104_p1(52 - 1 downto 0);
tmp_71_fu_1135_p1 <= p_uOut_load_4_to_int_fu_1122_p1(52 - 1 downto 0);
tmp_72_cast_fu_883_p1 <= std_logic_vector(resize(unsigned(tmp_60_fu_878_p2),64));
tmp_72_fu_1254_p2 <= std_logic_vector(unsigned(tmp_66_reg_1707) + unsigned(tmp_52_cast_fu_1250_p1));
tmp_73_cast_fu_860_p1 <= std_logic_vector(resize(unsigned(tmp_61_fu_855_p2),64));
tmp_74_cast_fu_870_p1 <= std_logic_vector(resize(signed(tmp_62_fu_865_p2),64));
tmp_75_cast_fu_1036_p1 <= std_logic_vector(resize(unsigned(tmp_63_fu_1031_p2),64));
tmp_76_cast_fu_1013_p1 <= std_logic_vector(resize(unsigned(tmp_64_fu_1008_p2),64));
tmp_77_cast_fu_1023_p1 <= std_logic_vector(resize(signed(tmp_65_fu_1018_p2),64));
tmp_78_cast_fu_1061_p1 <= std_logic_vector(resize(signed(tmp_59_fu_1056_p2),64));
tmp_7_fu_658_p2 <= "1" when (unsigned(i_3_reg_308) < unsigned(ST_numLayer_V_load_reg_1461)) else "0";
tmp_80_cast_fu_1085_p1 <= std_logic_vector(resize(signed(tmp_68_fu_1080_p2),64));
tmp_81_cast_fu_1099_p1 <= std_logic_vector(resize(signed(tmp_69_fu_1094_p2),64));
tmp_82_cast_fu_1259_p1 <= std_logic_vector(resize(unsigned(tmp_72_fu_1254_p2),64));
tmp_8_fu_1264_p2 <= "1" when (unsigned(i_1_reg_469) < unsigned(ST_numLayer_V_load_reg_1461)) else "0";
tmp_9_fu_1331_p1 <= std_logic_vector(resize(unsigned(tmp_2_fu_1317_p6),9));
tmp_cast_fu_1352_p1 <= std_logic_vector(resize(unsigned(j_reg_481),14));
tmp_fu_620_p2 <= "1" when (P_mode_V = ap_const_lv8_2) else "0";
tmp_s_fu_1273_p1 <= tmp_s_fu_1273_p10(8 - 1 downto 0);
tmp_s_fu_1273_p10 <= std_logic_vector(resize(unsigned(i_1_reg_469),14));
tmp_s_fu_1273_p2 <= std_logic_vector(resize(unsigned(ap_const_lv14_23) * unsigned(tmp_s_fu_1273_p1), 14));
end behav;
| gpl-3.0 | 94926e589f1f3e715da60a24081926fa | 0.642185 | 3.289267 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_3/hdl/vhdl/feedforward_AXILiteS_s_axi.vhd | 2 | 12,468 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity feedforward_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
P_mode_V :out STD_LOGIC_VECTOR(7 downto 0)
);
end entity feedforward_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of P_mode_V
-- bit 7~0 - P_mode_V[7:0] (Read/Write)
-- others - reserved
-- 0x14 : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of feedforward_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_P_MODE_V_DATA_0 : INTEGER := 16#10#;
constant ADDR_P_MODE_V_CTRL : INTEGER := 16#14#;
constant ADDR_BITS : INTEGER := 5;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_P_mode_V : UNSIGNED(7 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_P_MODE_V_DATA_0 =>
rdata_data <= RESIZE(int_P_mode_V(7 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
P_mode_V <= STD_LOGIC_VECTOR(int_P_mode_V);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_MODE_V_DATA_0) then
int_P_mode_V(7 downto 0) <= (UNSIGNED(WDATA(7 downto 0)) and wmask(7 downto 0)) or ((not wmask(7 downto 0)) and int_P_mode_V(7 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| gpl-3.0 | 87b51e7822205c8ef3d65b219a3f05f0 | 0.452198 | 3.782767 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/vhdl/feedforward_dadd_64ns_64ns_64_5_full_dsp.vhd | 2 | 3,380 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dadd_64ns_64ns_64_5_full_dsp is
generic (
ID : integer := 0;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dadd_64ns_64ns_64_5_full_dsp is
--------------------- Component ---------------------
component feedforward_ap_dadd_3_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dadd_3_full_dsp_64_u : component feedforward_ap_dadd_3_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | cb19621424d27aa118f8687f636a255c | 0.490533 | 3.51717 | false | false | false | false |
Rookfighter/aes-ss17 | ex02/lcd_tb.vhd | 1 | 2,785 | -- lcd_tb.vhd
--
-- Created on: 21 May 2017
-- Author: Fabian Meyer
--
-- Testbench for LCD component.
library ieee;
use ieee.std_logic_1164.all;
entity lcd_tb is
end lcd_tb;
architecture behavior of lcd_tb is
-- Component Declaration for the Unit Under Test (UUT)
component lcd
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic;
clk: in std_logic;
din: in std_logic_vector(7 downto 0);
posx: in std_logic_vector(3 downto 0);
posy: in std_logic;
flush: in std_logic;
rdy: out std_logic;
en: out std_logic;
rw: out std_logic;
rs: out std_logic;
bl: out std_logic;
data: inout std_logic_vector(3 downto 0));
end component;
--Inputs
signal rst: std_logic := '0';
signal clk: std_logic := '0';
signal din: std_logic_vector(7 downto 0) := (others => '0');
signal posx: std_logic_vector(3 downto 0) := (others => '0');
signal posy: std_logic := '0';
signal flush: std_logic := '0';
--BiDirs
signal data: std_logic_vector(3 downto 0);
--Outputs
signal rdy: std_logic;
signal en: std_logic;
signal rw: std_logic;
signal rs: std_logic;
signal bl: std_logic;
-- Clock period definitions
constant clk_period: time := 10 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: lcd
port map (rst => rst,
clk => clk,
din => din,
posx => posx,
posy => posy,
flush => flush,
rdy => rdy,
en => en,
rw => rw,
rs => rs,
bl => bl,
data => data);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
rst <= '1';
-- init sequence takes 41ms
-- with 24MHz this makes 984000 cycles (24000/ms)
wait for clk_period*984000;
-- en should always stay on for 8 cycles
-- rdy should turn 1 here!
-- write char at pos 4 in line 1
din <= "11000000";
posx <= "0100";
posy <= '1';
flush <= '1';
wait for clk_period;
flush <= '0';
--rdy should be 0 here!
-- write sequence takes 400us
-- with 24MHz this makes 9600 cycles (24/us)
wait for clk_period*9600;
-- rdy should be 1 here!
--wait;
end process;
end architecture;
| gpl-3.0 | af19955d99a1880a7b47f8d88cab2199 | 0.512747 | 3.763514 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_3/hdl/vhdl/feedforward_mux_4to1_sel2_8_1.vhd | 3 | 1,612 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity feedforward_mux_4to1_sel2_8_1 is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
din5_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din1 :in std_logic_vector(7 downto 0);
din2 :in std_logic_vector(7 downto 0);
din3 :in std_logic_vector(7 downto 0);
din4 :in std_logic_vector(7 downto 0);
din5 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(7 downto 0));
end entity;
architecture rtl of feedforward_mux_4to1_sel2_8_1 is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(7 downto 0);
signal mux_1_1 : std_logic_vector(7 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(7 downto 0);
begin
sel <= din5;
-- Generate level 1 logic
mux_1_0 <= din1 when sel(0) = '0' else din2;
mux_1_1 <= din3 when sel(0) = '0' else din4;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
| gpl-3.0 | 8dde5740b997877f23fa3357ba7cb685 | 0.560174 | 3.154599 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_fadd_32ns_32ns_32_5_full_dsp.vhd | 4 | 3,380 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_fadd_32ns_32ns_32_5_full_dsp is
generic (
ID : integer := 0;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_fadd_32ns_32ns_32_5_full_dsp is
--------------------- Component ---------------------
component feedforward_ap_fadd_3_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_fadd_3_full_dsp_32_u : component feedforward_ap_fadd_3_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 3351f7c948cdceb4a8b5b8ce3dd984d2 | 0.490533 | 3.51717 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0.vhd | 24 | 8,323 | `protect begin_protected
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| gpl-3.0 | 88dba0e9e42e36a13920058281e0f805 | 0.912291 | 1.947812 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd | 24 | 24,644 | `protect begin_protected
`protect version = 1
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`protect key_block
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`protect key_block
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`protect key_block
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`protect key_block
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`protect end_protected
| gpl-3.0 | ab1fe3e443a3e598a98640315acf4d03 | 0.940838 | 1.869235 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt | kr_fuzman_omegat.vhd | 1 | 861 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kr_fuzman_omegat is
port
( clock : in std_logic;
koft : in std_logic_vector (31 downto 0);
Ztcap : in std_logic_vector (31 downto 0);
omegat : out std_logic_vector (31 downto 0)
);
end kr_fuzman_omegat;
architecture struct of kr_fuzman_omegat is
component kn_kalman_mult IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1 : std_logic_vector(31 downto 0);
begin
M1 : kn_kalman_mult port map (clock => clock, dataa => koft, datab => koft, result => Z1);
M2 : kn_kalman_mult port map (clock => clock, dataa => Z1, datab => Ztcap, result => omegat);
end struct;
| mit | 3db70f4ab691f1087168be6d43c8c11b | 0.637631 | 3.188889 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/ip/ANN_ap_dexp_16_full_dsp_64.vhd | 6 | 12,418 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_dexp_16_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END ANN_ap_dexp_16_full_dsp_64;
ARCHITECTURE ANN_ap_dexp_16_full_dsp_64_arch OF ANN_ap_dexp_16_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_dexp_16_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_dexp_16_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_dexp_16_full_dsp_64_arch : ARCHITECTURE IS "ANN_ap_dexp_16_full_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_dexp_16_full_dsp_64_arch: ARCHITECTURE IS "ANN_ap_dexp_16_full_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=1,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=16,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 1,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 16,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_dexp_16_full_dsp_64_arch;
| gpl-3.0 | 267fb6fb93d4e8611043c500a2e8eba0 | 0.648414 | 3.012615 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt | kr_fuzman_Zt.vhd | 1 | 1,535 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kr_fuzman_Zt is
port
( clock : in std_logic;
koft : in std_logic_vector(31 downto 0);
Ztminus : in std_logic_vector(31 downto 0);
omegat : in std_logic_vector(31 downto 0);
Zt : out std_logic_vector(31 downto 0)
);
end kr_fuzman_Zt;
architecture struct of kr_fuzman_Zt is
component kn_kalman_add IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_mult IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_sub IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2 : std_logic_vector (31 downto 0);
signal I : std_logic_vector(31 downto 0) := "00111111100000000000000000000000";
begin
M1 : kn_kalman_sub port map (clock => clock, dataa => I, datab => koft, result => Z1);
M2 : kn_kalman_mult port map (clock => clock, dataa => Z1, datab => Ztminus, result => Z2);
M3 : kn_kalman_add port map (clock => clock, dataa => Z2, datab => omegat, result => Zt);
end struct; | mit | fc712840af683b2c0c51bfb140368441 | 0.631922 | 3.204593 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/vhdl/feedforward_AXILiteS_s_axi.vhd | 1 | 13,233 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity feedforward_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
ap_return :in STD_LOGIC_VECTOR(7 downto 0);
P_mode_V :out STD_LOGIC_VECTOR(7 downto 0)
);
end entity feedforward_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of ap_return
-- bit 7~0 - ap_return[7:0] (Read)
-- others - reserved
-- 0x18 : Data signal of P_mode_V
-- bit 7~0 - P_mode_V[7:0] (Read/Write)
-- others - reserved
-- 0x1c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of feedforward_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_AP_RETURN_0 : INTEGER := 16#10#;
constant ADDR_P_MODE_V_DATA_0 : INTEGER := 16#18#;
constant ADDR_P_MODE_V_CTRL : INTEGER := 16#1c#;
constant ADDR_BITS : INTEGER := 5;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_ap_return : UNSIGNED(7 downto 0);
signal int_P_mode_V : UNSIGNED(7 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_AP_RETURN_0 =>
rdata_data <= RESIZE(int_ap_return(7 downto 0), 32);
when ADDR_P_MODE_V_DATA_0 =>
rdata_data <= RESIZE(int_P_mode_V(7 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
P_mode_V <= STD_LOGIC_VECTOR(int_P_mode_V);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_return <= (others => '0');
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_return <= UNSIGNED(ap_return);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_MODE_V_DATA_0) then
int_P_mode_V(7 downto 0) <= (UNSIGNED(WDATA(7 downto 0)) and wmask(7 downto 0)) or ((not wmask(7 downto 0)) and int_P_mode_V(7 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| gpl-3.0 | ed7162b56aa5a963bfe48d2715f94243 | 0.45311 | 3.772235 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/hdl/design_TEST.vhd | 1 | 194,848 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
--Date : Thu Sep 01 18:18:58 2016
--Host : DESKTOP-I329812 running 64-bit major release (build 9200)
--Command : generate_target design_TEST.bd
--Design : design_TEST
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1FMN47O is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_1FMN47O;
architecture STRUCTURE of m00_couplers_imp_1FMN47O is
component design_TEST_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_TEST_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_WID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_WLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_m00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_m00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(0) <= auto_pc_to_m00_couplers_ARID(0);
M_AXI_arlen(3 downto 0) <= auto_pc_to_m00_couplers_ARLEN(3 downto 0);
M_AXI_arlock(1 downto 0) <= auto_pc_to_m00_couplers_ARLOCK(1 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_m00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_m00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_pc_to_m00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_pc_to_m00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(0) <= auto_pc_to_m00_couplers_AWID(0);
M_AXI_awlen(3 downto 0) <= auto_pc_to_m00_couplers_AWLEN(3 downto 0);
M_AXI_awlock(1 downto 0) <= auto_pc_to_m00_couplers_AWLOCK(1 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_pc_to_m00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_pc_to_m00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wid(0) <= auto_pc_to_m00_couplers_WID(0);
M_AXI_wlast <= auto_pc_to_m00_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= auto_pc_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(0) <= m00_couplers_to_auto_pc_BID(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(0) <= m00_couplers_to_auto_pc_RID(0);
S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m00_couplers_to_auto_pc_WREADY;
auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m00_couplers_BID(5 downto 0) <= M_AXI_bid(5 downto 0);
auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_m00_couplers_RID(5 downto 0) <= M_AXI_rid(5 downto 0);
auto_pc_to_m00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_auto_pc_ARID(0) <= S_AXI_arid(0);
m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_auto_pc_AWID(0) <= S_AXI_awid(0);
m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_TEST_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(0) => auto_pc_to_m00_couplers_ARID(0),
m_axi_arlen(3 downto 0) => auto_pc_to_m00_couplers_ARLEN(3 downto 0),
m_axi_arlock(1 downto 0) => auto_pc_to_m00_couplers_ARLOCK(1 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_m00_couplers_ARREADY,
m_axi_arsize(2 downto 0) => auto_pc_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_pc_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_pc_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => auto_pc_to_m00_couplers_AWID(0),
m_axi_awlen(3 downto 0) => auto_pc_to_m00_couplers_AWLEN(3 downto 0),
m_axi_awlock(1 downto 0) => auto_pc_to_m00_couplers_AWLOCK(1 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_pc_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_pc_to_m00_couplers_AWREADY,
m_axi_awsize(2 downto 0) => auto_pc_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID,
m_axi_bid(0) => auto_pc_to_m00_couplers_BID(0),
m_axi_bready => auto_pc_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_m00_couplers_RDATA(31 downto 0),
m_axi_rid(0) => auto_pc_to_m00_couplers_RID(0),
m_axi_rlast => auto_pc_to_m00_couplers_RLAST,
m_axi_rready => auto_pc_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_m00_couplers_WDATA(31 downto 0),
m_axi_wid(0) => auto_pc_to_m00_couplers_WID(0),
m_axi_wlast => auto_pc_to_m00_couplers_WLAST,
m_axi_wready => auto_pc_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_m00_couplers_WVALID,
s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(0) => m00_couplers_to_auto_pc_ARID(0),
s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(0) => m00_couplers_to_auto_pc_AWID(0),
s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m00_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID,
s_axi_bid(0) => m00_couplers_to_auto_pc_BID(0),
s_axi_bready => m00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => m00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(0) => m00_couplers_to_auto_pc_RID(0),
s_axi_rlast => m00_couplers_to_auto_pc_RLAST,
s_axi_rready => m00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => m00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wlast => m00_couplers_to_auto_pc_WLAST,
s_axi_wready => m00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => m00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => m00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_23E6MH is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_23E6MH;
architecture STRUCTURE of m00_couplers_imp_23E6MH is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_169O6FR is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m01_couplers_imp_169O6FR;
architecture STRUCTURE of m01_couplers_imp_169O6FR is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m01_couplers_to_m01_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m01_couplers_to_m01_couplers_AWVALID(0);
M_AXI_bready(0) <= m01_couplers_to_m01_couplers_BREADY(0);
M_AXI_rready(0) <= m01_couplers_to_m01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wvalid(0) <= m01_couplers_to_m01_couplers_WVALID(0);
S_AXI_arready(0) <= m01_couplers_to_m01_couplers_ARREADY(0);
S_AXI_awready(0) <= m01_couplers_to_m01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m01_couplers_to_m01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m01_couplers_to_m01_couplers_RVALID(0);
S_AXI_wready(0) <= m01_couplers_to_m01_couplers_WREADY(0);
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARREADY(0) <= M_AXI_arready(0);
m01_couplers_to_m01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWREADY(0) <= M_AXI_awready(0);
m01_couplers_to_m01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m01_couplers_to_m01_couplers_BREADY(0) <= S_AXI_bready(0);
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID(0) <= M_AXI_bvalid(0);
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY(0) <= S_AXI_rready(0);
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID(0) <= M_AXI_rvalid(0);
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY(0) <= M_AXI_wready(0);
m01_couplers_to_m01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1TCVZ15 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1TCVZ15;
architecture STRUCTURE of s00_couplers_imp_1TCVZ15 is
component design_TEST_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_TEST_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_TEST_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_NVS4CK is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end s00_couplers_imp_NVS4CK;
architecture STRUCTURE of s00_couplers_imp_NVS4CK is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= s00_couplers_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= s00_couplers_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= s00_couplers_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= s00_couplers_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rlast(0) <= s00_couplers_to_s00_couplers_RLAST(0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_s00_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_s00_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
s00_couplers_to_s00_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RLAST(0) <= M_AXI_rlast(0);
s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_1JZLSPM is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end s01_couplers_imp_1JZLSPM;
architecture STRUCTURE of s01_couplers_imp_1JZLSPM is
signal s01_couplers_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_awaddr(31 downto 0) <= s01_couplers_to_s01_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= s01_couplers_to_s01_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= s01_couplers_to_s01_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= s01_couplers_to_s01_couplers_AWLEN(7 downto 0);
M_AXI_awprot(2 downto 0) <= s01_couplers_to_s01_couplers_AWPROT(2 downto 0);
M_AXI_awsize(2 downto 0) <= s01_couplers_to_s01_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid(0) <= s01_couplers_to_s01_couplers_AWVALID(0);
M_AXI_bready(0) <= s01_couplers_to_s01_couplers_BREADY(0);
M_AXI_wdata(31 downto 0) <= s01_couplers_to_s01_couplers_WDATA(31 downto 0);
M_AXI_wlast(0) <= s01_couplers_to_s01_couplers_WLAST(0);
M_AXI_wstrb(3 downto 0) <= s01_couplers_to_s01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= s01_couplers_to_s01_couplers_WVALID(0);
S_AXI_awready(0) <= s01_couplers_to_s01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= s01_couplers_to_s01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= s01_couplers_to_s01_couplers_BVALID(0);
S_AXI_wready(0) <= s01_couplers_to_s01_couplers_WREADY(0);
s01_couplers_to_s01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s01_couplers_to_s01_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s01_couplers_to_s01_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s01_couplers_to_s01_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s01_couplers_to_s01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s01_couplers_to_s01_couplers_AWREADY(0) <= M_AXI_awready(0);
s01_couplers_to_s01_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s01_couplers_to_s01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
s01_couplers_to_s01_couplers_BREADY(0) <= S_AXI_bready(0);
s01_couplers_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s01_couplers_to_s01_couplers_BVALID(0) <= M_AXI_bvalid(0);
s01_couplers_to_s01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s01_couplers_to_s01_couplers_WLAST(0) <= S_AXI_wlast(0);
s01_couplers_to_s01_couplers_WREADY(0) <= M_AXI_wready(0);
s01_couplers_to_s01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s01_couplers_to_s01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_TEST_axi_mem_intercon_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end design_TEST_axi_mem_intercon_0;
architecture STRUCTURE of design_TEST_axi_mem_intercon_0 is
component design_TEST_xbar_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_TEST_xbar_1;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S01_ACLK_1 : STD_LOGIC;
signal S01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC;
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_arready_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_awready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_bvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 32 );
signal NLW_xbar_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_xbar_s_axi_rvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_wready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
M00_AXI_arid(0) <= m00_couplers_to_axi_mem_intercon_ARID(0);
M00_AXI_arlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0);
M00_AXI_arlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_mem_intercon_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0);
M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
M00_AXI_awid(0) <= m00_couplers_to_axi_mem_intercon_AWID(0);
M00_AXI_awlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0);
M00_AXI_awlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0);
M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_mem_intercon_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_mem_intercon_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_mem_intercon_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(31 downto 0);
M00_AXI_wid(0) <= m00_couplers_to_axi_mem_intercon_WID(0);
M00_AXI_wlast <= m00_couplers_to_axi_mem_intercon_WLAST;
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_mem_intercon_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready(0) <= axi_mem_intercon_to_s00_couplers_ARREADY(0);
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rlast(0) <= axi_mem_intercon_to_s00_couplers_RLAST(0);
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid(0) <= axi_mem_intercon_to_s00_couplers_RVALID(0);
S01_ACLK_1 <= S01_ACLK;
S01_ARESETN_1(0) <= S01_ARESETN(0);
S01_AXI_awready(0) <= axi_mem_intercon_to_s01_couplers_AWREADY(0);
S01_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0);
S01_AXI_bvalid(0) <= axi_mem_intercon_to_s01_couplers_BVALID(0);
S01_AXI_wready(0) <= axi_mem_intercon_to_s01_couplers_WREADY(0);
axi_mem_intercon_ACLK_net <= ACLK;
axi_mem_intercon_ARESETN_net(0) <= ARESETN(0);
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
axi_mem_intercon_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0) <= S01_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0) <= S01_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0) <= S01_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0) <= S01_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWVALID(0) <= S01_AXI_awvalid(0);
axi_mem_intercon_to_s01_couplers_BREADY(0) <= S01_AXI_bready(0);
axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s01_couplers_WLAST(0) <= S01_AXI_wlast(0);
axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s01_couplers_WVALID(0) <= S01_AXI_wvalid(0);
m00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_mem_intercon_BID(5 downto 0) <= M00_AXI_bid(5 downto 0);
m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_mem_intercon_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_axi_mem_intercon_RID(5 downto 0) <= M00_AXI_rid(5 downto 0);
m00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast;
m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_1FMN47O
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
M_AXI_arid(0) => m00_couplers_to_axi_mem_intercon_ARID(0),
M_AXI_arlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0),
M_AXI_arlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0),
M_AXI_arready => m00_couplers_to_axi_mem_intercon_ARREADY,
M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
M_AXI_arvalid => m00_couplers_to_axi_mem_intercon_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
M_AXI_awid(0) => m00_couplers_to_axi_mem_intercon_AWID(0),
M_AXI_awlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0),
M_AXI_awlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0),
M_AXI_awready => m00_couplers_to_axi_mem_intercon_AWREADY,
M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
M_AXI_awvalid => m00_couplers_to_axi_mem_intercon_AWVALID,
M_AXI_bid(5 downto 0) => m00_couplers_to_axi_mem_intercon_BID(5 downto 0),
M_AXI_bready => m00_couplers_to_axi_mem_intercon_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_mem_intercon_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(31 downto 0),
M_AXI_rid(5 downto 0) => m00_couplers_to_axi_mem_intercon_RID(5 downto 0),
M_AXI_rlast => m00_couplers_to_axi_mem_intercon_RLAST,
M_AXI_rready => m00_couplers_to_axi_mem_intercon_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_mem_intercon_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(31 downto 0),
M_AXI_wid(0) => m00_couplers_to_axi_mem_intercon_WID(0),
M_AXI_wlast => m00_couplers_to_axi_mem_intercon_WLAST,
M_AXI_wready => m00_couplers_to_axi_mem_intercon_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_mem_intercon_WVALID,
S_ACLK => axi_mem_intercon_ACLK_net,
S_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => xbar_to_m00_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => xbar_to_m00_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bid(0) => xbar_to_m00_couplers_BID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rid(0) => xbar_to_m00_couplers_RID(0),
S_AXI_rlast => xbar_to_m00_couplers_RLAST,
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wlast => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
s00_couplers: entity work.s00_couplers_imp_NVS4CK
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rlast(0) => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => axi_mem_intercon_to_s00_couplers_ARREADY(0),
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid(0) => axi_mem_intercon_to_s00_couplers_ARVALID(0),
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rlast(0) => axi_mem_intercon_to_s00_couplers_RLAST(0),
S_AXI_rready(0) => axi_mem_intercon_to_s00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => axi_mem_intercon_to_s00_couplers_RVALID(0)
);
s01_couplers: entity work.s01_couplers_imp_1JZLSPM
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s01_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s01_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready(0) => s01_couplers_to_xbar_AWREADY(1),
M_AXI_awsize(2 downto 0) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid(0) => s01_couplers_to_xbar_AWVALID(0),
M_AXI_bready(0) => s01_couplers_to_xbar_BREADY(0),
M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2),
M_AXI_bvalid(0) => s01_couplers_to_xbar_BVALID(1),
M_AXI_wdata(31 downto 0) => s01_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wlast(0) => s01_couplers_to_xbar_WLAST(0),
M_AXI_wready(0) => s01_couplers_to_xbar_WREADY(1),
M_AXI_wstrb(3 downto 0) => s01_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid(0) => s01_couplers_to_xbar_WVALID(0),
S_ACLK => S01_ACLK_1,
S_ARESETN(0) => S01_ARESETN_1(0),
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => axi_mem_intercon_to_s01_couplers_AWREADY(0),
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid(0) => axi_mem_intercon_to_s01_couplers_AWVALID(0),
S_AXI_bready(0) => axi_mem_intercon_to_s01_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => axi_mem_intercon_to_s01_couplers_BVALID(0),
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0),
S_AXI_wlast(0) => axi_mem_intercon_to_s01_couplers_WLAST(0),
S_AXI_wready(0) => axi_mem_intercon_to_s01_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => axi_mem_intercon_to_s01_couplers_WVALID(0)
);
xbar: component design_TEST_xbar_1
port map (
aclk => axi_mem_intercon_ACLK_net,
aresetn => axi_mem_intercon_ARESETN_net(0),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(0) => xbar_to_m00_couplers_ARID(0),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => xbar_to_m00_couplers_AWID(0),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bid(0) => xbar_to_m00_couplers_BID(0),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rid(0) => xbar_to_m00_couplers_RID(0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST,
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(63 downto 32) => B"00000000000000000000000000000000",
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(3 downto 2) => B"00",
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(7 downto 4) => B"0000",
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(1 downto 0) => B"00",
s_axi_arlen(15 downto 8) => B"00000000",
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(1 downto 0) => B"00",
s_axi_arprot(5 downto 3) => B"000",
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(7 downto 0) => B"00000000",
s_axi_arready(1) => NLW_xbar_s_axi_arready_UNCONNECTED(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(5 downto 3) => B"000",
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(1) => '0',
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(3 downto 2) => s01_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(7 downto 4) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(1 downto 0) => B"00",
s_axi_awlen(15 downto 8) => s01_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(1 downto 0) => B"00",
s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(7 downto 0) => B"00000000",
s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1),
s_axi_awready(0) => NLW_xbar_s_axi_awready_UNCONNECTED(0),
s_axi_awsize(5 downto 3) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID(0),
s_axi_awvalid(0) => '0',
s_axi_bid(1 downto 0) => NLW_xbar_s_axi_bid_UNCONNECTED(1 downto 0),
s_axi_bready(1) => s01_couplers_to_xbar_BREADY(0),
s_axi_bready(0) => '0',
s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2),
s_axi_bresp(1 downto 0) => NLW_xbar_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1),
s_axi_bvalid(0) => NLW_xbar_s_axi_bvalid_UNCONNECTED(0),
s_axi_rdata(63 downto 32) => NLW_xbar_s_axi_rdata_UNCONNECTED(63 downto 32),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rid(1 downto 0) => NLW_xbar_s_axi_rid_UNCONNECTED(1 downto 0),
s_axi_rlast(1) => NLW_xbar_s_axi_rlast_UNCONNECTED(1),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(1) => '0',
s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
s_axi_rresp(3 downto 2) => NLW_xbar_s_axi_rresp_UNCONNECTED(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(1) => NLW_xbar_s_axi_rvalid_UNCONNECTED(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(63 downto 32) => s01_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast(1) => s01_couplers_to_xbar_WLAST(0),
s_axi_wlast(0) => '1',
s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1),
s_axi_wready(0) => NLW_xbar_s_axi_wready_UNCONNECTED(0),
s_axi_wstrb(7 downto 4) => s01_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(3 downto 0) => B"1111",
s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID(0),
s_axi_wvalid(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_TEST_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end design_TEST_processing_system7_0_axi_periph_0;
architecture STRUCTURE of design_TEST_processing_system7_0_axi_periph_0 is
component design_TEST_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component design_TEST_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_xbar_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M01_AXI_arvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M01_AXI_awvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M01_AXI_bready(0) <= m01_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M01_AXI_rready(0) <= m01_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_WVALID(0);
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M01_AXI_arready(0);
m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M01_AXI_awready(0);
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M01_AXI_bvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M01_AXI_rvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M01_AXI_wready(0);
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_23E6MH
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_169O6FR
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m01_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m01_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m01_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arready(0) => xbar_to_m01_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awready(0) => xbar_to_m01_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready(0) => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready(0) => xbar_to_m01_couplers_WREADY(0),
S_AXI_wvalid(0) => xbar_to_m01_couplers_WVALID(1)
);
s00_couplers: entity work.s00_couplers_imp_1TCVZ15
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component design_TEST_xbar_0
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net(0),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(5 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(5 downto 0),
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY(0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(5 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(5 downto 0),
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY(0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID(0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID(0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(1) => xbar_to_m01_couplers_WREADY(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(7 downto 0) => NLW_xbar_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_TEST is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of design_TEST : entity is "design_TEST,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_TEST,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=16,numReposBlks=8,numNonXlnxBlks=0,numHierBlks=8,maxHierDepth=0,da_axi4_cnt=4,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of design_TEST : entity is "design_TEST.hwdef";
end design_TEST;
architecture STRUCTURE of design_TEST is
component design_TEST_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component design_TEST_processing_system7_0_0;
component design_TEST_axi_dma_0_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
mm2s_introut : out STD_LOGIC
);
end component design_TEST_axi_dma_0_0;
component design_TEST_axi_dma_1_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s2mm_prmry_reset_out_n : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC;
s_axis_s2mm_tlast : in STD_LOGIC;
s2mm_introut : out STD_LOGIC
);
end component design_TEST_axi_dma_1_0;
component design_TEST_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_TEST_rst_processing_system7_0_100M_0;
signal axi_dma_0_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_0_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_0_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_1_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_1_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWVALID : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_BREADY : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_1_M_AXI_S2MM_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_1_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_1_M_AXI_S2MM_WLAST : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_1_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_1_M_AXI_S2MM_WVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_WID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axi_dma_0_mm2s_introut_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_1_s2mm_introut_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_1_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
axi_dma_0: component design_TEST_axi_dma_0_0
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_0_M_AXI_MM2S_ARREADY(0),
m_axi_mm2s_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_0_M_AXI_MM2S_RLAST(0),
m_axi_mm2s_rready => axi_dma_0_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_0_M_AXI_MM2S_RVALID(0),
m_axis_mm2s_tdata(31 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => axi_dma_0_M_AXIS_MM2S_TKEEP(3 downto 0),
m_axis_mm2s_tlast => axi_dma_0_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_dma_0_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID,
mm2s_introut => NLW_axi_dma_0_mm2s_introut_UNCONNECTED,
mm2s_prmry_reset_out_n => NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
s_axi_lite_bready => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID(0)
);
axi_dma_1: component design_TEST_axi_dma_1_0
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0,
m_axi_s2mm_awaddr(31 downto 0) => axi_dma_1_M_AXI_S2MM_AWADDR(31 downto 0),
m_axi_s2mm_awburst(1 downto 0) => axi_dma_1_M_AXI_S2MM_AWBURST(1 downto 0),
m_axi_s2mm_awcache(3 downto 0) => axi_dma_1_M_AXI_S2MM_AWCACHE(3 downto 0),
m_axi_s2mm_awlen(7 downto 0) => axi_dma_1_M_AXI_S2MM_AWLEN(7 downto 0),
m_axi_s2mm_awprot(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWPROT(2 downto 0),
m_axi_s2mm_awready => axi_dma_1_M_AXI_S2MM_AWREADY(0),
m_axi_s2mm_awsize(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWSIZE(2 downto 0),
m_axi_s2mm_awvalid => axi_dma_1_M_AXI_S2MM_AWVALID,
m_axi_s2mm_bready => axi_dma_1_M_AXI_S2MM_BREADY,
m_axi_s2mm_bresp(1 downto 0) => axi_dma_1_M_AXI_S2MM_BRESP(1 downto 0),
m_axi_s2mm_bvalid => axi_dma_1_M_AXI_S2MM_BVALID(0),
m_axi_s2mm_wdata(31 downto 0) => axi_dma_1_M_AXI_S2MM_WDATA(31 downto 0),
m_axi_s2mm_wlast => axi_dma_1_M_AXI_S2MM_WLAST,
m_axi_s2mm_wready => axi_dma_1_M_AXI_S2MM_WREADY(0),
m_axi_s2mm_wstrb(3 downto 0) => axi_dma_1_M_AXI_S2MM_WSTRB(3 downto 0),
m_axi_s2mm_wvalid => axi_dma_1_M_AXI_S2MM_WVALID,
s2mm_introut => NLW_axi_dma_1_s2mm_introut_UNCONNECTED,
s2mm_prmry_reset_out_n => NLW_axi_dma_1_s2mm_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
s_axi_lite_bready => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID(0),
s_axis_s2mm_tdata(31 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(31 downto 0),
s_axis_s2mm_tkeep(3 downto 0) => axi_dma_0_M_AXIS_MM2S_TKEEP(3 downto 0),
s_axis_s2mm_tlast => axi_dma_0_M_AXIS_MM2S_TLAST,
s_axis_s2mm_tready => axi_dma_0_M_AXIS_MM2S_TREADY,
s_axis_s2mm_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID
);
axi_mem_intercon: entity work.design_TEST_axi_mem_intercon_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(0) => axi_mem_intercon_M00_AXI_ARID(0),
M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
M00_AXI_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(0) => axi_mem_intercon_M00_AXI_AWID(0),
M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
M00_AXI_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
M00_AXI_bid(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
M00_AXI_rid(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST,
M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
M00_AXI_wid(0) => axi_mem_intercon_M00_AXI_WID(0),
M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST,
M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
S00_AXI_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
S00_AXI_arready(0) => axi_dma_0_M_AXI_MM2S_ARREADY(0),
S00_AXI_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
S00_AXI_arvalid(0) => axi_dma_0_M_AXI_MM2S_ARVALID,
S00_AXI_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
S00_AXI_rlast(0) => axi_dma_0_M_AXI_MM2S_RLAST(0),
S00_AXI_rready(0) => axi_dma_0_M_AXI_MM2S_RREADY,
S00_AXI_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
S00_AXI_rvalid(0) => axi_dma_0_M_AXI_MM2S_RVALID(0),
S01_ACLK => processing_system7_0_FCLK_CLK0,
S01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S01_AXI_awaddr(31 downto 0) => axi_dma_1_M_AXI_S2MM_AWADDR(31 downto 0),
S01_AXI_awburst(1 downto 0) => axi_dma_1_M_AXI_S2MM_AWBURST(1 downto 0),
S01_AXI_awcache(3 downto 0) => axi_dma_1_M_AXI_S2MM_AWCACHE(3 downto 0),
S01_AXI_awlen(7 downto 0) => axi_dma_1_M_AXI_S2MM_AWLEN(7 downto 0),
S01_AXI_awprot(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWPROT(2 downto 0),
S01_AXI_awready(0) => axi_dma_1_M_AXI_S2MM_AWREADY(0),
S01_AXI_awsize(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWSIZE(2 downto 0),
S01_AXI_awvalid(0) => axi_dma_1_M_AXI_S2MM_AWVALID,
S01_AXI_bready(0) => axi_dma_1_M_AXI_S2MM_BREADY,
S01_AXI_bresp(1 downto 0) => axi_dma_1_M_AXI_S2MM_BRESP(1 downto 0),
S01_AXI_bvalid(0) => axi_dma_1_M_AXI_S2MM_BVALID(0),
S01_AXI_wdata(31 downto 0) => axi_dma_1_M_AXI_S2MM_WDATA(31 downto 0),
S01_AXI_wlast(0) => axi_dma_1_M_AXI_S2MM_WLAST,
S01_AXI_wready(0) => axi_dma_1_M_AXI_S2MM_WREADY(0),
S01_AXI_wstrb(3 downto 0) => axi_dma_1_M_AXI_S2MM_WSTRB(3 downto 0),
S01_AXI_wvalid(0) => axi_dma_1_M_AXI_S2MM_WVALID
);
processing_system7_0: component design_TEST_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
IRQ_F2P(0) => '0',
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SDIO0_WP => '0',
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_HP0_ARADDR(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
S_AXI_HP0_ARBURST(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
S_AXI_HP0_ARCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
S_AXI_HP0_ARID(5 downto 1) => B"00000",
S_AXI_HP0_ARID(0) => axi_mem_intercon_M00_AXI_ARID(0),
S_AXI_HP0_ARLEN(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
S_AXI_HP0_ARLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
S_AXI_HP0_ARPROT(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
S_AXI_HP0_ARQOS(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
S_AXI_HP0_ARREADY => axi_mem_intercon_M00_AXI_ARREADY,
S_AXI_HP0_ARSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
S_AXI_HP0_ARVALID => axi_mem_intercon_M00_AXI_ARVALID,
S_AXI_HP0_AWADDR(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
S_AXI_HP0_AWBURST(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
S_AXI_HP0_AWCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
S_AXI_HP0_AWID(5 downto 1) => B"00000",
S_AXI_HP0_AWID(0) => axi_mem_intercon_M00_AXI_AWID(0),
S_AXI_HP0_AWLEN(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
S_AXI_HP0_AWLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
S_AXI_HP0_AWPROT(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
S_AXI_HP0_AWQOS(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
S_AXI_HP0_AWREADY => axi_mem_intercon_M00_AXI_AWREADY,
S_AXI_HP0_AWSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
S_AXI_HP0_AWVALID => axi_mem_intercon_M00_AXI_AWVALID,
S_AXI_HP0_BID(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
S_AXI_HP0_BREADY => axi_mem_intercon_M00_AXI_BREADY,
S_AXI_HP0_BRESP(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
S_AXI_HP0_BVALID => axi_mem_intercon_M00_AXI_BVALID,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
S_AXI_HP0_RLAST => axi_mem_intercon_M00_AXI_RLAST,
S_AXI_HP0_RREADY => axi_mem_intercon_M00_AXI_RREADY,
S_AXI_HP0_RRESP(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
S_AXI_HP0_RVALID => axi_mem_intercon_M00_AXI_RVALID,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
S_AXI_HP0_WID(5 downto 1) => B"00000",
S_AXI_HP0_WID(0) => axi_mem_intercon_M00_AXI_WID(0),
S_AXI_HP0_WLAST => axi_mem_intercon_M00_AXI_WLAST,
S_AXI_HP0_WREADY => axi_mem_intercon_M00_AXI_WREADY,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
S_AXI_HP0_WVALID => axi_mem_intercon_M00_AXI_WVALID,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.design_TEST_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready(0) => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready(0) => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wvalid(0) => processing_system7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready(0) => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid(0) => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
M01_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready(0) => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid(0) => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
M01_AXI_bready(0) => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid(0) => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready(0) => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid(0) => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready(0) => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wvalid(0) => processing_system7_0_axi_periph_M01_AXI_WVALID(0),
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_100M: component design_TEST_rst_processing_system7_0_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
end STRUCTURE;
| gpl-3.0 | ccdb7558ab2d22c92ad91fa61d930b7d | 0.67293 | 2.776087 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_fcmp_32ns_32ns_1_1.vhd | 6 | 4,446 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fcmp_32ns_32ns_1_1 is
generic (
ID : integer := 6;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 1
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
opcode : in std_logic_vector(4 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fcmp_32ns_32ns_1_1 is
--------------------- Component ---------------------
component ANN_ap_fcmp_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
s_axis_operation_tvalid : in std_logic;
s_axis_operation_tdata : in std_logic_vector(7 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0)
);
end component;
--------------------- Constant ----------------------
-- AutoESL opcode
constant AP_OEQ : std_logic_vector(4 downto 0) := "00001";
constant AP_OGT : std_logic_vector(4 downto 0) := "00010";
constant AP_OGE : std_logic_vector(4 downto 0) := "00011";
constant AP_OLT : std_logic_vector(4 downto 0) := "00100";
constant AP_OLE : std_logic_vector(4 downto 0) := "00101";
constant AP_ONE : std_logic_vector(4 downto 0) := "00110";
constant AP_UNO : std_logic_vector(4 downto 0) := "01000";
-- FPV6 opcode
constant OP_EQ : std_logic_vector(7 downto 0) := "00010100";
constant OP_GT : std_logic_vector(7 downto 0) := "00100100";
constant OP_GE : std_logic_vector(7 downto 0) := "00110100";
constant OP_LT : std_logic_vector(7 downto 0) := "00001100";
constant OP_LE : std_logic_vector(7 downto 0) := "00011100";
constant OP_NE : std_logic_vector(7 downto 0) := "00101100";
constant OP_UO : std_logic_vector(7 downto 0) := "00000100";
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal op_tvalid : std_logic;
signal op_tdata : std_logic_vector(7 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(7 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fcmp_0_no_dsp_32_u : component ANN_ap_fcmp_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
s_axis_operation_tvalid => op_tvalid,
s_axis_operation_tdata => op_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1;
op_tvalid <= '1';
dout <= r_tdata(0 downto 0);
--------------------- Opcode ------------------------
process (opcode) begin
case (opcode) is
when AP_OEQ => op_tdata <= OP_EQ;
when AP_OGT => op_tdata <= OP_GT;
when AP_OGE => op_tdata <= OP_GE;
when AP_OLT => op_tdata <= OP_LT;
when AP_OLE => op_tdata <= OP_LE;
when AP_ONE => op_tdata <= OP_NE;
when AP_UNO => op_tdata <= OP_UO;
when others => op_tdata <= OP_EQ;
end case;
end process;
end architecture;
| gpl-3.0 | 886bf62aa2e20d3d34419bf6ac0a6ac6 | 0.51417 | 3.438515 | false | false | false | false |
aprgl/jtag_socket | vjtag_port.vhd | 1 | 2,981 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library vjtag;
--============================================================================
-- Virtual JTAG Port Generation Block
--============================================================================
-- Generate a vuirt JTAG block to allow control and data to flow from
-- the FPGA under development.
-- Version: 0.0.0 Initial Commit - vjtag port - compiles -Shaun
-- Version: 0.0.1 More general interfaces -Shaun
------------------------------------------------------------------------------
entity vjtag_port is
Port (
ir_out : out std_logic_vector(7 downto 0) := X"00";
dr_out : out std_logic_vector(31 downto 0) := X"00000000"
);
end entity vjtag_port;
architecture rtl of vjtag_port is
signal tdi_sig, tdo_sig, tck, sdr_valid, ir_solid, dr_solid, data_ready, load_dr : std_logic;
signal ir, ir_sig : std_logic_vector(7 downto 0);
signal dr : std_logic_vector(31 downto 0) := X"87654321";
-- Memory --
type mem is array(0 to 31) OF std_logic_vector(31 downto 0);
signal ram_block : mem;
signal write_address, read_address : std_logic_vector(4 downto 0);
signal data, q :std_logic_vector(31 downto 0);
signal we : std_logic;
begin
-- Instantiate RAM Block for testing
mem_proc: process (tck) begin
if (rising_edge(tck)) then
if (we = '1') then
ram_block(to_integer(unsigned(write_address))) <= data;
end if;
q <= ram_block(to_integer(unsigned(read_address)));
end if;
end process;
-- The instantiation will create connect this block to the JTAG chain
virtual_jtag : entity vjtag.vjtag(rtl)
port map(
TDI => tdi_sig,
TDO => tdo_sig,
TCK => tck,
IR_IN => ir_sig,
virtual_state_uir => ir_solid,
virtual_state_udr => data_ready,
virtual_state_sdr => sdr_valid,
virtual_state_cdr => load_dr
);
-- Virtual JTAG
tdo_sig <= dr(0);
-- IR latch process
ir_proc: process (tck, ir_solid) begin
if (rising_edge(tck)) then
if (ir_solid = '1') then
ir <= ir_sig;
end if;
end if;
end process;
-- Virtual JTAG FPGA -> CPU Data
data_out_proc: process (tck, tdi_sig, load_dr, sdr_valid) begin
if (rising_edge(tck)) then
if (load_dr = '1') then
if(ir = X"00") then
dr <= X"12345678";
elsif(ir = X"01") then
dr <= X"87654321";
elsif(ir = X"02") then
dr <= X"c0ffee" & ir;
else
dr <= q;
end if;
elsif (sdr_valid = '1') then
dr <= (tdi_sig & dr(31 downto 1));
end if;
end if;
end process;
-- Virtual JTAG CPU -> FPGA Data
data_in_proc: process (data_ready) begin
if (data_ready = '1') then
if(ir(0) = '1') then
write_address <= ir(5 downto 1);
data <= dr;
we <= '1';
else
read_address <= ir(5 downto 1);
we <= '0';
end if;
end if;
end process;
--==============================================
-- Stateless Signals
--==============================================
ir_out <= ir(7 downto 0);
end architecture rtl;
| gpl-3.0 | b21fa840b1d95172e180767f2b9bc959 | 0.560215 | 3.085921 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_ST_WandB.vhd | 7 | 3,065 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ANN_ST_WandB_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 13;
mem_size : integer := 6560
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of ANN_ST_WandB_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity ANN_ST_WandB is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 6560;
AddressWidth : INTEGER := 13);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of ANN_ST_WandB is
component ANN_ST_WandB_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
ANN_ST_WandB_ram_U : component ANN_ST_WandB_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
| gpl-3.0 | 3c48fad235e16495da20d47ae086e74e | 0.538662 | 3.555684 | false | false | false | false |
airlog/vhdl-rc4 | src/memory_tb.vhd | 1 | 2,116 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY memory_tb IS
END memory_tb;
ARCHITECTURE behavior OF memory_tb IS
-- Component Declaration for the Unit Under Test (UUT)
component memory
generic (
width: integer := 8; -- ilosc bitow adresów
size: integer := 256 -- rozmiar pamieci w bajtach
);
port (
SET: in STD_LOGIC; -- tryb pracy
CLK: in STD_LOGIC; -- zegar
INDEX: in STD_LOGIC_VECTOR ((width - 1) downto 0); -- indeks elementu tablicy
INVALUE: in STD_LOGIC_VECTOR ((width - 1) downto 0); -- wartoæ wejciowa
OUTVALUE: out STD_LOGIC_VECTOR ((width - 1) downto 0) -- wartoæ wyjciowa
);
end component;
--Inputs
signal SET : std_logic := '0';
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal INDEX : std_logic_vector(7 downto 0) := (others => '0');
signal INVALUE : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal OUTVALUE : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: memory PORT MAP (
SET => SET,
CLK => CLK,
RST => RST,
INDEX => INDEX,
INVALUE => INVALUE,
OUTVALUE => OUTVALUE
);
-- Clock process definitions
CLK_process : process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc : process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- ustawianie wartoci tablicy
set <= '1';
for i in 0 to 255 loop
index <= conv_std_logic_vector(i, 8);
invalue <= conv_std_logic_vector(i, 8);
wait for clk_period;
end loop;
invalue <= (others => '0');
-- odczytywanie wartoci tablicy
set <= '0';
for i in 0 to 255 loop
index <= conv_std_logic_vector(i, 8);
wait for clk_period;
assert (outvalue = conv_std_logic_vector(i, 8))
report "Oczekiwana inna wartosc"
severity failure;
end loop;
wait;
end process;
END;
| mit | 65643a490234bed5c9c6a359d06a3fc9 | 0.607278 | 3.005682 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_xlconcat_0_0/synth/design_SWandHW_standalone_xlconcat_0_0.vhd | 1 | 9,085 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlconcat:2.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconcat;
ENTITY design_SWandHW_standalone_xlconcat_0_0 IS
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END design_SWandHW_standalone_xlconcat_0_0;
ARCHITECTURE design_SWandHW_standalone_xlconcat_0_0_arch OF design_SWandHW_standalone_xlconcat_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_xlconcat_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconcat IS
GENERIC (
IN0_WIDTH : INTEGER;
IN1_WIDTH : INTEGER;
IN2_WIDTH : INTEGER;
IN3_WIDTH : INTEGER;
IN4_WIDTH : INTEGER;
IN5_WIDTH : INTEGER;
IN6_WIDTH : INTEGER;
IN7_WIDTH : INTEGER;
IN8_WIDTH : INTEGER;
IN9_WIDTH : INTEGER;
IN10_WIDTH : INTEGER;
IN11_WIDTH : INTEGER;
IN12_WIDTH : INTEGER;
IN13_WIDTH : INTEGER;
IN14_WIDTH : INTEGER;
IN15_WIDTH : INTEGER;
IN16_WIDTH : INTEGER;
IN17_WIDTH : INTEGER;
IN18_WIDTH : INTEGER;
IN19_WIDTH : INTEGER;
IN20_WIDTH : INTEGER;
IN21_WIDTH : INTEGER;
IN22_WIDTH : INTEGER;
IN23_WIDTH : INTEGER;
IN24_WIDTH : INTEGER;
IN25_WIDTH : INTEGER;
IN26_WIDTH : INTEGER;
IN27_WIDTH : INTEGER;
IN28_WIDTH : INTEGER;
IN29_WIDTH : INTEGER;
IN30_WIDTH : INTEGER;
IN31_WIDTH : INTEGER;
dout_width : INTEGER;
NUM_PORTS : INTEGER
);
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END COMPONENT xlconcat;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_xlconcat_0_0_arch: ARCHITECTURE IS "xlconcat,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_xlconcat_0_0_arch : ARCHITECTURE IS "design_SWandHW_standalone_xlconcat_0_0,xlconcat,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SWandHW_standalone_xlconcat_0_0_arch: ARCHITECTURE IS "design_SWandHW_standalone_xlconcat_0_0,xlconcat,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=6,NUM_PORTS=6}";
BEGIN
U0 : xlconcat
GENERIC MAP (
IN0_WIDTH => 1,
IN1_WIDTH => 1,
IN2_WIDTH => 1,
IN3_WIDTH => 1,
IN4_WIDTH => 1,
IN5_WIDTH => 1,
IN6_WIDTH => 1,
IN7_WIDTH => 1,
IN8_WIDTH => 1,
IN9_WIDTH => 1,
IN10_WIDTH => 1,
IN11_WIDTH => 1,
IN12_WIDTH => 1,
IN13_WIDTH => 1,
IN14_WIDTH => 1,
IN15_WIDTH => 1,
IN16_WIDTH => 1,
IN17_WIDTH => 1,
IN18_WIDTH => 1,
IN19_WIDTH => 1,
IN20_WIDTH => 1,
IN21_WIDTH => 1,
IN22_WIDTH => 1,
IN23_WIDTH => 1,
IN24_WIDTH => 1,
IN25_WIDTH => 1,
IN26_WIDTH => 1,
IN27_WIDTH => 1,
IN28_WIDTH => 1,
IN29_WIDTH => 1,
IN30_WIDTH => 1,
IN31_WIDTH => 1,
dout_width => 6,
NUM_PORTS => 6
)
PORT MAP (
In0 => In0,
In1 => In1,
In2 => In2,
In3 => In3,
In4 => In4,
In5 => In5,
In6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dout => dout
);
END design_SWandHW_standalone_xlconcat_0_0_arch;
| gpl-3.0 | d4fe28cd48741dd6c1b5f5d9fbd87a7f | 0.651624 | 3.26329 | false | false | false | false |
makestuff/spi-talk | vhdl/fifo-gen/fifo_wrapper_altera.vhdl | 1 | 1,923 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_wrapper is
port(
-- Clock and depth
clk_in : in std_logic;
-- Data is clocked into the FIFO on each clock edge where both valid & ready are high
inputData_in : in std_logic_vector(7 downto 0);
inputValid_in : in std_logic;
inputReady_out : out std_logic;
-- Data is clocked out of the FIFO on each clock edge where both valid & ready are high
outputData_out : out std_logic_vector(7 downto 0);
outputValid_out : out std_logic;
outputReady_in : in std_logic
);
end entity;
architecture structural of fifo_wrapper is
signal inputFull : std_logic;
signal outputEmpty : std_logic;
begin
-- Invert "full/empty" signals to give "ready/valid" signals
inputReady_out <= not(inputFull);
outputValid_out <= not(outputEmpty);
-- The encapsulated FIFO
fifo : entity work.altera_fifo
port map(
clock => clk_in,
-- Production end
data => inputData_in,
wrreq => inputValid_in,
full => inputFull,
-- Consumption end
q => outputData_out,
empty => outputEmpty,
rdreq => outputReady_in
);
end architecture;
| gpl-3.0 | 7ff09dae38216a1b4415e019b1b6e123 | 0.692148 | 3.655894 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_files/bd/design_TEST/hdl/design_TEST.vhd | 1 | 194,848 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
--Date : Thu Sep 01 17:22:48 2016
--Host : DESKTOP-I329812 running 64-bit major release (build 9200)
--Command : generate_target design_TEST.bd
--Design : design_TEST
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1FMN47O is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_1FMN47O;
architecture STRUCTURE of m00_couplers_imp_1FMN47O is
component design_TEST_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_TEST_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_WID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_WLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_m00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_m00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(0) <= auto_pc_to_m00_couplers_ARID(0);
M_AXI_arlen(3 downto 0) <= auto_pc_to_m00_couplers_ARLEN(3 downto 0);
M_AXI_arlock(1 downto 0) <= auto_pc_to_m00_couplers_ARLOCK(1 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_m00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_m00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_pc_to_m00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_pc_to_m00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(0) <= auto_pc_to_m00_couplers_AWID(0);
M_AXI_awlen(3 downto 0) <= auto_pc_to_m00_couplers_AWLEN(3 downto 0);
M_AXI_awlock(1 downto 0) <= auto_pc_to_m00_couplers_AWLOCK(1 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_pc_to_m00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_pc_to_m00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wid(0) <= auto_pc_to_m00_couplers_WID(0);
M_AXI_wlast <= auto_pc_to_m00_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= auto_pc_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(0) <= m00_couplers_to_auto_pc_BID(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(0) <= m00_couplers_to_auto_pc_RID(0);
S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m00_couplers_to_auto_pc_WREADY;
auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m00_couplers_BID(5 downto 0) <= M_AXI_bid(5 downto 0);
auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_m00_couplers_RID(5 downto 0) <= M_AXI_rid(5 downto 0);
auto_pc_to_m00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_auto_pc_ARID(0) <= S_AXI_arid(0);
m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_auto_pc_AWID(0) <= S_AXI_awid(0);
m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_TEST_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(0) => auto_pc_to_m00_couplers_ARID(0),
m_axi_arlen(3 downto 0) => auto_pc_to_m00_couplers_ARLEN(3 downto 0),
m_axi_arlock(1 downto 0) => auto_pc_to_m00_couplers_ARLOCK(1 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_m00_couplers_ARREADY,
m_axi_arsize(2 downto 0) => auto_pc_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_pc_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_pc_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => auto_pc_to_m00_couplers_AWID(0),
m_axi_awlen(3 downto 0) => auto_pc_to_m00_couplers_AWLEN(3 downto 0),
m_axi_awlock(1 downto 0) => auto_pc_to_m00_couplers_AWLOCK(1 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_pc_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_pc_to_m00_couplers_AWREADY,
m_axi_awsize(2 downto 0) => auto_pc_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID,
m_axi_bid(0) => auto_pc_to_m00_couplers_BID(0),
m_axi_bready => auto_pc_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_m00_couplers_RDATA(31 downto 0),
m_axi_rid(0) => auto_pc_to_m00_couplers_RID(0),
m_axi_rlast => auto_pc_to_m00_couplers_RLAST,
m_axi_rready => auto_pc_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_m00_couplers_WDATA(31 downto 0),
m_axi_wid(0) => auto_pc_to_m00_couplers_WID(0),
m_axi_wlast => auto_pc_to_m00_couplers_WLAST,
m_axi_wready => auto_pc_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_m00_couplers_WVALID,
s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(0) => m00_couplers_to_auto_pc_ARID(0),
s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(0) => m00_couplers_to_auto_pc_AWID(0),
s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m00_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID,
s_axi_bid(0) => m00_couplers_to_auto_pc_BID(0),
s_axi_bready => m00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => m00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(0) => m00_couplers_to_auto_pc_RID(0),
s_axi_rlast => m00_couplers_to_auto_pc_RLAST,
s_axi_rready => m00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => m00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wlast => m00_couplers_to_auto_pc_WLAST,
s_axi_wready => m00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => m00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => m00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_23E6MH is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_23E6MH;
architecture STRUCTURE of m00_couplers_imp_23E6MH is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_169O6FR is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m01_couplers_imp_169O6FR;
architecture STRUCTURE of m01_couplers_imp_169O6FR is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m01_couplers_to_m01_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m01_couplers_to_m01_couplers_AWVALID(0);
M_AXI_bready(0) <= m01_couplers_to_m01_couplers_BREADY(0);
M_AXI_rready(0) <= m01_couplers_to_m01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wvalid(0) <= m01_couplers_to_m01_couplers_WVALID(0);
S_AXI_arready(0) <= m01_couplers_to_m01_couplers_ARREADY(0);
S_AXI_awready(0) <= m01_couplers_to_m01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m01_couplers_to_m01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m01_couplers_to_m01_couplers_RVALID(0);
S_AXI_wready(0) <= m01_couplers_to_m01_couplers_WREADY(0);
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARREADY(0) <= M_AXI_arready(0);
m01_couplers_to_m01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWREADY(0) <= M_AXI_awready(0);
m01_couplers_to_m01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m01_couplers_to_m01_couplers_BREADY(0) <= S_AXI_bready(0);
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID(0) <= M_AXI_bvalid(0);
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY(0) <= S_AXI_rready(0);
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID(0) <= M_AXI_rvalid(0);
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY(0) <= M_AXI_wready(0);
m01_couplers_to_m01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1TCVZ15 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1TCVZ15;
architecture STRUCTURE of s00_couplers_imp_1TCVZ15 is
component design_TEST_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_TEST_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_TEST_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_NVS4CK is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end s00_couplers_imp_NVS4CK;
architecture STRUCTURE of s00_couplers_imp_NVS4CK is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= s00_couplers_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= s00_couplers_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= s00_couplers_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= s00_couplers_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rlast(0) <= s00_couplers_to_s00_couplers_RLAST(0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_s00_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_s00_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
s00_couplers_to_s00_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RLAST(0) <= M_AXI_rlast(0);
s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_1JZLSPM is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end s01_couplers_imp_1JZLSPM;
architecture STRUCTURE of s01_couplers_imp_1JZLSPM is
signal s01_couplers_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_awaddr(31 downto 0) <= s01_couplers_to_s01_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= s01_couplers_to_s01_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= s01_couplers_to_s01_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= s01_couplers_to_s01_couplers_AWLEN(7 downto 0);
M_AXI_awprot(2 downto 0) <= s01_couplers_to_s01_couplers_AWPROT(2 downto 0);
M_AXI_awsize(2 downto 0) <= s01_couplers_to_s01_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid(0) <= s01_couplers_to_s01_couplers_AWVALID(0);
M_AXI_bready(0) <= s01_couplers_to_s01_couplers_BREADY(0);
M_AXI_wdata(31 downto 0) <= s01_couplers_to_s01_couplers_WDATA(31 downto 0);
M_AXI_wlast(0) <= s01_couplers_to_s01_couplers_WLAST(0);
M_AXI_wstrb(3 downto 0) <= s01_couplers_to_s01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= s01_couplers_to_s01_couplers_WVALID(0);
S_AXI_awready(0) <= s01_couplers_to_s01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= s01_couplers_to_s01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= s01_couplers_to_s01_couplers_BVALID(0);
S_AXI_wready(0) <= s01_couplers_to_s01_couplers_WREADY(0);
s01_couplers_to_s01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s01_couplers_to_s01_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s01_couplers_to_s01_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s01_couplers_to_s01_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s01_couplers_to_s01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s01_couplers_to_s01_couplers_AWREADY(0) <= M_AXI_awready(0);
s01_couplers_to_s01_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s01_couplers_to_s01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
s01_couplers_to_s01_couplers_BREADY(0) <= S_AXI_bready(0);
s01_couplers_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s01_couplers_to_s01_couplers_BVALID(0) <= M_AXI_bvalid(0);
s01_couplers_to_s01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s01_couplers_to_s01_couplers_WLAST(0) <= S_AXI_wlast(0);
s01_couplers_to_s01_couplers_WREADY(0) <= M_AXI_wready(0);
s01_couplers_to_s01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s01_couplers_to_s01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_TEST_axi_mem_intercon_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end design_TEST_axi_mem_intercon_0;
architecture STRUCTURE of design_TEST_axi_mem_intercon_0 is
component design_TEST_xbar_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_TEST_xbar_1;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S01_ACLK_1 : STD_LOGIC;
signal S01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC;
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_arready_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_awready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_bvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 32 );
signal NLW_xbar_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_xbar_s_axi_rvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_wready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
M00_AXI_arid(0) <= m00_couplers_to_axi_mem_intercon_ARID(0);
M00_AXI_arlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0);
M00_AXI_arlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_mem_intercon_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0);
M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
M00_AXI_awid(0) <= m00_couplers_to_axi_mem_intercon_AWID(0);
M00_AXI_awlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0);
M00_AXI_awlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0);
M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_mem_intercon_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_mem_intercon_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_mem_intercon_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(31 downto 0);
M00_AXI_wid(0) <= m00_couplers_to_axi_mem_intercon_WID(0);
M00_AXI_wlast <= m00_couplers_to_axi_mem_intercon_WLAST;
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_mem_intercon_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready(0) <= axi_mem_intercon_to_s00_couplers_ARREADY(0);
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rlast(0) <= axi_mem_intercon_to_s00_couplers_RLAST(0);
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid(0) <= axi_mem_intercon_to_s00_couplers_RVALID(0);
S01_ACLK_1 <= S01_ACLK;
S01_ARESETN_1(0) <= S01_ARESETN(0);
S01_AXI_awready(0) <= axi_mem_intercon_to_s01_couplers_AWREADY(0);
S01_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0);
S01_AXI_bvalid(0) <= axi_mem_intercon_to_s01_couplers_BVALID(0);
S01_AXI_wready(0) <= axi_mem_intercon_to_s01_couplers_WREADY(0);
axi_mem_intercon_ACLK_net <= ACLK;
axi_mem_intercon_ARESETN_net(0) <= ARESETN(0);
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
axi_mem_intercon_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0) <= S01_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0) <= S01_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0) <= S01_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0) <= S01_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWVALID(0) <= S01_AXI_awvalid(0);
axi_mem_intercon_to_s01_couplers_BREADY(0) <= S01_AXI_bready(0);
axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s01_couplers_WLAST(0) <= S01_AXI_wlast(0);
axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s01_couplers_WVALID(0) <= S01_AXI_wvalid(0);
m00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_mem_intercon_BID(5 downto 0) <= M00_AXI_bid(5 downto 0);
m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_mem_intercon_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_axi_mem_intercon_RID(5 downto 0) <= M00_AXI_rid(5 downto 0);
m00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast;
m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_1FMN47O
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
M_AXI_arid(0) => m00_couplers_to_axi_mem_intercon_ARID(0),
M_AXI_arlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0),
M_AXI_arlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0),
M_AXI_arready => m00_couplers_to_axi_mem_intercon_ARREADY,
M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
M_AXI_arvalid => m00_couplers_to_axi_mem_intercon_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
M_AXI_awid(0) => m00_couplers_to_axi_mem_intercon_AWID(0),
M_AXI_awlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0),
M_AXI_awlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0),
M_AXI_awready => m00_couplers_to_axi_mem_intercon_AWREADY,
M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
M_AXI_awvalid => m00_couplers_to_axi_mem_intercon_AWVALID,
M_AXI_bid(5 downto 0) => m00_couplers_to_axi_mem_intercon_BID(5 downto 0),
M_AXI_bready => m00_couplers_to_axi_mem_intercon_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_mem_intercon_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(31 downto 0),
M_AXI_rid(5 downto 0) => m00_couplers_to_axi_mem_intercon_RID(5 downto 0),
M_AXI_rlast => m00_couplers_to_axi_mem_intercon_RLAST,
M_AXI_rready => m00_couplers_to_axi_mem_intercon_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_mem_intercon_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(31 downto 0),
M_AXI_wid(0) => m00_couplers_to_axi_mem_intercon_WID(0),
M_AXI_wlast => m00_couplers_to_axi_mem_intercon_WLAST,
M_AXI_wready => m00_couplers_to_axi_mem_intercon_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_mem_intercon_WVALID,
S_ACLK => axi_mem_intercon_ACLK_net,
S_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => xbar_to_m00_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => xbar_to_m00_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bid(0) => xbar_to_m00_couplers_BID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rid(0) => xbar_to_m00_couplers_RID(0),
S_AXI_rlast => xbar_to_m00_couplers_RLAST,
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wlast => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
s00_couplers: entity work.s00_couplers_imp_NVS4CK
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rlast(0) => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => axi_mem_intercon_to_s00_couplers_ARREADY(0),
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid(0) => axi_mem_intercon_to_s00_couplers_ARVALID(0),
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rlast(0) => axi_mem_intercon_to_s00_couplers_RLAST(0),
S_AXI_rready(0) => axi_mem_intercon_to_s00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => axi_mem_intercon_to_s00_couplers_RVALID(0)
);
s01_couplers: entity work.s01_couplers_imp_1JZLSPM
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s01_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s01_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready(0) => s01_couplers_to_xbar_AWREADY(1),
M_AXI_awsize(2 downto 0) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid(0) => s01_couplers_to_xbar_AWVALID(0),
M_AXI_bready(0) => s01_couplers_to_xbar_BREADY(0),
M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2),
M_AXI_bvalid(0) => s01_couplers_to_xbar_BVALID(1),
M_AXI_wdata(31 downto 0) => s01_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wlast(0) => s01_couplers_to_xbar_WLAST(0),
M_AXI_wready(0) => s01_couplers_to_xbar_WREADY(1),
M_AXI_wstrb(3 downto 0) => s01_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid(0) => s01_couplers_to_xbar_WVALID(0),
S_ACLK => S01_ACLK_1,
S_ARESETN(0) => S01_ARESETN_1(0),
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => axi_mem_intercon_to_s01_couplers_AWREADY(0),
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid(0) => axi_mem_intercon_to_s01_couplers_AWVALID(0),
S_AXI_bready(0) => axi_mem_intercon_to_s01_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => axi_mem_intercon_to_s01_couplers_BVALID(0),
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0),
S_AXI_wlast(0) => axi_mem_intercon_to_s01_couplers_WLAST(0),
S_AXI_wready(0) => axi_mem_intercon_to_s01_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => axi_mem_intercon_to_s01_couplers_WVALID(0)
);
xbar: component design_TEST_xbar_1
port map (
aclk => axi_mem_intercon_ACLK_net,
aresetn => axi_mem_intercon_ARESETN_net(0),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(0) => xbar_to_m00_couplers_ARID(0),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => xbar_to_m00_couplers_AWID(0),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bid(0) => xbar_to_m00_couplers_BID(0),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rid(0) => xbar_to_m00_couplers_RID(0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST,
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(63 downto 32) => B"00000000000000000000000000000000",
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(3 downto 2) => B"00",
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(7 downto 4) => B"0000",
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(1 downto 0) => B"00",
s_axi_arlen(15 downto 8) => B"00000000",
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(1 downto 0) => B"00",
s_axi_arprot(5 downto 3) => B"000",
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(7 downto 0) => B"00000000",
s_axi_arready(1) => NLW_xbar_s_axi_arready_UNCONNECTED(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(5 downto 3) => B"000",
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(1) => '0',
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(3 downto 2) => s01_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(7 downto 4) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(1 downto 0) => B"00",
s_axi_awlen(15 downto 8) => s01_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(1 downto 0) => B"00",
s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(7 downto 0) => B"00000000",
s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1),
s_axi_awready(0) => NLW_xbar_s_axi_awready_UNCONNECTED(0),
s_axi_awsize(5 downto 3) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID(0),
s_axi_awvalid(0) => '0',
s_axi_bid(1 downto 0) => NLW_xbar_s_axi_bid_UNCONNECTED(1 downto 0),
s_axi_bready(1) => s01_couplers_to_xbar_BREADY(0),
s_axi_bready(0) => '0',
s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2),
s_axi_bresp(1 downto 0) => NLW_xbar_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1),
s_axi_bvalid(0) => NLW_xbar_s_axi_bvalid_UNCONNECTED(0),
s_axi_rdata(63 downto 32) => NLW_xbar_s_axi_rdata_UNCONNECTED(63 downto 32),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rid(1 downto 0) => NLW_xbar_s_axi_rid_UNCONNECTED(1 downto 0),
s_axi_rlast(1) => NLW_xbar_s_axi_rlast_UNCONNECTED(1),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(1) => '0',
s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
s_axi_rresp(3 downto 2) => NLW_xbar_s_axi_rresp_UNCONNECTED(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(1) => NLW_xbar_s_axi_rvalid_UNCONNECTED(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(63 downto 32) => s01_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast(1) => s01_couplers_to_xbar_WLAST(0),
s_axi_wlast(0) => '1',
s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1),
s_axi_wready(0) => NLW_xbar_s_axi_wready_UNCONNECTED(0),
s_axi_wstrb(7 downto 4) => s01_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(3 downto 0) => B"1111",
s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID(0),
s_axi_wvalid(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_TEST_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end design_TEST_processing_system7_0_axi_periph_0;
architecture STRUCTURE of design_TEST_processing_system7_0_axi_periph_0 is
component design_TEST_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component design_TEST_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_xbar_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M01_AXI_arvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M01_AXI_awvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M01_AXI_bready(0) <= m01_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M01_AXI_rready(0) <= m01_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_WVALID(0);
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M01_AXI_arready(0);
m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M01_AXI_awready(0);
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M01_AXI_bvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M01_AXI_rvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M01_AXI_wready(0);
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_23E6MH
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_169O6FR
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m01_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m01_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m01_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arready(0) => xbar_to_m01_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awready(0) => xbar_to_m01_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready(0) => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready(0) => xbar_to_m01_couplers_WREADY(0),
S_AXI_wvalid(0) => xbar_to_m01_couplers_WVALID(1)
);
s00_couplers: entity work.s00_couplers_imp_1TCVZ15
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component design_TEST_xbar_0
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net(0),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(5 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(5 downto 0),
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY(0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(5 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(5 downto 0),
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY(0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID(0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID(0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(1) => xbar_to_m01_couplers_WREADY(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(7 downto 0) => NLW_xbar_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_TEST is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of design_TEST : entity is "design_TEST,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_TEST,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=16,numReposBlks=8,numNonXlnxBlks=0,numHierBlks=8,maxHierDepth=0,da_axi4_cnt=4,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of design_TEST : entity is "design_TEST.hwdef";
end design_TEST;
architecture STRUCTURE of design_TEST is
component design_TEST_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component design_TEST_processing_system7_0_0;
component design_TEST_axi_dma_0_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
mm2s_introut : out STD_LOGIC
);
end component design_TEST_axi_dma_0_0;
component design_TEST_axi_dma_1_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s2mm_prmry_reset_out_n : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC;
s_axis_s2mm_tlast : in STD_LOGIC;
s2mm_introut : out STD_LOGIC
);
end component design_TEST_axi_dma_1_0;
component design_TEST_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_TEST_rst_processing_system7_0_100M_0;
signal axi_dma_0_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_0_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_0_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_1_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_1_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWVALID : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_BREADY : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_1_M_AXI_S2MM_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_1_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_1_M_AXI_S2MM_WLAST : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_1_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_1_M_AXI_S2MM_WVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_WID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axi_dma_0_mm2s_introut_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_1_s2mm_introut_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_1_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
axi_dma_0: component design_TEST_axi_dma_0_0
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_0_M_AXI_MM2S_ARREADY(0),
m_axi_mm2s_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_0_M_AXI_MM2S_RLAST(0),
m_axi_mm2s_rready => axi_dma_0_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_0_M_AXI_MM2S_RVALID(0),
m_axis_mm2s_tdata(31 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => axi_dma_0_M_AXIS_MM2S_TKEEP(3 downto 0),
m_axis_mm2s_tlast => axi_dma_0_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_dma_0_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID,
mm2s_introut => NLW_axi_dma_0_mm2s_introut_UNCONNECTED,
mm2s_prmry_reset_out_n => NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
s_axi_lite_bready => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID(0)
);
axi_dma_1: component design_TEST_axi_dma_1_0
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0,
m_axi_s2mm_awaddr(31 downto 0) => axi_dma_1_M_AXI_S2MM_AWADDR(31 downto 0),
m_axi_s2mm_awburst(1 downto 0) => axi_dma_1_M_AXI_S2MM_AWBURST(1 downto 0),
m_axi_s2mm_awcache(3 downto 0) => axi_dma_1_M_AXI_S2MM_AWCACHE(3 downto 0),
m_axi_s2mm_awlen(7 downto 0) => axi_dma_1_M_AXI_S2MM_AWLEN(7 downto 0),
m_axi_s2mm_awprot(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWPROT(2 downto 0),
m_axi_s2mm_awready => axi_dma_1_M_AXI_S2MM_AWREADY(0),
m_axi_s2mm_awsize(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWSIZE(2 downto 0),
m_axi_s2mm_awvalid => axi_dma_1_M_AXI_S2MM_AWVALID,
m_axi_s2mm_bready => axi_dma_1_M_AXI_S2MM_BREADY,
m_axi_s2mm_bresp(1 downto 0) => axi_dma_1_M_AXI_S2MM_BRESP(1 downto 0),
m_axi_s2mm_bvalid => axi_dma_1_M_AXI_S2MM_BVALID(0),
m_axi_s2mm_wdata(31 downto 0) => axi_dma_1_M_AXI_S2MM_WDATA(31 downto 0),
m_axi_s2mm_wlast => axi_dma_1_M_AXI_S2MM_WLAST,
m_axi_s2mm_wready => axi_dma_1_M_AXI_S2MM_WREADY(0),
m_axi_s2mm_wstrb(3 downto 0) => axi_dma_1_M_AXI_S2MM_WSTRB(3 downto 0),
m_axi_s2mm_wvalid => axi_dma_1_M_AXI_S2MM_WVALID,
s2mm_introut => NLW_axi_dma_1_s2mm_introut_UNCONNECTED,
s2mm_prmry_reset_out_n => NLW_axi_dma_1_s2mm_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
s_axi_lite_bready => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID(0),
s_axis_s2mm_tdata(31 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(31 downto 0),
s_axis_s2mm_tkeep(3 downto 0) => axi_dma_0_M_AXIS_MM2S_TKEEP(3 downto 0),
s_axis_s2mm_tlast => axi_dma_0_M_AXIS_MM2S_TLAST,
s_axis_s2mm_tready => axi_dma_0_M_AXIS_MM2S_TREADY,
s_axis_s2mm_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID
);
axi_mem_intercon: entity work.design_TEST_axi_mem_intercon_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(0) => axi_mem_intercon_M00_AXI_ARID(0),
M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
M00_AXI_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(0) => axi_mem_intercon_M00_AXI_AWID(0),
M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
M00_AXI_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
M00_AXI_bid(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
M00_AXI_rid(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST,
M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
M00_AXI_wid(0) => axi_mem_intercon_M00_AXI_WID(0),
M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST,
M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
S00_AXI_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
S00_AXI_arready(0) => axi_dma_0_M_AXI_MM2S_ARREADY(0),
S00_AXI_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
S00_AXI_arvalid(0) => axi_dma_0_M_AXI_MM2S_ARVALID,
S00_AXI_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
S00_AXI_rlast(0) => axi_dma_0_M_AXI_MM2S_RLAST(0),
S00_AXI_rready(0) => axi_dma_0_M_AXI_MM2S_RREADY,
S00_AXI_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
S00_AXI_rvalid(0) => axi_dma_0_M_AXI_MM2S_RVALID(0),
S01_ACLK => processing_system7_0_FCLK_CLK0,
S01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S01_AXI_awaddr(31 downto 0) => axi_dma_1_M_AXI_S2MM_AWADDR(31 downto 0),
S01_AXI_awburst(1 downto 0) => axi_dma_1_M_AXI_S2MM_AWBURST(1 downto 0),
S01_AXI_awcache(3 downto 0) => axi_dma_1_M_AXI_S2MM_AWCACHE(3 downto 0),
S01_AXI_awlen(7 downto 0) => axi_dma_1_M_AXI_S2MM_AWLEN(7 downto 0),
S01_AXI_awprot(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWPROT(2 downto 0),
S01_AXI_awready(0) => axi_dma_1_M_AXI_S2MM_AWREADY(0),
S01_AXI_awsize(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWSIZE(2 downto 0),
S01_AXI_awvalid(0) => axi_dma_1_M_AXI_S2MM_AWVALID,
S01_AXI_bready(0) => axi_dma_1_M_AXI_S2MM_BREADY,
S01_AXI_bresp(1 downto 0) => axi_dma_1_M_AXI_S2MM_BRESP(1 downto 0),
S01_AXI_bvalid(0) => axi_dma_1_M_AXI_S2MM_BVALID(0),
S01_AXI_wdata(31 downto 0) => axi_dma_1_M_AXI_S2MM_WDATA(31 downto 0),
S01_AXI_wlast(0) => axi_dma_1_M_AXI_S2MM_WLAST,
S01_AXI_wready(0) => axi_dma_1_M_AXI_S2MM_WREADY(0),
S01_AXI_wstrb(3 downto 0) => axi_dma_1_M_AXI_S2MM_WSTRB(3 downto 0),
S01_AXI_wvalid(0) => axi_dma_1_M_AXI_S2MM_WVALID
);
processing_system7_0: component design_TEST_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
IRQ_F2P(0) => '0',
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SDIO0_WP => '0',
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_HP0_ARADDR(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
S_AXI_HP0_ARBURST(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
S_AXI_HP0_ARCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
S_AXI_HP0_ARID(5 downto 1) => B"00000",
S_AXI_HP0_ARID(0) => axi_mem_intercon_M00_AXI_ARID(0),
S_AXI_HP0_ARLEN(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
S_AXI_HP0_ARLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
S_AXI_HP0_ARPROT(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
S_AXI_HP0_ARQOS(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
S_AXI_HP0_ARREADY => axi_mem_intercon_M00_AXI_ARREADY,
S_AXI_HP0_ARSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
S_AXI_HP0_ARVALID => axi_mem_intercon_M00_AXI_ARVALID,
S_AXI_HP0_AWADDR(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
S_AXI_HP0_AWBURST(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
S_AXI_HP0_AWCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
S_AXI_HP0_AWID(5 downto 1) => B"00000",
S_AXI_HP0_AWID(0) => axi_mem_intercon_M00_AXI_AWID(0),
S_AXI_HP0_AWLEN(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
S_AXI_HP0_AWLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
S_AXI_HP0_AWPROT(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
S_AXI_HP0_AWQOS(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
S_AXI_HP0_AWREADY => axi_mem_intercon_M00_AXI_AWREADY,
S_AXI_HP0_AWSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
S_AXI_HP0_AWVALID => axi_mem_intercon_M00_AXI_AWVALID,
S_AXI_HP0_BID(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
S_AXI_HP0_BREADY => axi_mem_intercon_M00_AXI_BREADY,
S_AXI_HP0_BRESP(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
S_AXI_HP0_BVALID => axi_mem_intercon_M00_AXI_BVALID,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
S_AXI_HP0_RLAST => axi_mem_intercon_M00_AXI_RLAST,
S_AXI_HP0_RREADY => axi_mem_intercon_M00_AXI_RREADY,
S_AXI_HP0_RRESP(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
S_AXI_HP0_RVALID => axi_mem_intercon_M00_AXI_RVALID,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
S_AXI_HP0_WID(5 downto 1) => B"00000",
S_AXI_HP0_WID(0) => axi_mem_intercon_M00_AXI_WID(0),
S_AXI_HP0_WLAST => axi_mem_intercon_M00_AXI_WLAST,
S_AXI_HP0_WREADY => axi_mem_intercon_M00_AXI_WREADY,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
S_AXI_HP0_WVALID => axi_mem_intercon_M00_AXI_WVALID,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.design_TEST_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready(0) => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready(0) => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wvalid(0) => processing_system7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready(0) => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid(0) => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
M01_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready(0) => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid(0) => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
M01_AXI_bready(0) => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid(0) => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready(0) => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid(0) => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready(0) => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wvalid(0) => processing_system7_0_axi_periph_M01_AXI_WVALID(0),
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_100M: component design_TEST_rst_processing_system7_0_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
end STRUCTURE;
| gpl-3.0 | bfa0de24c71c0f995cebd2ff712a8756 | 0.67293 | 2.776087 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_axi_dma_2_0/synth/design_SWandHW_standalone_axi_dma_2_0.vhd | 1 | 21,724 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_8;
USE axi_dma_v7_1_8.axi_dma;
ENTITY design_SWandHW_standalone_axi_dma_2_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_SWandHW_standalone_axi_dma_2_0;
ARCHITECTURE design_SWandHW_standalone_axi_dma_2_0_arch OF design_SWandHW_standalone_axi_dma_2_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_axi_dma_2_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_axi_dma_2_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_axi_dma_2_0_arch : ARCHITECTURE IS "design_SWandHW_standalone_axi_dma_2_0,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SWandHW_standalone_axi_dma_2_0_arch: ARCHITECTURE IS "design_SWandHW_standalone_axi_dma_2_0,axi_dma,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=14,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=256,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_S2MM=0,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=0,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 256,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 1,
C_INCLUDE_S2MM => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => '0',
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awready => '0',
m_axi_s2mm_wready => '0',
m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_s2mm_bvalid => '0',
s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_tkeep => X"F",
s_axis_s2mm_tvalid => '0',
s_axis_s2mm_tlast => '0',
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END design_SWandHW_standalone_axi_dma_2_0_arch;
| gpl-3.0 | 72d1c1aa3fe7c893131b29f459ae94a9 | 0.67193 | 2.800567 | false | false | false | false |
kristapsdreija/IGLOO_NANO_FPGA_VGA_Generator_Libero_SoC | IGLOO_Updated_VGA/component/work/Top/Top.vhd | 1 | 6,253 | ----------------------------------------------------------------------
-- Created by SmartDesign Wed Jan 21 11:15:51 2015
-- Version: v11.4 SP1 11.4.1.17
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library igloo;
use igloo.all;
----------------------------------------------------------------------
-- Top entity declaration
----------------------------------------------------------------------
entity Top is
-- Port list
port(
-- Inputs
BUTTON_1 : in std_logic;
CLKA : in std_logic;
NSYSRESET : in std_logic;
PAD : in std_logic;
-- Outputs
blue : out std_logic;
green : out std_logic;
h_sync : out std_logic;
red : out std_logic;
v_sync : out std_logic
);
end Top;
----------------------------------------------------------------------
-- Top architecture body
----------------------------------------------------------------------
architecture RTL of Top is
----------------------------------------------------------------------
-- Component declarations
----------------------------------------------------------------------
-- AND2
component AND2
-- Port list
port(
-- Inputs
A : in std_logic;
B : in std_logic;
-- Outputs
Y : out std_logic
);
end component;
-- CLKGEN
component CLKGEN
-- Port list
port(
-- Inputs
CLKA : in std_logic;
POWERDOWN : in std_logic;
-- Outputs
GLA : out std_logic;
LOCK : out std_logic
);
end component;
-- hw_image_generator
component hw_image_generator
-- Port list
port(
-- Inputs
BUTTON_1 : in std_logic;
column : in std_logic_vector(0 to 9);
disp_ena : in std_logic;
row : in std_logic_vector(0 to 9);
-- Outputs
blue : out std_logic;
green : out std_logic;
red : out std_logic
);
end component;
-- INBUF_FF
component INBUF_FF
-- Port list
port(
-- Inputs
PAD : in std_logic;
-- Outputs
Y : out std_logic
);
end component;
-- vga_controller
component vga_controller
-- Port list
port(
-- Inputs
pixel_clk : in std_logic;
reset_n : in std_logic;
-- Outputs
column : out std_logic_vector(0 to 9);
disp_ena : out std_logic;
h_sync : out std_logic;
n_blank : out std_logic;
n_sync : out std_logic;
row : out std_logic_vector(0 to 9);
v_sync : out std_logic
);
end component;
----------------------------------------------------------------------
-- Signal declarations
----------------------------------------------------------------------
signal AND2_0_Y : std_logic;
signal blue_net_0 : std_logic;
signal CLKGEN_0_GLA : std_logic;
signal CLKGEN_0_LOCK : std_logic;
signal green_net_0 : std_logic;
signal h_sync_net_0 : std_logic;
signal red_net_0 : std_logic;
signal v_sync_net_0 : std_logic;
signal vga_controller_0_column_0 : std_logic_vector(0 to 9);
signal vga_controller_0_disp_ena : std_logic;
signal vga_controller_0_row_0 : std_logic_vector(0 to 9);
signal v_sync_net_1 : std_logic;
signal h_sync_net_1 : std_logic;
signal blue_net_1 : std_logic;
signal red_net_1 : std_logic;
signal green_net_1 : std_logic;
----------------------------------------------------------------------
-- TiedOff Signals
----------------------------------------------------------------------
signal VCC_net : std_logic;
begin
----------------------------------------------------------------------
-- Constant assignments
----------------------------------------------------------------------
VCC_net <= '1';
----------------------------------------------------------------------
-- Top level output port assignments
----------------------------------------------------------------------
v_sync_net_1 <= v_sync_net_0;
v_sync <= v_sync_net_1;
h_sync_net_1 <= h_sync_net_0;
h_sync <= h_sync_net_1;
blue_net_1 <= blue_net_0;
blue <= blue_net_1;
red_net_1 <= red_net_0;
red <= red_net_1;
green_net_1 <= green_net_0;
green <= green_net_1;
----------------------------------------------------------------------
-- Component instances
----------------------------------------------------------------------
-- AND2_0
AND2_0 : AND2
port map(
-- Inputs
A => NSYSRESET,
B => CLKGEN_0_LOCK,
-- Outputs
Y => AND2_0_Y
);
-- CLKGEN_0
CLKGEN_0 : CLKGEN
port map(
-- Inputs
POWERDOWN => VCC_net,
CLKA => CLKA,
-- Outputs
LOCK => CLKGEN_0_LOCK,
GLA => CLKGEN_0_GLA
);
-- hw_image_generator_0
hw_image_generator_0 : hw_image_generator
port map(
-- Inputs
disp_ena => vga_controller_0_disp_ena,
row => vga_controller_0_column_0,
column => vga_controller_0_row_0,
BUTTON_1 => BUTTON_1,
-- Outputs
red => red_net_0,
green => green_net_0,
blue => blue_net_0
);
-- INBUF_FF_0
INBUF_FF_0 : INBUF_FF
port map(
-- Inputs
PAD => PAD,
-- Outputs
Y => OPEN
);
-- vga_controller_0
vga_controller_0 : vga_controller
port map(
-- Inputs
pixel_clk => CLKGEN_0_GLA,
reset_n => AND2_0_Y,
-- Outputs
h_sync => h_sync_net_0,
v_sync => v_sync_net_0,
disp_ena => vga_controller_0_disp_ena,
n_blank => OPEN,
n_sync => OPEN,
row => vga_controller_0_row_0,
column => vga_controller_0_column_0
);
end RTL;
| gpl-2.0 | 0089001ec7768b6b177ed27d5d7b58b4 | 0.390692 | 4.268259 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt | kr_fuzman_system.vhd | 1 | 2,666 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kr_fuzman_system is
port
( clock : in std_logic;
Ut : in std_logic_vector(31 downto 0);
Vref : in std_logic_vector(31 downto 0);
Vtminusone : in std_logic_vector(31 downto 0);
Ztminusone : in std_logic_vector(31 downto 0);
Vt : out std_logic_vector(31 downto 0);
Zt : out std_logic_vector(31 downto 0)
);
end kr_fuzman_system;
architecture struct of kr_fuzman_system is
component kr_fuzman_Ztminus is
port
( clock : in std_logic;
Ztminusone: in std_logic_vector (31 downto 0);
Ztminus : out std_logic_vector (31 downto 0)
);
end component;
component kr_fuzman_koft is
port
( clock : in std_logic;
Ztminus : in std_logic_vector (31 downto 0);
Ztcap : out std_logic_vector (31 downto 0);
koft : out std_logic_vector (31 downto 0)
);
end component;
component kr_fuzman_Vtminus is
port
( clock : in std_logic;
Vtminusone : in std_logic_vector (31 downto 0);
Vref : in std_logic_vector (31 downto 0);
koft : in std_logic_vector (31 downto 0);
Vtminus : out std_logic_vector (31 downto 0)
);
end component;
component kr_fuzman_Vt is
port
( clock : in std_logic;
Ut : in std_logic_vector(31 downto 0);
Vtminus : in std_logic_vector(31 downto 0);
Vt : out std_logic_vector(31 downto 0)
);
end component;
component kr_fuzman_omegat is
port
( clock : in std_logic;
koft : in std_logic_vector (31 downto 0);
Ztcap : in std_logic_vector (31 downto 0);
omegat : out std_logic_vector (31 downto 0)
);
end component;
component kr_fuzman_Zt is
port
( clock : in std_logic;
koft : in std_logic_vector(31 downto 0);
Ztminus : in std_logic_vector(31 downto 0);
omegat : in std_logic_vector(31 downto 0);
Zt : out std_logic_vector(31 downto 0)
);
end component;
signal X1,X2,X3,X4,X5 : std_logic_vector(31 downto 0);
begin
M1 : kr_fuzman_Ztminus port map (clock => clock, Ztminusone => Ztminusone, Ztminus => X1);
M2 : kr_fuzman_koft port map (clock => clock, Ztminus => X1, Ztcap => X2, koft => X3);
M3 : kr_fuzman_Vtminus port map (clock => clock, Vtminusone => Vtminusone, Vref => Vref, koft => X3, Vtminus => X4);
M4 : kr_fuzman_Vt port map ( clock => clock, Ut => Ut, Vtminus => X4, Vt => Vt);
M5 : kr_fuzman_omegat port map (clock => clock, koft => X3, Ztcap => X2, omegat => X5);
M6 : kr_fuzman_Zt port map (clock => clock, koft => X3, Ztminus => X1, omegat => X5, Zt => Zt);
end struct;
| mit | 513cc568f24ac0f8f6d6788661e91f36 | 0.617779 | 3.307692 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ip/design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0/synth/design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0.vhd | 1 | 7,056 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_8;
USE proc_sys_reset_v5_0_8.proc_sys_reset;
ENTITY design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0;
ARCHITECTURE design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0_arch OF design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0_arch;
| gpl-3.0 | 07dea53ddca0471f870d50fa6471fc99 | 0.722789 | 3.441951 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_axi_dma_1/synth/design_SWandHW_standalone_axi_dma_1.vhd | 1 | 21,702 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_8;
USE axi_dma_v7_1_8.axi_dma;
ENTITY design_SWandHW_standalone_axi_dma_1 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_SWandHW_standalone_axi_dma_1;
ARCHITECTURE design_SWandHW_standalone_axi_dma_1_arch OF design_SWandHW_standalone_axi_dma_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_axi_dma_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_axi_dma_1_arch: ARCHITECTURE IS "axi_dma,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_axi_dma_1_arch : ARCHITECTURE IS "design_SWandHW_standalone_axi_dma_1,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SWandHW_standalone_axi_dma_1_arch: ARCHITECTURE IS "design_SWandHW_standalone_axi_dma_1,axi_dma,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=14,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=256,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_S2MM=0,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=0,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 256,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 1,
C_INCLUDE_S2MM => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => '0',
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awready => '0',
m_axi_s2mm_wready => '0',
m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_s2mm_bvalid => '0',
s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_tkeep => X"F",
s_axis_s2mm_tvalid => '0',
s_axis_s2mm_tlast => '0',
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END design_SWandHW_standalone_axi_dma_1_arch;
| gpl-3.0 | 289cbde5fc0de6afefda3a36e097b461 | 0.672104 | 2.805688 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/hdl/design_SWandHW_standalone_v2_wrapper.vhd | 1 | 3,832 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
--Date : Fri Sep 02 01:29:52 2016
--Host : DESKTOP-I329812 running 64-bit major release (build 9200)
--Command : generate_target design_SWandHW_standalone_v2_wrapper.bd
--Design : design_SWandHW_standalone_v2_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SWandHW_standalone_v2_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
btns_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end design_SWandHW_standalone_v2_wrapper;
architecture STRUCTURE of design_SWandHW_standalone_v2_wrapper is
component design_SWandHW_standalone_v2 is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
btns_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component design_SWandHW_standalone_v2;
begin
design_SWandHW_standalone_v2_i: component design_SWandHW_standalone_v2
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
btns_4bits_tri_i(3 downto 0) => btns_4bits_tri_i(3 downto 0)
);
end STRUCTURE;
| gpl-3.0 | 5a65f4d4b261c68f6ea2ad890eda0080 | 0.605428 | 3.075441 | false | false | false | false |
Rookfighter/aes-ss17 | ex01/whole_design.vhd | 1 | 2,408 | -- whole_design.vhd
--
-- Created on: 14 May 2017
-- Author: Fabian Meyer
--
-- Integrates ledblinker and freq_controller.
library ieee;
use ieee.std_logic_1164.all;
entity whole_design is
generic(RSTDEF: std_logic := '0'); -- reset button is low active
port(rst: in std_logic; -- reset, RESTDEF active
clk: in std_logic; -- clock, rising edge
btn0: in std_logic; -- increment button, low active
btn1: in std_logic; -- decrement button, low active
led: out std_logic; -- LED status, active high
freq: out std_logic_vector(2 downto 0)); -- blinking frequency, 000 = stop, 111 = fast
end whole_design;
architecture behavioral of whole_design is
component ledblinker is
generic(RSTDEF: std_logic := '1');
port (rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
freq: in std_logic_vector(2 downto 0); -- blinking frequency, 000 = stop, 111 = fast
led: out std_logic); -- LED status, active high
end component;
component freq_controller is
generic(RSTDEF: std_logic := '1');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
btn0: in std_logic; -- increment button, low active
btn1: in std_logic; -- decrement button, low active
freq: out std_logic_vector(2 downto 0)); -- frequency, 000 = stop, 111 = fast
end component;
-- signal to connect freq, ledblinker and freq_controller
signal freq_tmp: std_logic_vector(2 downto 0) := (others => '0');
begin
-- connect freq_tmp to out port freq
freq <= freq_tmp;
-- connect freq of ledblinker to freq_tmp (read)
lblink: ledblinker
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
freq => freq_tmp,
led => led);
-- connect freq of freq_controlelr to freq_tmp (write)
fcontr : freq_controller
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
btn0 => btn0,
btn1 => btn1,
freq => freq_tmp);
end behavioral;
| gpl-3.0 | 54d4a774fdc522625f39e7e5d3eebe8e | 0.542359 | 4.047059 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/TEST_hls_example_1_0/hdl/ip/example_ap_fadd_3_full_dsp_32.vhd | 1 | 12,744 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY example_ap_fadd_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END example_ap_fadd_3_full_dsp_32;
ARCHITECTURE example_ap_fadd_3_full_dsp_32_arch OF example_ap_fadd_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF example_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF example_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF example_ap_fadd_3_full_dsp_32_arch : ARCHITECTURE IS "example_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF example_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "example_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END example_ap_fadd_3_full_dsp_32_arch;
| gpl-3.0 | 245b17b71c2f89e572231fc7eef11d5a | 0.650973 | 3.013478 | false | false | false | false |
bonfireprocessor/bonfire-soc | cpu_dbus_connect.vhd | 1 | 3,109 | ---------------------------------------------------------------------
-- Simple WISHBONE interconnect
--
-- Generated by wigen at Tue Nov 7 19:42:31 2017
--
-- Configuration:
-- Number of masters: 1
-- Number of slaves: 2
-- Master address width: 32
-- Slave address width: 26
-- Port size: 32
-- Port granularity: 8
-- Entity name: cpu_dbus_connect
-- Pipelined arbiter: no
-- Registered feedback: no
-- Unsafe slave decoder: no
--
-- Command line:
-- wigen -e cpu_dbus_connect 1 2 32 26 32 8
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity cpu_dbus_connect is
port(
clk_i: in std_logic;
rst_i: in std_logic;
s0_cyc_i: in std_logic;
s0_stb_i: in std_logic;
s0_we_i: in std_logic;
s0_sel_i: in std_logic_vector(3 downto 0);
s0_ack_o: out std_logic;
s0_adr_i: in std_logic_vector(31 downto 2);
s0_dat_i: in std_logic_vector(31 downto 0);
s0_dat_o: out std_logic_vector(31 downto 0);
m0_cyc_o: out std_logic;
m0_stb_o: out std_logic;
m0_we_o: out std_logic;
m0_sel_o: out std_logic_vector(3 downto 0);
m0_ack_i: in std_logic;
m0_adr_o: out std_logic_vector(25 downto 2);
m0_dat_o: out std_logic_vector(31 downto 0);
m0_dat_i: in std_logic_vector(31 downto 0);
m1_cyc_o: out std_logic;
m1_stb_o: out std_logic;
m1_we_o: out std_logic;
m1_sel_o: out std_logic_vector(3 downto 0);
m1_ack_i: in std_logic;
m1_adr_o: out std_logic_vector(25 downto 2);
m1_dat_o: out std_logic_vector(31 downto 0);
m1_dat_i: in std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of cpu_dbus_connect is
signal select_slave: std_logic_vector(2 downto 0);
signal cyc_mux: std_logic;
signal stb_mux: std_logic;
signal we_mux: std_logic;
signal sel_mux: std_logic_vector(3 downto 0);
signal adr_mux: std_logic_vector(31 downto 2);
signal wdata_mux: std_logic_vector(31 downto 0);
signal ack_mux: std_logic;
signal rdata_mux: std_logic_vector(31 downto 0);
begin
-- MASTER->SLAVE MUX
cyc_mux<=s0_cyc_i;
stb_mux<=s0_stb_i;
we_mux<=s0_we_i;
sel_mux<=s0_sel_i;
adr_mux<=s0_adr_i;
wdata_mux<=s0_dat_i;
-- MASTER->SLAVE DEMUX
select_slave<="001" when adr_mux(31 downto 26)="000000" else
"010" when adr_mux(31 downto 26)="000001" else
"100"; -- fallback slave
m0_cyc_o<=cyc_mux and select_slave(0);
m0_stb_o<=stb_mux and select_slave(0);
m0_we_o<=we_mux;
m0_sel_o<=sel_mux;
m0_adr_o<=adr_mux(m0_adr_o'range);
m0_dat_o<=wdata_mux;
m1_cyc_o<=cyc_mux and select_slave(1);
m1_stb_o<=stb_mux and select_slave(1);
m1_we_o<=we_mux;
m1_sel_o<=sel_mux;
m1_adr_o<=adr_mux(m1_adr_o'range);
m1_dat_o<=wdata_mux;
-- SLAVE->MASTER MUX
ack_mux<=(m0_ack_i and select_slave(0)) or
(m1_ack_i and select_slave(1)) or
(cyc_mux and stb_mux and select_slave(2)); -- fallback slave
rdata_mux_gen: for i in rdata_mux'range generate
rdata_mux(i)<=(m0_dat_i(i) and select_slave(0)) or
(m1_dat_i(i) and select_slave(1));
end generate;
-- SLAVE->MASTER DEMUX
s0_ack_o<=ack_mux;
s0_dat_o<=rdata_mux;
end architecture;
| gpl-3.0 | 71274f18ac234e8ad3924c65babd6e9b | 0.627211 | 2.513339 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_fpext_32ns_64_1.vhd | 4 | 1,972 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_fpext_32ns_64_1 is
generic (
ID : integer := 4;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
dout_WIDTH : integer := 64
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_fpext_32ns_64_1 is
--------------------- Component ---------------------
component feedforward_ap_fpext_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_fpext_0_no_dsp_32_u : component feedforward_ap_fpext_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
dout <= r_tdata;
end architecture;
| gpl-3.0 | b7283e8c3894623ccb64588c8f430003 | 0.498479 | 3.713748 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/vhdl/feedforward_ST_WandB.vhd | 2 | 3,121 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity feedforward_ST_WandB_ram is
generic(
mem_type : string := "block";
dwidth : integer := 64;
awidth : integer := 13;
mem_size : integer := 5040
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of feedforward_ST_WandB_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_ST_WandB is
generic (
DataWidth : INTEGER := 64;
AddressRange : INTEGER := 5040;
AddressWidth : INTEGER := 13);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_ST_WandB is
component feedforward_ST_WandB_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_ST_WandB_ram_U : component feedforward_ST_WandB_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
| gpl-3.0 | 1b49b55078eda1de65efb3cc805a6306 | 0.54694 | 3.62907 | false | false | false | false |
brotatos/Whack-A-Mole | src/RandomNumberGenerator.vhd | 1 | 1,511 | ----------------------------------------------------------------------------------
-- Company: Rat Technologies
-- Engineer: Various Rats
--
-- Create Date: 15:06:58 10/02/2013
-- Design Name:
-- Module Name: mux_4to1_programnCounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Simple pseudo-random number generator based on a linear feedback
-- shift register.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments: This was originally written/provided by Jeff Gerfen.
-- Bryan Mealy made a few modificaitons to it in the general hope of making
-- the thing work better.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RandomNumberGenerator is
port ( clk : in std_logic;
random_num : out std_logic_vector (2 downto 0));
end RandomNumberGenerator;
architecture Behavioral of RandomNumberGenerator is
begin
process(clk)
variable rand_temp : std_logic_vector(7 downto 0):= (others => '0');
variable temp0 : std_logic;
variable temp5 : std_logic;
begin
if(rising_edge(clk)) then
temp5 := not rand_temp(2);
temp0 := rand_temp(7) xor rand_temp(6);
rand_temp := rand_temp(4 downto 3) & temp5 & rand_temp(1 downto 0) &
rand_temp(6 downto 5) & temp0;
end if;
random_num <= rand_temp(2 downto 0);
end process;
end;
| mit | bdbe88536f03c1dbb6ccd29c3a993374 | 0.579087 | 3.89433 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_fmul_32ns_32ns_32_4_max_dsp.vhd | 4 | 3,375 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_fmul_32ns_32ns_32_4_max_dsp is
generic (
ID : integer := 1;
NUM_STAGE : integer := 4;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_fmul_32ns_32ns_32_4_max_dsp is
--------------------- Component ---------------------
component feedforward_ap_fmul_2_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_fmul_2_max_dsp_32_u : component feedforward_ap_fmul_2_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 05d32b4573478b1b86858f19b61aeee2 | 0.489778 | 3.511967 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_AXILiteS_s_axi.vhd | 6 | 17,016 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ANN_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
ap_return :in STD_LOGIC_VECTOR(31 downto 0);
P_mode :out STD_LOGIC_VECTOR(31 downto 0);
P_index1 :out STD_LOGIC_VECTOR(31 downto 0);
P_index2 :out STD_LOGIC_VECTOR(31 downto 0);
P_intIn_index3 :out STD_LOGIC_VECTOR(31 downto 0);
P_floatIn :out STD_LOGIC_VECTOR(31 downto 0)
);
end entity ANN_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of ap_return
-- bit 31~0 - ap_return[31:0] (Read)
-- 0x18 : Data signal of P_mode
-- bit 31~0 - P_mode[31:0] (Read/Write)
-- 0x1c : reserved
-- 0x20 : Data signal of P_index1
-- bit 31~0 - P_index1[31:0] (Read/Write)
-- 0x24 : reserved
-- 0x28 : Data signal of P_index2
-- bit 31~0 - P_index2[31:0] (Read/Write)
-- 0x2c : reserved
-- 0x30 : Data signal of P_intIn_index3
-- bit 31~0 - P_intIn_index3[31:0] (Read/Write)
-- 0x34 : reserved
-- 0x38 : Data signal of P_floatIn
-- bit 31~0 - P_floatIn[31:0] (Read/Write)
-- 0x3c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of ANN_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_AP_RETURN_0 : INTEGER := 16#10#;
constant ADDR_P_MODE_DATA_0 : INTEGER := 16#18#;
constant ADDR_P_MODE_CTRL : INTEGER := 16#1c#;
constant ADDR_P_INDEX1_DATA_0 : INTEGER := 16#20#;
constant ADDR_P_INDEX1_CTRL : INTEGER := 16#24#;
constant ADDR_P_INDEX2_DATA_0 : INTEGER := 16#28#;
constant ADDR_P_INDEX2_CTRL : INTEGER := 16#2c#;
constant ADDR_P_INTIN_INDEX3_DATA_0 : INTEGER := 16#30#;
constant ADDR_P_INTIN_INDEX3_CTRL : INTEGER := 16#34#;
constant ADDR_P_FLOATIN_DATA_0 : INTEGER := 16#38#;
constant ADDR_P_FLOATIN_CTRL : INTEGER := 16#3c#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_ap_return : UNSIGNED(31 downto 0);
signal int_P_mode : UNSIGNED(31 downto 0);
signal int_P_index1 : UNSIGNED(31 downto 0);
signal int_P_index2 : UNSIGNED(31 downto 0);
signal int_P_intIn_index3 : UNSIGNED(31 downto 0);
signal int_P_floatIn : UNSIGNED(31 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_AP_RETURN_0 =>
rdata_data <= RESIZE(int_ap_return(31 downto 0), 32);
when ADDR_P_MODE_DATA_0 =>
rdata_data <= RESIZE(int_P_mode(31 downto 0), 32);
when ADDR_P_INDEX1_DATA_0 =>
rdata_data <= RESIZE(int_P_index1(31 downto 0), 32);
when ADDR_P_INDEX2_DATA_0 =>
rdata_data <= RESIZE(int_P_index2(31 downto 0), 32);
when ADDR_P_INTIN_INDEX3_DATA_0 =>
rdata_data <= RESIZE(int_P_intIn_index3(31 downto 0), 32);
when ADDR_P_FLOATIN_DATA_0 =>
rdata_data <= RESIZE(int_P_floatIn(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
P_mode <= STD_LOGIC_VECTOR(int_P_mode);
P_index1 <= STD_LOGIC_VECTOR(int_P_index1);
P_index2 <= STD_LOGIC_VECTOR(int_P_index2);
P_intIn_index3 <= STD_LOGIC_VECTOR(int_P_intIn_index3);
P_floatIn <= STD_LOGIC_VECTOR(int_P_floatIn);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_return <= (others => '0');
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_return <= UNSIGNED(ap_return);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_MODE_DATA_0) then
int_P_mode(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_mode(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_INDEX1_DATA_0) then
int_P_index1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_index1(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_INDEX2_DATA_0) then
int_P_index2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_index2(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_INTIN_INDEX3_DATA_0) then
int_P_intIn_index3(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_intIn_index3(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_FLOATIN_DATA_0) then
int_P_floatIn(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_floatIn(31 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| gpl-3.0 | 488a3bdee70ef92572b3447ba14d62df | 0.469676 | 3.660142 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/ip/feedforward_ap_dexp_16_full_dsp_64.vhd | 6 | 12,506 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_dexp_16_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END feedforward_ap_dexp_16_full_dsp_64;
ARCHITECTURE feedforward_ap_dexp_16_full_dsp_64_arch OF feedforward_ap_dexp_16_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_dexp_16_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_dexp_16_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_dexp_16_full_dsp_64_arch : ARCHITECTURE IS "feedforward_ap_dexp_16_full_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_dexp_16_full_dsp_64_arch: ARCHITECTURE IS "feedforward_ap_dexp_16_full_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=1,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=16,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 1,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 16,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_dexp_16_full_dsp_64_arch;
| gpl-3.0 | 454f5103504c418cbb8934c383b6b146 | 0.650888 | 3.033964 | false | false | false | false |
bonfireprocessor/bonfire-soc | obsolete/ram2048x8.vhd | 1 | 4,739 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:03:14 10/16/2016
-- Design Name:
-- Module Name: ram2048x8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- 2K*8 Bit RAM with one R/W and one Read-only Port.
-- Using Xilinx Primitives instead of inference to have more control over BRAM allocation.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ram2048x8 is
Port ( DOutA : out STD_LOGIC_VECTOR (7 downto 0);
DInA : in STD_LOGIC_VECTOR (7 downto 0);
AdrA : in STD_LOGIC_VECTOR (10 downto 0);
ENA : in STD_LOGIC;
WRENA : in STD_LOGIC;
CLKA : in STD_LOGIC;
DoutB : out STD_LOGIC_VECTOR (7 downto 0);
AdrB : in STD_LOGIC_VECTOR (10 downto 0);
ENB : in STD_LOGIC;
CLKB : in STD_LOGIC);
end ram2048x8;
architecture Behavioral of ram2048x8 is
signal DOA,DOB,DIA,DIB : std_logic_vector(31 downto 0);
signal DOPA,DOPB,DIPA,DIPB : std_logic_vector(3 downto 0);
signal ADDRA,ADDRB : std_logic_vector(13 downto 0);
signal WEA,WEB : std_logic_vector(3 downto 0);
begin
DIPA<=(others=>'0');
DIPB<=(others=>'0');
DIA<= X"000000"&DinA;
DIB<= (others => '0');
ADDRA<=AdrA&"000";
ADDRB<=AdrB&"000";
DOutA<= DOA(7 downto 0);
DoutB<= DOB(7 downto 0);
wegen: for i in WEA'range generate
WEA(i)<=WRENA;
WEB(i)<='0';
end generate;
RAMB16BWER_inst : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 9,
DATA_WIDTH_B => 9,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => FALSE,
EN_RSTRAM_B => FALSE,
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) output: Port A data
DOA => DOA, -- 32-bit output: A port data output
DOPA => DOPA, -- 4-bit output: A port parity output
-- Port B Data: 32-bit (each) output: Port B data
DOB => DOB, -- 32-bit output: B port data output
DOPB => DOPB, -- 4-bit output: B port parity output
-- Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals
ADDRA => ADDRA, -- 14-bit input: A port address input
CLKA => CLKA, -- 1-bit input: A port clock input
ENA => ENA, -- 1-bit input: A port enable input
REGCEA => '0', -- 1-bit input: A port register clock enable input
RSTA => '0', -- 1-bit input: A port register set/reset input
WEA => WEA, -- 4-bit input: Port A byte-wide write enable input
-- Port A Data: 32-bit (each) input: Port A data
DIA => DIA, -- 32-bit input: A port data input
DIPA => DIPA, -- 4-bit input: A port parity input
-- Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals
ADDRB => ADDRB, -- 14-bit input: B port address input
CLKB => CLKB, -- 1-bit input: B port clock input
ENB => ENB, -- 1-bit input: B port enable input
REGCEB => '0', -- 1-bit input: B port register clock enable input
RSTB => '0', -- 1-bit input: B port register set/reset input
WEB => WEB, -- 4-bit input: Port B byte-wide write enable input
-- Port B Data: 32-bit (each) input: Port B data
DIB => DIB, -- 32-bit input: B port data input
DIPB => DIPB -- 4-bit input: B port parity input
);
end Behavioral;
| gpl-3.0 | 98c3ee601abee78c427d499cd829e940 | 0.579025 | 3.573906 | false | false | false | false |
bonfireprocessor/bonfire-soc | uart/wb_uart_interface.vhd | 1 | 7,745 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:42:56 01/07/2017
-- Design Name:
-- Module Name: wb_uart_interface - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--! The following registers are defined:
--! |--------------------|--------------------------------------------|
--! | Address | Description |
--! |--------------------|--------------------------------------------|
--! | 0x00 | Transmit register (write-only) |
--! | 0x04 | Receive register (read-only) |
--! | 0x08 | Status register (read-only) |
--! | 0x0c | Sample clock divisor register (read/write) |
--! | 0x10 | Interrupt enable register (read/write) |
--! | 0x14 | Revision Code |
--! |--------------------|--------------------------------------------|
--!
--! The status register contains the following bits:
--! - Bit 0: receive buffer empty
--! - Bit 1: transmiter idle
--! - Bit 2: receive buffer full
--! - Bit 3: transmit buffer full
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.log2.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wb_uart_interface is
generic(
FIFO_DEPTH : natural := 64; --! Depth of the input FIFO
CLK_FREQUENCY : natural := (96 * 1000000)
);
port(
clk : in std_logic;
reset : in std_logic;
-- UART ports:
txd : out std_logic;
rxd : in std_logic;
-- Interrupt signal:
irq : out std_logic;
-- Wishbone ports:
wb_adr_in : in std_logic_vector(7 downto 0);
wb_dat_in : in std_logic_vector( 7 downto 0);
wb_dat_out : out std_logic_vector( 7 downto 0);
wb_we_in : in std_logic;
wb_cyc_in : in std_logic;
wb_stb_in : in std_logic;
wb_ack_out : out std_logic
);
end wb_uart_interface;
architecture Behavioral of wb_uart_interface is
constant uart_revsion : std_logic_vector(7 downto 0) :=X"12";
-- signal uart_data_in : std_logic_vector(7 downto 0);
signal uart_data_out : std_logic_vector(7 downto 0);
signal fifo_data_out : std_logic_vector(7 downto 0);
signal fifo_data_ready : std_logic;
signal uart_rx_ready : std_logic;
signal uart_tx_busy : std_logic;
signal uart_badbit : std_logic;
signal uart_data_load : std_logic;
signal fifo_data_ack : std_logic;
signal fifo_nearly_full : std_logic;
signal can_transmit : std_logic :='1'; -- constant value at the moment
signal status_register,
sample_clk_divisor_register,
transmit_register : std_logic_vector(7 downto 0);
signal interrupt_register : std_logic_vector(1 downto 0);
signal wb_read_buffer : std_logic_vector(7 downto 0); -- register for wishbone reads
signal ack_read : std_logic :='0';
signal tx_reg_pending : std_logic :='0'; -- Indicates that data is loaded into tx register
signal divisor_wen : std_logic :='0';
begin
wb_dat_out <= wb_read_buffer;
wb_ack_out <= ack_read or (wb_we_in and wb_stb_in);
-- assert uart_data_load only when uart is not busy anymore, so we know that data will be taken by the UART on the next clock
uart_data_load <= tx_reg_pending and not uart_tx_busy;
process(ack_read,wb_adr_in)
begin
if ack_read='1' and wb_adr_in(4 downto 2)="001" then
fifo_data_ack<='1';
else
fifo_data_ack<='0';
end if;
end process;
-- Read register assignments
-- - Bit 0: receive buffer empty
-- - Bit 1: transmitter idle
-- - Bit 2: receive buffer full
-- - Bit 3: transmit buffer full
status_register<= "0000" & tx_reg_pending & fifo_nearly_full & not uart_tx_busy & not fifo_data_ready;
-- we do registered read to not induce combinatorial complexity to the wishbone bus
-- for a slow device like an UART it does not matter that this will create an additonal clock of latency
process(clk) begin
if rising_edge(clk) then
if ack_read='1' then
ack_read<='0';
end if;
-- see above
if uart_data_load='1' then
tx_reg_pending <= '0';
end if;
if divisor_wen='1' then
divisor_wen <= '0';
end if;
if wb_cyc_in ='1' and wb_stb_in='1' then
if wb_we_in='0' and ack_read='0' then -- read access
-- Wishbone Read Multiplexer
-- Address bits 1..0 don't care
case wb_adr_in(4 downto 2) is
when "001" => -- Addr 0x4 UART receive register
wb_read_buffer <= fifo_data_out;
when "010" => -- Addr 0x8
wb_read_buffer <= status_register;
when "011" => -- Addr 0xC
wb_read_buffer <= sample_clk_divisor_register;
when "100" => -- Addr 0x10
wb_read_buffer <= "000000"&interrupt_register;
when "101" => -- Addr 0x14
wb_read_buffer <= uart_revsion;
when others => -- others don't care...
wb_read_buffer <= (others => 'X');
end case;
ack_read <='1';
elsif wb_we_in='1' then
case wb_adr_in(4 downto 2) is
when "000" => -- Adr 0x0 transmit register
transmit_register <= wb_dat_in;
tx_reg_pending<='1';
when "011" =>-- Addr 0xC
sample_clk_divisor_register <= wb_dat_in;
divisor_wen <= '1';
when "100" => -- Addr 0x10
interrupt_register <= wb_dat_in(1 downto 0);
when others => -- do nothing
end case;
end if;
end if;
end if;
end process;
fifo_instance: entity work.fifo
generic map (
depth_log2 => log2(FIFO_DEPTH)
)
PORT MAP(
clk => clk,
reset => reset,
data_in => uart_data_out,
data_out => fifo_data_out,
read_ready => fifo_data_ready,
read_en => fifo_data_ack,
write_ready => open,
write_en => uart_rx_ready,
high_water_mark => fifo_nearly_full
);
uart_instance: entity work.uart
GENERIC MAP(
CLK_FREQUENCY => CLK_FREQUENCY
)
PORT MAP(
clk => clk,
serial_out => txd,
serial_in => rxd,
data_in => transmit_register,
data_in_load => uart_data_load,
data_out => uart_data_out,
data_out_ready => uart_rx_ready,
bad_bit => uart_badbit,
transmitter_busy => uart_tx_busy,
can_transmit => can_transmit,
sample_clock_divisor => sample_clk_divisor_register,
divisor_wen => divisor_wen
);
end Behavioral;
| gpl-3.0 | 1eedd90e29f52679356f16a28474d128 | 0.504454 | 3.975873 | false | false | false | false |
yahniukov/AES-128_VHDL | Design Sources/aes.vhd | 1 | 5,914 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity aes is
Generic ( DATA_LENGTH : integer := 128;
COUNT_ROUND : integer := 10
);
Port ( out_data : out STD_LOGIC_VECTOR ( DATA_LENGTH-1 downto 0);
finish : out STD_LOGIC;
in_data : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
key : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
clock : in STD_LOGIC;
reset : in STD_LOGIC;
start_encryption : in STD_LOGIC;
start_decryption : in STD_LOGIC;
start_key_generation : in STD_LOGIC;
encryption_decryption : in STD_LOGIC
);
end aes;
architecture RTL of aes is
-----------------------------
---------- SIGNALS ----------
-----------------------------
-- Value of current round
signal round : integer;
-- Current key
signal current_key : std_logic_vector (DATA_LENGTH-1 downto 0);
-- Signal to get new key from Key_Expansion_Module
signal get_next_key : std_logic;
-- Registers to store:
-- 1. preround_register_bank - zero round value;
-- 2. result_register_bank - register for result;
-- 3. intermediate_register_bank_for_input - result between first and last round for input;
-- 4. intermediate_register_bank_for_output - result between first and last round for output;
signal preround_register_bank : std_logic_vector (DATA_LENGTH-1 downto 0);
signal result_register_bank : std_logic_vector (DATA_LENGTH-1 downto 0);
signal intermediate_register_bank_for_input : std_logic_vector (DATA_LENGTH-1 downto 0);
signal intermediate_register_bank_for_output : std_logic_vector (DATA_LENGTH-1 downto 0);
-- Signals to start general blocks
signal start_encryption_module : std_logic;
signal start_decryption_module : std_logic;
signal start_key_expansion_module : std_logic;
-- Signals that block finished work
signal finish_encryption_module : std_logic;
signal finish_decryption_module : std_logic;
signal finish_key_expansion_module : std_logic;
-----------------------------
--------- COMPONENTS --------
-----------------------------
component Encryption_Module is
Generic ( DATA_LENGTH : integer := 128 );
Port( cypher_text : out STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
finish_round : out STD_LOGIC;
plain_text : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
key : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
clock : in STD_LOGIC;
reset : in STD_LOGIC;
start_round : in STD_LOGIC;
current_round : in integer range 0 to 11);
end component;
component Decryption_Module is
end component;
component Key_Expansion_Module is
end component;
begin
-- Initialize and Reset process
reset_n_init_process : process(reset)
begin
if(rising_edge(reset)) then
round <= 0;
current_key <= (others => '0');
preround_register_bank <= (others => '0');
result_register_bank <= (others => '0');
intermediate_register_bank_for_input <= (others => '0');
intermediate_register_bank_for_output <= (others => '0');
start_encryption_module <= '0';
start_decryption_module <= '0';
start_key_expansion_module <= '0';
finish_encryption_module <= '0';
finish_decryption_module <= '0';
finish_key_expansion_module <= '0';
end if;
end process reset_n_init_process;
-- Zero round - XOR user key and input data
preround_register_bank <= in_data xor key when clock = '1';
Encryption_Module_1 : Encryption_Module
port map ( cypher_text => intermediate_register_bank_for_output,
finish_round => finish_encryption_module,
plain_text => intermediate_register_bank_for_input,
key => current_key,
clock => clock,
reset => reset,
start_round => start_encryption_module,
current_round => round);
encrypt_process : process(clock, start_encryption, encryption_decryption)
variable i : integer;
begin
if(rising_edge(start_encryption) and encryption_decryption = '1') then
for i in 0 to 15 loop
if(clock = '1') then
if(round = 0) then
round <= round + 1;
intermediate_register_bank_for_input <= preround_register_bank;
start_encryption_module <= '1';
elsif(round = 10) then
round <= round + 1;
result_register_bank <= intermediate_register_bank_for_output;
finish <= '1';
start_encryption_module <= '0';
exit;
else
if(finish_encryption_module = '1') then
round <= round + 1;
start_encryption_module <= '0';
finish_encryption_module <= '0';
intermediate_register_bank_for_input <= intermediate_register_bank_for_output;
start_encryption_module <= '1';
end if;
end if;
end if;
end loop;
end if;
end process encrypt_process;
-- After last round - outstandings result
out_data <= result_register_bank when clock = '1';
end RTL;
| mit | 3382bc63a5f1ce03b1fb602181f6af0b | 0.527562 | 4.514504 | false | false | false | false |
airlog/vhdl-rc4 | src/rc4_key_loader.vhd | 1 | 2,542 | --
-- rc4_key_loader
-- urz¹dzenie ³aduj¹ce kolejne bajty klucza do pamiêci
--
-- TODO: opis dzialania
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.ALL;
entity rc4_key_loader is
generic (
width: integer := 8; -- ilosc bitow na wartosci
key_width: integer := 8 -- ilosc bitow na dlugosc klucza
);
port (
input: in std_logic_vector((width - 1) downto 0); -- bajt do zaszyfrowania/deszyfrowania
input_ctrl: in std_logic; -- czytaj wartosc z wejscia
input_stop: in std_logic; -- koniec nadawania klucza
go: in std_logic; -- dzialac/nie dzialac
clk: in std_logic;
key_ctrl: out std_logic; -- zapisz wartosc w pamieci
key_index: out std_logic_vector((width - 1) downto 0); -- indeks bajtu w pamieci
key_output: out std_logic_vector((width - 1) downto 0); -- perm_ctrl=1 => zapisz te wartosc
key_len_ctrl: out std_logic;
key_len_output: out std_logic_vector((key_width - 1) downto 0);
rdy: out std_logic -- gotowy do wczytywania klucza
);
end rc4_key_loader;
architecture Behavioral of rc4_key_loader is
type rc4_key_loader_state is (IDLE, ZERO_MEMORY, READING);
constant key_length : integer := 2 ** key_width;
begin
process (clk)
variable clk_ctr : integer := 0;
variable i : integer := 0;
variable state : rc4_key_loader_state := IDLE;
begin
if rising_edge(clk) then
key_ctrl <= '0';
key_len_ctrl <= '0';
rdy <= '0';
case state is
when IDLE =>
if go = '1' then
clk_ctr := 0;
i := 0;
state := ZERO_MEMORY;
end if;
when ZERO_MEMORY =>
if i >= key_length then
clk_ctr := 0;
i := 0;
state := READING;
else
key_ctrl <= '1';
key_index <= conv_std_logic_vector(i, width);
key_output <= (others => '0');
i := i + 1;
clk_ctr := clk_ctr + 1;
state := ZERO_MEMORY;
end if;
when READING =>
if input_stop = '1' then
key_len_ctrl <= '1';
key_len_output <= conv_std_logic_vector(i, key_width);
state := IDLE;
else
rdy <= '1';
if i >= key_length then
clk_ctr := 0;
rdy <= '0';
elsif input_ctrl = '1' then
key_ctrl <= '1';
key_index <= conv_std_logic_vector(i, width);
key_output <= input;
i := i + 1;
state := READING;
end if;
end if;
when others =>
end case;
end if;
end process;
end Behavioral;
| mit | cba6a38793c0cb455495a52a8455f10d | 0.558615 | 2.911798 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_fdiv_32ns_32ns_32_16.vhd | 4 | 3,362 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_fdiv_32ns_32ns_32_16 is
generic (
ID : integer := 2;
NUM_STAGE : integer := 16;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_fdiv_32ns_32ns_32_16 is
--------------------- Component ---------------------
component feedforward_ap_fdiv_14_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_fdiv_14_no_dsp_32_u : component feedforward_ap_fdiv_14_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 615a32c0ae0d54662a0d5586b0b90861 | 0.488995 | 3.527807 | false | false | false | false |
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`protect end_protected
| gpl-3.0 | f43f783b891ab7abde0f2e59e02c2fcf | 0.917446 | 1.92299 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/vhdl/ANN.vhd | 1 | 161,903 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ANN is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 7;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of ANN is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"ANN,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=18,HLS_SYN_DSP=37,HLS_SYN_FF=8607,HLS_SYN_LUT=12250}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st79_fsm_78 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st80_fsm_79 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st81_fsm_80 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st82_fsm_81 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st83_fsm_82 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st84_fsm_83 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st85_fsm_84 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st86_fsm_85 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st87_fsm_86 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st88_fsm_87 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st89_fsm_88 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st90_fsm_89 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st91_fsm_90 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st92_fsm_91 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st93_fsm_92 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st94_fsm_93 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st95_fsm_94 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st96_fsm_95 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st97_fsm_96 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st98_fsm_97 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st99_fsm_98 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st100_fsm_99 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st101_fsm_100 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st102_fsm_101 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st103_fsm_102 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st104_fsm_103 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st105_fsm_104 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st106_fsm_105 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st107_fsm_106 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st108_fsm_107 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st109_fsm_108 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st110_fsm_109 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st111_fsm_110 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st112_fsm_111 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st113_fsm_112 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st114_fsm_113 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st115_fsm_114 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st116_fsm_115 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st117_fsm_116 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st118_fsm_117 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st119_fsm_118 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st120_fsm_119 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st121_fsm_120 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st122_fsm_121 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st123_fsm_122 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st124_fsm_123 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st125_fsm_124 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st126_fsm_125 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st127_fsm_126 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st128_fsm_127 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st129_fsm_128 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st130_fsm_129 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st131_fsm_130 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st132_fsm_131 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st133_fsm_132 : STD_LOGIC_VECTOR (142 downto 0) := "00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st134_fsm_133 : STD_LOGIC_VECTOR (142 downto 0) := "00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st135_fsm_134 : STD_LOGIC_VECTOR (142 downto 0) := "00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st136_fsm_135 : STD_LOGIC_VECTOR (142 downto 0) := "00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st137_fsm_136 : STD_LOGIC_VECTOR (142 downto 0) := "00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st138_fsm_137 : STD_LOGIC_VECTOR (142 downto 0) := "00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st139_fsm_138 : STD_LOGIC_VECTOR (142 downto 0) := "00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st140_fsm_139 : STD_LOGIC_VECTOR (142 downto 0) := "00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st141_fsm_140 : STD_LOGIC_VECTOR (142 downto 0) := "00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st142_fsm_141 : STD_LOGIC_VECTOR (142 downto 0) := "01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st143_fsm_142 : STD_LOGIC_VECTOR (142 downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_52 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010010";
constant ap_const_lv32_7B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111011";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_5B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011011";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_55 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010101";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_5A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011010";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_61 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100001";
constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001";
constant ap_const_lv32_73 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110011";
constant ap_const_lv32_4E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001110";
constant ap_const_lv32_74 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv32_4D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001101";
constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
constant ap_const_lv32_51 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010001";
constant ap_const_lv32_79 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111001";
constant ap_const_lv32_7A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111010";
constant ap_const_lv32_8B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001011";
constant ap_const_lv32_8D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001101";
constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
constant ap_const_lv32_8C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001100";
constant ap_const_lv32_8E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001110";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_75 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110101";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_56 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010110";
constant ap_const_lv32_5C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011100";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv23_0 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000000000";
constant ap_const_lv31_7FFFFFFF : STD_LOGIC_VECTOR (30 downto 0) := "1111111111111111111111111111111";
constant ap_const_lv32_FFFFFFFE : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111110";
constant ap_const_lv32_80000000 : STD_LOGIC_VECTOR (31 downto 0) := "10000000000000000000000000000000";
constant ap_const_lv14_29 : STD_LOGIC_VECTOR (13 downto 0) := "00000000101001";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_161 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal P_mode : STD_LOGIC_VECTOR (31 downto 0);
signal P_index1 : STD_LOGIC_VECTOR (31 downto 0);
signal P_index2 : STD_LOGIC_VECTOR (31 downto 0);
signal P_intIn_index3 : STD_LOGIC_VECTOR (31 downto 0);
signal P_floatIn : STD_LOGIC_VECTOR (31 downto 0);
signal P_floatOut : STD_LOGIC_VECTOR (31 downto 0);
signal P_floatOut_ap_vld : STD_LOGIC;
signal P_intOut : STD_LOGIC_VECTOR (31 downto 0);
signal P_intOut_ap_vld : STD_LOGIC;
signal ST_numLayer : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_WandB_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal ST_WandB_ce0 : STD_LOGIC;
signal ST_WandB_we0 : STD_LOGIC;
signal ST_WandB_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_WandB_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal ST_uOut_ce0 : STD_LOGIC;
signal ST_uOut_we0 : STD_LOGIC;
signal ST_uOut_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal ST_uOut_ce1 : STD_LOGIC;
signal ST_uOut_we1 : STD_LOGIC;
signal ST_uOut_d1 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_q1 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_layerSize_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ANN_AXILiteS_s_axi_U_ap_dummy_ce : STD_LOGIC;
signal reg_479 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_249 : BOOLEAN;
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_256 : BOOLEAN;
signal ap_sig_cseq_ST_st83_fsm_82 : STD_LOGIC;
signal ap_sig_bdd_263 : BOOLEAN;
signal ap_sig_cseq_ST_st124_fsm_123 : STD_LOGIC;
signal ap_sig_bdd_271 : BOOLEAN;
signal reg_487 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_280 : BOOLEAN;
signal ap_sig_cseq_ST_st92_fsm_91 : STD_LOGIC;
signal ap_sig_bdd_289 : BOOLEAN;
signal grp_fu_421_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_493 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_299 : BOOLEAN;
signal ap_sig_cseq_ST_st86_fsm_85 : STD_LOGIC;
signal ap_sig_bdd_306 : BOOLEAN;
signal grp_fu_414_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_316 : BOOLEAN;
signal ap_sig_cseq_ST_st91_fsm_90 : STD_LOGIC;
signal ap_sig_bdd_323 : BOOLEAN;
signal reg_504 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_332 : BOOLEAN;
signal ap_sig_cseq_ST_st97_fsm_96 : STD_LOGIC;
signal ap_sig_bdd_339 : BOOLEAN;
signal grp_fu_436_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_509 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st24_fsm_23 : STD_LOGIC;
signal ap_sig_bdd_349 : BOOLEAN;
signal ap_sig_cseq_ST_st98_fsm_97 : STD_LOGIC;
signal ap_sig_bdd_356 : BOOLEAN;
signal grp_fu_453_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_514 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st42_fsm_41 : STD_LOGIC;
signal ap_sig_bdd_366 : BOOLEAN;
signal ap_sig_cseq_ST_st116_fsm_115 : STD_LOGIC;
signal ap_sig_bdd_373 : BOOLEAN;
signal grp_fu_433_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_520 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st79_fsm_78 : STD_LOGIC;
signal ap_sig_bdd_383 : BOOLEAN;
signal ap_sig_cseq_ST_st117_fsm_116 : STD_LOGIC;
signal ap_sig_bdd_390 : BOOLEAN;
signal P_floatIn_read_reg_1333 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_526_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_1338 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_numLayer_load_reg_1342 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_537_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_1349 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_fu_543_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_reg_1353 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_549_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_reg_1357 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_fu_555_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_reg_1361 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_561_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_reg_1365 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_fu_567_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_reg_1369 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_75_fu_597_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_75_reg_1373 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_fu_607_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_31_reg_1379 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_fu_671_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_6_reg_1389 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_16_fu_709_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_16_reg_1394 : STD_LOGIC_VECTOR (13 downto 0);
signal max_2_cast_fu_749_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal max_2_cast_reg_1402 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_459 : BOOLEAN;
signal tmp_24_fu_753_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_4_fu_786_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_4_reg_1420 : STD_LOGIC_VECTOR (30 downto 0);
signal ST_uOut_load_2_reg_1425 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_62_fu_869_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_62_reg_1431 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_485 : BOOLEAN;
signal max_1_fu_875_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_494 : BOOLEAN;
signal tmp_28_fu_914_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_28_reg_1444 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_503 : BOOLEAN;
signal tmp_3_fu_885_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_fu_920_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_29_reg_1449 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_37_fu_954_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_37_reg_1454 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_44_fu_960_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_44_reg_1459 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_55_fu_988_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_55_reg_1464 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_57_fu_994_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_57_reg_1469 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_63_fu_998_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_63_reg_1474 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_68_fu_1031_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_68_reg_1479 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_69_fu_1037_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_69_reg_1484 : STD_LOGIC_VECTOR (1 downto 0);
signal j_2_fu_1060_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_2_reg_1492 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_533 : BOOLEAN;
signal tmp_52_fu_1066_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_52_reg_1497 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_1054_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_uOut_addr_5_reg_1503 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_fu_1327_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_79_reg_1508 : STD_LOGIC_VECTOR (13 downto 0);
signal i_3_fu_1093_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_1_fu_1108_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_1_reg_1522 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_555 : BOOLEAN;
signal tmp_32_fu_1103_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_443_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_41_reg_1542 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st47_fsm_46 : STD_LOGIC;
signal ap_sig_bdd_575 : BOOLEAN;
signal grp_fu_448_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_42_reg_1547 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st78_fsm_77 : STD_LOGIC;
signal ap_sig_bdd_584 : BOOLEAN;
signal tmp_27_fu_1170_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_reg_1552 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st81_fsm_80 : STD_LOGIC;
signal ap_sig_bdd_593 : BOOLEAN;
signal i_5_fu_1189_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_5_reg_1560 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_53_fu_1195_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_53_reg_1565 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_fu_1183_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_uOut_addr_7_reg_1571 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_82_fu_1321_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_82_reg_1576 : STD_LOGIC_VECTOR (13 downto 0);
signal j_3_fu_1231_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal j_3_reg_1585 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st82_fsm_81 : STD_LOGIC;
signal ap_sig_bdd_614 : BOOLEAN;
signal tmp_33_fu_1226_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st122_fsm_121 : STD_LOGIC;
signal ap_sig_bdd_633 : BOOLEAN;
signal i_6_fu_1287_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_6_reg_1613 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st123_fsm_122 : STD_LOGIC;
signal ap_sig_bdd_642 : BOOLEAN;
signal ST_uOut_addr_8_reg_1618 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_34_fu_1282_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_428_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_51_reg_1624 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st140_fsm_139 : STD_LOGIC;
signal ap_sig_bdd_669 : BOOLEAN;
signal tmp_21_fu_1312_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_21_reg_1629 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_cseq_ST_st142_fsm_141 : STD_LOGIC;
signal ap_sig_bdd_678 : BOOLEAN;
signal max_2_reg_287 : STD_LOGIC_VECTOR (30 downto 0);
signal max_reg_298 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_311 : STD_LOGIC_VECTOR (30 downto 0);
signal j_reg_323 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st80_fsm_79 : STD_LOGIC;
signal ap_sig_bdd_700 : BOOLEAN;
signal sum_reg_334 : STD_LOGIC_VECTOR (31 downto 0);
signal k_reg_346 : STD_LOGIC_VECTOR (30 downto 0);
signal sumsoft_reg_357 : STD_LOGIC_VECTOR (31 downto 0);
signal i_1_reg_369 : STD_LOGIC_VECTOR (31 downto 0);
signal sum_1_reg_380 : STD_LOGIC_VECTOR (31 downto 0);
signal j_1_reg_392 : STD_LOGIC_VECTOR (30 downto 0);
signal i_2_reg_403 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st141_fsm_140 : STD_LOGIC;
signal ap_sig_bdd_722 : BOOLEAN;
signal tmp_65_cast_fu_661_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_9_fu_666_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_85_cast_fu_767_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_86_cast_fu_781_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_81_cast_fu_1088_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_87_cast_fu_1127_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_88_cast_fu_1137_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_89_cast_fu_1150_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_83_cast_fu_1217_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_90_cast_fu_1250_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_91_cast_fu_1260_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_92_cast_fu_1273_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_93_cast_fu_1302_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_21_cast_fu_1317_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st143_fsm_142 : STD_LOGIC;
signal ap_sig_bdd_750 : BOOLEAN;
signal tmp_5_fu_715_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_cseq_ST_st118_fsm_117 : STD_LOGIC;
signal ap_sig_bdd_816 : BOOLEAN;
signal grp_fu_414_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_414_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_835 : BOOLEAN;
signal ap_sig_cseq_ST_st19_fsm_18 : STD_LOGIC;
signal ap_sig_bdd_842 : BOOLEAN;
signal ap_sig_cseq_ST_st87_fsm_86 : STD_LOGIC;
signal ap_sig_bdd_850 : BOOLEAN;
signal ap_sig_cseq_ST_st93_fsm_92 : STD_LOGIC;
signal ap_sig_bdd_857 : BOOLEAN;
signal grp_fu_421_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_433_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_436_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_38_fu_1165_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_458_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_458_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_73_fu_573_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_74_fu_585_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl12_cast_fu_577_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl13_cast_fu_589_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_fu_607_p5 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_71_fu_625_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_72_fu_637_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl10_cast_fu_629_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl11_cast_fu_641_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_70_fu_621_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_64_fu_649_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_65_fu_655_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_11_fu_679_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_12_fu_691_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal p_shl_cast_fu_683_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl1_cast_fu_695_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_7_fu_675_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_13_fu_703_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_93_fu_758_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_85_fu_762_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_94_fu_772_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_86_fu_776_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal ST_uOut_load_1_to_int_fu_792_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_load_2_to_int_fu_810_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_fu_796_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_95_fu_806_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs_fu_833_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs_fu_827_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_56_fu_813_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_96_fu_823_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs2_fu_851_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs1_fu_845_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_58_fu_839_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_59_fu_857_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_60_fu_863_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_61_fu_439_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_cast_fu_881_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_fu_890_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_26_fu_902_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal p_shl8_cast_fu_894_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl9_cast_fu_906_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_15_fu_924_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_30_fu_930_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_35_fu_942_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl6_cast_fu_934_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl7_cast_fu_946_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_46_fu_964_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_50_fu_976_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal p_shl4_cast_fu_968_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl5_cast_fu_980_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_23_fu_1002_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_66_fu_1007_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_67_fu_1019_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl2_cast_fu_1011_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl3_cast_fu_1023_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_fu_1041_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_77_fu_1079_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_78_fu_1083_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 : string;
attribute use_dsp48 of tmp_78_fu_1083_p2 : signal is "no";
signal k_cast_fu_1099_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_98_fu_1118_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_87_fu_1122_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_97_fu_1114_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_88_fu_1132_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_88_fu_1132_p2 : signal is "no";
signal tmp_99_fu_1142_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_89_fu_1145_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_89_fu_1145_p2 : signal is "no";
signal tmp_38_to_int_fu_1155_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_38_neg_fu_1159_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_80_fu_1208_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_81_fu_1212_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_81_fu_1212_p2 : signal is "no";
signal j_1_cast_fu_1222_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_101_fu_1241_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_90_fu_1245_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_100_fu_1237_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_91_fu_1255_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_91_fu_1255_p2 : signal is "no";
signal tmp_102_fu_1265_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_92_fu_1268_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_92_fu_1268_p2 : signal is "no";
signal i_2_cast_fu_1278_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_83_fu_1293_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_84_fu_1297_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_19_fu_1307_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_82_fu_1321_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_79_fu_1327_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal grp_fu_414_ce : STD_LOGIC;
signal grp_fu_421_ce : STD_LOGIC;
signal grp_fu_428_ce : STD_LOGIC;
signal tmp_61_fu_439_opcode : STD_LOGIC_VECTOR (4 downto 0);
signal grp_fu_443_ce : STD_LOGIC;
signal grp_fu_448_ce : STD_LOGIC;
signal grp_fu_453_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (142 downto 0);
component ANN_fadd_32ns_32ns_32_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fmul_32ns_32ns_32_4_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fdiv_32ns_32ns_32_16 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fptrunc_64ns_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fpext_32ns_64_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_fcmp_32ns_32ns_1_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
opcode : IN STD_LOGIC_VECTOR (4 downto 0);
dout : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component ANN_dadd_64ns_64ns_64_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_ddiv_64ns_64ns_64_31 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_dexp_64ns_64ns_64_18_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_mux_4to1_sel2_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
din3_WIDTH : INTEGER;
din4_WIDTH : INTEGER;
din5_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
din2 : IN STD_LOGIC_VECTOR (31 downto 0);
din3 : IN STD_LOGIC_VECTOR (31 downto 0);
din4 : IN STD_LOGIC_VECTOR (31 downto 0);
din5 : IN STD_LOGIC_VECTOR (1 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_mul_mul_7ns_14s_14_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (6 downto 0);
din1 : IN STD_LOGIC_VECTOR (13 downto 0);
dout : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
component ANN_ST_WandB IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_ST_uOut IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (31 downto 0);
q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
P_mode : OUT STD_LOGIC_VECTOR (31 downto 0);
P_index1 : OUT STD_LOGIC_VECTOR (31 downto 0);
P_index2 : OUT STD_LOGIC_VECTOR (31 downto 0);
P_intIn_index3 : OUT STD_LOGIC_VECTOR (31 downto 0);
P_floatIn : OUT STD_LOGIC_VECTOR (31 downto 0);
P_floatOut : IN STD_LOGIC_VECTOR (31 downto 0);
P_floatOut_ap_vld : IN STD_LOGIC;
P_intOut : IN STD_LOGIC_VECTOR (31 downto 0);
P_intOut_ap_vld : IN STD_LOGIC );
end component;
begin
ST_WandB_U : component ANN_ST_WandB
generic map (
DataWidth => 32,
AddressRange => 6560,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_WandB_address0,
ce0 => ST_WandB_ce0,
we0 => ST_WandB_we0,
d0 => ST_WandB_d0,
q0 => ST_WandB_q0);
ST_uOut_U : component ANN_ST_uOut
generic map (
DataWidth => 32,
AddressRange => 160,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_uOut_address0,
ce0 => ST_uOut_ce0,
we0 => ST_uOut_we0,
d0 => ST_uOut_d0,
q0 => ST_uOut_q0,
address1 => ST_uOut_address1,
ce1 => ST_uOut_ce1,
we1 => ST_uOut_we1,
d1 => ST_uOut_d1,
q1 => ST_uOut_q1);
ANN_AXILiteS_s_axi_U : component ANN_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ANN_AXILiteS_s_axi_U_ap_dummy_ce,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
P_mode => P_mode,
P_index1 => P_index1,
P_index2 => P_index2,
P_intIn_index3 => P_intIn_index3,
P_floatIn => P_floatIn,
P_floatOut => P_floatOut,
P_floatOut_ap_vld => P_floatOut_ap_vld,
P_intOut => P_intOut,
P_intOut_ap_vld => P_intOut_ap_vld);
ANN_fadd_32ns_32ns_32_5_full_dsp_U0 : component ANN_fadd_32ns_32ns_32_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_414_p0,
din1 => grp_fu_414_p1,
ce => grp_fu_414_ce,
dout => grp_fu_414_p2);
ANN_fmul_32ns_32ns_32_4_max_dsp_U1 : component ANN_fmul_32ns_32ns_32_4_max_dsp
generic map (
ID => 1,
NUM_STAGE => 4,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_421_p0,
din1 => ST_WandB_q0,
ce => grp_fu_421_ce,
dout => grp_fu_421_p2);
ANN_fdiv_32ns_32ns_32_16_U2 : component ANN_fdiv_32ns_32ns_32_16
generic map (
ID => 1,
NUM_STAGE => 16,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_479,
din1 => sumsoft_reg_357,
ce => grp_fu_428_ce,
dout => grp_fu_428_p2);
ANN_fptrunc_64ns_32_1_U3 : component ANN_fptrunc_64ns_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 64,
dout_WIDTH => 32)
port map (
din0 => grp_fu_433_p0,
dout => grp_fu_433_p1);
ANN_fpext_32ns_64_1_U4 : component ANN_fpext_32ns_64_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
din0 => grp_fu_436_p0,
dout => grp_fu_436_p1);
ANN_fcmp_32ns_32ns_1_1_U5 : component ANN_fcmp_32ns_32ns_1_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 1)
port map (
din0 => reg_479,
din1 => ST_uOut_load_2_reg_1425,
opcode => tmp_61_fu_439_opcode,
dout => tmp_61_fu_439_p2);
ANN_dadd_64ns_64ns_64_5_full_dsp_U6 : component ANN_dadd_64ns_64ns_64_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_514,
din1 => ap_const_lv64_3FF0000000000000,
ce => grp_fu_443_ce,
dout => grp_fu_443_p2);
ANN_ddiv_64ns_64ns_64_31_U7 : component ANN_ddiv_64ns_64ns_64_31
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_3FF0000000000000,
din1 => tmp_41_reg_1542,
ce => grp_fu_448_ce,
dout => grp_fu_448_p2);
ANN_dexp_64ns_64ns_64_18_full_dsp_U8 : component ANN_dexp_64ns_64ns_64_18_full_dsp
generic map (
ID => 1,
NUM_STAGE => 18,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_0,
din1 => reg_509,
ce => grp_fu_453_ce,
dout => grp_fu_453_p2);
ANN_mux_4to1_sel2_32_1_U9 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_31_fu_607_p5,
dout => tmp_31_fu_607_p6);
ANN_mux_4to1_sel2_32_1_U10 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_29_reg_1449,
dout => tmp_fu_1041_p6);
ANN_mux_4to1_sel2_32_1_U11 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_44_reg_1459,
dout => tmp_52_fu_1066_p6);
ANN_mux_4to1_sel2_32_1_U12 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_63_reg_1474,
dout => tmp_27_fu_1170_p6);
ANN_mux_4to1_sel2_32_1_U13 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_69_reg_1484,
dout => tmp_53_fu_1195_p6);
ANN_mul_mul_7ns_14s_14_1_U14 : component ANN_mul_mul_7ns_14s_14_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 7,
din1_WIDTH => 14,
dout_WIDTH => 14)
port map (
din0 => tmp_82_fu_1321_p0,
din1 => tmp_81_fu_1212_p2,
dout => tmp_82_fu_1321_p2);
ANN_mul_mul_7ns_14s_14_1_U15 : component ANN_mul_mul_7ns_14s_14_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 7,
din1_WIDTH => 14,
dout_WIDTH => 14)
port map (
din0 => tmp_79_fu_1327_p0,
din1 => tmp_78_fu_1083_p2,
dout => tmp_79_fu_1327_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- i_1_reg_369 assign process. --
i_1_reg_369_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and (ap_const_lv1_0 = tmp_3_fu_885_p2))) then
i_1_reg_369 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121)) then
i_1_reg_369 <= i_5_reg_1560;
end if;
end if;
end process;
-- i_2_reg_403 assign process. --
i_2_reg_403_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80) and (ap_const_lv1_0 = tmp_22_fu_1183_p2))) then
i_2_reg_403 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) then
i_2_reg_403 <= i_6_reg_1613;
end if;
end if;
end process;
-- i_reg_311 assign process. --
i_reg_311_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and not((ap_const_lv1_0 = tmp_s_fu_555_p2)))) then
i_reg_311 <= ap_const_lv31_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and (ap_const_lv1_0 = tmp_20_fu_1054_p2))) then
i_reg_311 <= i_3_fu_1093_p2;
end if;
end if;
end process;
-- j_1_reg_392 assign process. --
j_1_reg_392_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80) and not((ap_const_lv1_0 = tmp_22_fu_1183_p2)))) then
j_1_reg_392 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st91_fsm_90)) then
j_1_reg_392 <= j_3_reg_1585;
end if;
end if;
end process;
-- j_reg_323 assign process. --
j_reg_323_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_3_fu_885_p2)))) then
j_reg_323 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) then
j_reg_323 <= j_2_reg_1492;
end if;
end if;
end process;
-- k_reg_346 assign process. --
k_reg_346_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = tmp_20_fu_1054_p2)))) then
k_reg_346 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
k_reg_346 <= k_1_reg_1522;
end if;
end if;
end process;
-- max_2_reg_287 assign process. --
max_2_reg_287_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2) and (ap_const_lv1_0 = tmp_10_fu_561_p2) and not((ap_const_lv1_0 = tmp_14_fu_567_p2)))) then
max_2_reg_287 <= ap_const_lv31_1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
max_2_reg_287 <= i_4_reg_1420;
end if;
end if;
end process;
-- max_reg_298 assign process. --
max_reg_298_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2) and (ap_const_lv1_0 = tmp_10_fu_561_p2) and not((ap_const_lv1_0 = tmp_14_fu_567_p2)))) then
max_reg_298 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
max_reg_298 <= max_1_fu_875_p3;
end if;
end if;
end process;
-- reg_479 assign process. --
reg_479_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
reg_479 <= ST_uOut_q1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) or (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123))) then
reg_479 <= ST_uOut_q0;
end if;
end if;
end process;
-- sum_1_reg_380 assign process. --
sum_1_reg_380_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80) and not((ap_const_lv1_0 = tmp_22_fu_1183_p2)))) then
sum_1_reg_380 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st91_fsm_90)) then
sum_1_reg_380 <= grp_fu_414_p2;
end if;
end if;
end process;
-- sum_reg_334 assign process. --
sum_reg_334_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = tmp_20_fu_1054_p2)))) then
sum_reg_334 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
sum_reg_334 <= grp_fu_414_p2;
end if;
end if;
end process;
-- sumsoft_reg_357 assign process. --
sumsoft_reg_357_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and (ap_const_lv1_0 = tmp_3_fu_885_p2))) then
sumsoft_reg_357 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121)) then
sumsoft_reg_357 <= grp_fu_414_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
P_floatIn_read_reg_1333 <= P_floatIn;
ST_numLayer_load_reg_1342 <= ST_numLayer;
tmp_1_reg_1338 <= tmp_1_fu_526_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and not((tmp_2_fu_537_p2 = ap_const_lv1_0)) and (tmp_5_fu_715_p1 = ap_const_lv2_0))) then
ST_layerSize_0 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and not((tmp_2_fu_537_p2 = ap_const_lv1_0)) and (tmp_5_fu_715_p1 = ap_const_lv2_1))) then
ST_layerSize_1 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and not((tmp_2_fu_537_p2 = ap_const_lv1_0)) and (tmp_5_fu_715_p1 = ap_const_lv2_2))) then
ST_layerSize_2 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and not((tmp_2_fu_537_p2 = ap_const_lv1_0)) and not((tmp_5_fu_715_p1 = ap_const_lv2_2)) and not((tmp_5_fu_715_p1 = ap_const_lv2_1)) and not((tmp_5_fu_715_p1 = ap_const_lv2_0)))) then
ST_layerSize_3 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and not((tmp_1_fu_526_p2 = ap_const_lv1_0)))) then
ST_numLayer <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = tmp_20_fu_1054_p2)))) then
ST_uOut_addr_5_reg_1503 <= tmp_81_cast_fu_1088_p1(8 - 1 downto 0);
tmp_52_reg_1497 <= tmp_52_fu_1066_p6;
tmp_79_reg_1508 <= tmp_79_fu_1327_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80) and not((ap_const_lv1_0 = tmp_22_fu_1183_p2)))) then
ST_uOut_addr_7_reg_1571 <= tmp_83_cast_fu_1217_p1(8 - 1 downto 0);
tmp_53_reg_1565 <= tmp_53_fu_1195_p6;
tmp_82_reg_1576 <= tmp_82_fu_1321_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122) and (tmp_1_reg_1338 = ap_const_lv1_0) and (tmp_2_reg_1349 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_reg_1353) and (ap_const_lv1_0 = tmp_8_reg_1357) and not((ap_const_lv1_0 = tmp_s_reg_1361)) and not((ap_const_lv1_0 = tmp_34_fu_1282_p2)))) then
ST_uOut_addr_8_reg_1618 <= tmp_93_cast_fu_1302_p1(8 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
ST_uOut_load_2_reg_1425 <= ST_uOut_q1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_10_reg_1365) and not((ap_const_lv1_0 = tmp_14_reg_1369)) and not((ap_const_lv1_0 = tmp_24_fu_753_p2)))) then
i_4_reg_1420 <= i_4_fu_786_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) then
i_5_reg_1560 <= i_5_fu_1189_p2;
tmp_27_reg_1552 <= tmp_27_fu_1170_p6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122) and (tmp_1_reg_1338 = ap_const_lv1_0) and (tmp_2_reg_1349 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_reg_1353) and (ap_const_lv1_0 = tmp_8_reg_1357) and not((ap_const_lv1_0 = tmp_s_reg_1361)))) then
i_6_reg_1613 <= i_6_fu_1287_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
j_2_reg_1492 <= j_2_fu_1060_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81)) then
j_3_reg_1585 <= j_3_fu_1231_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
k_1_reg_1522 <= k_1_fu_1108_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_10_reg_1365) and not((ap_const_lv1_0 = tmp_14_reg_1369)))) then
max_2_cast_reg_1402(30 downto 0) <= max_2_cast_fu_749_p1(30 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or (ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91))) then
reg_487 <= ST_WandB_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85))) then
reg_493 <= grp_fu_421_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22) or (ap_const_logic_1 = ap_sig_cseq_ST_st97_fsm_96))) then
reg_504 <= grp_fu_414_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) or (ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97))) then
reg_509 <= grp_fu_436_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41) or (ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_115))) then
reg_514 <= grp_fu_453_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116))) then
reg_520 <= grp_fu_433_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2))) then
tmp_10_reg_1365 <= tmp_10_fu_561_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2) and (ap_const_lv1_0 = tmp_10_fu_561_p2))) then
tmp_14_reg_1369 <= tmp_14_fu_567_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_4_fu_543_p2)))) then
tmp_16_reg_1394 <= tmp_16_fu_709_p2;
tmp_6_reg_1389 <= tmp_6_fu_671_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
tmp_21_reg_1629 <= tmp_21_fu_1312_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_3_fu_885_p2)))) then
tmp_28_reg_1444(13 downto 3) <= tmp_28_fu_914_p2(13 downto 3);
tmp_29_reg_1449 <= tmp_29_fu_920_p1;
tmp_37_reg_1454(8 downto 3) <= tmp_37_fu_954_p2(8 downto 3);
tmp_44_reg_1459 <= tmp_44_fu_960_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0))) then
tmp_2_reg_1349 <= tmp_2_fu_537_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2) and (ap_const_lv1_0 = tmp_10_fu_561_p2) and not((ap_const_lv1_0 = tmp_14_fu_567_p2)))) then
tmp_31_reg_1379 <= tmp_31_fu_607_p6;
tmp_75_reg_1373(8 downto 3) <= tmp_75_fu_597_p2(8 downto 3);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st47_fsm_46)) then
tmp_41_reg_1542 <= grp_fu_443_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) then
tmp_42_reg_1547 <= grp_fu_448_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0))) then
tmp_4_reg_1353 <= tmp_4_fu_543_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st140_fsm_139)) then
tmp_51_reg_1624 <= grp_fu_428_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and (ap_const_lv1_0 = tmp_3_fu_885_p2))) then
tmp_55_reg_1464(13 downto 3) <= tmp_55_fu_988_p2(13 downto 3);
tmp_57_reg_1469(8 downto 3) <= tmp_57_fu_994_p1(8 downto 3);
tmp_63_reg_1474 <= tmp_63_fu_998_p1;
tmp_68_reg_1479(8 downto 3) <= tmp_68_fu_1031_p2(8 downto 3);
tmp_69_reg_1484 <= tmp_69_fu_1037_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
tmp_62_reg_1431 <= tmp_62_fu_869_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2))) then
tmp_8_reg_1357 <= tmp_8_fu_549_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2))) then
tmp_s_reg_1361 <= tmp_s_fu_555_p2;
end if;
end if;
end process;
tmp_75_reg_1373(2 downto 0) <= "000";
max_2_cast_reg_1402(31) <= '0';
tmp_28_reg_1444(2 downto 0) <= "000";
tmp_37_reg_1454(2 downto 0) <= "000";
tmp_55_reg_1464(2 downto 0) <= "000";
tmp_57_reg_1469(2 downto 0) <= "000";
tmp_68_reg_1479(2 downto 0) <= "000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, tmp_1_fu_526_p2, tmp_1_reg_1338, tmp_2_fu_537_p2, tmp_2_reg_1349, tmp_4_fu_543_p2, tmp_4_reg_1353, tmp_8_fu_549_p2, tmp_8_reg_1357, tmp_s_fu_555_p2, tmp_s_reg_1361, tmp_10_reg_1365, tmp_14_reg_1369, tmp_24_fu_753_p2, tmp_3_fu_885_p2, tmp_20_fu_1054_p2, tmp_32_fu_1103_p2, tmp_22_fu_1183_p2, tmp_33_fu_1226_p2, tmp_34_fu_1282_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if ((not((ap_start = ap_const_logic_0)) and (not((tmp_1_fu_526_p2 = ap_const_lv1_0)) or not((tmp_2_fu_537_p2 = ap_const_lv1_0)) or ((ap_const_lv1_0 = tmp_4_fu_543_p2) and not((ap_const_lv1_0 = tmp_8_fu_549_p2)))))) then
ap_NS_fsm <= ap_ST_st123_fsm_122;
elsif ((not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif ((not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and not((ap_const_lv1_0 = tmp_s_fu_555_p2)))) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
elsif ((not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_4_fu_543_p2)))) then
ap_NS_fsm <= ap_ST_st142_fsm_141;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (((ap_const_lv1_0 = tmp_14_reg_1369) or (ap_const_lv1_0 = tmp_24_fu_753_p2) or not((ap_const_lv1_0 = tmp_10_reg_1365)))) then
ap_NS_fsm <= ap_ST_st123_fsm_122;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st6_fsm_5 =>
if ((ap_const_lv1_0 = tmp_3_fu_885_p2)) then
ap_NS_fsm <= ap_ST_st81_fsm_80;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when ap_ST_st7_fsm_6 =>
if ((ap_const_lv1_0 = tmp_20_fu_1054_p2)) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st8_fsm_7 =>
if ((ap_const_lv1_0 = tmp_32_fu_1103_p2)) then
ap_NS_fsm <= ap_ST_st18_fsm_17;
else
ap_NS_fsm <= ap_ST_st9_fsm_8;
end if;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
ap_NS_fsm <= ap_ST_st46_fsm_45;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
ap_NS_fsm <= ap_ST_st50_fsm_49;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st52_fsm_51;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st54_fsm_53;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st55_fsm_54;
when ap_ST_st55_fsm_54 =>
ap_NS_fsm <= ap_ST_st56_fsm_55;
when ap_ST_st56_fsm_55 =>
ap_NS_fsm <= ap_ST_st57_fsm_56;
when ap_ST_st57_fsm_56 =>
ap_NS_fsm <= ap_ST_st58_fsm_57;
when ap_ST_st58_fsm_57 =>
ap_NS_fsm <= ap_ST_st59_fsm_58;
when ap_ST_st59_fsm_58 =>
ap_NS_fsm <= ap_ST_st60_fsm_59;
when ap_ST_st60_fsm_59 =>
ap_NS_fsm <= ap_ST_st61_fsm_60;
when ap_ST_st61_fsm_60 =>
ap_NS_fsm <= ap_ST_st62_fsm_61;
when ap_ST_st62_fsm_61 =>
ap_NS_fsm <= ap_ST_st63_fsm_62;
when ap_ST_st63_fsm_62 =>
ap_NS_fsm <= ap_ST_st64_fsm_63;
when ap_ST_st64_fsm_63 =>
ap_NS_fsm <= ap_ST_st65_fsm_64;
when ap_ST_st65_fsm_64 =>
ap_NS_fsm <= ap_ST_st66_fsm_65;
when ap_ST_st66_fsm_65 =>
ap_NS_fsm <= ap_ST_st67_fsm_66;
when ap_ST_st67_fsm_66 =>
ap_NS_fsm <= ap_ST_st68_fsm_67;
when ap_ST_st68_fsm_67 =>
ap_NS_fsm <= ap_ST_st69_fsm_68;
when ap_ST_st69_fsm_68 =>
ap_NS_fsm <= ap_ST_st70_fsm_69;
when ap_ST_st70_fsm_69 =>
ap_NS_fsm <= ap_ST_st71_fsm_70;
when ap_ST_st71_fsm_70 =>
ap_NS_fsm <= ap_ST_st72_fsm_71;
when ap_ST_st72_fsm_71 =>
ap_NS_fsm <= ap_ST_st73_fsm_72;
when ap_ST_st73_fsm_72 =>
ap_NS_fsm <= ap_ST_st74_fsm_73;
when ap_ST_st74_fsm_73 =>
ap_NS_fsm <= ap_ST_st75_fsm_74;
when ap_ST_st75_fsm_74 =>
ap_NS_fsm <= ap_ST_st76_fsm_75;
when ap_ST_st76_fsm_75 =>
ap_NS_fsm <= ap_ST_st77_fsm_76;
when ap_ST_st77_fsm_76 =>
ap_NS_fsm <= ap_ST_st78_fsm_77;
when ap_ST_st78_fsm_77 =>
ap_NS_fsm <= ap_ST_st79_fsm_78;
when ap_ST_st79_fsm_78 =>
ap_NS_fsm <= ap_ST_st80_fsm_79;
when ap_ST_st80_fsm_79 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st81_fsm_80 =>
if (not((ap_const_lv1_0 = tmp_22_fu_1183_p2))) then
ap_NS_fsm <= ap_ST_st82_fsm_81;
else
ap_NS_fsm <= ap_ST_st123_fsm_122;
end if;
when ap_ST_st82_fsm_81 =>
if ((ap_const_lv1_0 = tmp_33_fu_1226_p2)) then
ap_NS_fsm <= ap_ST_st92_fsm_91;
else
ap_NS_fsm <= ap_ST_st83_fsm_82;
end if;
when ap_ST_st83_fsm_82 =>
ap_NS_fsm <= ap_ST_st84_fsm_83;
when ap_ST_st84_fsm_83 =>
ap_NS_fsm <= ap_ST_st85_fsm_84;
when ap_ST_st85_fsm_84 =>
ap_NS_fsm <= ap_ST_st86_fsm_85;
when ap_ST_st86_fsm_85 =>
ap_NS_fsm <= ap_ST_st87_fsm_86;
when ap_ST_st87_fsm_86 =>
ap_NS_fsm <= ap_ST_st88_fsm_87;
when ap_ST_st88_fsm_87 =>
ap_NS_fsm <= ap_ST_st89_fsm_88;
when ap_ST_st89_fsm_88 =>
ap_NS_fsm <= ap_ST_st90_fsm_89;
when ap_ST_st90_fsm_89 =>
ap_NS_fsm <= ap_ST_st91_fsm_90;
when ap_ST_st91_fsm_90 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st92_fsm_91 =>
ap_NS_fsm <= ap_ST_st93_fsm_92;
when ap_ST_st93_fsm_92 =>
ap_NS_fsm <= ap_ST_st94_fsm_93;
when ap_ST_st94_fsm_93 =>
ap_NS_fsm <= ap_ST_st95_fsm_94;
when ap_ST_st95_fsm_94 =>
ap_NS_fsm <= ap_ST_st96_fsm_95;
when ap_ST_st96_fsm_95 =>
ap_NS_fsm <= ap_ST_st97_fsm_96;
when ap_ST_st97_fsm_96 =>
ap_NS_fsm <= ap_ST_st98_fsm_97;
when ap_ST_st98_fsm_97 =>
ap_NS_fsm <= ap_ST_st99_fsm_98;
when ap_ST_st99_fsm_98 =>
ap_NS_fsm <= ap_ST_st100_fsm_99;
when ap_ST_st100_fsm_99 =>
ap_NS_fsm <= ap_ST_st101_fsm_100;
when ap_ST_st101_fsm_100 =>
ap_NS_fsm <= ap_ST_st102_fsm_101;
when ap_ST_st102_fsm_101 =>
ap_NS_fsm <= ap_ST_st103_fsm_102;
when ap_ST_st103_fsm_102 =>
ap_NS_fsm <= ap_ST_st104_fsm_103;
when ap_ST_st104_fsm_103 =>
ap_NS_fsm <= ap_ST_st105_fsm_104;
when ap_ST_st105_fsm_104 =>
ap_NS_fsm <= ap_ST_st106_fsm_105;
when ap_ST_st106_fsm_105 =>
ap_NS_fsm <= ap_ST_st107_fsm_106;
when ap_ST_st107_fsm_106 =>
ap_NS_fsm <= ap_ST_st108_fsm_107;
when ap_ST_st108_fsm_107 =>
ap_NS_fsm <= ap_ST_st109_fsm_108;
when ap_ST_st109_fsm_108 =>
ap_NS_fsm <= ap_ST_st110_fsm_109;
when ap_ST_st110_fsm_109 =>
ap_NS_fsm <= ap_ST_st111_fsm_110;
when ap_ST_st111_fsm_110 =>
ap_NS_fsm <= ap_ST_st112_fsm_111;
when ap_ST_st112_fsm_111 =>
ap_NS_fsm <= ap_ST_st113_fsm_112;
when ap_ST_st113_fsm_112 =>
ap_NS_fsm <= ap_ST_st114_fsm_113;
when ap_ST_st114_fsm_113 =>
ap_NS_fsm <= ap_ST_st115_fsm_114;
when ap_ST_st115_fsm_114 =>
ap_NS_fsm <= ap_ST_st116_fsm_115;
when ap_ST_st116_fsm_115 =>
ap_NS_fsm <= ap_ST_st117_fsm_116;
when ap_ST_st117_fsm_116 =>
ap_NS_fsm <= ap_ST_st118_fsm_117;
when ap_ST_st118_fsm_117 =>
ap_NS_fsm <= ap_ST_st119_fsm_118;
when ap_ST_st119_fsm_118 =>
ap_NS_fsm <= ap_ST_st120_fsm_119;
when ap_ST_st120_fsm_119 =>
ap_NS_fsm <= ap_ST_st121_fsm_120;
when ap_ST_st121_fsm_120 =>
ap_NS_fsm <= ap_ST_st122_fsm_121;
when ap_ST_st122_fsm_121 =>
ap_NS_fsm <= ap_ST_st81_fsm_80;
when ap_ST_st123_fsm_122 =>
if (((ap_const_lv1_0 = tmp_s_reg_1361) or (ap_const_lv1_0 = tmp_34_fu_1282_p2) or not((tmp_1_reg_1338 = ap_const_lv1_0)) or not((tmp_2_reg_1349 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_4_reg_1353)) or not((ap_const_lv1_0 = tmp_8_reg_1357)))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st124_fsm_123;
end if;
when ap_ST_st124_fsm_123 =>
ap_NS_fsm <= ap_ST_st125_fsm_124;
when ap_ST_st125_fsm_124 =>
ap_NS_fsm <= ap_ST_st126_fsm_125;
when ap_ST_st126_fsm_125 =>
ap_NS_fsm <= ap_ST_st127_fsm_126;
when ap_ST_st127_fsm_126 =>
ap_NS_fsm <= ap_ST_st128_fsm_127;
when ap_ST_st128_fsm_127 =>
ap_NS_fsm <= ap_ST_st129_fsm_128;
when ap_ST_st129_fsm_128 =>
ap_NS_fsm <= ap_ST_st130_fsm_129;
when ap_ST_st130_fsm_129 =>
ap_NS_fsm <= ap_ST_st131_fsm_130;
when ap_ST_st131_fsm_130 =>
ap_NS_fsm <= ap_ST_st132_fsm_131;
when ap_ST_st132_fsm_131 =>
ap_NS_fsm <= ap_ST_st133_fsm_132;
when ap_ST_st133_fsm_132 =>
ap_NS_fsm <= ap_ST_st134_fsm_133;
when ap_ST_st134_fsm_133 =>
ap_NS_fsm <= ap_ST_st135_fsm_134;
when ap_ST_st135_fsm_134 =>
ap_NS_fsm <= ap_ST_st136_fsm_135;
when ap_ST_st136_fsm_135 =>
ap_NS_fsm <= ap_ST_st137_fsm_136;
when ap_ST_st137_fsm_136 =>
ap_NS_fsm <= ap_ST_st138_fsm_137;
when ap_ST_st138_fsm_137 =>
ap_NS_fsm <= ap_ST_st139_fsm_138;
when ap_ST_st139_fsm_138 =>
ap_NS_fsm <= ap_ST_st140_fsm_139;
when ap_ST_st140_fsm_139 =>
ap_NS_fsm <= ap_ST_st141_fsm_140;
when ap_ST_st141_fsm_140 =>
ap_NS_fsm <= ap_ST_st123_fsm_122;
when ap_ST_st142_fsm_141 =>
ap_NS_fsm <= ap_ST_st143_fsm_142;
when ap_ST_st143_fsm_142 =>
ap_NS_fsm <= ap_ST_st123_fsm_122;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ANN_AXILiteS_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
P_floatOut <= ST_uOut_q0;
-- P_floatOut_ap_vld assign process. --
P_floatOut_ap_vld_assign_proc : process(tmp_10_reg_1365, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_10_reg_1365)))) then
P_floatOut_ap_vld <= ap_const_logic_1;
else
P_floatOut_ap_vld <= ap_const_logic_0;
end if;
end process;
P_intOut <= max_reg_298;
-- P_intOut_ap_vld assign process. --
P_intOut_ap_vld_assign_proc : process(tmp_10_reg_1365, tmp_14_reg_1369, ap_sig_cseq_ST_st2_fsm_1, tmp_24_fu_753_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_10_reg_1365) and not((ap_const_lv1_0 = tmp_14_reg_1369)) and (ap_const_lv1_0 = tmp_24_fu_753_p2))) then
P_intOut_ap_vld <= ap_const_logic_1;
else
P_intOut_ap_vld <= ap_const_logic_0;
end if;
end process;
-- ST_WandB_address0 assign process. --
ST_WandB_address0_assign_proc : process(ap_sig_cseq_ST_st8_fsm_7, tmp_32_fu_1103_p2, ap_sig_cseq_ST_st82_fsm_81, tmp_33_fu_1226_p2, tmp_88_cast_fu_1137_p1, tmp_89_cast_fu_1150_p1, tmp_91_cast_fu_1260_p1, tmp_92_cast_fu_1273_p1, tmp_21_cast_fu_1317_p1, ap_sig_cseq_ST_st143_fsm_142)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) then
ST_WandB_address0 <= tmp_21_cast_fu_1317_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and (ap_const_lv1_0 = tmp_33_fu_1226_p2))) then
ST_WandB_address0 <= tmp_92_cast_fu_1273_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_33_fu_1226_p2)))) then
ST_WandB_address0 <= tmp_91_cast_fu_1260_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and (ap_const_lv1_0 = tmp_32_fu_1103_p2))) then
ST_WandB_address0 <= tmp_89_cast_fu_1150_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((ap_const_lv1_0 = tmp_32_fu_1103_p2)))) then
ST_WandB_address0 <= tmp_88_cast_fu_1137_p1(13 - 1 downto 0);
else
ST_WandB_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
-- ST_WandB_ce0 assign process. --
ST_WandB_ce0_assign_proc : process(ap_sig_cseq_ST_st8_fsm_7, tmp_32_fu_1103_p2, ap_sig_cseq_ST_st82_fsm_81, tmp_33_fu_1226_p2, ap_sig_cseq_ST_st143_fsm_142)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((ap_const_lv1_0 = tmp_32_fu_1103_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and (ap_const_lv1_0 = tmp_32_fu_1103_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_33_fu_1226_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and (ap_const_lv1_0 = tmp_33_fu_1226_p2)) or (ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142))) then
ST_WandB_ce0 <= ap_const_logic_1;
else
ST_WandB_ce0 <= ap_const_logic_0;
end if;
end process;
ST_WandB_d0 <= P_floatIn_read_reg_1333;
-- ST_WandB_we0 assign process. --
ST_WandB_we0_assign_proc : process(ap_sig_cseq_ST_st143_fsm_142)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142))) then
ST_WandB_we0 <= ap_const_logic_1;
else
ST_WandB_we0 <= ap_const_logic_0;
end if;
end process;
-- ST_uOut_address0 assign process. --
ST_uOut_address0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, tmp_1_fu_526_p2, tmp_2_fu_537_p2, tmp_4_fu_543_p2, tmp_8_fu_549_p2, tmp_s_fu_555_p2, tmp_10_fu_561_p2, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st82_fsm_81, ap_sig_cseq_ST_st123_fsm_122, tmp_65_cast_fu_661_p1, tmp_9_fu_666_p1, tmp_85_cast_fu_767_p1, tmp_90_cast_fu_1250_p1, tmp_93_cast_fu_1302_p1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and not((ap_const_lv1_0 = tmp_8_fu_549_p2)))) then
ST_uOut_address0 <= tmp_9_fu_666_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) then
ST_uOut_address0 <= tmp_93_cast_fu_1302_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81)) then
ST_uOut_address0 <= tmp_90_cast_fu_1250_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
ST_uOut_address0 <= tmp_85_cast_fu_767_p1(8 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2) and not((ap_const_lv1_0 = tmp_10_fu_561_p2)))) then
ST_uOut_address0 <= tmp_65_cast_fu_661_p1(8 - 1 downto 0);
else
ST_uOut_address0 <= "XXXXXXXX";
end if;
end process;
-- ST_uOut_address1 assign process. --
ST_uOut_address1_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ST_uOut_addr_5_reg_1503, ap_sig_cseq_ST_st8_fsm_7, ST_uOut_addr_7_reg_1571, ST_uOut_addr_8_reg_1618, ap_sig_cseq_ST_st80_fsm_79, ap_sig_cseq_ST_st141_fsm_140, tmp_86_cast_fu_781_p1, tmp_87_cast_fu_1127_p1, ap_sig_cseq_ST_st118_fsm_117)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) then
ST_uOut_address1 <= ST_uOut_addr_8_reg_1618;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117)) then
ST_uOut_address1 <= ST_uOut_addr_7_reg_1571;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) then
ST_uOut_address1 <= ST_uOut_addr_5_reg_1503;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
ST_uOut_address1 <= tmp_87_cast_fu_1127_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
ST_uOut_address1 <= tmp_86_cast_fu_781_p1(8 - 1 downto 0);
else
ST_uOut_address1 <= "XXXXXXXX";
end if;
end process;
-- ST_uOut_ce0 assign process. --
ST_uOut_ce0_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, tmp_1_fu_526_p2, tmp_2_fu_537_p2, tmp_4_fu_543_p2, tmp_8_fu_549_p2, tmp_s_fu_555_p2, tmp_10_fu_561_p2, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st82_fsm_81, ap_sig_cseq_ST_st123_fsm_122)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2) and not((ap_const_lv1_0 = tmp_10_fu_561_p2))) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) or (ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and not((ap_const_lv1_0 = tmp_8_fu_549_p2))))) then
ST_uOut_ce0 <= ap_const_logic_1;
else
ST_uOut_ce0 <= ap_const_logic_0;
end if;
end process;
-- ST_uOut_ce1 assign process. --
ST_uOut_ce1_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st80_fsm_79, ap_sig_cseq_ST_st141_fsm_140, ap_sig_cseq_ST_st118_fsm_117)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) or (ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140) or (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117))) then
ST_uOut_ce1 <= ap_const_logic_1;
else
ST_uOut_ce1 <= ap_const_logic_0;
end if;
end process;
ST_uOut_d0 <= P_floatIn;
-- ST_uOut_d1 assign process. --
ST_uOut_d1_assign_proc : process(reg_520, tmp_51_reg_1624, ap_sig_cseq_ST_st80_fsm_79, ap_sig_cseq_ST_st141_fsm_140, ap_sig_cseq_ST_st118_fsm_117)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) then
ST_uOut_d1 <= tmp_51_reg_1624;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) or (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117))) then
ST_uOut_d1 <= reg_520;
else
ST_uOut_d1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
ST_uOut_load_1_to_int_fu_792_p1 <= reg_479;
ST_uOut_load_2_to_int_fu_810_p1 <= ST_uOut_load_2_reg_1425;
-- ST_uOut_we0 assign process. --
ST_uOut_we0_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, tmp_1_fu_526_p2, tmp_2_fu_537_p2, tmp_4_fu_543_p2, tmp_8_fu_549_p2)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and not((ap_const_lv1_0 = tmp_8_fu_549_p2))))) then
ST_uOut_we0 <= ap_const_logic_1;
else
ST_uOut_we0 <= ap_const_logic_0;
end if;
end process;
-- ST_uOut_we1 assign process. --
ST_uOut_we1_assign_proc : process(ap_sig_cseq_ST_st80_fsm_79, ap_sig_cseq_ST_st141_fsm_140, ap_sig_cseq_ST_st118_fsm_117)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) or (ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140) or (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117))) then
ST_uOut_we1 <= ap_const_logic_1;
else
ST_uOut_we1 <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(tmp_1_reg_1338, tmp_2_reg_1349, tmp_4_reg_1353, tmp_8_reg_1357, tmp_s_reg_1361, ap_sig_cseq_ST_st123_fsm_122, tmp_34_fu_1282_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122) and ((ap_const_lv1_0 = tmp_s_reg_1361) or (ap_const_lv1_0 = tmp_34_fu_1282_p2) or not((tmp_1_reg_1338 = ap_const_lv1_0)) or not((tmp_2_reg_1349 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_4_reg_1353)) or not((ap_const_lv1_0 = tmp_8_reg_1357))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(tmp_1_reg_1338, tmp_2_reg_1349, tmp_4_reg_1353, tmp_8_reg_1357, tmp_s_reg_1361, ap_sig_cseq_ST_st123_fsm_122, tmp_34_fu_1282_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122) and ((ap_const_lv1_0 = tmp_s_reg_1361) or (ap_const_lv1_0 = tmp_34_fu_1282_p2) or not((tmp_1_reg_1338 = ap_const_lv1_0)) or not((tmp_2_reg_1349 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_4_reg_1353)) or not((ap_const_lv1_0 = tmp_8_reg_1357))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_161 assign process. --
ap_sig_bdd_161_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_161 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_249 assign process. --
ap_sig_bdd_249_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_249 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_256 assign process. --
ap_sig_bdd_256_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_256 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_263 assign process. --
ap_sig_bdd_263_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_263 <= (ap_const_lv1_1 = ap_CS_fsm(82 downto 82));
end process;
-- ap_sig_bdd_271 assign process. --
ap_sig_bdd_271_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_271 <= (ap_const_lv1_1 = ap_CS_fsm(123 downto 123));
end process;
-- ap_sig_bdd_280 assign process. --
ap_sig_bdd_280_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_280 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_289 assign process. --
ap_sig_bdd_289_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_289 <= (ap_const_lv1_1 = ap_CS_fsm(91 downto 91));
end process;
-- ap_sig_bdd_299 assign process. --
ap_sig_bdd_299_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_299 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_306 assign process. --
ap_sig_bdd_306_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_306 <= (ap_const_lv1_1 = ap_CS_fsm(85 downto 85));
end process;
-- ap_sig_bdd_316 assign process. --
ap_sig_bdd_316_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_316 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_323 assign process. --
ap_sig_bdd_323_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_323 <= (ap_const_lv1_1 = ap_CS_fsm(90 downto 90));
end process;
-- ap_sig_bdd_332 assign process. --
ap_sig_bdd_332_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_332 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_339 assign process. --
ap_sig_bdd_339_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_339 <= (ap_const_lv1_1 = ap_CS_fsm(96 downto 96));
end process;
-- ap_sig_bdd_349 assign process. --
ap_sig_bdd_349_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_349 <= (ap_const_lv1_1 = ap_CS_fsm(23 downto 23));
end process;
-- ap_sig_bdd_356 assign process. --
ap_sig_bdd_356_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_356 <= (ap_const_lv1_1 = ap_CS_fsm(97 downto 97));
end process;
-- ap_sig_bdd_366 assign process. --
ap_sig_bdd_366_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_366 <= (ap_const_lv1_1 = ap_CS_fsm(41 downto 41));
end process;
-- ap_sig_bdd_373 assign process. --
ap_sig_bdd_373_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_373 <= (ap_const_lv1_1 = ap_CS_fsm(115 downto 115));
end process;
-- ap_sig_bdd_383 assign process. --
ap_sig_bdd_383_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_383 <= (ap_const_lv1_1 = ap_CS_fsm(78 downto 78));
end process;
-- ap_sig_bdd_390 assign process. --
ap_sig_bdd_390_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_390 <= (ap_const_lv1_1 = ap_CS_fsm(116 downto 116));
end process;
-- ap_sig_bdd_459 assign process. --
ap_sig_bdd_459_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_459 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_485 assign process. --
ap_sig_bdd_485_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_485 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_494 assign process. --
ap_sig_bdd_494_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_494 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_503 assign process. --
ap_sig_bdd_503_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_503 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_533 assign process. --
ap_sig_bdd_533_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_533 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_555 assign process. --
ap_sig_bdd_555_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_555 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_575 assign process. --
ap_sig_bdd_575_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_575 <= (ap_const_lv1_1 = ap_CS_fsm(46 downto 46));
end process;
-- ap_sig_bdd_584 assign process. --
ap_sig_bdd_584_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_584 <= (ap_const_lv1_1 = ap_CS_fsm(77 downto 77));
end process;
-- ap_sig_bdd_593 assign process. --
ap_sig_bdd_593_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_593 <= (ap_const_lv1_1 = ap_CS_fsm(80 downto 80));
end process;
-- ap_sig_bdd_614 assign process. --
ap_sig_bdd_614_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_614 <= (ap_const_lv1_1 = ap_CS_fsm(81 downto 81));
end process;
-- ap_sig_bdd_633 assign process. --
ap_sig_bdd_633_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_633 <= (ap_const_lv1_1 = ap_CS_fsm(121 downto 121));
end process;
-- ap_sig_bdd_642 assign process. --
ap_sig_bdd_642_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_642 <= (ap_const_lv1_1 = ap_CS_fsm(122 downto 122));
end process;
-- ap_sig_bdd_669 assign process. --
ap_sig_bdd_669_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_669 <= (ap_const_lv1_1 = ap_CS_fsm(139 downto 139));
end process;
-- ap_sig_bdd_678 assign process. --
ap_sig_bdd_678_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_678 <= (ap_const_lv1_1 = ap_CS_fsm(141 downto 141));
end process;
-- ap_sig_bdd_700 assign process. --
ap_sig_bdd_700_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_700 <= (ap_const_lv1_1 = ap_CS_fsm(79 downto 79));
end process;
-- ap_sig_bdd_722 assign process. --
ap_sig_bdd_722_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_722 <= (ap_const_lv1_1 = ap_CS_fsm(140 downto 140));
end process;
-- ap_sig_bdd_750 assign process. --
ap_sig_bdd_750_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_750 <= (ap_const_lv1_1 = ap_CS_fsm(142 downto 142));
end process;
-- ap_sig_bdd_816 assign process. --
ap_sig_bdd_816_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_816 <= (ap_const_lv1_1 = ap_CS_fsm(117 downto 117));
end process;
-- ap_sig_bdd_835 assign process. --
ap_sig_bdd_835_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_835 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_842 assign process. --
ap_sig_bdd_842_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_842 <= (ap_const_lv1_1 = ap_CS_fsm(18 downto 18));
end process;
-- ap_sig_bdd_850 assign process. --
ap_sig_bdd_850_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_850 <= (ap_const_lv1_1 = ap_CS_fsm(86 downto 86));
end process;
-- ap_sig_bdd_857 assign process. --
ap_sig_bdd_857_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_857 <= (ap_const_lv1_1 = ap_CS_fsm(92 downto 92));
end process;
-- ap_sig_cseq_ST_st116_fsm_115 assign process. --
ap_sig_cseq_ST_st116_fsm_115_assign_proc : process(ap_sig_bdd_373)
begin
if (ap_sig_bdd_373) then
ap_sig_cseq_ST_st116_fsm_115 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st116_fsm_115 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st117_fsm_116 assign process. --
ap_sig_cseq_ST_st117_fsm_116_assign_proc : process(ap_sig_bdd_390)
begin
if (ap_sig_bdd_390) then
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st118_fsm_117 assign process. --
ap_sig_cseq_ST_st118_fsm_117_assign_proc : process(ap_sig_bdd_816)
begin
if (ap_sig_bdd_816) then
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st122_fsm_121 assign process. --
ap_sig_cseq_ST_st122_fsm_121_assign_proc : process(ap_sig_bdd_633)
begin
if (ap_sig_bdd_633) then
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st123_fsm_122 assign process. --
ap_sig_cseq_ST_st123_fsm_122_assign_proc : process(ap_sig_bdd_642)
begin
if (ap_sig_bdd_642) then
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st124_fsm_123 assign process. --
ap_sig_cseq_ST_st124_fsm_123_assign_proc : process(ap_sig_bdd_271)
begin
if (ap_sig_bdd_271) then
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_299)
begin
if (ap_sig_bdd_299) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_835)
begin
if (ap_sig_bdd_835) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st140_fsm_139 assign process. --
ap_sig_cseq_ST_st140_fsm_139_assign_proc : process(ap_sig_bdd_669)
begin
if (ap_sig_bdd_669) then
ap_sig_cseq_ST_st140_fsm_139 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st140_fsm_139 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st141_fsm_140 assign process. --
ap_sig_cseq_ST_st141_fsm_140_assign_proc : process(ap_sig_bdd_722)
begin
if (ap_sig_bdd_722) then
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st142_fsm_141 assign process. --
ap_sig_cseq_ST_st142_fsm_141_assign_proc : process(ap_sig_bdd_678)
begin
if (ap_sig_bdd_678) then
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st143_fsm_142 assign process. --
ap_sig_cseq_ST_st143_fsm_142_assign_proc : process(ap_sig_bdd_750)
begin
if (ap_sig_bdd_750) then
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_316)
begin
if (ap_sig_bdd_316) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_280)
begin
if (ap_sig_bdd_280) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st19_fsm_18 assign process. --
ap_sig_cseq_ST_st19_fsm_18_assign_proc : process(ap_sig_bdd_842)
begin
if (ap_sig_bdd_842) then
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_161)
begin
if (ap_sig_bdd_161) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_332)
begin
if (ap_sig_bdd_332) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st24_fsm_23 assign process. --
ap_sig_cseq_ST_st24_fsm_23_assign_proc : process(ap_sig_bdd_349)
begin
if (ap_sig_bdd_349) then
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_459)
begin
if (ap_sig_bdd_459) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_249)
begin
if (ap_sig_bdd_249) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st42_fsm_41 assign process. --
ap_sig_cseq_ST_st42_fsm_41_assign_proc : process(ap_sig_bdd_366)
begin
if (ap_sig_bdd_366) then
ap_sig_cseq_ST_st42_fsm_41 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st42_fsm_41 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st47_fsm_46 assign process. --
ap_sig_cseq_ST_st47_fsm_46_assign_proc : process(ap_sig_bdd_575)
begin
if (ap_sig_bdd_575) then
ap_sig_cseq_ST_st47_fsm_46 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st47_fsm_46 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_485)
begin
if (ap_sig_bdd_485) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_494)
begin
if (ap_sig_bdd_494) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_503)
begin
if (ap_sig_bdd_503) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st78_fsm_77 assign process. --
ap_sig_cseq_ST_st78_fsm_77_assign_proc : process(ap_sig_bdd_584)
begin
if (ap_sig_bdd_584) then
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st79_fsm_78 assign process. --
ap_sig_cseq_ST_st79_fsm_78_assign_proc : process(ap_sig_bdd_383)
begin
if (ap_sig_bdd_383) then
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_533)
begin
if (ap_sig_bdd_533) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st80_fsm_79 assign process. --
ap_sig_cseq_ST_st80_fsm_79_assign_proc : process(ap_sig_bdd_700)
begin
if (ap_sig_bdd_700) then
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st81_fsm_80 assign process. --
ap_sig_cseq_ST_st81_fsm_80_assign_proc : process(ap_sig_bdd_593)
begin
if (ap_sig_bdd_593) then
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st82_fsm_81 assign process. --
ap_sig_cseq_ST_st82_fsm_81_assign_proc : process(ap_sig_bdd_614)
begin
if (ap_sig_bdd_614) then
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st83_fsm_82 assign process. --
ap_sig_cseq_ST_st83_fsm_82_assign_proc : process(ap_sig_bdd_263)
begin
if (ap_sig_bdd_263) then
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st86_fsm_85 assign process. --
ap_sig_cseq_ST_st86_fsm_85_assign_proc : process(ap_sig_bdd_306)
begin
if (ap_sig_bdd_306) then
ap_sig_cseq_ST_st86_fsm_85 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st86_fsm_85 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st87_fsm_86 assign process. --
ap_sig_cseq_ST_st87_fsm_86_assign_proc : process(ap_sig_bdd_850)
begin
if (ap_sig_bdd_850) then
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_555)
begin
if (ap_sig_bdd_555) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st91_fsm_90 assign process. --
ap_sig_cseq_ST_st91_fsm_90_assign_proc : process(ap_sig_bdd_323)
begin
if (ap_sig_bdd_323) then
ap_sig_cseq_ST_st91_fsm_90 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st91_fsm_90 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st92_fsm_91 assign process. --
ap_sig_cseq_ST_st92_fsm_91_assign_proc : process(ap_sig_bdd_289)
begin
if (ap_sig_bdd_289) then
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st93_fsm_92 assign process. --
ap_sig_cseq_ST_st93_fsm_92_assign_proc : process(ap_sig_bdd_857)
begin
if (ap_sig_bdd_857) then
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st97_fsm_96 assign process. --
ap_sig_cseq_ST_st97_fsm_96_assign_proc : process(ap_sig_bdd_339)
begin
if (ap_sig_bdd_339) then
ap_sig_cseq_ST_st97_fsm_96 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st97_fsm_96 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st98_fsm_97 assign process. --
ap_sig_cseq_ST_st98_fsm_97_assign_proc : process(ap_sig_bdd_356)
begin
if (ap_sig_bdd_356) then
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_256)
begin
if (ap_sig_bdd_256) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
grp_fu_414_ce <= ap_const_logic_1;
-- grp_fu_414_p0 assign process. --
grp_fu_414_p0_assign_proc : process(sum_reg_334, sumsoft_reg_357, sum_1_reg_380, ap_sig_cseq_ST_st118_fsm_117, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st87_fsm_86, ap_sig_cseq_ST_st93_fsm_92)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117)) then
grp_fu_414_p0 <= sumsoft_reg_357;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86) or (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92))) then
grp_fu_414_p0 <= sum_1_reg_380;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) or (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18))) then
grp_fu_414_p0 <= sum_reg_334;
else
grp_fu_414_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_414_p1 assign process. --
grp_fu_414_p1_assign_proc : process(reg_487, reg_493, reg_520, ap_sig_cseq_ST_st118_fsm_117, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st87_fsm_86, ap_sig_cseq_ST_st93_fsm_92)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117)) then
grp_fu_414_p1 <= reg_520;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92))) then
grp_fu_414_p1 <= reg_487;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) or (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86))) then
grp_fu_414_p1 <= reg_493;
else
grp_fu_414_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_421_ce <= ap_const_logic_1;
-- grp_fu_421_p0 assign process. --
grp_fu_421_p0_assign_proc : process(ST_uOut_q0, ST_uOut_q1, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st83_fsm_82)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82)) then
grp_fu_421_p0 <= ST_uOut_q0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
grp_fu_421_p0 <= ST_uOut_q1;
else
grp_fu_421_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_428_ce <= ap_const_logic_1;
-- grp_fu_433_p0 assign process. --
grp_fu_433_p0_assign_proc : process(reg_514, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st117_fsm_116, tmp_42_reg_1547)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116)) then
grp_fu_433_p0 <= reg_514;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
grp_fu_433_p0 <= tmp_42_reg_1547;
else
grp_fu_433_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_436_p0 assign process. --
grp_fu_436_p0_assign_proc : process(reg_504, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st98_fsm_97, tmp_38_fu_1165_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97)) then
grp_fu_436_p0 <= reg_504;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23)) then
grp_fu_436_p0 <= tmp_38_fu_1165_p1;
else
grp_fu_436_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_443_ce <= ap_const_logic_1;
grp_fu_448_ce <= ap_const_logic_1;
grp_fu_453_ce <= ap_const_logic_1;
-- grp_fu_458_p1 assign process. --
grp_fu_458_p1_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ST_numLayer, ST_numLayer_load_reg_1342, ap_sig_cseq_ST_st6_fsm_5)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
grp_fu_458_p1 <= ST_numLayer_load_reg_1342;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
grp_fu_458_p1 <= ST_numLayer;
else
grp_fu_458_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_458_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFF) + signed(grp_fu_458_p1));
i_2_cast_fu_1278_p1 <= std_logic_vector(resize(unsigned(i_2_reg_403),32));
i_3_fu_1093_p2 <= std_logic_vector(unsigned(i_reg_311) + unsigned(ap_const_lv31_1));
i_4_fu_786_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(max_2_reg_287));
i_5_fu_1189_p2 <= std_logic_vector(unsigned(i_1_reg_369) + unsigned(ap_const_lv32_1));
i_6_fu_1287_p2 <= std_logic_vector(unsigned(i_2_reg_403) + unsigned(ap_const_lv31_1));
i_cast_fu_881_p1 <= std_logic_vector(resize(unsigned(i_reg_311),32));
j_1_cast_fu_1222_p1 <= std_logic_vector(resize(unsigned(j_1_reg_392),32));
j_2_fu_1060_p2 <= std_logic_vector(unsigned(j_reg_323) + unsigned(ap_const_lv32_1));
j_3_fu_1231_p2 <= std_logic_vector(unsigned(j_1_reg_392) + unsigned(ap_const_lv31_1));
k_1_fu_1108_p2 <= std_logic_vector(unsigned(k_reg_346) + unsigned(ap_const_lv31_1));
k_cast_fu_1099_p1 <= std_logic_vector(resize(unsigned(k_reg_346),32));
max_1_fu_875_p3 <=
max_2_cast_reg_1402 when (tmp_62_reg_1431(0) = '1') else
max_reg_298;
max_2_cast_fu_749_p1 <= std_logic_vector(resize(unsigned(max_2_reg_287),32));
notlhs1_fu_845_p2 <= "0" when (tmp_56_fu_813_p4 = ap_const_lv8_FF) else "1";
notlhs_fu_827_p2 <= "0" when (tmp_54_fu_796_p4 = ap_const_lv8_FF) else "1";
notrhs2_fu_851_p2 <= "1" when (tmp_96_fu_823_p1 = ap_const_lv23_0) else "0";
notrhs_fu_833_p2 <= "1" when (tmp_95_fu_806_p1 = ap_const_lv23_0) else "0";
p_shl10_cast_fu_629_p3 <= (tmp_71_fu_625_p1 & ap_const_lv5_0);
p_shl11_cast_fu_641_p3 <= (tmp_72_fu_637_p1 & ap_const_lv3_0);
p_shl12_cast_fu_577_p3 <= (tmp_73_fu_573_p1 & ap_const_lv5_0);
p_shl13_cast_fu_589_p3 <= (tmp_74_fu_585_p1 & ap_const_lv3_0);
p_shl1_cast_fu_695_p3 <= (tmp_12_fu_691_p1 & ap_const_lv3_0);
p_shl2_cast_fu_1011_p3 <= (tmp_66_fu_1007_p1 & ap_const_lv5_0);
p_shl3_cast_fu_1023_p3 <= (tmp_67_fu_1019_p1 & ap_const_lv3_0);
p_shl4_cast_fu_968_p3 <= (tmp_46_fu_964_p1 & ap_const_lv5_0);
p_shl5_cast_fu_980_p3 <= (tmp_50_fu_976_p1 & ap_const_lv3_0);
p_shl6_cast_fu_934_p3 <= (tmp_30_fu_930_p1 & ap_const_lv5_0);
p_shl7_cast_fu_946_p3 <= (tmp_35_fu_942_p1 & ap_const_lv3_0);
p_shl8_cast_fu_894_p3 <= (tmp_25_fu_890_p1 & ap_const_lv5_0);
p_shl9_cast_fu_906_p3 <= (tmp_26_fu_902_p1 & ap_const_lv3_0);
p_shl_cast_fu_683_p3 <= (tmp_11_fu_679_p1 & ap_const_lv5_0);
tmp_100_fu_1237_p1 <= j_1_reg_392(14 - 1 downto 0);
tmp_101_fu_1241_p1 <= j_1_reg_392(9 - 1 downto 0);
tmp_102_fu_1265_p1 <= tmp_53_reg_1565(14 - 1 downto 0);
tmp_10_fu_561_p2 <= "1" when (P_mode = ap_const_lv32_6) else "0";
tmp_11_fu_679_p1 <= P_index1(9 - 1 downto 0);
tmp_12_fu_691_p1 <= P_index1(11 - 1 downto 0);
tmp_13_fu_703_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_683_p3) + unsigned(p_shl1_cast_fu_695_p3));
tmp_14_fu_567_p2 <= "1" when (P_mode = ap_const_lv32_7) else "0";
tmp_15_fu_924_p2 <= std_logic_vector(signed(ap_const_lv31_7FFFFFFF) + signed(i_reg_311));
tmp_16_fu_709_p2 <= std_logic_vector(unsigned(tmp_7_fu_675_p1) + unsigned(tmp_13_fu_703_p2));
tmp_19_fu_1307_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv14_29) * signed(tmp_16_reg_1394))), 14));
tmp_1_fu_526_p2 <= "1" when (P_mode = ap_const_lv32_1) else "0";
tmp_20_fu_1054_p2 <= "1" when (signed(j_reg_323) < signed(tmp_fu_1041_p6)) else "0";
tmp_21_cast_fu_1317_p1 <= std_logic_vector(resize(signed(tmp_21_reg_1629),64));
tmp_21_fu_1312_p2 <= std_logic_vector(unsigned(tmp_6_reg_1389) + unsigned(tmp_19_fu_1307_p2));
tmp_22_fu_1183_p2 <= "1" when (signed(i_1_reg_369) < signed(tmp_27_fu_1170_p6)) else "0";
tmp_23_fu_1002_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFE) + signed(ST_numLayer_load_reg_1342));
tmp_24_fu_753_p2 <= "1" when (signed(max_2_cast_fu_749_p1) < signed(tmp_31_reg_1379)) else "0";
tmp_25_fu_890_p1 <= i_reg_311(9 - 1 downto 0);
tmp_26_fu_902_p1 <= i_reg_311(11 - 1 downto 0);
tmp_28_fu_914_p2 <= std_logic_vector(unsigned(p_shl8_cast_fu_894_p3) + unsigned(p_shl9_cast_fu_906_p3));
tmp_29_fu_920_p1 <= i_reg_311(2 - 1 downto 0);
tmp_2_fu_537_p2 <= "1" when (P_mode = ap_const_lv32_2) else "0";
tmp_30_fu_930_p1 <= tmp_15_fu_924_p2(4 - 1 downto 0);
tmp_31_fu_607_p5 <= grp_fu_458_p2(2 - 1 downto 0);
tmp_32_fu_1103_p2 <= "1" when (signed(k_cast_fu_1099_p1) < signed(tmp_52_reg_1497)) else "0";
tmp_33_fu_1226_p2 <= "1" when (signed(j_1_cast_fu_1222_p1) < signed(tmp_53_reg_1565)) else "0";
tmp_34_fu_1282_p2 <= "1" when (signed(i_2_cast_fu_1278_p1) < signed(tmp_27_reg_1552)) else "0";
tmp_35_fu_942_p1 <= tmp_15_fu_924_p2(6 - 1 downto 0);
tmp_37_fu_954_p2 <= std_logic_vector(unsigned(p_shl6_cast_fu_934_p3) + unsigned(p_shl7_cast_fu_946_p3));
tmp_38_fu_1165_p1 <= tmp_38_neg_fu_1159_p2;
tmp_38_neg_fu_1159_p2 <= (tmp_38_to_int_fu_1155_p1 xor ap_const_lv32_80000000);
tmp_38_to_int_fu_1155_p1 <= reg_504;
tmp_3_fu_885_p2 <= "1" when (signed(i_cast_fu_881_p1) < signed(ST_numLayer_load_reg_1342)) else "0";
tmp_44_fu_960_p1 <= tmp_15_fu_924_p2(2 - 1 downto 0);
tmp_46_fu_964_p1 <= grp_fu_458_p2(9 - 1 downto 0);
tmp_4_fu_543_p2 <= "1" when (P_mode = ap_const_lv32_3) else "0";
tmp_50_fu_976_p1 <= grp_fu_458_p2(11 - 1 downto 0);
tmp_54_fu_796_p4 <= ST_uOut_load_1_to_int_fu_792_p1(30 downto 23);
tmp_55_fu_988_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_968_p3) + unsigned(p_shl5_cast_fu_980_p3));
tmp_56_fu_813_p4 <= ST_uOut_load_2_to_int_fu_810_p1(30 downto 23);
tmp_57_fu_994_p1 <= tmp_55_fu_988_p2(9 - 1 downto 0);
tmp_58_fu_839_p2 <= (notrhs_fu_833_p2 or notlhs_fu_827_p2);
tmp_59_fu_857_p2 <= (notrhs2_fu_851_p2 or notlhs1_fu_845_p2);
tmp_5_fu_715_p1 <= P_index1(2 - 1 downto 0);
tmp_60_fu_863_p2 <= (tmp_58_fu_839_p2 and tmp_59_fu_857_p2);
tmp_61_fu_439_opcode <= ap_const_lv5_2;
tmp_62_fu_869_p2 <= (tmp_60_fu_863_p2 and tmp_61_fu_439_p2);
tmp_63_fu_998_p1 <= grp_fu_458_p2(2 - 1 downto 0);
tmp_64_fu_649_p2 <= std_logic_vector(unsigned(p_shl10_cast_fu_629_p3) + unsigned(p_shl11_cast_fu_641_p3));
tmp_65_cast_fu_661_p1 <= std_logic_vector(resize(signed(tmp_65_fu_655_p2),64));
tmp_65_fu_655_p2 <= std_logic_vector(unsigned(tmp_70_fu_621_p1) + unsigned(tmp_64_fu_649_p2));
tmp_66_fu_1007_p1 <= tmp_23_fu_1002_p2(4 - 1 downto 0);
tmp_67_fu_1019_p1 <= tmp_23_fu_1002_p2(6 - 1 downto 0);
tmp_68_fu_1031_p2 <= std_logic_vector(unsigned(p_shl2_cast_fu_1011_p3) + unsigned(p_shl3_cast_fu_1023_p3));
tmp_69_fu_1037_p1 <= tmp_23_fu_1002_p2(2 - 1 downto 0);
tmp_6_fu_671_p1 <= P_intIn_index3(14 - 1 downto 0);
tmp_70_fu_621_p1 <= P_index2(9 - 1 downto 0);
tmp_71_fu_625_p1 <= P_index1(4 - 1 downto 0);
tmp_72_fu_637_p1 <= P_index1(6 - 1 downto 0);
tmp_73_fu_573_p1 <= grp_fu_458_p2(4 - 1 downto 0);
tmp_74_fu_585_p1 <= grp_fu_458_p2(6 - 1 downto 0);
tmp_75_fu_597_p2 <= std_logic_vector(unsigned(p_shl12_cast_fu_577_p3) + unsigned(p_shl13_cast_fu_589_p3));
tmp_77_fu_1079_p1 <= j_reg_323(14 - 1 downto 0);
tmp_78_fu_1083_p2 <= std_logic_vector(unsigned(tmp_28_reg_1444) + unsigned(tmp_77_fu_1079_p1));
tmp_79_fu_1327_p0 <= ap_const_lv14_29(7 - 1 downto 0);
tmp_7_fu_675_p1 <= P_index2(14 - 1 downto 0);
tmp_80_fu_1208_p1 <= i_1_reg_369(14 - 1 downto 0);
tmp_81_cast_fu_1088_p1 <= std_logic_vector(resize(signed(tmp_78_fu_1083_p2),64));
tmp_81_fu_1212_p2 <= std_logic_vector(unsigned(tmp_55_reg_1464) + unsigned(tmp_80_fu_1208_p1));
tmp_82_fu_1321_p0 <= ap_const_lv14_29(7 - 1 downto 0);
tmp_83_cast_fu_1217_p1 <= std_logic_vector(resize(signed(tmp_81_fu_1212_p2),64));
tmp_83_fu_1293_p1 <= i_2_reg_403(9 - 1 downto 0);
tmp_84_fu_1297_p2 <= std_logic_vector(unsigned(tmp_57_reg_1469) + unsigned(tmp_83_fu_1293_p1));
tmp_85_cast_fu_767_p1 <= std_logic_vector(resize(signed(tmp_85_fu_762_p2),64));
tmp_85_fu_762_p2 <= std_logic_vector(unsigned(tmp_93_fu_758_p1) + unsigned(tmp_75_reg_1373));
tmp_86_cast_fu_781_p1 <= std_logic_vector(resize(signed(tmp_86_fu_776_p2),64));
tmp_86_fu_776_p2 <= std_logic_vector(unsigned(tmp_94_fu_772_p1) + unsigned(tmp_75_reg_1373));
tmp_87_cast_fu_1127_p1 <= std_logic_vector(resize(unsigned(tmp_87_fu_1122_p2),64));
tmp_87_fu_1122_p2 <= std_logic_vector(unsigned(tmp_37_reg_1454) + unsigned(tmp_98_fu_1118_p1));
tmp_88_cast_fu_1137_p1 <= std_logic_vector(resize(signed(tmp_88_fu_1132_p2),64));
tmp_88_fu_1132_p2 <= std_logic_vector(signed(tmp_79_reg_1508) + signed(tmp_97_fu_1114_p1));
tmp_89_cast_fu_1150_p1 <= std_logic_vector(resize(signed(tmp_89_fu_1145_p2),64));
tmp_89_fu_1145_p2 <= std_logic_vector(signed(tmp_79_reg_1508) + signed(tmp_99_fu_1142_p1));
tmp_8_fu_549_p2 <= "1" when (P_mode = ap_const_lv32_4) else "0";
tmp_90_cast_fu_1250_p1 <= std_logic_vector(resize(signed(tmp_90_fu_1245_p2),64));
tmp_90_fu_1245_p2 <= std_logic_vector(unsigned(tmp_68_reg_1479) + unsigned(tmp_101_fu_1241_p1));
tmp_91_cast_fu_1260_p1 <= std_logic_vector(resize(signed(tmp_91_fu_1255_p2),64));
tmp_91_fu_1255_p2 <= std_logic_vector(signed(tmp_82_reg_1576) + signed(tmp_100_fu_1237_p1));
tmp_92_cast_fu_1273_p1 <= std_logic_vector(resize(signed(tmp_92_fu_1268_p2),64));
tmp_92_fu_1268_p2 <= std_logic_vector(signed(tmp_82_reg_1576) + signed(tmp_102_fu_1265_p1));
tmp_93_cast_fu_1302_p1 <= std_logic_vector(resize(signed(tmp_84_fu_1297_p2),64));
tmp_93_fu_758_p1 <= max_2_reg_287(9 - 1 downto 0);
tmp_94_fu_772_p1 <= max_reg_298(9 - 1 downto 0);
tmp_95_fu_806_p1 <= ST_uOut_load_1_to_int_fu_792_p1(23 - 1 downto 0);
tmp_96_fu_823_p1 <= ST_uOut_load_2_to_int_fu_810_p1(23 - 1 downto 0);
tmp_97_fu_1114_p1 <= k_reg_346(14 - 1 downto 0);
tmp_98_fu_1118_p1 <= k_reg_346(9 - 1 downto 0);
tmp_99_fu_1142_p1 <= tmp_52_reg_1497(14 - 1 downto 0);
tmp_9_fu_666_p1 <= std_logic_vector(resize(signed(P_index1),64));
tmp_s_fu_555_p2 <= "1" when (P_mode = ap_const_lv32_5) else "0";
end behav;
| gpl-3.0 | bd87d6613b8677826dcf72d5bd84b0a2 | 0.629247 | 3.146008 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_rst_processing_system7_0_100M_0/synth/design_SWandHW_standalone_rst_processing_system7_0_100M_0.vhd | 1 | 7,023 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_8;
USE proc_sys_reset_v5_0_8.proc_sys_reset;
ENTITY design_SWandHW_standalone_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_SWandHW_standalone_rst_processing_system7_0_100M_0;
ARCHITECTURE design_SWandHW_standalone_rst_processing_system7_0_100M_0_arch OF design_SWandHW_standalone_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "design_SWandHW_standalone_rst_processing_system7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SWandHW_standalone_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "design_SWandHW_standalone_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_SWandHW_standalone_rst_processing_system7_0_100M_0_arch;
| gpl-3.0 | c0780f2ec37b46550d327d731d012853 | 0.723053 | 3.481904 | false | false | false | false |
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`protect end_protected
| gpl-3.0 | e524b2a1a837004dd1b44fe8d1088fe4 | 0.916595 | 1.935751 | false | false | false | false |
bonfireprocessor/bonfire-soc | uart/uart.vhd | 1 | 9,763 | --+-----------------------------------+-------------------------------------+--
--| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
--| ___ ___ ___ ___( _ ) / _ \ | [email protected] |--
--| / __|/ _ \ / __|_ / _ \| | | | | |--
--| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
--| |___/\___/ \___/___\___/ \___/ | |--
--| | http://sowerbutts.com/ |--
--+-----------------------------------+-------------------------------------+--
--| UART implementation |--
--| TH: Added runtime configuration of the baud rate |--
--+-------------------------------------------------------------------------+--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity uart is
generic (
clk_frequency : natural := (128 * 1000000)
);
port ( clk : in std_logic;
serial_out : out std_logic;
serial_in : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_in_load : in std_logic;
data_out : out std_logic_vector(7 downto 0);
data_out_ready : out std_logic;
bad_bit : out std_logic;
transmitter_busy : out std_logic;
can_transmit : in std_logic;
sample_clock_divisor : in std_logic_vector(7 downto 0); --TH
divisor_wen : in std_logic --TH
);
end uart;
architecture Behavioral of uart is
constant counter_len : natural := 13;
-- tested at 1,000,000bps with 48MHz clock. Works (apparently).
constant c_rx_sample_interval : unsigned(7 downto 0) := to_unsigned(clk_frequency / (115200 * 16) - 1,8); -- clock speed / (baud x 16) - 1 ; eg 32MHz / (9600 * 16) - 1 = 207
constant c_bit_duration : unsigned(counter_len-1 downto 0) := to_unsigned(clk_frequency / (115200 * 1) - 1, counter_len); -- clock speed / baud - 1 ; eg 32MHz / 9600 - 1 = 3332
signal rx_sample_interval : unsigned(7 downto 0) := c_rx_sample_interval;
signal bit_duration : unsigned(counter_len-1 downto 0) := c_bit_duration;
signal tx_counter : unsigned(counter_len-1 downto 0) := to_unsigned(0, counter_len);
signal tx_shift_reg : std_logic_vector(8 downto 0) := "111111111";
signal tx_bits_left : unsigned(3 downto 0) := to_unsigned(0, 4);
signal tx_busy : std_logic;
signal rx_counter : unsigned(counter_len-1 downto 0) := to_unsigned(0, counter_len);
signal rx_shift_reg : std_logic_vector(8 downto 0) := "000000000";
signal rx_bits_got : unsigned(3 downto 0) := to_unsigned(0, 4);
signal rx_state : unsigned(7 downto 0) := (others => '0'); -- 10 bits x 16 samples each = at least 160 states.
signal rx_out_ready : std_logic := '0';
signal data_out_buf : std_logic_vector(7 downto 0) := "00000000";
signal rx_clkin1 : std_logic := '0';
signal rx_clkin2 : std_logic := '0';
signal rx_sample1 : std_logic := '0';
signal rx_sample2 : std_logic := '0';
signal rx_sample3 : std_logic := '0';
signal rx_sample_majority : std_logic;
signal rx_badbit : std_logic := '0';
-- Place TX in IOB Register
signal tx : std_logic; -- UART Out
attribute IOB: string;
attribute IOB of tx: signal is "true";
begin
serial_out <= tx; -- Connect TX line...
-- Sample Clock Divisior setting
process(clk)
variable d : unsigned(7 downto 0);
begin
if rising_edge(clk) then
if divisor_wen='1' then
d:=unsigned(sample_clock_divisor);
rx_sample_interval <= d;
bit_duration <= ((resize(d,9)+1)&"0000"); -- (divisor+1) * 16
end if;
end if;
end process;
-- -- receiver -- --
--
-- Incoming data is oversampled 16 times. We check three samples in the
-- middle of each bit and take a simple majority. There is provision for
-- rejecting noise where a start bit should have been. We compensate for
-- small amounts of clock drift by potentially cutting a stop bit short.
--
-- This is not dissimilar to how the AVR USART receiver works.
--
data_out_ready <= rx_out_ready;
bad_bit <= rx_badbit;
data_out <= data_out_buf;
rx_sample_majority <= (rx_sample1 and rx_sample2) or (rx_sample1 and rx_sample3) or (rx_sample2 and rx_sample3); -- simple majority wins
receiver: process(clk)
begin
if rising_edge(clk) then
-- Bring serial_in into our clock domain
rx_clkin1 <= serial_in;
rx_clkin2 <= rx_clkin1; -- rx_clkin2 should now be safe to use.
-- We latch the incoming serial data at full clock speed (NOT divided down)
rx_sample1 <= rx_clkin2;
rx_out_ready <= '0';
-- bad bit
rx_badbit <= rx_badbit;
-- clock divider
rx_counter <= rx_counter + 1;
if rx_counter = rx_sample_interval then
rx_counter <= (others => '0');
if rx_state = "00000000" then
-- line is in the idle state, we're waiting for a start bit!
-- the anticipation is killing me.
if rx_sample1 = '0' then
rx_state <= "00000001"; -- and we're off!
rx_counter <= (others => '0');
end if;
elsif rx_state = "10011010" then
-- wait for the line to be idle. we don't leave this state until the serial line
-- goes high (it should be already, because we should be in mid stop bit).
if rx_sample1 = '1' then
rx_state <= "00000000";
end if;
else
-- we're in the normal bit reception pattern
rx_state <= rx_state + 1;
-- rx_sample1 contains the incoming serial data, latched
rx_sample3 <= rx_sample2;
rx_sample2 <= rx_sample1;
-- when we have the three middle samples, update the shift register
if rx_state(3 downto 0) = "1001" then
rx_shift_reg <= rx_sample_majority & rx_shift_reg(rx_shift_reg'length-1 downto 1);
-- false start bit noise rejection: if we read the start bit as a logical 1, start over again.
if (rx_state(7 downto 4) = "0000") and (rx_sample_majority = '1') then
rx_badbit <= '1';
rx_state <= "00000000";
end if;
-- check stop bit framing and alert CPU if valid byte received
if (rx_state(7 downto 4) = "1001") then
if (rx_sample_majority = '1') then
data_out_buf <= rx_shift_reg(8 downto 1);
rx_out_ready <= '1';
rx_badbit <= '0';
else
rx_badbit <= '1';
end if;
-- if line is high we can skip waiting for the line to go idle which buys us a little more tolerance for clock drift.
if rx_sample1 = '1' then
rx_state <= "00000000";
end if;
end if;
end if;
end if;
end if;
end if;
end process;
-- -- transmitter -- --
--
-- just clock out the bits, damn it.
--
--serial_out <= tx_shift_reg(0); -- we always output the bottom bit of the shift register.
transmitter_busy <= tx_busy; -- or data_in_load;
transmitter: process(clk)
begin
if rising_edge(clk) then
tx_busy <= '1';
tx <= tx_shift_reg(0); -- we always output the bottom bit of the shift register.
if tx_bits_left = 0 then
-- idle
if data_in_load = '1' then
tx_shift_reg <= data_in & '0'; -- data bits, start bit
tx_bits_left <= to_unsigned(10, 4); -- total ten bits to transmit including stop bit
tx_counter <= (others => '0'); -- reset counter
else
if can_transmit = '0' then
tx_busy <= '1';
else
tx_busy <= '0';
end if;
end if;
else
-- busy
if (tx_counter = 0) and (tx_bits_left = 10) and (can_transmit = '0') then
-- do nothing, we're waiting for our peer to indicate that we can transmit
tx_counter <= (others => '0');
else
tx_counter <= tx_counter + 1;
if tx_counter = bit_duration then
-- shift out the next bit
tx_shift_reg <= '1' & tx_shift_reg(8 downto 1); -- stop bit and line idle state are both 1 so shift that in the top
tx_counter <= (others => '0'); -- reset counter
tx_bits_left <= tx_bits_left - 1;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 2b67fe686efcd9e605d443ae985715ee | 0.468913 | 4.220925 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt | kr_fuzman_system1.vhd | 1 | 2,177 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kr_fuzman_system1 is
port
( clock : in std_logic;
V_mux_sel,Z_mux_sel : in std_logic;
V_load,V_load1,V_load2 : in std_logic;
Z_load,Z_load1,Z_load2 : in std_logic;
Ut : in std_logic_vector(31 downto 0);
Vref : in std_logic_vector(31 downto 0);
Vtminusone : in std_logic_vector(31 downto 0);
Ztminusone : in std_logic_vector(31 downto 0);
Vt : out std_logic_vector(31 downto 0);
Zt : out std_logic_vector(31 downto 0)
);
end kr_fuzman_system1;
architecture struct of kr_fuzman_system1 is
component mux21 is
port ( I0, I1 : in std_logic_vector (31 downto 0);
s : in std_logic;
Y : out std_logic_vector (31 downto 0) );
end component;
component reg is
port ( clock,reset,load : in std_logic;
I : in std_logic_vector (31 downto 0);
Y : out std_logic_vector (31 downto 0) );
end component;
component kr_fuzman_system is
port
( clock : in std_logic;
Ut : in std_logic_vector(31 downto 0);
Vref : in std_logic_vector(31 downto 0);
Vtminusone : in std_logic_vector(31 downto 0);
Ztminusone : in std_logic_vector(31 downto 0);
Vt : out std_logic_vector(31 downto 0);
Zt : out std_logic_vector(31 downto 0)
);
end component;
signal Z1,Z2,Z3,Z4,Z5,Z6,Z7,Z8 : std_logic_vector(31 downto 0);
signal R : std_logic := '0';
begin
M1 : mux21 port map (I0 => Vtminusone, I1 => Vt, s => V_mux_sel, Y => Z1);
M2 : reg port map (clock => clock, reset => R, load => V_load, I => Z1, Y => Z2);
M3 : mux21 port map (I0 => Ztminusone, I1 => Zt, s => Z_mux_sel, Y => Z5);
M4 : reg port map (clock => clock, reset => R, load => Z_load, I => Z5, Y => Z6);
M5 : kr_fuzman_system port map (clock => clock, Ut => Ut, Vref => Vref, Vtminusone => Z2, Ztminusone => Z6, Vt => Z3, Zt => Z7);
M6 : reg port map (clock => clock, reset => R, load => V_load2, I => Z4, Y => Vt);
M7 : reg port map (clock => clock, reset => R, load => Z_load2, I => Z8, Y => Zt);
end struct;
| mit | 284eae24d5a587bbe0fdfb9b525dc020 | 0.581075 | 3.015235 | false | false | false | false |
kristapsdreija/IGLOO_NANO_FPGA_VGA_Generator_Libero_SoC | IGLOO_Updated_VGA/hdl/my.vhd | 1 | 3,927 | --------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: my.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- Proceduuras dazhaadu figuuru ziimeeshanai uz ekraana.
--
-- Targeted device: <Family::IGLOO> <Die::AGLN250V2Z> <Package::100 VQFP>
-- Author: <Name>
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--h_pulse : INTEGER := 96; --horiztonal sync pulse width in pixels 800 un 525
--h_bp : INTEGER := 48; --horiztonal back porch width in pixels
--h_pixels : INTEGER := 640; --horiztonal display width in pixels
--h_fp : INTEGER := 16; --horiztonal front porch width in pixels
--v_pulse : INTEGER := 2; --vertical sync pulse width in rows
--v_bp : INTEGER := 33; --vertical back porch width in rows
--v_pixels : INTEGER := 480; --vertical display width in rows
--v_fp : INTEGER := 10 --vertical front porch width in rows
--h_pulse : INTEGER := 112; --horiztonal sync pulse width in pixels 1688 un 1066
--h_bp : INTEGER := 248; --horiztonal back porch width in pixels
--h_pixels : INTEGER := 1280; --horiztonal display width in pixels
--h_fp : INTEGER := 48; --horiztonal front porch width in pixels
--v_pulse : INTEGER := 3; --vertical sync pulse width in rows
--v_bp : INTEGER := 38; --vertical back porch width in rows
--v_pixels : INTEGER := 1024; --vertical display width in rows
--v_fp : INTEGER := 1 --vertical front porch width in rows
--h_pulse : INTEGER := 128; --horiztonal sync pulse width in pixels 1056 un 628
--h_bp : INTEGER := 88; --horiztonal back porch width in pixels
--h_pixels : INTEGER := 800; --horiztonal display width in pixels
--h_fp : INTEGER := 40; --horiztonal front porch width in pixels
--v_pulse : INTEGER := 4; --vertical sync pulse width in rows
--v_bp : INTEGER := 23; --vertical back porch width in rows
--v_pixels : INTEGER := 600; --vertical display width in rows
--v_fp : INTEGER := 1 --vertical front porch width in rows
PACKAGE MY IS
---------------------------------------------------------
-- Procedura sanjem pashreizejas koordinatas ekrana un --
-- ari koordinatu, no kuras sakt zimet kvadratu. --
-- Procedura atgriez RGB signalu un DRAW indikatoru, --
-- kursh pasaka, vai tiek zimets vai ne. --
---------------------------------------------------------
PROCEDURE SQ(
SIGNAL Xcur : IN INTEGER RANGE 0 TO 1688;
SIGNAL Ycur : IN INTEGER RANGE 0 TO 1066;
SIGNAL Xpos : IN INTEGER RANGE 0 TO 1688;
SIGNAL Ypos : IN INTEGER RANGE 0 TO 1688;
SIGNAL RGB : OUT STD_LOGIC;
SIGNAL DRAW : OUT STD_LOGIC
);
END MY;
PACKAGE BODY MY IS
PROCEDURE SQ(
SIGNAL Xcur : IN INTEGER RANGE 0 TO 1688;
SIGNAL Ycur : IN INTEGER RANGE 0 TO 1066;
SIGNAL Xpos : IN INTEGER RANGE 0 TO 1688;
SIGNAL Ypos : IN INTEGER RANGE 0 TO 1688;
SIGNAL RGB : OUT STD_LOGIC;
SIGNAL DRAW : OUT STD_LOGIC
) IS
BEGIN
IF(Xcur>Xpos AND Xcur<(Xpos+100) AND Ycur>Ypos AND Ycur<(Ypos+100))THEN -- 100x100 pikselu kvadrats.
RGB<='1';
DRAW<='1';
ELSE
DRAW<='0';
END IF;
END SQ;
END MY; | gpl-2.0 | 83066c0b541fe77d5fa41ac85da74a19 | 0.512096 | 3.966667 | false | false | false | false |
bonfireprocessor/bonfire-soc | obsolete/tb_soc.vhd | 1 | 3,411 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:33:00 09/05/2016
-- Design Name:
-- Module Name: C:/daten/development/fpga/lxp32proj/lxp32_soc/tb_soc.vhd
-- Project Name: lxp32_01
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: toplevel
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_soc IS
END tb_soc;
ARCHITECTURE behavior OF tb_soc IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT toplevel
generic (
-- generics are set by the simulator only, when instaniating from a testbench
-- when Design is physically build than the defaults are used
RamFileName : string;-- only used when UseBRAMPrimitives is false
mode : string; -- only used when UseBRAMPrimitives is false
Swapbytes : boolean := true -- SWAP Bytes in RAM word in low byte first order to use data2mem
);
PORT(
sysclk_32m : IN std_logic;
I_RESET : IN std_logic;
leds : OUT std_logic_vector(3 downto 0);
uart0_txd : OUT std_logic;
uart0_rxd : IN std_logic;
led1 : OUT std_logic
);
END COMPONENT;
--Inputs
signal sysclk_32m : std_logic := '0';
signal I_RESET : std_logic := '0';
signal uart0_rxd : std_logic := '0';
--Outputs
signal leds : std_logic_vector(3 downto 0);
signal uart0_txd : std_logic;
signal led1 : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clock_period : time := 31.25ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: toplevel
generic map (
--RamFileName => "../../lxp32soc/riscv/software/cpptest/ledsim.hex",
--RamFileName => "../../lxp32soc/riscv/software/cpptest/counter.hex",
--RamFileName => "../../lxp32-cpu/riscv_test/branch.hex",
RamFileName => "../../lxp32-cpu/riscv_test/trap01.hex",
--RamFileName => "../../lxp32-cpu/riscv_test/mult.hex",
mode=>"H",
Swapbytes=>false
)
PORT MAP (
sysclk_32m => sysclk_32m,
I_RESET => I_RESET,
leds => leds,
uart0_txd => uart0_txd,
uart0_rxd => uart0_rxd,
led1 => led1
);
-- Clock process definitions
clock_process :process
begin
sysclk_32m <= '0';
wait for clock_period/2;
sysclk_32m <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | 08319b03adaff427d8f0f6b00ac4c2c3 | 0.59572 | 3.938799 | false | true | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/ip/feedforward_ap_dcmp_0_no_dsp_64.vhd | 2 | 12,866 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_dcmp_0_no_dsp_64 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END feedforward_ap_dcmp_0_no_dsp_64;
ARCHITECTURE feedforward_ap_dcmp_0_no_dsp_64_arch OF feedforward_ap_dcmp_0_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_dcmp_0_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_dcmp_0_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_dcmp_0_no_dsp_64_arch : ARCHITECTURE IS "feedforward_ap_dcmp_0_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_dcmp_0_no_dsp_64_arch: ARCHITECTURE IS "feedforward_ap_dcmp_0_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=1,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=1,C_RESULT_FRACTION_WIDTH=0,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=1,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=8,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 1,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 1,
C_RESULT_FRACTION_WIDTH => 0,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 1,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 8,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => s_axis_operation_tvalid,
s_axis_operation_tdata => s_axis_operation_tdata,
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_dcmp_0_no_dsp_64_arch;
| gpl-3.0 | 0ca00ee26fc278fa75e953aaba602b95 | 0.652884 | 3.017355 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_AXILiteS_s_axi.vhd | 3 | 12,421 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity feedforward_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
P_mode :out STD_LOGIC_VECTOR(31 downto 0)
);
end entity feedforward_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of P_mode
-- bit 31~0 - P_mode[31:0] (Read/Write)
-- 0x14 : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of feedforward_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_P_MODE_DATA_0 : INTEGER := 16#10#;
constant ADDR_P_MODE_CTRL : INTEGER := 16#14#;
constant ADDR_BITS : INTEGER := 5;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_P_mode : UNSIGNED(31 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_P_MODE_DATA_0 =>
rdata_data <= RESIZE(int_P_mode(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
P_mode <= STD_LOGIC_VECTOR(int_P_mode);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_MODE_DATA_0) then
int_P_mode(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_mode(31 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| gpl-3.0 | 4640daa5a5b66e26cb6bc347a8473aac | 0.45254 | 3.80662 | false | false | false | false |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_dexp_16_full_dsp_64/synth/ANN_ap_dexp_16_full_dsp_64.vhd | 1 | 12,412 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_dexp_16_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END ANN_ap_dexp_16_full_dsp_64;
ARCHITECTURE ANN_ap_dexp_16_full_dsp_64_arch OF ANN_ap_dexp_16_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_dexp_16_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_dexp_16_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_dexp_16_full_dsp_64_arch : ARCHITECTURE IS "ANN_ap_dexp_16_full_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_dexp_16_full_dsp_64_arch: ARCHITECTURE IS "ANN_ap_dexp_16_full_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=1,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=16,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 1,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 16,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_dexp_16_full_dsp_64_arch;
| gpl-3.0 | a52208620532747d06b686789823dfdd | 0.648244 | 3.012621 | false | false | false | false |
airlog/vhdl-rc4 | src/rc4_crypto.vhd | 1 | 4,331 | --
-- rc4_crypto
-- urz¹dzenie szyfruj¹co/deszyfruj¹ce strumieñ bajtów przy pomocy RC4
--
-- Urz¹dzenie nie posiada swojej pamiêci na aktualny stan permutacji RC4, posiada natomiast
-- zestaw wejæ i wyjæ umo¿liwiaj¹cych kontakt z zewnêtrzn¹ pamiêci¹.
--
-- Urz¹dzenie rozpoczyna dzia³anie wtedy i tylko wtedy gdy wartoæ sygna³u go = 1. Powoduje to zaszyfrowanie
-- dok³adnie jednego bajtu z wejcia. Bajt na wejciu powinien byæ trzymany tak d³ugo a¿ sygna³ rdy = 1. Oznacza
-- to, ¿e bajt na wyjciu jest poprawnie zaszyfrowany/odszyfrowany.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.ALL;
entity rc4_crypto is
generic (
width: integer := 8
);
port (
enc_input: in std_logic_vector((width - 1) downto 0); -- bajt do zaszyfrowania/deszyfrowania
perm_input: in std_logic_vector((width - 1) downto 0); -- wejscie wartosci z pamieci
go: in std_logic; -- dzialac/nie dzialac
clk: in std_logic;
enc_output: out std_logic_vector((width - 1) downto 0); -- zaszyfrowany/deszyfrowany bajt
perm_ctrl: out std_logic; -- zapis/odczyt z pamieci
perm_index: out std_logic_vector((width - 1) downto 0); -- indeks bajtu w pamieci
perm_output: out std_logic_vector((width - 1) downto 0);-- perm_ctrl=1 => zapisz te wartosc
rdy: out std_logic -- wartosc na enc_output jest poprawna
);
end rc4_crypto;
architecture Behavioral of rc4_crypto is
type rc4_crypto_state is (
WHILE_GO_TEST, WHILE_GO_RET,
MAIN_BODY, MAIN_BODY_OUTPUT,
WHILE_0_RET
);
subtype rc4int is integer range 0 to 255;
shared variable cstate : rc4_crypto_state := WHILE_GO_TEST;
shared variable i, j, tmp, si, sj, sm : rc4int := 0;
begin
process (clk)
variable clk_ctr : integer := 0;
begin
if rising_edge(clk) then
rdy <= '0';
perm_ctrl <= '0';
case cstate is
when WHILE_GO_TEST =>
if go = '1' then
cstate := MAIN_BODY;
end if;
when WHILE_GO_RET =>
cstate := WHILE_GO_TEST;
when MAIN_BODY =>
case clk_ctr is
when 0 =>
clk_ctr := 0;
i := i + 1;
perm_index <= conv_std_logic_vector(i, width);
clk_ctr := clk_ctr + 1;
cstate := MAIN_BODY;
-- utrzymaj stan sygna³u perm_index ¿eby otrzymaæ poprawn¹ wartoæ
when 1 =>
clk_ctr := clk_ctr + 1;
cstate := MAIN_BODY;
when 2 =>
si := conv_integer(unsigned(perm_input));
clk_ctr := clk_ctr + 1;
cstate := MAIN_BODY;
when 3 =>
j := j + si;
perm_index <= conv_std_logic_vector(j, width);
clk_ctr := clk_ctr + 1;
cstate := MAIN_BODY;
-- utrzymaj stan sygna³u perm_index ¿eby otrzymaæ poprawn¹ wartoæ
when 4 =>
clk_ctr := clk_ctr + 1;
cstate := MAIN_BODY;
when 5 =>
sj := conv_integer(unsigned(perm_input));
clk_ctr := clk_ctr + 1;
cstate := MAIN_BODY;
when 6 =>
perm_ctrl <= '0';
perm_index <= conv_std_logic_vector(i, width);
perm_output <= conv_std_logic_vector(sj, width);
perm_ctrl <= '1';
clk_ctr := clk_ctr + 1;
cstate := MAIN_BODY;
when 7 =>
perm_ctrl <= '0';
perm_index <= conv_std_logic_vector(j, width);
perm_output <= conv_std_logic_vector(si, width);
perm_ctrl <= '1';
clk_ctr := clk_ctr + 1;
cstate := MAIN_BODY;
when 8 =>
perm_ctrl <= '0';
tmp := (si + sj) mod 256;
perm_index <= conv_std_logic_vector(tmp, width);
clk_ctr := clk_ctr + 1;
cstate := MAIN_BODY;
-- utrzymaj stan sygna³u perm_index ¿eby otrzymaæ poprawn¹ wartoæ
when 9 =>
clk_ctr := clk_ctr + 1;
cstate := MAIN_BODY;
when 10 =>
sm := conv_integer(unsigned(perm_input));
clk_ctr := 0;
cstate := MAIN_BODY_OUTPUT;
when others =>
end case;
when MAIN_BODY_OUTPUT =>
enc_output <= enc_input xor conv_std_logic_vector(sm, width);
rdy <= '1';
cstate := WHILE_0_RET;
when WHILE_0_RET =>
cstate := WHILE_GO_TEST;
end case;
end if;
end process;
end Behavioral;
| mit | 2ffd58f2eeac8825b494b927eb615c29 | 0.56592 | 2.930311 | false | false | false | false |
kristapsdreija/IGLOO_NANO_FPGA_VGA_Generator_Libero_SoC | IGLOO_Updated_VGA/hdl/hw_image_generator.vhd | 1 | 3,995 | --------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY hw_image_generator IS
GENERIC(
pixels_x_start : INTEGER := 280; -- Kvadratu koordinatas piecu 80x80 pikselu lielu kvadratu zimeshanai
pixels_y_start : INTEGER := 200;
pixels_x_end : INTEGER := 360;
pixels_y_end : INTEGER := 280;
pixels_x_start2 : INTEGER := 360;
pixels_y_start2 : INTEGER := 120;
pixels_x_end2 : INTEGER := 440;
pixels_y_end2 : INTEGER := 200;
pixels_x_start3 : INTEGER := 360;
pixels_y_start3 : INTEGER := 280;
pixels_x_end3 : INTEGER := 440;
pixels_y_end3 : INTEGER := 360;
pixels_x_start4 : INTEGER := 200;
pixels_y_start4 : INTEGER := 120;
pixels_x_end4 : INTEGER := 280;
pixels_y_end4 : INTEGER := 200;
pixels_x_start5 : INTEGER := 200;
pixels_y_start5 : INTEGER := 280;
pixels_x_end5 : INTEGER := 280;
pixels_y_end5 : INTEGER := 360
);
PORT(
disp_ena : IN STD_LOGIC; -- Ja disp_ena = 1, tad radit bildi. Ja 0, tad tukshuma ("blanking") periods.
row : IN STD_LOGIC_VECTOR(0 to 9); -- Rindas piksela koordinatas
column : IN STD_LOGIC_VECTOR(0 to 9); -- Kolonnas piksela koordinatas
BUTTON_1 : IN STD_LOGIC; -- pirma poga
red : OUT STD_LOGIC := '0'; -- Sarkana krasa
green : OUT STD_LOGIC := '0'; -- Zala krasa
blue : OUT STD_LOGIC := '0' -- Zila krasa
);
END hw_image_generator;
ARCHITECTURE behavior OF hw_image_generator IS
BEGIN
PROCESS(disp_ena, row, column, BUTTON_1)
VARIABLE column_int : INTEGER := to_integer(unsigned(column)); -- Tiek salidzinats ar INTEGER
VARIABLE row_int : INTEGER := to_integer(unsigned(row)); -- vertibu, tapec japarveido uz UNSIGNED INTEGER
VARIABLE crossValX : INTEGER := 320; -- Zilaa krusta rindas un kolonnas koordinatas.
VARIABLE crossValY : INTEGER := 240;
BEGIN
IF(disp_ena = '1') THEN -- Izvades laiks
IF(row_int = crossValX AND column_int = crossValY) THEN -- Izvadit sarkanu punktu pasha ekrana vidu
red <= '1';
green <= '0';
blue <= '0';
ELSIF(row_int = crossValX) THEN -- Izvadit zilu punktu katra x=320 piksela koordinata
red <= '0';
green <= '0';
blue <= '1';
ELSIF(column_int = crossValY) THEN -- Izvadit zilu punktu katra y = 240 piksela koordinata
red <= '0';
green <= '0';
blue <= '1';
ELSIF(row_int > pixels_x_start AND row_int < pixels_x_end AND column_int > pixels_y_start AND column_int < pixels_y_end) THEN
red <= '1'; -- Sarkans kvadrats
green <= '1';
blue <= '0';
ELSIF(row_int > pixels_x_start2 AND row_int < pixels_x_end2 AND column_int > pixels_y_start2 AND column_int < pixels_y_end2) THEN
red <= '1'; -- Violets kvadrats
green <= '0';
blue <= '1';
ELSIF(row_int > pixels_x_start3 AND row_int < pixels_x_end3 AND column_int > pixels_y_start3 AND column_int < pixels_y_end3) THEN
red <= '0'; -- Gaishi zils kvadrats
green <= '1';
blue <= '1';
ELSIF(row_int > pixels_x_start4 AND row_int < pixels_x_end4 AND column_int > pixels_y_start4 AND column_int < pixels_y_end4) THEN
red <= '0'; -- Zals kvadrats
green <= '1';
blue <= '0';
ELSIF(row_int > pixels_x_start5 AND row_int < pixels_x_end5 AND column_int > pixels_y_start5 AND column_int < pixels_y_end5) THEN
red <= '1'; -- Sarkans kvadrats
green <= '0';
blue <= '0';
ELSE
IF(BUTTON_1 = '1') THEN -- Ja sledzis stavolki "1", tad aiz kvadratiem balts fons.
red <= '1';
green <= '1';
blue <= '1';
ELSE
red <= '0'; -- Ja sledzis stavokli "0", tad aiz kvadratiem melns fons.
green <= '0';
blue <= '0';
END IF;
END IF;
ELSE
red <= '0'; -- "Tukshuma periods"
green <= '0';
blue <= '0';
END IF;
END PROCESS;
END behavior; | gpl-2.0 | 075eeffeef30fe0ca15f870144f89b21 | 0.579725 | 2.693864 | false | false | false | false |
hoglet67/AtomVGAWing | src/DCM_B.vhd | 1 | 2,523 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.4
-- \ \ Application : xaw2vhdl
-- / / Filename : DCM_B.vhd
-- /___/ /\ Timestamp : 03/01/2013 20:52:36
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-intstyle /home/dmb/papilio/projects/VGATest/ipcore_dir/DCM_B.xaw -st DCM_B.vhd
--Design Name: DCM_B
--Device: xc3s500e-5vq100
--
-- Module DCM_B
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 3.61 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity DCM_B is
port ( CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end DCM_B;
architecture BEHAVIORAL of DCM_B is
signal CLKFX_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 32,
CLKFX_MULTIPLY => 15,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>GND_BIT,
CLKIN=>CLKIN_IN,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>open,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| gpl-3.0 | ed6385a36684653c1c8d79d745f96bf5 | 0.467697 | 3.754464 | false | false | false | false |
bonfireprocessor/bonfire-soc | obsolete/MainMemorySpartan6.vhd | 1 | 4,916 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:54:55 10/16/2016
-- Design Name:
-- Module Name: MainMemorySpartan6 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_arith.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.util.all;
entity MainMemorySpartan6 is
generic (
NUMBANKS: natural:=1 -- number of RAM16B Banks, each Bank has 4*2K*8 BRAMS
);
Port ( DBOut : out STD_LOGIC_VECTOR (31 downto 0);
DBIn : in STD_LOGIC_VECTOR (31 downto 0);
AdrBus : in STD_LOGIC_VECTOR (10+log2(NUMBANKS) downto 0);
ENA : in STD_LOGIC;
WREN : in STD_LOGIC_VECTOR (3 downto 0);
CLK : in STD_LOGIC;
-- Second Port ( read only)
CLKB : in STD_LOGIC;
ENB : in STD_LOGIC;
AdrBusB : in STD_LOGIC_VECTOR (10+log2(NUMBANKS) downto 0);
DBOutB : out STD_LOGIC_VECTOR (31 downto 0)
);
end MainMemorySpartan6;
architecture Behavioral of MainMemorySpartan6 is
subtype word is STD_LOGIC_VECTOR (31 downto 0);
type tBusMux is array (0 to NUMBANKS-1) of STD_LOGIC_VECTOR (31 downto 0);
signal ena_v,enb_v : std_logic_vector (NUMBANKS-1 downto 0);
signal upper_adr_a,upper_adr_b : std_logic_vector (log2(NUMBANKS)-1 downto 0);
signal BusMuxA,BusMuxB : tBusMux;
COMPONENT ram2048x8
PORT(
DInA : IN std_logic_vector(7 downto 0);
AdrA : IN std_logic_vector(10 downto 0);
ENA : IN std_logic;
WRENA : IN std_logic;
CLKA : IN std_logic;
AdrB : IN std_logic_vector(10 downto 0);
ENB : IN std_logic;
CLKB : IN std_logic;
DOutA : OUT std_logic_vector(7 downto 0);
DoutB : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
begin
upper_adr_a <= AdrBus(AdrBus'length-1 downto 11);
upper_adr_b <= AdrBusB(AdrBusB'length-1 downto 11);
genmem: for i in 0 to NUMBANKS-1 generate
begin
Inst_ram2048x8_0: ram2048x8 PORT MAP(
DOutA => BusMuxA(i)(7 downto 0),
DInA => DBIn(7 downto 0),
AdrA => AdrBus(10 downto 0),
ENA => ena_v(i),
WRENA => wren(0),
CLKA => clk,
DoutB => BusMuxB(i)(7 downto 0),
AdrB => AdrBusB(10 downto 0),
ENB => enb_v(i),
CLKB => clkb
);
Inst_ram2048x8_1: ram2048x8 PORT MAP(
DOutA => BusMuxA(i)(15 downto 8),
DInA => DBIn(15 downto 8),
AdrA => AdrBus(10 downto 0),
ENA => ena_v(i),
WRENA => wren(1),
CLKA => clk,
DoutB => BusMuxB(i)(15 downto 8),
AdrB => AdrBusB(10 downto 0),
ENB => enb_v(i),
CLKB => clkb
);
Inst_ram2048x8_2: ram2048x8 PORT MAP(
DOutA => BusMuxA(i)(23 downto 16),
DInA => DBIn(23 downto 16),
AdrA => AdrBus(10 downto 0),
ENA => ena_v(i),
WRENA => wren(2),
CLKA => clk,
DoutB => BusMuxB(i)(23 downto 16),
AdrB => AdrBusB(10 downto 0),
ENB => enb_v(i),
CLKB => clkb
);
Inst_ram2048x8_3: ram2048x8 PORT MAP(
DOutA => BusMuxA(i)(31 downto 24),
DInA => DBIn(31 downto 24),
AdrA => AdrBus(10 downto 0),
ENA => ena_v(i),
WRENA => wren(3),
CLKA => clk,
DoutB => BusMuxB(i)(31 downto 24),
AdrB => AdrBusB(10 downto 0),
ENB => enb_v(i),
CLKB => clkb
);
end generate;
MuxA: process(upper_adr_a,ena,BusMuxA)
variable env: std_logic_vector (NUMBANKS-1 downto 0);
variable mux: std_logic_vector(31 downto 0);
begin
mux:=(others=>'0');
for i in 0 to NUMBANKS-1 loop
if upper_adr_a=CONV_STD_LOGIC_VECTOR(i,upper_adr_a'length) and ena='1' then
env(i):='1';
else
env(i):='0';
end if;
for k in DBOut'range loop
mux(k) := mux(k) or (BusMuxA(i)(k) and env(i));
end loop;
end loop;
ena_v<=env;
DBOut<=mux;
end process;
MuxB: process(upper_adr_b,enb,BusMuxB)
variable env: std_logic_vector (NUMBANKS-1 downto 0);
variable mux: std_logic_vector(31 downto 0);
begin
mux:=(others=>'0');
for i in 0 to NUMBANKS-1 loop
if upper_adr_b=CONV_STD_LOGIC_VECTOR(i,upper_adr_b'length) and enb='1' then
env(i):='1';
else
env(i):='0';
end if;
for k in DBOut'range loop
mux(k) := mux(k) or (BusMuxB(i)(k) and env(i));
end loop;
end loop;
enb_v<=env;
DBOutB<=mux;
end process;
end Behavioral;
| gpl-3.0 | 42edfd7e852dcd763112ad03b16ecbbe | 0.55716 | 3.167526 | false | false | false | false |
minijackson/school-vhdl | E2/TP2/states.vhd | 1 | 845 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity states is
port (
n : in std_logic_vector(1 downto 0);
-- _A
-- F|_|B
-- E|_|C
-- D
a : out std_logic;
b : out std_logic;
c : out std_logic;
d : out std_logic;
e : out std_logic;
f : out std_logic;
g : out std_logic;
);
end states
architecture statesArch of states is
begin
-- State 0: State 1: State 2: State 3:
-- _
-- _ |
-- _ | | |
a <= '0' when unsigned(n) = 3 else '1';
b <= '1';
c <= '0' when unsigned(n) = 2 else '1';
d <= '0' when unsigned(n) = 1 else '1';
e <= '0' when unsigned(n) = 2 or unsigned(n) = 3 else '1';
f <= '0' when unsigned(n) = 3 else '1';
g <= '0' when unsigned(n) = 2 else '1';
end statesArch;
| mit | 6c8d68611f477cdfc1acea537faaa783 | 0.484024 | 2.632399 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/hdl/design_SWandHW_standalone.vhd | 1 | 357,555 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
--Date : Thu Sep 01 16:06:02 2016
--Host : DESKTOP-I329812 running 64-bit major release (build 9200)
--Command : generate_target design_SWandHW_standalone.bd
--Design : design_SWandHW_standalone
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1MVOGV6 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_1MVOGV6;
architecture STRUCTURE of m00_couplers_imp_1MVOGV6 is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_3Z6JOL is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_3Z6JOL;
architecture STRUCTURE of m00_couplers_imp_3Z6JOL is
component design_SWandHW_standalone_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_SWandHW_standalone_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_WID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_WLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_m00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_m00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(2 downto 0) <= auto_pc_to_m00_couplers_ARID(2 downto 0);
M_AXI_arlen(3 downto 0) <= auto_pc_to_m00_couplers_ARLEN(3 downto 0);
M_AXI_arlock(1 downto 0) <= auto_pc_to_m00_couplers_ARLOCK(1 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_m00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_m00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_pc_to_m00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_pc_to_m00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(2 downto 0) <= auto_pc_to_m00_couplers_AWID(2 downto 0);
M_AXI_awlen(3 downto 0) <= auto_pc_to_m00_couplers_AWLEN(3 downto 0);
M_AXI_awlock(1 downto 0) <= auto_pc_to_m00_couplers_AWLOCK(1 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_pc_to_m00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_pc_to_m00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wid(2 downto 0) <= auto_pc_to_m00_couplers_WID(2 downto 0);
M_AXI_wlast <= auto_pc_to_m00_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= auto_pc_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(2 downto 0) <= m00_couplers_to_auto_pc_BID(2 downto 0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(2 downto 0) <= m00_couplers_to_auto_pc_RID(2 downto 0);
S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m00_couplers_to_auto_pc_WREADY;
auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m00_couplers_BID(5 downto 0) <= M_AXI_bid(5 downto 0);
auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_m00_couplers_RID(5 downto 0) <= M_AXI_rid(5 downto 0);
auto_pc_to_m00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_auto_pc_ARID(2 downto 0) <= S_AXI_arid(2 downto 0);
m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_auto_pc_AWID(2 downto 0) <= S_AXI_awid(2 downto 0);
m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_SWandHW_standalone_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(2 downto 0) => auto_pc_to_m00_couplers_ARID(2 downto 0),
m_axi_arlen(3 downto 0) => auto_pc_to_m00_couplers_ARLEN(3 downto 0),
m_axi_arlock(1 downto 0) => auto_pc_to_m00_couplers_ARLOCK(1 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_m00_couplers_ARREADY,
m_axi_arsize(2 downto 0) => auto_pc_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_pc_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_pc_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(2 downto 0) => auto_pc_to_m00_couplers_AWID(2 downto 0),
m_axi_awlen(3 downto 0) => auto_pc_to_m00_couplers_AWLEN(3 downto 0),
m_axi_awlock(1 downto 0) => auto_pc_to_m00_couplers_AWLOCK(1 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_pc_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_pc_to_m00_couplers_AWREADY,
m_axi_awsize(2 downto 0) => auto_pc_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID,
m_axi_bid(2 downto 0) => auto_pc_to_m00_couplers_BID(2 downto 0),
m_axi_bready => auto_pc_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_m00_couplers_RDATA(31 downto 0),
m_axi_rid(2 downto 0) => auto_pc_to_m00_couplers_RID(2 downto 0),
m_axi_rlast => auto_pc_to_m00_couplers_RLAST,
m_axi_rready => auto_pc_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_m00_couplers_WDATA(31 downto 0),
m_axi_wid(2 downto 0) => auto_pc_to_m00_couplers_WID(2 downto 0),
m_axi_wlast => auto_pc_to_m00_couplers_WLAST,
m_axi_wready => auto_pc_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_m00_couplers_WVALID,
s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(2 downto 0) => m00_couplers_to_auto_pc_ARID(2 downto 0),
s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(2 downto 0) => m00_couplers_to_auto_pc_AWID(2 downto 0),
s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m00_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID,
s_axi_bid(2 downto 0) => m00_couplers_to_auto_pc_BID(2 downto 0),
s_axi_bready => m00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => m00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(2 downto 0) => m00_couplers_to_auto_pc_RID(2 downto 0),
s_axi_rlast => m00_couplers_to_auto_pc_RLAST,
s_axi_rready => m00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => m00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wlast => m00_couplers_to_auto_pc_WLAST,
s_axi_wready => m00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => m00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => m00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_7OD9KA is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_7OD9KA;
architecture STRUCTURE of m01_couplers_imp_7OD9KA is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_1432F1V is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_1432F1V;
architecture STRUCTURE of m02_couplers_imp_1432F1V is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_QLWQRF is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_QLWQRF;
architecture STRUCTURE of m03_couplers_imp_QLWQRF is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_PPSTKW is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wvalid : in STD_LOGIC
);
end m04_couplers_imp_PPSTKW;
architecture STRUCTURE of m04_couplers_imp_PPSTKW is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m05_couplers_imp_14U9M2W is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wvalid : in STD_LOGIC
);
end m05_couplers_imp_14U9M2W;
architecture STRUCTURE of m05_couplers_imp_14U9M2W is
signal m05_couplers_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_ARREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_ARVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_AWREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_BVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_RREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_RVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_WREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m05_couplers_to_m05_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m05_couplers_to_m05_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m05_couplers_to_m05_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m05_couplers_to_m05_couplers_AWVALID;
M_AXI_bready <= m05_couplers_to_m05_couplers_BREADY;
M_AXI_rready <= m05_couplers_to_m05_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m05_couplers_to_m05_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= m05_couplers_to_m05_couplers_WVALID;
S_AXI_arready <= m05_couplers_to_m05_couplers_ARREADY;
S_AXI_awready <= m05_couplers_to_m05_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m05_couplers_to_m05_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m05_couplers_to_m05_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m05_couplers_to_m05_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m05_couplers_to_m05_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m05_couplers_to_m05_couplers_RVALID;
S_AXI_wready <= m05_couplers_to_m05_couplers_WREADY;
m05_couplers_to_m05_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m05_couplers_to_m05_couplers_ARREADY <= M_AXI_arready;
m05_couplers_to_m05_couplers_ARVALID <= S_AXI_arvalid;
m05_couplers_to_m05_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m05_couplers_to_m05_couplers_AWREADY <= M_AXI_awready;
m05_couplers_to_m05_couplers_AWVALID <= S_AXI_awvalid;
m05_couplers_to_m05_couplers_BREADY <= S_AXI_bready;
m05_couplers_to_m05_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m05_couplers_to_m05_couplers_BVALID <= M_AXI_bvalid;
m05_couplers_to_m05_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m05_couplers_to_m05_couplers_RREADY <= S_AXI_rready;
m05_couplers_to_m05_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m05_couplers_to_m05_couplers_RVALID <= M_AXI_rvalid;
m05_couplers_to_m05_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m05_couplers_to_m05_couplers_WREADY <= M_AXI_wready;
m05_couplers_to_m05_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m06_couplers_imp_6WKA35 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wvalid : in STD_LOGIC
);
end m06_couplers_imp_6WKA35;
architecture STRUCTURE of m06_couplers_imp_6WKA35 is
signal m06_couplers_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_ARREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_ARVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_AWREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_BVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_RREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_RVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_WREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m06_couplers_to_m06_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m06_couplers_to_m06_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m06_couplers_to_m06_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m06_couplers_to_m06_couplers_AWVALID;
M_AXI_bready <= m06_couplers_to_m06_couplers_BREADY;
M_AXI_rready <= m06_couplers_to_m06_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m06_couplers_to_m06_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= m06_couplers_to_m06_couplers_WVALID;
S_AXI_arready <= m06_couplers_to_m06_couplers_ARREADY;
S_AXI_awready <= m06_couplers_to_m06_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m06_couplers_to_m06_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m06_couplers_to_m06_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m06_couplers_to_m06_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m06_couplers_to_m06_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m06_couplers_to_m06_couplers_RVALID;
S_AXI_wready <= m06_couplers_to_m06_couplers_WREADY;
m06_couplers_to_m06_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m06_couplers_to_m06_couplers_ARREADY <= M_AXI_arready;
m06_couplers_to_m06_couplers_ARVALID <= S_AXI_arvalid;
m06_couplers_to_m06_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m06_couplers_to_m06_couplers_AWREADY <= M_AXI_awready;
m06_couplers_to_m06_couplers_AWVALID <= S_AXI_awvalid;
m06_couplers_to_m06_couplers_BREADY <= S_AXI_bready;
m06_couplers_to_m06_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m06_couplers_to_m06_couplers_BVALID <= M_AXI_bvalid;
m06_couplers_to_m06_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m06_couplers_to_m06_couplers_RREADY <= S_AXI_rready;
m06_couplers_to_m06_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m06_couplers_to_m06_couplers_RVALID <= M_AXI_rvalid;
m06_couplers_to_m06_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m06_couplers_to_m06_couplers_WREADY <= M_AXI_wready;
m06_couplers_to_m06_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_14GRHI is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end s00_couplers_imp_14GRHI;
architecture STRUCTURE of s00_couplers_imp_14GRHI is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= s00_couplers_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= s00_couplers_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= s00_couplers_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= s00_couplers_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rlast(0) <= s00_couplers_to_s00_couplers_RLAST(0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_s00_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_s00_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
s00_couplers_to_s00_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RLAST(0) <= M_AXI_rlast(0);
s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1PPRTY9 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1PPRTY9;
architecture STRUCTURE of s00_couplers_imp_1PPRTY9 is
component design_SWandHW_standalone_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_SWandHW_standalone_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_SWandHW_standalone_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_1KHG2CU is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s01_couplers_imp_1KHG2CU;
architecture STRUCTURE of s01_couplers_imp_1KHG2CU is
signal s01_couplers_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_BREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_BVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_WLAST : STD_LOGIC;
signal s01_couplers_to_s01_couplers_WREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_awaddr(31 downto 0) <= s01_couplers_to_s01_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= s01_couplers_to_s01_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= s01_couplers_to_s01_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= s01_couplers_to_s01_couplers_AWLEN(7 downto 0);
M_AXI_awprot(2 downto 0) <= s01_couplers_to_s01_couplers_AWPROT(2 downto 0);
M_AXI_awsize(2 downto 0) <= s01_couplers_to_s01_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= s01_couplers_to_s01_couplers_AWVALID;
M_AXI_bready <= s01_couplers_to_s01_couplers_BREADY;
M_AXI_wdata(31 downto 0) <= s01_couplers_to_s01_couplers_WDATA(31 downto 0);
M_AXI_wlast <= s01_couplers_to_s01_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= s01_couplers_to_s01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= s01_couplers_to_s01_couplers_WVALID;
S_AXI_awready <= s01_couplers_to_s01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= s01_couplers_to_s01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= s01_couplers_to_s01_couplers_BVALID;
S_AXI_wready <= s01_couplers_to_s01_couplers_WREADY;
s01_couplers_to_s01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s01_couplers_to_s01_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s01_couplers_to_s01_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s01_couplers_to_s01_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s01_couplers_to_s01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s01_couplers_to_s01_couplers_AWREADY <= M_AXI_awready;
s01_couplers_to_s01_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s01_couplers_to_s01_couplers_AWVALID <= S_AXI_awvalid;
s01_couplers_to_s01_couplers_BREADY <= S_AXI_bready;
s01_couplers_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s01_couplers_to_s01_couplers_BVALID <= M_AXI_bvalid;
s01_couplers_to_s01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s01_couplers_to_s01_couplers_WLAST <= S_AXI_wlast;
s01_couplers_to_s01_couplers_WREADY <= M_AXI_wready;
s01_couplers_to_s01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s01_couplers_to_s01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s02_couplers_imp_HTS99Z is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s02_couplers_imp_HTS99Z;
architecture STRUCTURE of s02_couplers_imp_HTS99Z is
signal s02_couplers_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_s02_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_s02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_s02_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_s02_couplers_ARREADY : STD_LOGIC;
signal s02_couplers_to_s02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_s02_couplers_ARVALID : STD_LOGIC;
signal s02_couplers_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_s02_couplers_RLAST : STD_LOGIC;
signal s02_couplers_to_s02_couplers_RREADY : STD_LOGIC;
signal s02_couplers_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_s02_couplers_RVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= s02_couplers_to_s02_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= s02_couplers_to_s02_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= s02_couplers_to_s02_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= s02_couplers_to_s02_couplers_ARLEN(7 downto 0);
M_AXI_arprot(2 downto 0) <= s02_couplers_to_s02_couplers_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= s02_couplers_to_s02_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= s02_couplers_to_s02_couplers_ARVALID;
M_AXI_rready <= s02_couplers_to_s02_couplers_RREADY;
S_AXI_arready <= s02_couplers_to_s02_couplers_ARREADY;
S_AXI_rdata(31 downto 0) <= s02_couplers_to_s02_couplers_RDATA(31 downto 0);
S_AXI_rlast <= s02_couplers_to_s02_couplers_RLAST;
S_AXI_rresp(1 downto 0) <= s02_couplers_to_s02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= s02_couplers_to_s02_couplers_RVALID;
s02_couplers_to_s02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s02_couplers_to_s02_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s02_couplers_to_s02_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s02_couplers_to_s02_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s02_couplers_to_s02_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s02_couplers_to_s02_couplers_ARREADY <= M_AXI_arready;
s02_couplers_to_s02_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s02_couplers_to_s02_couplers_ARVALID <= S_AXI_arvalid;
s02_couplers_to_s02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s02_couplers_to_s02_couplers_RLAST <= M_AXI_rlast;
s02_couplers_to_s02_couplers_RREADY <= S_AXI_rready;
s02_couplers_to_s02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s02_couplers_to_s02_couplers_RVALID <= M_AXI_rvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s03_couplers_imp_13X1ZY7 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s03_couplers_imp_13X1ZY7;
architecture STRUCTURE of s03_couplers_imp_13X1ZY7 is
signal s03_couplers_to_s03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s03_couplers_to_s03_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s03_couplers_to_s03_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s03_couplers_to_s03_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s03_couplers_to_s03_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s03_couplers_to_s03_couplers_AWREADY : STD_LOGIC;
signal s03_couplers_to_s03_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s03_couplers_to_s03_couplers_AWVALID : STD_LOGIC;
signal s03_couplers_to_s03_couplers_BREADY : STD_LOGIC;
signal s03_couplers_to_s03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s03_couplers_to_s03_couplers_BVALID : STD_LOGIC;
signal s03_couplers_to_s03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s03_couplers_to_s03_couplers_WLAST : STD_LOGIC;
signal s03_couplers_to_s03_couplers_WREADY : STD_LOGIC;
signal s03_couplers_to_s03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s03_couplers_to_s03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_awaddr(31 downto 0) <= s03_couplers_to_s03_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= s03_couplers_to_s03_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= s03_couplers_to_s03_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= s03_couplers_to_s03_couplers_AWLEN(7 downto 0);
M_AXI_awprot(2 downto 0) <= s03_couplers_to_s03_couplers_AWPROT(2 downto 0);
M_AXI_awsize(2 downto 0) <= s03_couplers_to_s03_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= s03_couplers_to_s03_couplers_AWVALID;
M_AXI_bready <= s03_couplers_to_s03_couplers_BREADY;
M_AXI_wdata(31 downto 0) <= s03_couplers_to_s03_couplers_WDATA(31 downto 0);
M_AXI_wlast <= s03_couplers_to_s03_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= s03_couplers_to_s03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= s03_couplers_to_s03_couplers_WVALID;
S_AXI_awready <= s03_couplers_to_s03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= s03_couplers_to_s03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= s03_couplers_to_s03_couplers_BVALID;
S_AXI_wready <= s03_couplers_to_s03_couplers_WREADY;
s03_couplers_to_s03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s03_couplers_to_s03_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s03_couplers_to_s03_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s03_couplers_to_s03_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s03_couplers_to_s03_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s03_couplers_to_s03_couplers_AWREADY <= M_AXI_awready;
s03_couplers_to_s03_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s03_couplers_to_s03_couplers_AWVALID <= S_AXI_awvalid;
s03_couplers_to_s03_couplers_BREADY <= S_AXI_bready;
s03_couplers_to_s03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s03_couplers_to_s03_couplers_BVALID <= M_AXI_bvalid;
s03_couplers_to_s03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s03_couplers_to_s03_couplers_WLAST <= S_AXI_wlast;
s03_couplers_to_s03_couplers_WREADY <= M_AXI_wready;
s03_couplers_to_s03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s03_couplers_to_s03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s04_couplers_imp_130BMV8 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s04_couplers_imp_130BMV8;
architecture STRUCTURE of s04_couplers_imp_130BMV8 is
signal s04_couplers_to_s04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s04_couplers_to_s04_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s04_couplers_to_s04_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s04_couplers_to_s04_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s04_couplers_to_s04_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s04_couplers_to_s04_couplers_ARREADY : STD_LOGIC;
signal s04_couplers_to_s04_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s04_couplers_to_s04_couplers_ARVALID : STD_LOGIC;
signal s04_couplers_to_s04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s04_couplers_to_s04_couplers_RLAST : STD_LOGIC;
signal s04_couplers_to_s04_couplers_RREADY : STD_LOGIC;
signal s04_couplers_to_s04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s04_couplers_to_s04_couplers_RVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= s04_couplers_to_s04_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= s04_couplers_to_s04_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= s04_couplers_to_s04_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= s04_couplers_to_s04_couplers_ARLEN(7 downto 0);
M_AXI_arprot(2 downto 0) <= s04_couplers_to_s04_couplers_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= s04_couplers_to_s04_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= s04_couplers_to_s04_couplers_ARVALID;
M_AXI_rready <= s04_couplers_to_s04_couplers_RREADY;
S_AXI_arready <= s04_couplers_to_s04_couplers_ARREADY;
S_AXI_rdata(31 downto 0) <= s04_couplers_to_s04_couplers_RDATA(31 downto 0);
S_AXI_rlast <= s04_couplers_to_s04_couplers_RLAST;
S_AXI_rresp(1 downto 0) <= s04_couplers_to_s04_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= s04_couplers_to_s04_couplers_RVALID;
s04_couplers_to_s04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s04_couplers_to_s04_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s04_couplers_to_s04_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s04_couplers_to_s04_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s04_couplers_to_s04_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s04_couplers_to_s04_couplers_ARREADY <= M_AXI_arready;
s04_couplers_to_s04_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s04_couplers_to_s04_couplers_ARVALID <= S_AXI_arvalid;
s04_couplers_to_s04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s04_couplers_to_s04_couplers_RLAST <= M_AXI_rlast;
s04_couplers_to_s04_couplers_RREADY <= S_AXI_rready;
s04_couplers_to_s04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s04_couplers_to_s04_couplers_RVALID <= M_AXI_rvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SWandHW_standalone_axi_mem_intercon_1 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awready : out STD_LOGIC;
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wlast : in STD_LOGIC;
S01_AXI_wready : out STD_LOGIC;
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC;
S02_ACLK : in STD_LOGIC;
S02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arready : out STD_LOGIC;
S02_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arvalid : in STD_LOGIC;
S02_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_rlast : out STD_LOGIC;
S02_AXI_rready : in STD_LOGIC;
S02_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_rvalid : out STD_LOGIC;
S03_ACLK : in STD_LOGIC;
S03_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S03_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S03_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S03_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_awready : out STD_LOGIC;
S03_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_awvalid : in STD_LOGIC;
S03_AXI_bready : in STD_LOGIC;
S03_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_bvalid : out STD_LOGIC;
S03_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S03_AXI_wlast : in STD_LOGIC;
S03_AXI_wready : out STD_LOGIC;
S03_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_wvalid : in STD_LOGIC;
S04_ACLK : in STD_LOGIC;
S04_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S04_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S04_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S04_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S04_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S04_AXI_arready : out STD_LOGIC;
S04_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S04_AXI_arvalid : in STD_LOGIC;
S04_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S04_AXI_rlast : out STD_LOGIC;
S04_AXI_rready : in STD_LOGIC;
S04_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S04_AXI_rvalid : out STD_LOGIC
);
end design_SWandHW_standalone_axi_mem_intercon_1;
architecture STRUCTURE of design_SWandHW_standalone_axi_mem_intercon_1 is
component design_SWandHW_standalone_xbar_2 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 159 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 39 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 159 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 159 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 39 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 159 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_SWandHW_standalone_xbar_2;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S01_ACLK_1 : STD_LOGIC;
signal S01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S02_ACLK_1 : STD_LOGIC;
signal S02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S03_ACLK_1 : STD_LOGIC;
signal S03_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S04_ACLK_1 : STD_LOGIC;
signal S04_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WVALID : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s02_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s02_couplers_RVALID : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s03_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s03_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s03_couplers_WVALID : STD_LOGIC;
signal axi_mem_intercon_to_s04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s04_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s04_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s04_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s04_couplers_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s01_couplers_to_xbar_BREADY : STD_LOGIC;
signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_WLAST : STD_LOGIC;
signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_WVALID : STD_LOGIC;
signal s02_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s02_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal s02_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_RREADY : STD_LOGIC;
signal s02_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 5 downto 4 );
signal s02_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal s03_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s03_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s03_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s03_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s03_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s03_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal s03_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s03_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s03_couplers_to_xbar_BREADY : STD_LOGIC;
signal s03_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 7 downto 6 );
signal s03_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal s03_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s03_couplers_to_xbar_WLAST : STD_LOGIC;
signal s03_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal s03_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s03_couplers_to_xbar_WVALID : STD_LOGIC;
signal s04_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s04_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s04_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s04_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s04_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s04_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal s04_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s04_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s04_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal s04_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 4 to 4 );
signal s04_couplers_to_xbar_RREADY : STD_LOGIC;
signal s04_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 9 downto 8 );
signal s04_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC;
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_arready_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_xbar_s_axi_awready_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_xbar_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_xbar_s_axi_bvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_xbar_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 32 );
signal NLW_xbar_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_xbar_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_xbar_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
signal NLW_xbar_s_axi_rvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_xbar_s_axi_wready_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
M00_AXI_arid(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARID(2 downto 0);
M00_AXI_arlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0);
M00_AXI_arlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_mem_intercon_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0);
M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
M00_AXI_awid(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWID(2 downto 0);
M00_AXI_awlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0);
M00_AXI_awlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0);
M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_mem_intercon_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_mem_intercon_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_mem_intercon_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(31 downto 0);
M00_AXI_wid(2 downto 0) <= m00_couplers_to_axi_mem_intercon_WID(2 downto 0);
M00_AXI_wlast <= m00_couplers_to_axi_mem_intercon_WLAST;
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_mem_intercon_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready(0) <= axi_mem_intercon_to_s00_couplers_ARREADY(0);
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rlast(0) <= axi_mem_intercon_to_s00_couplers_RLAST(0);
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid(0) <= axi_mem_intercon_to_s00_couplers_RVALID(0);
S01_ACLK_1 <= S01_ACLK;
S01_ARESETN_1(0) <= S01_ARESETN(0);
S01_AXI_awready <= axi_mem_intercon_to_s01_couplers_AWREADY;
S01_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0);
S01_AXI_bvalid <= axi_mem_intercon_to_s01_couplers_BVALID;
S01_AXI_wready <= axi_mem_intercon_to_s01_couplers_WREADY;
S02_ACLK_1 <= S02_ACLK;
S02_ARESETN_1(0) <= S02_ARESETN(0);
S02_AXI_arready <= axi_mem_intercon_to_s02_couplers_ARREADY;
S02_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s02_couplers_RDATA(31 downto 0);
S02_AXI_rlast <= axi_mem_intercon_to_s02_couplers_RLAST;
S02_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s02_couplers_RRESP(1 downto 0);
S02_AXI_rvalid <= axi_mem_intercon_to_s02_couplers_RVALID;
S03_ACLK_1 <= S03_ACLK;
S03_ARESETN_1(0) <= S03_ARESETN(0);
S03_AXI_awready <= axi_mem_intercon_to_s03_couplers_AWREADY;
S03_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s03_couplers_BRESP(1 downto 0);
S03_AXI_bvalid <= axi_mem_intercon_to_s03_couplers_BVALID;
S03_AXI_wready <= axi_mem_intercon_to_s03_couplers_WREADY;
S04_ACLK_1 <= S04_ACLK;
S04_ARESETN_1(0) <= S04_ARESETN(0);
S04_AXI_arready <= axi_mem_intercon_to_s04_couplers_ARREADY;
S04_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s04_couplers_RDATA(31 downto 0);
S04_AXI_rlast <= axi_mem_intercon_to_s04_couplers_RLAST;
S04_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s04_couplers_RRESP(1 downto 0);
S04_AXI_rvalid <= axi_mem_intercon_to_s04_couplers_RVALID;
axi_mem_intercon_ACLK_net <= ACLK;
axi_mem_intercon_ARESETN_net(0) <= ARESETN(0);
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
axi_mem_intercon_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0) <= S01_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0) <= S01_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0) <= S01_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0) <= S01_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWVALID <= S01_AXI_awvalid;
axi_mem_intercon_to_s01_couplers_BREADY <= S01_AXI_bready;
axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s01_couplers_WLAST <= S01_AXI_wlast;
axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s01_couplers_WVALID <= S01_AXI_wvalid;
axi_mem_intercon_to_s02_couplers_ARADDR(31 downto 0) <= S02_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s02_couplers_ARBURST(1 downto 0) <= S02_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s02_couplers_ARCACHE(3 downto 0) <= S02_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s02_couplers_ARLEN(7 downto 0) <= S02_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s02_couplers_ARPROT(2 downto 0) <= S02_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s02_couplers_ARSIZE(2 downto 0) <= S02_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s02_couplers_ARVALID <= S02_AXI_arvalid;
axi_mem_intercon_to_s02_couplers_RREADY <= S02_AXI_rready;
axi_mem_intercon_to_s03_couplers_AWADDR(31 downto 0) <= S03_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s03_couplers_AWBURST(1 downto 0) <= S03_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s03_couplers_AWCACHE(3 downto 0) <= S03_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s03_couplers_AWLEN(7 downto 0) <= S03_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s03_couplers_AWPROT(2 downto 0) <= S03_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s03_couplers_AWSIZE(2 downto 0) <= S03_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s03_couplers_AWVALID <= S03_AXI_awvalid;
axi_mem_intercon_to_s03_couplers_BREADY <= S03_AXI_bready;
axi_mem_intercon_to_s03_couplers_WDATA(31 downto 0) <= S03_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s03_couplers_WLAST <= S03_AXI_wlast;
axi_mem_intercon_to_s03_couplers_WSTRB(3 downto 0) <= S03_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s03_couplers_WVALID <= S03_AXI_wvalid;
axi_mem_intercon_to_s04_couplers_ARADDR(31 downto 0) <= S04_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s04_couplers_ARBURST(1 downto 0) <= S04_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s04_couplers_ARCACHE(3 downto 0) <= S04_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s04_couplers_ARLEN(7 downto 0) <= S04_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s04_couplers_ARPROT(2 downto 0) <= S04_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s04_couplers_ARSIZE(2 downto 0) <= S04_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s04_couplers_ARVALID <= S04_AXI_arvalid;
axi_mem_intercon_to_s04_couplers_RREADY <= S04_AXI_rready;
m00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_mem_intercon_BID(5 downto 0) <= M00_AXI_bid(5 downto 0);
m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_mem_intercon_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_axi_mem_intercon_RID(5 downto 0) <= M00_AXI_rid(5 downto 0);
m00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast;
m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_3Z6JOL
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
M_AXI_arid(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARID(2 downto 0),
M_AXI_arlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0),
M_AXI_arlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0),
M_AXI_arready => m00_couplers_to_axi_mem_intercon_ARREADY,
M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
M_AXI_arvalid => m00_couplers_to_axi_mem_intercon_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
M_AXI_awid(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWID(2 downto 0),
M_AXI_awlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0),
M_AXI_awlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0),
M_AXI_awready => m00_couplers_to_axi_mem_intercon_AWREADY,
M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
M_AXI_awvalid => m00_couplers_to_axi_mem_intercon_AWVALID,
M_AXI_bid(5 downto 0) => m00_couplers_to_axi_mem_intercon_BID(5 downto 0),
M_AXI_bready => m00_couplers_to_axi_mem_intercon_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_mem_intercon_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(31 downto 0),
M_AXI_rid(5 downto 0) => m00_couplers_to_axi_mem_intercon_RID(5 downto 0),
M_AXI_rlast => m00_couplers_to_axi_mem_intercon_RLAST,
M_AXI_rready => m00_couplers_to_axi_mem_intercon_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_mem_intercon_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(31 downto 0),
M_AXI_wid(2 downto 0) => m00_couplers_to_axi_mem_intercon_WID(2 downto 0),
M_AXI_wlast => m00_couplers_to_axi_mem_intercon_WLAST,
M_AXI_wready => m00_couplers_to_axi_mem_intercon_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_mem_intercon_WVALID,
S_ACLK => axi_mem_intercon_ACLK_net,
S_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(2 downto 0) => xbar_to_m00_couplers_ARID(2 downto 0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(2 downto 0) => xbar_to_m00_couplers_AWID(2 downto 0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bid(2 downto 0) => xbar_to_m00_couplers_BID(2 downto 0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rid(2 downto 0) => xbar_to_m00_couplers_RID(2 downto 0),
S_AXI_rlast => xbar_to_m00_couplers_RLAST,
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wlast => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
s00_couplers: entity work.s00_couplers_imp_14GRHI
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rlast(0) => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => axi_mem_intercon_to_s00_couplers_ARREADY(0),
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid(0) => axi_mem_intercon_to_s00_couplers_ARVALID(0),
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rlast(0) => axi_mem_intercon_to_s00_couplers_RLAST(0),
S_AXI_rready(0) => axi_mem_intercon_to_s00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => axi_mem_intercon_to_s00_couplers_RVALID(0)
);
s01_couplers: entity work.s01_couplers_imp_1KHG2CU
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s01_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s01_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s01_couplers_to_xbar_AWREADY(1),
M_AXI_awsize(2 downto 0) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s01_couplers_to_xbar_AWVALID,
M_AXI_bready => s01_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2),
M_AXI_bvalid => s01_couplers_to_xbar_BVALID(1),
M_AXI_wdata(31 downto 0) => s01_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wlast => s01_couplers_to_xbar_WLAST,
M_AXI_wready => s01_couplers_to_xbar_WREADY(1),
M_AXI_wstrb(3 downto 0) => s01_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s01_couplers_to_xbar_WVALID,
S_ACLK => S01_ACLK_1,
S_ARESETN(0) => S01_ARESETN_1(0),
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0),
S_AXI_awready => axi_mem_intercon_to_s01_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s01_couplers_AWVALID,
S_AXI_bready => axi_mem_intercon_to_s01_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s01_couplers_BVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s01_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s01_couplers_WVALID
);
s02_couplers: entity work.s02_couplers_imp_HTS99Z
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s02_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s02_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s02_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s02_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arprot(2 downto 0) => s02_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s02_couplers_to_xbar_ARREADY(2),
M_AXI_arsize(2 downto 0) => s02_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s02_couplers_to_xbar_ARVALID,
M_AXI_rdata(31 downto 0) => s02_couplers_to_xbar_RDATA(95 downto 64),
M_AXI_rlast => s02_couplers_to_xbar_RLAST(2),
M_AXI_rready => s02_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s02_couplers_to_xbar_RRESP(5 downto 4),
M_AXI_rvalid => s02_couplers_to_xbar_RVALID(2),
S_ACLK => S02_ACLK_1,
S_ARESETN(0) => S02_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s02_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s02_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s02_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s02_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s02_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_mem_intercon_to_s02_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s02_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s02_couplers_ARVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s02_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s02_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s02_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s02_couplers_RVALID
);
s03_couplers: entity work.s03_couplers_imp_13X1ZY7
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_awaddr(31 downto 0) => s03_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s03_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s03_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s03_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awprot(2 downto 0) => s03_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s03_couplers_to_xbar_AWREADY(3),
M_AXI_awsize(2 downto 0) => s03_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s03_couplers_to_xbar_AWVALID,
M_AXI_bready => s03_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s03_couplers_to_xbar_BRESP(7 downto 6),
M_AXI_bvalid => s03_couplers_to_xbar_BVALID(3),
M_AXI_wdata(31 downto 0) => s03_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wlast => s03_couplers_to_xbar_WLAST,
M_AXI_wready => s03_couplers_to_xbar_WREADY(3),
M_AXI_wstrb(3 downto 0) => s03_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s03_couplers_to_xbar_WVALID,
S_ACLK => S03_ACLK_1,
S_ARESETN(0) => S03_ARESETN_1(0),
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s03_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s03_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s03_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s03_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s03_couplers_AWPROT(2 downto 0),
S_AXI_awready => axi_mem_intercon_to_s03_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s03_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s03_couplers_AWVALID,
S_AXI_bready => axi_mem_intercon_to_s03_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s03_couplers_BVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s03_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s03_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s03_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s03_couplers_WVALID
);
s04_couplers: entity work.s04_couplers_imp_130BMV8
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s04_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s04_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s04_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s04_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arprot(2 downto 0) => s04_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s04_couplers_to_xbar_ARREADY(4),
M_AXI_arsize(2 downto 0) => s04_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s04_couplers_to_xbar_ARVALID,
M_AXI_rdata(31 downto 0) => s04_couplers_to_xbar_RDATA(159 downto 128),
M_AXI_rlast => s04_couplers_to_xbar_RLAST(4),
M_AXI_rready => s04_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s04_couplers_to_xbar_RRESP(9 downto 8),
M_AXI_rvalid => s04_couplers_to_xbar_RVALID(4),
S_ACLK => S04_ACLK_1,
S_ARESETN(0) => S04_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s04_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s04_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s04_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s04_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s04_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_mem_intercon_to_s04_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s04_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s04_couplers_ARVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s04_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s04_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s04_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s04_couplers_RVALID
);
xbar: component design_SWandHW_standalone_xbar_2
port map (
aclk => axi_mem_intercon_ACLK_net,
aresetn => axi_mem_intercon_ARESETN_net(0),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(2 downto 0) => xbar_to_m00_couplers_ARID(2 downto 0),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(2 downto 0) => xbar_to_m00_couplers_AWID(2 downto 0),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bid(2 downto 0) => xbar_to_m00_couplers_BID(2 downto 0),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rid(2 downto 0) => xbar_to_m00_couplers_RID(2 downto 0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST,
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(159 downto 128) => s04_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(127 downto 96) => B"00000000000000000000000000000000",
s_axi_araddr(95 downto 64) => s02_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(63 downto 32) => B"00000000000000000000000000000000",
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(9 downto 8) => s04_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arburst(7 downto 6) => B"00",
s_axi_arburst(5 downto 4) => s02_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arburst(3 downto 2) => B"00",
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(19 downto 16) => s04_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arcache(15 downto 12) => B"0000",
s_axi_arcache(11 downto 8) => s02_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arcache(7 downto 4) => B"0000",
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(14 downto 0) => B"000000000000000",
s_axi_arlen(39 downto 32) => s04_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlen(31 downto 24) => B"00000000",
s_axi_arlen(23 downto 16) => s02_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlen(15 downto 8) => B"00000000",
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(4 downto 0) => B"00000",
s_axi_arprot(14 downto 12) => s04_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(11 downto 9) => B"000",
s_axi_arprot(8 downto 6) => s02_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(5 downto 3) => B"000",
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(19 downto 0) => B"00000000000000000000",
s_axi_arready(4) => s04_couplers_to_xbar_ARREADY(4),
s_axi_arready(3) => NLW_xbar_s_axi_arready_UNCONNECTED(3),
s_axi_arready(2) => s02_couplers_to_xbar_ARREADY(2),
s_axi_arready(1) => NLW_xbar_s_axi_arready_UNCONNECTED(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(14 downto 12) => s04_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arsize(11 downto 9) => B"000",
s_axi_arsize(8 downto 6) => s02_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arsize(5 downto 3) => B"000",
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(4) => s04_couplers_to_xbar_ARVALID,
s_axi_arvalid(3) => '0',
s_axi_arvalid(2) => s02_couplers_to_xbar_ARVALID,
s_axi_arvalid(1) => '0',
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
s_axi_awaddr(159 downto 128) => B"00000000000000000000000000000000",
s_axi_awaddr(127 downto 96) => s03_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(95 downto 64) => B"00000000000000000000000000000000",
s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(9 downto 8) => B"00",
s_axi_awburst(7 downto 6) => s03_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(5 downto 4) => B"00",
s_axi_awburst(3 downto 2) => s01_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(19 downto 16) => B"0000",
s_axi_awcache(15 downto 12) => s03_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(11 downto 8) => B"0000",
s_axi_awcache(7 downto 4) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(14 downto 0) => B"000000000000000",
s_axi_awlen(39 downto 32) => B"00000000",
s_axi_awlen(31 downto 24) => s03_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(23 downto 16) => B"00000000",
s_axi_awlen(15 downto 8) => s01_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(4 downto 0) => B"00000",
s_axi_awprot(14 downto 12) => B"000",
s_axi_awprot(11 downto 9) => s03_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(8 downto 6) => B"000",
s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(19 downto 0) => B"00000000000000000000",
s_axi_awready(4) => NLW_xbar_s_axi_awready_UNCONNECTED(4),
s_axi_awready(3) => s03_couplers_to_xbar_AWREADY(3),
s_axi_awready(2) => NLW_xbar_s_axi_awready_UNCONNECTED(2),
s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1),
s_axi_awready(0) => NLW_xbar_s_axi_awready_UNCONNECTED(0),
s_axi_awsize(14 downto 12) => B"000",
s_axi_awsize(11 downto 9) => s03_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(8 downto 6) => B"000",
s_axi_awsize(5 downto 3) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid(4) => '0',
s_axi_awvalid(3) => s03_couplers_to_xbar_AWVALID,
s_axi_awvalid(2) => '0',
s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID,
s_axi_awvalid(0) => '0',
s_axi_bid(14 downto 0) => NLW_xbar_s_axi_bid_UNCONNECTED(14 downto 0),
s_axi_bready(4) => '0',
s_axi_bready(3) => s03_couplers_to_xbar_BREADY,
s_axi_bready(2) => '1',
s_axi_bready(1) => s01_couplers_to_xbar_BREADY,
s_axi_bready(0) => '0',
s_axi_bresp(9 downto 8) => NLW_xbar_s_axi_bresp_UNCONNECTED(9 downto 8),
s_axi_bresp(7 downto 6) => s03_couplers_to_xbar_BRESP(7 downto 6),
s_axi_bresp(5 downto 4) => NLW_xbar_s_axi_bresp_UNCONNECTED(5 downto 4),
s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2),
s_axi_bresp(1 downto 0) => NLW_xbar_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid(4) => NLW_xbar_s_axi_bvalid_UNCONNECTED(4),
s_axi_bvalid(3) => s03_couplers_to_xbar_BVALID(3),
s_axi_bvalid(2) => NLW_xbar_s_axi_bvalid_UNCONNECTED(2),
s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1),
s_axi_bvalid(0) => NLW_xbar_s_axi_bvalid_UNCONNECTED(0),
s_axi_rdata(159 downto 128) => s04_couplers_to_xbar_RDATA(159 downto 128),
s_axi_rdata(127 downto 96) => NLW_xbar_s_axi_rdata_UNCONNECTED(127 downto 96),
s_axi_rdata(95 downto 64) => s02_couplers_to_xbar_RDATA(95 downto 64),
s_axi_rdata(63 downto 32) => NLW_xbar_s_axi_rdata_UNCONNECTED(63 downto 32),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rid(14 downto 0) => NLW_xbar_s_axi_rid_UNCONNECTED(14 downto 0),
s_axi_rlast(4) => s04_couplers_to_xbar_RLAST(4),
s_axi_rlast(3) => NLW_xbar_s_axi_rlast_UNCONNECTED(3),
s_axi_rlast(2) => s02_couplers_to_xbar_RLAST(2),
s_axi_rlast(1) => NLW_xbar_s_axi_rlast_UNCONNECTED(1),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(4) => s04_couplers_to_xbar_RREADY,
s_axi_rready(3) => '0',
s_axi_rready(2) => s02_couplers_to_xbar_RREADY,
s_axi_rready(1) => '0',
s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
s_axi_rresp(9 downto 8) => s04_couplers_to_xbar_RRESP(9 downto 8),
s_axi_rresp(7 downto 6) => NLW_xbar_s_axi_rresp_UNCONNECTED(7 downto 6),
s_axi_rresp(5 downto 4) => s02_couplers_to_xbar_RRESP(5 downto 4),
s_axi_rresp(3 downto 2) => NLW_xbar_s_axi_rresp_UNCONNECTED(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(4) => s04_couplers_to_xbar_RVALID(4),
s_axi_rvalid(3) => NLW_xbar_s_axi_rvalid_UNCONNECTED(3),
s_axi_rvalid(2) => s02_couplers_to_xbar_RVALID(2),
s_axi_rvalid(1) => NLW_xbar_s_axi_rvalid_UNCONNECTED(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(159 downto 128) => B"00000000000000000000000000000000",
s_axi_wdata(127 downto 96) => s03_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(95 downto 64) => B"00000000000000000000000000000000",
s_axi_wdata(63 downto 32) => s01_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast(4) => '0',
s_axi_wlast(3) => s03_couplers_to_xbar_WLAST,
s_axi_wlast(2) => '1',
s_axi_wlast(1) => s01_couplers_to_xbar_WLAST,
s_axi_wlast(0) => '1',
s_axi_wready(4) => NLW_xbar_s_axi_wready_UNCONNECTED(4),
s_axi_wready(3) => s03_couplers_to_xbar_WREADY(3),
s_axi_wready(2) => NLW_xbar_s_axi_wready_UNCONNECTED(2),
s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1),
s_axi_wready(0) => NLW_xbar_s_axi_wready_UNCONNECTED(0),
s_axi_wstrb(19 downto 16) => B"0000",
s_axi_wstrb(15 downto 12) => s03_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(11 downto 8) => B"0000",
s_axi_wstrb(7 downto 4) => s01_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(3 downto 0) => B"1111",
s_axi_wvalid(4) => '0',
s_axi_wvalid(3) => s03_couplers_to_xbar_WVALID,
s_axi_wvalid(2) => '1',
s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID,
s_axi_wvalid(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SWandHW_standalone_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wvalid : out STD_LOGIC;
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_arready : in STD_LOGIC;
M04_AXI_arvalid : out STD_LOGIC;
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_awready : in STD_LOGIC;
M04_AXI_awvalid : out STD_LOGIC;
M04_AXI_bready : out STD_LOGIC;
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC;
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC;
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC;
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC;
M04_AXI_wvalid : out STD_LOGIC;
M05_ACLK : in STD_LOGIC;
M05_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_arready : in STD_LOGIC;
M05_AXI_arvalid : out STD_LOGIC;
M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_awready : in STD_LOGIC;
M05_AXI_awvalid : out STD_LOGIC;
M05_AXI_bready : out STD_LOGIC;
M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_bvalid : in STD_LOGIC;
M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_rready : out STD_LOGIC;
M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_rvalid : in STD_LOGIC;
M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_wready : in STD_LOGIC;
M05_AXI_wvalid : out STD_LOGIC;
M06_ACLK : in STD_LOGIC;
M06_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_arready : in STD_LOGIC;
M06_AXI_arvalid : out STD_LOGIC;
M06_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_awready : in STD_LOGIC;
M06_AXI_awvalid : out STD_LOGIC;
M06_AXI_bready : out STD_LOGIC;
M06_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_bvalid : in STD_LOGIC;
M06_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_rready : out STD_LOGIC;
M06_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_rvalid : in STD_LOGIC;
M06_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_wready : in STD_LOGIC;
M06_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end design_SWandHW_standalone_processing_system7_0_axi_periph_0;
architecture STRUCTURE of design_SWandHW_standalone_processing_system7_0_axi_periph_0 is
component design_SWandHW_standalone_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 6 downto 0 )
);
end component design_SWandHW_standalone_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M04_ACLK_1 : STD_LOGIC;
signal M04_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M05_ACLK_1 : STD_LOGIC;
signal M05_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M06_ACLK_1 : STD_LOGIC;
signal M06_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_BVALID : STD_LOGIC;
signal xbar_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_RVALID : STD_LOGIC;
signal xbar_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_WREADY : STD_LOGIC;
signal xbar_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m06_couplers_ARVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m06_couplers_AWVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_BVALID : STD_LOGIC;
signal xbar_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m06_couplers_RREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_RVALID : STD_LOGIC;
signal xbar_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_WREADY : STD_LOGIC;
signal xbar_to_m06_couplers_WVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 0 );
signal NLW_xbar_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 27 downto 8 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M01_AXI_arvalid <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M01_AXI_awvalid <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
M01_AXI_bready <= m01_couplers_to_processing_system7_0_axi_periph_BREADY;
M01_AXI_rready <= m01_couplers_to_processing_system7_0_axi_periph_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_processing_system7_0_axi_periph_WVALID;
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1(0) <= M02_ARESETN(0);
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M02_AXI_arvalid <= m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M02_AXI_awvalid <= m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
M02_AXI_bready <= m02_couplers_to_processing_system7_0_axi_periph_BREADY;
M02_AXI_rready <= m02_couplers_to_processing_system7_0_axi_periph_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wvalid <= m02_couplers_to_processing_system7_0_axi_periph_WVALID;
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1(0) <= M03_ARESETN(0);
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M03_AXI_arvalid <= m03_couplers_to_processing_system7_0_axi_periph_ARVALID;
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M03_AXI_awvalid <= m03_couplers_to_processing_system7_0_axi_periph_AWVALID;
M03_AXI_bready <= m03_couplers_to_processing_system7_0_axi_periph_BREADY;
M03_AXI_rready <= m03_couplers_to_processing_system7_0_axi_periph_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M03_AXI_wvalid <= m03_couplers_to_processing_system7_0_axi_periph_WVALID;
M04_ACLK_1 <= M04_ACLK;
M04_ARESETN_1(0) <= M04_ARESETN(0);
M04_AXI_araddr(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M04_AXI_arvalid <= m04_couplers_to_processing_system7_0_axi_periph_ARVALID;
M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M04_AXI_awvalid <= m04_couplers_to_processing_system7_0_axi_periph_AWVALID;
M04_AXI_bready <= m04_couplers_to_processing_system7_0_axi_periph_BREADY;
M04_AXI_rready <= m04_couplers_to_processing_system7_0_axi_periph_RREADY;
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M04_AXI_wvalid <= m04_couplers_to_processing_system7_0_axi_periph_WVALID;
M05_ACLK_1 <= M05_ACLK;
M05_ARESETN_1(0) <= M05_ARESETN(0);
M05_AXI_araddr(31 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M05_AXI_arvalid <= m05_couplers_to_processing_system7_0_axi_periph_ARVALID;
M05_AXI_awaddr(31 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M05_AXI_awvalid <= m05_couplers_to_processing_system7_0_axi_periph_AWVALID;
M05_AXI_bready <= m05_couplers_to_processing_system7_0_axi_periph_BREADY;
M05_AXI_rready <= m05_couplers_to_processing_system7_0_axi_periph_RREADY;
M05_AXI_wdata(31 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M05_AXI_wvalid <= m05_couplers_to_processing_system7_0_axi_periph_WVALID;
M06_ACLK_1 <= M06_ACLK;
M06_ARESETN_1(0) <= M06_ARESETN(0);
M06_AXI_araddr(31 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M06_AXI_arvalid <= m06_couplers_to_processing_system7_0_axi_periph_ARVALID;
M06_AXI_awaddr(31 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M06_AXI_awvalid <= m06_couplers_to_processing_system7_0_axi_periph_AWVALID;
M06_AXI_bready <= m06_couplers_to_processing_system7_0_axi_periph_BREADY;
M06_AXI_rready <= m06_couplers_to_processing_system7_0_axi_periph_RREADY;
M06_AXI_wdata(31 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M06_AXI_wvalid <= m06_couplers_to_processing_system7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_processing_system7_0_axi_periph_ARREADY <= M01_AXI_arready;
m01_couplers_to_processing_system7_0_axi_periph_AWREADY <= M01_AXI_awready;
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID <= M01_AXI_bvalid;
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID <= M01_AXI_rvalid;
m01_couplers_to_processing_system7_0_axi_periph_WREADY <= M01_AXI_wready;
m02_couplers_to_processing_system7_0_axi_periph_ARREADY <= M02_AXI_arready;
m02_couplers_to_processing_system7_0_axi_periph_AWREADY <= M02_AXI_awready;
m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_BVALID <= M02_AXI_bvalid;
m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RVALID <= M02_AXI_rvalid;
m02_couplers_to_processing_system7_0_axi_periph_WREADY <= M02_AXI_wready;
m03_couplers_to_processing_system7_0_axi_periph_ARREADY <= M03_AXI_arready;
m03_couplers_to_processing_system7_0_axi_periph_AWREADY <= M03_AXI_awready;
m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_BVALID <= M03_AXI_bvalid;
m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_RVALID <= M03_AXI_rvalid;
m03_couplers_to_processing_system7_0_axi_periph_WREADY <= M03_AXI_wready;
m04_couplers_to_processing_system7_0_axi_periph_ARREADY <= M04_AXI_arready;
m04_couplers_to_processing_system7_0_axi_periph_AWREADY <= M04_AXI_awready;
m04_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_BVALID <= M04_AXI_bvalid;
m04_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_RVALID <= M04_AXI_rvalid;
m04_couplers_to_processing_system7_0_axi_periph_WREADY <= M04_AXI_wready;
m05_couplers_to_processing_system7_0_axi_periph_ARREADY <= M05_AXI_arready;
m05_couplers_to_processing_system7_0_axi_periph_AWREADY <= M05_AXI_awready;
m05_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M05_AXI_bresp(1 downto 0);
m05_couplers_to_processing_system7_0_axi_periph_BVALID <= M05_AXI_bvalid;
m05_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M05_AXI_rdata(31 downto 0);
m05_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M05_AXI_rresp(1 downto 0);
m05_couplers_to_processing_system7_0_axi_periph_RVALID <= M05_AXI_rvalid;
m05_couplers_to_processing_system7_0_axi_periph_WREADY <= M05_AXI_wready;
m06_couplers_to_processing_system7_0_axi_periph_ARREADY <= M06_AXI_arready;
m06_couplers_to_processing_system7_0_axi_periph_AWREADY <= M06_AXI_awready;
m06_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M06_AXI_bresp(1 downto 0);
m06_couplers_to_processing_system7_0_axi_periph_BVALID <= M06_AXI_bvalid;
m06_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M06_AXI_rdata(31 downto 0);
m06_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M06_AXI_rresp(1 downto 0);
m06_couplers_to_processing_system7_0_axi_periph_RVALID <= M06_AXI_rvalid;
m06_couplers_to_processing_system7_0_axi_periph_WREADY <= M06_AXI_wready;
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_1MVOGV6
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_7OD9KA
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m01_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m01_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m01_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m01_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m01_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_1432F1V
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN(0) => M02_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m02_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m02_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m02_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m02_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m02_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wvalid => m02_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_QLWQRF
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN(0) => M03_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m03_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m03_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m03_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m03_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m03_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wvalid => m03_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_PPSTKW
port map (
M_ACLK => M04_ACLK_1,
M_ARESETN(0) => M04_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m04_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m04_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m04_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m04_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m04_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m04_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m04_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m04_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m04_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wvalid => m04_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
S_AXI_arready => xbar_to_m04_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
S_AXI_awready => xbar_to_m04_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready => xbar_to_m04_couplers_WREADY,
S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
);
m05_couplers: entity work.m05_couplers_imp_14U9M2W
port map (
M_ACLK => M05_ACLK_1,
M_ARESETN(0) => M05_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m05_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m05_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m05_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m05_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m05_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m05_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m05_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m05_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m05_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wvalid => m05_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m05_couplers_ARADDR(191 downto 160),
S_AXI_arready => xbar_to_m05_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m05_couplers_ARVALID(5),
S_AXI_awaddr(31 downto 0) => xbar_to_m05_couplers_AWADDR(191 downto 160),
S_AXI_awready => xbar_to_m05_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m05_couplers_AWVALID(5),
S_AXI_bready => xbar_to_m05_couplers_BREADY(5),
S_AXI_bresp(1 downto 0) => xbar_to_m05_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m05_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m05_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m05_couplers_RREADY(5),
S_AXI_rresp(1 downto 0) => xbar_to_m05_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m05_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m05_couplers_WDATA(191 downto 160),
S_AXI_wready => xbar_to_m05_couplers_WREADY,
S_AXI_wvalid => xbar_to_m05_couplers_WVALID(5)
);
m06_couplers: entity work.m06_couplers_imp_6WKA35
port map (
M_ACLK => M06_ACLK_1,
M_ARESETN(0) => M06_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m06_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m06_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m06_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m06_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m06_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m06_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m06_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m06_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m06_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wvalid => m06_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m06_couplers_ARADDR(223 downto 192),
S_AXI_arready => xbar_to_m06_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m06_couplers_ARVALID(6),
S_AXI_awaddr(31 downto 0) => xbar_to_m06_couplers_AWADDR(223 downto 192),
S_AXI_awready => xbar_to_m06_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m06_couplers_AWVALID(6),
S_AXI_bready => xbar_to_m06_couplers_BREADY(6),
S_AXI_bresp(1 downto 0) => xbar_to_m06_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m06_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m06_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m06_couplers_RREADY(6),
S_AXI_rresp(1 downto 0) => xbar_to_m06_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m06_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m06_couplers_WDATA(223 downto 192),
S_AXI_wready => xbar_to_m06_couplers_WREADY,
S_AXI_wvalid => xbar_to_m06_couplers_WVALID(6)
);
s00_couplers: entity work.s00_couplers_imp_1PPRTY9
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component design_SWandHW_standalone_xbar_0
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net(0),
m_axi_araddr(223 downto 192) => xbar_to_m06_couplers_ARADDR(223 downto 192),
m_axi_araddr(191 downto 160) => xbar_to_m05_couplers_ARADDR(191 downto 160),
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(20 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(20 downto 0),
m_axi_arready(6) => xbar_to_m06_couplers_ARREADY,
m_axi_arready(5) => xbar_to_m05_couplers_ARREADY,
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(6) => xbar_to_m06_couplers_ARVALID(6),
m_axi_arvalid(5) => xbar_to_m05_couplers_ARVALID(5),
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(223 downto 192) => xbar_to_m06_couplers_AWADDR(223 downto 192),
m_axi_awaddr(191 downto 160) => xbar_to_m05_couplers_AWADDR(191 downto 160),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(20 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(20 downto 0),
m_axi_awready(6) => xbar_to_m06_couplers_AWREADY,
m_axi_awready(5) => xbar_to_m05_couplers_AWREADY,
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(6) => xbar_to_m06_couplers_AWVALID(6),
m_axi_awvalid(5) => xbar_to_m05_couplers_AWVALID(5),
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(6) => xbar_to_m06_couplers_BREADY(6),
m_axi_bready(5) => xbar_to_m05_couplers_BREADY(5),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(13 downto 12) => xbar_to_m06_couplers_BRESP(1 downto 0),
m_axi_bresp(11 downto 10) => xbar_to_m05_couplers_BRESP(1 downto 0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(6) => xbar_to_m06_couplers_BVALID,
m_axi_bvalid(5) => xbar_to_m05_couplers_BVALID,
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(223 downto 192) => xbar_to_m06_couplers_RDATA(31 downto 0),
m_axi_rdata(191 downto 160) => xbar_to_m05_couplers_RDATA(31 downto 0),
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(6) => xbar_to_m06_couplers_RREADY(6),
m_axi_rready(5) => xbar_to_m05_couplers_RREADY(5),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(13 downto 12) => xbar_to_m06_couplers_RRESP(1 downto 0),
m_axi_rresp(11 downto 10) => xbar_to_m05_couplers_RRESP(1 downto 0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(6) => xbar_to_m06_couplers_RVALID,
m_axi_rvalid(5) => xbar_to_m05_couplers_RVALID,
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(223 downto 192) => xbar_to_m06_couplers_WDATA(223 downto 192),
m_axi_wdata(191 downto 160) => xbar_to_m05_couplers_WDATA(191 downto 160),
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(6) => xbar_to_m06_couplers_WREADY,
m_axi_wready(5) => xbar_to_m05_couplers_WREADY,
m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(27 downto 8) => NLW_xbar_m_axi_wstrb_UNCONNECTED(27 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(6) => xbar_to_m06_couplers_WVALID(6),
m_axi_wvalid(5) => xbar_to_m05_couplers_WVALID(5),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SWandHW_standalone is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
leds_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of design_SWandHW_standalone : entity is "design_SWandHW_standalone,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_SWandHW_standalone,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=35,numReposBlks=19,numNonXlnxBlks=1,numHierBlks=16,maxHierDepth=0,da_axi4_cnt=14,da_axi4_s2mm_cnt=7,da_board_cnt=1,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of design_SWandHW_standalone : entity is "design_SWandHW_standalone.hwdef";
end design_SWandHW_standalone;
architecture STRUCTURE of design_SWandHW_standalone is
component design_SWandHW_standalone_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 5 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component design_SWandHW_standalone_processing_system7_0_0;
component design_SWandHW_standalone_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component design_SWandHW_standalone_axi_gpio_0_0;
component design_SWandHW_standalone_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_SWandHW_standalone_rst_processing_system7_0_100M_0;
component design_SWandHW_standalone_feedforward_0_0 is
port (
s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_AXILiteS_AWVALID : in STD_LOGIC;
s_axi_AXILiteS_AWREADY : out STD_LOGIC;
s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_AXILiteS_WVALID : in STD_LOGIC;
s_axi_AXILiteS_WREADY : out STD_LOGIC;
s_axi_AXILiteS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_BVALID : out STD_LOGIC;
s_axi_AXILiteS_BREADY : in STD_LOGIC;
s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_AXILiteS_ARVALID : in STD_LOGIC;
s_axi_AXILiteS_ARREADY : out STD_LOGIC;
s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_RVALID : out STD_LOGIC;
s_axi_AXILiteS_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
interrupt : out STD_LOGIC;
P_config_TVALID : in STD_LOGIC;
P_config_TREADY : out STD_LOGIC;
P_config_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
P_WandB_TVALID : in STD_LOGIC;
P_WandB_TREADY : out STD_LOGIC;
P_WandB_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
P_uOut_TVALID : out STD_LOGIC;
P_uOut_TREADY : in STD_LOGIC;
P_uOut_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
P_netIn_TVALID : in STD_LOGIC;
P_netIn_TREADY : out STD_LOGIC;
P_netIn_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
P_netOut_TVALID : out STD_LOGIC;
P_netOut_TREADY : in STD_LOGIC;
P_netOut_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_SWandHW_standalone_feedforward_0_0;
component design_SWandHW_standalone_xlconcat_0_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
In2 : in STD_LOGIC_VECTOR ( 0 to 0 );
In3 : in STD_LOGIC_VECTOR ( 0 to 0 );
In4 : in STD_LOGIC_VECTOR ( 0 to 0 );
In5 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end component design_SWandHW_standalone_xlconcat_0_0;
component design_SWandHW_standalone_axi_dma_1 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
mm2s_introut : out STD_LOGIC
);
end component design_SWandHW_standalone_axi_dma_1;
component design_SWandHW_standalone_axi_dma_1_1 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s2mm_prmry_reset_out_n : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC;
s_axis_s2mm_tlast : in STD_LOGIC;
s2mm_introut : out STD_LOGIC
);
end component design_SWandHW_standalone_axi_dma_1_1;
component design_SWandHW_standalone_axi_dma_2_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
mm2s_introut : out STD_LOGIC
);
end component design_SWandHW_standalone_axi_dma_2_0;
component design_SWandHW_standalone_axi_dma_3_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s2mm_prmry_reset_out_n : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC;
s_axis_s2mm_tlast : in STD_LOGIC;
s2mm_introut : out STD_LOGIC
);
end component design_SWandHW_standalone_axi_dma_3_0;
component design_SWandHW_standalone_axi_dma_4_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
mm2s_introut : out STD_LOGIC
);
end component design_SWandHW_standalone_axi_dma_4_0;
component design_SWandHW_standalone_axis_data_fifo_0_0 is
port (
s_axis_aresetn : in STD_LOGIC;
s_axis_aclk : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
axis_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_SWandHW_standalone_axis_data_fifo_0_0;
component design_SWandHW_standalone_axis_data_fifo_1_0 is
port (
s_axis_aresetn : in STD_LOGIC;
s_axis_aclk : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
axis_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_SWandHW_standalone_axis_data_fifo_1_0;
component design_SWandHW_standalone_axis_data_fifo_2_0 is
port (
s_axis_aresetn : in STD_LOGIC;
s_axis_aclk : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
axis_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_SWandHW_standalone_axis_data_fifo_2_0;
component design_SWandHW_standalone_axis_data_fifo_3_0 is
port (
s_axis_aresetn : in STD_LOGIC;
s_axis_aclk : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
axis_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_SWandHW_standalone_axis_data_fifo_3_0;
component design_SWandHW_standalone_axis_data_fifo_4_0 is
port (
s_axis_aresetn : in STD_LOGIC;
s_axis_aclk : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
axis_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_SWandHW_standalone_axis_data_fifo_4_0;
signal axi_dma_1_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWREADY : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWVALID : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_BREADY : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_1_M_AXI_S2MM_BVALID : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_1_M_AXI_S2MM_WLAST : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_WREADY : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_1_M_AXI_S2MM_WVALID : STD_LOGIC;
signal axi_dma_1_s2mm_introut : STD_LOGIC;
signal axi_dma_2_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_2_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_2_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_dma_2_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_2_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_2_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARREADY : STD_LOGIC;
signal axi_dma_2_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_2_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_2_M_AXI_MM2S_RLAST : STD_LOGIC;
signal axi_dma_2_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_2_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_2_M_AXI_MM2S_RVALID : STD_LOGIC;
signal axi_dma_2_mm2s_introut : STD_LOGIC;
signal axi_dma_3_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_3_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_3_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_3_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_3_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_3_M_AXI_S2MM_AWREADY : STD_LOGIC;
signal axi_dma_3_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_3_M_AXI_S2MM_AWVALID : STD_LOGIC;
signal axi_dma_3_M_AXI_S2MM_BREADY : STD_LOGIC;
signal axi_dma_3_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_3_M_AXI_S2MM_BVALID : STD_LOGIC;
signal axi_dma_3_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_3_M_AXI_S2MM_WLAST : STD_LOGIC;
signal axi_dma_3_M_AXI_S2MM_WREADY : STD_LOGIC;
signal axi_dma_3_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_3_M_AXI_S2MM_WVALID : STD_LOGIC;
signal axi_dma_3_s2mm_introut : STD_LOGIC;
signal axi_dma_4_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_4_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_4_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_dma_4_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_4_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_4_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_4_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_4_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_4_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_4_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_4_M_AXI_MM2S_ARREADY : STD_LOGIC;
signal axi_dma_4_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_4_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_4_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_4_M_AXI_MM2S_RLAST : STD_LOGIC;
signal axi_dma_4_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_4_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_4_M_AXI_MM2S_RVALID : STD_LOGIC;
signal axi_dma_4_mm2s_introut : STD_LOGIC;
signal axi_dma_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_dma_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_M_AXI_MM2S_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_M_AXI_MM2S_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_M_AXI_MM2S_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_mm2s_introut : STD_LOGIC;
signal axi_gpio_0_GPIO_TRI_I : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_0_GPIO_TRI_O : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_0_GPIO_TRI_T : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_WID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
signal axis_data_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_data_fifo_0_M_AXIS_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axis_data_fifo_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_data_fifo_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_data_fifo_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_data_fifo_1_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_data_fifo_1_M_AXIS_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axis_data_fifo_1_M_AXIS_TLAST : STD_LOGIC;
signal axis_data_fifo_1_M_AXIS_TREADY : STD_LOGIC;
signal axis_data_fifo_1_M_AXIS_TVALID : STD_LOGIC;
signal axis_data_fifo_2_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_data_fifo_2_M_AXIS_TREADY : STD_LOGIC;
signal axis_data_fifo_2_M_AXIS_TVALID : STD_LOGIC;
signal axis_data_fifo_3_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_data_fifo_3_M_AXIS_TREADY : STD_LOGIC;
signal axis_data_fifo_3_M_AXIS_TVALID : STD_LOGIC;
signal axis_data_fifo_4_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_data_fifo_4_M_AXIS_TREADY : STD_LOGIC;
signal axis_data_fifo_4_M_AXIS_TVALID : STD_LOGIC;
signal feedforward_0_P_netOut_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal feedforward_0_P_netOut_TREADY : STD_LOGIC;
signal feedforward_0_P_netOut_TVALID : STD_LOGIC;
signal feedforward_0_P_uOut_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal feedforward_0_P_uOut_TREADY : STD_LOGIC;
signal feedforward_0_P_uOut_TVALID : STD_LOGIC;
signal feedforward_0_interrupt : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_WVALID : STD_LOGIC;
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_axi_dma_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_1_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_2_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_3_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_4_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axis_data_fifo_0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_1_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_1_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_1_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_2_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_axis_data_fifo_2_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_2_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_2_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_2_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_axis_data_fifo_3_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_axis_data_fifo_3_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_3_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_3_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_3_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_axis_data_fifo_4_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_axis_data_fifo_4_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_4_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_4_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_4_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
axi_gpio_0_GPIO_TRI_I(3 downto 0) <= leds_4bits_tri_i(3 downto 0);
leds_4bits_tri_o(3 downto 0) <= axi_gpio_0_GPIO_TRI_O(3 downto 0);
leds_4bits_tri_t(3 downto 0) <= axi_gpio_0_GPIO_TRI_T(3 downto 0);
axi_dma: component design_SWandHW_standalone_axi_dma_1
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_M_AXI_MM2S_ARREADY(0),
m_axi_mm2s_arsize(2 downto 0) => axi_dma_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_M_AXI_MM2S_RLAST(0),
m_axi_mm2s_rready => axi_dma_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_M_AXI_MM2S_RVALID(0),
m_axis_mm2s_tdata(31 downto 0) => axi_dma_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => axi_dma_M_AXIS_MM2S_TKEEP(3 downto 0),
m_axis_mm2s_tlast => axi_dma_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_dma_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_M_AXIS_MM2S_TVALID,
mm2s_introut => axi_dma_mm2s_introut,
mm2s_prmry_reset_out_n => NLW_axi_dma_mm2s_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
s_axi_lite_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID
);
axi_dma_1: component design_SWandHW_standalone_axi_dma_1_1
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0,
m_axi_s2mm_awaddr(31 downto 0) => axi_dma_1_M_AXI_S2MM_AWADDR(31 downto 0),
m_axi_s2mm_awburst(1 downto 0) => axi_dma_1_M_AXI_S2MM_AWBURST(1 downto 0),
m_axi_s2mm_awcache(3 downto 0) => axi_dma_1_M_AXI_S2MM_AWCACHE(3 downto 0),
m_axi_s2mm_awlen(7 downto 0) => axi_dma_1_M_AXI_S2MM_AWLEN(7 downto 0),
m_axi_s2mm_awprot(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWPROT(2 downto 0),
m_axi_s2mm_awready => axi_dma_1_M_AXI_S2MM_AWREADY,
m_axi_s2mm_awsize(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWSIZE(2 downto 0),
m_axi_s2mm_awvalid => axi_dma_1_M_AXI_S2MM_AWVALID,
m_axi_s2mm_bready => axi_dma_1_M_AXI_S2MM_BREADY,
m_axi_s2mm_bresp(1 downto 0) => axi_dma_1_M_AXI_S2MM_BRESP(1 downto 0),
m_axi_s2mm_bvalid => axi_dma_1_M_AXI_S2MM_BVALID,
m_axi_s2mm_wdata(31 downto 0) => axi_dma_1_M_AXI_S2MM_WDATA(31 downto 0),
m_axi_s2mm_wlast => axi_dma_1_M_AXI_S2MM_WLAST,
m_axi_s2mm_wready => axi_dma_1_M_AXI_S2MM_WREADY,
m_axi_s2mm_wstrb(3 downto 0) => axi_dma_1_M_AXI_S2MM_WSTRB(3 downto 0),
m_axi_s2mm_wvalid => axi_dma_1_M_AXI_S2MM_WVALID,
s2mm_introut => axi_dma_1_s2mm_introut,
s2mm_prmry_reset_out_n => NLW_axi_dma_1_s2mm_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M03_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M03_AXI_ARVALID,
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M03_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M03_AXI_AWVALID,
s_axi_lite_bready => processing_system7_0_axi_periph_M03_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M03_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M03_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M03_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M03_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID,
s_axis_s2mm_tdata(31 downto 0) => axis_data_fifo_1_M_AXIS_TDATA(31 downto 0),
s_axis_s2mm_tkeep(3 downto 0) => axis_data_fifo_1_M_AXIS_TKEEP(3 downto 0),
s_axis_s2mm_tlast => axis_data_fifo_1_M_AXIS_TLAST,
s_axis_s2mm_tready => axis_data_fifo_1_M_AXIS_TREADY,
s_axis_s2mm_tvalid => axis_data_fifo_1_M_AXIS_TVALID
);
axi_dma_2: component design_SWandHW_standalone_axi_dma_2_0
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_2_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_2_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_2_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_2_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_2_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_2_M_AXI_MM2S_ARREADY,
m_axi_mm2s_arsize(2 downto 0) => axi_dma_2_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_2_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_2_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_2_M_AXI_MM2S_RLAST,
m_axi_mm2s_rready => axi_dma_2_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_2_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_2_M_AXI_MM2S_RVALID,
m_axis_mm2s_tdata(31 downto 0) => axi_dma_2_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => axi_dma_2_M_AXIS_MM2S_TKEEP(3 downto 0),
m_axis_mm2s_tlast => axi_dma_2_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_dma_2_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_2_M_AXIS_MM2S_TVALID,
mm2s_introut => axi_dma_2_mm2s_introut,
mm2s_prmry_reset_out_n => NLW_axi_dma_2_mm2s_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M04_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M04_AXI_ARVALID,
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M04_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M04_AXI_AWVALID,
s_axi_lite_bready => processing_system7_0_axi_periph_M04_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M04_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M04_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M04_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M04_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M04_AXI_WVALID
);
axi_dma_3: component design_SWandHW_standalone_axi_dma_3_0
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0,
m_axi_s2mm_awaddr(31 downto 0) => axi_dma_3_M_AXI_S2MM_AWADDR(31 downto 0),
m_axi_s2mm_awburst(1 downto 0) => axi_dma_3_M_AXI_S2MM_AWBURST(1 downto 0),
m_axi_s2mm_awcache(3 downto 0) => axi_dma_3_M_AXI_S2MM_AWCACHE(3 downto 0),
m_axi_s2mm_awlen(7 downto 0) => axi_dma_3_M_AXI_S2MM_AWLEN(7 downto 0),
m_axi_s2mm_awprot(2 downto 0) => axi_dma_3_M_AXI_S2MM_AWPROT(2 downto 0),
m_axi_s2mm_awready => axi_dma_3_M_AXI_S2MM_AWREADY,
m_axi_s2mm_awsize(2 downto 0) => axi_dma_3_M_AXI_S2MM_AWSIZE(2 downto 0),
m_axi_s2mm_awvalid => axi_dma_3_M_AXI_S2MM_AWVALID,
m_axi_s2mm_bready => axi_dma_3_M_AXI_S2MM_BREADY,
m_axi_s2mm_bresp(1 downto 0) => axi_dma_3_M_AXI_S2MM_BRESP(1 downto 0),
m_axi_s2mm_bvalid => axi_dma_3_M_AXI_S2MM_BVALID,
m_axi_s2mm_wdata(31 downto 0) => axi_dma_3_M_AXI_S2MM_WDATA(31 downto 0),
m_axi_s2mm_wlast => axi_dma_3_M_AXI_S2MM_WLAST,
m_axi_s2mm_wready => axi_dma_3_M_AXI_S2MM_WREADY,
m_axi_s2mm_wstrb(3 downto 0) => axi_dma_3_M_AXI_S2MM_WSTRB(3 downto 0),
m_axi_s2mm_wvalid => axi_dma_3_M_AXI_S2MM_WVALID,
s2mm_introut => axi_dma_3_s2mm_introut,
s2mm_prmry_reset_out_n => NLW_axi_dma_3_s2mm_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M05_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M05_AXI_ARVALID,
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M05_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M05_AXI_AWVALID,
s_axi_lite_bready => processing_system7_0_axi_periph_M05_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M05_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M05_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M05_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M05_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M05_AXI_WVALID,
s_axis_s2mm_tdata(31 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(31 downto 0),
s_axis_s2mm_tkeep(3 downto 0) => axis_data_fifo_0_M_AXIS_TKEEP(3 downto 0),
s_axis_s2mm_tlast => axis_data_fifo_0_M_AXIS_TLAST,
s_axis_s2mm_tready => axis_data_fifo_0_M_AXIS_TREADY,
s_axis_s2mm_tvalid => axis_data_fifo_0_M_AXIS_TVALID
);
axi_dma_4: component design_SWandHW_standalone_axi_dma_4_0
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_4_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_4_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_4_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_4_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_4_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_4_M_AXI_MM2S_ARREADY,
m_axi_mm2s_arsize(2 downto 0) => axi_dma_4_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_4_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_4_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_4_M_AXI_MM2S_RLAST,
m_axi_mm2s_rready => axi_dma_4_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_4_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_4_M_AXI_MM2S_RVALID,
m_axis_mm2s_tdata(31 downto 0) => axi_dma_4_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => axi_dma_4_M_AXIS_MM2S_TKEEP(3 downto 0),
m_axis_mm2s_tlast => axi_dma_4_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_dma_4_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_4_M_AXIS_MM2S_TVALID,
mm2s_introut => axi_dma_4_mm2s_introut,
mm2s_prmry_reset_out_n => NLW_axi_dma_4_mm2s_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M06_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M06_AXI_ARVALID,
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M06_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M06_AXI_AWVALID,
s_axi_lite_bready => processing_system7_0_axi_periph_M06_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M06_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M06_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M06_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M06_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M06_AXI_WVALID
);
axi_gpio_0: component design_SWandHW_standalone_axi_gpio_0_0
port map (
gpio_io_i(3 downto 0) => axi_gpio_0_GPIO_TRI_I(3 downto 0),
gpio_io_o(3 downto 0) => axi_gpio_0_GPIO_TRI_O(3 downto 0),
gpio_io_t(3 downto 0) => axi_gpio_0_GPIO_TRI_T(3 downto 0),
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(8 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
s_axi_bready => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID(0)
);
axi_mem_intercon: entity work.design_SWandHW_standalone_axi_mem_intercon_1
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(2 downto 0) => axi_mem_intercon_M00_AXI_ARID(2 downto 0),
M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
M00_AXI_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(2 downto 0) => axi_mem_intercon_M00_AXI_AWID(2 downto 0),
M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
M00_AXI_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
M00_AXI_bid(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
M00_AXI_rid(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST,
M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
M00_AXI_wid(2 downto 0) => axi_mem_intercon_M00_AXI_WID(2 downto 0),
M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST,
M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => axi_dma_M_AXI_MM2S_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => axi_dma_M_AXI_MM2S_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => axi_dma_M_AXI_MM2S_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => axi_dma_M_AXI_MM2S_ARLEN(7 downto 0),
S00_AXI_arprot(2 downto 0) => axi_dma_M_AXI_MM2S_ARPROT(2 downto 0),
S00_AXI_arready(0) => axi_dma_M_AXI_MM2S_ARREADY(0),
S00_AXI_arsize(2 downto 0) => axi_dma_M_AXI_MM2S_ARSIZE(2 downto 0),
S00_AXI_arvalid(0) => axi_dma_M_AXI_MM2S_ARVALID,
S00_AXI_rdata(31 downto 0) => axi_dma_M_AXI_MM2S_RDATA(31 downto 0),
S00_AXI_rlast(0) => axi_dma_M_AXI_MM2S_RLAST(0),
S00_AXI_rready(0) => axi_dma_M_AXI_MM2S_RREADY,
S00_AXI_rresp(1 downto 0) => axi_dma_M_AXI_MM2S_RRESP(1 downto 0),
S00_AXI_rvalid(0) => axi_dma_M_AXI_MM2S_RVALID(0),
S01_ACLK => processing_system7_0_FCLK_CLK0,
S01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S01_AXI_awaddr(31 downto 0) => axi_dma_1_M_AXI_S2MM_AWADDR(31 downto 0),
S01_AXI_awburst(1 downto 0) => axi_dma_1_M_AXI_S2MM_AWBURST(1 downto 0),
S01_AXI_awcache(3 downto 0) => axi_dma_1_M_AXI_S2MM_AWCACHE(3 downto 0),
S01_AXI_awlen(7 downto 0) => axi_dma_1_M_AXI_S2MM_AWLEN(7 downto 0),
S01_AXI_awprot(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWPROT(2 downto 0),
S01_AXI_awready => axi_dma_1_M_AXI_S2MM_AWREADY,
S01_AXI_awsize(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWSIZE(2 downto 0),
S01_AXI_awvalid => axi_dma_1_M_AXI_S2MM_AWVALID,
S01_AXI_bready => axi_dma_1_M_AXI_S2MM_BREADY,
S01_AXI_bresp(1 downto 0) => axi_dma_1_M_AXI_S2MM_BRESP(1 downto 0),
S01_AXI_bvalid => axi_dma_1_M_AXI_S2MM_BVALID,
S01_AXI_wdata(31 downto 0) => axi_dma_1_M_AXI_S2MM_WDATA(31 downto 0),
S01_AXI_wlast => axi_dma_1_M_AXI_S2MM_WLAST,
S01_AXI_wready => axi_dma_1_M_AXI_S2MM_WREADY,
S01_AXI_wstrb(3 downto 0) => axi_dma_1_M_AXI_S2MM_WSTRB(3 downto 0),
S01_AXI_wvalid => axi_dma_1_M_AXI_S2MM_WVALID,
S02_ACLK => processing_system7_0_FCLK_CLK0,
S02_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S02_AXI_araddr(31 downto 0) => axi_dma_2_M_AXI_MM2S_ARADDR(31 downto 0),
S02_AXI_arburst(1 downto 0) => axi_dma_2_M_AXI_MM2S_ARBURST(1 downto 0),
S02_AXI_arcache(3 downto 0) => axi_dma_2_M_AXI_MM2S_ARCACHE(3 downto 0),
S02_AXI_arlen(7 downto 0) => axi_dma_2_M_AXI_MM2S_ARLEN(7 downto 0),
S02_AXI_arprot(2 downto 0) => axi_dma_2_M_AXI_MM2S_ARPROT(2 downto 0),
S02_AXI_arready => axi_dma_2_M_AXI_MM2S_ARREADY,
S02_AXI_arsize(2 downto 0) => axi_dma_2_M_AXI_MM2S_ARSIZE(2 downto 0),
S02_AXI_arvalid => axi_dma_2_M_AXI_MM2S_ARVALID,
S02_AXI_rdata(31 downto 0) => axi_dma_2_M_AXI_MM2S_RDATA(31 downto 0),
S02_AXI_rlast => axi_dma_2_M_AXI_MM2S_RLAST,
S02_AXI_rready => axi_dma_2_M_AXI_MM2S_RREADY,
S02_AXI_rresp(1 downto 0) => axi_dma_2_M_AXI_MM2S_RRESP(1 downto 0),
S02_AXI_rvalid => axi_dma_2_M_AXI_MM2S_RVALID,
S03_ACLK => processing_system7_0_FCLK_CLK0,
S03_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S03_AXI_awaddr(31 downto 0) => axi_dma_3_M_AXI_S2MM_AWADDR(31 downto 0),
S03_AXI_awburst(1 downto 0) => axi_dma_3_M_AXI_S2MM_AWBURST(1 downto 0),
S03_AXI_awcache(3 downto 0) => axi_dma_3_M_AXI_S2MM_AWCACHE(3 downto 0),
S03_AXI_awlen(7 downto 0) => axi_dma_3_M_AXI_S2MM_AWLEN(7 downto 0),
S03_AXI_awprot(2 downto 0) => axi_dma_3_M_AXI_S2MM_AWPROT(2 downto 0),
S03_AXI_awready => axi_dma_3_M_AXI_S2MM_AWREADY,
S03_AXI_awsize(2 downto 0) => axi_dma_3_M_AXI_S2MM_AWSIZE(2 downto 0),
S03_AXI_awvalid => axi_dma_3_M_AXI_S2MM_AWVALID,
S03_AXI_bready => axi_dma_3_M_AXI_S2MM_BREADY,
S03_AXI_bresp(1 downto 0) => axi_dma_3_M_AXI_S2MM_BRESP(1 downto 0),
S03_AXI_bvalid => axi_dma_3_M_AXI_S2MM_BVALID,
S03_AXI_wdata(31 downto 0) => axi_dma_3_M_AXI_S2MM_WDATA(31 downto 0),
S03_AXI_wlast => axi_dma_3_M_AXI_S2MM_WLAST,
S03_AXI_wready => axi_dma_3_M_AXI_S2MM_WREADY,
S03_AXI_wstrb(3 downto 0) => axi_dma_3_M_AXI_S2MM_WSTRB(3 downto 0),
S03_AXI_wvalid => axi_dma_3_M_AXI_S2MM_WVALID,
S04_ACLK => processing_system7_0_FCLK_CLK0,
S04_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S04_AXI_araddr(31 downto 0) => axi_dma_4_M_AXI_MM2S_ARADDR(31 downto 0),
S04_AXI_arburst(1 downto 0) => axi_dma_4_M_AXI_MM2S_ARBURST(1 downto 0),
S04_AXI_arcache(3 downto 0) => axi_dma_4_M_AXI_MM2S_ARCACHE(3 downto 0),
S04_AXI_arlen(7 downto 0) => axi_dma_4_M_AXI_MM2S_ARLEN(7 downto 0),
S04_AXI_arprot(2 downto 0) => axi_dma_4_M_AXI_MM2S_ARPROT(2 downto 0),
S04_AXI_arready => axi_dma_4_M_AXI_MM2S_ARREADY,
S04_AXI_arsize(2 downto 0) => axi_dma_4_M_AXI_MM2S_ARSIZE(2 downto 0),
S04_AXI_arvalid => axi_dma_4_M_AXI_MM2S_ARVALID,
S04_AXI_rdata(31 downto 0) => axi_dma_4_M_AXI_MM2S_RDATA(31 downto 0),
S04_AXI_rlast => axi_dma_4_M_AXI_MM2S_RLAST,
S04_AXI_rready => axi_dma_4_M_AXI_MM2S_RREADY,
S04_AXI_rresp(1 downto 0) => axi_dma_4_M_AXI_MM2S_RRESP(1 downto 0),
S04_AXI_rvalid => axi_dma_4_M_AXI_MM2S_RVALID
);
axis_data_fifo_0: component design_SWandHW_standalone_axis_data_fifo_0_0
port map (
axis_data_count(31 downto 0) => NLW_axis_data_fifo_0_axis_data_count_UNCONNECTED(31 downto 0),
axis_rd_data_count(31 downto 0) => NLW_axis_data_fifo_0_axis_rd_data_count_UNCONNECTED(31 downto 0),
axis_wr_data_count(31 downto 0) => NLW_axis_data_fifo_0_axis_wr_data_count_UNCONNECTED(31 downto 0),
m_axis_tdata(31 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(31 downto 0),
m_axis_tkeep(3 downto 0) => axis_data_fifo_0_M_AXIS_TKEEP(3 downto 0),
m_axis_tlast => axis_data_fifo_0_M_AXIS_TLAST,
m_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
m_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID,
s_axis_aclk => processing_system7_0_FCLK_CLK0,
s_axis_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axis_tdata(31 downto 0) => feedforward_0_P_uOut_TDATA(31 downto 0),
s_axis_tkeep(3 downto 0) => B"1111",
s_axis_tlast => '1',
s_axis_tready => feedforward_0_P_uOut_TREADY,
s_axis_tvalid => feedforward_0_P_uOut_TVALID
);
axis_data_fifo_1: component design_SWandHW_standalone_axis_data_fifo_1_0
port map (
axis_data_count(31 downto 0) => NLW_axis_data_fifo_1_axis_data_count_UNCONNECTED(31 downto 0),
axis_rd_data_count(31 downto 0) => NLW_axis_data_fifo_1_axis_rd_data_count_UNCONNECTED(31 downto 0),
axis_wr_data_count(31 downto 0) => NLW_axis_data_fifo_1_axis_wr_data_count_UNCONNECTED(31 downto 0),
m_axis_tdata(31 downto 0) => axis_data_fifo_1_M_AXIS_TDATA(31 downto 0),
m_axis_tkeep(3 downto 0) => axis_data_fifo_1_M_AXIS_TKEEP(3 downto 0),
m_axis_tlast => axis_data_fifo_1_M_AXIS_TLAST,
m_axis_tready => axis_data_fifo_1_M_AXIS_TREADY,
m_axis_tvalid => axis_data_fifo_1_M_AXIS_TVALID,
s_axis_aclk => processing_system7_0_FCLK_CLK0,
s_axis_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axis_tdata(31 downto 0) => feedforward_0_P_netOut_TDATA(31 downto 0),
s_axis_tkeep(3 downto 0) => B"1111",
s_axis_tlast => '1',
s_axis_tready => feedforward_0_P_netOut_TREADY,
s_axis_tvalid => feedforward_0_P_netOut_TVALID
);
axis_data_fifo_2: component design_SWandHW_standalone_axis_data_fifo_2_0
port map (
axis_data_count(31 downto 0) => NLW_axis_data_fifo_2_axis_data_count_UNCONNECTED(31 downto 0),
axis_rd_data_count(31 downto 0) => NLW_axis_data_fifo_2_axis_rd_data_count_UNCONNECTED(31 downto 0),
axis_wr_data_count(31 downto 0) => NLW_axis_data_fifo_2_axis_wr_data_count_UNCONNECTED(31 downto 0),
m_axis_tdata(31 downto 0) => axis_data_fifo_2_M_AXIS_TDATA(31 downto 0),
m_axis_tkeep(3 downto 0) => NLW_axis_data_fifo_2_m_axis_tkeep_UNCONNECTED(3 downto 0),
m_axis_tlast => NLW_axis_data_fifo_2_m_axis_tlast_UNCONNECTED,
m_axis_tready => axis_data_fifo_2_M_AXIS_TREADY,
m_axis_tvalid => axis_data_fifo_2_M_AXIS_TVALID,
s_axis_aclk => processing_system7_0_FCLK_CLK0,
s_axis_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axis_tdata(31 downto 0) => axi_dma_2_M_AXIS_MM2S_TDATA(31 downto 0),
s_axis_tkeep(3 downto 0) => axi_dma_2_M_AXIS_MM2S_TKEEP(3 downto 0),
s_axis_tlast => axi_dma_2_M_AXIS_MM2S_TLAST,
s_axis_tready => axi_dma_2_M_AXIS_MM2S_TREADY,
s_axis_tvalid => axi_dma_2_M_AXIS_MM2S_TVALID
);
axis_data_fifo_3: component design_SWandHW_standalone_axis_data_fifo_3_0
port map (
axis_data_count(31 downto 0) => NLW_axis_data_fifo_3_axis_data_count_UNCONNECTED(31 downto 0),
axis_rd_data_count(31 downto 0) => NLW_axis_data_fifo_3_axis_rd_data_count_UNCONNECTED(31 downto 0),
axis_wr_data_count(31 downto 0) => NLW_axis_data_fifo_3_axis_wr_data_count_UNCONNECTED(31 downto 0),
m_axis_tdata(31 downto 0) => axis_data_fifo_3_M_AXIS_TDATA(31 downto 0),
m_axis_tkeep(3 downto 0) => NLW_axis_data_fifo_3_m_axis_tkeep_UNCONNECTED(3 downto 0),
m_axis_tlast => NLW_axis_data_fifo_3_m_axis_tlast_UNCONNECTED,
m_axis_tready => axis_data_fifo_3_M_AXIS_TREADY,
m_axis_tvalid => axis_data_fifo_3_M_AXIS_TVALID,
s_axis_aclk => processing_system7_0_FCLK_CLK0,
s_axis_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axis_tdata(31 downto 0) => axi_dma_4_M_AXIS_MM2S_TDATA(31 downto 0),
s_axis_tkeep(3 downto 0) => axi_dma_4_M_AXIS_MM2S_TKEEP(3 downto 0),
s_axis_tlast => axi_dma_4_M_AXIS_MM2S_TLAST,
s_axis_tready => axi_dma_4_M_AXIS_MM2S_TREADY,
s_axis_tvalid => axi_dma_4_M_AXIS_MM2S_TVALID
);
axis_data_fifo_4: component design_SWandHW_standalone_axis_data_fifo_4_0
port map (
axis_data_count(31 downto 0) => NLW_axis_data_fifo_4_axis_data_count_UNCONNECTED(31 downto 0),
axis_rd_data_count(31 downto 0) => NLW_axis_data_fifo_4_axis_rd_data_count_UNCONNECTED(31 downto 0),
axis_wr_data_count(31 downto 0) => NLW_axis_data_fifo_4_axis_wr_data_count_UNCONNECTED(31 downto 0),
m_axis_tdata(31 downto 0) => axis_data_fifo_4_M_AXIS_TDATA(31 downto 0),
m_axis_tkeep(3 downto 0) => NLW_axis_data_fifo_4_m_axis_tkeep_UNCONNECTED(3 downto 0),
m_axis_tlast => NLW_axis_data_fifo_4_m_axis_tlast_UNCONNECTED,
m_axis_tready => axis_data_fifo_4_M_AXIS_TREADY,
m_axis_tvalid => axis_data_fifo_4_M_AXIS_TVALID,
s_axis_aclk => processing_system7_0_FCLK_CLK0,
s_axis_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axis_tdata(31 downto 0) => axi_dma_M_AXIS_MM2S_TDATA(31 downto 0),
s_axis_tkeep(3 downto 0) => axi_dma_M_AXIS_MM2S_TKEEP(3 downto 0),
s_axis_tlast => axi_dma_M_AXIS_MM2S_TLAST,
s_axis_tready => axi_dma_M_AXIS_MM2S_TREADY,
s_axis_tvalid => axi_dma_M_AXIS_MM2S_TVALID
);
feedforward_0: component design_SWandHW_standalone_feedforward_0_0
port map (
P_WandB_TDATA(31 downto 0) => axis_data_fifo_3_M_AXIS_TDATA(31 downto 0),
P_WandB_TREADY => axis_data_fifo_3_M_AXIS_TREADY,
P_WandB_TVALID => axis_data_fifo_3_M_AXIS_TVALID,
P_config_TDATA(31 downto 0) => axis_data_fifo_2_M_AXIS_TDATA(31 downto 0),
P_config_TREADY => axis_data_fifo_2_M_AXIS_TREADY,
P_config_TVALID => axis_data_fifo_2_M_AXIS_TVALID,
P_netIn_TDATA(31 downto 0) => axis_data_fifo_4_M_AXIS_TDATA(31 downto 0),
P_netIn_TREADY => axis_data_fifo_4_M_AXIS_TREADY,
P_netIn_TVALID => axis_data_fifo_4_M_AXIS_TVALID,
P_netOut_TDATA(31 downto 0) => feedforward_0_P_netOut_TDATA(31 downto 0),
P_netOut_TREADY => feedforward_0_P_netOut_TREADY,
P_netOut_TVALID => feedforward_0_P_netOut_TVALID,
P_uOut_TDATA(31 downto 0) => feedforward_0_P_uOut_TDATA(31 downto 0),
P_uOut_TREADY => feedforward_0_P_uOut_TREADY,
P_uOut_TVALID => feedforward_0_P_uOut_TVALID,
ap_clk => processing_system7_0_FCLK_CLK0,
ap_rst_n => rst_processing_system7_0_100M_peripheral_aresetn(0),
interrupt => feedforward_0_interrupt,
s_axi_AXILiteS_ARADDR(4 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(4 downto 0),
s_axi_AXILiteS_ARREADY => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s_axi_AXILiteS_ARVALID => processing_system7_0_axi_periph_M01_AXI_ARVALID,
s_axi_AXILiteS_AWADDR(4 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(4 downto 0),
s_axi_AXILiteS_AWREADY => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s_axi_AXILiteS_AWVALID => processing_system7_0_axi_periph_M01_AXI_AWVALID,
s_axi_AXILiteS_BREADY => processing_system7_0_axi_periph_M01_AXI_BREADY,
s_axi_AXILiteS_BRESP(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_AXILiteS_BVALID => processing_system7_0_axi_periph_M01_AXI_BVALID,
s_axi_AXILiteS_RDATA(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_AXILiteS_RREADY => processing_system7_0_axi_periph_M01_AXI_RREADY,
s_axi_AXILiteS_RRESP(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_AXILiteS_RVALID => processing_system7_0_axi_periph_M01_AXI_RVALID,
s_axi_AXILiteS_WDATA(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_AXILiteS_WREADY => processing_system7_0_axi_periph_M01_AXI_WREADY,
s_axi_AXILiteS_WSTRB(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_AXILiteS_WVALID => processing_system7_0_axi_periph_M01_AXI_WVALID
);
processing_system7_0: component design_SWandHW_standalone_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
IRQ_F2P(5 downto 0) => xlconcat_0_dout(5 downto 0),
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SDIO0_WP => '0',
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_HP0_ARADDR(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
S_AXI_HP0_ARBURST(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
S_AXI_HP0_ARCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
S_AXI_HP0_ARID(5 downto 3) => B"000",
S_AXI_HP0_ARID(2 downto 0) => axi_mem_intercon_M00_AXI_ARID(2 downto 0),
S_AXI_HP0_ARLEN(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
S_AXI_HP0_ARLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
S_AXI_HP0_ARPROT(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
S_AXI_HP0_ARQOS(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
S_AXI_HP0_ARREADY => axi_mem_intercon_M00_AXI_ARREADY,
S_AXI_HP0_ARSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
S_AXI_HP0_ARVALID => axi_mem_intercon_M00_AXI_ARVALID,
S_AXI_HP0_AWADDR(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
S_AXI_HP0_AWBURST(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
S_AXI_HP0_AWCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
S_AXI_HP0_AWID(5 downto 3) => B"000",
S_AXI_HP0_AWID(2 downto 0) => axi_mem_intercon_M00_AXI_AWID(2 downto 0),
S_AXI_HP0_AWLEN(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
S_AXI_HP0_AWLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
S_AXI_HP0_AWPROT(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
S_AXI_HP0_AWQOS(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
S_AXI_HP0_AWREADY => axi_mem_intercon_M00_AXI_AWREADY,
S_AXI_HP0_AWSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
S_AXI_HP0_AWVALID => axi_mem_intercon_M00_AXI_AWVALID,
S_AXI_HP0_BID(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
S_AXI_HP0_BREADY => axi_mem_intercon_M00_AXI_BREADY,
S_AXI_HP0_BRESP(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
S_AXI_HP0_BVALID => axi_mem_intercon_M00_AXI_BVALID,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
S_AXI_HP0_RLAST => axi_mem_intercon_M00_AXI_RLAST,
S_AXI_HP0_RREADY => axi_mem_intercon_M00_AXI_RREADY,
S_AXI_HP0_RRESP(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
S_AXI_HP0_RVALID => axi_mem_intercon_M00_AXI_RVALID,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
S_AXI_HP0_WID(5 downto 3) => B"000",
S_AXI_HP0_WID(2 downto 0) => axi_mem_intercon_M00_AXI_WID(2 downto 0),
S_AXI_HP0_WLAST => axi_mem_intercon_M00_AXI_WLAST,
S_AXI_HP0_WREADY => axi_mem_intercon_M00_AXI_WREADY,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
S_AXI_HP0_WVALID => axi_mem_intercon_M00_AXI_WVALID,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.design_SWandHW_standalone_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready(0) => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready(0) => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => processing_system7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID,
M01_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID,
M01_AXI_bready => processing_system7_0_axi_periph_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => processing_system7_0_axi_periph_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID,
M02_ACLK => processing_system7_0_FCLK_CLK0,
M02_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M02_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
M02_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
M02_AXI_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID,
M03_ACLK => processing_system7_0_FCLK_CLK0,
M03_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M03_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arready => processing_system7_0_axi_periph_M03_AXI_ARREADY,
M03_AXI_arvalid => processing_system7_0_axi_periph_M03_AXI_ARVALID,
M03_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awready => processing_system7_0_axi_periph_M03_AXI_AWREADY,
M03_AXI_awvalid => processing_system7_0_axi_periph_M03_AXI_AWVALID,
M03_AXI_bready => processing_system7_0_axi_periph_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => processing_system7_0_axi_periph_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => processing_system7_0_axi_periph_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => processing_system7_0_axi_periph_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => processing_system7_0_axi_periph_M03_AXI_WREADY,
M03_AXI_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID,
M04_ACLK => processing_system7_0_FCLK_CLK0,
M04_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M04_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARADDR(31 downto 0),
M04_AXI_arready => processing_system7_0_axi_periph_M04_AXI_ARREADY,
M04_AXI_arvalid => processing_system7_0_axi_periph_M04_AXI_ARVALID,
M04_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWADDR(31 downto 0),
M04_AXI_awready => processing_system7_0_axi_periph_M04_AXI_AWREADY,
M04_AXI_awvalid => processing_system7_0_axi_periph_M04_AXI_AWVALID,
M04_AXI_bready => processing_system7_0_axi_periph_M04_AXI_BREADY,
M04_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid => processing_system7_0_axi_periph_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready => processing_system7_0_axi_periph_M04_AXI_RREADY,
M04_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid => processing_system7_0_axi_periph_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready => processing_system7_0_axi_periph_M04_AXI_WREADY,
M04_AXI_wvalid => processing_system7_0_axi_periph_M04_AXI_WVALID,
M05_ACLK => processing_system7_0_FCLK_CLK0,
M05_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M05_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARADDR(31 downto 0),
M05_AXI_arready => processing_system7_0_axi_periph_M05_AXI_ARREADY,
M05_AXI_arvalid => processing_system7_0_axi_periph_M05_AXI_ARVALID,
M05_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWADDR(31 downto 0),
M05_AXI_awready => processing_system7_0_axi_periph_M05_AXI_AWREADY,
M05_AXI_awvalid => processing_system7_0_axi_periph_M05_AXI_AWVALID,
M05_AXI_bready => processing_system7_0_axi_periph_M05_AXI_BREADY,
M05_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_BRESP(1 downto 0),
M05_AXI_bvalid => processing_system7_0_axi_periph_M05_AXI_BVALID,
M05_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_RDATA(31 downto 0),
M05_AXI_rready => processing_system7_0_axi_periph_M05_AXI_RREADY,
M05_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_RRESP(1 downto 0),
M05_AXI_rvalid => processing_system7_0_axi_periph_M05_AXI_RVALID,
M05_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_WDATA(31 downto 0),
M05_AXI_wready => processing_system7_0_axi_periph_M05_AXI_WREADY,
M05_AXI_wvalid => processing_system7_0_axi_periph_M05_AXI_WVALID,
M06_ACLK => processing_system7_0_FCLK_CLK0,
M06_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M06_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARADDR(31 downto 0),
M06_AXI_arready => processing_system7_0_axi_periph_M06_AXI_ARREADY,
M06_AXI_arvalid => processing_system7_0_axi_periph_M06_AXI_ARVALID,
M06_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWADDR(31 downto 0),
M06_AXI_awready => processing_system7_0_axi_periph_M06_AXI_AWREADY,
M06_AXI_awvalid => processing_system7_0_axi_periph_M06_AXI_AWVALID,
M06_AXI_bready => processing_system7_0_axi_periph_M06_AXI_BREADY,
M06_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_BRESP(1 downto 0),
M06_AXI_bvalid => processing_system7_0_axi_periph_M06_AXI_BVALID,
M06_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_RDATA(31 downto 0),
M06_AXI_rready => processing_system7_0_axi_periph_M06_AXI_RREADY,
M06_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_RRESP(1 downto 0),
M06_AXI_rvalid => processing_system7_0_axi_periph_M06_AXI_RVALID,
M06_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_WDATA(31 downto 0),
M06_AXI_wready => processing_system7_0_axi_periph_M06_AXI_WREADY,
M06_AXI_wvalid => processing_system7_0_axi_periph_M06_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_100M: component design_SWandHW_standalone_rst_processing_system7_0_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
xlconcat_0: component design_SWandHW_standalone_xlconcat_0_0
port map (
In0(0) => feedforward_0_interrupt,
In1(0) => axi_dma_mm2s_introut,
In2(0) => axi_dma_1_s2mm_introut,
In3(0) => axi_dma_2_mm2s_introut,
In4(0) => axi_dma_3_s2mm_introut,
In5(0) => axi_dma_4_mm2s_introut,
dout(5 downto 0) => xlconcat_0_dout(5 downto 0)
);
end STRUCTURE;
| gpl-3.0 | 80d5a1ce46b0ee9720906bfe615b121c | 0.682122 | 2.800487 | false | false | false | false |
Cpt-Quantum/VHDL | FPGA_Intro/Switches_LEDS_OwnBoards.vhd | 1 | 2,199 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19.08.2016 14:48:09
-- Design Name:
-- Module Name: Switches_LEDS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Switches_LEDS is
Port ( Switch : in STD_LOGIC_VECTOR(7 downto 0);
LED : out STD_LOGIC_VECTOR(7 downto 0)
);
end Switches_LEDS;
architecture Behavioral of Switches_LEDS is
signal number_1 : STD_LOGIC_VECTOR(3 downto 0);
signal number_2 : STD_LOGIC_VECTOR(3 downto 0);
signal carry : STD_LOGIC_VECTOR(3 downto 0);
signal result : STD_LOGIC_VECTOR(7 downto 0);
begin
-- Define addition operation
result(0) <= number_1(0) XOR number_2(0);
carry(0) <= number_1(0) AND number_2(0);
result(1) <= number_1(1) XOR number_2(1) XOR carry(0);
carry(1) <= (number_1(1) AND number_2(1)) OR (number_1(1) AND carry(0)) OR (number_2(1) AND carry(0));
result(2) <= number_1(2) XOR number_2(2) XOR carry(1);
carry(2) <= (number_1(2) AND number_2(2)) OR (number_1(2) AND carry(1)) OR (number_2(2) AND carry(1));
result(3) <= number_1(3) XOR number_2(3) XOR carry(2);
carry(3) <= (number_1(3) AND number_2(3)) OR (number_1(3) AND carry(2)) OR (number_2(3) AND carry(2));
result(4) <= carry(3);
-- Assign the two 4-bit numbers
number_1 <= Switch(3 downto 0);
number_2 <= Switch(7 downto 4);
-- Fill in empty part of the result vector
result(7 downto 5) <= "000";
-- Assign the result to the LEDs
LED <= result(7 downto 0);
end Behavioral;
| mit | 805da6129418caded3fffa856803684a | 0.580264 | 3.430577 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_dexp_64ns_64ns_64_18_full_dsp.vhd | 4 | 2,809 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dexp_64ns_64ns_64_18_full_dsp is
generic (
ID : integer := 8;
NUM_STAGE : integer := 18;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dexp_64ns_64ns_64_18_full_dsp is
--------------------- Component ---------------------
component feedforward_ap_dexp_16_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dexp_16_full_dsp_64_u : component feedforward_ap_dexp_16_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | ea1dd7a4f6e6ef792b1b5df02a425ba9 | 0.482378 | 3.7107 | false | false | false | false |
Rookfighter/aes-ss17 | ex01/freq_controller.vhd | 1 | 3,567 | -- freq_controller.vhd
--
-- Created on: 12 May 2017
-- Author: Fabian Meyer
--
-- Component that allows to set blinking frequency from user input (buttons).
-- Uses sync_buffer component to debounce buttons signals. Button signals
-- are sampled with ~732Hz (24MHz / 2**15).
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity freq_controller is
generic(RSTDEF: std_logic := '1');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
btn0: in std_logic; -- increment button, low active
btn1: in std_logic; -- decrement button, low active
freq: out std_logic_vector(2 downto 0)); -- frequency, 000 = stop, 111 = fast
end entity freq_controller;
architecture behavioral of freq_controller is
-- debounce buffer component for buttons
component sync_buffer is
generic(RSTDEF: std_logic);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
en: in std_logic; -- enable, high active
din: in std_logic; -- data bit, input
dout: out std_logic; -- data bit, output
redge: out std_logic; -- rising edge on din detected
fedge: out std_logic); -- falling edge on din detected
end component;
-- frequency divider by 2**CNTLEN
constant CNTLEN: natural := 15;
signal cnt: std_logic_vector(CNTLEN-1 downto 0) := (others => '0');
signal cnt_tmp: std_logic_vector(CNTLEN downto 0) := (others => '0');
signal cnt_en: std_logic := '0';
-- if set, increment frequency
signal inc: std_logic := '0';
-- if set, decrement frequency
signal dec: std_logic := '0';
-- signal for internal freq computation
signal freq_tmp: std_logic_vector(2 downto 0) :=(others => '0');
begin
-- carry bit defines enable for sync_buffers
cnt_en <= cnt_tmp(CNTLEN);
cnt <= cnt_tmp(CNTLEN-1 downto 0);
-- connect freq out port with internal freq_tmp
freq <= freq_tmp;
process(rst, clk)
begin
if rst = RSTDEF then
cnt_tmp <= (others => '0');
freq_tmp <= (others => '0');
elsif rising_edge(clk) then
-- increment frequency divider
cnt_tmp <= '0' & cnt + 1;
if inc = '1' then
-- increment frequency, overflow not handled
-- just start at 0 again
freq_tmp <= freq_tmp + 1;
elsif dec = '1' then
-- decrement frequency, overflow not handled
-- just start at full freq again
freq_tmp <= freq_tmp - 1;
end if;
end if;
end process;
-- map rising edge (release button) of btn0 to inc
-- connect frequency divider carry to enable
sbuf0: sync_buffer
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
en => cnt_en,
din => btn0,
dout => open,
redge => inc,
fedge => open);
-- map rising edge (release button) of btn1 to dec
-- connect frequency divider carry to enable
sbuf1: sync_buffer
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
en => cnt_en,
din => btn1,
dout => open,
redge => dec,
fedge => open);
end architecture behavioral;
| gpl-3.0 | 65f6cf71605e501c599d9e60a6ac67c8 | 0.552846 | 4.044218 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_axi_gpio_0_0/synth/design_SWandHW_standalone_axi_gpio_0_0.vhd | 1 | 10,202 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_9;
USE axi_gpio_v2_0_9.axi_gpio;
ENTITY design_SWandHW_standalone_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END design_SWandHW_standalone_axi_gpio_0_0;
ARCHITECTURE design_SWandHW_standalone_axi_gpio_0_0_arch OF design_SWandHW_standalone_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_axi_gpio_0_0_arch : ARCHITECTURE IS "design_SWandHW_standalone_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SWandHW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "design_SWandHW_standalone_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_SWandHW_standalone_axi_gpio_0_0_arch;
| gpl-3.0 | 2baf8fea44aca6383d0362b305d760a5 | 0.691041 | 3.185139 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_mul_mul_7ns_14s_14_1.vhd | 7 | 1,533 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ANN_mul_mul_7ns_14s_14_1_DSP48_0 is
port (
a: in std_logic_vector(7 - 1 downto 0);
b: in std_logic_vector(14 - 1 downto 0);
p: out std_logic_vector(14 - 1 downto 0));
end entity;
architecture behav of ANN_mul_mul_7ns_14s_14_1_DSP48_0 is
signal a_cvt: unsigned(7 - 1 downto 0);
signal b_cvt: signed(14 - 1 downto 0);
signal p_cvt: signed(14 - 1 downto 0);
begin
a_cvt <= unsigned(a);
b_cvt <= signed(b);
p_cvt <= signed (resize(unsigned (signed ('0' & a_cvt) * signed (b_cvt)), 14));
p <= std_logic_vector(p_cvt);
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity ANN_mul_mul_7ns_14s_14_1 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of ANN_mul_mul_7ns_14s_14_1 is
component ANN_mul_mul_7ns_14s_14_1_DSP48_0 is
port (
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
ANN_mul_mul_7ns_14s_14_1_DSP48_0_U : component ANN_mul_mul_7ns_14s_14_1_DSP48_0
port map (
a => din0,
b => din1,
p => dout);
end architecture;
| gpl-3.0 | f055d70d06d424442a3318f90bfb3d63 | 0.598174 | 2.849442 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_ST_uOut.vhd | 7 | 4,489 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ANN_ST_uOut_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 8;
mem_size : integer := 160
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
d1 : in std_logic_vector(dwidth-1 downto 0);
we1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of ANN_ST_uOut_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
if (we1 = '1') then
ram(CONV_INTEGER(addr1_tmp)) := d1;
end if;
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity ANN_ST_uOut is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 160;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of ANN_ST_uOut is
component ANN_ST_uOut_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR;
we1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
ANN_ST_uOut_ram_U : component ANN_ST_uOut_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
d1 => d1,
we1 => we1,
q1 => q1);
end architecture;
| gpl-3.0 | bb48fbe6c210c86ac7d8a19c48438ff0 | 0.529071 | 3.469088 | false | false | false | false |
bonfireprocessor/bonfire-soc | obsolete/toplevel.vhd | 1 | 9,445 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:39:44 09/04/2016
-- Design Name:
-- Module Name: toplevel - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity toplevel is
generic (
-- generics are set by the simulator only, when instaniating from a testbench
-- when Design is physically build than the defaults are used
RamFileName : string := ""; -- only used when UseBRAMPrimitives is false
mode : string := "H"; -- only used when UseBRAMPrimitives is false
Swapbytes : boolean := true -- SWAP Bytes in RAM word in low byte first order to use data2mem
);
port(
sysclk_32m : in std_logic;
I_RESET : in std_logic;
-- GPIOs:
-- 4x LEDs
leds : out std_logic_vector(3 downto 0);
-- UART0 signals:
uart0_txd : out std_logic;
uart0_rxd : in std_logic :='1';
-- LED on Papilio Pro Board
led1 : out std_logic
-- UART1 signals:
--uart1_txd : out std_logic;
--uart1_rxd : in std_logic
);
end toplevel;
architecture Behavioral of toplevel is
constant ram_adr_width : natural := 12;
constant ram_size : natural := 4096;
signal clk32Mhz, -- buffered osc clock
clk : std_logic; -- logical CPU clock
signal reset,res1 : std_logic;
-- Instruction Bus
signal ib_data : std_logic_vector(31 downto 0);
signal ib_busy,ib_rden : std_logic;
signal ib_adr : std_logic_vector(29 downto 0);
-- Data Bus Master
signal dbus_cyc_o : std_logic;
signal dbus_stb_o : std_logic;
signal dbus_we_o : std_logic;
signal dbus_sel_o : std_logic_vector(3 downto 0);
signal dbus_adr_o : std_logic_vector(31 downto 2);
signal dbus_dat_o : std_logic_vector(31 downto 0);
signal dbus_ack_i : std_logic;
signal dbus_dat_i : std_logic_vector(31 downto 0);
-- Slaves
constant slave_adr_high : natural := 27;
-- Memory bus
signal mem_cyc,mem_stb,mem_we,mem_ack : std_logic;
signal mem_sel : std_logic_vector(3 downto 0);
signal mem_dat_rd,mem_dat_wr : std_logic_vector(31 downto 0);
signal mem_adr : std_logic_vector(27 downto 2);
-- Memory 2 bus
signal mem2_cyc,mem2_stb,mem2_we,mem2_ack : std_logic;
signal mem2_sel : std_logic_vector(3 downto 0);
signal mem2_dat_rd,mem2_dat_wr : std_logic_vector(31 downto 0);
signal mem2_adr : std_logic_vector(27 downto 2);
-- gpio bus
signal gpio_cyc,gpio_stb,gpio_we,gpio_ack : std_logic;
signal gpio_sel : std_logic_vector(3 downto 0);
signal gpio_dat_rd,gpio_dat_wr : std_logic_vector(31 downto 0);
signal gpio_adr : std_logic_vector(27 downto 2);
-- lpc bus
signal lpc_cyc,lpc_stb,lpc_stb0, lpc_we,lpc_ack : std_logic;
signal lpc_sel : std_logic_vector(3 downto 0);
signal lpc_dat_rd,lpc_dat_wr : std_logic_vector(31 downto 0);
signal lpc_adr : std_logic_vector(27 downto 2);
signal lpcio_adr : std_logic_vector(27 downto 0);
signal lpc_dat_rd8, lpc_dat_wr8 : std_logic_vector(7 downto 0);
-- lpc slaves
-- uart bus
signal uart_cyc,uart_stb,uart_we,uart_ack : std_logic;
signal uart_sel : std_logic_vector(3 downto 0);
signal uart_dat_rd,uart_dat_wr : std_logic_vector(7 downto 0);
signal uart_adr : std_logic_vector(7 downto 0);
signal irq_i : std_logic_vector(7 downto 0);
begin
irq_i <= (others=>'0'); -- currently no interrupts
led1<='1';
Inst_lxp32u_top: entity work.lxp32u_top
generic map (
USE_RISCV => true,
MUL_ARCH => "spartandsp",
REG_RAM_STYLE => "block"
)
PORT MAP(
clk_i => clk,
rst_i => reset,
lli_re_o => ib_rden,
lli_adr_o =>ib_adr ,
lli_dat_i => ib_data,
lli_busy_i => ib_busy,
dbus_cyc_o => dbus_cyc_o,
dbus_stb_o => dbus_stb_o,
dbus_we_o => dbus_we_o,
dbus_sel_o => dbus_sel_o,
dbus_ack_i => dbus_ack_i,
dbus_adr_o => dbus_adr_o,
dbus_dat_o => dbus_dat_o,
dbus_dat_i => dbus_dat_i,
irq_i => irq_i
);
Firmware: entity work.memory_interface
GENERIC MAP (
ram_adr_width => ram_adr_width,
ram_size => ram_size,
RamFileName => RamFileName,
mode => mode,
Swapbytes => Swapbytes
)
PORT MAP(
clk_i =>clk ,
rst_i => reset,
wbs_cyc_i => mem_cyc,
wbs_stb_i => mem_stb,
wbs_we_i => mem_we,
wbs_sel_i => mem_sel,
wbs_ack_o => mem_ack,
wbs_adr_i => mem_adr,
wbs_dat_i => mem_dat_wr,
wbs_dat_o => mem_dat_rd,
lli_re_i => ib_rden,
lli_adr_i => ib_adr,
lli_dat_o => ib_data,
lli_busy_o => ib_busy
);
BRAM: entity work.memory_interface
GENERIC MAP (
ram_adr_width => ram_adr_width,
ram_size => ram_size,
RamFileName => RamFileName,
mode => mode
)
PORT MAP(
clk_i =>clk ,
rst_i => reset,
wbs_cyc_i => mem2_cyc,
wbs_stb_i => mem2_stb,
wbs_we_i => mem2_we,
wbs_sel_i => mem2_sel,
wbs_ack_o => mem2_ack,
wbs_adr_i => mem2_adr,
wbs_dat_i => mem2_dat_wr,
wbs_dat_o => mem2_dat_rd,
lli_re_i => '0',
lli_adr_i => ib_adr,
lli_dat_o => open,
lli_busy_o => open
);
Inst_gpio: entity work.gpio PORT MAP(
leds => leds ,
clk_i =>clk ,
rst_i => reset,
wbs_cyc_i => gpio_cyc ,
wbs_stb_i => gpio_stb,
wbs_we_i => gpio_we,
wbs_sel_i => gpio_sel,
wbs_ack_o => gpio_ack,
wbs_adr_i => gpio_adr,
wbs_dat_i => gpio_dat_wr,
wbs_dat_o => gpio_dat_rd
);
lpc_dat_wr8<= lpc_dat_wr(7 downto 0);
lpc_dat_rd<= X"000000"&lpc_dat_rd8;
-- extend Adress bus with lower two bits
process(lpc_adr,lpc_sel)
variable lowadr : std_logic_vector( 1 downto 0);
begin
case lpc_sel is
when "0001" => lowadr:="00";
when "0010" =>lowadr:="01";
when "0100"=>lowadr:="10";
when "1000"=>lowadr:="11";
when others => lowadr:="00";
end case;
lpcio_adr<=lpc_adr & lowadr;
end process;
inst_lpcbus: entity work.lpcbus PORT MAP(
clk_i => clk,
rst_i => reset,
s0_cyc_i => lpc_cyc,
s0_stb_i => lpc_stb,
s0_we_i => lpc_we,
s0_ack_o => lpc_ack,
s0_adr_i => lpcio_adr,
s0_dat_i => lpc_dat_wr8,
s0_dat_o => lpc_dat_rd8,
m0_cyc_o => uart_cyc,
m0_stb_o => uart_stb,
m0_we_o => uart_we,
m0_ack_i => uart_ack,
m0_adr_o => uart_adr,
m0_dat_o => uart_dat_wr ,
m0_dat_i => uart_dat_rd
);
inst_uart: entity work.pp_soc_uart PORT MAP(
clk =>clk ,
reset => reset,
txd => uart0_txd,
rxd => uart0_rxd,
irq => open,
wb_adr_in => uart_adr,
wb_dat_in => uart_dat_wr,
wb_dat_out => uart_dat_rd,
wb_we_in => uart_we,
wb_cyc_in => uart_cyc,
wb_stb_in => uart_stb,
wb_ack_out => uart_ack
);
inst_busconnect: entity work.busconnect PORT MAP(
clk_i => clk,
rst_i => reset,
s0_cyc_i => dbus_cyc_o,
s0_stb_i => dbus_stb_o,
s0_we_i => dbus_we_o,
s0_sel_i => dbus_sel_o,
s0_ack_o => dbus_ack_i,
s0_adr_i => dbus_adr_o,
s0_dat_i => dbus_dat_o,
s0_dat_o => dbus_dat_i,
-- Memory at Adress 0XXXXXXX
m0_cyc_o => mem_cyc,
m0_stb_o => mem_stb,
m0_we_o => mem_we,
m0_sel_o => mem_sel,
m0_ack_i => mem_ack,
m0_adr_o => mem_adr,
m0_dat_o => mem_dat_wr,
m0_dat_i => mem_dat_rd,
--GPIO starts at address 1XXXXXXX
m1_cyc_o => gpio_cyc,
m1_stb_o => gpio_stb,
m1_we_o => gpio_we,
m1_sel_o => gpio_sel,
m1_ack_i => gpio_ack,
m1_adr_o => gpio_adr,
m1_dat_o => gpio_dat_wr,
m1_dat_i => gpio_dat_rd,
-- LPC starts at address 2XXXXXXX
m2_cyc_o => lpc_cyc,
m2_stb_o => lpc_stb,
m2_we_o => lpc_we,
m2_sel_o => lpc_sel,
m2_ack_i => lpc_ack,
m2_adr_o => lpc_adr,
m2_dat_o => lpc_dat_wr,
m2_dat_i => lpc_dat_rd,
-- Memory at Adress 3XXXXXXX
m3_cyc_o => mem2_cyc,
m3_stb_o => mem2_stb,
m3_we_o => mem2_we,
m3_sel_o => mem2_sel,
m3_ack_i => mem2_ack,
m3_adr_o => mem2_adr,
m3_dat_o => mem2_dat_wr,
m3_dat_i => mem2_dat_rd
);
-- Clock Buffer
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clk32Mhz,
I => sysclk_32m);
clk<=clk32Mhz; -- for the moment we set the CPU clock to the OSC.
process(clk) begin
if rising_edge(clk) then
res1<= I_RESET;
reset <= res1;
end if;
end process;
end Behavioral;
| gpl-3.0 | fa6fd3469304cd5af8e3d37e13df8cf6 | 0.542509 | 2.903474 | false | false | false | false |
hoglet67/AtomVGAWing | src/DCM_C.vhd | 1 | 2,563 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.4
-- \ \ Application : xaw2vhdl
-- / / Filename : DCM_C.vhd
-- /___/ /\ Timestamp : 03/01/2013 22:02:23
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-intstyle /home/dmb/papilio/projects/VGATest/ipcore_dir/DCM_C.xaw -st DCM_C.vhd
--Design Name: DCM_C
--Device: xc3s500e-5vq100
--
-- Module DCM_C
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.72 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity DCM_C is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end DCM_C;
architecture BEHAVIORAL of DCM_C is
signal CLKFX_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 11,
CLKFX_MULTIPLY => 21,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 66.667,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>GND_BIT,
CLKIN=>CLKIN_IN,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>open,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| gpl-3.0 | 38e1910ea046b877114e5905c2b20faa | 0.46586 | 3.747076 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/ip/feedforward_ap_dadd_3_full_dsp_64.vhd | 6 | 12,788 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_dadd_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END feedforward_ap_dadd_3_full_dsp_64;
ARCHITECTURE feedforward_ap_dadd_3_full_dsp_64_arch OF feedforward_ap_dadd_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_dadd_3_full_dsp_64_arch : ARCHITECTURE IS "feedforward_ap_dadd_3_full_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "feedforward_ap_dadd_3_full_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_dadd_3_full_dsp_64_arch;
| gpl-3.0 | 5ca0d12c7782fec66ecf5e83190eb46e | 0.652174 | 3.023883 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt | kn_kalman_mult.vhd | 2 | 100,266 | -- megafunction wizard: %ALTFP_MULT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTFP_MULT
-- ============================================================
-- File Name: kn_kalman_mult.vhd
-- Megafunction Name(s):
-- ALTFP_MULT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_mult CBX_AUTO_BLACKBOX="ALL" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" EXCEPTION_HANDLING="NO" PIPELINE=11 REDUCED_FUNCTIONALITY="NO" ROUNDING="TO_NEAREST" WIDTH_EXP=8 WIDTH_MAN=23 clock dataa datab result
--VERSION_BEGIN 11.1SP2 cbx_alt_ded_mult_y 2012:01:25:21:13:53:SJ cbx_altbarrel_shift 2012:01:25:21:13:53:SJ cbx_altera_mult_add 2012:01:25:21:13:53:SJ cbx_altfp_mult 2012:01:25:21:13:53:SJ cbx_altmult_add 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_mult 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_padd 2012:01:25:21:13:53:SJ cbx_parallel_add 2012:01:25:21:13:53:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 4 lpm_mult 1 reg 293
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_mult_altfp_mult_oon IS
PORT
(
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END kn_kalman_mult_altfp_mult_oon;
ARCHITECTURE RTL OF kn_kalman_mult_altfp_mult_oon IS
SIGNAL dataa_exp_all_one_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_dataa_exp_all_one_ff_p1_w_lg_q296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dataa_exp_all_one_ff_p1_w_lg_q291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL dataa_exp_not_zero_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dataa_man_not_zero_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_dataa_man_not_zero_ff_p1_w_lg_w_lg_q290w295w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dataa_man_not_zero_ff_p1_w_lg_q290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL dataa_man_not_zero_ff_p2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_exp_all_one_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_datab_exp_all_one_ff_p1_w_lg_q294w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_datab_exp_all_one_ff_p1_w_lg_q289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL datab_exp_not_zero_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_man_not_zero_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_datab_man_not_zero_ff_p1_w_lg_w_lg_q288w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_datab_man_not_zero_ff_p1_w_lg_q288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL datab_man_not_zero_ff_p2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL delay_exp2_bias : STD_LOGIC_VECTOR(9 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL delay_exp3_bias : STD_LOGIC_VECTOR(9 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL delay_exp_bias : STD_LOGIC_VECTOR(9 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL delay_man_product_msb : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL delay_man_product_msb2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_delay_man_product_msb2_w_lg_q393w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_delay_man_product_msb2_w_lg_q395w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL delay_man_product_msb_p0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL delay_man_product_msb_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL delay_round : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_delay_round_w485w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_lg_w_lg_w_lg_w_q_range480w481w482w483w484w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_lg_w_lg_w_lg_w_q_range470w471w472w473w474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_lg_w_lg_w_q_range480w481w482w483w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_lg_w_lg_w_q_range470w471w472w473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_lg_w_q_range480w481w482w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_lg_w_q_range470w471w472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_q_range480w481w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_q_range470w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_delay_round_w475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w475w476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_delay_round_w_q_range480w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_delay_round_w_q_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL exp_add_p1 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_exp_add_p1_w_q_range63w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adj_p1 : STD_LOGIC_VECTOR(9 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_adj_p2 : STD_LOGIC_VECTOR(9 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_exp_adj_p2_w_lg_w_lg_w_q_range459w460w461w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_lg_w_q_range459w460w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_lg_w_q_range432w457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range410w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range413w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range459w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL exp_bias_p1 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_bias_p2 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_bias_p3 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_result_ff : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL input_is_infinity_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_dffe_3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_ff1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_ff2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_ff3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_ff4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_ff5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_input_is_infinity_ff5_w_lg_q467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_input_is_infinity_ff5_w_lg_q469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL input_is_nan_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe_3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_ff1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_ff2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_ff3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_ff4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_ff5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_input_is_nan_ff5_w_lg_q479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL input_not_zero_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_dffe_3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_ff1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_ff2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_ff3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_ff4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_ff5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_input_not_zero_ff5_w_lg_q466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL lsb_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_result_ff : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_round_carry : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_round_carry_p0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_round_p : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_round_p0 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_round_p1 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_round_p2 : STD_LOGIC_VECTOR(24 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_man_round_p2_w_lg_w_q_range404w405w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_round_p2_w_lg_w_q_range401w402w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_round_p2_w_lg_w_q_range391w403w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_round_p2_w_lg_w_lg_w_q_range404w405w406w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_round_p2_w_q_range404w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_round_p2_w_q_range401w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_round_p2_w_q_range391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL round_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_exp_add_adder_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_add_adder_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_add_adder_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_adj_adder_datab : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_exp_adj_adder_result : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_exp_bias_subtr_dataa : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_exp_bias_subtr_datab : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_exp_bias_subtr_result : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_man_round_adder_dataa : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_round_adder_datab : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_round_adder_result : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_lg_w_result_range302w303w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_lg_w_result_range299w300w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_lg_w_result_range298w373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_lg_w_result_range298w301w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_dataa : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_product2_mult_datab : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_product2_mult_result : STD_LOGIC_VECTOR (47 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range335w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range341w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range344w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range347w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range350w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range353w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range356w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range359w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range362w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range308w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range365w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range368w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range371w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range311w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range314w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range302w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range299w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range298w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range317w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range320w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range323w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range332w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_inf_num464w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range81w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range91w98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range101w108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range121w128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range131w138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range84w90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range94w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range104w110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range124w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range134w140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range408w412w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range411w415w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range414w418w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range417w421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range420w424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range423w427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range426w430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_is_inf468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_is_zero458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range454w456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_inf_num464w465w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_is_inf462w463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_is_inf462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range211w213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range221w223w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range227w229w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range233w235w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range239w241w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range245w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range251w253w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range257w259w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range263w265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range157w159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range269w271w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range275w277w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range281w283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range81w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range91w93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range101w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range121w123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range131w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range163w165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range169w171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range175w177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range181w183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range187w189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range193w195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range199w201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range205w207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range214w216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range224w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range230w232w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range236w238w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range242w244w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range248w250w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range254w256w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range260w262w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range266w268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range160w162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range272w274w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range278w280w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range284w286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range84w86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range94w96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range104w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range124w126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range134w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range166w168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range172w174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range178w180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range184w186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range190w192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range196w198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range202w204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range208w210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range438w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range440w443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range442w445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range444w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range446w449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range448w451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range450w453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range452w455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range306w310w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range336w340w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range339w343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range342w346w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range345w349w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range348w352w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range351w355w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range354w358w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range357w361w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range360w364w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range363w367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range309w313w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range366w370w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range369w374w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range312w316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range315w319w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range318w322w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range321w325w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range324w328w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range327w331w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range330w334w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range333w337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL aclr : STD_LOGIC;
SIGNAL bias : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL clk_en : STD_LOGIC;
SIGNAL dataa_exp_all_one : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_exp_not_zero : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_man_not_zero : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL datab_exp_all_one : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL datab_exp_not_zero : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL datab_man_not_zero : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL exp_is_inf : STD_LOGIC;
SIGNAL exp_is_zero : STD_LOGIC;
SIGNAL expmod : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL inf_num : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL lsb_bit : STD_LOGIC;
SIGNAL man_shift_full : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL result_exp_all_one : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL result_exp_not_zero : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL round_bit : STD_LOGIC;
SIGNAL round_carry : STD_LOGIC;
SIGNAL sticky_bit : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_dataa_range211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range221w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range227w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range239w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range251w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range263w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range281w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range222w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range228w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range234w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range240w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range224w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range230w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range236w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range242w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range272w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range278w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range284w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range231w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range243w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range261w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range273w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range279w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_shift_full_range379w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range408w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range411w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range414w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range339w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range345w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range348w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range351w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range357w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range360w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range363w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range309w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range366w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range369w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range312w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range315w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range318w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range324w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range327w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range330w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range333w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_mult
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTHA : NATURAL;
LPM_WIDTHB : NATURAL;
LPM_WIDTHP : NATURAL;
LPM_WIDTHS : NATURAL := 1;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_mult"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTHA-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR(LPM_WIDTHB-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(LPM_WIDTHP-1 DOWNTO 0);
sum : IN STD_LOGIC_VECTOR(LPM_WIDTHS-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
loop0 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_inf_num464w(i) <= inf_num(i) AND wire_w_lg_w_lg_exp_is_inf462w463w(0);
END GENERATE loop0;
wire_w_lg_w_dataa_range81w88w(0) <= wire_w_dataa_range81w(0) AND wire_w_dataa_exp_all_one_range77w(0);
wire_w_lg_w_dataa_range91w98w(0) <= wire_w_dataa_range91w(0) AND wire_w_dataa_exp_all_one_range87w(0);
wire_w_lg_w_dataa_range101w108w(0) <= wire_w_dataa_range101w(0) AND wire_w_dataa_exp_all_one_range97w(0);
wire_w_lg_w_dataa_range111w118w(0) <= wire_w_dataa_range111w(0) AND wire_w_dataa_exp_all_one_range107w(0);
wire_w_lg_w_dataa_range121w128w(0) <= wire_w_dataa_range121w(0) AND wire_w_dataa_exp_all_one_range117w(0);
wire_w_lg_w_dataa_range131w138w(0) <= wire_w_dataa_range131w(0) AND wire_w_dataa_exp_all_one_range127w(0);
wire_w_lg_w_dataa_range141w148w(0) <= wire_w_dataa_range141w(0) AND wire_w_dataa_exp_all_one_range137w(0);
wire_w_lg_w_datab_range84w90w(0) <= wire_w_datab_range84w(0) AND wire_w_datab_exp_all_one_range79w(0);
wire_w_lg_w_datab_range94w100w(0) <= wire_w_datab_range94w(0) AND wire_w_datab_exp_all_one_range89w(0);
wire_w_lg_w_datab_range104w110w(0) <= wire_w_datab_range104w(0) AND wire_w_datab_exp_all_one_range99w(0);
wire_w_lg_w_datab_range114w120w(0) <= wire_w_datab_range114w(0) AND wire_w_datab_exp_all_one_range109w(0);
wire_w_lg_w_datab_range124w130w(0) <= wire_w_datab_range124w(0) AND wire_w_datab_exp_all_one_range119w(0);
wire_w_lg_w_datab_range134w140w(0) <= wire_w_datab_range134w(0) AND wire_w_datab_exp_all_one_range129w(0);
wire_w_lg_w_datab_range144w150w(0) <= wire_w_datab_range144w(0) AND wire_w_datab_exp_all_one_range139w(0);
wire_w_lg_w_result_exp_all_one_range408w412w(0) <= wire_w_result_exp_all_one_range408w(0) AND wire_exp_adj_p2_w_q_range410w(0);
wire_w_lg_w_result_exp_all_one_range411w415w(0) <= wire_w_result_exp_all_one_range411w(0) AND wire_exp_adj_p2_w_q_range413w(0);
wire_w_lg_w_result_exp_all_one_range414w418w(0) <= wire_w_result_exp_all_one_range414w(0) AND wire_exp_adj_p2_w_q_range416w(0);
wire_w_lg_w_result_exp_all_one_range417w421w(0) <= wire_w_result_exp_all_one_range417w(0) AND wire_exp_adj_p2_w_q_range419w(0);
wire_w_lg_w_result_exp_all_one_range420w424w(0) <= wire_w_result_exp_all_one_range420w(0) AND wire_exp_adj_p2_w_q_range422w(0);
wire_w_lg_w_result_exp_all_one_range423w427w(0) <= wire_w_result_exp_all_one_range423w(0) AND wire_exp_adj_p2_w_q_range425w(0);
wire_w_lg_w_result_exp_all_one_range426w430w(0) <= wire_w_result_exp_all_one_range426w(0) AND wire_exp_adj_p2_w_q_range428w(0);
wire_w_lg_exp_is_inf468w(0) <= NOT exp_is_inf;
wire_w_lg_exp_is_zero458w(0) <= NOT exp_is_zero;
wire_w_lg_w_result_exp_not_zero_range454w456w(0) <= NOT wire_w_result_exp_not_zero_range454w(0);
loop1 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_inf_num464w465w(i) <= wire_w_lg_inf_num464w(i) OR wire_exp_adj_p2_w_lg_w_lg_w_q_range459w460w461w(i);
END GENERATE loop1;
wire_w_lg_w_lg_exp_is_inf462w463w(0) <= wire_w_lg_exp_is_inf462w(0) OR input_is_nan_ff5;
wire_w_lg_exp_is_inf462w(0) <= exp_is_inf OR input_is_infinity_ff5;
wire_w_lg_w_dataa_range211w213w(0) <= wire_w_dataa_range211w(0) OR wire_w_dataa_man_not_zero_range206w(0);
wire_w_lg_w_dataa_range221w223w(0) <= wire_w_dataa_range221w(0) OR wire_w_dataa_man_not_zero_range218w(0);
wire_w_lg_w_dataa_range227w229w(0) <= wire_w_dataa_range227w(0) OR wire_w_dataa_man_not_zero_range222w(0);
wire_w_lg_w_dataa_range233w235w(0) <= wire_w_dataa_range233w(0) OR wire_w_dataa_man_not_zero_range228w(0);
wire_w_lg_w_dataa_range239w241w(0) <= wire_w_dataa_range239w(0) OR wire_w_dataa_man_not_zero_range234w(0);
wire_w_lg_w_dataa_range245w247w(0) <= wire_w_dataa_range245w(0) OR wire_w_dataa_man_not_zero_range240w(0);
wire_w_lg_w_dataa_range251w253w(0) <= wire_w_dataa_range251w(0) OR wire_w_dataa_man_not_zero_range246w(0);
wire_w_lg_w_dataa_range257w259w(0) <= wire_w_dataa_range257w(0) OR wire_w_dataa_man_not_zero_range252w(0);
wire_w_lg_w_dataa_range263w265w(0) <= wire_w_dataa_range263w(0) OR wire_w_dataa_man_not_zero_range258w(0);
wire_w_lg_w_dataa_range157w159w(0) <= wire_w_dataa_range157w(0) OR wire_w_dataa_man_not_zero_range152w(0);
wire_w_lg_w_dataa_range269w271w(0) <= wire_w_dataa_range269w(0) OR wire_w_dataa_man_not_zero_range264w(0);
wire_w_lg_w_dataa_range275w277w(0) <= wire_w_dataa_range275w(0) OR wire_w_dataa_man_not_zero_range270w(0);
wire_w_lg_w_dataa_range281w283w(0) <= wire_w_dataa_range281w(0) OR wire_w_dataa_man_not_zero_range276w(0);
wire_w_lg_w_dataa_range81w83w(0) <= wire_w_dataa_range81w(0) OR wire_w_dataa_exp_not_zero_range72w(0);
wire_w_lg_w_dataa_range91w93w(0) <= wire_w_dataa_range91w(0) OR wire_w_dataa_exp_not_zero_range82w(0);
wire_w_lg_w_dataa_range101w103w(0) <= wire_w_dataa_range101w(0) OR wire_w_dataa_exp_not_zero_range92w(0);
wire_w_lg_w_dataa_range111w113w(0) <= wire_w_dataa_range111w(0) OR wire_w_dataa_exp_not_zero_range102w(0);
wire_w_lg_w_dataa_range121w123w(0) <= wire_w_dataa_range121w(0) OR wire_w_dataa_exp_not_zero_range112w(0);
wire_w_lg_w_dataa_range131w133w(0) <= wire_w_dataa_range131w(0) OR wire_w_dataa_exp_not_zero_range122w(0);
wire_w_lg_w_dataa_range163w165w(0) <= wire_w_dataa_range163w(0) OR wire_w_dataa_man_not_zero_range158w(0);
wire_w_lg_w_dataa_range141w143w(0) <= wire_w_dataa_range141w(0) OR wire_w_dataa_exp_not_zero_range132w(0);
wire_w_lg_w_dataa_range169w171w(0) <= wire_w_dataa_range169w(0) OR wire_w_dataa_man_not_zero_range164w(0);
wire_w_lg_w_dataa_range175w177w(0) <= wire_w_dataa_range175w(0) OR wire_w_dataa_man_not_zero_range170w(0);
wire_w_lg_w_dataa_range181w183w(0) <= wire_w_dataa_range181w(0) OR wire_w_dataa_man_not_zero_range176w(0);
wire_w_lg_w_dataa_range187w189w(0) <= wire_w_dataa_range187w(0) OR wire_w_dataa_man_not_zero_range182w(0);
wire_w_lg_w_dataa_range193w195w(0) <= wire_w_dataa_range193w(0) OR wire_w_dataa_man_not_zero_range188w(0);
wire_w_lg_w_dataa_range199w201w(0) <= wire_w_dataa_range199w(0) OR wire_w_dataa_man_not_zero_range194w(0);
wire_w_lg_w_dataa_range205w207w(0) <= wire_w_dataa_range205w(0) OR wire_w_dataa_man_not_zero_range200w(0);
wire_w_lg_w_datab_range214w216w(0) <= wire_w_datab_range214w(0) OR wire_w_datab_man_not_zero_range209w(0);
wire_w_lg_w_datab_range224w226w(0) <= wire_w_datab_range224w(0) OR wire_w_datab_man_not_zero_range220w(0);
wire_w_lg_w_datab_range230w232w(0) <= wire_w_datab_range230w(0) OR wire_w_datab_man_not_zero_range225w(0);
wire_w_lg_w_datab_range236w238w(0) <= wire_w_datab_range236w(0) OR wire_w_datab_man_not_zero_range231w(0);
wire_w_lg_w_datab_range242w244w(0) <= wire_w_datab_range242w(0) OR wire_w_datab_man_not_zero_range237w(0);
wire_w_lg_w_datab_range248w250w(0) <= wire_w_datab_range248w(0) OR wire_w_datab_man_not_zero_range243w(0);
wire_w_lg_w_datab_range254w256w(0) <= wire_w_datab_range254w(0) OR wire_w_datab_man_not_zero_range249w(0);
wire_w_lg_w_datab_range260w262w(0) <= wire_w_datab_range260w(0) OR wire_w_datab_man_not_zero_range255w(0);
wire_w_lg_w_datab_range266w268w(0) <= wire_w_datab_range266w(0) OR wire_w_datab_man_not_zero_range261w(0);
wire_w_lg_w_datab_range160w162w(0) <= wire_w_datab_range160w(0) OR wire_w_datab_man_not_zero_range155w(0);
wire_w_lg_w_datab_range272w274w(0) <= wire_w_datab_range272w(0) OR wire_w_datab_man_not_zero_range267w(0);
wire_w_lg_w_datab_range278w280w(0) <= wire_w_datab_range278w(0) OR wire_w_datab_man_not_zero_range273w(0);
wire_w_lg_w_datab_range284w286w(0) <= wire_w_datab_range284w(0) OR wire_w_datab_man_not_zero_range279w(0);
wire_w_lg_w_datab_range84w86w(0) <= wire_w_datab_range84w(0) OR wire_w_datab_exp_not_zero_range75w(0);
wire_w_lg_w_datab_range94w96w(0) <= wire_w_datab_range94w(0) OR wire_w_datab_exp_not_zero_range85w(0);
wire_w_lg_w_datab_range104w106w(0) <= wire_w_datab_range104w(0) OR wire_w_datab_exp_not_zero_range95w(0);
wire_w_lg_w_datab_range114w116w(0) <= wire_w_datab_range114w(0) OR wire_w_datab_exp_not_zero_range105w(0);
wire_w_lg_w_datab_range124w126w(0) <= wire_w_datab_range124w(0) OR wire_w_datab_exp_not_zero_range115w(0);
wire_w_lg_w_datab_range134w136w(0) <= wire_w_datab_range134w(0) OR wire_w_datab_exp_not_zero_range125w(0);
wire_w_lg_w_datab_range166w168w(0) <= wire_w_datab_range166w(0) OR wire_w_datab_man_not_zero_range161w(0);
wire_w_lg_w_datab_range144w146w(0) <= wire_w_datab_range144w(0) OR wire_w_datab_exp_not_zero_range135w(0);
wire_w_lg_w_datab_range172w174w(0) <= wire_w_datab_range172w(0) OR wire_w_datab_man_not_zero_range167w(0);
wire_w_lg_w_datab_range178w180w(0) <= wire_w_datab_range178w(0) OR wire_w_datab_man_not_zero_range173w(0);
wire_w_lg_w_datab_range184w186w(0) <= wire_w_datab_range184w(0) OR wire_w_datab_man_not_zero_range179w(0);
wire_w_lg_w_datab_range190w192w(0) <= wire_w_datab_range190w(0) OR wire_w_datab_man_not_zero_range185w(0);
wire_w_lg_w_datab_range196w198w(0) <= wire_w_datab_range196w(0) OR wire_w_datab_man_not_zero_range191w(0);
wire_w_lg_w_datab_range202w204w(0) <= wire_w_datab_range202w(0) OR wire_w_datab_man_not_zero_range197w(0);
wire_w_lg_w_datab_range208w210w(0) <= wire_w_datab_range208w(0) OR wire_w_datab_man_not_zero_range203w(0);
wire_w_lg_w_result_exp_not_zero_range438w441w(0) <= wire_w_result_exp_not_zero_range438w(0) OR wire_exp_adj_p2_w_q_range410w(0);
wire_w_lg_w_result_exp_not_zero_range440w443w(0) <= wire_w_result_exp_not_zero_range440w(0) OR wire_exp_adj_p2_w_q_range413w(0);
wire_w_lg_w_result_exp_not_zero_range442w445w(0) <= wire_w_result_exp_not_zero_range442w(0) OR wire_exp_adj_p2_w_q_range416w(0);
wire_w_lg_w_result_exp_not_zero_range444w447w(0) <= wire_w_result_exp_not_zero_range444w(0) OR wire_exp_adj_p2_w_q_range419w(0);
wire_w_lg_w_result_exp_not_zero_range446w449w(0) <= wire_w_result_exp_not_zero_range446w(0) OR wire_exp_adj_p2_w_q_range422w(0);
wire_w_lg_w_result_exp_not_zero_range448w451w(0) <= wire_w_result_exp_not_zero_range448w(0) OR wire_exp_adj_p2_w_q_range425w(0);
wire_w_lg_w_result_exp_not_zero_range450w453w(0) <= wire_w_result_exp_not_zero_range450w(0) OR wire_exp_adj_p2_w_q_range428w(0);
wire_w_lg_w_result_exp_not_zero_range452w455w(0) <= wire_w_result_exp_not_zero_range452w(0) OR wire_exp_adj_p2_w_q_range431w(0);
wire_w_lg_w_sticky_bit_range306w310w(0) <= wire_w_sticky_bit_range306w(0) OR wire_man_product2_mult_w_result_range308w(0);
wire_w_lg_w_sticky_bit_range336w340w(0) <= wire_w_sticky_bit_range336w(0) OR wire_man_product2_mult_w_result_range338w(0);
wire_w_lg_w_sticky_bit_range339w343w(0) <= wire_w_sticky_bit_range339w(0) OR wire_man_product2_mult_w_result_range341w(0);
wire_w_lg_w_sticky_bit_range342w346w(0) <= wire_w_sticky_bit_range342w(0) OR wire_man_product2_mult_w_result_range344w(0);
wire_w_lg_w_sticky_bit_range345w349w(0) <= wire_w_sticky_bit_range345w(0) OR wire_man_product2_mult_w_result_range347w(0);
wire_w_lg_w_sticky_bit_range348w352w(0) <= wire_w_sticky_bit_range348w(0) OR wire_man_product2_mult_w_result_range350w(0);
wire_w_lg_w_sticky_bit_range351w355w(0) <= wire_w_sticky_bit_range351w(0) OR wire_man_product2_mult_w_result_range353w(0);
wire_w_lg_w_sticky_bit_range354w358w(0) <= wire_w_sticky_bit_range354w(0) OR wire_man_product2_mult_w_result_range356w(0);
wire_w_lg_w_sticky_bit_range357w361w(0) <= wire_w_sticky_bit_range357w(0) OR wire_man_product2_mult_w_result_range359w(0);
wire_w_lg_w_sticky_bit_range360w364w(0) <= wire_w_sticky_bit_range360w(0) OR wire_man_product2_mult_w_result_range362w(0);
wire_w_lg_w_sticky_bit_range363w367w(0) <= wire_w_sticky_bit_range363w(0) OR wire_man_product2_mult_w_result_range365w(0);
wire_w_lg_w_sticky_bit_range309w313w(0) <= wire_w_sticky_bit_range309w(0) OR wire_man_product2_mult_w_result_range311w(0);
wire_w_lg_w_sticky_bit_range366w370w(0) <= wire_w_sticky_bit_range366w(0) OR wire_man_product2_mult_w_result_range368w(0);
wire_w_lg_w_sticky_bit_range369w374w(0) <= wire_w_sticky_bit_range369w(0) OR wire_man_product2_mult_w_lg_w_result_range298w373w(0);
wire_w_lg_w_sticky_bit_range312w316w(0) <= wire_w_sticky_bit_range312w(0) OR wire_man_product2_mult_w_result_range314w(0);
wire_w_lg_w_sticky_bit_range315w319w(0) <= wire_w_sticky_bit_range315w(0) OR wire_man_product2_mult_w_result_range317w(0);
wire_w_lg_w_sticky_bit_range318w322w(0) <= wire_w_sticky_bit_range318w(0) OR wire_man_product2_mult_w_result_range320w(0);
wire_w_lg_w_sticky_bit_range321w325w(0) <= wire_w_sticky_bit_range321w(0) OR wire_man_product2_mult_w_result_range323w(0);
wire_w_lg_w_sticky_bit_range324w328w(0) <= wire_w_sticky_bit_range324w(0) OR wire_man_product2_mult_w_result_range326w(0);
wire_w_lg_w_sticky_bit_range327w331w(0) <= wire_w_sticky_bit_range327w(0) OR wire_man_product2_mult_w_result_range329w(0);
wire_w_lg_w_sticky_bit_range330w334w(0) <= wire_w_sticky_bit_range330w(0) OR wire_man_product2_mult_w_result_range332w(0);
wire_w_lg_w_sticky_bit_range333w337w(0) <= wire_w_sticky_bit_range333w(0) OR wire_man_product2_mult_w_result_range335w(0);
aclr <= '0';
bias <= ( "0" & "0" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1");
clk_en <= '1';
dataa_exp_all_one <= ( wire_w_lg_w_dataa_range141w148w & wire_w_lg_w_dataa_range131w138w & wire_w_lg_w_dataa_range121w128w & wire_w_lg_w_dataa_range111w118w & wire_w_lg_w_dataa_range101w108w & wire_w_lg_w_dataa_range91w98w & wire_w_lg_w_dataa_range81w88w & dataa(23));
dataa_exp_not_zero <= ( wire_w_lg_w_dataa_range141w143w & wire_w_lg_w_dataa_range131w133w & wire_w_lg_w_dataa_range121w123w & wire_w_lg_w_dataa_range111w113w & wire_w_lg_w_dataa_range101w103w & wire_w_lg_w_dataa_range91w93w & wire_w_lg_w_dataa_range81w83w & dataa(23));
dataa_man_not_zero <= ( wire_w_lg_w_dataa_range281w283w & wire_w_lg_w_dataa_range275w277w & wire_w_lg_w_dataa_range269w271w & wire_w_lg_w_dataa_range263w265w & wire_w_lg_w_dataa_range257w259w & wire_w_lg_w_dataa_range251w253w & wire_w_lg_w_dataa_range245w247w & wire_w_lg_w_dataa_range239w241w & wire_w_lg_w_dataa_range233w235w & wire_w_lg_w_dataa_range227w229w & wire_w_lg_w_dataa_range221w223w & dataa(11) & wire_w_lg_w_dataa_range211w213w & wire_w_lg_w_dataa_range205w207w & wire_w_lg_w_dataa_range199w201w & wire_w_lg_w_dataa_range193w195w & wire_w_lg_w_dataa_range187w189w & wire_w_lg_w_dataa_range181w183w & wire_w_lg_w_dataa_range175w177w & wire_w_lg_w_dataa_range169w171w & wire_w_lg_w_dataa_range163w165w & wire_w_lg_w_dataa_range157w159w & dataa(0));
datab_exp_all_one <= ( wire_w_lg_w_datab_range144w150w & wire_w_lg_w_datab_range134w140w & wire_w_lg_w_datab_range124w130w & wire_w_lg_w_datab_range114w120w & wire_w_lg_w_datab_range104w110w & wire_w_lg_w_datab_range94w100w & wire_w_lg_w_datab_range84w90w & datab(23));
datab_exp_not_zero <= ( wire_w_lg_w_datab_range144w146w & wire_w_lg_w_datab_range134w136w & wire_w_lg_w_datab_range124w126w & wire_w_lg_w_datab_range114w116w & wire_w_lg_w_datab_range104w106w & wire_w_lg_w_datab_range94w96w & wire_w_lg_w_datab_range84w86w & datab(23));
datab_man_not_zero <= ( wire_w_lg_w_datab_range284w286w & wire_w_lg_w_datab_range278w280w & wire_w_lg_w_datab_range272w274w & wire_w_lg_w_datab_range266w268w & wire_w_lg_w_datab_range260w262w & wire_w_lg_w_datab_range254w256w & wire_w_lg_w_datab_range248w250w & wire_w_lg_w_datab_range242w244w & wire_w_lg_w_datab_range236w238w & wire_w_lg_w_datab_range230w232w & wire_w_lg_w_datab_range224w226w & datab(11) & wire_w_lg_w_datab_range214w216w & wire_w_lg_w_datab_range208w210w & wire_w_lg_w_datab_range202w204w & wire_w_lg_w_datab_range196w198w & wire_w_lg_w_datab_range190w192w & wire_w_lg_w_datab_range184w186w & wire_w_lg_w_datab_range178w180w & wire_w_lg_w_datab_range172w174w & wire_w_lg_w_datab_range166w168w & wire_w_lg_w_datab_range160w162w & datab(0));
exp_is_inf <= (((NOT exp_adj_p2(9)) AND exp_adj_p2(8)) OR ((NOT exp_adj_p2(8)) AND result_exp_all_one(7)));
exp_is_zero <= wire_exp_adj_p2_w_lg_w_q_range432w457w(0);
expmod <= ( "00000000" & wire_delay_man_product_msb2_w_lg_q393w & wire_delay_man_product_msb2_w_lg_q395w);
inf_num <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1");
lsb_bit <= man_shift_full(1);
man_shift_full <= (wire_man_product2_mult_w_lg_w_result_range302w303w OR wire_man_product2_mult_w_lg_w_result_range299w300w);
result <= ( sign_node_ff10 & exp_result_ff(7 DOWNTO 0) & man_result_ff(22 DOWNTO 0));
result_exp_all_one <= ( wire_w_lg_w_result_exp_all_one_range426w430w & wire_w_lg_w_result_exp_all_one_range423w427w & wire_w_lg_w_result_exp_all_one_range420w424w & wire_w_lg_w_result_exp_all_one_range417w421w & wire_w_lg_w_result_exp_all_one_range414w418w & wire_w_lg_w_result_exp_all_one_range411w415w & wire_w_lg_w_result_exp_all_one_range408w412w & exp_adj_p2(0));
result_exp_not_zero <= ( wire_w_lg_w_result_exp_not_zero_range452w455w & wire_w_lg_w_result_exp_not_zero_range450w453w & wire_w_lg_w_result_exp_not_zero_range448w451w & wire_w_lg_w_result_exp_not_zero_range446w449w & wire_w_lg_w_result_exp_not_zero_range444w447w & wire_w_lg_w_result_exp_not_zero_range442w445w & wire_w_lg_w_result_exp_not_zero_range440w443w & wire_w_lg_w_result_exp_not_zero_range438w441w & exp_adj_p2(0));
round_bit <= man_shift_full(0);
round_carry <= (round_dffe AND (lsb_dffe OR sticky_dffe));
sticky_bit <= ( wire_w_lg_w_sticky_bit_range369w374w & wire_w_lg_w_sticky_bit_range366w370w & wire_w_lg_w_sticky_bit_range363w367w & wire_w_lg_w_sticky_bit_range360w364w & wire_w_lg_w_sticky_bit_range357w361w & wire_w_lg_w_sticky_bit_range354w358w & wire_w_lg_w_sticky_bit_range351w355w & wire_w_lg_w_sticky_bit_range348w352w & wire_w_lg_w_sticky_bit_range345w349w & wire_w_lg_w_sticky_bit_range342w346w & wire_w_lg_w_sticky_bit_range339w343w & wire_w_lg_w_sticky_bit_range336w340w & wire_w_lg_w_sticky_bit_range333w337w & wire_w_lg_w_sticky_bit_range330w334w & wire_w_lg_w_sticky_bit_range327w331w & wire_w_lg_w_sticky_bit_range324w328w & wire_w_lg_w_sticky_bit_range321w325w & wire_w_lg_w_sticky_bit_range318w322w & wire_w_lg_w_sticky_bit_range315w319w & wire_w_lg_w_sticky_bit_range312w316w & wire_w_lg_w_sticky_bit_range309w313w & wire_w_lg_w_sticky_bit_range306w310w & wire_man_product2_mult_result(0));
wire_w_dataa_range211w(0) <= dataa(10);
wire_w_dataa_range221w(0) <= dataa(12);
wire_w_dataa_range227w(0) <= dataa(13);
wire_w_dataa_range233w(0) <= dataa(14);
wire_w_dataa_range239w(0) <= dataa(15);
wire_w_dataa_range245w(0) <= dataa(16);
wire_w_dataa_range251w(0) <= dataa(17);
wire_w_dataa_range257w(0) <= dataa(18);
wire_w_dataa_range263w(0) <= dataa(19);
wire_w_dataa_range157w(0) <= dataa(1);
wire_w_dataa_range269w(0) <= dataa(20);
wire_w_dataa_range275w(0) <= dataa(21);
wire_w_dataa_range281w(0) <= dataa(22);
wire_w_dataa_range81w(0) <= dataa(24);
wire_w_dataa_range91w(0) <= dataa(25);
wire_w_dataa_range101w(0) <= dataa(26);
wire_w_dataa_range111w(0) <= dataa(27);
wire_w_dataa_range121w(0) <= dataa(28);
wire_w_dataa_range131w(0) <= dataa(29);
wire_w_dataa_range163w(0) <= dataa(2);
wire_w_dataa_range141w(0) <= dataa(30);
wire_w_dataa_range169w(0) <= dataa(3);
wire_w_dataa_range175w(0) <= dataa(4);
wire_w_dataa_range181w(0) <= dataa(5);
wire_w_dataa_range187w(0) <= dataa(6);
wire_w_dataa_range193w(0) <= dataa(7);
wire_w_dataa_range199w(0) <= dataa(8);
wire_w_dataa_range205w(0) <= dataa(9);
wire_w_dataa_exp_all_one_range77w(0) <= dataa_exp_all_one(0);
wire_w_dataa_exp_all_one_range87w(0) <= dataa_exp_all_one(1);
wire_w_dataa_exp_all_one_range97w(0) <= dataa_exp_all_one(2);
wire_w_dataa_exp_all_one_range107w(0) <= dataa_exp_all_one(3);
wire_w_dataa_exp_all_one_range117w(0) <= dataa_exp_all_one(4);
wire_w_dataa_exp_all_one_range127w(0) <= dataa_exp_all_one(5);
wire_w_dataa_exp_all_one_range137w(0) <= dataa_exp_all_one(6);
wire_w_dataa_exp_not_zero_range72w(0) <= dataa_exp_not_zero(0);
wire_w_dataa_exp_not_zero_range82w(0) <= dataa_exp_not_zero(1);
wire_w_dataa_exp_not_zero_range92w(0) <= dataa_exp_not_zero(2);
wire_w_dataa_exp_not_zero_range102w(0) <= dataa_exp_not_zero(3);
wire_w_dataa_exp_not_zero_range112w(0) <= dataa_exp_not_zero(4);
wire_w_dataa_exp_not_zero_range122w(0) <= dataa_exp_not_zero(5);
wire_w_dataa_exp_not_zero_range132w(0) <= dataa_exp_not_zero(6);
wire_w_dataa_man_not_zero_range152w(0) <= dataa_man_not_zero(0);
wire_w_dataa_man_not_zero_range218w(0) <= dataa_man_not_zero(11);
wire_w_dataa_man_not_zero_range222w(0) <= dataa_man_not_zero(12);
wire_w_dataa_man_not_zero_range228w(0) <= dataa_man_not_zero(13);
wire_w_dataa_man_not_zero_range234w(0) <= dataa_man_not_zero(14);
wire_w_dataa_man_not_zero_range240w(0) <= dataa_man_not_zero(15);
wire_w_dataa_man_not_zero_range246w(0) <= dataa_man_not_zero(16);
wire_w_dataa_man_not_zero_range252w(0) <= dataa_man_not_zero(17);
wire_w_dataa_man_not_zero_range258w(0) <= dataa_man_not_zero(18);
wire_w_dataa_man_not_zero_range264w(0) <= dataa_man_not_zero(19);
wire_w_dataa_man_not_zero_range158w(0) <= dataa_man_not_zero(1);
wire_w_dataa_man_not_zero_range270w(0) <= dataa_man_not_zero(20);
wire_w_dataa_man_not_zero_range276w(0) <= dataa_man_not_zero(21);
wire_w_dataa_man_not_zero_range164w(0) <= dataa_man_not_zero(2);
wire_w_dataa_man_not_zero_range170w(0) <= dataa_man_not_zero(3);
wire_w_dataa_man_not_zero_range176w(0) <= dataa_man_not_zero(4);
wire_w_dataa_man_not_zero_range182w(0) <= dataa_man_not_zero(5);
wire_w_dataa_man_not_zero_range188w(0) <= dataa_man_not_zero(6);
wire_w_dataa_man_not_zero_range194w(0) <= dataa_man_not_zero(7);
wire_w_dataa_man_not_zero_range200w(0) <= dataa_man_not_zero(8);
wire_w_dataa_man_not_zero_range206w(0) <= dataa_man_not_zero(9);
wire_w_datab_range214w(0) <= datab(10);
wire_w_datab_range224w(0) <= datab(12);
wire_w_datab_range230w(0) <= datab(13);
wire_w_datab_range236w(0) <= datab(14);
wire_w_datab_range242w(0) <= datab(15);
wire_w_datab_range248w(0) <= datab(16);
wire_w_datab_range254w(0) <= datab(17);
wire_w_datab_range260w(0) <= datab(18);
wire_w_datab_range266w(0) <= datab(19);
wire_w_datab_range160w(0) <= datab(1);
wire_w_datab_range272w(0) <= datab(20);
wire_w_datab_range278w(0) <= datab(21);
wire_w_datab_range284w(0) <= datab(22);
wire_w_datab_range84w(0) <= datab(24);
wire_w_datab_range94w(0) <= datab(25);
wire_w_datab_range104w(0) <= datab(26);
wire_w_datab_range114w(0) <= datab(27);
wire_w_datab_range124w(0) <= datab(28);
wire_w_datab_range134w(0) <= datab(29);
wire_w_datab_range166w(0) <= datab(2);
wire_w_datab_range144w(0) <= datab(30);
wire_w_datab_range172w(0) <= datab(3);
wire_w_datab_range178w(0) <= datab(4);
wire_w_datab_range184w(0) <= datab(5);
wire_w_datab_range190w(0) <= datab(6);
wire_w_datab_range196w(0) <= datab(7);
wire_w_datab_range202w(0) <= datab(8);
wire_w_datab_range208w(0) <= datab(9);
wire_w_datab_exp_all_one_range79w(0) <= datab_exp_all_one(0);
wire_w_datab_exp_all_one_range89w(0) <= datab_exp_all_one(1);
wire_w_datab_exp_all_one_range99w(0) <= datab_exp_all_one(2);
wire_w_datab_exp_all_one_range109w(0) <= datab_exp_all_one(3);
wire_w_datab_exp_all_one_range119w(0) <= datab_exp_all_one(4);
wire_w_datab_exp_all_one_range129w(0) <= datab_exp_all_one(5);
wire_w_datab_exp_all_one_range139w(0) <= datab_exp_all_one(6);
wire_w_datab_exp_not_zero_range75w(0) <= datab_exp_not_zero(0);
wire_w_datab_exp_not_zero_range85w(0) <= datab_exp_not_zero(1);
wire_w_datab_exp_not_zero_range95w(0) <= datab_exp_not_zero(2);
wire_w_datab_exp_not_zero_range105w(0) <= datab_exp_not_zero(3);
wire_w_datab_exp_not_zero_range115w(0) <= datab_exp_not_zero(4);
wire_w_datab_exp_not_zero_range125w(0) <= datab_exp_not_zero(5);
wire_w_datab_exp_not_zero_range135w(0) <= datab_exp_not_zero(6);
wire_w_datab_man_not_zero_range155w(0) <= datab_man_not_zero(0);
wire_w_datab_man_not_zero_range220w(0) <= datab_man_not_zero(11);
wire_w_datab_man_not_zero_range225w(0) <= datab_man_not_zero(12);
wire_w_datab_man_not_zero_range231w(0) <= datab_man_not_zero(13);
wire_w_datab_man_not_zero_range237w(0) <= datab_man_not_zero(14);
wire_w_datab_man_not_zero_range243w(0) <= datab_man_not_zero(15);
wire_w_datab_man_not_zero_range249w(0) <= datab_man_not_zero(16);
wire_w_datab_man_not_zero_range255w(0) <= datab_man_not_zero(17);
wire_w_datab_man_not_zero_range261w(0) <= datab_man_not_zero(18);
wire_w_datab_man_not_zero_range267w(0) <= datab_man_not_zero(19);
wire_w_datab_man_not_zero_range161w(0) <= datab_man_not_zero(1);
wire_w_datab_man_not_zero_range273w(0) <= datab_man_not_zero(20);
wire_w_datab_man_not_zero_range279w(0) <= datab_man_not_zero(21);
wire_w_datab_man_not_zero_range167w(0) <= datab_man_not_zero(2);
wire_w_datab_man_not_zero_range173w(0) <= datab_man_not_zero(3);
wire_w_datab_man_not_zero_range179w(0) <= datab_man_not_zero(4);
wire_w_datab_man_not_zero_range185w(0) <= datab_man_not_zero(5);
wire_w_datab_man_not_zero_range191w(0) <= datab_man_not_zero(6);
wire_w_datab_man_not_zero_range197w(0) <= datab_man_not_zero(7);
wire_w_datab_man_not_zero_range203w(0) <= datab_man_not_zero(8);
wire_w_datab_man_not_zero_range209w(0) <= datab_man_not_zero(9);
wire_w_man_shift_full_range379w <= man_shift_full(24 DOWNTO 1);
wire_w_result_exp_all_one_range408w(0) <= result_exp_all_one(0);
wire_w_result_exp_all_one_range411w(0) <= result_exp_all_one(1);
wire_w_result_exp_all_one_range414w(0) <= result_exp_all_one(2);
wire_w_result_exp_all_one_range417w(0) <= result_exp_all_one(3);
wire_w_result_exp_all_one_range420w(0) <= result_exp_all_one(4);
wire_w_result_exp_all_one_range423w(0) <= result_exp_all_one(5);
wire_w_result_exp_all_one_range426w(0) <= result_exp_all_one(6);
wire_w_result_exp_not_zero_range438w(0) <= result_exp_not_zero(0);
wire_w_result_exp_not_zero_range440w(0) <= result_exp_not_zero(1);
wire_w_result_exp_not_zero_range442w(0) <= result_exp_not_zero(2);
wire_w_result_exp_not_zero_range444w(0) <= result_exp_not_zero(3);
wire_w_result_exp_not_zero_range446w(0) <= result_exp_not_zero(4);
wire_w_result_exp_not_zero_range448w(0) <= result_exp_not_zero(5);
wire_w_result_exp_not_zero_range450w(0) <= result_exp_not_zero(6);
wire_w_result_exp_not_zero_range452w(0) <= result_exp_not_zero(7);
wire_w_result_exp_not_zero_range454w(0) <= result_exp_not_zero(8);
wire_w_sticky_bit_range306w(0) <= sticky_bit(0);
wire_w_sticky_bit_range336w(0) <= sticky_bit(10);
wire_w_sticky_bit_range339w(0) <= sticky_bit(11);
wire_w_sticky_bit_range342w(0) <= sticky_bit(12);
wire_w_sticky_bit_range345w(0) <= sticky_bit(13);
wire_w_sticky_bit_range348w(0) <= sticky_bit(14);
wire_w_sticky_bit_range351w(0) <= sticky_bit(15);
wire_w_sticky_bit_range354w(0) <= sticky_bit(16);
wire_w_sticky_bit_range357w(0) <= sticky_bit(17);
wire_w_sticky_bit_range360w(0) <= sticky_bit(18);
wire_w_sticky_bit_range363w(0) <= sticky_bit(19);
wire_w_sticky_bit_range309w(0) <= sticky_bit(1);
wire_w_sticky_bit_range366w(0) <= sticky_bit(20);
wire_w_sticky_bit_range369w(0) <= sticky_bit(21);
wire_w_sticky_bit_range312w(0) <= sticky_bit(2);
wire_w_sticky_bit_range315w(0) <= sticky_bit(3);
wire_w_sticky_bit_range318w(0) <= sticky_bit(4);
wire_w_sticky_bit_range321w(0) <= sticky_bit(5);
wire_w_sticky_bit_range324w(0) <= sticky_bit(6);
wire_w_sticky_bit_range327w(0) <= sticky_bit(7);
wire_w_sticky_bit_range330w(0) <= sticky_bit(8);
wire_w_sticky_bit_range333w(0) <= sticky_bit(9);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_exp_all_one_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_exp_all_one_ff_p1 <= dataa_exp_all_one(7);
END IF;
END IF;
END PROCESS;
wire_dataa_exp_all_one_ff_p1_w_lg_q296w(0) <= dataa_exp_all_one_ff_p1 AND wire_dataa_man_not_zero_ff_p1_w_lg_w_lg_q290w295w(0);
wire_dataa_exp_all_one_ff_p1_w_lg_q291w(0) <= dataa_exp_all_one_ff_p1 AND wire_dataa_man_not_zero_ff_p1_w_lg_q290w(0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_exp_not_zero_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_exp_not_zero_ff_p1 <= dataa_exp_not_zero(7);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_not_zero_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_not_zero_ff_p1 <= dataa_man_not_zero(10);
END IF;
END IF;
END PROCESS;
wire_dataa_man_not_zero_ff_p1_w_lg_w_lg_q290w295w(0) <= NOT wire_dataa_man_not_zero_ff_p1_w_lg_q290w(0);
wire_dataa_man_not_zero_ff_p1_w_lg_q290w(0) <= dataa_man_not_zero_ff_p1 OR dataa_man_not_zero_ff_p2;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_not_zero_ff_p2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_not_zero_ff_p2 <= dataa_man_not_zero(22);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_exp_all_one_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_exp_all_one_ff_p1 <= datab_exp_all_one(7);
END IF;
END IF;
END PROCESS;
wire_datab_exp_all_one_ff_p1_w_lg_q294w(0) <= datab_exp_all_one_ff_p1 AND wire_datab_man_not_zero_ff_p1_w_lg_w_lg_q288w293w(0);
wire_datab_exp_all_one_ff_p1_w_lg_q289w(0) <= datab_exp_all_one_ff_p1 AND wire_datab_man_not_zero_ff_p1_w_lg_q288w(0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_exp_not_zero_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_exp_not_zero_ff_p1 <= datab_exp_not_zero(7);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_not_zero_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_not_zero_ff_p1 <= datab_man_not_zero(10);
END IF;
END IF;
END PROCESS;
wire_datab_man_not_zero_ff_p1_w_lg_w_lg_q288w293w(0) <= NOT wire_datab_man_not_zero_ff_p1_w_lg_q288w(0);
wire_datab_man_not_zero_ff_p1_w_lg_q288w(0) <= datab_man_not_zero_ff_p1 OR datab_man_not_zero_ff_p2;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_not_zero_ff_p2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_not_zero_ff_p2 <= datab_man_not_zero(22);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_exp2_bias <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_exp2_bias <= delay_exp_bias;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_exp3_bias <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_exp3_bias <= delay_exp2_bias;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_exp_bias <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_exp_bias <= wire_exp_bias_subtr_result;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_man_product_msb <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_man_product_msb <= delay_man_product_msb_p1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_man_product_msb2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_man_product_msb2 <= delay_man_product_msb;
END IF;
END IF;
END PROCESS;
wire_delay_man_product_msb2_w_lg_q393w(0) <= delay_man_product_msb2 AND wire_man_round_p2_w_q_range391w(0);
wire_delay_man_product_msb2_w_lg_q395w(0) <= delay_man_product_msb2 XOR wire_man_round_p2_w_q_range391w(0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_man_product_msb_p0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_man_product_msb_p0 <= wire_man_product2_mult_w_result_range298w(0);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_man_product_msb_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_man_product_msb_p1 <= delay_man_product_msb_p0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_round <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_round <= wire_man_round_p2_w_lg_w_lg_w_q_range404w405w406w;
END IF;
END IF;
END PROCESS;
loop2 : FOR i IN 0 TO 21 GENERATE
wire_delay_round_w485w(i) <= wire_delay_round_w_lg_w_lg_w_lg_w_lg_w_q_range480w481w482w483w484w(i) AND wire_input_is_nan_ff5_w_lg_q479w(0);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 21 GENERATE
wire_delay_round_w_lg_w_lg_w_lg_w_lg_w_q_range480w481w482w483w484w(i) <= wire_delay_round_w_lg_w_lg_w_lg_w_q_range480w481w482w483w(i) AND wire_w_lg_exp_is_zero458w(0);
END GENERATE loop3;
wire_delay_round_w_lg_w_lg_w_lg_w_lg_w_q_range470w471w472w473w474w(0) <= wire_delay_round_w_lg_w_lg_w_lg_w_q_range470w471w472w473w(0) AND wire_w_lg_exp_is_zero458w(0);
loop4 : FOR i IN 0 TO 21 GENERATE
wire_delay_round_w_lg_w_lg_w_lg_w_q_range480w481w482w483w(i) <= wire_delay_round_w_lg_w_lg_w_q_range480w481w482w(i) AND wire_w_lg_exp_is_inf468w(0);
END GENERATE loop4;
wire_delay_round_w_lg_w_lg_w_lg_w_q_range470w471w472w473w(0) <= wire_delay_round_w_lg_w_lg_w_q_range470w471w472w(0) AND wire_w_lg_exp_is_inf468w(0);
loop5 : FOR i IN 0 TO 21 GENERATE
wire_delay_round_w_lg_w_lg_w_q_range480w481w482w(i) <= wire_delay_round_w_lg_w_q_range480w481w(i) AND wire_input_is_infinity_ff5_w_lg_q469w(0);
END GENERATE loop5;
wire_delay_round_w_lg_w_lg_w_q_range470w471w472w(0) <= wire_delay_round_w_lg_w_q_range470w471w(0) AND wire_input_is_infinity_ff5_w_lg_q469w(0);
loop6 : FOR i IN 0 TO 21 GENERATE
wire_delay_round_w_lg_w_q_range480w481w(i) <= wire_delay_round_w_q_range480w(i) AND input_not_zero_ff5;
END GENERATE loop6;
wire_delay_round_w_lg_w_q_range470w471w(0) <= wire_delay_round_w_q_range470w(0) AND input_not_zero_ff5;
wire_delay_round_w475w(0) <= wire_delay_round_w_lg_w_lg_w_lg_w_lg_w_q_range470w471w472w473w474w(0) OR wire_input_is_infinity_ff5_w_lg_q467w(0);
wire_delay_round_w_lg_w475w476w(0) <= wire_delay_round_w475w(0) OR input_is_nan_ff5;
wire_delay_round_w_q_range480w <= delay_round(21 DOWNTO 0);
wire_delay_round_w_q_range470w(0) <= delay_round(22);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_add_p1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_add_p1 <= wire_exp_add_adder_result;
END IF;
END IF;
END PROCESS;
wire_exp_add_p1_w_q_range63w <= exp_add_p1(8 DOWNTO 0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_p1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_p1 <= delay_exp3_bias;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_p2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_p2 <= wire_exp_adj_adder_result;
END IF;
END IF;
END PROCESS;
loop7 : FOR i IN 0 TO 7 GENERATE
wire_exp_adj_p2_w_lg_w_lg_w_q_range459w460w461w(i) <= wire_exp_adj_p2_w_lg_w_q_range459w460w(i) AND input_not_zero_ff5;
END GENERATE loop7;
loop8 : FOR i IN 0 TO 7 GENERATE
wire_exp_adj_p2_w_lg_w_q_range459w460w(i) <= wire_exp_adj_p2_w_q_range459w(i) AND wire_w_lg_exp_is_zero458w(0);
END GENERATE loop8;
wire_exp_adj_p2_w_lg_w_q_range432w457w(0) <= wire_exp_adj_p2_w_q_range432w(0) OR wire_w_lg_w_result_exp_not_zero_range454w456w(0);
wire_exp_adj_p2_w_q_range410w(0) <= exp_adj_p2(1);
wire_exp_adj_p2_w_q_range413w(0) <= exp_adj_p2(2);
wire_exp_adj_p2_w_q_range416w(0) <= exp_adj_p2(3);
wire_exp_adj_p2_w_q_range419w(0) <= exp_adj_p2(4);
wire_exp_adj_p2_w_q_range422w(0) <= exp_adj_p2(5);
wire_exp_adj_p2_w_q_range425w(0) <= exp_adj_p2(6);
wire_exp_adj_p2_w_q_range459w <= exp_adj_p2(7 DOWNTO 0);
wire_exp_adj_p2_w_q_range428w(0) <= exp_adj_p2(7);
wire_exp_adj_p2_w_q_range431w(0) <= exp_adj_p2(8);
wire_exp_adj_p2_w_q_range432w(0) <= exp_adj_p2(9);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_bias_p1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_bias_p1 <= wire_exp_add_p1_w_q_range63w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_bias_p2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_bias_p2 <= exp_bias_p1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_bias_p3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_bias_p3 <= exp_bias_p2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_result_ff <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_result_ff <= wire_w_lg_w_lg_inf_num464w465w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_dffe_0 <= (wire_dataa_exp_all_one_ff_p1_w_lg_q296w(0) OR wire_datab_exp_all_one_ff_p1_w_lg_q294w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_dffe_1 <= input_is_infinity_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_dffe_2 <= input_is_infinity_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_dffe_3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_dffe_3 <= input_is_infinity_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_ff1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_ff1 <= input_is_infinity_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_ff2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_ff2 <= input_is_infinity_ff1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_ff3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_ff3 <= input_is_infinity_ff2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_ff4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_ff4 <= input_is_infinity_ff3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_ff5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_ff5 <= input_is_infinity_ff4;
END IF;
END IF;
END PROCESS;
wire_input_is_infinity_ff5_w_lg_q467w(0) <= input_is_infinity_ff5 AND wire_input_not_zero_ff5_w_lg_q466w(0);
wire_input_is_infinity_ff5_w_lg_q469w(0) <= NOT input_is_infinity_ff5;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe_0 <= (wire_dataa_exp_all_one_ff_p1_w_lg_q291w(0) OR wire_datab_exp_all_one_ff_p1_w_lg_q289w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe_1 <= input_is_nan_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe_2 <= input_is_nan_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe_3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe_3 <= input_is_nan_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_ff1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_ff1 <= input_is_nan_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_ff2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_ff2 <= input_is_nan_ff1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_ff3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_ff3 <= input_is_nan_ff2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_ff4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_ff4 <= input_is_nan_ff3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_ff5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_ff5 <= input_is_nan_ff4;
END IF;
END IF;
END PROCESS;
wire_input_is_nan_ff5_w_lg_q479w(0) <= NOT input_is_nan_ff5;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_dffe_0 <= (dataa_exp_not_zero_ff_p1 AND datab_exp_not_zero_ff_p1);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_dffe_1 <= input_not_zero_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_dffe_2 <= input_not_zero_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_dffe_3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_dffe_3 <= input_not_zero_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_ff1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_ff1 <= input_not_zero_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_ff2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_ff2 <= input_not_zero_ff1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_ff3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_ff3 <= input_not_zero_ff2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_ff4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_ff4 <= input_not_zero_ff3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_ff5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_ff5 <= input_not_zero_ff4;
END IF;
END IF;
END PROCESS;
wire_input_not_zero_ff5_w_lg_q466w(0) <= NOT input_not_zero_ff5;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN lsb_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN lsb_dffe <= lsb_bit;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_result_ff <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_result_ff <= ( wire_delay_round_w_lg_w475w476w & wire_delay_round_w485w);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_carry <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_carry <= man_round_carry_p0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_carry_p0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_carry_p0 <= round_carry;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_p <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_p <= wire_w_man_shift_full_range379w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_p0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_p0 <= man_round_p;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_p1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_p1 <= man_round_p0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_p2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_p2 <= wire_man_round_adder_result;
END IF;
END IF;
END PROCESS;
loop9 : FOR i IN 0 TO 23 GENERATE
wire_man_round_p2_w_lg_w_q_range404w405w(i) <= wire_man_round_p2_w_q_range404w(i) AND wire_man_round_p2_w_lg_w_q_range391w403w(0);
END GENERATE loop9;
loop10 : FOR i IN 0 TO 23 GENERATE
wire_man_round_p2_w_lg_w_q_range401w402w(i) <= wire_man_round_p2_w_q_range401w(i) AND wire_man_round_p2_w_q_range391w(0);
END GENERATE loop10;
wire_man_round_p2_w_lg_w_q_range391w403w(0) <= NOT wire_man_round_p2_w_q_range391w(0);
loop11 : FOR i IN 0 TO 23 GENERATE
wire_man_round_p2_w_lg_w_lg_w_q_range404w405w406w(i) <= wire_man_round_p2_w_lg_w_q_range404w405w(i) OR wire_man_round_p2_w_lg_w_q_range401w402w(i);
END GENERATE loop11;
wire_man_round_p2_w_q_range404w <= man_round_p2(23 DOWNTO 0);
wire_man_round_p2_w_q_range401w <= man_round_p2(24 DOWNTO 1);
wire_man_round_p2_w_q_range391w(0) <= man_round_p2(24);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_dffe <= round_bit;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff0 <= (dataa(31) XOR datab(31));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff1 <= sign_node_ff0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff2 <= sign_node_ff1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff3 <= sign_node_ff2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff4 <= sign_node_ff3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff5 <= sign_node_ff4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff6 <= sign_node_ff5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff7 <= sign_node_ff6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff8 <= sign_node_ff7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff9 <= sign_node_ff8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff10 <= sign_node_ff9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_dffe <= sticky_bit(22);
END IF;
END IF;
END PROCESS;
wire_exp_add_adder_dataa <= ( "0" & dataa(30 DOWNTO 23));
wire_exp_add_adder_datab <= ( "0" & datab(30 DOWNTO 23));
exp_add_adder : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => wire_exp_add_adder_dataa,
datab => wire_exp_add_adder_datab,
result => wire_exp_add_adder_result
);
wire_exp_adj_adder_datab <= ( expmod(9 DOWNTO 0));
exp_adj_adder : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 0,
LPM_WIDTH => 10
)
PORT MAP (
cin => wire_gnd,
dataa => exp_adj_p1,
datab => wire_exp_adj_adder_datab,
result => wire_exp_adj_adder_result
);
wire_exp_bias_subtr_dataa <= ( "0" & exp_bias_p3);
wire_exp_bias_subtr_datab <= ( bias(9 DOWNTO 0));
exp_bias_subtr : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 0,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 10
)
PORT MAP (
dataa => wire_exp_bias_subtr_dataa,
datab => wire_exp_bias_subtr_datab,
result => wire_exp_bias_subtr_result
);
wire_man_round_adder_dataa <= ( "0" & man_round_p1);
wire_man_round_adder_datab <= ( "000000000000000000000000" & man_round_carry);
man_round_adder : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 0,
LPM_WIDTH => 25
)
PORT MAP (
dataa => wire_man_round_adder_dataa,
datab => wire_man_round_adder_datab,
result => wire_man_round_adder_result
);
loop12 : FOR i IN 0 TO 24 GENERATE
wire_man_product2_mult_w_lg_w_result_range302w303w(i) <= wire_man_product2_mult_w_result_range302w(i) AND wire_man_product2_mult_w_lg_w_result_range298w301w(0);
END GENERATE loop12;
loop13 : FOR i IN 0 TO 24 GENERATE
wire_man_product2_mult_w_lg_w_result_range299w300w(i) <= wire_man_product2_mult_w_result_range299w(i) AND wire_man_product2_mult_w_result_range298w(0);
END GENERATE loop13;
wire_man_product2_mult_w_lg_w_result_range298w373w(0) <= wire_man_product2_mult_w_result_range298w(0) AND wire_man_product2_mult_w_result_range371w(0);
wire_man_product2_mult_w_lg_w_result_range298w301w(0) <= NOT wire_man_product2_mult_w_result_range298w(0);
wire_man_product2_mult_dataa <= ( "1" & dataa(22 DOWNTO 0));
wire_man_product2_mult_datab <= ( "1" & datab(22 DOWNTO 0));
wire_man_product2_mult_w_result_range335w(0) <= wire_man_product2_mult_result(10);
wire_man_product2_mult_w_result_range338w(0) <= wire_man_product2_mult_result(11);
wire_man_product2_mult_w_result_range341w(0) <= wire_man_product2_mult_result(12);
wire_man_product2_mult_w_result_range344w(0) <= wire_man_product2_mult_result(13);
wire_man_product2_mult_w_result_range347w(0) <= wire_man_product2_mult_result(14);
wire_man_product2_mult_w_result_range350w(0) <= wire_man_product2_mult_result(15);
wire_man_product2_mult_w_result_range353w(0) <= wire_man_product2_mult_result(16);
wire_man_product2_mult_w_result_range356w(0) <= wire_man_product2_mult_result(17);
wire_man_product2_mult_w_result_range359w(0) <= wire_man_product2_mult_result(18);
wire_man_product2_mult_w_result_range362w(0) <= wire_man_product2_mult_result(19);
wire_man_product2_mult_w_result_range308w(0) <= wire_man_product2_mult_result(1);
wire_man_product2_mult_w_result_range365w(0) <= wire_man_product2_mult_result(20);
wire_man_product2_mult_w_result_range368w(0) <= wire_man_product2_mult_result(21);
wire_man_product2_mult_w_result_range371w(0) <= wire_man_product2_mult_result(22);
wire_man_product2_mult_w_result_range311w(0) <= wire_man_product2_mult_result(2);
wire_man_product2_mult_w_result_range314w(0) <= wire_man_product2_mult_result(3);
wire_man_product2_mult_w_result_range302w <= wire_man_product2_mult_result(46 DOWNTO 22);
wire_man_product2_mult_w_result_range299w <= wire_man_product2_mult_result(47 DOWNTO 23);
wire_man_product2_mult_w_result_range298w(0) <= wire_man_product2_mult_result(47);
wire_man_product2_mult_w_result_range317w(0) <= wire_man_product2_mult_result(4);
wire_man_product2_mult_w_result_range320w(0) <= wire_man_product2_mult_result(5);
wire_man_product2_mult_w_result_range323w(0) <= wire_man_product2_mult_result(6);
wire_man_product2_mult_w_result_range326w(0) <= wire_man_product2_mult_result(7);
wire_man_product2_mult_w_result_range329w(0) <= wire_man_product2_mult_result(8);
wire_man_product2_mult_w_result_range332w(0) <= wire_man_product2_mult_result(9);
man_product2_mult : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 5,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 24,
LPM_WIDTHB => 24,
LPM_WIDTHP => 48,
LPM_WIDTHS => 1,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_man_product2_mult_dataa,
datab => wire_man_product2_mult_datab,
result => wire_man_product2_mult_result
);
END RTL; --kn_kalman_mult_altfp_mult_oon
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END kn_kalman_mult;
ARCHITECTURE RTL OF kn_kalman_mult IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT kn_kalman_mult_altfp_mult_oon
PORT (
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
kn_kalman_mult_altfp_mult_oon_component : kn_kalman_mult_altfp_mult_oon
PORT MAP (
clock => clock,
dataa => dataa,
datab => datab,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: FPM_FORMAT STRING "Single"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: EXCEPTION_HANDLING STRING "NO"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_mult"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "11"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_mult.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_mult.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_mult.bsf TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_mult_inst.vhd TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_mult.inc FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_mult.cmp TRUE TRUE
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX NUMERIC "1"
-- Retrieval info: LIB_FILE: lpm
| mit | 108512d0b249a6be3ecdf133b498afed | 0.671663 | 2.452091 | false | false | false | false |
hoglet67/AtomVGAWing | src/DCM_A2.vhd | 1 | 2,571 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.4
-- \ \ Application : xaw2vhdl
-- / / Filename : DCM_A2.vhd
-- /___/ /\ Timestamp : 03/01/2013 22:02:25
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-intstyle /home/dmb/papilio/projects/VGATest/ipcore_dir/DCM_A2.xaw -st DCM_A2.vhd
--Design Name: DCM_A2
--Device: xc3s500e-5vq100
--
-- Module DCM_A2
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.97 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity DCM_A2 is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end DCM_A2;
architecture BEHAVIORAL of DCM_A2 is
signal CLKFX_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 23,
CLKFX_MULTIPLY => 13,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 22.500,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>GND_BIT,
CLKIN=>CLKIN_IN,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>open,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| gpl-3.0 | 1845e80d58cbdbdcb326c8434e4754a7 | 0.467522 | 3.715318 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt | kn_kalman_inv.vhd | 2 | 112,822 | -- megafunction wizard: %ALTFP_INV%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTFP_INV
-- ============================================================
-- File Name: kn_kalman_inv.vhd
-- Megafunction Name(s):
-- ALTFP_INV
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_inv CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=20 ROUNDING="TO_NEAREST" WIDTH_EXP=8 WIDTH_MAN=23 clock data result
--VERSION_BEGIN 11.1SP2 cbx_altfp_inv 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_mult 2012:01:25:21:13:53:SJ cbx_lpm_mux 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_padd 2012:01:25:21:13:53:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END
--altfp_inv_and_or CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" LUT_INPUT_COUNT=4 OPERATION="OR" PIPELINE=3 WIDTH=23 aclr clken clock data result
--VERSION_BEGIN 11.1SP2 cbx_altfp_inv 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_mult 2012:01:25:21:13:53:SJ cbx_lpm_mux 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_padd 2012:01:25:21:13:53:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END
--synthesis_resources = reg 9
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_inv_altfp_inv_and_or_6nd IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (22 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC
);
END kn_kalman_inv_altfp_inv_and_or_6nd;
ARCHITECTURE RTL OF kn_kalman_inv_altfp_inv_and_or_6nd IS
SIGNAL connection_dffe0 : STD_LOGIC_VECTOR(5 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL connection_dffe1 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL connection_dffe2 : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range303w307w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range331w335w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range337w340w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range339w343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range342w346w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range348w351w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range350w354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range353w357w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range306w310w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range359w362w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range361w365w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range309w313w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range315w318w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range317w321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range320w324w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range326w329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range328w332w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r2_w_range375w379w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r2_w_range378w382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r2_w_range381w385w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r2_w_range387w390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_lg_w_operation_r3_w_range395w399w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL connection_r0_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL connection_r1_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL connection_r2_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL connection_r3_w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL operation_r1_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL operation_r2_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL operation_r3_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range330w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range333w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range341w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range344w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range349w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range352w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range355w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range360w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range363w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range308w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range311w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range319w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range322w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r0_w_range327w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r1_w_range377w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r1_w_range380w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r1_w_range383w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r1_w_range388w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_connection_r2_w_range397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range303w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range331w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range339w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range348w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range350w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range353w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range359w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range361w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range309w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range315w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range317w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range320w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r1_w_range328w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r2_w_range375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r2_w_range378w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r2_w_range381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r2_w_range387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or2_w_operation_r3_w_range395w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range303w307w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range303w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range305w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range331w335w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range331w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range333w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range337w340w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range337w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range338w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range339w343w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range339w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range341w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range342w346w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range342w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range344w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range348w351w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range348w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range349w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range350w354w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range350w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range352w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range353w357w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range353w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range355w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range306w310w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range306w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range308w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range359w362w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range359w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range360w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range361w365w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range361w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range363w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range309w313w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range309w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range311w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range315w318w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range315w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range316w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range317w321w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range317w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range319w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range320w324w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range320w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range322w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range326w329w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range326w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range327w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range328w332w(0) <= wire_altfp_inv_and_or2_w_operation_r1_w_range328w(0) OR wire_altfp_inv_and_or2_w_connection_r0_w_range330w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r2_w_range375w379w(0) <= wire_altfp_inv_and_or2_w_operation_r2_w_range375w(0) OR wire_altfp_inv_and_or2_w_connection_r1_w_range377w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r2_w_range378w382w(0) <= wire_altfp_inv_and_or2_w_operation_r2_w_range378w(0) OR wire_altfp_inv_and_or2_w_connection_r1_w_range380w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r2_w_range381w385w(0) <= wire_altfp_inv_and_or2_w_operation_r2_w_range381w(0) OR wire_altfp_inv_and_or2_w_connection_r1_w_range383w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r2_w_range387w390w(0) <= wire_altfp_inv_and_or2_w_operation_r2_w_range387w(0) OR wire_altfp_inv_and_or2_w_connection_r1_w_range388w(0);
wire_altfp_inv_and_or2_w_lg_w_operation_r3_w_range395w399w(0) <= wire_altfp_inv_and_or2_w_operation_r3_w_range395w(0) OR wire_altfp_inv_and_or2_w_connection_r2_w_range397w(0);
connection_r0_w <= data;
connection_r1_w <= connection_dffe0;
connection_r2_w <= connection_dffe1;
connection_r3_w <= connection_dffe2;
operation_r1_w <= ( wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range361w365w & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range359w362w & connection_r0_w(20) & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range353w357w & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range350w354w & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range348w351w & connection_r0_w(16) & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range342w346w & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range339w343w & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range337w340w & connection_r0_w(12) & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range331w335w & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range328w332w & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range326w329w & connection_r0_w(8) & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range320w324w & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range317w321w & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range315w318w & connection_r0_w(4) & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range309w313w & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range306w310w & wire_altfp_inv_and_or2_w_lg_w_operation_r1_w_range303w307w & connection_r0_w(0));
operation_r2_w <= ( wire_altfp_inv_and_or2_w_lg_w_operation_r2_w_range387w390w & connection_r1_w(4) & wire_altfp_inv_and_or2_w_lg_w_operation_r2_w_range381w385w & wire_altfp_inv_and_or2_w_lg_w_operation_r2_w_range378w382w & wire_altfp_inv_and_or2_w_lg_w_operation_r2_w_range375w379w & connection_r1_w(0));
operation_r3_w <= ( wire_altfp_inv_and_or2_w_lg_w_operation_r3_w_range395w399w & connection_r2_w(0));
result <= connection_r3_w(0);
wire_altfp_inv_and_or2_w_connection_r0_w_range330w(0) <= connection_r0_w(10);
wire_altfp_inv_and_or2_w_connection_r0_w_range333w(0) <= connection_r0_w(11);
wire_altfp_inv_and_or2_w_connection_r0_w_range338w(0) <= connection_r0_w(13);
wire_altfp_inv_and_or2_w_connection_r0_w_range341w(0) <= connection_r0_w(14);
wire_altfp_inv_and_or2_w_connection_r0_w_range344w(0) <= connection_r0_w(15);
wire_altfp_inv_and_or2_w_connection_r0_w_range349w(0) <= connection_r0_w(17);
wire_altfp_inv_and_or2_w_connection_r0_w_range352w(0) <= connection_r0_w(18);
wire_altfp_inv_and_or2_w_connection_r0_w_range355w(0) <= connection_r0_w(19);
wire_altfp_inv_and_or2_w_connection_r0_w_range305w(0) <= connection_r0_w(1);
wire_altfp_inv_and_or2_w_connection_r0_w_range360w(0) <= connection_r0_w(21);
wire_altfp_inv_and_or2_w_connection_r0_w_range363w(0) <= connection_r0_w(22);
wire_altfp_inv_and_or2_w_connection_r0_w_range308w(0) <= connection_r0_w(2);
wire_altfp_inv_and_or2_w_connection_r0_w_range311w(0) <= connection_r0_w(3);
wire_altfp_inv_and_or2_w_connection_r0_w_range316w(0) <= connection_r0_w(5);
wire_altfp_inv_and_or2_w_connection_r0_w_range319w(0) <= connection_r0_w(6);
wire_altfp_inv_and_or2_w_connection_r0_w_range322w(0) <= connection_r0_w(7);
wire_altfp_inv_and_or2_w_connection_r0_w_range327w(0) <= connection_r0_w(9);
wire_altfp_inv_and_or2_w_connection_r1_w_range377w(0) <= connection_r1_w(1);
wire_altfp_inv_and_or2_w_connection_r1_w_range380w(0) <= connection_r1_w(2);
wire_altfp_inv_and_or2_w_connection_r1_w_range383w(0) <= connection_r1_w(3);
wire_altfp_inv_and_or2_w_connection_r1_w_range388w(0) <= connection_r1_w(5);
wire_altfp_inv_and_or2_w_connection_r2_w_range397w(0) <= connection_r2_w(1);
wire_altfp_inv_and_or2_w_operation_r1_w_range303w(0) <= operation_r1_w(0);
wire_altfp_inv_and_or2_w_operation_r1_w_range331w(0) <= operation_r1_w(10);
wire_altfp_inv_and_or2_w_operation_r1_w_range337w(0) <= operation_r1_w(12);
wire_altfp_inv_and_or2_w_operation_r1_w_range339w(0) <= operation_r1_w(13);
wire_altfp_inv_and_or2_w_operation_r1_w_range342w(0) <= operation_r1_w(14);
wire_altfp_inv_and_or2_w_operation_r1_w_range348w(0) <= operation_r1_w(16);
wire_altfp_inv_and_or2_w_operation_r1_w_range350w(0) <= operation_r1_w(17);
wire_altfp_inv_and_or2_w_operation_r1_w_range353w(0) <= operation_r1_w(18);
wire_altfp_inv_and_or2_w_operation_r1_w_range306w(0) <= operation_r1_w(1);
wire_altfp_inv_and_or2_w_operation_r1_w_range359w(0) <= operation_r1_w(20);
wire_altfp_inv_and_or2_w_operation_r1_w_range361w(0) <= operation_r1_w(21);
wire_altfp_inv_and_or2_w_operation_r1_w_range309w(0) <= operation_r1_w(2);
wire_altfp_inv_and_or2_w_operation_r1_w_range315w(0) <= operation_r1_w(4);
wire_altfp_inv_and_or2_w_operation_r1_w_range317w(0) <= operation_r1_w(5);
wire_altfp_inv_and_or2_w_operation_r1_w_range320w(0) <= operation_r1_w(6);
wire_altfp_inv_and_or2_w_operation_r1_w_range326w(0) <= operation_r1_w(8);
wire_altfp_inv_and_or2_w_operation_r1_w_range328w(0) <= operation_r1_w(9);
wire_altfp_inv_and_or2_w_operation_r2_w_range375w(0) <= operation_r2_w(0);
wire_altfp_inv_and_or2_w_operation_r2_w_range378w(0) <= operation_r2_w(1);
wire_altfp_inv_and_or2_w_operation_r2_w_range381w(0) <= operation_r2_w(2);
wire_altfp_inv_and_or2_w_operation_r2_w_range387w(0) <= operation_r2_w(4);
wire_altfp_inv_and_or2_w_operation_r3_w_range395w(0) <= operation_r3_w(0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN connection_dffe0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN connection_dffe0 <= ( operation_r1_w(22) & operation_r1_w(19) & operation_r1_w(15) & operation_r1_w(11) & operation_r1_w(7) & operation_r1_w(3));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN connection_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN connection_dffe1 <= ( operation_r2_w(5) & operation_r2_w(3));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN connection_dffe2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN connection_dffe2(0) <= ( operation_r3_w(1));
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_inv_altfp_inv_and_or_6nd
--altfp_inv_and_or CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" LUT_INPUT_COUNT=4 OPERATION="AND" PIPELINE=3 WIDTH=23 aclr clken clock data result
--VERSION_BEGIN 11.1SP2 cbx_altfp_inv 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_mult 2012:01:25:21:13:53:SJ cbx_lpm_mux 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_padd 2012:01:25:21:13:53:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END
--synthesis_resources = reg 9
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_inv_altfp_inv_and_or_opd IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (22 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC
);
END kn_kalman_inv_altfp_inv_and_or_opd;
ARCHITECTURE RTL OF kn_kalman_inv_altfp_inv_and_or_opd IS
SIGNAL connection_dffe0 : STD_LOGIC_VECTOR(5 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL connection_dffe1 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL connection_dffe2 : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range404w408w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range432w436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range438w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range440w444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range443w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range449w452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range451w455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range454w458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range407w411w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range460w463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range462w466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range410w414w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range416w419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range418w422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range421w425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range427w430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range429w433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r2_w_range476w480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r2_w_range479w483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r2_w_range482w486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r2_w_range488w491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_lg_w_operation_r3_w_range496w500w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL connection_r0_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL connection_r1_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL connection_r2_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL connection_r3_w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL operation_r1_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL operation_r2_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL operation_r3_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range406w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range409w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range412w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r0_w_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r1_w_range478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r1_w_range481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r1_w_range484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r1_w_range489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_connection_r2_w_range498w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range404w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range410w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range418w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r1_w_range429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r2_w_range476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r2_w_range479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r2_w_range482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r2_w_range488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or3_w_operation_r3_w_range496w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range404w408w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range404w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range406w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range432w436w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range432w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range434w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range438w441w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range438w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range439w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range440w444w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range440w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range442w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range443w447w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range443w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range445w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range449w452w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range449w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range450w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range451w455w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range451w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range453w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range454w458w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range454w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range456w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range407w411w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range407w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range409w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range460w463w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range460w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range461w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range462w466w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range462w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range464w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range410w414w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range410w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range412w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range416w419w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range416w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range417w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range418w422w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range418w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range420w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range421w425w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range421w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range423w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range427w430w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range427w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range428w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range429w433w(0) <= wire_altfp_inv_and_or3_w_operation_r1_w_range429w(0) AND wire_altfp_inv_and_or3_w_connection_r0_w_range431w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r2_w_range476w480w(0) <= wire_altfp_inv_and_or3_w_operation_r2_w_range476w(0) AND wire_altfp_inv_and_or3_w_connection_r1_w_range478w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r2_w_range479w483w(0) <= wire_altfp_inv_and_or3_w_operation_r2_w_range479w(0) AND wire_altfp_inv_and_or3_w_connection_r1_w_range481w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r2_w_range482w486w(0) <= wire_altfp_inv_and_or3_w_operation_r2_w_range482w(0) AND wire_altfp_inv_and_or3_w_connection_r1_w_range484w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r2_w_range488w491w(0) <= wire_altfp_inv_and_or3_w_operation_r2_w_range488w(0) AND wire_altfp_inv_and_or3_w_connection_r1_w_range489w(0);
wire_altfp_inv_and_or3_w_lg_w_operation_r3_w_range496w500w(0) <= wire_altfp_inv_and_or3_w_operation_r3_w_range496w(0) AND wire_altfp_inv_and_or3_w_connection_r2_w_range498w(0);
connection_r0_w <= data;
connection_r1_w <= connection_dffe0;
connection_r2_w <= connection_dffe1;
connection_r3_w <= connection_dffe2;
operation_r1_w <= ( wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range462w466w & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range460w463w & connection_r0_w(20) & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range454w458w & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range451w455w & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range449w452w & connection_r0_w(16) & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range443w447w & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range440w444w & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range438w441w & connection_r0_w(12) & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range432w436w & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range429w433w & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range427w430w & connection_r0_w(8) & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range421w425w & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range418w422w & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range416w419w & connection_r0_w(4) & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range410w414w & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range407w411w & wire_altfp_inv_and_or3_w_lg_w_operation_r1_w_range404w408w & connection_r0_w(0));
operation_r2_w <= ( wire_altfp_inv_and_or3_w_lg_w_operation_r2_w_range488w491w & connection_r1_w(4) & wire_altfp_inv_and_or3_w_lg_w_operation_r2_w_range482w486w & wire_altfp_inv_and_or3_w_lg_w_operation_r2_w_range479w483w & wire_altfp_inv_and_or3_w_lg_w_operation_r2_w_range476w480w & connection_r1_w(0));
operation_r3_w <= ( wire_altfp_inv_and_or3_w_lg_w_operation_r3_w_range496w500w & connection_r2_w(0));
result <= connection_r3_w(0);
wire_altfp_inv_and_or3_w_connection_r0_w_range431w(0) <= connection_r0_w(10);
wire_altfp_inv_and_or3_w_connection_r0_w_range434w(0) <= connection_r0_w(11);
wire_altfp_inv_and_or3_w_connection_r0_w_range439w(0) <= connection_r0_w(13);
wire_altfp_inv_and_or3_w_connection_r0_w_range442w(0) <= connection_r0_w(14);
wire_altfp_inv_and_or3_w_connection_r0_w_range445w(0) <= connection_r0_w(15);
wire_altfp_inv_and_or3_w_connection_r0_w_range450w(0) <= connection_r0_w(17);
wire_altfp_inv_and_or3_w_connection_r0_w_range453w(0) <= connection_r0_w(18);
wire_altfp_inv_and_or3_w_connection_r0_w_range456w(0) <= connection_r0_w(19);
wire_altfp_inv_and_or3_w_connection_r0_w_range406w(0) <= connection_r0_w(1);
wire_altfp_inv_and_or3_w_connection_r0_w_range461w(0) <= connection_r0_w(21);
wire_altfp_inv_and_or3_w_connection_r0_w_range464w(0) <= connection_r0_w(22);
wire_altfp_inv_and_or3_w_connection_r0_w_range409w(0) <= connection_r0_w(2);
wire_altfp_inv_and_or3_w_connection_r0_w_range412w(0) <= connection_r0_w(3);
wire_altfp_inv_and_or3_w_connection_r0_w_range417w(0) <= connection_r0_w(5);
wire_altfp_inv_and_or3_w_connection_r0_w_range420w(0) <= connection_r0_w(6);
wire_altfp_inv_and_or3_w_connection_r0_w_range423w(0) <= connection_r0_w(7);
wire_altfp_inv_and_or3_w_connection_r0_w_range428w(0) <= connection_r0_w(9);
wire_altfp_inv_and_or3_w_connection_r1_w_range478w(0) <= connection_r1_w(1);
wire_altfp_inv_and_or3_w_connection_r1_w_range481w(0) <= connection_r1_w(2);
wire_altfp_inv_and_or3_w_connection_r1_w_range484w(0) <= connection_r1_w(3);
wire_altfp_inv_and_or3_w_connection_r1_w_range489w(0) <= connection_r1_w(5);
wire_altfp_inv_and_or3_w_connection_r2_w_range498w(0) <= connection_r2_w(1);
wire_altfp_inv_and_or3_w_operation_r1_w_range404w(0) <= operation_r1_w(0);
wire_altfp_inv_and_or3_w_operation_r1_w_range432w(0) <= operation_r1_w(10);
wire_altfp_inv_and_or3_w_operation_r1_w_range438w(0) <= operation_r1_w(12);
wire_altfp_inv_and_or3_w_operation_r1_w_range440w(0) <= operation_r1_w(13);
wire_altfp_inv_and_or3_w_operation_r1_w_range443w(0) <= operation_r1_w(14);
wire_altfp_inv_and_or3_w_operation_r1_w_range449w(0) <= operation_r1_w(16);
wire_altfp_inv_and_or3_w_operation_r1_w_range451w(0) <= operation_r1_w(17);
wire_altfp_inv_and_or3_w_operation_r1_w_range454w(0) <= operation_r1_w(18);
wire_altfp_inv_and_or3_w_operation_r1_w_range407w(0) <= operation_r1_w(1);
wire_altfp_inv_and_or3_w_operation_r1_w_range460w(0) <= operation_r1_w(20);
wire_altfp_inv_and_or3_w_operation_r1_w_range462w(0) <= operation_r1_w(21);
wire_altfp_inv_and_or3_w_operation_r1_w_range410w(0) <= operation_r1_w(2);
wire_altfp_inv_and_or3_w_operation_r1_w_range416w(0) <= operation_r1_w(4);
wire_altfp_inv_and_or3_w_operation_r1_w_range418w(0) <= operation_r1_w(5);
wire_altfp_inv_and_or3_w_operation_r1_w_range421w(0) <= operation_r1_w(6);
wire_altfp_inv_and_or3_w_operation_r1_w_range427w(0) <= operation_r1_w(8);
wire_altfp_inv_and_or3_w_operation_r1_w_range429w(0) <= operation_r1_w(9);
wire_altfp_inv_and_or3_w_operation_r2_w_range476w(0) <= operation_r2_w(0);
wire_altfp_inv_and_or3_w_operation_r2_w_range479w(0) <= operation_r2_w(1);
wire_altfp_inv_and_or3_w_operation_r2_w_range482w(0) <= operation_r2_w(2);
wire_altfp_inv_and_or3_w_operation_r2_w_range488w(0) <= operation_r2_w(4);
wire_altfp_inv_and_or3_w_operation_r3_w_range496w(0) <= operation_r3_w(0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN connection_dffe0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN connection_dffe0 <= ( operation_r1_w(22) & operation_r1_w(19) & operation_r1_w(15) & operation_r1_w(11) & operation_r1_w(7) & operation_r1_w(3));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN connection_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN connection_dffe1 <= ( operation_r2_w(5) & operation_r2_w(3));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN connection_dffe2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN connection_dffe2(0) <= ( operation_r3_w(1));
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_inv_altfp_inv_and_or_opd
--altfp_inv_and_or CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" LUT_INPUT_COUNT=4 OPERATION="OR" PIPELINE=3 WIDTH=8 aclr clken clock data result
--VERSION_BEGIN 11.1SP2 cbx_altfp_inv 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_mult 2012:01:25:21:13:53:SJ cbx_lpm_mux 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_padd 2012:01:25:21:13:53:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END
--synthesis_resources = reg 4
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_inv_altfp_inv_and_or_pld IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC
);
END kn_kalman_inv_altfp_inv_and_or_pld;
ARCHITECTURE RTL OF kn_kalman_inv_altfp_inv_and_or_pld IS
SIGNAL connection_dffe0 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL connection_dffe1 : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL connection_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range505w509w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range508w512w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range511w515w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range517w520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range519w523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range522w526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_lg_w_operation_r2_w_range532w536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL connection_r0_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL connection_r1_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL connection_r2_w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL operation_r1_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL operation_r2_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_connection_r0_w_range507w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_connection_r0_w_range510w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_connection_r0_w_range513w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_connection_r0_w_range518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_connection_r0_w_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_connection_r0_w_range524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_connection_r1_w_range534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_operation_r1_w_range505w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_operation_r1_w_range508w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_operation_r1_w_range511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_operation_r1_w_range517w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_operation_r1_w_range519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_operation_r1_w_range522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or4_w_operation_r2_w_range532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range505w509w(0) <= wire_altfp_inv_and_or4_w_operation_r1_w_range505w(0) OR wire_altfp_inv_and_or4_w_connection_r0_w_range507w(0);
wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range508w512w(0) <= wire_altfp_inv_and_or4_w_operation_r1_w_range508w(0) OR wire_altfp_inv_and_or4_w_connection_r0_w_range510w(0);
wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range511w515w(0) <= wire_altfp_inv_and_or4_w_operation_r1_w_range511w(0) OR wire_altfp_inv_and_or4_w_connection_r0_w_range513w(0);
wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range517w520w(0) <= wire_altfp_inv_and_or4_w_operation_r1_w_range517w(0) OR wire_altfp_inv_and_or4_w_connection_r0_w_range518w(0);
wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range519w523w(0) <= wire_altfp_inv_and_or4_w_operation_r1_w_range519w(0) OR wire_altfp_inv_and_or4_w_connection_r0_w_range521w(0);
wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range522w526w(0) <= wire_altfp_inv_and_or4_w_operation_r1_w_range522w(0) OR wire_altfp_inv_and_or4_w_connection_r0_w_range524w(0);
wire_altfp_inv_and_or4_w_lg_w_operation_r2_w_range532w536w(0) <= wire_altfp_inv_and_or4_w_operation_r2_w_range532w(0) OR wire_altfp_inv_and_or4_w_connection_r1_w_range534w(0);
connection_r0_w <= data;
connection_r1_w <= connection_dffe0;
connection_r2_w <= connection_dffe1;
operation_r1_w <= ( wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range522w526w & wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range519w523w & wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range517w520w & connection_r0_w(4) & wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range511w515w & wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range508w512w & wire_altfp_inv_and_or4_w_lg_w_operation_r1_w_range505w509w & connection_r0_w(0));
operation_r2_w <= ( wire_altfp_inv_and_or4_w_lg_w_operation_r2_w_range532w536w & connection_r1_w(0));
result <= connection_dffe2;
wire_altfp_inv_and_or4_w_connection_r0_w_range507w(0) <= connection_r0_w(1);
wire_altfp_inv_and_or4_w_connection_r0_w_range510w(0) <= connection_r0_w(2);
wire_altfp_inv_and_or4_w_connection_r0_w_range513w(0) <= connection_r0_w(3);
wire_altfp_inv_and_or4_w_connection_r0_w_range518w(0) <= connection_r0_w(5);
wire_altfp_inv_and_or4_w_connection_r0_w_range521w(0) <= connection_r0_w(6);
wire_altfp_inv_and_or4_w_connection_r0_w_range524w(0) <= connection_r0_w(7);
wire_altfp_inv_and_or4_w_connection_r1_w_range534w(0) <= connection_r1_w(1);
wire_altfp_inv_and_or4_w_operation_r1_w_range505w(0) <= operation_r1_w(0);
wire_altfp_inv_and_or4_w_operation_r1_w_range508w(0) <= operation_r1_w(1);
wire_altfp_inv_and_or4_w_operation_r1_w_range511w(0) <= operation_r1_w(2);
wire_altfp_inv_and_or4_w_operation_r1_w_range517w(0) <= operation_r1_w(4);
wire_altfp_inv_and_or4_w_operation_r1_w_range519w(0) <= operation_r1_w(5);
wire_altfp_inv_and_or4_w_operation_r1_w_range522w(0) <= operation_r1_w(6);
wire_altfp_inv_and_or4_w_operation_r2_w_range532w(0) <= operation_r2_w(0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN connection_dffe0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN connection_dffe0 <= ( operation_r1_w(7) & operation_r1_w(3));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN connection_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN connection_dffe1(0) <= ( operation_r2_w(1));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN connection_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN connection_dffe2 <= connection_r2_w(0);
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_inv_altfp_inv_and_or_pld
--altfp_inv_and_or CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" LUT_INPUT_COUNT=4 OPERATION="AND" PIPELINE=3 WIDTH=8 aclr clken clock data result
--VERSION_BEGIN 11.1SP2 cbx_altfp_inv 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_mult 2012:01:25:21:13:53:SJ cbx_lpm_mux 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_padd 2012:01:25:21:13:53:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END
--synthesis_resources = reg 4
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_inv_altfp_inv_and_or_bod IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC
);
END kn_kalman_inv_altfp_inv_and_or_bod;
ARCHITECTURE RTL OF kn_kalman_inv_altfp_inv_and_or_bod IS
SIGNAL connection_dffe0 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL connection_dffe1 : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL connection_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range541w545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range544w548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range547w551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range553w556w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range555w559w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range558w562w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_lg_w_operation_r2_w_range568w572w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL connection_r0_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL connection_r1_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL connection_r2_w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL operation_r1_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL operation_r2_w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_connection_r0_w_range543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_connection_r0_w_range546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_connection_r0_w_range549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_connection_r0_w_range554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_connection_r0_w_range557w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_connection_r0_w_range560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_connection_r1_w_range570w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_operation_r1_w_range541w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_operation_r1_w_range544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_operation_r1_w_range547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_operation_r1_w_range553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_operation_r1_w_range555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_operation_r1_w_range558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altfp_inv_and_or5_w_operation_r2_w_range568w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range541w545w(0) <= wire_altfp_inv_and_or5_w_operation_r1_w_range541w(0) AND wire_altfp_inv_and_or5_w_connection_r0_w_range543w(0);
wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range544w548w(0) <= wire_altfp_inv_and_or5_w_operation_r1_w_range544w(0) AND wire_altfp_inv_and_or5_w_connection_r0_w_range546w(0);
wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range547w551w(0) <= wire_altfp_inv_and_or5_w_operation_r1_w_range547w(0) AND wire_altfp_inv_and_or5_w_connection_r0_w_range549w(0);
wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range553w556w(0) <= wire_altfp_inv_and_or5_w_operation_r1_w_range553w(0) AND wire_altfp_inv_and_or5_w_connection_r0_w_range554w(0);
wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range555w559w(0) <= wire_altfp_inv_and_or5_w_operation_r1_w_range555w(0) AND wire_altfp_inv_and_or5_w_connection_r0_w_range557w(0);
wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range558w562w(0) <= wire_altfp_inv_and_or5_w_operation_r1_w_range558w(0) AND wire_altfp_inv_and_or5_w_connection_r0_w_range560w(0);
wire_altfp_inv_and_or5_w_lg_w_operation_r2_w_range568w572w(0) <= wire_altfp_inv_and_or5_w_operation_r2_w_range568w(0) AND wire_altfp_inv_and_or5_w_connection_r1_w_range570w(0);
connection_r0_w <= data;
connection_r1_w <= connection_dffe0;
connection_r2_w <= connection_dffe1;
operation_r1_w <= ( wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range558w562w & wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range555w559w & wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range553w556w & connection_r0_w(4) & wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range547w551w & wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range544w548w & wire_altfp_inv_and_or5_w_lg_w_operation_r1_w_range541w545w & connection_r0_w(0));
operation_r2_w <= ( wire_altfp_inv_and_or5_w_lg_w_operation_r2_w_range568w572w & connection_r1_w(0));
result <= connection_dffe2;
wire_altfp_inv_and_or5_w_connection_r0_w_range543w(0) <= connection_r0_w(1);
wire_altfp_inv_and_or5_w_connection_r0_w_range546w(0) <= connection_r0_w(2);
wire_altfp_inv_and_or5_w_connection_r0_w_range549w(0) <= connection_r0_w(3);
wire_altfp_inv_and_or5_w_connection_r0_w_range554w(0) <= connection_r0_w(5);
wire_altfp_inv_and_or5_w_connection_r0_w_range557w(0) <= connection_r0_w(6);
wire_altfp_inv_and_or5_w_connection_r0_w_range560w(0) <= connection_r0_w(7);
wire_altfp_inv_and_or5_w_connection_r1_w_range570w(0) <= connection_r1_w(1);
wire_altfp_inv_and_or5_w_operation_r1_w_range541w(0) <= operation_r1_w(0);
wire_altfp_inv_and_or5_w_operation_r1_w_range544w(0) <= operation_r1_w(1);
wire_altfp_inv_and_or5_w_operation_r1_w_range547w(0) <= operation_r1_w(2);
wire_altfp_inv_and_or5_w_operation_r1_w_range553w(0) <= operation_r1_w(4);
wire_altfp_inv_and_or5_w_operation_r1_w_range555w(0) <= operation_r1_w(5);
wire_altfp_inv_and_or5_w_operation_r1_w_range558w(0) <= operation_r1_w(6);
wire_altfp_inv_and_or5_w_operation_r2_w_range568w(0) <= operation_r2_w(0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN connection_dffe0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN connection_dffe0 <= ( operation_r1_w(7) & operation_r1_w(3));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN connection_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN connection_dffe1(0) <= ( operation_r2_w(1));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN connection_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN connection_dffe2 <= connection_r2_w(0);
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_inv_altfp_inv_and_or_bod
--altfp_inv_csa CARRY_SELECT="YES" CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" DIRECTION="SUB" PIPELINE=1 REGISTER_INPUT="NO" REPRESENTATION="UNSIGNED" WIDTH=26 aclr clken clock dataa datab result
--VERSION_BEGIN 11.1SP2 cbx_altfp_inv 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_mult 2012:01:25:21:13:53:SJ cbx_lpm_mux 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_padd 2012:01:25:21:13:53:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 3
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_inv_altfp_inv_csa_pei IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR (25 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR (25 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END kn_kalman_inv_altfp_inv_csa_pei;
ARCHITECTURE RTL OF kn_kalman_inv_altfp_inv_csa_pei IS
SIGNAL wire_csa_lower_w_lg_w_lg_cout583w584w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_csa_lower_w_lg_cout582w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_csa_lower_w_lg_cout583w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_csa_lower_w_lg_w_lg_w_lg_cout583w584w585w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_csa_lower_cout : STD_LOGIC;
SIGNAL wire_csa_lower_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_csa_upper0_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_csa_upper1_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL dataa_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL result_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
wire_vcc <= '1';
dataa_w <= dataa;
datab_w <= datab;
result <= result_w;
result_w <= ( wire_csa_lower_w_lg_w_lg_w_lg_cout583w584w585w & wire_csa_lower_result);
loop0 : FOR i IN 0 TO 12 GENERATE
wire_csa_lower_w_lg_w_lg_cout583w584w(i) <= wire_csa_lower_w_lg_cout583w(0) AND wire_csa_upper0_result(i);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 12 GENERATE
wire_csa_lower_w_lg_cout582w(i) <= wire_csa_lower_cout AND wire_csa_upper1_result(i);
END GENERATE loop1;
wire_csa_lower_w_lg_cout583w(0) <= NOT wire_csa_lower_cout;
loop2 : FOR i IN 0 TO 12 GENERATE
wire_csa_lower_w_lg_w_lg_w_lg_cout583w584w585w(i) <= wire_csa_lower_w_lg_w_lg_cout583w584w(i) OR wire_csa_lower_w_lg_cout582w(i);
END GENERATE loop2;
csa_lower : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 13
)
PORT MAP (
aclr => aclr,
clken => clken,
clock => clock,
cout => wire_csa_lower_cout,
dataa => dataa_w(12 DOWNTO 0),
datab => datab_w(12 DOWNTO 0),
result => wire_csa_lower_result
);
csa_upper0 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 13
)
PORT MAP (
aclr => aclr,
cin => wire_gnd,
clken => clken,
clock => clock,
dataa => dataa_w(25 DOWNTO 13),
datab => datab_w(25 DOWNTO 13),
result => wire_csa_upper0_result
);
csa_upper1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 13
)
PORT MAP (
aclr => aclr,
cin => wire_vcc,
clken => clken,
clock => clock,
dataa => dataa_w(25 DOWNTO 13),
datab => datab_w(25 DOWNTO 13),
result => wire_csa_upper1_result
);
END RTL; --kn_kalman_inv_altfp_inv_csa_pei
--altfp_inv_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" DIRECTION="ADD" PIPELINE=1 REGISTER_INPUT="NO" REPRESENTATION="UNSIGNED" WIDTH=13 aclr clken clock dataa datab result
--VERSION_BEGIN 11.1SP2 cbx_altfp_inv 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_mult 2012:01:25:21:13:53:SJ cbx_lpm_mux 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_padd 2012:01:25:21:13:53:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_inv_altfp_inv_csa_0ai IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR (12 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR (12 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
);
END kn_kalman_inv_altfp_inv_csa_0ai;
ARCHITECTURE RTL OF kn_kalman_inv_altfp_inv_csa_0ai IS
SIGNAL wire_add_sub7_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL dataa_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL datab_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL result_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataa_w <= dataa;
datab_w <= datab;
result <= result_w;
result_w <= wire_add_sub7_result;
add_sub7 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 13
)
PORT MAP (
aclr => aclr,
clken => clken,
clock => clock,
dataa => dataa_w,
datab => datab_w,
result => wire_add_sub7_result
);
END RTL; --kn_kalman_inv_altfp_inv_csa_0ai
--altfp_inv_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" DIRECTION="SUB" PIPELINE=1 REGISTER_INPUT="NO" REPRESENTATION="UNSIGNED" WIDTH=13 aclr clken clock dataa datab result
--VERSION_BEGIN 11.1SP2 cbx_altfp_inv 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_mult 2012:01:25:21:13:53:SJ cbx_lpm_mux 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_padd 2012:01:25:21:13:53:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_inv_altfp_inv_csa_1bi IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR (12 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR (12 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
);
END kn_kalman_inv_altfp_inv_csa_1bi;
ARCHITECTURE RTL OF kn_kalman_inv_altfp_inv_csa_1bi IS
SIGNAL wire_add_sub8_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL dataa_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL datab_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL result_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataa_w <= dataa;
datab_w <= datab;
result <= result_w;
result_w <= wire_add_sub8_result;
add_sub8 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 13
)
PORT MAP (
aclr => aclr,
clken => clken,
clock => clock,
dataa => dataa_w,
datab => datab_w,
result => wire_add_sub8_result
);
END RTL; --kn_kalman_inv_altfp_inv_csa_1bi
LIBRARY lpm;
USE lpm.lpm_components.all;
--synthesis_resources = lpm_add_sub 15 lpm_compare 1 lpm_mult 4 lpm_mux 1 reg 755
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_inv_altfp_inv_rhc IS
PORT
(
clock : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END kn_kalman_inv_altfp_inv_rhc;
ARCHITECTURE RTL OF kn_kalman_inv_altfp_inv_rhc IS
SIGNAL wire_altfp_inv_and_or2_result : STD_LOGIC;
SIGNAL wire_altfp_inv_and_or3_result : STD_LOGIC;
SIGNAL wire_altfp_inv_and_or4_result : STD_LOGIC;
SIGNAL wire_altfp_inv_and_or5_result : STD_LOGIC;
SIGNAL wire_diff_adder_0_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_diff_adder_1_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_slope_r1c1_add_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_slope_r1c2_add_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_slope_r1c3_add_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_slope_r2c1_add_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_slope_r2c2_add_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_slope_r3c1_add_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL and_dffe_0 : STD_LOGIC_VECTOR(12 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL and_dffe_1 : STD_LOGIC_VECTOR(12 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL and_dffe_2 : STD_LOGIC_VECTOR(12 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL and_dffe_3 : STD_LOGIC_VECTOR(12 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL and_dffe_4 : STD_LOGIC_VECTOR(12 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL and_dffe_5 : STD_LOGIC_VECTOR(12 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL division_by_zero_dffe : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe1_0 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe1_1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe1_10 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe1_11 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe1_12 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe1_13 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe1_14 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe1_2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe1_3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe1_4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe1_5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe1_6 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe1_7 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe1_8 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe1_9 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe2_0 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe2_1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_dffe2_2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL infinite_dffe : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL infinite_input_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL intercept_dffe : STD_LOGIC_VECTOR(9 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_dffe_0 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_dffe_1 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_dffe_10 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_dffe_11 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_dffe_2 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_dffe_3 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_dffe_4 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_dffe_5 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_dffe_6 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_dffe_7 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_dffe_8 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_dffe_9 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL nan_dffe : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL nan_input_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL result_output_dffe : STD_LOGIC_VECTOR(31 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sign_dffe : STD_LOGIC_VECTOR(18 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL underflow_dffe : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_dffe_0 : STD_LOGIC_VECTOR(12 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_dffe_1 : STD_LOGIC_VECTOR(12 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_dffe_2 : STD_LOGIC_VECTOR(12 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_dffe_3 : STD_LOGIC_VECTOR(12 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_dffe_4 : STD_LOGIC_VECTOR(24 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_dffe_5 : STD_LOGIC_VECTOR(24 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_dffe_6 : STD_LOGIC_VECTOR(24 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_dffe_7 : STD_LOGIC_VECTOR(24 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL zero_dffe : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL zero_input_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_approx_sub_result : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_bias_adjustment_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_bias_adjustment_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_bias_adjustment_w_result_range267w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_modified_add_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_cmpr6_ageb : STD_LOGIC;
SIGNAL wire_cmpr6_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_inner_mult0_result : STD_LOGIC_VECTOR (36 DOWNTO 0);
SIGNAL wire_inner_mult1_result : STD_LOGIC_VECTOR (48 DOWNTO 0);
SIGNAL wire_outer_mult0_result : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL wire_outer_mult1_result : STD_LOGIC_VECTOR (49 DOWNTO 0);
SIGNAL wire_mux1_data_2d : STD_LOGIC_2D(31 DOWNTO 0, 15 DOWNTO 0);
SIGNAL wire_mux1_result : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_mux1_w_result_range183w : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_infinite_out_w290w291w : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_man_zero_w215w216w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_nan_out_w298w299w : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_zero_out_w294w295w : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_w_lg_infinite_out_w292w : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_w_lg_man_zero_w214w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_w_lg_nan_out_w300w : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_w_lg_zero_out_w296w : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_w_lg_w_slope_w_range171w172w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL wire_w_lg_w_slope_w_range164w165w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL wire_w_lg_w_slope_w_range156w157w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL wire_w_lg_w_slope_w_range148w149w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL wire_w_lg_w_slope_w_range140w141w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL wire_w_lg_w_slope_w_range132w133w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL wire_w_lg_exp_or_msb_w204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_infinite_input_w221w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_infinite_out_w290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_or_msb_w203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_zero_w215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nan_input_w212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_nan_out_w298w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_zero_out_w294w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL aclr : STD_LOGIC;
SIGNAL and_b0_w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL and_b1_w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL and_b2_w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL and_b3_w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL and_b4_w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL and_b5_w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL approx_c_w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL approx_mx_w : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL approx_y_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL c_offset_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL clk_en : STD_LOGIC;
SIGNAL const_2_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL const_bias_adj_greater_one_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL const_bias_adj_one_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL const_bias_adj_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL data_exp_bus_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL data_man_bus_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL data_sign_w : STD_LOGIC;
SIGNAL division_by_zero_w : STD_LOGIC;
SIGNAL exp_and_msb_w : STD_LOGIC;
SIGNAL exp_bus_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_exc_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_exc_zeros_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_one_w : STD_LOGIC;
SIGNAL exp_or_msb_w : STD_LOGIC;
SIGNAL exp_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_zero_w : STD_LOGIC;
SIGNAL gnd_w : STD_LOGIC;
SIGNAL infi_res_w : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL infinite_input_w : STD_LOGIC;
SIGNAL infinite_out_w : STD_LOGIC;
SIGNAL infinite_w : STD_LOGIC;
SIGNAL man_and_msb_w : STD_LOGIC;
SIGNAL man_bus_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_exc_nan_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_exc_zeros_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_non_zero_w : STD_LOGIC;
SIGNAL man_one_w : STD_LOGIC;
SIGNAL man_or_msb_w : STD_LOGIC;
SIGNAL man_out_0_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_out_1_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_res_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_zero_w : STD_LOGIC;
SIGNAL modified_c_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL mux_1_res_w : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL mux_2_res_w : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL mux_3_res_w : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL nan_input_w : STD_LOGIC;
SIGNAL nan_out_w : STD_LOGIC;
SIGNAL nan_res_w : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL nan_w : STD_LOGIC;
SIGNAL norm_res_int_w : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL shift_b0_w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL shift_b1_w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL shift_b2_w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL shift_b3_w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL shift_b4_w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL shift_b5_w : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL sign_exc_bit_w : STD_LOGIC;
SIGNAL sign_res_w : STD_LOGIC;
SIGNAL slope_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL table_bus_full_w : STD_LOGIC_VECTOR (511 DOWNTO 0);
SIGNAL underflow_w : STD_LOGIC;
SIGNAL vcc_w : STD_LOGIC;
SIGNAL x_0_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL x_1_w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL x_2_w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL x_initial_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL zero_input_w : STD_LOGIC;
SIGNAL zero_out_w : STD_LOGIC;
SIGNAL zero_res_w : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL zero_w : STD_LOGIC;
SIGNAL wire_w_and_b0_w_range134w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_w_and_b1_w_range142w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_w_and_b2_w_range150w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_w_and_b3_w_range158w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_w_and_b4_w_range166w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_w_and_b5_w_range173w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_w_slope_w_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_slope_w_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_slope_w_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_slope_w_range148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_slope_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_slope_w_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT kn_kalman_inv_altfp_inv_and_or_6nd
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_inv_altfp_inv_and_or_opd
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_inv_altfp_inv_and_or_pld
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_inv_altfp_inv_and_or_bod
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_inv_altfp_inv_csa_pei
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(25 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(25 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_inv_altfp_inv_csa_0ai
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_inv_altfp_inv_csa_1bi
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT lpm_mult
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTHA : NATURAL;
LPM_WIDTHB : NATURAL;
LPM_WIDTHP : NATURAL;
LPM_WIDTHS : NATURAL := 1;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_mult"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTHA-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR(LPM_WIDTHB-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(LPM_WIDTHP-1 DOWNTO 0);
sum : IN STD_LOGIC_VECTOR(LPM_WIDTHS-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
loop3 : FOR i IN 0 TO 31 GENERATE
wire_w_lg_w_lg_infinite_out_w290w291w(i) <= wire_w_lg_infinite_out_w290w(0) AND norm_res_int_w(i);
END GENERATE loop3;
loop4 : FOR i IN 0 TO 8 GENERATE
wire_w_lg_w_lg_man_zero_w215w216w(i) <= wire_w_lg_man_zero_w215w(0) AND const_bias_adj_greater_one_w(i);
END GENERATE loop4;
loop5 : FOR i IN 0 TO 31 GENERATE
wire_w_lg_w_lg_nan_out_w298w299w(i) <= wire_w_lg_nan_out_w298w(0) AND mux_2_res_w(i);
END GENERATE loop5;
loop6 : FOR i IN 0 TO 31 GENERATE
wire_w_lg_w_lg_zero_out_w294w295w(i) <= wire_w_lg_zero_out_w294w(0) AND mux_1_res_w(i);
END GENERATE loop6;
loop7 : FOR i IN 0 TO 31 GENERATE
wire_w_lg_infinite_out_w292w(i) <= infinite_out_w AND infi_res_w(i);
END GENERATE loop7;
loop8 : FOR i IN 0 TO 8 GENERATE
wire_w_lg_man_zero_w214w(i) <= man_zero_w AND const_bias_adj_one_w(i);
END GENERATE loop8;
loop9 : FOR i IN 0 TO 31 GENERATE
wire_w_lg_nan_out_w300w(i) <= nan_out_w AND nan_res_w(i);
END GENERATE loop9;
loop10 : FOR i IN 0 TO 31 GENERATE
wire_w_lg_zero_out_w296w(i) <= zero_out_w AND zero_res_w(i);
END GENERATE loop10;
loop11 : FOR i IN 0 TO 29 GENERATE
wire_w_lg_w_slope_w_range171w172w(i) <= wire_w_slope_w_range171w(0) AND shift_b5_w(i);
END GENERATE loop11;
loop12 : FOR i IN 0 TO 29 GENERATE
wire_w_lg_w_slope_w_range164w165w(i) <= wire_w_slope_w_range164w(0) AND shift_b4_w(i);
END GENERATE loop12;
loop13 : FOR i IN 0 TO 29 GENERATE
wire_w_lg_w_slope_w_range156w157w(i) <= wire_w_slope_w_range156w(0) AND shift_b3_w(i);
END GENERATE loop13;
loop14 : FOR i IN 0 TO 29 GENERATE
wire_w_lg_w_slope_w_range148w149w(i) <= wire_w_slope_w_range148w(0) AND shift_b2_w(i);
END GENERATE loop14;
loop15 : FOR i IN 0 TO 29 GENERATE
wire_w_lg_w_slope_w_range140w141w(i) <= wire_w_slope_w_range140w(0) AND shift_b1_w(i);
END GENERATE loop15;
loop16 : FOR i IN 0 TO 29 GENERATE
wire_w_lg_w_slope_w_range132w133w(i) <= wire_w_slope_w_range132w(0) AND shift_b0_w(i);
END GENERATE loop16;
wire_w_lg_exp_or_msb_w204w(0) <= NOT exp_or_msb_w;
wire_w_lg_infinite_input_w221w(0) <= NOT infinite_input_w;
wire_w_lg_infinite_out_w290w(0) <= NOT infinite_out_w;
wire_w_lg_man_or_msb_w203w(0) <= NOT man_or_msb_w;
wire_w_lg_man_zero_w215w(0) <= NOT man_zero_w;
wire_w_lg_nan_input_w212w(0) <= NOT nan_input_w;
wire_w_lg_nan_out_w298w(0) <= NOT nan_out_w;
wire_w_lg_zero_out_w294w(0) <= NOT zero_out_w;
aclr <= '0';
and_b0_w <= wire_w_lg_w_slope_w_range132w133w;
and_b1_w <= wire_w_lg_w_slope_w_range140w141w;
and_b2_w <= wire_w_lg_w_slope_w_range148w149w;
and_b3_w <= wire_w_lg_w_slope_w_range156w157w;
and_b4_w <= wire_w_lg_w_slope_w_range164w165w;
and_b5_w <= wire_w_lg_w_slope_w_range171w172w;
approx_c_w <= "1100000";
approx_mx_w <= ( gnd_w & vcc_w & man_dffe_0(22 DOWNTO 18));
approx_y_w <= ( wire_approx_sub_result(5 DOWNTO 0) & gnd_w & gnd_w & gnd_w & gnd_w & gnd_w & gnd_w & gnd_w);
c_offset_w <= ( gnd_w & gnd_w & gnd_w & intercept_dffe);
clk_en <= '1';
const_2_w <= "10000000000000000000000000";
const_bias_adj_greater_one_w <= "011111101";
const_bias_adj_one_w <= "011111110";
const_bias_adj_w <= (wire_w_lg_w_lg_man_zero_w215w216w OR wire_w_lg_man_zero_w214w);
data_exp_bus_w <= data(30 DOWNTO 23);
data_man_bus_w <= data(22 DOWNTO 0);
data_sign_w <= data(31);
division_by_zero_w <= zero_input_w;
exp_and_msb_w <= wire_altfp_inv_and_or5_result;
exp_bus_w <= exp_dffe1_11;
exp_exc_ones_w <= (OTHERS => '1');
exp_exc_zeros_w <= (OTHERS => '0');
exp_one_w <= exp_and_msb_w;
exp_or_msb_w <= wire_altfp_inv_and_or4_result;
exp_res_w <= exp_dffe2_2;
exp_zero_w <= wire_w_lg_exp_or_msb_w204w(0);
gnd_w <= '0';
infi_res_w <= ( sign_exc_bit_w & exp_exc_ones_w & man_exc_zeros_w);
infinite_input_w <= infinite_input_dffe;
infinite_out_w <= infinite_dffe(2);
infinite_w <= zero_input_w;
man_and_msb_w <= wire_altfp_inv_and_or3_result;
man_bus_w <= man_dffe_11;
man_exc_nan_w <= ( vcc_w & man_exc_zeros_w(21 DOWNTO 0));
man_exc_zeros_w <= (OTHERS => '0');
man_non_zero_w <= man_or_msb_w;
man_one_w <= man_and_msb_w;
man_or_msb_w <= wire_altfp_inv_and_or2_result;
man_out_0_w <= ( vcc_w & man_dffe_4(22 DOWNTO 0));
man_out_1_w <= ( vcc_w & man_dffe_11(22 DOWNTO 0));
man_res_w <= x_2_w(22 DOWNTO 0);
man_zero_w <= wire_w_lg_man_or_msb_w203w(0);
modified_c_w <= wire_modified_add_result(12 DOWNTO 0);
mux_1_res_w <= (wire_w_lg_infinite_out_w292w OR wire_w_lg_w_lg_infinite_out_w290w291w);
mux_2_res_w <= (wire_w_lg_zero_out_w296w OR wire_w_lg_w_lg_zero_out_w294w295w);
mux_3_res_w <= (wire_w_lg_nan_out_w300w OR wire_w_lg_w_lg_nan_out_w298w299w);
nan_input_w <= nan_input_dffe;
nan_out_w <= nan_dffe(2);
nan_res_w <= ( sign_exc_bit_w & exp_exc_ones_w & man_exc_nan_w);
nan_w <= nan_input_w;
norm_res_int_w <= ( sign_res_w & exp_res_w & man_res_w);
result <= result_output_dffe;
shift_b0_w <= ( gnd_w & vcc_w & man_dffe_0 & gnd_w & gnd_w & gnd_w & gnd_w & gnd_w);
shift_b1_w <= ( gnd_w & gnd_w & vcc_w & man_dffe_0 & gnd_w & gnd_w & gnd_w & gnd_w);
shift_b2_w <= ( gnd_w & gnd_w & gnd_w & vcc_w & man_dffe_0 & gnd_w & gnd_w & gnd_w);
shift_b3_w <= ( gnd_w & gnd_w & gnd_w & gnd_w & vcc_w & man_dffe_0 & gnd_w & gnd_w);
shift_b4_w <= ( gnd_w & gnd_w & gnd_w & gnd_w & gnd_w & vcc_w & man_dffe_0 & gnd_w);
shift_b5_w <= ( gnd_w & gnd_w & gnd_w & gnd_w & gnd_w & gnd_w & vcc_w & man_dffe_0);
sign_exc_bit_w <= sign_res_w;
sign_res_w <= sign_dffe(18);
slope_w <= wire_mux1_result(15 DOWNTO 10);
table_bus_full_w <= ( "0100010000000001" & "0100010010000001" & "0100100010000111" & "0100100100000111" & "0100110100010000" & "0101000100011100" & "0101000110011100" & "0101010110101011" & "0101100110111100" & "0101110111010000" & "0101111001010001" & "0110001001100111" & "0110011001111111" & "0110101010011010" & "0110111010110111" & "0111001011010101" & "0111101010010111" & "0111111010111010" & "1000001011011111" & "1000101010101101" & "1000111011010101" & "1001011010101011" & "1001111010000101" & "1010001010110011" & "1010111001000101" & "1011011000101010" & "1011111000010011" & "1100100110110111" & "1101010101100001" & "1110000100010001" & "1110110011000110" & "1111110001000000");
underflow_w <= ((wire_w_lg_infinite_input_w221w(0) AND wire_w_lg_nan_input_w212w(0)) AND wire_cmpr6_ageb);
vcc_w <= '1';
x_0_w <= x_initial_w;
x_1_w <= wire_outer_mult0_result(36 DOWNTO 12);
x_2_w <= wire_outer_mult1_result(48 DOWNTO 24);
x_initial_w <= wire_slope_r3c1_add_result;
zero_input_w <= zero_input_dffe;
zero_out_w <= zero_dffe(2);
zero_res_w <= ( sign_exc_bit_w & exp_exc_zeros_w & man_exc_zeros_w);
zero_w <= (wire_w_lg_nan_input_w212w(0) AND (infinite_input_w OR underflow_w));
wire_w_and_b0_w_range134w <= and_b0_w(29 DOWNTO 17);
wire_w_and_b1_w_range142w <= and_b1_w(29 DOWNTO 17);
wire_w_and_b2_w_range150w <= and_b2_w(29 DOWNTO 17);
wire_w_and_b3_w_range158w <= and_b3_w(29 DOWNTO 17);
wire_w_and_b4_w_range166w <= and_b4_w(29 DOWNTO 17);
wire_w_and_b5_w_range173w <= and_b5_w(29 DOWNTO 17);
wire_w_slope_w_range171w(0) <= slope_w(0);
wire_w_slope_w_range164w(0) <= slope_w(1);
wire_w_slope_w_range156w(0) <= slope_w(2);
wire_w_slope_w_range148w(0) <= slope_w(3);
wire_w_slope_w_range140w(0) <= slope_w(4);
wire_w_slope_w_range132w(0) <= slope_w(5);
altfp_inv_and_or2 : kn_kalman_inv_altfp_inv_and_or_6nd
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
data => man_bus_w,
result => wire_altfp_inv_and_or2_result
);
altfp_inv_and_or3 : kn_kalman_inv_altfp_inv_and_or_opd
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
data => man_bus_w,
result => wire_altfp_inv_and_or3_result
);
altfp_inv_and_or4 : kn_kalman_inv_altfp_inv_and_or_pld
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
data => exp_bus_w,
result => wire_altfp_inv_and_or4_result
);
altfp_inv_and_or5 : kn_kalman_inv_altfp_inv_and_or_bod
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
data => exp_bus_w,
result => wire_altfp_inv_and_or5_result
);
diff_adder_0 : kn_kalman_inv_altfp_inv_csa_pei
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => const_2_w(25 DOWNTO 0),
datab => wire_inner_mult0_result(36 DOWNTO 11),
result => wire_diff_adder_0_result
);
diff_adder_1 : kn_kalman_inv_altfp_inv_csa_pei
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => const_2_w(25 DOWNTO 0),
datab => wire_inner_mult1_result(48 DOWNTO 23),
result => wire_diff_adder_1_result
);
slope_r1c1_add : kn_kalman_inv_altfp_inv_csa_0ai
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => and_dffe_0,
datab => and_dffe_1,
result => wire_slope_r1c1_add_result
);
slope_r1c2_add : kn_kalman_inv_altfp_inv_csa_0ai
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => and_dffe_2,
datab => and_dffe_3,
result => wire_slope_r1c2_add_result
);
slope_r1c3_add : kn_kalman_inv_altfp_inv_csa_0ai
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => and_dffe_4,
datab => and_dffe_5,
result => wire_slope_r1c3_add_result
);
slope_r2c1_add : kn_kalman_inv_altfp_inv_csa_0ai
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_slope_r1c1_add_result,
datab => wire_slope_r1c2_add_result,
result => wire_slope_r2c1_add_result
);
slope_r2c2_add : kn_kalman_inv_altfp_inv_csa_1bi
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => modified_c_w,
datab => wire_slope_r1c3_add_result,
result => wire_slope_r2c2_add_result
);
slope_r3c1_add : kn_kalman_inv_altfp_inv_csa_1bi
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_slope_r2c2_add_result,
datab => wire_slope_r2c1_add_result,
result => wire_slope_r3c1_add_result
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN and_dffe_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN and_dffe_0 <= wire_w_and_b0_w_range134w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN and_dffe_1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN and_dffe_1 <= wire_w_and_b1_w_range142w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN and_dffe_2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN and_dffe_2 <= wire_w_and_b2_w_range150w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN and_dffe_3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN and_dffe_3 <= wire_w_and_b3_w_range158w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN and_dffe_4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN and_dffe_4 <= wire_w_and_b4_w_range166w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN and_dffe_5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN and_dffe_5 <= wire_w_and_b5_w_range173w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN division_by_zero_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN division_by_zero_dffe <= ( division_by_zero_dffe(1 DOWNTO 0) & division_by_zero_w);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe1_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe1_0 <= data_exp_bus_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe1_1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe1_1 <= exp_dffe1_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe1_10 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe1_10 <= exp_dffe1_9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe1_11 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe1_11 <= exp_dffe1_10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe1_12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe1_12 <= exp_dffe1_11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe1_13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe1_13 <= exp_dffe1_12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe1_14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe1_14 <= exp_dffe1_13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe1_2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe1_2 <= exp_dffe1_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe1_3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe1_3 <= exp_dffe1_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe1_4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe1_4 <= exp_dffe1_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe1_5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe1_5 <= exp_dffe1_4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe1_6 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe1_6 <= exp_dffe1_5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe1_7 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe1_7 <= exp_dffe1_6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe1_8 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe1_8 <= exp_dffe1_7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe1_9 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe1_9 <= exp_dffe1_8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe2_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe2_0 <= wire_bias_adjustment_w_result_range267w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe2_1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe2_1 <= exp_dffe2_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_dffe2_2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_dffe2_2 <= exp_dffe2_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_dffe <= ( infinite_dffe(1 DOWNTO 0) & infinite_w);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_input_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_input_dffe <= (exp_one_w AND man_zero_w);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN intercept_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN intercept_dffe <= wire_mux1_w_result_range183w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe_0 <= data_man_bus_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe_1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe_1 <= man_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe_10 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe_10 <= man_dffe_9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe_11 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe_11 <= man_dffe_10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe_2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe_2 <= man_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe_3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe_3 <= man_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe_4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe_4 <= man_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe_5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe_5 <= man_dffe_4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe_6 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe_6 <= man_dffe_5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe_7 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe_7 <= man_dffe_6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe_8 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe_8 <= man_dffe_7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe_9 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe_9 <= man_dffe_8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN nan_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN nan_dffe <= ( nan_dffe(1 DOWNTO 0) & nan_w);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN nan_input_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN nan_input_dffe <= (exp_one_w AND (man_non_zero_w OR man_one_w));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN result_output_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN result_output_dffe <= mux_3_res_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe <= ( sign_dffe(17 DOWNTO 0) & data_sign_w);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN underflow_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN underflow_dffe <= ( underflow_dffe(1 DOWNTO 0) & underflow_w);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_dffe_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_dffe_0 <= x_0_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_dffe_1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_dffe_1 <= x_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_dffe_2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_dffe_2 <= x_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_dffe_3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_dffe_3 <= x_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_dffe_4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_dffe_4 <= x_1_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_dffe_5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_dffe_5 <= x_dffe_4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_dffe_6 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_dffe_6 <= x_dffe_5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_dffe_7 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_dffe_7 <= x_dffe_6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_dffe <= ( zero_dffe(1 DOWNTO 0) & zero_w);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_input_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_input_dffe <= (exp_zero_w AND ((man_one_w OR man_non_zero_w) OR man_zero_w));
END IF;
END IF;
END PROCESS;
approx_sub : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 7
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => approx_c_w,
datab => approx_mx_w,
result => wire_approx_sub_result
);
wire_bias_adjustment_datab <= ( gnd_w & exp_dffe1_14);
wire_bias_adjustment_w_result_range267w <= wire_bias_adjustment_result(7 DOWNTO 0);
bias_adjustment : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 9,
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => const_bias_adj_w,
datab => wire_bias_adjustment_datab,
result => wire_bias_adjustment_result
);
modified_add : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 13
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => approx_y_w,
datab => c_offset_w,
result => wire_modified_add_result
);
wire_cmpr6_dataa <= ( gnd_w & exp_dffe1_14);
cmpr6 : lpm_compare
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
ageb => wire_cmpr6_ageb,
clken => clk_en,
clock => clock,
dataa => wire_cmpr6_dataa,
datab => const_bias_adj_w
);
inner_mult0 : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 3,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 24,
LPM_WIDTHB => 13,
LPM_WIDTHP => 37,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=AUTO"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => man_out_0_w,
datab => x_0_w,
result => wire_inner_mult0_result
);
inner_mult1 : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 3,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 24,
LPM_WIDTHB => 25,
LPM_WIDTHP => 49,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=AUTO"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => man_out_1_w,
datab => x_1_w,
result => wire_inner_mult1_result
);
outer_mult0 : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 3,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 25,
LPM_WIDTHB => 13,
LPM_WIDTHP => 38,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=AUTO"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_diff_adder_0_result(24 DOWNTO 0),
datab => x_dffe_3,
result => wire_outer_mult0_result
);
outer_mult1 : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 3,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 25,
LPM_WIDTHB => 25,
LPM_WIDTHP => 50,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=AUTO"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_diff_adder_1_result(24 DOWNTO 0),
datab => x_dffe_7,
result => wire_outer_mult1_result
);
loop17 : FOR i IN 0 TO 31 GENERATE
loop18 : FOR j IN 0 TO 15 GENERATE
wire_mux1_data_2d(i, j) <= table_bus_full_w(i*16+j);
END GENERATE loop18;
END GENERATE loop17;
wire_mux1_w_result_range183w <= wire_mux1_result(9 DOWNTO 0);
mux1 : lpm_mux
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_SIZE => 32,
LPM_WIDTH => 16,
LPM_WIDTHS => 5
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
data => wire_mux1_data_2d,
result => wire_mux1_result,
sel => data_man_bus_w(22 DOWNTO 18)
);
END RTL; --kn_kalman_inv_altfp_inv_rhc
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_inv IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END kn_kalman_inv;
ARCHITECTURE RTL OF kn_kalman_inv IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT kn_kalman_inv_altfp_inv_rhc
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
kn_kalman_inv_altfp_inv_rhc_component : kn_kalman_inv_altfp_inv_rhc
PORT MAP (
clock => clock,
data => data,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_inv"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "20"
-- Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_inv.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_inv.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_inv.bsf TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_inv_inst.vhd TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_inv.inc FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_inv.cmp TRUE TRUE
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX NUMERIC "1"
-- Retrieval info: LIB_FILE: lpm
| mit | ec0f14b252fe4a9a4d4cac2fed41f7cb | 0.65707 | 2.472377 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_dexp_64ns_64ns_64_18_full_dsp.vhd | 6 | 2,769 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_dexp_64ns_64ns_64_18_full_dsp is
generic (
ID : integer := 9;
NUM_STAGE : integer := 18;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_dexp_64ns_64ns_64_18_full_dsp is
--------------------- Component ---------------------
component ANN_ap_dexp_16_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_dexp_16_full_dsp_64_u : component ANN_ap_dexp_16_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 1fd6684755f72f36c9cd5dbb1057286a | 0.474901 | 3.65786 | false | false | false | false |
dugagjinll/MIPS | MIPS/instructionMemory.vhd | 1 | 1,429 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY instructionMemory IS
PORT (
readAddress : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
instruction : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END instructionMemory;
ARCHITECTURE Behavioral OF instructionMemory IS
TYPE RAM_16_x_32 IS ARRAY(0 TO 15) OF std_logic_vector(31 DOWNTO 0);
SIGNAL IM : RAM_16_x_32 := (
x"01285024", -- 0x0040 0000: and $t2, $t1, $t0
x"018b6825", -- 0x0040 0004: or $t5, $t4, $t3
x"01285020", -- 0x0040 0008: add $t2, $t1, $t0
x"01285022", -- 0x0040 0004: sub $t5, $t1, $t0
x"0149402a", -- 0x0040 0010: slt $t0, $t2, $t1
x"1211fffb", -- 0x0040 0014: branchequal $s0, $s1, $L1 (1210fffb for $s1, $s1)
x"01285024", -- 0x0040 0018: and $t2, $t1, $t0
x"018b6825", -- 0x0040 001C: or $t5, $t4, $t3
x"01285020", -- 0x0040 0020: add $t2, $t1, $t0
x"01285022", -- 0x0040 0004: sub $t5, $t1, $t0
x"0149402a", -- 0x0040 0010: slt $t0, $t2, $t1
x"08100000", -- 0x0040 002C: j 0x00400000 => 0000 1000 0001 0000 0000 0000 0000 (jump to address 0x00400000 (begining))
x"00000000",
x"00000000",
x"00000000",
x"00000000"
);
BEGIN
-- Note: 4194304 = 0x0040 0000
-- reset when address is 003FFFFC else if readAddress is 0040 0000 then reset also
instruction <= x"00000000" when readAddress = x"003FFFFC" else
IM(( to_integer(unsigned(readAddress)) - 4194304) /4);
END Behavioral; | mit | b906b744789b57fdbdc4c3e74bd03129 | 0.649405 | 2.29374 | false | false | false | false |
TMU-VHDL-team2/sqrt | fpga/sqrt.vhd | 1 | 17,681 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sqrt is
port(pulse : in std_logic;
btn : in std_logic_vector(2 downto 0);
sw : in std_logic_vector(9 downto 0);
led : out std_logic_vector(9 downto 0);
hex0 : out std_logic_vector(7 downto 0);
hex1 : out std_logic_vector(7 downto 0);
hex2 : out std_logic_vector(7 downto 0);
hex3 : out std_logic_vector(7 downto 0));
end sqrt;
architecture BEHAVIOR of sqrt is
--component clock is
-- port(pulse : out std_logic);
--end component;
component alu is
port(func : in std_logic_vector(3 downto 0);
busA : in std_logic_vector(15 downto 0);
busB : in std_logic_vector(15 downto 0);
inZ : in std_logic;
inS : in std_logic;
inO : in std_logic;
outZ : out std_logic;
outS : out std_logic;
outO : out std_logic;
busC : out std_logic_vector(15 downto 0));
end component;
component bB is
port(S_GRB : in std_logic_vector(15 downto 0);
S_PR_F : in std_logic_vector(15 downto 0);
S_MAR_F : in std_logic_vector(15 downto 0);
S_MDR_F : in std_logic_vector(15 downto 0);
addr : in std_logic_vector(7 downto 0);
S_s_ctl : in std_logic_vector(4 downto 0);
S_BUS_B : out std_logic_vector(15 downto 0));
end component;
--component bC is
-- port(S_BUS_C : inout std_logic_vector(15 downto 0));
--end component;
component busA is
port(clock : in std_logic;
MDR : in std_logic_vector(15 downto 0);
GR : in std_logic_vector(15 downto 0);
ADDR : in std_logic_vector(7 downto 0);
SI : in std_logic_vector(2 downto 0);
busA_out : out std_logic_vector(15 downto 0));
end component;
component csgc is
port(clk : in std_logic;
init_phase : in std_logic_vector(3 downto 0);
mlang : in std_logic_vector(15 downto 0);
ba_ctl : out std_logic_vector(2 downto 0);
bb_ctl : out std_logic_vector(4 downto 0);
address : out std_logic_vector(7 downto 0);
gr_lat : out std_logic;
gra : out std_logic_vector(3 downto 0);
grb : out std_logic_vector(3 downto 0);
grc : out std_logic_vector(3 downto 0);
ir_lat : out std_logic;
fr_lat : out std_logic;
pr_lat : out std_logic;
pr_cnt : out std_logic;
mar_lat : out std_logic;
mdr_lat : out std_logic;
mdr_sel : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
func : out std_logic_vector(3 downto 0);
phaseView : out std_logic_vector(3 downto 0));
end component;
component fr is
port(clk : in std_logic;
latch : in std_logic;
inZF : in std_logic;
inSF : in std_logic;
inOF : in std_logic;
outZF : out std_logic;
outSF : out std_logic;
outOF : out std_logic);
end component;
component gr is
port(clk : in std_logic;
S_GRlat : in std_logic;
S_ctl_a : in std_logic_vector(3 downto 0);
S_ctl_b : in std_logic_vector(3 downto 0);
S_ctl_c : in std_logic_vector(3 downto 0);
S_BUS_C : in std_logic_vector(15 downto 0);
S_BUS_A : out std_logic_vector(15 downto 0);
S_BUS_B : out std_logic_vector(15 downto 0);
GR0_View : out std_logic_vector(15 downto 0);
GR1_View : out std_logic_vector(15 downto 0);
GR2_View : out std_logic_vector(15 downto 0);
GR3_View : out std_logic_vector(15 downto 0);
GR4_View : out std_logic_vector(15 downto 0);
GR5_View : out std_logic_vector(15 downto 0);
GR6_View : out std_logic_vector(15 downto 0);
GR7_View : out std_logic_vector(15 downto 0);
GR8_View : out std_logic_vector(15 downto 0);
GR9_View : out std_logic_vector(15 downto 0);
GR10_View : out std_logic_vector(15 downto 0);
GR11_View : out std_logic_vector(15 downto 0);
GR12_View : out std_logic_vector(15 downto 0);
GR13_View : out std_logic_vector(15 downto 0);
GR14_View : out std_logic_vector(15 downto 0);
GR15_View : out std_logic_vector(15 downto 0));
end component;
component inst is
port(clock : in std_logic;
busA : in std_logic_vector(15 downto 0);
latch : in std_logic;
Mlang : out std_logic_vector(15 downto 0));
end component;
component MAR is
port(clk : in std_logic;
lat : in std_logic;
busC : in std_logic_vector(15 downto 0);
M_ad16 : out std_logic_vector(15 downto 0);
M_ad8 : out std_logic_vector(7 downto 0));
end component;
component mdr is
port(clock : in std_logic;
busC : in std_logic_vector(15 downto 0);
latch : in std_logic;
memo : in std_logic_vector(15 downto 0);
sel : in std_logic;
data : out std_logic_vector(15 downto 0));
end component;
--component mem is
-- port(clk : in std_logic;
-- read : in std_logic;
-- write : in std_logic;
-- init_phase : in std_logic_vector(3 downto 0);
-- input : in std_logic_vector(15 downto 0);
-- S_MAR_F : in std_logic_vector(7 downto 0);
-- S_MDR_F : in std_logic_vector(15 downto 0);
-- data : out std_logic_vector(15 downto 0));
--end component;
component M9K_RAM is
port(address : in std_logic_vector(7 downto 0);
clock : in std_logic;
init_phase : in std_logic_vector(3 downto 0);
input : in std_logic_vector(15 downto 0);
data : in std_logic_vector(15 downto 0);
rden : in std_logic;
wren : in std_logic;
q : out std_logic_vector(15 downto 0));
end component;
component pr is
port(clk : in std_logic;
S_PRlat : in std_logic;
S_s_inc : in std_logic;
S_BUS_C : in std_logic_vector(15 downto 0);
S_PR_F : out std_logic_vector(15 downto 0));
end component;
--signal pulse : std_logic;
signal alu_fr_z : std_logic;
signal alu_fr_s : std_logic;
signal alu_fr_o : std_logic;
signal busb_alu : std_logic_vector(15 downto 0);
signal alu_busc_others : std_logic_vector(15 downto 0);
signal busa_alu_ir : std_logic_vector(15 downto 0);
signal csgc_busa_ctl : std_logic_vector(2 downto 0);
signal csgc_busb_ctl : std_logic_vector(4 downto 0);
signal csgc_busab_addr : std_logic_vector(7 downto 0);
signal csgc_gr_lat : std_logic;
signal csgc_gr_asel : std_logic_vector(3 downto 0);
signal csgc_gr_bsel : std_logic_vector(3 downto 0);
signal csgc_gr_csel : std_logic_vector(3 downto 0);
signal csgc_ir_lat : std_logic;
signal csgc_fr_lat : std_logic;
signal csgc_pr_lat : std_logic;
signal csgc_pr_cntup : std_logic;
signal csgc_mar_lat : std_logic;
signal csgc_mdr_lat : std_logic;
signal csgc_mdr_sel : std_logic;
signal csgc_mem_read : std_logic;
signal csgc_mem_write : std_logic;
signal csgc_alu_func : std_logic_vector(3 downto 0);
signal phaseView : std_logic_vector(3 downto 0);
signal fr_alu_z : std_logic;
signal fr_alu_s : std_logic;
signal fr_alu_o : std_logic;
signal gr_busa : std_logic_vector(15 downto 0);
signal gr_busb : std_logic_vector(15 downto 0);
signal GR0_View : std_logic_vector(15 downto 0);
signal GR1_View : std_logic_vector(15 downto 0);
signal GR2_View : std_logic_vector(15 downto 0);
signal GR3_View : std_logic_vector(15 downto 0);
signal GR4_View : std_logic_vector(15 downto 0);
signal GR5_View : std_logic_vector(15 downto 0);
signal GR6_View : std_logic_vector(15 downto 0);
signal GR7_View : std_logic_vector(15 downto 0);
signal GR8_View : std_logic_vector(15 downto 0);
signal GR9_View : std_logic_vector(15 downto 0);
signal GR10_View : std_logic_vector(15 downto 0);
signal GR11_View : std_logic_vector(15 downto 0);
signal GR12_View : std_logic_vector(15 downto 0);
signal GR13_View : std_logic_vector(15 downto 0);
signal GR14_View : std_logic_vector(15 downto 0);
signal GR15_View : std_logic_vector(15 downto 0);
signal ir_csgc : std_logic_vector(15 downto 0);
signal mar_busb : std_logic_vector(15 downto 0);
signal mar_mem : std_logic_vector(7 downto 0);
signal mdr_busab_mem : std_logic_vector(15 downto 0);
signal mem_mdr : std_logic_vector(15 downto 0);
signal pr_busb : std_logic_vector(15 downto 0);
signal init_phase : std_logic_vector(3 downto 0);
signal input : std_logic_vector(15 downto 0);
function LedDec(num : std_logic_vector(3 downto 0))
return std_logic_vector is
begin
case num is
when X"0" => return "11000000";
when X"1" => return "11111001";
when X"2" => return "10100100";
when X"3" => return "10110000";
when X"4" => return "10011001";
when X"5" => return "10010010";
when X"6" => return "10000010";
when X"7" => return "11111000";
when X"8" => return "10000000";
when X"9" => return "10011000";
when X"a" => return "10001000";
when X"b" => return "10000011";
when X"c" => return "10100111";
when X"d" => return "10100001";
when X"e" => return "10000110";
when X"f" => return "10001110";
when others => return "11111111";
end case;
end function;
begin
led(2 downto 0) <= not btn(2 downto 0);
led(6 downto 3) <= init_phase;
-- clock_a : clock port map(pulse => pulse);
alu_a : alu port map(func => csgc_alu_func,
busA => busa_alu_ir,
busB => busb_alu,
inZ => fr_alu_z,
inS => fr_alu_s,
inO => fr_alu_o,
outZ => alu_fr_z,
outS => alu_fr_s,
outO => alu_fr_o,
busC => alu_busc_others);
bB_a : bB port map(S_GRB => gr_busb,
S_PR_F => pr_busb,
S_MAR_F => mar_busb,
S_MDR_F => mdr_busab_mem,
addr => csgc_busab_addr,
S_s_ctl => csgc_busb_ctl,
S_BUS_B => busb_alu);
--bC_a : bC port map(S_BUS_C => alu_busc_others);
busA_a : busA port map(clock => pulse,
MDR => mdr_busab_mem,
GR => gr_busa,
ADDR => csgc_busab_addr,
SI => csgc_busa_ctl,
busA_out => busa_alu_ir);
csgc_a : csgc port map(clk => pulse,
init_phase => init_phase,
mlang => ir_csgc,
ba_ctl => csgc_busa_ctl,
bb_ctl => csgc_busb_ctl,
address => csgc_busab_addr,
gr_lat => csgc_gr_lat,
gra => csgc_gr_asel,
grb => csgc_gr_bsel,
grc => csgc_gr_csel,
ir_lat => csgc_ir_lat,
fr_lat => csgc_fr_lat,
pr_lat => csgc_pr_lat,
pr_cnt => csgc_pr_cntup,
mar_lat => csgc_mar_lat,
mdr_lat => csgc_mdr_lat,
mdr_sel => csgc_mdr_sel,
m_read => csgc_mem_read,
m_write => csgc_mem_write,
func => csgc_alu_func,
phaseView => phaseView);
fr_a : fr port map(clk => pulse,
latch => csgc_fr_lat,
inZF => alu_fr_z,
inSF => alu_fr_s,
inOF => alu_fr_o,
outZF => fr_alu_z,
outSF => fr_alu_s,
outOF => fr_alu_o);
gr_a : gr port map(clk => pulse,
S_GRlat => csgc_gr_lat,
S_ctl_a => csgc_gr_asel,
S_ctl_b => csgc_gr_bsel,
S_ctl_c => csgc_gr_csel,
S_BUS_C => alu_busc_others,
S_BUS_A => gr_busa,
S_BUS_B => gr_busb,
GR0_View => GR0_View,
GR1_View => GR1_View,
GR2_View => GR2_View,
GR3_View => GR3_View,
GR4_View => GR4_View,
GR5_View => GR5_View,
GR6_View => GR6_View,
GR7_View => GR7_View,
GR8_View => GR8_View,
GR9_View => GR9_View,
GR10_View => GR10_View,
GR11_View => GR11_View,
GR12_View => GR12_View,
GR13_View => GR13_View,
GR14_View => GR14_View,
GR15_View => GR15_View);
inst_a : inst port map(clock => pulse,
busA => busa_alu_ir,
latch => csgc_ir_lat,
Mlang => ir_csgc);
MAR_a : MAR port map(clk => pulse,
lat => csgc_mar_lat,
busC => alu_busc_others,
M_ad16 => mar_busb,
M_ad8 => mar_mem);
mdr_a : mdr port map(clock => pulse,
busC => alu_busc_others,
latch => csgc_mdr_lat,
memo => mem_mdr,
sel => csgc_mdr_sel,
data => mdr_busab_mem);
-- mem_a : mem port map(clk => pulse,
-- read => csgc_mem_read,
-- write => csgc_mem_write,
-- init_phase => init_phase,
-- input => input,
-- S_MAR_F => mar_mem,
-- S_MDR_F => mdr_busab_mem,
-- data => mem_mdr);
M9K_RAM_inst : M9K_RAM port map(address => mar_mem,
clock => pulse,
init_phase => init_phase,
input => input,
data => mdr_busab_mem,
rden => csgc_mem_read,
wren => csgc_mem_write,
q => mem_mdr);
pr_a : pr port map(clk => pulse,
S_PRlat => csgc_pr_lat,
S_s_inc => csgc_pr_cntup,
S_BUS_C => alu_busc_others,
S_PR_F => pr_busb);
process(pulse)
variable GR_View : std_logic_vector(15 downto 0);
begin
if pulse'event and pulse = '1' then
if btn(0) = '0' then
input(7 downto 0) <= sw(7 downto 0);
init_phase <= X"1";
end if;
if btn(1) = '0' then
input(15 downto 8) <= sw(7 downto 0);
init_phase <= X"1";
end if;
if btn(2) = '0' then
if (init_phase = X"1") then
init_phase <= X"2";
end if;
end if;
if init_phase >= X"2" then
if init_phase = X"f" then
init_phase <= X"0";
end if;
init_phase <= init_phase + 1;
end if;
if ir_csgc(15 downto 12) = X"f" then
case ir_csgc(11 downto 8) is
when X"0" => GR_View := GR0_View;
when X"1" => GR_View := GR1_View;
when X"2" => GR_View := GR2_View;
when X"3" => GR_View := GR3_View;
when X"4" => GR_View := GR4_View;
when X"5" => GR_View := GR5_View;
when X"6" => GR_View := GR6_View;
when X"7" => GR_View := GR7_View;
when X"8" => GR_View := GR8_View;
when X"9" => GR_View := GR9_View;
when X"a" => GR_View := GR10_View;
when X"b" => GR_View := GR11_View;
when X"c" => GR_View := GR12_View;
when X"d" => GR_View := GR13_View;
when X"e" => GR_View := GR14_View;
when X"f" => GR_View := GR15_View;
when others => null;
end case;
case ir_csgc(3 downto 0) is
when X"0" => hex0 <= LedDec(GR_View(3 downto 0));
when X"1" => hex1 <= LedDec(GR_View(3 downto 0));
when X"2" => hex2 <= LedDec(GR_View(3 downto 0));
when X"3" => hex3 <= LedDec(GR_View(3 downto 0));
when others => null;
end case;
hex2(7) <= '0';
elsif init_phase = X"1" then
hex0 <= LedDec(input(3 downto 0));
hex1 <= LedDec(input(7 downto 4));
hex2 <= LedDec(input(11 downto 8));
hex3 <= LedDec(input(15 downto 12));
hex0(7) <= '0';
end if;
end if;
end process;
end BEHAVIOR;
| mit | e196258be7d224c668d55fc91ae5654b | 0.479328 | 3.370377 | false | false | false | false |
znuh/open-nexys | bscan_new/top.vhd | 1 | 2,481 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity top is
Port (
sys_clk : in std_logic;
Led: out std_logic_vector(7 downto 0);
sw: in std_logic_vector(7 downto 0)
);
end top;
architecture Behavioral of top is
component bscan_sreg is
GENERIC (
SREG_LEN : integer := 16
);
Port (
CAPTURE_i : in std_logic;
DRCK_i : in std_logic;
SEL_i : in std_logic;
SHIFT_i : in std_logic;
UPDATE_i : in std_logic;
TDI_i : in std_logic;
TDO_o: out std_logic;
clk_i : in std_logic;
Data_i : in std_logic_vector((SREG_LEN - 1) downto 0);
Data_o : out std_logic_vector((SREG_LEN - 1) downto 0);
strobe_o : out std_logic
);
end component;
signal CAPTURE : std_logic;
signal DRCK1 : std_logic;
signal SEL1 : std_logic;
signal SHIFT : std_logic;
signal UPDATE : std_logic;
signal TDO1 : std_logic;
signal TDI : std_logic;
signal din : std_logic_vector(15 downto 0);
signal dout : std_logic_vector(15 downto 0);
signal strobe : std_logic;
begin
BSCAN_SPARTAN3_inst : BSCAN_SPARTAN3
port map (
CAPTURE => CAPTURE, -- CAPTURE output from TAP controller
DRCK1 => DRCK1, -- Data register output for USER1 functions
DRCK2 => open, -- Data register output for USER2 functions
RESET => open, -- Reset output from TAP controller
SEL1 => SEL1, -- USER1 active output
SEL2 => open, -- USER2 active output
SHIFT => SHIFT, -- SHIFT output from TAP controller
TDI => TDI, -- TDI output from TAP controller
UPDATE => UPDATE, -- UPDATE output from TAP controller
TDO1 => TDO1, -- Data input for USER1 function
TDO2 => open -- Data input for USER2 function
);
bscan_sreg_inst : bscan_sreg
Port map (
CAPTURE_i => CAPTURE,
DRCK_i => DRCK1,
SEL_i => SEL1,
SHIFT_i => SHIFT,
UPDATE_i => UPDATE,
TDI_i => TDI,
TDO_o => TDO1,
clk_i => sys_clk,
Data_i => din,
Data_o => dout,
strobe_o => strobe
);
process(sys_clk)
begin
if rising_edge(sys_clk) then
if strobe = '1' then
din <= dout;
case dout(15 downto 8) is
when x"00" => din(7 downto 0) <= sw;
when x"81" => Led <= dout(7 downto 0);
when others => null;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 382a9ac84ff1a484835c7ded9f64d411 | 0.631197 | 3.089664 | false | false | false | false |
dugagjinll/MIPS | MIPS/tb_dataMemory.vhd | 1 | 1,510 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.numeric_std.ALL;
ENTITY tb_dataMemory IS
END tb_dataMemory;
ARCHITECTURE behavior OF tb_dataMemory IS
--Inputs
SIGNAL tb_address : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_writeData : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_memRead : std_logic := '0';
SIGNAL tb_memWrite : std_logic := '0';
--Outputs
SIGNAL tb_readData : std_logic_vector(31 DOWNTO 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : ENTITY work.dataMemory(Behavioral)
PORT MAP(
address => tb_address,
writeData => tb_writeData,
memRead => tb_memRead,
memWrite => tb_memWrite,
readData => tb_readData
);
-- Stimulus process
stim_proc : PROCESS
BEGIN
-- write two memory locations
tb_address <= x"10010000";
tb_writeData <= x"11112222";
tb_memWrite <= '0';
WAIT FOR 10 ns;
tb_memWrite <= '1';
WAIT FOR 10 ns;
tb_memWrite <= '0';
WAIT FOR 10 ns;
tb_address <= x"10010004";
tb_writeData <= x"33334444";
tb_memWrite <= '0';
WAIT FOR 10 ns;
tb_memWrite <= '1';
WAIT FOR 10 ns;
tb_memWrite <= '0';
WAIT FOR 10 ns;
-- read two memory locations
tb_address <= x"10010000";
tb_memRead <= '0';
WAIT FOR 10 ns;
tb_memRead <= '1';
WAIT FOR 10 ns;
tb_memRead <= '0';
WAIT FOR 10 ns;
tb_address <= x"10010004";
tb_memRead <= '0';
WAIT FOR 10 ns;
tb_memRead <= '1';
WAIT FOR 10 ns;
tb_memRead <= '0';
WAIT FOR 10 ns;
ASSERT false
REPORT "END"
SEVERITY failure;
END PROCESS;
END; | mit | 1b924b60015040a12b7fd557c796c611 | 0.647682 | 2.801484 | false | false | false | false |
e8johan/jamcpu | iu.vhd | 1 | 3,808 | ---------------------------------------------------------
-- JAM CPU
-- Integer Unit
--
-- License: LGPL v2+ (see the file LICENSE)
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Library General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--This integer unit uses a basic ALU with shift
--and adds a multicycle multiplier.
--The multiplier uses Booth's algorithm.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
entity IU is
port(
a_in, b_in : in std_logic_vector(31 downto 0); -- IU input
do_mult : in std_logic; -- Do multicycle mult?
mult_op : in std_logic; -- Return [0=LSW] or [1=MSW) of mult result
alu_op : in std_logic_vector(2 downto 0); -- ALU op
inv_in2 : in std_logic; -- Invert operator in2 in ALU
clk : in std_logic; -- Global clock
reset : in std_logic; -- Global reset
ovf : out std_logic; -- Overflow
result : out std_logic_vector(31 downto 0); -- IU result
mc : out std_logic); -- Goes high during the last cycle of multicycle ops
end;
architecture rev1 of IU is
component ALU
port(
op : in std_logic_vector(2 downto 0); -- ALU operation
inv_in2 : in std_logic; -- Invert operator in2
in1, in2 : in std_logic_vector(31 downto 0); -- ALU input
ovf : out std_logic; -- ALU overflow
alu_out : out std_logic_vector(31 downto 0)); -- ALU result
end component;
for alu_unit : ALU use entity work.ALU(rev2);
signal a, b, alu_data : std_logic_vector(31 downto 0);
signal b_reg : std_logic_vector(31 downto 0);
signal op : std_logic_vector(2 downto 0);
signal running : std_logic;
signal finished : std_logic;
signal from_latch : std_logic_vector(64 downto 0);
begin
alu_unit : ALU port map(op, inv_in2, a, b, ovf, alu_data);
result <=
alu_data when do_mult = '0' else
from_latch(32 downto 1) when mult_op = '0' else
from_latch(64 downto 33);
a <=
a_in when do_mult = '0' else
from_latch(64 downto 33);
b <=
b_in when do_mult = '0' else
b_reg;
op <=
alu_op when do_mult = '0' else
"001" when from_latch(1 downto 0) = "01" else
"010" when from_latch(1 downto 0) = "10" else
"000";
--65bit register + 32 bit buffer for b_in
process(clk)
constant zero32: std_logic_vector(31 downto 0) := (others => '0');
begin
if clk'event and clk='1' then
if do_mult = '1' and running = '0' then
from_latch <= zero32 & a_in & '0';
b_reg <= b_in;
elsif do_mult ='1' then
from_latch <= alu_data(31) & alu_data & from_latch(32 downto 1);
end if;
end if;
end process;
process(clk)
variable loop_nr: std_logic_vector(5 downto 0);
begin
if clk'event and clk='1' then
if reset='1' then
running <= '0';
finished <= '0';
mc <= '0';
else
if do_mult = '1' then
--multicycle mult
if running = '0' then
--setup
running <= '1';
loop_nr := (others => '0');
end if;
if loop_nr(5) = '1' then --last cycle?
finished <= '1';
loop_nr := (others => '0');
mc <= '1';
else
mc <= '0';
loop_nr := loop_nr + '1';
end if;
if finished = '1' then
finished <= '0';
running <= '0';
end if;
else
mc <= '0';
running <= '0';
end if;
end if;
end if;
end process;
end;
| lgpl-2.1 | 9023862a4d91946b9414f5e3c1c0d668 | 0.550683 | 3.170691 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_32x512/simulation/fg_tb_top.vhd | 1 | 5,679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 35
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| mit | e1eb5828643caa2bf52e749a2554535a | 0.616306 | 4.175735 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_64x1024/example_design/fifo_fwft_64x1024_top_wrapper.vhd | 1 | 19,141 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_fwft_64x1024_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_fwft_64x1024_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(64-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(10-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(64-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_fwft_64x1024_top_wrapper;
architecture xilinx of fifo_fwft_64x1024_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_fwft_64x1024_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_fwft_64x1024_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 9f7331d886a93d0bec49a33444248252 | 0.486234 | 3.967869 | false | false | false | false |
dugagjinll/MIPS | MIPS/tb_ALU.vhd | 1 | 1,225 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_ALU IS
END tb_ALU;
ARCHITECTURE behavior OF tb_ALU IS
--Inputs
SIGNAL tb_a1 : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_a2 : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_alu_control : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
--Outputs
SIGNAL tb_alu_result : std_logic_vector(31 DOWNTO 0);
SIGNAL tb_zero : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : ENTITY work.ALU(Behavioral)
PORT MAP(
a1 => tb_a1,
a2 => tb_a2,
alu_control => tb_alu_control,
alu_result => tb_alu_result,
zero => tb_zero
);
-- Stimulus process
stim_proc : PROCESS
BEGIN
tb_a1 <= x"00000003";
tb_a2 <= x"FFFFFFFF";
tb_alu_control <= "0000"; --bitwise and
WAIT FOR 50 ns;
tb_alu_control <= "0001"; --bitwise or
WAIT FOR 50 ns;
tb_alu_control <= "0010"; --bitwise addition
WAIT FOR 50 ns;
tb_alu_control <= "0110"; --bitwise substraction
WAIT FOR 50 ns;
tb_alu_control <= "0111"; --set les than
WAIT FOR 50 ns;
tb_alu_control <= "1100"; --bitwise nor
WAIT FOR 50 ns;
ASSERT false
REPORT "END"
SEVERITY failure;
END PROCESS;
END; | mit | c77d2be8f728be4a0258bb99aa35c7f5 | 0.619592 | 2.882353 | false | false | false | false |
TMU-VHDL-team2/sqrt | fpga/fr.vhd | 2 | 851 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fr is
port(
clk : in std_logic;
latch : in std_logic;
inZF : in std_logic;
inSF : in std_logic;
inOF : in std_logic;
outZF : out std_logic;
outSF : out std_logic;
outOF : out std_logic
);
end fr;
architecture BEHAVIOR of fr is
-- Definitions --
signal ZFG : std_logic;
signal SFG : std_logic;
signal OFG : std_logic;
-- Main --
begin
process(clk) begin
if(clk'event and (clk = '1') and (latch = '1')) then
ZFG <= inZF;
SFG <= inSF;
OFG <= inOF;
else
null;
end if;
end process;
outZF <= ZFG;
outSF <= SFG;
outOF <= OFG;
end BEHAVIOR;
| mit | f005e44a9e830cc237525fbcc4384278 | 0.490012 | 3.45935 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/tb_pr.vhd | 1 | 1,166 | -- Include packages --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity tb is
end tb;
architecture SIM of tb is
-- Definitions --
constant STEP : time := 10 ns; -- A clock cycle is set to be 100ns --
signal clk, S_PRlat, S_s_inc : std_logic;
signal S_BUS_C, S_PR_F : std_logic_vector(15 downto 0);
-- Modules declaration
component pr
port(clk, S_PRlat, S_s_inc : in std_logic;
S_BUS_C : in std_logic_vector(15 downto 0);
S_PR_F : out std_logic_vector(15 downto 0));
end component;
-- Process --
begin
uut: pr port map(clk, S_PRlat, S_s_inc, S_BUS_C, S_PR_F);
clk_process:
process begin
clk <= '0';
wait for STEP/2; --for 0.5 ns signal is '0'.
clk <= '1';
wait for STEP/2; --for next 0.5 ns signal is '1'.
end process;
tb:
process begin
S_BUS_C <= "0000000010001011";
wait for 10ns;
S_PRlat <= '1';
wait for 30ns;
S_PRlat <= '0';
wait for 50ns;
S_s_inc <= '1';
wait for 70ns;
S_s_inc <= '0';
wait;
end process;
end SIM;
| mit | 8e2bf57d03187d412dc0c73e4958b31d | 0.542882 | 3.01292 | false | false | false | false |
fabianschuiki/moore | test/vhdl/exprs.vhd | 1 | 3,732 | package pkg is
type SMALLINT is range 0 to 3;
constant two : SMALLINT := 2;
end;
library work;
use work.pkg;
entity foo is end;
architecture bar of foo is
--type BOOLEAN is (false, true);
--type BIT is ('0', '1');
--type BIT2 is ('1', '2');
--type BIT3 is ('X', '0');
--type INTEGER is range -256 to 255;
--type BIT_VECTOR is array (INTEGER range <>) of BIT;
subtype TRIBITS is BIT_VECTOR (0 to 2);
subtype PENTABITS is BIT_VECTOR (0 to 4);
type REC is record
a : BIT;
b : BIT;
c : BIT;
end record;
--attribute STUFF : BIT;
--attribute STUFF of BIT : type is '0';
-- primary literal
constant s00 : INTEGER := 123;
constant s01 : BIT := '0';
--constant s02 : BIT_VECTOR(0 to 4) := "00100";
-- primary name
constant s10 : INTEGER := s00;
--constant s11 : BIT := BIT'STUFF;
constant s12 : INTEGER := pkg.two;
-- primary aggregate
constant s20 : REC := ('0', '1', '0');
constant s21 : REC := (a => '0', b => '1', c => '0');
constant s22 : REC := ('0', c => '0', b => '1');
constant s23 : TRIBITS := ('0', '1', '0');
constant s24 : TRIBITS := (0 => '0', 1 => '1', 2 => '0');
constant s25 : TRIBITS := ('0', 2 => '1', 1 => '0');
-- primary function call
constant s30 : INTEGER := square(2);
-- primary qualified expression
constant s40 : INTEGER := INTEGER'(123);
constant s41 : REC := REC'('0', '1', '0');
constant s42 : REC := REC'(a => '0', b => '1', c => '0');
constant s43 : REC := REC'('0', c => '0', b => '1');
constant s44 : TRIBITS := TRIBITS'('0', '1', '0');
constant s45 : TRIBITS := TRIBITS'(0 => '0', 1 => '1', 2 => '0');
constant s46 : TRIBITS := TRIBITS'('0', 2 => '1', 1 => '0');
-- primary type conversion
--constant s50 : INTEGER := INTEGER('0');
constant s51 : INTEGER := INTEGER(123);
-- primary allocator
constant s60 : INTEGER := new INTEGER;
constant s61 : INTEGER := new INTEGER'(123);
-- primary parenthesized
constant s70 : INTEGER := (123);
constant s71 : INTEGER := (s10);
-- factor
constant s80 : INTEGER := 2 ** 4;
constant s81 : INTEGER := abs s00;
constant s82 : TRIBITS := not s23;
constant s83 : TRIBITS := and s23;
constant s84 : TRIBITS := or s23;
constant s85 : TRIBITS := nand s23;
constant s86 : TRIBITS := nor s23;
constant s87 : TRIBITS := xor s23;
constant s88 : TRIBITS := xnor s23;
-- term
constant s90 : INTEGER := 2 * 2;
constant s91 : INTEGER := 8 / 2;
constant s92 : INTEGER := 8 mod 2;
constant s93 : INTEGER := 8 rem 2;
-- simple expression
constant s100 : INTEGER := -2;
constant s101 : INTEGER := +2;
constant s102 : INTEGER := 2 + 2;
constant s103 : INTEGER := 4 + 2;
constant s104 : BIT_VECTOR := "00" & "100";
-- shift expression
constant s110 : TRIBITS := s23 sll 4;
constant s111 : TRIBITS := s23 srl 4;
constant s112 : TRIBITS := s23 sla 4;
constant s113 : TRIBITS := s23 sra 4;
constant s114 : TRIBITS := s23 rol 4;
constant s115 : TRIBITS := s23 ror 4;
-- relation
constant s120 : INTEGER := 8 = 4;
constant s121 : INTEGER := 8 /= 4;
constant s122 : INTEGER := 8 < 4;
constant s123 : INTEGER := 8 <= 4;
constant s124 : INTEGER := 8 > 4;
constant s125 : INTEGER := 8 >= 4;
constant s126 : BIT := '0' ?= '1';
constant s127 : BIT := '0' ?/= '1';
constant s128 : BIT := s23 ?= s23;
constant s129 : BIT := s23 ?/= s23;
constant s12A : BIT := '0' ?< '1';
constant s12B : BIT := '0' ?<= '1';
constant s12C : BIT := '0' ?> '1';
constant s12D : BIT := '0' ?>= '1';
-- logical expression
constant s130 : BIT := '0' and '1';
constant s131 : BIT := '0' or '1';
constant s132 : BIT := '0' xor '1';
constant s133 : BIT := '0' nand '1';
constant s134 : BIT := '0' nor '1';
constant s135 : BIT := '0' xnor '1';
-- condition
constant s140 : BOOLEAN := ?? 123;
begin end;
| apache-2.0 | 83b75d38fb5cb7edfa8c6c9076bb43bf | 0.587889 | 2.85977 | false | false | false | false |
intelligenttoasters/CPC2.0 | FPGA/rtl/cpc/YM2149/YM2149_tb.vhd | 1 | 5,604 |
use std.textio.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity YM2149_TB is
end;
architecture Sim of YM2149_TB is
component YM2149
port (
-- data bus
I_DA : in std_logic_vector(7 downto 0);
O_DA : out std_logic_vector(7 downto 0);
O_DA_OE_L : out std_logic;
-- control
I_A9_L : in std_logic;
I_A8 : in std_logic;
I_BDIR : in std_logic;
I_BC2 : in std_logic;
I_BC1 : in std_logic;
I_SEL_L : in std_logic;
O_AUDIO : out std_logic_vector(7 downto 0);
-- port a
I_IOA : in std_logic_vector(7 downto 0);
O_IOA : out std_logic_vector(7 downto 0);
O_IOA_OE_L : out std_logic;
-- port b
I_IOB : in std_logic_vector(7 downto 0);
O_IOB : out std_logic_vector(7 downto 0);
O_IOB_OE_L : out std_logic;
ENA : in std_logic; -- clock enable for higher speed operation
RESET_L : in std_logic;
CLK : in std_logic -- note 6 Mhz
);
end component;
-- signals
constant CLKPERIOD : time := 25 ns;
signal func : string(8 downto 1);
signal clk : std_logic;
signal reset_l : std_logic;
signal reset_h : std_logic;
signal da_in : std_logic_vector(7 downto 0);
signal da_out : std_logic_vector(7 downto 0);
signal da_oe_l : std_logic;
signal bdir : std_logic;
signal bc2 : std_logic;
signal bc1 : std_logic;
signal audio : std_logic_vector(7 downto 0);
signal ioa_in : std_logic_vector(7 downto 0);
signal ioa_out : std_logic_vector(7 downto 0);
signal ioa_oe_l : std_logic;
signal iob_in : std_logic_vector(7 downto 0);
signal iob_out : std_logic_vector(7 downto 0);
signal iob_oe_l : std_logic;
begin
u0 : YM2149
port map (
-- data bus
I_DA => da_in,
O_DA => da_out,
O_DA_OE_L => da_oe_l,
-- control
I_A9_L => '0',
I_A8 => '1',
I_BDIR => bdir,
I_BC2 => bc2,
I_BC1 => bc1,
I_SEL_L => '1',
O_AUDIO => audio,
-- port a
I_IOA => ioa_in,
O_IOA => ioa_out,
O_IOA_OE_L => ioa_oe_l,
-- port b
I_IOB => iob_in,
O_IOB => iob_out,
O_IOB_OE_L => iob_oe_l,
ENA => '1',
RESET_L => reset_l,
CLK => clk
);
p_clk : process
begin
CLK <= '0';
wait for CLKPERIOD / 2;
CLK <= '1';
wait for CLKPERIOD - (CLKPERIOD / 2);
end process;
p_debug_comb : process(bdir, bc2, bc1)
variable sel : std_logic_vector(2 downto 0);
begin
func <= "-XXXXXX-";
sel := bdir & bc2 & bc1;
case sel is
when "000" |
"010" |
"101" => func <= "inactive";
when "001" |
"100" |
"111" => func <= "address ";
when "011" => func <= "read ";
when "110" => func <= "write ";
when others => null;
end case;
end process;
p_test : process
procedure write(
addr : in bit_vector(3 downto 0);
data : in bit_vector(7 downto 0)
) is
begin
wait until rising_edge(clk);
-- addr
bdir <= '1';
bc2 <= '1';
bc1 <= '1';
da_in <= x"0" & to_stdlogicvector(addr);
wait for 300 ns;
bdir <= '0';
bc2 <= '0';
bc1 <= '0';
wait for 80 ns;
da_in <= (others => 'Z');
wait for 100 ns;
-- write
bdir <= '1';
bc2 <= '1';
bc1 <= '0';
da_in <= to_stdlogicvector(data);
wait for 300 ns;
bdir <= '0';
bc2 <= '0';
bc1 <= '0';
wait for 80 ns;
da_in <= (others => 'Z');
wait for 100 ns;
wait until rising_edge(clk);
end write;
procedure read(
addr : in bit_vector(3 downto 0)
) is
begin
wait until rising_edge(clk);
-- addr
bdir <= '1';
bc2 <= '1';
bc1 <= '1';
da_in <= x"0" & to_stdlogicvector(addr);
wait for 300 ns;
bdir <= '0';
bc2 <= '0';
bc1 <= '0';
wait for 80 ns;
da_in <= (others => 'Z');
wait for 100 ns;
-- read
bdir <= '0';
bc2 <= '1';
bc1 <= '1';
da_in <= (others => 'Z');
wait for 300 ns;
bdir <= '0';
bc2 <= '0';
bc1 <= '0';
wait for 180 ns;
wait until rising_edge(clk);
end read;
begin
reset_l <= '0';
reset_h <= '1';
da_in <= (others => 'Z');
bdir <= '0';
bc2 <= '0';
bc1 <= '0';
wait for 100 ns;
reset_l <= '1';
reset_h <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
write(x"0",x"08");
write(x"1",x"00");
read(x"0");
wait for 500 ns;
write(x"7",x"fb");
write(x"8",x"00");
write(x"a",x"0f");
write(x"B",x"00");
write(x"C",x"00");
write(x"D",x"0E");
wait;
end process;
end Sim;
| gpl-3.0 | 3eb6ec86f3b6008c1c75b1a8d86f9c43 | 0.430764 | 3.329768 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_96x512/example_design/fifo_96x512_top_wrapper.vhd | 1 | 18,992 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_96x512_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_96x512_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(96-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(96-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_96x512_top_wrapper;
architecture xilinx of fifo_96x512_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_96x512_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(96-1 DOWNTO 0);
DOUT : OUT std_logic_vector(96-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_96x512_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | ae07a1dcdeb10c826f53e5f4eb10dfae | 0.48631 | 3.964099 | false | false | false | false |
mzakharo/usb-de2-fpga | src/drv.vhd | 1 | 14,034 | -- drv.vhd
-- -----------------------------------------------------------------------
-- Copyright © 2012 Mikhail Zakharov
-- -----------------------------------------------------------------------
--
-- This file is part of "ISP1362 VHDL interface for DE2"
--
-- "ISP1362 VHDL interface for DE2" is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3
--
-- "ISP1362 VHDL interface for DE2" is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with "ISP1362 VHDL interface for DE2". If not, see <http://www.gnu.org/licenses/>.
-- -----------------------------------------------------------------------
-- ISP1362 Driver
-- -----------------------------------------------------------------------
-- Version : 1.0
-- Date : Sept 2012
-- Author : Mikhail Zakharov
-- Web : http://ca.linkedin.com/in/mzakharo
-- Contact : [email protected]
-- -----------------------------------------------------------------------
-- FUNCTION :
-- 1. Configures ISP1362
-- 2. Handles IRQ from ISP1362
-- 3. I/O interface with external HW
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.isp_hal.all;
use work.devreq_inc.all;
package isp_drv is
type io_t is record
SData : std_logic_vector(15 downto 0);
RDy : std_logic;
end record;
type isp_drv_in_t is record
hal : drv_iface_out_t;
int : std_logic;
devreq : devreq_out_t;
io : io_t;
end record;
type isp_drv_out_t is record
hal : drv_iface_in_t;
devreq : devreq_in_t;
io : io_t;
end record;
component drv is
port(
clk : in std_logic;
reset : in std_logic;
d : in isp_drv_in_t;
q : out isp_drv_out_t );
end component;
end package;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.isp_hal.all;
use work.isp_drv.all;
use work.isp_inc.all;
use work.usb_inc.all;
entity drv is
port(
clk : in std_logic;
reset : in std_logic;
d : in isp_drv_in_t;
q : out isp_drv_out_t );
end drv;
architecture handler of drv is
type cfg_t is (cfg, cfg1, cfg2, cfg3, cfg4, cfg5, cfg6, cfg7, cfg8, cfg9,
cfg10, cfg11, cfg12, cfg13, cfg14, cfg15, cfg16, cfg17,
cfg18, cfg19, cfg20, cfg21, cfg22, cfg23, cfg24, cfg25, cfg26 ,
cfg27, cfg28, cfg29, cfg30, cfg31, cfg32, cfg33, cfg34, cfg_complete);
type irq_t is ( reset_irq, wait_irq, serve_irq, serve_irq1, serve_irq2,serve_irq3,
ep0_out, ep0_out1, ep0_out2, bus_reset, ctrl, ctrl1,
ctrl2, ctrl3, ctrl4, ctrl5, ctrl6, ctrl7, idev_req, ep1_out, ep1_out1,
ep1_out2,ep1_out3,ep1_out4,ep1_out5, TxLoads, TxLoads1, TxLoads2, TxLoadDone);
type drv_t is (configure, handle_irq, gdev_req);
type dev_t is ( in_reset, configured);
type txfsm_t is (TxIdle, TxLoad);
type not_reset_t is record
hdata_out : data_t;
hcmd : cmd_t;
hcmd_cfg : cmd_t;
hdata_out_cfg : data_t;
hcmd_irq : cmd_t;
hdata_out_irq : data_t;
int : std_logic;
DcInterrupt : data_t;
DeviceReq : device_request_t;
req_rdy : bit;
Din : std_logic_vector(io_t.SData'high downto 0);
end record;
type state_t is record
cfg : cfg_t;
global : drv_t;
irq : irq_t;
dev : dev_t;
TxFSM : txfsm_t;
end record;
type reg_t is record
st : state_t;
nr : not_reset_t;
RxRdy : std_logic;
end record;
signal r, rin : reg_t;
alias hdatah : byte is d.hal.data(15 downto 8);
alias hdatal : byte is d.hal.data(7 downto 0);
procedure hal_handler( variable v : inout reg_t ; constant hcmd : in cmd_t ;
constant data : in data_t; constant next_st : in cfg_t) is
begin
v.nr.hdata_out_cfg :=data ;
v.nr.hcmd_cfg := hcmd ;
if (d.hal.rdy = '1') then
v.st.cfg := next_st;
end if;
end procedure hal_handler;
procedure hal_out_cmd( variable v : inout reg_t ; constant data : in data_t ;
constant next_st : in cfg_t) is
begin
hal_handler(v, otg_wr_cmd, data, next_st);
end procedure hal_out_cmd;
procedure hal_out( variable v : inout reg_t ; constant data : in data_t ;
constant next_st : in cfg_t) is
begin
hal_handler(v, otg_wr, data, next_st);
end procedure hal_out;
procedure hal_in( variable v : inout reg_t ; constant next_st : in cfg_t) is
begin
hal_handler(v,otg_rd, dont_care_data_t, next_st);
end procedure hal_in;
procedure hal_handler_irq( variable v : inout reg_t ; constant hcmd : in cmd_t ;
constant data : in data_t; constant next_st : in irq_t) is
begin
v.nr.hdata_out_irq :=data ;
v.nr.hcmd_irq := hcmd ;
if (d.hal.rdy = '1') then
v.st.irq := next_st;
end if;
end procedure hal_handler_irq;
procedure hal_out_cmd_irq( variable v : inout reg_t ; constant data : in data_t ;
constant next_st : irq_t) is
begin
hal_handler_irq(v, otg_wr_cmd, data, next_st);
end procedure hal_out_cmd_irq;
procedure hal_out_irq( variable v : inout reg_t ; constant data : in data_t ;
constant next_st : in irq_t) is
begin
hal_handler_irq(v, otg_wr, data, next_st);
end procedure hal_out_irq;
procedure hal_in_irq( variable v : inout reg_t ; constant next_st : in irq_t) is
begin
hal_handler_irq(v,otg_rd, dont_care_data_t, next_st);
end procedure hal_in_irq;
begin --architecture
comb : process(r,d)
variable v : reg_t;
begin
v := r; --parameters
v.nr.hdata_out_cfg := dont_care_data_t;
v.nr.hcmd_cfg := otg_idle;
case r.st.cfg is
when cfg => hal_out_cmd(v, Wr_DcMode, cfg1);
when cfg1 => hal_out(v, MODE_INT_EN or MODE_SOFTCONNECT, cfg2);
when cfg2 => hal_out_cmd(v, Wr_DcHardwareConfiguration, cfg3);
when cfg3 => hal_out(v,DEVCNFG_NOLAZYCLOCK, cfg4);
when cfg4 => hal_out_cmd(v, Wr_DcEndpointConfiguration & EPINDEX4EP0_CONTROL_OUT, cfg5);
when cfg5 => hal_out(v, EPCNFG_FIFO_EN or EPCNFG_NONISOSZ_64, cfg6);
when cfg6 => hal_out_cmd(v, Wr_DcEndpointConfiguration & EPINDEX4EP0_CONTROL_IN, cfg7);
when cfg7 => hal_out(v, EPCNFG_FIFO_EN or EPCNFG_IN_EN or EPCNFG_NONISOSZ_64, cfg8);
when cfg8 => hal_out_cmd(v, Wr_DcEndpointConfiguration & EPINDEX4EP01, cfg9);
when cfg9 => hal_out(v, EPCNFG_FIFO_EN or EPCNFG_DBLBUF_EN or EPCNFG_NONISOSZ_64, cfg10);
when cfg10 => hal_out_cmd(v, Wr_DcEndpointConfiguration & EPINDEX4EP02, cfg11);
when cfg11 => hal_out(v, EPCNFG_FIFO_EN or EPCNFG_DBLBUF_EN or EPCNFG_IN_EN or EPCNFG_NONISOSZ_64, cfg12);
when cfg12 => hal_out_cmd(v, Wr_DcEndpointConfiguration & EPINDEX4EP03, cfg13);
when cfg13 => hal_out(v, EP_DISABLE, cfg14);
when cfg14 => hal_out_cmd(v, Wr_DcEndpointConfiguration & EPINDEX4EP04, cfg15);
when cfg15 => hal_out(v, EP_DISABLE, cfg16);
when cfg16 => hal_out_cmd(v, Wr_DcEndpointConfiguration & EPINDEX4EP05, cfg17);
when cfg17 => hal_out(v, EP_DISABLE, cfg18);
when cfg18 => hal_out_cmd(v, Wr_DcEndpointConfiguration & EPINDEX4EP06, cfg19);
when cfg19 => hal_out(v, EP_DISABLE, cfg20);
when cfg20 => hal_out_cmd(v, Wr_DcEndpointConfiguration & EPINDEX4EP07, cfg21);
when cfg21 => hal_out(v, EP_DISABLE, cfg22);
when cfg22 => hal_out_cmd(v, Wr_DcEndpointConfiguration & EPINDEX4EP0A, cfg23);
when cfg23 => hal_out(v, EP_DISABLE, cfg24);
when cfg24 => hal_out_cmd(v, Wr_DcEndpointConfiguration & EPINDEX4EP0B, cfg25);
when cfg25 => hal_out(v, EP_DISABLE, cfg26);
when cfg26 => hal_out_cmd(v, Wr_DcEndpointConfiguration & EPINDEX4EP0C, cfg27);
when cfg27 => hal_out(v, EP_DISABLE, cfg28);
when cfg28 => hal_out_cmd(v, Wr_DcEndpointConfiguration & EPINDEX4EP0D, cfg29);
when cfg29 => hal_out(v, EP_DISABLE, cfg30);
when cfg30 => hal_out_cmd(v, Wr_DcEndpointConfiguration & EPINDEX4EP0E, cfg31);
when cfg31 => hal_out(v, EP_DISABLE, cfg32);
when cfg32 => hal_out_cmd(v, Wr_DcInterruptEnable, cfg33);
when cfg33 => hal_out(v, INTSRC_EP0OUT or INTSRC_EP01 or INTSRC_BUSRESET, cfg34);
when cfg34 => hal_out(v, (others => '0'), cfg_complete); --ignore upper bytes
when cfg_complete =>
if (r.st.irq = bus_reset) then
v.st.cfg := cfg;
end if;
when others => v.st.cfg := r.st.cfg; --hang
end case;
v.nr.hdata_out_irq := dont_care_data_t;
v.nr.hcmd_irq := otg_idle;
v.RxRdy := '0';
case r.st.irq is
when reset_irq =>
v.st.irq := wait_irq;
when wait_irq =>
if (r.st.TxFsm = TxLoad and r.st.dev = configured) then
v.st.irq := TxLoads;
elsif (r.nr.int = '1') then
v.st.irq := serve_irq;
end if;
when serve_irq => hal_out_cmd_irq(v, Rd_DcInterrupt , serve_irq1);
when serve_irq1 => hal_in_irq (v,serve_irq2);
v.nr.DcInterrupt := d.hal.data;
when serve_irq2 => hal_in_irq (v,serve_irq3);
when serve_irq3 =>
if (r.nr.DcInterrupt(0) = '1') then --BUS RESET =1
v.st.irq := bus_reset;
elsif (r.nr.DcInterrupt(8) = '1') then --EP0_OUT =1
v.st.irq := ep0_out;
elsif (r.nr.DcInterrupt(10) = '1') then --EP1_OUT =1
v.st.irq := ep1_out;
else
v.st.irq := wait_irq;
end if;
when bus_reset =>
v.st.irq := reset_irq;
--ENDPOINT 0 Handler (no handshake)
when ep0_out => hal_out_cmd_irq (v,Rd_ESR & EPINDEX4EP0_CONTROL_OUT, ep0_out1);
when ep0_out1 => hal_in_irq(v, ep0_out2);
when ep0_out2 =>
if (d.hal.data(3 downto 2) = "01") then --OVERWRITE =0, SETUPT =1
v.st.irq := ctrl;
else
v.st.irq := wait_irq;
end if;
--ENDPOINT 1 Handler (no handshake) (RX)
when ep1_out => hal_out_cmd_irq (v,Rd_ESR & EPINDEX4EP01, ep1_out1);
when ep1_out1 => hal_in_irq(v, ep1_out2); --ignore status info
when ep1_out2 => hal_out_cmd_irq(v,Rd_Buffer & EPINDEX4EP01, ep1_out3);
when ep1_out3 => hal_in_irq(v, ep1_out4); --ignore length
when ep1_out4 => hal_in_irq(v, ep1_out5);
v.RxRdy := To_StdULogic(d.hal.rdy);
when ep1_out5 => hal_out_cmd_irq(v,ClearBuffer & EPINDEX4EP01, wait_irq);
--ENDPOINT 2 Handler (no handshake) (TX)
when TxLoads => hal_out_cmd_irq (v, Wr_Buffer & EPINDEX4EP02, TxLoads1);
when TxLoads1 => hal_out_irq(v, x"0002", TxLoads2); -- Tx 2 Bytes
when TxLoads2 => hal_out_irq(v, r.nr.Din, TxLoadDone);
when txLoadDone => hal_out_cmd_irq(v,Validate & EPINDEX4EP02, wait_irq);
--CONTROL Packet Handler
when ctrl => hal_out_cmd_irq(v,Rd_Buffer & EPINDEX4EP0_CONTROL_OUT, ctrl1);
when ctrl1 => hal_in_irq(v, ctrl2); --ignore length
when ctrl2 => hal_in_irq(v, ctrl3);
v.nr.DeviceReq.bmRequestType := hdatal;
v.nr.DeviceReq.bRequest := hdatah;
when ctrl3 => hal_in_irq(v, ctrl4);
v.nr.DeviceReq.wValue := d.hal.data;
when ctrl4 => hal_in_irq(v, ctrl5);
v.nr.DeviceReq.wIndex := d.hal.data;
when ctrl5 => hal_in_irq(v, ctrl6);
v.nr.DeviceReq.wLength:= d.hal.data;
when ctrl6 => hal_out_cmd_irq(v, AcknowledgeSetup, ctrl7);
when ctrl7 => hal_out_cmd_irq(v, ClearBuffer & EPINDEX4EP0_CONTROL_OUT, idev_req);
when idev_req =>
if (d.devreq.done = '1') then
v.st.irq := wait_irq;
end if;
when others => v.st.irq := r.st.irq; --hang
end case;
--outputs
q.io.RDy <= r.RxRdy;
q.io.SData <= d.hal.data;
q.devreq.req <= r.nr.DeviceReq;
q.devreq.req_rdy <= r.nr.req_rdy;
q.devreq.hal <= d.hal;
v.nr.hcmd := otg_idle;
v.nr.hdata_out := dont_care_data_t;
v.nr.req_rdy := '0';
v.nr.int := '0';
case r.st.global is
when configure =>
v.nr.hcmd := r.nr.hcmd_cfg;
v.nr.hdata_out := r.nr.hdata_out_cfg;
if (r.st.cfg = cfg_complete) then
v.st.global := handle_irq;
end if;
when handle_irq =>
v.nr.int := not(d.int);
v.nr.hcmd := r.nr.hcmd_irq;
v.nr.hdata_out := r.nr.hdata_out_irq;
if (r.st.irq = bus_reset) then
v.st.global := configure;
elsif (r.st.irq = idev_req) then
v.st.global := gdev_req;
v.nr.req_rdy := '1';
end if;
when gdev_req =>
v.nr.hcmd := d.devreq.hal.cmd;
v.nr.hdata_out := d.devreq.hal.data;
if (d.devreq.done = '1') then
v.st.global := handle_irq;
end if;
end case;
q.hal.cmd <= r.nr.hcmd;
q.hal.data <= r.nr.hdata_out;
case r.st.dev is
when in_reset =>
if (d.devreq.configured = '1') then
v.st.dev := configured;
end if;
when configured =>
if (r.st.cfg = cfg) then
v.st.dev := in_reset;
end if;
end case;
case r.st.TxFSM is
when TxIdle =>
if d.io.RDy ='1' then
v.nr.Din := d.io.SData; -- Latch input data immediately.
v.st.TxFSM := TxLoad;
end if;
when TxLoad =>
if (r.st.irq = TxLoadDone) then
v.st.TxFSM := TxIdle;
end if;
end case;
rin <= v; --return (v);
end process;
seq : process(reset, clk)
begin
if (reset= '1') then
r.st.global <= configure;
r.st.cfg <= cfg;
r.st.irq <= reset_irq;
r.st.dev <= in_reset;
r.st.TxFSM <= TxIdle;
r.RxRdy <= '0';
elsif rising_edge(clk) then
r.st <= rin.st;
r.RxRdy <= rin.RxRdy;
end if;
end process;
seq_nrst : process
begin
wait until rising_edge(clk);
r.nr <= rin.nr;
end process;
end architecture;
| gpl-3.0 | b0bc16af0e25816133dd93cdf80cf175 | 0.580733 | 2.774614 | false | true | false | false |
kevintownsend/R3 | coregen/fifo_69x512_hf/example_design/fifo_69x512_hf_top.vhd | 1 | 4,956 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_69x512_hf_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_69x512_hf_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(69-1 DOWNTO 0);
DOUT : OUT std_logic_vector(69-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_69x512_hf_top;
architecture xilinx of fifo_69x512_hf_top is
SIGNAL clk_i : std_logic;
component fifo_69x512_hf is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(69-1 DOWNTO 0);
DOUT : OUT std_logic_vector(69-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_69x512_hf PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | f8d6e8bca8c81742b9490d0feb85faa4 | 0.520581 | 4.868369 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_64x512/example_design/fifo_fwft_64x512_top_wrapper.vhd | 1 | 19,126 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_fwft_64x512_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_fwft_64x512_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(64-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(64-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_fwft_64x512_top_wrapper;
architecture xilinx of fifo_fwft_64x512_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_fwft_64x512_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_fwft_64x512_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | ca98ba3e31623ebee4f57d2d52c6a3da | 0.485831 | 3.96476 | false | false | false | false |
capitanov/MinesweeperFPGA | src/game_cores/cl_text.vhd | 1 | 3,368 | --------------------------------------------------------------------------------
--
-- Title : cl_text.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game block for main text
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.ctrl_types_pkg.array8x8;
entity cl_text is
generic(
constant yend : std_logic_vector(4 downto 0):="11000";
constant ystart : std_logic_vector(4 downto 0):="10000";
constant xend : std_logic_vector(6 downto 0):="0011000";
constant xstart : std_logic_vector(6 downto 0):="0010000"
);
port(
-- system signals:
clk : in std_logic;
reset : in std_logic;
-- control signals:
addr_rnd : in std_logic_vector(4 downto 0);
display : in std_logic;
cntgames : in std_logic;
win : in std_logic;
lose : in std_logic;
game : in std_logic;
flash : in std_logic_vector(2 downto 0);
-- vga XoY:
x_char : in std_logic_vector(9 downto 0);
y_char : in std_logic_vector(8 downto 0);
-- out color scheme:
rgb : out std_logic_vector(2 downto 0)
);
end cl_text;
architecture cl_text of cl_text is
component ctrl_8x16_rom is
port(
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end component;
component cl_select_text is
port(
x_char : in std_logic_vector(6 downto 0);
y_char : in std_logic_vector(4 downto 0);
win : in std_logic;
lose : in std_logic;
game : in std_logic;
cntgames: in std_logic;
addr_rnd: in std_logic_vector(4 downto 0);
ch_data : out std_logic_vector(7 downto 0)
);
end component;
signal x_in : std_logic_vector(6 downto 0);
signal y_in : std_logic_vector(4 downto 0);
signal data : std_logic;
signal x_rev : std_logic_vector(2 downto 0);
signal x_del : std_logic_vector(2 downto 0);
signal color : std_logic_vector(2 downto 0):="111";
signal addr_rom : std_logic_vector(10 downto 0);
signal data_rom : std_logic_vector(7 downto 0);
signal data_box : std_logic_vector(7 downto 0);
begin
x_in <= x_char(9 downto 3);
y_in <= y_char(8 downto 4);
x_select_text: cl_select_text
port map (
x_char => x_in,
y_char => y_in,
win => win,
lose => lose,
game => game,
cntgames=> cntgames,
addr_rnd=> addr_rnd,
ch_data => data_box
);
addr_rom <= data_box(6 downto 0) & y_char(3 downto 0) when rising_edge(clk);
x_char_rom: ctrl_8x16_rom
port map (
clk => clk,
addr => addr_rom,
data => data_rom
);
g_rev: for ii in 0 to 2 generate
begin
x_rev(ii) <= not x_char(ii) when rising_edge(clk);
end generate;
x_del <= x_rev when rising_edge(clk);
color <= flash when (x_in > "0011001") and (y_in = "10000") else "100" when (y_in < "00111") else "010";
pr_sw_sel: process(clk, reset) is
begin
if reset = '0' then
data <= '0';
elsif rising_edge(clk) then
if display = '0' then
data <= '0';
else
data <= data_rom(to_integer(unsigned(x_del)));
end if;
end if;
end process;
g_rgb: for ii in 0 to 2 generate
begin
rgb(ii) <= data and color(ii);
end generate;
end cl_text; | mit | 318f8037990336d4c7ac504a4011aee1 | 0.580166 | 2.679395 | false | false | false | false |
Wynjones1/VHDL-Tests | src/memory.vhd | 1 | 879 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity memory is
port( clk : in std_logic;
address : in std_logic_vector;
we : in std_logic;
data_in : in std_logic_vector;
data_out : out std_logic_vector);
end entity;
architecture rtl of memory is
constant MEM_WIDTH : integer := address'length;
constant MEM_MAX_ADDR : integer := 2 ** MEM_WIDTH - 1;
type ram_t is array(0 to MEM_MAX_ADDR) of std_logic_vector(data_in'length - 1 downto 0);
signal ram : ram_t;
signal read_address : std_logic_vector(address'length - 1 downto 0);
begin
process(clk, address, we, data_in)
begin
if rising_edge(clk) then
if we = '1' then
ram(to_integer(unsigned(address))) <= data_in;
end if;
read_address <= address;
end if;
end process;
data_out <= ram(to_integer(unsigned(read_address)));
end rtl;
| mit | dd8f5cb3c8598dd48e142832e539cf37 | 0.656428 | 2.920266 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_37x512/example_design/fifo_37x512_top.vhd | 1 | 4,780 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_37x512_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_37x512_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(37-1 DOWNTO 0);
DOUT : OUT std_logic_vector(37-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_37x512_top;
architecture xilinx of fifo_37x512_top is
SIGNAL clk_i : std_logic;
component fifo_37x512 is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(37-1 DOWNTO 0);
DOUT : OUT std_logic_vector(37-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_37x512 PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 91d84e1feaf3f55c98b55932e35a7152 | 0.526778 | 4.907598 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_36x512_hf/simulation/fg_tb_synth.vhd | 1 | 9,401 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL prog_empty : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(36-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(36-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(36-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(36-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 36,
C_DOUT_WIDTH => 36,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 36,
C_DIN_WIDTH => 36,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 36,
C_DIN_WIDTH => 36,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_36x512_hf_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit | f075ed8b0165a1496a68f002aa720a8a | 0.451654 | 4.210031 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/old_data/alu_32.vhd | 1 | 8,160 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity alu is
port(
func : in std_logic_vector(3 downto 0);
busA : in std_logic_vector(31 downto 0);
busB : in std_logic_vector(31 downto 0);
inZ : in std_logic;
inS : in std_logic;
inO : in std_logic;
outZ : out std_logic;
outS : out std_logic;
outO : out std_logic;
busC : out std_logic_vector(31 downto 0)
);
end alu;
architecture BEHAVIOR of alu is
-- Definitions --
signal ans : std_logic_vector(31 downto 0);
signal atop : std_logic;
signal btop : std_logic;
signal ftop : std_logic;
signal shift_ov : std_logic;
-- Main --
begin
busC <= ans;
-- Calculate Process --
process(func, busA, busB)
variable num : integer;
variable zero : std_logic_vector(31 downto 0);
begin
case func is
when "0000" => -- select busA (not only HALT) --
ans <= busA;
when "0001" => -- select busB (not only LD1) --
ans <= busB;
when "0101" => -- ADD --
ans <= busA + busB;
when "0110" => -- SUB --
ans <= busA - busB;
when "0111" => -- SL --
case conv_integer(busB(4 downto 0)) is
when 1 to 32 =>
num := conv_integer(busB(7 downto 0));
zero := (others => '0');
shift_ov <= busA(32 - num);
ans <= busA(31 - num downto 0) & zero(num - 1 downto 0);
when others =>
shift_ov <= '0';
ans <= busA;
end case;
-- case busB(3 downto 0) is
-- when "0000" => shift_ov <= '0'; ans <= busA;
-- when "0001" => shift_ov <= busA(15); ans <= busA(14 downto 0) & '0';
-- when "0010" => shift_ov <= busA(14); ans <= busA(13 downto 0) & "00";
-- when "0011" => shift_ov <= busA(13); ans <= busA(12 downto 0) & "000";
-- when "0100" => shift_ov <= busA(12); ans <= busA(11 downto 0) & "0000";
-- when "0101" => shift_ov <= busA(11); ans <= busA(10 downto 0) & "00000";
-- when "0110" => shift_ov <= busA(10); ans <= busA( 9 downto 0) & "000000";
-- when "0111" => shift_ov <= busA( 9); ans <= busA( 8 downto 0) & "0000000";
-- when "1000" => shift_ov <= busA( 8); ans <= busA( 7 downto 0) & "00000000";
-- when "1001" => shift_ov <= busA( 7); ans <= busA( 6 downto 0) & "000000000";
-- when "1010" => shift_ov <= busA( 6); ans <= busA( 5 downto 0) & "0000000000";
-- when "1011" => shift_ov <= busA( 5); ans <= busA( 4 downto 0) & "00000000000";
-- when "1100" => shift_ov <= busA( 4); ans <= busA( 3 downto 0) & "000000000000";
-- when "1101" => shift_ov <= busA( 3); ans <= busA( 2 downto 0) & "0000000000000";
-- when "1110" => shift_ov <= busA( 2); ans <= busA( 1 downto 0) & "00000000000000";
-- when "1111" => shift_ov <= busA( 1); ans <= busA(0) & "000000000000000";
-- when others => shift_ov <= '0'; ans <= busA;
-- end case;
when "1000" => -- SR --
case conv_integer(busB(4 downto 0)) is
when 1 to 32 =>
num := conv_integer(busB(7 downto 0));
zero := (others => '0');
shift_ov <= busA(num - 1);
ans <= zero(num - 1 downto 0) & busA(31 downto num);
when others =>
shift_ov <= '0';
ans <= busA;
end case;
-- case busB(3 downto 0) is
-- when "0000" => shift_ov <= '0'; ans <= busA;
-- when "0001" => shift_ov <= busA( 0); ans <= '0' & busA(15 downto 1);
-- when "0010" => shift_ov <= busA( 1); ans <= "00" & busA(15 downto 2);
-- when "0011" => shift_ov <= busA( 2); ans <= "000" & busA(15 downto 3);
-- when "0100" => shift_ov <= busA( 3); ans <= "0000" & busA(15 downto 4);
-- when "0101" => shift_ov <= busA( 4); ans <= "00000" & busA(15 downto 5);
-- when "0110" => shift_ov <= busA( 5); ans <= "000000" & busA(15 downto 6);
-- when "0111" => shift_ov <= busA( 6); ans <= "0000000" & busA(15 downto 7);
-- when "1000" => shift_ov <= busA( 7); ans <= "00000000" & busA(15 downto 8);
-- when "1001" => shift_ov <= busA( 8); ans <= "000000000" & busA(15 downto 9);
-- when "1010" => shift_ov <= busA( 9); ans <= "0000000000" & busA(15 downto 10);
-- when "1011" => shift_ov <= busA(10); ans <= "00000000000" & busA(15 downto 11);
-- when "1100" => shift_ov <= busA(11); ans <= "000000000000" & busA(15 downto 12);
-- when "1101" => shift_ov <= busA(12); ans <= "0000000000000" & busA(15 downto 13);
-- when "1110" => shift_ov <= busA(13); ans <= "00000000000000" & busA(15 downto 14);
-- when "1111" => shift_ov <= busA(14); ans <= "000000000000000" & busA(15);
-- when others => shift_ov <= '0'; ans <= busA;
-- end case;
when "1001" => -- NAND --
ans <= busA nand busB;
when "1010" => -- JMP --
ans <= busA; --------------------------- effective address
when "1011" => -- JZE --
if(inZ = '1') then
ans <= busA; ----------------------- effective address
else
ans <= busB + '1'; -- program register
end if;
when "1100" => -- JMI --
if(inS = '1') then
ans <= busA; ----------------------- effective address
else
ans <= busB + '1'; -- program register
end if;
when "1101" => -- JOV --
if(inO = '1') then
ans <= busA; ----------------------- effective address
else
ans <= busB + '1'; -- program register
end if;
when "1110" => -- RJMP --
ans <= busA; --------------------------- general register
when "1111" => -- DISP --
ans <= "0000000000000000000000000000" & busA(3 downto 0);
when others =>
ans <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- GetTop Process --
process(busA, busB, ans) begin
atop <= busA(31);
btop <= busB(31);
ftop <= ans(31);
if(ans = "00000000000000000000000000000000") then
outZ <= '1';
else
outZ <= '0';
end if;
end process;
-- Flag Process --
process(func, atop, btop, ftop) begin
case func is
when "0101" =>
if(((atop and btop) or (atop and not ftop) or (btop and not ftop)) = '1') then
outO <= '1';
else
outO <= '0';
end if;
when "0110" =>
if(((atop and btop) or (atop and not ftop) or (btop and not ftop)) = '1') then
outO <= '0';
else
outO <= '1';
end if;
when "0111" =>
outO <= shift_ov;
when "1000" =>
outO <= shift_ov;
when others =>
outO <= '0';
end case;
outS <= ftop;
end process;
end BEHAVIOR;
| mit | d7813afef8c2ee21967dbd571dfa1f88 | 0.406373 | 4.137931 | false | false | false | false |
freecores/pcounter | pcount_tb.vhdl | 1 | 827 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity pcount_tb is
end pcount_tb;
architecture test of pcount_tb is
component pdchain
generic (
n: natural
);
port (
clock: in std_logic;
en: in std_logic;
q: out std_logic_vector (n-1 downto 0)
);
end component;
--
constant T: time := 5 ns;
signal clock: std_logic := '0';
signal count: std_logic_vector (23 downto 0);
begin
pdchain0: pdchain
generic map (
n => count'length
)
port map (
clock => clock,
en => '1',
q => count
);
clk: process
variable s: line;
begin
clock <= '1';
wait for T/2;
clock <= '0';
wait for T/2;
--
write(s, to_bitvector(count));
writeline(output, s);
end process;
end test;
| lgpl-3.0 | 3751951266d6e740e358caa9182136f7 | 0.574365 | 3.255906 | false | false | false | false |
e8johan/jamcpu | imm_ext.vhd | 1 | 1,258 | ---------------------------------------------------------
-- JAM CPU
-- Immediate operand extender
--
-- License: LGPL v2+ (see the file LICENSE)
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Library General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
library IEEE;
use IEEE.std_logic_1164.all;
entity imm_ext is
port (
mode: in STD_LOGIC_VECTOR (1 downto 0);
op5: in STD_LOGIC;
imm: in STD_LOGIC_VECTOR (15 downto 0);
r: out STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture rev1 of imm_ext is
signal im, ximm, disp : std_logic_vector(31 downto 0);
begin
-- IMM (01)
im(31 downto 16) <= (others=>(not op5) and imm(15));
im(15 downto 0) <= imm;
-- XIMM(10)
ximm(31 downto 16) <= imm;
ximm(15 downto 0) <= (others=>'0');
-- DISP(11)
disp(31 downto 18) <= (others=>imm(15));
disp(17 downto 2) <= imm;
disp(1 downto 0) <= (others=>'0');
r <= im when mode = "01" else
ximm when mode = "10" else
disp;
end;
| lgpl-2.1 | 1cea8fce9b8d374a8e3a83355a05739c | 0.579491 | 3.409214 | false | false | false | false |
znuh/open-nexys | fx2_usb/fx2_usb.vhd | 1 | 4,335 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fx2_usb is
Port (
clk_i : in std_logic;
rst_i : in std_logic;
fx2_wr_full_i : in std_logic;
fx2_rd_empty_i : in std_logic;
fx2_data_io : inout std_logic_vector(7 downto 0);
fx2_clk_i : in std_logic;
fx2_slcs_o : out std_logic;
fx2_slrd_o : out std_logic;
fx2_sloe_o : out std_logic;
fx2_slwr_o : out std_logic;
fx2_pktend_o : out std_logic;
fx2_fifo_addr_o : out std_logic_vector(1 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
wr_full : out std_logic;
rd_empty : out std_logic;
pktend_i : in std_logic;
sync : out std_logic
);
end fx2_usb;
architecture Behavioral of fx2_usb is
component tiny_fifo
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;
signal tx_dout : std_logic_vector(7 downto 0);
signal tx_empty, rx_full, rx_empty : std_logic;
signal tx_rd_en, rx_wr_en : std_logic;
type mode is (IDLE, RD, DELAY, PKTEND);
signal state : mode;
signal tx_fifo_selected : std_logic;
signal pktend_r1 : std_logic;
signal pktend_r2 : std_logic;
signal pktend_r3 : std_logic;
signal pktend_pending : std_logic;
signal pktend_delay : integer;
signal fx2_rx_empty_r1 : std_logic;
signal fx2_rx_empty_r2 : std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
sync <= '0';
else
sync <= '0';
fx2_rx_empty_r1 <= fx2_rd_empty_i;
fx2_rx_empty_r2 <= fx2_rx_empty_r1;
if fx2_rx_empty_r2 = '0' and rx_empty = '1' then
sync <= '1';
end if;
end if;
end if;
end process;
fx2_slcs_o <= '0';
fx2_sloe_o <= '0' when tx_fifo_selected = '0' else '1';
fx2_data_io <= tx_dout when tx_fifo_selected = '1' else (others => 'Z');
fx2_fifo_addr_o <= "10" when tx_fifo_selected = '1' else "00";
process(fx2_clk_i)
begin
if rising_edge(fx2_clk_i) then
fx2_slwr_o <= not tx_rd_en;
fx2_slrd_o <= '1';
fx2_pktend_o <= '1';
pktend_r1 <= pktend_i;
pktend_r2 <= pktend_r1;
pktend_r3 <= pktend_r2;
if pktend_r3 = '0' and pktend_r2 = '1' then
pktend_pending <= '1';
end if;
rx_wr_en <= '0';
tx_rd_en <= '0';
if rst_i = '1' then
tx_fifo_selected <= '0';
state <= IDLE;
pktend_pending <= '0';
else
-- always go back to idle state
state <= IDLE;
case state is
when IDLE =>
-- pktend?
if fx2_wr_full_i = '1' and tx_empty = '1' and pktend_pending = '1' then
pktend_pending <= '0';
pktend_delay <= 4;
tx_fifo_selected <= '1';
state <= PKTEND;
-- send
elsif fx2_wr_full_i = '1' and tx_empty = '0' and tx_fifo_selected = '1' then
tx_rd_en <= '1';
state <= DELAY;
-- receive
elsif fx2_rd_empty_i = '1' and rx_full = '0' and tx_fifo_selected = '0' then
rx_wr_en <= '1';
state <= RD;
-- switch to sending
elsif fx2_wr_full_i = '1' and tx_empty = '0' then
tx_fifo_selected <= '1';
state <= DELAY;
-- switch to receiving
elsif fx2_rd_empty_i = '1' and rx_full = '0' then
tx_fifo_selected <= '0';
state <= DELAY;
end if;
when RD =>
fx2_slrd_o <= '0';
when DELAY => null;
when PKTEND =>
state <= PKTEND;
pktend_delay <= pktend_delay - 1;
if pktend_delay = 0 then
fx2_pktend_o <= '0';
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
rx_fifo : tiny_fifo
port map (
din => fx2_data_io,
rd_clk => clk_i,
rd_en => rd_en,
rst => rst_i,
wr_clk => fx2_clk_i,
wr_en => rx_wr_en,
dout => dout,
empty => rx_empty,
full => rx_full);
rd_empty <= rx_empty;
tx_fifo : tiny_fifo
port map (
din => din,
rd_clk => fx2_clk_i,
rd_en => tx_rd_en,
rst => rst_i,
wr_clk => clk_i,
wr_en => wr_en,
dout => tx_dout,
empty => tx_empty,
full => wr_full);
end Behavioral;
| gpl-2.0 | 595cd401202264fa4f09aa7c61bec391 | 0.561938 | 2.553004 | false | false | false | false |
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