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capitanov/MinesweeperFPGA | src/game_cores/cl_square.vhd | 1 | 3,602 | --------------------------------------------------------------------------------
--
-- Title : cl_square.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game block for square 8x8
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.ctrl_types_pkg.array8x8;
entity cl_square is
generic(
constant yend : std_logic_vector(4 downto 0):="11000";
constant ystart : std_logic_vector(4 downto 0):="10000";
constant xend : std_logic_vector(6 downto 0):="0011000";
constant xstart : std_logic_vector(6 downto 0):="0010000"
);
port(
-- system signals:
clk : in std_logic;
reset : in std_logic;
-- vga XoY coordinates:
show_disp : in array8x8;
--data_hide : in std_logic;
display : in std_logic;
x_char : in std_logic_vector(9 downto 0); -- X line: 0:79
y_char : in std_logic_vector(8 downto 0); -- Y line: 0:29
-- out color scheme:
rgb : out std_logic_vector(2 downto 0)
);
end cl_square;
architecture cl_square of cl_square is
signal data_rom : std_logic_vector(7 downto 0);
signal x_in : std_logic_vector(6 downto 0);
signal y_in : std_logic_vector(4 downto 0);
signal data : std_logic;
signal dataxy : std_logic;
signal x_rev : std_logic_vector(2 downto 0);
signal x_del : std_logic_vector(2 downto 0);
signal x_z : std_logic_vector(2 downto 0);
signal y_charz : std_logic_vector(3 downto 0);
constant color : std_logic_vector(2 downto 0):="001";
begin
y_charz <= y_char(3 downto 0) when rising_edge(clk);
x_in <= x_char(9 downto 3);
y_in <= y_char(8 downto 4);
pr_select3: process(clk, reset) is
begin
if reset = '0' then
dataxy <= '0';
elsif rising_edge(clk) then
if display = '0' then
dataxy <= '0';
else
if ((xstart <= x_in) and (x_in < xend)) then
if ((ystart <= y_in) and (y_in < yend)) then
dataxy <= not show_disp(conv_integer(x_in(2 downto 0)))(conv_integer(y_in(2 downto 0)));
else
dataxy <= '0';
end if;
else
dataxy <= '0';
end if;
end if;
end if;
end process;
pr_new_box: process(clk, reset)
begin
if reset = '0' then
data_rom <= x"00";
elsif rising_edge(clk) then
if (dataxy = '1') then
case y_charz(3 downto 0) is
when x"0" => data_rom <= x"FE";
when x"1" => data_rom <= x"FE";
when x"2" => data_rom <= x"FE";
when x"3" => data_rom <= x"FE";
when x"4" => data_rom <= x"FE";
when x"5" => data_rom <= x"FE";
when x"6" => data_rom <= x"FE";
when x"7" => data_rom <= x"FE";
when x"8" => data_rom <= x"FE";
when x"9" => data_rom <= x"FE";
when x"A" => data_rom <= x"FE";
when x"B" => data_rom <= x"FE";
when x"C" => data_rom <= x"FE";
when x"D" => data_rom <= x"FE";
when x"E" => data_rom <= x"FE";
when others => data_rom <= x"00";
end case;
else
data_rom <= x"00";
end if;
end if;
end process;
g_rev: for ii in 0 to 2 generate
begin
x_rev(ii) <= not x_char(ii) when rising_edge(clk);
end generate;
x_del <= x_rev when rising_edge(clk);
x_z <= x_del when rising_edge(clk);
pr_sw_sel: process(clk, reset) is
begin
if reset = '0' then
data <= '0';
elsif rising_edge(clk) then
data <= data_rom(to_integer(unsigned(x_z)));
end if;
end process;
g_rgb: for ii in 0 to 2 generate
begin
rgb(ii) <= data and color(ii);
end generate;
end cl_square; | mit | 6a12bd47b71664af66394fda07ee9e61 | 0.555802 | 2.68006 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/core.vhd | 1 | 10,477 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity core is
end core;
architecture BEHAVIOR of core is
component clock is
port(
pulse : out std_logic
);
end component;
component alu is
port(
func : in std_logic_vector(3 downto 0);
busA : in std_logic_vector(15 downto 0);
busB : in std_logic_vector(15 downto 0);
inZ : in std_logic;
inS : in std_logic;
inO : in std_logic;
outZ : out std_logic;
outS : out std_logic;
outO : out std_logic;
busC : out std_logic_vector(15 downto 0)
);
end component;
component bB is
port(
S_GRB, S_PR_F, S_MAR_F, S_MDR_F : in std_logic_vector(15 downto 0);
addr : in std_logic_vector(7 downto 0);
S_s_ctl : in std_logic_vector(4 downto 0);
S_BUS_B : out std_logic_vector(15 downto 0)
);
end component;
component bC is
port(
S_BUS_C : inout std_logic_vector(15 downto 0)
);
end component;
component busA is
port(
clock : in std_logic;
MDR : in std_logic_vector(15 downto 0);
GR : in std_logic_vector(15 downto 0);
ADDR : in std_logic_vector(7 downto 0);
SI : in std_logic_vector(2 downto 0);
busA_out : out std_logic_vector(15 downto 0)
);
end component;
component csgc is
port(
clk : in std_logic;
mlang : in std_logic_vector(15 downto 0);
ba_ctl : out std_logic_vector(2 downto 0);
bb_ctl : out std_logic_vector(4 downto 0);
address : out std_logic_vector(7 downto 0);
gr_lat : out std_logic;
gra : out std_logic_vector(3 downto 0);
grb : out std_logic_vector(3 downto 0);
grc : out std_logic_vector(3 downto 0);
ir_lat : out std_logic;
fr_lat : out std_logic;
pr_lat : out std_logic;
pr_cnt : out std_logic;
mar_lat : out std_logic;
mdr_lat : out std_logic;
mdr_sel : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
func : out std_logic_vector(3 downto 0);
phaseView : out std_logic_vector(3 downto 0)
);
end component;
component fr is
port(
clk : in std_logic;
latch : in std_logic;
inZF : in std_logic;
inSF : in std_logic;
inOF : in std_logic;
outZF : out std_logic;
outSF : out std_logic;
outOF : out std_logic
);
end component;
component gr is
port(
clk, S_GRlat : in std_logic;
S_ctl_a, S_ctl_b, S_ctl_c : in std_logic_vector(3 downto 0);
S_BUS_C : in std_logic_vector(15 downto 0);
S_BUS_A, S_BUS_B : out std_logic_vector(15 downto 0);
GR0_View, GR1_View, GR2_View, GR3_View,
GR4_View, GR5_View, GR6_View, GR7_View,
GR8_View, GR9_View, GR10_View, GR11_View,
GR12_View, GR13_View, GR14_View, GR15_View : out std_logic_vector(15 downto 0)
);
end component;
component inst is
port(
clock : in std_logic;
busA : in std_logic_vector(15 downto 0);
latch : in std_logic;
Mlang : out std_logic_vector(15 downto 0)
);
end component;
component MAR is
port(
clk, lat : in std_logic;
busC : in std_logic_vector(15 downto 0);
M_ad16 : out std_logic_vector(15 downto 0);
M_ad8 : out std_logic_vector(7 downto 0)
);
end component;
component mdr is
port(
clock : in std_logic;
busC : in std_logic_vector(15 downto 0);
latch : in std_logic;
memo : in std_logic_vector(15 downto 0);
sel : in std_logic;
data : out std_logic_vector(15 downto 0)
);
end component;
component mem is
port(
clk, read, write : in std_logic;
S_MAR_F : in std_logic_vector(7 downto 0);
S_MDR_F : in std_logic_vector(15 downto 0);
data : out std_logic_vector(15 downto 0)
);
end component;
component pr is
port(
clk, S_PRlat, S_s_inc : in std_logic;
S_BUS_C : in std_logic_vector(15 downto 0);
S_PR_F : out std_logic_vector(15 downto 0)
);
end component;
-- clock
signal pulse : std_logic;
-- alu
signal alu_fr_z : std_logic;
signal alu_fr_s : std_logic;
signal alu_fr_o : std_logic;
-- bB
signal busb_alu : std_logic_vector(15 downto 0);
-- bC
signal alu_busc_others : std_logic_vector(15 downto 0);
-- busA
signal busa_alu_ir: std_logic_vector(15 downto 0);
-- csgc
signal csgc_busa_ctl : std_logic_vector(2 downto 0);
signal csgc_busb_ctl : std_logic_vector(4 downto 0);
signal csgc_busab_addr : std_logic_vector(7 downto 0);
signal csgc_gr_lat : std_logic;
signal csgc_gr_asel : std_logic_vector(3 downto 0);
signal csgc_gr_bsel : std_logic_vector(3 downto 0);
signal csgc_gr_csel : std_logic_vector(3 downto 0);
signal csgc_ir_lat : std_logic;
signal csgc_fr_lat : std_logic;
signal csgc_pr_lat : std_logic;
signal csgc_pr_cntup : std_logic;
signal csgc_mar_lat : std_logic;
signal csgc_mdr_lat : std_logic;
signal csgc_mdr_sel : std_logic;
signal csgc_mem_read : std_logic;
signal csgc_mem_write : std_logic;
signal csgc_alu_func : std_logic_vector(3 downto 0);
signal phaseView : std_logic_vector(3 downto 0);
-- fr
signal fr_alu_z : std_logic;
signal fr_alu_s : std_logic;
signal fr_alu_o : std_logic;
-- gr
signal gr_busa : std_logic_vector(15 downto 0);
signal gr_busb : std_logic_vector(15 downto 0);
signal GR0_View, GR1_View, GR2_View, GR3_View,
GR4_View, GR5_View, GR6_View, GR7_View,
GR8_View, GR9_View, GR10_View, GR11_View,
GR12_View, GR13_View, GR14_View, GR15_View : std_logic_vector(15 downto 0);
-- inst
signal ir_csgc : std_logic_vector(15 downto 0);
-- MAR
signal mar_busb : std_logic_vector(15 downto 0);
signal mar_mem : std_logic_vector(7 downto 0);
-- mdr
signal mdr_busab_mem : std_logic_vector(15 downto 0);
-- memory
signal mem_mdr : std_logic_vector(15 downto 0);
-- pr
signal pr_busb : std_logic_vector(15 downto 0);
begin
clock_a : clock port map(
pulse => pulse
);
alu_a : alu port map(
func => csgc_alu_func,
busA => busa_alu_ir,
busB => busb_alu,
inZ => fr_alu_z,
inS => fr_alu_s,
inO => fr_alu_o,
outZ => alu_fr_z,
outS => alu_fr_s,
outO => alu_fr_o,
busC => alu_busc_others
);
bB_a : bB port map(
S_GRB => gr_busb,
S_PR_F => pr_busb,
S_MAR_F => mar_busb,
S_MDR_F => mdr_busab_mem,
addr => csgc_busab_addr,
S_s_ctl => csgc_busb_ctl,
S_BUS_B => busb_alu
);
-- bC_a : bC port map(
-- S_BUS_C => alu_busc_others
-- );
busA_a : busA port map(
clock => pulse,
MDR => mdr_busab_mem,
GR => gr_busa,
ADDR => csgc_busab_addr,
SI => csgc_busa_ctl,
busA_out => busa_alu_ir
);
csgc_a : csgc port map(
clk => pulse,
mlang => ir_csgc,
ba_ctl => csgc_busa_ctl,
bb_ctl => csgc_busb_ctl,
address => csgc_busab_addr,
gr_lat => csgc_gr_lat,
gra => csgc_gr_asel,
grb => csgc_gr_bsel,
grc => csgc_gr_csel,
ir_lat => csgc_ir_lat,
fr_lat => csgc_fr_lat,
pr_lat => csgc_pr_lat,
pr_cnt => csgc_pr_cntup,
mar_lat => csgc_mar_lat,
mdr_lat => csgc_mdr_lat,
mdr_sel => csgc_mdr_sel,
m_read => csgc_mem_read,
m_write => csgc_mem_write,
func => csgc_alu_func,
phaseView => phaseView
);
fr_a : fr port map(
clk => pulse,
latch => csgc_fr_lat,
inZF => alu_fr_z,
inSF => alu_fr_s,
inOF => alu_fr_o,
outZF => fr_alu_z,
outSF => fr_alu_s,
outOF => fr_alu_o
);
gr_a : gr port map(
clk => pulse,
S_GRlat => csgc_gr_lat,
S_ctl_a => csgc_gr_asel,
S_ctl_b => csgc_gr_bsel,
S_ctl_c => csgc_gr_csel,
S_BUS_C => alu_busc_others,
S_BUS_A => gr_busa,
S_BUS_B => gr_busb,
GR0_View => GR0_View, GR1_View => GR1_View, GR2_View => GR2_View, GR3_View => GR3_View,
GR4_View => GR4_View, GR5_View => GR5_View, GR6_View => GR6_View, GR7_View => GR7_View,
GR8_View => GR8_View, GR9_View => GR9_View, GR10_View => GR10_View, GR11_View => GR11_View,
GR12_View => GR12_View, GR13_View => GR13_View, GR14_View => GR14_View, GR15_View => GR15_View
);
inst_a : inst port map(
clock => pulse,
busA => busa_alu_ir,
latch => csgc_ir_lat,
Mlang => ir_csgc
);
MAR_a : MAR port map(
clk => pulse,
lat => csgc_mar_lat,
busC => alu_busc_others,
M_ad16 => mar_busb,
M_ad8 => mar_mem
);
mdr_a : mdr port map(
clock => pulse,
busC => alu_busc_others,
latch => csgc_mdr_lat,
memo => mem_mdr,
sel => csgc_mdr_sel,
data => mdr_busab_mem
);
mem_a : mem port map(
clk => pulse,
read => csgc_mem_read,
write => csgc_mem_write,
S_MAR_F => mar_mem,
S_MDR_F => mdr_busab_mem,
data => mem_mdr
);
pr_a : pr port map(
clk => pulse,
S_PRlat => csgc_pr_lat,
S_s_inc => csgc_pr_cntup,
S_BUS_C => alu_busc_others,
S_PR_F => pr_busb
);
end BEHAVIOR;
| mit | 6ff068e0893dadaf16fc83eceb4167d9 | 0.49938 | 3.256761 | false | false | false | false |
znuh/open-nexys | fx2async/top.vhd | 1 | 3,418 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
port ( clk_i: in std_logic;
fx2_wr_full_i : in STD_LOGIC;
fx2_rd_empty_i : in STD_LOGIC;
fx2_data_io : inout STD_LOGIC_VECTOR (7 downto 0);
fx2_fifo_addr_o : out STD_LOGIC_VECTOR (1 downto 0);
fx2_slwr_o : out STD_LOGIC;
fx2_slrd_o : out std_logic;
fx2_sloe_o : out std_logic;
fx2_slcs_o : out std_logic;
fx2_pktend_o : out STD_LOGIC;
sw_i: in std_logic_vector(7 downto 0);
btn_i: in std_logic_vector(3 downto 0);
led_o: out std_logic_vector(7 downto 0)
);
end top;
architecture Behavioral of top is
component fx2async is
Port(
fx2_wr_full_i : in STD_LOGIC;
fx2_rd_empty_i : in STD_LOGIC;
fx2_data_io : inout STD_LOGIC_VECTOR (7 downto 0);
fx2_fifo_addr_o : out STD_LOGIC_VECTOR (1 downto 0);
fx2_slwr_o : out STD_LOGIC;
fx2_slrd_o : out std_logic;
fx2_sloe_o : out std_logic;
fx2_slcs_o : out std_logic;
fx2_pktend_o : out STD_LOGIC;
usb_data_i : in std_logic_vector(7 downto 0);
usb_data_o : out std_logic_vector(7 downto 0);
usb_wr_en_i : in std_logic;
usb_rd_en_i : in std_logic;
usb_wr_strobe_o : out std_logic;
usb_rd_strobe_o : out std_logic;
usb_pktend_i : in std_logic;
usb_pktstart_o : out std_logic;
clk_i : in std_logic;
rst_i : in std_logic
);
end component;
signal usb_txd : std_logic_vector(7 downto 0);
signal usb_rxd : std_logic_vector(7 downto 0);
signal usb_wr : std_logic;
signal usb_rd : std_logic;
signal usb_wr_strobe : std_logic;
signal usb_rd_strobe : std_logic;
signal usb_pktend : std_logic;
signal usb_pktstart: std_logic;
signal rst : std_logic := '1';
signal delay_cnt : std_logic_vector(15 downto 0) := (others => '0');
signal sw_r1 : std_logic_vector(7 downto 0);
signal sw_r2 : std_logic_vector(7 downto 0);
begin
fx2async_inst : fx2async
port map (
-- einfach durchreichen...
fx2_wr_full_i => fx2_wr_full_i,
fx2_rd_empty_i => fx2_rd_empty_i,
fx2_data_io => fx2_data_io,
fx2_fifo_addr_o => fx2_fifo_addr_o,
fx2_slwr_o => fx2_slwr_o,
fx2_slrd_o => fx2_slrd_o,
fx2_sloe_o => fx2_sloe_o,
fx2_slcs_o => fx2_slcs_o,
fx2_pktend_o => fx2_pktend_o,
-- user interface zum USB interface
usb_data_i => usb_txd,
usb_data_o => usb_rxd,
usb_wr_en_i => usb_wr,
usb_rd_en_i => usb_rd,
usb_wr_strobe_o => usb_wr_strobe,
usb_rd_strobe_o => usb_rd_strobe,
usb_pktend_i => usb_pktend,
usb_pktstart_o => usb_pktstart,
clk_i => clk_i,
rst_i => rst
);
process
begin
wait until rising_edge(clk_i);
-- reset generator for usb if
if delay_cnt /= x"ffff" then
delay_cnt <= delay_cnt + 1;
rst <= '1';
else
rst <= '0';
end if;
-- we like well defined init states!
if rst = '1' then
usb_wr <= '0';
usb_rd <= '0';
usb_pktend <= '0';
else
-- always receive
usb_rd <= '1';
-- got a byte
if usb_rd_strobe = '1' then
-- output 1st byte on LEDs
if usb_pktstart = '1' then
led_o <= usb_rxd;
end if;
end if;
-- always send
usb_wr <= '1';
-- sync switches
sw_r1 <= sw_i;
sw_r2 <= sw_r1;
-- send switches
usb_txd <= sw_r2;
end if;
end process;
end Behavioral;
| gpl-2.0 | 18f631149bbf2c7c7dc45e7cc2042b0f | 0.587185 | 2.579623 | false | false | false | false |
znuh/open-nexys | bscan_la/bscan_la.vhd | 1 | 4,874 | ----------------------------------------------------------------------------------
-- la.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependend IO modules and defines all inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bscan_la is
Port(
clock : in std_logic;
exClock : in std_logic;
input : in std_logic_vector(31 downto 0);
reset : in std_logic;
CAPTURE : in std_logic;
DRCK : in std_logic;
SEL : in std_logic;
SHIFT : in std_logic;
UPDATE : in std_logic;
TDO : out std_logic;
TDI : in std_logic
);
end bscan_la;
architecture Behavioral of bscan_la is
COMPONENT core
PORT(
clock : IN std_logic;
extReset : IN std_logic;
cmd : IN std_logic_vector(39 downto 0);
execute : IN std_logic;
input : IN std_logic_vector(31 downto 0);
inputClock : IN std_logic;
sampleReady50 : OUT std_logic;
output : out STD_LOGIC_VECTOR (31 downto 0);
outputSend : out STD_LOGIC;
outputBusy : in STD_LOGIC;
memoryIn : IN std_logic_vector(31 downto 0);
memoryOut : OUT std_logic_vector(31 downto 0);
memoryRead : OUT std_logic;
memoryWrite : OUT std_logic
);
END COMPONENT;
COMPONENT sram_bram
PORT(
clock : IN std_logic;
input : IN std_logic_vector(31 downto 0);
output : OUT std_logic_vector(31 downto 0);
read : IN std_logic;
write : IN std_logic
);
END COMPONENT;
component bscan_sreg is
GENERIC (
SREG_LEN : integer := 40
);
Port (
CAPTURE_i : in std_logic;
DRCK_i : in std_logic;
SEL_i : in std_logic;
SHIFT_i : in std_logic;
UPDATE_i : in std_logic;
TDI_i : in std_logic;
TDO_o: out std_logic;
clk_i : in std_logic;
Data_i : in std_logic_vector((SREG_LEN - 1) downto 0);
Data_o : out std_logic_vector((SREG_LEN - 1) downto 0);
strobe_o : out std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (31 downto 0);
signal output : std_logic_vector (31 downto 0);
signal read, write, execute, send, busy : std_logic;
signal din, dout : std_logic_vector(39 downto 0);
signal strobe : std_logic;
begin
-- JTAG
process(clock)
begin
if rising_edge(clock) then
execute <= '0';
-- update from jtag
if strobe = '1' then
busy <= '0';
cmd <= dout;
din(39) <= '0';
if dout(7 downto 0) = x"02" then
din <= x"80534c4131";
else
execute <= '1';
end if;
end if;
-- TODO: this isn't safe yet!
-- TODO: output -> din on strobe = '1'
if send = '1' then
busy <= '1';
din <= x"80" & output;
end if;
end if;
end process;
Inst_core: core PORT MAP(
clock => clock,
extReset => reset,
cmd => cmd,
execute => execute,
input => input,
inputClock => exClock,
--sampleReady50 => ready50,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write
);
bscan_sreg_inst : bscan_sreg
Port map (
CAPTURE_i => CAPTURE,
DRCK_i => DRCK,
SEL_i => SEL,
SHIFT_i => SHIFT,
UPDATE_i => UPDATE,
TDI_i => TDI,
TDO_o => TDO,
clk_i => clock,
Data_i => din,
Data_o => dout,
strobe_o => strobe
);
Inst_sram: sram_bram PORT MAP(
clock => clock,
input => memoryOut,
output => memoryIn,
read => read,
write => write
);
end Behavioral;
| gpl-2.0 | f183b4d7ce5903555fb54b0be00e181e | 0.621871 | 3.361379 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_37x512/example_design/fifo_37x512_top_wrapper.vhd | 1 | 18,992 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_37x512_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_37x512_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(37-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(37-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_37x512_top_wrapper;
architecture xilinx of fifo_37x512_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_37x512_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(37-1 DOWNTO 0);
DOUT : OUT std_logic_vector(37-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_37x512_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 405ef4963a4ed3dc8f43795c91253a54 | 0.48631 | 3.964099 | false | false | false | false |
znuh/open-nexys | bscan_user/top.vhd | 1 | 2,487 | -- Copyright 2009 Benedikt 'Hunz' Heinz - [email protected]
--
-- simple BSCAN_SPARTAN3 USER1 sample for digilent nexys board
-- 8 Bit DR
--
-- references:
-- http://www.xilinx.com/itp/xilinx5/data/docs/lib/lib0061_45.html
-- http://www.xilinx.com/support/answers/10703.htm
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
Port ( led : out std_logic_vector(7 downto 0);
switch : in std_logic_vector(7 downto 0) );
end top;
architecture Behavioral of top is
component BSCAN_SPARTAN3
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal CAPTURE: STD_ULOGIC;
signal DRCK1: STD_ULOGIC;
signal DRCK2: STD_ULOGIC;
signal RESET: STD_ULOGIC;
signal SEL1: STD_ULOGIC;
signal SEL2: STD_ULOGIC;
signal SHIFT: STD_ULOGIC;
signal TDI: STD_ULOGIC;
signal UPDATE: STD_ULOGIC;
signal TDO1: STD_ULOGIC;
signal TDO2: STD_ULOGIC;
signal shiftreg: std_logic_vector(7 downto 0);
begin
BSCAN_SPARTAN3_inst : BSCAN_SPARTAN3
port map (
CAPTURE => CAPTURE, -- CAPTURE output from TAP controller
DRCK1 => DRCK1, -- Data register output for USER1 functions
DRCK2 => DRCK2, -- Data register output for USER2 functions
RESET => RESET, -- Reset output from TAP controller
SEL1 => SEL1, -- USER1 active output
SEL2 => SEL2, -- USER2 active output
SHIFT => SHIFT, -- SHIFT output from TAP controller
TDI => TDI, -- TDI output from TAP controller
UPDATE => UPDATE, -- UPDATE output from TAP controller
TDO1 => TDO1, -- Data input for USER1 function
TDO2 => TDO2 -- Data input for USER2 function
);
--led <= CAPTURE & DRCK1 & SEL1 & SHIFT & TDI & UPDATE & "00";
process(DRCK1,UPDATE,SEL1)
begin
if SEL1='1' then
if UPDATE='1' then
led <= shiftreg;
elsif CAPTURE='1' then
shiftreg <= switch;
elsif rising_edge(DRCK1) then
shiftreg <= TDI & shiftreg(7 downto 1);
--if CAPTURE='1' then
-- shiftreg <= switch;
--end if;
end if;
end if;
end process;
TDO1 <= shiftreg(0);
end Behavioral;
| gpl-2.0 | 3d6bda823ac2347c2958681efb3e7813 | 0.629674 | 3.420908 | false | false | false | false |
TMU-VHDL-team2/sqrt | fpga/tb_sqrt.vhd | 1 | 2,218 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY tb_sqrt IS
END tb_sqrt;
ARCHITECTURE sqrt_arch OF tb_sqrt IS
-- constants
-- signals
SIGNAL btn : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL hex0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL hex1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL hex2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL hex3 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL led : STD_LOGIC_VECTOR(9 DOWNTO 0);
--SIGNAL pulse : STD_LOGIC;
SIGNAL sw : STD_LOGIC_VECTOR(9 DOWNTO 0);
COMPONENT sqrt
PORT (
btn : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
hex0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
hex1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
hex2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
hex3 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
led : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
--pulse : IN STD_LOGIC;
sw : IN STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
BEGIN
i1 : sqrt
PORT MAP (
-- list connections between master ports and signals
btn => btn,
hex0 => hex0,
hex1 => hex1,
hex2 => hex2,
hex3 => hex3,
led => led,
--pulse => pulse,
sw => sw
);
init : PROCESS
-- variable declarations
BEGIN
-- code that executes only once
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
-- wait for about 3 ms;
-- ans = sqrt("c350") = X"df.9b" (preset)
-- hex[0, 1, 2, 3] = [83, 98, 0e, a1]
btn <= "111";
sw <= "0000000000";
wait for 1 ms;
-- ans = sqrt(X"fe00") = X"fe.ff"
-- hex[0, 1, 2, 3] = [8e, 8e, 06, 8e]
btn <= "110"; -- set sw <= X"00", pushing btn(0)
sw(7 downto 0) <= X"00";
wait for 50 ns;
btn <= "101"; -- set sw <= X"fe", pushing btn(1)
sw(7 downto 0) <= X"fe";
wait for 1 us;
btn <= "011"; -- push btn(2), and wait for finishing program
wait for 1 ms;
-- ans = sqrt(X"c350") = X"df.9b"
-- hex[0, 1, 2, 3] = [83, 98, 0e, a1]
btn <= "110"; -- set sw <= X"50", pushing btn(0)
sw(7 downto 0) <= X"50";
wait for 50 ns;
btn <= "101"; -- set sw <= X"c3", pushing btn(1)
sw(7 downto 0) <= X"c3";
wait for 1 us;
btn <= "011"; -- push btn(2), and wait for finishing program
wait for 1 ms;
WAIT;
END PROCESS always;
END sqrt_arch;
| mit | e0197d6dce8abe67093885b109354a96 | 0.62083 | 2.738272 | false | false | false | false |
intelligenttoasters/CPC2.0 | FPGA/rtl/cpc/YM2149/YM2149_volmix.vhd | 1 | 19,471 | --
-- A simulation model of YM2149 (AY-3-8910 with bells on)
-- Copyright (c) MikeJ - Jan 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email [email protected]
--
-- Revision list
--
-- version 001 initial release
--
-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
--
-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
-- vol 15 .. 0
-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
-- to produced all the required values.
-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
--
-- NOTE, this component uses a volume table for accurate mixing of the three analogue channels,
-- where the outputs are wired together - like in the Atari ST
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity YM2149 is
port (
-- data bus
I_DA : in std_logic_vector(7 downto 0);
O_DA : out std_logic_vector(7 downto 0);
O_DA_OE_L : out std_logic;
-- control
I_A9_L : in std_logic;
I_A8 : in std_logic;
I_BDIR : in std_logic;
I_BC2 : in std_logic;
I_BC1 : in std_logic;
I_SEL_L : in std_logic;
O_AUDIO : out std_logic_vector(7 downto 0);
-- port a
I_IOA : in std_logic_vector(7 downto 0);
O_IOA : out std_logic_vector(7 downto 0);
O_IOA_OE_L : out std_logic;
-- port b
I_IOB : in std_logic_vector(7 downto 0);
O_IOB : out std_logic_vector(7 downto 0);
O_IOB_OE_L : out std_logic;
--
ENA : in std_logic; -- clock enable for higher speed operation
RESET_L : in std_logic;
CLK : in std_logic -- note 6 Mhz
);
end;
architecture RTL of YM2149 is
component vol_table
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(9 downto 0)
);
end component;
-- signals
type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0);
type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
signal noise_div : std_logic := '0';
signal ena_div : std_logic;
signal ena_div_noise : std_logic;
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
-- registers
signal addr : std_logic_vector(7 downto 0);
signal busctrl_addr : std_logic;
signal busctrl_we : std_logic;
signal busctrl_re : std_logic;
signal reg : array_16x8;
signal env_reset : std_logic;
signal ioa_inreg : std_logic_vector(7 downto 0);
signal iob_inreg : std_logic_vector(7 downto 0);
signal noise_gen_cnt : std_logic_vector(4 downto 0);
signal noise_gen_op : std_logic;
signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
signal env_gen_cnt : std_logic_vector(15 downto 0);
signal env_ena : std_logic;
signal env_hold : std_logic;
signal env_inc : std_logic;
signal env_vol : std_logic_vector(4 downto 0);
signal vol_table_in : std_logic_vector(11 downto 0);
signal vol_table_out : std_logic_vector(9 downto 0);
begin
-- cpu i/f
p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
variable cs : std_logic;
variable sel : std_logic_vector(2 downto 0);
begin
-- BDIR BC2 BC1 MODE
-- 0 0 0 inactive
-- 0 0 1 address
-- 0 1 0 inactive
-- 0 1 1 read
-- 1 0 0 address
-- 1 0 1 inactive
-- 1 1 0 write
-- 1 1 1 read
busctrl_addr <= '0';
busctrl_we <= '0';
busctrl_re <= '0';
cs := '0';
if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
cs := '1';
end if;
sel := (I_BDIR & I_BC2 & I_BC1);
case sel is
when "000" => null;
when "001" => busctrl_addr <= '1';
when "010" => null;
when "011" => busctrl_re <= cs;
when "100" => busctrl_addr <= '1';
when "101" => null;
when "110" => busctrl_we <= cs;
when "111" => busctrl_addr <= '1';
when others => null;
end case;
end process;
p_oe : process(busctrl_re)
begin
-- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
O_DA_OE_L <= not (busctrl_re);
end process;
-- CLOCKED
--p_waddr : process
--begin
---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
--wait until rising_edge(CLK);
--if (RESET_L = '0') then
--addr <= (others => '0');
--else
--if (busctrl_addr = '1') then
--addr <= I_DA;
--end if;
--end if;
--end process;
--p_wdata : process
--begin
---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
--wait until rising_edge(CLK);
--env_reset <= '0';
--if (RESET_L = '0') then
--reg <= (others => (others => '0'));
--env_reset <= '1';
--else
--env_reset <= '0';
--if (busctrl_we = '1') then
--case addr(3 downto 0) is
--when x"0" => reg(0) <= I_DA;
--when x"1" => reg(1) <= I_DA;
--when x"2" => reg(2) <= I_DA;
--when x"3" => reg(3) <= I_DA;
--when x"4" => reg(4) <= I_DA;
--when x"5" => reg(5) <= I_DA;
--when x"6" => reg(6) <= I_DA;
--when x"7" => reg(7) <= I_DA;
--when x"8" => reg(8) <= I_DA;
--when x"9" => reg(9) <= I_DA;
--when x"A" => reg(10) <= I_DA;
--when x"B" => reg(11) <= I_DA;
--when x"C" => reg(12) <= I_DA;
--when x"D" => reg(13) <= I_DA; env_reset <= '1';
--when x"E" => reg(14) <= I_DA;
--when x"F" => reg(15) <= I_DA;
--when others => null;
--end case;
--end if;
--end if;
--end process;
-- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock.
p_waddr : process(reset_l, busctrl_addr)
begin
-- looks like registers are latches in real chip, but the address is caught at the end of the address state.
if (RESET_L = '0') then
addr <= (others => '0');
elsif falling_edge(busctrl_addr) then -- yuk
addr <= I_DA;
end if;
end process;
p_wdata : process(reset_l, busctrl_we, addr)
begin
if (RESET_L = '0') then
reg <= (others => (others => '0'));
elsif falling_edge(busctrl_we) then
case addr(3 downto 0) is
when x"0" => reg(0) <= I_DA;
when x"1" => reg(1) <= I_DA;
when x"2" => reg(2) <= I_DA;
when x"3" => reg(3) <= I_DA;
when x"4" => reg(4) <= I_DA;
when x"5" => reg(5) <= I_DA;
when x"6" => reg(6) <= I_DA;
when x"7" => reg(7) <= I_DA;
when x"8" => reg(8) <= I_DA;
when x"9" => reg(9) <= I_DA;
when x"A" => reg(10) <= I_DA;
when x"B" => reg(11) <= I_DA;
when x"C" => reg(12) <= I_DA;
when x"D" => reg(13) <= I_DA;
when x"E" => reg(14) <= I_DA;
when x"F" => reg(15) <= I_DA;
when others => null;
end case;
end if;
env_reset <= '0';
if (busctrl_we = '1') and (addr(3 downto 0) = x"D") then
env_reset <= '1';
end if;
end process;
p_rdata : process(busctrl_re, addr, reg)
begin
O_DA <= (others => '0'); -- 'X'
if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
case addr(3 downto 0) is
when x"0" => O_DA <= reg(0) ;
when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
when x"2" => O_DA <= reg(2) ;
when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
when x"4" => O_DA <= reg(4) ;
when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ;
when x"7" => O_DA <= reg(7) ;
when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ;
when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ;
when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ;
when x"B" => O_DA <= reg(11);
when x"C" => O_DA <= reg(12);
when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
when x"E" => if (reg(7)(6) = '0') then -- input
O_DA <= ioa_inreg;
else
O_DA <= reg(14); -- read output reg
end if;
when x"F" => if (Reg(7)(7) = '0') then
O_DA <= iob_inreg;
else
O_DA <= reg(15);
end if;
when others => null;
end case;
end if;
end process;
--
p_divider : process
begin
wait until rising_edge(CLK);
-- / 8 when SEL is high and /16 when SEL is low
if (ENA = '1') then
ena_div <= '0';
ena_div_noise <= '0';
if (cnt_div = "0000") then
cnt_div <= (not I_SEL_L) & "111";
ena_div <= '1';
noise_div <= not noise_div;
if (noise_div = '1') then
ena_div_noise <= '1';
end if;
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
p_noise_gen : process
variable noise_gen_comp : std_logic_vector(4 downto 0);
variable poly17_zero : std_logic;
begin
wait until rising_edge(CLK);
if (reg(6)(4 downto 0) = "00000") then
noise_gen_comp := "00000";
else
noise_gen_comp := (reg(6)(4 downto 0) - "1");
end if;
poly17_zero := '0';
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
if (ENA = '1') then
if (ena_div_noise = '1') then -- divider ena
if (noise_gen_cnt >= noise_gen_comp) then
noise_gen_cnt <= "00000";
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
else
noise_gen_cnt <= (noise_gen_cnt + "1");
end if;
end if;
end if;
end process;
noise_gen_op <= poly17(0);
p_tone_gens : process
variable tone_gen_freq : array_3x12;
variable tone_gen_comp : array_3x12;
begin
wait until rising_edge(CLK);
-- looks like real chips count up - we need to get the Exact behaviour ..
tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
-- period 0 = period 1
for i in 1 to 3 loop
if (tone_gen_freq(i) = x"000") then
tone_gen_comp(i) := x"000";
else
tone_gen_comp(i) := (tone_gen_freq(i) - "1");
end if;
end loop;
if (ENA = '1') then
for i in 1 to 3 loop
if (ena_div = '1') then -- divider ena
if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
tone_gen_cnt(i) <= x"000";
tone_gen_op(i) <= not tone_gen_op(i);
else
tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
end if;
end if;
end loop;
end if;
end process;
p_envelope_freq : process
variable env_gen_freq : std_logic_vector(15 downto 0);
variable env_gen_comp : std_logic_vector(15 downto 0);
begin
wait until rising_edge(CLK);
env_gen_freq := reg(12) & reg(11);
-- envelope freqs 1 and 0 are the same.
if (env_gen_freq = x"0000") then
env_gen_comp := x"0000";
else
env_gen_comp := (env_gen_freq - "1");
end if;
if (ENA = '1') then
env_ena <= '0';
if (ena_div = '1') then -- divider ena
if (env_gen_cnt >= env_gen_comp) then
env_gen_cnt <= x"0000";
env_ena <= '1';
else
env_gen_cnt <= (env_gen_cnt + "1");
end if;
end if;
end if;
end process;
p_envelope_shape : process(env_reset, CLK)
variable is_bot : boolean;
variable is_bot_p1 : boolean;
variable is_top_m1 : boolean;
variable is_top : boolean;
begin
-- envelope shapes
-- C AtAlH
-- 0 0 x x \___
--
-- 0 1 x x /___
--
-- 1 0 0 0 \\\\
--
-- 1 0 0 1 \___
--
-- 1 0 1 0 \/\/
-- ___
-- 1 0 1 1 \
--
-- 1 1 0 0 ////
-- ___
-- 1 1 0 1 /
--
-- 1 1 1 0 /\/\
--
-- 1 1 1 1 /___
if (env_reset = '1') then
-- load initial state
if (reg(13)(2) = '0') then -- attack
env_vol <= "11111";
env_inc <= '0'; -- -1
else
env_vol <= "00000";
env_inc <= '1'; -- +1
end if;
env_hold <= '0';
elsif rising_edge(CLK) then
is_bot := (env_vol = "00000");
is_bot_p1 := (env_vol = "00001");
is_top_m1 := (env_vol = "11110");
is_top := (env_vol = "11111");
if (ENA = '1') then
if (env_ena = '1') then
if (env_hold = '0') then
if (env_inc = '1') then
env_vol <= (env_vol + "00001");
else
env_vol <= (env_vol + "11111");
end if;
end if;
-- envelope shape control.
if (reg(13)(3) = '0') then
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
else
if is_top then env_hold <= '1'; end if;
end if;
else
if (reg(13)(0) = '1') then -- hold = 1
if (env_inc = '0') then -- down
if (reg(13)(1) = '1') then -- alt
if is_bot then env_hold <= '1'; end if;
else
if is_bot_p1 then env_hold <= '1'; end if;
end if;
else
if (reg(13)(1) = '1') then -- alt
if is_top then env_hold <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
end if;
end if;
elsif (reg(13)(1) = '1') then -- alternate
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
if is_top then env_hold <= '0'; env_inc <= '0'; end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
p_chan_mixer_table : process
variable chan_mixed : std_logic_vector(2 downto 0);
begin
wait until rising_edge(CLK);
if (ENA = '1') then
chan_mixed(0) := (reg(7)(0) or tone_gen_op(1)) and (reg(7)(3) or noise_gen_op);
chan_mixed(1) := (reg(7)(1) or tone_gen_op(2)) and (reg(7)(4) or noise_gen_op);
chan_mixed(2) := (reg(7)(2) or tone_gen_op(3)) and (reg(7)(5) or noise_gen_op);
vol_table_in <= x"000";
if (chan_mixed(0) = '1') then
if (reg(8)(4) = '0') then
vol_table_in(3 downto 0) <= reg(8)(3 downto 0);
else
vol_table_in(3 downto 0) <= env_vol(4 downto 1);
end if;
end if;
if (chan_mixed(1) = '1') then
if (reg(9)(4) = '0') then
vol_table_in(7 downto 4) <= reg(9)(3 downto 0);
else
vol_table_in(7 downto 4) <= env_vol(4 downto 1);
end if;
end if;
if (chan_mixed(2) = '1') then
if (reg(10)(4) = '0') then
vol_table_in(11 downto 8) <= reg(10)(3 downto 0);
else
vol_table_in(11 downto 8) <= env_vol(4 downto 1);
end if;
end if;
end if;
end process;
u_vol_table : vol_table
port map (
CLK => clk,
ADDR => vol_table_in,
DATA => vol_table_out
);
p_op_mixer : process
variable chan_mixed : std_logic;
variable chan_amp : std_logic_vector(4 downto 0);
begin
wait until rising_edge(CLK);
if (RESET_L = '0') then
O_AUDIO(7 downto 0) <= "00000000";
else
O_AUDIO(7 downto 0) <= vol_table_out(9 downto 2);
end if;
end process;
p_io_ports : process(reg)
begin
-- input low
O_IOA <= reg(14);
O_IOA_OE_L <= not reg(7)(6);
O_IOB <= reg(15);
O_IOB_OE_L <= not reg(7)(7);
end process;
p_io_ports_inreg : process
begin
wait until rising_edge(CLK);
ioa_inreg <= I_IOA;
iob_inreg <= I_IOB;
end process;
end architecture RTL;
| gpl-3.0 | ab6b08dcab4487b7fdddb272a49c1058 | 0.486878 | 3.301289 | false | false | false | false |
znuh/open-nexys | fx2_fifo_test/top_with_la.vhd | 1 | 6,596 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity top is
Port (
sys_clk : in std_logic;
Led: out std_logic_vector(7 downto 0);
sw: in std_logic_vector(7 downto 0);
fx2_wr_full_i : in std_logic;
fx2_rd_empty_i : in std_logic;
fx2_data_io : inout std_logic_vector(7 downto 0);
fx2_clk_i : in std_logic;
fx2_slcs_o : out std_logic;
fx2_slrd_o : out std_logic;
fx2_sloe_o : out std_logic;
fx2_slwr_o : out std_logic;
fx2_pktend_o : out std_logic;
fx2_fifo_addr_o : out std_logic_vector(1 downto 0);
btn : in std_logic_vector(3 downto 0)
);
end top;
architecture Behavioral of top is
component bscan_sreg is
GENERIC (
SREG_LEN : integer := 24
);
Port (
CAPTURE_i : in std_logic;
DRCK_i : in std_logic;
SEL_i : in std_logic;
SHIFT_i : in std_logic;
UPDATE_i : in std_logic;
TDI_i : in std_logic;
TDO_o: out std_logic;
clk_i : in std_logic;
Data_i : in std_logic_vector((SREG_LEN - 1) downto 0);
Data_o : out std_logic_vector((SREG_LEN - 1) downto 0);
strobe_o : out std_logic
);
end component;
component bscan_la is
Port(
clock : in std_logic;
exClock : in std_logic;
input : in std_logic_vector(31 downto 0);
reset : in std_logic;
CAPTURE : in std_logic;
DRCK : in std_logic;
SEL : in std_logic;
SHIFT : in std_logic;
UPDATE : in std_logic;
TDO : out std_logic;
TDI : in std_logic
);
end component;
signal CAPTURE : std_logic;
signal DRCK1 : std_logic;
signal SEL1 : std_logic;
signal SHIFT : std_logic;
signal UPDATE : std_logic;
signal TDO1 : std_logic;
signal TDI : std_logic;
signal din : std_logic_vector(23 downto 0);
signal dout : std_logic_vector(23 downto 0);
signal strobe : std_logic;
signal fx2_dout : std_logic_vector(7 downto 0);
signal fx2_wr : std_logic := '0';
signal fx2_wr_cnt : std_logic_vector(15 downto 0);
signal fx2_notfull_cnt : std_logic_vector(15 downto 0);
signal fx2_wasfull : std_logic := '0';
signal fx2_stop_on_full : std_logic := '0';
signal fx2_no_delay : std_logic := '0';
signal run : std_logic := '0';
signal autostop : std_logic := '1';
signal fx2_last_full : std_logic;
signal fx2_one_left : std_logic;
signal delay : std_logic_vector(3 downto 0);
signal delay_cnt : std_logic_vector(3 downto 0);
signal DRCK2 : std_logic;
signal SEL2 : std_logic;
signal TDO2 : std_logic;
signal la_input : std_logic_vector(31 downto 0);
begin
BSCAN_SPARTAN3_inst : BSCAN_SPARTAN3
port map (
CAPTURE => CAPTURE, -- CAPTURE output from TAP controller
DRCK1 => DRCK1, -- Data register output for USER1 functions
DRCK2 => DRCK2, -- Data register output for USER2 functions
RESET => open, -- Reset output from TAP controller
SEL1 => SEL1, -- USER1 active output
SEL2 => SEL2, -- USER2 active output
SHIFT => SHIFT, -- SHIFT output from TAP controller
TDI => TDI, -- TDI output from TAP controller
UPDATE => UPDATE, -- UPDATE output from TAP controller
TDO1 => TDO1, -- Data input for USER1 function
TDO2 => TDO2 -- Data input for USER2 function
);
bscan_la_inst: bscan_la
port map (
clock => fx2_clk_i,
exClock => '0',
input => la_input,
reset => btn(1),
CAPTURE => CAPTURE,
DRCK => DRCK2,
SEL => SEL2,
SHIFT => SHIFT,
UPDATE => UPDATE,
TDO => TDO2,
TDI => TDI
);
bscan_sreg_inst : bscan_sreg
Port map (
CAPTURE_i => CAPTURE,
DRCK_i => DRCK1,
SEL_i => SEL1,
SHIFT_i => SHIFT,
UPDATE_i => UPDATE,
TDI_i => TDI,
TDO_o => TDO1,
clk_i => fx2_clk_i, --sys_clk,
Data_i => din,
Data_o => dout,
strobe_o => strobe
);
la_input <= x"00000" & fx2_one_left & fx2_wr_full_i & fx2_wasfull & fx2_wr & fx2_data_io;
fx2_fifo_addr_o <= "10";
fx2_slcs_o <= '0';
fx2_slrd_o <= '1';
fx2_sloe_o <= '1';
fx2_slwr_o <= fx2_wr;
Led <= fx2_wr & (not fx2_wr_full_i) & fx2_wasfull & fx2_stop_on_full & fx2_no_delay & "00" & fx2_one_left;
process(fx2_clk_i)
begin
if rising_edge(fx2_clk_i) then
-- FX2 default signals
fx2_data_io <= (others => 'Z');
fx2_pktend_o <= '1';
fx2_wr <= '1';
if fx2_wr_full_i = '0' then
fx2_wasfull <= '1';
end if;
-- did a write cycle
if fx2_wr = '0' then
if fx2_wr_full_i = '1' and fx2_wasfull = '0' then
fx2_notfull_cnt <= fx2_notfull_cnt + 1;
end if;
end if;
-- start button
if btn(0) = '1' then
run <= '1';
end if;
fx2_last_full <= fx2_wr_full_i;
-- insert delay after frame
if fx2_last_full = '1' and fx2_wr_full_i = '0' then
delay_cnt <= delay;
end if;
-- detect rare "full though one left" "corner condition"
if fx2_wr = '1' and fx2_last_full = '1' and fx2_wr_full_i = '0' then
fx2_one_left <= '1';
end if;
-- write?
if delay_cnt /= "000" then
delay_cnt <= delay_cnt - 1;
elsif fx2_wr_cnt /= x"0000" or autostop = '0' then
if (run = '1') and (fx2_wr = '1' or fx2_no_delay = '1') then
--if (fx2_wr_full_i = '1' or fx2_last_full = '1' or fx2_stop_on_full = '0') then
if (fx2_wr_full_i = '1' or fx2_one_left = '1' or fx2_stop_on_full = '0') then
fx2_one_left <= '0';
fx2_data_io <= fx2_dout;
fx2_dout <= fx2_dout + 1;
fx2_wr <= '0';
fx2_wr_cnt <= fx2_wr_cnt - 1;
end if;
end if;
else
run <= '0';
end if;
-- JTAG strobe
if strobe = '1' then
din <= dout;
-- reg. addr
case dout(23 downto 16) is
-- FX2 ctl
when x"80" => fx2_stop_on_full <= dout(0);
fx2_no_delay <= dout(1);
-- some kind of raw mode...
fx2_wr <= not dout(2);
fx2_pktend_o <= not dout(4);
autostop <= not dout(5);
delay <= dout(11 downto 8);
-- FX2 status
when x"00" => din(7 downto 0) <= "000000" & fx2_wr_full_i & fx2_rd_empty_i;
-- FX2 write count
when x"81" => fx2_wr_cnt <= dout(15 downto 0);
fx2_notfull_cnt <= x"0000";
fx2_wasfull <= '0';
-- FX2 written count
when x"01" => din(15 downto 0) <= fx2_notfull_cnt;
-- FX2 data out
when x"82" => fx2_dout <= dout(7 downto 0);
-- FX2 data out
when x"02" => din(7 downto 0) <= fx2_dout;
when others => null;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | da660c8a4a5ef3a579a5e07c17e3e00c | 0.582777 | 2.682391 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_69x512/simulation/fg_tb_synth.vhd | 1 | 10,346 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(69-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(69-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(69-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(69-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 24 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 69,
C_DOUT_WIDTH => 69,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 69,
C_DIN_WIDTH => 69,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 69,
C_DIN_WIDTH => 69,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_69x512_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit | 17a08cbd5e54fe9d014ae72e5dda778e | 0.460275 | 4.108817 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_69x512_hf/simulation/fg_tb_pkg.vhd | 1 | 11,304 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_69x512_hf_top IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(69-1 DOWNTO 0);
DOUT : OUT std_logic_vector(69-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit | dd9f5db4383568913102ed18820dae2b | 0.503715 | 3.931826 | false | false | false | false |
capitanov/MinesweeperFPGA | src/top_level/top_minesweeper.vhd | 1 | 5,284 | --------------------------------------------------------------------------------
--
-- Title : top_minesweeper.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Top level for VGA controller ver. 1.0 based on Spartan3E Starter Kit
--
-- Xilinx Spartan3e - XC3S500E-4FG320C
-- Switches, LEDs, VGA 640x480, Keyboard
--
-- SW<0> - RESET
-- SW<1> - ENABLE
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity top_minesweeper is
generic (
CHIPSCOPE_USE : boolean:=false
);
port(
---- PS/2 IO ----
PS2_CLK : in std_logic; -- CLK FROM PS/2 KEYBOARD
PS2_DATA : in std_logic; -- DATA FROM PS/2 KEYBOAD
---- CLOCK 50 MHz ----
CLK : in std_logic; -- MAIN CLOCK
---- VGA SYNC ----
VGA_HSYNC : out std_logic; -- Horiztonal sync
VGA_VSYNC : out std_logic; -- Vertical sync
VGA_R : out std_logic; -- RED
VGA_G : out std_logic; -- GREEN
VGA_B : out std_logic; -- BLUE
---- LED Display ----
LEDX : out std_logic_vector(7 downto 0); -- LEDs
LEDY : out std_logic_vector(7 downto 0); -- LEDs
---- SWITCHES ----
-- SW : in std_logic_vector(7 downto 2); -- SWITCHES
RESET : in std_logic; -- Asycnchronous reset: SW(0)
-- ENABLE : in std_logic; -- Enable logic: SW(1)
---- BUTTONS ----
-- KB : in std_logic_vector(5 downto 1); -- BUTTONS
---- DOORBELL ----
BELL : out std_logic-- BELL
);
end top_minesweeper;
architecture top_minesweeper of top_minesweeper is
------------- COMPONENT Declaration ------
signal ps2_clock : std_logic;
signal ps2_din : std_logic;
signal reset_vga : std_logic;
signal rst : std_logic;
signal RGB : std_logic_vector(2 downto 0);
signal clk_fb : std_logic;
signal clk0 : std_logic;
signal clk_in : std_logic;
signal locked : std_logic;
signal clk_dv : std_logic;
signal rst_dcm : std_logic;
signal v, h : std_logic;
signal leds : std_logic_vector(8 downto 1);
component ctrl_main_block is
port(
-- system signals
reset : in std_logic; -- SW(0)
clk : in std_logic; -- Pixel clk - DCM should generate 25 MHz freq;
-- ps/2 signals
ps2_clk : in std_logic; -- PS/2 CLOCK
ps2_data : in std_logic; -- PS/2 SERIAL DATA
-- vga output signals
h_vga : out std_logic; -- horizontal
v_vga : out std_logic; -- vertical
rgb : out std_logic_vector(2 downto 0); -- (R-G-B)
-- test leds signals
leds : out std_logic_vector(8 downto 1)
);
end component;
begin
x_MAIN_BLOCK : ctrl_main_block
port map(
clk => clk_dv, -- 25 MHz freq;
reset => reset_vga,
ps2_clk => ps2_clock,
ps2_data => ps2_din,
h_vga => H,
v_vga => V,
rgb => RGB,
leds => LEDS
);
---------------- I/O BUFFERS ----------------
ps2c: ibuf port map(i => ps2_clk, o => ps2_clock);
ps2d: ibuf port map(i => ps2_data, o => ps2_din);
xreset: ibuf port map(i => reset, o => rst);
--
xBELL: obuf port map(i => '1', o => BELL);
xVGA_v: obuf port map(i => v, o => VGA_VSYNC);
xVGA_h: obuf port map(i => h, o => VGA_HSYNC);
xVGA_R: obuf port map(i => RGB(2), o => VGA_R);
xVGA_G: obuf port map(i => RGB(1), o => VGA_G);
xVGA_B: obuf port map(i => RGB(0), o => VGA_B);
LEDX <= leds;
LEDY <= leds;
-- DCM CLK :
xclkfb: bufg port map(i => clk0, o => clk_fb);
xclkin: ibufg port map(i => clk,o => clk_in);
xsrl_reset: SRLC16
generic map (
init => x"0000"
)
port map(
Q15 => reset_vga,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CLK => clk_in,
D => rst -- '1',
);
rst_dcm <= not rst;
xDCM_CLK_VGA : dcm
generic map(
--DCM_AUTOCALIBRATION => FALSE, -- DCM ADV
CLKDV_DIVIDE => 2.0, -- clk divide for CLKIN: Fdv = Fclkin / CLK_DIV
CLKFX_DIVIDE => 2, -- clk divide for CLKFX and CLKFX180 : Ffx = (Fclkin * MULTIPLY) / CLKFX_DIV
CLKFX_MULTIPLY => 2, -- clk multiply for CLKFX and CLKFX180 : Ffx = (Fclkin * MULTIPLY) / CLKFX_DIV
CLKIN_DIVIDE_BY_2 => FALSE, -- divide clk / 2 before DCM block
CLKIN_PERIOD => 20.0, -- clk period in ns (for DRC)
CLKOUT_PHASE_SHIFT => "NONE", -- phase shift mode: NONE, FIXED, VARIABLE
CLK_FEEDBACK => "1X", -- freq on the feedback clock: 1x, 2x, None
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- clk delay alignment
DFS_FREQUENCY_MODE => "LOW", -- freq mode CLKFX and CLKFX180: LOW, HIGH
DLL_FREQUENCY_MODE => "LOW", -- freq mode CLKIN: LOW, HIGH
DUTY_CYCLE_CORRECTION => TRUE, -- 50% duty-cycle correction for the CLK0, CLK90, CLK180 and CLK270: TRUE, FALSE
PHASE_SHIFT => 0 -- phase shift (with CLKOUT_PHASE_SHIFT): -255 to 255
)
port map(
clk0 => clk0,
-- clk180 => clk180,
-- clk270 => clk270,
-- clk2x => clk2x,
-- clk2x180 => clk2x180,
-- clk90 => clk90,
clkdv => clk_dv,
-- clkfx => clkfx,
-- clkfx180 => clkfx180,
locked => locked,
-- status => status,
-- psdone => psdone,
clkfb => clk_fb,
clkin => clk_in,
-- dssen => dssen,
-- psclk => psclk,
psen => '0',
psincdec => '0',
rst => rst_dcm
);
end top_minesweeper; | mit | 8370b99f2bc5f8afc0b81d98dd4f00d4 | 0.559046 | 2.613254 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_37x512/simulation/fg_tb_pkg.vhd | 1 | 11,247 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_37x512_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(37-1 DOWNTO 0);
DOUT : OUT std_logic_vector(37-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit | 9c9772f8557b3f8835768d3018a31406 | 0.50449 | 3.929769 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_96x512/simulation/fg_tb_top.vhd | 1 | 5,680 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 101
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| mit | 751a00ea9c895985ec892981b54ba8d9 | 0.616373 | 4.176471 | false | false | false | false |
dugagjinll/MIPS | MIPS/ALU.vhd | 1 | 1,232 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ALU IS
PORT (
a1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
a2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
alu_control : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
alu_result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
zero : OUT STD_LOGIC
);
END ALU;
ARCHITECTURE Behavioral OF ALU IS
SIGNAL resultX : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
PROCESS (a1, a2, alu_control)
BEGIN
CASE alu_control IS
-- Bitwise and
WHEN "0000" =>
resultX <= a1 AND a2;
-- Bitwise or
WHEN "0001" =>
resultX <= a1 OR a2;
-- addition
WHEN "0010" =>
resultX <= std_logic_vector(unsigned(a1) + unsigned(a2));
-- subtract
WHEN "0110" =>
resultX <= std_logic_vector(unsigned(a1) - unsigned(a2));
-- set les than
WHEN "0111" =>
IF (signed(a1) < signed(a2)) THEN
resultX <= x"00000001";
ELSE
resultX <= x"00000000";
END IF;
-- Bitwise nor
WHEN "1100" =>
resultX <= a1 NOR a2;
-- Nop
WHEN others => NULL;
resultX <= x"00000000";
END CASE;
END PROCESS;
-- concurent code
alu_result <= resultX;
zero <= '1' WHEN resultX = x"00000000" ELSE
'0';
END Behavioral; | mit | 8c1be251a7807ad2aa698fbd73be5c8d | 0.596591 | 2.933333 | false | false | false | false |
RowdyRajan/GestureControlInterfaceCapstone | USBProject/DE2Component.vhd | 1 | 8,043 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.VITAL_Primitives.all;
use work.DE2_CONSTANTS.all;
entity DE2Component is
port (
KEY : in std_logic_vector (3 downto 0); --Buttons
SW : in std_logic_vector (7 downto 0); -- Switches
CLOCK_50 : in std_logic; -- 50 MHz Clock
LEDG : out DE2_LED_GREEN; -- Green LEDs
--DRAM_ADDR : out std_logic_vector (11 downto 0);
DRAM_ADDR : out DE2_SDRAM_ADDR_BUS;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
--DRAM_DQ : inout std_logic_vector (15 downto 0);
DRAM_DQ : inout DE2_SDRAM_DATA_BUS;
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- SRAM on board
SRAM_ADDR : out DE2_SRAM_ADDR_BUS;
SRAM_DQ : inout DE2_SRAM_DATA_BUS;
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic;
--UART Connection
UART_TXD : out std_logic; --Transmitter
UART_RXD : in std_logic; --Receiver
-- USB controller
OTG_INT0 : in std_logic;
OTG_INT1 : in std_logic;
OTG_DREQ0 : in std_logic;
OTG_DREQ1 : in std_logic;
OTG_DACK0_N : out std_logic;
OTG_DACK1_N : out std_logic;
OTG_FSPEED : out std_logic;
OTG_LSPEED : out std_logic;
OTG_ADDR : out std_logic_vector(1 downto 0);
OTG_DATA : inout std_logic_vector(15 downto 0);
OTG_CS_N : out std_logic;
OTG_RD_N : out std_logic;
OTG_WR_N : out std_logic;
OTG_RST_N : out std_logic
);
end DE2Component;
architecture structure of DE2Component is
component niosII_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
green_leds_external_connection_export : out DE2_LED_GREEN; -- export
switches_external_connection_export : in std_logic := 'X'; -- export
sdram_0_wire_addr : out DE2_SDRAM_ADDR_BUS; -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout DE2_SDRAM_DATA_BUS := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
sram_0_external_interface_DQ : inout DE2_SRAM_DATA_BUS := (others => 'X'); -- DQ
sram_0_external_interface_ADDR : out DE2_SRAM_ADDR_BUS; -- ADDR
sram_0_external_interface_LB_N : out std_logic; -- LB_N
sram_0_external_interface_UB_N : out std_logic; -- UB_N
sram_0_external_interface_CE_N : out std_logic; -- CE_N
sram_0_external_interface_OE_N : out std_logic; -- OE_N
sram_0_external_interface_WE_N : out std_logic; -- WE_N
altpll_0_c0_clk : out std_logic; -- clk
usb_0_external_interface_INT1 : in std_logic := 'X'; -- Interrupt1
usb_0_external_interface_INT0 : in std_logic := 'X'; -- Interrupt2
usb_0_external_interface_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- DATA
usb_0_external_interface_RST_N : out std_logic; -- reset_n
usb_0_external_interface_ADDR : out std_logic_vector(1 downto 0); -- ADDR
usb_0_external_interface_CS_N : out std_logic; -- CS_N
usb_0_external_interface_RD_N : out std_logic; -- RD_N
usb_0_external_interface_WR_N : out std_logic; -- WR_N
rs232_0_external_interface_RXD : in std_logic; --:= 'X'; -- RXD
rs232_0_external_interface_TXD : out std_logic -- TXD
);
end component niosII_system;
-- These signals are for matching the provided IP core to
-- The specific SDRAM chip in our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
-- DACK not used
OTG_DACK0_N <= 'Z';
OTG_DACK1_N <= 'Z';
-- Speed set to Full-speed
OTG_FSPEED <= 'Z';
OTG_LSPEED <= '0';
--Memory related signal settings. Appears to be used for combining two signals into a singal interface.
DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
-- Component Instantiation Statement (optional)
u0 : component niosII_system
port map (
clk_clk => CLOCK_50,
reset_reset_n => KEY(0),
sdram_0_wire_addr => DRAM_ADDR,
sdram_0_wire_ba => BA,
sdram_0_wire_cas_n => DRAM_CAS_N,
sdram_0_wire_cke => DRAM_CKE,
sdram_0_wire_cs_n => DRAM_CS_N,
sdram_0_wire_dq => DRAM_DQ,
sdram_0_wire_dqm => DQM,
sdram_0_wire_ras_n => DRAM_RAS_N,
sdram_0_wire_we_n => DRAM_WE_N,
altpll_0_c0_clk => DRAM_CLK,
green_leds_external_connection_export => LEDG,
switches_external_connection_export => SW(0),
sram_0_external_interface_DQ => SRAM_DQ,
sram_0_external_interface_ADDR => SRAM_ADDR,
sram_0_external_interface_LB_N => SRAM_LB_N,
sram_0_external_interface_UB_N => SRAM_UB_N,
sram_0_external_interface_CE_N => SRAM_CE_N,
sram_0_external_interface_OE_N => SRAM_OE_N,
sram_0_external_interface_WE_N => SRAM_WE_N,
usb_0_external_interface_INT1 => OTG_INT1,
usb_0_external_interface_INT0 => OTG_INT0,
usb_0_external_interface_DATA => OTG_DATA,
usb_0_external_interface_RST_N => OTG_RST_N,
usb_0_external_interface_ADDR => OTG_ADDR,
usb_0_external_interface_CS_N => OTG_CS_N,
usb_0_external_interface_RD_N => OTG_RD_N,
usb_0_external_interface_WR_N => OTG_WR_N,
rs232_0_external_interface_RXD => UART_RXD,
rs232_0_external_interface_TXD => UART_TXD
);
end structure;
library ieee;
use ieee.std_logic_1164.all;
package DE2_CONSTANTS is
type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic;
type DE2_LED_GREEN is array(7 downto 0) of std_logic;
type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic;
type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic;
end DE2_CONSTANTS;
| gpl-3.0 | 3351aac46727c7ef4f8c09c54218f391 | 0.4931 | 3.124709 | false | false | false | false |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/HPS/HPS_inst.vhd | 1 | 8,140 | component HPS is
port (
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
hps_io_hps_io_gpio_inst_LOANIO01 : inout std_logic := 'X'; -- hps_io_gpio_inst_LOANIO01
hps_io_hps_io_gpio_inst_LOANIO02 : inout std_logic := 'X'; -- hps_io_gpio_inst_LOANIO02
hps_io_hps_io_gpio_inst_LOANIO03 : inout std_logic := 'X'; -- hps_io_gpio_inst_LOANIO03
hps_io_hps_io_gpio_inst_LOANIO04 : inout std_logic := 'X'; -- hps_io_gpio_inst_LOANIO04
hps_io_hps_io_gpio_inst_LOANIO05 : inout std_logic := 'X'; -- hps_io_gpio_inst_LOANIO05
hps_io_hps_io_gpio_inst_LOANIO06 : inout std_logic := 'X'; -- hps_io_gpio_inst_LOANIO06
hps_io_hps_io_gpio_inst_LOANIO07 : inout std_logic := 'X'; -- hps_io_gpio_inst_LOANIO07
hps_io_hps_io_gpio_inst_LOANIO08 : inout std_logic := 'X'; -- hps_io_gpio_inst_LOANIO08
hps_io_hps_io_gpio_inst_LOANIO10 : inout std_logic := 'X'; -- hps_io_gpio_inst_LOANIO10
hps_io_hps_io_gpio_inst_LOANIO11 : inout std_logic := 'X'; -- hps_io_gpio_inst_LOANIO11
hps_io_hps_io_gpio_inst_LOANIO12 : inout std_logic := 'X'; -- hps_io_gpio_inst_LOANIO12
hps_io_hps_io_gpio_inst_LOANIO13 : inout std_logic := 'X'; -- hps_io_gpio_inst_LOANIO13
hps_io_hps_io_gpio_inst_LOANIO42 : inout std_logic := 'X'; -- hps_io_gpio_inst_LOANIO42
hps_io_hps_io_gpio_inst_LOANIO49 : inout std_logic := 'X'; -- hps_io_gpio_inst_LOANIO49
hps_io_hps_io_gpio_inst_LOANIO50 : inout std_logic := 'X'; -- hps_io_gpio_inst_LOANIO50
loanio_in : out std_logic_vector(66 downto 0); -- in
loanio_out : in std_logic_vector(66 downto 0) := (others => 'X'); -- out
loanio_oe : in std_logic_vector(66 downto 0) := (others => 'X'); -- oe
hps_gp_gp_in : in std_logic_vector(31 downto 0) := (others => 'X'); -- gp_in
hps_gp_gp_out : out std_logic_vector(31 downto 0) -- gp_out
);
end component HPS;
u0 : component HPS
port map (
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
hps_io_hps_io_gpio_inst_LOANIO01 => CONNECTED_TO_hps_io_hps_io_gpio_inst_LOANIO01, -- hps_io.hps_io_gpio_inst_LOANIO01
hps_io_hps_io_gpio_inst_LOANIO02 => CONNECTED_TO_hps_io_hps_io_gpio_inst_LOANIO02, -- .hps_io_gpio_inst_LOANIO02
hps_io_hps_io_gpio_inst_LOANIO03 => CONNECTED_TO_hps_io_hps_io_gpio_inst_LOANIO03, -- .hps_io_gpio_inst_LOANIO03
hps_io_hps_io_gpio_inst_LOANIO04 => CONNECTED_TO_hps_io_hps_io_gpio_inst_LOANIO04, -- .hps_io_gpio_inst_LOANIO04
hps_io_hps_io_gpio_inst_LOANIO05 => CONNECTED_TO_hps_io_hps_io_gpio_inst_LOANIO05, -- .hps_io_gpio_inst_LOANIO05
hps_io_hps_io_gpio_inst_LOANIO06 => CONNECTED_TO_hps_io_hps_io_gpio_inst_LOANIO06, -- .hps_io_gpio_inst_LOANIO06
hps_io_hps_io_gpio_inst_LOANIO07 => CONNECTED_TO_hps_io_hps_io_gpio_inst_LOANIO07, -- .hps_io_gpio_inst_LOANIO07
hps_io_hps_io_gpio_inst_LOANIO08 => CONNECTED_TO_hps_io_hps_io_gpio_inst_LOANIO08, -- .hps_io_gpio_inst_LOANIO08
hps_io_hps_io_gpio_inst_LOANIO10 => CONNECTED_TO_hps_io_hps_io_gpio_inst_LOANIO10, -- .hps_io_gpio_inst_LOANIO10
hps_io_hps_io_gpio_inst_LOANIO11 => CONNECTED_TO_hps_io_hps_io_gpio_inst_LOANIO11, -- .hps_io_gpio_inst_LOANIO11
hps_io_hps_io_gpio_inst_LOANIO12 => CONNECTED_TO_hps_io_hps_io_gpio_inst_LOANIO12, -- .hps_io_gpio_inst_LOANIO12
hps_io_hps_io_gpio_inst_LOANIO13 => CONNECTED_TO_hps_io_hps_io_gpio_inst_LOANIO13, -- .hps_io_gpio_inst_LOANIO13
hps_io_hps_io_gpio_inst_LOANIO42 => CONNECTED_TO_hps_io_hps_io_gpio_inst_LOANIO42, -- .hps_io_gpio_inst_LOANIO42
hps_io_hps_io_gpio_inst_LOANIO49 => CONNECTED_TO_hps_io_hps_io_gpio_inst_LOANIO49, -- .hps_io_gpio_inst_LOANIO49
hps_io_hps_io_gpio_inst_LOANIO50 => CONNECTED_TO_hps_io_hps_io_gpio_inst_LOANIO50, -- .hps_io_gpio_inst_LOANIO50
loanio_in => CONNECTED_TO_loanio_in, -- loanio.in
loanio_out => CONNECTED_TO_loanio_out, -- .out
loanio_oe => CONNECTED_TO_loanio_oe, -- .oe
hps_gp_gp_in => CONNECTED_TO_hps_gp_gp_in, -- hps_gp.gp_in
hps_gp_gp_out => CONNECTED_TO_hps_gp_gp_out -- .gp_out
);
| gpl-3.0 | d11aed78e766272ab9c5212b49b68aab | 0.474324 | 3.300892 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/tb_mem.vhd | 1 | 2,607 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity tb is
end tb;
architecture BEHAVIOR of tb is
-- Definitions --
constant STEP : time := 10 ns; -- A clock cycle is set to be 10ns --
signal clk, read, write, S_MEMlat : std_logic;
signal S_MAR_F : std_logic_vector(7 downto 0);
signal S_MDR_F : std_logic_vector(15 downto 0);
signal data : std_logic_vector(15 downto 0);
component mem is
port(clk, read, write, S_MEMlat : in std_logic;
S_MAR_F : in std_logic_vector(7 downto 0);
S_MDR_F : in std_logic_vector(15 downto 0);
data : out std_logic_vector(15 downto 0));
end component;
-- Main --
begin
uut : mem port map(clk, read, write, S_MEMlat, S_MAR_F, S_MDR_F, data);
clk_process:
process begin
clk <= '0';
wait for STEP/2; --for 5 ns signal is '0'.
clk <= '1';
wait for STEP/2; --for next 5 ns signal is '1'.
end process;
tb:
process begin
read <= '0';
write <= '0';
S_MEMlat <= '0';
-- No action --
wait for 10ns;
write <= '1';
wait for 10ns;
write <= '0';
wait for 10ns;
S_MEMlat <= '1';
wait for 10ns;
S_MEMlat <= '0';
wait for 10ns;
read <= '1';
wait for 10ns;
read <= '0';
-- RAM_DATA(1) <= 7777 --
wait for 10ns;
S_MAR_F <= "00000001";
S_MDR_F <= "0111011101110111";
wait for 10ns;
S_MEMlat <= '1';
wait for 10ns;
S_MEMlat <= '0';
wait for 10ns;
write <= '1';
wait for 10ns;
write <= '0';
-- RAM_DATA(2) <= 5555 (concurrent) --
wait for 10ns;
S_MAR_F <= "00000010";
S_MDR_F <= "0101010101010101";
wait for 10ns;
S_MEMlat <= '1';
write <= '1';
wait for 10ns;
S_MEMlat <= '0';
write <= '0';
-- data <= RAM_DATA(1) --
wait for 10ns;
S_MAR_F <= "00000001";
wait for 10ns;
S_MEMlat <= '1';
wait for 10ns;
S_MEMlat <= '0';
wait for 10ns;
read <= '1';
wait for 10ns;
read <= '0';
-- data <= RAM_DATA(2) --
wait for 10ns;
S_MAR_F <= "00000010";
wait for 10ns;
S_MEMlat <= '1';
wait for 10ns;
S_MEMlat <= '0';
wait for 10ns;
read <= '1';
wait for 10ns;
read <= '0';
-- data <= RAM_DATA(1) (concurrent) --
wait for 10ns;
S_MAR_F <= "00000001";
wait for 10ns;
S_MEMlat <= '1';
read <= '1';
wait for 10ns;
S_MEMlat <= '0';
read <= '0';
wait;
end process;
end BEHAVIOR;
| mit | 13c6666f6e7bd932e80834ef812a5aaa | 0.502877 | 3.103571 | false | false | false | false |
znuh/open-nexys | bscan_la/clockman.vhd | 1 | 2,891 | ----------------------------------------------------------------------------------
-- clockman.vhd
--
-- Author: Michael "Mr. Sump" Poppitz
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- This is only a wrapper for Xilinx' DCM component so it doesn't
-- have to go in the main code and can be replaced more easily.
--
-- Creates clk0 with 100MHz.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity clockman is
Port (
clkin : in STD_LOGIC; -- clock input
clk0 : out std_logic -- double clock rate output
);
end clockman;
architecture Behavioral of clockman is
signal clkfb, clkfbbuf, realclk0 : std_logic;
begin
-- DCM: Digital Clock Manager Circuit for Virtex-II/II-Pro and Spartan-3/3E
-- Xilinx HDL Language Template version 8.1i
DCM_baseClock : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 20.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => FALSE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => TRUE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKIN => clkin, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0', -- DCM asynchronous reset input
CLK2X => realclk0,
CLK0 => clkfb,
CLKFB => clkfbbuf
);
-- clkfb is run through a BUFG only to shut up ISE 8.1
BUFG_clkfb : BUFG
port map (
O => clkfbbuf, -- Clock buffer output
I => clkfb -- Clock buffer input
);
clk0 <= realclk0;
end Behavioral;
| gpl-2.0 | e8382273719074604335976d9e82cbfb | 0.57973 | 3.696931 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_96x512_hf/example_design/fifo_fwft_96x512_hf_top.vhd | 1 | 5,146 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_fwft_96x512_hf_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_fwft_96x512_hf_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(96-1 DOWNTO 0);
DOUT : OUT std_logic_vector(96-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_fwft_96x512_hf_top;
architecture xilinx of fifo_fwft_96x512_hf_top is
SIGNAL clk_i : std_logic;
component fifo_fwft_96x512_hf is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(96-1 DOWNTO 0);
DOUT : OUT std_logic_vector(96-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_fwft_96x512_hf PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | bdad28dd5f16932b3453d3237d907d5d | 0.517295 | 4.845574 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_138x16_shift/example_design/fifo_138x16_shift_top.vhd | 1 | 4,820 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_138x16_shift_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_138x16_shift_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(138-1 DOWNTO 0);
DOUT : OUT std_logic_vector(138-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_138x16_shift_top;
architecture xilinx of fifo_138x16_shift_top is
SIGNAL clk_i : std_logic;
component fifo_138x16_shift is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(138-1 DOWNTO 0);
DOUT : OUT std_logic_vector(138-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_138x16_shift PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 86dbd2cc8dac3e4805be5bbbe822ff0f | 0.529461 | 4.888438 | false | false | false | false |
mzakharo/usb-de2-fpga | src/usb.vhd | 1 | 5,477 | -- usb.vhd
-- -----------------------------------------------------------------------
-- Copyright � 2012 Mikhail Zakharov
-- -----------------------------------------------------------------------
--
-- This file is part of "ISP1362 VHDL interface for DE2"
--
-- "ISP1362 VHDL interface for DE2" is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3
--
-- "ISP1362 VHDL interface for DE2" is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with "ISP1362 VHDL interface for DE2". If not, see <http://www.gnu.org/licenses/>.
-- -----------------------------------------------------------------------
-- ISP1362 Inteface for DE2 - VHDL Model
-- -----------------------------------------------------------------------
-- Version : 1.0
-- Date : Sept 2012
-- Author : Mikhail Zakharov
-- Web : http://ca.linkedin.com/in/mzakharo
-- Contact : [email protected]
-- -----------------------------------------------------------------------
-- FUNCTION :
-- A standalone (NIOS II free) interface in VHDL to the ISP1362 USB device
-- for Altera DE2 Development board.
--
-- Typical Area :
-- ~ 352 LEs (Cyclone II)
-- VHDL synthesis tool tested
-- QuartusII 11 & 12
--
-- Design notes :
--
-- 1. 2 Bulk endpoints (IN/OUT)
--
-- 2. Transfer rate: 180 KB/s with 2 Bytes/USB Transaction.
-- ISP1362 supports up to 1MB/s with 64 Bytes/USB Transaction
--
-- 3. Hardware flow control: ISP1362 can detect overflow of internal buffers.
-- Currently overflows must be avoided by the host software application.
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.isp_hal.all;
use work.isp_drv.all;
use work.devreq_inc.all;
entity usb is
port(
--clock
CLOCK_50 : in std_logic;
--DE2 board config
OTG_FSPEED : out std_logic; --USB Full Speed
OTG_LSPEED : out std_logic; --USB Low Speed
--ISP1368
OTG_DATA : inout std_logic_vector(15 downto 0); --ISP1362 Data bus 16 bits
OTG_INT1 : in std_logic; --ISP1362 Interrupt 2 (Peripheral Interrupts)
OTG_RST_N : out std_logic; --ISP1362 Reset pin
OTG_ADDR : out std_logic_vector(1 downto 0); --ISP1362 Address 2 Bits[peripheral,command]
OTG_CS_N : out std_logic; --ISP1362 Chip Select
OTG_RD_N : out std_logic; --ISP1362 Write
OTG_WR_N : out std_logic; --ISP1362 Read
-- not used
OTG_DACK0_N : out std_logic; --ISP1362 DMA Acknowledge 1
OTG_DACK1_N : out std_logic; --ISP1362 DMA Acknowledge 2
--I/O...
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(17 downto 0);
LEDR : out std_logic_vector(17 downto 0);
LEDG : out std_logic_vector(8 downto 0);
HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7 : out std_logic_vector(6 downto 0)
);
end usb;
architecture handler of usb is
--DE2 config signals
signal clk : std_logic;
signal slowclk_en : bit;
signal reset, reset_synch : std_logic;
--USB stuff
signal hal_i : isp_hal_in_t;
signal hal_o : isp_hal_out_t;
signal drv_i : isp_drv_in_t;
signal drv_o : isp_drv_out_t;
begin --architecture
--DE2 USB config
OTG_FSPEED <='0'; -- 0 = Enable, Z = Disable
OTG_LSPEED <='Z'; -- 0 = Enable, Z = Disable
--DE2 clock and reset config
clk <= CLOCK_50;
p_reset: process
begin
wait until rising_edge(clk);
reset_synch <= not(KEY(0));
reset <= reset_synch;
end process;
--produces 25MHz clock enable pulse for HAL
--assumes 50MHz clk, if this assumption changes,
--this code needs to be modified
p_pulse25MHz: process
-- Example 1: design clk is @ 50MHz
-- _ _ _ _ _ _ _ _
--clk @ 50MHz | |_| |_| |_| |_| |_| |_| |_| |_
-- _ _ _ _ _ _ _ _
--pulse @ 25MHz | |_ _| |_ _| |_ _| |_ _
--
-- Example 2: design clk is @ 200MHz
-- _ _ _ _ _ _ _ _
--clk @ 200MHz | |_| |_| |_| |_| |_| |_| |_| |_
-- _ _ _ _
--pulse @ 25MHz | |_ _ _ _ _ _| |_ _ _ _ _ _
begin
wait until rising_edge(clk);
slowclk_en <= not(slowclk_en);
end process;
-- hal port map
hal_i.slowclk_en <= slowclk_en;
OTG_RST_N <= hal_o.rst_n ;
OTG_ADDR <= hal_o.addr;
OTG_CS_N <= hal_o.cs_n;
OTG_RD_N <= hal_o.rd_n;
OTG_WR_N <= hal_o.wr_n;
OTG_DACK0_N <= hal_o.dack0_n;
OTG_DACK1_N <= hal_o.dack1_n;
--hal
hal_i.drv <= drv_o.hal;
h: hal port map (clk, reset, OTG_DATA , hal_i, hal_o);
--driver port map
drv_i.int <= OTG_INT1;
--driver
drv_i.hal <= hal_o.drv;
d: drv port map(clk,reset, drv_i , drv_o);
--device request handler
dvrq: devreq port map(clk, reset, drv_o.devreq, drv_i.devreq);
--loopback (for demo)
drv_i.io <= drv_o.io; --when io.SData is ready, io.RDy will pulse for one clock cycle.
--demo LEDs
LEDR(drv_o.io.Sdata'high downto 0) <= drv_o.io.Sdata;
end handler;
| gpl-3.0 | 8a994bf0bd0a12024da8bf5cef5fe4c4 | 0.540822 | 3.055246 | false | false | false | false |
znuh/open-nexys | fx2_fifo_test/top.vhd | 1 | 5,462 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity top is
Port (
sys_clk : in std_logic;
Led: out std_logic_vector(7 downto 0);
sw: in std_logic_vector(7 downto 0);
fx2_wr_full_i : in std_logic;
fx2_rd_empty_i : in std_logic;
fx2_data_io : inout std_logic_vector(7 downto 0);
fx2_clk_i : in std_logic;
fx2_slcs_o : out std_logic;
fx2_slrd_o : out std_logic;
fx2_sloe_o : out std_logic;
fx2_slwr_o : out std_logic;
fx2_pktend_o : out std_logic;
fx2_fifo_addr_o : out std_logic_vector(1 downto 0);
btn : in std_logic_vector(3 downto 0)
);
end top;
architecture Behavioral of top is
component bscan_sreg is
GENERIC (
SREG_LEN : integer := 24
);
Port (
CAPTURE_i : in std_logic;
DRCK_i : in std_logic;
SEL_i : in std_logic;
SHIFT_i : in std_logic;
UPDATE_i : in std_logic;
TDI_i : in std_logic;
TDO_o: out std_logic;
clk_i : in std_logic;
Data_i : in std_logic_vector((SREG_LEN - 1) downto 0);
Data_o : out std_logic_vector((SREG_LEN - 1) downto 0);
strobe_o : out std_logic
);
end component;
signal CAPTURE : std_logic;
signal DRCK1 : std_logic;
signal SEL1 : std_logic;
signal SHIFT : std_logic;
signal UPDATE : std_logic;
signal TDO1 : std_logic;
signal TDI : std_logic;
signal din : std_logic_vector(23 downto 0);
signal dout : std_logic_vector(23 downto 0);
signal strobe : std_logic;
signal fx2_dout : std_logic_vector(7 downto 0);
signal fx2_wr : std_logic := '0';
signal fx2_wr_cnt : std_logic_vector(15 downto 0);
signal fx2_notfull_cnt : std_logic_vector(15 downto 0);
signal fx2_wasfull : std_logic := '0';
signal fx2_stop_on_full : std_logic := '0';
signal fx2_no_delay : std_logic := '0';
signal run : std_logic := '0';
signal autostop : std_logic := '1';
signal fx2_last_full : std_logic;
signal delay : std_logic_vector(3 downto 0);
signal delay_cnt : std_logic_vector(3 downto 0);
begin
BSCAN_SPARTAN3_inst : BSCAN_SPARTAN3
port map (
CAPTURE => CAPTURE, -- CAPTURE output from TAP controller
DRCK1 => DRCK1, -- Data register output for USER1 functions
DRCK2 => open, -- Data register output for USER2 functions
RESET => open, -- Reset output from TAP controller
SEL1 => SEL1, -- USER1 active output
SEL2 => open, -- USER2 active output
SHIFT => SHIFT, -- SHIFT output from TAP controller
TDI => TDI, -- TDI output from TAP controller
UPDATE => UPDATE, -- UPDATE output from TAP controller
TDO1 => TDO1, -- Data input for USER1 function
TDO2 => open -- Data input for USER2 function
);
bscan_sreg_inst : bscan_sreg
Port map (
CAPTURE_i => CAPTURE,
DRCK_i => DRCK1,
SEL_i => SEL1,
SHIFT_i => SHIFT,
UPDATE_i => UPDATE,
TDI_i => TDI,
TDO_o => TDO1,
clk_i => fx2_clk_i, --sys_clk,
Data_i => din,
Data_o => dout,
strobe_o => strobe
);
fx2_fifo_addr_o <= "10";
fx2_slcs_o <= '0';
fx2_slrd_o <= '1';
fx2_sloe_o <= '1';
fx2_slwr_o <= fx2_wr;
Led <= fx2_wr & (not fx2_wr_full_i) & fx2_wasfull & fx2_stop_on_full & fx2_no_delay & "000";
process(fx2_clk_i)
begin
if rising_edge(fx2_clk_i) then
-- FX2 default signals
fx2_data_io <= (others => 'Z');
fx2_pktend_o <= '1';
fx2_wr <= '1';
if fx2_wr_full_i = '0' then
fx2_wasfull <= '1';
end if;
-- did a write cycle
if fx2_wr = '0' then
if fx2_wr_full_i = '1' and fx2_wasfull = '0' then
fx2_notfull_cnt <= fx2_notfull_cnt + 1;
end if;
end if;
-- start button
if btn(0) = '1' then
run <= '1';
end if;
fx2_last_full <= fx2_wr_full_i;
-- insert delay after frame
if fx2_last_full = '1' and fx2_wr_full_i = '0' then
delay_cnt <= delay;
end if;
-- write?
if delay_cnt /= "000" then
delay_cnt <= delay_cnt - 1;
elsif fx2_wr_cnt /= x"0000" or autostop = '0' then
if (run = '1') and (fx2_wr = '1' or fx2_no_delay = '1') then
if (fx2_wr_full_i = '1' or fx2_last_full = '1' or fx2_stop_on_full = '0') then
fx2_data_io <= fx2_dout;
fx2_dout <= fx2_dout + 1;
fx2_wr <= '0';
fx2_wr_cnt <= fx2_wr_cnt - 1;
end if;
end if;
else
run <= '0';
end if;
-- JTAG strobe
if strobe = '1' then
din <= dout;
-- reg. addr
case dout(23 downto 16) is
-- FX2 ctl
when x"80" => fx2_stop_on_full <= dout(0);
fx2_no_delay <= dout(1);
-- some kind of raw mode...
fx2_wr <= not dout(2);
fx2_pktend_o <= not dout(4);
autostop <= not dout(5);
delay <= dout(11 downto 8);
-- FX2 status
when x"00" => din(7 downto 0) <= "000000" & fx2_wr_full_i & fx2_rd_empty_i;
-- FX2 write count
when x"81" => fx2_wr_cnt <= dout(15 downto 0);
fx2_notfull_cnt <= x"0000";
fx2_wasfull <= '0';
-- FX2 written count
when x"01" => din(15 downto 0) <= fx2_notfull_cnt;
-- FX2 data out
when x"82" => fx2_dout <= dout(7 downto 0);
-- FX2 data out
when x"02" => din(7 downto 0) <= fx2_dout;
when others => null;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 9da31de76742b56fab9487a4fe491f13 | 0.578909 | 2.731 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_96x512/simulation/fg_tb_dverif.vhd | 11 | 5,803 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| mit | 548131d227537f675557f6b40a7952b6 | 0.566259 | 3.999311 | false | false | false | false |
Wynjones1/VHDL-Tests | src/top.vhd | 1 | 2,596 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library IEEE;
use std.textio.all;
entity top is
port( clk : in std_logic;
vs : out std_logic;
hs : out std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(1 downto 0));
end entity;
architecture rtl of top is
component vga is
port( clk : in std_logic;
hs : out std_logic;
vs : out std_logic;
pix_x : out integer range 0 to 799;
pix_y : out integer range 0 to 520;
en : out std_logic);
end component;
constant CLK_SPEED : integer := 50000000;
constant XMAX : integer := 5;
constant YMAX : integer := 5;
constant XRES : integer := 160;
constant YRES : integer := 144;
signal s_half_clk : std_logic;
signal s_display_en : std_logic;
signal pix_x : integer;
signal pix_y : integer;
type framebuffer_t is array(0 to YRES - 1) of std_logic_vector(XRES - 1 downto 0);
impure function init_fb(filename : in string) return framebuffer_t is
file romfile : text is in filename;
variable file_line : line;
variable fb : framebuffer_t;
variable temp : bit_vector(XRES - 1 downto 0);
begin
for i in framebuffer_t'range loop
readline (romfile, file_line);
read (file_line, temp);
fb(i) := to_stdlogicvector(temp);
end loop;
return fb;
end function;
function inrange(
min : in integer;
val : in integer;
max : in integer)
return boolean is
begin
return (min <= val) and (val < (min + max));
end function;
signal fb : framebuffer_t := init_fb("fb.rom");
begin
gen_pixel_clk:
process(clk)
begin
if rising_edge(clk) then
if s_half_clk = '1' then
s_half_clk <= '0';
else
s_half_clk <= '1';
end if;
end if;
end process;
vga0: vga
port map ( s_half_clk, hs, vs, pix_x, pix_y, s_display_en);
colour_process:
process(s_half_clk, s_display_en, pix_x, pix_y, fb)
variable x : std_logic_vector(2 downto 0);
variable y : std_logic_vector(2 downto 0);
constant start : integer := 4;
constant cross : integer := 7;
variable p : std_logic;
begin
if rising_edge(s_half_clk) then
if s_display_en = '1'and inrange(240, pix_x, XRES) and inrange(168, pix_y, YRES) then
p := fb(pix_y - 168)(pix_x - 240);
red <= (others => p);
green <= (others => p);
blue <= (others => p);
else
red <= "000";
green <= "000";
blue <= "00";
end if;
end if;
end process;
end architecture;
| mit | 0e5b828b7ca47c7e1b43824f906f9cd3 | 0.604391 | 2.884444 | false | false | false | false |
znuh/open-nexys | fx2async/fx2async.vhd | 1 | 3,425 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fx2async is
port (
fx2_wr_full_i : in STD_LOGIC;
fx2_rd_empty_i : in STD_LOGIC;
fx2_data_io : inout STD_LOGIC_VECTOR (7 downto 0);
fx2_fifo_addr_o : out STD_LOGIC_VECTOR (1 downto 0);
fx2_slwr_o : out STD_LOGIC;
fx2_slrd_o : out std_logic;
fx2_sloe_o : out std_logic;
fx2_slcs_o : out std_logic;
fx2_pktend_o : out STD_LOGIC;
usb_data_i : in std_logic_vector(7 downto 0);
usb_data_o : out std_logic_vector(7 downto 0);
usb_wr_en_i : in std_logic;
usb_rd_en_i : in std_logic;
usb_wr_strobe_o : out std_logic;
usb_rd_strobe_o : out std_logic;
usb_pktend_i : in std_logic;
usb_pktstart_o : out std_logic;
clk_i : in std_logic;
rst_i : in std_logic
);
end fx2async;
architecture Behavioral of fx2async is
type mode is (USB_RD1, USB_RD2, USB_WR1, USB_WR2);
signal state: mode;
signal wr, rd: std_logic;
signal rd_empty, wr_full: std_logic;
signal delay: std_logic_vector(3 downto 0);
signal data_i, data_i_r1, data_i_r2 : std_logic_vector(7 downto 0);
signal rd_empty_r1, rd_empty_r2 : std_logic;
signal wr_full_r1, wr_full_r2 : std_logic;
signal pktend_pending : std_logic;
signal usb_rd_strobe, usb_wr_strobe : std_logic;
begin
fx2_slcs_o <= '0';
fx2_slrd_o <= not rd;
fx2_sloe_o <= not rd;
fx2_slwr_o <= not wr;
usb_wr_strobe_o <= usb_wr_strobe;
usb_rd_strobe_o <= usb_rd_strobe;
process
begin
wait until rising_edge(clk_i);
-- flags und daten eintakten
rd_empty_r1 <= fx2_rd_empty_i;
rd_empty_r2 <= rd_empty_r1;
rd_empty <= rd_empty_r2;
wr_full_r1 <= fx2_wr_full_i;
wr_full_r2 <= wr_full_r1;
wr_full <= wr_full_r2;
data_i_r1 <= fx2_data_io;
data_i_r2 <= data_i_r1;
data_i <= data_i_r2;
usb_wr_strobe <= '0';
usb_rd_strobe <= '0';
if usb_rd_strobe = '1' and rd_empty = '1' then
usb_pktstart_o <= '0';
end if;
if rd_empty = '0' then
usb_pktstart_o <= '1';
end if;
if rst_i = '1' then
wr <= '0';
rd <= '0';
fx2_data_io <= (others => 'Z');
fx2_pktend_o <= '1';
state <= USB_RD1;
fx2_fifo_addr_o <= "00"; -- read - write: 10
pktend_pending <= '0';
else
if usb_pktend_i = '1' then
pktend_pending <= '1';
end if;
delay <= delay + 1;
if delay = "0000" then
wr <= '0';
rd <= '0';
fx2_data_io <= (others => 'Z');
fx2_pktend_o <= '1';
if pktend_pending = '1' then
fx2_pktend_o <= '0';
pktend_pending <= '0';
end if;
case state is
when USB_RD1 =>
if usb_rd_en_i = '1' and rd_empty = '1' then
rd <= '1';
state <= USB_RD2;
elsif usb_wr_en_i = '1' and wr_full = '1' then
state <= USB_WR1;
fx2_fifo_addr_o <= "10";
end if;
when USB_RD2 =>
usb_data_o <= data_i;
usb_rd_strobe <= '1';
state <= USB_RD1;
when USB_WR1 =>
if usb_wr_en_i = '1' and wr_full = '1' then
fx2_data_io <= usb_data_i;
usb_wr_strobe <= '1';
wr <= '1';
state <= USB_WR2;
elsif usb_rd_en_i = '1' and rd_empty = '1' then
state <= USB_RD1;
fx2_fifo_addr_o <= "00";
end if;
when USB_WR2 =>
state <= USB_WR1;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 35e1b4c713c21390e405e9947c628a04 | 0.550073 | 2.456958 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_37x512_hf/example_design/fifo_37x512_hf_top_wrapper.vhd | 1 | 19,135 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_37x512_hf_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_37x512_hf_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(37-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(1-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(37-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_37x512_hf_top_wrapper;
architecture xilinx of fifo_37x512_hf_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_37x512_hf_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(1-1 DOWNTO 0);
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(37-1 DOWNTO 0);
DOUT : OUT std_logic_vector(37-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_37x512_hf_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 55d205e8df300f55604e8c05599401ad | 0.486073 | 3.960058 | false | false | false | false |
Mafus1/bluetooth-receiver | source/rxreg.vhd | 1 | 3,607 | -- Library & Use Statements
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- Entity Declaration
ENTITY rxreg IS
PORT(
clk : IN std_logic;
reset_n : IN std_logic;
valid_data : IN std_logic;
par_data_in : IN std_logic_vector(7 downto 0);
reg_0_l : OUT std_logic_vector(3 downto 0); -- to sevseg1 / only 4bit, split reg 0 least
reg_0_m : OUT std_logic_vector(3 downto 0); -- to sevseg2 / only 4bit, split reg 0 most
reg_1_l : OUT std_logic_vector(3 downto 0); -- to sevseg3 / only 4bit, split reg 1 least
reg_1_m : OUT std_logic_vector(3 downto 0); -- to sevseg4 / only 4bit, split reg 1 most
reg_2_l : OUT std_logic_vector(3 downto 0); -- to sevseg5 / only 4bit, split reg 2 least
reg_2_m : OUT std_logic_vector(3 downto 0); -- to sevseg6 / only 4bit, split reg 2 most
reg_3_l : OUT std_logic_vector(3 downto 0); -- to sevseg7 / only 4bit, split reg 3 least
reg_3_m : OUT std_logic_vector(3 downto 0) -- to sevseg8 / only 4bit, split reg 3 most
);
END rxreg;
-- Architecture Declaration
ARCHITECTURE rtl OF rxreg IS
-- Signals & Constants Declaration
CONSTANT default_data : std_logic_vector(7 downto 0):= "00000000";
CONSTANT default_reg : unsigned(1 downto 0):= to_unsigned(0, 2);
CONSTANT reg_0_state : unsigned(1 downto 0):= to_unsigned(0, 2);
CONSTANT reg_1_state : unsigned(1 downto 0):= to_unsigned(1, 2);
CONSTANT reg_2_state : unsigned(1 downto 0):= to_unsigned(2, 2);
CONSTANT reg_3_state : unsigned(1 downto 0):= to_unsigned(3, 2);
SIGNAL current_reg, next_reg : unsigned(1 downto 0):= default_reg;
SIGNAL reg_0, reg_1, reg_2, reg_3 : std_logic_vector(7 downto 0):= default_data;
SIGNAL next_reg_0, next_reg_1, next_reg_2, next_reg_3 : std_logic_vector(7 downto 0):= default_data;
-- Begin Architecture
BEGIN
input_logic: PROCESS (ALL)
BEGIN
IF current_reg < 3 AND valid_data = '1' THEN
next_reg <= current_reg + 1;
ELSIF current_reg = 3 AND valid_data = '1' THEN
next_reg <= default_reg;
ELSE
next_reg <= current_reg;
END IF;
END PROCESS input_logic;
register_logic: PROCESS (ALL)
BEGIN
IF valid_data = '1' AND current_reg = reg_0_state THEN
next_reg_0 <= par_data_in;
ELSE
next_reg_0 <= reg_0;
END IF;
IF valid_data = '1' AND current_reg = reg_1_state THEN
next_reg_1 <= par_data_in;
ELSE
next_reg_1 <= reg_1;
END IF;
IF valid_data = '1' AND current_reg = reg_2_state THEN
next_reg_2 <= par_data_in;
ELSE
next_reg_2 <= reg_2;
END IF;
IF valid_data = '1' AND current_reg = reg_3_state THEN
next_reg_3 <= par_data_in;
ELSE
next_reg_3 <= reg_3;
END IF;
END PROCESS register_logic;
flip_flops : PROCESS(reset_n, clk)
BEGIN
IF reset_n = '0' THEN
current_reg <= default_reg;
ELSIF rising_edge(clk) THEN
current_reg <= next_reg;
END IF;
END PROCESS flip_flops;
register_flip_flops: PROCESS(reset_n, clk)
BEGIN
IF reset_n = '0' THEN
reg_0 <= default_data;
reg_1 <= default_data;
reg_2 <= default_data;
reg_3 <= default_data;
ELSIF rising_edge(clk) THEN
reg_0 <= next_reg_0;
reg_1 <= next_reg_1;
reg_2 <= next_reg_2;
reg_3 <= next_reg_3;
END IF;
END PROCESS register_flip_flops;
reg_0_l <= reg_0 (3 downto 0);
reg_0_m <= reg_0 (7 downto 4);
reg_1_l <= reg_1 (3 downto 0);
reg_1_m <= reg_1 (7 downto 4);
reg_2_l <= reg_2 (3 downto 0);
reg_2_m <= reg_2 (7 downto 4);
reg_3_l <= reg_3 (3 downto 0);
reg_3_m <= reg_3 (7 downto 4);
END rtl;
| mit | 728db551cdb8c77e231ee67c36e0784c | 0.618863 | 2.589799 | false | false | false | false |
zeruniverse/Single-cycle_CPU | ISE project/ipcore_dir/Data_Mem.vhd | 1 | 5,918 | --------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file Data_Mem.vhd when simulating
-- the core, Data_Mem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY Data_Mem IS
port (
a: in std_logic_vector(5 downto 0);
d: in std_logic_vector(31 downto 0);
clk: in std_logic;
we: in std_logic;
spo: out std_logic_vector(31 downto 0));
END Data_Mem;
ARCHITECTURE Data_Mem_a OF Data_Mem IS
-- synthesis translate_off
component wrapped_Data_Mem
port (
a: in std_logic_vector(5 downto 0);
d: in std_logic_vector(31 downto 0);
clk: in std_logic;
we: in std_logic;
spo: out std_logic_vector(31 downto 0));
end component;
-- Configuration specification
for all : wrapped_Data_Mem use entity XilinxCoreLib.dist_mem_gen_v5_1(behavioral)
generic map(
c_has_clk => 1,
c_has_qdpo_clk => 0,
c_has_qdpo_ce => 0,
c_parser_type => 1,
c_has_d => 1,
c_has_spo => 1,
c_read_mif => 1,
c_has_qspo => 0,
c_width => 32,
c_reg_a_d_inputs => 0,
c_has_we => 1,
c_pipeline_stages => 0,
c_has_qdpo_rst => 0,
c_reg_dpra_input => 0,
c_qualify_we => 0,
c_family => "spartan3",
c_sync_enable => 1,
c_depth => 64,
c_has_qspo_srst => 0,
c_has_qdpo_srst => 0,
c_has_dpra => 0,
c_qce_joined => 0,
c_mem_type => 1,
c_has_i_ce => 0,
c_has_dpo => 0,
c_mem_init_file => "Data_Mem.mif",
c_default_data => "0",
c_has_spra => 0,
c_has_qspo_ce => 0,
c_addr_width => 6,
c_has_qspo_rst => 0,
c_has_qdpo => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_Data_Mem
port map (
a => a,
d => d,
clk => clk,
we => we,
spo => spo);
-- synthesis translate_on
END Data_Mem_a;
| gpl-3.0 | 48cc149abb8e8690b63a98ec92dc5a03 | 0.515377 | 4.29463 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_96x512_hf/simulation/fg_tb_top.vhd | 1 | 5,679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 97
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| mit | fc0b9cde89570a6221164c532cc796fe | 0.616306 | 4.175735 | false | false | false | false |
dugagjinll/MIPS | MIPS/tb_registerFile.vhd | 1 | 1,575 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY tb_registerFile IS
END tb_registerFile;
ARCHITECTURE behavior OF tb_registerFile IS
--Inputs
SIGNAL tb_readRegister1 : std_logic_vector(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_readRegister2 : std_logic_vector(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_writeRegister : std_logic_vector(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_writeData : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_registerWrite : std_logic := '0';
--Outputs
SIGNAL tb_readData1 : std_logic_vector(31 DOWNTO 0);
SIGNAL tb_readData2 : std_logic_vector(31 DOWNTO 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
U1_Reg : ENTITY work.registerFile(Behavioral)
PORT MAP(
readRegister1 => tb_readRegister1,
readRegister2 => tb_readRegister2,
writeRegister => tb_writeRegister,
writeData => tb_writeData,
registerWrite => tb_registerWrite,
readData1 => tb_readData1,
readData2 => tb_readData2
);
-- Stimulus process
stim_proc : PROCESS
BEGIN
-- read all 32 registers
-- FOR I IN 0 TO 30 LOOP
-- tb_readRegister1 <= std_logic_vector(to_unsigned(I, 5));
-- tb_readRegister2 <= std_logic_vector(to_unsigned(I + 1, 5));
-- WAIT FOR 25 ns;
-- END LOOP;
-- Overwriting a register
tb_writeRegister <= "01000"; -- $t0 register
tb_writeData <= x"a5a5a5a5";
WAIT FOR 50 ns;
tb_registerWrite <= '1';
WAIT FOR 5 ns;
tb_registerWrite <= '0';
WAIT FOR 5ns;
-- register $t0 should now be written
ASSERT false
REPORT "END"
SEVERITY failure;
END PROCESS;
END; | mit | 244dafee566924ab355cbb90abf67813 | 0.685079 | 3.076172 | false | false | false | false |
dugagjinll/MIPS | MIPS/dataMemory.vhd | 1 | 1,102 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY dataMemory IS
PORT (
address : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
writeData : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
memRead : IN STD_LOGIC;
memWrite : IN STD_LOGIC;
readData : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END dataMemory;
ARCHITECTURE Behavioral OF dataMemory IS
TYPE RAM_16_x_32 IS ARRAY(0 TO 15) OF std_logic_vector(31 DOWNTO 0);
SIGNAL DM : RAM_16_x_32 := (
x"00000000", -- assume starts at 0x1000100000
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000"
);
BEGIN
PROCESS (memWrite, memRead) -- pulse on write
-- Note: 268500992 = 0x10010000
BEGIN
IF (memWrite = '1') THEN
DM((to_integer(unsigned(address)) - 268500992) / 4) <= writeData;
END IF;
IF (memRead = '1') THEN
readData <= DM((to_integer(unsigned(address)) - 268500992)/4);
END IF;
-- it gives, 0, 1, 2, 3, 4, ...
END PROCESS;
END Behavioral; | mit | d257c22b5242ec7d1d38b231db68606a | 0.656987 | 2.804071 | false | false | false | false |
znuh/open-nexys | bscan_bram/top.vhd | 1 | 11,323 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:39:25 07/31/2009
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port ( sys_clk: in std_logic;
Led: out std_logic_vector(7 downto 0));
end top;
architecture Behavioral of top is
signal CAPTURE: std_logic;
signal UPDATE: std_logic;
signal UPDATE_sync: std_logic;
signal DRCK1: std_logic;
signal last_DRCK1: std_logic;
signal TDI: std_logic;
signal TDO1: std_logic;
signal SEL1: std_logic;
signal SEL1_sync: std_logic;
signal SHIFT: std_logic;
signal RESET: std_logic;
signal ctl: std_logic_vector(7 downto 0);
signal addr: std_logic_vector(15 downto 0);
signal data_wr: std_logic_vector(15 downto 0);
signal data_rd: std_logic_vector(15 downto 0);
signal shift_in: std_logic_vector(39 downto 0);
signal shift_out: std_logic_vector(39 downto 0);
signal ram_we: std_logic := '0';
signal last_update: std_logic;
begin
JTAG : BSCAN_SPARTAN3
port map (CAPTURE => CAPTURE,
DRCK1 => DRCK1,
DRCK2 => open,
RESET => RESET,
SEL1 => SEL1,
SEL2 => open,
SHIFT => SHIFT,
TDI => TDI,
UPDATE => UPDATE,
TDO1 => TDO1,
TDO2 => open);
RAMB16_S18_S18_inst : RAMB16_S18_S18
generic map (
INIT_A => X"00000", -- Value of output RAM registers on Port A at startup
INIT_B => X"00000", -- Value of output RAM registers on Port B at startup
SRVAL_A => X"00000", -- Port A ouput value upon SSR assertion
SRVAL_B => X"00000", -- Port B ouput value upon SSR assertion
WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
-- The follosing INIT_xx declarations specify the intiial contents of the RAM
-- Address 0 to 255
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 256 to 511
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 767
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
-- Address 0 to 255
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 256 to 511
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 767
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DOA => data_rd, -- Port A 16-bit Data Output
DOB => open, -- Port B 16-bit Data Output
DOPA => open, -- Port A 2-bit Parity Output
DOPB => open, -- Port B 2-bit Parity Output
ADDRA => addr(9 downto 0), -- Port A 10-bit Address Input
ADDRB => "0000000000", -- Port B 10-bit Address Input
CLKA => sys_clk, -- Port A Clock
CLKB => sys_clk, -- Port B Clock
DIA => data_wr, -- Port A 16-bit Data Input
DIB => x"0000", -- Port B 16-bit Data Input
DIPA => "00", -- Port A 2-bit parity Input
DIPB => "00", -- Port-B 2-bit parity Input
ENA => '1', -- Port A RAM Enable Input
ENB => '0', -- PortB RAM Enable Input
SSRA => '0', -- Port A Synchronous Set/Reset Input
SSRB => '0', -- Port B Synchronous Set/Reset Input
WEA => ram_we, -- Port A Write Enable Input
WEB => '0' -- Port B Write Enable Input
);
process(sys_clk)
begin
if rising_edge(sys_clk) then
ram_we <= '0';
--last_DRCK1 <= DRCK1;
SEL1_sync <= SEL1;
UPDATE_sync <= UPDATE;
last_update <= UPDATE_sync;
if last_update = '0' and UPDATE_sync = '1' and SEL1_sync = '1' then
ctl <= shift_in(39 downto 32);
addr <= shift_in(31 downto 16);
data_wr <= shift_in(15 downto 0);
ram_we <= shift_in(32);
Led <= shift_in(39 downto 32);
end if;
end if;
end process;
process(DRCK1)
begin
if rising_edge(DRCK1) then
if SEL1 = '1' then
if SHIFT = '1' then
shift_in <= shift_in(38 downto 0) & TDI;
shift_out <= shift_out(38 downto 0) & '0';
else
shift_out <= ctl & addr & data_rd;
end if;
end if;
--if SEL1 = '1' and SHIFT = '1' then
--shift_in <= shift_in(38 downto 0) & TDI;
--shift_out <= shift_out(38 downto 0) & '0';
--end if;
--if SEL1 = '1' and CAPTURE = '1' then
--shift_out <= ctl & addr & data_rd;
--end if;
end if;
end process;
--process(DRCK1)
--begin
-- if falling_edge(DRCK1) and SHIFT='1' and SEL1='1' then
-- shift_out <= shift_out(38 downto 0) & '0';
-- TDO1 <= shift_out(38);
--end if;
--end process;
TDO1 <= shift_out(39);
end Behavioral;
| gpl-2.0 | f7c2a5dbcc81b14070b8dd2fa65c4bb0 | 0.706085 | 5.123529 | false | false | false | false |
fabianschuiki/moore | test/vhdl/type_int.vhd | 1 | 1,536 | package pkg is
type TWOS_COMPLEMENT_INTEGER is range -32768 to 32767;
type BYTE_LENGTH_INTEGER is range 0 to 255;
type WORD_INDEX is range 31 downto 0;
subtype HIGH_BIT_LOW is BYTE_LENGTH_INTEGER range 0 to 127;
end;
library work;
use work.pkg.all;
entity foo is end;
architecture bar of foo is
signal a0 : TWOS_COMPLEMENT_INTEGER; -- should be initialized to -32768
signal a1 : TWOS_COMPLEMENT_INTEGER := 0;
signal a2 : TWOS_COMPLEMENT_INTEGER := -42;
signal a3 : TWOS_COMPLEMENT_INTEGER := 42;
signal b0 : BYTE_LENGTH_INTEGER; -- should be initialized to 0
signal b1 : BYTE_LENGTH_INTEGER := 0;
signal b2 : BYTE_LENGTH_INTEGER := 42;
signal c0 : WORD_INDEX; -- should be initialized to 31
signal c1 : WORD_INDEX := 0;
signal c2 : WORD_INDEX := 21;
signal d0 : HIGH_BIT_LOW; -- should be initialized to 0
signal d1 : HIGH_BIT_LOW := 0;
signal d2 : HIGH_BIT_LOW := 42;
signal e0 : TWOS_COMPLEMENT_INTEGER range 0 to 3; -- should be initialized to 0
signal e1 : TWOS_COMPLEMENT_INTEGER range 0 to 3 := 3;
signal f0 : TWOS_COMPLEMENT_INTEGER range 8 to 7;
begin end;
--!@ elab foo(bar)
--| entity @foo_bar () () {
--| %a0 = sig i16 -32768
--| %a1 = sig i16 0
--| %a2 = sig i16 -42
--| %a3 = sig i16 42
--| %b0 = sig i8 0
--| %b1 = sig i8 0
--| %b2 = sig i8 42
--| %c0 = sig i5 31
--| %c1 = sig i5 0
--| %c2 = sig i5 21
--| %d0 = sig i7 0
--| %d1 = sig i7 0
--| %d2 = sig i7 42
--| %e0 = sig i2 0
--| %e1 = sig i2 3
--| %f0 = sig void void
--| }
| apache-2.0 | 175b38eeb949c6fea17440df6f10f903 | 0.615885 | 2.813187 | false | false | false | false |
RowdyRajan/GestureControlInterfaceCapstone | DE2Component.vhd | 1 | 10,710 | -- Group 2: Gesture Control Interface top level file
-- Eric Smith, Chris Chmilar, Rajan Jassal
-- This file is a modified version of the top level file provided in lab 1
-- Nancy Minderman
-- [email protected]
-- This file makes extensive use of Altera template structures.
-- This file is the top-level file for lab 1 winter 2014 for version 12.1sp1 on Windows 7
-- A library clause declares a name as a library. It
-- does not create the library; it simply forward declares
-- it.
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
-- SIGNED and UNSIGNED types, and relevant functions
use ieee.numeric_std.all;
-- Basic sequential functions and concurrent procedures
use ieee.VITAL_Primitives.all;
use work.DE2_CONSTANTS.all;
entity DE2Component is
port
(
-- Input ports and 50 MHz Clock --
-- Push Buttons
KEY : in std_logic_vector (3 downto 0);
-- Switches
SW : in std_logic_vector (7 downto 0);
-- Clock
CLOCK_50 : in std_logic;
-- Green leds on board --
LEDG : out DE2_LED_GREEN;
--LCD on board
--LCD_BLON : out std_logic;
--LCD_ON : out std_logic;
--LCD_DATA : inout DE2_LCD_DATA_BUS;
--LCD_RS : out std_logic;
--LCD_EN : out std_logic;
--LCD_RW : out std_logic;
--UART interface
--UART_TXD : out std_logic; -- UART Transmitter
--UART_RXD : in std_logic; -- UART Receiver
--SDRAM on board
--DRAM_ADDR : out std_logic_vector (11 downto 0);
DRAM_ADDR : out DE2_SDRAM_ADDR_BUS;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
--DRAM_DQ : inout std_logic_vector (15 downto 0);
DRAM_DQ : inout DE2_SDRAM_DATA_BUS;
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- SRAM on board
SRAM_ADDR : out DE2_SRAM_ADDR_BUS;
SRAM_DQ : inout DE2_SRAM_DATA_BUS;
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic;
-- ISP1362 USB core interface
OTG_DATA : inout std_logic_vector(15 downto 0); -- ISP1362 Data bus 16 Bits
OTG_ADDR : out std_logic_vector(1 downto 0); -- ISP1362 Address 2 Bits
OTG_CS_N : out std_logic; -- ISP1362 Chip Select
OTG_RD_N : out std_logic; -- ISP1362 Write
OTG_WR_N : out std_logic; -- ISP1362 Read
OTG_RST_N : out std_logic; -- ISP1362 Reset
OTG_INT0 : in std_logic; -- ISP1362 Interrupt 0 (for DC)
OTG_INT1 : in std_logic; -- ISP1362 Interrupt 1 (for HC)
OTG_FSPEED : out std_logic; -- USB Full Speed, 0 = Enable, Z = Disable
OTG_LSPEED : out std_logic; -- USB Low Speed, 0 = Enable, Z = Disable
OTG_DREQ0 : in std_logic; -- ISP1362 DMA Request 0
OTG_DREQ1 : in std_logic; -- ISP1362 DMA Request 1
OTG_DACK0_N : out std_logic_vector(0 downto 0) := "Z"; -- ISP1362 DMA Acknowledge 0 (not used)
OTG_DACK1_N : out std_logic_vector(0 downto 0) := "Z" -- ISP1362 DMA Acknowledge 1 (not used)
);
end DE2Component;
architecture structure of DE2Component is
component niosII_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
--sdram
sdram_0_wire_addr : out DE2_SDRAM_ADDR_BUS; -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout DE2_SDRAM_DATA_BUS := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
altpll_0_c0_clk : out std_logic; -- clk
green_leds_external_connection_export : out DE2_LED_GREEN; -- export
switches_external_connection_export : in std_logic := 'X'; -- export
--sram
sram_0_external_interface_DQ : inout DE2_SRAM_DATA_BUS := (others => 'X'); -- DQ
sram_0_external_interface_ADDR : out DE2_SRAM_ADDR_BUS; -- ADDR
sram_0_external_interface_LB_N : out std_logic; -- LB_N
sram_0_external_interface_UB_N : out std_logic; -- UB_N
sram_0_external_interface_CE_N : out std_logic; -- CE_N
sram_0_external_interface_OE_N : out std_logic; -- OE_N
sram_0_external_interface_WE_N : out std_logic; -- WE_N
--ISP1362 Interface
usb_component_0_conduit_DATA : inout std_logic_vector(15 downto 0);
usb_component_0_conduit_ADDR : out std_logic_vector(1 downto 0);
usb_component_0_conduit_CS_N : out std_logic;
usb_component_0_conduit_RD_N : out std_logic;
usb_component_0_conduit_WR_N : out std_logic;
usb_component_0_conduit_RST_N : out std_logic;
usb_component_0_conduit_INT0 : in std_logic;
usb_component_0_conduit_INT1 : in std_logic
--LCD interface
--character_lcd_0_external_interface_DATA : inout DE2_LCD_DATA_BUS := (others => 'X'); -- DATA
--character_lcd_0_external_interface_ON : out std_logic; -- ON
--character_lcd_0_external_interface_BLON : out std_logic; -- BLON
--character_lcd_0_external_interface_EN : out std_logic; -- EN
--character_lcd_0_external_interface_RS : out std_logic; -- RS
--character_lcd_0_external_interface_RW : out std_logic -- RW
);
end component niosII_system;
-- These signals are for matching the provided IP core to
-- The specific SDRAM chip in our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
--Setting USB Speed config
OTG_FSPEED <= '0';
OTG_LSPEED <= 'Z';
--Memory related signal settings. Appears to be used for combining two signals into a singal interface.
DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
-- Component Instantiation Statement (optional)
u0 : component niosII_system
port map (
clk_clk => CLOCK_50,
reset_reset_n => KEY(0),
sdram_0_wire_addr => DRAM_ADDR,
sdram_0_wire_ba => BA,
sdram_0_wire_cas_n => DRAM_CAS_N,
sdram_0_wire_cke => DRAM_CKE,
sdram_0_wire_cs_n => DRAM_CS_N,
sdram_0_wire_dq => DRAM_DQ,
sdram_0_wire_dqm => DQM,
sdram_0_wire_ras_n => DRAM_RAS_N,
sdram_0_wire_we_n => DRAM_WE_N,
altpll_0_c0_clk => DRAM_CLK,
green_leds_external_connection_export => LEDG,
switches_external_connection_export => SW(0),
sram_0_external_interface_DQ => SRAM_DQ,
sram_0_external_interface_ADDR => SRAM_ADDR,
sram_0_external_interface_LB_N => SRAM_LB_N,
sram_0_external_interface_UB_N => SRAM_UB_N,
sram_0_external_interface_CE_N => SRAM_CE_N,
sram_0_external_interface_OE_N => SRAM_OE_N,
sram_0_external_interface_WE_N => SRAM_WE_N,
--character_lcd_0_external_interface_DATA => LCD_DATA,
--character_lcd_0_external_interface_ON => LCD_ON,
--character_lcd_0_external_interface_BLON => LCD_BLON,
--character_lcd_0_external_interface_EN => LCD_EN,
--character_lcd_0_external_interface_RS => LCD_RS,
--character_lcd_0_external_interface_RW => LCD_RW,
usb_component_0_conduit_DATA => OTG_DATA,
usb_component_0_conduit_ADDR => OTG_ADDR,
usb_component_0_conduit_CS_N => OTG_CS_N,
usb_component_0_conduit_RD_N => OTG_RD_N,
usb_component_0_conduit_WR_N => OTG_WR_N,
usb_component_0_conduit_RST_N => OTG_RST_N,
usb_component_0_conduit_INT0 => OTG_INT0,
usb_component_0_conduit_INT1 => OTG_INT1
);
end structure;
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
package DE2_CONSTANTS is
type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic;
type DE2_LED_GREEN is array(7 downto 0) of std_logic;
type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic;
type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic;
end DE2_CONSTANTS;
| gpl-3.0 | 227f07eae408b2c139a6946d63e0a138 | 0.502334 | 3.503435 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/old_data/pr_32.vhd | 1 | 626 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pr is
port(clk, S_PRlat, S_s_inc : in std_logic;
S_BUS_C : in std_logic_vector(31 downto 0);
S_PR_F : out std_logic_vector(15 downto 0));
end pr;
architecture BEHAVIOR of pr is
signal rst : std_logic_vector(15 downto 0) := "0000000010000000";
begin
S_PR_F <= rst;
process(clk) begin
if clk'event and clk = '1' then
if S_PRlat = '1' then
rst <= S_BUS_C(15 downto 0);
elsif S_s_inc = '1' then
rst <= rst + 1;
else
null;
end if;
end if;
end process;
end BEHAVIOR;
| mit | 6101e261e24c453f0238e351e43f44e2 | 0.599042 | 2.95283 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_96x512_hf/simulation/fg_tb_pkg.vhd | 1 | 11,363 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_fwft_96x512_hf_top IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(96-1 DOWNTO 0);
DOUT : OUT std_logic_vector(96-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit | 5f059cb2a28ad6f7412730dcb73a678b | 0.503212 | 3.934557 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_96x512/simulation/fg_tb_top.vhd | 1 | 5,679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 480 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 99
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| mit | 582882fe61db88eefaeca8606680e9c8 | 0.616306 | 4.175735 | false | false | false | false |
e8johan/jamcpu | control.vhd | 1 | 31,307 | ---------------------------------------------------------
-- JAM CPU
-- Control unit
--
-- License: LGPL v2+ (see the file LICENSE)
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Library General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
library ieee;
use ieee.std_logic_1164.all;
entity control is
port (
op : in std_logic_vector (5 downto 0); -- The op code
ex_asel : out std_logic; -- (ra,psw)
ex_bsel : out std_logic; -- (rb,imm)
ex_ressel : out std_logic; -- (res,sign)
ex_regsel : out std_logic_vector (1 downto 0); -- (psw,pc,b,in)
ex_aluop : out std_logic_vector (2 downto 0); -- (nop,add,sub,or,and,xor,shz,shs)
ex_domult : out std_logic; -- (off,on)
ex_multop : out std_logic; -- (low,high)
ex_invin2 : out std_logic; -- (off,on)
ex_valid_reg : out std_logic; -- Forwarding valid
ex_valid_res : out std_logic; -- Forwarding valid
ex_psw_enable : out std_logic; -- PSW will be updated
ex_put : out std_logic; -- This is a PUT
m_write : out std_logic; -- Write signal to the DM
m_read : out std_logic; -- Read signal to the DM
m_valid_mem : out std_logic; -- Forwarding valid
m_valid_reg : out std_logic; -- Forwarding valid
wb_sel : out std_logic; -- (mem,reg)
wb_enable : out std_logic; -- (off,on)
id_bsel : out std_logic; -- '0' if rd is used as r2
id_beq : out std_logic; -- '1' if the op is a branch
id_bne : out std_logic; -- '1' if the op is a branch n.eq.
illegal_op : out std_logic; -- '1' when illegal op
trap : out std_logic;
jump : out std_logic);
end;
architecture rev1 of control is
begin
process(op)
begin
case op is
when "000000" => -- ADD
ex_asel <= '0'; -- register
ex_bsel <= '0'; -- register
ex_ressel <= '0'; -- result
ex_regsel <= "10"; -- b register
ex_aluop <= "001"; -- add
ex_domult <= '0'; -- no mult
ex_multop <= '0'; -- low
ex_invin2 <= '0'; -- do not invert
ex_valid_reg <= '0'; -- reg is not valid
ex_valid_res <= '1'; -- res is valid
ex_psw_enable <= '0'; -- psw is not updated
ex_put <= '0'; -- this is not a put
m_write <= '0'; -- no write
m_read <= '0'; -- no read
m_valid_mem <= '1'; -- mem is valid
m_valid_reg <= '0'; -- reg is not valid
trap <= '0'; -- no trap
jump <= '0'; -- no jump
wb_sel <= '0'; -- memory
wb_enable <= '1'; -- enable
id_bsel <= '1'; -- use b
id_beq <= '0'; -- no branch
id_bne <= '0'; -- no branch
illegal_op <= '0'; -- legal op
when "000001" => -- ADDI
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "001";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "000010" => -- ADDX
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "001";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "000011" => -- ADDD
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "001";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "000100" => -- ADDV
ex_asel <= '0';
ex_bsel <= '0';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "001";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '1';
ex_valid_res <= '0';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "000101" => -- ADDVI
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "001";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "000110" => -- ADDVX
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "001";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "000111" => -- ADDVD
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "001";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "001000" => -- MUL
ex_asel <= '0';
ex_bsel <= '0';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= (others=>'0');
ex_domult <= '1';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "001001" => -- MULI
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= (others=>'0');
ex_domult <= '1';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
-- when "001010" => -- -
-- when "001011" => -- -
when "001100" => -- MULH
ex_asel <= '0';
ex_bsel <= '0';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= (others=>'0');
ex_domult <= '1';
ex_multop <= '1';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "001101" => -- MULHI
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= (others=>'0');
ex_domult <= '1';
ex_multop <= '1';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
-- when "001110" => -- -
-- when "001111" => -- -
when "010000" => -- SHZ
ex_asel <= '0';
ex_bsel <= '0';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "110";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "010001" => -- SHZI
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "110";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
-- when "010010" => -- -
when "010011" => -- BEQ
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= (others=>'0');
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '0';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '0';
id_bsel <= '0';
id_beq <= '1';
id_bne <= '0';
illegal_op <= '0';
when "010100" => -- SHS
ex_asel <= '0';
ex_bsel <= '0';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "111";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "010101" => -- SHSI
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "111";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
-- when "010110" => -- -
when "010111" => -- BNE
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= (others=>'0');
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '0';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '0';
id_bsel <= '0';
id_beq <= '0';
id_bne <= '1';
illegal_op <= '0';
when "011000" => -- CMP
ex_asel <= '0';
ex_bsel <= '0';
ex_ressel <= '1';
ex_regsel <= "10";
ex_aluop <= "010";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "011001" => -- CMPI
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '1';
ex_regsel <= "10";
ex_aluop <= "010";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "011010" => -- CMPX
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '1';
ex_regsel <= "10";
ex_aluop <= "010";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "011011" => -- CMPD
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '1';
ex_regsel <= "10";
ex_aluop <= "010";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "011100" => -- JUMP
ex_asel <= '0';
ex_bsel <= '0';
ex_ressel <= '0';
ex_regsel <= "01";
ex_aluop <= "001";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '0';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '0';
trap <= '0';
jump <= '1';
wb_sel <= '1';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
-- when "011101" => -- -
when "011110" => -- JUMPX
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "01";
ex_aluop <= "001";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '0';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '0';
trap <= '0';
jump <= '1';
wb_sel <= '1';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "011111" => -- JUMPD
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "01";
ex_aluop <= "001";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '0';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '0';
trap <= '0';
jump <= '1';
wb_sel <= '1';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "100000" => -- SUB
ex_asel <= '0';
ex_bsel <= '0';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "010";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "100001" => -- GET
ex_asel <= '1';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "11";
ex_aluop <= "100";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '1';
ex_valid_reg <= '1';
ex_valid_res <= '0';
ex_psw_enable <= '1';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '1';
trap <= '0';
jump <= '0';
wb_sel <= '1';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
-- when "100010" => -- -
when "100011" => -- LW
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "001";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '0';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '1';
m_valid_mem <= '0';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "100100" => -- SUBV
ex_asel <= '0';
ex_bsel <= '0';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "010";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "100101" => -- PUT
ex_asel <= '1';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "00";
ex_aluop <= "011";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '0';
ex_psw_enable <= '1';
ex_put <= '1';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '0';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
-- when "100110" => -- -
when "100111" => -- SW
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "001";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '0';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '1';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '0';
id_bsel <= '0';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
-- when "101000" => -- -
when "101001" => -- TRAP
ex_asel <= '1';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "01";
ex_aluop <= "011";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '0';
ex_psw_enable <= '1';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '0';
trap <= '1';
jump <= '0';
wb_sel <= '1';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
-- when "101010" => -- -
-- when "101011" => -- -
when "101100" => -- AND
ex_asel <= '0';
ex_bsel <= '0';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "100";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "101101" => -- ANDI
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "100";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "101110" => -- ANDX
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "100";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
-- when "101111" => -- -
when "110000" => -- OR
ex_asel <= '0';
ex_bsel <= '0';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "011";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "110001" => -- ORI
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "011";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "110010" => -- ORX
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "011";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
-- when "110011" => -- -
when "110100" => -- XOR
ex_asel <= '0';
ex_bsel <= '0';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "101";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "110101" => -- XORI
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "101";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "110110" => -- XORX
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "10";
ex_aluop <= "101";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '1';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '1';
m_valid_reg <= '0';
trap <= '0';
jump <= '0';
wb_sel <= '0';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
-- when "110111" => -- -
when "111000" => -- SET
ex_asel <= '1';
ex_bsel <= '0';
ex_ressel <= '0';
ex_regsel <= "00";
ex_aluop <= "011";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '1';
ex_valid_res <= '0';
ex_psw_enable <= '1';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '1';
trap <= '0';
jump <= '0';
wb_sel <= '1';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "111001" => -- SETI
ex_asel <= '1';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "00";
ex_aluop <= "011";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '1';
ex_valid_res <= '0';
ex_psw_enable <= '1';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '1';
trap <= '0';
jump <= '0';
wb_sel <= '1';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "111010" => -- SETX
ex_asel <= '1';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "00";
ex_aluop <= "011";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '1';
ex_valid_res <= '0';
ex_psw_enable <= '1';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '1';
trap <= '0';
jump <= '0';
wb_sel <= '1';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
-- when "111011" => -- -
when "111100" => -- RESET
ex_asel <= '1';
ex_bsel <= '0';
ex_ressel <= '0';
ex_regsel <= "00";
ex_aluop <= "100";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '1';
ex_valid_reg <= '1';
ex_valid_res <= '0';
ex_psw_enable <= '1';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '1';
trap <= '0';
jump <= '0';
wb_sel <= '1';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "111101" => -- RESETI
ex_asel <= '1';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "00";
ex_aluop <= "100";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '1';
ex_valid_reg <= '1';
ex_valid_res <= '0';
ex_psw_enable <= '1';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '1';
trap <= '0';
jump <= '0';
wb_sel <= '1';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
when "111110" => -- RESETX
ex_asel <= '1';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "00";
ex_aluop <= "100";
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '1';
ex_valid_reg <= '1';
ex_valid_res <= '0';
ex_psw_enable <= '1';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '1';
trap <= '0';
jump <= '0';
wb_sel <= '1';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '0';
-- when "111111" => -- -
when others => -- Undefined signals, etc.
ex_asel <= '0';
ex_bsel <= '1';
ex_ressel <= '0';
ex_regsel <= "01";
ex_aluop <= (others=>'0');
ex_domult <= '0';
ex_multop <= '0';
ex_invin2 <= '0';
ex_valid_reg <= '0';
ex_valid_res <= '0';
ex_psw_enable <= '0';
ex_put <= '0';
m_write <= '0';
m_read <= '0';
m_valid_mem <= '0';
m_valid_reg <= '0';
trap <= '1';
jump <= '0';
wb_sel <= '1';
wb_enable <= '1';
id_bsel <= '1';
id_beq <= '0';
id_bne <= '0';
illegal_op <= '1';
end case;
end process;
end;
| lgpl-2.1 | 3e8190ee8b8426b53600b3b08c93f0e8 | 0.37391 | 2.555882 | false | false | false | false |
fabianschuiki/moore | test/vhdl/type_enum.vhd | 1 | 1,405 | package pkg is
type MULTI_LEVEL_LOGIC is (LOW, HIGH, RISING, FALLING, AMBIGUOUS);
type BIT is ('0', '1');
type SWITCH_LEVEL is ('0', '1', 'X');
type MIXED is ('0', '1', SOME_OTHER);
end;
library work;
use work.pkg.all;
entity foo is end;
architecture bar of foo is
signal a0 : MULTI_LEVEL_LOGIC; -- should be initialized to LOW
signal a1 : MULTI_LEVEL_LOGIC := LOW;
signal a2 : MULTI_LEVEL_LOGIC := HIGH;
signal a3 : MULTI_LEVEL_LOGIC := RISING;
signal a4 : MULTI_LEVEL_LOGIC := FALLING;
signal a5 : MULTI_LEVEL_LOGIC := AMBIGUOUS;
signal b0 : BIT; -- should be initialized to '0'
signal b1 : BIT := '0';
signal b2 : BIT := '1';
signal c0 : SWITCH_LEVEL; -- should be initialized to '0'
signal c1 : SWITCH_LEVEL := '0';
signal c2 : SWITCH_LEVEL := '1';
signal c3 : SWITCH_LEVEL := 'X';
signal d0 : MIXED; -- should be initialized to '0'
signal d1 : MIXED := '0';
signal d2 : MIXED := '1';
signal d3 : MIXED := SOME_OTHER;
begin end;
--!@ elab foo(bar)
--| entity @foo_bar () () {
--| %a0 = sig n5 0
--| %a1 = sig n5 0
--| %a2 = sig n5 1
--| %a3 = sig n5 2
--| %a4 = sig n5 3
--| %a5 = sig n5 4
--| %b0 = sig n2 0
--| %b1 = sig n2 0
--| %b2 = sig n2 1
--| %c0 = sig n3 0
--| %c1 = sig n3 0
--| %c2 = sig n3 1
--| %c3 = sig n3 2
--| %d0 = sig n3 0
--| %d1 = sig n3 0
--| %d2 = sig n3 1
--| %d3 = sig n3 2
--| }
| apache-2.0 | 262c4979ef9a689d98bf67a43574ec7e | 0.553737 | 2.559199 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_64x512/simulation/fg_tb_pkg.vhd | 1 | 11,306 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_fwft_64x512_top IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit | 4853419ae8627914560dafeea3a64fcf | 0.503803 | 3.932522 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_37x512_hf/simulation/fg_tb_synth.vhd | 1 | 10,479 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(37-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(37-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(37-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(37-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 24 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 37,
C_DOUT_WIDTH => 37,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 37,
C_DIN_WIDTH => 37,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 37,
C_DIN_WIDTH => 37,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_37x512_hf_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit | d4f2fe047fc3dbe219ab5e612f554446 | 0.459968 | 4.109412 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_138x512/simulation/fg_tb_synth.vhd | 1 | 10,357 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 138,
C_DOUT_WIDTH => 138,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 138,
C_DIN_WIDTH => 138,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 138,
C_DIN_WIDTH => 138,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_138x512_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit | 222f29d26504b58f3bbc2dd6764a3fbe | 0.460848 | 4.113185 | false | false | false | false |
capitanov/MinesweeperFPGA | src/game_cores/cl_check.vhd | 1 | 3,748 | --------------------------------------------------------------------------------
--
-- Title : cl_check.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game block for square 8x8
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity cl_check is
generic(
constant yend : std_logic_vector(4 downto 0):="11000";
constant ystart : std_logic_vector(4 downto 0):="10000";
constant xend : std_logic_vector(6 downto 0):="0011000";
constant xstart : std_logic_vector(6 downto 0):="0010000"
);
port(
-- system signals:
clk : in std_logic;
reset : in std_logic;
-- vga XoY coordinates:
cnt_yy : in std_logic_vector(2 downto 0);
cnt_xx : in std_logic_vector(2 downto 0);
--data_hide : in std_logic;
display : in std_logic;
x_char : in std_logic_vector(9 downto 0); -- X line: 0:79
y_char : in std_logic_vector(8 downto 0); -- Y line: 0:29
-- out color scheme:
rgb : out std_logic_vector(2 downto 0)
);
end cl_check;
architecture cl_check of cl_check is
signal data_rom : std_logic_vector(7 downto 0);
signal x_in : std_logic_vector(6 downto 0);
signal y_in : std_logic_vector(4 downto 0);
signal data : std_logic;
signal x_rev : std_logic_vector(2 downto 0);
signal x_del : std_logic_vector(2 downto 0);
signal y_charz : std_logic_vector(3 downto 0);
constant color : std_logic_vector(2 downto 0):="111";
signal comp_yy : std_logic_vector(3 downto 0);
signal comp_xx : std_logic_vector(3 downto 0);
signal data_x, data_y : std_logic;
begin
y_charz <= y_char(3 downto 0) when rising_edge(clk);
g_rev: for ii in 0 to 2 generate
begin
x_rev(ii) <= not x_char(ii) when rising_edge(clk);
end generate;
x_del <= x_rev when rising_edge(clk);
comp_yy <= '0' & cnt_yy;
comp_xx <= '0' & cnt_xx;
x_in <= x_char(9 downto 3);
y_in <= y_char(8 downto 4);
pr_select: process(clk, reset) is
begin
if reset = '0' then
data_x <= '0';
data_y <= '0';
elsif rising_edge(clk) then
if display = '1' then
if (x_in = (xstart + comp_xx)) then
data_x <= '1';
else
data_x <= '0';
end if;
if (y_in = (ystart + comp_yy)) then
data_y <= '1';
else
data_y <= '0';
end if;
else
data_x <= '0';
data_y <= '0';
end if;
end if;
end process;
pr_new_box: process(clk, reset)
begin
if reset = '0' then
data_rom <= x"00";
elsif rising_edge(clk) then
if (data_x = '1' and data_y = '1') then
case y_charz(3 downto 0) is
when x"0" => data_rom <= x"FF";
when x"1" => data_rom <= x"81";
when x"2" => data_rom <= x"81";
when x"3" => data_rom <= x"81";
when x"4" => data_rom <= x"81";
when x"5" => data_rom <= x"81";
when x"6" => data_rom <= x"81";
when x"7" => data_rom <= x"81";
when x"8" => data_rom <= x"81";
when x"9" => data_rom <= x"81";
when x"A" => data_rom <= x"81";
when x"B" => data_rom <= x"81";
when x"C" => data_rom <= x"81";
when x"D" => data_rom <= x"83";
when x"E" => data_rom <= x"87";
when others => data_rom <= x"FF";
end case;
else
data_rom <= x"00";
end if;
end if;
end process;
---------------- stage 5: RGB DATA ----------------
pr_sw_sel: process(clk, reset) is
begin
if reset = '0' then
data <= '0';
elsif rising_edge(clk) then
data <= data_rom(to_integer(unsigned(x_del)));
end if;
end process;
g_rgb: for ii in 0 to 2 generate
begin
rgb(ii) <= data and color(ii);
end generate;
end cl_check;
| mit | f1eb1be45a2a883a7f1822885ffa4572 | 0.540288 | 2.639437 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/old_data/mem_32.vhd | 1 | 1,246 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
entity mem is
port(clk, read, write : in std_logic;
S_MAR_F : in std_logic_vector(7 downto 0);
S_MDR_F : in std_logic_vector(15 downto 0);
data : out std_logic_vector(15 downto 0));
end mem;
architecture BEHAVIOR of mem is
subtype RAM_WORD is std_logic_vector(15 downto 0);
type RAM_TYPE is array (0 to 255) of RAM_WORD;
impure function init_ram_file(RAM_FILE_NAME : in string) return RAM_TYPE is
file RAM_FILE : TEXT is in RAM_FILE_NAME;
variable RAM_FILE_LINE : line;
variable RAM_DIN : RAM_TYPE;
begin
for I in RAM_TYPE'range loop
readline(RAM_FILE, RAM_FILE_LINE);
hread(RAM_FILE_LINE, RAM_DIN(I));
end loop;
return RAM_DIN;
end function;
signal RAM_DATA : RAM_TYPE := init_ram_file("mem_16_32.txt");
signal addr : std_logic_vector(7 downto 0);
begin
data <= RAM_DATA(conv_integer(addr));
process(clk) begin
if clk'event and clk = '1' then
if write = '1' then
RAM_DATA(conv_integer(S_MAR_F)) <= S_MDR_F;
elsif read = '1' then
addr <= S_MAR_F;
else
null;
end if;
end if;
end process;
end BEHAVIOR;
| mit | 6d24a9919a0832e44eeb73736ff798da | 0.658106 | 2.966667 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_37x512_hf/simulation/fg_tb_top.vhd | 2 | 5,679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 40
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| mit | 30e0684c9d2102bb96bee56d8c901984 | 0.616306 | 4.175735 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_96x512/example_design/fifo_fwft_96x512_top.vhd | 1 | 4,810 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_fwft_96x512_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_fwft_96x512_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(96-1 DOWNTO 0);
DOUT : OUT std_logic_vector(96-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_fwft_96x512_top;
architecture xilinx of fifo_fwft_96x512_top is
SIGNAL clk_i : std_logic;
component fifo_fwft_96x512 is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(96-1 DOWNTO 0);
DOUT : OUT std_logic_vector(96-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_fwft_96x512 PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | df6badba4feb6394206e803aa580c91c | 0.528482 | 4.878296 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/mem.vhd | 1 | 1,241 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
entity mem is
port(clk, read, write : in std_logic;
S_MAR_F : in std_logic_vector(7 downto 0);
S_MDR_F : in std_logic_vector(15 downto 0);
data : out std_logic_vector(15 downto 0));
end mem;
architecture BEHAVIOR of mem is
subtype RAM_WORD is std_logic_vector(15 downto 0);
type RAM_TYPE is array (0 to 255) of RAM_WORD;
impure function init_ram_file(RAM_FILE_NAME : in string) return RAM_TYPE is
file RAM_FILE : TEXT is in RAM_FILE_NAME;
variable RAM_FILE_LINE : line;
variable RAM_DIN : RAM_TYPE;
begin
for I in RAM_TYPE'range loop
readline(RAM_FILE, RAM_FILE_LINE);
hread(RAM_FILE_LINE, RAM_DIN(I));
end loop;
return RAM_DIN;
end function;
signal RAM_DATA : RAM_TYPE := init_ram_file("mem2.txt");
signal addr : std_logic_vector(7 downto 0);
begin
data <= RAM_DATA(conv_integer(addr));
process(clk) begin
if clk'event and clk = '1' then
if write = '1' then
RAM_DATA(conv_integer(S_MAR_F)) <= S_MDR_F;
elsif read = '1' then
addr <= S_MAR_F;
else
null;
end if;
end if;
end process;
end BEHAVIOR;
| mit | ca03c32825cd087dfaa58bb79f4aa991 | 0.65834 | 2.976019 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/csgc.vhd | 1 | 13,071 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity csgc is
port(
clk : in std_logic;
mlang : in std_logic_vector(15 downto 0);
ba_ctl : out std_logic_vector(2 downto 0);
bb_ctl : out std_logic_vector(4 downto 0);
address : out std_logic_vector(7 downto 0);
gr_lat : out std_logic;
gra : out std_logic_vector(3 downto 0);
grb : out std_logic_vector(3 downto 0);
grc : out std_logic_vector(3 downto 0);
ir_lat : out std_logic;
fr_lat : out std_logic;
pr_lat : out std_logic;
pr_cnt : out std_logic;
mar_lat : out std_logic;
mdr_lat : out std_logic;
mdr_sel : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
func : out std_logic_vector(3 downto 0);
phaseView : out std_logic_vector(3 downto 0)
);
end csgc;
architecture BEHAVIOR of csgc is
-- Definitions --
signal mnemo : std_logic_vector(3 downto 0);
signal opeA : std_logic_vector(3 downto 0);
signal opeB_addr : std_logic_vector(7 downto 0);
signal opeB_gr : std_logic_vector(3 downto 0);
signal phase : std_logic_vector(3 downto 0);
signal serial : std_logic_vector(41 downto 0);
-- Main --
begin
phaseView <= phase;
mnemo <= mlang(15 downto 12);
opeA <= mlang(11 downto 8);
opeB_addr <= mlang( 7 downto 0);
opeB_gr <= mlang( 3 downto 0);
-- Process --
process(clk) begin
if(clk'event and (clk = '1')) then
-- do instruction --
case mnemo is
when "0000" => -- HALT --
phase <= "1000";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "00000" & "0000";
when "0001" => -- LD1 --
case phase is
when "0000" => -- GRB->GRA, PR=PR+1
phase <= "1000";
serial <= "010" & "00000" & "00000000" & "1" & opeB_gr & "0000" & opeA & "0001" & "00000" & "0000";
-- busA | busB | address |grlat| gra | grb | grc | i/f/pr |mem,mda/r| func
when others => null;
end case;
when "0010" => -- LD2 --
case phase is
when "0000" => -- address->MAR
phase <= "0001";
serial <= "000" & "00001" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0000" & "10000" & "0001";
when "0001" => -- change memory address
phase <= "0010";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "00010" & "0000";
when "0010" => -- mem(MAR)->MDR
phase <= "0011";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "01110" & "0000";
when "0011" => -- MDR->GRA, PR=PR+1
phase <= "1000";
serial <= "000" & "00010" & "00000000" & "1" & "0000" & "0000" & opeA & "0001" & "00000" & "0001";
when others => null;
end case;
when "0011" => -- LAD --
case phase is
when "0000" => -- address->GRA, PR=PR+1
phase <= "1000";
serial <= "000" & "00001" & opeB_addr & "1" & "0000" & "0000" & opeA & "0001" & "00000" & "0001";
when others => null;
end case;
when "0100" => -- STR --
case phase is
when "0000" => -- GRA->MDR
phase <= "0001";
serial <= "010" & "00000" & "00000000" & "0" & opeA & "0000" & "0000" & "0000" & "01000" & "0000";
when "0001" => -- address->MAR
phase <= "0010";
serial <= "000" & "00001" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0000" & "10000" & "0001";
when "0010" => -- MDR->mem(MAR), PR=PR+1
phase <= "1000";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0001" & "00001" & "0000";
when others => null;
end case;
when "0101" => -- ADD --
case phase is
when "0000" => -- GRA=GRA+GRB, PR=PR+1
phase <= "1000";
serial <= "010" & "10000" & "00000000" & "1" & opeA & opeB_gr & opeA & "0101" & "00000" & "0101";
when others => null;
end case;
when "0110" => -- SUB --
case phase is
when "0000" => -- GRA=GRA-GRB, PR=PR+1
phase <= "1000";
serial <= "010" & "10000" & "00000000" & "1" & opeA & opeB_gr & opeA & "0101" & "00000" & "0110";
when others => null;
end case;
when "0111" => -- SL --
case phase is
when "0000" => -- GRA=GRA<<GRB, PR=PR+1
phase <= "1000";
serial <= "010" & "10000" & "00000000" & "1" & opeA & opeB_gr & opeA & "0101" & "00000" & "0111";
when others => null;
end case;
when "1000" => -- SR --
case phase is
when "0000" => -- GRA=GRA>>GRB, PR=PR+1
phase <= "1000";
serial <= "010" & "10000" & "00000000" & "1" & opeA & opeB_gr & opeA & "0101" & "00000" & "1000";
when others => null;
end case;
when "1001" => -- NAND --
case phase is
when "0000" => -- GRA=GRAnandGRB, PR=PR+1
phase <= "1000";
serial <= "010" & "10000" & "00000000" & "1" & opeA & opeB_gr & opeA & "0101" & "00000" & "1001";
when others => null;
end case;
when "1010" => -- JMP --
if(opeA = "0000") then
case phase is
when "0000" => -- address->PR
phase <= "1000";
serial <= "000" & "00001" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "0001";
when others => null;
end case;
else
case phase is
when "0000" => -- PR->GRA
phase <= "0001";
serial <= "000" & "01000" & "00000000" & "1" & "0000" & "0000" & opeA & "0000" & "00000" & "0001";
when "0001" => -- address->PR
phase <= "1000";
serial <= "000" & "00001" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "0001";
when others => null;
end case;
end if;
when "1011" => -- JZE --
if(opeA = "0000") then
case phase is
when "0000" => -- if(ZF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1011";
when others => null;
end case;
else
case phase is
when "0000" => -- PR->GRA
phase <= "0001";
serial <= "000" & "01000" & "00000000" & "1" & "0000" & "0000" & opeA & "0000" & "00000" & "0001";
when "0001" => -- if(ZF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1011";
when others => null;
end case;
end if;
when "1100" => -- JMI --
if(opeA = "0000") then
case phase is
when "0000" => -- if(SF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1100";
when others => null;
end case;
else
case phase is
when "0000" => -- PR->GRA
phase <= "0001";
serial <= "000" & "01000" & "00000000" & "1" & "0000" & "0000" & opeA & "0000" & "00000" & "0001";
when "0001" => -- if(SF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1100";
when others => null;
end case;
end if;
when "1101" => -- JOV --
if(opeA = "0000") then
case phase is
when "0000" => -- if(OF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1101";
when others => null;
end case;
else
case phase is
when "0000" => -- PR->GRA
phase <= "0001";
serial <= "000" & "01000" & "00000000" & "1" & "0000" & "0000" & opeA & "0000" & "00000" & "0001";
when "0001" => -- if(OF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1101";
when others => null;
end case;
end if;
when "1110" => -- RJMP --
case phase is
when "0000" => -- GRA->PR
phase <= "0001";
serial <= "000" & "10000" & "00000000" & "0" & "0000" & opeA & "0000" & "0010" & "00000" & "0001";
when "0001" => -- PR=PR+1
phase <= "1000";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0001" & "00000" & "0000";
when others => null;
end case;
when "1111" => -- DISP --
phase <= "1000"; -- PR=PR+1
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0001" & "00000" & "0000";
when others =>
phase <= "1000";
end case;
-- go next instruction --
case phase is
when "1000" => -- PR->MAR
phase <= "1001";
serial <= "000" & "01000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "10000" & "0001";
when "1001" => -- change memory address
phase <= "1010";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "00010" & "0000";
when "1010" => -- mem(MAR)->MDR
phase <= "1011";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "01110" & "0000";
when "1011" => -- MDR->IR
phase <= "1100";
serial <= "001" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "1000" & "00000" & "0000";
when "1100" => -- changing Mlang
phase <= "0000";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "00000" & "0000";
when others => null;
end case;
else
null;
end if;
end process;
ba_ctl <= serial(41 downto 39);
bb_ctl <= serial(38 downto 34);
address <= serial(33 downto 26);
gr_lat <= serial(25);
gra <= serial(24 downto 21);
grb <= serial(20 downto 17);
grc <= serial(16 downto 13);
ir_lat <= serial(12);
fr_lat <= serial(11);
pr_lat <= serial(10);
pr_cnt <= serial(9);
mar_lat <= serial(8);
mdr_lat <= serial(7);
mdr_sel <= serial(6);
m_read <= serial(5);
m_write <= serial(4);
func <= serial(3 downto 0);
end BEHAVIOR;
| mit | 21dedd142d3e488d4b8a165aac7fe18a | 0.376482 | 3.785404 | false | false | false | false |
RowdyRajan/GestureControlInterfaceCapstone | usb_component.vhd | 1 | 2,445 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb is
port(
--Clock and Reset
clk : in std_logic;
reset_n : in std_logic;
-- USB Conduit interface to DE2 (Export)
USB_DATA : inout std_logic_vector(15 downto 0);
USB_ADDR : out std_logic_vector(1 downto 0);
USB_WR_N : out std_logic := '1';
USB_RD_N : out std_logic := '1';
USB_RST_N : out std_logic := '1';
USB_CS_N : out std_logic := '1';
USB_INT0 : in std_logic; -- Irq 0 DC
USB_INT1 : in std_logic; -- Irq 1 HC
-- Avalon Memory-Mapped-Slave interface Device Controller (DC)
avs_dc_address : in std_logic;
avs_dc_writedata : in std_logic_vector(15 downto 0);
avs_dc_write_n : in std_logic;
avs_dc_read_n : in std_logic;
avs_dc_CS_n : in std_logic;
avs_dc_readdata : out std_logic_vector(15 downto 0);
avs_dc_irq : out std_logic;
-- Avalon Memory-Mapped-Slave interface Host Controller (HC)
-- Probably will not use this interface.
avs_hc_address : in std_logic;
avs_hc_writedata : in std_logic_vector(15 downto 0);
avs_hc_write_n : in std_logic;
avs_hc_read_n : in std_logic;
avs_hc_CS_n : in std_logic;
avs_hc_readdata : out std_logic_vector(15 downto 0);
avs_hc_irq : out std_logic
);
end usb;
architecture connections of usb is
begin
-- Send interrupt from DE2 connection to proper controller
avs_dc_irq <= USB_INT0;
avs_hc_irq <= USB_INT1;
-- Two cases possible, using the host controller or the device controller.
-- Currently this does not full function for the Host Controller (HC) but we
-- do not need it for our project. I do intend to make the architecture generalized later
--Device controller signals
USB_DATA <= avs_dc_writedata when avs_dc_write_n = '0' else (others => 'Z'); -- Only does device controller
avs_dc_readdata <= USB_DATA when avs_dc_read_n = '0' else (others => 'Z');
avs_hc_readdata <= USB_DATA when avs_hc_read_n = '0' else (others => 'Z');
USB_CS_N <= '1' when avs_dc_CS_n = '0' and avs_hc_CS_n = '0' else '0';
USB_ADDR(0) <= '1';
USB_ADDR(1) <= avs_dc_address;
USB_RD_N <= avs_dc_read_n; --Just Ignoring the HC controller right now.
USB_WR_N <= avs_dc_write_n;
USB_RST_N <= reset_n;
end architecture connections;
-- If chip_select_n == 1
-- I could probably have processes for chip select for toggling between HC and DC
-- but for now i'm less than interested when I havent gotten DC working
| gpl-3.0 | 18a60d02a79826f0268360729b24d4b3 | 0.659305 | 2.759594 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_64x512/simulation/fg_tb_synth.vhd | 1 | 10,346 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => 64,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_64x512_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit | fca93175f6fbf94ffdb546c739b2337a | 0.460275 | 4.108817 | false | false | false | false |
TMU-VHDL-team2/sqrt | fpga/csgc.vhd | 1 | 13,819 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity csgc is
port(
clk : in std_logic;
init_phase : in std_logic_vector(3 downto 0);
mlang : in std_logic_vector(15 downto 0);
ba_ctl : out std_logic_vector(2 downto 0);
bb_ctl : out std_logic_vector(4 downto 0);
address : out std_logic_vector(7 downto 0);
gr_lat : out std_logic;
gra : out std_logic_vector(3 downto 0);
grb : out std_logic_vector(3 downto 0);
grc : out std_logic_vector(3 downto 0);
ir_lat : out std_logic;
fr_lat : out std_logic;
pr_lat : out std_logic;
pr_cnt : out std_logic;
mar_lat : out std_logic;
mdr_lat : out std_logic;
mdr_sel : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
func : out std_logic_vector(3 downto 0);
phaseView : out std_logic_vector(3 downto 0)
);
end csgc;
architecture BEHAVIOR of csgc is
-- Definitions --
signal mnemo : std_logic_vector(3 downto 0);
signal opeA : std_logic_vector(3 downto 0);
signal opeB_addr : std_logic_vector(7 downto 0);
signal opeB_gr : std_logic_vector(3 downto 0);
signal phase : std_logic_vector(3 downto 0);
signal serial : std_logic_vector(41 downto 0);
-- Main --
begin
phaseView <= phase;
mnemo <= mlang(15 downto 12);
opeA <= mlang(11 downto 8);
opeB_addr <= mlang( 7 downto 0);
opeB_gr <= mlang( 3 downto 0);
-- Process --
process(clk) begin
if(clk'event and (clk = '1')) then
-- do instruction --
case mnemo is
when "0000" => -- HALT --
case phase is
when "0000" =>
if (init_phase = X"1") then
phase <= "0000";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "00000" & "0000";
elsif (init_phase = X"2") then -- X"80"->PR
phase <= "1000";
serial <= "000" & "00001" & "10000000" & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "0001";
else
phase <= "1000";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "00000" & "0000";
end if;
when others => null;
end case;
when "0001" => -- LD1 --
case phase is
when "0000" => -- GRB->GRA, PR=PR+1
phase <= "1000";
serial <= "010" & "00000" & "00000000" & "1" & opeB_gr & "0000" & opeA & "0001" & "00000" & "0000";
-- busA | busB | address |grlat| gra | grb | grc | i/f/pr |mem,mda/r| func
when others => null;
end case;
when "0010" => -- LD2 --
case phase is
when "0000" => -- address->MAR
phase <= "0001";
serial <= "000" & "00001" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0000" & "10000" & "0001";
when "0001" => -- change memory address
phase <= "0010";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "00010" & "0000";
when "0010" => -- mem(MAR)->MDR
phase <= "0011";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "01110" & "0000";
when "0011" => -- MDR->GRA, PR=PR+1
phase <= "1000";
serial <= "000" & "00010" & "00000000" & "1" & "0000" & "0000" & opeA & "0001" & "00000" & "0001";
when others => null;
end case;
when "0011" => -- LAD --
case phase is
when "0000" => -- address->GRA, PR=PR+1
phase <= "1000";
serial <= "000" & "00001" & opeB_addr & "1" & "0000" & "0000" & opeA & "0001" & "00000" & "0001";
when others => null;
end case;
when "0100" => -- STR --
case phase is
when "0000" => -- GRA->MDR
phase <= "0001";
serial <= "010" & "00000" & "00000000" & "0" & opeA & "0000" & "0000" & "0000" & "01000" & "0000";
when "0001" => -- address->MAR
phase <= "0010";
serial <= "000" & "00001" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0000" & "10000" & "0001";
when "0010" => -- MDR->mem(MAR), PR=PR+1
phase <= "1000";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0001" & "00001" & "0000";
when others => null;
end case;
when "0101" => -- ADD --
case phase is
when "0000" => -- GRA=GRA+GRB, PR=PR+1
phase <= "1000";
serial <= "010" & "10000" & "00000000" & "1" & opeA & opeB_gr & opeA & "0101" & "00000" & "0101";
when others => null;
end case;
when "0110" => -- SUB --
case phase is
when "0000" => -- GRA=GRA-GRB, PR=PR+1
phase <= "1000";
serial <= "010" & "10000" & "00000000" & "1" & opeA & opeB_gr & opeA & "0101" & "00000" & "0110";
when others => null;
end case;
when "0111" => -- SL --
case phase is
when "0000" => -- GRA=GRA<<GRB, PR=PR+1
phase <= "1000";
serial <= "010" & "10000" & "00000000" & "1" & opeA & opeB_gr & opeA & "0101" & "00000" & "0111";
when others => null;
end case;
when "1000" => -- SR --
case phase is
when "0000" => -- GRA=GRA>>GRB, PR=PR+1
phase <= "1000";
serial <= "010" & "10000" & "00000000" & "1" & opeA & opeB_gr & opeA & "0101" & "00000" & "1000";
when others => null;
end case;
when "1001" => -- NAND --
case phase is
when "0000" => -- GRA=GRAnandGRB, PR=PR+1
phase <= "1000";
serial <= "010" & "10000" & "00000000" & "1" & opeA & opeB_gr & opeA & "0101" & "00000" & "1001";
when others => null;
end case;
when "1010" => -- JMP --
if(opeA = "0000") then
case phase is
when "0000" => -- address->PR
phase <= "1000";
serial <= "000" & "00001" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "0001";
when others => null;
end case;
else
case phase is
when "0000" => -- PR->GRA
phase <= "0001";
serial <= "000" & "01000" & "00000000" & "1" & "0000" & "0000" & opeA & "0000" & "00000" & "0001";
when "0001" => -- address->PR
phase <= "1000";
serial <= "000" & "00001" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "0001";
when others => null;
end case;
end if;
when "1011" => -- JZE --
if(opeA = "0000") then
case phase is
when "0000" => -- if(ZF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1011";
when others => null;
end case;
else
case phase is
when "0000" => -- PR->GRA
phase <= "0001";
serial <= "000" & "01000" & "00000000" & "1" & "0000" & "0000" & opeA & "0000" & "00000" & "0001";
when "0001" => -- if(ZF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1011";
when others => null;
end case;
end if;
when "1100" => -- JMI --
if(opeA = "0000") then
case phase is
when "0000" => -- if(SF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1100";
when others => null;
end case;
else
case phase is
when "0000" => -- PR->GRA
phase <= "0001";
serial <= "000" & "01000" & "00000000" & "1" & "0000" & "0000" & opeA & "0000" & "00000" & "0001";
when "0001" => -- if(SF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1100";
when others => null;
end case;
end if;
when "1101" => -- JOV --
if(opeA = "0000") then
case phase is
when "0000" => -- if(OF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1101";
when others => null;
end case;
else
case phase is
when "0000" => -- PR->GRA
phase <= "0001";
serial <= "000" & "01000" & "00000000" & "1" & "0000" & "0000" & opeA & "0000" & "00000" & "0001";
when "0001" => -- if(OF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1101";
when others => null;
end case;
end if;
when "1110" => -- RJMP --
case phase is
when "0000" => -- GRA->PR
phase <= "0001";
serial <= "000" & "10000" & "00000000" & "0" & "0000" & opeA & "0000" & "0010" & "00000" & "0001";
when "0001" => -- PR=PR+1
phase <= "1000";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0001" & "00000" & "0000";
when others => null;
end case;
when "1111" => -- DISP --
phase <= "1000"; -- PR=PR+1
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0001" & "00000" & "0000";
when others =>
phase <= "1000";
end case;
-- go next instruction --
case phase is
when "1000" => -- PR->MAR
phase <= "1001";
serial <= "000" & "01000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "10000" & "0001";
when "1001" => -- change memory address
phase <= "1010";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "00010" & "0000";
when "1010" => -- mem(MAR)->MDR
phase <= "1011";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "01110" & "0000";
when "1011" => -- MDR->IR
phase <= "1100";
serial <= "001" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "1000" & "00000" & "0000";
when "1100" => -- changing Mlang
phase <= "0000";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "00000" & "0000";
when others => null;
end case;
else
null;
end if;
end process;
ba_ctl <= serial(41 downto 39);
bb_ctl <= serial(38 downto 34);
address <= serial(33 downto 26);
gr_lat <= serial(25);
gra <= serial(24 downto 21);
grb <= serial(20 downto 17);
grc <= serial(16 downto 13);
ir_lat <= serial(12);
fr_lat <= serial(11);
pr_lat <= serial(10);
pr_cnt <= serial(9);
mar_lat <= serial(8);
mdr_lat <= serial(7);
mdr_sel <= serial(6);
m_read <= serial(5);
m_write <= serial(4);
func <= serial(3 downto 0);
end BEHAVIOR;
| mit | 393cd74952ed9c5b654b53a09c1dcede | 0.373327 | 3.810036 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_37x512_hf/example_design/fifo_37x512_hf_top.vhd | 1 | 4,996 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_37x512_hf_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_37x512_hf_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(1-1 DOWNTO 0);
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(37-1 DOWNTO 0);
DOUT : OUT std_logic_vector(37-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_37x512_hf_top;
architecture xilinx of fifo_37x512_hf_top is
SIGNAL clk_i : std_logic;
component fifo_37x512_hf is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(1-1 DOWNTO 0);
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(37-1 DOWNTO 0);
DOUT : OUT std_logic_vector(37-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_37x512_hf PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 5c8397337190f7ab11ceda355d616bd0 | 0.524019 | 4.831721 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_69x512/example_design/fifo_69x512_top.vhd | 1 | 4,780 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_69x512_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_69x512_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(69-1 DOWNTO 0);
DOUT : OUT std_logic_vector(69-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_69x512_top;
architecture xilinx of fifo_69x512_top is
SIGNAL clk_i : std_logic;
component fifo_69x512 is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(69-1 DOWNTO 0);
DOUT : OUT std_logic_vector(69-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_69x512 PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | cf3a6687416de07831a992561d9acfdb | 0.526778 | 4.907598 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_96x512/example_design/fifo_fwft_96x512_top_wrapper.vhd | 1 | 19,025 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_fwft_96x512_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_fwft_96x512_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(96-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(96-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_fwft_96x512_top_wrapper;
architecture xilinx of fifo_fwft_96x512_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_fwft_96x512_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(96-1 DOWNTO 0);
DOUT : OUT std_logic_vector(96-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_fwft_96x512_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 83c7252b43bb9e5033f9f406142b7062 | 0.486886 | 3.961066 | false | false | false | false |
freecores/pcounter | pdchain.vhdl | 1 | 1,099 | --
-- * pipelined synchronous pulse counter *
-- pdchain -- multi-bit counter top-level entity
--
-- fast counter for slow-carry architectures
-- non-monotonic counting, value calculable by HDL/CPU
--
-- idea&code by Marek Peca <[email protected]> 08/2012
-- Vyzkumny a zkusebni letecky ustav, a.s. http://vzlu.cz/
-- thanks to Michael Vacek <[email protected]> for testing
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pdchain is
generic (
n: natural := 32
);
port (
clock: in std_logic;
en: in std_logic;
q: out std_logic_vector (n-1 downto 0)
);
end pdchain;
architecture behavioral of pdchain is
component pdivtwo
port (
clock: in std_logic;
en: in std_logic;
q, p: out std_logic
);
end component;
--
signal b: std_logic_vector (q'range);
begin
q0: pdivtwo
port map (
clock => clock, en => en, p => b(0), q => q(0)
);
ch: for k in 1 to b'high generate
qk: pdivtwo
port map (
clock => clock, en => b(k-1), p => b(k), q => q(k)
);
end generate;
end behavioral;
| lgpl-3.0 | a6d71be136aac3aef230423de49d39a1 | 0.618744 | 2.99455 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_138x16_shift/simulation/fg_tb_top.vhd | 1 | 5,679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 480 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 29
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| mit | 6e9686609c6d9db1a237fd1689fc1f42 | 0.616306 | 4.175735 | false | false | false | false |
capitanov/MinesweeperFPGA | src/keyboard/ctrl_key_decoder.vhd | 1 | 3,273 | --------------------------------------------------------------------------------
--
-- Title : ctrl_key_decoder.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : KEYBOARD DECODER
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.ctrl_types_pkg.key_data;
entity ctrl_key_decoder is
port(
-- system signals
clk : in std_logic; -- SYSTEM CLOCK
-- keyboard in:
ps2_clk : in std_logic; -- PS/2 CLK
ps2_data : in std_logic; -- PS/2 DATA
-- keyboard out:
keys_out : out key_data; -- KEY DATA
new_key : out std_logic -- DETECT NEW KEY
);
end ctrl_key_decoder;
architecture ctrl_key_decoder of ctrl_key_decoder is
component ps2_keyboard is
generic(
clk_freq : integer := 50_000_000; --system clock frequency in hz
debounce_counter_size : integer := 8); --set such that (2^size)/clk_freq = 5us (size = 8 for 50mhz)
port(
clk : in std_logic; --system clock
ps2_clk : in std_logic; --clock signal from ps/2 keyboard
ps2_data : in std_logic; --data signal from ps/2 keyboard
ps2_code_new : out std_logic; --flag that new ps/2 code is available on ps2_code bus
ps2_code : out std_logic_vector(7 downto 0)); --code received from ps/2
end component;
signal new_code : std_logic;
signal key_code : std_logic_vector(7 downto 0);
signal key_codez : std_logic_vector(7 downto 0);
signal arrowU, arrowD, arrowL, arrowR : std_logic;
signal arrowEn, arrowSp, arrowY, arrowN : std_logic;
signal Esc : std_logic;
begin
key_codez <= key_code after 1 ns when rising_edge(clk);
------------------------------------------------
new_key <= new_code when rising_edge(clk);
------------------------------------------------
keys_out.wsad <= arrowU & arrowD & arrowL & arrowR when rising_edge(clk);
keys_out.enter <= arrowEn when rising_edge(clk);
keys_out.space <= arrowSp when rising_edge(clk);
keys_out.kY <= arrowY when rising_edge(clk);
keys_out.kN <= arrowN when rising_edge(clk);
keys_out.Esc <= Esc when rising_edge(clk);
------------------------------------------------
arrowU <= '1' when key_codez = x"1D" and key_code = x"F0" else '0';
arrowD <= '1' when key_codez = x"1B" and key_code = x"F0" else '0';
arrowL <= '1' when key_codez = x"1C" and key_code = x"F0" else '0';
arrowR <= '1' when key_codez = x"23" and key_code = x"F0" else '0';
arrowN <= '1' when key_codez = x"31" and key_code = x"F0" else '0';
arrowY <= '1' when key_codez = x"35" and key_code = x"F0" else '0';
arrowSp <= '1' when key_codez = x"29" and key_code = x"F0" else '0';
arrowEn <= '1' when key_codez = x"5A" and key_code = x"F0" else '0';
Esc <= '1' when key_codez = x"76" and key_code = x"F0" else '0';
------------------------------------------------
x_key: ps2_keyboard
port map(
clk => clk,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
ps2_code_new => new_code,
ps2_code => key_code
);
end ctrl_key_decoder; | mit | 013f0b63c6a7b11abd7930d57a5aefe4 | 0.523984 | 3.067479 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/tb_csgc.vhd | 1 | 3,316 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity tb_csgc is
end tb_csgc;
architecture BEHAVIOR of tb_csgc is
-- Definitions --
constant STEP : time := 10 ns; -- A clock cycle is set to be 10ns --
signal mnemo : std_logic_vector(3 downto 0) := "0000";
signal opeA : std_logic_vector(3 downto 0) := "1011";
signal opeB : std_logic_vector(7 downto 0) := "10010110";
signal clk : std_logic;
signal mlang : std_logic_vector(15 downto 0);
signal ba_ctl : std_logic_vector(2 downto 0);
signal bb_ctl : std_logic_vector(4 downto 0);
signal address : std_logic_vector(7 downto 0);
signal gr_lat : std_logic;
signal gra : std_logic_vector(3 downto 0);
signal grb : std_logic_vector(3 downto 0);
signal grc : std_logic_vector(3 downto 0);
signal ir_lat : std_logic;
signal fr_lat : std_logic;
signal pr_lat : std_logic;
signal pr_cnt : std_logic;
signal mar_lat : std_logic;
signal mdr_lat : std_logic;
signal mdr_sel : std_logic;
signal m_read : std_logic;
signal m_write : std_logic;
signal func : std_logic_vector(3 downto 0);
signal phaseView : std_logic_vector(3 downto 0);
component csgc is
port(
clk : in std_logic;
mlang : in std_logic_vector(15 downto 0);
ba_ctl : out std_logic_vector(2 downto 0);
bb_ctl : out std_logic_vector(4 downto 0);
address : out std_logic_vector(7 downto 0);
gr_lat : out std_logic;
gra : out std_logic_vector(3 downto 0);
grb : out std_logic_vector(3 downto 0);
grc : out std_logic_vector(3 downto 0);
ir_lat : out std_logic;
fr_lat : out std_logic;
pr_lat : out std_logic;
pr_cnt : out std_logic;
mar_lat : out std_logic;
mdr_lat : out std_logic;
mdr_sel : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
func : out std_logic_vector(3 downto 0);
phaseView : out std_logic_vector(3 downto 0)
);
end component;
-- Main --
begin
uut : csgc port map(
clk => clk ,
mlang => mlang ,
ba_ctl => ba_ctl ,
bb_ctl => bb_ctl ,
address => address,
gr_lat => gr_lat ,
gra => gra ,
grb => grb ,
grc => grc ,
ir_lat => ir_lat ,
fr_lat => fr_lat ,
pr_lat => pr_lat ,
pr_cnt => pr_cnt ,
mar_lat => mar_lat,
mdr_lat => mdr_lat,
mdr_sel => mdr_sel,
m_read => m_read ,
m_write => m_write,
func => func,
phaseView => phaseView
);
mlang <= mnemo & opeA & opeB;
clk_process: process
begin
clk <= '0';
wait for STEP/2; --for 0.5 ns signal is '0'.
clk <= '1';
wait for STEP/2; --for next 0.5 ns signal is '1'.
end process;
tb_csgc: process
begin
if(phaseView = "0000") then
mnemo <= mnemo + "0001";
else
null;
end if;
wait for STEP;
end process;
end BEHAVIOR;
| mit | ae9af089ceefbe25eb12a033e2b628ba | 0.513269 | 3.319319 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_64x512_hf/simulation/fg_tb_synth.vhd | 1 | 9,401 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL prog_empty : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => 64,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_64x512_hf_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit | 610e43815ffc2102526f3a8ee155643f | 0.451654 | 4.210031 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_138x512/simulation/fg_tb_top.vhd | 1 | 5,679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 480 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 13
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| mit | a8f5099f93d68ce72cd6508a3133e6e7 | 0.616306 | 4.175735 | false | false | false | false |
fabianschuiki/moore | test/vhdl/seq_stmts.vhd | 1 | 3,972 | package body foo is
function bar return std_logic is
begin
-- Wait Statement
wait;
wait for 10 ns;
wait until false;
wait on S;
wait until F(S(3)) and (S(l) or S(r));
wait on S(3), S, l, r until F(S(3)) and (S(l) or S(r));
wait on S(3), S, l, r until F(S(3)) and (S(l) or S(r)) for 20 ns;
loop
wait on Clk;
exit when Clk = '1';
end loop;
-- Assertion Statement
assert (J /= C) report "J = C" severity note;
assert (not OVERFLOW) report "Accumulator overflowed" severity failure;
assert false report "Stack overflow" severity error;
assert D'stable(SETUP_TIME) report "Setup Violation..." severity warning;
assert 3 = 2 + 2;
assert 3 = 2 + 2 report "Assertion violation.";
assert 3 = 2 + 2 report "Assertion violation." severity error;
assert i < 5 report "unexpected value. i = " & integer'image(i);
-- Report Statement
report "Entering process P";
report "Setup or Hold violation; outputs driven to 'X'" severity WARNING;
-- Signal Assignment Statement
-- If Statement
if (X = 5) and (Y = 9) then
Z <= A;
elsif (X >= 5) then
Z <= B;
else
Z <= C;
end if;
if RESET = '1' then
COUNT <= 0;
elsif CLK'event and CLK = '1' then
if (COUNT >= 9) then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
end if;
-- Case Statement
case SEL is
when "01" => Z <= A;
when "10" => Z <= B;
when others => Z <= 'X';
end case;
case INT_A is
when 0 => Z <= A;
when 1 to 3 => Z <= B;
when 4|6|8 => Z <= C;
when others => Z <= 'X';
end case;
-- Loop Statement
for I in o to 3 loop
if (A = I) then
Z(I) <= '1';
end if;
end loop;
TMP := '0';
for I in A'low to A'high loop
TMP := TMP xor A(I);
end loop;
ODD <= TMP;
for SEL in PRIMARY loop
V_BUS <= VIDEO(SEL);
wait for 10 ns;
end loop;
Z <= "0000";
I := 0;
while (I <= 3) loop
if (A = I) then
Z(I) <= '1';
end if;
I := I + 1;
end loop;
while NOW < MAX_SIM_TIME loop
CLK <= not CLK;
wait for PERIOD/2;
end loop;
wait;
Z <= "0000";
I := 0;
L1: loop
if (A = I) then
Z(I) <= '1';
end if;
I := I + 1;
end loop;
-- Next Statement
next;
next foo;
next when I = 4;
next bar when I = 4;
-- Exit Statement
exit;
exit foo;
exit when I = 4;
exit L1 when I = 4;
-- Return Statement
return;
return 123;
return 102 downto 9;
-- Null Statement
null;
-- Process Statement
process (ALARM_TIME, CURRENT_TIME)
begin
if (ALARM_TIME = CURRENT_TIME) then
SOUND_ALARM <= '1';
else
SOUND_ALARM <= '0';
end if;
end process;
process
begin
if (ALARM_TIME = CURRENT_TIME) then
SOUND_ALARM <= '1';
else
SOUND_ALARM <= '0';
end if;
wait on ALARM_TIME, CURRENT_TIME;
end process;
WAIT_PROC: process
begin
wait until CLK'event and CLK='1';
Q1 <= D1;
end process;
SENSE_PROC: process (CLK)
begin
if CLK'event and CLK='1' then
Q2 <= D2;
end if;
end process;
-- Block Statement
CONTROL_LOGIC: block
begin
U1: CONTROLLER_A port map (CLK,X,Y,Z);
U2: CONTROLLER_A port map (CLK,A,B,C);
end block CONTROL_LOGIC;
DATA_PATH: block
begin
U3: DATAPATH_A port map (BUS_A,BUS_B,BUS_C,Z);
U4: DATAPATH_B port map (BUS_A,BUS_C,BUS_D,C);
end block DATA_PATH;
-- Generate Statement
L1: CELL port map (Top, Bottom, A(0), B(0));
L2: for I in 1 to 3 generate
L3: for J in 1 to 3 generate
L4: if I+J>4 generate
L5: CELL port map (A(I-1),B(J-1),A(I),B(J));
end generate;
end generate;
end generate;
L6: for I in 1 to 3 generate
L7: for J in 1 to 3 generate
L8: if I+J<4 generate
L9: CELL port map (A(I+1),B(J+1),A(I),B(J));
end generate;
end generate;
end generate;
L1: case verify_mode generate
when V_rtl: all_rtl | cpu_rtl =>
CPU1: entity work.cpu(rtl) port map (foo);
when V_bfm: others =>
signal bfm_sig : BIT;
begin
CPU1: entity work.cpu(bfm) port map (bar);
end V_bfm;
end generate L1;
L2: if A1: max_latency < 10 generate
signal s1 : BIT;
begin
multiplier1: parallel_multiplier port map (foo);
end A1;
else A2: generate
signal s1 : STD_LOGIC;
begin
multiplier1: sequential_multiplier port map (bar);
end A2;
end generate L2;
end;
end;
| apache-2.0 | f0878d8d0f4cc42d8d7af8f2f4b7c087 | 0.632679 | 2.582575 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_69x512_hf/simulation/fg_tb_top.vhd | 2 | 5,679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 72
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| mit | 1b54e38d60d65141d9dd4f1a7864c457 | 0.616306 | 4.175735 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_64x512/simulation/fg_tb_pkg.vhd | 1 | 11,247 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_64x512_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit | 4e3eeefd1cc3e054e922f8720ff09699 | 0.50449 | 3.929769 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_138x16_shift/example_design/fifo_138x16_shift_top_wrapper.vhd | 1 | 19,032 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_138x16_shift_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_138x16_shift_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(138-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(138-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_138x16_shift_top_wrapper;
architecture xilinx of fifo_138x16_shift_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_138x16_shift_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(138-1 DOWNTO 0);
DOUT : OUT std_logic_vector(138-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_138x16_shift_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 0ce16c593216258eedde9c503acdd672 | 0.487074 | 3.962523 | false | false | false | false |
freecores/pcounter | pdivtwo.vhdl | 1 | 979 | --
-- * pipelined synchronous pulse counter *
-- pdivtwo -- core 1-stage element (pipelined f/2 divider)
--
-- fast counter for slow-carry architectures
-- non-monotonic counting, value calculable by HDL/CPU
--
-- idea&code by Marek Peca <[email protected]> 08/2012
-- Vyzkumny a zkusebni letecky ustav, a.s. http://vzlu.cz/
-- thanks to Michael Vacek <[email protected]> for testing
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pdivtwo is
port (
clock: in std_logic;
en: in std_logic;
q, p: out std_logic
);
end pdivtwo;
architecture behavioral of pdivtwo is
signal state: std_logic := '1';
signal pipe: std_logic := '0';
signal next_state, next_pipe: std_logic;
begin
next_state <= not state when en = '1' else state;
next_pipe <= state and en;
p <= pipe;
q <= state;
process
begin
wait until clock'event and clock = '1';
state <= next_state;
pipe <= next_pipe;
end process;
end behavioral;
| lgpl-3.0 | 99146b394cd4f65ffbe9697a8e5dc78b | 0.670072 | 3.078616 | false | false | false | false |
fabianschuiki/moore | test/vhdl/type_phys.vhd | 1 | 537 | entity foo is end;
architecture bar of foo is
type TIME is range -1E18 to 1E18 units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
type DISTANCE is range 0 to 1E16 units
Å;
nm = 10 Å;
um = 1000 nm;
mm = 1000 um;
cm = 10 mm;
m = 1000 mm;
km = 1000 m;
mil = 254000 Å;
inch = 1000 mil;
ft = 12 inch;
yd = 3 ft;
fm = 6 ft;
mi = 5280 ft;
lg = 3 mi;
end units;
constant t : TIME;
begin end;
| apache-2.0 | 7ced82454d2dbca12849ac7f24500629 | 0.535581 | 2.362832 | false | false | false | false |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/mmio_if/mmio_if_inst.vhd | 2 | 3,982 | component mmio_if is
port (
clk_i_clk : in std_logic := 'X'; -- clk
hps_ddr3_mem_a : out std_logic_vector(14 downto 0); -- mem_a
hps_ddr3_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
hps_ddr3_mem_ck : out std_logic; -- mem_ck
hps_ddr3_mem_ck_n : out std_logic; -- mem_ck_n
hps_ddr3_mem_cke : out std_logic; -- mem_cke
hps_ddr3_mem_cs_n : out std_logic; -- mem_cs_n
hps_ddr3_mem_ras_n : out std_logic; -- mem_ras_n
hps_ddr3_mem_cas_n : out std_logic; -- mem_cas_n
hps_ddr3_mem_we_n : out std_logic; -- mem_we_n
hps_ddr3_mem_reset_n : out std_logic; -- mem_reset_n
hps_ddr3_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
hps_ddr3_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
hps_ddr3_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
hps_ddr3_mem_odt : out std_logic; -- mem_odt
hps_ddr3_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
hps_ddr3_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
cpc_keys_keys : out std_logic_vector(79 downto 0); -- keys
uart_tx_o : out std_logic; -- tx_o
uart_rx_i : in std_logic := 'X'; -- rx_i
uart_reset_o : out std_logic; -- reset_o
uart_clk_i_clk : in std_logic := 'X' -- clk
);
end component mmio_if;
u0 : component mmio_if
port map (
clk_i_clk => CONNECTED_TO_clk_i_clk, -- clk_i.clk
hps_ddr3_mem_a => CONNECTED_TO_hps_ddr3_mem_a, -- hps_ddr3.mem_a
hps_ddr3_mem_ba => CONNECTED_TO_hps_ddr3_mem_ba, -- .mem_ba
hps_ddr3_mem_ck => CONNECTED_TO_hps_ddr3_mem_ck, -- .mem_ck
hps_ddr3_mem_ck_n => CONNECTED_TO_hps_ddr3_mem_ck_n, -- .mem_ck_n
hps_ddr3_mem_cke => CONNECTED_TO_hps_ddr3_mem_cke, -- .mem_cke
hps_ddr3_mem_cs_n => CONNECTED_TO_hps_ddr3_mem_cs_n, -- .mem_cs_n
hps_ddr3_mem_ras_n => CONNECTED_TO_hps_ddr3_mem_ras_n, -- .mem_ras_n
hps_ddr3_mem_cas_n => CONNECTED_TO_hps_ddr3_mem_cas_n, -- .mem_cas_n
hps_ddr3_mem_we_n => CONNECTED_TO_hps_ddr3_mem_we_n, -- .mem_we_n
hps_ddr3_mem_reset_n => CONNECTED_TO_hps_ddr3_mem_reset_n, -- .mem_reset_n
hps_ddr3_mem_dq => CONNECTED_TO_hps_ddr3_mem_dq, -- .mem_dq
hps_ddr3_mem_dqs => CONNECTED_TO_hps_ddr3_mem_dqs, -- .mem_dqs
hps_ddr3_mem_dqs_n => CONNECTED_TO_hps_ddr3_mem_dqs_n, -- .mem_dqs_n
hps_ddr3_mem_odt => CONNECTED_TO_hps_ddr3_mem_odt, -- .mem_odt
hps_ddr3_mem_dm => CONNECTED_TO_hps_ddr3_mem_dm, -- .mem_dm
hps_ddr3_oct_rzqin => CONNECTED_TO_hps_ddr3_oct_rzqin, -- .oct_rzqin
cpc_keys_keys => CONNECTED_TO_cpc_keys_keys, -- cpc_keys.keys
uart_tx_o => CONNECTED_TO_uart_tx_o, -- uart.tx_o
uart_rx_i => CONNECTED_TO_uart_rx_i, -- .rx_i
uart_reset_o => CONNECTED_TO_uart_reset_o, -- .reset_o
uart_clk_i_clk => CONNECTED_TO_uart_clk_i_clk -- uart_clk_i.clk
);
| gpl-3.0 | b0db89a6621d7507b415ddc10a207bbe | 0.43546 | 2.960595 | false | false | false | false |
fabianschuiki/moore | test/vhdl/subprog_0.vhd | 1 | 1,167 | entity foo is end;
architecture bar of foo is
type BIT is ('0', '1');
signal A : BIT;
function F1 return BIT is
--variable X : BIT;
begin
wait;
wait on A;
wait for blah;
wait until false;
wait for 10 ns;
assert false;
assert false report "holy moly";
assert false severity warning;
assert false report "explosion" severity error;
report "hello";
report "hello" severity warning;
X := '0';
X := '0' when true else '1';
with 123 select X :=
'0' when 1,
'0' when 2|3,
'0' when 4 to 10,
'0' when asdf,
'1' when others;
--F1(x);
--Image(x);
if true then
wait;
elsif false then
wait;
else
wait;
end if;
case 123 is
when 1 => wait;
when 2|3 => wait;
when 4 to 10 => wait;
when asdf => wait;
when others => wait;
end case;
while true loop
wait;
end loop;
for x in 0 to 31 loop
wait;
end loop;
l0: for x in 0 to 31 loop
next;
next when false;
--next l0;
--next l0 when false;
end loop;
l1: for x in 0 to 31 loop
exit;
exit when true;
--exit l1;
--exit l1 when true;
end loop;
return;
return 1234;
null;
end;
begin end;
| apache-2.0 | dc619e860b5ac5728604ed605710b58f | 0.586975 | 2.69515 | false | false | false | false |
dugagjinll/MIPS | MIPS/Controller.vhd | 1 | 2,453 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Controller IS
PORT (
opcode : IN std_logic_vector(5 DOWNTO 0); -- instruction 31-26
regDst : OUT std_logic;
jump : OUT std_logic;
branch : OUT std_logic;
memRead : OUT std_logic;
memToRegister : OUT std_logic;
ALUop : OUT std_logic_vector(1 DOWNTO 0);
memWrite : OUT std_logic;
ALUsrc : OUT std_logic;
regWrite : OUT std_logic
);
END Controller;
ARCHITECTURE Behavioral OF Controller IS
BEGIN
PROCESS (opcode)
BEGIN
regWrite <= '0'; --Deassert for next command
CASE opcode IS
WHEN "000000" => -- and, or, add, sub, slt: 0x00
regDst <= '1';
jump <= '0';
branch <= '0';
memRead <= '0';
memToRegister <= '0';
ALUop <= "10";
memWrite <= '0';
ALUsrc <= '0';
regWrite <= '1' AFTER 10 ns;
WHEN "100011" => -- load word(lw): 0x23
regDst <= '0';
jump <= '0';
branch <= '0';
memRead <= '1';
memToRegister <= '1';
ALUop <= "00";
memWrite <= '0';
ALUsrc <= '1';
regWrite <= '1' AFTER 10 ns;
WHEN "101011" => -- store word(beq): 0x2B
regDst <= 'X'; -- don't care
jump <= '0';
branch <= '0' AFTER 2 ns;
memRead <= '0';
memToRegister <= 'X'; -- don't care
ALUop <= "00";
memWrite <= '1';
ALUsrc <= '1';
regWrite <= '0';
WHEN "000100" => -- branch equal(beq): 0x04
regDst <= 'X'; -- don't care
jump <= '0';
branch <= '1' AFTER 2 ns;
memRead <= '0';
memToRegister <= 'X'; -- don't care
ALUop <= "01";
memWrite <= '0';
ALUsrc <= '0';
regWrite <= '0';
WHEN "000010" => -- jump(j): 0x02
regDst <= 'X';
jump <= '1';
branch <= '0';
memRead <= '0';
memToRegister <= 'X';
ALUop <= "00";
memWrite <= '0';
ALUsrc <= '0';
regWrite <= '0';
WHEN OTHERS => NULL; --implement other commands down here
regDst <= '0';
jump <= '0';
branch <= '0';
memRead <= '0';
memToRegister <= '0';
ALUop <= "00";
memWrite <= '0';
ALUsrc <= '0';
regWrite <= '0';
END CASE;
END PROCESS;
END Behavioral; | mit | b6769258a4640b5b170f4a18cab9d359 | 0.445985 | 3.275033 | false | false | false | false |
mzakharo/usb-de2-fpga | src/devreq.vhd | 1 | 11,651 | -- devreq.vhd
-- -----------------------------------------------------------------------
-- Copyright © 2012 Mikhail Zakharov
-- -----------------------------------------------------------------------
--
-- This file is part of "ISP1362 VHDL interface for DE2"
--
-- "ISP1362 VHDL interface for DE2" is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3
--
-- "ISP1362 VHDL interface for DE2" is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with "ISP1362 VHDL interface for DE2". If not, see <http://www.gnu.org/licenses/>.
-- -----------------------------------------------------------------------
-- USB 2.0 Device Request handler
-- -----------------------------------------------------------------------
-- Version : 1.0
-- Date : Sept 2012
-- Author : Mikhail Zakharov
-- Web : http://ca.linkedin.com/in/mzakharo
-- Contact : [email protected]
-- -----------------------------------------------------------------------
-- FUNCTION :
-- 1. Handles control endpoint requests sent by the USB Host
-- 2. Sends USB Descriptors, defined in usb_inc.vhd to the host
-- 4. Can be used to implement Vendor Specific Device Requests
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.usb_inc.all;
use work.isp_hal.all;
package devreq_inc is -- component declaration package
type devreq_in_t is record
hal : drv_iface_out_t;
req : device_request_t;
req_rdy : bit;
end record;
type devreq_out_t is record
hal : drv_iface_in_t;
done : bit;
configured : bit;
end record;
component devreq is
port(
clk : in std_logic;
reset : in std_logic;
d : in devreq_in_t;
q : out devreq_out_t);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.devreq_inc.all;
use work.usb_inc.all;
use work.isp_hal.all;
use work.isp_inc.all;
entity devreq is
port(
clk : in std_logic;
reset : in std_logic;
d : in devreq_in_t;
q : out devreq_out_t);
end devreq;
architecture handler of devreq is
type not_reset_t is record
hal : drv_iface_in_t;
tx_greater : signed(8 downto 0);
tx_len : std_logic_vector(7 downto 0);
descr_len : unsigned(7 downto 0);
cnt : unsigned(4 downto 0);
inline : bit_vector(2 downto 0);
tmpcnt : unsigned(4 downto 0);
neq : bit;
end record;
type state_t is (idle , decode, dev_descr, conf_descr, zero, stall, set_addr, wait_ready);
constant dev_len : integer := byte_deviceDescriptor(CRD_devDesc)'length; --bits
constant conf_len : integer := CRD_Full_Desc'length; --bits
--length of functions
constant fsend_ep_len : integer := 2;
constant fdev_len : integer := dev_len / 2 / 8;
constant fconf_len : integer := conf_len /2 /8;
constant fstall_len : integer := 2;
constant fvalid_len : integer := 1;
constant fset_addr_len : integer := 2;
--total number of functions
constant func_states : integer := fsend_ep_len + fdev_len + fconf_len + fstall_len + fvalid_len + fset_addr_len;
type reg_t is record
nr : not_reset_t;
state : state_t;
shift : bit_vector(func_states downto 0);
configured : bit;
end record;
signal r, rin : reg_t;
function swap( constant word : in std_logic_vector(0 to 15) ) return std_logic_vector is
begin
return( word(8 to 15) & word(0 to 7));
end function swap;
begin --architecture
comb : process(r,d)
variable v : reg_t;
constant fsend_ep_start : integer := 0;
alias r_fsend_ep : bit_vector(fsend_ep_len -1 downto 0) is r.shift(fsend_ep_len -1 + fsend_ep_start downto fsend_ep_start);
alias v_fsend_ep : bit_vector(fsend_ep_len- 1 downto 0) is v.shift(fsend_ep_len -1 + fsend_ep_start downto fsend_ep_start);
constant fdev_start : integer := fsend_ep_len + fsend_ep_start;
alias r_fdev_descr : bit_vector(fdev_len-1 downto 0) is r.shift(fdev_len -1 + fdev_start downto fdev_start);
alias v_fdev_descr : bit_vector(fdev_len-1 downto 0) is v.shift(fdev_len -1 + fdev_start downto fdev_start);
constant fconf_start : integer := fdev_len + fdev_start;
alias r_fconf_descr : bit_vector(fconf_len-1 downto 0) is r.shift(fconf_len -1 + fconf_start downto fconf_start);
alias v_fconf_descr : bit_vector(fconf_len-1 downto 0) is v.shift(fconf_len -1 + fconf_start downto fconf_start);
constant fstall_start : integer := fconf_len + fconf_start;
alias r_fstall : bit_vector(fstall_len-1 downto 0) is r.shift(fstall_len -1 + fstall_start downto fstall_start);
alias v_fstall : bit_vector(fstall_len-1 downto 0) is v.shift(fstall_len -1 + fstall_start downto fstall_start);
constant fvalid_start : integer := fstall_len + fstall_start;
constant fset_addr_start : integer := fvalid_len + fvalid_start;
alias r_fset_addr : bit_vector(fset_addr_len-1 downto 0) is r.shift(fset_addr_len -1 + fset_addr_start downto fset_addr_start);
alias v_fset_addr : bit_vector(fset_addr_len-1 downto 0) is v.shift(fset_addr_len -1 + fset_addr_start downto fset_addr_start);
type func_data_t is array(func_states - 1 downto 0) of data_t;
type func_cmd_t is array(func_states - 1 downto 0) of cmd_t;
variable datas : func_data_t;
variable cmds : func_cmd_t;
begin
--parameters
v := r;
case r.state is
when idle =>
if (d.req_rdy = '1') then
v.state := decode ;
end if;
v.configured := '0';
when decode =>
--INFO: not checking bRequestType - assuming all requests are USB_STANDARD request types
if (d.req.bRequest(3 downto 0) = GET_DESCRIPTOR and d.req.wValue(11 downto 8) = desc_DEVICE) then
v.state := dev_descr;
elsif (d.req.bRequest(3 downto 0) = GET_DESCRIPTOR and d.req.wValue(11 downto 8) = desc_CONFIGURATION) then
v.state := conf_descr;
elsif (d.req.bRequest(3 downto 0) = SET_CONFIGURATION) then
v.state := zero;
v.configured := '1';
elsif (d.req.bRequest(3 downto 0) = SET_ADDRESS) then
v.state := set_addr;
else
v.state := stall;
end if;
v.nr.inline := (others => '0');
v.nr.descr_len :=to_unsigned(0, 8);
when dev_descr => v.state := wait_ready;
v_fsend_ep(0) := '1';
v.nr.descr_len :=to_unsigned((dev_len / 8), 8);
v.nr.inline(0) := '1';
when conf_descr => v.state := wait_ready;
v.nr.descr_len :=to_unsigned((conf_len / 8), 8);
v_fsend_ep(0) := '1';
v.nr.inline(1) := '1';
when zero => v.state := wait_ready;
v_fsend_ep(0) := '1';
v.nr.inline(2) := '1';
when stall => v.state := wait_ready;
v_fstall(0) := '1';
when set_addr => v.state := wait_ready;
v_fset_addr(0) := '1';
v.nr.inline(2) := '1';
when wait_ready =>
if r.shift(func_states) = '1' then
v.state := idle;
end if;
end case;
q.done <= r.shift(func_states);
q.configured <= r.configured and r.shift(func_states);
--output length to send for desc_DEVICE
v.nr.tx_greater := ('0' & signed(d.req.wLength(7 downto 0)) - ('0' & signed(r.nr.descr_len)) ); --INFO: max length supported : 0xFF
if (r.nr.tx_greater(r.nr.tx_greater'high) = '1') then --wLength < sizeof(desc_DEVICE)
v.nr.tx_len := d.req.wLength( 7 downto 1) & '0'; -- force even transactions - just to make the code simpler for now.
else
v.nr.tx_len := std_logic_vector(r.nr.descr_len);
end if;
if (unsigned(to_stdlogicvector(r_fsend_ep)) /= 0) then
v.nr.tmpcnt := unsigned(r.nr.tx_len(5 downto 1)); --divide by 2
else
v.nr.tmpcnt := r.nr.cnt;
end if;
if (r.nr.cnt /= 0) then
v.nr.neq := '1';
else
v.nr.neq := '0';
end if;
--function shift register
if(d.hal.rdy = '1') then
v_fsend_ep := (r_fsend_ep sll 1);
v_fsend_ep(0) := v_fsend_ep(0) or r_fset_addr(r_fset_addr'high);
--inline functions
v_fdev_descr(v_fdev_descr'low) := r_fsend_ep(r_fsend_ep'high) and r.nr.inline(0);
v_fconf_descr(v_fconf_descr'low) := r_fsend_ep(r_fsend_ep'high) and r.nr.inline(1);
v.nr.cnt := r.nr.tmpcnt - 1; -- descriptor words left to send
for i in v_fdev_descr'high downto 1 loop
v_fdev_descr(i) := r_fdev_descr(i - 1) and r.nr.neq;
end loop;
for i in v_fconf_descr'high downto 1 loop
v_fconf_descr(i) := r_fconf_descr(i - 1) and r.nr.neq;
end loop;
v_fstall := (r_fstall sll 1);
v_fset_addr := (r_fset_addr sll 1);
v.shift(fvalid_start) := ((r.nr.inline(0) or r.nr.inline(1)) and not(v.nr.neq))
or (r_fsend_ep(r_fsend_ep'high) and r.nr.inline(2));
end if;
if(d.hal.rdy = '1') then
v.shift(func_states) := r.shift(fvalid_start) or r_fstall(r_fstall'high);
else
v.shift(func_states) := '0';
end if;
--initialize temporary outputs
for i in 0 to (func_states - 1) loop
cmds(i) := (others => '0');
datas(i) := (others => '0');
end loop;
--function code start
if (r.shift(fsend_ep_start) = '1') then
cmds(fsend_ep_start) := otg_wr_cmd;
datas(fsend_ep_start) := Wr_Buffer & EPINDEX4EP0_CONTROL_IN;
end if;
if (r.shift(fsend_ep_start + 1) = '1') then
cmds(fsend_ep_start + 1) := otg_wr;
datas(fsend_ep_start+ 1) := x"00" & r.nr.tx_len;
end if;
for i in 0 to r_fdev_descr'high loop
if (r.shift(fdev_start + i) = '1' )then
cmds(fdev_start + i) := otg_wr;
datas(fdev_start + i) := swap(byte_deviceDescriptor(CRD_devDesc)( i*16 to (i+1)*16 - 1)) ;
end if;
end loop;
for i in 0 to r_fconf_descr'high loop
if (r.shift(fconf_start + i) = '1' )then
cmds(fconf_start + i) := otg_wr;
datas(fconf_start + i) := swap(CRD_Full_Desc( i*16 to (i+1)*16 - 1));
end if;
end loop;
if (r.shift(fstall_start) = '1') then
cmds(fstall_start) := otg_wr_cmd;
datas(fstall_start) := EPSTS_STALL & EPINDEX4EP0_CONTROL_OUT;
end if;
if (r.shift(fstall_start + 1) = '1') then
cmds(fstall_start + 1) := otg_wr_cmd;
datas(fstall_start+ 1) := EPSTS_STALL & EPINDEX4EP0_CONTROL_IN;
end if;
if (r.shift(fvalid_start) = '1') then
cmds(fstall_start + 1) := otg_wr_cmd;
datas(fstall_start+ 1) := Validate & EPINDEX4EP0_CONTROL_IN;
end if;
if (r.shift(fset_addr_start) = '1') then
cmds(fset_addr_start) := otg_wr_cmd;
datas(fset_addr_start) := Wr_DcAddress;
end if;
if (r.shift(fset_addr_start + 1) = '1') then
cmds(fset_addr_start + 1) := otg_wr;
datas(fset_addr_start + 1) := x"0080" or d.req.wValue;
end if;
--function code end
--assign temporary outputs to real outputs
v.nr.hal.data := (others => '0');
v.nr.hal.cmd := (others => '0');
for i in 0 to (func_states - 1) loop
v.nr.hal.cmd := v.nr.hal.cmd or cmds(i);
v.nr.hal.data := v.nr.hal.data or datas(i);
end loop;
--and finally
q.hal.cmd <= r.nr.hal.cmd;
q.hal.data <= r.nr.hal.data;
rin <= v; --return (v);
end process;
seq : process(reset, clk)
begin
if (reset= '1') then
r.state <= idle;
r.shift <= (others => '0');
r.configured <= '0';
elsif rising_edge(clk) then
r.shift <= rin.shift;
r.state <= rin.state;
r.configured <= rin.configured;
end if;
end process;
seq_nrst : process
begin
wait until rising_edge(clk);
r.nr <= rin.nr;
end process;
end architecture;
| gpl-3.0 | fd75e2fcf8876b897cc3ae3a7777819d | 0.602523 | 2.833414 | false | false | false | false |
mzakharo/usb-de2-fpga | src/hal.vhd | 1 | 6,838 | -- hal.vhd
-- -----------------------------------------------------------------------
-- Copyright © 2012 Mikhail Zakharov
-- -----------------------------------------------------------------------
--
-- This file is part of "ISP1362 VHDL interface for DE2"
--
-- "ISP1362 VHDL interface for DE2" is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3
--
-- "ISP1362 VHDL interface for DE2" is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with "ISP1362 VHDL interface for DE2". If not, see <http://www.gnu.org/licenses/>.
-- -----------------------------------------------------------------------
-- ISP1362 low-level interface
-- -----------------------------------------------------------------------
-- Version : 1.0
-- Date : Sept 2012
-- Author : Mikhail Zakharov
-- Web : http://ca.linkedin.com/in/mzakharo
-- Contact : [email protected]
-- -----------------------------------------------------------------------
-- FUNCTION :
-- 1. Implements ISP1362 I/O Timing
-- 2. More info: ISP1362 Datasheet, Chapter 19, Sec 1.2
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package isp_hal is -- component declaration package
subtype cmd_t is bit_vector(1 downto 0);
subtype data_t is std_logic_vector(15 downto 0);
constant dont_care_data_t : data_t := (others => '-');
constant otg_idle : cmd_t := "00";
constant otg_rd : cmd_t := "01";
constant otg_wr : cmd_t := "10";
constant otg_wr_cmd : cmd_t := "11";
type drv_iface_in_t is record
cmd : cmd_t;
data : data_t;
end record;
type isp_hal_in_t is record
drv : drv_iface_in_t;
slowclk_en : bit;
end record;
type drv_iface_out_t is record
data : data_t;
rdy: bit;
end record;
type isp_hal_out_t is record
drv : drv_iface_out_t;
rst_n : std_logic; --ISP1362 Reset pin
addr : std_logic_vector(1 downto 0); --ISP1362 Address 2 Bits[peripheral,command]
cs_n : std_logic; --ISP1362 Chip Select
rd_n : std_logic; --ISP1362 Write
wr_n : std_logic; --ISP1362 Read
-- not used
dack0_n : std_logic; --ISP1362 DMA Acknowledge 1
dack1_n : std_logic; --ISP1362 DMA Acknowledge 2
end record;
component hal is
GENERIC(
delay :INTEGER := 275 --for testbench
);
port(
clk : in std_logic;
reset : in std_logic;
otg_data : inout std_logic_vector(15 downto 0);
d : in isp_hal_in_t;
q : out isp_hal_out_t);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.isp_hal.all;
entity hal is
GENERIC(
delay :INTEGER := 275
);
port(
clk : in std_logic;
reset : in std_logic;
otg_data : inout std_logic_vector(15 downto 0);
d : in isp_hal_in_t;
q : out isp_hal_out_t );
end hal;
architecture handler of hal is
type iface_t is record
wr : bit;
rd : bit;
data_out: data_t;
rdy : bit;
end record;
type state_t is (reset_st,idle_st,write_st, writeA_st, writeB_st, idleA_st, idleB_st, read_st, readA_st);
type reg_t is record
reset : std_logic;
go : bit;
count : unsigned(8 downto 0);
state : state_t;
iface : iface_t;
rdy_out : bit;
end record;
signal r, rin : reg_t;
begin --architecture
--ISP1362 config
q.dack0_n <= '1'; --must be set (datahseet)
q.dack1_n <= '1'; --must be set (datasheet)
q.addr(1) <= '1'; --always talking to the peripheral
comb : process(r,d, otg_data)
variable v : reg_t;
begin
--parameters
v := r;
--resets the ISP1362 by driving otg_reset low for 11us
--assumes that slow clk enable is toggling at a rate of 25MHz
if (r.count = delay ) then
v.reset := '1';
end if;
--POR pulse lasts 800 ns
if (r.count = delay + 20) then
v.go := '1';
end if;
v.count := r.count + 1;
--end reset
v.iface.rdy := '0';
--non registered outputs
q.cs_n <= '1';
q.rd_n <= '1';
q.wr_n <= '1';
--handle bidir port
otg_data <= (others => 'Z'); --to device
--I/O with the ISP1362 FSM
case r.state is
when reset_st =>
if (r.go = '1') then
v.state := idle_st;
end if;
when idle_st => -- 240 ns cmd / 200 ns data
if (d.drv.cmd(0) = '1') then
v.state := read_st;
end if;
if (d.drv.cmd(1) = '1' ) then
v.state := write_st;
end if;
when write_st => --this will take 40 ns
q.wr_n <= '0';
q.cs_n <= '0';
otg_data <= d.drv.data;
v.state := writeA_st;
when writeA_st => -- 80 ns
-- data hold time after wr high (3 ns min)
otg_data <= d.drv.data;
v.iface.rdy := '1'; --signal early so that new data can be setup
if (d.drv.cmd(0) = '1') then
--In the command to data phase, the minimum value of the write command
--to the read data or write data cycle time must be 205 ns (src Datasheet)
v.state := writeB_st;
else
v.state := idleA_st;
end if;
when writeB_st => v.state := idleA_st; -- 120 ns cmd / 80 ns data
when idleA_st => v.state := idleB_st; -- 160 ns cmd / 120 ns data
when idleB_st => v.state := idle_st; -- 200 ns cmd / 160 ns data
when read_st => --read will take 40 ns
q.rd_n <= '0';
q.cs_n <= '0';
v.state := readA_st;
v.iface.data_out := otg_data; --to interface
when readA_st => -- 80 ns
v.state := idleA_st;
v.iface.rdy := '1';
when others => v.state := reset_st;
end case;
v.rdy_out := v.iface.rdy and not(r.iface.rdy) ; --generate pulse of one cycle
--outputs
q.drv.rdy <= r.rdy_out;
q.drv.data <= r.iface.data_out;
q.rst_n <= r.reset;
q.addr(0) <= to_stdulogic(d.drv.cmd(0) and d.drv.cmd(1));
rin <= v; --return (v);
end process;
seq : process(reset, clk)
begin
if (reset= '1') then
r.reset <= '0';
r.go <= '0';
r.count <= (others => '0');
r.state <= reset_st;
r.rdy_out <= '0';
elsif rising_edge(clk) then
r.reset <= rin.reset;
r.go <= rin.go;
r.rdy_out <= rin.rdy_out;
if (d.slowclk_en = '1') then --slow clock
r.count <= rin.count;
r.state <= rin.state;
end if;
end if;
end process;
--everything in iface does not need to be reset
--since it is driven by the logic/FSM
seq_nrst : process
begin
wait until rising_edge(clk);
r.iface <= rin.iface;
end process;
end architecture;
| gpl-3.0 | bbf4ef9aa8ea384f3a02d2d93bf2d0ab | 0.555279 | 2.885232 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_64x512_hf/example_design/fifo_64x512_hf_top_wrapper.vhd | 1 | 19,220 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_64x512_hf_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_64x512_hf_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(64-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(64-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_64x512_hf_top_wrapper;
architecture xilinx of fifo_64x512_hf_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_64x512_hf_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_64x512_hf_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | f2d7e298605ae527fe24d20e1d482bbf | 0.484807 | 3.966976 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_96x512/simulation/fg_tb_synth.vhd | 1 | 10,346 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 96,
C_DOUT_WIDTH => 96,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 96,
C_DIN_WIDTH => 96,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 96,
C_DIN_WIDTH => 96,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_96x512_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit | e7aa82d802bf30c29642163ef799c551 | 0.460275 | 4.108817 | false | false | false | false |
capitanov/MinesweeperFPGA | src/game_cores/ctrl_comp_pkg.vhd | 1 | 4,162 | --------------------------------------------------------------------------------
--
-- Title : ctrl_comp_pkg.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Components for display
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.ctrl_types_pkg.array8x8;
package ctrl_comp_pkg is
component cl_square is
generic(
constant yend : std_logic_vector(4 downto 0):="11000";
constant ystart : std_logic_vector(4 downto 0):="10000";
constant xend : std_logic_vector(6 downto 0):="0011000";
constant xstart : std_logic_vector(6 downto 0):="0010000"
);
port(
-- system signals:
clk : in std_logic;
reset : in std_logic;
-- vga XoY coordinates:
show_disp : in array8x8;
display : in std_logic;
x_char : in std_logic_vector(9 downto 0); -- X line: 0:79
y_char : in std_logic_vector(8 downto 0); -- Y line: 0:29
-- out color scheme:
rgb : out std_logic_vector(2 downto 0)
);
end component;
component cl_borders is
generic(
constant yend : std_logic_vector(4 downto 0):="11000";
constant ystart : std_logic_vector(4 downto 0):="10000";
constant xend : std_logic_vector(6 downto 0):="0011000";
constant xstart : std_logic_vector(6 downto 0):="0010000"
);
port(
-- system signals:
clk : in std_logic;
reset : in std_logic;
-- vga XoY coordinates:
display : in std_logic;
x_char : in std_logic_vector(9 downto 0); -- X line: 0:79
y_char : in std_logic_vector(8 downto 0); -- Y line: 0:29
-- out color scheme:
rgb : out std_logic_vector(2 downto 0)
);
end component;
component cl_mines is
generic(
constant yend : std_logic_vector(4 downto 0):="11000";
constant ystart : std_logic_vector(4 downto 0):="10000";
constant xend : std_logic_vector(6 downto 0):="0011000";
constant xstart : std_logic_vector(6 downto 0):="0010000"
);
port(
-- system signals:
clk : in std_logic;
reset : in std_logic;
-- vga XoY coordinates:
show_disp : in array8x8;
-- vga XoY coordinates:
addr_rnd : in std_logic_vector(4 downto 0);
display : in std_logic;
x_char : in std_logic_vector(9 downto 0); -- X line: 0:79
y_char : in std_logic_vector(8 downto 0); -- Y line: 0:29
-- out color scheme:
data_out : out std_logic_vector(7 downto 0);
rgb : out std_logic_vector(2 downto 0)
);
end component;
component cl_text is
generic(
constant yend : std_logic_vector(4 downto 0):="11000";
constant ystart : std_logic_vector(4 downto 0):="10000";
constant xend : std_logic_vector(6 downto 0):="0011000";
constant xstart : std_logic_vector(6 downto 0):="0010000"
);
port(
-- system signals:
clk : in std_logic;
reset : in std_logic;
-- control signals:
addr_rnd : in std_logic_vector(4 downto 0);
display : in std_logic;
cntgames : in std_logic;
win : in std_logic;
lose : in std_logic;
game : in std_logic;
flash : in std_logic_vector(2 downto 0);
-- vga XoY:
x_char : in std_logic_vector(9 downto 0);
y_char : in std_logic_vector(8 downto 0);
-- out color scheme:
rgb : out std_logic_vector(2 downto 0)
);
end component;
component cl_check is
generic(
constant yend : std_logic_vector(4 downto 0):="11000";
constant ystart : std_logic_vector(4 downto 0):="10000";
constant xend : std_logic_vector(6 downto 0):="0011000";
constant xstart : std_logic_vector(6 downto 0):="0010000"
);
port(
-- system signals:
clk : in std_logic;
reset : in std_logic;
-- vga XoY coordinates:
cnt_yy : in std_logic_vector(2 downto 0);
cnt_xx : in std_logic_vector(2 downto 0);
--data_hide : in std_logic;
display : in std_logic;
x_char : in std_logic_vector(9 downto 0); -- X line: 0:79
y_char : in std_logic_vector(8 downto 0); -- Y line: 0:29
-- out color scheme:
rgb : out std_logic_vector(2 downto 0)
);
end component;
end ctrl_comp_pkg; | mit | b70299690435db89893cfac872cf7d81 | 0.593224 | 2.758118 | false | false | false | false |
capitanov/MinesweeperFPGA | src/game_cores/cl_borders.vhd | 1 | 9,675 | --------------------------------------------------------------------------------
--
-- Title : cl_borders.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game block for borders 8x8
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity cl_borders is
generic(
constant yend : std_logic_vector(4 downto 0):="11000";
constant ystart : std_logic_vector(4 downto 0):="10000";
constant xend : std_logic_vector(6 downto 0):="0011000";
constant xstart : std_logic_vector(6 downto 0):="0010000"
);
port(
-- system signals:
clk : in std_logic;
reset : in std_logic;
-- vga XoY coordinates:
display : in std_logic;
x_char : in std_logic_vector(9 downto 0); -- X line: 0:79
y_char : in std_logic_vector(8 downto 0); -- Y line: 0:29
-- out color scheme:
rgb : out std_logic_vector(2 downto 0)
);
end cl_borders;
architecture cl_borders of cl_borders is
signal data_rom : std_logic_vector(7 downto 0);
signal x_in : std_logic_vector(6 downto 0);
signal y_in : std_logic_vector(4 downto 0);
signal data : std_logic;
signal data_x1 : std_logic;
signal data_x2 : std_logic;
signal data_y1 : std_logic;
signal data_y2 : std_logic;
signal data_ul : std_logic;
signal data_ur : std_logic;
signal data_dl : std_logic;
signal data_dr : std_logic;
signal x_rev : std_logic_vector(2 downto 0);
signal x_del : std_logic_vector(2 downto 0);
--signal x_z : std_logic_vector(2 downto 0);
signal y_charz : std_logic_vector(3 downto 0);
constant color : std_logic_vector(2 downto 0):="001";
begin
y_charz <= y_char(3 downto 0) when rising_edge(clk);
g_rev: for ii in 0 to 2 generate
begin
x_rev(ii) <= not x_char(ii) when rising_edge(clk);
end generate;
x_del <= x_rev when rising_edge(clk);
--x_z <= x_del when rising_edge(clk);
x_in <= x_char(9 downto 3);
y_in <= y_char(8 downto 4);
pr_select3: process(clk, reset) is
begin
if reset = '0' then
data_x1 <= '0';
data_x2 <= '0';
data_y1 <= '0';
data_y2 <= '0';
data_ul <= '0';
data_ur <= '0';
data_dl <= '0';
data_dr <= '0';
elsif rising_edge(clk) then
if display = '0' then
data_x1 <= '0';
data_x2 <= '0';
data_y1 <= '0';
data_y2 <= '0';
data_ul <= '0';
data_ur <= '0';
data_dl <= '0';
data_dr <= '0';
else
if (yend = y_in) then
if (xstart-1 = x_in) then
data_ul <= '1';
else
data_ul <= '0';
end if;
else
data_ul <= '0';
end if;
if (yend = y_in) then
if (xend = x_in) then
data_ur <= '1';
else
data_ur <= '0';
end if;
else
data_ur <= '0';
end if;
if (ystart-1 = y_in) then
if (xstart-1 = x_in) then
data_dl <= '1';
else
data_dl <= '0';
end if;
else
data_dl <= '0';
end if;
if (ystart-1 = y_in) then
if (xend = x_in) then
data_dr <= '1';
else
data_dr <= '0';
end if;
else
data_dr <= '0';
end if;
if (yend = y_in) then
if (xstart <= x_in) and (x_in < xend) then
data_x1 <= '1';
else
data_x1 <= '0';
end if;
else
data_x1 <= '0';
end if;
if ((ystart-1) = y_in) then
if (xstart <= x_in) and (x_in < xend) then
data_x2 <= '1';
else
data_x2 <= '0';
end if;
else
data_x2 <= '0';
end if;
if (xstart-1 = x_in) then
if (ystart <= y_in) and (y_in < yend) then
data_y1 <= '1';
else
data_y1 <= '0';
end if;
else
data_y1 <= '0';
end if;
if (xend = x_in) then
if (ystart <= y_in) and (y_in < yend) then
data_y2 <= '1';
else
data_y2 <= '0';
end if;
else
data_y2 <= '0';
end if;
end if;
end if;
end process;
pr_new_box: process(clk, reset)
begin
if reset = '0' then
data_rom <= x"00";
elsif rising_edge(clk) then
if data_x1 = '1' then
case y_charz(3 downto 0) is
when x"0" => data_rom <= x"00";
when x"1" => data_rom <= x"00";
when x"2" => data_rom <= x"FF";
when x"3" => data_rom <= x"FF";
when x"4" => data_rom <= x"00";
when x"5" => data_rom <= x"00";
when x"6" => data_rom <= x"00";
when x"7" => data_rom <= x"00";
when x"8" => data_rom <= x"00";
when x"9" => data_rom <= x"00";
when x"A" => data_rom <= x"00";
when x"B" => data_rom <= x"00";
when x"C" => data_rom <= x"00";
when x"D" => data_rom <= x"00";
when x"E" => data_rom <= x"00";
when others => data_rom <= x"00";
end case;
elsif data_x2 = '1' then
case y_charz(3 downto 0) is
when x"0" => data_rom <= x"00";
when x"1" => data_rom <= x"00";
when x"2" => data_rom <= x"00";
when x"3" => data_rom <= x"00";
when x"4" => data_rom <= x"00";
when x"5" => data_rom <= x"00";
when x"6" => data_rom <= x"00";
when x"7" => data_rom <= x"00";
when x"8" => data_rom <= x"00";
when x"9" => data_rom <= x"00";
when x"A" => data_rom <= x"00";
when x"B" => data_rom <= x"FF";
when x"C" => data_rom <= x"FF";
when x"D" => data_rom <= x"00";
when x"E" => data_rom <= x"00";
when others => data_rom <= x"00";
end case;
elsif data_y1 = '1' then
case y_charz(3 downto 0) is
when x"0" => data_rom <= x"0C";
when x"1" => data_rom <= x"0C";
when x"2" => data_rom <= x"0C";
when x"3" => data_rom <= x"0C";
when x"4" => data_rom <= x"0C";
when x"5" => data_rom <= x"0C";
when x"6" => data_rom <= x"0C";
when x"7" => data_rom <= x"0C";
when x"8" => data_rom <= x"0C";
when x"9" => data_rom <= x"0C";
when x"A" => data_rom <= x"0C";
when x"B" => data_rom <= x"0C";
when x"C" => data_rom <= x"0C";
when x"D" => data_rom <= x"0C";
when x"E" => data_rom <= x"0C";
when others => data_rom <= x"0C";
end case;
elsif data_y2 = '1' then
case y_charz(3 downto 0) is
when x"0" => data_rom <= x"18";
when x"1" => data_rom <= x"18";
when x"2" => data_rom <= x"18";
when x"3" => data_rom <= x"18";
when x"4" => data_rom <= x"18";
when x"5" => data_rom <= x"18";
when x"6" => data_rom <= x"18";
when x"7" => data_rom <= x"18";
when x"8" => data_rom <= x"18";
when x"9" => data_rom <= x"18";
when x"A" => data_rom <= x"18";
when x"B" => data_rom <= x"18";
when x"C" => data_rom <= x"18";
when x"D" => data_rom <= x"18";
when x"E" => data_rom <= x"18";
when others => data_rom <= x"18";
end case;
elsif data_ur = '1' then
case y_charz(3 downto 0) is
when x"0" => data_rom <= x"18";
when x"1" => data_rom <= x"18";
when x"2" => data_rom <= x"F8";
when x"3" => data_rom <= x"F8";
when x"4" => data_rom <= x"00";
when x"5" => data_rom <= x"00";
when x"6" => data_rom <= x"00";
when x"7" => data_rom <= x"00";
when x"8" => data_rom <= x"00";
when x"9" => data_rom <= x"00";
when x"A" => data_rom <= x"00";
when x"B" => data_rom <= x"00";
when x"C" => data_rom <= x"00";
when x"D" => data_rom <= x"00";
when x"E" => data_rom <= x"00";
when others => data_rom <= x"00";
end case;
elsif data_ul = '1' then
case y_charz(3 downto 0) is
when x"0" => data_rom <= x"0C";
when x"1" => data_rom <= x"0C";
when x"2" => data_rom <= x"0F";
when x"3" => data_rom <= x"0F";
when x"4" => data_rom <= x"00";
when x"5" => data_rom <= x"00";
when x"6" => data_rom <= x"00";
when x"7" => data_rom <= x"00";
when x"8" => data_rom <= x"00";
when x"9" => data_rom <= x"00";
when x"A" => data_rom <= x"00";
when x"B" => data_rom <= x"00";
when x"C" => data_rom <= x"00";
when x"D" => data_rom <= x"00";
when x"E" => data_rom <= x"00";
when others => data_rom <= x"00";
end case;
elsif data_dr = '1' then
case y_charz(3 downto 0) is
when x"0" => data_rom <= x"00";
when x"1" => data_rom <= x"00";
when x"2" => data_rom <= x"00";
when x"3" => data_rom <= x"00";
when x"4" => data_rom <= x"00";
when x"5" => data_rom <= x"00";
when x"6" => data_rom <= x"00";
when x"7" => data_rom <= x"00";
when x"8" => data_rom <= x"00";
when x"9" => data_rom <= x"00";
when x"A" => data_rom <= x"00";
when x"B" => data_rom <= x"F8";
when x"C" => data_rom <= x"F8";
when x"D" => data_rom <= x"18";
when x"E" => data_rom <= x"18";
when others => data_rom <= x"18";
end case;
elsif data_dl = '1' then
case y_charz(3 downto 0) is
when x"0" => data_rom <= x"00";
when x"1" => data_rom <= x"00";
when x"2" => data_rom <= x"00";
when x"3" => data_rom <= x"00";
when x"4" => data_rom <= x"00";
when x"5" => data_rom <= x"00";
when x"6" => data_rom <= x"00";
when x"7" => data_rom <= x"00";
when x"8" => data_rom <= x"00";
when x"9" => data_rom <= x"00";
when x"A" => data_rom <= x"00";
when x"B" => data_rom <= x"0F";
when x"C" => data_rom <= x"0F";
when x"D" => data_rom <= x"0C";
when x"E" => data_rom <= x"0C";
when others => data_rom <= x"0C";
end case;
else
data_rom <= x"00";
end if;
end if;
end process;
g_rgb: for ii in 0 to 2 generate
begin
rgb(ii) <= data and color(ii);
end generate;
pr_sw_sel: process(clk, reset) is
begin
if reset = '0' then
data <= '0';
elsif rising_edge(clk) then
data <= data_rom(to_integer(unsigned(x_del)));
end if;
end process;
end cl_borders; | mit | 1e474800db9d21d49ffbfee4fd1859fe | 0.490956 | 2.353442 | false | false | false | false |
Wynjones1/VHDL-Tests | simu/test.vhd | 1 | 1,034 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity test is
end test;
architecture rtl of test is
component top is
port( clk : in std_logic;
reset : in std_logic;
vs : out std_logic;
hs : out std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(1 downto 0));
end component;
signal red : std_logic_vector(2 downto 0);
signal green : std_logic_vector(2 downto 0);
signal blue : std_logic_vector(1 downto 0);
signal HS : std_logic;
signal VS : std_logic;
signal clk : std_logic;
signal s_reset : std_logic;
begin
top0 : top port map(clk => clk,
reset => s_reset,
red => red,
blue => blue,
green => green,
HS => HS,
VS => VS);
process
begin
s_reset <= '1';
wait for 20 ns;
s_reset <= '0';
wait;
end process;
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
end rtl;
| mit | 632bbf3a93f9fd58908ba4ee09e22930 | 0.588008 | 2.825137 | false | true | false | false |
kevintownsend/R3 | coregen/fifo_69x512/example_design/fifo_69x512_top_wrapper.vhd | 1 | 18,992 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_69x512_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_69x512_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(69-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(69-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_69x512_top_wrapper;
architecture xilinx of fifo_69x512_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_69x512_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(69-1 DOWNTO 0);
DOUT : OUT std_logic_vector(69-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_69x512_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | f7df49632e8e68548b3b8d56352a0535 | 0.48631 | 3.964099 | false | false | false | false |
fabianschuiki/moore | test/vhdl/use_with_generic_pkgs.vhd | 1 | 1,222 | package gen1_pkg is
generic (type element_type);
type ptr is access element_type;
end;
package gen2_pkg is
generic (value : integer);
constant konst : integer := value;
end;
package comb_pkg is
generic (
type element_type;
value : integer
);
package p1 is new gen1_pkg generic map (element_type => element_type);
package p2 is new gen2_pkg generic map (value => value);
end;
package root_pkg is
type foo is access integer;
constant bar : integer := 42;
package inst1_pkg is new gen1_pkg generic map (element_type => string);
package inst2_pkg is new gen2_pkg generic map (value => 42);
end;
use work.root_pkg.foo, work.root_pkg.bar;
entity e1 is
type out_foo is access foo;
constant out_bar : integer := bar;
end;
use work.root_pkg.inst1_pkg.ptr, work.root_pkg.inst2_pkg.konst;
entity e2 is
type out_ptr is access ptr;
constant out_konst : integer := konst;
end;
use work.all;
entity e3 is
package p1a is new gen1_pkg generic map (element_type => integer);
package p1b is new gen1_pkg generic map (element_type => string);
package p2a is new gen2_pkg generic map (value => 42);
package p2b is new gen2_pkg generic map (value => 99);
end;
architecture empty of e3 is
begin
end architecture;
| apache-2.0 | 25fc22d29b2a4ea42dbd22fcdd8575cc | 0.719313 | 2.951691 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_138x512/example_design/fifo_138x512_top.vhd | 1 | 4,790 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_138x512_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_138x512_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(138-1 DOWNTO 0);
DOUT : OUT std_logic_vector(138-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_138x512_top;
architecture xilinx of fifo_138x512_top is
SIGNAL clk_i : std_logic;
component fifo_138x512 is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(138-1 DOWNTO 0);
DOUT : OUT std_logic_vector(138-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_138x512 PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 713bb662631c1e635a6507d030b8cd39 | 0.527766 | 4.917864 | false | false | false | false |
fabianschuiki/moore | test/vhdl/bit_string_literals.vhd | 1 | 2,458 | library ieee;
use ieee.std_logic_1164.all;
package pkg_bit_string_literals is
constant b000 : std_logic_vector(7 downto 0) := B"00000000";
constant b001 : std_logic_vector(7 downto 0) := B"01010011";
constant b002 : std_logic_vector(7 downto 0) := "00000000";
constant b003 : std_logic_vector(7 downto 0) := "01010011";
constant x000 : std_logic_vector(7 downto 0) := x"00";
constant x001 : std_logic_vector(7 downto 0) := x"AB";
constant x002 : std_logic_vector(7 downto 0) := x"ab";
constant x003 : std_logic_vector(7 downto 0) := x"aB";
constant x004 : std_logic_vector(7 downto 0) := X"00";
constant x005 : std_logic_vector(7 downto 0) := X"AB";
constant x006 : std_logic_vector(7 downto 0) := X"ab";
constant x007 : std_logic_vector(7 downto 0) := X"aB";
constant o000 : std_logic_vector(5 downto 0) := O"00";
constant o001 : std_logic_vector(5 downto 0) := O"11";
constant o002 : std_logic_vector(5 downto 0) := O"13";
constant o003 : std_logic_vector(5 downto 0) := O"07";
-- the cases below are actually not accepted by some commercial tools
-- I still think they are correct according to the standard
constant u000 : std_logic_vector(7 downto 0) := x"0_0";
constant u001 : std_logic_vector(7 downto 0) := "0000_0000";
constant u002 : std_logic_vector(7 downto 0) := "0_00_0_00_00";
constant ux000 : std_logic_vector(7 downto 0) := Ux"AB";
constant ux001 : std_logic_vector(7 downto 0) := Ux"AB";
constant ux002 : std_logic_vector(7 downto 0) := UX"AB";
constant ux003 : std_logic_vector(7 downto 0) := uX"AB";
constant ux004 : std_logic_vector(7 downto 0) := 8ux"00000AB";
constant sx000 : std_logic_vector(7 downto 0) := Sx"AB";
constant sx001 : std_logic_vector(7 downto 0) := Sx"AB";
constant sx002 : std_logic_vector(7 downto 0) := SX"AB";
constant sx003 : std_logic_vector(7 downto 0) := sX"AB";
constant sx004 : std_logic_vector(7 downto 0) := 8sx"FFFFFAB";
constant sx005 : std_logic_vector(7 downto 0) := 8sx"FFAB";
constant sx006 : std_logic_vector(7 downto 0) := 8sx"00000AB";
constant sx007 : std_logic_vector(7 downto 0) := 8sx"00AB";
constant d000 : std_logic_vector(7 downto 0) := 8D"0";
constant d001 : std_logic_vector(7 downto 0) := 8D"255";
constant d002 : std_logic_vector(7 downto 0) := 8D"128";
constant d003 : std_logic_vector(7 downto 0) := 8D"12";
constant d003 : std_logic_vector(7 downto 0) := 8D"12";
constant x007 : std_logic_vector(7 downto 0) := 8X"aB";
end package;
| apache-2.0 | 240c0a8772a745bf8b3b781dca6ad115 | 0.679414 | 2.790011 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_138x16_shift/simulation/fg_tb_pkg.vhd | 1 | 11,255 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_138x16_shift_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(138-1 DOWNTO 0);
DOUT : OUT std_logic_vector(138-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit | c9706d902a13a58a0e67a0cc13921b83 | 0.504753 | 3.929818 | false | false | false | false |
e8johan/jamcpu | simcpu.vhd | 1 | 5,627 | ---------------------------------------------------------
-- JAM CPU
-- Simulation wrapper
--
-- License: LGPL v2+ (see the file LICENSE)
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Library General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version
library ieee;
library work;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned.conv_integer;
-- Include your ROM image here
use work.p1_rom.all;
entity simcpu is
port (
clk, clk2: in std_logic;
reset : in std_logic;
synctrap : in std_logic );
end;
architecture rev1 of simcpu is
component cpu
port(
--clock and reset
clk, reset : in std_logic;
--in and out ports
inport : in std_logic_vector(31 downto 0);
outport : out std_logic_vector(31 downto 0);
--IO interface
synctrap : in std_logic;
put : out std_logic;
curpsw11_31 : out std_logic_vector(31 downto 11);
curpsw0_7 : out std_logic_vector(7 downto 0);
newpsw11_31 : in std_logic_vector(31 downto 11);
newpsw0_7 : in std_logic_vector(7 downto 0);
--IM
im_cs : out std_logic_vector(7 downto 0);
im_oe : out std_logic;
im_wri : out std_logic;
im_adr : out std_logic_vector( 16 downto 0 );
im_dat : inout std_logic_vector( 63 downto 0 );
--DM
dm_cs : out std_logic_vector(7 downto 0);
dm_oe : out std_logic;
dm_wri : out std_logic;
dm_adr : out std_logic_vector( 16 downto 0 );
dm_dat : inout std_logic_vector( 63 downto 0 ));
end component;
component sram
port (
ncs : in std_logic_vector( 3 downto 0 ); -- not chip select
addr : in std_logic_vector( 16 downto 0 );
data : inout std_logic_vector( 31 downto 0 );
nwe : in std_logic; -- not write enable
noe : in std_logic ); -- not output enable
end component;
for U_cpu : cpu use entity work.cpu(rev1);
for U_dm1 : sram use entity work.sram(behav);
for U_dm2 : sram use entity work.sram(behav);
signal dm_cs : std_logic_vector (7 downto 0);
signal dm_oe : std_logic;
signal dm_write : std_logic;
signal dm_adr : std_logic_vector( 16 downto 0 );
signal dm_data : std_logic_vector (63 downto 0);
signal im_cs : std_logic_vector (7 downto 0);
signal im_oe : std_logic;
signal im_write : std_logic;
signal im_adr : std_logic_vector( 16 downto 0 );
signal im_data : std_logic_vector (63 downto 0);
signal inport : std_logic_vector( 31 downto 0 );
signal outport : std_logic_vector( 31 downto 0 );
-- signal synctrap : std_logic;
signal curpsw11_31 : std_logic_vector(31 downto 11);
signal curpsw0_7 : std_logic_vector(7 downto 0);
signal newpsw11_31 : std_logic_vector(31 downto 11);
signal newpsw0_7 : std_logic_vector(7 downto 0);
begin
-- STU and I/O
-- synctrap <= '0';
newpsw11_31 <= curpsw11_31;
newpsw0_7 <= curpsw0_7;
-- Data memory
U_dm1 : sram port map(
ncs => dm_cs(3 downto 0),
noe => dm_oe,
nwe => dm_write,
addr => dm_adr,
data => dm_data(31 downto 0));
U_dm2 : sram port map(
ncs => dm_cs(7 downto 4),
noe => dm_oe,
nwe => dm_write,
addr => dm_adr,
data => dm_data(63 downto 32));
-- CPU
U_cpu : cpu port map(
--clock and reset
clk => clk,
reset => reset,
--in and out ports
inport => inport,
outport => outport,
--IO interface
synctrap => synctrap,
curpsw11_31 => curpsw11_31,
curpsw0_7 => curpsw0_7,
newpsw11_31 => newpsw11_31,
newpsw0_7 => newpsw0_7,
--IM
im_cs => im_cs,
im_oe => im_oe,
im_wri => im_write,
im_adr => im_adr,
im_dat => im_data,
--DM
dm_cs => dm_cs,
dm_oe => dm_oe,
dm_wri => dm_write,
dm_adr => dm_adr,
dm_dat => dm_data);
-- simulate IM SRAM from rom image (32bit wide => 64bit wide)
process
variable address : natural;
begin
im_data <= (others => 'Z') ;
--
--
-- process memory cycles
--
loop
--
-- wait for chip-select,
--
if (im_cs(0) = '0') then
-- decode address
address := conv_integer( im_adr(16 downto 0) & '0' );
--
if im_write = '0' then
elsif im_write = '1' then
-- read cycle
if im_oe = '0' then
im_data(31 downto 0) <= rom_image(address);
else
im_data <= (others => 'Z');
end if;
else
im_data <= (others => 'Z');
end if;
else
--
-- Chip not selected, disable output
--
im_data <= (others => 'Z');
end if;
wait on im_cs, im_write, im_oe, im_adr, im_data;
end loop;
end process;
process
variable address : natural;
begin
im_data <= (others => 'Z') ;
--
--
-- process memory cycles
--
loop
--
-- wait for chip-select,
--
if (im_cs(7) = '0') then
-- decode address
address := conv_integer( im_adr(16 downto 0) & '0');
--
if im_write = '0' then
elsif im_write = '1' then
-- read cycle
if im_oe = '0' then
im_data(63 downto 32) <= rom_image(address +1);
else
im_data <= (others => 'Z');
end if;
else
im_data <= (others => 'Z');
end if;
else
--
-- Chip not selected, disable output
--
im_data <= (others => 'Z');
end if;
wait on im_cs, im_write, im_oe, im_adr, im_data;
end loop;
end process;
end;
| lgpl-2.1 | 271594cfabfcd000572b51e5a23565f3 | 0.56922 | 2.917055 | false | false | false | false |
fabianschuiki/moore | test/vhdl/package_decl.vhd | 1 | 742 | package foo is end;
package foo is end package;
package foo is end package foo;
-- package foo is end package bar;
package foo is
generic (stuff : INTEGER := 0);
end;
package foo is
generic (stuff : INTEGER := 0);
generic map (stuff => 0);
end;
package TimeConstants is
constant tPLH: Time := 10 ns;
constant tPHL: Time := 12 ns;
constant tPLZ: Time := 7 ns;
constant tPZL: Time := 8 ns;
constant tPHZ: Time := 8 ns;
constant tPZH: Time := 9 ns;
end TimeConstants;
package TriState is
type Tri is ('0', '1', 'Z', 'E');
function BitVal (Value: Tri) return Bit;
function TriVal (Value: Bit) return Tri;
type TriVector is array (Natural range <>) of Tri;
function Resolve (Sources: TriVector) return Tri;
end package TriState;
| apache-2.0 | 156a7ff0ebabc8251509da9623c69296 | 0.692722 | 3.268722 | false | false | false | false |
fabianschuiki/moore | test/vhdl/type_array.vhd | 1 | 1,838 | package pkg is
type BIT is ('0','1');
type FIVE_LEVEL_LOGIC is (LOW, HIGH, RISING, FALLING, AMBIGUOUS);
type INTEGER is range -2147483648 to 2147483647;
type NATURAL is range 0 to 4294967295;
type MY_WORD is array (0 to 31) of BIT; -- fully constrained
type BITMAP is array(BIT) of FIVE_LEVEL_LOGIC;
type DATA_IN is array (7 downto 0) of FIVE_LEVEL_LOGIC; -- fully constrained
type MEMORY is array (INTEGER range <>) of MY_WORD; -- partially constrained
type SIGNED_FXPT is array (INTEGER range <>) of BIT; -- unconstrained
type SIGNED_FXPT_VECTOR is array (NATURAL range <>) of SIGNED_FXPT; -- unconstrained
type SIGNED_FXPT_5x4 is array (1 to 5, 1 to 4) of SIGNED_FXPT; -- partially constrained
type MEMORY2 is array (INTEGER range 0 to 18) of MY_WORD;
type E is array (NATURAL range <>) of INTEGER;
type F is array (NATURAL range <>) of MY_WORD;
type T0 is array (1 to 10) of F (1 to 0);
type T1 is array (10 to 1) of F (0 to 1);
type T2 is array (1 to 10) of F (0 to 1) (4 to 8);
type T3 is array (1 to 10) of F (open);
type T4 is array (1 to 10) of F (open) (4 to 8);
end;
library work;
use work.pkg.all;
entity foo is end;
architecture bar of foo is
--signal a: DATA_IN;
--signal b: MEMORY (0 to 255);
--signal c: SIGNED_FXPT (3 downto -4);
--signal d: SIGNED_FXPT_VECTOR (1 to 20)(9 downto 0);
--signal e: SIGNED_FXPT_5x4 (open)(3 downto -4);
--signal f0: T0;
--signal f1: T1;
begin end;
--!@ elab foo(bar)
--| entity @foo_bar () () {
--| %a = sig [8 x n5] [.. 0]
--| %b = sig [256 x [32 x n2]] [.. [.. 0]]
--| %c = sig [8 x n2] [.. 0]
--| %d = sig [20 x [10 x n2]] [.. [.. 0]]
--| %e = sig [5 x [4 x [8 x n2]]] [.. [.. [.. 0]]]
--| %f0 = sig [10 x void] [.. void]
--| %f1 = sig void void
--| }
| apache-2.0 | 5c9aed1557ed80ab3a8715de44eb6b77 | 0.588139 | 2.912837 | false | false | false | false |
kevintownsend/R3 | coregen/block_ram_64x1024/simulation/bmg_stim_gen.vhd | 1 | 15,558 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For TDP
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_TDP IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_TDP;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(64,64);
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(64,64);
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_INT : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(1024,11);
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
SIGNAL DO_READ_RA : STD_LOGIC := '0';
SIGNAL DO_READ_RB : STD_LOGIC := '0';
SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 6;
CONSTANT READ_CNT_A : integer := 6;
CONSTANT WRITE_CNT_B : integer := 4;
CONSTANT READ_CNT_B : integer := 4;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(9 DOWNTO 0) <= WRITE_ADDR_A(9 DOWNTO 0);
READ_ADDR_INT_A(9 DOWNTO 0) <= READ_ADDR_A(9 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) AFTER 50 ns;
WRITE_ADDR_INT_B(9 DOWNTO 0) <= WRITE_ADDR_B(9 DOWNTO 0);
--To avoid collision during idle period, negating the read_addr
READ_ADDR_INT_B(9 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),NOT(READ_ADDR_B(9 DOWNTO 0)),READ_ADDR_B(9 DOWNTO 0));
ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) AFTER 50 ns;
DINA <= DINA_INT AFTER 50 ns;
DINB <= DINB_INT AFTER 50 ns;
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_B;
RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024)
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>1024 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>64,
DOUT_WIDTH => 64,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK =>CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
DATA_OUT => DINA_INT
);
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>64,
DOUT_WIDTH =>64 ,
DATA_PART_CNT =>1,
SEED => 2)
PORT MAP (
CLK =>CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
DATA_OUT => DINB_INT
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(0),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(I),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_A;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(0),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(I),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
REGCEA_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
DO_READ_RA <= '0';
ELSE
DO_READ_RA <= DO_READ_A;
END IF;
END IF;
END PROCESS;
REGCEB_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_RB <= '0';
ELSE
DO_READ_RB <= DO_READ_B;
END IF;
END IF;
END PROCESS;
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
WEA(0) <= IF_THEN_ELSE(DO_WRITE_A='1','1','0') AFTER 50 ns;
WEB(0) <= IF_THEN_ELSE(DO_WRITE_B='1','1','0') AFTER 50 ns;
END ARCHITECTURE;
| mit | 0f87f72a3fa78a2f55bb4c4130b72918 | 0.578738 | 3.202552 | false | false | false | false |
TMU-VHDL-team2/sqrt | fpga/mdr.vhd | 2 | 886 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity mdr is
port(
clock : in std_logic;
busC : in std_logic_vector(15 downto 0);
latch : in std_logic;
memo : in std_logic_vector(15 downto 0);
sel : in std_logic;
data : out std_logic_vector(15 downto 0)
);
end mdr;
architecture BEHAVIOR of mdr is
begin
process(clock) begin
if(clock'event and clock = '1')then
if(latch = '1')then
if(sel = '0')then
data <= busC;
elsif(sel = '1')then
data <= memo;
else
null;
end if;
else
null;
end if;
else
null;
end if;
end process;
end BEHAVIOR;
| mit | 0de28faa41eb448f0876e37033608095 | 0.446953 | 4.045662 | false | false | false | false |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/clock_control/clock_control_inst.vhd | 1 | 432 | component clock_control is
port (
inclk : in std_logic := 'X'; -- inclk
ena : in std_logic := 'X'; -- ena
outclk : out std_logic -- outclk
);
end component clock_control;
u0 : component clock_control
port map (
inclk => CONNECTED_TO_inclk, -- altclkctrl_input.inclk
ena => CONNECTED_TO_ena, -- .ena
outclk => CONNECTED_TO_outclk -- altclkctrl_output.outclk
);
| gpl-3.0 | fdbe76459f8235fe47f2527d74252417 | 0.574074 | 3.24812 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_138x16_shift/simulation/fg_tb_synth.vhd | 1 | 9,659 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(138-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 138,
C_DOUT_WIDTH => 138,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 138,
C_DIN_WIDTH => 138,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 138,
C_DIN_WIDTH => 138,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_138x16_shift_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit | 0d939312ad06bfacaff89aa4a870eb9c | 0.456569 | 4.141938 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_96x512/simulation/fg_tb_pkg.vhd | 1 | 11,252 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_fwft_96x512_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(96-1 DOWNTO 0);
DOUT : OUT std_logic_vector(96-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit | 305e9e9bb3ad3cceabfbefd3d6be6303 | 0.504621 | 3.928771 | false | false | false | false |
capitanov/MinesweeperFPGA | src/vga_main/ctrl_8x16_rom.vhd | 1 | 47,129 | --------------------------------------------------------------------------------
--
-- Title : ctrl_8x16_rom
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Description : ROM generator for VGA characters
--
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ctrl_8x16_rom is
port(
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end ctrl_8x16_rom;
architecture ctrl_8x16_rom of ctrl_8x16_rom is
constant addr_width : integer:= 11;
constant data_width : integer:= 8;
signal addr_reg : std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition
constant ROM: rom_type:=(
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000001", -- 8 *
"00000001", -- 9 *
"00000001", -- a *
"00000001", -- b *
"00000011", -- c **
"00000111", -- d ***
"00001111", -- e ****
"11111111", -- f ********
-- code x09
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3 **
"00011000", -- 4 **
"01011010", -- 5 ** ** **
"00111100", -- 6 ****
"01111110", -- 7 *** ***
"00111100", -- 8 ****
"01011010", -- 9 ** ** **
"00011000", -- a **
"00000000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x510
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f
"00000000", -- 0
"11111110", -- 1
"11111110", -- 2
"11111110", -- 3
"11111110", -- 4 *
"11111110", -- 5 ***
"11111110", -- 6 ** **
"11111110", -- 7 ** **
"11111110", -- 8 ** **
"11111110", -- 9 ** **
"11111110", -- a *******
"11111110", -- b
"11111110", -- c
"11111110", -- d
"11111110", -- e
"00000000" -- f
);
begin
addr_reg <= addr when rising_edge(clk);
data <= ROM(to_integer(unsigned(addr_reg)));
end ctrl_8x16_rom;
| mit | bd526e4a4539729bcfca506f568202be | 0.421842 | 2.616679 | false | false | false | false |
fabianschuiki/moore | test/vhdl/pkg_1.vhd | 1 | 1,031 | package TimeConstants is
constant tPLH: Time := 10 ns;
constant tPHL: Time := 12 ns;
constant tPLZ: Time := 7 ns;
constant tPZL: Time := 8 ns;
constant tPHZ: Time := 8 ns;
constant tPZH: Time := 9 ns;
end TimeConstants;
package TriState is
type Tri is ('0', '1', 'Z', 'E');
function BitVal (Value: Tri) return Bit;
function TriVal (Value: Bit) return Tri;
type TriVector is array (Natural range <>) of Tri;
function Resolve (Sources: TriVector) return Tri;
end package TriState;
package body TriState is
function BitVal (Value: Tri) return Bit is
constant Bits : Bit_Vector := "0100";
begin
return Bits(Tri'Pos(Value));
end;
function TriVal (Value: Bit) return Tri is
begin
return Tri'Val(Bit'Pos(Value));
end;
function Resolve (Sources: TriVector) return Tri is
variable V: Tri := 'Z';
begin
for i in Sources'Range loop
if Sources(i) /= 'Z' then
if V = 'Z' then
V := Sources(i);
else
return 'E';
end if;
end if;
end loop;
return V;
end;
end package body TriState;
| apache-2.0 | e9439e77ce00942e9327e6c37e30bb7c | 0.666343 | 3.059347 | false | false | false | false |
dugagjinll/MIPS | MIPS/tb_controller.vhd | 1 | 1,461 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.numeric_std.ALL;
ENTITY tb_controller IS
END tb_controller;
ARCHITECTURE behavior OF tb_controller IS
--Inputs
SIGNAL tb_opcode : std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
--Outputs
SIGNAL tb_regDst : std_logic;
SIGNAL tb_jump : std_logic;
SIGNAL tb_branch : std_logic;
SIGNAL tb_memRead : std_logic;
SIGNAL tb_memToRegister : std_logic;
SIGNAL tb_ALUop : std_logic_vector(1 DOWNTO 0);
SIGNAL tb_memWrite : std_logic;
SIGNAL tb_ALUsrc : std_logic;
SIGNAL tb_regWrite : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
U1_Test : ENTITY work.Controller(Behavioral)
PORT MAP(
opcode => tb_opcode,
regDst => tb_regDst,
jump => tb_jump,
branch => tb_branch,
memRead => tb_memRead,
memToRegister => tb_memToRegister,
ALUop => tb_ALUop,
memWrite => tb_memWrite,
ALUsrc => tb_ALUsrc,
regWrite => tb_regWrite
);
-- Stimulus process
stim_proc : PROCESS
BEGIN
tb_opcode <= "000000"; --R-type
WAIT FOR 50 ns;
tb_opcode <= "100011"; --load word
WAIT FOR 50 ns;
tb_opcode <= "101011"; --store word
WAIT FOR 50 ns;
tb_opcode <= "000100"; --breanh equal
WAIT FOR 50 ns;
tb_opcode <= "000010"; --jump
WAIT FOR 50 ns;
tb_opcode <= "111111"; --unknown
WAIT FOR 50 ns;
ASSERT false
REPORT "END"
SEVERITY failure;
END PROCESS;
END; | mit | cb4b2d627c33a80fa6f6096d663fd90e | 0.625599 | 3.148707 | false | false | false | false |
TMU-VHDL-team2/sqrt | fpga/pr.vhd | 2 | 613 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pr is
port(clk, S_PRlat, S_s_inc : in std_logic;
S_BUS_C : in std_logic_vector(15 downto 0);
S_PR_F : out std_logic_vector(15 downto 0));
end pr;
architecture BEHAVIOR of pr is
signal rst : std_logic_vector(15 downto 0) := "0000000010000000";
begin
S_PR_F <= rst;
process(clk) begin
if clk'event and clk = '1' then
if S_PRlat = '1' then
rst <= S_BUS_C;
elsif S_s_inc = '1' then
rst <= rst + 1;
else
null;
end if;
end if;
end process;
end BEHAVIOR;
| mit | 96965cd49d231977ec4a240289587057 | 0.597064 | 2.947115 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_69x512_hf/simulation/fg_tb_synth.vhd | 1 | 9,292 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(69-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(69-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(69-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(69-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 69,
C_DOUT_WIDTH => 69,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 69,
C_DIN_WIDTH => 69,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 69,
C_DIN_WIDTH => 69,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_69x512_hf_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit | 557f548b4708e17f2abe23235a58a501 | 0.45254 | 4.202623 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_96x512_hf/simulation/fg_tb_synth.vhd | 1 | 9,406 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL prog_empty : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 96,
C_DOUT_WIDTH => 96,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 96,
C_DIN_WIDTH => 96,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 96,
C_DIN_WIDTH => 96,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_fwft_96x512_hf_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit | dba840a667ef85a73d57046797c42084 | 0.451839 | 4.208501 | false | false | false | false |
capitanov/MinesweeperFPGA | src/game_cores/cl_mines.vhd | 1 | 5,640 | --------------------------------------------------------------------------------
--
-- Title : cl_mines.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game block for mines
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.ctrl_types_pkg.array8x8;
use work.ctrl_types_pkg.data3x8;
use work.ctrl_types_pkg.data8x8;
entity cl_mines is
generic(
constant yend : std_logic_vector(4 downto 0):="11000";
constant ystart : std_logic_vector(4 downto 0):="10000";
constant xend : std_logic_vector(6 downto 0):="0011000";
constant xstart : std_logic_vector(6 downto 0):="0010000"
);
port(
-- system signals:
clk : in std_logic;
reset : in std_logic;
-- vga XoY coordinates:
show_disp : in array8x8;
-- vga XoY coordinates:
addr_rnd : in std_logic_vector(4 downto 0);
display : in std_logic;
x_char : in std_logic_vector(9 downto 0); -- X line: 0:79
y_char : in std_logic_vector(8 downto 0); -- Y line: 0:29
-- out color scheme:
data_out : out std_logic_vector(7 downto 0);
rgb : out std_logic_vector(2 downto 0)
);
end cl_mines;
architecture cl_mines of cl_mines is
component ctrl_rounds_rom is
port(
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(23 downto 0)
);
end component;
component ctrl_8x16_rom is
port(
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end component;
signal x_in : std_logic_vector(6 downto 0);
signal y_in : std_logic_vector(4 downto 0);
signal x_rev : std_logic_vector(2 downto 0);
signal x_del : std_logic_vector(2 downto 0);
signal x_z : std_logic_vector(2 downto 0);
signal y_charzz : std_logic_vector(3 downto 0);
signal y_charz : std_logic_vector(3 downto 0);
constant color2 : std_logic_vector(2 downto 0):="010";
signal addr_round : std_logic_vector(7 downto 0);
signal data_round : std_logic_vector(23 downto 0);
signal addr_rom2 : std_logic_vector(10 downto 0);
signal data_rom2 : std_logic_vector(7 downto 0);
signal data_box : std_logic_vector(7 downto 0);
signal data_disp : data8x8;
signal data2 : std_logic;
signal x_inz : std_logic_vector(6 downto 0);
signal y_inz : std_logic_vector(4 downto 0);
signal dataxy : std_logic;
begin
y_charz <= y_char(3 downto 0) when rising_edge(clk);
y_charzz <= y_charz when rising_edge(clk);
x_in <= x_char(9 downto 3);
y_in <= y_char(8 downto 4);
x_inz <= x_in after 1 ns when rising_edge(clk);
y_inz <= y_in after 1 ns when rising_edge(clk);
addr_round <= ((not addr_rnd) & (not y_in(2 downto 0))) when (y_in(4 downto 3) = "10");
x_rounds: ctrl_rounds_rom
port map(
clk => clk,
addr => addr_round,
data => data_round
);
x_char_rom2: ctrl_8x16_rom
port map(
clk => clk,
addr => addr_rom2,
data => data_rom2
);
x_gen_round: for ii in 0 to 7 generate
signal conv_3x8 : data3x8;
begin
conv_3x8(ii) <= data_round(23-3*ii downto 21-3*ii);
pr_round_box2: process(clk, reset) is
begin
if reset = '0' then
data_disp(ii) <= x"00";
elsif rising_edge(clk) then
case conv_3x8(ii) is
when "000" => data_disp(ii) <= x"30";
when "001" => data_disp(ii) <= x"31";
when "010" => data_disp(ii) <= x"32";
when "011" => data_disp(ii) <= x"33";
when "100" => data_disp(ii) <= x"34";
when "101" => data_disp(ii) <= x"35";
when "110" => data_disp(ii) <= x"36";
when others => data_disp(ii) <= x"0F";
end case;
end if;
end process;
end generate;
pr_select2: process(clk, reset) is
begin
if reset = '0' then
data_box <= x"00";
elsif rising_edge(clk) then
if (dataxy = '1') then
if (ystart <= y_inz) and (y_inz < yend) then
if x_inz(6 downto 3) = "0010" then
case x_inz(2 downto 0) is
when "000" => data_box <= data_disp(0);
when "001" => data_box <= data_disp(1);
when "010" => data_box <= data_disp(2);
when "011" => data_box <= data_disp(3);
when "100" => data_box <= data_disp(4);
when "101" => data_box <= data_disp(5);
when "110" => data_box <= data_disp(6);
when others => data_box <= data_disp(7);
end case;
else
data_box <= x"00";
end if;
else
data_box <= x"00";
end if;
else
data_box <= x"00";
end if;
end if;
end process;
addr_rom2 <= data_box(6 downto 0) & y_charzz(3 downto 0);
pr_select3: process(clk, reset) is
begin
if reset = '0' then
dataxy <= '0';
elsif rising_edge(clk) then
if display = '0' then
dataxy <= '0';
else
if ((xstart <= x_in) and (x_in < xend)) then
if ((ystart <= y_in) and (y_in < yend)) then
dataxy <= show_disp(conv_integer(x_in(2 downto 0)))(conv_integer(y_in(2 downto 0)));
else
dataxy <= '0';
end if;
else
dataxy <= '0';
end if;
end if;
end if;
end process;
data_out <= data_box;
g_rev: for ii in 0 to 2 generate
begin
x_rev(ii) <= not x_char(ii) when rising_edge(clk);
end generate;
x_del <= x_rev when rising_edge(clk);
x_z <= x_del when rising_edge(clk);
pr_sw_sel2: process(clk, reset) is
begin
if reset = '0' then
data2 <= '0';
elsif rising_edge(clk) then
data2 <= data_rom2(to_integer(unsigned(x_z)));
end if;
end process;
g_rgb2: for ii in 0 to 2 generate
begin
rgb(ii) <= data2 and color2(ii);
end generate;
end cl_mines; | mit | 8c763521c1d87cf7cd9784ecb6b3fc71 | 0.585993 | 2.637979 | false | false | false | false |
mzakharo/usb-de2-fpga | sim/hal_tb.vhd | 1 | 2,867 |
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
use work.isp_hal.all;
-- Add your library and packages declaration here ...
entity hal_tb is
end hal_tb;
architecture TB_ARCHITECTURE of hal_tb is
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal clk : STD_LOGIC;
signal reset : STD_LOGIC;
signal d : isp_hal_in_t;
signal otg_data : STD_LOGIC_VECTOR(15 downto 0);
-- Observed signals - signals mapped to the output ports of tested entity
signal q : isp_hal_out_t;
--local signals
signal slowclk_en : bit := '1';
signal write_sense :std_logic;
signal write_end_sense : std_logic;
--------------------------------------------------------------
-- clock cycle
constant period : time := 20 ns;
--------------------------------------------------------------
begin
-- Unit Under Test port map
UUT : hal
generic map(3)
port map (
clk => clk,
reset => reset,
otg_data => otg_data,
d => d,
q => q
);
--d.int <= '1'; -- not used in this tb
----------------------------------------------------
-- clock
process
begin
clk <= '0';
wait for period/2;
clk <= '1';
wait for period/2;
end process;
--produces 25MHz clock enable for OTG
p_slowclk_en: process
begin
wait until rising_edge(clk);
slowclk_en <= not(slowclk_en);
end process;
d.slowclk_en <= slowclk_en;
----------------------------------------------------
-- resets
process
begin
reset <= '1';
wait for period;
reset <= '0';
wait;
end process;
----------------------------------------------------
-- read emulation
----------------------------------------------------
process
begin
otg_data <= (others => 'Z');
wait until falling_edge(q.rd_n);
wait for 22 ns;
otg_data <= x"BEAD";
wait until rising_edge(q.cs_n);
wait for 3 ns;
end process;
----------------------------------------------------
-- write emulation
----------------------------------------------------
write_sense <= to_stdulogic(d.drv.cmd(1));
write_end_sense <= to_stdulogic(q.drv.rdy);
process
begin
wait for period;
if (write_sense = '1') then
d.drv.data <= x"FACE";
else
d.drv.data <= x"0000";
end if;
wait until rising_edge(write_end_sense);
wait until rising_edge(clk);
d.drv.data <= x"0000";
wait for period * 4;
end process;
--choose what to do
d.drv.cmd <= otg_rd; -- otg_wr; -- otg_wr_cmd;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_hal of hal_tb is
for TB_ARCHITECTURE
for UUT : hal
use entity work.hal(handler);
end for;
end for;
end TESTBENCH_FOR_hal;
| gpl-3.0 | 968e7b8140c8098635068a0cf14707a0 | 0.487269 | 3.680359 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/gr.vhd | 1 | 3,713 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gr is
port(clk, S_GRlat : in std_logic;
S_ctl_a, S_ctl_b, S_ctl_c : in std_logic_vector(3 downto 0);
S_BUS_C : in std_logic_vector(15 downto 0);
S_BUS_A, S_BUS_B : out std_logic_vector(15 downto 0);
GR0_View, GR1_View, GR2_View, GR3_View,
GR4_View, GR5_View, GR6_View, GR7_View,
GR8_View, GR9_View, GR10_View, GR11_View,
GR12_View, GR13_View, GR14_View, GR15_View : out std_logic_vector(15 downto 0));
end gr;
architecture BEHAVIOR of gr is
signal S_GR0_F, S_GR1_F, S_GR2_F, S_GR3_F, S_GR4_F, S_GR5_F, S_GR6_F, S_GR7_F,
S_GR8_F, S_GR9_F, S_GR10_F, S_GR11_F, S_GR12_F, S_GR13_F, S_GR14_F, S_GR15_F
: std_logic_vector(15 downto 0);
begin
GR0_View <= S_GR0_F; GR1_View <= S_GR1_F; GR2_View <= S_GR2_F; GR3_View <= S_GR3_F;
GR4_View <= S_GR4_F; GR5_View <= S_GR5_F; GR6_View <= S_GR6_F; GR7_View <= S_GR7_F;
GR8_View <= S_GR8_F; GR9_View <= S_GR9_F; GR10_View <= S_GR10_F; GR11_View <= S_GR11_F;
GR12_View <= S_GR12_F; GR13_View <= S_GR13_F; GR14_View <= S_GR14_F; GR15_View <= S_GR15_F;
process(clk) begin
if clk'event and (clk and S_GRlat) = '1' then
case S_ctl_c is
when "0000" => S_GR0_F <= S_BUS_C;
when "0001" => S_GR1_F <= S_BUS_C;
when "0010" => S_GR2_F <= S_BUS_C;
when "0011" => S_GR3_F <= S_BUS_C;
when "0100" => S_GR4_F <= S_BUS_C;
when "0101" => S_GR5_F <= S_BUS_C;
when "0110" => S_GR6_F <= S_BUS_C;
when "0111" => S_GR7_F <= S_BUS_C;
when "1000" => S_GR8_F <= S_BUS_C;
when "1001" => S_GR9_F <= S_BUS_C;
when "1010" => S_GR10_F <= S_BUS_C;
when "1011" => S_GR11_F <= S_BUS_C;
when "1100" => S_GR12_F <= S_BUS_C;
when "1101" => S_GR13_F <= S_BUS_C;
when "1110" => S_GR14_F <= S_BUS_C;
when "1111" => S_GR15_F <= S_BUS_C;
when others => null;
end case;
end if;
end process;
process(S_GR0_F, S_GR1_F, S_GR2_F, S_GR3_F, S_GR4_F, S_GR5_F, S_GR6_F,
S_GR7_F, S_GR8_F, S_GR9_F, S_GR10_F, S_GR11_F, S_GR12_F, S_GR13_F,
S_GR14_F, S_GR15_F, S_ctl_a, S_ctl_b) begin
case S_ctl_a is
when "0000" => S_BUS_A <= S_GR0_F;
when "0001" => S_BUS_A <= S_GR1_F;
when "0010" => S_BUS_A <= S_GR2_F;
when "0011" => S_BUS_A <= S_GR3_F;
when "0100" => S_BUS_A <= S_GR4_F;
when "0101" => S_BUS_A <= S_GR5_F;
when "0110" => S_BUS_A <= S_GR6_F;
when "0111" => S_BUS_A <= S_GR7_F;
when "1000" => S_BUS_A <= S_GR8_F;
when "1001" => S_BUS_A <= S_GR9_F;
when "1010" => S_BUS_A <= S_GR10_F;
when "1011" => S_BUS_A <= S_GR11_F;
when "1100" => S_BUS_A <= S_GR12_F;
when "1101" => S_BUS_A <= S_GR13_F;
when "1110" => S_BUS_A <= S_GR14_F;
when "1111" => S_BUS_A <= S_GR15_F;
when others => null;
end case;
case S_ctl_b is
when "0000" => S_BUS_B <= S_GR0_F;
when "0001" => S_BUS_B <= S_GR1_F;
when "0010" => S_BUS_B <= S_GR2_F;
when "0011" => S_BUS_B <= S_GR3_F;
when "0100" => S_BUS_B <= S_GR4_F;
when "0101" => S_BUS_B <= S_GR5_F;
when "0110" => S_BUS_B <= S_GR6_F;
when "0111" => S_BUS_B <= S_GR7_F;
when "1000" => S_BUS_B <= S_GR8_F;
when "1001" => S_BUS_B <= S_GR9_F;
when "1010" => S_BUS_B <= S_GR10_F;
when "1011" => S_BUS_B <= S_GR11_F;
when "1100" => S_BUS_B <= S_GR12_F;
when "1101" => S_BUS_B <= S_GR13_F;
when "1110" => S_BUS_B <= S_GR14_F;
when "1111" => S_BUS_B <= S_GR15_F;
when others => null;
end case;
end process;
end BEHAVIOR;
| mit | e44475e633bd824a257a05c635ae15ce | 0.501751 | 2.177713 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/tb_alu.vhd | 1 | 2,720 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity alu_tb is
end alu_tb;
architecture BEHAVIOR of alu_tb is
-- Definitions --
constant STEP : time := 10 ns; -- A clock cycle is set to be 10ns --
signal func : std_logic_vector(3 downto 0);
signal busA : std_logic_vector(15 downto 0);
signal busB : std_logic_vector(15 downto 0);
signal inZ : std_logic;
signal inS : std_logic;
signal inO : std_logic;
signal outZ : std_logic;
signal outS : std_logic;
signal outO : std_logic;
signal busC : std_logic_vector(15 downto 0);
component alu is
port(
func : in std_logic_vector(3 downto 0);
busA : in std_logic_vector(15 downto 0);
busB : in std_logic_vector(15 downto 0);
inZ : in std_logic;
inS : in std_logic;
inO : in std_logic;
outZ : out std_logic;
outS : out std_logic;
outO : out std_logic;
busC : out std_logic_vector(15 downto 0)
);
end component;
-- Main --
begin
uut : alu port map(
func => func,
busA => busA,
busB => busB,
inZ => inZ ,
inS => inS ,
inO => inO ,
outZ => outZ,
outS => outS,
outO => outO,
busC => busC );
-- clk_process: process
-- begin
-- clk <= '0';
-- wait for STEP/2; --for 0.5 ns signal is '0'.
-- clk <= '1';
-- wait for STEP/2; --for next 0.5 ns signal is '1'.
-- end process;
tb_alu: process
begin
func <= "0000";
busA <= "0001000100010001";
busB <= "0100010001000100";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
func <= func + "0001";
wait for STEP * 4;
--wait;
end process;
end BEHAVIOR;
| mit | 5fdb8ff7dff231921a54b0dfa64890dd | 0.481618 | 3.636364 | false | false | false | false |
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